THCV244A-QP_ Rev.4.31_E

THCV244A-QP
SerDes receiver with bi-directional transceiver

1.

Several fault and error detection function including
CRC provides hardware functional safety design.

General Description

THCV244A-QP is designed to support 4 cameras
with 1080p 30fps 10bit or 1080p 60fps 8bit, 3
cameras with 1080p 60fps 10bit and 2cameras with
8Mpixel 30fps 10bit camera data. It can be achieved
lengths of 15m by 100ohm differential STP or singleend 50ohm coaxial cable with 4 in-line connectors
between camera and processor by V-by-One® HStechnology.
Multiple camera data input stream can be combined
into one or two MIPI output stream using installed
line memory and MIPI virtual channel technology.
THCV244A-QP supports a MIPI CSI-2. Each CSI-2
data lane can transmit up to 1.49Gbps/lane at single
clock output mode.
V-by-One® HS maximum serial data rate is
4Gbps/lane. Four input lane supports HDR large
amount of data or camera switch experience.
THCV244A-QP is capable to control and monitor
remote camera module from main MPU via GPIO, or
1Mbps 2-wire serial interface.

3.

2.

Features

MIPI CSI-2 with 1,2 or 4-lane output
MIPI D-PHY supports 80Mbps~1.49Gbps
MIPI Virtual channel supported
Video formats: RAW8/10/12/14/16/20,
YUV422/420, RGB888/666/565, JPEG, Userdefined generic 8-bit
V-by-One® HS 400Mbps~4Gbps x4lane
V-by-One® HS standard version1.5
4 camera data integration into one MIPI stream
Video stream switch and copy/distribution
Frame sync remote supply scheme for multiple
camera stream synchronization
Wide range IO voltage from 1.7V to 3.6V
2-wire serial interface 1Mbps bridge function
Remote GPIO control and monitoring
Error detection including CRC and notification
QFN64 9x9mm 0.5mm pitch Exp-pad package
AEC-Q100 Support

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Block Diagram
Main-Link receiver

MIPI transmitter

THCV244A-QP

Sub-Link tranceiver

2 ports

SLINK

RX1P/NDES

RCM1P/N

SLINK

RX2P/NDES

RCM2P/N

SLINK

RX3P/NDES

RCM3P/N

SLINK
controlOSC

MTX0P/NMIPI D-PHY

RCM0P/NMIPI CSI-2 formatter

DES

Line memory

4 ports
RX0P/NMTX1P/NMTXCLK0P/N
MTX2P/N
MTX3P/NMTXCLK1P/N

2-wire I/F
GPIO
setting*DES stands for “Main-Link Deserializer”*SLINK stands for “Sub-Link PHY”

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THCV244A-QP_ Rev.4.31_E
Contents page
1.

General Description ......................................................................................................................................... 1

2.

Features ........................................................................................................................................................... 1

3.

Block Diagram ................................................................................................................................................ 1

4.

Pin Configuration ............................................................................................................................................ 4

5.

Pin Description ................................................................................................................................................ 5

6.

Functional Description .................................................................................................................................... 6
6.1.

Functional Overview ............................................................................................................................... 6

6.2.

HTPDN/LOCKN ..................................................................................................................................... 6

6.3.

V-by-One® HS input setting ................................................................................................................... 8
MPRF (Main-Link PRivate Format) ............................................................................................. 11
V-by-One® HS standard format .................................................................................................... 12

6.4.

eader/Packet/Sync Pre-processing ......................................................................................................... 16

6.5.

MIPI Line Start/Line End code output setting....................................................................................... 20

6.6.

PLL setting reference............................................................................................................................. 21

6.7.

Data stream handling ............................................................................................................................. 23
Data stream handling mode1 ......................................................................................................... 23
Data stream handling mode2 ......................................................................................................... 24

6.8.

MIPI Virtual Channel ............................................................................................................................ 25

6.9.

MIPI output setting ................................................................................................................................ 26

6.10.

2-wire serial interface ........................................................................................................................ 30
2-wire serial I/F slave Device ID ................................................................................................... 30
2-wire serial Read/Write access to local Register.......................................................................... 31

6.11.

2-wire serial I/F Watch Dog Timer ........................................................................................................ 32

6.12.

Register Auto Checksum diagnosis ................................................................................................... 32

6.13.

Sub-Link setting ................................................................................................................................ 33
Sub-Link 2-wire Set and Trigger mode (2-wire Normal mode) .................................................... 34
Sub-Link 2-wire Pass Through mode ............................................................................................ 38
Sub-Link transaction time accuracy Improvement ........................................................................ 44

6.14.

GPIO setting ...................................................................................................................................... 45
Register GPIO ............................................................................................................................... 46
GPIO as secondary 2-wire port ..................................................................................................... 46
Through GPIO Sub-Link Polling input/output .............................................................................. 47

6.15.

Internal Error / status signal monitoring ERR0/ERR1 pin output ..................................................... 49

6.16.

Internal Error / status signal monitoring register ............................................................................... 52

6.17.

Interrupt monitoring .......................................................................................................................... 54

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THCV244A-QP_ Rev.4.31_E
6.18.

Multiple camera synchronization Frame Vsync supply .................................................................... 56

6.19.

Power On Sequence........................................................................................................................... 59

6.20.

Lock / Re-Lock Sequence ................................................................................................................. 60

7.

Absolute Maximum Ratings .......................................................................................................................... 61

8.

Electrostatic discharge Ratings ...................................................................................................................... 61

9.

Recommended Operating Conditions............................................................................................................ 61

10.

Consumption Current ................................................................................................................................ 62

11.

DC Specifications ...................................................................................................................................... 64

11.1.

LVCMOS DC Specifications................................................................................................................. 64

11.2.

CML Receiver DC Specifications ......................................................................................................... 64

11.3.

CML Bi-directional Buffer DC Specifications ...................................................................................... 65

11.4.

MIPI Transmitter DC Specifications ..................................................................................................... 65

12.

AC Specifications ...................................................................................................................................... 66

12.1.

General AC Specifications ................................................................................................................ 66

12.2.

CML Receiver AC Specifications ..................................................................................................... 66

12.3.

CML B-directional Buffer AC Specifications ................................................................................... 66

12.4.

2-wire serial Slave AC Specifications ............................................................................................... 66

12.5.

MIPI Transmitter AC Specifications ................................................................................................. 67

13.

Package...................................................................................................................................................... 68

14.

Notices and Requests................................................................................................................................. 69

MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions.

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THCV244A-QP_ Rev.4.31_E

VDDIO1

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

INT1

INT0

AIN1

AIN0

SDA

SCL

VDDIO1

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

Pin Configuration

48
ERR0

49

32 EXTSYNC

ERR1

50

31

PDN

30

VDDPLLTHCV244A-QP

VDDCORE 51
VDDRX

52

29

VDDTX

RX0N

53

28

MTX3P

RX0P

54

27

MTX3N

VSSRX

55

26

MTX1P

RX1N

56

25

MTX1N

RX1P

57

VDDRX

58

23 MTXCLK0N

RX2N

59

22

MTX0P

RX2P

60

21

MTX0N

VSSRX

61

20

MTX2P

RX3N

62

19

MTX2N

RX3P

63

VDDRX

64

(TOP VIEW)
65 EXPGND

24 MTXCLK0P●

18 MTXCLK1P

7

8

9

10

11

RCM2N

RCM2P

RCM3N

RCM3P

VDDIO2

16

6
RCM1P

VDDTX

5
RCM1N

VDDCORE 15

4
RCM0P

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RSVDH2 14

3
RCM0N

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RSVDT1L2 13

2
VDDIO2VDDCORE 1

17 MTXCLK1N
RSVDT2H2 12

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THCV244A-QP_ Rev.4.31_E

5.

Pin Description
Pin Name
RX0P/NPin #54, 53type*
CI

Description
V-by-One® HS Input lane0

RX1P/N

57, 56CI

V-by-One® HS Input lane1

RX2P/N60, 59CI

V-by-One® HS Input lane2

RX3P/N63, 62CI

V-by-One® HS Input lane3

RCM0P/N

4, 3

CB

CML Bi-directiona Input/Output (Sub-Link) lane0

RCM1P/N6, 5

CB

CML Bi-directiona Input/Output (Sub-Link) lane1

RCM2P/N8, 7

CB

CML Bi-directiona Input/Output (Sub-Link) lane2

RCM3P/N

10, 9

CB

CML Bi-directiona Input/Output (Sub-Link) lane3

MTX0P/N

22, 21MO

MIPI differential data outputs lane0

MTX1P/N26, 25MO

MIPI differential data outputs lane1

MTX2P/N

20, 19MO

MIPI differential data outputs lane2

MTX3P/N

28, 27MO

MIPI differential data outputs lane3

MTXCLK0P/N

24, 23MO

MIPI differential clock outputs lane0

MTXCLK1P/N

18, 17MO

MIPI differential clock outputs lane1

RSVDT1L2

13

I

Reserved pin, Must be tied to Ground for normal operation.

RSVDT2H2

12

I

PDN

31

IL

Reserved pin. Must be tied to VDDIO2 for normal operation.
Power Down (User Power On Reset control must be
reuiquired.)
0: Power Down Mode
1: Normal Operation

AIN1

37

IL

AIN0

36

IL

Device Address Setting for 2-wire Serial Interface[AIN1:AIN0]=00: ID=7'h0B[AIN1:AIN0]=01: ID=7'h34[AIN1:AIN0]=10: ID=7'h77[AIN1:AIN0]=11: ID=7'h65

SCL

34

B

2-wire Serial Interface clock line

SDA

35

B

2-wire Serial Interface data line

GPIO0

40

B

General Purpose Input/Output

GPIO1

41

B

General Purpose Input/Output

GPIO2

42

B

General Purpose Input/Output

GPIO3

43

B

General Purpose Input/Output

GPIO4

44

B

General Purpose Input/Output

GPIO5

45

B

General Purpose Input/Output

GPIO6

46

B

General Purpose Input/Output

GPIO7

47

B

INT0

38

O

INT1

39

O

General Purpose Input/Output
Interrupt signal output.
It must be connected w ith a pull-up resistor.
0 : Interrupt occurred
1 : Steady state

ERR0

49

O

Internal Error / status signal monitoring output

ERR1

50

O

Internal Error / status signal monitoring output

EXTSYNC
RSVDH2
VDDIO132
14
33, 48B
I
P

External Sync input/output for multiple camera syncronization
Reserved Pins, Must be tied to VDDIO2 for normal operation.
Power Supply for CMOS I/O

VDDIO2

2,11

PPower Supply for Sub-Link I/O

VDDCORE

1,15,51

P

Power Supply for Digital Circuit

VDDRX

52,58,64

PPower Supply for Analog Circuit

VSSRX

55,61

G

GND for Analog Circuit

VDDTX

16,29

P

Power Supply for Analog Circuit

VDDPLL30

PPower Supply for Analog Circuit

EXPGND
65
G
Exposed GND Pad*type symbol ; MO=MIPI Output, CI=CML Input, CB=CML Bi-directional input/output
IL=Low Speed LVCMOS Input, I=Input, O=LVCMOS Output, B=LVCMOS Bi-directional input/output
P=Power, G=Ground

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6.

Functional Description

6.1.

Functional Overview

THCV244A-QP can receive CML video signal transmitted over 15m length and encode it to MIPI CSI-2 format.
With High Speed CML SerDes, high reliability and robustness encoding scheme and CDR (Clock and Data
Recovery) architecture, the THCV244A-QP enables to receive RAW/YUV/RGB/JPEG/Generic8bit data throughMain-Link by single 100ohm differential pair or 50ohm coaxial cable with minimal external components. In
addition, THCV244A-QP has Sub-Link which enables bi-directional transmission of 2-wire serial interface signals,
GPIO signals and also HTPDN/LOCKN signals for Main-Link through the other 1-pair of CML-Line. The
THCV244A-QP system is able to watch remote devices and to control them via 2-wire serial interface or GPIOs.
They also can report interrupt events caused by change of remote device statuses and internal statuses such as
CRC error.
Multiple camera data input stream can be combined into one or two MIPI output stream using installed line
memory and MIPI virtual channel technology.

6.2.

HTPDN/LOCKN

Hot-Plug Function
HTPDN indicates Main-Link connect condition between Transmitter and Receiver. HTPDN of Transmitter side
is high when Receiver is not active or not connected. Then Transmitter can enter into power down mode. HTPDN
is set to Low by the Receiver when Receiver is active and connects to the Transmitter, and then Transmitter must
start up and transmit CDR training pattern for link training. HTPDN is open drain output at the receiver side.
Transmitter side needs Pull-up resistor.
There is an application option to omit HTPDN connection between Transmitter and Receiver. In this case,
HTPDN at Transmitter side should always be at Low.

Lock Detect Function
LOCKN indicates whether CDR PLL of Main-Link is in lock status or not. LOCKN at Transmitter input is set
to High by pull-up resistor when Receiver is not active or in CDR PLL training. LOCKN is set to Low by Receiver
when CDR lock is completed. After that the CDR training mode finishes and then Transmitter shifts to the normal
mode. LOCKN of Receiver is open drain. Transmitter side needs pull-up resistor.
When an application omits HTPDN, LOCKN signal should only be considered with HTPDN pulled low byReceiver.

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Vcc(Tx side)
V-by-One®
HS Tx

THCV244A-QP

30kΩ

THCV244A-QP

30kΩ

V-by-One®
HS Tx

30kΩ

Vcc
(Tx side)

HTPDN

ERRy
(HTPDN)

HTPDN

HTPDN

LOCKN

ERRx
(LOCKN)

LOCKN

ERRx
(LOCKN)

With HTPDN connect

Figure 1.

Without HTPDN connect

Physical wire connection for wired Hot-plug and Lock detect scheme

It will need same GND potential reference between transmitter and receiver device to connect HTPDN andLOCKN pins directly like above. HTPDN and LOCKN can also be transmitted via Sub-Link without physicalwire connection. Assignment can be configurable by 2-wire access to internal register.

Table 1. HTPDN/LOCKN register
Address
0x0019bit Register Name
[7:6] R_LOCKN_LN3_SEL

width
2

R/W
RW

Init
2'h0

[5:4] R_LOCKN_LN2_SEL

2

RW

2'h0

[3:2] R_LOCKN_LN1_SEL

2

RW

2'h0

[1:0] R_LOCKN_LN0_SEL

2

RW

2'h0

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Description<this regiseter is valid when 0x0010[3]=0x1>
Select the source signal to be transmitted as LOCKN and HTPDN via Sub-Link
Lane30x0: LOCKN3
0x1: LOCKN2 or LOCKN3
0x2: LOCKN0 or LOCKN1 or LOCKN2 or LOCKN3
0x3: LOCKN and HTPDN signal level are LOW forcibly*LOCKN3: LOCKN signal of V-by-One(R) HS Lane3 (RX3P/RX3N)*HTPDN of the same lane as above set LOCKN lane is used
<this regiseter is valid when 0x0010[2]=0x1>
Select the source signal to be transmitted as LOCKN and HTPDN via Sub-Link
Lane20x0: LOCKN2
0x1: LOCKN2 or LOCKN3
0x2: LOCKN0 or LOCKN1 or LOCKN2 or LOCKN3
0x3: LOCKN and HTPDN signal level are LOW forcibly*LOCKN2: LOCKN signal of V-by-One(R) HS Lane2 (RX2P/RX2N)*HTPDN of the same lane as above set LOCKN lane is used
<this regiseter is valid when 0x0010[1]=0x1>
Select the source signal to be transmitted as LOCKN and HTPDN via Sub-Link
Lane10x0: LOCKN1
0x1: LOCKN0 or LOCKN1
0x2: LOCKN0 or LOCKN1 or LOCKN2 or LOCKN3
0x3: LOCKN and HTPDN signal level are LOW forcibly*LOCKN1: LOCKN signal of V-by-One(R) HS Lane1 (RX1P/RX1N)*HTPDN of the same lane as above set LOCKN lane is used
<this regiseter is valid when 0x0010[0]=0x1>
Select the source signal to be transmitted as LOCKN and HTPDN via Sub-Link
Lane0
0x0: LOCKN0
0x1: LOCKN0 or LOCKN1
0x2: Reserved
0x3: LOCKN and HTPDN signal level are LOW forcibly*LOCKN0: LOCKN signal of V-by-One(R) HS Lane0 (RX0P/RX0N)*HTPDN of the same lane as above set LOCKN lane is used

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6.3.

V-by-One® HS input setting

THCV244A-QP has a V-by-One® HS receiver and it can be connected a V-by-One® HS transmitter via
transmission line divided by AC-coupled.

Figure 2. V-by-One® HS connection scheme (differential transmission case)

Setting of V-by-One® HS input format can be configurable by 2-wire access to internal register.

Table 2. V-by-One® HS input format setting (all lanes)
Address
0x1012

bit Register Name
[7:5] reserved[4] R_RGB565_ON_L0

width
3
1

R/W
R/W

init
1'h0

[3:0] R_VX1_LANE_FMT0

4

R/W

4'h0

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Description<this regiseter is valid only when 0x1012[3:0]=0x1>
Main-Link Input Data Format Setting2 for all lane
0x0: RGB888
0x1: RGB565
Main-Link Input Data Format Setting for all lane
0x0: MPRF (Main-Link PRivate Format)
0x1: RGB888 or RGB565
0x2: YUV422 - Normal Mode1
0x3: YUV422 - Normal Mode2
0x4: YUV422 - Normal Mode3
0x5: YUV422 - Demux Mode1
0x6: YUV422 - Demux Mode2
0x7: RAW8 - Normal Mode1
0x8: RAW8 - Normal Mode2
0x9: RAW8 - Demux Mode1
0xA: RAW10 - Normal Mode1
0xB: RAW10 - Demux Mode1
0xC: RAW10 - Demux Mode2
0xD: RAW12 - Normal Mode1
0xE: RAW12 - Demux Mode1
0xF: RAW12 - Demux Mode2

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Table 3. V-by-One® HS input format setting (Lane0)
Address
0x1010bit Register Name
[7:6] R_MLINK_NHSEL0

width
2

R/W
R/W

init
2'h2

[5:4] R_MLINK_COL0

2

R/W

2'h1

Description
V-by-One® Main-Link Mode Select (for Lane0)0x2: V-by-One® HS standard mode
Other: Reserved
V-by-One® Main-Link Byte Mode Select (for Lane0)
0x1: 3Byte mode
0x2: 4Byte mode
Other: Reserved* use case setting example
MPRF : 0x2
RGB888 or RGB565 : 0x1
YUV422 - Normal Mode1 : 0x1
YUV422 - Normal Mode2 : 0x1
YUV422 - Normal Mode3 : 0x1
YUV422 - Demux Mode1 : 0x2
YUV422 - Demux Mode2 : 0x2
RAW8 - Normal Mode1 : 0x1
RAW8 - Normal Mode2 : 0x1
RAW8 - Demux Mode1 : 0x2
RAW10 - Normal Mode1 : 0x1
RAW10 - Demux Mode1 : 0x2
RAW10 - Demux Mode2 : 0x1
RAW12 - Normal Mode1 : 0x1
RAW12 - Demux Mode1 : 0x2
RAW12 - Demux Mode2 : 0x1

Table 4. V-by-One® HS input format setting (Lane1)
Address
0x1014

bit Register Name
[7:6] R_MLINK_NHSEL1

width
2

R/W
R/W

init
2'h2

[5:4] R_MLINK_COL1

2

R/W

2'h1

Description
V-by-One® Main-Link Mode Select (for Lane1)
0x2: V-by-One® HS standard mode
Ohter: Reserved
V-by-One® Main-Link Byte Mode Select (for Lane1)
0x1: 3Byte mode
0x2: 4Byte mode
Other: Reserved* use case setting example
MPRF : 0x2
RGB888 or RGB565 : 0x1
YUV422 - Normal Mode1 : 0x1
YUV422 - Normal Mode2 : 0x1
YUV422 - Normal Mode3 : 0x1
YUV422 - Demux Mode1 : 0x2
YUV422 - Demux Mode2 : 0x2
RAW8 - Normal Mode1 : 0x1
RAW8 - Normal Mode2 : 0x1
RAW8 - Demux Mode1 : 0x2
RAW10 - Normal Mode1 : 0x1
RAW10 - Demux Mode1 : 0x2
RAW10 - Demux Mode2 : 0x1
RAW12 - Normal Mode1 : 0x1
RAW12 - Demux Mode1 : 0x2
RAW12 - Demux Mode2 : 0x1

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Table 5. V-by-One® HS input format setting (Lane2)
Address
0x1018bit Register Name
[7:6] R_MLINK_NHSEL2

width
2

R/W
R/W

init
2'h2

[5:4] R_MLINK_COL2

2

R/W

2'h1

Description
V-by-One® Main-Link Mode Select (for Lane2)
0x2: V-by-One® HS standard mode
Other: Reserved
V-by-One® Main-Link Byte Mode Select (for Lane2)
0x1: 3Byte mode
0x2: 4Byte mode
Other: Reserved* use case setting example
MPRF : 0x2
RGB888 or RGB565 : 0x1
YUV422 - Normal Mode1 : 0x1
YUV422 - Normal Mode2 : 0x1
YUV422 - Normal Mode3 : 0x1
YUV422 - Demux Mode1 : 0x2
YUV422 - Demux Mode2 : 0x2
RAW8 - Normal Mode1 : 0x1
RAW8 - Normal Mode2 : 0x1
RAW8 - Demux Mode1 : 0x2
RAW10 - Normal Mode1 : 0x1
RAW10 - Demux Mode1 : 0x2
RAW10 - Demux Mode2 : 0x1
RAW12 - Normal Mode1 : 0x1
RAW12 - Demux Mode1 : 0x2
RAW12 - Demux Mode2 : 0x1

Table 6. V-by-One® HS input format setting (Lane3)
Address
0x101Cbit Register Name
[7:6] R_MLINK_NHSEL3

width
2

R/W
R/W

init
2'h2

[5:4] R_MLINK_COL3

2

R/W

2'h1

Description
V-by-One® Main-Link Mode Select (for Lane3)
0x2: V-by-One® HS standard mode
Other: Reserved
V-by-One® Main-Link Byte Mode Select (for Lane3)
0x1: 3Byte mode
0x2: 4Byte mode
Other: Reserved* use case setting example
MPRF : 0x2
RGB888 or RGB565 : 0x1
YUV422 - Normal Mode1 : 0x1
YUV422 - Normal Mode2 : 0x1
YUV422 - Normal Mode3 : 0x1
YUV422 - Demux Mode1 : 0x2
YUV422 - Demux Mode2 : 0x2
RAW8 - Normal Mode1 : 0x1
RAW8 - Normal Mode2 : 0x1
RAW8 - Demux Mode1 : 0x2
RAW10 - Normal Mode1 : 0x1
RAW10 - Demux Mode1 : 0x2
RAW10 - Demux Mode2 : 0x1
RAW12 - Normal Mode1 : 0x1
RAW12 - Demux Mode1 : 0x2
RAW12 - Demux Mode2 : 0x1

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THCV244A-QP_ Rev.4.31_E

MPRF (Main-Link PRivate Format)
MPRF format encoding preserves original data packet input to V-by-One® HS transmitter and output the data
packet from THCV244A-QP. The counterpart transmitter must have installed MPRF format decoder like
THCV241A-Q because MPRF is not standard format.
Input V-by-One® HS Byte Mode is 4Byte Mode.
Video formats: RAW8/10/12/14/16/20, YUV422/420, RGB888/666/565, JPEG, and User-defined generic 8-bit
are all supported with MPRF.

CMOS Sensor

CMOS Sensor

CMOS Sensor

CMOS Sensor

Original
Data packet(format,payload, etc.)

Original
Data packet(format,payload, etc.)

Original
Data packet(format,payload, etc.)

Original
Data packet(format,payload, etc.)

THCV241A-Q

THCV241A-Q

THCV241A-Q

THCV241A-Q

Figure 3.

Copyright©2023 THine Electronics, Inc.

Main-Link
MPRF
formatMain-Link
MPRF
formatMain-Link
MPRF
format

THCV244A-QP

Preserved
Data packet(format,payload, etc.)

Processor
In a SoC

Main-Link
MPRF
formatMPRF (Main-Link PRivate Format)

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THCV244A-QP_ Rev.4.31_E
V-by-One® HS standard format
THCV244A-QP input format capabilities as receiver are shown as follows. D[31:0] indicates V-by-One® HS
standard version1.5 UnPacker packet definition. Data can be transmitted normally only when both transmitter andreceiver are set to the same available format. Some of the THCV244A-QP format may not be supported byparticular counterpart transmitter because THCV244A-QP prepares multiple formats that suit to multiple
transmitter devices alternatives.

Table 7. V-by-One® HS input data mapping format (1/4)
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]RGB888
0
0
0
0
0
0
0
0
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]

Copyright©2023 THine Electronics, Inc.

Normal Mode1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]Normal Mode2
0
0
0
0
0
0
0
0
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]

12/69

YUV422
Normal Mode3
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
0
0
0
0
0
0
0
0
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]Demux Mode1
Y[7](1st pixel)
Y[6](1st pixel)
Y[5](1st pixel)
Y[4](1st pixel)
Y[3](1st pixel)
Y[2](1st pixel)
Y[1](1st pixel)
Y[0](1st pixel)
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Y[7](2nd pixel)
Y[6](2nd pixel)
Y[5](2nd pixel)
Y[4](2nd pixel)
Y[3](2nd pixel)
Y[2](2nd pixel)
Y[1](2nd pixel)
Y[0](2nd pixel)
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]

Demux Mode2
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Y[7](1st pixel)
Y[6](1st pixel)
Y[5](1st pixel)
Y[4](1st pixel)
Y[3](1st pixel)
Y[2](1st pixel)
Y[1](1st pixel)
Y[0](1st pixel)
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Y[7](2nd pixel)
Y[6](2nd pixel)
Y[5](2nd pixel)
Y[4](2nd pixel)
Y[3](2nd pixel)
Y[2](2nd pixel)
Y[1](2nd pixel)
Y[0](2nd pixel)

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

Table 8. V-by-One® HS input data mapping format (2/4)
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW8
Normal Mode2
0
0
0
0
0
0
0
0
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)
0
0
0
0
0
0
0
0
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)

Normal Mode1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)

13/69

Demux Mode1
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)
RAW[7] (4th pixel)
RAW[6] (4th pixel)
RAW[5] (4th pixel)
RAW[4] (4th pixel)
RAW[3] (4th pixel)
RAW[2] (4th pixel)
RAW[1] (4th pixel)
RAW[0] (4th pixel)
RAW[7] (3rd pixel)
RAW[6] (3rd pixel)
RAW[5] (3rd pixel)
RAW[4] (3rd pixel)
RAW[3] (3rd pixel)
RAW[2] (3rd pixel)
RAW[1] (3rd pixel)
RAW[0] (3rd pixel)

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

Table 9. V-by-One® HS input data mapping format (3/4)
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW10
Demux Mode1
0
0
0
0
0
0
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](1st pixel)
RAW[2](1st pixel)
0
0
0
0
0
0
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)

Normal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[1]
RAW[0]
RAW[9]
RAW[8]
RAW[7]
RAW[6]
RAW[5]
RAW[4]
RAW[3]
RAW[2]

14/69

Demux Mode2
0
0
0
0
0
0
0
0
0
0
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](1st pixel)
RAW[2](1st pixel)
00RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

Table 10. V-by-One® HS input data mapping format (4/4)
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW12
Demux Mode10000RAW[3](1st pixel)
RAW[2](1st pixel)
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[11](1st pixel)
RAW[10](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
0000RAW[3](2nd pixel)
RAW[2](2nd pixel)
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[11](2nd pixel)
RAW[10](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)

Normal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[3]
RAW[2]
RAW[1]
RAW[0]
RAW[11]
RAW[10]RAW[9]
RAW[8]
RAW[7]
RAW[6]
RAW[5]
RAW[4]

15/69

Demux Mode2
0
0
0
0
0
0
0
0
RAW[3](1st pixel)
RAW[2](1st pixel)
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[11](1st pixel)
RAW[10](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[11](2nd pixel)
RAW[10](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E
6.4.

eader/Packet/Sync Pre-processing

Setting of Header, Packet and Sync pre-processing can be configurable by 2-wire access to internal register.
Settings of Header, Packet and Sync pre-processing exist for each Main-Link input lanes respectively.

Table 11. Header/Packet/Sync pre-processing setting for Main-Link (Lane0)
Address
0x1100bit Register Name
[7:1] reserved[0] R_VX1_PH_EN0

width
7
1

R/W
R/W

Init
7'h00
1'h0

0x1101[7:1] reserved[0] R_VX1_CRC_EN0

7
1

R/W

7'h00
1'h0

0x1102[7:1] reserved[0] R_VX1_SP_EN0

7
1

R/W

7'h00
1'h0

0x1103[7:1] reserved[0] R_VX1_VVALID_MODE0

7
1

R/W

7'h00
1'h0

0x1104[7:1] reserved[0] R_VX1_VSYNC_POL0

7
1

R/W

7'h00
1'h0

0x1105[7:0] R_VX1_WC_LOW0

8

R/W

8'h00

0x1106[7:0] R_VX1_WC_UP0

8

R/W

8'h00

0x1107[7:0] R_VX1_DATAID0

8

R/W

8'h00

0x1108[7:1] reserved[0] R_VX1_MASK_ECC0

7
1

R/W

7'h00
1'h0

0x1109

[7:1]
[0]
[7:1]
[0]

reserved
reservedL
reserved
R_CRC_ERR0

7
1
7
1

R/W
RC

7'h00
1'h0
7'h00
1'h0

0x110B[7:1] reserved[0] R_ECC_CRCT_ERR0

7
1

RC

7'h00
1'h0

0x110C[7:1] reserved[0] R_ECC_DOUBLE_ERR0

7
1

RC

7'h00
1'h0

0x110A

Copyright©2023 THine Electronics, Inc.

Description
MIPI Packet Header mode select for Main-Link Lane0
0x0: Packet Header is generated by register settings
0x1: Packet Header is through from Main-Link input stream
Main-Link CRC mode select for Main-Link Lane0
0x0: Main-Link input stream does not have CRC data
0x1: Main-Link input stream has CRC data
MIPI Short Packet mode select for Main-Link Lane0
0x0: Main-Link input stream does not have Short Packet
0x1: Short Packet is through from Main-Link input stream
MIPI Frame Start & Frame End (FS/FE) mode select for Main-Link Lane0
0x0: FS/FE data are through from Main-Link input stream
0x1: FS/FE data are generated based on the timing of the VSYNC signal<this register is valid only when 0x1103[0]=0x1>
Polarity setting of VSYNC signal to generate FS/FE for Main-Link Lane0
0x0: use Low pulse VSYNC signal (FE: Falling timing, FS: Rising timing)
0x1: use High pulse VSYNC signal (FE: Rising timing, FS: Falling timing)<this register is valid only when 0x1100[0]=0x0>
MIPI Packet Header's Word Count (LSB) manual setting for Main-Link Lane0<this register is valid only when 0x1100[0]=0x0>
MIPI Packet Header's Word Count (MSB) manual setting for Main-Link Lane0<this register is valid only when 0x1100[0]=0x0>
MIPI Packet Header's Data ID manual setting for Main-Link Lane0* use case setting example
YUV422-8bit: 0x1E
RGB888: 0x24
RAW8: 0x2A
RAW10: 0x2B
RAW12: 0x2C
Masking and Ignoring both MIPI short packet and MIPI long packet when ECC
double error is detected for Main-Link Lane0
0x0: Disable
0x1: Mask Processing when ECC double error is detectedmust be left 0x0 (default setting)
CRC error register for Main-Link Lane0(clear the error status after reading register automatically)
0x0: no error
0x1: detect CRC error
ECC single error register for Main-Link Lane0(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC single error
ECC double error register for Main-Link Lane0(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC double error

16/69

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

Table 12. Header/Packet/Sync pre-processing setting for Main-Link (Lane1)
Address
0x1200bit Register Name
[7:1] reserved[0] R_VX1_PH_EN1

width
7
1

R/W
R/W

Init
7'h00
1'h0

0x1201[7:1] reserved[0] R_VX1_CRC_EN1

7
1

R/W

7'h00
1'h0

0x1202[7:1] reserved[0] R_VX1_SP_EN1

7
1

R/W

7'h00
1'h0

0x1203[7:1] reserved[0] R_VX1_VVALID_MODE1

7
1

R/W

7'h00
1'h0

0x1204[7:1] reserved[0] R_VX1_VSYNC_POL1

7
1

R/W

7'h00
1'h0

0x1205[7:0] R_VX1_WC_LOW1

8

R/W

8'h00

0x1206[7:0] R_VX1_WC_UP1

8

R/W

8'h00

0x1207[7:0] R_VX1_DATAID1

8

R/W

8'h00

0x1208[7:1] reserved[0] R_VX1_MASK_ECC1

7
1

R/W

7'h00
1'h0

0x1209

[7:1]
[0]
[7:1]
[0]

reserved
reservedL
reserved
R_CRC_ERR1

7
1
7
1

R/W
RC

7'h00
1'h0
7'h00
1'h0

0x120B[7:1] reserved[0] R_ECC_CRCT_ERR1

7
1

RC

7'h00
1'h0

0x120C[7:1] reserved[0] R_ECC_DOUBLE_ERR1

7
1

RC

7'h00
1'h0

0x120A

Copyright©2023 THine Electronics, Inc.

Description
MIPI Packet Header mode select for Main-Link Lane1
0x0: Packet Header is generated by register settings
0x1: Packet Header is through from Main-Link input stream
Main-Link CRC mode select for Main-Link Lane1
0x0: Main-Link input stream does not have CRC data
0x1: Main-Link input stream has CRC data
MIPI Short Packet mode select for Main-Link Lane1
0x0: Main-Link input stream does not have Short Packet
0x1: Short Packet is through from Main-Link input stream
MIPI Frame Start & Frame End (FS/FE) mode select for Main-Link Lane1
0x0: FS/FE data are through from Main-Link input stream
0x1: FS/FE data are generated based on the timing of the VSYNC signal<this register is valid only when 0x1203[0]=0x1>
Polarity setting of VSYNC signal to generate FS/FE for Main-Link Lane1
0x0: use Low pulse VSYNC signal (FE: Falling timing, FS: Rising timing)
0x1: use High pulse VSYNC signal (FE: Rising timing, FS: Falling timing)<this register is valid only when 0x1200[0]=0x0>
MIPI Packet Header's Word Count (LSB) manual setting for Main-Link Lane1<this register is valid only when 0x1200[0]=0x0>
MIPI Packet Header's Word Count (MSB) manual setting for Main-Link Lane1<this register is valid only when 0x1200[0]=0x0>
MIPI Packet Header's Data ID manual setting for Main-Link Lane1* use case setting example
YUV422-8bit: 0x1E
RGB888: 0x24
RAW8: 0x2A
RAW10: 0x2B
RAW12: 0x2C
Masking and Ignoring both MIPI short packet and MIPI long packet when ECC
double error is detected for Main-Link Lane1
0x0: Disable
0x1: Mask Processing when ECC double error is detectedmust be left 0x0 (default setting)
CRC error register for Main-Link Lane1(clear the error status after reading register automatically)
0x0: no error
0x1: detect CRC error
ECC single error register for Main-Link Lane1(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC single error
ECC double error register for Main-Link Lane1(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC double error

17/69

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

Table 13. Header/Packet/Sync pre-processing setting for Main-Link (Lane2)
Address
0x1300bit Register Name
[7:1] reserved[0] R_VX1_PH_EN2

width
7
1

R/W
R/W

Init
7'h00
1'h0

0x1301[7:1] reserved[0] R_VX1_CRC_EN2

7
1

R/W

7'h00
1'h0

0x1302[7:1] reserved[0] R_VX1_SP_EN2

7
1

R/W

7'h00
1'h0

0x1303[7:1] reserved[0] R_VX1_VVALID_MODE2

7
1

R/W

7'h00
1'h0

0x1304[7:1] reserved[0] R_VX1_VSYNC_POL2

7
1

R/W

7'h00
1'h0

0x1305[7:0] R_VX1_WC_LOW2

8

R/W

8'h00

0x1306[7:0] R_VX1_WC_UP2

8

R/W

8'h00

0x1307[7:0] R_VX1_DATAID2

8

R/W

8'h00

0x1308[7:1] reserved[0] R_VX1_MASK_ECC2

7
1

R/W

7'h00
1'h0

0x1309

[7:1]
[0]
[7:1]
[0]

reserved
reservedL
reserved
R_CRC_ERR2

7
1
7
1

R/W
RC

7'h00
1'h0
7'h00
1'h0

0x130B[7:1] reserved[0] R_ECC_CRCT_ERR2

7
1

RC

7'h00
1'h0

0x130C[7:1] reserved[0] R_ECC_DOUBLE_ERR2

7
1

RC

7'h00
1'h0

0x130A

Copyright©2023 THine Electronics, Inc.

Description
MIPI Packet Header mode select for Main-Link Lane2
0x0: Packet Header is generated by register settings
0x1: Packet Header is through from Main-Link input stream
Main-Link CRC mode select for Main-Link Lane2
0x0: Main-Link input stream does not have CRC data
0x1: Main-Link input stream has CRC data
MIPI Short Packet mode select for Main-Link Lane2
0x0: Main-Link input stream does not have Short Packet
0x1: Short Packet is through from Main-Link input stream
MIPI Frame Start & Frame End (FS/FE) mode select for Main-Link Lane2
0x0: FS/FE data are through from Main-Link input stream
0x1: FS/FE data are generated based on the timing of the VSYNC signal<this register is valid only when 0x1303[0]=0x1>
Polarity setting of VSYNC signal to generate FS/FE for Main-Link Lane2
0x0: use Low pulse VSYNC signal (FE: Falling timing, FS: Rising timing)
0x1: use High pulse VSYNC signal (FE: Rising timing, FS: Falling timing)<this register is valid only when 0x1300[0]=0x0>
MIPI Packet Header's Word Count (LSB) manual setting for Main-Link Lane2<this register is valid only when 0x1300[0]=0x0>
MIPI Packet Header's Word Count (MSB) manual setting for Main-Link Lane2<this register is valid only when 0x1300[0]=0x0>
MIPI Packet Header's Data ID manual setting for Main-Link Lane2* use case setting example
YUV422-8bit: 0x1E
RGB888: 0x24
RAW8: 0x2A
RAW10: 0x2B
RAW12: 0x2C
Masking and Ignoring both MIPI short packet and MIPI long packet when ECC
double error is detected for Main-Link Lane2
0x0: Disable
0x1: Mask Processing when ECC double error is detectedmust be left 0x0 (default setting)
CRC error register for Main-Link Lane2(clear the error status after reading register automatically)
0x0: no error
0x1: detect CRC error
ECC single error register for Main-Link Lane2(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC single error
ECC double error register for Main-Link Lane2(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC double error

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THCV244A-QP_ Rev.4.31_E

Table 14. Header/Packet/Sync pre-processing setting for Main-Link (Lane3)
Address
0x1400bit Register Name
[7:1] reserved[0] R_VX1_PH_EN3

width
7
1

R/W
R/W

Init
7'h00
1'h0

0x1401[7:1] reserved[0] R_VX1_CRC_EN3

7
1

R/W

7'h00
1'h0

0x1402[7:1] reserved[0] R_VX1_SP_EN3

7
1

R/W

7'h00
1'h0

0x1403[7:1] reserved[0] R_VX1_VVALID_MODE3

7
1

R/W

7'h00
1'h0

0x1404[7:1] reserved[0] R_VX1_VSYNC_POL3

7
1

R/W

7'h00
1'h0

0x1405[7:0] R_VX1_WC_LOW3

8

R/W

8'h00

0x1406[7:0] R_VX1_WC_UP3

8

R/W

8'h00

0x1407[7:0] R_VX1_DATAID3

8

R/W

8'h00

0x1408[7:1] reserved[0] R_VX1_MASK_ECC3

7
1

R/W

7'h00
1'h0

0x1409

[7:1]
[0]
[7:1]
[0]

reserved
reservedL
reserved
R_CRC_ERR3

7
1
7
1

R/W
RC

7'h00
1'h0
7'h00
1'h0

0x140B[7:1] reserved[0] R_ECC_CRCT_ERR3

7
1

RC

7'h00
1'h0

0x140C[7:1] reserved[0] R_ECC_DOUBLE_ERR3

7
1

RC

7'h00
1'h0

0x140A

Copyright©2023 THine Electronics, Inc.

Description
MIPI Packet Header mode select for Main-Link Lane3
0x0: Packet Header is generated by register settings
0x1: Packet Header is through from Main-Link input stream
Main-Link CRC mode select for Main-Link Lane3
0x0: Main-Link input stream does not have CRC data
0x1: Main-Link input stream has CRC data
MIPI Short Packet mode select for Main-Link Lane3
0x0: Main-Link input stream does not have Short Packet
0x1: Short Packet is through from Main-Link input stream
MIPI Frame Start & Frame End (FS/FE) mode select for Main-Link Lane3
0x0: FS/FE data are through from Main-Link input stream
0x1: FS/FE data are generated based on the timing of the VSYNC signal<this register is valid only when 0x1403[0]=0x1>
Polarity setting of VSYNC signal to generate FS/FE for Main-Link Lane3
0x0: use Low pulse VSYNC signal (FE: Falling timing, FS: Rising timing)
0x1: use High pulse VSYNC signal (FE: Rising timing, FS: Falling timing)<this register is valid only when 0x1400[0]=0x0>
MIPI Packet Header's Word Count (LSB) manual setting for Main-Link Lane3<this register is valid only when 0x1400[0]=0x0>
MIPI Packet Header's Word Count (MSB) manual setting for Main-Link Lane3<this register is valid only when 0x1400[0]=0x0>
MIPI Packet Header's Data ID manual setting for Main-Link Lane3* use case setting example
YUV422-8bit: 0x1E
RGB888: 0x24
RAW8: 0x2A
RAW10: 0x2B
RAW12: 0x2C
Masking and Ignoring both MIPI short packet and MIPI long packet when ECC
double error is detected for Main-Link Lane3
0x0: Disable
0x1: Mask Processing when ECC double error is detectedmust be left 0x0 (default setting)
CRC error register for Main-Link Lane3(clear the error status after reading register automatically)
0x0: no error
0x1: detect CRC error
ECC single error register for Main-Link Lane3(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC single error
ECC double error register for Main-Link Lane3(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC double error

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THCV244A-QP_ Rev.4.31_E

6.5.

MIPI Line Start/Line End code output setting

Both Line Start (LS) code and Line End (LE) code are optional code in MIPI CSI-2. When R_NONUSE_LSLE
register is set 1’b1, both inputted LS and LE data are masked and ignored. On the other hands, when
R_NONUSE_LSLE register is set 1’b0, both inputted LS and LE data are transmitted normally. For a systemthat do not use LS/LE code, R_NONUSE_LSLE_ register must be set 1’b1 to prevent unexpected behavior.

Table 15. MIPI Line Start and Line End code setting
Address
0x1013

bit Register Name
[7:1] ReservedL[0] R_NONUSE_LSLE

Copyright©2023 THine Electronics, Inc.

width
7
1

R/W
R/W
R/W

init
7'h00
1'h0

Description
must be left 0x00 (default setting)Line start and Line end code use or non-use setting for all Main-LInk lane
0x0: When a system is used mipi line start and line end, must be set 0x0 (*)
0x1: When a system is not use mipi line start and line end, must be set 0x1(*) When 0x1013[0] = 0x0, 0x1606[1:0] must be set 0x3.

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THCV244A-QP_ Rev.4.31_E
6.6.

PLL setting reference

PLL setting is required. PLL setting set R_PLL_SETTING[47:0] is related with Main-Link data-rate.
PLL Configuration
F(Main-Link input)
10-133MHz

F(VCO)
500-1490MHz

Reference Divider
x 1/RefDiv
1-7

PFD

F(PFD)> 10MHz

1st Output Divider
x 1/OutDiv1
1-7

VCO

2nd Output Divider
x 1/OutDiv2
1-7

F(MIPI output)
80-1490MHz

FeedBack Divider
x 1/FBDiv
20-130Figure 4. Reference clock supply basic method

PLL_SETTING[47:0] must be selected proper to meet below constraints.
Table 16. PLL constraints
symbolF(IN)RefDiv
FBDiv
OutDiv1
OutDiv2
F(PFD)
F(VCO)
F(OUT)

description
PLL input pixel clock frequency
Reference Divider value
FeedBack Divider value
1st Output Divider value (OutDiv1 must be >= OutDiv2)
2nd Output Divider value (OutDiv1 must be >= OutDiv2)
PFD frequency
VCO frequency
PLL output pixel clock frequency

min
10
1
20
1
1
10
500
80

typ
-

max
133.3
7
130
7
7
1490
1490

unit
MHz
MHz
MHz
MHz

Pixel clock frequency made by PLL is calculated as below.
[PCLK.input] = Pixel clock recovered on V-by-One® HS per lane = [F(Main-Link input)] = F(IN)[F(Main-Link input)] = Main-Link data-rate per lane / (Byte mode x 8 x 10/8)

MIPI data-rate per lane (Mbps) = [F(MIPI output)] (MHz)= MIPI High Speed mode data-rate per lane

F(VCO) =[PCLK.output] = [F(MIPI output)] =[F(MIPI output)][F(Main-Link input)]=[F(Main-Link input)] x [FBDiv][RefDiv][F(Main-Link input)] x [FBDiv][RefDiv] x [OutDiv1] x [OutDiv2]= F(OUT)[FBDiv][RefDiv] x [OutDiv1] x [OutDiv2]MIPI High Speed mode DDR output clock per lane = [F(MIPI output)] / 2 (MHz)Copyright©2023 THine Electronics, Inc.

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THCV244A-QP_ Rev.4.31_E

Table 17. PLL setting
Address
0x10 210x10 220x10 230x10 240x10 25
0x10 26

bit
[7:0]
[7:3]
[2:0]
[7]
[6:4]
[3]
[2:0]
[7:0]
[7:0]
[7:0]

Register Name
R_PLL_SETTING[47:40]
R_PLL_SETTING[39:35]
R_PLL_SETTING[34:32]
R_PLL_SETTING[31]R_PLL_SETTING[30:28]
R_PLL_SETTING[27]
R_PLL_SETTING[26:24]
R_PLL_SETTING[23:16]
R_PLL_SETTING[15:8]
R_PLL_SETTING[7:0]

width R/W
8
R/W
5
3
R/W
1
3
R/W
1
3
R/W
8
R/W
8
R/W
8
R/W

Init
Description
8'h0 PLL setting value, Feedback Divider value (integer part)5'h0 PLL setting value (Must be set 0)
3'h0 PLL setting value, Reference Divider value
1'h0 PLL setting value (Must be set 0)
3'h0 PLL setting value, OutDiv1 (OutDiv1 must be >= OutDiv2)
1'h0 PLL setting value (Must be set 0)
3'h0 PLL setting value, OutDiv2 (OutDiv1 must be >= OutDiv2)
8'h0 PLL setting value, Feedback Divider value (decimal part MSB)
8'h0 PLL setting value, Feedback Divider value (decimal part)8'h0 PLL setting value, Feedback Divider value (decimal part LSB)

PLL setting must fulfill below frequency ratio rule.
Table 18. PLL frequency ratio rule
FormatMPRF
RGB888
YUV422 Normal
YUV422 Demux
RAW8 Normal
RAW8 Demux
RAW10 Normal
RAW10 Demux
RAW12 Normal
RAW12 Demux[F(MIPI output)] / [F(Main-Link input)]frequency ratio
1*[Main-Link input lane#]*4*8/ [MIPI output lane#]
3/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]
2/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]
1*[Main-Link input lane#]*4*8/ [MIPI output lane#]
2/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]
1*[Main-Link input lane#]*4*8/ [MIPI output lane#]
10/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]
20/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]
12/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]
24/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]

Below Table is Look Up Table example for typical cases. (“PLL[*]” stands for “R_PLL_SETTING[*]”)
Table 19. PLL setting Look Up Table example
index condition1
720p30fps RAW3
720p30fps YUV422
4
720p60fps RAW
51080p30fps RAW6
720p60fps YUV422
71080p30fps YUV422
8
720p60fps YUV422
9720p120fps RAW
101080p60fps RAW
11
720p120fps YUV422
121080p60fps YUV422
131080p120f ps RAW
15
720p30fps RAW
17
720p30fps YUV422
18
720p60fps RAW
191080p30fps RAW
20
720p60fps YUV422
211080p30fps YUV422

Main-Link input
742.5Mbps 1lane MPRF
750Mbps 1lane MPRF

MIPI output
594Mbps x1lane
600Mbps x1lane

1.114Gbps 1lane MPRF

445.5Mbps x2lane

1.485Gbps 1lane MPRF

594Mbps x2lane

1.485Gbps 1lane MPRF

594Mbps x2lane x2

2.2275Gbps 1lane MPRF

891Mbps x2lane

2.97Gbps 1lane MPRF

594Mbps x4lane

2.2275Gbps 2lane MPRF
990Mbps 1lane RAW12 Demux
1.6Gbps 1lane YUV422 Normal

891Mbps x4lane
594Mbps x1lane
640Mbps x1lane

1.485Gbps 1lane RAW12 Demux 445.5Mbps x2lane
2.97Gbps 1lane YUV422 Normal 594Mbps x2lane

Distribution
off
off
off
off
off
off
on
off
off
off
off
off
off
off
off
off
off
off

F(MLINK in)
18.562518.75
27.84375
27.84375
37.12537.12537.12555.6875
55.6875
74.25
74.25
55.687524.75
40
37.12537.12574.25
74.25

F(VCO)
1188
1200
891
891
1188
1188
1188
891
891
1188
1188
891
594
640
891
891
1188
1188

F(MIPI out)
594
600
445.5
445.5
594
594
594
891
891
594
594
891
594
640
445.5
445.5
594
594

PLL[47:40]
0x40
0x40
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x18
0x20
0x30
0x30
0x20
0x20

PLL[39:32]
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x02
0x02
0x02
0x02
0x02
0x01
0x02
0x02
0x02
0x02
0x02

PLL[31:24]
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x11
0x11
0x21
0x21
0x11
0x11
0x11
0x21
0x21
0x21
0x21

PLL[23:16]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[15:8]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

For informative example just for laboratory trial use not for mass-production, 1080p60fps RAW10 1.49Gbps
MPRF format Data stream handler Main-Link 4port (A/B/C/D) input / MIPI 2PORT2LANE (A+B / C+D) output
can be temporarily activated with PLL[47:40]='h20, PLL[34:32]='h01, PLL[30:28]='h1, PLL[26:24] ='h1.

Copyright©2023 THine Electronics, Inc.

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THCV244A-QP_ Rev.4.31_E
6.7.

Data stream handling

Setting of data stream handling can be configurable by 2-wire access to internal register.

Table 20. Data stream handler function mode setting
Address
0x1500bit Register Name
[7:2] reserved[1:0] R_DSHNDLR_FUNC_MODE

0x1501[7:5] reserved[4:0] R_MODE_NO

width
6
2

R/W
R/W

Init
6'h00
2'h0

3
5

R/W

3'h0
5'h00

Description
Main-Link Data Stream Handling function mode select0x00: Data Stream Handling mode1
0x01: Data Stream Handling mode2
Others: Reserved
Main-Link Data Stream Handling mode number

Data stream handling mode1
Data stream handling mode1 does not manage line memory and stream non-buffering streaming.
Video stream switch and copy/distribution can be achieved by this mode.

0x0

R_MODE_NO

R_DSHNDLR_FUNC_MODE

Table 21. Data stream handling mode1 setting

port0

port1

port2

port3

port0

0x0

Cam A

-

-

-

Cam A

0x1

Cam A

-

-

-

Cam A

0x2

-

Cam B

-

-

Cam B

0x3

-

Cam B

-

-

Cam B

0x4

-

-

Cam C

-

Cam C

0x5

-

-

Cam C

-

Cam C

0x6

-

-

-

Cam D

Cam D

0x7

-

-

-

Cam D

Cam D

0x8

Cam A

Cam A

-

-

0x9

-

-

Cam B

0xA

Cam A

Cam B

0xB

Cam A

Cam B

Main-Link Input

MIPI Output

Input port
numberDistribution

Output port
numberOutput
Swap

1

Off

1

-

1

On

2

-

1

Off

1

-

1

On

2

-

1

Off

1

-

1

On

2

-

1

Off

1

-

1

On

2

-

Cam A

1(2port)

Off

1

-

Cam B

Cam B

1(2port)

Off

1

-

-

-

Cam A

Cam B

2

-

2

Off

-

-

Cam B

Cam A

2

-

2

On

Copyright©2023 THine Electronics, Inc.

23/69

port1
Cam A
Cam B
Cam C
Cam D

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THCV244A-QP_ Rev.4.31_E
Data stream handling mode2
Data stream handling mode2 manage buffering of data stream with line memory. Output order is First-In-FirstOut scheme. Virtual channel IDs of each Main-Link port can be re-numbered by 2-wire register control. RGB888
format is not supported on Data stream handling mode2.

Main-Link input

Main-Link port0

Camera1 Line1 VirtualCh.0 long packet

Main-Link port1

Camera1 Line2 VirtualCh.0 long packet

Camera2 Line1 VirtualCh.0 long packet

Main-Link port2

Camera2 Line2 VirtualCh.0 long packet

Camera3 Line1 VirtualCh.0 long packet

Main-Link port3

Camera3 Line2 VirtualCh.0 long packet

Camera4 Line1 VirtualCh.0 long packet

Camera4 Line2 VirtualCh.0 long packet

MIPI output

MIPI port0

Cam1 Line1
VC0

Cam4 Line1
VC3

Cam2 Line1
VC1

Cam3 Line1
VC2

Cam1 Line2
VC0

Cam4 Line2
VC3

Cam2 Line2
VC1

Cam3 Line2VC2MIPI port1

Cam1 Line1
VC0

Cam4 Line1
VC3

Cam2 Line1
VC1

Cam3 Line1
VC2

Cam1 Line2
VC0

Cam4 Line2
VC3

Cam2 Line2
VC1

Cam3 Line2
VC2

Figure 5. Data stream handling mode2 example 4port (A/B/C/D) input integration (A+B+C+D) output

R_MODE_NO

R_DSHNDLR_FUNC_MODE

Table 22. Data stream handling mode2 setting

port0

port1

port2

port3

port0

0x00

Cam A

Cam B

-

-

A+B

0x01

Cam A

Cam B

-

-

A+B

0x02

Cam A

Cam A

Cam C

-

0x03

Cam A

Cam A

Cam B

0x04

Cam A

Cam B

0x05

Cam A

0x06

Main-Link Input

MIPI Output

Input port
numberDistribution

Output port
numberOutput
Swap

2

Off

1

-

2

On

2

-

A+C

2(3port)

Off

1

-

Cam B

A+B

2(4port)

Off

1

-

Cam C

-

A+B+C

3

Off

1

-

Cam B

Cam C

-

A+B+C

3

On

2

-

Cam A

Cam A

Cam C

Cam D

A+C+D

3(2port)

Off

1

-

0x07

Cam A

Cam B

Cam C

-

B+C

3(2select)

Off

2

-

0x08

Cam A

Cam B

Cam C

-

B+C

3(2select)

On

1

-

0x09

Cam A

Cam B

Cam C

-

A+C

3(2select)

Off

2

-

0x0A

Cam A

Cam B

Cam C

-

A+C

3(2select)

On

1

-

0x0B

Cam A

Cam B

Cam C

Cam D

A+B+C+D

4

Off

1

-

0x1 0x0C

Cam A

Cam B

Cam C

Cam D

A+B+C+D

4

On

2

-

0x0D

Cam A

Cam B

Cam C

Cam D

A+D

4(2select)

Off

1

-

0x0E

Cam A

Cam B

Cam C

Cam D

A+D

4(2select)

On

1

-

0x0F

Cam A

Cam B

Cam C

Cam D

B+D

4(2select)

Off

1

-

0x10

Cam A

Cam B

Cam C

Cam D

B+D

4(2select)

On

1

-

0x11

Cam A

Cam B

Cam C

Cam D

C+D

4(2select)

Off

1

-

0x12

Cam A

Cam B

Cam C

Cam D

C+D

C+D

4(2select)

On

1

-

0x13

Cam A

Cam B

Cam C

-

A+B

C

3

-

2

Off

0x14

Cam A

Cam B

Cam C

-

C

A+B

3

-

2

On

0x15

Cam A

Cam B

Cam C

Cam D

A+B

C+D

4

-

2

Off

0x16

Cam A

Cam B

Cam C

Cam D

C+D

A+B

4

-

2

On

0x17

Cam A

Cam B

Cam C

Cam D

A+B+C

D

4

-

2

Off

0x18

Cam A

Cam B

Cam C

Cam D

D

A+B+C

4

-

2

On

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port1
A+B

A+B+C

B+C
A+C
A+B+C+D
A+D
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THCV244A-QP_ Rev.4.31_E

In case of Data stream handling mode2, Virtual Channel ID on each V-by-One® HS input lanes are recognized
and re-numbering according to register setting into integrated interleaved MIPI output stream.

Table 23. Data stream handling mode2 Virtual channel renumbering setting
Address
0x150Bbit Register Name
[7:0] R_MODE2_VC_REQCTRL0

width
8

R/W
R/W

Init
8'hE4

0x150C[7:0] R_MODE2_VC_REQCTRL1

8

R/W

8'hE4

0x150D[7:0] R_MODE2_VC_REQCTRL2

8

R/W

8'hE4

0x150E[7:0] R_MODE2_VC_REQCTRL3

8

R/W

8'hE4

6.8.

Description<this register is valid only when 0x1500[1:0]=0x1>
renumbering Virtual Channel (VC) for Lane0[7:6] exchanging VC number from inputted VC3[5:4] exchanging VC number from inputted VC2[3:2] exchanging VC number from inputted VC1[1:0] exchanging VC number from inputted VC0<this register is valid only when 0x1500[1:0]=0x1>
renumbering Virtual Channel (VC) for Lane1[7:6] exchanging VC number from inputted VC3[5:4] exchanging VC number from inputted VC2[3:2] exchanging VC number from inputted VC1[1:0] exchanging VC number from inputted VC0<this register is valid only when 0x1500[1:0]=0x1>
renumbering Virtual Channel (VC) for Lane2[7:6] exchanging VC number from inputted VC3[5:4] exchanging VC number from inputted VC2[3:2] exchanging VC number from inputted VC1[1:0] exchanging VC number from inputted VC0<this register is valid only when 0x1500[1:0]=0x1>
renumbering Virtual Channel (VC) for Lane3[7:6] exchanging VC number from inputted VC3[5:4] exchanging VC number from inputted VC2[3:2] exchanging VC number from inputted VC1[1:0] exchanging VC number from inputted VC0

MIPI Virtual Channel

When MIPI PH (Packet Header) is intake from V-by-One® HS on Data stream handling mode1, MIPI Virtual
Channel information in PH is also bridged from V-by-One® HS at the same time.
On the other hands with Data stream handling mode2, Virtual Channel information on each V-by-One® HS
input lanes are recognized and re-labeled according to register setting into integrated interleaved MIPI output
stream.

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THCV244A-QP_ Rev.4.31_E
6.9.

MIPI output setting

Setting of MIPI output can be configurable by 2-wire access to internal register.

Table 24. MIPI output setting (1/3)
Address
0x1600bit Register Name
[7:5] Reserved[4:0] R_ANALOG

width
3
5

R/W
R/W

Init
3'h0
5'h00

Description[4] MIPI Power Down
0x0: Power Down
0x1: Normal operation[3] MIPI Soft Reset
0x0: Reset
0x1: Normal operation[2] ReservedL (must be set 0x0)
[1] ReservedH (must be set 0x1)
[0] ReservedL (must be set 0x0)

0x16010x1602[7:0] ReservedX[7:0] R_TX_LANE_SEL0

8
8

R/W
R/W

8'h1B
8'hE4

must be left as default 0x1B
MIPI Tx Lane assignment select (*each bit setting)[7:6] MTX3P/N (MTX3) (*)[5:4] MTX2P/N (MTX2) (*)[3:2] MTX1P/N (MTX1) (*)[1:0] MTX0P/N (MTX0) (*)
0x0: 1st Byte output
0x1: 2nd Byte output
0x2: 3rd Byte output (or 1st Byte on 2PORT mode)
0x3: 4th Byte output (or 2nd Byte on 2PORT mode)* use case setting example
1PORT1LANE: 0xE4 (Port0:MTX0)
1PORT2LANE: 0xE4 (Port0:MTX0, MTX1)
1PORT4LANE: 0xE4 (Port0:MTX0, MTX1, MTX2, MTX3)
2PORT1LANE: 0x72 (Port0:MTX1, Port1:MTX0)0x63 (Port0:MTX1, Port1:MTX2)
0x36 (Port0:MTX3, Port1:MTX0)
2PORT2LANE: 0x72 (Port0:MTX3,MTX1, Port1:MTX0,MTX2)

0x1603[7:2] Reserved[1:0] R_TX_LANE_SEL1

6
2

R/W

6'h00
2'h0

<this register is valid when 0x1605[2:0]=0x4 or 0x5>
MIPI Tx Lane assignment select for Port1 on 2PORT mode
* use case setting example
2PORT1LANE: 0x0 (Port1:MTX0)
2PORT1LANE: 0x2 (Port1:MTX2)
2PORT2LANE: 0x0 (Port1:MTX0,MTX2)

0x1604[7:0] ReservedX

Copyright©2023 THine Electronics, Inc.

8

R/W

8'h3F

must be left as default 0x3F

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THCV244A-QP_ Rev.4.31_E

Table 25. MIPI output setting (2/3)
Address
0x1605bit Register Name
[7] Reserved[6:0] R_LANE_EN

width
1
7

R/W
R/W

Init
1'h0
7'h2B

Description[6:5] MIPI Data lane Enable (*each bit setting)[6] Data Port1 (*)[5] Data Port0 (*)
0x0: OFF0x1: ON[4:3] MIPI CLK lane Enable (*each bit setting)[4] CLK Port1 (*)[3] CLK Port0 (*)
0x0: OFF0x1: ON[2:0] MIPI Configuration
0x0 (=0b000): 1PORT1LANE
0x1 (=0b001): 1PORT2LANE
0x3 (=0b011): 1PORT4LANE
0x4 (=0b100): 2PORT1LANE
0x5 (=0b101): 2PORT2LANE
Other:Reserved* use case setting example
1PORT1LANE: 0x28 (=0b0101_000)
1PORT2LANE: 0x29 (=0b0101_001)
1PORT4LANE: 0x2B (=0b0101_011)
2PORT1LANE: 0x7C (=0b1111_100)
2PORT2LANE: 0x7D (=0b1111_101)

0x1606[7:2] ReservedX

6

R/W

6'h10

must be set 0x13

[1:0] R_MODE_SET

2

R/W

2'h0

0x16070x1608[7:0] ReservedX[7:4] Reserved[3:0] ReservedX

8
4
4

R/W
R/W

8'hE4
4'h0
4'hE

clock continous mode select (*each bit setting)[1] clock continous mode select for Port1 (*)[0] clock continous mode select for Port0 (*)
0x0:OFF (HS clock off and become LP mode during V-Blanking term)
0x1:ON (HS clock permanently on)(*) When 0x1013[0] = 0x0, 0x1606[1:0] must be set 0x3.
must be left 0xE4 (default setting)must be left 0xE (default setting)

0x161f[7:4] Reserved[3:0] R_REQ_SEL

4
4

R/W

4'h0
4'h0

MIPI Tx Lane Port assignment (*each bit setting)[3] MTX3P/N (MTX3) (*)[2] MTX2P/N (MTX2) (*)[1] MTX1P/N (MTX1) (*)[0] MTX0P/N (MTX0) (*)
0: Port0
1: Port1* use case setting example
1PORT mode: 0x0 (=0b0000)
2PORT mode: 0x5 (=0b0101) (Port0:MTX3,MTX1, Port1:MTX0,MTX2)

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THCV244A-QP_ Rev.4.31_E

Table 26. MIPI output setting (3/3)
Address
0x1609bit Register Name
[7:0] R_TX_CLK_PREPARE0

width
8

R/W
R/W

Init
8'h04

Description
CLK lane Prepare period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_PREPARE0"0x160a[7:0] R_TX_CLK_ZERO0

8

R/W

8'h1D

CLK lane ZERO period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_ZERO0"

0x160b[7:0] R_TX_CLK_TRAIL0

8

R/W

8'h07

CLK lane TRAIL period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_TRAIL0"0x160c[7:0] reservedX

8

R/W

8'h02

must be left 0x2 (default setting)

0x160d[7:0] R_TX_CLK_POST0

8

R/W

8'h0C

CLK lane POST period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_POST0"0x160e[7:0] R_TX_THS_EXIT0

8

R/W

8'h0B

CLK and Data lane EXIT period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_EXIT0"0x160f[7:0] R_TX_TLPX0

8

R/W

8'h05

CLK and Data lane TLPX period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_TLPX0"0x1610[7:0] R_TX_THS_PREPARE0

8

R/W

8'h04

Data lane Prepare period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_PREPARE0"0x1611[7:0] R_TX_THS_ZERO0

8

R/W

8'h10

Data lane ZERO period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_ZERO0"0x1612[7:0] R_TX_THS_TRAIL0

8

R/W

8'h07

Data lane TRAIL period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_TRAIL0"0x1613[7:0] reservedX

8

R/W

8'h40

must be left 0x40 (default setting)

0x1614[7:0] R_TX_CLK_PREPARE1

8

R/W

8'h04

CLK lane Prepare period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_PREPARE1"

0x1615[7:0] R_TX_CLK_ZERO1

8

R/W

8'h1D

CLK lane ZERO period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_ZERO1"

0x1616[7:0] R_TX_CLK_TRAIL1

8

R/W

8'h07

CLK lane TRAIL period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_TRAIL1"

0x1617[7:0] reservedX

8

R/W

8'h02

must be left 0x2 (default setting)

0x1618[7:0] R_TX_CLK_POST1

8

R/W

8'h0C

CLK lane POST period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_POST1"

0x1619[7:0] R_TX_THS_EXIT1

8

R/W

8'h0B

CLK and Data lane EXIT period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_EXIT1"

0x161a[7:0] R_TX_TLPX1

8

R/W

8'h05

CLK and Data lane TLPX period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_TLPX1"

0x161b[7:0] R_TX_THS_PREPARE1

8

R/W

8'h04

Data lane Prepare period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_PREPARE1"

0x161c[7:0] R_TX_THS_ZERO1

8

R/W

8'h10

Data lane ZERO period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_ZERO1"

0x161d[7:0] R_TX_THS_TRAIL1

8

R/W

8'h07

Data lane TRAIL period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_TRAIL1"

0x161e[7:0] reservedX

8

R/W

8'h40

must be left 0x40 (default setting)

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THCV244A-QP_ Rev.4.31_E

MTX0P/N and MTX2P/N can be assigned to be MIPI 2nd port (port1).
MTXCLK1P/N and MIPI 2nd port available maximum speed is 1.2Gbps.
The frequency of MIPI 2nd port clock lane is the same as that of MIPI 1st port clock lane.

THCV244A
-QP

28

MTX3P

27

MTX3N

26

MTX1P

25

MTX1N

24 MTXCLK0P
23 MTXCLK0N
22

MTX0P

MIPI Tx

21

MTX0N

available

20

MTX2P

2nd port1

19

MTX2N

data pins

18 MTXCLK1P

2nd port1 clock

17 MTXCLK1N

2nd port1 clock

Figure 6. MIPI 2nd port available pins

Setting of MIPI 2port output examples are shown below.

Table 27. MIPI 2port output setting example
R_TX_LANE_SEL0
lane3 lane2 lane1 lane0
[7:6]
[5:4]
[3:2]
[1:0]
01
11
00
10
01
10
00
11
00
11
01
10
01
11
00
10
01
10
00
11
00
11
01
10

R_TX_LANE_SEL1
R_LANE_EN
port1 selectport enable clk enable
[1:0]
[6:5]
[4:3]
00
11
11
10
11
11
00
11
11
00
11
11
10
11
11
00
11
11
other settings

Copyright©2023 THine Electronics, Inc.

config
[2:0]
101
101
101
100
100
100

lane3
[3]
0
0
0
0
0
0

R_REQ_SEL
lane2 lane1
[2]
[1]
1
0
1
0
1
0
1
0
1
0
1
0

lane0
lane3
[0]
MTX3P/N
port0 2nd Byte11
port0 2nd Byte1
port0 1st Byte
1
No output
1
No output
port0 1st Byte
1

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MIPI Physical pin order output assignment
lane1
lane0
lane2
MTX1P/NMTXCLK0P/N
MTX0P/NMTX2P/N
port0 1st Byte
port0 clock
port1 1st Byte port1 2nd Byte
port0 1st Byte
port0 clock
port1 2nd Byte port1 1st Byte
port0 2nd Byte
port0 clock
port1 1st Byte port1 2nd Byte
port0 1st Byte
port0 clock
port1 1st Byte
No output
port0 1st Byte
port0 clock
No output
port1 1st Byte
No output
port0 clock
port1 1st Byte
No output
forbidden

MTXCLK1P/N
port1 clock
port1 clock
port1 clock
port1 clock
port1 clock
port1 clock

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THCV244A-QP_ Rev.4.31_E
6.10. 2-wire serial interface
2-wire serial I/F slave Device ID
To use GPIO (General Purpose Input/Output), fault/error detection, and interrupt function, 2-wire serial I/F
enables to access registers. AIN<1:0> pin determines 2-wire slave Device ID setting.

Table 28. 2-wire serial I/F Device ID select by AIN pin
Pin Name
AIN1

AIN0

Description
Device Address Setting for 2-wire Serial Interface[AIN1:AIN0]=00: ID=7'h0B[AIN1:AIN0]=01: ID=7'h34[AIN1:AIN0]=10: ID=7'h77[AIN1:AIN0]=11: ID=7'h65

As an additional method, 2-wire slave Device ID setting can be changed from default value by register setting.

Table 29. 2-wire serial I/F Device ID select by register setting
Address
0x0030bit Register Name
[7:0] R_2WIRE_SADR

width
8

R/W
RW

Init
8'h00

Description
2-wire slave device address setting[7] 2-wire slave device address control
0x0: 2-wire slave device addr. is set by AIN1 and AIN0 pin
0x1: 2-wire slave device addr. is set by following register [6:0]<this regiseter is valid when 0x0030[1:0]=0x1>[6:0] 2-wire slave device address value for register control

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THCV244A-QP_ Rev.4.31_E
2-wire serial Read/Write access to local Register
HOST MPU can directly access THCV244A-QP local register by 2-wire serial I/F.

THCV244A-QP
Sub-Link Block
Sub-Link
Master2-wire
Slave

SCL
SDA

Host
MPU

Register

AIN<1:0> = User SelectFigure 7.

Host to THCV244A-QP local register access configuration

Figure 8.

2-wire serial I/F write to THCV244A-QP local register protocol

Figure 9.

2-wire serial I/F read to THCV244A-QP local register protocol

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THCV244A-QP_ Rev.4.31_E
6.11. 2-wire serial I/F Watch Dog Timer
2-wire Watch Dog Timer (WDT) is installed to monitor status.

Table 30. 2-wire WDT setting
Address
0x003B

0x003Cbit Register Name
[7:5] reserved[4] R_2WIRE_WD_EN

width
3
1

R/W
RW

Init
1'h1

[3:1] reserved[0] R_2WIRE_WD_OFFSET

3
1

RW

1'h1

[7:0] R_2WIRE_WD_TIM

8

RW

8'hFF

Description
2-wire I/F Watch Dog Timer (WDT) Enable
0x0: Disable
0x1: Enable<this register is valid only when 0x003B[4]=0x1>
2-wire I/F WDT Offset Time
0x1: 0x7FF (=d2047)
0x0: 0x3FF (=d1023)<this register is valid only when 0x003B[4]=0x1>
2-wire I/F WDT time
=64×{R_2WIRE_WD_TIM<7:0>+1}×{2WIRE_WDT_OffsetTime}×tOSC

6.12. Register Auto Checksum diagnosis
Register values checksum is continuously calculated as R_CKSUM_RVAL.

Table 31. Register Auto Checksum diagnosis control and monitoring
Address
0x0008bit Register Name
[7:1] reserved[0] R_CKSUM_EN

width
7
1

R/W
RW

Init
1'h0

0x0009[7:0] R_CKSUM_TIM

8

RW

8'h13

0x000A[7:0] R_CKSUM_VAL

8

RW

8'h00

0x000B[7:0] R_CKSUM_RVAL

8

R

-

Copyright©2023 THine Electronics, Inc.

Description
Internal Register AutoCheckSum Enable
0x0: Disable
0x1: Enable<this regiseters is valid only when 0x0008[0]=0x1>
Internal Register AutoCheckSum check interval=1024×64×(R_CKSUM_TIM<7:0>+1) × tOSC
<this regiseters is valid only when 0x0008[0]=0x1>
Internal Register AutoCheckSum expected target value<this regiseters is valid only when 0x0008[0]=0x1>
Internal Register AutoCheckSum read value

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THCV244A-QP_ Rev.4.31_E
6.13. Sub-Link setting
THCV244A-QP is Sub-Link Master and connectable to Sub-Link Slave device such as THCV241A-Q.
Sub-Link Polling interval is controllable from about 20us to 800us, that may have relationships on fault/error
detection, interrupt, or other GPIO transfer time designed on application. SSR (Sub-Link Status Read) interval
determines recovery quickness from 2-wire serial remote communication completion.

Table 32. Sub-Link Master protocol basic setting
0x0004[7:3] reserved[2:0] R_SLINK_MODE

5
3

RW

3'h1

0x0010[7:4] R_SLINK_EN

4

RW

4'h0

[3:0] R_SLINK_POL_EN

4

RW

4'hF

0x0011[7:4] reservedX[3:0] R_SLINK_WD_EN

4
4

RW
RW

4'hF
4'hF

0x001A[7:5] reserved[4] R_SLINK_POL_OFSET_EN

3
1

RW

1'h0

[3:2] reserved[1:0] R_SLINK_POL_TIM_UP

2
2

RW

2'h0

0x001B[7:0] R_SLINK_POL_TIM_DN

8

RW

8'h7C

0x001C[7:2] reserved[1:0] R_SLINK_SSR_TIM_UP[7:0] R_SLINK_SSR_TIM_DN

6
2
8

RW
RW

2'h0
8'hF9

0x001D

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Sub-Link basic protocol setting as Sub-Link Master0x1: 2-wire Set & Trigger mode1
0x3: 2-wire Pass Through mode1
Other: Reserved
Sub-Link Enable (*each bit setting)[7] Sub-Link Enable for Lane3 (*)[6] Sub-Link Enable for Lane2 (*)[5] Sub-Link Enable for Lane1 (*)[4] Sub-Link Enable for Lane0 (*)
0x0: Sub-Link Disable
0x1: Sub-Link Enable
Sub-Link Polling Enable (*each bit setting)[3] Sub-Link Polling Enable for Lane3 (*)[2] Sub-Link Polling Enable for Lane2 (*)[1] Sub-Link Polling Enable for Lane1 (*)[0] Sub-Link Polling Enable for Lane0 (*)
0x0: Polling Disable
0x1: Polling Enablemust be left 0xF (default setting)
Sub-Link Watch Dog Timer (WDT) Enable (*each bit setting)[3] Sub-Link WDT Enable for Lane3 (*)[2] Sub-Link WDT Enable for Lane2 (*)[1] Sub-Link WDT Enable for Lane1 (*)[0] Sub-Link WDT Enable for Lane0 (*)
0x0: WDT Disable
0x1: WDT Enable<this regiseter is valid when 0x0010[n ]=0x1, n =0,1,2,3>
Enable of shifting the Sub-Link Polling output timing
0x0: Disable
0x1: Enable
The Polling output timing of Sub-Link
Lane1 is delayed by Sub-Link Polling interval x 1/4 from the Sub-Link Lane0.
Lane2 is delayed by Sub-Link Polling interval x 2/4 from the Sub-Link Lane0.
Lane3 is delayed by Sub-Link Polling interval x 3/4 from the Sub-Link Lane0.
<this regiseter is valid when 0x0010[n ]=0x1, n =0,1,2,3>
Sub-Link Polling interval setting (min. 0x018, about 20us)<this regiseter is valid when 0x0010[n ]=0x1, n =0,1,2,3>
Sub-Link Polling interval time=64×(256×R_SLINK_POL_TIM_UP<1:0>+R_SLINK_POL_TIM_DN<7:0>+1)×tOSC*No Polling when R_SLINK_POL_TIM_UP=0x0 and R_SLINK_POL_TIM_DN=0x0
Sub-Link SSR interval setting
Sub-Link SSR interval time=64×(256×R_SLINK_SSR_TIM_UP<1:0>+R_SLINK_SSR_TIM_DN<7:0>+1)×tOSC*No SSR when R_SLINK_SSR_TIM_UP=0x0 and R_SLINK_SSR_TIM_DN=0x0

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THCV244A-QP_ Rev.4.31_E

To use GPIO (General Purpose Input/Output) pin, fault/error detection and interrupt function, “2-wire
Set&Trigger mode1” and “2-wire Pass Through mode1” enables remote register access. THCV244A-QP, SubLink Master device has 2-wire serial slave block and can connect to HOST MPU. On the other hand, thecounterpart Sub-Link Slave device has 2-wire serial master block and can connect to remote side 2-wire serial
slave devices.
HOST MPU can access register of Sub-Link Master device, Sub-Link Slave device and remote side 2-wire serial
slave devices.

Sub-Link 2-wire Set and Trigger mode (2-wire Normal mode)
HOST MPU can access to Sub-Link Slave’s register via THCV244A-QP as Sub-Link Master only by
THCV244A-QP internal local register control and monitoring on 2-wire Set&Trigger mode1.

Sub-Link Slave Device

THCV244A-QP as Sub-Link Master

Sub-Link Block

Sub-Link Block
Sub-Link
line

2-wireMaster

Sub-Link
Slave

Sub-Link
MasterSCL

2-wire
Slave

Host
MPU

SDA
INT

Register

RegisterInterrupt signal(MSSEL=1)

Triggered access by Sub-Link Master
Access from/to HOST

Figure 10.

Host MPU to Sub-Link Slave Register via THCV244A-QP access configuration

AIN<1:0> = User Select

HOST MPU can access to remote side 2-wire serial slave register via THCV244A-QP as Sub-Link Master only
by THCV244A-QP internal local register control and monitoring on 2-wire Set&Trigger mode1.

Sub-Link Slave Device

THCV244A-QP as Sub-Link Master

Sub-Link Block2-wireSlave
Device#a

SCL
SDA

2-wireMaster

Sub-Link Block
Sub-Link
Slave

Sub-Link
line

Sub-Link
MasterSCL

2-wire
Slave

SDA
INT

・
・

Register2-wireSlave
Device#b(MSSEL=1)

Figure 11.

Register

Triggered access by Sub-Link Master
Access from/to HOST

Host
MPU

Interrupt signal

AIN<1:0> = User SelectHost MPU to remote 2-wire slave devices via THCV244A-QP access configuration

Copyright©2023 THine Electronics, Inc.

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In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial accessand Sub-Link Slave internal bus access or remote side 2-wire serial access.
R_2WIRE_CLKSEN (Sub-Link Master side register, 0x00E2 bit0) selects whether 2-wire serial slave of SubLink Master perform clock stretching.
When R_2WIRE_CLKSEN = 1, Sub-Link Master device waits HOST MPU until Sub-Link Slave register accessor remote side 2-wire serial slave register access complete by clock stretching.
When R_2WIRE_CLKSEN = 0, Sub-Link Master device informs HOST MPU that Sub-Link Slave register
access or remote side 2-wire serial register access has completed by interruption (detectable on INT pin) without
clock stretching.

Figure 12.

Copyright©2023 THine Electronics, Inc.

Sub-Link Master 2-wire slave clock stretching operation

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Table 33. 2-wire serial I/F Set& Trigger mode remote access control and monitoring local registers (1/2)
Address
0x00D0bit Register Name
[7:0] R_2WIRE_DATA0

width
8

R/W
RW

Init
8'h00

0x00D1[7:0] R_2WIRE_DATA1

8

RW

8'h00

0x00D2[7:0] R_2WIRE_DATA2

8

RW

8'h00

0x00D3[7:0] R_2WIRE_DATA3

8

RW

8'h00

0x00D4[7:0] R_2WIRE_DATA4

8

RW

8'h00

0x00D5[7:0] R_2WIRE_DATA5

8

RW

8'h00

0x00D6[7:0] R_2WIRE_DATA6

8

RW

8'h00

0x00D7[7:0] R_2WIRE_DATA7

8

RW

8'h00

0x00D8[7:0] R_2WIRE_DATA8

8

RW

8'h00

0x00D9[7:0] R_2WIRE_DATA9

8

RW

8'h00

0x00DA[7:0] R_2WIRE_DATA10

8

RW

8'h00

0x00DB[7:0] R_2WIRE_DATA11

8

RW

8'h00

0x00DC[7:0] R_2WIRE_DATA12

8

RW

8'h00

0x00DD[7:0] R_2WIRE_DATA13

8

RW

8'h00

0x00DE[7:0] R_2WIRE_DATA14

8

RW

8'h00

0x00DF[7:0] R_2WIRE_DATA15

8

RW

8'h00

0x00E0[7:1] R_2WIRE_DEVADR

7

RW

7'h00

[0]

1

RW

1'h0

[7] reserved[6:4] R_2WIRE_WADR_BYTE

1
3

RW

3'h0

[3:0] R_2WIRE_DATA_BYTE

4

RW

4'h0

0x00E1

R_2WIRE_WR

Copyright©2023 THine Electronics, Inc.

Description<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #0<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #1<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #2<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #3<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #4<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #5<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #6<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #7<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #8<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #9<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #10<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #11<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #12<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #13<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #14<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #15<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote access target device address.
if target addr. = self addr.; access to Sub-Link slave internal registers,
else; access to remote side 2-wire serial slave devices externally connected to
Sub-Link slave<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote access write or read select0x0: Write
0x1: Read<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote device's sub address (Word Address, register address)
Byte width. Sub Address Byte width = R_2WIRE_WADR_BYTE<2:0>+1
0x0: 1Byte (= 8bit) sub address
0x1: 2Byte (=16bit) sub address
Other : Reserved<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote access data Byte number.
Byte Number = R_2WIRE_DATA_BYTE + 1 (e.g. 0x2 for 3Byte burst)[Write rule] R_2WIRE_WADR_BYTE+R_2WIRE_DATA_BYTE < 'd16
[Read rule] R_2WIRE_DATA_BYTE < 'd16

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Table 34. 2-wire serial I/F Set& Trigger mode remote access control and monitoring local registers (2/2)
Address
0x00E2

bit Register Name
[7:1] reserved[0] R_2WIRE_CLKSEN

width
7
1

R/W
RW

Init
1'h0

0x00E3[7:2] reserved[1:0] R_2WIRE_RD_LANE_SEL

6
2

RW

2'h0

0x00E4[7:4] reserved[3:0] R_2WIRE_WR_LANE_SEL

4
4

RW

4'hF

0x00E5[7:1] reserved[0] R_2WIRE_START

7
1

W

-

Copyright©2023 THine Electronics, Inc.

Description<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F local response clock stretching Enable
0x0: Sub-Link Master (2-wire slave) No clock stretching
0x1: Sub-Link Master (2-wire slave) clock stretching Enable*2-wire Pass Through mode (R_SLINK_MODE=0x3) forces clock stretching
Enable<this regiseter is valid when 0x0004[2:0]=0x1 or 0x3>
Sub-Link read transaction lane select0x0: Read from Sub-Link Lane00x1: Read from Sub-Link Lane1
0x2: Read from Sub-Link Lane2
0x3: Read from Sub-Link Lane3<this regiseter is valid only when 0x0004[2:0]=0x1>
Sub-Link Write transaction lane select (multiple lanes can be written at the sametime) (*each bit setting)[3] Write for Sub-Link Lane3 (*)[2] Write for Sub-Link Lane2 (*)[1] Write for Sub-Link Lane1 (*)[0] Write for Sub-Link Lane0 (*)
0x0: Disable
0x1: Enable<this regiseter is valid only when 0x0004[2:0]=0x1>
0x1: 2-wire serial I/F remote access start trigger

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THCV244A-QP_ Rev.4.31_E
Sub-Link 2-wire Pass Through mode
Sub-Link Master 2-wire Pass Through mode1 can bridge original local 2-wire commands to remote side.
2-wire Pass Through mode1 uses 2-wire slave clock stretching scheme at local Sub-Link Master side. Host
MCU 2-wire master must be no problem with clock stretching wait from 2-wire slave.

Sub-Link Slave side processing protocol “Divided write/read” scheme divides 2-wire commands into
determined data Byte groups. Each data Byte groups are sent separately on remote side. Burst write/read accesstarget Sub-Address (Word-Address) is interpreted so that subsequent Sub-Address (Word-Address) from 2nd
group is automatically and properly incremented. As shown below, remote side 2-wire accesses are independent
each other by determined Byte, which are defined in R_2WIREPT_WA_BYTE and
R_2WIREPT_DATA_BYTE at R_2WIREPT1_PASS_MODE[1]=1.

Divided w rite acces s at R_2WIREPT1_PASS_MODE[1]=1 (case: 1Byte Word Address and 16Byte burst 2-w ire w rite w ith R_2WIREPT_WA_BYTE=3'd1 and R_2WIREPT_DATA_BYTE=4'd8)

SP

ACK

…

WD15

Figure 13.

ACK+W: Write command indicator

WD9

WD： Write Data

AD： Word Address

ACK

SID： Slave Address （ Device Address)

ACK： Acknow ledge

WD8

SP： Stop Condition

ST： Start Condition

ACK[ list of abbreviations ]

AD' *

ST

Bus Free

SID+W

SP

ACK

…

WD7

ACK

WD1

WD0

AD

ACK

ACK

ST

Bus FreeRemote 2-w ire line

SID+W

Sub-Link Slave side

Bus Free2-wire Pass Through mode1 Sub-Link Slave command Divided scheme

On address processing protocol “Assigned address & rename”, THCV244A-QP 2-wire slave respond only to 2wire device address defined in R_2WIREPT1_PASS_ADRxy1 (x=Lane0/1/2/3, y=0/1/2/3) for remote Pass
Through operation. Otherwise, 2-wire commands are ignored except THCV244A-QP itself address. The device
address can be renamed before remote send. The counterpart Sub-Link Slave internal register access is available
with R_2WIREPT1_PASS_ADRINx (x=Lane0/1/2/3) setting.
On address processing protocol “All Through”, THCV244A-QP 2-wire slave respond basically all 2-wire device
address for remote Pass Through operation except THCV244A-QP itself address. Additionally, Defined addresses
in R_2WIREPT2_NOPASS_ADRxz (x=Lane0/1/2/3, z=0/1/2/3/4/5/6/7) can be ignored by THCV244A-QP.

Copyright©2023 THine Electronics, Inc.

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THCV244A-QP_ Rev.4.31_E

Table 35. 2-wire serial I/F Pass Through mode remote access common setting
Address
0x0031

bit Register Name
[7:2] reserved[1:0] R_2WIREPT_MODE

width
6
2

R/W
RW

Init
2'h0

Description<this regiseter is valid only when 0x0004[2:0]=0x3>
Sub-Link 2WIRE Pass Through mode setting[1]Pass Through processing protocol on Sub-Link Slave
0x0: Reserved
0x1: Divided Write & Divided Read
Transaction address and data Byte number are set as R_2WIREPT_WA_BYTE
and R_2WIREPT_DATA_BYTE.
[0]Pass Through 2WIRE device addrress processing
0x0: Address rename(rule as R_2WIREPT1_PASS_ADRxy0/1. x is Lane0 or Lane1, y=<3:0>)
0x1: All Through(exception definition of address to ignore as R_2WIREPT2_NOPASS_ADRxz.
x is Lane0 or Lane1, z=<7:0>)

0x0032[7] reserved[6:4] R_2WIREPT_WA_BYTE

1
3

RW

3'h0

[3:0] R_2WIREPT_DATA_BYTE

4

RW

4'h0

Copyright©2023 THine Electronics, Inc.

<this register is valid only when 0x0031[1]=0x1>
Sub-Link 2WIRE Pass Through Divided Write/Read Sub Address (WordAddress) Byte number setting
Byte Number = R_2WIREPT_WA_BYTE + 1
0x0: 1Byte (= 8bit) sub address
0x1: 2Byte (=16bit) sub address
Other: Reserved
Sub-Link 2WIRE Pass Through Divided Write/Read data Byte number per atransaction setting, Byte Number = R_2WIREPT_DATA_BYTE + 1(e.g. 0x2 for 3Byte per a transaction)*R_2WIREPT_WA_BYTE + R_2WIREPT_DATA_BYTE < d14 is required.

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Table 36. 2-wire serial I/F Pass Through mode remote access common setting (Lane0)
Address
0x0040bit Register Name
[7:0] R_2WIREPT1_PASS_ADR000

width
8

R/W
RW

Init
8'h00

0x0041[7:0] R_2WIREPT1_PASS_ADR001

8

RW

8'h00

0x0042[7:0] R_2WIREPT1_PASS_ADR010

8

RW

8'h00

0x0043[7:0] R_2WIREPT1_PASS_ADR011

8

RW

8'h00

0x0044[7:0] R_2WIREPT1_PASS_ADR020

8

RW

8'h00

0x0045[7:0] R_2WIREPT1_PASS_ADR021

8

RW

8'h00

0x0046[7:0] R_2WIREPT1_PASS_ADR030

8

RW

8'h00

0x0047[7:0] R_2WIREPT1_PASS_ADR031

8

RW

8'h00

0x0048[7:0] R_2WIREPT2_NOPASS_ADR00

8

RW

8'h00

0x0049[7:0] R_2WIREPT2_NOPASS_ADR01

8

RW

8'h00

0x004A[7:0] R_2WIREPT2_NOPASS_ADR02

8

RW

8'h00

0x004B[7:0] R_2WIREPT2_NOPASS_ADR03

8

RW

8'h00

0x004C[7:0] R_2WIREPT2_NOPASS_ADR04

8

RW

8'h00

0x004D[7:0] R_2WIREPT2_NOPASS_ADR05

8

RW

8'h00

0x004E[7:0] R_2WIREPT2_NOPASS_ADR06

8

RW

8'h00

0x004F[7:0] R_2WIREPT2_NOPASS_ADR07

8

RW

8'h00

0x0050[7:0] R_2WIREPT1_PASS_ADRIN0

8

RW

8'h00

Copyright©2023 THine Electronics, Inc.

Description<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane0 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane0 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane0 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane0 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane0 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane0 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane0 #3<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane0 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #0<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #1<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #2<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #4<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #5<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #6<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #7<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through counterpart Sub-Link Slave internal register accessdedicated address for Lane0

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Table 37. 2-wire serial I/F Pass Through mode remote access common setting (Lane1)
Address
0x0060bit Register Name
[7:0] R_2WIREPT1_PASS_ADR100

width
8

R/W
RW

Init
8'h00

0x0061[7:0] R_2WIREPT1_PASS_ADR101

8

RW

8'h00

0x0062[7:0] R_2WIREPT1_PASS_ADR110

8

RW

8'h00

0x0063[7:0] R_2WIREPT1_PASS_ADR111

8

RW

8'h00

0x0064[7:0] R_2WIREPT1_PASS_ADR120

8

RW

8'h00

0x0065[7:0] R_2WIREPT1_PASS_ADR121

8

RW

8'h00

0x0066[7:0] R_2WIREPT1_PASS_ADR130

8

RW

8'h00

0x0067[7:0] R_2WIREPT1_PASS_ADR131

8

RW

8'h00

0x0068[7:0] R_2WIREPT2_NOPASS_ADR10

8

RW

8'h00

0x0069[7:0] R_2WIREPT2_NOPASS_ADR11

8

RW

8'h00

0x006A[7:0] R_2WIREPT2_NOPASS_ADR12

8

RW

8'h00

0x006B[7:0] R_2WIREPT2_NOPASS_ADR13

8

RW

8'h00

0x006C[7:0] R_2WIREPT2_NOPASS_ADR14

8

RW

8'h00

0x006D[7:0] R_2WIREPT2_NOPASS_ADR15

8

RW

8'h00

0x006E[7:0] R_2WIREPT2_NOPASS_ADR16

8

RW

8'h00

0x006F[7:0] R_2WIREPT2_NOPASS_ADR17

8

RW

8'h00

0x0070[7:0] R_2WIREPT1_PASS_ADRIN1

8

RW

8'h00

Copyright©2023 THine Electronics, Inc.

Description<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane1 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane1 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane1 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane1 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane1 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane1 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane1 #3<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane1 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #0<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #1<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #2<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #4<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #5<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #6<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #7<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through counterpart Sub-Link Slave internal register accessdedicated address for Lane1

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Table 38. 2-wire serial I/F Pass Through mode remote access common setting (Lane2)
Address
0x0080bit Register Name
[7:0] R_2WIREPT1_PASS_ADR200

width
8

R/W
RW

Init
8'h00

0x0081[7:0] R_2WIREPT1_PASS_ADR201

8

RW

8'h00

0x0082[7:0] R_2WIREPT1_PASS_ADR210

8

RW

8'h00

0x0083[7:0] R_2WIREPT1_PASS_ADR211

8

RW

8'h00

0x0084[7:0] R_2WIREPT1_PASS_ADR220

8

RW

8'h00

0x0085[7:0] R_2WIREPT1_PASS_ADR221

8

RW

8'h00

0x0086[7:0] R_2WIREPT1_PASS_ADR230

8

RW

8'h00

0x0087[7:0] R_2WIREPT1_PASS_ADR231

8

RW

8'h00

0x0088[7:0] R_2WIREPT2_NOPASS_ADR20

8

RW

8'h00

0x0089[7:0] R_2WIREPT2_NOPASS_ADR21

8

RW

8'h00

0x008A[7:0] R_2WIREPT2_NOPASS_ADR22

8

RW

8'h00

0x008B[7:0] R_2WIREPT2_NOPASS_ADR23

8

RW

8'h00

0x008C[7:0] R_2WIREPT2_NOPASS_ADR24

8

RW

8'h00

0x008D[7:0] R_2WIREPT2_NOPASS_ADR25

8

RW

8'h00

0x008E[7:0] R_2WIREPT2_NOPASS_ADR26

8

RW

8'h00

0x008F[7:0] R_2WIREPT2_NOPASS_ADR27

8

RW

8'h00

0x0090[7:0] R_2WIREPT1_PASS_ADRIN2

8

RW

8'h00

Copyright©2023 THine Electronics, Inc.

Description<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane2 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane2 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane2 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane2 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane2 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane2 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane2 #3<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane2 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane2 #0<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane2 #1<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane2 #2<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane2 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane2 #4<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane2 #5<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane2 #6<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane2 #7<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through counterpart Sub-Link Slave internal register accessdedicated address for Lane2

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Table 39. 2-wire serial I/F Pass Through mode remote access common setting (Lane3)
Address
0x00A0bit Register Name
[7:0] R_2WIREPT1_PASS_ADR300

width
8

R/W
RW

Init
8'h00

0x00A1[7:0] R_2WIREPT1_PASS_ADR301

8

RW

8'h00

0x00A2[7:0] R_2WIREPT1_PASS_ADR310

8

RW

8'h00

0x00A3[7:0] R_2WIREPT1_PASS_ADR311

8

RW

8'h00

0x00A4[7:0] R_2WIREPT1_PASS_ADR320

8

RW

8'h00

0x00A5[7:0] R_2WIREPT1_PASS_ADR321

8

RW

8'h00

0x00A6[7:0] R_2WIREPT1_PASS_ADR330

8

RW

8'h00

0x00A7[7:0] R_2WIREPT1_PASS_ADR331

8

RW

8'h00

0x00A8[7:0] R_2WIREPT2_NOPASS_ADR30

8

RW

8'h00

0x00A9[7:0] R_2WIREPT2_NOPASS_ADR31

8

RW

8'h00

0x00AA[7:0] R_2WIREPT2_NOPASS_ADR32

8

RW

8'h00

0x00AB[7:0] R_2WIREPT2_NOPASS_ADR33

8

RW

8'h00

0x00AC[7:0] R_2WIREPT2_NOPASS_ADR34

8

RW

8'h00

0x00AD[7:0] R_2WIREPT2_NOPASS_ADR35

8

RW

8'h00

0x00AE[7:0] R_2WIREPT2_NOPASS_ADR36

8

RW

8'h00

0x00AF[7:0] R_2WIREPT2_NOPASS_ADR37

8

RW

8'h00

0x00B0[7:0] R_2WIREPT1_PASS_ADRIN3

8

RW

8'h00

Copyright©2023 THine Electronics, Inc.

Description<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane3 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane3 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane3 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane3 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane3 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane3 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane3 #3<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane3 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane3 #0<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane3 #1<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane3 #2<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane3 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane3 #4<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane3 #5<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane3 #6<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane3 #7<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through counterpart Sub-Link Slave internal register accessdedicated address for Lane3

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THCV244A-QP_ Rev.4.31_E
Sub-Link transaction time accuracy Improvement
Sub-Link Polling timing can be controllable by GPI input. All Sub-Link lane transaction timing can bearranged.

Table 40. Sub-Link transaction time accuracy control
Address
0x0016

bit Register Name
[7:6] reserved[5:4] R_POL_TIM_CLR_EN

width
2
2

R/W
RW

Init
2'h0

1
3

RW

3'h0

[3] reserved[2:0] R_GPI_TRG_SEL

Description<this regiseter is valid when 0x0010[n ]=0x1, n =0,1,2,3>
Polling Timer Clear/Mask setting
0x1: The polling timer is cleared when the inputted GPIO changes
0x2: The polling timer masked when inputted GPIO signal is high, and the pollingtransmission is outputted after inputted GPIO signal is falling.
<this regiseter is valid when 0x0010[n ]=0x1, n =0,1,2,3>
Polling Timer Clear/Mask GPIO signal select0x0: GPIO0 (this setting is valid only when 0x1004[3:0]=0x3)
0x1: GPIO1 (this setting is valid only when 0x1004[7:4]=0x3)
Other: Reserved

Polling Timer Clear
Trigger GPI

Polling IntervalOne
polingCleared new
Polling Interval

Polling Interval

Sub-Link Master
Polling transaction
to all Sub-Link lanes
Ignored previous
Polling Interval

Polling Timer Mask
Trigger GPI

Polling IntervalOne
polingCleared new
Polling Interval

Polling Interval

Sub-Link Master
Polling transaction
to all Sub-Link lanes
Ignored previous
Polling Interval

Ignored previous
Polling Interval

Figure 14. Sub-Link transaction time accuracy control

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THCV244A-QP_ Rev.4.31_E
6.14. GPIO setting
Setting of GPIO can be configurable by 2-wire access to internal register.

Table 41. GPIO setting (1/2)
Address
0x10010x1002

bit Register Name
[7:4] R_GPIO7_MODE

width
4

R/W
R/W

init
4'h0

[3:0] R_GPIO6_MODE

4

R/W

4'h0

[7:4] R_GPIO5_MODE

4

R/W

4'h0

[3:0] R_GPIO4_MODE

4

R/W

4'h0

Copyright©2023 THine Electronics, Inc.

Description
GPIO7 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO6 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO5 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO4 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved

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THCV244A-QP_ Rev.4.31_E

Table 42. GPIO setting (2/2)
Address
0x10030x1004

bit Register Name
[7:4] R_GPIO3_MODE

width
4

R/W
R/W

init
4'h0

[3:0] R_GPIO2_MODE

4

R/W

4'h0

[7:4] R_GPIO1_MODE

4

R/W

4'h0

[3:0] R_GPIO0_MODE

4

R/W

4'h0

Description
GPIO3 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO2 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO1 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO0 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved

Register GPIO
GPIO output control are available with register.

GPIO as secondary 2-wire port
GPIO port can be secondary 2-wire port, which can accommodate dual 2-wire access from two processors.
If two 2-wire commands are inputted at the same time, the earlier command can be communicated and the latercommand are kept wait by clock stretching scheme.

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THCV244A-QP_ Rev.4.31_E
Through GPIO Sub-Link Polling input/output
Local GPIO input is continuously reflected to remote GPIO output via Sub-Link polling. Bridging data aresampled every Sub-Link polling, whose basic interval is controlled by register R_SLINK_POL_TIM_UP/_DN.
Remote 2-wire access may become long transaction and could lengthen Through GPIO polling reflection interval.
Through GPIO input
to local Sub-Link device

Sub-Link Polling

Polling

Polling

Polling

Polling

Polling

Through GPIO output
from remote Sub-Link device
Sub-Link Polling interval

Figure 15. Through GPIO bridge sampling
As default setting with THCV231-Q as Sub-Link Slave communication (THCV244A-QP as Sub-Link Master),
GPIO1 Sub-Link Polling bridges input to THCV231-Q’s GPIO4 through mode and GPIO0 Sub-Link Polling
bridges input to THCV231-Q’s GPIO3 through mode respectively.

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THCV244A-QP_ Rev.4.31_E

As default setting with THCV241A-Q as Sub-Link Slave communication (THCV244A-QP as Sub-Link Master),
GPIO0/1 are dedicated to GPI to Sub-Link Lane0. GPIO2/3 are dedicated to GPI to Sub-Link Lane1. GPIO2/3
are also dedicated to GPO from selected Sub-Link Lane.

THCV241A-Q #0

THCV244A-QP
Upstream

Lane0

GPIO1/GPIO0

GPIO1/GPIO0

Downstrea m

GPIO3/GPIO2
THCV241A-Q #1
GPIO1/GPIO0

Upstream

Lane1

GPIO3/GPIO2

Do wnstrea m

GPIO3/GPIO2

GPIO3/GPIO2
THCV241A-Q #2

Upstream

Lane2

GPIO1/GPIO0

GPIO5/GPIO4

Downstrea m

GPIO3/GPIO2
THCV241A-Q #3
GPIO1/GPIO0

Upstream

Lane3

GPIO7/GPIO6

Downstrea m

GPIO3/GPIO2
R_RES_GP3_LN_SEL
R_RES_GP2_LN_SEL

Figure 16. Through GPIO via Sub-Link transaction assignment with THCV241A-Q

Remote UART bridge is supported with Sub-Link Polling GPIO input/output. Remote UART Tx and Rx bridge
baud rate is supposed to be designed against Sub-Link Polling interval to accommodate deterministic jitter
caused by intermittent Sub-Link communication timing.

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THCV244A-QP_ Rev.4.31_E
6.15. Internal Error / status signal monitoring ERR0/ERR1 pin output
Internal error or status signal can be monitored as external ERR0/ERR1 pin output by register setting.

Table 43. Internal Error / status signal monitoring ERR0/ERR1 pin output setting
Address
0x10050x100C
0x100D

bit Register Name
[7:4] R_ERR1_MODE

width
4

R/W
R/W

init
4'h0

[3:0] R_ERR0_MODE

4

R/W

4'h0

[7:0] R_ERR1_SEL[7:0] R_ERR0_SEL

8
8

R/W
R/W

8'h00
8'h00

Description
ERR1 I/O Mode0x0: Disable
0x1: OpenDrain Output Mode0x2: Push/Pull Output Mode
Other: Reserved
ERR0 I/O Mode0x0: Disable
0x1: OpenDrain Output Mode0x2: Push/Pull Output Mode
Other: Reserved
ERR1 Pin Output Signal Select
ERR0 Pin Output Signal SelectTable 44. IC Internal selectable Error / status signal (1/3)
R_ERR1/0_SEL[7:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F

Error signal
0 Fixed
1 FixedVx1_LOCKN_ALL
Vx1_HTPDN_ALL
Vx1_FBETOUT_LATCH_ALL
Vx1_FBETOUT_REAL_ALL
Vx1_PERR_ALL
MLINK_CRCERR_ALL
Vx1_CLOCKSTP_ALL
MLINK_VDSK_OK_ALL
MLINK_VDSK_NG_ALL
Reserved
Reserved
SLINK_PERR_ALL
SLINK_TMOUT_ALL
SLINK_FBETOUT
Vx1_LOCKN0
Vx1_LOCKN1
Vx1_LOCKN2
Vx1_LOCKN3
Vx1_HTPDN0
Vx1_HTPDN1
Vx1_HTPDN2
Vx1_HTPDN3
Vx1_BETOUT_LATCH0
Vx1_BETOUT_LATCH1
Vx1_BETOUT_LATCH2
Vx1_BETOUT_LATCH3
Vx1_BETOUT_REAL0
Vx1_BETOUT_REAL1
Vx1_BETOUT_REAL2
Vx1_BETOUT_REAL3

Copyright©2023 THine Electronics, Inc.

Description

OR operated of all operating lanes, LOCKN signal
OR operated of all operating lanes, HTPDN signal
OR operated of all operating lanes, field-bet latched result
OR operated of all operating lanes, field-bet real result
OR operated of all operating lanes, protocol error
OR operated of all operating lanes, crc error
clock stop detector of all lanes
Vsync synchronization OK flag of all lanes
Vsync synchronization NG flag of all lanes

OR operated of all operating lanes, protocol error
OR operated of all operating lanes, time out error
OR operated of all operating lanes, sub-link field-bet result
lane0 LOCKN signal
lane1 LOCKN signal
lane2 LOCKN signal
lane3 LOCKN signal
lane0 HTPDN signal
lane1 HTPDN signal
lane2 HTPDN signal
lane3 HTPDN signal
lane0 field-bet latched result
lane1 field-bet latched result
lane2 field-bet latched result
lane3 field-bet latched result
lane0 field-bet real result
lane1 field-bet real result
lane2 field-bet real result
lane3 field-bet real result

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THCV244A-QP_ Rev.4.31_E

Table 45. IC Internal selectable Error / status signal (2/3)
R_ERR1/0_SEL[7:0]
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F

Error signal
Vx1_PERR0
Vx1_PERR1
Vx1_PERR2
Vx1_PERR3
MLINK_CRCERR0
MLINK_CRCERR1
MLINK_CRCERR2
MLINK_CRCERR3
MLINK_VSYNC0MLINK_VSYNC1MLINK_VSYNC2MLINK_VSYNC3MLINK_HSYNC0MLINK_HSYNC1MLINK_HSYNC2MLINK_HSYNC3MLINK_DE0
MLINK_DE1
MLINK_DE2
MLINK_DE3
MLINK_CLK0
MLINK_CLK1
MLINK_CLK2
MLINK_CLK3
MIPI_BYTECLKOSCCLK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Copyright©2023 THine Electronics, Inc.

Description
lane0, protocol error
lane1, protocol error
lane2, protocol error
lane3, protocol error
lane0, crc error
lane1, crc error
lane2, crc error
lane3, crc error
lane0, Vsync signal
lane1, Vsync signal
lane2, Vsync signal
lane3, Vsync signal
lane0, Hsync signal
lane1, Hsync signal
lane2, Hsync signal
lane3, Hsync signal
lane0, DE signal
lane1, DE signal
lane2, DE signal
lane3, DE signal
lane0, clock signal
lane1, clock signal
lane2, clock signal
lane3, clock signal
CSI byte clock signal
internal oscilltor clock signal

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THCV244A-QP_ Rev.4.31_E

Table 46. IC Internal selectable Error / status signal (3/3)
R_ERR1/0_SEL[7:0]
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B

Error signal
MLINK_FS0
MLINK_FS1
MLINK_FS2
MLINK_FS3
MLINK_FE0
MLINK_FE1
MLINK_FE2
MLINK_FE3
MLINK_VDSK_NG0
MLINK_VDSK_NG1
MLINK_VDSK_NG2
MLINK_VDSK_NG3
TOP_CKSUM_ERR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SLINK_PERR0SLINK_PERR1SLINK_PERR2SLINK_PERR3SLINK_TMOUT0SLINK_TMOUT1SLINK_TMOUT2SLINK_TMOUT3

Copyright©2023 THine Electronics, Inc.

Description
lane0, Frame Start
lane1, Frame Start
lane2, Frame Start
lane3, Frame Start
lane0, Frame End
lane1, Frame End
lane2, Frame End
lane3, Frame End
lane0, Vsync synchronization NG flaglane1, Vsync synchronization NG flaglane2, Vsync synchronization NG flaglane3, Vsync synchronization NG flagregister checksum error

lane0, protocol error
lane1, protocol error
lane2, protocol error
lane3, protocol error
lane0, time out error
lane1, time out error
lane2, time out error
lane3, time out error

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THCV244A-QP_ Rev.4.31_E
6.16. Internal Error / status signal monitoring register
Internal error or status signal can be monitored as register read value.
Error count register can be cleared by particular register write “1” access.

Table 47. Internal Error / status signal monitoring register (1/2)
Address
0x00F1

bit Register Name
[7:1] reserved[0] R_SLINK_FBETERR_CLR

width
7
1

R/W
W

Init
-

0x00F2[7:0] R_SLINK_FBETERR_NUM_UP

8

R

-

0x00F3[7:0] R_SLINK_FBETERR_NUM_DN

8

R

-

Copyright©2023 THine Electronics, Inc.

Description<this register is valid only when 0x1035[4]=0x1>
Sub-Link FieldBET error count clear
0x1: Clear<this register is valid only when 0x1035[4]=0x1>
Sub-Link FieldBET error count parameter<this register is valid only when 0x1035[4]=0x1>
Sub-Link FieldBET error count =256×R_SLINK_FBETERR_NUM_UP<7:0>＋R_SLINK_FBETERR_NUM_DN<7:0>

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THCV244A-QP_ Rev.4.31_E

Table 48. Internal Error / status signal monitoring register (2/2)
Address
0x174Fbit Register Name
[7:4] R_MLINK_CRC_ERRCLR

width
4

R/W
W

init
-

Description
Main-Link CRC Error Counter Clear<0x174F[7] register is valid only when 0x1401[0]=0x1>[7] Main-Link CRC Error Counter Clear for Lane3
0x1: Clear<0x174F[6] register is valid only when 0x1301[0]=0x1>[6] Main-Link CRC Error Counter Clear for Lane2
0x1: Clear<0x174F[5] register is valid only when 0x1201[0]=0x1>[5] Main-Link CRC Error Counter Clear for Lane1
0x1: Clear[3:0] R_MLINK_BET_ERRCLR

4

W

-

<0x174F[4] register is valid only when 0x1101[0]=0x1>[4] Main-Link CRC Error Counter Clear for Lane00x1: Clear
Main-Link BET Error Counter Clear<0x174F[3] register is valid only when 0x1035[3]=0x1>[3] Main-Link BET Error Counter Clear for Lane3
0x1: Clear<0x174F[2] register is valid only when 0x1035[2]=0x1>[2] Main-Link BET Error Counter Clear for Lane2
0x1: Clear<0x174F[1] register is valid only when 0x1035[1]=0x1>[1] Main-Link BET Error Counter Clear for Lane1
0x1: Clear

0x1750[7:0] MLINK0_CRC_ERRNUM[15:8]

8

R

-

0x1751[7:0] MLINK0_CRC_ERRNUM[7:0]

8

R

-

0x1752[7:0] MLINK1_CRC_ERRNUM[15:8]

8

R

-

0x1753[7:0] MLINK1_CRC_ERRNUM[7:0]

8

R

-

0x1754[7:0] MLINK2_CRC_ERRNUM[15:8]

8

R

-

0x1755[7:0] MLINK2_CRC_ERRNUM[7:0]

8

R

-

0x1756[7:0] MLINK3_CRC_ERRNUM[15:8]

8

R

-

0x1757[7:0] MLINK3_CRC_ERRNUM[7:0]

8

R

-

0x1758[7:0] MLINK0_BET_ERRNUM[15:8]

8

R

-

0x1759[7:0] MLINK0_BET_ERRNUM[7:0]

8

R

-

0x175A[7:0] MLINK1_BET_ERRNUM[15:8]

8

R

-

0x175B[7:0] MLINK1_BET_ERRNUM[7:0]

8

R

-

0x175C[7:0] MLINK2_BET_ERRNUM[15:8]

8

R

-

0x175D[7:0] MLINK2_BET_ERRNUM[7:0]

8

R

-

0x175E[7:0] MLINK3_BET_ERRNUM[15:8]

8

R

-

0x175F[7:0] MLINK3_BET_ERRNUM[7:0]

8

R

-

Copyright©2023 THine Electronics, Inc.

<0x174F[0] register is valid only when 0x1035[0]=0x1>[0] Main-Link BET Error Counter Clear for Lane00x1: Clear<this register is valid only when 0x1101[0]=0x1>
Main-Link(Lane0) CRC Error Number (Upper Byte)<this register is valid only when 0x1101[0]=0x1>
Main-Link(Lane0) CRC Error Number (Lower Byte)<this register is valid only when 0x1201[0]=0x1>
Main-Link(Lane1) CRC Error Number (Upper Byte)<this register is valid only when 0x1201[0]=0x1>
Main-Link(Lane1) CRC Error Number (Lower Byte)<this register is valid only when 0x1301[0]=0x1>
Main-Link(Lane2) CRC Error Number (Upper Byte)<this register is valid only when 0x1301[0]=0x1>
Main-Link(Lane2) CRC Error Number (Lower Byte)<this register is valid only when 0x1401[0]=0x1>
Main-Link(Lane3) CRC Error Number (Upper Byte)<this register is valid only when 0x1401[0]=0x1>
Main-Link(Lane3) CRC Error Number (Lower Byte)<this register is valid only when 0x1035[0]=0x1>
Main-Link(Lane0) BET Error Number (Upper Byte)<this register is valid only when 0x1035[0]=0x1>
Main-Link(Lane0) BET Error Number (Lower Byte)<this register is valid only when 0x1035[1]=0x1>
Main-Link(Lane1) BET Error Number (Upper Byte)<this register is valid only when 0x1035[1]=0x1>
Main-Link(Lane1) BET Error Number (Lower Byte)<this register is valid only when 0x1035[2]=0x1>
Main-Link(Lane2) BET Error Number (Upper Byte)<this register is valid only when 0x1035[2]=0x1>
Main-Link(Lane2) BET Error Number (Lower Byte)<this register is valid only when 0x1035[3]=0x1>
Main-Link(Lane3) BET Error Number (Upper Byte)<this register is valid only when 0x1035[3]=0x1>
Main-Link(Lane3) BET Error Number (Lower Byte)

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THCV244A-QP_ Rev.4.31_E
6.17. Interrupt monitoring
Interrupt (INT1/0) detects occurrence of internal error or status signal and then, latch the detected state.
Interrupt factor can be cleared by particular register write “1” access. (*They are indicated as “R_INTC_*”)Interrupt factor can be masked to “0” fixed by particular register appropriate write access.
INT interrupt function is supposed to be cleared before start monitoring any desired status because INT status
may change at power on condition and THCV244A-QP internal boot up procedure.

Table 49. Interrupt monitoring
Register

Address

R_INTR_MLRX

0x1710/0x1718

R_INTR_MODE
R_INTR_DSHNDLR

0x1711/0x1719R_INTR_FMT
0x1712/0x171A

R_INTR_CSI

0x1713/0x171B

0x1714/0x171CR_INTR_BDC2Q

0x1715/0x171D

0x1716/0x171E
R_INTR_DSHNDLR

Copyright©2023 THine Electronics, Inc.

bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
6
5
4
3
2
1
0
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0

Description
Main-Link protocol error for Lane3
Main-Link protocol error for Lane2
Main-Link protocol error for Lane1
Main-Link protocol error for Lane0
Main-Link RX LOCKN=L to H detection flag for Lane3
Main-Link RX LOCKN=L to H detection flag for Lane2
Main-Link RX LOCKN=L to H detection flag for Lane1
Main-Link RX LOCKN=L to H detection flag for Lane0
Vsync synchronization OK flag of all lanes
All Main-Link RX LOCKN=H detection flag
Data Stream Handler Distribution error
Reserved
Main-Link RX CRC error1 for Lane3
Main-Link RX CRC error1 for Lane2
Main-Link RX CRC error1 for Lane1
Main-Link RX CRC error1 for Lane0
MIPI CSI-2 status error for port1
MIPI CSI-2 status error for port0
MIPI CSI-2 general error
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Internal Register AutoCheckSum error flag
Reserved
Sub-Link Slave side 2-wire access complete flag for Lane3
Sub-Link Slave side 2-wire access complete flag for Lane2
Sub-Link Slave side 2-wire access complete flag for Lane1
Sub-Link Slave side 2-wire access complete flag for Lane0
Sub-Link Slave side interrupt detection flag for Lane3
Sub-Link Slave side interrupt detection flag for Lane2
Sub-Link Slave side interrupt detection flag for Lane1
Sub-Link Slave side interrupt detection flag for Lane0
Sub-Link protocol error for Lane3
Sub-Link protocol error for Lane2
Sub-Link protocol error for Lane1
Sub-Link protocol error for Lane0
Data Stream Hander error2 for Lane3
Data Stream Hander error2 for Lane2
Data Stream Hander error2 for Lane1
Data Stream Hander error2 for Lane0

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THCV244A-QP_ Rev.4.31_E

As a register, interrupt detected state is “1” and cleared state is “0”. When multiple interrupt sources areactivated, the OR operated result is indicated as IC external INT1/0 pin output.
As an external INT1/0 pin output, open drain output interrupt detected state is “Low” and cleared state is “HiZ”, while INT1/0 pin CMOS push-pull output interrupt detected state is “Low” and cleared state is “High”.

Table 50. INT1/0 pin output control
Address
0x1006

bit Register Name
[7:4] R_INT1_MODE

width
4

R/W
R/W

init
4'h0

[3:0] R_INT0_MODE

4

R/W

4'h0

Description
INT1 I/O Mode0x0: Disable
0x1: OpenDrain Output Mode0x2: Push/Pull Output Mode
Other: Reserved
INT0 I/O Mode0x0: Disable
0x1: OpenDrain Output Mode0x2: Push/Pull Output Mode
Other: Reserved

INT1/0 interrupt function is supposed to be cleared before start monitoring any desired status because INT1/0
status may have been changed before monitoring activation.

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THCV244A-QP_ Rev.4.31_E
6.18. Multiple camera synchronization Frame Vsync supply
Frame VSYNC can be supplied from THCV244A-QP to Sub-Link Slave GPO.
EXTSYNC input or internally generated VSYNC become supply source. Settings are configurable by 2-wireaccess to internal register. When internal VSYNC is selected, generated VSYNC is not only sent to remote SubLink Slave but also output from EXTSYNC pin.

Internal VSYNC uses two clock source, internal oscillator clock and video pixel clock from Main-Link input. At
the beginning of internal VSYNC generation operation, oscillator clock is used to supply VSYNC. After MainLink video source is received stable, internal VSYNC generation source is switched to video pixel clock fromselected Main-Link input. When Main-Link video pixel clock input is lost, internal VSYNC generator again uses
internal oscillator clock until Main-Link video pixel clock input is regained.

Table 51. Multiple camera synchronization Frame Vsync supply setting (1/3)
Address
0x1007

bit Register Name
[7:4] reserved[3:0] R_EXTSYNC_MODE

Copyright©2023 THine Electronics, Inc.

width
4
4

R/W
R/W

init
4'h0

Description
EXTSYNC I/O Mode0x0: Disable
0x1: Normal Mode (Controlled by Sub-Link Register)
Other: Reserved

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THCV244A-QP_ Rev.4.31_E

Table 52. Multiple camera synchronization Frame Vsync supply setting (2/3)
Address
0x0020bit Register Name
[7:5] reserved[4] R_VS_PHASE_EN

width
3
1

R/W
RW

Init
1'h0

Description<this regiseter is valid only when 0x0020[1:0]=0x2>
Enable of shifting the Internal VSYNC output timing
0x0: Disable
0x1: Enable (*)(*) 0x002E register is related for output timing[3:2] reserved[1:0] R_VS_MODE

2
2

RW

2'h0

0x0021

[7:5]
[4]
[3:1]
[0]

reserved
ReservedL
reserved
R_VS_POL

3
1
3
1

RW
RW

1'h0
1'h0

0x0022[7] reserved[6:4] R_VS_GPI_SEL

1
3

RW

3'h0

[3:2] ReservedL[1:0] R_VS_LANE_SEL

2
2

RW
RW

2'h0
2'h0

0x0023[7:4] reserved[3:0] R_VSOSC_LINE_UP

4
4

RW

4'h0

<this regiseter is valid when 0x0010[n ]=0x1, n =0,1,2,3>
multiple camera synchronization Frame VSYNC supply mode setting
0x1: Select external VSYNC signal from EXTSYNC pin (*)
0x2: Select internal VSYNC signal and output for EXTSYNC pin (**)
Other: Disable(*) 0x1007 register is related to this mode(**) set this mode after setting both 0x0021 and 0x0023 - 0x002E registers
must be left 0x0 (default setting)<this regiseter is valid only when 0x0020[1:0]=0x2>
Internal VSYNC Pulse Polarity
0x0: Low Pulse
0x1: High Pulse<this regiseter is valid when 0x0020[1:0]=0x1 or 0x2>
Select a assignment bit for Frame VSYNC signal to send
0x0: a bit of Sub-Link for GPIO00x1: a bit of Sub-Link for GPIO1
Other: Reserved
Must be set 0x0<this regiseter is valid when 0x0020[1:0]=0x1 or 0x2>
Select Sub-Link Lane for Frame VSYNC signal to send (*each bit setting)[3]:Sub-Link Lane3 (*)[2]:Sub-Link Lane2 (*)[1]:Sub-Link Lane1 (*)[0]:Sub-Link Lane0 (*)
0x0: no send
0x1: send Frame VSYNC signal<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC clock number / line by oscillator setting

0x0024[7:0] R_VSOSC_LINE_DN

8

RW

8'h0F

0x0025[7:0] R_VSOSC_WIDTH

8

RW

8'h00

0x0026[7:4] reserved[3:0] R_VSOSC_TIM_UP

4
4

RW

4'h0

0x0027[7:0] R_VSOSC_TIM_DN

8

RW

8'h0F

Copyright©2023 THine Electronics, Inc.

<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC clock number / line by oscillator= (256×R_VSOSC_LINE_UP<3:0> +R_VSOSC_LINE_DN<7:0>+1)×tOSC*Clock / line is 1 when R_VSOSC_LINE_UP=0x0 and R_VSOSC_LINE_DN=0x0<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse width line number by oscillator settingLine Number = R_VSOSC_WIDTH + 1 (e.g. 0x00 for 1line)<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse interval line number by oscillator setting<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse interval line number by oscillator= (256×R_VSOSC_TIM_UP<3:0> +R_VSOSC_TIM_DN<7:0>+1)×tOSC*Interval line is 2 when R_VSOSC_TIM_UP=0x0 and R_VSOSC_TIM_DN=0x0

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THCV244A-QP_ Rev.4.31_E

Table 53. Multiple camera synchronization Frame Vsync supply setting (3/3)
Address
0x0028bit Register Name
[7:2] reserved[1:0] R_VS_PCLK_SEL

width
6
2

R/W
RW

Init
2'h0

0x0029[7:4] reserved[3:0] R_VSP_LINE_UP

4
4

RW

4'h0

0x002A[7:0] R_VSP_LINE_DN

8

RW

8'h0F

0x002B[7:0] R_VSP_WIDTH

8

RW

8'h04

0x002C[7:4] reserved[3:0] R_VSP_TIM_UP

4
4

RW

4'h0

0x002D[7:0] R_VSP_TIM_DN

8

RW

8'h0F

0x002E[7:0] R_VS_PHASE_WIDTH

8

RW

8'h01

Copyright©2023 THine Electronics, Inc.

Description<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC generation base pixel clock domain select0x0: select source clock (CLK_I) from Main-Link Lane00x1: select source clock (CLK_I) from Main-Link Lane1
0x2: select source clock (CLK_I) from Main-Link Lane2
0x3: select source clock (CLK_I) from Main-Link Lane3
Other: Reserved<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC clock number / line by base pixel clock setting<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC clock number / line by base pixel clock = (256×
R_VSP_LINE_UP<3:0> +R_VSP_LINE_DN<7:0>+1)×CLK_I*Clock / line is 1 when R_VSP_LINE_UP=0x0 and R_VSP_LINE_DN=0x0<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse width line number by base pixel clock settingLine Number = R_VSP_WIDTH + 1 (e.g. 0x00 for 1line)<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse interval line number setting<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse interval line number = (256×R_VSP_TIM_UP<3:0>+R_VSP_TIM_DN<7:0>+1)
Internal VSYNC pulse interval frame period by base pixel clock =(256×R_VSP_TIM_UP<3:0> +R_VSP_TIM_DN<7:0>+0x1)×(256×R_VSP_LINE_UP<3:0> +R_VSP_LINE_DN<7:0>+0x1)×CLK_I*Interval line is 2 when R_VSP_TIM_UP=0x0 and R_VSP_TIM_DN=0x0*For setting or reset of this register, R_VS_MODE is supposed to be disable<this register is valid only when 0x0020[1:0]=0x2>
The internal VSYNC output timing of Sub-Link Lane1 is delayed by"16 × R_VS_PHASE_WIDTH × CLK_I" from Sub-Link Lane0.
(e.g. 0x00 is 16×CLK_I)

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THCV244A-QP_ Rev.4.31_E
6.19. Power On Sequence
Power On Sequence must be controlled appropriate.
For Power On Reset, PDN input must be low at the moment when VDDCORE (VDD12) reach operating
condition voltage. As a note, PDN pin itself does not belongs to VDDCORE (VDD12) but to VDDIO1 (VDDH).
PDN Power On Reset control is mandatory.
MIPI, PLL and V-by-One® HS block are reset state at power on default and require Reset Release.

Operating Condition min.

VDDH
(3.3V~1.8V domain)
t1

Operating Condition min.

VDD12
(1.2V domain)

t2

t11

VIH
VIL

PDN
2-wireSCL/SDA

Sub-Link slave
IC settings

THCV244A-QP
settings

Sub-Link
RCMP/N

THCV244A-QP
PowerON

2-wire accessprohibited
2-wire remote
access prohibited

2-wire remote access

V-by-One®HS Rx Soft
reset

Polling

Pollingt3

V-by-One®HS
Rx HTPDN
V-by-One®HS
Rx LOCKN
V-by-One®HS
Rx RX*N/P

t12
Hi-Z

Training Pattern

Normal Pattern

PLL
soft reset
MIPI Tx
soft reset
MIPI Tx
TXN/P

t6
Hi-Z

MIPI LP11

NormalOperation

Figure 17.

HS-modePower On Sequence procedure

Table 54. Power On Sequence specification
symbol
t1
t2
t11
t3
t12
t6

description
Required waitfrom VDDH assert to VDD12 assert
Required waitfrom Power On to PDN High control
Required waitfrom PDN High to Register AccessTime of V-by-One®HS Rx soft reset Highto HTPDN Low
Time of Training Pattern Input
to LOCKN Low
Time of V-by-One®HS Normal operation input
to MIPI normal operation output

min.

typ.

max.

unit

0

-

-

us

1000

-

-

us

300

-

-

us

-

-

10

us

-

-

980

us

-

-

50+
1frameus

The first MIPI output from Power On waits vertical blanking period and starts output; therefore, MIPI normal
operation may be hold for maximum 1frame, which depends on used video format.

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THCV244A-QP_ Rev.4.31_E
6.20. Lock / Re-Lock Sequence
Lock and re-lock sequence are as follows. V-by-One® HS automatically shifts into lock status from initial
status or unlock status caused by external noise under appropriate parameter set condition.

THCV244A-QP LOCK Sequence
THCV244A-QP RXnP/RXnN (n=0,1)

CDR Training

ALN Training

Normal Operationt12
THCV244A-QP LOCKN

One
polingPolling Interval
THCV244A-QP (Sub-Link Master)
polling (worst. case)

LOCKN=H

Main-Link Tx LOCKN=Low
to Data pattern output delay

LOCKN=Lt6

THCV244A-QP MTXmP/MTXmN(m=0,1,2,3)

NormalOperation

MIPI LP11

Figure 18.

Normal Operation

Lock Sequence

THCV244A-QP Re-LOCK Sequence
THCV244A-QP LOCKN

One
polingPolling Interval
THCV244A-QP (Sub-Link Master)
polling (worst. case)

LOCKN=L

Polling Interval

LOCKN=HLOCKN=HOne
polingMain-Link Tx LOCKN=Low
to Data pattern output delay

LOCKN=Lt12
THCV244A-QP RXnP/RXnN (n=0,1)

Normal output

CDR Training

ALN Training

Normal Operation

Main-Link Tx LOCKN=H toTraining pattern output delayt13
THCV244A-QP MTXmP/MTXmN(m=0,1,2,3)

NormalOperation

t6B
MIPI LP11

NormalOperation

MIPI LP11

Figure 19.

Normal Operation

Re-Lock Sequence

Table 55. Lock / Re-Lock Sequence specification
symbolt13
t6B

description
Time of LOCKN=H
to MIPI Stand-by LP11 output
Time of V-by-One®HS Normal operation re-input to
MIPI normal operation re-output

Copyright©2023 THine Electronics, Inc.

60/69

min.

typ.

max.

unit

-

-

98

us

-

-

50

us

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

7.

Absolute Maximum Ratings
Table 56. Absolute Maximum Ratings*

Parameter
Supply Voltage (VDDIO1,VDDIO2)
Supply Voltage (VDDCORE,VDDRX,VDDTX,VDDPLL)LVCMOS Input Voltage (1.2V domain)
LVCMOS Input Voltage (VDDIO1 domain)
LVCMOS Output Voltage
LVCMOS Bi-directional buffer Input Voltage
LVCMOS Bi-directional buffer Output Voltage
LVCMOS Input Voltage (VDDIO2 domain)
CML Receiver Voltage
MIPI Transmitter Voltage
CML Bi-directional buffer Input Voltage
CML Bi-directional buffer Output Voltage
Output Current
Storage Temperature
Junction Temperature
Reflow Peak Temperature/time
Maximum Power Dissipation @ +25℃
*1 Max. must be below 4V at the same time
*2 Max. must be below 1.6V at the same time

min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-30
-55
-

typ.
-

max.
4
1.6
VDDRX+0.3 *2
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO2+0.3 *1
VDDRX+0.3 *2
VDDTX+0.3 *2
VDDIO2+0.3 *1
VDDIO2+0.3 *1
30
125
125
26
3.9

Unit
V
V
V
V
V
V
V
V
V
V
V
V
mA
°C
°C
°C/secW

 “Absolute Maximum Ratings” are values of safety limit for a device beyond which a device safety cannot be

guaranteed.
They do not imply that a device should be operated at these limits. The tables of “Electrical Characteristics” specify
conditions for device operation.

8.

Electrostatic discharge Ratings
Table 57. Electrostatic discharge (ESD) Ratings
SymbolVESD

9.

Parameter
Electrostatic discharge

Condition
Human Body Model (HBM)
on AEC-Q100-002
Charged Device Model (CDM)
on AEC-Q100-011

Value

Unit

+/-8000

V+/-1000

V

Recommended Operating Conditions
Table 58. Recommended Operating Conditions
SymbolVDDH

Parameter
Supply Voltage (VDDIO1, VDDIO2)

VDD12Supply Voltage 1.2V (VDDCORE, VDDRX, VDDTX, VDDPLL)Ta

Operating Ambient Temperature

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Condition
1.2Gbps < fMIPIMTXCLK0P/N
single clock out
-

min.
1.7
1.1

typ.
-

max.
3.6
1.3

Unit
V
V

1.15

1.25

1.3

V

-40

-

105

°C

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

10. Consumption Current
Table 59. Consumption Current at Power Down
symbolICCS33
ICCS12parameter
Power Down Supply Current

condition
PDN=0, VDDH=3.6V
PDN=0, VDD12=1.3V

min.
-

typ.
0.1
8

max.
-

unit
mA
mA

min.
-

typ.
16
32
48
64
14
27
41
55

max.
20
38
55
73
17
32
46
61

unit
mA
mA
mA
mA
mA
mA
mA
mA

Table 60. Consumption Current of VDDH
symbolparameter
ICCWH_33_1
ICCWH_33_2
VDDIO1/2=3.3V
ICCWH_33_3
ICCWH_33_4
ICCWH_18_1
ICCWH_18_2
VDDIO1/2=1.8V
ICCWH_18_3
ICCWH_18_4

condition
Sub-Link 1lane active
Sub-Link 2lane active
Sub-Link 3lane active
Sub-Link 4lane active
Sub-Link 1lane active
Sub-Link 2lane active
Sub-Link 3lane active
Sub-Link 4lane active

Table 61. Consumption Current of VDD12 at Data stream handling mode1
SymbolIccw12_01
Iccw12_02
Iccw12_157

port.in#1

port.out#

1

2

Iccw12_03
Iccw12_04
Iccw12_05

1

Iccw12_06
Iccw12_07
Iccw12_08

2

Iccw12_09

input
400Mbps x1lane

quasi-1080p high fps
720p30fps RAW
720p30fps YUV422
720p60fps RAW
1080p30fps RAW
720p60fps YUV422

4Gbps x2lane selected742.5Mbps x1lane
1Gbps x1lane

output
320Mbps x1lane
80Mbps x4lane
800Mbps x4lane
594Mbps x1lane
600Mbps x1lane

1.11375Gbps x1lane

445.5Mbps x2lane

1080p30fps YUV422

1

Iccw12_12

1080p60fps RAW
1

Iccw12_13

1080p60fps YUV422

Iccw12_15

Iccw12_B12

1

Iccw12_B13
Iccw12_B90
Iccw12_31
Iccw12_33
Iccw12_34
Iccw12_35

Iccw12_37
Iccw12_38
Iccw12_39
Iccw12_402
Iccw12_412

2.2275Gbps x1lane

2

2

891Mbps x2lane
445.5Mbps x4lane
594Mbps x4lane

2.97Gbps x1lane

2

Iccw12_153

594Mbps x2lane
594Mbps x2lane x2port Dist.

720p120fps YUV422

Iccw12_14

Iccw12_36

1.485Gbps x1lane

720p120fps RAW

Iccw12_10
Iccw12_11

video format
quasi-1080p low fps

1188Mbps x2lane
1188Mbps x2lane x2port Dist.

1080p120fps RAW
1080p120fps YUV422
4K60fps RAW
720p30fps RAW
720p30fps YUV422
720p60fps RAW
1080p30fps RAW
720p60fps YUV422
1080p30fps YUV422
720p120fps RAW
1080p60fps RAW
720p120fps YUV422
1080p60fps YUV422

Copyright©2023 THine Electronics, Inc.

2.2275Gbps x2lane
3Gbps x2lane
3.75Gbps x2lane
742.5Mbps x1lane x2port
750Mbps x1lane x2port

891Mbps x4lane
1200Mbps x4lane
1490Mbps x4lane
594Mbps x1lane x2port
600Mbps x1lane x2port

1.11375Gbps x1lane x2port

445.5Mbps x2lane x2port

1.485Gbps x1lane x2port

594Mbps x2lane x2port

2.2275Gbps x1lane x2port

891Mbps x2lane x2port

2.97Gbps x1lane x2port

1188Mbps x2lane x2port

62/69

min.
-

typ.
49
49
177
60
64
65
65
75
75
89
93
95
85
98
100
113
135
149
184
213
89
90
102
102
120
121
151
153
184
188

max.
111
109
251
123
126
128
128
139
139
158
160
161
150
165
166
184
224
238
276
310
148
148
165
164
186
186
219
226
258
266

Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

Table 62. Consumption Current of VDD12 at Data stream handling mode2
Symbolport.in#Iccw12_51

2
2
4
2
2
3
4
4
4
2
3
4
2
4
2
3
4
2
2
2
2
2

Iccw12_52
Iccw12_53
Iccw12_61
Iccw12_62
Iccw12_63
Iccw12_64
Iccw12_65
Iccw12_66
Iccw12_68
Iccw12_69
Iccw12_70
Iccw12_72
Iccw12_813
Iccw12_73
Iccw12_74
Iccw12_75
Iccw12_76
Iccw12_77
Iccw12_78
Iccw12_79
Iccw12_80

port.out#

1
1
1
1
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1

video format

input

quasi-1080p low fps

400Mbps x1lane x2port

quasi-1080p high fps
720p30fps RAW

1.5Gbps x1lane x4port
742.5Mbps x1lane x2port
750Mbps 1lane x2port
750Mbps 1lane x3port
750Mbps 1lane x4port
750Mbps 1lane x4port
750Mbps 1lane x4port
1.11375Gbps 1lane x2port
1.11375Gbps 1lane x3port
1.11375Gbps 1lane x4port
1.11375Gbps 1lane x2port
1.11375Gbps 1lane x4port
1.485Gbps 1lane x2port
1.485Gbps 1lane x3port
1.485Gbps 1lane x4port
1.485Gbps 1lane x2port
2.2275Gbps x1lane x2port
2.2275Gbps x1lane x2port
2.97Gbps x1lane x2port
2.97Gbps x1lane x2port

720p30fps YUV422

720p30fps YUV422 dist
720p60fps RAW

1080p30fps RAW

720p60fps YUV422
1080p30fps YUV422
720p120fps RAW
1080p60fps RAW
720p120fps YUV422
1080p60fps YUV422

Copyright©2023 THine Electronics, Inc.

63/69

output
640Mbps x1lane
160Mbps x4lane
1200Mbps x4lane
594Mbps x2lane
600Mbps x2lane
900Mbps x2lane
600Mbps x4lane
1.2Gbps x2lane
1.2Gbps x2lane x2port Dist.

891Mbps x2lane
668.25Mbpx x4lane
891Mbps x4lane
891Mbps x2lane
891Mbps x2lane x2port
594Mbps x4lane
891Mbps x4lane
1188Mbps x4lane
594Mbps x4lane
891Mbps x4lane
891Mbps x4lane
1188Mbps x4lane
1188Mbps x4lane

min.
-

typ.
73
66
199
84
84
115
132
147
165
105
129
165
105
172
113
153
195
114
142
144
173
176

max. Unit
140 mA132 mA286 mA
153 mA
154 mA
192 mA
209 mA
230 mA259 mA
177 mA
207 mA244 mA
174 mA
253 mA
187 mA
235 mA
281 mA
184 mA
221 mA219 mA257 mA255 mA

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

11. DC Specifications
11.1. LVCMOS DC Specifications

Table 63. LVCMOS DC Specifications
symbolIIH
IIL

parameter
LVCMOS Input Leak Current HighLVCMOS Input Leak Current Low

VIH

LVCMOS High Level Input Voltage

pin typeILIL

condition
VIN=VDDIO1
VIN=GNDVDDIO1=1.7~2.0V
VDDIO1=2.0~3.0V
VDDIO1=3.0~3.6V
VDDIO1=1.7~3.6V
VDDIO1=1.7~2.0V
VDDIO1=2.0~3.0V
VDDIO1=3.0~3.6V

min.
-10
0.65*VDDIO1
0.70*VDDIO1
2.0
0.70*VDDIO1
0
0
0

typ.
-

max.
10
VDDIO1VDDIO1VDDIO1VDDIO10.35*VDDIO1
0.30*VDDIO1
0.8

unit
uA
uA
V
V
V
V
V
V
V

IL

VDDIO1=1.7~3.6V

0-0.30*VDDIO1

V

B
IL
B

VIL

LVCMOS Low Level Input Voltage

VOH

LVCMOS High Level Output Voltage

B,O

IOH=-1mA

VDDIO1-0.45-

VDDIO1V

VOL

LVCMOS Low Level Output Voltage

B,O

IOL=1mA

0

-

0.45

V

11.2. CML Receiver DC Specifications

Table 64. CML Receiver DC Specifications
symbolVRTH
VRTL

parameter
CML Differential Input High Threshold
CML Differential Input Low Threshold

IRIH

CML Input Leak Current HighIRIL

CML Input Leak Current Low

IRRIH
IRRIL
RRIN

CML Input Current HighCML Input Current Low
CML Differential Input Resistance

Copyright©2023 THine Electronics, Inc.

condition
PDN=L,
RXP/N=VDDRXPDN=L,
RXP/N=GND
RXP/N=VDDRX
RXP/N=GND
-

64/69

min.
-50

typ.
-

max.
50
-

unit
mV
mV

-

-

±15

uA

-

-

±15

uA

-4.6
80

100

1.6
120

mA
mA
ohm

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E
11.3. CML Bi-directional Buffer DC Specifications

Table 65. CML Bi-directional Buffer DC Specifications
symbol
VBTH
VBTL
VBIC
IBIH
IBIL
VBOD
VBOC
IBOZ

parameter
CML Bi-Directional Buffer
Differential Input High Threshold
CML Bi-Directional Buffer
Differential Input Low Threshold
CML Bi-Directional Buffer Input
Terminated Common Voltage
CML Bi-Directional Buffer
Output Leak Current HighCML Bi-Directional Buffer
Output Leak Current Low
CML Bi-Directional Buffer
Differential Output Voltage
CML Bi-Directional Buffer
Common Output Voltage
CML Bi-Directional Buffer
TRI-STATE Current

RTERM

CML Bi-Directional Buffer
Termination Registance

IDRIVE

CML Bi-Directional Buffer
Drive Current

condition
R_BDCZ_HYS=0
R_BDCZ_HYS=1
R_BDCZ_HYS=0
R_BDCZ_HYS=1
R_BDCZ_TERM_**= 2'b00
R_BDCZ_DRIVE_**= 2'b00

min.
-50
-150

typ.
-

max.
50
150
-

unit
mV
mV
mV
mV

-

VDDIO2-300-

mV

RCMP/N=VDDIO2

-10

-

10

uA

RCMP/N=GND

-10

-

10

uA

200

300

400

mV

-

VDDIO2-300

-

mV

PDN=L

-10

-

10

uA

R_BDCZ_TERM_**=2'b10
R_BDCZ_TERM_**=2'b01
R_BDCZ_TERM_**=2'b00
R_BDCZ_DRIVE_**=2'b10
R_BDCZ_DRIVE_**=2'b01
R_BDCZ_DRIVE_**=2'b00

-

50
100
200
12
6
3

-

ohm
ohm
ohm
mA
mA
mA

typ.
200
200
-

max.
250
270
350
1.3
0.05
-

unit
mV
mV
mV
V
V
ohm

R_BDCZ_TERM_**=2'b10
R_BDCZ_DRIVE_**=2'b10
Diff. 100ohm terminated
R_BDCZ_TERM_**=2'b00
R_BDCZ_DRIVE_**=2'b00

11.4. MIPI Transmitter DC Specifications

Table 66. MIPI Transmitter DC Specifications
symbolVTCMTX|VTOD|VTOHHSVTOHLP
VTOLLP
ZTOLP

parameter
HS-mode statics Common-mode Voltage
HS-mode Differential Voltage
HS-mode High Level Output Voltage
LP-mode High Level Output Voltage
LP-mode Low Level Output Voltage
LP-mode Output Impedance

Copyright©2023 THine Electronics, Inc.

condition
ZID=80~125ohm
ZID=100ohm
ZID=100ohm
-

65/69

min.
150
140
1.1
-0.05
110

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

12. AC Specifications
12.1. General AC Specifications
Table 67. General AC Specifications
symboltDLparameter

Data Latency

condition
MainLink 1Gbps,
Data stream
handling mode1,
0x1502 - 0x1505
registers are set
default value.

min.

typ.

max.

unit

typ.-98

16,000typ.+98

ns

typ.
-

max.
2500
4

unit
ps
Gbps

typ.
137.5

max.
172.7

unit
ns

12.2. CML Receiver AC Specifications
Table 68. CML Receiver AC Specifications
symboltRBIT
fRBITparameter

condition-

Unit Interval

min.
250
0.4

12.3. CML B-directional Buffer AC Specifications
Table 69. CML B-directional Buffer AC Specifications
symboltBUIparameter
Bi-Directional CML Buffer Unit Interval

condition
-

min.
128.7

12.4. 2-wire serial Slave AC Specifications
Table 70. 2-wire serial Slave AC Specifications
symboltOSC
fSCLtHD;STA
tLOW
tHIGH

tr

parameter
Cycle of internal oscillator clock
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START
condition
Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals

tf

Fall time of both SDA and SCL signals

tSU;STAtHD;DATtSU;DATtSU;STO

condition
-

min.
11.7
0.26
0.5
0.26

typ.
12.5
-

max.
15.7
1000
-

unit
ns
kHz
us
us
us

-

0.26

-

-

us

pull-up:2.5kΩ, bus
capacitance :
400pF
-

0
0
50
50
-

2*tOSC-

120(*1)

us
ns
ns
ns
ns

-

-

120

ns

0.26

-

-

ns

0.5

-

-

us

-

-

50

ns

300

-

-

us

Setup time for STOP condition
Bus free time between a STOP
and START condition
Pulse width of spikes which must be
tSP
suppressed by the input filter
Required wait time from PDN0 hightPDS
to START condition*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.
tBUF

Copyright©2023 THine Electronics, Inc.

66/69

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SC:E

THCV244A-QP_ Rev.4.31_E
12.5. MIPI Transmitter AC Specifications
Table 71. MIPI Transmitter AC Specifications
symbol
tTBIT
fMIPI
tTBIT
fMIPI
tCLK-POSTtCLK-PREtCLK-PREPAREtCLK-TRAIL

parameter

condition

min.
0.833
80
0.671
1200

typ.
-

max.
12.5
1200
0.833
1490

unit
ns
Mbps
ns
Mbps

60+52*tTBIT

-

-

ns

fMIPI = 1200Mbps

8

-

-

fMIPI = 600Mbps

4

Tx Unit Interval
1.15V < VDD12MTXCLK0P/N single clock out

Time that the transmitter continues to send HS
clock after the last associated Data Lanes has
transitioned to LP Mode.
Time that the HS clock shall be driven by thetransmitter prior to any associated Data Lane
beginning the transition from LP to HS mode.
Time that the transmitter drives the Clock Lane
LP-00 Line state immediately before the HS-0
Line state starting the HS transmission.
Time that the transmitter drives the HS-0 state
after the last payload clock bit of a HStransmission burst.

fMIPI = 1200Mbps
R_T X_CLK_POST* = 0x0F
fMIPI = 600Mbps
R_T X_CLK_POST* = 0x0A

tTBIT
fMIPI = 1200Mbps
R_T X_CLK_PREPARE* =0x06
fMIPI = 600Mbps

38

-

95

ns

60

-

-

ns

300

-

-

ns

-

-

105+12*tTBIT

ns

100

-

-

ns

40+4*tTBIT-

85+6*tTBIT

ns

145+10*tTBIT

-

-

ns

60+4*tTBIT

-

-

ns

50

-

-

ns

R_T X_CLK_PREPARE* =0x03
fMIPI = 1200Mbps
R_T X_CLK_TRAIL* = 0x0C
fMIPI = 600Mbps
R_T X_CLK_TRAIL* = 0x07
fMIPI = 1200Mbps
R_T X_CLK_PREPARE* =tCLK-PREPARE+ tCLK-ZERO

tCLK-PREPARE + Time that the transmitter
drives the HS-0 state prior starting the Clock.

0x06
R_T X_CLK_ZERO* = 0x29
fMIPI = 600Mbps
R_T X_CLK_PREPARE* =0x03
R_T X_CLK_ZERO* = 0x13
fMIPI = 1200Mbps

tEOT

Transmitted time interval from the start of tHSTRAIL or tCLK-TRAIL, to the stat of the LP-11
state follow ing a HS burst.

R_T X_CLK_TRAIL* = 0x0C
R_T X_THS_TRAIL* = 0x0C
fMIPI = 600Mbps
R_T X_CLK_TRAIL* = 0x07
R_T X_THS_TRAIL* = 0x07
fMIPI = 1200Mbps

tHS-EXITTime that the transmitter drives LP-11 follow ing
a HS burst.

R_T X_THS_EXIT* = 0x04
fMIPI = 600Mbps
R_T X_THS_EXIT* = 0x00

tHS-PREPARETime that the transmitter drives the Data Lane
LP-00 Line state immediately before the HS-0
Line state starting the HS transmission.

fMIPI = 1200Mbps
R_T X_THS_PREPARE*= 0x06
fMIPI = 600Mbps
R_T X_THS_PREPARE*= 0x03
fMIPI = 1200Mbps
R_T X_THS_PREPARE* =tHS-PREPARE+ tHS-ZERO

tHS-PREPARE + Time that the transmitter drives
the HS-0 state prior to transmitting the Sync
sequence.

0x06
R_T X_THS_ZERO* = 0x10
fMIPI = 600Mbps
R_T X_THS_PREPARE* =0x03
R_T X_THS_ZERO* = 0x06

tHS-TRAIL

Time that the transmitter drives the flipped
differential state after last payload data bit of a
HS transmission burst.

fMIPI = 1200Mbps
R_T X_THS_TRAIL* = 0x0C
fMIPI = 600Mbps
R_T X_THS_TRAIL* = 0x07
fMIPI = 1200Mbps

tLPX

Transmitted length of any Low -Pow er state
period.

R_T X_TLPX* = 0x08
fMIPI = 600Mbps
R_T X_TLPX* = 0x04

Copyright©2023 THine Electronics, Inc.

67/69

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SC:E

THCV244A-QP_ Rev.4.31_E

13. Package
TOP VIEW

9.00

LASER MARKFOR PIN1

9.00

BOTTOM VIEW
1.10

6.00
17

32

16

33

0.09
R

0.45

6.00

PIN1 ID
0.20 R

1

48

0.50

SIDE VIEW

0.40

0.65

0.25

1.10

49

0.90 MAX

64

Unit: mm

Copyright©2023 THine Electronics, Inc.

68/69

THine Electronics, Inc.

SC:E

THCV244A-QP_ Rev.4.31_E

14. Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

Copyright©2023 THine Electronics, Inc.

69/69

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