THCV233-234_Design Guide_Rev.2.00_E

Application Note THCV233-234_Design Guide_Rev.2.00_E

THCV233/THCV234 Application Note
System Diagram and PCB Design Guideline

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THCV233-234_Design Guide_Rev.2.00_E

Contents
Selection table ........................................................................................................................................................ 3
Application Diagram (Case1) ............................................................................................................................... 4
Application Diagram (Case2) ............................................................................................................................... 5
Application Diagram (Case3) ............................................................................................................................... 6
Application Diagram (Case4) ............................................................................................................................... 7
Recommendations for Power Supply ................................................................................................................... 8
Recommended Power Supply for THCV233 ............................................................................................................................................................................. 8

Recommendations for Power Supply ................................................................................................................... 9
Recommended Power Supply for THCV234 ............................................................................................................................................................................. 9Note ....................................................................................................................................................................... 10
PCB Layout Considerations ............................................................................................................................... 12
Notices and Requests ........................................................................................................................................... 13

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THCV233-234_Design Guide_Rev.2.00_E

Selection table*High Speed CML Link

THCV233

THCV234
High Speed CML Link

Data Input

Main-Link
Block

Main-Link
Block

Clock
Input

Data
OutputClock
OutputLOCKN/HTPDNHigh Speed CML Link Operation

Case No.
Page No.
se No

THCV233

THCV234

Single-In/Single-Out

Single-In/Single-Out

3.4G

32bit

3.4G

32bit

@85MHz@85MHzLVDS

LVDS

Single-In/Dual-Out

32bit

Dual-In/Single-Out

1.7G

1.7G

32bit

@85MHz@85MHz

LVDS

LVDS

1.7G

Dual-In/Selected Single-Out

3.4G

3.4G

@85MHz

32bit

LVDS
32bit

Case 2→Page 6

1.7G

Single-In/Single-Out * 2
32bit

Case 1→Page 5

Case 3→Page 7

@85MHz

3.4G

3.4G@85MHzLVDS

LVDS

Single-In/Distributed Dual-Out

Single-In/Single-Out * 2
3.4G

3.4G

32bit
@85MHz

32bit

LVDS

@85MHz
LVDS

3.4G

3.4G

Case 4→Page 832bit
@85MHzLVDS

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Application Diagram (Case1)
Case1
THCV233
THCV234

High Speed CML-Link
Single-In/Single-Out
Single-In/Single-Out

THCV233

LVDS
Driver

THCV234

TLA0.1F
TLA+
TX0n
TLBTX0p
TLB+
TLCTX1n
TLC+
OPEN
TX1p
TLCLKTLCLK+TLDReserved[3]TLD+
Reserved[2] OPEN
TLEReserved[0]TLE+

OPEN or GND

OPEN or GND

RLARLA+RX0nRLBRX0pRLB+
RLCRX1nRLC+
RX1p
RLCLKRLCLK+RLDReserved[2]RLD+
Reserved[1]RLERLE+

10k

PDN=H
->Normal operation
MODE1=L, MODE0=H-> Single-In/Single-Out
PRE=L-> Pre-emphasis0%

COL
PDN

LOCKN

MODE1
MODE0
DESEL

HTPDN

LOCKN
*4

OPEN

*4

MODE1=H, MODE0=H

PDN
MODE1
MODE0
Reserved[5]HTPDN-> Single-In/Single-Out
COL=L-> 32bit mode
PDN=H-> Normal operation

COL
Reserved[0,3,4,6,7,8,9]

Reserved[4:8]

DE Signal input (CMOS)

LVDS
Receiver

VDH

VDH

VDH

COL=L
-> 32bit mode

0.1F



RS=H
Normal swing-> LVDS output

DEIN(When DE input from LVDS,
DEIN: OPEN)

DEOUT

TP
*3
DE signal output (CMOS)/Field BET result(When DE input from LVDS,DEOUT: OPEN)

VDH
10k
VDH

VDH
10k

RS
NC

*3

NC

PRE
0

Reserved[1]

VDH
OPEN

VDH

*3

*3 0 

*2

BET
GND

*1
*2
*3
*4

NC
BET

NC
0

DGLOCK

GND

indicates micro-strip lines or cables with their differential characteristic impedance being 100ΩConnect GNDs of both Tx and Rx PCB
Field BET Operation. Please see the datasheet for details. ( THCV233-234_Rev.x.xx_E.pdf )No HTPDN connection option. Please see the datasheet for details. (THCV233-234_Rev.x.xx_E.pdf)

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THCV233-234_Design Guide_Rev.2.00_E

Application Diagram (Case2)
Case2
THCV233
THCV234

High Speed CML-Link
Single-In/Dual-Out
Dual-In/Single-Out

THCV233

LVDS
Driver

THCV234

TLA0.1F
TLA+
TX0n
TLBTX0p
TLB+
0.1F
TLCTX1n
TLC+
TX1p
TLCLKTLCLK+TLDReserved[3]TLD+
Reserved[2] OPEN
TLE- Reserved[0]TLE+

RLARLA+RX0nRLBRX0p
RLB+
0.1F
RLCRX1nRLC+
RX1p
RLCLKRLCLK+RLDReserved[2]RLD+
OPEN or GND
Reserved[1]RLERLE+

VDH
10k

COL
PDN

PDN=H
->Normal operation

LOCKN

MODE0
MODE1

MODE1=H, MODE0=L-> Single-In/Single-Out

HTPDN

*4

OPEN

*4

Reserved[4:8]

PRE=L-> Pre-emphasis0%

DE Signal input (CMOS)

LVDS
Receiver

0.1F

VDH

VDH

COL=L
-> 32bit mode



LOCKN

PDN

HTPDN

MODE1
MODE0
Reserved[5]MODE1=L, MODE0=H-> Single-In/Single-Out
COL=L-> 32bit mode
PDN=H-> Normal operation

COL
Reserved[0,3,4,6,7,8,9]

RS=H
Normal swing-> LVDS output

DEIN(When DE input from LVDS,
DEIN: OPEN)

DEOUT
VDH

TP
*3

10k 

DE signal output (CMOS)/Field BET result

DESEL(When DE input from LVDS,DEOUT: OPEN)

NC
VDH
10k
VDH

VDH
10k

RS
NC

*3

NC

PRE
0

Reserved[1]

VDH
OPEN

VDH

*3

*3 0 

*2

BET
GND

*1
*2
*3
*4

NC
BET

NC
0

DGLOCK

GND

indicates micro-strip lines or cables with their differential characteristic impedance being 100ΩConnect GNDs of both Tx and Rx PCB
Field BET Operation. Please see the datasheet for details. ( THCV233-234_Rev.x.xx_E.pdf )No HTPDN connection option. Please see the datasheet for details. (THCV233-234_Rev.x.xx_E.pdf)

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THCV233-234_Design Guide_Rev.2.00_E

Application Diagram (Case3)
Case3
THCV233
THCV234

High Speed CML-Link
Single-In/Single-Out*2
Dual-In/Selected Single-Out

LVDS Driver

THCV233
TLA-

PDN=H
MODE1=L, MODE0=H->Single-In/Single-Out*2
COL=L->32bit mode0

DE Signal input (CMOS)

TX1n
TX1p

OPEN

VDH

VDH

NC

VDH

OPEN or GND

*4

OPEN

NC
MODE0
COL
MODE1
Reserved[4:8]
DESEL

PRE

THCV234RX0n
RLARX0p
RLA+

0
VDH
Select input for High-speed
CML Link (Lane0=L/Lane1=H)NC
BET *3
0

PDN

10k

Reserved[1]
LOCKN
DEIN

LOCKN

HTPDN

*4

(When DE input from LVDS,
DEIN: OPEN)

*1
*2
*3
*4

10k

RX1n
RX1p

DEOUT

TP
*3

VDH

RS=H
->LVDS output
Normal swing
DE signal output(CMOS)/
FieldBET result(DE input from LVDS,DEOUT: OPEN)

10k
RS
NC

VDH
NC
OPEN

*2

Reserved[1]
DEIN

COL=L
->32bit mode

0.1F

0.1F

TX0n
TX0p
TLCLKTX1n
TLCLK+OPEN
TLDTX1p
TLD+
Reserved[3]TLEReserved[2] OPEN
TLE+
Reserved[0]VDH
Power Down
PDN
NC
(Normal Operation=H/ VDH
PREPower Down=L)
MODE0
0
COL
VDH
VDH
MODE1
0
Reserved[4:8]NC
BET *3
0
DESEL
NC
VDH
DE Signal input (CMOS)

MODE0=L
MODE1=H or L->Dual-In/
Selected Single-Out

COL
Reserved[0,3,4,6,7,8,9]

THCV233
LOCKN

PDN=H

MODE1
MODE0
Reserved[5]VDH

TLATLA+TLBTLB+TLCTLC+LVDS
ReceiverRLBRLB+RLCRLC+
Reserved[2]Reserved[1] RLCLKRLCLK+RLDHTPDNRLD+RLERLE+

VDH

10k

(When DE input from LVDS,
DEIN: OPEN)

0.1F

TLCLKTLCLK+ Reserved[3] OPEN
Reserved[2]TLDReserved[0]TLD+
TLEHTPDN *4
TLE+
VDH
PDN

PRE=L
->Pre-emphasis 0%

Power Down
(Normal Operation=H/
Power Down=L)

0.1F

TX0n
TX0p

TLA+
TLBTLB+TLCTLC+GND

DGLOCKBET*3 0 

GND

indicates micro-strip lines or cables with their differential characteristic impedance being 100ΩConnect GNDs of both Tx and Rx PCB
Field BET Operation. Please see the datasheet for details. ( THCV233-234_Rev.x.xx_E.pdf )No HTPDN connection option. Please see the datasheet for details. (THCV233-234_Rev.x.xx_E.pdf)

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THCV233-234_Design Guide_Rev.2.00_E

Application Diagram (Case4)
Case4
THCV233
THCV234

High Speed CML-Link
Single-In/Distributed Dual-Out
Single-In/ Single-Out*2

THCV234

THCV233

LVDS
Driver

0.1F

TLATLA+TLBTLB+TLCTLC+TLCLKTLCLK+TLDTLD+TLETLE+

MODE1=L, MODE0=L->Single-In/
Distributed Dual-Out
COL=L-> 32bit mode
PDN=H->Normal operation

RLARLA+
0.1 F
RLBRX0nRLB+
RX0pRLCRLC+RLCLKRX1nRLCLK+
OPEN or GND
RX1p
RLDRLD+
RLEReserved[2]RLE+
OPEN or GND
Reserved[1]

TX0n
TX0p

VDH
10k
LOCKN

PRE=L
-> Pre-emphasis0%
Power Down

HTPDN

PDN
COL
MODE1
MODE0

OPEN *4HTPDN(DE input from LVDS,DEOUT: OPEN)
VDH
k
*3

VDH
NC

DGLOCK

OPEN *4

10k 

HTPDN

DESEL
NC

LOCKN

OPEN

0.1F

0.1F

TX1n
TX1p

RX0n
RX0p

Reserved[3]Reserved[2] OPEN
Reserved[0]

RX1n
RX1p

RLA-



RLA+
RLB
RLB+
RLCRLC+RLCLKRLCLK+RLDRLD+RLERLE+

MODE1=H, MODE0=H-> Single-In/Single-Out
COL=L-> 32bit mode
PDN=H-> Normal Operation
RS=H-> LVDS output Normal swing

Reserved[1]
VDH
NC
0

*3

OPEN or GND

BETOPEN or GND

RCMN
RCMP

GND

DE signal output

PDN
MODE1
MODE0
Reserved[5](CMOS)/
FieldBET result(DE input from LVDS,DEOUT: OPEN)
VDH

COL
Reserved[0,3,4,6,7,8,9]
DEOUT
RS
BET

*2

*1
*2
*3
*4

0

LVDS Receiver

THCV234

VDH

VDH

NC

TP

*3

0

DEIN

10k

DE signal output(CMOS)/
FieldBET result

RS
BET

DGLOCKNC(When DE input from LVDS,
DEIN: OPEN)

Power Down

VDH
PRE

DE Signal input (CMOS)

VDH

COL
Reserved[0,3,4,6,7,8,9]
DEOUT

Reserved[4:8]

LVDS Receiver

PDN
MODE1
MODE0
Reserved[5]

LOCKN
*5



k
*3

NC

TP
VDH
NC
*3

GND

0

indicates microstrip lines or cables with their differential characteristic impedance being 100ΩConnect GNDs of both Tx and Rx PCB
Field BET Operation. Please see the datasheet for details. (THCV233-234_Rev.x.xx_E.pdf)
No HTPDN connection option. Please see the datasheet for details. (THCV233-234_Rev.x.xx_E.pdf)

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THCV233-234_Design Guide_Rev.2.00_E

Recommendations for Power Supply

Separate all the power domains in order to avoid unwanted noise coupling between noisy digital andsensitive analog domains.
Use high frequency ceramic capacitors of 10nF or 0.1μF as bypass capacitors between power and groundpins. Place them as close to each power pin as possible.
Adding 4.7μF capacitors to PLL's power pins, along with the smaller bypass capacitors, is recommended.

Recommended Power Supply for THCV233

ferrite bead
LAVDH
10uF

3.3V

LAVDH

CAVDL
10uF
CPVDL
10uF

VDD

10uF

LAGND

0.1uF

VDD
1.8V

0.1uF

ferrite bead

36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48

THCV233
Exposed PAD
49 EXPGND

24
23
22 CAVDL
21 CAGND
20
19
18 CAGND
17
16
15 CAGND
14 CAVDL
13 CPVDL

0.1uF

0.1uF
0.1uF

4.7uF

1 2 3 4 5 6 7 8 9 10 11 12

VDD
VSS

LAVDH

LAGND

0.1uF

0.1uF

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THCV233-234_Design Guide_Rev.2.00_E

Recommendations for Power Supply

Separate all the power domains in order to avoid unwanted noise coupling between noisy digital andsensitive analog domains.
Use high frequency ceramic capacitors of 10nF or 0.1μF as bypass capacitors between power and groundpins. Place them as close to each power pin as possible.

Recommended Power Supply for THCV234

ferrite bead
LAVDH
10uF

3.3V

CAVDL
VDD

10uF

LAVDH

10uF

LAGND

0.1uF

VDD
1.8V

0.1uF

ferrite bead

36 35 34 33 32 31 30 29 28 27 26 25

0.1uF

0.1uF

37
38
CAGND 39
40
41
CAVDL 42CAGND 43
44
45
CAGND 46CAVDL 47
48

24
23
22
21
20
19
18
17
16
15
14
13

THCV234
Exposed PAD
49 EXPGND

1 2 3 4 5 6 7 8 9 10 11 12

LAVDH
LAGND

0.1uF

0.1uF

9/13

VSS
VDD

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THCV233-234_Design Guide_Rev.2.00_E

Note1)LVDS input pin connection
When LVDS line is not driven from the previous device, the line is pulled up to 3.3V internally in THCV233.
This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose operating
condition is lower voltage power supply than 3.3V. This phenomenon may happen at power on phase of thewhole system including THCV233. One solution for this problem is PDN=L control during no LVDS input
period because pull-up resistors are cut off at power down state.
LVDS Tx side PCB

LVDS Rx side PCB
VDD

Low VDD

THCV233
LVDS Txor
LVDS Tx
integrated
device
LVDS input bufferInternal circuit of THCV233

2)Power On Sequence
Do not apply VDH before VDL. VDL and VDH can be applied at the same time.
3)Data Input Sequence
Don’t input TLCLK+/- before THCV233 is on in order to keep absolute maximum ratings.
4)Cable Connection and Disconnection
Don’t connect and disconnect the LVDS and CML cable, when the power is supplied to the system.
5)GND Connection
Connect the each GND of the PCB which Transmitter, Receiver and THCV233 on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.
6) Low Input Pulse into PDN Period Requirement
Don’t Input Low Pulse within 1msec into PDN.
7) Multi Drop Connection
Multi drop connection is not recommended.
RLCLK THCV 234

LVDS RxRLCLK +LVDS Rx

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8)Multiple device connection
HTPDN and LOCKN signals are supposed to be connected proper for their purpose like the following figure.
HTPDN should be from just one Rx to multiple Tx because its purpose is only ignition of all Tx.
LOCKN should be connected so as to indicate that all Rx CDR become ready to receive normal operation data.
LOCKN of Tx side can be simply split to multiple Tx.
THCV234 DGLOCK connection is appropriate for multiple Rx use.
Also possible time difference of internal processing time (Data sheet THCV233 tTCD and THCV234 tRDC)
on multiple data stream must be accommodated and compensated by the following destination device connected
to multiple THCV234, which may have internal FIFO.

THCV233

THCV234

HTPDN

HTPDN

LOCKN

LOCKN

clkin.1

clkout.1
FIFO

DGLOCK
SourceDeviceEx. synchronizedTime diff. comes up

THCV233

THCV234

HTPDN

HTPDN

LOCKN

LOCKN

Destination
Device

FIFO
clkin.2

clkout.2

DGLOCKInternal processing time tTCD

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THCV233-234_Design Guide_Rev.2.00_E

PCB Layout Considerations








Use at least four-layer PCBs with signals, ground, power, and signals assigned for each layer. (Refer tofigure below.)
PCB traces for high-speed signals must be single-ended micorstirp lines or coupled microstrip lines whose
differential characteristic impedance is 100Ω.
Minimize the distance between traces of a differential pair (S1) to maximize common mode rejection andcoupling effect which works to reduce EMI (Electro-Magnetic Interference).
Route differential signal traces symmetrically.
Avoid right-angle turns or minimize the number of vias on the high speed traces because they usually cause
impedance discontinuity in the transmission lines and degrade the signal integrity.
Mismatch among impedances of PCB traces, connectors, or cables also caused reflection, limiting the
bandwidth of the high-speed channels.
Using common-mode filter on differential traces is desirable to reduce EMI. Pay attention on data-rate
driven noise. For example, if data-rate is 1.5Gbps, common mode choke coil of 1.5GHz common mode
impedance is desired to be high, while 1.5GHz differential impedance is low.

PCB Cross-sectional View
for Microstrip Lines> 3 x S1

S1

GND

> 3 x S1

GND

Layer1: Signals
Layer2: Ground
Layer3: Power
Layer3: Signals

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THCV233-234_Design Guide_Rev.2.00_E

Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply
to the customer's design. We are not responsible for possible errors and omissions in this material. Please
note if errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.

5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video
device, office automation device, communication device, consumer electronics, smartphone, featurephone, and amusement machine device. This product must not be used for applications that require
extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear
power control device, combustion chamber device, medical device related to critical care, or any kindof safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") inthis data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product otherthan the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent
that the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with acertain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged tohave sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems
necessary to support warranty for performance of this product. Except where mandated by applicablelaw or deemed necessary by THine based on the user’s request, testing of all functions and performanceof the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings ormalfunction, if pins of the product are shorted by such as foreign substance. The damages may cause asmoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.

THine Electronics, Inc.
sales@thine.co.jp

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