THCV226_Rev.1.30_E

THCV226
V-by-One® HS High-speed Video Data Receiver

General Description

Features

THCV226 is designed to support video datatransmission between the host and display. This chipcan receive 32bit video data and 3bit control data via
four differential pairs of V-by-One® HS lanes. This
chip in TQFP package supports the video datatransmission up to 1080p/10b/120Hz. The maximum
serial data rate is 3.4Gbps/lane.

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Normal / High-speed LVDS output selectable
1.8V single power supply
Color depth selectable: 8/10 bits per colors
Crossing / Distribution mode selectable
Monitoring signal function
1.8V LVCMOS I/O interface
Package: 128pin 0.4mm-pitch TQFP
(16mm x 16mm)
AC coupling for CML inputs
CDR requires no external frequency reference
Supports Spread Spectrum Clocking tolerancewith up to 30kHz/0.5%(center spread)V-by-One® HS standard compliant
PLL requires no external components
Power down / Output enable mode
Compliant with RoHS and REACH

Block Diagram
VDD

HTPDN
LOCKN
MONOUTDGLOCK

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…..

…..

RLE0p/nRLCLK0p/n

Color
Depth

Normal Speed
LVDS Mode

High-Speed
LVDS Mode

8bit

1.2 to 2.7Gbps

1.2 to 2.36Gbps

10bit

1.6 to 3.4Gbps

1.6 to 3.14Gbps

…..

…..

RLA1p/nRLE1p/nRLCLK1p/n…..

 Clock Frequency of LVDS Output

RLE2p/nRLCLK2p/n

Color
Depth

Normal Speed
LVDS Mode

High-Speed
LVDS Mode

RLA3p/n

8bit

40 to 90MHz

80 to 157MHz

10bit

40 to 85MHz

80 to 157MHz

…..

…..

RLA2p/n…..

LVDS
Serializer

LVDS
Serializer

LVDS
Serializer

LVDS
Serializer

Controls

 Data Transmission Rate of CML Input

RLA0p/nRLE3p/nRLCLK3p/n

PLL

Cross Switch

Deskew & Formatter

CML
Deserializer
CDR

Rx3p
Rx3n

Deskew & Formatter

Rx2p
Rx2n

CML
Deserializer

Rx1p
Rx1n

CML
Deserializer

Rx0p
Rx0n

CML
Deserializer(1.8V)

Color Depth
Transmission Mode Setting
Power Down
Output Enable
Monitoring Signal Setting

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THCV226_Rev.1.30_E

PIN Configuration

LVDD 65
GND 66CVDD 67
RLE0p 68
RLE0n 69
RLD0p 70
RLD0n 71
GND 72
LVDD 73
RLCLK0p 74
RLCLK0n 75
RLC0p 76
RLC0n 77
GND 78
LVDD 79
RLB0p 80
RLB0n 81
RLA0p 82
RLA0n 83
GND 84
LVDD 85
CVDD 86
GND 87
COL 88
OPF 89MODE0 90
MODE1 91
MODE2 92
Reserved3 93
Reserved4 94
Reserved5 95
GND 96
Reserved6 97
Reserved7 98
OE 99
IOVDD 100
DGLOCK 101
HTPDN 102LOCKN 103
CVDD 104
GND 105
VVDD 106
Rx0n 107
Rx0p 108
GND 109
Rx1n 110
Rx1p 111
VVDD 112
GND 113
Rx2n 114
Rx2p 115
GND 116
Rx3n 117
Rx3p 118
VVDD 119
GND 120
CVDD 121
MON_SEL0 122
MON_SEL1 123
MON_EN 124
Reserved8 125
MON_SEL2 126
MONOUT 127
GND 128

64
63
62
61
60
59
58
57
56
55
54
53
52
51

THCV226

50
49

TQFP 128pin

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
LVDD
GND
RLCLK1nRLCLK1p
RLD1n
RLD1p
LPVDD
GND
RLE1n
RLE1p
RLA2n
RLA2p
LPVDD
GND
RLB2n
RLB2p
RLC2n
RLC2p
LVDD
GND
RLCLK2nRLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p

32 LVDD
31 GND
30 CVDD
29 RLA3n
28 RLA3p
27 RLB3n26 RLB3p
25 GND
24 LVDD
23 RLC3n22 RLC3p
21 RLCLK3n20 RLCLK3p
19 GND
18 LVDD
17 RLD3n
16 RLD3p
15 RLE3n
14 RLE3p
13 GND
12 LVDD
11 PVDD
10 CVDD
9PDN
8Reserved2
7
Reserved1
6
Reserved0
5
MAP
4
RS
3
MON_SEL3
IOVDD
GND

2

1

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PIN Description
PIN Name
Rx0n , Rx0p
Rx1n , Rx1p
Rx2n , Rx2p
Rx3n , Rx3p
RLA0n , RLA0p
RLB0n , RLB0p
RLC0n , RLC0p
RLCLK0n , RLCLK0p
RLD0n , RLD0p
RLE0n , RLE0p
RLA1n , RLA1p
RLB1n , RLB1p
RLC1n , RLC1p
RLCLK1n , RLCLK1p
RLD1n , RLD1p
RLE1n , RLE1p
RLA2n , RLA2p
RLB2n , RLB2p
RLC2n , RLC2p
RLCLK2n , RLCLK2p
RLD2n , RLD2p
RLE2n , RLE2p
RLA3n , RLA3p
RLB3n , RLB3p
RLC3n , RLC3p
RLCLK3n , RLCLK3p
RLD3n , RLD3p
RLE3n , RLE3p
DGLOCKPIN No107, 108
110, 111
114, 115
117, 118
83, 8281, 8077, 7675, 7471, 7069, 6864, 6362, 6160, 5956, 5554, 5350, 4948, 4744, 4342, 4138, 3736, 3534, 3329, 2827, 2623, 2221, 2017, 1615, 14
101

Type
CI
CI
CI
CI
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
BI

HTPDN

102

OD

LOCKN

103

OD

COL

88

I

OPF

89

I

MODE2,1,0OE

92,91,90
99

I
I

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Description
CML Data Input
CML Data Input
CML Data Input
CML Data Input
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
LVDS Data Output
Connect all DGLOCK pins in multiple-chip
configuration.
Must be left OPEN for single-chip configuration
Hot plug detect output
Must be connected to Tx HTPDN with a 10Kpull-up resistor
Lock detect output
Must be connected to Tx LOCKN with a 10Kpull-up resistor
Color depth selectH : 10bit mode
L : 8bit mode
Output Pattern at CDR Fail Condition(LOCKN=L)
H : LVDS output Low data
L : LVDS output Hi-Z data
Input / Output mode select
LVDS Output Enable
H : Normal Operation
L : Output Disable

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THCV226_Rev.1.30_E

PIN Description (Continued)
PIN Name
MON_SEL1,0
MON_SEL3,2
MON_ENPIN No123, 122
3, 126
124

Type
I
I
I

RS

4

I

MAP

5

I

PDN

9

I

MONOUT
Reserved 0,1,2,3,4,5,8

Description
Monitoring Input Lane select (See Table 8)
Monitoring Input Signal select (See Table 8)
Monitoring mode enable
H : Enable
L : Disable
LVDS swing level selectH : Normal swing (350mV)
L : Reduced swing (200mV)
LVDS output format selectH : JEIDA format
L : VESA format
Power down
H : Normal operation
L : Power down operation
Monitoring signal output
Must be tied to GND

127
O6, 7, 8, 93, 94, I
95, 125
Reserved 6,797, 98O
Must be open
CVDD
10, 30, 67, 86, PWR
1.8V power supply for Logic block
104, 121
VVDD
106, 112, 119
PWR
1.8V power supply for V-by-One® HS block
LVDD
12, 18, 24, 32, PWR
1.8V power supply for LVDS block40, 58, 65, 73,
79, 85PVDD
11PWR
1.8V power supply for PLL block
LPVDD
46, 52PWR
1.8V power supply for LVDS analog block
IOVDD
2, 100,PWR
1.8V power supply for LVCMOS I/O buffer
GND
1, 13, 19, 25, GND
Ground31, 39, 45, 51,
57, 66, 72, 78,
84, 87, 96, 105,
109, 113, 116,
120, 128
CI : CML Input buffer , LO : LVDS Output buffer , BI : LVCMOS Bi-directional buffer
I : LVCMOS Input buffer , O : LVCMOS Output buffer , OD : Open Drain buffer
PWR : 1.8V Power supply , GND : Ground

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THCV226_Rev.1.30_E

Functional Description
Functional Overview
With V-by-One® HS’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
THCV226 enables the transmission of 8 or 10-bit video data, 2-bit synchronizing control data of HSYNC,
VSYNC, and Data Enable (DE), by a pair cable with minimal external components.
THCV226 automatically extracts the clock from the incoming data streams and converts the serial data into
video data with DE being high or synchronizing control data with DE being low, recognizing which type ofserial data is being sent by the transmitter. Also, THCV226 outputs the recovered data in the LVDS data format.
THCV226 can operate for a wide range of a serial bit rate from 1.2Gbps to 3.4Gbps. It is unnecessary to use
any external frequency reference, such as a crystal oscillator.

Data Enable Requirement (DE)
There are some requirements for DE signal as described in Figure1 and Figure2.
If DE=Low and MODE0=0, control data of same cycle and particular assigned data bit ‘CTL’ except the firstand last pixel are transmitted. If DE=Low and MODE0=1, control data of same cycle and particular assigned
data bit ‘CTL’ except the first 2cycle and last 2pixel are transmitted. Otherwise video data is transmitted during
DE=High. The length of DE being low and high must be at least 8 clock cycles long, as described in Figure15
and Switching Characteristics. DE must be toggled as High -> Low -> High at regular interval. The length ofparticular DE cycle must be same at all lane.

CTL Bit Transmission
There is particular assigned data bit ‘CTL’ which can be transmitted at blanking period except the first and thelast pixel on DE=Low.
Transmitter
Data bit : R/G/B, CONTTHCV226

1

R/G/B
CONT
CTL

0

VSYNC
HSYNC

Control bit : HSYNC, VSYNC
Data bit : CTL*

DE

DE=1 , R/G/B, CONT
DE=0 , CTL* except the 1st and the last pixel
Other R/G/B, CONT=Invalid.

DE=1 , HSYNC, VSYNC=Fixed
DE=0 , HSYNC, VSYNC

DE

CTL* are particular assigned bits among R/G/B, CONT that can carry arbitrary data during DE=Low period.

Figure 1. Conceptual Diagram of Basic Operation of Chipset

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THCV226_Rev.1.30_E

LVDS Input of Source Device
TLyzp/n

DE=High
Active period

Data : Invalid

DE=Low
Blanking period

Data : Particular assigned bit ‘CTL’ is transmitted except the first andlast pixel of Blanking period.

6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2(LVDS In/put)

TLCp/n

D
D
D
D
D
D
D
D
D
V H 3 2 1 0
V H 3 2 1 0
V H 3 2 1 0
V H 3 2 1 0
V H 3 2 1 0
V H 3 2 1 0
V H 3 2 1 0
V H 3 2 1 0
V H 3 2
E
E
E
E
E
E
E
E
E

(LVDS In/put)

TLCLKp/n(LVDS In/put)

THCV226 LVDS Transmitter Output
RLyzp/n

6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2(LVDS Output)

RLCp/nHi V H(LVDS Output)

3 2 1 0 Hi V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Hi V H 3 2 1 0 Hi V H 3 2

RLCLKp/n(LVDS Output)
y=A,B,D,E
z=0,1,2,3

Figure 2-1.

Timing Diagram of Data and Synchronizing Signals (Normal LVDS mode)

LVDS Input of Source Device
TLyzp/n(LVDS In/put)

TLCp/n(LVDS In/put)

DE=High
Active period

Data : Invalid

DE=Low
Blanking period

Data : Particular assigned bit ‘CTL’ is transmitted except the first andlast pixel of Blanking period.

3

2

1

0

6

5

4

3

2

1

0

6

5

4

3

2

1 4

3

2

1

0

6

5

4

3

2

1

0

6

5

4

3

2

1

0

D
E

V

H

3

2

1

0

D
E

V

H

3

2

1 H

3

2

1

0

D
E

V

H

3

2

1

0

D
E

V

H

TLCLKp/n(LVDS In/put)

THCV226 LVDS Transmitter Output
RLyzp/n(LVDS Output)

RLCp/n(LVDS Output)

6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2

Hi V H3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Hi V H 3 2

RLCLKp/n(LVDS Output)
y=A,B,D,E
z=0,1,2,3

Figure 2-2.

Timing Diagram of Data and Synchronizing Signals (HSLVDS mode)

Color Depth Mode Function
Table 1. Color Depth Mode SelectCOL
10Operation Mode
10-bit R/G/B data (4byte mode for V-by-One® HS Standard)
8-bit R/G/B data (3byte mode for V-by-One® HS Standard)

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THCV226_Rev.1.30_E
Transmission Mode SelectTable 2. Transmission Mode SelectMODE 2, 1, 0
111
110
101
100
011
010
001
000

COL
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

V-by-One HS
40 – 78.5MHz
40 – 78.5MHz
40 – 85MHz
40 – 90MHz
40 – 78.5MHz
40 – 78.5MHz
40 – 85MHz
40 – 90MHz
40 – 78.5MHz
40 – 78.5MHz
40 – 85MHz
40 – 90MHz
40 – 78.5MHz
40 – 78.5MHz
40 – 85MHz
40 – 90MHz

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LVDS
80 – 157MHz
80 – 157MHz
40 – 85MHz
40 – 90MHz
80 – 157MHz
80 – 157MHz
40 – 85MHz
40 – 90MHz
80 – 157MHz
80 – 157MHz
40 – 85MHz
40 – 90MHz
80 – 157MHz
80 – 157MHz
40 – 85MHz
40 – 90MHz

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Operation Mode
HSLVDS / Distribution mode2
Normal LVDS / Distribution mode2
HSLVDS / Distribution mode1
Normal LVDS / Distribution mode1
HSLVDS / Crossing Mode
Normal LVDS / Crossing mode
HSLVDS mode
Normal LVDS mode

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THCV226_Rev.1.30_E

HSLVDS / Distribution mode

Normal LVDS / Distribution mode

MODE2,1,0 = 111

MODE2,1,0 = 110

Rx0n/pRLy0n/p

Rx0n/pRLy0n/p

Rx1n/pRLy1n/p

Rx1n/pRLy1n/p

Rx2n/pRLy2n/p

Rx2n/pRLy2n/p

Rx3n/pRLy3n/p

Rx3n/pRLy3n/p

MODE2,1,0 = 101

MODE2,1,0 = 100

Rx0n/pRLy0n/p

Rx0n/pRLy0n/p

Rx1n/pRLy1n/p

Rx1n/pRLy1n/p

Rx2n/pRLy2n/p

Rx2n/pRLy2n/p

Rx3n/pRLy3n/p

Rx3n/pRLy3n/p

HSLVDS mode

Normal LVDS mode

MODE2,1,0 = 011

MODE2,1,0 = 010

Rx0n/pRLy0n/p

Rx0n/pRLy0n/p

Rx1n/pRLy1n/p

Rx1n/pRLy1n/p

Rx2n/pRLy2n/p

Rx2n/pRLy2n/p

Rx3n/pRLy3n/p

Rx3n/pRLy3n/p

MODE2,1,0 = 001

MODE2,1,0 = 000

Rx0n/pRLy0n/p

Rx0n/pRLy0n/p

Rx1n/pRLy1n/p

Rx1n/pRLy1n/p

Rx2n/pRLy2n/p

Rx2n/pRLy2n/p

Rx3n/pRLy3n/p

Rx3n/pRLy3n/py=A,B,C,CLK,D,E

Figure 3.

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Transmission Mode Select Diagram

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THCV226_Rev.1.30_E
Power Down Mode
Table 3. Power Down Mode
PDN
10

Operation
Normal operation
Power down operation

Hot-plug and Lock Detect Function
HTPDN and LOCKN are both open drain outputs from THCV226. Pull-up resistors must be placed at
V-by-One® HS transmitter side. See Figure.4 and 5.
If THCV226 is not active (power down mode (PDN=0) or powered off), HTPDN is open. Otherwise, HTPDN
is pulled down by THCV226.
HTPDN at V-by-One® HS transmitter side is High when THCV226 is not active or the receiver board is notconnected. Then V-by-One® HS transmitter side enters into the power down mode. When HTPDN transits fromHigh to Low, V-by-One® HS transmitter starts up and transmits training pattern for link training.
LOCKN indicates whether THCV226 is in CDR state or not. If THCV226 is in the CDR unlock state, LOCKN
is open. Otherwise (in the CDR lock state), it is pulled down by THCV226.
V-by-One® HS transmitter side keeps transmitting training pattern until LOCKN transition to Low. After
training is done, THCV226 sinks current, and LOCKN turns to Low. Then V-by-One® HS transmitter side starts
transmitting normal video pattern.
(Tx side)

VDD
PDN

Transmitter

HTPDN

THCV226

HTPDN(Tx side)

LOCKN

Transmitter

LOCKN

HTPDN
DGLOCK

LOCKN

Figure 4.

HTPDN and LOCKN Scheme
VDD
PDN

Transmitter

HTPDN

THCV226

HTPDN(Tx side)

LOCKN

Transmitter

LOCKN

HTPDN
DGLOCK

LOCKN

Figure 5.

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HTPDN and LOCKN Scheme without HTPDN Connection

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THCV226_Rev.1.30_E
Multiple-chip Configuration
In order to reduce the number of cables needed for HTPDN and LOCKN in multiple-chip configuration,
THCV226 is equipped with the DGLOCK pin. When all the DGLOCK pins are connected as in Figure 6 ,the connected Rx chips can share the CDR lock status via DGLOCK, making all the Rx chips in the same
operation status.
(Tx side)

VDD
PDN

Transmitter

HTPDN(Tx side)

LOCKN

Transmitter

THCV226

HTPDN(Rx side)

LOCKN

HTPDN
DGLOCKLOCKN

PDNTransmitter

Transmitter

HTPDN

HTPDN

LOCKN

LOCKN

THCV226HTPDN
DGLOCK

LOCKN

Figure 6.

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Usage of DGLOCK in Multiple-Rx Configuration

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THCV226_Rev.1.30_E
LVDS Reduced Swing Output Function
RS pin controls LVDS output swing level.
Table 4. LVDS Output Level SelectRS01

Output Swing Level
Reduced Swing Level ( 200mV typical )Normal Swing Level ( 350mV typical )LVDS Output Enable Function
By setting the OE and OPF pins, the following output enable function can be selected.
In output disable condition, all the outputs take low fixed data or High-Z except for HTPDN, LOCKN andDGLOCK.
Table 5. LVDS Output Enable Function
LOCKN

OE

OPF

LVDS Outputs
Output Condition
Low Fixed Data
EnableHi-Z
Low Fixed Data
DisableHi-Z
Status

1
0
1
0
1
0
1
0

1
1
0
1
0
0

EnableNormal Data

DisableLow Fixed Data
Hi-Z

LVDS Data Mapping
LVDS data (video data, control data, DE) are mapped as Figure 7. RLC[6] is special bit for DE (data enable).
RLC[5:4] are for control data bits, and the other bits are for video data. Also there are special assigned bits,‘CTL’ transmitted under DE=0 condition.
The number of LVDS channels depends on color depth mode, COL.
RLD[6] is not available at COL=0, 8-bit color depth mode.
Vdiff = 0

(RLCLKzp) – (RLCLKzn)tRCOP
Data width
32 24Previous cycle

Current cycle

Next cycle

RLAzp/nRLAz[1] RLAz[0]RLAz[6]

RLAz[5]RLAz[4]

RLAz[3]RLAz[2]RLAz[1]

RLAz[0]RLAz[6] RLAz[5]RLAz[4]

RLAz[3]RLAz[2]RLAz[1]

RLAz[0]RLBzp/nRLBz[1]RLBz[0]RLBz[6]

RLBz[5]RLBz[4]RLBz[3]

RLBz[2]RLBz[1]RLBz[0]RLBz[6]

RLBz[5]RLBz[4]RLBz[3]

RLBz[2]RLBz[1]RLBz[0]RLCzp/nRLCz[1]

RLCz[0]RLCz[6](DE)

RLCz[5](V)

RLCz[4](H)

RLCz[3]

RLCz[2]

RLCz[1]

RLCz[0]RLCz[6](DE)

RLCz[5](V)

RLCz[4](H)

RLCz[3]

RLCz[2]

RLCz[1]

RLCz[0]RLDzp/nRLDz[1]RLDz[0]RLDz[6]

RLDz[5]RLDz[4] RLDz[3]RLDz[2]RLDz[1]RLDz[0]RLDz[6]

RLDz[5]RLDz[4]RLDz[3]RLDz[2] RLDz[1]RLDz[0]RLEzp/nRLEz[1]RLEz[0]RLEz[6]RLEz[5]RLEz[4]RLEz[2]RLEz[1]RLEz[0]RLEz[6]RLEz[5]RLEz[4]RLEz[3]RLEz[2]RLEz[0]RLEz[3]RLEz[1]z = 0,1,2,3

Data Enable

Control Data Bits

Figure 7. LVDS Output Switching Timing Diagram

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Table 6. LVDS Data Mapping Table for JEIDA Format (MAP=1)
THCV226
OutputRLAz[0]RLAz[1]
RLAz[2]RLAz[3]RLAz[4]
RLAz[5]RLAz[6]
RLBz[0]RLBz[1]RLBz[2]RLBz[3]
RLBz[4]RLBz[5]RLBz[6]
RLCz[0]RLCz[1]
RLCz[2]
RLCz[3]
RLCz[4]
RLCz[5]
RLCz[6]
RLDz[0]RLDz[1]RLDz[2]RLDz[3]RLDz[4]RLDz[5]RLDz[6]RLEz[0]RLEz[1]RLEz[2]RLEz[3]RLEz[4]RLEz[5]RLEz[6]COL
0 (8bit)
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[2]*2
B[3]*2
B[4]*2
B[5]*2
B[6]*2
B[7]*2
HSYNC
VSYNC
DE
R[0]
R[1]
G[0]
G[1]
B[0]*2
B[1]*2
N/A*1

ChannelPower
Down

Comment

1 (10bit)
R[4]
R[5]
R[6]
R[7]
R[8]
R[9]
G[4]
G[5]
G[6]
G[7]
G[8]
G[9]
B[4]*2
B[5]*2
B[6]*2
B[7]*2
B[8]*2
B[9]*2
HSYNC
VSYNC
DE
R[2]
R[3]
G[2]
G[3]
B[2]*2
B[3]*2
CONT[1]*2*3
R[0]*2
R[1]*2
G[0]*2
G[1]*2
B[0]*2
B[1]*2
CONT[2]*2*3

Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Control bit
Control bit
Data Enable*2
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Table 1.

*1 N/A : Not available. THCV226 outputs RLDz[6]=0*2 CTL bits, which are carried during DE=0 expect the 1st and the last pixel.(If MODE0=0)
Which are carried during DE=0 except the 1st, 2nd and last 2pixel.(IF MODE0=1)*3 3D flags defined in the V-by-One® HS Standard are assigned to the following bits.
V-by-One® HS Standard Packer/Unpacker D[24](3DLR)  LVDS RLEz[6].
V-by-One® HS Standard Packer/Unpacker D[25](3DEN)  LVDS RLDz[6].
( z=0,1,2,3)

Copyright©2023 THine Electronics, Inc.

12/25

THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E
Table 7. LVDS Data Mapping Table for VESA Format (MAP=0)
THCV226
COL
Comment
Output0 (8bit)
1 (10bit)
RLAz[0]R[0]R[0]*2
Data bit
RLAz[1]R[1]R[1]*2
Data bit
RLAz[2]R[2]R[2]Data bit
RLAz[3]R[3]R[3]Data bit
RLAz[4]R[4]R[4]Data bit
RLAz[5]R[5]R[5]Data bit
RLAz[6]
G[0]G[0]*2
Data bit
RLBz[0]G[1]G[1]*2
Data bit
RLBz[1]G[2]G[2]Data bit
RLBz[2]G[3]G[3]Data bit
RLBz[3]G[4]G[4]Data bit
RLBz[4]G[5]G[5]Data bit
RLBz[5]
B[0]*2
B[0]*2
Data bit
RLBz[6]
B[1]*2
B[1]*2
Data bit
RLCz[0]B[2]*2
B[2]*2
Data bit
RLCz[1]
B[3]*2
B[3]*2
Data bit
RLCz[2]
B[4]*2
B[4]*2
Data bit
RLCz[3]
B[5]*2
B[5]*2
Data bit
RLCz[4]HSYNC
HSYNC
Control bit
RLCz[5]VSYNC
VSYNC
Control bit
RLCz[6]DEDE
Data Enable*2
RLDz[0]R[6]R[6]Data bit
RLDz[1]R[7]R[7]Data bit
RLDz[2]G[6]G[6]Data bit
RLDz[3]G[7]G[7]Data bit
RLDz[4]
B[6]*2
B[6]*2
Data bit
RLDz[5]
B[7]*2
B[7]*2
Data bit
RLDz[6]
N/A*1
CONT[1]*2*3
Data bit
RLEz[0]R[8]Data bit
RLEz[1]R[9]Data bit
ChannelRLEz[2]G[8]Data bitPower
RLEz[3]G[9]Data bit
Down
RLEz[4]
B[8]*2
Data bit
RLEz[5]
B[9]*2
Data bit
RLEz[6]
CONT[2]*2*3
Data bit*1 N/A : Not available. THCV226 outputs RLDz[6]=0*2 CTL bits, which are carried during DE=0 expect the 1st and the last pixel.(If MODE0=0)
Which are carried during DE=0 except the 1st, 2nd and last 2pixel.(IF MODE0=1)*3 3D flags defined in the V-by-One® HS Standard are assigned to the following bits.
V-by-One® HS Standard Packer/Unpacker D[24](3DLR)  LVDS RLEz[6].
V-by-One® HS Standard Packer/Unpacker D[25](3DEN)  LVDS RLDz[6].
( z=0,1,2,3)

Copyright©2023 THine Electronics, Inc.

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THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

Monitoring Signal Function
The recovered HSYNC, VSYNC, DE or CLK from V-by-One® HS signals can be monitored by “Monitoring
Signal Function”. The monitoring lane out of four high-speed data lane is selectable. This function is used fordebugging purpose and set by five pins, MON_EN, MON SEL0/1/2/3.
The monitoring signal is outputted from MONOUT pin as 1.8V LVCMOS signal.
All signals operate as normal mode except these setting pins and monitoring output pin when “Monitoring
Signal Function” is enabled. See the table below.
Table 8. Monitoring Signal Function
Function
MON_EN
01

Pin Option
Lane Selection
Signal Selection
MON_SEL0 MON_SEL1 MON_SEL2 MON_SEL3
0
0
0
0
0
0
0
1
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
0
0
0
1
0
1
1
0
1
1
0
0
0
1
1
1
1
0
1
1

Copyright©2023 THine Electronics, Inc.

14/25

Monitoring
OutputMONOUT(Invalid)
DE
HSYNC
VSYNC
CLK
DE
HSYNC
VSYNC
CLK
DE
HSYNC
VSYNC
CLK
DE
HSYNC
VSYNC
CLK

Description
Normal mode
Monitoring Signal
Mode toCheck Lane0
Monitoring Signal
Mode toCheck Lane1
Monitoring Signal
Mode toCheck Lane2
Monitoring Signal
Mode toCheck Lane3

THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

Absolute Maximum Ratings
Parameter
Supply Voltage(VVDD,LVDD,LPVDD,PVDD,CVDD,IOVDD)CMOS Input Voltage
CMOS Output Voltage
Open Drain Output Voltage
CML Receiver Input Voltage
LVDS Transmitter Output Voltage
Output Current
Storage temperature
Junction temperature
Reflow Peak Temperature/Time
Maximum Power Dissipation @+25deg

Min

Typ

Max

Unit

-0.3

-

2.1

V

-0.3
-0.3
-0.3
-0.3
-0.3
-50
-55
-

-

IOVDD+0.3
IOVDD+0.3
3.6
VVDD+0.3
LVDD+0.350
125125
260/10
2.5

V
V
V
V
V
mA
C
C
C/sec
W

Min

Typ

Max

Unit

1.62

1.80

1.98

V

-40

-

85

C

Min
-

Typ*
450
360
420
295
370
300
345
245
-

Max
515
415
475
335
440
355
405
285
1

Unit

Recommended Operating Conditions
SymbolVDDTaParameter
Supply Voltage(VVDD,LVDD,LPVDD,PVDD,CVDD,IOVDD)
Operating Temperature

Supply Current
SymbolParameter
Power Supply Current(Worst case pattern)
10bit mode

IRCCW
Power Supply Current(Gray scale pattern)
10bit mode
IRCCS Power Down Supply Current* VDD=1.8V, Room temperature

Copyright©2023 THine Electronics, Inc.

Conditions
MODE2,1,0=111
MODE2,1,0=001
MODE2,1,0=000
MODE2,1,0=100
MODE2,1,0=111
MODE2,1,0=001
MODE2,1,0=000
MODE2,1,0=100
PDN = 015/25

THine Electronics, Inc.

SC: E

mA

mA

THCV226_Rev.1.30_E

Electrical Specifications
Symbol Parameter
LVCMOS DC Specifications
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
High Level Output Voltage
VOH( IO Type : O )Low Level Output Voltage( IO Type : O,OD )VOL
Low Level Output Voltage( IO Type : BI )Output Leak Current High in
IOZH
Hi-Z State
Output Leak Current Low in
IOZL
Hi-Z State
High Level Input Leakage
IIH
Current
Low Level Input Leakage
IIL
Current
CML DC Specifications
CML Differential Input High
VRTH
Threshold
CML Differential Input Low
VRTL
Threshold
CML Input High Leak
IRIH
Current
CML Input Low Leak
IRIL
Current
IRRIH CML Input High Current
IRRIL CML Input Low Current
CML Differential Input
RRIN
Resistance
CML Differential Input High
VRTH
Threshold
LVDS DC Specifications
LVDS Differential Mode
Output Voltage
VROD
LVDS Differential Mode
Output Voltage
ROD Change in VROD between
Complementary Output States
LVDS Common Mode Output
VROC
Voltage
ROC Change in VROD between
Complementary Output States
LVDS Output Short Circuit
IROS Current

IROZ

LVDS Output Tri-State
Current

Condition

Min

Typ

Max

Unit

-

0.65VDD-0.3-

VDD+0.3
0.35VDDV
V

IOH = -2mA

VDD-0.2-

VDD

V

IOL = 2mA

GND

-

0.2

V

IOL = 160uA

GND

-

0.2

V

-

-10

-

10

uA

-

-10

-

10

uA

-

-10

-

10

uA

-

-10

-

10

uA

-

-

-

50

mV

-

-50

-

-

mV

-10

-

10

uA

-10

-

10

uA

-6

-

2
-

mA
mA

-

80

100

120



-

-

-

50

mV

250

350

450

mV

100

200

300

mV

-

-

35

mV

1.125

1.25

1.375

V

-

-

35

mV

-

-

100

mA

-20

-

20

uA

PDN=0,
Rxzp/n=VDD
PDN=0
Rxzp/n=GND
Rxzp/n=VDD
Rxzp/n=GND

RL = 100
RS = 1
RL = 100
RS = 0
RL = 100
RL = 100
RL = 100
RLyzp/n=GND
RL = 100
PDN = 0RLyzp/n=GND VDD*y=A,B,C,CLK,D,E / z=0,1,2,3
Copyright©2023 THine Electronics, Inc.

16/25

THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

Switching Characteristics
Symbol Parameter
CML AC Specifications
Unit Interval (UI)tRBITCML Lane0/1/2/3 Input Inter
Pair Skew Margin
CML Lane0/1/2/3 Input JittertRIJT
Margin
LVDS AC Specifications
tRCOP Clock Out Period
LVDS Differential OutputtRLVT
Transition Time
tROP1 LVDS Output Data Position0
LVDS Output Data Position1
tROP0
tRISK

tROP6
tROP5
tROP4
tROP3
tROP2
tROP1
tROP0
tROP6
tROP5
tROP4
tROP3
tROP2
tROSK

LVDS Output Data Position2

Condition

Min

Typ

Max

Unit

COL = 0
COL = 1
COL = 0
COL = 1
COL = 0
COL = 1

370
294
-30
-40
-

tRCOP/30
tRCOP/40
-

833
625
30
40
15
20

ps
ps
UI
UI
UI
UI

-

6.37

-

25

ns

-

-

0.6

1.5

ns

-0.20
tRCOP/7-0.20
2tRCOP/7-0.20
3tRCOP/7-0.20
4tRCOP/7-0.20
5tRCOP/7-0.20
6tRCOP/7
-0.20
-0.25
tRCOP/7-0.25
2tRCOP/7-0.25
3tRCOP/7-0.25
4tRCOP/7-0.25
5tRCOP/7-0.25
6tRCOP/7
-0.25

-

0.20
tRCOP/7+0.20
2tRCOP/7+0.20
3tRCOP/7+0.20
4tRCOP/7+0.20
5tRCOP/7+0.20
6tRCOP/7+0.20
0.25
tRCOP/7+0.25
2tRCOP/7+0.25
3tRCOP/7+0.25
4tRCOP/7+0.25
5tRCOP/7+0.25
6tRCOP/7
+0.25

ns

500

ps

HSLVDS
mode(tRCOP=
6.37ns – 8.33ns)

LVDS Output Data Position3
LVDS Output Data Position4
LVDS Output Data Position5
LVDS Output Data Position6
LVDS Output Data Position0
LVDS Output Data Position1

Normal LVDS
mode

LVDS Output Data Position2(tRCOP=
11.1ns -16.6ns)

LVDS Output Data Position3
LVDS Output Data Position4
LVDS Output Data Position5
LVDS Output Data Position6
Link0/1/2/3 LVDS Output
Clock Skew

Copyright©2023 THine Electronics, Inc.

-

-

17/25

tRCOP/7
2tRCOP/7
3tRCOP/7
4tRCOP/7
5tRCOP/7
6tRCOP/7
tRCOP/7
2tRCOP/7
3tRCOP/7
4tRCOP/7
5tRCOP/7
6tRCOP/7
-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

Switching Characteristics (Continued)
Symbol Parameter
Delay time
Input Data to Output Data
Delay
tRDC

Power On to PDN HighDelay
PDN High to HTPDN Low
tRHPD0Delay
PDN Low to HTPDN HightRHPD1
Delay
Training Pattern Input totRPLL0LOCKN Low Delay
PDN Low to LOCKN HightRPLL1Delay
LOCKN Low to LVDS CLKtRPLL2
Lock TimeLOCKN Low to LVDStRLCK0
Output Delay
LOCKN High to LVDStRLCK1
Output High-Z/Low Delay
DGLOCK High to LOCKN
tRDLH
Low
DGLOCK Low to LOCKN
tRDLL
High
DE Input Timing
DE=1 Duration
tRDEH
tRPD

tRDEL

DE=0 Duration

Copyright©2023 THine Electronics, Inc.

ConditionMin

MODE0 = 0
COL = 0
MODE0 = 1
COL = 0
MODE0 = 0
COL = 1
MODE0 = 1
COL = 1

(17+27/30)
tRCOP+4.5(34+24/30)
tRCOP+5.0(17+7/40)
tRCOP+4.5(33+14/40)
tRCOP+5.0

Typ
-

Max
(17+27/30)
tRCOP+13.5(34+24/30)
tRCOP+15.5(17+7/40)
tRCOP+13.5(33+14/40)
tRCOP+15.5

Unit

ns

ns

-

0

-

-

ns

-

-

-

1

us

-

-

-

1

us

-

-

-

10

ms

-

-

-

10

us

-

-

-

10

ms

-

-

-

1

ms

-

-

-

1

ms

-

0

-

-

ns

-

0

-

-

ns

8tRCOP
16tRCOP
8tRCOP
16tRCOP

-

-

ns
ns
ns
ns

MODE0 = 0
MODE0 = 1
MODE0 = 0
MODE0 = 1

18/25

THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

AC Timing Diagram and Test Circuit(Tx side)(Tx side)

50

C=75
200nF

50
Txzp

Txzn

C=75
200nF Rxzp

Rxzn

Zo=50

50

z=0,1,2,3

50

Vterm = 1.3V(typ)CML Transmitter

CML Receiver (THCV226)

Figure 8.

CML Buffer Scheme

Vdiff = (Rx0p) – (Rx0n)

tRBIT
(1UI)

Vdiff = 0

-tRISK

Vdiff = (Rx1p) – (Rx1n)

Vdiff = 0tRIJT+tRISK

Vdiff = (Rx2p) – (Rx2n)

Vdiff = 0

+tRISK

Vdiff = (Rx3p) – (Rx3n)

Vdiff = 0

Figure 9.

CML Input Timing Diagram

RLyzp
RL=100CL=5pF
RLyzn
80%

Vdiff = (RLyzp) – (RLyzn)
y=A,B,C,CLK,D,E
z=0,1,2,3

20%

tRLVT

Figure 10.

Copyright©2023 THine Electronics, Inc.

tRLVTLVDS Output Switching Timing Diagram and Test Circuit

19/25

THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

tROP2
tROP3
tROP4
tROP5
tROP6
tROP0
tROP1
Vdiff = (RLyzp) – (RLyzn)

RLyz5 RLyz4 RLyz3 RLyz2 RLyz1 RLyz0 RLyz6 RLyz5 RLyz4 RLyz3 RLyz2 RLyz1 RLyz0

Vdiff = (RLCLKzp) – (RLCLKzn)

Vdiff = 0y = A,B,C,D,E
z = 0,1,2,3

tRCOP
Figure 11.

LVDS Output Switching Timing Diagram

Vdiff = (RLCLKzp) – (RLCLKzn)

Vdiff = 0tROSKVdiff = (RLCLKzp) – (RLCLKzn)
z = 0,1,2,3

Figure 12.

Vdiff = 0

LVDS Output Switching Timing Diagram

Pixel 1st bit

Vdiff = (Rxzp) – (Rxzn)
Vdiff = 0

Vdiff = (RLCLKzp) – (RLCLKzn)

tRDC

z = 0,1,2,3

Previous cycle

Current cycle

Figure 13. V-by-One® HS Input to LVDS Output Latency

Copyright©2023 THine Electronics, Inc.

20/25

THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

VDD
tRPD
PDN
tRHPD0tRHPD1HTPDN
Training
PatternRxzp/N

Training
Pattern

NormalPattern

NormalPattern

Training
PatterntRPLL1tRPLL0
LOCKN
tRDLH

tRDLL

DGLOCKtRPLL2
RLCLKzp/n

Hi-Z

Invalid
Clock

Hi-Z

Invalid
Pattern

OPF=0tRLCK1
Invalid
Clock

Hi-Z

Invalid
Clock

Invalid
Pattern

Hi-Z

Invalid
PatternHi-Z

tRLCK0RLyzp/n
OPF=0

Valid
Pattern

Valid
Pattern

Hi-Z

VDD
tRPD
PDN
tRHPD0tRHPD1HTPDN
Training
Pattern

Rxz/p/nNormalPattern

Training
Pattern

NormalPattern

Training
PatterntRPLL1tRPLL0
LOCKN
tRDLH

tRDLL

DGLOCKtRPLL2
RLCLKzp/n
OPF=1

tRLCK1

Invalid
Clock

Invalid
Clock

Low
Pattern

Invalid
Clock

Invalid
Pattern

Low
Pattern

Invalid
Pattern

Hi-Z

Invalid
Clock

Hi-Z

Invalid
PatterntRLCK0RLyzp/n
OPF=1
y = A,B,C,D,E
z = 0,1,2,3

Invalid
Pattern

Valid
Pattern

Figure 14.

Valid
Pattern

THCV226 Lock/Unlock Sequence

Vdiff = (RLCLKzp)-(RLCLKzn)
DE

DE

DE

DE

DE

DE

Vdiff = (RLCzp)-(RLCzn)
Z = 0,1,2,3

tRDEH

tRDEL

Figure 15. DE Period Requirement

Copyright©2023 THine Electronics, Inc.

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SC: E

THCV226_Rev.1.30_E

Note1) LVDS Output Pin Connection
In case that the LVDS Rx of destination device is equipped with pull-up resistors connected to higher than
THCV226’s VDD voltage, this can cause violation of absolute maximum ratings to THCV226. Thisphenomenon may be happened at power-on phase and Hi-Z state of the whole system including LVDS Rx
device.
One solution for this problem is power-down control for LVDS Rx device during no LVDS input or Hi-Z state
period, if its pull-up resistors can be cut off at power-down state. Another solution is to set THCV226’s OPF
option pin to VDD. This setting provides low fixed data output mode at PDN=1, not Hi-Z state mode.
HVDD(3.3V)

LVDS Receiver

LVDD(1.8V)!

LVDS
Buffer

1.8V thin transistor

2) Cable Connection and Disconnection
Do not connect and disconnect the LVDS and CML cables, when the power is supplied to the system.
3) GND Connection
Connect the each GND of the PCB which Transmitter and Receiver. It is better for EMI reduction to place
GND cables as close to LVDS and CML cables as possible.
4) Multi-drop Connect
Multi-drop connect is not recommended.

THCV226

LVDS Rx

LVDS Rx

5) Multiple Counterpart Use
Multiple counterpart use such as the following system is not recommended. If it is not avoidable, please check
whether tRISK and tRIJT spec of THCV226 can be kept or not. Furthermore, please contact toTx0n/p

CLKOUT
DATA
IC

V-by-One® HS Tx

Copyright©2023 THine Electronics, Inc.

!

Tx2n/p

CLKOUT
DATA

Tx1n/pV-by-One® HS Tx

22/25

THCV226

Tx3n/pTHine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E
6) Multiple Device Connection
HTPDN and LOCKN signals are supposed to be connected properly for their purpose like the following figure.
HTPDN should be from just one THCV226 to multiple Tx devices because its purpose is only ignition of all Tx
devices. LOCKN should be connected so as to indicate that CDR status of all Rx devices becomes ready toreceive normal operation data. LOCKN of Tx side can be simply split to multiple Tx devices. THCV226’s
DGLOCK is appropriate for multiple Rx use.
Also possible time difference of internal processing time (THCV226 tRDC) on multiple data stream must be
accommodated and compensated by the following destination device connected to multiple THCV226s, which
may have internal FIFO.

SourceDevice

THCV226

clkout.1

HTPDN

HTPDN

clkout.2

LOCKN

LOCKN

clkout.3

DGLOCK

clkout.4

FIFO

clkin
Time diff. comes up

THCV226

clkout.1

HTPDN

clkout.2

LOCKN

clkout.3

DGLOCK

clkout.4

Destination
DeviceFIFOInternal processing time tRDC

clkin.1

SourceDevice 1

THCV226

clkout.1

HTPDN

HTPDN

clkout.2

LOCKN

LOCKN

clkout.3

DGLOCK

clkout.4

Ex. synchronizedclkin.2

Time diff. comes up

SourceDevice 2

THCV226

clkout.1

HTPDN

HTPDN

clkout.2

LOCKN

LOCKN

clkout.3

DGLOCK

clkout.4

FIFO

Destination
DeviceFIFOInternal processing time tRDC

Copyright©2023 THine Electronics, Inc.

23/25

THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

Package

97

65

64

128

33

16.00
14.00

98

1

32

16.00
14.00
0.40 +0.05
0.18 +0.05

0.08MAX

1.20 MAX
1.00 +0.05
0.05 0.15
0.25TYP
0 7

0.45 0.75
1.00TYP

Unit : mm

Detail of Lead End

Copyright©2023 THine Electronics, Inc.

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THine Electronics, Inc.

SC: E

THCV226_Rev.1.30_E

Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

Copyright©2023 THine Electronics, Inc.

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THine Electronics, Inc.

SC: E