THAN0196_Rev.1.30_E

Application Note

THAN0196_Rev.1.30_E

THCV231(-Q)/THCV236(-Q) Application Note
System Diagram, Register Setting and PCB Design Guideline

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Contents
Contents.................................................................................................................................................................. 2
Application Diagram ............................................................................................................................................. 3
RAW12bit per pixel falling edge system ........................................................................................................................... 3
YCbCr8bit bus-width rising edge system ......................................................................................................................... 4

Signaling Usage ...................................................................................................................................................... 5
Example Connection 1: Sharing Power Supply ............................................................................................................... 5

Sub-Link Communication .................................................................................................................................... 6
Sub-Link Notification ........................................................................................................................................................ 6
Example Operation 1-1: Access to Sub-Link Master Device Register ........................................................................... 7
Example Operation 1-2: Access to Sub-Link Slave Device Register .............................................................................. 9
Example Operation 1-3: Access to 2-wire serial Slave Device with 8bit Register Address ......................................... 12
Example Operation 1-4: Access to 2-wire serial Slave Device with 16bit Register Address ....................................... 14
Example Operation 2-1: Through GPIO Sub-Link Master to Sub-Link Slave .......................................................... 16
Example Operation 2-2: Programmable GPIO output control .................................................................................... 17
Example Operation 2-3: Programmable GPIO input control ...................................................................................... 18
Example Operation 3-1: Interrupt feedback as internal factor.................................................................................... 19
Example Operation 3-2: Interrupt output as external factor by Slave side ................................................................ 20

Power Supply Usage ............................................................................................................................................ 21
Power Supply for THCV231(-Q)..................................................................................................................................... 21
Power Supply for THCV236(-Q)..................................................................................................................................... 22
PCB layout guideline between VDD (41Pin) and AVDD (40Pin) for THCV236(-Q)................................................... 23

Note ....................................................................................................................................................................... 24
1)Power On Sequence .............................................................................................................................................. 24

2)

Cable Connection and Disconnection ................................................................................................................. 24

3)

GND Connection................................................................................................................................................... 24

4)

Low Input Pulse into PDN, PDN1 and PDN0 Period Requirement ................................................................. 24

PCB Layout Considerations ............................................................................................................................... 25
Notices and Requests ........................................................................................................................................... 26

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Application Diagram
RAW12bit per pixel falling edge system
GPIO4 and GPIO3 input to the THCV236(-Q) are output from the THCV231(-Q) by through GPIO function inorder to send camera reset signal etc.
Set RF pin Low (Falling edge LVCMOS input).
BET, BETOUT and LATEN pins can be used as Bit Error Test in actual configuration in order for debug or test
purpose.
[THCV231(-Q)]
PDN can be controlled by external resistor or other driving source like MCU.
Unused LVCMOS inputs pins should be connected to Low (GND).
[THCV236(-Q)]
Set RXDEFSEL pin Low. Default setting is Sync Free Mode for the THCV231(-Q). Sync Free Mode issuitable to transmitting data of the system without DE sync signal like camera. PDN0 and OE can be controlled
by external resistor or other driving source like MCU.
Unused LVCMOS output pins should be left Open. Place 10Ω resistor close to outputs, which can beeliminated when freq. is low and trace is short.
LVCMOS
Driver10kΩ

TxGPIO4

RAW11-RAW4

THCV231(-Q)
Sub-Link
Slave side

THCV236(-Q)
Sub-Link
Master side

D7-D0
RAW3-RAW0

10kΩ

HTPDN/SUBMODE

D11-D8

D23-D12

NC

D31-D26

RxBETset

H/VSYNCLOCKN/MSSELTxGPIO4
CAM_RESET

TXN

RXN

PDN0

TXP

RXP

BET

0.1uF

GPIO4

0.1uF

OE
TTLDRV/SD2/AIN0/GPIO1
D25/GPIO4
D24/GPIO3

SDL
SDA

TCMN

0.1uF

OUTSEL/SD1
COL1/SD0

1kΩ

10uF

10uF

0.1uF

0.1uF

CAPOUT

NC

0Ω

PDN1
RXDEFSELCAPINA

10kΩ

RxGPIO4
10kΩ

RxSCL

10kΩ

RxSDA

To MPU (Host Device)
1kΩ

NC

CAPINP

RF/BETOUT

TEST1

TEST1

TEST2

TEST2

10kΩ
RESET_fromAP

When GPIO
set input, push
pull output or
unused, there
pull upresistors must
be dispensed
with.

LFSEL

0.1uF

NC

RESET_fromAP

COL0/INT/GPIO2CAPOUT

CAPINA
RF/BETOUT

NC

10kΩ

HFSEL/RCMP

0.1uF

TxPDWN

1kΩ

OEset

RxGPIO4

MAINMODE/RCMN

TCMP

To 2-wire serial
Slave Device

RxPDWNRxBETset
OEset

LATEN/SD3/AIN1/GPIO0

GPIO3

10kΩ
10kΩ

0Ω

DE
CLKOUT

CLKIN

PDN

NC

CAM3-CAM0

D11-D8

H/VSYNC

TxPDWN1kΩ

RxPDWNCAM11-CAM4

D7-D0

CAM_RESET

When GPIO
set input, push
pull output or
unused, there
pull upresistors must
be dispensed
with.

Damping resistor
ex. 10Ω
LVCMOS
Close toReceiver
THCV236(-Q)

0Ω*1indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB*3 Field BET Operation. Please see the datasheet for details. (THCV231(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)

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YCbCr8bit bus-width rising edge system
GPIO4 and GPIO3 input to the THCV236(-Q) are output from the THCV231(-Q) by through GPIO function inorder to send camera reset signal etc.
Set RF pin High (Rising edge LVCMOS input).
BET, BETOUT and LATEN pins can be used as Bit Error Test in actual configuration in order for debug or test
purpose.
Note: This case of transmit 8bit or below, CML bit rate can be slowed if set COL1 (Register Name: refer topage 7 and page 9) to 1 and set COL0 to 0.
[THCV231(-Q)]
PDN can be controlled by external resistor or other driving source like MCU.
Unused LVCMOS inputs pins should be connected to Low (GND).
[THCV236(-Q)]
Set RXDEFSEL pin Low. Default setting is Sync Free Mode for the THCV231(-Q). Sync Free Mode is alsoavailable to transmitting data of embedded sync system without a separate sync signal (ITU656 etc.). PDN0 andOE can be controlled by external resistor or other driving source like MCU.
Unused LVCMOS output pins should be left Open. Place 10Ω resistor close to outputs, which can beeliminated when freq. is low and trace is short.
LVCMOS
Driver10kΩ

TxGPIO4
10kΩ

THCV231(-Q)
Sub-Link
Slave side

Damping resistor
ex. 10Ω
LVCMOS
Close toReceiver
THCV236(-Q)

THCV236(-Q)
Sub-Link
Master side1kΩRxPDWN
NC

D7-D0

D7-D0

D11-D8HTPDN/SUBMODE
D23-D8NC

D31-D26

TxGPIO3

H/VSYNC

H/VSYNC

When GPIO
set input, push
pull output or
unused, there
pull upresistors must
be dispensed
with.

LOCKN/MSSELTxGPIO4TxGPIO3

PDN

TXN

RXN

PDN0

TXP

RXP

BET

0.1uF

GPIO4

0.1uF

OE

GPIO3

TTLDRV/SD2/AIN0/GPIO1
D25/GPIO4
D24/GPIO3

SDL
SDA

0.1uF

OUTSEL/SD1
COL1/SD0

1kΩ

10uF

10uF

0.1uF

0.1uF

RxGPIO4
10kΩ

RxSCL

10kΩ

RxSDA

To MPU (Host Device)
1kΩ

1kΩ

RF/BETOUT

CAPINP

TEST1

TEST1

TEST2

TEST2

10kΩ

RxGPIO3
When GPIO
set input, push
pull output or
unused, there
pull upresistors must
be dispensed
with.

LFSEL

0.1uF
RF/BETOUTNC

PDN1
RXDEFSELCAPINA

CAPINA
1kΩ

10kΩ

COL0/INT/GPIO2CAPOUTCAPOUT

NC

NC

10kΩ

HFSEL/RCMP

0.1uF

TxPDWN

1kΩ

OEset

RxGPIO4
RxGPIO3

MAINMODE/RCMN

TCMN
TCMP

To 2-wire serial
Slave Device

RxPDWNRxBETset
OEset

LATEN/SD3/AIN1/GPIO0

10kΩ
10kΩ

0Ω

DE
CLKOUT

CLKIN

TxPDWNRxBETsetNC*1
indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB*3 Field BET Operation. Please see the datasheet for details. (THCV231(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)

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Signaling Usage
Example Connection 1: Sharing Power Supply
Power supply on common trace is also accomplished by another simple PCB circuit. Put 1uH inductor on bothside. Inductor SRF (Self-resonant frequency) should be more than 160MHz. Inductor supply current tolerance
must be more than requirement (ex. 500mA).
The THCV236(-Q) side AC coupling capacitors must be 100pF.

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Sub-Link Communication
Sub-Link Notification
All of Sub-Link specifications are on the premise that Sub-Link transmission is established because Sub-Link
continues the polling operation even if there are no data accesses.
Please keep below conditions.
1.
Sub-Link I/O is connected between the THCV231(-Q) and THCV236(-Q).
2.
The THCV231(-Q) is powered on and PDN=1, the THCV236(-Q) is powered on and PDN1=1.
In order to incoming data transmit with the THCV231(-Q) and THCV236(-Q), Sub-Link must be continued
communication.
The THCV231(-Q) is set Sub-Link Slave side at all times, and the THCV236(-Q) is set Sub-Link Master side at
all times.
THCV236(-Q)
Sub-Link Master

THCV231(-Q)
Sub-Link Slave
Main-Link
Block

Main-Link
Block

Sub-Link Block

Host

SCL
SDA
INT

2-wire serial
Slave

Sub-Link Block

Sub-Link
MasterCopyright© 2016 THine Electronics, Inc.

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Sub-Link
Slave

2-wire serial
MasterSCL
SDA

2-wire serial
Slave Device

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Example Operation 1-1: Access to Sub-Link Master Device Register
Writing BET to Sub-Link Master Device Register.

SCL
SDA
INT

HOST

SUBMODE=0

THCV236(-Q) : Sub-Link Master Device

THCV231(-Q) : Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

InternalBus

Ex. AIN0=1, AIN1=0→Device ID: 7'h34

2-wire serial
Slave Device

InternalBus
Sub-Link Master side Register

MSSEL
=0

SCL
SDA

2-wire serial
Master

Sub-Link Slave side Register

Step

Address

Bits

W/R

Value

Step

Address

Bits

W/R

Value

1

0x53

1

W

1

1

-

-

-

-

1. Write bit[1] of 0x53 in Sub-Link Master Device Register.
0 = Normal Mode (Default)
1 = Field BET Operation
Note: Sub-Link Master Register can set by 0x00-0x7F.
S

7'h34

W

A

8'h53

A

6'h00

1

0

A

P

8'h02

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Reading 2WIRE_DATA0 on Sub-Link Master Register.

1. Read 0x10 of Sub-Link Master Device Register.
Bit[7:0] 2-wire serial I/F Write/Read Data #0
Note: Sub-Link Master Register can set by 0x00-0x7F.

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Example Operation 1-2: Access to Sub-Link Slave Device Register
Writing BET to Sub-Link Slave Device.

HOST

SCL
SDA
INT
Step 7
INT: H→L
SUBMODE
=0
MSSEL
=0

Ex. AIN0=1, AIN1=0→Device ID: 7'h34

THCV236(-Q) : Sub-Link Master Device

THCV231(-Q) : Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

SCL
SDA

2-wire serial
MasterInternalBus

2-wire serial
Slave Device

InternalBus
Sub-Link Master side Register

Sub-Link Slave side Register

Step

Address

Bits

W/R

Value

Step

Address

Bits

W/R

Value

1

0x02

7

W

*

1

-

-

-

-

2

0x10

1

W

1

2

-

-

-

-

3

0x20

6:0

W

0x34

3

-

-

-

-

4

0x21

3:0

W

0x0

4

-

-

-

-

5

0x23

7:0

W

0xD3

5

-

-

-

-

6

0x25

0

W

1

6

0xD3

1

W

1

7

0x02

7

R

1

7

-

-

-

-

1. Write any value to bit[7] of 0x02 for clear access status register. This bit is into 0 after any write action.
S

7'h34

W

A

8'h02

A

1

7'h00

A

P

8'h80

2. Set 1 to bit[1] of 0x10 for BET change.
0 = Normal Mode (Default)
1 = Field BET Operation

3. Set target Device ID (0x34) to bit[6:0] of 0x20.

4. Set 0x00 to bit[3:0] of 0x21 for the amount of data byte intended to be sent.
Note 1: The actual number of sent byte is register value +1.
Note 2: The maximum data size is 16byte.

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5. Set start address (0xD3) to bit[7:0] of 0x23.

6. Write 1 to bit[0] of 0x25 to start write access to Sub-Link Slave register.

7. When write access is complete, bit[7] of 0x02 value becomes “1” and INT pin H→L. HOST MPU thenreceives interruption read access status register, confirming that write access is complete. If normally ended,
the read result should be 0x80.

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Reading FMOD on Sub-Link Slave Register.

HOST

SCL
SDA
INT
Step 6
INT: H→L
SUBMODE
=0
MSSEL
=0

Ex. AIN0=1, AIN1=0→Device ID: 7'h34

THCV236(-Q) : Sub-Link Master Device

THCV231(-Q) : Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

2-wire serial
MasterInternal
Bus

SCL
SDA
2-wire serial
Slave Device

InternalBus
Sub-Link Master side Register

Sub-Link Slave side Register

Step

Address

Bits

W/R

Value

Step

Address

Bits

W/R

Value

1

0x02

7

W

*

1

-

-

-

-

2

0x20

6:0

W

0x34

2

-

-

-

-

3

0x22

3:0

W

0x0

3

-

-

-

-

4

0x24

7:0

W

0xD2

4

-

-

-

-

5

0x26

0

W

1

5

-

-

-

-

6

0x02

7

R

1

6

0xD2

3:0

R

0x3

7

0x10

3:0

R

0x3

7

-

-

-

-

1. Write any value to bit[7] of 0x02 for clear access status register. This bit is into 0 after any write action.

2. Set target Device ID (0x34) in 0x20.

3. Set “the number of reading register -1” (0x0) to bit[3:0] of 0x22.
Note: The maximum data size is 16byte.

4. Set start address (0xD2) in 0x24 for setting Slave Device Address.

5. Write 1 to bit[0] of 0x26, and start read access to Sub-Link Slave register.

6. When read access is complete, read data is stored bit[7:0] in 0x10 (FMOD value is bit[3:0]), bit[7] of 0x02
value becomes “1” and INT pin H→L. If normally ended, the read result should be 0x80.

7. Read FMOD setting in 0x10.

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Example Operation 1-3: Access to 2-wire serial Slave Device with 8bit Register Address
Writing 3byte data to 2-wire serial Slave Device with 8bit Register Address.

1. Set 2-wire serial Slave Device ID (ex. 0x27) to bit[6:0] in 0x04 and set 1 to bit[7]. This step is not supposed
to be repeated.
Bit[6:0] Device ID
Bit[7]
0=Disable / 1=Enable

Note: The maximum entry is 8devices, 0x04-0x0B.
2. Write any value to bit[7] of 0x02 for clear access status register. This bit is into 0 after any write action.

3. Set 3byte data (ex. 0x1A, 0x2B, 0x3C) into 0x10-0x12 for writing into 2-wire serial Slave Device.

Note: The maximum data size is 16byte.

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4. Set target 2-wire serial Slave Device ID (0x27) bit[6:0] of 0x20 and set 0 to bit[7].
Bit[7]
0 = 8bit Register Address (Default)
1 = 16bit Register Address
Bit[6:0]
Target Device ID

5. Set “the number of write byte -1” (0x02) in 0x21.

6. Set start address of 2-wire serial Slave Device (ex. 0xC2) in 0x23.

7. Write 1 to bit[0] of 0x25 to start write access to 2-wire serial Slave Device register.

8. When write access is complete, bit[7] of 0x02 value becomes “1” and INT pin H→L. HOST MPU thenreceives interruption read access status register, confirming that write access is complete. If normally ended,
the read result should be 0x80.

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Example Operation 1-4: Access to 2-wire serial Slave Device with 16bit Register Address
Reading 3byte data to 2-wire serial Slave Device with 16bit Register Address.

HOST

SCL
SDA
INT
Step 8
INT: H→L
SUBMODE
=0
MSSEL
=0

Ex. AIN0=1, AIN1=0→Device ID: 7'h34

THCV236(-Q) : Sub-Link Master Device

THCV231(-Q) : Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

2-wire serial
Master2-wire serial Slave Device
Ex. device ID: 7'h3B
Register Address: 16bit

SCL
SDA

2-wire serial Slave Device Register

Internal
Bus

InternalBus
Sub-Link Master side Register

Sub-Link Slave side Register

Step

Address

Bits

W/R

Value

Step

Address

Bits

W/R

Value

1

0x04

7:0

W

0xBB

1

-

-

-

-

2

0x02

7

W

*

2

-

-

-

-

3

0x20

7:0

W

0xBB

3

-

-

-

-

4

0x22

3:0

W

0x2

4

-

-

-

-

5-1

0x29

7:0

W

0xA2

5-2

0x2A

7:0

W

0x5D

5

-

-

-

-

6

0x2C

0

W

1

6

-

-

-

7

0x02

7

R

1

7

0x5DA20x5DA4

7:0

R

0xA1,
0x92,
0x83

8

0x100x12

7:0

R

0xA1,
0x92,
0x83

8

-

-

-

-

1. Set 2-wire serial Slave Device ID (ex. 0x3B) to bit[6:0] of 0x04 and set 1 to bit[7]. This step is not supposed
to be repeated.
Bit[7]
0=Disable (Default) / 1=EnableBit[6:0] Device ID

Note: The maximum entry is 8devices, 0x04-0x0B.
2. Write any value to bit[7] of 0x02 for clear access status register. This bit is into 0 after any write action.

3. Set target 2-wire serial Slave Device ID (0x3B) bit[6:0] of 0x20 for reading register access and set 1 tobit[7] for 16bit Register Address.
Bit[7]
0 = 8bit Register Address (Default)
1 = 16bit Register Address
Bit[6:0] Target Device ID

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4. Set “the number of read byte -1” (0x02) in 0x22.
Note: The maximum data size is 16byte.

5. Set start address of 2-wire serial Slave Device ID (ex. 0x5DA2) in 0x29 and 0x2A.
0x29:
start address [7:0]
0x2A: start address [15:8]
S

7'h34

W

A

8'h29

A

8'hA2

A

8'h5D

A

P

6. Write 1 to bit[0] of 0x2C to start read access to 2-wire serial Slave Device register.

7. When read access is complete, reading data is stored into 0x10-0x12, bit[7] of 0x02 becomes “1”, and INT
pin H→L. If normally ended, the read result should be 0x80.

8. Read 3 byte data in 0x10-0x12.
S

7'h34

W

A

A

8'h10

8'hA1

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7'h34

Sr

A

8'h92

15/26

R

A

8'h83

A

P

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Example Operation 2-1: Through GPIO Sub-Link Master to Sub-Link Slave
Control through GPIO of the THCV236(-Q) (Sub-Link Master) and through GPIO of the THCV231(-Q)(Sub-Link Slave Device).

1. GPIO transmission type setting with bit[4:3] of 0x40 (Master side Register) and bit[4:3] of 0xC0 (Slave side
Register, refer to page 9).
0 = Programmable GPIO enable
1 = Through GPIO enable (Default)
2. GPIO output buffer type setting with bit[4:3] of 0xC6 (Slave side Register).
1=Push-pull output
0=Open-Drain output (Default)
3. GPIO polarity setting with bit[4:3] of 0x43 (Master side Register) and bit[4:3] of 0xC3 (Slave side
Register).
1=Input0=Output
4. GPIO4 and GPIO3 input of Master side is updated automatically to GPIO4 and GPIO3 output of Slave side.
Note: This through GPIO function is able to use with default register setting.

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Example Operation 2-2: Programmable GPIO output control
Control output GPIO of the THCV236(-Q) (Sub-Link Master side) and GPIO of the THCV231(-Q)(Sub-Link Slave side).

HOST

SCL
SDA
INT
SUBMODE
=0
MSSEL
=0

AIN1, AIN0=00:7'h0B
01:7'h34
10:7'h77
11:7'h65

THCV236(-Q) : Sub-Link Master Device

THCV231(-Q) : Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

2-wire serial
MasterInternal
Bus

SCL
SDA
2-wire serial
Slave Device

InternalBus
Sub-Link Master side Register

Sub-Link Slave side Register

Step

Address

Bits

W/R

Value

Step

Address

Bits

W/R

1

0x40

4:3

W

0x0

1

0xC0

4:3

W

0x0

2

0x46

4:3

W

Valid

2

0xC6

4:3

W

Valid

3

0x42

4:3

W

Valid

3

0xC2

4:3

W

Valid

4

0x43

4:3

W

0x0

4

0xC3

4:3

W

0x0

GPIO4, GPIO3 = H / L

Value

GPIO4, GPIO3 = H / L

1. GPIO transmission type setting with bit[4:3] of 0x40 (Master side Register) and bit[4:3] of 0xC0 (Slave side
Register, refer to page9).
0 = Programmable GPIO enable
1 = Through GPIO enable (Default)
2. GPIO output buffer type setting with bit[4:3] of 0x46 (Master side Register) and bit[4:3] of 0xC6 (Slaveside Register).
1=Push-pull output
0=Open-Drain output (Default)
3. GPIO output value setting with bit[4:3] of 0x42 (Master side Register) and bit[4:3] of 0xC2 (Slave side
Register).
1=H (Push-pull output: H / Open-Drain output: Hi-Z)
0=L (Default)
4. GPIO polarity setting with bit[4:3] of 0x43 (Master side Register) and bit[4:3] of 0xC3 (Slave side
Register).
1=Input0=Output

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Example Operation 2-3: Programmable GPIO input control
Control input GPIO of the THCV236(-Q) (Sub-Link Master side) and GPIO of the THCV231(-Q) (Sub-Link
Slave side).

1. GPIO transmission type setting with bit[4:3] of 0x40 (Master side Register) and bit[4:3] of 0xC0 (Slave side
Register, refer to page9).
0 = Programmable GPIO enable
1 = Through GPIO enable (Default)
2. GPIO polarity setting with bit[4:3] of 0x43 (Master side Register) and bit[4:3] of 0xC3 (Slave side
Register).
1=Input0=Output
3. Read bit[4:3] of 0x41 (Master side Register) and bit[4:3] of 0xC1 (Slave side Register, refer to page 11).

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Example Operation 3-1: Interrupt feedback as internal factor
Cause of interrupt is internal factor (ex. Sub-Link time out)

1. Set interrupt permission status about Sub-Link time out with bit[0] of 0x03 (Master side Register).
1=Interrupt allowed
0=Interrupt blocked (Default)
2. When disconnection occurs or Sub-Link access time out is occurred by Noise or other elements, aninterruption occurs. (INT=H → L)
3. Read the cause of interruption register with bit[7:0] in 0x02 (Master side Register).
4. Write any value to the cause of interruption register on bit[0] in 0x02 (Master side Register).
The cause of interruption register is cleared.
Interruption released. (INT=L → H)

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Example Operation 3-2: Interrupt output as external factor by Slave side
Cause of interrupt is external factor (ex. NACK signal from 2-wire serial Slave Device).

HOST

SCL
SDA
INT
Step 3
INT: H→L
Step6
INT: L→H

MSSEL=0
AIN1, AIN0=00:7'h0B
01:7'h34
10:7'h77
11:7'h65

THCV236(-Q) : Sub-Link Master Device

THCV231(-Q) : Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

2-wire serial
MasterInternal
Bus

InternalBus
Sub-Link Master side Register

SCL
SDA
Step 3
NACK
signal2-wire serial
Slave Device

Sub-Link Slave side Register

Step

Address

Bits

W/R

Value

Step

Address

Bits

W/R

1

0x03

4

W

1

1

-

-

-

Value

-

2

-

-

-

-

2

0x83

4

W

1
-

3

-

-

-

-

3

-

-

-

4

0x02

7:0

R

0x10

4

-

-

-

-

5

-

-

-

-

5

0x82

7:0

R

0x10

6

0x02

4

W

*

6

0x82

4

W

*

1. Set interrupt permission status about Slave side interrupt action with bit[4] of 0x03 (Master side Register).
1=Interrupt allowed
0=Interrupt blocked (Default)
2. Set interrupt permission status about 2-wire serial Slave Device NACK action with bit[4] of 0x83 (Slaveside Register, refer to page9).
1=Allowed to be reported to Master side
0=Blocked to be reported to Master side (Default)
3. Slave side device receive NACK signal from 2-wire serial Slave Device. An interruption occurs. (INT=H →L)
4. Read the cause of interruption register (SLAVESIDE_INT) with bit[4] of 0x02 (Master side Register).
5. Read the cause of interruption register (2WIRE_NACK_INT) with bit[4] of 0x82 (Slave side Register, referto page 11).
6. Write any value to a cause of interruption register with bit4 of 0x02 (Master side Register) and bit[4] of
0x82 (Slave side register).
Cause of interruption register is cleared.
Interruption released. (INT=L → H)

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Power Supply Usage

Separate all power domains in order to avoid unwanted noise coupling between noisy digital and sensitive
analog domains. In particular, PCB layout guide between AVDD (40 Pin) and VDD (41 Pin) are shown
page 23 for the THCV236(-Q).
Use 0.1uF high frequency ceramic capacitors as bypass capacitors between power and ground pins. Placethe capacitors as close to each power pin as possible.

Power Supply for THCV231(-Q)

VDD
0.1uF

10uF

AVDD
AVDD

10uF

24

23

22

21

20

19

18

17

25

16

26

15

27

14

28

12

30

11

33 EXPGND

31

10

32

9
1

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0.1uF

13

Exposed PAD

29

VDD

2

3

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4

5

6

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0.1uF

Power Supply for THCV236(-Q)

VDD
0.1uF

10uF

AVDD

0.1uF

VDD

47

46

45

44

43

42

AVDD

48

VDD

10uF

41

40

39

38

37

36

35

34

33

49

32

50

31

51

30

52

29

53

28

54

27

55

26

56

25

Exposed PAD

57

VDD

VDD

0.1uF

0.1uF

24

58

23

65 EXPGND

59

22

60

21

61

20

62

19

63

18

64

17
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VDD
0.1uF

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PCB layout guideline between VDD (41Pin) and AVDD (40Pin) for THCV236(-Q)
When power is supplied from reverse side layer to AVDD, please place ferrite bead behind through-hole (GoodExample1, 2). If it is needed to set ferrite beads on reverse side, please set GND-through-hole between AVDD
and VDD, and separate the distance as possible (Example). Do not set through-holes next to each other behind
ferrite beads (Bad Example).
Good Example 1
Good Example 2
3.6V-1.7V
BottomLayerthrough-hole

ferrite bead
bypasscapasitor

Close to power pin
as possible

39

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VDD
D8

AVDD

VDD

D7

D8

AVDD

VDD

Bad Example

D7

Example

D8

40

AVDD

41

D7

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Note1) Power On Sequence
Do not input clock or data before the THCV231(-Q) on in order to keep absolute maximum ratings.
2) Cable Connection and Disconnection
Do not connect and disconnect the LVCMOS and CML cable/connector, when the power is supplied to thesystem.

3) GND Connection
Connect the each GND of the PCB where the THCV231(-Q) and THCV236(-Q) are on it. It is better for
EMI reduction to place GND cable as close to LVCMOS and CML cable as possible.
4) Low Input Pulse into PDN, PDN1 and PDN0 Period Requirement
Do not input Low Pulse within 1msec into PDN (THCV231(-Q)), PDN1 and PDN0 (THCV236(-Q)).

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PCB Layout Considerations








Use at least four-layer PCBs with signals, ground, power, and signals assigned for each layer. (Refer tofigure below.)
PCB traces for high-speed signals must be single-ended microstirp lines or coupled microstrip lines whose
differential characteristic impedance is 100Ω.
Minimize the distance between traces of a differential pair (S1) to maximize common mode rejection andcoupling effect which works to reduce EMI (Electro-Magnetic Interference).
Route differential signal traces symmetrically.
Avoid right-angle turns or minimize the number of vias on the high speed traces because they usually cause
impedance discontinuity in the transmission lines and degrade the signal integrity.
Mismatch among impedances of PCB traces, connectors, or cables also caused reflection, limiting the
bandwidth of the high-speed channels.
Using common-mode filter on differential traces is desirable to reduce EMI. Pay attention on data-rate
driven noise. For example, if data-rate is 1.5Gbps, common mode choke coil of 1.5GHz common mode
impedance is desired to be high, while 1.5GHz differential impedance is low.

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Notices and Requests
1.
2.

The product specifications described in this material are subject to change without prior notice.
The circuit diagrams described in this material are examples of the application which may not always apply
to the customer's design. We are not responsible for possible errors and omissions in this material. Please
note if errors or omissions should be found in this material, we may not be able to correct them
immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.
5. Product Application
5.1. Application of this product is intended for and limited to the following applications:audio-video device, office automation device, communication device, consumer electronics, smartphone,feature phone, and amusement machine device. This product must not be used for applications that
requireextremely
high-reliability/safetysuchasaerospacedevice, traffic
device,transportation device, nuclear power control device, combustion chamber device, medical
device related to critical care, or any kind of safety device.
5.2. This product is not intended to be used as an automotive part, unless the product is specified as a productconforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet.
THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than the Specified
Product for it not conforming to the aforementioned demands and specifications.
5.3. THine accepts liability for demands and specifications of the Specified Product only to the extent that theuser and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with acertain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged tohave sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary
to support warranty for performance of this product. Except where mandated byapplicable law or deemed necessary by THine based on the user’s request, testing of all
functions and performance of the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over theabsolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance.
The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safetymeasures by adding protection devices, such as fuses.

THine Electronics, Inc.
sales@thine.co.jp

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