THC63LVDM83D_Rev.4.51_E

THC63LVDM83D
24bit COLOR LVDS TRANSMITTER

General Description

Features

The THC63LVDM83D transmitter is designed to support pixel
data transmission between Host and Flat Panel Display up to
1080p/WUXGA resolutions.
The THC63LVDM83D converts 28bits of LVCMOS data into
four OpenLDI(LVDS) data streams. The transmitter can be
programmed for rising edge or falling edge clock through a
dedicated pin. At a transmit clock frequency of 160MHz,
24bits of RGB data and 4bits of timing and control data
(HSYNC, VSYNC, DE, CONT1) are transmitted at an effective
rate of 1120Mbps per OpenLDI(LVDS) channel.

･Compatible with TIA/EIA-644 LVDS Standard･7:1 OpenLDI(LVDS) Transmitter･Operating Temperature Range : 0 to +70C･No Special Start-up Sequence Required･Spread Spectrum Clocking Tolerant up to 100kHz Frequency
Modulation and +/-2.5% Deviations.
･Wide Dot Clock Range: 8 to 160MHz Suited for
TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz)PC Signal : QVGA(8MHz) - WUXGA(154MHz)･56pin TSSOP Package･1.2V to 3.3V LVCMOS/ inputs are supported.
･LVDS swing is reducible as 200mV by RS-pin to reduce EMI
and power consumption.
･PLL requires no external components.
･Power Down Mode.

Application･Medium and Small Size Panel･Tablet PC / Notebook PC･Security Camera / Industrial Camera･Multi Function Printer･Industrial Equipment･Medical Equipment Monitor･Input clock triggering edge is selectable by R/F-pin･EU RoHS Compliant.

Block Diagram
THC63LVDM83D

TA0-6
TB0-6
TC0-6
TD0-6

DATA
(LVDS)
7
7
7
7

CMOS/TTL PARALLELTO SERIAL

CMOS/TTLINPUTS

TA +/TB +/TC +/TD +/(56-1120Mbit/On Each
LVDS Channel)

TRANSMITTER
CLKIN(8 to 160MHz)

TCLK +/-

PLL

CLOCK
(LVDS)
8-160MHz

R/F
/PDWN
RS

Figure 1. Block Diagram

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Pin Diagram

Figure 2. Pin Diagram

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Pin Description
Pin Name
TA+, TATB+, TBTC+, TCTD+, TDTCLK+,TCLKTA0 ~ TA6

Pin #47, 4845, 4641, 4237, 3839, 40/PDWN

51, 52, 54, 55, 56, 3,
4
6, 7, 11, 12, 14, 15,1920, 22, 23, 24, 27, 28,3050, 2, 8, 10, 16, 18,
25
32

RS

1

TB0 ~ TB6
TC0 ~ TC6
TD0 ~ TD6

DirectionType

Description
LVDS Data Out

Output

LVDS
LVDS Clock Out

Pixel Data Input

Input

LVCMOS

H : Normal Operation
L : Power Down (All outputs are Hi-Z)
LVDS Swing Mode, VREF Select See Fig.7,
8
RS PinVCC
0.6 to 1.4V
GND

R/F

17

CLKIN
VCC

31
9, 26

GND

5, 13, 21, 29, 53

LVDS VCC
LVDS GND
PLL VCC
PLL GND

4436, 43 49
34
33, 35

Power

-

LVDS
Swing
350mV
350mV
200mV

Small Swing
Input Support
N/A
RS=VREFN.A

VREF : is Input Reference Voltage
Input Clock Triggering Edge SelectH : Rising Edge
L : Falling Edge
Input Clock
Power Supply Pins for LVCMOS inputs anddigital circuit.
Ground Pins for LVCMOS Inputs and Digital
Circuitry.
Power Supply Pins for LVDS Outputs.
Ground Pins for LVDS Outputs.
Power Supply Pin for PLL Circuitry.
Ground Supply Pin for PLL Circuitry.

Table 1. Pin Description

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Absolute Maximum Ratings
Parameter
All Supply Voltage (VCC, LVDS VCC, PLL VCC)
LVCMOS Input Voltage
LVDS Output Pin
Output Current
Junction Temperature
Storage Temperature
Reflow Peak Temperature
Reflow Peak Temperature Time
Maximum Power Dissipation @+25C

Min
-0.3
-0.3
-0.3
-30
-55
-

Max
+4.0
VCC + 0.3
VCC + 0.3
30
+125
+150
+260
10
1.8

Unit
V
V
V
mA
C
C
C
sec
W

Table 2. Absolute Maximum Ratings

Recommended Operating Conditions
Symbol
VCC, LVDS VCC
PLL VCCTa-

Parameter
All Supply Voltage

Min
3.0

Typ
3.3

Max
3.6

Unit
V

Operating Ambient Temperature
Clock Frequency

0
8

25
-

+70
160

C
MHz

Table 3. Recommended Operating Conditions“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics
Table4, 5, 6, 7” specify conditions for device operation.
“Absolute Maximum Rating” value also includes behavior of overshooting and undershooting.

Equivalent LVDS Output Schematic Diagram
3.5mA

IN_N

LVDS_OutN

LVDS_OutP

IN_P

Figure 3. LVDS Output Schematic Diagram

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Power Consumption
Over recommended operating supply and temperature range unless otherwise specified
SymbolParameter
Conditions
Typ*
Max
Unit
RL=100,CL=5pF,
f=85MHz,
61
67
mA
RS=VCC
RL=100,CL=5pF,
f=135MHz,
77
83
mA
RS=VCC
RL=100,CL=5pF,
f=160MHz,LVDS Transmitter
84
92
mA
RS=VCCOperating Current
ITCCW
Worst Case Pattern RL=100,CL=5pF,
f=85MHz,
50
56
mA(Fig.4)
RS=GND
RL=100,CL=5pF,
f=135MHz,
65
71mA
RS=GND
RL=100,CL=5pF,
f=160MHz,
73
80mA
RS=GND
LVDS Transmitter
ITCCS
Power
Down /PDWN=L, All Inputs=L or H
10
µA
Current*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
Table 4. Power Consumption

Worst Case Pattern
CLKIN

Tx0-6

x=A,B,C,D
Figure 4. Worst Case Pattern

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Electrical Characteristics
LVCMOS DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Parameter
Conditions
Min
Typ*
Max
Unit
High Level Input Voltage
RS=VCC or GND
2.0
VCC
V
Low Level Input Voltage
RS=VCC or GND
GND
0.8
V
Small Swing Voltage
1.2
2.8
V
Input Reference Voltage
Small Swing (RS=VDDQ/2)
VDDQ/2
VDDQ/2
Small Swing High Level
VREF= VDDQ/2+100m
V
Input Voltage
V
VSL2
Small Swing Low LevelVDDQ/2
VREF= VDDQ/2
V
Input Voltage-100mV
IINC
Input Current
GND  VIN  VCC
10
A*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
Notes : 1 VDDQ voltage defines the max voltage of small swing inputs at RS=VREF. It is not an actual input
Symbol
VIH
VIL
VDDQ1
VREF
VSH2

voltage.
2 Small swing signals are applied to TA0-6, TB0-6, TC0-6, TD0-6 and CLKIN.

Table 5. LV-CMOS DC Specifications

LVDS Transmitter DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Parameter
Conditions
Min
Typ*
Max
Unit
Normal swing
250
350
450
mV
RS=VCC
VOD
Differential Output Voltage RL=100Ω
Reduced
swing
100
200
300
mV
RS=GND∆VOD
Change in VOD between
complementary
output35
mV
statesVOC
Common Mode Voltage
RL=100Ω
1.125
1.25
1.375
V
∆VOC
Change in VOC between
complementary
output35
mV
states
IOS
OutputShort
Circuit
VOUT=GND, RL=100Ω
-24
mA
Current/PDWN=GND,
IOZ
Output TRI-STATE Current
10
A
VOUT=GND to VCC*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
Table 6. LVDS Transmitter DC Specifications
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LVCMOS & LVDS Transmitter AC Specifications
Over recommended operating supply and temperature range unless otherwise specified
SymbolParameter
Min
Typ
Max
Unit
tTCIT
CLK IN Transition Time
5.0
ns
tTCP
CLK IN Period
6.25
T
125
ns
tTCH
CLK IN High Time
0.35T
0.5T
0.65T
ns
tTCL
CLK IN Low Time
0.35T
0.5T
0.65T
ns
tTCD
CLK IN to TCLK+/- Delay
3T
ns
tTS
LVCMOS Data Setup to CLK IN
2.0
ns
tTH
LVCMOS Data Hold from CLK IN
0.0
ns
tLVT
LVDS Transition Time
0.6
1.5
ns
tTOP1
Output Data Position0 (T=6.25ns ~ 20ns)
-0.15
0.0
+0.15
ns
tTop0
Output Data Position1 (T=6.25ns ~ 20ns)
T/7-0.15
T/7
T/7+0.15
ns
tTop6
Output Data Position2 (T=6.25ns ~ 20ns)
2T/7-0.15
2T/7
2T/7+0.15ns
tTop5
Output Data Position3 (T=6.25ns ~ 20ns)
3T/7-0.15
3T/7
3T/7+0.15ns
tTop4
Output Data Position4 (T=6.25ns ~ 20ns)
4T/7-0.15
4T/7
4T/7+0.15ns
tTop3
Output Data Position5 (T=6.25ns ~ 20ns)
5T/7-0.15
5T/7
5T/7+0.15ns
tTop2
Output Data Position6 (T=6.25ns ~ 20ns)
6T/7-0.15
6T/7
6T/7+0.15
ns
tTPLL
Phase Lock Loop Set
10.0
ms*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
Table 7. LVCMOS & LVDS Transmitter AC Specifications

LVCMOS Input90%

CLK IN

90%
10%

10%
t TCITt TCIT

Figure 5. CLKIN Transmission Time

LVDS Output

LVDS Output Load
Figure 6. LVDS Output Load and Transmission Time

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AC Timing Diagrams
LVCMOS Inputs

RS
VCC
0.6 ~ 1.4V
GND

Normal Swing Input

VOD
350mV
200mV

Note :
CLKIN : Solid line denotes the setting of R/F=GND
Dashed line denotes the setting of R/F = VCC
Figure 7. LVCOMS Inputs and LVDS Clock Output Timing 1

Small Swing Inputs

RS
VREF
VCC
--0.6 ~ 1.4V VDDQ/2
GND
---

tTCP
tTCH

V DDQ

CLKIN

V DDQ /2

VDDQ /2

VDDQ /2

VREF
GND

tTCL
tTS

tTH

V DDQ

Tx0-Tx6

V DDQ /2

VDDQ /2

V REF
GND

tTCD

TCLK+
VOC

TCLK-

Note :
CLKIN : Solid line denotes the setting of R/F=GND
Dashed line denotes the setting of R/F = VCC
Figure 8. LVCMOS Inputs and LVDS Output Timing 2

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LVDS Output Data Position
Vdiff = 0V

Vdiff = 0V

TCLK+/(Differential)
TA+/-

TA6

TA5

TA4

TA3

TA2

TA1

TA0

TB+/-

TB6

TB5

TB4

TB3

TB2

TB1

TB0

TC+/-

TC6

TC5

TC4

TC3

TC2

TC1

TC0

TD+/-

TD6

TD5

TD4

TD3

TD2

TD1

TD0

Previous Cycle

Next Cyclet T OP1
t TOP0t TOP6t TOP5t TOP4t TOP3t TOP2

Figure 9. LVDS Output Data Position

Phase Lock Loop Set Time
/PDWN

VCC

2.0V

3.0V
tTPLL

CLKIN
Vdiff = 0V

TCLK+/-

Figure 10. PLL Lock Loop Set Time

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Spread Spectrum Clocking Tolerant

Figure 11. Spread Spectrum Clocking Tolerant

The graph indicates the range that the IC works normally under SS clock input operation.
The results are measured with a typical sample on condition of +25Cº and 3.3V, therefore thesevalues are for reference and do not guarantee the performance of a product under other circumstance.

LVDS Data Timing Diagram

Figure 12. LVDS Data Timing Diagram

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For Display Application
THC63LVDM83D Pixel Data Mapping for JEIDA Format (6bit, 8bit Application)
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6

6bit
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
Hsync
Vsync
DE
-

8bit
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
Hsync
Vsync
DE
R0
R1
G0
G1
B0
B1
N/A

Note : Use TA to TC channels and open TD channel for 6bit application.
Table 8. Data Mapping for JEIDA Format

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THC63LVDM83D Pixel Data Mapping for VESA Format (6bit, 8bit Application)
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6

6bit
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
Hsync
Vsync
DE
-

8bit
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
Hsync
Vsync
DE
R6
R7
G6
G7
B6
B7
N/A

Note : Use TA to TC channels and open TD channel for 6bit application.
Table 9. Data Mapping for VESA Format

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Typical Connection

Figure 13. Typical Connection Diagram

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Notes
1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.

2) GND Connection
Connect each GND of the PCB which THC63LVDM83D and LVDS-Rx on it.
to place GND cable as close to LVDS cable as possible.

It is better for EMI reduction3) Multi Drop Connection
Multi drop connection is not recommended.

TCLK+
THC63LVDM83D

LVDS-RXTCLKLVDS-RX

Figure 14. Multi Drop Connection4) Asynchronous use
Asynchronous using such as following systems is not recommended.

CLKOUTTCLK+DATA THC63LVDM83D

TCLK-IC CLKOUT

CLKOUT
LVDS-RX

DATA
IC

TCLK+

DATA THC63LVDM83D

TCLK-

LVDS-RX

CLKOUTTCLK+DATA THC63LVDM83D

TCLK-IC CLKOUTTCLK+DATA THC63LVDM83D

DATA

IC

TCLK-

Figure 15. Asynchronous Use

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8.10 NOM

0.05~0.15

0.25

1.20MAX

6.10+/-0.1

Package

Figure 16. Package Diagram

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Reference Land Pattern
CY1=
10.34

HE=

e=
8.100

0.500

E=
6.10
Package
Land PatternTtyp.=
0.60
Gmin=
5.50

1.90

b=
0.200

Zmax=

Xmax=
0.470

9.30

Zmax/2
Unit mmFigure 17. Reference of Land Pattern

The recommendation mounting method of THine device is reflow soldering.
The reference pattern is using the calculation result on condition of reflow soldering.

Notes
This land pattern design is a calculated value based on JEITA ET-7501.
Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity ofconnection, the density of mounting, and the solder paste used, etc… The optimal land pattern size changes
with these parameters. Please use the value shown by the land pattern as reference data.

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THC63LVDM83D_Rev.4.51_E

Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

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