THPM4301A_Rev.1.11_E

THPM4301A
3.3V/5V Input 6A Output POL Power Module
Features

Description



THPM4301A is an easy-to-use 6A output integrated
Point of Load (POL) power supply module. It contains
integrated power MOSFETs, driver, PWM controller, ahigh-performance inductor, input and output capacitorsand other passive components in one low profile LGA
package using Inductor technology.
There is no need for loop compensation, sensitive PCB
layout, inductor selection or in-circuit production testing.
Each module is fully tested.
The THPM4301A can be programmed for any output
voltage between 0.6V and 3.6V using a single external
resistor. For an output voltage of 0.6V no resistor isrequired.
THPM4301A can deliver full 6A load current without
derating at 85°C ambient temperature with no airflow.
Small size (11mm x 9.1mm) and low profile (2.8mm)
allows the THPM4301A to be placed very close to its loador on the back side of the PCB for high density
applications.

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Integrated Point of Load power module using in
Inductor technology
Small footprint, low-profile, 11mm x 9.1mm x
2.8mm, with LGA Package (0.63 mm Pads)
Efficiency up to 96%
High output current, 6A without derating at 85°C
ambient with no air flow
Wide output voltage adjustment: 0.6V to 3.6V
Pre-bias startup capability
User adjustable switching frequency
Synchronization to external clock signal
Adjustable soft-start time for output voltage
Output voltage sequencing / tracking
Enable signal input and Power Good signal output
Programmable Under Voltage Lock Out (UVLO)
Output Over Current Protection (OCP)
Over temperature protection
Operating temperature range -40°C to 85°C

Applications

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Broadband and communications equipment
DSP and FPGA Point of Load applications
High density distributed power systems
PCI express / PXI express
Automated test and medical equipment

SIMPLIFIED APPLICATION

PWRGD

COMP

SS/TR

PHASE

VIN

VOUT
COUT

SPM1005
THPM4301A

CIN
47uF

100uF

VSENSE

RT/CLK

EN

VADJ
PGND

AGND

STSEL

RADJ

Efficiency (%)

VOUT

VIN= 2.95-6V

ON/OFFCONTROLEFFICIENCY VS LOAD CURRENT
100
98
96
94
92
90
88
86
84
82
80

Vin = 5 V, Vout = 3.3 V
Vin = 3.3 V, Vout = 1.8 V
0

1

2
3
4
Output Current (A)56THine Electronics, Inc.

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ABSOLUTE MAXIMUM (1) RATINGS over operating temperature range(unless otherwise noted)
VALUE

Unit
MAX
VIN
7
V
EN
7
V
VSENSE
VOUT
V
COMP
3
V
Input Voltage
PWRGD
6
V
SS / TR
3
V
STSEL
3
V
RT / CLK
6
V
Output Voltage
VOUT
VIN
V
EN
100
μA
Source Current
RT / CLK
100
μA
COMP
100
μA
Sink Current
PWRGD
10
mA
SS / TR
100
μA
Operating Junction Temperature
150°C
Temperature
Storage Temperature
-55
150
°C
Peak solder reflow body temperature
245°C(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the module. These are stressratings only, and functional operation of the module at these or any other conditions beyond those indicated underrecommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect reliability.
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.6

ORDERING INFORMATION
Output Voltage
Adjustable

Module Part Number
THPM4301A

Pad Finish
Au (RoHS)

Package Type
LGA

Temperature Range-40˚C to 85˚C

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ELECTRICAL CHARACTERISTICS:
The electrical performance is based on the following conditions unless otherwise stated: 25°C ambient temperature,no air flow; VIN = 5V, (1) VOUT = 1.8V, IOUT = 6A, CIN1 = 47μF ceramic, COUT = 2×47μF ceramic.
PARAMETERSIOUT: Output current
VIN: Input voltage
VSTART Startup voltage
UVLO Under Voltage Lock Out
Hysteresis between VSTART and UVLO
Set point accuracy
Temperature variation
VOUT
Line regulation
Load regulation
VOUT(adj): Output voltage adjust rangeη Efficiency
FS Switching frequency [Note 3]
Output voltage ripple
ILIM Current Limit Point
VEN-H Enable control
VEN-L Enable control

TEST CONDITIONSTA = -40°C to 85°C, natural convection
Over IOUT range, -40°C to 85°C
Over IOUT range, -40°C to 85°C [Note 1]
Over IOUT range, -40°C to 85°C [Note 1]
Over IOUT range [Note 1]
TA = 25°C, IOUT = 3A [Note 2]-40°C < TA < +85°C, IOUT = 3A
Over VIN range, TA = 25°C, IOUT = 3A
Over IOUT range, TA = 25°C, VIN = 5V
Over IOUT range, TA = -40°C to 85°C
VOUT = 3.3V, IOUT = 3A
VIN = 5V
VOUT = 3.3V, IOUT = 6A
VOUT = 2.5V, IOUT = 3A
VIN = 3.3V
VOUT = 2.5V, IOUT = 6A
RT = 127KΩ between RT/CLK and AGND
20MHz bandwidth
Enable high voltage
Enable low voltage
VOUT rising threshold

PWR Good:
VOUT falling threshold
Thermal shutdown

Good
Fault
Good
Fault

Thermal shutdown
Thermal shutdown recovery hysteresis

MIN
0
2.95

TYP

MAX
6
6

UNIT
A
V
V
V
V

3.6

V

2.8
2.5
0.3
±1%
±0.3%
±0.2%
±0.2%
0.6
96.1%
94.2%
95.4%
92.3%
750
20
9.0
1.3
1.18
93%
105%
103%
91%
170
15

kHz
mVpp
A
V
V

°C
°C

Note 1: With REN1 = 14.7k Ω and REN2 = 12.7k Ω as shown in Fig. 28.
Note 2: With 0.1% tolerance external voltage set resistor.
Note 3: 750kHz is suitable for 3.3V output, but lower switching frequencies are recommended for lower output voltages. See
Table 3 for recommended switching frequency, and refer to page 19 for information on adjusting the frequency.

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FUNCTIONAL BLOCK DIAGRAM
ThermalShutdown
PWRGD

PWRGD
Logic

Shutdown
Logic

EN

VIN
UVLO

VIN

COMP

Compensation
Network

VADJ

PHASE
Power
Stage
and
Control
Logic

SS/TR

STSEL

VREF

VOUT

VSENSE
PGND
RT/CLKOSC w/PLL

OCP

AGND

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PIN DESCRIPTIONSPIN Name
VIN(B5-C5, A6-C6, A7-C7)
PHASE
(F7)
VOUT
(A1-D1, B2-D2)
PGND(F1-H1, E2-H2, A3-G3,
A4-G4, D5-G5, D6-G6,
D7-E7)
AGND
(H3)

STSEL
(G7)

SS/TR
(H7)

RT/CLK
(H6)

EN
(A5)
COMP
(H5)
VADJ
(H4)
PWRGD
(A2)
VSENSE(E1)

Description
The positive input voltage power pin, which is referenced to PGND. Connect external input
filter capacitors between these pins and PGND plane, close to module.
Switching node pin. Connect this pin to a small copper island under the module for best
thermal performance. Do not connect any external component to this pin or use this pin for any
other functions.
Output voltage. Connect external output filter capacitors between these pins and PGND plane,close to the module.
Zero DC voltage reference for power circuitry. These pins should be connected directly to
the PCB ground plane. The module's heat transfer is through these pins and all of them must beconnected together externally with a copper plane located directly under the module.
Zero DC voltage reference for the analog control circuitry. A small analog ground plane isrecommended. RT/CLK, STSEL, SS/TR pins should be referenced to analog ground. AGND
and PGND should be connected at a single point is such a way that load current does not flowin the AGND plane.
Startup mode selection. Short to AGND for soft-start operation with extended soft-start time
determined by a capacitor connected between SS/TR pin and AGND. Leave this pin open for
tracking operation or selecting default soft-start time that is nominally 1.1ms. See SS/TR pin
description below for more details.
Soft-start or tracking operation. When SS/TR pin is open and STSEL pin is shorted to
AGND, the power module operates in soft-start mode with the default soft-start time of 1.1ms.
Longer soft-start time can be achieved with an additional capacitor connected between SS/TR
pin and AGND.
Capacitor value can be selected based on Equation 4 or values provided in Table 2. For
tracking operation, leave STSEL open and do not connect additional capacitor between SS/TR
and AGND. Connect this pin to the voltage to be tracked. Refer to Fig. 30 for more details.
Switching frequency and external synchronization pin. An internal 90.9KΩ resistor isconnected between RT/CLK and AGND to set the switching frequency to 450KHz. An external
synchronization clock can be connected to RT/CLK pin to synchronize the switching frequencyof the module. More details are provided on page 19.
Enable pin with internal pull-up current source. Pull this pin to below 1.18V to disable thepower module. Float this pin or pull to above 1.3V to enable the power module. This pin can beused to adjust the under voltage lockout (UVLO) level with two additional resistors forming a
voltage divider from VIN to AGND as shown in Fig. 28.
Compensation pin. The COMP pin should be open.
Output voltage adjustment pin. Connect a resistor, RADJ, between VADJ pin and AGND pin
to set the desired output voltage, as shown in Fig. 15.
Power Good pin. An open drain output that is pulled low when VSENSE voltage is less than
91% or greater than 105% of the nominal output voltage. PWRGD is floating when the voltage
at VSENSE pin is between 93% and 103% of the nominal output voltage.
Remote sensing pin for the output voltage. Connect this signal to VOUT close to the load for
improved regulation. Do not use an LC filter between VOUT pins of the module and the point
where VSENSE is connected.
Note: this pin is not connected to VOUT inside the module and must be connected externally.

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LGA PACKAGE
56 PINS(TOP VIEW)

7
6
5
4
3
2
1
A

B

C

D

E

F

G

H

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TYPICAL CHARACTERISTICS (Note 1)
100

1.4

98

1.2

Power Dissipation (W)Efficiency (%)

VOUT = 3.3V

96
94
92
90

Vin = 5 V
Vin = 6 V

88

Vin = 5 V
Vin = 6 V

1
0.8
0.6
0.4
0.2
0

86
0

1

2

3

4

5

0

6

1

2

3

4

5

6

Output Current (A)Output Current (A)Fig. 1 Efficiency vs Output Current

Fig. 2 Power Dissipation vs Output Current

1.4

100
98
96
94
92
90
88
86
84
82
80

Power Dissipation (W)Efficiency (%)

VOUT = 2.5V

Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0

1

2

3

4

Vin = 3.3 V
Vin = 5 V
Vin = 6 V

1.2
1
0.8
0.6
0.4
0.2
0

5

0

6

1

2

3

4

5

6

Output Current (A)Output Current (A)Fig. 3 Efficiency vs Output Current

Fig. 4 Power Dissipation vs Output Current

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100
98
96
94
92
90
88
86
84
82
80

1.4
Power Dissipation (W)Efficiency (%)

VOUT = 1.8V

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0

1

2

3

4

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V

1.2
1
0.8
0.6
0.4
0.2
0

5

0

6

1

2

3

4

5

6

Output Current (A)Output Current (A)Fig. 5 Efficiency vs Output Current

Fig. 6 Power Dissipation vs Output Current

98
96
94
92
90
88
86
84
82
80
78

1.4

Power Dissipation (W)Efficiency (%)

VOUT = 1.5V

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0

1

2

3

4

5

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V

1.2
1
0.8
0.6
0.4
0.2
0

6

0

1

2

3

4

5

6

Output Current (A)Output Current (A)Fig. 7 Efficiency vs Output Current

Fig. 8 Power Dissipation vs Output Current

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VOUT = 1.0V
96

1.4

94

1.2

Power Dissipation (W)Efficiency (%)

92
90
88
86
84

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V

82
80
78
0

1

2

3

4

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V

1
0.8
0.6
0.4
0.2
0

5

6

0

1

2

3

4

5

6

Output Current (A)Output Current (A)Fig. 9 Efficiency vs Output Current

Fig. 10 Power Dissipation vs Output Current

VOUT = 0.8V
94

1.4

92

1.2
Power Dissipation (W)Efficiency (%)

90
88
86
84
82

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V

80
78
76
0

1

2

3

4

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V

1
0.8
0.6
0.4
0.2
0

5

0

6

1

2

3

4

5

6

Output Current (A)Output Current (A)Fig. 11 Efficiency vs Output Current

Fig. 12 Power Dissipation vs Output Current

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VOUT = 0.6V
90

1.4

88

1.2

Power Dissipation (W)Efficiency (%)

86
84
82
80
78

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V

76
74
72
0

1

2

3

4

Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V

1
0.8
0.6
0.4
0.2
0

5

6

0

1

2

3

4

5

6

Output Current (A)Output Current (A)Fig. 13 Efficiency vs Output Current

Fig. 14 Power Dissipation vs Output Current

Note 1: The above curves (Fig. 1 to Fig. 14) are derived from measured data taken on samples of the THPM4301A
tested at room temperature (25°C), and are considered to be typical for the product.

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APPLICATION INFORMATION
Output Voltage Adjustment
The output voltage of THPM4301A can be adjusted from 0.6V to 3.6V using an external resistor between VADJ pin
and AGND pin, as shown in Fig. 15. The required resistor value RADJ can be calculated using equation (1).

SPM1005
THPM4301A

VOUT

VOUT
COUT

VSENSE
R1

VADJ
0.6V AGND

RADJ

Fig. 15 Output Voltage Setting

RADJ ( K) 

R1  0.6
VO  0.6(1)

where R1 = 20kΩ and VO is the desired output voltage in Volts. For best set-point accuracy, it is recommended touse a 0.1% tolerance resistor. [Note: R1 is internal to the module as shown in Fig. 15].

Transient Response
The following table summarizes the measured output voltage overshoot and undershoot when the load current
undergoes a step change between 2A and 5A. The slew rate for the current change is 1A/µs. The measured waveforms
are given from Fig. 16 to Fig. 21. The measurement is obtained when the input capacitor consists of one 47µF ceramic
capacitor in parallel with one 220µF electrolytic capacitor, and the output capacitor consists of four 47µF ceramic
capacitors in parallel. If smaller output voltage deviation is required, larger output capacitor values can be used.
Table 1. Output Voltage Transient Response
Testing Conditions: CIN1 = 1 x 47µF CERAMIC, CIN2 = 220µF ELECTROLYTIC, COUT = 4 × 47µF CERAMIC
VIN (V)
3.3
5.0
3.3
5
3.3
5

VOUT (V)
1.0
1.2
1.8

3A LOAD STEP, 2A to 5A, (1A/µs)
VOLTAGE DEVIATIONRECOVERY TIME
(mV)
(µs)
50
155
45
145
55
150
50
150
70
170
65
165

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Fig. 16 VIN = 5V, VOUT = 1.0V, 3A Load Step

Fig. 17 VIN = 3.3V, VOUT = 1.0V, 3A Load Step

Fig. 18 VIN = 5V, VOUT = 1.2V, 3A Load Step

Fig. 19 VIN = 3.3V, VOUT = 1.2V, 3A Load Step

Fig. 20 VIN = 5V, VOUT = 1.8V, 3A Load Step

Fig. 21 VIN = 3.3V, VOUT = 1.8V, 3A Load Step

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Application Schematics
Fig. 22 shows a typical schematic for a 1.2V output application using THPM4301A with switching frequency of 500
kHz. The adjustment resistor, RADJ, is selected as 20kΩ calculated based on Equation (1). RT/CLK is connected to
ground with a 787kΩ resistor to select the recommended switching frequency. STSEL pin is connected to AGND toselect the default startup time. The ON/OFF CONTROL signal is used to turn on and off the power module.

THPM4301A

Fig. 22 Typical Schematic VIN = 2.95V to 6.0V, VOUT = 1.2V, FS = 500kHz
Fig. 23 shows a typical schematic for a 5V input, 3.6V output application using THPM4301A. The adjustment resistor,
RADJ, is selected as 4.02kΩ calculated based on Equation (1). In this example, the switching frequency is selected as
750kHz by connecting the timing resistor of 127kΩ between RT/CLK pin and AGND pin.

THPM4301A

Fig. 23 Typical Schematic VIN = 4.4V to 6.0V, VOUT = 3.6V, FS = 750kHz

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Power Good (PWRGD)
The PWRGD pin is an open drain output, and can be used to indicate when the output voltage is within the normal
operating range. This pin is pulled low when VSENSE voltage is less than 91% or greater than 105% of the nominal
output voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted, or if the EN
pin is pulled low.
There is a 2% hysteresis, so once the VSENSE pin is within 93% to 103% of the nominal output voltage the PWRGD
pin is de-asserted and the pin floats.
It is recommended to use a pull-up resistor between 1kΩ and 100kΩ to a voltage source that is 5.5V or less. The
PWRGD will be in a valid state (high or low as above) once the VIN input voltage is greater than 1.2V.

Power-Up Characteristics
When configured as shown in the front page schematic (page 1), THPM4301A produces a regulated output voltage
whenever a valid input voltage is present.
During the power-up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting thecharging current to the output capacitor.
Fig. 24 shows the startup waveforms for THPM4301A, operating from a 5V input and with the output voltage
adjusted to 1.8V. The waveform is measured with a 3A constant current load.

Fig. 24 Startup Waveforms

Enable (On/Off) Operation and Under Voltage Lockout (UVLO) Setup
The EN pin provides an external on/off control of the power module and is lightly pulled up internally with a current
source. The module is enabled if this pin is left open or its voltage exceeds the VEN-H threshold voltage, and the power
module starts operation once the input voltage is higher than VSTART.
When the voltage at EN pin is below the VEN-L threshold voltage, the power module stops switching and enters low
quiescent current state.
If an application requires controlling the EN pin, an open drain or open collector logic can be used to interface withthe pin, as shown in Fig. 25. In this figure, high ON/OFF CONTROL signal level (Low EN) disables the power
module.

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THPM4301A

Fig. 25 Typical ON/OFF Control SchematicFig. 26 and Fig. 27 show the typical output voltage waveforms when THPM4301A is enabled (turned on) and disabled(turned off) by the EN pin. In these figures, the top trace is the power good signal, the middle trace is the EN pin
voltage, and the bottom trace is the output voltage.

Fig. 26 Waveforms at Enable Turn-On

Fig. 27 Waveforms at Enable Turn-Off

Under-voltage lockout can be used to prevent the output from starting until the input voltage is within its normal
range. For input under voltage lockout (UVLO) adjustment, use the EN pin as shown in Fig. 28 to set the UVLO
level by using two external resistors. Once the EN pin voltage exceeds 1.3V, an additional 2.8μA of current is added
to provide input voltage hysteresis. Resistor REN1 and REN2 can be calculated using Equations (4) and (5) based on
the required startup voltage and shutdown voltage.

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Fig. 28 Input Under-Voltage Lockout Setup

(4)

(5)

Ih = 2.8μA, Ip = 0.7μA, VEN_RISING = 1.3V, VEN_FALLING = 1.18V.
As an example, if REN1 = 14.7k Ω and REN2 = 12.7k Ω, VSTART will be 2.8V and UVLO will be 2.5V.
It is recommended to set the minimum UVLO level of the module at 2.45V or higher to ensure proper operation
before shutdown.

Soft-Start or Tracking Pin (SS/TR)
The soft-start function forces the output voltage to rise gradually to its nominal value rather than rising as rapidly as
possible. Soft-Start mode is selected when the module is used independently without tracking or sequencing. To
select soft-start operation mode the STSEL pin is connected to AGND. This will activate the internal soft-startcapacitor for a nominal soft-start time of 1.1ms. An external capacitor between the SS/TR pin to ground can be used
to increase the soft-start time to higher values if desired.
Table 2 shows the soft-start time using typical soft-start capacitor values.
Table 2. Soft-start capacitor values and soft-start time
External capacitor (nF)
SS Time (ms)

open
1.1

4.7
2.7

10
4.4

If other startup time is needed, Equation (6) provides the relationship between the external soft-start capacitor value
CSS and the soft-start time, TSS.

CSS  3  TSS (ms )  3.3(nF )(6)THine Electronics, Inc.

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During the soft-start period, VSENSE voltage will follow the SS/TR pin voltage up to 90% of the nominal voltage
setpoint. When the SS/TR voltage is greater than 90% of the nominal voltage, the effective system reference voltage
will be changed from the SS/TR voltage to the internal voltage reference to close the voltage loop.
If the input voltage falls below the UVLO, or a thermal shutdown event occurs, or the EN pin is pulled down to below
1.18V, the THPM4301A will stop switching and the SS/TR will be discharged to below 60mV before the module
restarts.

Sequencing and Tracking
The term sequencing is used when two or more separate modules are configured to start one after the other, insequence. The term tracking is used when two or more modules are configured so that they start together, with their
output voltages tracking each other during startup. This is done by having one module act as a master and the other(s)act as slave(s). Sequencing and tracking startup can be implemented using the SS/TR, EN and PWRGD pins.
The sequential startup connection is shown in Fig. 29. The power good pin (PWRGD) of the first THPM4301A
module is connected to the EN pin of the second THPM4301A module, which will be enabled only after the output
voltage of the first THPM4301A module reaches regulation range and its PWRGD is asserted. Note: The
THPM4301A can start in sequence with another THPM4301A or with any other POL having a compatible Power
Good output.
With tracking mode the output voltage of the THPM4301A is controlled by another voltage applied to its SS/TR
input. Tracking startup of two THPM4301A modules can be achieved by connecting a resistor network of R1 and R2
as shown in Fig. 30, where the output voltage of the second THPM4301A module (bottom) will track the output
voltage of the first THPM4301A module (top). In this case, the soft-start time of THPM4301A module #1 isdetermined by the capacitor connected to its SS/TR pin and the STSEL pin is connected to ground. The voltage at SS/ TR pin of the second THPM4301A module is directly controlled by the output voltage of the first THPM4301A
module through the resistor divider (R1 and R2). The STSEL pin of the second THPM4301A module should be left
open.Resistor divider R1 and R2 in Fig. 30 can be calculated using Equations (7) and (8). Note: The THPM4301A
can track any external voltage, so the master can be a THPM4301A or any other POL.

VOUT 1  5( k )
0 .9
0.9  R1R2 (k)
VOUT 1  0.9
R1 

(7)
(8)

Fig. 31 gives the output voltage waveforms of two THPM4301A modules operating in sequential startup mode. Itshows that PWRGD signal becomes high when the first THPM4301A (2.5V output in this example) enters regulationand then the second THPM4301A (1.2V output in the example) begins to start up.
Fig. 32 gives the output voltage waveforms of two THPM4301A modules operating in tracking startup mode. Itshows that VOUT1 follows VOUT2 until the lower voltage rail (VOUT2) enters regulation (1.2V in this example). Then,
VOUT1 continues to rise to its steady state value (2.5V in the example).

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THPM4301A#1
THPM4301A#1

THPM4301A#2

THPM4301A#2

Fig. 29 Sequencing Startup SchematicFig. 30 Tracking Startup Schematic

Note: when used in tracking mode, if the slave unit (module #2 in Fig. 30) shuts down while the other module is still
operating, a latch-up condition can occur where the slave unit does not restart. To avoid this, it is necessary to pull
down the SS/TR pin of module #2 to below 60mV momentarily, to initiate a normal start-up sequence.

Fig. 31 Sequencing Startup,

Fig. 32 Tracking Startup,

VOUT1 = 2.5V, VOUT2 = 1.2V

VOUT1 = 2.5V, VOUT2 = 1.2V

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Switching Frequency Selection and Timing Resistor (RT/CLK Pin)
The switching frequency of the THPM4301A can be adjusted over a wide range from approximately 450 kHz to
750kHz. A resistor between RT/CLK and AGND can be used to increase the switching frequency. An internal resistor,
RCLK = 90.9kΩ, sets the minimum (default) switching frequency to 450 KHz. Generally, a higher frequency ispreferred for higher output voltages as indicated in Table 3 .
The user can increase the switching frequency by adding an external resistor, RT, between RT/CLK pin and AGND,
as shown in Fig. 33, where RT is calculated using Equation (9). The relationship between switching frequency and
RT resistor value is shown in Fig. 34.

RCLK
FSW (kHz)1.052  R  1
CLK
56183

Switching Frequency in KHz

RT ( kΩ ) 

THPM4301A

(9)

1500
1400
1300
1200
1100
1000
900
800
700
600
500
0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800

Resistance in
RRTEQResistanceinKΩkΩFig. 34 Switching Frequency vs RT for
THPM4301A

Fig. 33 Switching Frequency Adjustment

The recommended switching frequency for different output voltages is shown in Table 3, which also shows thenearest standard 1% values for RT.
Table 3. - Recommended switching frequency and RT value

Output voltage Recommended switching frequency (kHz) Resistor RT
3.3
750
127kΩ
2.5
650
191kΩ
1.8
600
255kΩ
1.5
550
383kΩ
1.2
500
787kΩ
1.0
500
787kΩ
0.8
450
Open
0.6
450
Open

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Synchronization with RT/CLK pin
RT/CLK pin can also be used to synchronize the THPM4301A to an external system clock, as shown in Fig. 35. To
implement the synchronization feature, a clock signal with on time of at least 75ns should be applied to the RT/CLK
pin. The logic zero level of the clock signal must be lower than 0.6V and the logic high level of the clock signal mustbe higher than 1.6V. The synchronization frequency range is between 450kHz and 750kHz.
The rising edge of the phase node (PHASE) will be synchronized to the falling edge of RT/CLK pin.

THPM4301A

Fig. 35 Synchronizing to a System Clock

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Over-Current Protection
A hiccup current limiting function is provided in the THPM4301A to protect against output overload or short-circuit.
During an over-current condition, the load current is initially limited to approximately 9A and the output voltage isreduced to approximately 0.8V as shown in Fig. 36. If the over-current condition is not removed within approximately
1ms, the module will be shut down, as shown in Fig. 37. [Please note that the time scale is different for these two
figures.

Fig. 36 Over-current Limiting

Fig. 37 Hiccup Mode Current Limit Shut-down

When the over-current condition is removed, the output voltage recovers automatically to the nominal voltage, as
shown in Fig. 38. If the over-current condition is not removed, the power module operates in hiccup mode, as shownin Fig. 39. The hiccup period is about 25ms.

Fig. 38 Recovery from Over-current Shut-down

Fig. 39 Hiccup Mode Current Limit Restart
into Short-Circuit

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Input protection
In most applications, the input power source provides current limiting (typically fold-back or hiccup mode) and aslong as the average fault current is limited to approximately 10A or less, no further protection is required.
If the THPM4301A is powered from a battery or other high current source, it is recommended to include an externalfuse (maximum 10A) in the input to the module. The THPM4301A includes full protection against output overcurrent
or short-circuit, and the fuse will not operate under any output overload condition.

Thermal Considerations
The absolute maximum junction temperature is 150°C but it is recommended to keep the operating temperature well
below this value. Maximum recommended case temperature is 115°C, which corresponds to a junction temperatureof approximately 125°C.
The thermal resistance from case to ambient (θCA) depends on the PCB layout as well as the amount of cooling airflow.
When mounted on the EVM, θCA is approximately 15°C/watt in still air.
THPM4301A implements an internal thermal shutdown to protect itself if the junction temperature of the power
MOSFET exceeds 170°C. The thermal shutdown forces the module to stop switching when the junction temperature
exceeds the thermal shutdown threshold. Once the die temperature reduces by about 15°C, the module restarts
automatically.

Layout Considerations
To achieve the best electrical and thermal performance, an optimized PCB layout is required. Some considerations
for the PCB layout are:








Use large copper areas for power planes (VIN, VOUT, and especially PGND) to minimize conduction loss andthermal stress.
Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.
Place any additional output capacitors between the main ceramic capacitor and the load.
Connect the AGND and PGND copper areas at a single point, preferable under the AGND pin of the module.
Place RSENSE, RT, and CSS as close as possible to their respective pins.
Do not connect the PHASE pin to any other components.
Use multiple vias to connect the power planes to internal layers.

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Package dimensions and PCB pads
ALL DIMENSIONS IN MILLIMETERSFLATNESS OF LGA PLANE: MAX 0.1mm

3.00
2.60

11.20
10.80

9.30
8.90

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THPM4301A_Rev.1.11_E

Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s design.
THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note even if errors oromissions should be found in this material, THine may not be able to correct them immediately.
3. This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer or disclosing to third
parties the contents of this material without THine’s prior written permission is prohibited.
4. THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE RELATING TO
INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISING OUT OF THIS PRODUCT,EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTES SUCCESSFULLY PROVED BY THE USER THATSUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE, HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINEACCEPTS NO LIABILITY FOR SUCH DAMAGE OR LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.
5. This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear power control
device, or medical device related to critical care, excluding when this product is specified for automotive use by THine and used it for that
purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of the uses set forth above.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which isinevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe design principles such as redundant or
error preventive design applied to the use of the product so as not to have our product cause any social or public damage.
7. This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if subjected toelectrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth ground must be provided toanything in contact with the product, including any operator, floor, tester and soldering iron.
8. Please note that this product is not designed to be radiation-proof.
9. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for
performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s request, testingof all functions and performance of the product is not necessarily performed.
10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability whatsoever
for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign
Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America on export or transitof this product. This product is prohibited for the purpose of developing military modernization, including the development of weapons ofmass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the
product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to
implement safety measures by adding protection devices, such as fuses. THine accepts no liability whatsoever for any damage or loss
caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual property rights
concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user for any intellectual property
right or other proprietary right now or in the future owned by THine or THine’s licensor. The user must enter into a license agreement with
THine or THine’s licensor to be granted of such license or right.

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https://www.thine.co.jp

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