THCV242A-P_ Rev.4.11_E

THCV242A-P
SerDes receiver with bi-directional transceiver

1.

General Description

2.




THCV242A-P is designed to support 8Mpixel/4K
60fps RAW10 uncompressed video data over long
length 100ohm differential STP or single-end 50ohm
Coaxial cable with several in-line connectors between
camera and processor by V-by-One® HS.
THCV242A-P supports a MIPI CSI-2. Each CSI-2
data lane can transmit up to 1.5Gbps/lane with single
clock pair (1st port) output or up to 1.2Gbps/lane
with dual clock outputs.
One high-speed V-by-One® HS lane can transmit up
to 1080p60fps. The maximum serial data rate is
4Gbps/lane. 2nd input lane supports HDR large
amount of data or camera switch experience.
THCV242A-P is capable to control and monitor
remote camera module from MPU via GPIO or
1Mbps 2-wire serial interface.
Several fault and error detection function including
CRC provides hardware functional safety design.

3.











Features
MIPI CSI-2 with 1,2 or 4-lane output
MIPI D-PHY supports 80Mbps~1.5Gbps
Video formats: RAW8/10/12/14/16/20,
YUV422/420, RGB888/666/565, JPEG, Userdefined generic 8-bit
V-by-One® HS 400Mbps~4Gbps x2lane
V-by-One® HS standard version1.5
Video stream switch and copy/distribution
Frame sync remote supply scheme for multiple
camera stream synchronization
Wide range IO voltage from 1.7V to 3.6V
2-wire serial interface 1Mbps bridge function
Remote GPIO/UART control and monitoring
Error detection including CRC and notification
QFN64 9x9mm 0.5mm pitch Exp-pad package

Block Diagram
MIPI CSI-2
Data Tx 4-lane
Clock Tx 2-port

THCV242A-P

MTX0P

V-by-One® HS
Main-Link
Rx 2-lane

MTX0N
MTX1P

RX0P

Sub-Link 2-lane

CSI2 / Formatter

RX1N

Deserializer

RX1P

MTX1N
MTXCLK0P
MTXCLK0N
MTX2P
MTX2N
MTX3P

CDR

RX0N

MTX3N

RCM0P
MTXCLK1P

RCM0N

MTXCLK1N
Settings
RCM1P
RCM1N

Controls

GPIO
2-wireserial I/F

OSC

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THCV242A-P_ Rev.4.11_E
Contents page
1.

General Description ......................................................................................................................................... 1

2.

Features ........................................................................................................................................................... 1

3.

Block Diagram ................................................................................................................................................ 1

4.

Pin Configuration ............................................................................................................................................ 4

5.

Pin Description ................................................................................................................................................ 5

6.

Functional Description .................................................................................................................................... 6
6.1.

Functional Overview ............................................................................................................................... 6

6.2.

V-by-One® HS ........................................................................................................................................ 7
V-by-One® HS input setting ........................................................................................................... 7
MPRF (Main-Link PRivate Format) ............................................................................................... 9
V-by-One® HS standard format .................................................................................................... 10
Link Status (HTPDN/LOCKN) ..................................................................................................... 14

6.3.

Local, Remote and Remote Slave Register Programming .................................................................... 16
2-wire serial I/F slave Device ID ................................................................................................... 16
2-wire serial Read/Write access to local Register.......................................................................... 17
2-wire serial I/F Watch Dog Timer ................................................................................................ 18
Sub-Link setting ............................................................................................................................ 19
Sub-Link 2-wire Read/Write access to remote Register ................................................................ 20
6.3.5.1.

Sub-Link 2-wire Set and Trigger mode ................................................................................. 20

6.3.5.2.

Sub-Link 2-wire Pass Through mode .................................................................................... 24

Sub-Link transaction time accuracy Improvement ........................................................................ 28
6.4.

GPIO setting .......................................................................................................................................... 29
Register GPIO ............................................................................................................................... 30
Through GPIO ............................................................................................................................... 31
GPIO as secondary 2-wire port ..................................................................................................... 32

6.5.

MIPI ...................................................................................................................................................... 33
Deserializer and CSI-2 Formatter .................................................................................................. 33
6.5.1.1.

PLL setting ............................................................................................................................ 33

6.5.1.2.

Video stream switch and copy/distribution............................................................................ 35

Header/Packet/Sync Pre-processing .............................................................................................. 36
MIPI output setting ........................................................................................................................ 38
MIPI CSI-2 Virtual Channel .......................................................................................................... 41
MIPI Line Start/Line End code output setting ............................................................................... 43
Multiple camera synchronization Frame Vsync supply ................................................................ 43
6.6.

Status monitoring, Interrupt and Error Detection .................................................................................. 46

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THCV242A-P_ Rev.4.11_E
Internal Error / status signal monitoring pin output....................................................................... 46
Internal Error / status signal monitoring register ........................................................................... 49
Interrupt monitoring ...................................................................................................................... 50
Register Auto Checksum diagnosis ............................................................................................... 51
6.7.

Power On Sequence............................................................................................................................... 52

6.8.

Lock / Re-Lock Sequence ..................................................................................................................... 53

7.

Absolute Maximum Ratings .......................................................................................................................... 54

8.

Recommended Operating Conditions............................................................................................................ 54

9.

Consumption Current .................................................................................................................................... 55

10.

DC Specifications ...................................................................................................................................... 56

10.1.

LVCMOS DC Specifications............................................................................................................. 56

10.2.

CML Receiver DC Specifications ..................................................................................................... 56

10.3.

CML Bi-directional Buffer DC Specifications .................................................................................. 57

10.4.

MIPI Transmitter DC Specifications ................................................................................................. 57

11.

AC Specifications ...................................................................................................................................... 58

11.1.

General AC Specifications .................................................................................................................... 58

11.2.

CML Receiver AC Specifications ......................................................................................................... 58

11.3.

CML B-directional Buffer AC Specifications ....................................................................................... 58

11.4.

2-wire serial Slave AC Specifications ................................................................................................... 58

11.5.

MIPI Transmitter AC Specifications ..................................................................................................... 59

12.

Package...................................................................................................................................................... 60

13.

Notices and Requests................................................................................................................................. 61

MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions.

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THCV242A-P_ Rev.4.11_E

VDDIO1

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

INT1

INT0

AIN1

AIN0

SDA

SCL

VDDIO1

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

Pin Configuration

48
ERR0

49

32 EXTSYNC

ERR1

50

31

PDN

30

VDDPLLTHCV242A-P

VDDCORE 51
VDDRX

52

29

VDDTX

RX0N

53

28

MTX3P

RX0P

54

27

MTX3N

VSSRX

55

26

MTX1P

RX1N

56

25

MTX1N

RX1P

57

VDDRX

58

23 MTXCLK0N

RSVDL0

59

22

MTX0P

RSVDL0

60

21

MTX0N

VSSRX

61

20

MTX2P

RSVDL0

62

19

MTX2N

RSVDL063

18 MTXCLK1P

VDDRX

64

17 MTXCLK1N(TOP VIEW)
65 EXPGND

24 MTXCLK0P

4

16
VDDTX

VDDCORE 15

14
RSVDL2

8
RSVDL2RSVDT1L2 13

7
RSVDL2RSVDT2H2 12

6
RCM1P

11

5
RCM1N

VDDIO2

4
RCM0P

10

3
RCM0N

RSVDL2

2
VDDIO2

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91
VDDCORE●RSVDL2

4.

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THCV242A-P_ Rev.4.11_E

5.

Pin Description
Pin Name
RX0P/NPin #54, 53type*
CI

Description
V-by-One® HS Input lane0

RX1P/N

57, 56CI

V-by-One® HS Input lane1

RCM0P/N

4, 3

CB

CML Bi-directiona Input/Output (Sub-Link).

RCM1P/N6, 5

CB

CML Bi-directiona Input/Output (Sub-Link).

MTX0P/N

22, 21MO

MIPI differential data outputs lane0

MTX1P/N26, 25MO

MIPI differential data outputs lane1

MTX2P/N

20, 19MO

MIPI differential data outputs lane2

MTX3P/N

28, 27MO

MIPI differential data outputs lane3

MTXCLK0P/N

24, 23MO

MIPI differential clock outputs lane0

MTXCLK1P/N

18, 17MO

MIPI differential clock outputs lane1

RSVDT1L2

13

I

Reserved pin, Must be tied to Ground for normal operation.

RSVDT2H2

12

I

PDN

31

IL

Reserved pin. Must be tied to VDDIO2 for normal operation.
Power Down (User Power On Reset control must be
reuiquired.)
0: Power Down Mode
1: Normal Operation

AIN1

37

IL

AIN0

36

IL

Device Address Setting for 2-wire Serial Interface[AIN1:AIN0]=00: ID=7'h0B[AIN1:AIN0]=01: ID=7'h34[AIN1:AIN0]=10: ID=7'h77[AIN1:AIN0]=11: ID=7'h65

SCL

34

B

2-wire Serial Interface clock line

SDA

35

B

2-wire Serial Interface data line

GPIO0

40

B

General Purpose Input/Output

GPIO1

41

B

General Purpose Input/Output

GPIO2

42

B

General Purpose Input/Output

GPIO3

43

B

General Purpose Input/Output

GPIO4

44

B

General Purpose Input/Output

GPIO5

45

B

General Purpose Input/Output

GPIO6

46

B

General Purpose Input/Output

GPIO7

47

B

General Purpose Input/Output

INT0

38

O

INT1

39

O

Interrupt signal output.
It must be connected w ith a pull-up resistor.
0 : Interrupt occurred
1 : Steady state

ERR0

49

O

Internal Error / status signal monitoring output

ERR1

50

O

Internal Error / status signal monitoring output

EXTSYNC

32

B

External Sync input/output for multiple camera syncronization

RSVDL0RSVDL2
VDDIO159, 60, 62, 63
7, 8, 9, 10, 14
33, 48I
I
PReserved Pins, Must be tied to ground for normal operation.
Reserved Pins, Must be tied to ground for normal operation.
Power Supply for CMOS I/O

VDDIO2

2,11

PPower Supply for Sub-Link I/O

VDDCORE

1,15,51

P

Power Supply for Digital Circuit

VDDRX

52,58,64

PPower Supply for Analog Circuit

VSSRX

55,61

G

GND for Analog Circuit

VDDTX

16,29

P

Power Supply for Analog Circuit

VDDPLL30

PPower Supply for Analog Circuit

EXPGND
65
G
Exposed GND Pad*type symbol ; MO=MIPI Output, CI=CML Input, CB=CML Bi-directional input/output
IL=Low Speed LVCMOS Input, I=Input, O=LVCMOS Output, B=LVCMOS Bi-directional input/output
P=Power, G=Ground

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THCV242A-P_ Rev.4.11_E

6.

Functional Description

6.1.

Functional Overview

THCV242A-P can receive CML video signal transmitted over 15m length and encode it to MIPI CSI-2 format.
With High Speed CML SerDes, high reliability and robustness encoding scheme and CDR (Clock and Data
Recovery) architecture, the THCV242A-P enables to receive RAW/YUV/RGB/JPEG/Generic8bit data throughMain-Link by single 100ohm differential pair or 50ohm Coax cable with minimal external components. In addition,
THCV242A-P has Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO
signals and also HTPDN/LOCKN signals for Main-Link through the other 1-pair of CML-Line. The THCV242AP system is able to watch remote devices and to control them via 2-wire serial interface or GPIOs. They also canreport interrupt events caused by change of remote device statuses and internal statuses such as CRC error.

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THCV242A-P_ Rev.4.11_E
6.2.

V-by-One® HS
V-by-One® HS input setting

THCV242A-P has a V-by-One® HS receiver and it can be connected a V-by-One® HS transmitter via transmission
line divided by AC-coupled.
V-by-One® HS
Transmitter

V-by-One® HS
Reciever
Vbias

50ohm

50ohm

50ohm

50ohm

Zdiff=100ohm

GND

Figure 1.

V-by-One® HS connection scheme (differential transmission case)

Setting of V-by-One® HS input format can be configurable by 2-wire access to internal register.

Table 1. V-by-One® HS input format setting (all lanes)
Address
0x1012

bit Register Name
[7:5] reserved[4] R_RGB565_ON_L0

width
3
1

R/W
R/W

init
1'h0

[3:0] R_VX1_LANE_FMT0

4

R/W

4'h0

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Description<this regiseter is valid only when 0x1012[3:0]=0x1>
Main-Link Input Data Format Setting2 for all lane
0x0: RGB888
0x1: RGB565
Main-Link Input Data Format Setting for all lane
0x0: MPRF (Main-Link PRivate Format)
0x1: RGB888 or RGB565
0x2: YUV422 - Normal Mode1
0x3: YUV422 - Normal Mode2
0x4: YUV422 - Normal Mode3
0x5: YUV422 - Demux Mode1
0x6: YUV422 - Demux Mode2
0x7: RAW8 - Normal Mode1
0x8: RAW8 - Normal Mode2
0x9: RAW8 - Demux Mode1
0xA: RAW10 - Normal Mode1
0xB: RAW10 - Demux Mode1
0xC: RAW10 - Demux Mode2
0xD: RAW12 - Normal Mode1
0xE: RAW12 - Demux Mode1
0xF: RAW12 - Demux Mode27

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THCV242A-P_ Rev.4.11_E

Table 2. V-by-One® HS input format setting (Lane 0)
Address
0x1010bit Register Name
[7:6] R_MLINK_NHSEL0

width
2

R/W
R/W

init
2'h2

[5:4] R_MLINK_COL0

2

R/W

2'h1

Description
V-by-One® Main-Link Mode Select (for Lane0)0x2: V-by-One® HS standard mode
Other: Reserved
V-by-One® Main-Link Byte Mode Select (for Lane0)
0x1: 3Byte mode
0x2: 4Byte mode
Other: Reserved* use case setting example
MPRF : 0x2
RGB888 or RGB565 : 0x1
YUV422 - Normal Mode1 : 0x1
YUV422 - Normal Mode2 : 0x1
YUV422 - Normal Mode3 : 0x1
YUV422 - Demux Mode1 : 0x2
YUV422 - Demux Mode2 : 0x2
RAW8 - Normal Mode1 : 0x1
RAW8 - Normal Mode2 : 0x1
RAW8 - Demux Mode1 : 0x2
RAW10 - Normal Mode1 : 0x1
RAW10 - Demux Mode1 : 0x2
RAW10 - Demux Mode2 : 0x1
RAW12 - Normal Mode1 : 0x1
RAW12 - Demux Mode1 : 0x2
RAW12 - Demux Mode2 : 0x1

Table 3. V-by-One® HS input format setting (Lane 1)
Address
0x1014

bit Register Name
[7:6] R_MLINK_NHSEL1

width
2

R/W
R/W

init
2'h2

[5:4] R_MLINK_COL1

2

R/W

2'h1

Description
V-by-One® Main-Link Mode Select (for Lane1)
0x2: V-by-One® HS standard mode
Ohter: Reserved
V-by-One® Main-Link Byte Mode Select (for Lane1)
0x1: 3Byte mode
0x2: 4Byte mode
Other: Reserved* use case setting example
MPRF : 0x2
RGB888 or RGB565 : 0x1
YUV422 - Normal Mode1 : 0x1
YUV422 - Normal Mode2 : 0x1
YUV422 - Normal Mode3 : 0x1
YUV422 - Demux Mode1 : 0x2
YUV422 - Demux Mode2 : 0x2
RAW8 - Normal Mode1 : 0x1
RAW8 - Normal Mode2 : 0x1
RAW8 - Demux Mode1 : 0x2
RAW10 - Normal Mode1 : 0x1
RAW10 - Demux Mode1 : 0x2
RAW10 - Demux Mode2 : 0x1
RAW12 - Normal Mode1 : 0x1
RAW12 - Demux Mode1 : 0x2
RAW12 - Demux Mode2 : 0x1

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THCV242A-P_ Rev.4.11_E
MPRF (Main-Link PRivate Format)
MPRF format encoding preserves original data packet input to V-by-One® HS transmitter and output the data
packet from THCV242A-P. The counterpart transmitter must have installed MPRF format decoder like
THCV241A-P because MPRF is not standard format.
Input V-by-One® HS Byte Mode is 4Byte Mode.
Video formats: RAW8/10/12/14/16/20, YUV422/420, RGB888/666/565, JPEG, and User-defined generic 8-bit
are all supported with MPRF.

CMOS Sensor

Original
Data packet(format,payload, etc.)

THCV241A-P

Figure 2.

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Main-Link
MPRF
format

THCV242A-P

Preserved
Data packet(format,payload, etc.)

Processor
in a SoC

MPRF (Main-Link PRivate Format)

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THCV242A-P_ Rev.4.11_E
V-by-One® HS standard format
THCV242A-P input format capabilities as receiver are shown as follows. D[31:0] indicates V-by-One® HS
standard version1.5 UnPacker packet definition. Data can be transmitted normally only when both transmitter andreceiver are set to the same available format. Some of the THCV242A-P format may not be supported by particularcounterpart transmitter because THCV242A-P prepares multiple formats that suit to multiple transmitter devices
alternatives.

Table 4. V-by-One® HS input data mapping format (1/4)
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]RGB888
0
0
0
0
0
0
0
0
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]

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Normal Mode1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]Normal Mode2
0
0
0
0
0
0
0
0
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]

10

YUV422
Normal Mode3
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
0
0
0
0
0
0
0
0
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]Demux Mode1
Y[7](1st pixel)
Y[6](1st pixel)
Y[5](1st pixel)
Y[4](1st pixel)
Y[3](1st pixel)
Y[2](1st pixel)
Y[1](1st pixel)
Y[0](1st pixel)
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Y[7](2nd pixel)
Y[6](2nd pixel)
Y[5](2nd pixel)
Y[4](2nd pixel)
Y[3](2nd pixel)
Y[2](2nd pixel)
Y[1](2nd pixel)
Y[0](2nd pixel)
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]

Demux Mode2
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Y[7](1st pixel)
Y[6](1st pixel)
Y[5](1st pixel)
Y[4](1st pixel)
Y[3](1st pixel)
Y[2](1st pixel)
Y[1](1st pixel)
Y[0](1st pixel)
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Y[7](2nd pixel)
Y[6](2nd pixel)
Y[5](2nd pixel)
Y[4](2nd pixel)
Y[3](2nd pixel)
Y[2](2nd pixel)
Y[1](2nd pixel)
Y[0](2nd pixel)

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THCV242A-P_ Rev.4.11_E

Table 5. V-by-One® HS input data mapping format (2/4)
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW8
Normal Mode2
0
0
0
0
0
0
0
0
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)
0
0
0
0
0
0
0
0
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)

Normal Mode1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)

11

Demux Mode1
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)
RAW[7] (4th pixel)
RAW[6] (4th pixel)
RAW[5] (4th pixel)
RAW[4] (4th pixel)
RAW[3] (4th pixel)
RAW[2] (4th pixel)
RAW[1] (4th pixel)
RAW[0] (4th pixel)
RAW[7] (3rd pixel)
RAW[6] (3rd pixel)
RAW[5] (3rd pixel)
RAW[4] (3rd pixel)
RAW[3] (3rd pixel)
RAW[2] (3rd pixel)
RAW[1] (3rd pixel)
RAW[0] (3rd pixel)

THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E

Table 6. V-by-One® HS input data mapping format (3/4)
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW10
Demux Mode1
0
0
0
0
0
0
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](1st pixel)
RAW[2](1st pixel)
0
0
0
0
0
0
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)

Normal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[1]
RAW[0]
RAW[9]
RAW[8]
RAW[7]
RAW[6]
RAW[5]
RAW[4]
RAW[3]
RAW[2]

12

Demux Mode2
0
0
0
0
0
0
0
0
0
0
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](1st pixel)
RAW[2](1st pixel)
00RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)

THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E

Table 7. V-by-One® HS input data mapping format (4/4)
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW12
Demux Mode10000RAW[3](1st pixel)
RAW[2](1st pixel)
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[11](1st pixel)
RAW[10](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
0000RAW[3](2nd pixel)
RAW[2](2nd pixel)
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[11](2nd pixel)
RAW[10](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)

Normal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[3]
RAW[2]
RAW[1]
RAW[0]
RAW[11]
RAW[10]RAW[9]
RAW[8]
RAW[7]
RAW[6]
RAW[5]
RAW[4]

13

Demux Mode2
0
0
0
0
0
0
0
0
RAW[3](1st pixel)
RAW[2](1st pixel)
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[11](1st pixel)
RAW[10](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[11](2nd pixel)
RAW[10](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)

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THCV242A-P_ Rev.4.11_E
Link Status (HTPDN/LOCKN)
Hot-Plug Function
HTPDN indicates Main-Link connect condition between Transmitter and Receiver. HTPDN of Transmitter side
is high when Receiver is not active or not connected. Then Transmitter can enter into power down mode. HTPDN
is set to Low by the Receiver when Receiver is active and connects to the Transmitter, and then Transmitter must
start up and transmit CDR training pattern for link training. HTPDN is open drain output at the receiver side.
Transmitter side needs Pull-up resistor.
There is an application option to omit HTPDN connection between Transmitter and Receiver. In this case,
HTPDN at Transmitter side should always be at Low.

Lock Detect Function
LOCKN indicates whether CDR PLL of Main-Link is in lock status or not. LOCKN at Transmitter input is set
to High by pull-up resistor when Receiver is not active or in CDR PLL training. LOCKN is set to Low by Receiver
when CDR lock is completed. After that the CDR training mode finishes and then Transmitter shifts to the normal
mode. LOCKN of Receiver is open drain. Transmitter side needs pull-up resistor.
When an application omits HTPDN, LOCKN signal should only be considered with HTPDN pulled low byReceiver.

V-by-One®
HS Tx

THCV242A-P

30kΩ

Vcc
(Tx side)30kΩ

V-by-One®
HS Tx

30kΩ

Vcc
(Tx side)

THCV242A-P

HTPDN

ERRy
(HTPDN)

HTPDN

HTPDN

LOCKN

ERRx
(LOCKN)

LOCKN

ERRx
(LOCKN)

With HTPDN connect

Figure 3.

Without HTPDN connect

Physical wire connection for wired Hot-plug and Lock detect scheme

It will need same GND potential reference between transmitter and receiver device to connect HTPDN andLOCKN pins directly like above. HTPDN and LOCKN can also be transmitted via Sub-Link without physicalwire connection. Assignment can be configurable by 2-wire access to internal register.

Copyright©2023 THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E

Table 8. HTPDN/LOCKN register
Address
0x0019bit Register Name
[7:4] ReservedL[3:2] R_LOCKN_LN1_SEL

width
4
2

R/W
RW
RW

Init
4'h0
2'h0

[1:0] R_LOCKN_LN0_SEL

2

RW

2'h0

Copyright©2023 THine Electronics, Inc.

Description
must be left 0x0 (default setting)<this regiseter is valid when 0x0010[3:0]=0x1 or 0x2 or 0x3>
Select the source signal to be transmitted as LOCKN and HTPDN via Sub-Link
Lane10x0: LOCKN1
0x1: LOCKN0 or LOCKN1
0x2: Reserved
0x3: LOCKN and HTPDN signal level are LOW forcibly*LOCKN1: LOCKN signal of V-by-One(R) HS Lane1 (RX1P/RX1N)*HTPDN of the same lane as above set LOCKN lane is used
<this regiseter is valid when 0x0010[3:0]=0x1 or 0x2 or 0x3>
Select the source signal to be transmitted as LOCKN and HTPDN via Sub-Link
Lane0
0x0: LOCKN0
0x1: LOCKN0 or LOCKN1
0x2: Reserved
0x3: LOCKN and HTPDN signal level are LOW forcibly*LOCKN0: LOCKN signal of V-by-One(R) HS Lane0 (RX0P/RX0N)*HTPDN of the same lane as above set LOCKN lane is used15

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THCV242A-P_ Rev.4.11_E
6.3.

Local, Remote and Remote Slave Register Programming
2-wire serial I/F slave Device ID

To use basic functions, initialization, GPIO (General Purpose Input/Output), fault/error detection, and interrupt
function, 2-wire serial I/F enables to access registers. AIN<1:0> pin determines 2-wire slave Device ID setting.

Table 9. 2-wire serial I/F Device ID select by AIN pin
Pin Name
AIN1

AIN0

Description
Device Address Setting for 2-wire Serial Interface[AIN1:AIN0]=00: ID=7'h0B[AIN1:AIN0]=01: ID=7'h34[AIN1:AIN0]=10: ID=7'h77[AIN1:AIN0]=11: ID=7'h65

As an additional method, 2-wire slave Device ID setting can be changed from default value by register setting.

Table 10. 2-wire serial I/F Device ID select by register setting
Address
0x0030bit Register Name
[7:0] R_2WIRE_SADR

width
8

R/W
RW

Init
8'h00

Description
2-wire slave device address setting[7] 2-wire slave device address control
0x0: 2-wire slave device addr. is set by AIN1 and AIN0 pin
0x1: 2-wire slave device addr. is set by following register [6:0]<this regiseter is valid when 0x0030[1:0]=0x1>[6:0] 2-wire slave device address value for register control

Copyright©2023 THine Electronics, Inc.

16

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THCV242A-P_ Rev.4.11_E
2-wire serial Read/Write access to local Register
HOST MPU can directly access THCV242A-P local register by 2-wire serial I/F.

THCV242A-P
Sub-Link Block
Sub-Link
Master2-wire
Slave

SCL
SDA

Host
MPU

Register

AIN<1:0> = User SelectFigure 4.

Host to THCV242A-P local register access configuration

Figure 5.

2-wire serial I/F write to THCV242A-P local register protocol

Figure 6.

2-wire serial I/F read to THCV242A-P local register protocol

Copyright©2023 THine Electronics, Inc.

17

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THCV242A-P_ Rev.4.11_E
2-wire serial I/F Watch Dog Timer
2-wire Watch Dog Timer (WDT) is installed to monitor status.

Table 11. 2-wire WDT setting
Address
0x003B

0x003Cbit Register Name
[7:5] reserved[4] R_2WIRE_WD_EN

width
3
1

R/W
RW

Init
1'h1

[3:1] reserved[0] R_2WIRE_WD_OFFSET

3
1

RW

1'h1

[7:0] R_2WIRE_WD_TIM

8

RW

8'hFF

Copyright©2023 THine Electronics, Inc.

Description
2-wire I/F Watch Dog Timer (WDT) Enable
0x0: Disable
0x1: Enable<this register is valid only when 0x003B[4]=0x1>
2-wire I/F WDT Offset Time
0x1: 0x7FF (=d2047)
0x0: 0x3FF (=d1023)<this register is valid only when 0x003B[4]=0x1>
2-wire I/F WDT time
=64×{R_2WIRE_WD_TIM<7:0>+1}×{2WIRE_WDT_OffsetTime}×tOSC

18

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THCV242A-P_ Rev.4.11_E
Sub-Link setting
THCV242A-P has Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO
signals and also HTPDN/LOCKN signals for Main-Link. THCV242A-P is Sub-Link Master and connectable to
Sub-Link Slave device such as THCV241A-P.
Sub-Link Polling interval is controllable from about 20us to 800us, that may have relationships on fault/error
detection, interrupt, or other UART / GPIO transfer time designed on application. SSR (Sub-Link Status Read)
interval determines recovery quickness from 2-wire serial remote communication completion.

Table 12. Sub-Link Master protocol basic setting
Address
0x0004

bit Register Name
[7:3] reserved[2:0] R_SLINK_MODE

width
5
3

R/W
RW

Init
3'h1

0x0010[7:4] R_SLINK_EN

4

RW

4'h0

[3:0] R_SLINK_POL_EN

4

RW

4'hF

0x0011[7:4] reservedX[3:0] R_SLINK_WD_EN

4
4

RW
RW

4'hF
4'hF

0x001A[7:5] reserved[4] R_SLINK_POL_OFSET_EN

3
1

RW

1'h0

[3:2] reserved[1:0] R_SLINK_POL_TIM_UP

2
2

RW

2'h0

0x001B[7:0] R_SLINK_POL_TIM_DN

8

RW

8'h7C

0x001C[7:2] reserved[1:0] R_SLINK_SSR_TIM_UP[7:0] R_SLINK_SSR_TIM_DN

6
2
8

RW
RW

2'h0
8'hF9

0x001D

Copyright©2023 THine Electronics, Inc.

Description
Sub-Link basic protocol setting as Sub-Link Master0x1: 2-wire Set & Trigger mode1
0x3: 2-wire Pass Through mode1
Other: Reserved
Sub-Link Enable (*each bit setting)[7] ReservedL (must be set 0x0)
[6] ReservedL (must be set 0x0)[5] Sub-Link Enable for Lane1 (*)[4] Sub-Link Enable for Lane0 (*)
0x0: Sub-Link Disable
0x1: Sub-Link Enable
Sub-Link Polling Enable (*each bit setting)[3] ReservedL (must be set 0x0)
[2] ReservedL (must be set 0x0)
[1] Sub-Link Polling Enable for Lane1 (*)[0] Sub-Link Polling Enable for Lane0 (*)
0x0: Polling Disable
0x1: Polling Enablemust be left 0xF (default setting)
Sub-Link Watch Dog Timer (WDT) Enable (*each bit setting)[3] ReservedL (must be set 0x0)
[2] ReservedL (must be set 0x0)
[1] Sub-Link WDT Enable for Lane1 (*)[0] Sub-Link WDT Enable for Lane0 (*)
0x0: WDT Disable
0x1: WDT Enable<this regiseter is valid when 0x0010[3:0]=0x1 or 0x2 or 0x3>
Enable of shifting the Sub-Link Polling output timing
0x0: Disable
0x1: Enable
The Polling output timing of Sub-Link Lane1 is delayed by Sub-Link Pollinginterval x 1/4 from the Sub-Link Lane0.
<this regiseter is valid when 0x0010[3:0]=0x1 or 0x2 or 0x3>
Sub-Link Polling interval setting (min. 0x018, about 20us)<this regiseter is valid when 0x0010[3:0]=0x1 or 0x2 or 0x3>
Sub-Link Polling interval time=64×(256×R_SLINK_POL_TIM_UP<1:0>+R_SLINK_POL_TIM_DN<7:0>+1)×tOSC*No Polling when R_SLINK_POL_TIM_UP=0x0 and R_SLINK_POL_TIM_DN=0x0
Sub-Link SSR interval setting
Sub-Link SSR interval time=64×(256×R_SLINK_SSR_TIM_UP<1:0>+R_SLINK_SSR_TIM_DN<7:0>+1)×tOSC*No SSR when R_SLINK_SSR_TIM_UP=0x0 and R_SLINK_SSR_TIM_DN=0x019

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THCV242A-P_ Rev.4.11_E

To use GPIO (General Purpose Input/Output) pin, fault/error detection and interrupt function, “2-wire Set &Trigger mode1”, “2-wire Pass Through mode1” enables remote register access. THCV242A-P, Sub-Link Masterdevice has 2-wire serial slave block and can connect to HOST MPU. On the other hand, the counterpart Sub-Link
Slave device has 2-wire serial master block and can connect to remote side 2-wire serial slave devices.
HOST MPU can access register of Sub-Link Master device, Sub-Link Slave device and remote side 2-wire serial
slave devices.

Sub-Link 2-wire Read/Write access to remote Register
6.3.5.1.

Sub-Link 2-wire Set and Trigger mode

HOST MPU can access to Sub-Link Slave’s register via THCV242A-P as Sub-Link Master only by
THCV242A-P internal local register control and monitoring on 2-wire Set&Trigger mode1.

Sub-Link Slave Device

THCV242A-P as Sub-Link Master

Sub-Link Block

Sub-Link Block
Sub-Link
line

2-wireMaster

Sub-Link
Slave

Sub-Link
Master2-wire
Slave

SCL
Host
MPU

SDA
INT

Register

Register(MSSEL=1)

Figure 7.

Interrupt signal

Triggered access by Sub-Link Master
Access from/to HOST

AIN<1:0> = User SelectHost MPU to Sub-Link Slave Register via THCV242A-P access configuration

HOST MPU can access to remote side 2-wire serial slave register via THCV242A-P as Sub-Link Master only
by THCV242A-P internal local register control and monitoring on 2-wire Set&Trigger mode1.

Sub-Link Slave Device

THCV242A-P as Sub-Link Master

Sub-Link Block2-wireSlave
Device#a

SCL
SDA

2-wireMaster

Sub-Link Block
Sub-Link
Slave

Sub-Linkline

SCL

2-wire
Slave

Host
MPU

SDA
INT

・
・

Register2-wireSlave
Device#b(MSSEL=1)

Figure 8.

Sub-Link
MasterRegister

Triggered access by Sub-Link Master
Access from/to HOST

Interrupt signal

AIN<1:0> = User SelectHost MPU to remote 2-wire slave devices via THCV242A-P access configuration

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20

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THCV242A-P_ Rev.4.11_E

In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial accessand Sub-Link Slave internal bus access or remote side 2-wire serial access.
R_2WIRE_CLKSEN (Sub-Link Master side register, 0x00E2 bit0) selects whether 2-wire serial slave of SubLink Master perform clock stretching.
When R_2WIRE_CLKSEN = 1, Sub-Link Master device waits HOST MPU until Sub-Link Slave register accessor remote side 2-wire serial slave register access complete by clock stretching.
When R_2WIRE_CLKSEN = 0, Sub-Link Master device informs HOST MPU that Sub-Link Slave register
access or remote side 2-wire serial register access has completed by interruption (detectable on INT pin) without
clock stretching.

Figure 9.

Copyright©2023 THine Electronics, Inc.

Sub-Link Master 2-wire slave clock stretching operation

21

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THCV242A-P_ Rev.4.11_E

Table 13. 2-wire serial I/F Set& Trigger mode remote access control and monitoring local registers (1/2)
Address
0x00D0bit Register Name
[7:0] R_2WIRE_DATA0

width
8

R/W
RW

Init
8'h00

0x00D1[7:0] R_2WIRE_DATA1

8

RW

8'h00

0x00D2[7:0] R_2WIRE_DATA2

8

RW

8'h00

0x00D3[7:0] R_2WIRE_DATA3

8

RW

8'h00

0x00D4[7:0] R_2WIRE_DATA4

8

RW

8'h00

0x00D5[7:0] R_2WIRE_DATA5

8

RW

8'h00

0x00D6[7:0] R_2WIRE_DATA6

8

RW

8'h00

0x00D7[7:0] R_2WIRE_DATA7

8

RW

8'h00

0x00D8[7:0] R_2WIRE_DATA8

8

RW

8'h00

0x00D9[7:0] R_2WIRE_DATA9

8

RW

8'h00

0x00DA[7:0] R_2WIRE_DATA10

8

RW

8'h00

0x00DB[7:0] R_2WIRE_DATA11

8

RW

8'h00

0x00DC[7:0] R_2WIRE_DATA12

8

RW

8'h00

0x00DD[7:0] R_2WIRE_DATA13

8

RW

8'h00

0x00DE[7:0] R_2WIRE_DATA14

8

RW

8'h00

0x00DF[7:0] R_2WIRE_DATA15

8

RW

8'h00

0x00E0[7:1] R_2WIRE_DEVADR

7

RW

7'h00

[0]

1

RW

1'h0

[7] reserved[6:4] R_2WIRE_WADR_BYTE

1
3

RW

3'h0

[3:0] R_2WIRE_DATA_BYTE

4

RW

4'h0

0x00E1

R_2WIRE_WR

Copyright©2023 THine Electronics, Inc.

Description<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #0<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #1<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #2<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #3<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #4<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #5<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #6<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #7<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #8<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #9<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #10<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #11<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #12<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #13<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #14<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote write/read data #15<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote access target device address.
if target addr. = self addr.; access to Sub-Link slave internal registers,
else; access to remote side 2-wire serial slave devices externally connected to
Sub-Link slave<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote access write or read select0x0: Write
0x1: Read<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote device's sub address (Word Address, register address)
Byte width. Sub Address Byte width = R_2WIRE_WADR_BYTE<2:0>+1
0x0: 1Byte (= 8bit) sub address
0x1: 2Byte (=16bit) sub address
Other : Reserved<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F remote access data Byte number.
Byte Number = R_2WIRE_DATA_BYTE + 1 (e.g. 0x2 for 3Byte burst)[Write rule] R_2WIRE_WADR_BYTE+R_2WIRE_DATA_BYTE < 'd16
[Read rule] R_2WIRE_DATA_BYTE < 'd1622

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THCV242A-P_ Rev.4.11_E

Table 14. 2-wire serial I/F Set& Trigger mode remote access control and monitoring local registers (2/2)
Address
0x00E2

bit Register Name
[7:1] reserved[0] R_2WIRE_CLKSEN

width
7
1

R/W
RW

Init
1'h0

0x00E3[7:2] reserved[1:0] R_2WIRE_RD_LANE_SEL

6
2

RW

2'h0

0x00E4[7:4] reserved[3:0] R_2WIRE_WR_LANE_SEL

4
4

RW

4'hF

0x00E5[7:1] reserved[0] R_2WIRE_START

7
1

W

-

Copyright©2023 THine Electronics, Inc.

Description<this regiseter is valid only when 0x0004[2:0]=0x1>
2-wire serial I/F local response clock stretching Enable
0x0: Sub-Link Master (2-wire slave) No clock stretching
0x1: Sub-Link Master (2-wire slave) clock stretching Enable*2-wire Pass Through mode (R_SLINK_MODE=0x3) forces clock stretching
Enable<this regiseter is valid when 0x0004[2:0]=0x1 or 0x3>
Sub-Link read transaction lane select0x0: Read from Sub-Link Lane00x1: Read from Sub-Link Lane1
Other: Reserved<this regiseter is valid only when 0x0004[2:0]=0x1>
Sub-Link Write transaction lane select (multiple lanes can be written at the sametime) (*each bit setting)[3] ReservedL (must be set 0x0)
[3] ReservedL (must be set 0x0)
[1] Write for Sub-Link Lane1 (*)[0] Write for Sub-Link Lane0 (*)
0x0: Disable
0x1: Enable<this regiseter is valid only when 0x0004[2:0]=0x1>
0x1: 2-wire serial I/F remote access start trigger

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THCV242A-P_ Rev.4.11_E
6.3.5.2.

Sub-Link 2-wire Pass Through mode

Sub-Link Master 2-wire Pass Through mode1 can bridge original local 2-wire commands to remote side.
2-wire Pass Through mode1 uses 2-wire slave clock stretching scheme at local Sub-Link Master side. Host
MCU 2-wire master must be no problem with clock stretching wait from 2-wire slave.

Sub-Link Slave side processing protocol “Divided write/read” scheme divides 2-wire commands into
determined data Byte groups. Each data Byte groups are sent separately on remote side. Burst write/read accesstarget Sub-Address (Word-Address) is interpreted so that subsequent Sub-Address (Word-Address) from 2nd
group is automatically and properly incremented. As shown below, remote side 2-wire accesses are independent
each other by determined Byte, which are defined in R_2WIREPT_WA_BYTE and
R_2WIREPT_DATA_BYTE at R_2WIREPT1_PASS_MODE[1]=1.

Divided w rite access at R_2WIREPT1_PASS_MODE[1]=1 (case: 1Byte Word Addres s and 16Byte burs t 2-w ire w rite w ith R_2WIREPT_WA_BYTE=3'd1 and R_2WIREPT_DATA_BYTE=4'd8)

SP

ACK

…

WD15

Figure 10.

ACK+W: Write command indicator

WD9

WD：Write Data

AD：Word Address

ACK

SID：Slave Address（Device Address)

ACK：Acknow ledge

WD8

SP：Stop Condition

ST：Start Condition

ACK[ list of abbreviations ]

AD' *

ST

Bus Free

SID+W

SP

ACK

…

WD7

ACK

WD1

WD0

AD

ACK

ACK

ST

Bus FreeRemote 2-w ire line

SID+W

Sub-Link Slave side

Bus Free2-wire Pass Through mode1 Sub-Link Slave command Divided scheme

On address processing protocol “Assigned address & rename”, THCV242A-P 2-wire slave respond only to 2wire device address defined in R_2WIREPT1_PASS_ADRxy1 (x=Lane0 or Lane1, y=0/1/2/3) for remote Pass
Through operation. Otherwise, 2-wire commands are ignored except THCV242A-P itself address. The device
address can be renamed before remote send. The counterpart Sub-Link Slave internal register access is available
with R_2WIREPT1_PASS_ADRINx (x=Lane0 or Lane1) setting.
On address processing protocol “All Through”, THCV242A-P 2-wire slave respond basically all 2-wire device
address for remote Pass Through operation except THCV242A-P itself address. Additionally, Defined addresses
in R_2WIREPT2_NOPASS_ADRxz (x=Lane0 or Lane1, z=0/1/2/3/4/5/6/7) can be ignored by THCV242A-P.

Copyright©2023 THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E

Table 15. 2-wire serial I/F Pass Through mode remote access setting
Address
0x0031

bit Register Name
[7:2] reserved[1:0] R_2WIREPT_MODE

width
6
2

R/W
RW

Init
2'h0

Description<this regiseter is valid only when 0x0004[2:0]=0x3>
Sub-Link 2WIRE Pass Through mode setting[1]Pass Through processing protocol on Sub-Link Slave
0x0: Reserved
0x1: Divided Write & Divided Read
Transaction address and data Byte number are set as R_2WIREPT_WA_BYTE
and R_2WIREPT_DATA_BYTE.
[0]Pass Through 2WIRE device addrress processing
0x0: Address rename(rule as R_2WIREPT1_PASS_ADRxy0/1. x is Lane0 or Lane1, y=<3:0>)
0x1: All Through(exception definition of address to ignore as R_2WIREPT2_NOPASS_ADRxz.
x is Lane0 or Lane1, z=<7:0>)

0x0032[7] reserved[6:4] R_2WIREPT_WA_BYTE

1
3

RW

3'h0

[3:0] R_2WIREPT_DATA_BYTE

4

RW

4'h0

Copyright©2023 THine Electronics, Inc.

<this register is valid only when 0x0031[1]=0x1>
Sub-Link 2WIRE Pass Through Divided Write/Read Sub Address (WordAddress) Byte number setting
Byte Number = R_2WIREPT_WA_BYTE + 1
0x0: 1Byte (= 8bit) sub address
0x1: 2Byte (=16bit) sub address
Other: Reserved
Sub-Link 2WIRE Pass Through Divided Write/Read data Byte number per atransaction setting, Byte Number = R_2WIREPT_DATA_BYTE + 1(e.g. 0x2 for 3Byte per a transaction)*R_2WIREPT_WA_BYTE + R_2WIREPT_DATA_BYTE < d14 is required.

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THCV242A-P_ Rev.4.11_E

Table 16. 2-wire serial I/F Pass Through mode remote access setting (Lane0)
Address
0x0040bit Register Name
[7:0] R_2WIREPT1_PASS_ADR000

width
8

R/W
RW

Init
8'h00

0x0041[7:0] R_2WIREPT1_PASS_ADR001

8

RW

8'h00

0x0042[7:0] R_2WIREPT1_PASS_ADR010

8

RW

8'h00

0x0043[7:0] R_2WIREPT1_PASS_ADR011

8

RW

8'h00

0x0044[7:0] R_2WIREPT1_PASS_ADR020

8

RW

8'h00

0x0045[7:0] R_2WIREPT1_PASS_ADR021

8

RW

8'h00

0x0046[7:0] R_2WIREPT1_PASS_ADR030

8

RW

8'h00

0x0047[7:0] R_2WIREPT1_PASS_ADR031

8

RW

8'h00

0x0048[7:0] R_2WIREPT2_NOPASS_ADR00

8

RW

8'h00

0x0049[7:0] R_2WIREPT2_NOPASS_ADR01

8

RW

8'h00

0x004A[7:0] R_2WIREPT2_NOPASS_ADR02

8

RW

8'h00

0x004B[7:0] R_2WIREPT2_NOPASS_ADR03

8

RW

8'h00

0x004C[7:0] R_2WIREPT2_NOPASS_ADR04

8

RW

8'h00

0x004D[7:0] R_2WIREPT2_NOPASS_ADR05

8

RW

8'h00

0x004E[7:0] R_2WIREPT2_NOPASS_ADR06

8

RW

8'h00

0x004F[7:0] R_2WIREPT2_NOPASS_ADR07

8

RW

8'h00

0x0050[7:0] R_2WIREPT1_PASS_ADRIN0

8

RW

8'h00

Copyright©2023 THine Electronics, Inc.

Description<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane0 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane0 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane0 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane0 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane0 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane0 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane0 #3<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane0 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #0<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #1<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #2<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #4<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #5<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #6<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane0 #7<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through counterpart Sub-Link Slave internal register accessdedicated address for Lane026

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THCV242A-P_ Rev.4.11_E

Table 17. 2-wire serial I/F Pass Through mode remote access setting (Lane1)
Address
0x0060bit Register Name
[7:0] R_2WIREPT1_PASS_ADR100

width
8

R/W
RW

Init
8'h00

0x0061[7:0] R_2WIREPT1_PASS_ADR101

8

RW

8'h00

0x0062[7:0] R_2WIREPT1_PASS_ADR110

8

RW

8'h00

0x0063[7:0] R_2WIREPT1_PASS_ADR111

8

RW

8'h00

0x0064[7:0] R_2WIREPT1_PASS_ADR120

8

RW

8'h00

0x0065[7:0] R_2WIREPT1_PASS_ADR121

8

RW

8'h00

0x0066[7:0] R_2WIREPT1_PASS_ADR130

8

RW

8'h00

0x0067[7:0] R_2WIREPT1_PASS_ADR131

8

RW

8'h00

0x0068[7:0] R_2WIREPT2_NOPASS_ADR10

8

RW

8'h00

0x0069[7:0] R_2WIREPT2_NOPASS_ADR11

8

RW

8'h00

0x006A[7:0] R_2WIREPT2_NOPASS_ADR12

8

RW

8'h00

0x006B[7:0] R_2WIREPT2_NOPASS_ADR13

8

RW

8'h00

0x006C[7:0] R_2WIREPT2_NOPASS_ADR14

8

RW

8'h00

0x006D[7:0] R_2WIREPT2_NOPASS_ADR15

8

RW

8'h00

0x006E[7:0] R_2WIREPT2_NOPASS_ADR16

8

RW

8'h00

0x006F[7:0] R_2WIREPT2_NOPASS_ADR17

8

RW

8'h00

0x0070[7:0] R_2WIREPT1_PASS_ADRIN1

8

RW

8'h00

Copyright©2023 THine Electronics, Inc.

Description<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane1 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane1 #0<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane1 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane1 #1<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane1 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane1 #2<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through received "before rename" address for Lane1 #3<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through "after renamed" address to send for Lane1 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #0<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #1<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #2<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #3<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #4<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #5<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #6<this regiseters is valid only when 0x0031[0]=0x1>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through ignore address /otherwise All Through for Lane1 #7<this regiseters is valid only when 0x0031[0]=0x0>[7] ReservedL (must be set 0x0)
[6:0] 2WIRE Pass Through counterpart Sub-Link Slave internal register accessdedicated address for Lane127

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THCV242A-P_ Rev.4.11_E
Sub-Link transaction time accuracy Improvement
Sub-Link Polling timing can be controllable by GPI input. All Sub-Link lane transaction timing can bearranged.

Table 18. Sub-Link transaction time accuracy control
Address
0x0016

bit Register Name
[7:6] reserved[5:4] R_POL_TIM_CLR_EN

width
2
2

R/W
RW

Init
2'h0

1
3

RW

3'h0

[3] reserved[2:0] R_GPI_TRG_SEL

Description<this regiseter is valid when 0x0010[3:0]=0x1 or 0x2 or 0x3>
Polling Timer Clear/Mask setting
0x1: The polling timer is cleared when the inputted GPIO changes
0x2: The polling timer masked when inputted GPIO signal is high, and the pollingtransmission is outputted after inputted GPIO signal is falling.
<this regiseter is valid when 0x0010[3:0]=0x1 or 0x2 or 0x3>
Polling Timer Clear/Mask GPIO signal select0x0: GPIO0 (this setting is valid only when 0x1004[3:0]=0x3)
0x1: GPIO1 (this setting is valid only when 0x1004[7:4]=0x3)
Other: Reserved

Polling Timer Clear
Trigger GPI

Polling IntervalOne
polingCleared new
Polling Interval

Polling Interval

Sub-Link Master
Polling transaction
to all Sub-Link lanes
Ignored previous
Polling Interval

Polling Timer Mask
Trigger GPI

Polling IntervalOne
polingCleared new
Polling Interval

Polling Interval

Sub-Link Master
Polling transaction
to all Sub-Link lanes
Ignored previous
Polling Interval

Ignored previous
Polling Interval

Figure 11. Sub-Link transaction time accuracy control

Copyright©2023 THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E
6.4.

GPIO setting

Setting of GPIO can be configurable by 2-wire access to internal register.

Table 19. GPIO setting (1/2)
Address
0x10010x1002

bit Register Name
[7:4] R_GPIO7_MODE

width
4

R/W
R/W

init
4'h0

[3:0] R_GPIO6_MODE

4

R/W

4'h0

[7:4] R_GPIO5_MODE

4

R/W

4'h0

[3:0] R_GPIO4_MODE

4

R/W

4'h0

Copyright©2023 THine Electronics, Inc.

Description
GPIO7 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO6 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO5 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO4 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved29

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THCV242A-P_ Rev.4.11_E

Table 20. GPIO setting (2/2)
Address
0x10030x1004

bit Register Name
[7:4] R_GPIO3_MODE

width
4

R/W
R/W

init
4'h0

[3:0] R_GPIO2_MODE

4

R/W

4'h0

[7:4] R_GPIO1_MODE

4

R/W

4'h0

[3:0] R_GPIO0_MODE

4

R/W

4'h0

Description
GPIO3 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO2 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO1 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved
GPIO0 I/O Mode0x0: Disable
0x1: Programable GPO (Output Low)
0x2: Programable GPO (Output High)
0x3: Through GPI Mode
0x4: Through GPO Mode0x5: Second 2WIRE Mode (SCL)
0x6: Second 2WIRE Mode (SDA)
Other: Reserved

Register GPIO
GPIO output control are available with register.

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THCV242A-P_ Rev.4.11_E
Through GPIO
Local GPIO input is continuously reflected to remote GPIO output via Sub-Link polling. Bridging data aresampled every Sub-Link polling, whose basic interval is controlled by register R_SLINK_POL_TIM_UP/_DN.
Remote 2-wire access may become long transaction and could lengthen Through GPIO polling reflection interval.
Through GPIO input
to local Sub-Link device

Sub-Link Polling

Polling

Polling

Polling

Polling

Polling

Through GPIO output
from remote Sub-Link device
Sub-Link Polling interval

Figure 12. Through GPIO bridge sampling
As default setting with THCV231 as Sub-Link Slave communication (THCV242A-P as Sub-Link Master),
GPIO1 Sub-Link Polling bridges input to THCV231‘s GPIO4 through mode and GPIO0 Sub-Link Polling bridges
input to THCV231’s GPIO3 through mode respectively.
As default setting with THCV241A-P as Sub-Link Slave communication (THCV242A-P as Sub-Link Master),
GPIO0/1 are dedicated to GPI to Sub-Link Lane0. GPIO2/3 are dedicated to GPI to Sub-Link Lane1. GPIO2/3
are also dedicated to GPO from selected Sub-Link Lane.
THCV242A-P

THCV241A-P #0
Up stream

Lane0

GPIO1/GPIO0

GPIO1/GPIO0

Downstrea m

GPIO3/GPIO2
THCV241A-P #1
GPIO1/GPIO0

Up stream

Lane1

Downstrea m

GPIO3/GPIO2
GPIO3/GPIO2

GPIO3/GPIO2
R_RES_GP[3/2]_LN_SEL

Figure 13. Through GPIO via Sub-Link transaction assignment with THCV241A-P
Remote UART bridge is supported with Sub-Link Through GPIO input/output. Remote UART Tx and Rx
bridge baud rate is supposed to be designed against Sub-Link Polling interval to accommodate deterministic
jitter caused by intermittent Sub-Link communication timing.

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THCV242A-P_ Rev.4.11_E
GPIO as secondary 2-wire port
GPIO port can be secondary 2-wire port, which can accommodate dual 2-wire access from two processors.
If two 2-wire commands are inputted at the same time, the earlier command can be communicated and the latercommand are kept wait by clock stretching scheme.

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THCV242A-P_ Rev.4.11_E
6.5.

MIPI
Deserializer and CSI-2 Formatter
6.5.1.1.

PLL setting

PLL setting is required. PLL setting set R_PLL_SETTING[47:0] is related with Main-Link data-rate.

PLL Configuration
F(VCO)
F(Main-Link input)

Reference Divider

10-133MHz

x 1/RefDiv

500-1500MHz
PFD

1-7

VCO

1st Output Divider

2nd Output Divider

F(MIPI output)

x 1/OutDiv1

x 1/OutDiv2

80-1500MHz

1-7

1-7

F(PFD)> 10MHz

FeedBack Divider
x 1/FBDiv
20-130Figure 14. Reference clock supply basic method

PLL_SETTING[47:0] must be selected proper to meet below constraints.
Table 21. PLL constraints
symboldescription
F(IN) PLL input pixel clock frequency
RefDiv Reference Divider value
FBDiv FeedBack Divider value
OutDiv1 1st Output Divider value (OutDiv1 must be >= OutDiv2)
OutDiv2 2nd Output Divider value (OutDiv1 must be >= OutDiv2)F(PFD) PFD frequency
F(VCO) VCO frequency
F(OUT) PLL output pixel clock frequency

min
10
1
20
1
1
10
500
80

typ max unit
133 MHz
7
130
7
7
MHz
1500 MHz
1500 MHz

Pixel clock frequency made by PLL is calculated as below.
[PCLK.input] = Pixel clock recovered on V-by-One® HS per lane = [F(Main-Link input)] = F(IN)[F(Main-Link input)] = Main-Link data-rate per lane / (Byte mode x 8 x 10/8)

MIPI data-rate per lane (Mbps) = [F(MIPI output)] (MHz)= MIPI High Speed mode data-rate per lane

F(VCO) =[PCLK.output] = [F(MIPI output)] =[F(MIPI output)][F(Main-Link input)]=[F(Main-Link input)] x [FBDiv][RefDiv][F(Main-Link input)] x [FBDiv][RefDiv] x [OutDiv1] x [OutDiv2]= F(OUT)[FBDiv][RefDiv] x [OutDiv1] x [OutDiv2]MIPI High Speed mode DDR output clock per lane = [F(MIPI output)] / 2 (MHz)Copyright©2023 THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E

Table 22. PLL setting
Address
0x10210x10220x10230x10240x10250x1026

bit
[7:0]
[7:3]
[2:0]
[7]
[6:4]
[3]
[2:0]
[7:0]
[7:0]
[7:0]

Register Name
R_PLL_SETTING[47:40]
R_PLL_SETTING[39:35]
R_PLL_SETTING[34:32]
R_PLL_SETTING[31]R_PLL_SETTING[30:28]
R_PLL_SETTING[27]
R_PLL_SETTING[26:24]
R_PLL_SETTING[23:16]
R_PLL_SETTING[15:8]
R_PLL_SETTING[7:0]

width
8
5
3
1
3
1
3
8
8
8

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

init
8'h00
5'h00
3'h0
1'h0
3'h0
1'h0
3'h0
8'h00
8'h00
8'h00

Description
PLL setting value, Feedback Divider value (integer part)
PLL setting value (Must be set 0x00)
PLL setting value, Reference Divider value
PLL setting value (Must be set 0x0)
PLL setting value, OutDiv1 (OutDiv1 must be >= OutDiv2)
PLL setting value (Must be set 0x0)
PLL setting value, OutDiv2 (OutDiv1 must be >= OutDiv2)
PLL setting value, Feedback Divider value (decimal part MSB)PLL setting value, Feedback Divider value (decimal part)
PLL setting value, Feedback Divider value (decimal part LSB)

PLL setting must fulfill below frequency ratio rule.

Table 23. PLL frequency ratio rule
Format[F(MIPI output)] / [F(Main-Link input)]frequency ratio

MPRF

1*[Main-Link input lane#]*4*8/ [MIPI output lane#]

RGB888

3/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]

YUV422 Normal

2/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]

YUV422 Demux

1*[Main-Link input lane#]*4*8/ [MIPI output lane#]

RAW8 Normal

2/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]

RAW8 Demux

1*[Main-Link input lane#]*4*8/ [MIPI output lane#]

RAW10 Normal

10/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]

RAW10 Demux

20/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]

RAW12 Normal

12/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]

RAW12 Demux

24/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]

Below Table is Look Up Table example for typical cases.
Table 24. PLL setting Look up table example
index condition1
720p30fps RAW3
720p30fps YUV422
4
720p60fps RAW
51080p30fps RAW6
720p60fps YUV422
71080p30fps YUV422
8
720p60fps YUV422
9720p120fps RAW
101080p60fps RAW
11
720p120fps YUV422
121080p60fps YUV422
131080p120f ps RAW
15
720p30fps RAW
17
720p30fps YUV422
18
720p60fps RAW
191080p30fps RAW
20
720p60fps YUV422
211080p30fps YUV422

Main-Link input
742.5Mbps 1lane MPRF
750Mbps 1lane MPRF

MIPI output
594Mbps x1lane
600Mbps x1lane

1.114Gbps 1lane MPRF

445.5Mbps x2lane

1.485Gbps 1lane MPRF

594Mbps x2lane

1.485Gbps 1lane MPRF

594Mbps x2lane x2

2.2275Gbps 1lane MPRF

891Mbps x2lane

2.97Gbps 1lane MPRF

594Mbps x4lane

2.2275Gbps 2lane MPRF
990Mbps 1lane RAW12 Demux
1.6Gbps 1lane YUV422 Normal

891Mbps x4lane
594Mbps x1lane
640Mbps x1lane

1.485Gbps 1lane RAW12 Demux 445.5Mbps x2lane
2.97Gbps 1lane YUV422 Normal 594Mbps x2lane

Copyright©2023 THine Electronics, Inc.

Distribution
off
off
off
off
off
off
on
off
off
off
off
off
off
off
off
off
off
off

F(MLINK in)
18.562518.75
27.84375
27.84375
37.12537.12537.12555.6875
55.6875
74.25
74.25
55.687524.75
40
37.12537.125
74.25
74.25

34

F(VCO)
1188
1200
891
891
1188
1188
1188
891
891
1188
1188
891
594
640
891
891
1188
1188

F(MIPI out)
594
600
445.5
445.5
594
594
594
891
891
594
594
891
594
640
445.5
445.5
594
594

PLL[47:40]
0x40
0x40
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x18
0x20
0x30
0x30
0x20
0x20

PLL[39:32]
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x02
0x02
0x02
0x02
0x02
0x01
0x02
0x02
0x02
0x02
0x02

PLL[31:24]
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x11
0x11
0x21
0x21
0x11
0x11
0x11
0x21
0x21
0x21
0x21

PLL[23:16]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[15:8]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

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THCV242A-P_ Rev.4.11_E
6.5.1.2.

Video stream switch and copy/distribution

Setting of data stream handling can be configurable by 2-wire access to internal register.

Table 25. Data stream handling setting
Address
0x1501

bit Register Name
[7:5] reserved[4:0] R_MODE_NO

width
3
5

R/W
R/W

Init
3'h0
5'h00

Description
Main-Link input data stream handling mode number
0x00: CAM A : Main-Link Lane0 -> MIPI port00x01: CAM A : Main-Link Lane0 -> MIPI port0 and port1 (distribution)
0x02: CAM B : Main-Link Lane1 -> MIPI port00x03: CAM B : Main-Link Lane1 -> MIPI port0 and port1 (distribution)
0x08: CAM A : Main-Link Lane0 and Lane1 -> MIPI port0
0x0A: CAM A : Main-Link Lane0 -> MIPI port0
CAM B : Main-Link Lane1 -> MIPI port1
0x0B: CAM A : Main-Link Lane0 -> MIPI port1
CAM B : Main-Link Lane1 -> MIPI port0
Others: Reserved

Table 26. Data stream handling mode
Handling
R_MODE_NO
5'h0
5'h1
5'h2
5'h3
5'h8
5'hA
5'hB

Input
Camera111
11(2port)2
2

Distribution Output port Output swap
DisableEnableDisableEnableDisable
-

1
2
1
2
1
2
2

DisableEnableInput
Main-Link_0 Main-Link_1
Cam A
Cam A
Cam B
Cam B
Cam A
Cam A
Cam A
Cam B
Cam A
Cam B

OutputMIPI_0MIPI_1
Cam A
Cam A
Cam A
Cam B
Cam B
Cam B
Cam A
Cam A
Cam B
Cam B
Cam A

The MIPI data rates for MIPI_0 and MIPI_1 must be the same.

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THCV242A-P_ Rev.4.11_E
Header/Packet/Sync Pre-processing
Setting of Header, Packet and Sync pre-processing can be configurable by 2-wire access to internal register.
Settings of Header, Packet and Sync pre-processing exist for each Main-Link input lanes respectively.

Table 27. Header/Packet/Sync pre-processing setting for Main-Link (Lane0)
Address
0x1100bit Register Name
[7:1] reserved[0] R_VX1_PH_EN0

width
7
1

R/W
R/W

Init
7'h00
1'h0

0x1101[7:1] reserved[0] R_VX1_CRC_EN0

7
1

R/W

7'h00
1'h0

0x1102[7:1] reserved[0] R_VX1_SP_EN0

7
1

R/W

7'h00
1'h0

0x1103[7:1] reserved[0] R_VX1_VVALID_MODE0

7
1

R/W

7'h00
1'h0

0x1104[7:1] reserved[0] R_VX1_VSYNC_POL0

7
1

R/W

7'h00
1'h0

0x1105[7:0] R_VX1_WC_LOW0

8

R/W

8'h00

0x1106[7:0] R_VX1_WC_UP0

8

R/W

8'h00

0x1107[7:0] R_VX1_DATAID0

8

R/W

8'h00

0x1108[7:1] reserved[0] R_VX1_MASK_ECC0

7
1

R/W

7'h00
1'h0

0x1109

[7:1]
[0]
[7:1]
[0]

reserved
reservedL
reserved
R_CRC_ERR0

7
1
7
1

R/W
RC

7'h00
1'h0
7'h00
1'h0

0x110B[7:1] reserved[0] R_ECC_CRCT_ERR0

7
1

RC

7'h00
1'h0

0x110C[7:1] reserved[0] R_ECC_DOUBLE_ERR0

7
1

RC

7'h00
1'h0

0x110A

Copyright©2023 THine Electronics, Inc.

Description
MIPI Packet Header mode select for Main-Link Lane0
0x0: Packet Header is generated by register settings
0x1: Packet Header is through from Main-Link input stream
Main-Link CRC mode select for Main-Link Lane0
0x0: Main-Link input stream does not have CRC data
0x1: Main-Link input stream has CRC data
MIPI Short Packet mode select for Main-Link Lane0
0x0: Main-Link input stream does not have Short Packet
0x1: Short Packet is through from Main-Link input stream
MIPI Frame Start & Frame End (FS/FE) mode select for Main-Link Lane0
0x0: FS/FE data are through from Main-Link input stream
0x1: FS/FE data are generated based on the timing of the VSYNC signal<this register is valid only when 0x1103[0]=0x1>
Polarity setting of VSYNC signal to generate FS/FE for Main-Link Lane0
0x0: use Low pulse VSYNC signal (FE: Falling timing, FS: Rising timing)
0x1: use High pulse VSYNC signal (FE: Rising timing, FS: Falling timing)<this register is valid only when 0x1100[0]=0x0>
MIPI Packet Header's Word Count (LSB) manual setting for Main-Link Lane0<this register is valid only when 0x1100[0]=0x0>
MIPI Packet Header's Word Count (MSB) manual setting for Main-Link Lane0<this register is valid only when 0x1100[0]=0x0>
MIPI Packet Header's Data ID manual setting for Main-Link Lane0* use case setting example
YUV422-8bit: 0x1E
RGB888: 0x24
RAW8: 0x2A
RAW10: 0x2B
RAW12: 0x2C
Masking and Ignoring both MIPI short packet and MIPI long packet when ECC
double error is detected for Main-Link Lane0
0x0: Disable
0x1: Mask Processing when ECC double error is detectedmust be left 0x0 (default setting)
CRC error register for Main-Link Lane0(clear the error status after reading register automatically)
0x0: no error
0x1: detect CRC error
ECC single error register for Main-Link Lane0(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC single error
ECC double error register for Main-Link Lane0(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC double error

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THCV242A-P_ Rev.4.11_E

Table 28. Header/Packet/Sync pre-processing setting for Main-Link (Lane1)
Address
0x1200bit Register Name
[7:1] reserved[0] R_VX1_PH_EN1

width
7
1

R/W
R/W

Init
7'h00
1'h0

0x1201[7:1] reserved[0] R_VX1_CRC_EN1

7
1

R/W

7'h00
1'h0

0x1202[7:1] reserved[0] R_VX1_SP_EN1

7
1

R/W

7'h00
1'h0

0x1203[7:1] reserved[0] R_VX1_VVALID_MODE1

7
1

R/W

7'h00
1'h0

0x1204[7:1] reserved[0] R_VX1_VSYNC_POL1

7
1

R/W

7'h00
1'h0

0x1205[7:0] R_VX1_WC_LOW1

8

R/W

8'h00

0x1206[7:0] R_VX1_WC_UP1

8

R/W

8'h00

0x1207[7:0] R_VX1_DATAID1

8

R/W

8'h00

0x1208[7:1] reserved[0] R_VX1_MASK_ECC1

7
1

R/W

7'h00
1'h0

0x1209

[7:1]
[0]
[7:1]
[0]

reserved
reservedL
reserved
R_CRC_ERR1

7
1
7
1

R/W
RC

7'h00
1'h0
7'h00
1'h0

0x120B[7:1] reserved[0] R_ECC_CRCT_ERR1

7
1

RC

7'h00
1'h0

0x120C[7:1] reserved[0] R_ECC_DOUBLE_ERR1

7
1

RC

7'h00
1'h0

0x120A

Copyright©2023 THine Electronics, Inc.

Description
MIPI Packet Header mode select for Main-Link Lane1
0x0: Packet Header is generated by register settings
0x1: Packet Header is through from Main-Link input stream
Main-Link CRC mode select for Main-Link Lane1
0x0: Main-Link input stream does not have CRC data
0x1: Main-Link input stream has CRC data
MIPI Short Packet mode select for Main-Link Lane1
0x0: Main-Link input stream does not have Short Packet
0x1: Short Packet is through from Main-Link input stream
MIPI Frame Start & Frame End (FS/FE) mode select for Main-Link Lane1
0x0: FS/FE data are through from Main-Link input stream
0x1: FS/FE data are generated based on the timing of the VSYNC signal<this register is valid only when 0x1203[0]=0x1>
Polarity setting of VSYNC signal to generate FS/FE for Main-Link Lane1
0x0: use Low pulse VSYNC signal (FE: Falling timing, FS: Rising timing)
0x1: use High pulse VSYNC signal (FE: Rising timing, FS: Falling timing)<this register is valid only when 0x1200[0]=0x0>
MIPI Packet Header's Word Count (LSB) manual setting for Main-Link Lane1<this register is valid only when 0x1200[0]=0x0>
MIPI Packet Header's Word Count (MSB) manual setting for Main-Link Lane1<this register is valid only when 0x1200[0]=0x0>
MIPI Packet Header's Data ID manual setting for Main-Link Lane1* use case setting example
YUV422-8bit: 0x1E
RGB888: 0x24
RAW8: 0x2A
RAW10: 0x2B
RAW12: 0x2C
Masking and Ignoring both MIPI short packet and MIPI long packet when ECC
double error is detected for Main-Link Lane1
0x0: Disable
0x1: Mask Processing when ECC double error is detectedmust be left 0x0 (default setting)
CRC error register for Main-Link Lane1(clear the error status after reading register automatically)
0x0: no error
0x1: detect CRC error
ECC single error register for Main-Link Lane1(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC single error
ECC double error register for Main-Link Lane1(clear the error status after reading register automatically)
0x0: no error
0x1: detect ECC double error

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THCV242A-P_ Rev.4.11_E
MIPI output setting
Setting of MIPI output can be configurable by 2-wire access to internal register.

Table 29. MIPI output setting (1/3)
Address
0x1600bit Register Name
[7:5] Reserved[4:0] R_ANALOG

width
3
5

R/W
R/W

Init
3'h0
5'h00

Description[4] MIPI Power Down
0x0: Power Down
0x1: Normal operation[3] MIPI Soft Reset
0x0: Reset
0x1: Normal operation[2] ReservedL (must be set 0x0)
[1] ReservedH (must be set 0x1)
[0] ReservedL (must be set 0x0)

0x16010x1602[7:0] ReservedX[7:0] R_TX_LANE_SEL0

8
8

R/W
R/W

8'h1B
8'hE4

must be left as default 0x1B
MIPI Tx Lane assignment select (*each bit setting)[7:6] MTX3P/N (MTX3) (*)[5:4] MTX2P/N (MTX2) (*)[3:2] MTX1P/N (MTX1) (*)[1:0] MTX0P/N (MTX0) (*)
0x0: 1st Byte output
0x1: 2nd Byte output
0x2: 3rd Byte output (or 1st Byte on 2PORT mode)
0x3: 4th Byte output (or 2nd Byte on 2PORT mode)* use case setting example
1PORT1LANE: 0xE4 (Port0:MTX0)
1PORT2LANE: 0xE4 (Port0:MTX0, MTX1)
1PORT4LANE: 0xE4 (Port0:MTX0, MTX1, MTX2, MTX3)
2PORT1LANE: 0x72 (Port0:MTX1, Port1:MTX0)0x63 (Port0:MTX1, Port1:MTX2)
0x36 (Port0:MTX3, Port1:MTX0)
2PORT2LANE: 0x72 (Port0:MTX3,MTX1, Port1:MTX0,MTX2)

0x1603[7:2] Reserved[1:0] R_TX_LANE_SEL1

6
2

R/W

6'h00
2'h0

<this register is valid when 0x1605[2:0]=0x4 or 0x5>
MIPI Tx Lane assignment select for Port1 on 2PORT mode
* use case setting example
2PORT1LANE: 0x0 (Port1:MTX0)
2PORT1LANE: 0x2 (Port1:MTX2)
2PORT2LANE: 0x0 (Port1:MTX0,MTX2)

0x1604[7:0] ReservedX

Copyright©2023 THine Electronics, Inc.

8

R/W

8'h3F

must be left as default 0x3F

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THCV242A-P_ Rev.4.11_E

Table 30. MIPI output setting (2/3)
Address
0x1605bit Register Name
[7] Reserved[6:0] R_LANE_EN

width
1
7

R/W
R/W

Init
1'h0
7'h2B

Description[6:5] MIPI Data lane Enable (*each bit setting)[6] Data Port1 (*)[5] Data Port0 (*)
0x0: OFF0x1: ON[4:3] MIPI CLK lane Enable (*each bit setting)[4] CLK Port1 (*)[3] CLK Port0 (*)
0x0: OFF0x1: ON[2:0] MIPI Configuration
0x0 (=0b000): 1PORT1LANE
0x1 (=0b001): 1PORT2LANE
0x3 (=0b011): 1PORT4LANE
0x4 (=0b100): 2PORT1LANE
0x5 (=0b101): 2PORT2LANE
Other:Reserved* use case setting example
1PORT1LANE: 0x28 (=0b0101_000)
1PORT2LANE: 0x29 (=0b0101_001)
1PORT4LANE: 0x2B (=0b0101_011)
2PORT1LANE: 0x7C (=0b1111_100)
2PORT2LANE: 0x7D (=0b1111_101)

0x16060x16070x1608[7:2] ReservedX

6

R/W

6'h10

must be set 0x13

[1:0] R_MODE_SET

2

R/W

2'h0

[7:0] ReservedX[7:4] Reserved[3:0] ReservedX

8
4
4

R/W
R/W

8'hE4
4'h0
4'hE

clock continous mode select (*each bit setting)[1] clock continous mode select for Port1 (*)[0] clock continous mode select for Port0 (*)
0x0:OFF (HS clock off and become LP mode during V-Blanking term)
0x1:ON (HS clock permanently on)(*) When 0x1013[0] = 0x0, 0x1606[1:0] must be set 0x3.
must be left 0xE4 (default setting)must be left 0xE (default setting)

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THCV242A-P_ Rev.4.11_E

Table 31. MIPI output setting (3/3)
Address
0x1609bit Register Name
[7:0] R_TX_CLK_PREPARE0

width
8

R/W
R/W

Init
8'h04

Description
CLK lane Prepare period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_PREPARE0"0x160a[7:0] R_TX_CLK_ZERO0

8

R/W

8'h1D

CLK lane ZERO period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_ZERO0"

0x160b[7:0] R_TX_CLK_TRAIL0

8

R/W

8'h07

CLK lane TRAIL period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_TRAIL0"0x160c[7:0] reservedX

8

R/W

8'h02

must be left 0x2 (default setting)

0x160d[7:0] R_TX_CLK_POST0

8

R/W

8'h0C

CLK lane POST period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_POST0"0x160e[7:0] R_TX_THS_EXIT0

8

R/W

8'h0B

CLK and Data lane EXIT period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_EXIT0"0x160f[7:0] R_TX_TLPX0

8

R/W

8'h05

CLK and Data lane TLPX period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_TLPX0"0x1610[7:0] R_TX_THS_PREPARE0

8

R/W

8'h04

Data lane Prepare period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_PREPARE0"0x1611[7:0] R_TX_THS_ZERO0

8

R/W

8'h10

Data lane ZERO period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_ZERO0"0x1612[7:0] R_TX_THS_TRAIL0

8

R/W

8'h07

Data lane TRAIL period setting Port0
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_TRAIL0"0x1613[7:0] reservedX

8

R/W

8'h40

must be left 0x40 (default setting)

0x1614[7:0] R_TX_CLK_PREPARE1

8

R/W

8'h04

CLK lane Prepare period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_PREPARE1"

0x1615[7:0] R_TX_CLK_ZERO1

8

R/W

8'h1D

CLK lane ZERO period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_ZERO1"

0x1616[7:0] R_TX_CLK_TRAIL1

8

R/W

8'h07

CLK lane TRAIL period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_TRAIL1"

0x1617[7:0] reservedX

8

R/W

8'h02

must be left 0x2 (default setting)

0x1618[7:0] R_TX_CLK_POST1

8

R/W

8'h0C

CLK lane POST period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_CLK_POST1"

0x1619[7:0] R_TX_THS_EXIT1

8

R/W

8'h0B

CLK and Data lane EXIT period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_EXIT1"

0x161a[7:0] R_TX_TLPX1

8

R/W

8'h05

CLK and Data lane TLPX period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_TLPX1"

0x161b[7:0] R_TX_THS_PREPARE1

8

R/W

8'h04

Data lane Prepare period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_PREPARE1"

0x161c[7:0] R_TX_THS_ZERO1

8

R/W

8'h10

Data lane ZERO period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_ZERO1"

0x161d[7:0] R_TX_THS_TRAIL1

8

R/W

8'h07

Data lane TRAIL period setting Port1
Adjustable delay value in units of "8 × tTBIT × R_TX_THS_TRAIL1"

0x161e[7:0] reservedX

8

R/W

8'h40

must be left 0x40 (default setting)

Copyright©2023 THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E

MTX0P/N and MTX2P/N can be assigned to be MIPI 2nd port (port1).
MTXCLK1P/N and MIPI 2nd port available maximum speed is 1.2Gbps.
The MIPI clock frequency output from MTXCLK0 and MTXCLK1 is the same frequency. It is not possible tooutput a different frequency.

THCV242A-P

28

MTX3P

27

MTX3N

26

MTX1P

25

MTX1N

24 MTXCLK0P
23 MTXCLK0N
22

MTX0P

MIPI Tx

21

MTX0N

available

20

MTX2P

2nd port1

19

MTX2N

data pins

18 MTXCLK1P

2nd port1 clock

17 MTXCLK1N

2nd port1 clock

Figure 15. MIPI 2nd port available pins

Setting of MIPI 2port output examples are shown below.

Table 32. MIPI 2port output setting example
R_TX_LANE_SEL0
lane3 lane2 lane1 lane0
[7:6]
[5:4]
[3:2]
[1:0]
01
11
00
10
01
10
00
11
00
11
01
10
01
11
00
10
01
10
00
11
00
11
01
10

R_TX_LANE_SEL1
R_LANE_EN
port1 selectport enable clk enable
[1:0]
[6:5]
[4:3]
00
11
11
10
11
11
00
11
11
00
11
11
10
11
11
00
11
11
other settings

config
[2:0]
101
101
101
100
100
100

lane3
[3]
0
0
0
0
0
0

R_REQ_SEL
lane2 lane1
[2]
[1]
1
0
1
0
1
0
1
0
1
0
1
0

lane0
[0]
1
1
1
1
1
1

lane3
MTX3P/N
port0 2nd Byte
port0 2nd Byte
port0 1st Byte
No output
No output
port0 1st Byte

MIPI Physical pin order output assignment
lane1
lane0
lane2
MTX1P/NMTXCLK0P/N
MTX0P/NMTX2P/N
port0 1st Byte port0 clock
port1 1st Byte port1 2nd Byte
port0 1st Byte port0 clock
port1 2nd Byte port1 1st Byte
port0 2nd Byte port0 clock
port1 1st Byte port1 2nd Byte
port0 1st Byte port0 clock
port1 1st Byte No output
port0 1st Byte port0 clock
No output
port1 1st Byte
No output
port0 clock
port1 1st Byte No output
forbidden

MTXCLK1P/N
port1 clock
port1 clock
port1 clock
port1 clock
port1 clock
port1 clock

MIPI CSI-2 Virtual Channel
MIPI Virtual Channel (VC) is supported. When MIPI PH (Packet Header) is intake from V-by-One® HS input,
MIPI Virtual Channel information in PH is also bridged from V-by-One® HS at the same time. Virtual Channel
information can be intake from Main-Link input and properly applied on MIPI Packet Header by selectableregister setting.

Copyright©2023 THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E

Copyright©2023 THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E
MIPI Line Start/Line End code output setting
Both Line Start (LS) code and Line End (LE) code are optional code in MIPI CSI-2. When R_NONUSE_LSLE
register is set 1’b1, both inputted LS and LE data are masked and ignored. On the other hands, when
R_NONUSE_LSLE register is set 1’b0, both inputted LS and LE data are transmitted normally. For a systemthat do not use LS/LE code, R_NONUSE_LSLE_ register must be set 1’b1 to prevent unexpected behavior.

Table 33. MIPI Line Start and Line End code setting
Address
0x1013

bit Register Name
[7:1] ReservedL[0] R_NONUSE_LSLE

width
7
1

R/W
R/W
R/W

init
7'h00
1'h0

Description
must be left 0x00 (default setting)Line start and Line end code use or non-use setting for all Main-LInk lane
0x0: When a system is used mipi line start and line end, must be set 0x0 (*)
0x1: When a system is not use mipi line start and line end, must be set 0x1(*) When 0x1013[0] = 0x0, 0x1606[1:0] must be set 0x3.

Multiple camera synchronization Frame Vsync supply
Frame VSYNC can be supplied from THCV242A-P to Sub-Link Slave GPO.
EXTSYNC input or internally generated VSYNC become supply source. Settings are configurable by 2-wireaccess to internal register. When internal VSYNC is selected, generated VSYNC is not only sent to remote SubLink Slave but also output from EXTSYNC pin.

Internal VSYNC uses two clock source, internal oscillator clock and video pixel clock from Main-Link input. At
the beginning of internal VSYNC generation operation, oscillator clock is used to supply VSYNC. After MainLink video source is received stable, internal VSYNC generation source is switched to video pixel clock fromselected Main-Link input. When Main-Link video pixel clock input is lost, internal VSYNC generator again uses
internal oscillator clock until Main-Link video pixel clock input is regained.

Table 34. Multiple camera synchronization Frame Vsync supply setting (1/3)
Address
0x1007

bit Register Name
[7:4] reserved[3:0] R_EXTSYNC_MODE

Copyright©2023 THine Electronics, Inc.

width
4
4

R/W
R/W

init
4'h0

Description
EXTSYNC I/O Mode0x0: Disable
0x1: Normal Mode (Controlled by Sub-Link Register)
Other: Reserved

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THCV242A-P_ Rev.4.11_E

Table 35. Multiple camera synchronization Frame Vsync supply setting (2/3)
Address
0x0020bit Register Name
[7:5] reserved[4] R_VS_PHASE_EN

width
3
1

R/W
RW

Init
1'h0

Description<this regiseter is valid only when 0x0020[1:0]=0x2>
Enable of shifting the Internal VSYNC output timing
0x0: Disable
0x1: Enable (*)(*) 0x002E register is related for output timing[3:2] reserved[1:0] R_VS_MODE

2
2

RW

2'h0

0x0021

[7:5]
[4]
[3:1]
[0]

reserved
ReservedL
reserved
R_VS_POL

3
1
3
1

RW
RW

1'h0
1'h0

0x0022[7] reserved[6:4] R_VS_GPI_SEL

1
3

RW

3'h0

[3:2] ReservedL[1:0] R_VS_LANE_SEL

2
2

RW
RW

2'h0
2'h0

0x0023[7:4] reserved[3:0] R_VSOSC_LINE_UP

4
4

RW

4'h0

<this regiseter is valid when 0x0010[3:0]=0x1 or 0x2 or 0x3>
multiple camera synchronization Frame VSYNC supply mode setting
0x1: Select external VSYNC signal from EXTSYNC pin (*)
0x2: Select internal VSYNC signal and output for EXTSYNC pin (**)
Other: Disable(*) 0x1007 register is related to this mode(**) set this mode after setting both 0x0021 and 0x0023 - 0x002E registers
must be left 0x0 (default setting)<this regiseter is valid only when 0x0020[1:0]=0x2>
Internal VSYNC Pulse Polarity
0x0: Low Pulse
0x1: High Pulse<this regiseter is valid when 0x0020[1:0]=0x1 or 0x2>
Select a assignment bit for Frame VSYNC signal to send
0x0: a bit of Sub-Link for GPIO00x1: a bit of Sub-Link for GPIO1
Other: Reserved
Must be set 0x0<this regiseter is valid when 0x0020[1:0]=0x1 or 0x2>
Select Sub-Link Lane for Frame VSYNC signal to send (*each bit setting)[0]:Sub-Link Lane0 (*)[1]:Sub-Link Lane1 (*)
0x0: no send
0x1: send Frame VSYNC signal<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC clock number / line by oscillator setting

0x0024[7:0] R_VSOSC_LINE_DN

8

RW

8'h0F

0x0025[7:0] R_VSOSC_WIDTH

8

RW

8'h00

0x0026[7:4] reserved[3:0] R_VSOSC_TIM_UP

4
4

RW

4'h0

0x0027[7:0] R_VSOSC_TIM_DN

8

RW

8'h0F

Copyright©2023 THine Electronics, Inc.

<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC clock number / line by oscillator= (256×R_VSOSC_LINE_UP<3:0> +R_VSOSC_LINE_DN<7:0>+1)×tOSC*Clock / line is 1 when R_VSOSC_LINE_UP=0x0 and R_VSOSC_LINE_DN=0x0<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse width line number by oscillator settingLine Number = R_VSOSC_WIDTH + 1 (e.g. 0x00 for 1line)<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse interval line number by oscillator setting<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse interval line number by oscillator= (256×R_VSOSC_TIM_UP<3:0> +R_VSOSC_TIM_DN<7:0>+1)×tOSC*Interval line is 2 when R_VSOSC_TIM_UP=0x0 and R_VSOSC_TIM_DN=0x044

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THCV242A-P_ Rev.4.11_E

Table 36. Multiple camera synchronization Frame Vsync supply setting (3/3)
Address
0x0028bit Register Name
[7:2] reserved[1:0] R_VS_PCLK_SEL

width
6
2

R/W
RW

Init
2'h0

0x0029[7:4] reserved[3:0] R_VSP_LINE_UP

4
4

RW

4'h0

0x002A[7:0] R_VSP_LINE_DN

8

RW

8'h0F

0x002B[7:0] R_VSP_WIDTH

8

RW

8'h04

0x002C[7:4] reserved[3:0] R_VSP_TIM_UP

4
4

RW

4'h0

0x002D[7:0] R_VSP_TIM_DN

8

RW

8'h0F

0x002E[7:0] R_VS_PHASE_WIDTH

8

RW

8'h01

Copyright©2023 THine Electronics, Inc.

Description<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC generation base pixel clock domain select0x0: select source clock (CLK_I) from Main-Link Lane00x1: select source clock (CLK_I) from Main-Link Lane1
Other: Reserved<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC clock number / line by base pixel clock setting<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC clock number / line by base pixel clock = (256×
R_VSP_LINE_UP<3:0> +R_VSP_LINE_DN<7:0>+1)×CLK_I*Clock / line is 1 when R_VSP_LINE_UP=0x0 and R_VSP_LINE_DN=0x0<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse width line number by base pixel clock settingLine Number = R_VSP_WIDTH + 1 (e.g. 0x00 for 1line)<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse interval line number setting<this register is valid only when 0x0020[1:0]=0x2>
Internal VSYNC pulse interval line number = (256×R_VSP_TIM_UP<3:0>+R_VSP_TIM_DN<7:0>+1)
Internal VSYNC pulse interval frame period by base pixel clock =(256×R_VSP_TIM_UP<3:0> +R_VSP_TIM_DN<7:0>+0x1)×(256×R_VSP_LINE_UP<3:0> +R_VSP_LINE_DN<7:0>+0x1)×CLK_I*Interval line is 2 when R_VSP_TIM_UP=0x0 and R_VSP_TIM_DN=0x0*For setting or reset of this register, R_VS_MODE is supposed to be disable<this register is valid only when 0x0020[1:0]=0x2>
The internal VSYNC output timing of Sub-Link Lane1 is delayed by"16 × R_VS_PHASE_WIDTH × CLK_I" from Sub-Link Lane0.
(e.g. 0x00 is 16×CLK_I)

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THCV242A-P_ Rev.4.11_E
6.6.

Status monitoring, Interrupt and Error Detection
Internal Error / status signal monitoring pin output

Internal error or status signal can be monitored as external ERR0/ERR1 pin output by register setting.

Table 37. Internal Error / status signal monitoring ERR0/ERR1 pin output setting
Address
0x1005bit Register Name
[7:4] R_ERR1_MODE

width
4

R/W
R/W

init
4'h0

[3:0] R_ERR0_MODE

4

R/W

4'h0

Description
ERR1 I/O Mode0x0: Disable
0x1: OpenDrain Output Mode0x2: Push/Pull Output Mode
Other: Reserved
ERR0 I/O Mode0x0: Disable
0x1: OpenDrain Output Mode0x2: Push/Pull Output Mode
Other: Reserved

Table 38. IC Internal selectable Error / status signal (1/3)
R_ERR1/0_SEL[7:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F

Error signal
0 Fixed
1 FixedVx1_LOCKN_ALL
Vx1_HTPDN_ALL
Vx1_FBETOUT_LATCH_ALL
Vx1_FBETOUT_REAL_ALL
Vx1_PERR_ALL
MLINK_CRCERR_ALL
Vx1_CLOCKSTP_ALL
MLINK_VDSK_OK_ALL
MLINK_VDSK_NG_ALL
MLINK_DSHNDLRERR_ALL
Reserved
SLINK_PERR_ALL
SLINK_TMOUT_ALL
SLINK_FBETOUT
Vx1_LOCKN0
Vx1_LOCKN1Reserved
Reserved
Vx1_HTPDN0
Vx1_HTPDN1
Reserved
Reserved
Vx1_BETOUT_LATCH0
Vx1_BETOUT_LATCH1
Reserved
Reserved
Vx1_BETOUT_REAL0
Vx1_BETOUT_REAL1
Reserved
Reserved

Copyright©2023 THine Electronics, Inc.

Description

OR operated of all operating lanes, LOCKN signal
OR operated of all operating lanes, HTPDN signal
OR operated of all operating lanes, field-bet latched result
OR operated of all operating lanes, field-bet real result
OR operated of all operating lanes, protocol error
OR operated of all operating lanes, crc error
clock stop detector of all lanes
Vsync synchronization OK flag of all lanes
Vsync synchronization NG flag of all lanes
Data Stream Handler Error of all lanes
OR operated of all operating lanes, protocol error
OR operated of all operating lanes, time out error
OR operated of all operating lanes, sub-link field-bet result
lane0 LOCKN signal
lane1 LOCKN signal

lane0 HTPDN signal
lane1 HTPDN signal

lane0 field-bet latched result
lane1 field-bet latched result

lane0 field-bet real result
lane1 field-bet real result

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THCV242A-P_ Rev.4.11_E

Table 39. IC Internal selectable Error / status signal (2/3)
R_ERR1/0_SEL[7:0]
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F

Error signal
Vx1_PERR0
Vx1_PERR1
Reserved
Reserved
MLINK_CRCERR0
MLINK_CRCERR1Reserved
Reserved
MLINK_VSYNC0MLINK_VSYNC1Reserved
Reserved
MLINK_HSYNC0MLINK_HSYNC1Reserved
Reserved
MLINK_DE0
MLINK_DE1
Reserved
Reserved
MLINK_CLK0
MLINK_CLK1
Reserved
Reserved
MIPI_BYTECLKOSCCLK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Copyright©2023 THine Electronics, Inc.

Description
lane0, protocol error
lane1, protocol error

lane0, crc error
lane1, crc error

lane0, Vsync signal
lane1, Vsync signal

lane0, Hsync signal
lane1, Hsync signal

lane0, DE signal
lane1, DE signal

lane0, clock signal
lane1, clock signal

CSI byte clock signal
internal oscilltor clock signal

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THCV242A-P_ Rev.4.11_E

Table 40. IC Internal selectable Error / status signal (3/3)
R_ERR1/0_SEL[7:0]
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A

Error signal
MLINK_FS0
MLINK_FS1
Reserved
Reserved
MLINK_FE0
MLINK_FE1
Reserved
Reserved
MLINK_VDSK_NG0
MLINK_VDSK_NG1
Reserved
Reserved
TOP_CKSUM_ERR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SLINK_PERR0SLINK_PERR1
Reserved
Reserved
SLINK_TMOUT0SLINK_TMOUT1
Reserved

Copyright©2023 THine Electronics, Inc.

Description
lane0, Frame Start
lane1, Frame Start

lane0, Frame End
lane1, Frame End

lane0, Vsync synchronization NG flaglane1, Vsync synchronization NG flagregister checksum error

lane0, protocol error
lane1, protocol error

lane0, time out error
lane1, time out error

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THCV242A-P_ Rev.4.11_E
Internal Error / status signal monitoring register
Internal error or status signal can be monitored as register read value.
Error count register can be cleared by particular register write “1” access.

Table 41. Internal Error / status signal monitoring register (1/2)
Address
0x00F1

bit Register Name
[7:1] reserved[0] R_SLINK_FBETERR_CLR

width
7
1

R/W
W

Init
-

0x00F2[7:0] R_SLINK_FBETERR_NUM_UP

8

R

-

0x00F3[7:0] R_SLINK_FBETERR_NUM_DN

8

R

-

Description<this register is valid only when 0x1035[4]=0x1>
Sub-Link FieldBET error count clear
0x1: Clear<this register is valid only when 0x1035[4]=0x1>
Sub-Link FieldBET error count parameter<this register is valid only when 0x1035[4]=0x1>
Sub-Link FieldBET error count =256×R_SLINK_FBETERR_NUM_UP<7:0>＋R_SLINK_FBETERR_NUM_DN<7:0>

Table 42. Internal Error / status signal monitoring register (2/2)
Address
0x174Fbit Register Name
[7:6] reserved[5:4] R_MLINK_CRC_ERRCLR

width
2
2

R/W
W

init
-

Description
Main-Link CRC Error Counter Clear<0x174F[5] register is valid only when 0x1101[0]=0x1>[5] Main-Link CRC Error Counter Clear for Lane1
0x1: Clear[3:2] reserved[1:0] R_MLINK_BET_ERRCLR

2
2

W

-

<0x174F[4] register is valid only when 0x1201[0]=0x1>[4] Main-Link CRC Error Counter Clear for Lane00x1: Clear
Main-Link BET Error Counter Clear<0x174F[1] register is valid only when 0x1035[0]=0x1>[1] Main-Link BET Error Counter Clear for Lane1
0x1: Clear

0x1750[7:0] MLINK0_CRC_ERRNUM[15:8]

8

R

-

0x1751[7:0] MLINK0_CRC_ERRNUM[7:0]

8

R

-

0x1752[7:0] MLINK1_CRC_ERRNUM[15:8]

8

R

-

0x1753[7:0] MLINK1_CRC_ERRNUM[7:0]

8

R

-

0x1758[7:0] MLINK0_BET_ERRNUM[15:8]

8

R

-

0x1759[7:0] MLINK0_BET_ERRNUM[7:0]

8

R

-

0x175A[7:0] MLINK1_BET_ERRNUM[15:8]

8

R

-

0x175B[7:0] MLINK1_BET_ERRNUM[7:0]

8

R

-

Copyright©2023 THine Electronics, Inc.

<0x174F[0] register is valid only when 0x1035[0]=0x1>[0] Main-Link BET Error Counter Clear for Lane00x1: Clear<this register is valid only when 0x1101[0]=0x1>
Main-Link(Lane0) CRC Error Number (Upper Byte)<this register is valid only when 0x1101[0]=0x1>
Main-Link(Lane0) CRC Error Number (Lower Byte)<this register is valid only when 0x1201[0]=0x1>
Main-Link(Lane1) CRC Error Number (Upper Byte)<this register is valid only when 0x1201[0]=0x1>
Main-Link(Lane1) CRC Error Number (Lower Byte)<this register is valid only when 0x1035[0]=0x1>
Main-Link(Lane0) BET Error Number (Upper Byte)<this register is valid only when 0x1035[0]=0x1>
Main-Link(Lane0) BET Error Number (Lower Byte)<this register is valid only when 0x1035[1]=0x1>
Main-Link(Lane1) BET Error Number (Upper Byte)<this register is valid only when 0x1035[1]=0x1>
Main-Link(Lane1) BET Error Number (Lower Byte)

49

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SC:E

THCV242A-P_ Rev.4.11_E
Interrupt monitoring
Interrupt (INT1/0) detects occurrence of internal error or status signal and then, latch the detected state.
Interrupt factor can be cleared by particular register* write “1” access. (*They are indicated as “R_INTC_*”)Interrupt factor can be masked to “0” fixed by particular register appropriate write access.
INT interrupt function is supposed to be cleared before start monitoring any desired status because INT status
may change at power on condition and THCV242A-P internal boot up procedure.
Table 43. Interrupt monitoring
Register

Address

R_INTR_MLRX

0x1710/0x1718

R_INTR_MODE
R_INTR_DSHNDLR

0x1711/0x1719R_INTR_FMT
0x1712/0x171A

R_INTR_CSI

0x1713/0x171B

0x1714/0x171CR_INTR_BDC2Q

0x1715/0x171D

0x1716/0x171E
R_INTR_DSHNDLR

Copyright©2023 THine Electronics, Inc.

bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
6
5
4
3
2
1
0
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0

Description
Reserved
Reserved
Main-Link protocol error for Lane1
Main-Link protocol error for Lane0
Reserved
Reserved
Main-Link RX LOCKN=L to H detection flag for Lane1
Main-Link RX LOCKN=L to H detection flag for Lane0
Vsync synchronization OK flag of all lanes
All Main-Link RX LOCKN=H detection flag
Data Stream Handler Distribution error
Data Stream Handler error
Reserved
Reserved
Main-Link RX CRC error1 for Lane1
Main-Link RX CRC error1 for Lane0
MIPI CSI-2 status error for port1
MIPI CSI-2 status error for port0
MIPI CSI-2 general error
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Internal Register AutoCheckSum error flag
Reserved
Reserved
Reserved
Sub-Link Slave side 2-wire access complete flag for Lane1
Sub-Link Slave side 2-wire access complete flag for Lane0
Reserved
Reserved
Sub-Link Slave side interrupt detection flag for Lane1
Sub-Link Slave side interrupt detection flag for Lane0
Reserved
Reserved
Sub-Link protocol error for Lane1
Sub-Link protocol error for Lane0
Reserved
Reserved
Data Stream Hander error2 for Lane1
Data Stream Hander error2 for Lane050

THine Electronics, Inc.

SC:E

THCV242A-P_ Rev.4.11_E

As a register, interrupt detected state is “1” and cleared state is “0”. When multiple interrupt sources areactivated, the OR operated result is indicated as IC external INT1/0 pin output.
As an external INT1/0 pin output, open drain output interrupt detected state is “Low” and cleared state is “HiZ”, while INT1/0 pin CMOS push-pull output interrupt detected state is “Low” and cleared state is “High”.

Table 44. INT1/0 pin output control
Address
0x1006

bit Register Name
[7:4] R_INT1_MODE

width
4

R/W
R/W

init
4'h0

[3:0] R_INT0_MODE

4

R/W

4'h0

Description
INT1 I/O Mode0x0: Disable
0x1: OpenDrain Output Mode0x2: Push/Pull Output Mode
Other: Reserved
INT0 I/O Mode0x0: Disable
0x1: OpenDrain Output Mode0x2: Push/Pull Output Mode
Other: Reserved

INT1/0 interrupt function is supposed to be cleared before start monitoring any desired status because INT1/0
status may have been changed before monitoring activation.

Register Auto Checksum diagnosis
Register values checksum is continuously calculated as R_CKSUM_RVAL.

Table 45. Register Auto Checksum diagnosis control and monitoring
Address
0x0008bit Register Name
[7:1] reserved[0] R_CKSUM_EN

width
7
1

R/W
RW

Init
1'h0

0x0009[7:0] R_CKSUM_TIM

8

RW

8'h13

0x000A[7:0] R_CKSUM_VAL

8

RW

8'h00

0x000B[7:0] R_CKSUM_RVAL

8

R

-

Copyright©2023 THine Electronics, Inc.

Description
Internal Register AutoCheckSum Enable
0x0: Disable
0x1: Enable<this regiseters is valid only when 0x0008[0]=0x1>
Internal Register AutoCheckSum check interval=1024×64×(R_CKSUM_TIM<7:0>+1) × tOSC
<this regiseters is valid only when 0x0008[0]=0x1>
Internal Register AutoCheckSum expected target value<this regiseters is valid only when 0x0008[0]=0x1>
Internal Register AutoCheckSum read value

51

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SC:E

THCV242A-P_ Rev.4.11_E
6.7.

Power On Sequence

Power On Sequence must be controlled appropriate.
For Power On Reset, PDN input must be low at the moment when VDDCORE (VDD12) reach operating
condition voltage. As a note, PDN pin itself does not belongs to VDDCORE (VDD12) but to VDDIO1 (VDDH).
PDN Power On Reset control is mandatory.
MIPI, PLL and V-by-One® HS block are reset state at power on default and require Reset Release.
V-by-One® HS Soft Reset / PLL Soft Reset => MIPI Soft Reset is proper. See below detail.

Operating Condition min.

VDDH
(3.3V~1.8V domain)
t1

Operating Condition min.

VDD12
(1.2V domain)

t2

t11

VIH
VIL

PDN
2-wireSCL/SDATHCV242A-P
settings

Sub-Link
slave

THCV242A-P
PowerON

Sub-Link
RCMP/N

2-wireaccess2-wire remote
2-wire remote access

V-by-One®HS Rx
Soft reset

Polling

Pollingt3

V-by-One®HS
Rx HTPDN
V-by-One®HS
Rx LOCKN
V-by-One®HS
Rx RX*N/P

t12
Hi-Z

Training Pattern

Normal Pattern

PLL
soft reset
MIPI Tx
soft reset

t6

MIPI Tx
TXN/P

Hi-Z

MIPI LP11

NormalOperation

Figure 16.

HS-modePower On Sequence procedure

Table 46. Power On Sequence specification
symbol
t1
t2
t11
t3
t12
t6

description
Required waitfrom VDDH assert to VDD12 assert
Required waitfrom Power On to PDN High control
Required waitfrom PDN High to Register AccessTime of V-by-One®HS Rx soft reset Highto HTPDN Low
Time of Training Pattern Input
to LOCKN Low
Time of V-by-One®HS Normal operation input
to MIPI normal operation output

min.

typ.

max.

unit

0

-

-

us

1000

-

-

us

300

-

-

us

-

-

10

us

-

-

980

us

-

-

50+
1frameus

The first MIPI output from Power On waits vertical blanking period and starts output; therefore, MIPI normal
operation may be hold for maximum 1frame, which depends on used video format.

Copyright©2023 THine Electronics, Inc.

52

THine Electronics, Inc.

SC:E

THCV242A-P_ Rev.4.11_E
6.8.

Lock / Re-Lock Sequence

Lock and re-lock sequence are as follows. V-by-One® HS automatically shifts into lock status from initial
status or unlock status caused by external noise under appropriate parameter set condition.

THCV242A-P LOCK Sequence
THCV242A-P RXnP/RXnN (n=0,1)

CDR Training

ALN Training

Normal Operationt12
THCV242A-P LOCKN

One
polingPolling Interval
THCV242A-P (Sub-Link Master)
polling (worst. case)

LOCKN=H

Main-Link Tx LOCKN=Low
to Data pattern output delay

LOCKN=Lt6

THCV242A-P MTXmP/MTXmN(m=0,1,2,3)

NormalOperation

MIPI LP11

Figure 17.

Normal Operation

Lock Sequence

THCV242A-P Re-LOCK Sequence
THCV242A-P LOCKN

One
polingPolling Interval
THCV242A-P (Sub-Link Master)
polling (worst. case)

LOCKN=L

Polling Interval

LOCKN=HLOCKN=HOne
polingMain-Link Tx LOCKN=Low
to Data pattern output delay

LOCKN=Lt12
THCV242A-P RXnP/RXnN (n=0,1)

Normal output

CDR Training

ALN Training

Normal Operation

Main-Link Tx LOCKN=H toTraining pattern output delayt13
THCV242A-P MTXmP/MTXmN(m=0,1,2,3)

NormalOperation

t6B
MIPI LP11

MIPI LP11

Figure 18.

NormalOperation

Normal Operation

Re-Lock Sequence

Table 47. Lock / Re-Lock Sequence specification
symbolt13
t6B

description
Time of LOCKN=H
to MIPI Stand-by LP11 output
Time of V-by-One®HS Normal operation re-input
to MIPI normal operation re-output

Copyright©2023 THine Electronics, Inc.

53

min.

typ.

max.

unit

-

-

98

us

-

-

50

us

THine Electronics, Inc.

SC:E

THCV242A-P_ Rev.4.11_E

7.

Absolute Maximum Ratings
Table 48. Absolute Maximum Ratings*

Parameter
Supply Voltage (VDDIO1,VDDIO2)
Supply Voltage (VDDCORE,VDDRX,VDDTX,VDDPLL)LVCMOS Input Voltage (1.2V domain)
LVCMOS Input Voltage (VDDIO1 domain)
LVCMOS Output Voltage
LVCMOS Bi-directional buffer Input Voltage
LVCMOS Bi-directional buffer Output Voltage
LVCMOS Input Voltage (VDDIO2 domain)
CML Receiver Voltage
MIPI Transmitter Voltage
CML Bi-directional buffer Input Voltage
CML Bi-directional buffer Output Voltage
Output Current
Storage Temperature
Junction Temperature
Reflow Peak Temperature/time
Maximum Power Dissipation @ +25℃
*1 Max. must be below 4V at the same time
*2 Max. must be below 1.6V at the same time

min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-30
-55
-

typ.
-

max.
4
1.6
VDDRX+0.3 *2
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO2+0.3 *1
VDDRX+0.3 *2
VDDTX+0.3 *2
VDDIO2+0.3 *1
VDDIO2+0.3 *1
30
125
125
26
3.9

Unit
V
V
V
V
V
V
V
V
V
V
V
V
mA
°C
°C
°C/secW

 “Absolute Maximum Ratings” are values of safety limit for a device beyond which a device safety cannot be

guaranteed.
They do not imply that a device should be operated at these limits. The tables of “Recommended Operating
Condition” specify conditions for device operation.

8.

Recommended Operating Conditions
Table 49. Recommended Operating Conditions
SymbolVDDH

Parameter
Supply Voltage (VDDIO1, VDDIO2)

VDD12Supply Voltage 1.2V (VDDCORE, VDDRX, VDDTX, VDDPLL)Ta

Operating Ambient Temperature

Copyright©2023 THine Electronics, Inc.

54

Condition
1.2Gbps < fMIPIMTXCLK0P/N
single clock out
-

min.
1.7
1.1

typ.
-

max.
3.6
1.3

Unit
V
V

1.15

1.25

1.3

V

-40

-

105

°C

THine Electronics, Inc.

SC:E

THCV242A-P_ Rev.4.11_E

9.

Consumption Current
Table 50. Consumption Current at Power Down
symbolICCS33
ICCS12parameter
Power Down Supply Current

condition
PDN=0, VDDH=3.6V
PDN=0, VDD12=1.3V

min.
-

typ.
0.1
8

max.
-

unit
mA
mA

min.
-

typ.
16
32
14
27

max.
20
38
17
32

unit
mA
mA
mA
mA

typ.
49
49
177
60
64
65
65
75
75
89
93
95
85
98
100
113
135
149
184
213
89
90
102
102
120
121
151
153
184
188

max. Unit
111 mA
109 mA251 mA123 mA
126 mA
128 mA
128 mA
139 mA
139 mA
158 mA
160 mA
161 mA
150 mA
165 mA
166 mA
184 mA
224 mA
238 mA276 mA
310 mA
148 mA
148 mA
165 mA
164 mA
186 mA
186 mA219 mA
226 mA
258 mA266 mA

Table 51. Consumption Current of VDDH
symbolparameter
ICCWH_33_1
VDDIO1/2=3.3V
ICCWH_33_2
ICCWH_18_1
VDDIO1/2=1.8V
ICCWH_18_2

condition
Sub-Link 1lane active
Sub-Link 2lane active
Sub-Link 1lane active
Sub-Link 2lane active

Table 52. Consumption Current of VDD12
SymbolIccw12_01
Iccw12_02
Iccw12_157

port.in#1

port.out#

1

2

Iccw12_03
Iccw12_04
Iccw12_05

1

Iccw12_06
Iccw12_07
Iccw12_08

2

Iccw12_09

input

quasi-1080p low fps

400Mbps x1lane

quasi-1080p high fps
720p30fps RAW
720p30fps YUV422
720p60fps RAW
1080p30fps RAW
720p60fps YUV422

4Gbps x2lane selected742.5Mbps x1lane
1Gbps x1lane

output
320Mbps x1lane
80Mbps x4lane
800Mbps x4lane
594Mbps x1lane
600Mbps x1lane

1.11375Gbps x1lane

445.5Mbps x2lane

1080p30fps YUV422

1

Iccw12_12

1080p60fps RAW
1

Iccw12_13

1080p60fps YUV422

Iccw12_15

Iccw12_B12

1

Iccw12_B13
Iccw12_B90
Iccw12_31
Iccw12_33
Iccw12_34
Iccw12_35

Iccw12_37
Iccw12_38
Iccw12_39
Iccw12_402
Iccw12_412

2.2275Gbps x1lane

2

2

891Mbps x2lane
445.5Mbps x4lane
594Mbps x4lane

2.97Gbps x1lane

2

Iccw12_153

594Mbps x2lane
594Mbps x2lane x2port Dist.

720p120fps YUV422

Iccw12_14

Iccw12_36

1.485Gbps x1lane

720p120fps RAW

Iccw12_10
Iccw12_11

video format

1188Mbps x2lane
1188Mbps x2lane x2port Dist.

1080p120fps RAW
1080p120fps YUV422
4K60fps RAW
720p30fps RAW
720p30fps YUV422
720p60fps RAW
1080p30fps RAW
720p60fps YUV422
1080p30fps YUV422
720p120fps RAW
1080p60fps RAW
720p120fps YUV422
1080p60fps YUV422

Copyright©2023 THine Electronics, Inc.

2.2275Gbps x2lane
3Gbps x2lane
3.75Gbps x2lane
742.5Mbps x1lane x2port
750Mbps x1lane x2port

891Mbps x4lane
1200Mbps x4lane
1500Mbps x4lane
594Mbps x1lane x2port
600Mbps x1lane x2port

1.11375Gbps x1lane x2port

445.5Mbps x2lane x2port

1.485Gbps x1lane x2port

594Mbps x2lane x2port

2.2275Gbps x1lane x2port

891Mbps x2lane x2port

2.97Gbps x1lane x2port

1188Mbps x2lane x2port

55

min.
-

THine Electronics, Inc.

SC:E

THCV242A-P_ Rev.4.11_E

10. DC Specifications
10.1. LVCMOS DC Specifications

Table 53. LVCMOS DC Specifications
symbolIIH
IIL

parameter
LVCMOS Input Leak Current HighLVCMOS Input Leak Current Low

VIH

LVCMOS High Level Input Voltage

pin type
ILIL

IL

condition
VIN=VDDIO1
VIN=GNDVDDIO1=1.7~2.0V
VDDIO1=2.0~3.0V
VDDIO1=3.0~3.6V
VDDIO1=1.7~3.6V
VDDIO1=1.7~2.0V
VDDIO1=2.0~3.0V
VDDIO1=3.0~3.6V
VDDIO1=1.7~3.6V

min.
-10
0.65*VDDIO1
0.70*VDDIO1
2.0
0.70*VDDIO1
0
0
0
0

typ.
-

max.
10
VDDIO1VDDIO1VDDIO1VDDIO10.35*VDDIO1
0.30*VDDIO1
0.8
0.30*VDDIO1

unit
uA
uA
V
V
V
V
V
V
V
V

B
IL

VIL

LVCMOS Low Level Input Voltage

B

VOH

LVCMOS High Level Output Voltage

B,O

IOH=-1mA

VDDIO1-0.45-

VDDIO1V

VOL

LVCMOS Low Level Output Voltage

B,O

IOL=1mA

0

-

0.45

V

10.2. CML Receiver DC Specifications

Table 54. CML Receiver DC Specifications
symbolVRTH
VRTL

parameter
CML Differential Input High Threshold
CML Differential Input Low Threshold

IRIH

CML Input Leak Current HighIRIL

CML Input Leak Current Low

IRRIH
IRRIL
RRIN

CML Input Current HighCML Input Current Low
CML Differential Input Resistance

Copyright©2023 THine Electronics, Inc.

condition
PDN=L,
RXP/N=VDDRXPDN=L,
RXP/N=GND
RXP/N=VDDRX
RXP/N=GND
-

56

min.
-50

typ.
-

max.
50
-

unit
mV
mV

-

-

±15

uA

-

-

±15

uA

-4.6
80

100

1.6
120

mA
mA
ohm

THine Electronics, Inc.

SC:E

THCV242A-P_ Rev.4.11_E
10.3. CML Bi-directional Buffer DC Specifications

Table 55. CML Bi-directional Buffer DC Specifications
symbol
VBTH
VBTL
VBIC
IBIH
IBIL
VBOD
VBOC
IBOZ

parameter
CML Bi-Directional Buffer
Differential Input High Threshold
CML Bi-Directional Buffer
Differential Input Low Threshold
CML Bi-Directional Buffer Input
Terminated Common Voltage
CML Bi-Directional Buffer
Output Leak Current HighCML Bi-Directional Buffer
Output Leak Current Low
CML Bi-Directional Buffer
Differential Output Voltage
CML Bi-Directional Buffer
Common Output Voltage
CML Bi-Directional Buffer
TRI-STATE Current

RTERM

CML Bi-Directional Buffer
Termination Registance

IDRIVE

CML Bi-Directional Buffer
Drive Current

condition
R_BDCZ_HYS=0
R_BDCZ_HYS=1
R_BDCZ_HYS=0
R_BDCZ_HYS=1
R_BDCZ_TERM_**= 2'b00
R_BDCZ_DRIVE_**= 2'b00

min.
-50
-150

typ.
-

max.
50
150
-

unit
mV
mV
mV
mV

-

VDDIO2-300-

mV

RCM*P/N=VDDIO2

-10

-

10

uA

RCM*P/N=GND

-10

-

10

uA

200

300

400

mV

-

VDDIO2-300

-

mV

PDN=L

-10

-

10

uA

R_BDCZ_TERM_**=2'b10
R_BDCZ_TERM_**=2'b01
R_BDCZ_TERM_**=2'b00
R_BDCZ_DRIVE_**=2'b10
R_BDCZ_DRIVE_**=2'b01
R_BDCZ_DRIVE_**=2'b00

-

50
100
200
12
6
3

-

ohm
ohm
ohm
mA
mA
mA

typ.
200
200
-

max.
250
270
350
1.3
0.05
-

unit
mV
mV
mV
V
V
ohm

R_BDCZ_TERM_**=2'b10
R_BDCZ_DRIVE_**=2'b10
Diff. 100ohm terminated
R_BDCZ_TERM_**=2'b00
R_BDCZ_DRIVE_**=2'b00

10.4. MIPI Transmitter DC Specifications

Table 56. MIPI Transmitter DC Specifications
symbolVTCMTX|VTOD|VTOHHSVTOHLP
VTOLLP
ZTOLP

parameter
HS-mode statics Common-mode Voltage
HS-mode Differential Voltage
HS-mode High Level Output Voltage
LP-mode High Level Output Voltage
LP-mode Low Level Output Voltage
LP-mode Output Impedance

Copyright©2023 THine Electronics, Inc.

condition
ZID=80~125ohm
ZID=100ohm
ZID=100ohm
-

57

min.
150
140
1.1
-0.05
110

THine Electronics, Inc.

SC:E

THCV242A-P_ Rev.4.11_E

11. AC Specifications
11.1. General AC Specifications
Table 57. General AC Specifications
symboltDLparameter
Data Latency

condition
MainLink 1Gbps,
0x1502 - 0x1505
registers are set default
value.

min.

typ.

max.

unit

typ.-98

16,000typ.+98

ns

typ.
-

max.
2500
4

unit
ps
Gbps

typ.
137.5

max.
172.7

unit
ns

typ.
12.5
-

max.
15.7
1000
-

unit
ns
kHz
us
us
us

11.2. CML Receiver AC Specifications
Table 58. CML Receiver AC Specifications
symboltRBIT
fRBITparameter

condition-

Unit Interval

min.
250
0.4

11.3. CML B-directional Buffer AC Specifications
Table 59. CML B-directional Buffer AC Specifications
symboltBUIparameter
Bi-Directional CML Buffer Unit Interval

condition
-

min.
128.7

11.4. 2-wire serial Slave AC Specifications
Table 60. 2-wire serial Slave AC Specifications
symboltOSC
fSCLtHD;STA
tLOW
tHIGH

tr

parameter
Cycle of internal oscillator clock
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START
condition
Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals

tf

Fall time of both SDA and SCL signals

tSU;STAtHD;DATtSU;DATtSU;STO

condition
-

min.
11.7
0.26
0.5
0.26

-

0.26

-

-

us

pull-up:2.5kΩ, bus
capacitance :
400pF
-

0
0
50
50
-

2*tOSC-

120(*1)

us
ns
ns
ns
ns

-

-

120

ns

0.26

-

-

ns

0.5

-

-

us

-

-

50

ns

300

-

-

us

Setup time for STOP condition
Bus free time between a STOPtBUFand START condition
Pulse width of spikes which must be
tSP
suppressed by the input filter
Required wait time from PDN0 hightPDS
to START condition*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.

Copyright©2023 THine Electronics, Inc.

58

THine Electronics, Inc.

SC:E

THCV242A-P_ Rev.4.11_E

11.5. MIPI Transmitter AC Specifications
Table 61. MIPI Transmitter AC Specifications
symbol
tTBIT
fTBIT
tTBIT
fTBIT

min.
0.833
80
0.667
1200

typ.
-

max.
12.5
1200
0.833
1500

unit
ns
Mbps
ns
Mbps

60+52*tTBIT

-

-

ns

8

-

-

4

-

-

38

-

95

ns

60

-

-

ns

tCLK-PREPARE tCLK-PREPARE + Time that the transmitter R_TX_CLK_ZERO* = 0x29
+ tCLK-ZERO drives the HS-0 state prior starting the Clock. tTBIT = 600Mbps

300

-

-

ns

Transmitted time interval from the start oftHS-TRAIL or tCLK-TRAIL, to the stat of the
LP-11 state following a HS burst.

--

105+12*tTBIT

ns

100

-

-

ns

40+4*tTBIT-

85+6*tTBIT

ns

145+10*tTBIT

-

-

ns

60+4*tTBIT

-

-

ns

50

-

-

ns

tCLK-POST

parameter

condition-

Tx Unit Interval
1.15V < VDD12MTXCLK0P/N single clock out

Time that the transmitter continues to send
HS clock after the last associated Data
Lanes has transitioned to LP Mode.

tTBIT = 1200Mbps
R_TX_CLK_POST* = 0x0F
tTBIT = 600Mbps
R_TX_CLK_POST* = 0x0A

Time that the HS clock shall be driven by thetTBIT = 1200Mbps
transmitter prior to any associated DatatCLK-PRE
Lane beginning the transition from LP to HS
tTBIT = 600Mbps
mode.
Time that the transmitter drives the ClocktTBIT = 1200Mbps
R_TX_CLK_PREPARE* = 0x06
Lane LP-00 Line state immediately before
tCLK-PREPARE
the HS-0 Line state starting the HS
tTBIT = 600Mbps
R_TX_CLK_PREPARE* = 0x03
transmission.
tCLK-TRAIL

Time that the transmitter drives the HS-0
state after the last payload clock bit of a HStransmission burst.

tTBIT

tTBIT = 1200Mbps
R_TX_CLK_TRAIL* = 0x0C
tTBIT = 600Mbps
R_TX_CLK_TRAIL* = 0x07
tTBIT = 1200Mbps
R_TX_CLK_PREPARE* = 0x06

tEOT

tHS-EXITtHS-PREPARETime that the transmitter drives LP-11
following a HS burst.
Time that the transmitter drives the Data
Lane LP-00 Line state immediately before
the HS-0 Line state starting the HStransmission.
tHS-PREPARE + Time that the transmitter

R_TX_CLK_PREPARE* = 0x03
R_TX_CLK_ZERO* = 0x13
tTBIT = 1200Mbps
R_TX_CLK_TRAIL* = 0x0C
R_TX_THS_TRAIL* = 0x0C
tTBIT = 600Mbps
R_TX_CLK_TRAIL* = 0x07
R_TX_THS_TRAIL* = 0x07
tTBIT = 1200Mbps
R_TX_THS_EXIT* = 0x04
tTBIT = 600Mbps
R_TX_THS_EXIT* = 0x00
tTBIT = 1200Mbps
R_TX_THS_PREPARE*= 0x06
tTBIT = 600Mbps
R_TX_THS_PREPARE*= 0x03
tTBIT = 1200Mbps
R_TX_THS_PREPARE* = 0x06

tHS-PREPARE
R_TX_THS_ZERO* = 0x10
drives the HS-0 state prior to transmitting the tTBIT = 600Mbps+ tHS-ZERO

Sync sequence.

R_TX_THS_PREPARE* = 0x03
R_TX_THS_ZERO* = 0x06
tTBIT = 1200Mbps

tHS-TRAILtLPXTime that the transmitter drives the flipped
R_TX_THS_TRAIL* = 0x0C
differential state after last payload data bit oftTBIT = 600Mbps
a HS transmission burst.
R_TX_THS_TRAIL* = 0x07
Transmitted length of any Low-Power state
period.

Copyright©2023 THine Electronics, Inc.

tTBIT = 1200Mbps
R_TX_TLPX* = 0x08
tTBIT = 600Mbps
R_TX_TLPX* = 0x04

59

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THCV242A-P_ Rev.4.11_E

12. Package
TOP VIEW

9.00

LASER MARKFOR PIN1

9.00

BOTTOM VIEW
1.10

6.00
17

32

16

33

0.09
R

0.45

6.00

PIN1 ID
0.20 R

1

48

0.50

SIDE VIEW

0.40

0.65

0.25

1.10

49

0.90 MAX

64

Unit: mm

Copyright©2023 THine Electronics, Inc.

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THCV242A-P_ Rev.4.11_E

13. Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note evenif errors or omissions should be found in this material, THine may not be able to correct them immediately.
3. This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.
4. THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE RELATINGTO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISING OUT OF THISPRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTES SUCCESSFULLY PROVED
BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE, HOWEVER, EVEN IN THE
AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR LOSS IF THE DISPUTE IS
CAUSED BY THE USER’S INSTRUCTION.
5. This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability,
which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe design principles
such as redundant or error preventive design applied to the use of the product so as not to have our product cause any social or
public damage.
7. This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.
8. Please note that this product is not designed to be radiation-proof.
9. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.
10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

Copyright©2023 THine Electronics, Inc.

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