THCS251_Rev.3.01_E

THCS251
35-bits GPIO or high speed Bus signal Transceiver

General description

Features

The THCS251 integrates Serializer and Deserializer
onto a single chip, which supports general purpose
input and output (GPIO) signals through two pairs ofdifferential signal.

Support up to 35-bits GPIO
Not required to input GPIO sampling clock ininternal oscillator clock mode
Full duplex communication by two pairs ofdifferential signal
Output buffer open-drain or push-pull selectable
Support up to 8-bits low speed GPIO in low
power Standby mode
Integrated adaptive equalizer for long or lossy
media
8B10B encoding and decoding
Configurable digital noise filter
Error detection and indication
External reference clock frequency: 9-100MHz
Spread Spectrum Clock Generator to reduce EMI
Operating single power supply voltage: 1.7 V 3.6 V
Wide range IO voltage: 1.7V - 3.6V
Operating ambient temperature: -40°C to 85°C




GPIO sampling clock is selectable from externalreference clock or internal oscillator clock.
The 8B10B encoding and decoding adopted by
THCS251 is easy to connect to optical / wirelesscommunication devices with high robustness and DC
balanced signal.
The built-in adaptive equalizer enables flexible cableselection.

Application
The THCS251 can applicable to any systems whichhave many control signals between PCBs, forexample Multi-function printers, Amusement
machines, Factory Automation and TVs.











Block diagram
THCS251 (Master mode)

THCS251 (Slave mode)

REFEN
OSC

LDO

SSCG

GPIO
D34/D0...
D0/D34REFOUT

PLL

LDO

Copyright©2023 THine Electronics, Inc.

TXN
TXP

LVCMOS I/O

RXN
RXP

RXP
RXN

Formatter

TXP
TXN

Tx
(Serializer)

Tx(Serializer)
Rx(Deserializer)

Formatter

GPIO
D0/D34...
D34/D0LVCMOS I/O

REFIN

Rx
(Deserializer)

PLL

SSCG

1/33

OSC

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
Contents page
General description.................................................................................................................................................. 1
Application .............................................................................................................................................................. 1
Features ................................................................................................................................................................... 1
Block diagram ......................................................................................................................................................... 1
1. Pin configuration ............................................................................................................................................. 3
2. Pin description ................................................................................................................................................. 4
3. Absolute maximum ratings.............................................................................................................................. 8
4. Recommended operating conditions ............................................................................................................... 8
5. Electrical characteristics .................................................................................................................................. 95.1. Current consumption ............................................................................................................................... 95.2. LVCMOS/Analog input DC specifications ........................................................................................... 10
5.3. LVCMOS AC characteristics ................................................................................................................. 11
5.4. CML DC characteristics ........................................................................................................................ 14
5.5. CML AC characteristics ........................................................................................................................ 14
6. CML Line Eye diagrams ............................................................................................................................... 19
6.1. CML output Eye diagrams..................................................................................................................... 19
6.2. CML input Eye diagrams ...................................................................................................................... 20
7. Function ......................................................................................................................................................... 21
7.1. Functional overview .............................................................................................................................. 21
7.2. Power supply ......................................................................................................................................... 21
7.2.1.
Internal regulator output/input function (CAPOUT, CAPINA, CAPINP) .................................... 21
7.3. Operating mode ..................................................................................................................................... 21
7.4. Transmission mode ................................................................................................................................ 22
7.4.1.
Full duplex Bi-directional transmission mode ............................................................................... 22
7.4.2.
Unidirectional transmission mode ................................................................................................. 24
7.5. IO configuration .................................................................................................................................... 25
7.5.1.
Input and Output digital noise filter .............................................................................................. 25
7.5.2.
LVCMOS output buffer type configuration................................................................................... 25
7.5.3.
5V Tolerant I/O .............................................................................................................................. 25
7.6. Sampling clock configuration................................................................................................................ 26
7.6.1.
Sampling clock selection ............................................................................................................... 26
7.6.2.
Spread Spectrum Clock Generator (SSCG) and REFIN frequency............................................... 28
7.7. Error detection and indication ............................................................................................................... 29
7.8. Standby mode ........................................................................................................................................ 30
8. Package.......................................................................................................................................................... 31
Notices and Requests............................................................................................................................................. 32

Copyright©2023 THine Electronics, Inc.

2/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

DIRSEL1DIRSEL0REFEN

D34 / D0

D33 / D1

D32 / D2

D31 / D3

D30 / D4

D29 / D5

D28 / D6

D27 / D7

D26 / D8

D25 / D9VDD

D24 / D10

Pin configuration

STANDBY

1.

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

OBUF 49

32 D23 / D11

QFN-64

DATA_WIDTH 50

31 D22 / D12

TEST2 51

30 D21 / D13

AVDD 52

29 D20 / D14

CAPOUT 53

28 D19 / D15

RXP 5427 D18 / D16

RXN 5526 REFIN / REFOUT/ OSCSEL1(TOP VIEW)
65 EXPGND

CAPINA 56
TXN 5725 VDD24 D17 / D17

TXP 5823 D16 / D18

CAPINP 59

22 D15 / D19

INT / LOCKN 60

21 D14 / D20

TEST1 61

20 D13 / D21

RESETN 62

19 D12 / D22

RESERVED 63

18 D11 / D23

FILTSEL1 64

17 D10 / D24

READY

SSEN

FILTSEL0D0 / D34

D1 / D33

10

11

12

13

14

15

16

VDD

RF / OSCSEL0

9

D9 / D25

MSSEL

Copyright©2023 THine Electronics, Inc.

8

D8 / D26

7

D7 / D27

6

D6 / D28

5

D5 / D29

4

D4 / D30

3

D3 / D31

2

D2 / D32

1

3/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

2.

Pin description

Pin Name
TXP
TXN
RXP
RXN

Pin No.
58
57
54
55

RESETN62

IL

STANDBY

48

IL

RESERVED

63

IL

MSSEL

1

IL

FILTSEL164IL

DIRSEL0

Type
CO
CO
CI
CI

46

IL

DIRSEL1

47

IL

OBUF

49

IL

REFEN

45

REFIN/REFOUT/
OSCSEL126

DATA_WIDTH

50

IL

B

IL

Description
High-speed CML signal output
High-speed CML signal output
High-speed CML signal input
High-speed CML signal input
Chip reset
0: Chip reset
1: Chip operation
Standby mode entry
0:Normal mode operation
1:Standby mode operation
RESERVED shall be tied to Ground.
Master/Slave mode select0: Master mode
1: Slave mode

2

IL

-

Table 5
Table 2
Table 4DIRSEL0: GPIO direction selectTable 2
Table 4DIRSEL1: GPIO direction selectOutput buffer type select0: open-drain
1: push-pull
Data sampling clock select (Master mode)
0: Internal oscillator clock
1: External reference clock
CDR clock output enable (Slave mode)
0: REFOUT pin is Hi-Z state
1: CDR clock output from REFOUT pin
REFIN: (Master mode) External Reference
clock input
REFOUT: (Slave mode) CDR clock output
OSCSEL1: (Master mode) Oscillator clock
frequency selectOSCSEL1: (Slave mode) Hi-Z
GPIO Aggregator/Deaggregator data width
select---Table 10
Table 2
Table 4
Table 14
Table 11
Figure 14

RF:(Slave mode) output clock edge selectOSCSEL0: (Master mode) Oscillator clock
frequency selectCopyright©2023 THine Electronics, Inc.

-

FILTSEL1: digital noise filter selectRF:(Master mode) input clock edge selectRF/
OSCSEL0

Reference-

4/33

Table 10THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
Pin Name

Pin No.

Type

Description

Reference

OSCSEL0: (Slave mode) Set to Low
D0/
D34

6

BT

7

BT

8

BT

9

BT

10

B

11

B

12

B

13

B

14

B

15

B

17

B

D11/
D23

18

B

D12/
D22

19

B

D13/
D21

20

B

21

B

22

B

23

B

24

B

27

B

28

B

29

B

30

B

31

B

D1/
D33
D2/
D32
D3/
D31
D4/
D30
D5/
D29
D6/
D28
D7/
D27
D8/
D26
D9/
D25
D10/
D24

D14/
D20
D15/
D19
D16/
D18
D17/
D17
D18/
D16
D19/
D15
D20/
D14
D21/
D13
D22/
D12

Copyright©2023 THine Electronics, Inc.

D0(Master mode): Data input
D34(Slave mode): Data output
D1(Master mode): Data input
D33(Slave mode): Data output
D2(Master mode): Data input
D32(Slave mode): Data output
D3(Master mode): Data input
D31(Slave mode): Data output
D4(Master mode): Data input
D30(Slave mode): Data output
D5(Master mode): Data input
D29(Slave mode): Data output
D6(Master mode): Data input
D28(Slave mode): Data output
D7(Master mode): Data input
D27(Slave mode): Data output
D8(Master mode): Data input
D26(Slave mode): Data output
D9(Master mode): Data input
D25(Slave mode): Data output
D10(Master mode): Data input
D24(Slave mode): Data output
D11(Master mode): Data input-

D23(Slave mode): Data output-

D12(Master mode): Data input
D22(Slave mode): Data output-

D13(Master mode): Data input-

D21(Slave mode): Data output-

D14(Master mode): Data input/output
D20(Slave mode): Data input/output
D15(Master mode): Data input/output
D19(Slave mode): Data input/output
D16(Master mode): Data input/output
D18(Slave mode): Data input/output
D17(Master mode): Data input/output
D17(Slave mode): Data input/output
D18(Master mode): Data input/output
D16(Slave mode): Data input/output
D19(Master mode): Data input/output
D15(Slave mode): Data input/output
D20(Master mode): Data input/output
D14(Slave mode): Data input/output
D21(Master mode): Data input/output
D13(Slave mode): Data input/output
D22(Master mode): Data input/output
D12(Slave mode): Data input/output

-

5/33

-

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
Pin Name
D23/
D11
D24/
D10
D25/
D9
D26/
D8
D27/
D7
D28/
D6
D29/
D5
D30/
D4
D31/
D3
D32/
D2
D33/
D1
D34/
D0

Pin No.

Type

32

B

33

B

35

B

36

B

37

B

38

B

39

B

40

B

41

BT

42

BT

43

BT

44

BT

SSEN

4

BL

FILTSEL0

5

BL

INT/
LOCKN

60

BO

READY

3

B

TEST1
TEST2

61
51

IL
AI

CAPOUT53

PWR

CAPINA

56

PWR

Copyright©2023 THine Electronics, Inc.

Description
D23(Master mode): Data input/output
D11(Slave mode): Data input/output
D24(Master mode): Data input/output
D10(Slave mode): Data input/output
D25(Master mode): Data input/output
D9(Slave mode): Data input/output
D26(Master mode): Data input/output
D8(Slave mode): Data input/output
D27(Master mode): Data input/output
D7(Slave mode): Data input/output
D28(Master mode): Data input/output
D6(Slave mode): Data input/output
D29(Master mode): Data input/output
D5(Slave mode): Data input/output
D30(Master mode): Data input/output
D4(Slave mode): Data input/output
D31(Master mode): Data input/output
D3(Slave mode): Data input/output
D32(Master mode): Data input/output
D2(Slave mode): Data input/output
D33(Master mode): Data input/output
D1(Slave mode): Data input/output
D34(Master mode): Data input/output
D0(Slave mode): Data input/output
SSEN(Master mode): SSCG PLL enable
0: SSCG PLL is disabled
1: SSCG PLL is enabled
SSEN(Slave mode): Set to Low
FILTSEL0: digital noise filter select
INT: Interrupt output when READY=1
0: Error occurred1(pull-up): No Error

Reference-

Table 5-LOCKN(Master mode): Lock detect input
0: Lock state
1(pull-up): Unlock state-

LOCKN(Slave mode): Lock detect output
0: Lock state
1(pull-up): Unlock state-

CML Link communication status
0: Unlock state
1: Lock state-

TEST1 shall be tied to Ground.
TEST2 shall be tied to Ground.
Decoupling capacitor Pin, 1.2V output.

Figure 9

1.2V Analog power supply input.

Figure 9

6/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
Pin Name

Pin No.

Type

Description
1.2V Analog power supply input.

Reference
Figure 9

CAPINP

59

PWR

VDD

16
25
34

1.7-3.6V Digital power supply input for
LVCMOS I/O.

-

PWR

AVDD

PWR

1.7-3.6V Analog power supply input for onchip regulator.

Figure 952

EXPGND

GND

Exposed Pad Ground. Must be tied to the PCB
ground plane through an array of vias.

-

65

Pin Type definition
Analog Buffer
CO : CML Output buffer
CI : CML Input buffer
AI : Analog Input buffer
LVCMOS buffer
IL : Low speed schmitt trigger LVCMOS Input buffer
B : LVCMOS Bi-directional buffer
BO : Open-drain LVCMOS Bi-directional buffer
BL : Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer
BT : Low speed 5V tolerant LVCMOS Bi-directional bufferPower/Ground
PWR : Power supply
GND : Ground

Copyright©2023 THine Electronics, Inc.

7/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

3.

Absolute maximum ratings

Parameter
Supply voltage(VDD,AVDD)LVCMOS input voltage
LVCMOS output voltage
5V tolerant Bi-directional buffer input voltage
5V tolerant Bi-directional buffer output voltage
Open-drain output voltage
CML receiver input voltage
CML transmitter output voltage
Output current
Storage temperature
Junction temperature
Reflow peak temperature/time
Theta-ja (Junction-to-Ambient)Psi-jt (Junction-to-Top of Package)
Maximum power dissipation @+25°C

Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-50
-55
-

Typ
Max
4.0
VDD+0.3
VDD+0.3
VDD+2.5
VDD+2.5
4.0
CAPINA+0.3
CAPINP+0.3
50
125
125
260/1029.1 [*1]
1.1 [*1]
3.4[*1]

Unit
V
V
V
V
V
V
V
V
mA
°C
°C
°C/sec°C/W°C/W
W“Absolute maximum ratings” are those values beyond which the safety of the device cannot be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics” specify conditions for device operation.
*1: Thermal parameters are not guaranteed value. This value assists board and system level designers.

4.

Recommended operating conditions
Parameter
Supply voltage(VDD,AVDD)
Operating ambient temperature

Min
1.7
-40

Typ
-

Max
3.6
85

Unit
V
°C

VDD and AVDD supply voltage shall be the same voltage.

Copyright©2023 THine Electronics, Inc.

8/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

5.

Electrical characteristics

5.1.

Current consumption
SymbolIdd_w1
Idd_w2

Idda_stby
Idda_slp
Idda_rst

Parameter
Normal mode current
Low current use case [*1]Normal mode current
High current use case [*2]Standby mode current
Sleep mode current
Reset mode current

Pin
Type
PWR
PWR
PWR
PWR
PWR

Condition
AVDD=3.3V
VDD=3.3V
AVDD=3.3V
VDD=3.3V
AVDD=3.3V
VDD=3.3V
AVDD=3.3V
VDD=3.3V
AVDD=3.3V
VDD=3.3V

Min

Typ

Max

Unit

-

80

-

mA

-

260

-

mA

-

4

-

mA

-

3

-

mA

-

3

-

mA

PWR : Power supply*1: Master mode of Unidirectional transmission mode, 35-bits GPIO input, 80MHz of REFIN clock*2: Slave mode of Unidirectional transmission mode, 35-bits GPIO output, 80MHz of REFOUT clock

Copyright©2023 THine Electronics, Inc.

9/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
5.2.

LVCMOS/Analog input DC specifications
Symbol

VIH

Parameter

High level input voltage

Pin
Type

Condition

Min

Typ

Max

Unit

1.7V≦VDD<2.0V

0.65 VDD

-

VDD

V

2.0V≦VDD<3.0V

0.70 VDD

-

VDD

V

3.0V≦VDD≦3.6V

2.0

-

VDD

V

1.7V≦VDD≦3.6V

0.70 VDD

-

VDD

V

1.7V≦VDD<2.0V

0-0.35 VDD

V

2.0V≦VDD<3.0V

0-0.30 VDD

V

3.0V≦VDD≦3.6V

0

-

0.8

V

IL,BL

1.7V≦VDD≦3.6V

0-0.30 VDD

V

AI

1.7V≦VDD≦3.6V

0-0.15 VDD

V

1.7V≦VDD<2.0V
IOH=-2mA

VDD 0.30

-

VDD

V

2.0V≦VDD≦3.6V
IOH=-4mA

VDD 0.45

-

VDD

V

1.7V≦VDD<2.0V
IOL=2mA

0

-

0.30

V

2.0V≦VDD≦3.6V
IOL=4mA

0

-

0.45

V

0

-

0.27

V

-10
-10

-

10
10

uA
uA

-10

-

10

uA

-10

-

10

uA

B,BT,
BO
IL,BL
B,BT,
BO

VIL

VOH

VOL

Low level input voltage

High level output voltage

Low level output voltage

B,BT,
BL

B,BT,
BL

BO
IIH
IIL

1.7V≦VDD≦3.6V
IOL=2mA
VIN=VDD
VIN=0V

Input leak current highIL
Input leak current low
IL
Output leak current high in B,BT,
IOZH
VIN=VDD
Hi-Z state
BL,BO
Output leak current low in
B,BT,
IOZL
VIN=0V
Hi-Z state
BL,BO
AI : Analog Input buffer
IL : Low speed schmitt trigger LVCMOS Input buffer
B : LVCMOS Bi-directional buffer
BO : Open-drain LVCMOS Bi-directional buffer
BL : Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer
BT : Low speed 5V tolerant LVCMOS Bi-directional buffer

Copyright©2023 THine Electronics, Inc.

10/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
5.3.

LVCMOS AC characteristics

SymbolParametertRSNRESETN low time

tTCIP

REFIN period

tTCH
tTCL

REFIN high time
REFIN low time

Condition

Min

Typ

Max

Unit

3

-

-

us

10
12.5
0.35 tTCIP
0.35 tTCIP

0.5 tTCIP
0.5 tTCIP

66.6
111
0.65 tTCIP
0.65 tTCIP

ns
ns
ns
ns

2.0

-

-

ns

1.7V≦VDD<2.25V

25

-

-

ns

2.25V≦VDD≦2.75V

2.5

-

-

ns

2.75V<VDD≦3.6V

2.0

-

-

ns

DATA_WIDTH=0
DATA_WIDTH=1
Pin type:
1.7V≦VDD≦3.6V
B

tTS

Data input setup to REFIN

Pin type:
BTtTH

Data input hold to REFIN

-

1.0

-

-

ns

tTPD

Power on to RESETN high
delay

-

0

-

-

ns

41.67

50

62.5

ns

20.84

25

31.25

ns

10.42

12.5

15.62

ns

-

tOSC

-

ns

REFEN=1

-

tTCIP

-

ns

REFEN=0

10.42

12.5

15.62

ns

-

tTCIP

-

ns

12 tDCP-

25 tDCPns

19 tDCP-

35 tDCPns

24 tDCP-

43 tDCPns

34 tDCP-

59 tDCPns

57 tDCP-

110 tDCP

ns

64 tDCP-

120 tDCP

ns

69 tDCP-

128 tDCP

ns

79 tDCP-

144 tDCP

ns

tOSC

tDCP
tFLTCKInternal
periodoscillator

clock

Data sampling clock period
Noise filter clock period

OSCSEL1=0
OSCSEL0=0
OSCSEL1=1
OSCSEL0=0
OSCSEL1=1
OSCSEL0=1
REFEN=0

REFEN=1
FILTSEL1=0
FILTSEL0=0
FILTSEL1=0
FILTSEL0=1
FILTSEL1=1
FILTSEL0=0
FILTSEL1=1
FILTSEL0=1
FILTSEL1=0
FILTSEL0=0
FILTSEL1=0
FILTSEL0=1
FILTSEL1=1
FILTSEL0=0
FILTSEL1=1
FILTSEL0=1

SSEN=0tTCD

Input data to output data
delay (Master mode to
Slave mode)
SSEN=1tRCP

REFOUT period

-

-

tDCP

-

ns

tRCH

REFOUT high time--

0.5 tDCP

-

ns

tRCL

REFOUT low time--

0.5 tDCP

-

ns

tDOUT

Data output period

-

-

tDCP

-

ns

tRS

Data output setup to
REFOUT-

0.45 tDCP- 0.675

-

-

ns

tRH

Data output hold to
REFOUT-

0.45 tDCP- 2.175--

ns

12 tDCP-

25 tDCPns

Input data to output data
delay (Slave mode to Master
mode)

FILTSEL1=0
FILTSEL0=0
FILTSEL1=0
FILTSEL0=1
FILTSEL1=1
FILTSEL0=0
FILTSEL1=1

19 tDCP-

35 tDCPns

24 tDCP-

43 tDCPns

34 tDCP-

59 tDCPnstRCD

Copyright©2023 THine Electronics, Inc.

11/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
Symbol
tRRDY
tNRDY
tSRDY
tSSKW

tTLH

tTHL

Parameter
RESETN high to READY
high delay
STANDBY low to READY
high delay
STANDBY high to READY
high delay
STANDBY high of Mastermode and Slave modeskew margin
Clock and Data output low
to high transition time

Clock and data output highto low transition time

Condition
FILTSEL0=1

Min

Typ

Max

Unit

-

0

-

10

ms

-

0

-

10

ms

-

0

-

10

ms

-

-400

-

+400

us

Clock

-

-

2.1

ns

Data(Pin type=B)

-

-

4.2

ns

Data(Pin type=BT)

-

-

5.9

ns

Clock

-

-

2.1

ns

Data(Pin type=B)

-

-

4.3

ns

Data(Pin type=BT)

-

-

6.1

ns

tTCIP
tTCH(RF=0)tTCL(RF=0)tTCL(RF=1)tTCH(RF=1)
RF=0

REFIN

VDD/2

VDD/2

VDD/2

RF=1
tTS

D0-D34

tTH

VDD/2

VDD/2

Figure 1 LVCMOS input timing diagram
RD = 10Ω
Test Point

CL = 8pF

Copyright©2023 THine Electronics, Inc.

12/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
tRCP
tRCH(RF=0)tRCL(RF=0)tRCL(RF=1)tRCH(RF=1)
RF=0

REFOUT

VDD/2

VDD/2

VDD/2

RF=1
tRS

D34-D0

tRH

VDD/2

VDD/2

tDOUT

Figure 2 LVCMOS output timing diagram

Chip Mastermode Inputs
D0-D34DATA1

Chip Slave
mode Outputs
D34-D0

DATA2

DATA1

DATA3

DATA2

DATA3

tTCD

Chip Slave
mode Inputs
D34-D0DATA1Chip Mastermode Outputs
D0-D34

DATA2

DATA1

DATA3

DATA2

DATA3

tRCD

Figure 3 GPIO Input to Output delay timing diagram

Copyright©2023 THine Electronics, Inc.

13/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
5.4.

CML DC characteristics

SymbolParameter
CML differential output peak
to peak signal
CML common mode output
voltage
CML output leak currenthigh
CML output short current

VTOD
VTOC
ITOH
ITOS
VRTH
VRTL
IRIH
IRIL
IRRIH
IRRIL
RRIN

CML differential input highthreshold
CML differential input low
threshold
CML input leak current high
CML input leak current low
CML input current high
CML input current low
CML differential input
resistance

5.5.
SymboltTRF
tTPLL0tTPLL1
tTNP0

Condition

Min

Typ

Max

Unit

600

800

1000

mVpp

-

1200 - 0.5
VTOD

-

mV

-30

-

30

uA

-80

-

-

mA

-

-

-

50

mV

-

-50

-

-

mV

-10

-

10

uA

-10

-

10

uA

-6

-

2
-

mA
mA

80

100

120

Ω

RESETN=0
TXP/N=CAPINARESETN=0
TXP/N=0V

RESETN=0
RXP/N=CAPINARESETN=0
RXP/N=0V
RXP/N=CAPINA
RXP/N=0V-

CML AC characteristics
Parameter
CML output rise and fall time (20%80%)
RESETN=1 to CML output delay
RESETN=0 to CML output high fix
delay
READY low to training pattern output
delay

tTBIT

Output unit intervaltRBIT

Input unit intervalTraining pattern input to LOCKN low
delay
RESETN low to LOCKN High delay
LOCKN low to data output delaytRPLL0tRPLL1tRLCK0

Copyright©2023 THine Electronics, Inc.

Condition

Min

Typ

Max

Unit

-

50

-

150

ps

-

-

-

10

ms

-

-

-

500

ns

-

-

-

100

us

DATA_WIDTH=0
DATA_WIDTH=1-250tDCP÷30tDCP÷50
-

2222

ns
ns
ps

Unidirectional mode

-

-

10

ms

Unidirectional mode
Unidirectional mode

-

-

10
5

us
ms

14/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
75～200nF50Ω

75～200nF

50Ω

80%

80%

TXP

TXN

< 5mm

Vdiff = (TXP) - (TXN)
20%

20%

tTRF

tTRF

Figure 4 CML output AC characteristics diagram

THCS251

THCS251

CAPINP

50Ω

C=75～
200nF
TXP

50Ω

C=75～
200nF
RXP

TXN

CML Receiver

RXN
Zdiff=100ohm
50Ω

50Ω

CML Transmitter

Vbias
GND

Figure 5 CML buffer equivalent circuit

Copyright©2023 THine Electronics, Inc.

15/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
REFIN

THCS251 (Chip Master mode)

RESETNm

TXm

Tx

READYm(Master side)

D0/D34m
D17/D17m

Rx

RESETNs

Rx(Slave side)

READYsTx

D34/D0s
D17/D17s

TXs(Master side)

D18/D16m
D34/D0m

REFOUT

THCS251 (Chip Slave mode)(Slave side)

D18/D16s
D0/D34s

DATA_WIDTH=0, DIRSEL1/0=00

VDD
tTPD

RESETNmtTPLL0REFIN
D0/D34m
D17/D17m

Invalid Input

Invalid Input

Valid Input

Valid Input

Invalid Input

tTPLL1TXm

Training

NormalTraining

tTNP0

READYm
D18/D16m
D34/D0m

Hi-Z

Invalid Output

Hi-Z

Valid Output

Valid

Invalid

RESETNs
REFOUT
D34/D0s
D17/D17s

Hi-Z

Hi-Z

Solid line : RF=0
Dashed line : RF=1

Invalid clock

Invalid clock

Invalid Output

TXs

Valid Output
Training

Hi-Z

Invalid clock

Hi-Z

Valid

Invalid

NormaltRRDY

READYs
D18/D16s
D34/D0s

Invalid Input

Figure 6

Valid Input

Invalid Input

Valid

Invalid Input

GPIO/CML Bi-directional mode Power on & Reset timing diagram

Copyright©2023 THine Electronics, Inc.

16/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

REFIN

THCS251 (Chip Master mode)

RESETNm

TXm

Tx

D0/D34m

REFOUT

THCS251 (Chip Slave mode)

RESETNs

Rx(Master side)(Slave side)

Rx

Tx

D34/D0s(Slave side)(Master side)LOCKN

DIRSEL1/0=11

VDD

tTPD

RESETNmtTPLL0REFIN
D0/D34m

Invalid Input

TXm

Valid Input

Training

LOCKN

Valid Input

Invalid Input

NormalTrainingtRPLL1tRPLL1tRPLL0RESETNstRLCK0REFOUT
D34/D0s

Invalid Input

Solid line : RF=0
Dashed line : RF=1

Hi-Z

Invalid Clock

Invalid Output

Invalid Clock

Valid Output

Invalid
OutputInvalid Clock

Hi-Z
Hi-Z

Valid

Figure 7 GPIO/CML Unidirectional mode lock & unlock timing diagram

Copyright©2023 THine Electronics, Inc.

17/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

Master
STANDBY
tSSKW

tSRDY

Master
READY

tNRDY

Slave
READY
MasterStandby mode
GPIO

Normal mode
operation

SlaveStandby mode
GPIO

Normal mode
operation

Normal mode
operation

Standby mode
operation

Hi-ZStandby mode
operation

Normal mode
operation

Figure 8 Standby mode timing diagram

Copyright©2023 THine Electronics, Inc.

18/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

6.

CML Line Eye diagrams

6.1.

CML output Eye diagrams

1UI=1/(serial data rate)
C

D

B
Y

A

E
Y=0mV
H

X

G

F

X=0 UI

X=1 UIA
B
C
D

Copyright©2023 THine Electronics, Inc.

X[UI]
0.15
0.355
0.5
0.645

Y[mV]
0
140
175
175

E

0.85

0

F

0.645

-175

G

0.5

-175

H

0.355

-140

19/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
6.2.

CML input Eye diagrams

1UI=1/(serial data rate)

B
Y

C

A

D

E

F

X
X=0 UI

Copyright©2023 THine Electronics, Inc.

Y=0mV

X=1 UI

A
B
C
D

X[UI]
0.25
0.3
0.7
0.75

Y[mV]
0
50
50
0

E

0.7

-50

F

0.3

-50

20/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

7.

Function

7.1.

Functional overview

With high speed CML Serializer and Deserializer integrated onto a single chip, THCS251 enables
Aggregation/Deaggregation up to 35-bits parallel General-Purpose I/O (GPIO) signal through full-duplex
communication by two pairs of differential signal with minimal external components. THCS251 supports up to 8bits low speed GPIO signal in low power Standby mode. It does not require any external clock generators e.g. acrystal oscillator. A pair of THCS251 enables to monitor and control peripheral devices via GPIOs. In casecommunication errors occur, they keep the GPIO signals and report by an interrupt signal.

7.2.

Power supply

7.2.1.

Internal regulator output/input function (CAPOUT, CAPINA, CAPINP)

An internal regulator produces 1.2V (CAPOUT) only for internal use. It shall not be used for any other externalloads. Bypass CAPOUT to GND with 10uF as a power supply pin. Bypass AVDD to GND with >10uF.
CAPINP and CAPINA supply reference voltage for internal analog circuits. Bypass CAPINP/CAPINA to GND
with 0.1uF as power supply pins to reduce high frequency noise. CAPOUT, CAPINA and CAPINP must be tied
together as Figure 9.
It is recommended to place ferrite bead for AVDD pins to reduce noise as Figure 9.
THCS251
10uF

Power
SupplyAVDDCAPOUT

>10uF

0.1uF
CAPINA
VDD

0.1uF
CAPINP

Figure 9 Connection of CAPOUT, CAPINA, CAPINP and decoupling capacitor

7.3.

Operating mode

Table 1 shows operating mode setting.
Table 1 Operating mode setting
Operatingmode

Setting
RESETNSTANDBY

Reset

0

-

Normal10Standby1

1

Copyright©2023 THine Electronics, Inc.

description
Chip reset
All outputs are Hi-Z
Normal operating modeLow power and low frequency sampling rate transmission
through up to 8-bits GPIO.

21/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E
7.4.

Transmission mode

THCS251 has a Bi-directional transmission mode with full-duplex communication and a Unidirectional
communication mode.

7.4.1.

Full duplex Bi-directional transmission mode

THCS251 can be used a pair of Master mode and Slave mode. Master mode samples data by external reference
clock or internal oscillator clock. Slave mode samples data by CDR (Clock Data Recovery) clock generated by
Rx. Same configuration of MSSEL between Master mode and Slave mode is prohibited. See Figure 10.

MSSEL=0

THCS251(Master mode)Tx

THCS251(Slave mode)
TXP

RXP

TXN

RXN

(Serializer)

MSSEL=1

Rx(Deserializer)

D0– D34

D34– D0

Rx

RXP

TXP

RXN

TXN

(Deserializer)

Tx(Serializer)

Figure 10 Setting for Bi-directional transmission mode

Copyright©2023 THine Electronics, Inc.

22/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

Setting
Mode
Data pin for Master mode

Downstream bit count
Upstream bit count
CML line data rate
D0/D34
D1/D33
D2/D32
D3/D31
D4/D30
D5/D29
D6/D28
D7/D27
D8/D26
D9/D25
D10/D24
D11/D23
D12/D22
D13/D21
D14/D20
D15/D19
D16/D18
D17/D17
D18/D16
D19/D15
D20/D14
D21/D13
D22/D12
D23/D11
D24/D10
D25/D9D26/D8
D27/D7
D28/D6
D29/D5
D30/D4
D31/D3
D32/D2
D33/D1
D34/D0

A-1
0

A-2
0

A-3
0

B-1
1

B-2
1

B-3
1

00

01

10

00

01

10

18
21
14
17
14
21
External reference clock mode: 1/tTCIP x 30
Internal oscillator clock mode: 1/tOSC x 30
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
<=
=>
=>
<=
=>
=>
<=
=>
=>
<=
<=
=>
<=
<=
=>
<=
<=
=>
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

24
30
34
11
5
1
External reference clock mode: 1/tTCIP x 50
Internal oscillator clock mode: 1/tOSC x 50
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
<=
=>
=>
<=
=>
=>
<=
=>
=>
<=
=>
=>
<=
=>
=>
<=
=>
=>
<=
<=
=>
<=
<=
=>
<=
<=
=>
<=
<=
=>
<=
<=
<=

D34/D0
D33/D1
D32/D2
D31/D3
D30/D4
D29/D5
D28/D6
D27/D7
D26/D8
D25/D9
D24/D10
D23/D11
D22/D12
D21/D13
D20/D14
D19/D15
D18/D16
D17/D17
D16/D18
D15/D19
D14/D20
D13/D21
D12/D22
D11/D23
D10/D24
D9/D25
D8/D26
D7/D27
D6/D28
D5/D29
D4/D30D3/D31
D2/D32
D1/D33
D0/D34“=>” means Downstream (GPIO input in Master mode and GPIO output in Slave mode).
“<=” means Upstream (GPIO input in Slave mode and GPIO output in Master mode).
Start communication after setting each "Use case" in both Master/Slave.

Copyright©2023 THine Electronics, Inc.

23/33

THine Electronics, Inc.

SC: E

Data pin for Slave mode

Table 2 Common setting of Master/Slave mode for Full duplex modeUse case
DATA_WIDTHDIRSEL1,DIRSEL0

THCS251_Rev.3.01_E

7.4.2.

Unidirectional transmission mode

THCS251 operates in Unidirectional transmission mode by setting DIRSEL1=1 and DIRSEL0=1. A pair ofdifferential signal from Slave mode to Master mode shall not be connected. LOCKN connection from Slave mode
to Master mode is required.
Table 3 INT/LOCKN function in Unidirectional transmission mode
Setting
DIRSEL1DIRSEL0

1

1

MSSEL=0LOCKN0LOCKN Input

Master mode

1

LOCKN Output(open-drain)

Slave mode

THCS251(Master mode)

THCS251(Slave mode)
TXP

D0– D34

Tx

RXN

LOCKN

D34– D0

Rx

VDD(Deserializer)
LOCKN

RXP
RXN

MSSEL=1

RXP

TXN(Serializer)

Rx

Description

MSSEL

TXP
Disconnected

TXN

Tx

(Deserializer)(Serializer)

Power Down

Power Down

Figure 11 Setting for Unidirectional transmission mode

Table 4 Common setting of Master/Slave mode for Unidirectional transmission modeUse case
Setting DATA_WIDTH
Downstream bit count
Upstream bit count
CML line data rate
Mode

D0/D34
Data pin D21/D13
for
Master D22/D12mode D34/D0

U-1
U-2
0
1
22
35
0
0
External reference clock External reference clock
mode: 1/tTCIP x 30
mode: 1/tTCIP x 50
Internal oscillator clock
mode: 1/tOSC x 30

Internal oscillator clock
mode: 1/tOSC x 50

=>

=>

-

=>

D34/D0
D13/D21
D12/D22
D0/D34

Data pinfor Slavemode“=>” means Downstream (GPIO input in Master mode and GPIO output in Slave mode).
Start communication after setting each "Use case" in both Master/Slave.

Copyright©2023 THine Electronics, Inc.

24/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

7.5.

IO configuration

7.5.1.

Input and Output digital noise filter

THCS251 has digital noise filters for GPIO input (for CMOS input noise immunity) and output (for CML Linenoise immunity) which are configured by setting FILTSEL1 and FILTSEL0 shown in Table 5 and Table 6. The
data width less than (tap_num - 1) tFLTCK is filtered. tap_num is shown in Table 5 and Table 6.

Table 5 Input digital noise filter setting
FILTSEL1

FILTSEL0
0
1
0
1

0
1

Function

Filter number of taps (tap_num)

All digital noise filter setting

Disable48
16

Table 6 Output digital noise filter setting
FILTSEL1

FILTSEL0
0
1
0
1

0
1

7.5.2.

Function

Filter number of taps (tap_num)

All digital noise filter setting

Disable4
8
16

LVCMOS output buffer type configuration

GPIO output buffer types are selectable from open-drain or push-pull by setting OBUF.
Table 7 Output buffer type configuration
Setting
OBUF

7.5.3.

Function0

All GPIO outputs buffer type are selected to open-drain.

1

All GPIO outputs buffer type are selected to push-pull.

5V Tolerant I/O

Figure 12 shows the 5V tolerant I/O. Master and Slave has eight 5V tolerant I/O each.
Master mode (MSSEL=0)

5V Tolerant I/O

D0/D34
D1/D33
D2/D32
D3/D31

Normal I/O

D4/D30...
D30/D4

5V Tolerant I/O

D31/D3
D32/D2
D33/D1
D34/D0Slave mode (MSSEL=1)
Downstream

TXP
TXN

RXP
RXN

RXN
RXP

TXN
TXP
Upstream

D34/D0
D33/D1
D32/D2
D31/D3
D30/D4...
D4/D30D3/D31
D2/D32
D1/D33
D0/D34

Figure 12 5V tolerant I/O

Copyright©2023 THine Electronics, Inc.

25/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

7.6.

Sampling clock configuration

7.6.1.

Sampling clock selection

GPIO sampling clock is always supplied from the Master mode and Master mode is selectable from internal
oscillator clock or external reference clock input as shown in Figure 13, Table 8 and Table 9. Internal oscillator
frequency is selectable from 20MHz, 40MHz or 80MHz.
Table 10 shows internal oscillator frequency and CML Line data rate. REFEN of Master mode and Slave modeshall be the same setting. GPIO data sampling clock of Slave mode is CDR clock from Rx.

THCS251(Master mode)

MSSEL=0

THCS251(Slave mode)

REFIN

Tx

Rx

(Serializer)(Deserializer)

MSSEL=1

CDR clockOSC

CDR clock

Rx

Tx(Deserializer)(Serializer)

Figure 13 GPIO sampling clock source
Table 9 Sampling clock and REFIN/REFOUT/OSCSEL1 and RF/OSCSEL0 function
REFEN

Setting
MSSEL

Sampling
clock0(Mastermode)Internal
oscillator
clock

1(Slave mode)

CDR clock

Hi-Z

0(Mastermode)

Externalreferenceclock

External reference
clock input
REFIN

1(Slave mode)

CDR clock

CDR clock output
REFOUT

0

1

REFIN/REFOUT/
OSCSEL1

RF/OSCSEL0

Description
GPIO inputs are sampled by internal
oscillator clock. Internal oscillator clock
frequency is selected by setting of OSCSEL1
and OSCSEL0 (SeeTable 10)

Internal oscillator clock setting
OSCSEL1, OSCSEL0(Set to Low)
Sampling clockedge selection
RF
GPIO output clockedge selection
RF

GPIO inputs are sampled by externalreference clock
CDR clock output

Table 10 Oscillator Clock Frequency and CML Line data rate
REFEN

Setting
MSSEL
OSCSEL1

OSCSEL0

Sampling
frequency
[*1]

0

0
(Master
mode)

0
0
1
1

0
1
0
1

20MHz
40MHz
80MHz

CML Line data rate[*1]
DATA_
DATA_
WIDTH=0
WIDTH=1
600Mbps
1Gbps
1.2Gbps
2.0Gbps
2.4Gbps
Prohibition

Description
Prohibition-*1 Typical value, Spec is typical±20%

Copyright©2023 THine Electronics, Inc.

26/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

When REFEN=1, RF selects REFIN sampling clock edge of Master mode and REFOUT output clock edge ofSlave mode.

Table 11 RF Function
SettingRF
01

Description
REFIN sampling edge
REFOUT output edge
Fall edge
Fall edge
Rise edge
Rise edge

Data

Data

REFIN

REFOUT
RF=1
RF=0

RF=1
RF=0

Figure 14 Input / Output clock edge

Copyright©2023 THine Electronics, Inc.

27/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

7.6.2.

Spread Spectrum Clock Generator (SSCG) and REFIN frequency

THCS251 CML serial data output, GPIO data output and clock output are modulated by integrated SSCG. Only
Master mode operates SSCG function. The SSCG is enabled by setting SSEN. When SSCG is enabled andoperated with an external REF clock, RESET should be released after the input clock has stabilized.

Table 12 SSCG setting registers
Setting

Description

SSEN
0

SSCG is off.
SSCG is on and fixed setting.
Modulation rate is ±0.5%.
Modulation frequency is 12kHz when
fCLKSSCG = FREF = 20MHz.
( 20MHz / 1664) = 12kHz )1

Table 13 fCLKSSSG
Setting
REFEN

OSCSEL1

OSCSEL0

0

0
0
1
1

0
1
0
1

1

-

Sampling clock

Internal oscillator clock
External reference clock input
REFIN

Sampling clock
frequency

fCLKSSCG

Low
Low
High
15 – 57MHz

FREF[*1]
FREF[*1]
FREF[*1]/2
FREF[*1]*1 FREF : Sampling clock frequency

Table 14 External reference clock input frequency range and SSCG setting
Setting
DATA_WIDTH
0
1

SSEN
0
1
0
1

Copyright©2023 THine Electronics, Inc.

External reference clock
input frequency range[MHz]
15 - 100
15 - 57
9 - 80
9 - 32.5

28/33

CML Line
multiply ratio
x30
x30
x50
x50

CML Line
data rate[Gbps]
0.45- 3.0
0.45 - 1.71
0.45 - 4.0
0.45 - 1.625

SSCG
DisableEnableDisableEnableTHine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

7.7.

Error detection and indication

THCS251 has READY and INT for indicating Link status of CML Line communication.
READY indicates establishment of communication for GPIOs. INT indicates CML Link communication error.

Table 15 READY and INT
StatusREADY

Description

INT
[*1]

0

1 (pull-up)
0

1
1 (pull-up)

CML Link communication unlock state
GPIO cannot transmit
CML Link communication lock state
Bit level error occurred
CML Link communication lock stateNo error*1 INT buffer type is open-drain. “1” output means pull-up.

Copyright©2023 THine Electronics, Inc.

29/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

7.8.

Standby mode

THCS251 operates in Standby mode by setting STANDBY=1. The Standby mode is low power consumption andlow frequency sampling rate transmission mode. In Standby mode, THCS251 can transmit up to 8-bits GPIO
through handshake communication between Master mode and Slave mode. Polling period is 100ms.
READY is also enabled in Standby mode. When handshake communication is completed, READY goes from low
to high.

The GPIO pins shown in Table 16 are configured to Downstream, Upstream or Static state. On the other hand
D4/D30 - D30/D4 are fixed to Static state as Hi-Z.

D0/D34=>

D34/D0D1/D33=>

D33/D1

D2/D32=>

D32/D2

D3/D31=>

D31/D3

D4/D30
D30/D4

StaticD30/D4
D4/D30

D31/D3<=

D3/D31

D32/D2<=

D2/D32

D33/D1<=

D1/D33

D34/D0<=D0/D34

Data Pin for Slave mode

Data Pin for Master mode

Table 16 Standby mode direction setting“=>” means Downstream (GPIO input in Master mode and GPIO output in Slave mode).
“<=” means Upstream (GPIO input in Slave mode and GPIO output in Master mode).
Static” means GPIO pins are Static state.

Copyright©2023 THine Electronics, Inc.

30/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

8.

Package
TOP VIEW

9.00

LASER MARKFOR PIN1

9.00

BOTTOM VIEW
1.10

6.00
17

32

16

33

6.00

0.09 R

0.45

PIN1 ID
0.20 R1

48

0.05 MAX

0.40

0.20

SIDE VIEW

0.50

0.65

0.25

1.10

49

0.90 MAX

64

Figure 15 64-pin QFN package physical dimension
Unit : mm

Copyright©2023 THine Electronics, Inc.

31/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply tothe customer’s design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions
in this material. Please note even if errors or omissions should be found in this material, THine may not beable to correct them immediately.
3. This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverseengineer or disclosing to third parties the contents of this material without THine’s prior written permission isprohibited.
4. Note that even if infringement of any third party’s intellectual property rights should occur by using thisproduct, THine will be exempted from the responsibility unless it directly relates to the production process orfunctions of the product.
5. This product is not designed for applications that require extremely high-reliability/safety such as aerospacedevice, nuclear power control device, or medical device related to critical care, excluding when this product is
specified for automotive use by THine and used it for that purpose. THine accepts no liability whatsoever for
any damages, claims or losses arising out of the uses set forth above.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain
small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to havesufficiently fail-safe design principles such as redundant or error preventive design applied to the use of the
product so as not to have our product cause any social or public damage.
7. This product may be permanently damaged and suffer from performance degradation or loss of mechanicalfunctionality if subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge)
protection circuitry. Safety earth ground must be provided to anything in contact with the product, including
any operator, floor, tester and soldering iron.
8. Please note that this product is not designed to be radiation-proof.
9. Testing and other quality control techniques are used to this product to the extent THine deems necessary tosupport warranty for performance of this product. Except where mandated by applicable law or deemednecessary by THine based on the user’s request, testing of all functions and performance of the product is notnecessarily performed.
10. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Act in Japan and the Export Administration
Regulations in the United States of America on export or transit of this product. This product is prohibited forthe purpose of developing military modernization, including the development of weapons of mass destruction(WMD), and the purpose of violating human rights.
11. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings ormalfunction, if pins of the product are shorted by such as foreign substance. The damages may cause asmoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses. THine accepts no liability whatsoever for any damage or loss caused to the user due to
use under a condition exceeding the limiting values.

Copyright©2023 THine Electronics, Inc.

32/33

THine Electronics, Inc.

SC: E

THCS251_Rev.3.01_E

12. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or otherintellectual property rights concerned with this product belong to THine or licensor(s) of THine. No license or
right is granted to the user for any intellectual property right or other proprietary right now or in the future
owned by THine or THine’s licensor. The user must enter into a license agreement with THine or THine’s
licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

Copyright©2023 THine Electronics, Inc.

33/33

THine Electronics, Inc.

SC: E