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SOI

The 27th International Workshop on Vertex Detectors
21-26 October 2018
International Advisory Committee"MGM Beach Resorts" in Chennai, India.
Marina Artuso, Syracuse University
https://indico.cern.ch/event/710050/
Gian Mario Bilei, INFN Perugia
Daniela Bortoletto, University of OxfordRichard Brenner, Uppsala University
Davis Christian, Fermilab
Paula Collins, CERN
Zdenek Dolezal, Charles University in PragueLars Eklund, University of Glasgow
Francesco Forti, University of Pisa and INFN Pisa
Kazuhiko Hara, University of Tsukuba
Roland Horisberger, PSI
Manfred Kramer, CERN
Hans-Guenther Moser, Max Plank Institute for Physics, Munich
Hwanbae Park, Kyungpook University
Chris Parkes, University of Manchester
Sally Seidel, University of New Mexico
4 2018.11.22

Development of SOI Monolithic Pixel
Detector for Fine Measurement ofSpace and Time SOFISTK. Hara (Univ. Tsukuba)
for SOIPIX Collaboration

SOFIST development:
U. Tsukuba: K. Hara, D. Yamauchi, R. Abe, S. Iwanami, H. Murayama, K. Watanabe
KEK: T. Tsuboyama, M. Yamada, S. Ono, Y. Arai, Y. Ikegami, I. Kurachi, M. Togawa, J. Haba
Tohoku U.: Li. Taohan

Project supported by
JSPS Grant-in-Aid for Scientific Research on Innovative Areas (2013-2017)

OUTLINE
1. SOI PIXEL Sensor Development - Introduction
2. Highlights from 5-Year Grant-in-Aid (summary by Y. Arai)
3. SOFISTØ design & developments
Ø SOFIST-1 position resolution
Ø SOFIST-2 timestamp resolution
Ø SOFIST-3 quick evaluation
4. SOFIST-4 3D stacking
5. Summary

2018.11.22

6

SOI PIXEL DEVICES
SOI: SILICON-ON-INSULATORCMOS circuitry fabricated onburied oxide(BOX)LAPIS 0.2um FD-SOIFeatures:• Monolithic (no metal bumps)• SOI-CMOS (FETs fully isolated)• Can choose* substrate of optimum
resistivity (fully depleted CMOS
sensors possible)*SOITEC SmartCutTM

many excellent features•••

Material budget
S/Npower dissipation•••speedcostPixel size•••single event effects
latch upOperation temp. (0.3K570K)

TID tolerance improved to 1MGy by introducing double SOI wafer (HSTD11)

2018.11.22

7

GRANT-IN-AID (FY2013-17)

INTERDISCIPLINARY RESEARCH ON QUANTUM IMAGINGOPENED WITH 3D SEMICONDUCTOR DETECTOR

2018.11.22

8

25-26 Sept 2018
i n - ai dtnargImagingr
5-yearofnoitaappl i cweti u mnrrosofnoycdrag sensoni
ü B e regamiIish SOai (KE K)rA.
Yyü E s tablbr y tal kammus
I
ü SO





2018.11.22

9

HIGHLIGHT-1 (SOIPIX-PDD)

Fe-55





2018.11.22

10HIGHLIGHT-1 (SOIPIX-PDD)

Fe-55





2018.11.22

11HIGHLIGHT-2 (INTPIX4)
Integration&global shutter

Fe-55





2018.11.22

12

HIGHLIGHT-2 (INTPIX4)





2018.11.22

13

INTPIX4: Computed Tomography with Syncrotron X-ray

3mm(by R. Nishimura, K. Hirano (KEK)

2018.11.22

14

14

HIGHLIGHT-3 (FPIX2)µmµm
U Tsukuba/KEK

2018.11.2215

HIGHLIGHT-3 (FPIX2)

1.9
U Tsukuba/KEK

2018.11.22

16

HIGHLIGHT-4 (XRPIX5)



2018.11.22

17

HIGHLIGHT-4 (XRPIX5)





2018.11.22

18

HIGHLIGHT-4 (XRPIX5)

149eV/FWHM
20us→2~4us/line

Energy resolution as good as CCD’s
Much faster!
Muon veto possible

2018.11.22

19

SOFIST SOI MONOLITHIC PIXEL DETECTORFOR FINE MEASUREMENT OF SPACE AND TIME
Allows time and space point measurement
Design specified to meet the requirements for the ILC experiment
Main requirements:• Position resolution <3um
• Low material <0.2%Xo/layer• TID~1kGy/year• NIEL ~1011neq/cm2/year
Readout between trains
bunch ID highly preferredPower dissipation: <50mW/cm2
The goal is a sensor with both good spatial resolution of <3um and time resolution <1us.
ü pixel size ~20um-sq with analog readout
ü timestamp recording the ramping voltage
ü store the data allowing multiple hits on the same pixelü on-chip ADCs &zero-suppression for fast data transfer




2018.11.22

20

SOFIST PIXEL ARCHITECTURE
Start Vramp per beam train
Signals exceeding Vthshift-register chooses* memory cell to record
analog signal recorded
timestamp voltage recorded
Recorded memories are digitized by column ADCs
(8bit has been implemented)
Zero-suppression applicable

2018.11.22

Main requirements:• Position resolution <3um• Low material <0.2%Xo/layer• TID~1kGy/year• NIEL ~1011neq/cm2/year
Readout between trains
bunch ID highly preferred

21

SOFIST – IN DEVELOPMENT
FNALmtested )B e a an al o g(o n l yFNALmtested
B e a h bu t i n e l s )(bot rate pixs e pati o n l )aulaev e pixered
U n h i n s am(bo tdelivered

2018.11.22

Under 3D22

SOFIST-1 SPATIAL RESOLUTIONSOFIST residual to FPIX track (s_track~0.57/0.65µm)
Bias=130V (~500um depletion) =>15V (~200µm depletion)
Readout: external 12-b ADCs =>on-chip 8-b ADCs
SOFIST#2(BPW16x16)

SOFIST#1(BPW14x14)
plots for “black case”
140120Residual X

Residual X: 5
h_resx_4
Entries1784

Mean
Std Dev
χ2 / ndf

0.15032.795

Constant
Mean
Sigma

100
80

4020

h_resx_5220
200

12.1 / 9139.5 ± 5.81800.2746 ± 0.0553

160

1.504 ± 0.054

1.50
1.57
1.5860

EventsEventsResidual X: 42401

Mean
Std Dev
χ2 / ndf

0.1677

Constant

120

1.367 ± 0.035

1.37
1.49
1.33

100
80
6040

2.721
12.58 / 9227.7 ± 7.6
0.1668 ± 0.0386

Mean
Sigma

140

0.05 µm
0.08 µm
0.05 µm

Entries0.04 µm
0.06 µm
0.03 µm

200−15−10−5050−151015
Residual X [um]−10−5Residual Y

160

Entries

1784

140

Mean
Std Dev
χ2 / ndf

0.019722.825

120Constant

100

Mean
Sigma

1.381.55
1.546040

 

16.79 / 9148.5 ± 6.40.1282 ± 0.0481
1.378 ± 0.048

0.05 µm
0.08 µm0.04 µm200−151015
Residual X [um]h_resy_5

240

Entries

220

Mean

2002401− 0.1204

Std Dev

2.694

χ 2 / ndf

11.4 / 9180

Constant

160

Mean

0.06111 ± 0.03750

Sigma

1.348 ± 0.035

14080

S/N~300 (130V)~120 (15V)

5

Residual Y: 5
h_resy_4

EventsEventsResidual Y: 401.35
1.38
1.32

12010080
6040

231.2 ± 7.9

0.04 µm
0.05 µm
0.03 µm

20−10−52018.11.22

051015Residual Y [um]0−15−10Ono (KEK)−5051015
Residual Y [um]23

SOFIST-1 SPATIAL RESOLUTION
Track uncertainty (0.6um) subtracted

depletion
0um0um00~2~5Compatible with DEFFET ([22])η correction may improve further~040um

1000500





2018.11.22

Ono (KEK)

24

SOFIST-2 BEAM TEST 2018MAR
Beamline Setup
SOFIST(2mm )scint.+MPPC

INTPIX4 (17um , 8.7x14.1mm)
RoI(2,3,,mm ) adjustable

120GeV pevent tag

BUSY

INTPIX4RO

SOFISTROVramp

1ms

RO

spaceROspace&time
RO with external 12-bit ADCs

BUSYSTORE

500µs

spillevent tagtimestamp

Timing Chart 4.2s
2018.11.22

25

SOFIST-2 TIMESTAMP CALIBRATION
conducted on site

1ms1V

linear correlation
assumedAll pixels

Ttest=250usconducted on site
Ono (KEK)

2018.11.22

Ono (KEK)

26

SOFIST-2 TIMESTAMP CORRELATION
Correlation of timestamps in two SOFISTs
Overlapping events in same 500us gate

Ono (KEK)

Periodic clusters?



Timestamp resolution Ono (KEK)
2.78/√2=1.89us
2018.11.22

27

SIZE OF FNAL MAIN INJECTOR (MI)Yamada (KEK)

Beam structure due to bunch rotation in
the MI: 11us→3.3km (3319m actual)

2018.11.22

Yamada (KEK)28

c2 / ndf
58.94 / 19p0
12.14 ± 1.078
p1 3.866 ± 0.003468

500
Test-pulse input [µ s]

SOFIST-2 TIMESTAMP PRECISION
300

400

conducted on testbench

0200

400

600

800

1000

1200

1400

1600

1800

2000

100200Graph

ADC counts(0,0) linearity

ΔADC/Δdelay[us]Test pulse delay [us]Timestamp [ADC]

Murayama (Tsukuba)
Time spread for 500us delay pulses
Slight rowdependence

resolution~0.75us(~2.9ADC)
No notable position
dependence

2018.11.22

29

SOFIST-2 ANALOG SIGNAL
8BNW
p6725um

Yamada (KEK)

Cluster charge(HV dependence)-5V-20V





2018.11.22-40V
Yamada (KEK)30

SOFIST-2 FULL DEPLETION

Yamada (KEK)
Full depletion expected ~30V for 9x1012/cm3 (0.5kΩcm) concentration (measured)
S>700 ADC (N~5 ADC) for 67um thickness

2018.11.22

31

SOFIST-2 CLUSTER CHARGE

Mostly one-cluster events
Vth ~1/2 mippeak~300ADC: X-talk atComparator ONevents

Seed>10σ
3x3 cluster

Seed>3σVth ~1/4 mip should
be possible…

Yamada (KEK)

2018.11.22

Yamada (KEK)32

SOFIST-3 – QUICK TEST
Both functions implemented on 30um pixels

S. Ono(KEK)

2018.11.22

33

SOFIST-3 – PIXEL LAYOUT..

SFanalog..
X2 fortimestamp

Yamada (KEK)30um

2018.11.22

MIM(50fF, 1.5fF/um2)
1 for CDS
2 for comparator

34

SOFIST VER.4
Upper pixel

Lower pixel

Shift-register

Up to comparator
VTH

PIX_TRG_SEL_X

COMP_ENREGOUT_1

SREG_INCOMP_OFFD

REGOUT_2

Q

DQ

REGOUT_3

DQ

PIX_TRG
TIN

Q

CF_RST_X

PAD PADQQ

REG_RST

RST_COMP1
RST_COMP2

Shift-registers
3 Memory cells each

Comparator

TEST

CDS

VB_CSA

VB_NSFCDS_RSTREGOUT_1

Pre-amp(Charge sensitive amplifier+ N-SF )SW1

PIX_SIG

VB_CDS_RST

AOUT_1VB_NSFBuﬀer-amp(N-SF)REGOUT_1

Output amplifier

SW1

Output amplifier
TOUT_1

RAMP_IN

PAD PADREGOUT_2

REGOUT_2

SW2

SW2

AOUT_2

TOUT_2REGOUT_3

REGOUT_3

SW3

SW3

AOUT_3

TOUT_3AOUT_SEL_X

COLOUT_1/2/3

AOUT_1/2/3
TOUT_1/2/3
REGOUT_1/2/3

20um

2018.11.22

TOUT_SEL_X
REGOUT_SEL_X

35

3D IS COMING (SOFIST-4)
Cylinder-type is more reliable

T-Micro slight mis-alignment to UBM ⇒corrected
Upper&lower bumps are stacked well(peel off one sensor layer)
Bonding<200degC

2018.11.22

36

REMAINING PROCESSES (SOFIST-4)
etching8μm(d) Bulk-Si removal
glue injection
High R-Si

Bond Pad

Passivation

Back gate adjust electrode(e) Pad patterningand passivation

High R-Si

T-Micro

2018.11.22

37

ILC 1-PAGE SUMMARY••

SID: VTX AND SILICON TRACKER
Baseline pixel pitch: 20×20 μm2
Technology options: either monolithic CMOS chip ➠ Chronopix
or 3D vertically integrated silicon

ILD: VTX & Silicon Tracking System•

Barrel (VTX): 3 double-sided ladders• Inner layers (< 300 cm2), SIT: priority on readout, speed and σsp
16×16/80 μm2 pixels and binary o/p: tro ~ 50/8 μs and σsp ~ 3/5 μm• Outer layers (~3000 cm2), SET: importance of power consumption and σsp
35×35 μm2 pixels and 3-4 bit charge encoding: tro ~ 100 μs and σsp ~ 4 μm
• R&D on several technologies, namely DEPFET, FPCCD, SOI and CMOS



2018.11.22

38

CLIC 1-PAGE SUMMARY
To reach impact parameter resolution:- Spatial resolution: 3 μm
- Material: 0.2 % X0/layer
To reduce impact of beam-beam background:- Pixel size of 25 μm x 25 μm, timing resolution O(ns)Moderate radiation exposure (~104 below LHC):- NIEL: < 1011 neq/cm2/y, TID: < 1 kGy / year
CLICpix: - 4 bit ToT and ToA, 64 x 64 pixels
CLICpix2: - 5 bit ToT and 8 bit ToA,128 x 128 pixels- 65 nm CMOS technology- Pixel size of 25 μm x 25 μm- Power pulsing

Bump bond orCapacitive coupling

CLICpix2 (hybrid)

Cracow SOI test-chip produced in 200 nm LAPIS SOI process- pixel size >= 30 μm x 30 μm σ=3um- High resistivity substrate with thickness of 500 μm
HR-CMOSSpatial resolution below 7 μm for threshold values of ~400e- Fully efficient operations to threshold values below ~400e- Timing resolution ~ 6 ns

2018.11.22

In Investigator chip39

SUMMARY (SOI)
q 5-year Grant-in-Aid (2013-2017) accelerated
development/application of various SOI devices.
q SOFIST has been tested in FNAL beam
SOFISTv1 <20um pixel size>
spatial resolution:
1.3 um(500um)-1.4 um (200um) with no h-correction applied
SOFISTv2 <25um pixel size>
time resolution: 1.89us (linear calibration)
good S/N~120 for 67um thickness
cluster size~1 (Vth was set slightly high)- spatial resolution results to come shortly
q SOFISTv3 is to be beam tested
q SOFISTv4 fabrication is underway
q Submitting new 5-year Grant-in-Aid application

2018.11.22

40