THCS251_Design_Guide_Rev.2.10_E

THCS251
35bit GPIO High Speed Bus Signal Transceiver
System Design Guide

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THCS251_Design_Guide_Rev.2.10_E

Contents
Contents.................................................................................................................................................................. 2
Connection Selection Guide: Standard Application 1........................................................................................ 3
Connection Selection Guide: Standard Application 2........................................................................................ 4
Example1-1. Bi-directional transmit using internal oscillator -1-..................................................................... 5
Example1-2. Bi-directional transmit using external reference clock -2- .......................................................... 6
Example2. Uni-directional transmit using internal oscillator ........................................................................... 7
Baud rate calculation method for UART communication ................................................................................. 8
SCLK frequency calculation method for SPI communication .......................................................................... 9
Design Guideline for Power Supply ................................................................................................................... 11
Design Guideline for High-Speed Signal ........................................................................................................... 12
Notices and Requests ........................................................................................................................................... 13

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THCS251_Design_Guide_Rev.2.10_E

Connection Selection Guide: Standard Application 1■Example1-1. Bi-directional transmit using internal oscillator. -1-Internal clock frequency: 20MHz-Downstream: 18bit-Upstream: 17bit-Output: Push-Pull[Details: Page.5.]
THCS251 Master
Data Input(18bit)Down Link
Serializer
Internal
Oscillator

Data Output(17bit)High Speed CML
Downstream

THCS251 Slave

Down Link
De-Serializer

Data Output(18bit)Up Link
Serializer

Data Input(17bit)(20MHz)Up Link
De-Serializer

High Speed CML
Upstream■Example1-2. Bi-directional transmit using external reference clock. -2-Downstream: 18bit-Upstream: 17bit-Output: Open-Drain*Some I/O Pins are 5V tolerant.
[Details: Page.6]
THCS251 Master
Data Input(5V Tolerant_4bit)(14bit)Clock Input
Data Output(13bit)(5V Tolerant_4bit)

High Speed CML
Downstream

Down Link
Serializer

THCS251 Slave
Data Output

Down Link
De-Serializer

Internal
Oscillator

Up Link
De-Serializer

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(5V Tolerant_4bit)(14bit)Clock Output
Data Intput

High Speed CML
Upstream

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Up Link
Serializer(13bit)(5V Tolerant_4bit)

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Connection Selection Guide: Standard Application 2■Example2. Uni-directional transmit using internal oscillator-Internal clock frequency: 20MHz-Downstream: 35bit-Upstream: -Output: Push-Pull[Details: Page.7]
THCS251 Master
Data Input(35bit)High Speed CML
Downstream

Down Link
Serializer
Internal
Oscillator

THCS251 Slave
Down Link
De-Serializer

Data Output(35bit)(20MHz)Up Link
De-Serializer

Up Link
Serializer
LOCKN(High or Low)

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Example1-1. Bi-directional transmit using internal oscillator -1This case shows bi-directional transmit 18bit downstream and 17bit upstream using internal oscillator (20MHz).
It can be reduced the external parts by using internal oscillator.
Pin settings are as follows.
[Chip-Master/Slave common settings]*1. RESERVED (#63) is must be tied to Low.
*2. DIRSEL0 (#46), DIRSEL1 (#47) and DATA_WIDTH (#50) are set Low to support the 18bit downstream and17bit upstream.
*3. OBUF (#49) is set High to select Push-Pull output type.
[Only Chip-Master settings]*4. MSSEL (#1) is set Low to select Chip-Master.
*5. REFEN (#45) is set Low to use internal oscillator.
*6. RF/OSCSEL0 (#2) and REFIN/REFOUT/OSCSEL1 (#26) are set Low to select internal oscillator frequency as
20MHz.
*7. SSEN (#4) can be set Spread Spectrum. In this case, the Spread Spectrum is OFF.
[Only Chip-Slave settings]*8. MSSEL (#1) is set High to select Chip-Slave.
*9. REFEN (#45) is set Low to disable the clock output from REFIN/REFOUT/OSCSEL1 (#26).
*10. RF/OSCSEL0 (#2) is disabled and should be connected to GND.
*11. SSEN (#4) is disabled and should be connected to GND.
[Other settings]*12. RESETN (#62) and STANDBY (#48) can be controlled regardless of the above settings.
*13. FILTSEL0 (#5) and FILTSEL1 (#64) are enabled to control digital filters.
In this case, the digital filter of 8 stages is selected.
*14. Damping resistor (ex. 33Ω) should be put close each Push-Pull output pin of the device.
THCS251
Master

LVCMOS Driver

THCS251
Slave*14

D0/D34

D34/D0D1/D33

D33/D1

D16/D18

D18/D16(18bit)(18bit)D17/D17*2

D17/D17

VDD
*6

*2

D19/D15*2

VDD

REFIN/REFOUT/OSCSEL1

D18/D16

REFIN/REFOUT/OSCSEL1
10kΩ

10kΩ

TP

TP

INT/LOCKN

INT/LOCKNREADY/BETOUTREADY/BETOUTOPEN *9*2

D16/D18

D15/D19(17bit)(17bit)0.1uF

D33/D1
D34/D0LVCMOS Receiver

0.1uF

TXN

Cable

RXN

TXP

Cable

RXP

*12 RESETN*120Ω

*12 STANDBYRESETN

VDD
NC

*12

STANDBYRESETNRESERVED*2

DATA_WIDTH*2DIRSEL0*2

DIRSEL1
OBUF

*4

MSSEL

*5

REFEN

*6

RF/OSCSEL0

*13

0.1uF

RXN

Cable

TXN

RXP

Cable

TXP

STANDBY

*1

*3

0Ω

D0/D34
LVCMOS Driver

VDD
NC

D1/D33

*14

0.1uF
VDD

LVCMOS ReceiverRESETNSTANDBY
TEST1

TEST1

TEST2

TEST2

10uF

10uF
CAPOUTCAPOUT

0.1uF

0.1uF

0.1uF

0.1uF

CAPINA

CAPINA

CAPINP

CAPINPRESETN *12
STANDBY *12

RESETNVDD

ENI2C0*1

DATA_WIDTH*2DIRSEL0*2

DIRSEL1

*2

OBUF

MSSEL
*9

RF/OSCSEL0*10

FILTSEL1

FILTSEL1

FILTSEL0FILTSEL0

*13

*7

SSEN

SSEN

*11

5/14

VDD

*8

REFEN

0Ω

NC

*12
*3

*13

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VDD

*12

STANDBY

NC

0Ω

*13

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Example1-2. Bi-directional transmit using external reference clock -2This case shows bi-directional transmit 18bit downstream and 17bit upstream using external reference clock.
Pin settings are as follows.
[Chip-Master/Slave common settings]*1. RESERVED (#63) is must be tied to Low.
*2. DIRSEL0 (#46), DIRSEL1 (#47) and DATA_WIDTH (#50) are set Low to support the 18bit downstream and17bit upstream.
*3. OBUF (#49) is set Low to select Open-Drain output type.
[Only Chip-Master settings]*4. MSSEL (#1) is set Low to select Chip-Master.
*5. REFEN (#45) is set High to use external clock that is input to REFIN/REFOUT/OSCSEL1 (#26).
*6. RF/OSCSEL0 (#2) is enabled and it is adjusted to external clock edge.
*7. SSEN (#4) can be set Spread Spectrum. In this case, the Spread Spectrum is OFF.
[Only Chip-Slave settings]*8. MSSEL (#1) is set High to select Chip-Slave.
*9. REFEN (#45) is set High to enable the clock output from REFIN/REFOUT/OSCSEL1 (#26).
*10. RF/OSCSEL0 (#2) is enabled and adjusted to clock edge of the later device.
In this case, RF is Low and it is set as Fall Edge.
*11. SSEN (#4) is disabled and should be connected to GND.
[Other settings]*12. RESETN (#62) and STANDBY (#48) can be controlled regardless of the above settings.
*13. FILTSEL0 (#5) and FILTSEL1 (#64) are enabled to control digital filters.
In this case, the digital filter of 8 stages is selected.
*14. Some I/O Pins are 5V tolerant.
5V LVCMOS Driver

THCS251
Master

LVCMOS Driver*14
5V Tolerant(4bit)(14bit)

THCS251
Slave

D0/D34

D34/D0D1/D33

D33/D1

D2/D32

D32/D2

D3/D31

D31/D3

VDD

REFIN/REFOUT/OSCSEL1 VDD
VDD

5V

10kΩ

10kΩ

TP

TP

READY/BETOUT

D32/D2

D33/D1*12 RESETN

0Ω*12 STANDBYRESETN

TXN

Cable

RXN

D2/D32

TXP

Cable

RXP

D1/D33VDD
NC

0Ω

RESERVED*2

DATA_WIDTH*2DIRSEL0*12*2

DIRSEL1

STANDBY

*3

OBUF

*4

MSSEL

*5

REFEN

*6
*13

0.1uF

RXN

Cable

TXN

RXP

Cable

TXP

STANDBY*1

RF/OSCSEL0*14
5V Tolerant(4bit)

D0/D34RESETN

VDD
NC(13bit)D3/D31

0.1uF

0.1uF

*12

LVCMOS Driver

READY/BETOUT

D34/D0VDD*9

D16/D18 - D4/D30
0.1uF

D31/D3*14
5V Tolerant(4bit)(14bit)REFIN/REFOUT/OSCSEL1

D18/D16 – D30/D4(13bit)10kΩ

INT/LOCKN

INT/LOCKN

10kΩ

VDD

D30/D4 – D17/D17

D4/D30 - D17/D17*5*14
5V Tolerant(4bit)RESETNSTANDBY
TEST1

TEST1

TEST2

TEST2

10uF

10uF
CAPOUTCAPOUT

0.1uF

0.1uF

0.1uF

0.1uF

CAPINA

CAPINA

CAPINP

CAPINPRESETN *12
STANDBY *12

RESETNNC*1

DATA_WIDTH*2DIRSEL0*2

DIRSEL1

*2

*12

OBUF

*3

STANDBY

VDD

MSSEL

*8

REFEN

*9

RF/OSCSEL0

NC
0Ω

*10

FILTSEL1*13

FILTSEL0FILTSEL0

*13

*7

SSEN

SSEN

*11

6/14

0Ω

VDD

RESERVEDFILTSEL1

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VDD
*12

*13

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Example2. Uni-directional transmit using internal oscillator
This case shows uni-directional transmit 35bit downstream using the internal oscillator (20MHz).
It can be reduced the external parts by using internal oscillator. The High Speed Signal line is only 1 Pair.
Pin settings are as follows.
[Chip-Master/Slave common settings]*1. RESERVED (#63) is must to be tied to Low.
*2. DIRSEL0 (#46) and DIRSEL1 (#47) are set High and DATA_WIDTH (#50) is set High to support the connectionof the 35bit downstream.
[Only Chip-Master settings]*3. MSSEL (#1) is set Low to select Chip-Master.
*4. REFEN (#45) is set Low to use internal oscillator.
*5. RF/OSCSEL0 (#2) and REFIN/REFOUT/OSCSEL1 (#26) are set Low to select internal oscillator frequency as
20MHz.
*6. OBUF (#49) is disabled and should be connected to GND.
*7. SSEN (#4) can be set the Spread Spectrum.
In this case, the Spread Spectrum is OFF.
[Only Chip-Slave settings]*8. MSSEL (#1) is set High to select Chip-Slave.
*9. REFEN (#45) is set Low to disable the clock output from REFIN/REFOUT/OSCSEL1 (#26).
*10. RF/OSCSEL0 (#2) is disabled and should be connected to GND.
*11. OBUF (#49) is set High to select Push-Pull output type.
*12. SSEN (#4) is disabled and should be connected to GND.
[Other settings]*13. RESETN (#62) and STANDBY (#48) can be controlled regardless of the above settings.
*14. FILTSEL0 (#5) and FILTSEL1 (#64) are enabled to control the digital filters.
In this case, the digital filter of 8 stages is selected.
*15. Damping resistor (ex. 33Ω) should be put close each Push-Pull output pin of the device.
*16. INT/LOCKN (#60) is connected to Pull Up at the Chip-Master side.
*17. Unused TXN/P and RXN/P should be open.
THCS251
Master

LVCMOS Driver

THCS251
Slave*15

D0/D34

D34/D0D1/D33

D33/D1

D33/D1

D1/D33

D34/D0D0/D34(35bit)

LVCMOS Receiver(35bit)*2*5

REFIN/REFOUT/OSCSEL1

VDD

*2

REFIN/REFOUT/OSCSEL1

OPEN *910kΩ

*16

INT/LOCKNREADY/BETOUT

*16

TP

TP

0.1uF

*13 RESETN

VDD
*13

0Ω

*13 STANDBYRESETN
NC

*1

VDD
NC

*13

DATA_WIDTH*2DIRSEL0*2

DIRSEL1

STANDBY
0Ω

*6

OBUF

*3

MSSEL

*4

REFEN

*5

RF/OSCSEL0

*14

RXN

TXP

Cable

RXP

RXP

RESERVED

*2

0.1uF
Cable

STANDBY

VDD

READY/BETOUT

TXN

RXN
RESETNINT/LOCKN

OPEN

OPEN

*17

*17

TXN

TXP

TEST1

TEST1

TEST2

TEST2

10uF

10uF

CAPOUTCAPOUT

0.1uF

0.1uF

CAPINA

CAPINA
0.1uF

RESETNSTANDBY

0.1uF

CAPINP

CAPINPRESETN *13
STANDBY *13

RESETNRESERVEDNC*1

DATA_WIDTH*2DIRSEL0*2

DIRSEL1

*2

*13

OBUF

*11

STANDBY

MSSEL

*8

REFEN

*9

RF/OSCSEL0*10

FILTSEL1

FILTSEL1

FILTSEL0FILTSEL0

*14

*7

SSEN

SSEN

*12

7/14

0Ω

VDD

*14

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VDD
*13

VDD
NC

0Ω

*14

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Baud rate calculation method for UART communication
When propagating UART signals, sampling errors on the GPI pin that inputs the UART signals limit the baudrate of the UART device and the clock accuracy of the baud rate generator compared to when THCS251 is not
used.
The following is an example of a UART communication method with 1-bit start bit, 8-bit data without parity,
1-bit stop bit, and 16 times baud rate oversampling for the receiving device.
Detect High to Low
transition

10bit
9.5bit0.5bit(8cycle)ST

1bit(16cycle)

D0

D1

D2

D3

D4

D5

D6

D7

SP

The receiving device considers the sampling data 0.5 bits (8 sampling cycles) after detecting Low to be thestart bit if it is Low, and then captures 8 bits of data and 1 bit of stop bit every 1 bit (16 sampling cycles) for a
total of 9 times. In this case, if each bit is ideally sampled in the center, there is a margin of ±0.5 bits relative tothe sampling point. However, it is necessary to take into account the sampling error in detecting the first low at
the receiving side (one sampling period at the receiving side), the input setting time, the THCS251 sampling
error, and the baud rate error between transmission and reception, which requires attention in asynchronous
communications. Since the baud rate is generated by dividing the clock source of the UART transmitter/receiverdevice, an error in the clock source can be considered a baud rate error as it is. It should also be noted that baudrate error is different in nature from sampling error and is an accumulated error. In other words, in order toaccurately sample the stop bit 9.5 bits after the first low is detected, there must remain a margin of at least the
input setup and hold time required for the receiving device after 9.5 bits. Therefore, the allowable baud rate error
per bit is the remaining time after subtracting each sampling error and setup time from the 0.5-bit margin,
divided by 9.5 bits. This results in the following equation for the baud rate tolerance between UART
transmitting and receiving devices.
1
1
1
1
{(
−
−
− 𝑡𝑆𝐻) ÷ 9.5} ÷× 100 > 𝐵𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 𝑡𝑜𝑙𝑒𝑟𝑎𝑛𝑐𝑒(%)
2 × 𝐵𝐴𝑈𝐷 16 × 𝐵𝐴𝑈𝐷 𝑅𝐸𝐹𝐶𝐾
𝐵𝐴𝑈𝐷
BAUD
: Baud rate (Hz)REFCK ：THCS251 operation frequency (Hz)tSH
：UART device input setup/hold time, whichever is greater (sec)Note that the baud rate error is the relative difference in baud rates generated at each of the transmitter andreceiver. For example, if your device has a tolerance of ±2% on the transmit side and ±1% on the receive side
for the clock source, the relative maximum error is 3%.
With a UART device input setup and hold time of 10ns and a THCS251 internal oscillator set to 80MHz(*tOSC = max.15.7ns), the acceptable baud rate error for UART communication at a baud rate of 1Mbps isapproximately 4.3% according to the above formula. The baud rate error is about 4.3%.If the maximum baudrate error of the UART device used is 4%, it means that communication is possible at a maximum baud rate of
2.56 Mbps. However, since there may be factors other than the above formulas such as transition time dependingon the environment, the above calculations should be considered only as a guide and should be used with asufficient margin.

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SCLK frequency calculation method for SPI communication
Write operation
It is calculated by the following formula, which takes into account the sampling error at the GPI pin input andthe setup/hold time of the SPI Target device input.
1
1>() + 𝑡𝑆𝑈𝑃/𝑡𝐻𝐿𝐷
2 × 𝑓𝑆𝐶𝐿𝐾
𝑅𝐸𝐹𝐶𝐾
fSCLK
REFCK
tSUP/tHLD: SCLK frequency (Hz): THCS251 operation frequency (Hz): SPI Controller device input setup/hold time (sec)

If the tSUP/tHLD time is 10ns and REFCK is 80MHz, the maximum SCLK is 22MHz from the above formula.

Read operation
Read speed is limited by the delay (tTCD, tRCD) between Primary/Secondary of THCS251 and sampling error(equivalent to REFCK) at GPI pin input.
The timing chart for SPI read is shown below.
SS

SCLK

MOSI

7

6

5

4

3

2

1

0

MISO

7

6

5

4

3

2

1

0

1/fSCLK
1/(2×fSCLK)SCLKSPI Controller/THCS253

MOSI

0
tSUP

MISO

tTCD

7

tRCD

SCLK

THCS253/SPI Target

MOSI

0

tRES

7

MISO

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THCS251_Design_Guide_Rev.2.10_E
For the SPI Controller device to sample Read data correctly, the total delay shown in the timing chart above mustbe less than SCLK period x 1/2. Since the above timing chart does not show the sampling error due toasynchronous sampling of THCS251, the following equation is obtained by adding the sampling error (1/REFCK)
to tTCD and tRCD.
1
1
1> (𝑡𝑇𝐶𝐷 +) + 𝑡𝑅𝐸𝑆 + (𝑡𝑅𝐶𝐷 +) + 𝑡𝑆𝑈𝑃
2 × 𝑓𝑆𝐶𝐿𝐾
𝑅𝐸𝐹𝐶𝐾
𝑅𝐸𝐹𝐶𝐾
fSCLK
REFCK
tTCD
tRCD
tRES
tSUP

:
:
:
:
:
:

SCLK frequency (Hz)THCS251 operation frequency (Hz)THCS251 Primary to Secondary delay time (sec)
THCS251 Secondary to Primary delay time (sec)
SPI Target device response time (sec)
SPI Controller device input setup time (sec)Assuming that the response time of the SPI target device and the input setup time of the SPI controller device
are 10ns each, the calculation results are as follows.
𝑓𝑆𝐶𝐿𝐾 < 600𝐾𝐻𝑧
REFCK
tTCD
tRCD
tRES
tSUP

:
:
:
:
:

64MHz * Minimum frequency when the built-in OSC is set to 80 MHz.
12.5ns(64MHz)×25=390.6ns *digital noise filter disable
12.5ns(64MHz)×25=390.6ns *digital noise filter disable
10ns
10ns

The above calculation example shows the maximum SCLK frequency when the built-in OSC is used, but a faster
SCLK frequency can be supported by using the REFCK input pin to input a high-speed clock. When a 133 MHz
clock signal is input to the REFCK input pin, the maximum SCLK frequency is 1.2 MHz.
In the actual environment, multiple target devices are connected on the SPI bus, which deteriorates thetransition time. The delay caused by this transition time deterioration cannot be ignored. In this case, the amountof delay due to transition time must be added to the right side of the above equation.
In the THCS series, either an external REFIN input or an internal oscillator can be selected as the REFCK, but itshould be noted that the internal oscillator has a large frequency error. When using the THCS series productbuilt-in oscillator, calculate using the maximum value of tOSC specified in the datasheet.

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Design Guideline for Power Supply
Insert filters (Ferrite Beads and Capacitors) in the Power Supply (VDD and AVDD).
And insert Bypass Capacitor (0.1uF) in the Power Supply pins.
This device is equipped with a 1.2V built-in regulator
Insert Bypass Capacitors (CAPOUT: 10uF and CAPINA/CAPINP: 0.1uF) also for this regulator.
Bypass Capacitors should be attached just near the device.
Insert the GND-Via to the Exposed-Pad to strengthen.
Ferrite Beads

0.1uF

Power
SupplyVDD

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

Ferrite Beads

0.1uF

32

50

31

51

10uF

30

52

AVDD

29

53

CAPOUT

28

54

27

55

26

56 CAPINAVDD 25

Exposed-Pad

0.1uF

57

24

58
59

23
22

CAPINP

60

21

61

20

62

19

63

18
VDD

0.1uF

0.1uF

64

1

2

3

4

5

6

7

8

9

17

10 11 12 13 14 15 16

0.1uF

Top Layer

Bottom Layer
0.1uF

0.1uF
VDD

10uF

AVDD
CAPOUTCAPOUT

Grand Via
0.1uF

0.1uF
VDD

CAPINA

CAPINA

0.1uF
CAPINP

ExposedPad

VDD

CAPINP

0.1uF

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THCS251_Design_Guide_Rev.2.10_E

Design Guideline for High-Speed Signal
TXP/TXN and RXP/RXN are differential pairs of high-speed serial signals.
Differential pairs should be closely spaced and coupled to eliminate common mode noise.
Also, differential should be designed as 100Ω differential characteristic impedance (Zdiff).
The following is an example of microstrip line design.
The high-speed signal lines trace in only single layer.
The AC coupled capacitors should be attached just near the device.

Top Layer

48 47 46 45 44 43 42
49
50
Connector

Connector

51
AC Couple
capacitor

52
53

0.1uF

54 RXP

0.1uF

55 RXN

0.1uF
0.1uF

56

RXN/RXP

57 TXN

TXP/TXN

58 TXPAC Couple
Capacitor

Connector

59
60
61
62
63
64
1

2

3

4

5

6

7

Differential signal traces (Microstrip Lines)> 3 x S1

Layer1: Signals

GND

S1

> 3 x S1

GND

Layer2: Ground

Layer3: Power

Layer4: Signals

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THCS251_Design_Guide_Rev.2.10_E

Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may notalways apply to the customer’s design. THine Electronics, Inc. (“THine”) is not responsible
for possible errors and omissions in this material. Please note even if errors or omissions
should be found in this material, THine may not be able to correct them immediately.
3. This material contains THine’s copyright, know-how or other intellectual property rights.

Copying, reverse-engineer or disclosing to third parties the contents of this material without
THine’s prior written permission is prohibited.
4. THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION

WITH ANY DISPUTE RELATING TO INTELLECTUAL PROPERTY RIGHTSBETWEEN THE USER AND ANY THIRD PARTY, ARISING OUT OF THIS PRODUCT,EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELYTO THINE. NOTE, HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINEACCEPTS NO LIABILITY FOR SUCH DAMAGE OR LOSS IF THE DISPUTE IS
CAUSED BY THE USER’S INSTRUCTION.
5. This product is not designed for applications that require extremely high-reliability/safety suchas aerospace device, nuclear power control device, or medical device related to critical care,excluding when this product is specified for automotive use by THine and used it for that
purpose. THine accepts no liability whatsoever for any damages, claims or losses arising outof the uses set forth above.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will

occur with a certain small probability, which is inevitable to a semi-conductor product.
Therefore, you are encouraged to have sufficiently fail-safe design principles such as
redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. This product may be permanently damaged and suffer from performance degradation or loss of

mechanical functionality if subjected to electrostatic charge exceeding capacity of the ESD(Electrostatic Discharge) protection circuitry. Safety earth ground must be provided toanything in contact with the product, including any operator, floor, tester and soldering iron.

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THCS251_Design_Guide_Rev.2.10_E
8. Please note that this product is not designed to be radiation-proof.
9. Testing and other quality control techniques are used to this product to the extent THine deems

necessary to support warranty for performance of this product. Except where mandated byapplicable law or deemed necessary by THine based on the user’s request, testing of all
functions and performance of the product is not necessarily performed.
10. This product must be stored according to storage method which is specified in thisspecifications. THine accepts no liability whatsoever for any damage or loss caused to the user
due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the

category of strategic goods under the Foreign Exchange and Foreign Trade Act in Japan andthe Export Administration Regulations in the United States of America on export or transit ofthis product. This product is prohibited for the purpose of developing military modernization,
including the development of weapons of mass destruction (WMD), and the purpose of
violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute

maximum ratings or malfunction, if pins of the product are shorted by such as foreign
substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to
implement safety measures by adding protection devices, such as fuses. THine accepts noliability whatsoever for any damage or loss caused to the user due to use under a condition
exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitationrights or other intellectual property rights concerned with this product belong to THine or
licensor(s) of THine. No license or right is granted to the user for any intellectual property
right or other proprietary right now or in the future owned by THine or THine’s licensor. The
user must enter into a license agreement with THine or THine’s licensor to be granted of suchlicense or right.

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