THC63LVDM87_DesignGuide_Rev.1.20_E

THC63LVDM87
System Diagram and PCB Design Guide

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THC63LVDM87_DesignGuide_Rev.1.20_E

Contents
1. CMOS/TTL Data Timing Diagram

P.3

2. LVDS Data Timing Diagram

P.4

3. Example of System Diagram
1) 8bit CMOS/TTL Input / IO VCC = 1.8V
2) 6bit CMOS/TTL Input / IO VCC = 3.3V

P.6
P.7

4. NOTE

P.8

5. Trace Example for BGA

P.9

6. PCB Design Guide Line for LVDS

P.10

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THC63LVDM87_DesignGuide_Rev.1.20_E

1. CMOS/TTL Data Timing Diagram

HSYNC
DEDotCLK
R1x/G1x/B1x#1#2#1#2#3#4#1919 #1024
#1920
1918
1022 #1023#1920#1919 #1024#1023

TFT Panel(1024x 768)
(1920x1200)

Note :MSB

6Bit LSB
8Bit LSB

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Red
R7R6R5R4R3R2R1R03

Green
G7
G6G5G4G3G2G1G0Blue
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THC63LVDM87_DesignGuide_Rev.1.20_E

2. LVDS Data Timing Diagram

Vdiff = 0V

Vdiff = 0V

TCLK OUT(Differential)

Tx+/x=A,B,C,D,E

Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0

Previous Pixel DataPixel Data

THC63LVDM87 Pixel Data Assign _ JEITA (6bit, 8Bit Application)
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD66Bit
R2
R3
R4
R5
R6
R7
G2
G3G4G5G6G7B2B3B4B5B6B7Hsync
Vsync
DE-8Bit
R2R3R4R5R6R7G2G3G4G5G6G7B2B3B4B5B6B7Hsync
Vsync
DER0R1G0G1B0
B1
N/A

Note : For 6Bit application use A to C channel and open TD+/- pin.

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THC63LVDM87_DesignGuide_Rev.1.20_E

THC63LVDM87 Pixel Data Assign _VESA (6bit, 8Bit Application)
TA0
TA1
TA2
TA3
TA4TA5TA6TB0
TB1
TB2
TB3
TB4
TB5
TB6TC0TC1TC2TC3TC4TC5TC6TD0
TD1TD2TD3TD4TD5TD66Bit
R0R1R2R3R4R5G0G1G2G3G4G5B0B1B2B3B4B5Hsync
Vsync
DE-8Bit
R0R1R2R3R4R5G0G1G2G3G4G5B0B1B2B3B4B5Hsync
Vsync
DER6R7G6G7
B6B7N/A

Note : For 6Bit application use A to C channel and open TD+/- pin.

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THC63LVDM87_DesignGuide_Rev.1.20_E

3. Example of System Diagram
1) 8 bit 1.8V CMOS/TTL Input
THC63LVDM87 Setting : Falling edge / Normal swing / JEITA mapping
PCB Transmitter

PCB Receiver

1.8 VCC
F.BeadF.Bead
0.01uF
0.1uF

0.01uFVCC
GND

LVDS VCC
0.1uF

0.01uFIO VCC
0.1uF
0.01uF
PLL VCC

/PDWN
R/F

0.1uF

R1100ohm pair cableor
PCB trace

RS
R2
CLKIN
R2
R3R4
R5
R6R7G2G3G4G5G6G7B2B3B4B5B6B7HSYNC
VSYNC
DE
R0R1G1G0
B0B1

CLKIN
TA0TA1TA2TA3TA4TA5TA6TB0TB1TB2TB3TB4TB5TB6TC0TC1TC2TC3TC4TC5TC6TD0TD1TD2TD3TD4TD5TD6TATA+100ohm

TBTB+100ohm

TCTC+100ohm

TCLKTCLK+100ohm

TDTD+100ohm

Setting
IO VCCGND/PDWN
Normal Operation
Power Down

Setting
IO VCC
GND

R/F
Input Clock Triggering Rising Edge
Input Clock Triggering Falling Edge

R10ohmNC (default)

R2NC
0ohm (default)

GND

COMS/TTL
1.8V
1.8V

LVDS Receiver
CircuitGND

RS
LVDS=350mV
LVDS=200mV

Note :Regarding the /PDWN, please use switching if needed.
Regarding the R/F and RS pin, please select IOVCC level or GND level it depends onuser operation.
Please prepare the 100ohm pair cable or PCB pattern trace that is controlled with 100ohm forLVDS signal.
Connect each Board GND
COMS/TTL input pin that not in use, it must be tied to GND.

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THC63LVDM87_DesignGuide_Rev.1.20_E

2) 6 bit 3.3V CMOS/TTL Input
THC63LVDM87 Setting : Falling edge / Normal swing / JEITA mapping
PCB Transmitter
3.3 VCCPCB Receiver

1.8 VCC
F.BeadF.Bead0.01uF

0.1uF

0.01uFVCC
GND

LVDS VCC
0.1uF

0.01uFIO VCC
0.1uF
0.01uF/PDWN
R/F

PLL VCC
0.1uF

R1100ohm pair cable
orPCB traceRS
R2CLKIN
R2R3
R4R5
R6R7G2G3G4G5G6G7B2B3B4B5B6B7HSYNC
VSYNC
DE

CLKIN
TA0TA1TA2
TA3
TA4TA5TA6
TB0TB1TB2
TB3
TB4
TB5TB6
TC0TC1TC2TC3TC4
TC5TC6
TD0TD1
TD2
TD3TD4TD5TD6TATA+

100ohmTBTB+

100ohm

TCTC+

100ohmTCLKTCLK+
TDTD+Setting
IO VCC
GND/PDWN
Normal Operation
Power DownSetting
IO VCC
GND

R/F
Input Clock Triggering Rising Edge
Input Clock Triggering Falling Edge

R10ohmNC (default)

R2NC0ohm (default)

100ohmOPENOPEN

GND

COMS/TTL
1.8V
3.3V
1.8V
3.3V

LVDS Receiver
CircuitGND

RS
LVDS=350mV
LVDS=200mV

Note :Regarding the /PDWN, please use switching if needed.
Regarding the R/F and RS pin, please select IOVCC level or GND level it depends onuser operation.
Please prepare the 100ohm pair cable or PCB pattern trace that is controlled with 100ohm for
LVDS signal.
Connect each Board GND
COMS/TTL input pin that not in use, it must be tied to GND.

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THC63LVDM87_DesignGuide_Rev.1.20_E

4. Note4.1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.

4.2) GND Connection
Connect the each GND of the Board which THC63LVDM87 and Receiver on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.

4.3) Multi Drop Connection
Multi drop connection is not recommended.

TCLK+
THC63LVDM87

Receiver IC
TCLKReceiver IC

4.4) Asynchronous use
Asynchronous uses such as following systems are not recommended. If it’s not avoidable, please contact tomspsupport@thine.co.jp(for FAE mailing list)

CLKOUT
DATA
IC

TCLK+
THC63LVDM87!

CLKOUTDATA

TCLK-

THC63LVDM87

DATA
IC

DATA
CLKOUT

Receiver IC

IC

DATA

TCLK+
THC63LVDM87

TCLK-!

CLKOUTDATA

Receiver IC

TCLK+
TCLK-

CLKOUT

CLKOUT

THC63LVDM87

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TCLK+

IC

TCLK-

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5. Trace Example for BGA

TOP VIEW
1234567A

TA6TA5TA4TA3TA2TA1TA0A

B

TB4TD3TD2

TD1

TD0

TA-

TA+

B

C

TB5TB0

GND

VCC

RS

TB-

TB+

C

D

TB6TB1

GND

IO
VCC

LVDS
VCC

TC-

TC+

D

E

TC0TB2

GND

PLL
VCC

R/F

TCLK-

TCLK+

E

F

TC1

TB3

TD4TD5TD6TD-

TD+F

GTC2

TC3TC4TC5TC6

CLKIN/PWDN

G1234567R0R1R2R3R4R5R6R7B0B1G0G1G2G3G4G5G6G7TA6TA5TA4TA3TA2TA1TA0TB4TD3TD2TD1TD0TA-TA+

TB5TB0GND

VCC

RS

TB-

TB+

TB6TB1GND

LVDS
IO
VCC
VCC

LVDS
VCC

TC-TC+

TC0

TB2

GND

PLL
VCC

R/F

TCLK-

TCLK+

TC1

TB3TC2TC3

TD4TC4

TD5TC5TD6
TC6

TDCLKIN

TD+/PWDN

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THC63LVDM87_DesignGuide_Rev.1.20_E

6. PCB Design Guide LineGeneral GuidelineUse 4 layers PCB (minimum).

Locate by-pass capacitors adjacent close to the device pins to a maximum extent.

Make the loop minimum which is consist of Power line and GND line.

Use large GND plane.

Separate VDD power supply for each block via ferrite bead.

LVDS Trace
Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector and cable) should bewell balanced. (Keep all these differential impedance and the length of media as same as possible)

Minimize the distance between traces of a pair (S1) to maximize common mode rejection. See followingfigure.

Place adjacent LVDS trace pair at least twice (>2 x S1) as far away as possible.

Avoid 90 degree bends and sharp angles.

Minimize the number of VIA on LVDS traces.

Match impedance of PCB trace, connector, cable and termination to minimize reflections (emissions) for
cabled applications (typically 100ohm differential mode characteristic impedance).

Place terminal resistor close to the Receiver pins to a maximum extent.

To place common mode choke coil is desired for EMI reduction.

S1> 2 x S1

GND+Signal

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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may notalways apply to the customer’s design. THine Electronics, Inc. (“THine”) is not responsible
for possible errors and omissions in this material. Please note even if errors or omissions
should be found in this material, THine may not be able to correct them immediately.
3. This material contains THine’s copyright, know-how or other intellectual property rights.

Copying, reverse-engineer or disclosing to third parties the contents of this material without
THine’s prior written permission is prohibited.
4. THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION

WITH ANY DISPUTE RELATING TO INTELLECTUAL PROPERTY RIGHTSBETWEEN THE USER AND ANY THIRD PARTY, ARISING OUT OF THIS PRODUCT,EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELYTO THINE. NOTE, HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINEACCEPTS NO LIABILITY FOR SUCH DAMAGE OR LOSS IF THE DISPUTE IS
CAUSED BY THE USER’S INSTRUCTION.
5. This product is not designed for applications that require extremely high-reliability/safety suchas aerospace device, nuclear power control device, or medical device related to critical care,excluding when this product is specified for automotive use by THine and used it for thatpurpose. THine accepts no liability whatsoever for any damages, claims or losses arising outof the uses set forth above.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will

occur with a certain small probability, which is inevitable to a semi-conductor product.
Therefore, you are encouraged to have sufficiently fail-safe design principles such as
redundant or error preventive design applied to the use of the product so as not to have ourproduct cause any social or public damage.
7. This product may be permanently damaged and suffer from performance degradation or loss of

mechanical functionality if subjected to electrostatic charge exceeding capacity of the ESD(Electrostatic Discharge) protection circuitry. Safety earth ground must be provided toCopyright©2024 THine Electronics, Inc.

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anything in contact with the product, including any operator, floor, tester and soldering iron.
8. Please note that this product is not designed to be radiation-proof.
9. Testing and other quality control techniques are used to this product to the extent THine deems

necessary to support warranty for performance of this product. Except where mandated byapplicable law or deemed necessary by THine based on the user’s request, testing of all
functions and performance of the product is not necessarily performed.
10. This product must be stored according to storage method which is specified in thisspecifications. THine accepts no liability whatsoever for any damage or loss caused to the user
due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under thecategory of strategic goods under the Foreign Exchange and Foreign Trade Act in Japan andthe Export Administration Regulations in the United States of America on export or transit ofthis product. This product is prohibited for the purpose of developing military modernization,
including the development of weapons of mass destruction (WMD), and the purpose ofviolating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute
maximum ratings or malfunction, if pins of the product are shorted by such as foreign
substance. The damages may cause a smoking and ignition. Therefore, you are encouraged toimplement safety measures by adding protection devices, such as fuses. THine accepts noliability whatsoever for any damage or loss caused to the user due to use under a condition
exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitationrights or other intellectual property rights concerned with this product belong to THine orlicensor(s) of THine. No license or right is granted to the user for any intellectual propertyright or other proprietary right now or in the future owned by THine or THine’s licensor. The
user must enter into a license agreement with THine or THine’s licensor to be granted of suchlicense or right.

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https:www.thine.co.jp

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