THC63LVD1027_Rev.5.01_E

THC63LVD1027
Dual Link LVDS Repeater

General Description
The THC63LVD1027 LVDS(Low Voltage Differential
Signaling) repeater is designed to support pixel datatransmission between Host and Flat Panel Display up to
WUXGA resolution.
THC63LVD1027 receives the dual link LVDS data streams
and transmits the LVDS data through various line rate
conversion modes, Dual Link Input / Dual Link Output,
Single Link Input / Dual Link Output, and Dual Link Input /Single Link Output.

Features• 30bits/pixel dual link LVDS Receiver• 30bits/pixel dual Link LVDS Transmitter• Operating Temperature Range : -40ºC~85ºC• Wide LVDS input skew margin: ± 480ps at 75MHz• Accurate LVDS output timing: ± 250ps at 75MHz• Reduced swing LVDS output mode supported tosuppress the system EMI• Various line rate conversion modes supported
Dual link input / Dual link output [clkout=1x clkin]
Single link input / Dual link output [clkout=1/2x clkin]
Dual link input / Single link output [clkout=2x clkin]• Distribution (signal duplication) mode supported• Power down mode supported• 3.3V single voltage power supply• No external components required for PLLs
• 64pin TSSOP with Exposed PAD (0.5mm lead pitch)

Block Diagram

Figure 1. Block Diagram

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Pin Diagram

Figure 2. Pin Diagram

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Pin Description
Pin Name
RA1+/RB1+/RC1+/RD1+/RE1+/RCLK1+/RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/TA1+/TB1+/TC1+/TD1+/TE1+/TCLK1+/TA2+/TB2+/TC2+/TD2+/TE2+/TCLK2+/PD

Direction

Input

Table 1. Pin Description
Type
Description
LVDS data input for channel A of 1st Link
LVDS data input for channel B of 1st Link
LVDS data input for channel C of 1st Link
LVDS data input for channel D of 1st Link
LVDS data input for channel E of 1st Link
LVDS clock input for 1st Link
LVDS data input for channel A of 2nd Link
LVDS data input for channel B of 2nd Link
LVDS data input for channel C of 2nd Link
LVDS data input for channel D of 2nd Link
LVDS data input for channel E of 2nd Link
LVDS clock input for 2nd Link
In Distribution and Single-in/Dual-out mode,RCLK2+/- must be Hi-Z.
LVDS(See “Mode selection” below in this page.)
LVDS data output for channel A of 1st Link
LVDS data output for channel B of 1st Link
LVDS data output for channel C of 1st Link
LVDS data output for channel D of 1st Link
LVDS data output for channel E of 1st Link
LVDS clock output for 1st Link
LVDS data output for channel A of 2nd Link
LVDS data output for channel B of 2nd Link
LVDS data output for channel C of 2nd Link
LVDS data output for channel D of 2nd Link
LVDS data output for channel E of 2nd Link
LVDS clock output for 2nd Link
Power Down

Output

H: Normal operation
L: Power down state, all LVDS output signals turn to Hi-Z

RS

LVDS output swing level selection
H: Normal swing
L: Reduced swing

MODE1
MODE0

Input

LV-TTL

VDD
GND
CAP

Power

-

Mode selection
MODE1
MODE0
RCLK2+/Description
L
L
Clkin
Dual-in/Dual-out mode
L
L
Hi-Z
Distribution mode
H
L
Hi-Z
Single-in/Dual-out mode
L
H
Clkin
Dual-in/Single-out mode
H
H
Reserved
In Distribution and Single-in/Dual-out mode, RCLK2+/- must be Hi-Z.

3.3V power supply pins
Ground pins (Exposed PAD is also Ground)
Decoupling capacitor pins
These pins should be connected to external decoupling capacitors(Ccap).
Recommended Ccap is 0.1F.

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Mode Setting
Table 2. Mode Setting
Input/Output

Dual-In/Dual-Out

RCLK2+/-

MODE1

MODE0

(Input mode)(Output mode)

H: Single

H: Single

L: Dual

L: Dual

CLK in

L

L

Hi-Z

L

L

Hi-Z

H

L

CLK in

L

H

-

H

H

(Fig.3-1,14-1)
Distribution(Fig.3-2,14-2)
Single-In/Dual-Out(Fig.3-3,14-3)
Dual-In/Single-Out(Fig.3-4,14-4)
Reserved

Signal Flow for Each Setting

Figure 3-1

Figure 3-2

Figure 3-3

Figure 3-4

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Output Control / Fail Safe
THC63LVD1027 has a function to control output depending on LVDS input condition.
Table 3. Output Control
RCLK2+/Output*
All Hi-Z*
All Hi-Z
CLK inRefer to p.4 Mode Setting #Hi-ZRefer to p.4 Mode Setting #PD
RCLK1+/L*
H
Hi-ZH
CLK inH
CLK in*: Don’t care#: If a particular input data pair is Hi-Z, the corresponding output data become L according to LVDS DC spec.
For fail-safe purpose, all LVDS input pins are connected to VDD via resistance for detecting Hi-Z state.

Figure 4. Fail Safe Circuit

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Absolute Maximum Ratings
Table 4. Absolute Maximum Rating
Parameter
Min
Max
Power Supply Voltage
-0.3
+4.0
LVCMOS Input Voltage-0.3
VDD+0.3
LVDS Input Voltage-0.3
VDD+0.3
125
Junction Temperature-55
125
Storage Temperature
260 / 10sec
Reflow Peak Temperature / Time
2.5
Maximum Power Dissipation @+25C

Unit
V
V
V
C
C
C
W

Operating Conditions
Symbol
Ta
VDD

Fclk

Table 5. Operating Condition
ParameterMin
TypOperating Ambient Temperature-40
25Power Supply Voltage
3.0
3.3
Input
20
Dual-In/Dual-Out
Output20
Input
20
Distribution
Output20
Input
40
Single-In/Dual-Out
Output20
Input
20
Dual-In/Single-Out
Output40-

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Max
+85
3.6
85
85
85
85
135
67.5
42.5
85

Unit
C
V
MHz
MHz
MHz
MHz

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Power Consumption
Table 6. Power Consumption
SymbolParameter

Dual-In/Dual-Out

Conditions

Min

Typ.

Max

CLKIN=40MHz

-

-

265
305
325
340
215
235
245
260
175
190
200
210
230
250
215
235
245
260
8

CLKIN=65MHz
CLKIN=75MHz
CLKIN=85MHz
CLKIN=40MHz
CLKIN=65MHz

Distribution

ICCW

CLKIN=75MHz

Operating Current

CLKIN=85MHz(Worst Case Pattern)

CLKIN=40MHz
CLKIN=65MHz

Fig 5.
Single-In/Dual-Out

RL_Tx=100
CL=5pF
RS=VDD

CLKIN=75MHz
CLKIN=85MHz

Fig 6.

CLKIN=112MHz
CLKIN=135MHz
CLKIN=20MHz

Dual-In/Single-Out

CLKIN=32.5MHz
CLKIN=37.5MHz
CLKIN=42.5MHz

ICCS

Power Down Current

-

-

-

Unit

mA

mA

mA

mA

mA

Figure 5. Test Pattern (LVDS Output Full Toggle Pattern)

Figure 6. LVDS Output Load

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Electrical Characteristics
DC Specifications
Table 7. DC Specifications
SymbolParameter

Conditions

Min

Typ

Max

Unit

-

1.8

-

V

VCAP

Capacitor pin appearance voltage

VIL

LV-TTL Input Low Voltage

-

GND

-

0.8

V

VIH

LV-TTL Input High Voltage

-

2.0

-

VDD

V

IIN_TTL

LV-TTL Input Leakage Current

-

-4

-

+4

A

Unit

CCAP=0.1F

LVDS Receiver DC Specifications
Table 8. LVDS Receiver DC Specifications
SymbolParameter

Conditions

Min

Typ

Max

VIN_RX

LVDS-Rx Input Voltage Range

-

0.3

-

2.1

VIC_RX

LVDS-Rx Common Voltage

-

0.6

1.2

1.8

VTH_RX

LVDS-Rx Differential High Threshold

-

-

+100

-100

-

-

100

-

600

PD=VDD

-0.3

-

+0.3

mA

PD=GND
Vin=GND or VDD

-10

-

+10

A

V

VIC_RX = 1.2V
VTL_RX

LVDS-Rx Differential Low Threshold|VID_RX|LVDS-Rx Differential Input Voltage

IIN_RX-

LVDS-Rx Input Leakage Current

mV

LVDS Transmitter DC Specifications
Table 9. LVDS Transmitter DC Specifications
SymbolParameter

Conditions

Min

Typ

Max

Unit

VOC_TX

LVDS-Tx Common Voltage

-

1.125

1.25

1.375

V

VOC_TX

Change in VOC between
complementary output states

-

-

-

35

mV

Normal Swing

250

350

450

Reduced Swing

100

200

300

-

-

-

35

mV

|VOD_TX|

LVDS-Tx Differential
Output Threshold

RL_TX =mV100

VOD_TX

Change in VOD between
complementary output states

IOS_TX

LVDS-Tx Output Short Current

VDD=3.3V

Vout=GND

-24

-

-

mA

IOZ_TX

LVDS-Tx Output Tri-state Current

PD=GND

Vout=GND to VDD

-10

-

+10

A

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AC Specifications
Table 10. AC Specifications
SymbolParameter

tLT

Phase Lock Loop Set Time
(Fig 7.)

tDL

Min

Typ

Max

Unit
ms

-

-

-

-

10

Dual-In/Dual-Out

CLKIN=75MHz

9tRCP+3

9tRCP+5

9tRCP+7

Distribution

CLKIN=75MHz

9tRCP+3

9tRCP+5

9tRCP+7

Single-In/Dual-Out

CLKIN=75MHz(11+2/7)tRCP+3(11+2/7)tRCP+5(11+2/7)tRCP+7

Dual-In/Single-Out

CLKIN=37.5MHz(8+5/14)tRCP+3(8+5/14)tRCP+5(8+5/14)tRCP+7

-

2tRCP

-

-

-

2tRCP

-

-

4tRCP

Must be 2n tRCP
(n=integer)-ns

Data Latency (Fig 8.)tDEH

DE Input High Time (Fig 9.)tDEL

DE Input Low Time (Fig 9.)tDEINT

Conditions

Single-In/Dual-Out-

DE Input Period (Fig 9.)

AC Timing Diagrams

Figure 7. Phase Lock Loop Set Time

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AC Timing Diagrams (Continued)

Figure 8. DATA Latency

Figure 9. Single Link Input / Dual Link Output Mode RC1(DE) Input Timing

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LVDS Receiver AC Specifications
Table 11. LVDS Receiver AC Specifications
SymbolParameter

Conditions

Min

Typ

Max

tRCP

LVDS Clock Period

-

7.4

-

50

tRCH

LVDS Clock High Duration-

2/7tRCP

4/7tRCP

5/7tRCPtRCL

LVDS Clock Low Duration-

2/7tRCP

3/7tRCP

5/7tRCP

CLKIN=75MHz(1)

480

-

-

CLKIN=112MHz(1)

250

-

-

CLKIN=135MHz(1)

220

-

-

CLKIN=75MHz(1)

480

-

-

CLKIN=112MHz(1)

250

-

-

CLKIN=135MHz(1)

220

-

-

tRSUP

tRHLD

LVDS Data Input Setup Margin

LVDS Data Input Hold MargintRIP6

LVDS Data Input Position 6-

2/7tRCP-tRHLD

2/7tRCP

2/7tRCP+tRSUPtRIP5

LVDS Data Input Position 5-

3/7tRCP-tRHLD

3/7tRCP

3/7tRCP+tRSUPtRIP4

LVDS Data Input Position 4-

4/7tRCP-tRHLD

4/7tRCP

4/7tRCP+tRSUPtRIP3

LVDS Data Input Position 3-

5/7tRCP-tRHLD

5/7tRCP

5/7tRCP+tRSUPtRIP2

LVDS Data Input Position 2-

6/7tRCP-tRHLD

6/7tRCP

6/7tRCP+tRSUPtRIP1

LVDS Data Input Position 1-

7/7tRCP-tRHLD

7/7tRCP

7/7tRCP+tRSUPtRIP0

LVDS Data Input Position 0-

8/7tRCP-tRHLD

8/7tRCP

8/7tRCP+tRSUP--0.3 tRCP-+0.3 tRCP

Skew Time Between
RCLK1 and RCLK2(1) VIC_RX=1.2V, tRCH=4/7 tRCP

tCK12

Unit

ns

ps

ps

ps

ps

`

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LVDS Receiver Input Timing

Figure 10. LVDS Receiver Timing

Figure 11. Skew time between RCLK1 and RCLK2

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LVDS Transmitter AC Specifications
Table 12. LVDS Transmitter AC Specifications
SymbolParameter

Conditions

Min

Typ

Max

tTCP

LVDS Clock Period

-

11.76

-

50

tTCH

LVDS Clock High Duration--

4/7tTCP-tTCL

LVDS Clock Low Duration--

3/7tTCP-tTSUP

LVDS Data Output Setup

CLKOUT=75MHz

-

-

250

ps

tTHLD

LVDS Data Output Hold

CLKOUT=75MHz

-

-

250

ps

tTOP6

LVDS Data Output Position 6-

2/7tTCP-tTHLD

2/7tTCP

2/7tTCP+tTSUP

tTOP5

LVDS Data Output Position 5-

3/7tTCP-tTHLD

3/7tTCP

3/7tTCP+tTSUP

tTOP4

LVDS Data Output Position 4-

4/7tTCP-tTHLD

4/7tTCP

4/7tTCP+tTSUP

tTOP3

LVDS Data Output Position 3-

5/7tTCP-tTHLD

5/7tTCP

5/7tTCP+tTSUP

tTOP2

LVDS Data Output Position 2-

6/7tTCP-tTHLD

6/7tTCP

6/7tTCP+tTSUP

tTOP1

LVDS Data Output Position 1-

7/7tTCP-tTHLD

7/7tTCP

7/7tTCP+tTSUP

tTOP0

LVDS Data Output Position 0-

8/7tTCP-tTHLD

8/7tTCP

8/7tTCP+tTSUP

tLVT

LVDS Transition Time (Fig 13.)

Fig.6

-

0.6

1.5

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Unit

ns

ps

ns

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LVDS Transmitter Output Diagram

Figure 12. LVDS Transmitter Timing

Figure 13. LVDS Transition Timing

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LVDS Data MappingDual-In / Dual-Out

Figure 14-1. Data Mapping for Dual-In/Dual-Out

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Distribution Mode
In Distribution mode, RCLK2+/- must be Hi-Z.

Figure 14-2. Data Mapping for Distribution mode

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Single-In / Dual-Out
In Single-in / Dual-out mode, RCLK2+/- must be Hi-Z.

Figure 14-3(a). Data Mapping for Single-In/Dual-Out

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Figure 14-3(b). Data Mapping for Single-In/Dual-Out

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Dual-In / Single-Out

Figure 14-4. Data Mapping for Dual-In/Single-Out

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Notes

1) LVDS input pin connection
When LVDS line is not derived from the previous device, the line is pulled up to 3.3V internally in THC63LVD1027.
This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose operating condition islower voltage power supply than 3.3V. This phenomenon may happen at power on phase of the whole system including
THC63LVD1027. One solution for this problem is PD=L control during no LVDS input period because pull-up resistors
are cut off at power down state.

Figure 15. LVDS input pin connection2) Power On Sequence
Don’t input RCLK1+/- and RCLK2+/- before THC63LVD1027 is on in order to keep absolute maximum ratings.

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3) Cable Connection and Disconnection
Don’t connect and disconnect the LVDS cable, when the power is supplied to the system.

4) GND Connection
Connect the each GND of the PCB which Transmitter, Receiver and THC63LVD1027 on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.

5) Multi Drop Connection
Multi drop connection is not recommended.

Figure 16.Multi Drop Connection6) Asynchronous use
Asynchronous use such as following systems are not recommended.
Page.11 tCK12 spec should be kept.

Figure 17-1. Asynchronous Use1
Asynchronous use such as following systems are not recommended.

Figure 17-2. Asynchronous Use2

7) De-coupling capacitor
THC63LVD1027 requires appropriate de-coupling capacitor placement on VDD.
Especially, VDD pin 36 and pin 61 requires 0.1uF and 4.7nF capacitor parallel placement close to IC pins.

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Package

THC63LVD1027

0.5 BSC
0.17 ~ 0.27

1.20 MAX

Figure 18. Package Diagram

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Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

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