Report Title:

ADSP-21479W-02 Automotive Grade
2 at UT2 Qualification

Report Number:

17607

Revision:A

Date:

27 July 2022

Reliability Report: 17607

SummaryThis report documents the successful completion of the reliability qualification requirements
for the release of the ADSP-21479W-02 automotive grade 2 product in an 88-LFCSP
package at UTAC (UT2). The ADSP-21479W-02 SHARC® processor is a member of theSIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture.
Table 1 describes the ADSP-21479W-02 product characteristics.

Table 1: ADSP-21479W-02 Product Characteristics
Die/FabDie Id

TMAP60 D-T2

Die Size (mm)4.74 x 5.44

Wafer Fabrication Site

E_TSMC1212

Wafer Fabrication Process

65nm CMOS

Approximate Transistor Count

50.0 million

Passivation Layer
Bond Pad Metal Composition
Polyimide

undoped-oxide/SiN
AlCu(0.5%)
Yes

Package/Assembly
Package

88-LFCSP

Body Size (mm)12.00 x 12.00 x 0.85

Assembly Location

UTAC (UT2)

Molding Compound

Sumitomo G700LTD

Die Attach

Ablestik 8600 conductive

Wire Type

4N Gold

Wire Diameter (mil)

1.00

Lead Frame MaterialCopper

Lead FinishNA

Moisture Sensitivity Level3Maximum Peak Reflow Temperature (°C)

260

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Reliability Report: 17607

Description / Results of Tests Performed
Table 2 provides a description of the qualification tests conducted and the associated test
results for products manufactured on the same technologies as described in Table 1. All
devices were electrically tested before and after each stress. Any device that did not meet allelectrical data sheet limits following stressing would be considered a valid (stressattributable) failure unless there was conclusive evidence to indicate otherwise.

Table 2: LFCSP at UTAC (UT2) Package Qualification Test Results
Test Name

Specification

Conditions
130C 85%RH
33.3 psia,
Biased, 192
Hours

JESD22A110

LT8355-1
LT8277
LT8390
LT8391D

MAX20081ATNK/V+
130C 85%RH
33.3 psia,
Biased, 96
Hours

MAX20069BGTLA/VY+

MAX20028ATJA/VY+

MAX20430ATIA/VY+
High
Temperature
Storage Life(HTSL)2
Solder Heat
Resistance(SHR) 1,3

Solderability

Temperature
Cycling (TC)
1,4,5

Unbiased
HAST(UHST) 1,3

Qty.
Failures00000000000000000000

Lot #MAX25500ATMA/V+
HighlyAccelerated
Temperatureand Humidity
Stress Test
(HAST)1,2

Q19285.1ABHAST
Q19306.1BHAST
Q19306.2HASTQ19204.2BHAST
Q19204.3BHAST
R41514A
R41514B
R41514C
R41199A
R41199B
R41199C
JCFZ1A012BQ
JCFZ1A012BA
JCFZ1A012B
JCTJ1Q002RC
JCTJ1Q002RD
JCTJ1Q002RE
JCDD33003D
JCDD33003G
JCDD33003E

Sample
Size
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77

Device

JESD22A103

150°C, 1,000
Hours

ADSP-21479W-02

Q17607.1.HS177

0J-STD-020

MSL-3

ADSP-21479W-02

Q17607.1.SH1
Q17607.2.SH2
Q17607.3.SH3111111000

ADSP-21479W-02

Q17607.1.ST1150

Q17607.1.TC1
Q17607.2.TC2
Q17607.3.TC3
Q17607.1.UH1
Q17607.2.UH2
Q17607.3.UH37777777777
77000000JESD22B102

JESD22A104
JESD22A118

SolderingTemp of245°C, Single
Duration
55°C/+125°C,
1,000 Cycles
130C 85%RH
33.3 psia, 96
Hours

ADSP-21479W-02

ADSP-21479W-02

Page 3 of 6

Reliability Report: 17607
1 These samples were subjected to preconditioning (per J-STD-020 Level 3) prior to the start of the stress test. Level 3

preconditioning consists of the following: Bake: 24 hrs @ 125°C, Unbiased Soak: 192 hrs @ 30°C, 60%RH, Reflow:
3 passes through an oven with a peak temperature of 260°C.
2 Electrical test was performed at room and hot temperatures.
3 Electrical test was performed at room temperature.
4 Electrical test was performed at hot temperature.
5 Post-TCT wire bond pull testing was performed per AEC-Q100 on five units each from TCT lots Q17607.1.TC1,Q17607.2.TC2 and Q17607.3.TC3. Minimum bond pull results were 8.270 grams, 8.843 grams and 9.190 grams
respectively. Complete data for the five units each lot are presented in Appendix A of this report.

Samples of the many devices manufactured with these package and process technologies arecontinuously undergoing reliability evaluation as part of the ADI Reliability Monitor
Program. Additional qualification data is available on Analog Devices' web site.

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Reliability Report: 17607

ESD Test Results
The results of Field-Induced Charged Device Model (FICDM) ESD testing is summarized inTable 3. ADI measures ESD results using stringent test procedures based on thespecifications listed. Any comparison with another supplier's results should ensure that thesame ESD test procedures have been used. For further details, please see the EOS/ESD
chapter of the ADI Reliability Handbook (available via the 'Quality and Reliability' link onAnalog Devices' web site).

Table 3: ADSP-21479W-02 ESD Test Results
ESD ModelPackage

ESD Test Spec

FICDM

88-LFCSP

JS-002RC Network

HighestPass Level

First FailLevel

Class1Ω, Cpkg

±1250VNAC3

Approvals
Reliability Engineer: Jordan Placido

Additional Information
Data sheets and other additional information are available on Analog Devices' web site

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Reliability Report: 17607

Appendix A: Post-TCT Wire Pull Test Results

UnitBall12345678910111213MINMAX
AVE
STDEV

Q17607.1.TC1
Q17607.2.TC2
Q17607.3.TC3
Force (gf) Mode Force (gf) Mode Force (gf) Mode Force (gf) Mode Force (gf) Mode Force (gf) Mode
11.551a-1
11.422a-1
11.224a-1
11.161a-1
11.342a-1
11.016a-1
11.612a-1
11.741a-1
11.699a-1
11.626
a-1
9.804
a-1
11.102a-1
12.076a-1
11.490a-111.577
a-1
11.079
a-1
9.896
a-1
10.599a-1
10.023a-1
11.503a-1
11.232a-1
10.820a-1
11.107a-1
10.693a-1
12.595a-1
11.791a-1
12.214a-1
11.130a-1
10.735a-1
11.398a-1
10.921
a-1
9.833
a-1
10.998a-1
10.159a-1
11.188a-1
10.581a-1
10.062
a-1
8.270
a-1
10.820
a-1
8.843
a-1
9.223
a-1
9.969
a-1
10.741
a-1
9.100
a-1
10.191
a-1
9.972
a-1
10.879
a-1
9.472
a-1
11.285a-1
11.292a-1
10.567a-1
11.101a-1
11.312a-1
11.097
a-1
9.119
a-1
11.244a-1
10.977a-1
11.103a-1
11.630a-1
11.794a-1
11.507a-1
11.362a-1
10.795a-1
11.794a-1
11.924a-1
11.794a-1
11.616a-1
11.490a-1
10.997a-1
12.065a-1
11.976a-1
11.837a-1
11.599a-1
11.633a-1
10.921a-1
11.939
a-1
9.190
a-1
10.239
a-1
9.119
8.270
10.191
8.843
9.190
9.472
12.59511.791
12.21412.06511.976
11.837
11.13110.93611.09310.98410.78510.892
0.943
1.123
0.517
0.892
0.959
0.730

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