THAN0127_Rev.1.40_E

Application Note

THAN0127_Rev.1.40_E

THCV219/THCV220 Application Note
System Diagram and PCB Design Guideline

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Contents
Contents................................................................................................................................................................... 2
Application Diagrams.............................................................................................................................................. 3
RGB24bit per pixel falling edge system with only LOCKN connection ....................................................... 3
32bit (RGB30bit and arbitrary 2bit (ex. kHz)) per pixel falling edge with only one pair ........................... 4
CCIR601/656 8bit, HS, VS camera image per pixel with only one pair, meters distance ........................... 5
CCIR601/656 10bit, HS, VS camera image per pixel with only one pair, meters distance ......................... 6
Recommendations for Power Supply ...................................................................................................................... 7
Recommended Power Supply for THCV219................................................................................................... 7
Recommended Power Supply for THCV220................................................................................................... 7
Note ......................................................................................................................................................................... 8
1)Power On Sequence ....................................................................................................................................... 82)Cable Connection and Disconnection ........................................................................................................... 83)GND Connection ............................................................................................................................................ 84)Multiple device connection ............................................................................................................................ 85)In case of No DE in video signal stream ....................................................................................................... 96)In case of long cable over meters transmission with frequency change in operation............................. 10
PCB Layout Considerations .................................................................................................................................. 11
Notices and Requests.............................................................. エラー! ブックマークが定義されていません。

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Application Diagrams
RGB24bit per pixel falling edge system with only LOCKN connection[V-by-One® HS]
HTPDN connection can be eliminated. Set THCV219 HTPDN Low and leave THCV220 HTPDN Open.
[THCV219]
PDN can be controlled by external resistor or other driving source like MCU.
Design PRE pin and CMLDRV pin in order to adjust setting appropriate to actual PCB/cable transmission line.
Set COL pin High (24bit), LFSEL pin Low (over 20MHz) and RF pin Low (Falling edge TTL/CMOS input).
BET pin can be used as Bit Error Test entry in actual configuration in order for debug or test purpose.
Unused TTL/CMOS input pins should be connected to Low (GND).
[THCV220]
PDN and OE can be controlled by external resistor or other driving source like MCU.
Design TTLDRV pin in order to adjust setting appropriate to actual PCB transmission trace.
Set COL pin High (24bit), LFSEL pin Low (over 20MHz) and RF pin Low (Falling edge TTL/CMOS output).
BET, BETOUT and LATEN pin can be used for Bit Error Test in actual configuration in order for debug or test.
Unused TTL/CMOS output pins should be left Open.
Place 10 resistor close to outputs, which can be eliminated when freq. is low, trace is short, and TTLDRV=L.

VCC
1kΩ TxPDWN

TTL/
CMOS
Driver

THCV219
R9-R2
R1,R0
G9-G2
G1,G0
B9-B2
B1,B0
CONT1,2NC
VCC
NC Pre0Ω

THCV220

HTPDN

HTPDN

VCC

LOCKN

LOCKN

Damping resistor
ex. 10close to TTL/
THCV220 CMOS
*3
Receiver

R9-R2
R1,R0
G9-G2
G1,G0
B9-B2
B1,B0
CONT1,2VCC

NC

NC TTLDrv
0Ω

DE, H/VSYNC

VCC

*1

1kΩ CMLDrv

CLKIN

TXN
TXP

NC

RXN
RXP
0.1uF

VCC
NC TxBETset
0Ω

TxPDWNPDN

Pre
CMLDrv
VCC

PRE
CMLDRV

1kΩ

ASYNDE
1kΩ
COL
LFSEL
RF
CAPOUT

PDN=H (controllable)-> Normal operation
PRE=L (adjustable)-> CML Pre-emp. 0dB
CMLDRV=H (adjustable)-> CML 600mV swing
COL=H-> 24 bit per pixel
LFSEL=L-> Over 20MHz freq.
RF=L-> Falling edge TTL in
BET=L (control)-> Normal operation

*1
*2
*3

BET

NC

PDN

RxPDWNTTLDRVOE

TTLDrv
OutEnable

VCC
1kΩ
COL
2.2uF

CAPOUT
0.1uF

TxBETset

1kΩ OutEnable

CLKOUT

0.1uF

2.2uF

LFSEL
RF

0.1uF

CAPINA

CAPINA
0.1uF

CAPINPBET
BETOUT
LATEN
TEST1
TEST2

TEST1
TEST2

*2

GND

GND

1kΩ RxPDWN

VCC

10k

DE, H/VSYNC

VCC

VCC
NC RxBETset
0Ω
VCC
NC BETlatch0Ω

RxBETset
TP PDN=H (controllable)
BETlatch-> Normal operation
TTLDRV=L (adjustable)-> Weak TTL drive
OE=H (controllable)-> Output enable
COL=H-> 24 bit per pixel
LFSEL=L-> Over 20MHz freq.
RF=L-> Falling edge TTL out
BET/LATEN=L (control)-> Normal operation

indicates microstrip lines or cables with their differential characteristic impedance being 100Connect GNDs of both Tx and Rx PCB
TTL output dampling resistor can be totally eliminated if freq. is low, trace is short and TTLDRV=L

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32bit (RGB30bit and arbitrary 2bit (ex. kHz)) per pixel falling edge with only one pair
[V-by-One® HS]
HTPDN connection can be eliminated. Set THCV219 HTPDN Low and leave THCV220 HTPDN Open.
LOCKN connection can be shared with V-by-One® HS trace. Put 1k resistors on both side.
[THCV219]
PDN can be controlled by external resistor or other driving source like MCU.
Design PRE pin and CMLDRV pin in order to adjust setting appropriate to actual PCB/cable transmission line.
Set COL pin Low (32bit), LFSEL pin Low (over 20MHz) and RF pin Low (Falling edge TTL/CMOS input).
BET pin can be used as Bit Error Test entry in actual configuration in order for debug or test purpose.
Arbitrary slow pulse should be assigned to CTL bits (ex. CONT1,2) for continuous transfer independent of DE[THCV220]
PDN and OE can be controlled by external resistor or other driving source like MCU.
Design TTLDRV pin in order to adjust setting appropriate to actual PCB transmission trace.
Set COL pin Low (32bit), LFSEL pin Low (over 20MHz) and RF pin Low (Falling edge TTL/CMOS output).
BET, BETOUT and LATEN pin can be used for Bit Error Test in actual configuration in order for debug or test.
Place 10 resistor close to outputs, which can be eliminated when freq. is low, trace is short, and TTLDRV=L.
TTL/
CMOS
Driver

VCC
1kΩ TxPDWN

THCV219
R9-R0

NC

0Ω

HTPDN

HTPDN

G9-G0

VCC
NC Pre

THCV220

CONT1,2

LOCKN
30k
1k

CONT1,2

Arbitrarysignalex. kHz

CLKIN

TXN
TXP

NC

RXN
RXP
0.1uF

TxPDWNVCC
NC TxBETset
0Ω

Pre
PRE
CMLDrvCMLDRVVCC
ASYNDE
1kΩ

COL
LFSEL
RF

CAPOUT

BET

CAPINA

2.2uF

2.2uF

CAPOUT
0.1uF

TxBETset
PDN=H (controllable)-> Normal operation
PRE=L (adjustable)-> CML Pre-emp. 0dB
CMLDRV=H (adjustable)-> CML 600mV swing
COL=L-> 32 bit per pixel
LFSEL=L-> Over 20MHz freq.
RF=L-> Falling edge TTL in
BET=L (control)-> Normal operation

*1
*2
*3

NC

PDN

RxPDWNTTLDRVOE

TTLDrv
OutEnable

COL
LFSEL
RF

0.1uF

CAPINA
0.1uF

CAPINPBET
BETOUT
LATEN
TEST1
TEST2

TEST1
TEST2

*2

GND

GND

0Ω

1kΩ OutEnable

CLKOUT

0.1uF

PDN

NC TTLDrv

VCC*11kΩ CMLDrv

1kΩ RxPDWN
NC

DE, H/VSYNC

1k

VCC

VCC

B9-B0

LOCKN

DE, H/VSYNC

VCC

R9-R0
G9-G0

VCC

B9-B0
Arbitrarysignalex. kHz

Damping resistor
ex. 10close to TTL/
THCV220 CMOS
*3
Receiver

VCC
NC RxBETset
0Ω
VCC
NC BETlatch0Ω

RxBETset
TP PDN=H (controllable)
BETlatch-> Normal operation
TTLDRV=L (adjustable)-> Weak TTL drive
OE=H (controllable)-> Output enable
COL=L-> 32 bit per pixel
LFSEL=L-> Over 20MHz freq.
RF=L-> Falling edge TTL out
BET/LATEN=L (control)-> Normal operation

indicates microstrip lines or cables with their differential characteristic impedance being 100Connect GNDs of both Tx and Rx PCB
TTL output dampling resistor can be totally eliminated if freq. is low and trace is short and TTLDRV=L

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CCIR601/656 8bit, HS, VS camera image per pixel with only one pair, meters distance[V-by-One® HS]
HTPDN connection can be eliminated. Set THCV219 HTPDN Low and leave THCV220 HTPDN Open.
LOCKN connection can be shared with V-by-One® HS trace. Put 1k resistors on both side.
[THCV219]
PDN can be controlled by external resistor or other driving source like MCU.
Set PRE pin and CMLDRV pin High for long distance operation.
Set COL pin High (24bit), LFSEL pin Low (over 20MHz) and RF pin properly (Falling or Rising edge).
BET pin can be used as Bit Error Test entry in actual configuration in order for debug or test purpose.
Camera HSYNC should be connected to THCV219 DE and polarity must be cared by ASYNDE setting.
[THCV220]
PDN and OE can be controlled by external resistor or other driving source like MCU.
Set COL pin High (24bit), LFSEL pin Low (over 20MHz) and RF pin properly (Falling or Rising edge).
BET, BETOUT and LATEN pin can be used for Bit Error Test in actual configuration in order for debug or test.
Place 10 resistor close to outputs, which can be eliminated when freq. is low, trace is short, and TTLDRV=L.
Processor HSYNC should be connected to THCV220 DE and polarity must be cared by external inverter.
CCIR601
/656
VCC
CMOS
1kΩ TxPDWN Sensor

THCV219

VCC*4

D[7:0]

1kΩ HSYNCInv
NC

VCC

*4

HS

THCV220

R9-R0
HTPDN
G9-G0
B1,B0,CONT1,2
HSYNC
VCC
B9-B2

NC

VS

DE

HTPDN

R9-R0
G9-G0
B1,B0,CONT1,2
HSYNC
B9-B2

LOCKN

LOCKN
30k
1k

VSYNC

Damping resistor
ex. 10close to CMOSTHCV220 input*3
Processor

DE
VSYNC

1k

CLKIN

TXN
TXP

0Ω

RXN
RXP
0.1uF

D[7:0]
mount/NC*4
NC/mount*4VS

NC TxRFCMLDRVASYNDE*40Ω

HSYNCInv*4
VCC
COL
1kΩ
TxRF

CAPOUT

TxBETset

BET

CAPINA

2.2uF

2.2uF

CAPOUT
0.1uF

*1
*2
*3
*4

RxPDWNTTLDRVOE

TTLDrv
OutEnable

LFSEL
RF

0.1uF

CAPINA
0.1uF

CAPINPBET
BETOUT
LATEN
TEST1
TEST2

TEST1
TEST2

*2

GND

GND

0Ω
VCC
1kΩ OutEnable
NC

PDN

VCC
1kΩ
COL

LFSEL
RF

PDN=H (controllable)-> Normal operation
PRE=H / CMLDRV=H-> CML 600mV / Pre4dB
ASYNDE=H (adjustable)-> HS (DE) not inverted
COL=H-> 24 bit per pixel
LFSEL=L-> Over 20MHz freq.
RF=L (adjustable)-> Falling edge TTL in
BET=L (controllable)-> Normal operation

PCLK

CLKOUT

VCC
NC TTLDrv

HS

0.1uF

TxPDWN
PDN
VCC
1kΩ 1kΩ PRE

VCC

1kΩ RxPDWN
NC*1

NC TxBETsetPCLK

VCC

VCC
NC RxRF0Ω
VCC
NC RxBET*

RxRF

0Ω

RxBETset
TP PDN=H (controllable)
RxBETlatch -> Normal operation
TTLDRV=L (adjustable)-> Weak TTL drive
OE=H (controllable)-> Output enable
COL=H-> 24 bit per pixel
LFSEL=L-> Over 20MHz freq.
RF=L (adjustable)-> Falling edge TTL out
BET/LATEN=L (control)-> Normal operation

indicates microstrip lines or cables with their differential characteristic impedance being 100Connect GNDs of both Tx and Rx PCB
TTL output dampling resistor can be totally eliminated if freq. is low and trace is short and TTLDRV=L
System HSYNC signal should be matched to Vx1HS DE requirement. Active image should be during DE=H.

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CCIR601/656 10bit, HS, VS camera image per pixel with only one pair, meters distance
10 bit least significant two bits are allocated to R19-R18 (default) and B11-B10 (CTL packet in 10 bit mode).
8 bit mode is recommended for long distance transmission; however, sometimes CTL in 10 bit mode are needed.
[V-by-One® HS]
HTPDN connection can be eliminated. Set THCV219 HTPDN Low and leave THCV220 HTPDN Open.
LOCKN connection can be shared with V-by-One® HS trace. Put 1k resistors on both side.
[THCV219]
PDN can be controlled by external resistor or other driving source like MCU.
Set PRE pin and CMLDRV pin High for long distance operation.
Set COL pin High (24bit), LFSEL pin Low (over 20MHz) and RF pin properly (Falling or Rising edge).
BET pin can be used as Bit Error Test entry in actual configuration in order for debug or test purpose.
Camera HSYNC should be connected to THCV219 DE and polarity must be cared by ASYNDE setting.
[THCV220]
PDN and OE can be controlled by external resistor or other driving source like MCU.
Set COL pin High (24bit), LFSEL pin Low (over 20MHz) and RF pin properly (Falling or Rising edge).
BET, BETOUT and LATEN pin can be used for Bit Error Test in actual configuration in order for debug or test.
Place 10 resistor close to outputs, which can be eliminated when freq. is low, trace is short, and TTLDRV=L.
Processor HSYNC should be connected to THCV220 DE and polarity must be cared by external inverter.
CCIR601/656
CMOS
1kΩ TxPDWN Sensor

VCC

NC

D[9:2]
D[1:0]VCC*4

1kΩ HSYNCInv

HS

NC
VCC
1kΩ TxCOL

THCV219
R7-R0
G9-G0
CONT1,2HSYNC
B9-B2mount/NC
R9-R8
B1-B0
NC/mount
DE
*4

VS

VSYNC

PCLK

CLKIN

THCV220

HTPDN

HTPDN

VCC

LOCKN

LOCKN
30k
1k

*3 Processor VCC
R7-R0
1kΩ RxPDWN
G9-G0
CONT1,2NC
HSYNC
B9-B2 mount/NC
D[9:2]
VCC
R9-R8
D[1:0]
NC/mount
NC TTLDrv
B1-B0
mount/NC*4
HS
DE
0Ω

VSYNC

1k

Damping resistor
ex. 10close to CMOSTHCV220 input

NC/mount*4

VS

*1
TXN
TXP

NC

RXN
RXP
0.1uF

NC TxRF0Ω

HSYNCInv*4
TxCOL

TxRF

CMLDRVASYNDE*4
COL
LFSEL
RF

CAPOUT

BET

CAPINA

2.2uF

2.2uF

CAPOUT
0.1uF

TxBETset (=L default)
PDN=H (controllable)-> Normal operation
PRE=H / CMLDRV=H-> CML 600mV / Pre4dB
ASYNDE=H (adjustable)-> HS (DE) not inverted
COL=H (selectable)-> 24 bit per pixel
LFSEL=L-> Over 20MHz freq.
RF=L (adjustable)-> Falling edge TTL in
BET=L (controllable)-> Normal operation

*1
*2
*3
*4

PDN

RxPDWNTTLDRVOE

TTLDrv
OutEnable

COL

RxCOL

LFSEL
RF

RxRF

0.1uF

CAPINA
0.1uF

CAPINPBET
BETOUT
LATEN
TEST1
TEST2

TEST1
TEST2

*2

GND

GND

1kΩ OutEnable
NC

0.1uF

TxPDWN
PDN
VCC
1kΩ 1kΩ PRE

VCC

PCLK

CLKOUT

VCC

VCC
NC RxRF0Ω
VCC
1kΩ RxCOL
NC

RxBETset (=L default)
TP PDN=H (controllable)
RxBETlatch -> Normal operation
TTLDRV=L (adjustable)-> Weak TTL drive
OE=H (controllable)-> Output enable
COL=H (selectable)-> 24 bit per pixel
LFSEL=L-> Over 20MHz freq.
RF=L (adjustable)-> Falling edge TTL out
BET/LATEN=L (control)-> Normal operation

indicates microstrip lines or cables with their differential characteristic impedance being 100Connect GNDs of both Tx and Rx PCB
TTL output dampling resistor can be totally eliminated if freq. is low and trace is short and TTLDRV=L
System HSYNC signal should be matched to Vx1HS DE requirement. Active image should be during DE=H.

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Recommendations for Power Supply

Separate all the power domains in order to avoid unwanted noise coupling between noisy digital andsensitive analog domains.
Use high frequency ceramic capacitors of 0.1uF as bypass capacitors between power and ground pins.
Place them as close to each power pin as possible. All supply pins need capacitor placement one by one.
Use the same ground plane for all ground pins including EXPGND.

Recommended Power Supply for THCV219

3.3V
-2.5V

VCC

VCC
x6
GND

10uF

0.1uF

AVCC
10uF

EXPGNDGND

THCV219

AVCC
GND

0.1uF

Recommended Power Supply for THCV220

3.3V
-2.5V

VCC

VCC
x6
GND

10uF

0.1uF

AVCC
10uF

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EXPGND
GND

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THCV220

AVCC
GND

0.1uF

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Note1)Power On Sequence
Don’t input clock nor data before THCV219 is on in order to keep absolute maximum ratings.
2)Cable Connection and Disconnection
Don’t connect and disconnect the TLL and CML cable/connector, when the power is supplied to the system.
3)GND Connection
Connect the each GND of the PCB where THCV219 and THCV220 are on it. It is better for EMI reduction toplace GND cable as close to TTL and CML cable as possible.
4)Multiple device connection
HTPDN and LOCKN signals are supposed to be connected proper for their purpose like the following figure.
HTPDN should be from just one Rx to multiple Tx because its purpose is only ignition of all Tx.
LOCKN should be connected so as to indicate that all Rx CDR become ready to receive normal operation data.
LOCKN of Tx side can be simply split to multiple Tx.
There could be other applicable circuit like ‘OR gate of LOCKN’, ‘npn transistor with resistors as inverter’, etc.
Also possible time difference of internal processing time (THCV219 Data sheet p.10 tTCD and THCV220 Data
sheet p.11 tRDC) on multiple data stream must be accommodated and compensated by the following destination
device connected to multiple THCV220, which may have internal FIFO.
THCV219

THCV220

HTPDN

HTPDN

LOCKN

LOCKN

clkin.1

clkout.1
FIFO

PDN
SourceDeviceEx. synchronizedTime diff. comes up

THCV219

THCV220

HTPDN

HTPDN

LOCKN

LOCKN

Destination
Device

FIFO
clkin.2

clkout.2

PDN

Internal processing time tTCD

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Internal processing time tRDC

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5)In case of No DE in video signal stream
V-by-One® HS transmission always requires DE, while some system has only HSync and VSync.
Sometimes Hsync should be connected to DE and other treatment is at the same time required.
DE polarity on active data transmission period must be High, which sometimes needs external inverter.
DATAIN

HTPDN
LOCKN

HTPDN
LOCKN

CLKIN
THCV219
HSYNC

Hsync from camera
Vsync from camera

VSYNC*mounted/NC

FLD from camera

DATAOUT

CLKOUT
THCV220
RXN
HSYNC
RXP
VSYNC

TXN
TXP

DE
*System HSYNC must be treated properly
in order to match Vx1HS DE requirement

Inversion is applied by ASYNDE

Vsync for use*mounted/NC

ASYNDEDE

Hsync for use

Camera Module
Active Data bits

CameraImage

FLD for use*NC/mounted

CameraImage

Camera Module
Horizontal Indicator

H signal inverted
and to Vx1HS Tx DE(Vx1HS requirement)Time*V-by-One® HS DE polarity must be High during video
image is transmitted. (One of the requirements)

Below are consideration points if there is no DE signal on original data format.

DE Requirement
Data bits
input to Vx1HS Tx

Normal data bits Requirement

Targetdata

Normal Data bits
input to Vx1HS Tx

DEinput to Vx1HS Tx

Transmitted
dataDE
input to Vx1HS Tx
At least 2 pix clock
Normal Data bits is transmitted when DE=High.
Time

Control bits (Hsync, Vsync) Requirement
Control bits
input to Vx1HS Tx

Control bits
transition banned

CTL data bits Requirement
CTL Data bits
input to Vx1HS Tx

Transmitted
dataDE
input to Vx1HS Tx

DEinput to Vx1HS Tx

Control bits are named as Hsync and Vsync input to V-by-One® HS Tx.
Control bits transition is allowed when DE=H=>L edge and during DE=L.
Control bits transition is allowed when DE=L=>H edge and during DE=H.

CTL Data bits is transmitted except DE=Low first and last pixel.
CTL of DE=L first and last pixel is fixed low at THCV218 and THCV234.
CTL of DE=L first and last pixel keeps preceding pix. value at THCV220.

If this kind of configuration is required, please contact tomspsupport@thine.co.jp

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6)In case of long cable over meters transmission with frequency change in operation
Frequency change during operation with long cable may be problematical because long cable has its huge
capacitance to slow down LOCKN rise waveform.
LOCKN node must be over VIH at least more than 10ms* for ideal operation.
Behavior against frequency change
Short lengthLong cable

THCV219

THCV220

THCV219

Ideal operation

THCV220

Abnormal operation
There is no training signal because
cable capacitance cause slow rize of LOCKN.

pix.
clk

40MHz

Ser
Des

40MHz
Video
signal

LOCKN
voltage

78MHz

78MHz
Training
signal78MHzVideo
signal(LOCKN=H)

40MHz

78MHz

40MHz
Video
signal78MHzVideo
signal

VIH
THCV219 High LOCKN
recognition
voltagethreshold

More
than
10ms

time

time

There are 3 available solutions.
Solution1. To start pixel clock as 78MHz from the first time on THCV219 side.
Solution2. To make enough interval before 78MHz to discharge LOCKN up to above VIH on THCV219 side.
Solution3. To make THCV220 power down operation to discharge LOCKN up to above VIH.
Solution proposals
Long cableLong cable

THCV219

THCV219

THCV220

THCV219

THCV220

Solution 1 (THCV219 side)

Solution 2 (THCV219 side)

Solution 3 (THCV220 side)

To start 78MHz from the first time does not have any
bothersome.

To make enough interval before freq. change candischarge LOCKN, resulting into proper training.

To make THCV220 power down operation candischarge LOCKN, resulting into proper training.

pix.
clk
Ser
Des

THCV220

Long cable

78MHz

78MHz
Training
signal(LOCKN=H)

78MHz
Video
signal

LOCKN
voltage

40MHz

No clock

78MHz

40MHz

40MHz
Video
signalNo signal

78MHz
Training
signal40MHzVideosignal(LOCKN=H)

78MHz
Video
signal78MHz
Training
signal(LOCKN=H)

LOCKN

LOCKN
voltage

THCV220 PDN

voltagetime

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78MHz

time

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THCV220 PDN (dot line)

time

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PCB Layout Considerations








Use at least four-layer PCBs with signals, ground, power, and signals assigned for each layer. (Refer tofigure below.)
PCB traces for high-speed signals must be single-ended micorstirp lines or coupled microstrip lines whose
differential characteristic impedance is 100Ω.
Minimize the distance between traces of a differential pair (S1) to maximize common mode rejection andcoupling effect which works to reduce EMI(Electro-Magnetic Interference).
Route differential signal traces symmetrically.
Avoid right-angle turns or minimize the number of vias on the high speed traces because they usually cause
impedance discontinuity in the transmission lines and degrade the signal integrity.
Mismatch among impedances of PCB traces, connectors, or cables also caused reflection, limiting the
bandwidth of the high-speed channels.
Using common-mode filter on differential traces is desirable to reduce EMI. Pay attention on data-rate
driven noise. For example, if data-rate is 1.5Gbps, common mode choke coil of 1.5GHz common mode
impedance is desired to be high, while 1.5GHz differential impedance is low.

PCB Cross-sectional View
for Microstrip Lines> 3 x S1

S1

GND

> 3 x S1

GND

Layer1: Signals
Layer2: Ground
Layer3: Power
Layer3: Signals

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THAN0127_Rev.1.40_E

Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply
to the customer's design. We are not responsible for possible errors and omissions in this material. Please
note if errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.

5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video
device, office automation device, communication device, consumer electronics, smartphone, featurephone, and amusement machine device. This product must not be used for applications that require
extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear
power control device, combustion chamber device, medical device related to critical care, or any kindof safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") inthis data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product otherthan the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent
that the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with acertain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged tohave sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems
necessary to support warranty for performance of this product. Except where mandated by applicablelaw or deemed necessary by THine based on the user’s request, testing of all functions and performanceof the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings ormalfunction, if pins of the product are shorted by such as foreign substance. The damages may cause asmoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.

THine Electronics, Inc.
sales@thine.co.jp

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