THCV213-214_Rev.2.60_E

THC
THCV213and THCV214
LVDS SerDes transmitter and receiver

General Description
THCV213 and THCV214
214 are designed to support
pixel data transmission between the Host and Display.
The chipset can transmit 18bit data and 4bit control
data through only a single differential cable at a pixel
clock frequency from 5MHz to 40MHz.
By V-by-One®
One® technologies, unique encoding
scheme and proprietary CDR technique, a linksynchronization is achieved without any externalfrequency reference such as a crystal oscillator. It
drastically improves the cost and space of PCBs of adisplay system.
THCV213 transmitter converts input data into asingle LVDS serial data stream with the embedded
clock. It supports pre-emphasis
emphasis for a long cabletransmission.
THCV214214 receiver extracts the clock from theembedded clock and transforms the serial data stream
back into the parallel data.

To confirm the reliability of the link, several
functions are supported. THCV213 can transmit the
SYNC pattern which expedites the link establishment.
THCV214 has an indicator of its PLL status.

Features












Transmit 18bit data and 4bit control data via asingle differential cable
Wide frequency range: 5MHz to 40MHz
Support SYNC pattern and LOCK indicator
Pre Emphasis mode
Clock edge selectable
Dual Display mode
Power Down modeLow power single 3.3V CMOS design
48pin TQFP
AEC-Q100
Q100 ESD Protection
EU RoHS Compliant

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Output Buffer

Deserializer

Serializer

Input Buffer

Block Diagram

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Package InformationPART

TEMP.RANGEPACKAGETHCV213-1TTN

0°C to 70°C

48pin TQFP

THCV214-1TTN

0°C to 70°C

48pin TQFP

THCV213-5TTP-40°C to 85°C

48pin TQFP

THCV214-5TTP-40°C to 85°C

48pin TQFPPIN Configuration

MOD1
MOD0
PDWN
RESERVED0
VDDO
CLKOUT
GNDO
D17
D16
D15
D14
VDDO

1
2
3
4
5
6
7
8
9
10
11
12

36
35
34
33
32
31
30
29
28
27
26
25

D14
D15
D16
D17
GND
CLKIN
VDD
PRBS
DUAL
PDWN
PRE0
PRE1

LOCKN
VDD
SYNC2
SYNC1
SYNC0
DE
GND
GNDO
D0
D1
D2
D3

1
2
3
4
5
6
7
8
9
10
11
12

36
35
34
33
32
31
30
29
28
27
26
25

VDD
D3
D2
D1
D0
GND
DE
SYNC0
SYNC1
SYNC2
VDD
INIT

48Pin TQFP

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PIN Description
THCV213 Pin Description
PIN Name
TXOUT1-,TXOUT1+TXOUT2-,TXOUT2+PIN No20, 1916, 15Type
LVDSOUTLVDSOUT

D0-D17IN

SYNC2-SYNC032, 33, 34, 35,
37, 38, 39, 40,
41, 43, 44, 45,
46, 47, 1, 2, 3, 4
27, 28, 29

DE

30

IN

CLKIN

6

IN

PDWN

10

IN

EDGE

23

IN

PRE0, PRE1

11, 12

IN

IN

INIT

25

IN

DUAL

9

IN

PRBS

8

IN

VDD
GND
LVDSVDDLVDSGNDPLLVDDPLLGND7, 26, 36, 48
5, 22, 24, 31, 42
17
18, 21
13
14

Power
Power
Power
Power
Power
Power

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Description
LVDS output.
LVDS output for Dual Display mode.
Identical to TXOUT1+/TXOUT1+/-.
Hi-Z
Z when Normal operation.
Data input.
Active if input DE=High
Sync input.
Active if input DE =Low.
Input sync data pulse must be wider than or equal to
two input clock periods.
Data Enable (DE) input.
Refer to Table2 for requirements.
Clock input.
5 MHz to 40MHz.
H: Normal operation.
L: Power Down, TXOUT1+/TXOUT1+/-, (TXOUT2+/-) are
Hi-Z.
Input clock triggering edge select.
H: Rise edge, L: Fall edge.
Select the level of pre-emphasis.
emphasis.
PRE1
PRE0
DescriptionLL
w/o PrePre-EmphasisLH
w/ 25% Pre
Pre-Emphasis
HL
w/ 50% Pre
Pre-EmphasisHH
w/ 100% Pre
Pre-Emphasis
H: Triggers SYNC pattern output fromTXOUT1+/
fromTXOUT1+/and (TXOUT2+/-),), normally used in Shake
Hand mode.
L: Normal operation.
H: Dual Display mode
Both TXOUT1+/- and TXOUT2TXOUT2+/- enabled.
L: Normal operation
Only TXOUT1+/- enabled.
H: Internal test pattern generator is enabled.
Pseudo-Random
Random Bit Sequence (PRBS) is
generated and is fed into input data latches.
Normally used for debug.
L: Normal operation.
Power supply pins for digital circuitry.
Ground pins for digital circuitry.
Power supply pin for LVDS output.
Ground pins for LVDS output.
put.
Power supply pin for PLL circuitry.
Ground pin for PLL circuitry.

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THCV214 Pin Description
PIN Name
RXIN-, RXIN+
D17-D0TypeLVDSIN
OUT

Description
LVDS input.
Data outputs.

SYNC0-SYNC2DECLKOUTLOCKNPIN No41, 428, 9, 10, 11, 13,
14, 15, 16, 17,
19, 20, 21, 22,
23, 25, 26, 27, 28
32, 33, 34
31
6
36

OUT
OUT
OUT
OUT

PDWN

3

IN

EDGE

38

IN

OE

39

IN

MOD1, MOD0

1, 2

IN

Sync output.
Data Enable (DE) output.
Clock output.
Lock detects output.
H: Unlock, L: Lock.
Can be used as an input signal detector, too.
H: Normal operation.
L: Power Down, all outputs except LOCKN and
CLKOUT are held low. Refer to Fig9 for details.
(Note1)
Output clock triggering edge select.
H: Rise edge, L: Fall edge.
Output Enable.
(DE, SYNC0-SYNC2, D0-D17,CLKOUT)
D17,CLKOUT)
H: Output disabled, all outputs are Hi
Hi-Z.
L: Output enabled. (Note1)
Select operation mode.
Both must be tied to GND.
MOD0
L

RESERVED0
RESERVED1
RESERVED2VDD
GND
LVDSVDDLVDSGNDPLLVDDPLLGND
VDDO
GNDO

4
45
46
35
30, 37
44
40,43
48
47
5, 12, 24
7, 18, 29

MOD1
L

Normal Mode
Shake Hand Mode
Not Available

OthersMust be tied to GND.
Must be tied to LVDSGND.
Must be tied to LVDSGND.
Power supply pin for digital circuitry.
Ground pins for digital circuitry.
Power supply pin for LVDS input.
Ground pins for LVDS input.
Power supply pin for PLL circuitry.
Ground pin for PLL circuitry.
Power supply pins for TTL output.
Ground pins for TTL output.

IN
IN
IN
Power
Power
Power
Power
Power
Power
Power
Power

Note1: The state of outputs determined by the combination of OE and PDWN is as follow.
follow

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THCV213-214_Rev.2.60_E
OE
L
L

H
H

Table1. Output State determined by OE and PDWN (THCV214)
PDWN
Output State
H
Normal Operation.
L
All outputs except LOCKN and CLKOUT are held low.
LOCKN is held high.
high
CLKOUT is driven high when EDGE input is high and is driven low
when EDGE input is low.
H
All outputs are Hi-Z.
HiL
All outputs are Hi-Z.
Hi

Operation Mode
NormalShake Hand

Table2. Requirements for DE input
DE = HighDE = Low
Min. 2tTCIP (See Fig. 5 for tTCIP )Min. 50tTCIP (See Fig
Fig. 5 for tTCIP )Max. 80usec
Min. 2tTCIP (See Fig. 5 for tTCIP )Min. 2tTCIP (See Fig
Fig. 5 for tTCIP )Absolute Maximum Ratings
Parameter
Supply Voltage (VDD)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Output Current
Junction Temperature
Storage Temperature Range
Reflow Peak Temperature / Time
Maximum Power Dissipation @+25°C°C
ESD Protection AEC-Q100-002(HBM)
002(HBM)
ESD Protection AEC-Q100-003(MM)003(MM)
ESD Protection AEC-Q100-011(CDM)
011(CDM) (Corner.750)

Min
-0.3
-0.3
-0.3
-0.3
-30
-55
-

Typ
±2
±200
±500

M
Max
4.0
VDD +0.3
VDDD +0.3
VDD +0.330
125125
260/101.9-

Consumer
Typ
Max
3.3
3.6
70

Min
3.0
-40

Industrial
Typ
Max
3.3
3.6
85

Unit
V
V
V
V
mA
°C
°C
°C/secW
kV
V
V

Operation Condition
Parameter
Supply Voltage
Operating Ambient Temperature

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Min
3.0
0

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Unit
V
°C

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Electrical Characteristics
CMOS/TTL DC Specifications
THCV213: VDD=VDD=LVDSVDD=PLLVDD, THCV214: VDD=VDD=VDDO=LVDSVDD=PLLVDD

Symbol
VIH
VIL
VOH

Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage

Conditions

VDD= 3.0V ~ 3.6V

VOL

Low Level Output Voltage

VDD= 3.0V ~ 3.6V

IIL

Input Leak Current

IOH = -4mA

IOL=4mA
0V ≤ VIN ≤ VDD

Min
2.0
GND

Typ
-

Max
VDD
0.8

Unit
V
V

2.4

-

-

V

-

-

0.4

V

-

-

±10

uA

THCV213 DC Specifications
VDD=VDD=LVDSVDD=PLLVDD

SymbolVODParameter
Differential Output Voltage

ΔVOD

Change in VOD between
complementary output states
Common Mode Voltage

VOC
ΔVOC
IOS
IOZ

Change in VOC between
complementary output states
Output Short Circuit Current
Output TRI-STATE
STATE Current

Conditions
RL=100Ω,
PRE<1:0>=L,L
RL=100Ω,
PRE<1:0>=L,L
RL=100Ω,
PRE<1:0>=L,L
RL=100Ω,
PRE<1:0>=L,L
VOUT=0V,RL=100Ω
PDWN=L,
VOUT=0V to VDD

Min

Typ

Max

Unit

250

350

450

mV

-

-

35

mV

1.125

1.25

1.375

V

-

-

35

mV

-

-

24

mA

-

-

±10

uA

THCV214 DC Specifications
VDD=VDD=VDDO=LVDSVDD=PLLVDD

Symbol
VTH
VTL
IILD

Parameter
Differential Input High Threshold
Differential Input Low Threshold
Differential Input Leakage Current

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Conditions
VIC = +1.2V
VIN = 2.4V/0V
VDD = 3.6V

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Min
-100

Typ
-

Max
100
-

Unit
mV
mV

-

-

±10

uA

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Supply Current
THCV213 Supply Current
VDD=VDD=LVDSVDD=PLLVDD

Symbol
ITCCW1ITCCW2ITCCS

Parameter
Transmitter Supply Current(Worst Case Pattern)(Fig. 1)
Transmitter Supply Current(Worst Case Pattern)(Fig. 1)
Transmitter Power Down
Supply Current

Conditions
Normal Operation
fCLKIN =40MHz
VDD=3.3V
Dual Display Mode
fCLKIN =40MHz
VDD=3.3V
PDWN = L

Min

Typ

Max

Unit

-

-

60

mA

-

-

90

mA

-

-

10

uA

THCV214 Supply Current
VDD=VDD=VDDO=LVDSVDD=PLLVDD

Symbol
IRCCW
IRCCS

Parameter
Receiver Supply Current(Worst Case Pattern)(Fig. 1)
Receiver Power Down
Supply Current

Conditions
fCLKOUT = 40MHz
VDD=3.3V
CL=8pF (Fig. 4)
PDWN = L

Min

Typ

Max

Unit

-

-

70

mA

-

-

10

uA

Fig. 1 Test Pattern

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Switching Characteristics
THCV213 Switching Characteristics
VDD=VDD=LVDSVDD=PLLVDD

Symbol
tTCIP
tTCP
tTCH
tTCL
tTS
tTH
tTO

Parameter
CLKIN Period (Fig. 5)
TXOUT Period (Fig. 5)
CLKIN High Time (Fig. 5)
CLKIN Low Time (Fig. 5)
TTL Data Setup to CLKIN (Fig. 5)
TTL Data Hold from CLKIN
C(Fig. 5)
CLKIN to TXOUT+/- Delay (Fig. 5)

tTLH

TTL Input Low to High Transition Time
(Fig. 2)TTL Input High to Low Transition Time
(Fig. 2)
LVDS Differential Output Transition
Time (Fig. 3)
Phase Lock Loop Set Time (Fig. 7)
PDWN Low to Output Hi-Z
Hi Set Delay(Fig. 7)
INIT High to Sync Pattern Output Delay(Fig. 8)INIT Low to Normal Pattern Output
Delay (Fig. 8)

tTHL
tTLVT
tTPLL
tTHZ
tTSYNC1tTSYNC2

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Min
25
0.35tTCIP
0.35tTCIP
5
0(3+17/21)
tTCIP

Typ
tTCIP
0.5tTCIP
0.5tTCIP-

Max
200
0.65tTCIP
0.65tTCIP(3+17/21)
tTCIP+7

Unit
ns
ns
ns
ns
ns
ns

-

3.0

5.0

ns

-

3.0

5.0

ns

-

0.6

1.5

ns

-

-

10.0

ms

-

3.6

-

ns

-

ns

-

ns

-

8/19

-

(17/21)tTCIP+3(1026+17/21)
tTCIP+3ns

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THCV214 Switching Characteristics
VDD=VDD=VDDO=LVDSVDD=PLLVDD

Symbol
tRCIP
tRCP
tRCH
tRCL
tRS
tRH
tRO
tRLH
tRHL
tRPLL1
tRPDD
tRDO
tRCOL
tRLCS
tRPLL2tRLN

Parameter
RXIN Period (Fig. 6)
CLKOUT Period (Fig. 6)
CLKOUT High Time (Fig. 6)
CLKOUT
KOUT Low Time (Fig. 6)
TTL Data Setup to CLKOUT (Fig. 6)
TTL Data Hold from CLKOUT
CL(Fig. 6)
RXIN+/- to CLKOUT Delay (Fig. 6)
TTL Output Low to High Transition Time
(Fig. 4)
TTL Output High to Low Transition Time
(Fig. 4)Phase Lock Loop Set (Fig. 9)Power-Down Delay (Fig. 9)
LOCKN transition to TTL Data Output
Delay (Fig. 9)
Beginning of Clock Output to LOCKN
transition Time(Fig. 9)
LOCKN transition to Stop of Clock Output
Time(Fig. 9)
Phase Lock Loop Set (Fig. 10)
Data Stop to LOCKN Transition Delay(Fig. 10)

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Min
25
0.3tRCP
0.3tRCP(4+13.5/21)
tRCP

Typ
tRCIP
tRCIP/2
tRCIP/2-

Max
200(4+13.5/21)
tRCP+7

Unit
ns
ns
ns
ns
ns
ns

-

3.0

5.0

ns

-

3.0

5.0

ns

-

9

10.0
-

-

2

-

10

-

-

3

-

-

-

-

10.0

ms
ns
clock
cyclesclock
cyclesclock
cycles
ms

-

7

-

ns

-

ns

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AC Timing Diagram and Test Circuits
90%

90%

CLKIN
D17
17-D0
SYNC
SYNC2-SYNC0
DE
10%

10%

tTLH

tTHL

Fig. 2 CMOS/TTL Inputs Transition Time (THCV213)

Fig. 3 LVDS Outputs Transition Time (THCV213)

Fig. 4 CMOS/TTL Outputs Load and Transition Time (THCV214)

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Fig. 5 Transmitter Output Timing (THCV213)

tRCIP
Stop Start

RXIN+/-

Stop Start
#1

#19

#2

#3

#18

#19

Stop Start
#1

#2

#3

#18

#19

#1

tRO

CLKOUT

VDD/2

tRCH

tRCL

Solid line: EDGE=”HIGH”
Dashed line: EDGE=”LOW”

tRCP
D17-D0SYNC2-SYNC0
DE

VDD/2

VDD/2

tRS

tRH

Fig. 6 Receiver Output Timing (THCV214)

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Fig. 7 Transmitter Start-up
Start
and Power-down
down Sequence (THCV213)

Fig. 8 Transmitter Timing Sequence (THCV213)

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Fig. 9 Receiver Start-up
Start
and Power-down
down Sequence (THCV214)

Fig. 10 Receiver Lock Recovery Sequence (THCV214)

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THCV213-214_Rev.2.60_E

Detailed Description
With V-by-One®’sOne®’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV213
and THCV214 enable transmission of 18bit video signals (D17 to D0) and 4bit
bit control signals (SYNC2 toSYNC0, and DE) by a single differential pair cable withth minimal external components.
components.THCV214, the receiver,can seamlessly operate for a wide range of a parallel
parallel clock frequency of 5MHz to 40MHz, detecting thefrequency of an incoming data stream, and recovering both
both the clock and data by itself. It does not need any
external frequency reference, such as a crystal oscillator.
THCV213 serializes video signals and control signals separately, depending on the polarity of Data Enable(DE) input. DE is a signal which indicates whether video or control signals
ls are active. When DE input is high, it
serializes D17 to D0 inputs into a single differential
different data stream. And it transmits serialized control signals(SYNC2 to SYNC0) when DE input is low.
THCV214 automaticallylly extracts the clock from the incoming data stream andd converts the serial data into 18
bit parallel
llel data with DE being high or three controlcosignals with DE being low, recognizing which type of serial
data is being sent by the transmitter.

Operation ModeIn order to accommodate various types of data format or to expedite the link establishment betw
between thetransmitter and receiver, THCV214 has two modes of operation, namely Normal Modeode and Shake Hand Mode.
Normal Mode
The Normal mode operation is the one described above in “Detailed Description”. This mode fully utilizes thechipset’s capability, enabling the transmission of 18bit video signals and 4bit control signals. It is required tohave DE signal which indicates whether video or control signals are active.
Shake Hand Mode
This mode requires an extra wire connecting THCV214’s LOCKN and THCV213’s
3’s INIT pin. This wire does
not need to be controlled impedance.. While the link is not being established between the transmitter and receiver,
the receiver’s LOCKN is driven high so that the receiver tells the transmitter to send a special set of data patternwhich makes them connect easily. The chipset automatically enters the Shake Hand mode, once THCV214’s
LOCKN pin and THCV213’s INIT pin are connected together. If there is no DE signal, THCV213/214 can stillwork in the Shake Hand mode with the transmitter’s DE input tied high. In this case, the amou
amount of datatransmission reduces to 18 bit digital signals (D17 to D0.)

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DE Requirement
There are some requirements for DE signal if the chipset is to be used in the Normal mode as described inTable 2.
DE Requirements for Normal Mode
The length of DE being low is at least 50 clock cycles
cycle long. The maximum time of DE being high is 80us, theminimum of DE=High is 2 clock cycles.

THCV213 Power Down (PDWN)THCV213 is set as the Power Down mode when PDWN is low.. All the internal circuitry turns off and the
TXOUT+/- outputs turn to Hi-Z.
Z. Refer to Fig. 7

THCV213 EDGE
The polarity of the EDGE pin selects which edge (rising or falling) of the input clock by which the input data
are latched in. When EDGE is set high, the transmitter uses the rising edge of the input clock to take in the input
data. When EDGE is low, it takes in the data at the falling edge of the clock. Select its polarity so that thetransmitter latches in the data withith better setup/hold time margin.

THCV213 Pre-Emphasis
Emphasis (PRE1,0)Pre-emphasis
emphasis can equalize severe signal degradation caused by long distance or high--speed transmission. Twopins, PRE1 and PRE0, select the strength of pre-emphasis.
pre

THCV213 INIT
Driving the INIT pin high makess the transmitter send a special set of pattern called SYNC pattern, whichmakes it easier for the receiver to recover the clock and data. This function is normally used in the Shake Hand
mode with a wire connecting the transmitter INIT pin and the receiver LOCKN pin. It can also be used to
expedite the link establishment in the Normal mode by driving the INIT pin high at power up, forcing thetransmitter to output the SYNC pattern for a certain amount of time in order to train the recei
receiver.

THCV213 Dual Display Mode (DUAL)
THCV213 has two high speed output buffers so that it can be used in an application where a video source
wants to send the same data to two displays. The DUAL pin activates the Dual Display mode.

THCV213 PRBS
Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo
Pseudo-Random Bit
Sequence of 223-1.
The generated PRBS is fed into input data latches, formatted as VGA video like data, encoded and serialized
into TXOUT output.
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THCV213-214_Rev.2.60_E
This function iss normally to be used for analyzing the signal integrity of the transmission channel including
PCB traces, connectors, and cables.

THCV214 Lock/Input Detect (LOCKN)
When the PLL of THCV214 has locked to the incoming data stream, it drives LOCKN low. And then
TTL/CMOS outputs become valid. This LOCKN signal can also be used as an indicator of whether the incoming
data is valid or not.
This pin is to be connected to the transmitter INIT pin with a cable in the Shake Hand mode.

THCV214 Power Down (PDWN)THCV214 is set as the Power Down mode when PDWN is low. All the internal circuitry and input buffers turnoff, and all outputs except LOCKN and CLKOUT are held low. The LOCKN pin is driven high when in thePower Down mode. The CLKOUT is fixed one way or the otherther depending on the EDGE input. Refer to Fig. 9.

THCV214 EDGE
The polarity of the EDGE pin selects which edge (rising or falling) of the output clock by which the output data
are latched out. When EDGE is set high, the receiver uses the falling edge of the output clock to put out the dataso that the next-stagestage chip can use the rising edge of the clock to latch in the data with the maximum setup/holdtime margin, and vice versa. Select its polarity according to the next-stagestage chip input characteristics.

THCV214 Output Enable (OE)The OE pin can disable TTL/CMOS outputs and place them in Hi-Z.
Z. Thus THCV214’s TTL/CMOS outputs
can be bused so that the receiver can be used in an application where there are multiple video sources and one
display.

THCV214 MOD1,0
Both MOD1 and MOD0 must be tied to GND. The receiver enters into an appropriate operation mode by itself.

Cables and Connectors
In a system with high speed digital signals, a special care must be taken to avoid loss and degradation of thesignals due to limited bandwidth and impedance mismatch along the transmission line. Characteristic impedanceof PCB traces, cables, and connectors must be tightly controlled.
Use cables that have a differential characteristic impedance of 100Ω. Shielded twisted pair cables arerecommended for increasing noise immunity and lowering EMI.
Connectors are recommended that cause minimum discontinuities in terms of characteristic impedance andgeometry of the transmission path.

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PCB Layout Considerations
Use a four-layer PCB with signal, ground, power, and signal assigned for each layer. PCB traces for high-speed
signals (TXOUT, RXIN) must be microstrip lines with a differential impedance of 100Ω. Route differential
signal traces symmetrically. Avoid right angle turns of thehe high speed traces because they usually cause
impedance discontinuity.
Place a 100 Ω termination resistor between RXIN+ and RXIN- as close to the receiver as possible to reducereflection.
Separate all the power domains in order to avoid unwanted noise coupling between noisy digital and sensitive
analog domains. Use high frequency ceramic capacitors of 10nF or 0.1μF as bypass capacitors between powerand ground pins. Place them as close to each power pin as possible. A 4.7μF capacitor in parallel with thesmaller capacitor to PLLVDD is recommended for the receiver.

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THCV213-214_Rev.2.60_E

Package
9.0+/-0.2
7.0+/-0.2

1.2 Max
1.00+/-0.05
0.10+/-0.05
2.3

2.3

7.0+/-0.2

9.0+/-0.2

2.3

ø1.0

ø 0..8
ø00.4

48

2.3

1

0.50
0.75

0.22+/-0.05

0.09~0.20

0.08 M0° ~ 8°SSEATING PLANE

0.10 S

0.50

0.25
0.60+/-0.15
1.00

Copyright©2023 THine Electronics, Inc.

Unit : mm

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THCV213-214_Rev.2.60_E

Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp
Copyright©2023 THine Electronics, Inc.

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