Report Title:

ADSP-2156x in LQFP Automotive
Grade 2 Cu Wire Qualification

Report Number: 17599
Revision:B

Date:

9 February 2023

Reliability Report: 17599

SummaryThis report documents the successful completion of the reliability qualification requirements
for the release of the ADSP-21562/21562W, ADSP-21563/21563W, ADSP-21565/21565W
product with Cu wire in a 120-LQFP_EP package at SC3. The ADSP-2156x are the next
generation SHARC DSP processor family.

Table 1: ADSP-2156x Product Characteristics
Die/FabDie Id

TMKK81

Die Size (mm)4.44 x 4.4

Wafer Fabrication Site
Wafer Fabrication Process
Approximate Transistor Count
Passivation Layer
Bond Pad Metal Composition

E_TSMC1512
CMOS
20.0 million
undoped-oxide/SiN
AlCu(0.5%)

Package/AssemblyPackage

120-LQFP_EP

Body Size (mm)14.00 x 14.00 x 1.40

Assembly Location

STATS (SC3)

Molding Compound

Sumitomo G700SQ

Die Attach

Ablestik 8200T

Wire TypeNMC EX1F

Wire Diameter (mils)

0.8

Lead Frame Material

CopperLead Finish

N/A

Moisture Sensitivity Level

3

Maximum Peak Reflow Temperature (°C)

260

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Reliability Report: 17599

Description / Results of Tests Performed
Tables 2 through 4 provide a description of the qualification tests conducted and the associatedtest results for products manufactured on the same technologies as described in Table 1. Alldevices were electrically tested before and after each stress. Any device that did not meet allelectrical data sheet limits following stressing would be considered a valid (stress-attributable)
failure unless there was conclusive evidence to indicate otherwise.

Table 2: LQFP_EP at STATS (SC3) with Cu Wire Package
Qualification Test Results
SampleQty.
SizeFailures
Q17599.1.2450High Temperature Storage Life
150°C, 1,000
ADSPJESD22-A103
Q17599.2.2450(HTSL) 2Hours
21565
Q17599.3.2450
Q17599.1.3
110
ADSPSolder Heat Resistance (SHR) 1,2
J-STD-020
MSL-3
Q17599.2.3
11021565
Q17599.3.3
110
Q17599.1.3
770-55°C/+125°C,
ADSPTemperature Cycling (TC) 1,2
JESD22-A104
Q17599.2.3
7702,000 Cycles
21565
Q17599.3.3
770
Q17599.1.1
77085°C, 85%RH,
Temperature Humidity BiasADSPJESD22-A118
Biased, 2,000
Q17599.2.1770(THB) 1,221565Hours
Q17599.3.1
7701 These samples were subjected to preconditioning (per J-STD-020 Level 3) prior to the start of the stress test. Level 3
preconditioning consists of the following: Bake: 24 hrs @ 125°C, Unbiased Soak: 192 hrs @ 30°C, 60%RH, Reflow:
3 passes through an oven with a peak temperature of 260°C.
Test Name

Specification

Conditions

DeviceLot #2 Units were tested pre and post stress and ambient and hot temperature

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Reliability Report: 17599

Table 3: LQFP_EP at STATS (SC3) with Au Wire Package
Qualification Test Results
Test Name

Specification

Conditions

Device

JESD22A118

130C
85%RH
33.3 psia,
96 Hours

ADSP21565

Unbiased HAST (UHST) 1,2

Q13566.11
Q13566.12

Sample
Size
77
77

Qty.
Failures00

Q13566.13

77

0Lot #1 These samples were subjected to preconditioning (per J-STD-020 Level 3) prior to the start of the stress test. Level 3

preconditioning consists of the following: Bake: 24 hrs @ 125°C, Unbiased Soak: 192 hrs @ 30°C, 60%RH, Reflow:
3 passes through an oven with a peak temperature of 260°C.
2 Units were tested pre and post stress and ambient and hot temperature

Table 4: 28nm CMOS at TSMC Fab-15 Fab Qualification Test Results
Test Name

Q13499.1
Q13499.2
Q13499.3
Q16972.1.1
Q17599.1.2
Q17599.2.2
Q17599.3.2

SampleSize777777
77454545

Qty.
Failures0000000

ADSP-21565

Q16792.1.11

450

ADSP-21569

Q16972.1.14
Q16972.2.3
Q16972.3.3
Q16972.1.15
Q16972.1.19
Q16972.4.1
Q16972.5.2
Q16972.5.3
Q16972.5.1
Q16972.5.4
Q16972.5.5
Q16972.5.6
Q16972.5.8
Q16972.5.7Q16972.4.2
Q16972.3.4
Q16972.5.9
Q16972.3.5
Q16972.4.3
Q16972.4.4

1159216410239165148148114
45160160160160
149104269311915400000000000000000000

SpecificationConditions

High Temperature Operating Life(HTOL) 1,3

JESD22-A108

125°C<Tj<135°C,Biased,
1,000 Hours

ADSP-21569

High Temperature Storage Life(HTSL) 1,2

JESD22-A103

150°C, 1,000 Hours

ADSP-21565

Power and Temp Cycling(PTC)1,2

JESD22-A105-40°C/+105°C,
P1000

Early Life Failure Rate
(ELFR) 2AEC
Q100-008

Tj=125C, Biased,
48 Hours

DeviceLot #Page 4 of 6

Reliability Report: 17599
1 These samples were subjected to preconditioning (per J-STD-020 Level 3) prior to the start of the stress test. Level 3

preconditioning consists of the following: Bake: 24 hrs @ 125°C, Unbiased Soak: 192 hrs @ 30°C, 60%RH, Reflow: 3
passes through an oven with a peak temperature of 260°C.
2 Pre- and post-stress electrical test was performed at room and hot temperatures.
3 Pre- and post-stress electrical test was performed at room, hot, and cold temperatures

Samples of the many devices manufactured with these package and process technologies arecontinuously undergoing reliability evaluation as part of the ADI Reliability Monitor Program.
Additional qualification data is available on Analog Devices' web site.

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Reliability Report: 17599

ESD Test Results
The results of Human Body Model (HBM) and Field-Induced Charged Device Model(FICDM) ESD testing are summarized in Table 5. ADI measures ESD results using stringent
test procedures based on the specifications listed. Any comparison with another supplier's
results should ensure that the same ESD test procedures have been used. For further details,
please see the EOS/ESD chapter of the ADI Reliability Handbook (available via the 'Qualityand Reliability' link on Analog Devices' web site).

Table 5: ADSP-21565 ESD Test Results
ESD ModelPackage

RC NetworkHighest
Pass Level

First FailLevel

1Ω, Cpkg±750V±1000V

1.5kΩ, 100pF±3000V±3500V

ESD Test Spec

FICDM

120-LQFP_EP

AEC Q100-011

HBM

400-CSP_BGA

ESDA/JEDEC JS-001-2011

Latch-Up Test Results
Three samples of the ADSP-21565 were latch-up tested at TA=105°C per JEDEC Standard
JESD78, Class II. All pins passed.
Passing Positive Current

Passing Negative Current

Passing Over-Voltage+200mA-200mA

2.842/5.205/2.37/1.185/1.582V

Approvals
Reliability Engineer: Carolyn Pipitone

Additional Information
Data sheets and other additional information are available on Analog Devices' web site

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