THCV241A_Rev.2.11_E

THCV241A
SerDes transmitter with bi-directional transceiver

1

General Description

THCV241A is designed to support 1080p60 2Mpixel
uncompressed video data over 15m 100ohm
differential STP or single-end 50ohm Coaxial cablewith 4 in-line connectors between camera andprocessor by V-by-One® HS.
THCV241A supports a MIPI CSI-2. Each CSI-2 datalane can transmit up to 1.2Gbps/lane. Virtual channel
is supported.
One high-speed V-by-One® HS lane can transmit up
to 1080p60fps. The maximum serial data rate is
4Gbps/lane. 2nd output lane supports HDR large
amount of data or data copy-and-distribution
experience.
THCV241A is capable to control and monitor
camera module from remote ECU via GPIO, UART or
1Mbps 2-wire serial interface.
Several fault and error detection function including
CRC provides hardware functional safety design.

3

2

Features

MIPI CSI-2 with 1,2 or 4-lane input
MIPI D-PHY supports 80Mbps~1.2Gbps
MIPI Virtual channel supported
Video formats: RAW8/10/12/14/16/20,
YUV422/420, RGB888/666/565, JPEG, Userdefined generic 8-bit
V-by-One® HS 400Mbps~4Gbps x2lane
V-by-One® HS standard version1.5
Reference clock input CKI range 10~40MHz
shareable with video source CMOS sensor
Wide range IO voltage from 1.7V to 3.6V
Additional spread spectrum to reduce EMI
2-wire serial interface 1Mbps bridge function
Remote GPIO/UART control and monitoring
Error detection including CRC and notification
QFN40 5x5mm 0.4mm pitch Exp-pad package

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Block Diagram
MIPI CSI-2
Rx 4-lane

V-by-One® HS
Tx 2 lane

THCV241A

RD3p

TX0N

RD1n
RCKp
RCKn
RD0p

CSI2 / Formatter

RD1p

TX0P

TX1N
TX1P

PLL

RD0n

Serializer

RD3n

RD2p
RD2n

Sub-Link

CKI

TCMN

Settings
GPIO
2-wireserial I/F

Controls

TCMP

OSC

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Contents Page
1

General Description ......................................................................................................................................... 1

2

Features ........................................................................................................................................................... 1

3

Block Diagram ................................................................................................................................................ 1

4

Pin Configuration ............................................................................................................................................ 4

5

Pin Description ................................................................................................................................................ 5

6

Functional Description .................................................................................................................................... 6
6.1

Functional Overview ............................................................................................................................... 6

6.2

Reference clock supply............................................................................................................................ 6

6.3

MIPI input setting .................................................................................................................................... 7

6.4

HTPDN/LOCKN ..................................................................................................................................... 8

6.5

V-by-One® HS output setting ................................................................................................................. 96.5.1

MPRF (Main-Link PRivate Format) ............................................................................................... 9

6.5.2

V-by-One® HS standard format .................................................................................................... 10

6.5.3

V-by-One® HS output Byte mode................................................................................................. 16

6.5.4

V-by-One® HS output Distribution mode ..................................................................................... 16

6.5.5

V-by-One® HS Low Radiation Emission or High Immunity Resistance mode ............................ 16

6.5.6

V-by-One® HS output Odd/Even swap......................................................................................... 17

6.5.7

V-by-One® HS output Drivability ................................................................................................ 17

6.5.8

V-by-One® HS output Low Frequency mode ............................................................................... 17

6.5.9

Target Pixel clock .......................................................................................................................... 18

6.6

Blanking period restriction under low MIPI data-rate environment...................................................... 18

6.7

PLL setting ............................................................................................................................................ 19

6.8

PLL Auto setting function ..................................................................................................................... 22

6.9

V-by-One® HS output data-rate ............................................................................................................ 23

6.10

V-by-One® HS output Spread Spectrum............................................................................................... 23

6.11

V-by-One® HS CRC ............................................................................................................................. 24

6.12

MIPI Packet Header V-by-One® HS output bridge mode .................................................................... 25

6.13

MIPI Virtual Channel bridge ................................................................................................................. 26

6.14

V-by-One® HS VSYNC generation ...................................................................................................... 27

6.15

V-by-One® HS HSYNC generation ...................................................................................................... 28

6.16

MIPI Short Packet V-by-One® HS output bridge mode ....................................................................... 30

6.17

2-wire serial interface ............................................................................................................................ 32

6.17.1

2-wire serial I/F slave Device ID ................................................................................................... 32

6.17.2

2-wire serial Read/Write access to local Register.......................................................................... 33

6.18

2-wire serial I/F Watch Dog Timer ........................................................................................................ 34

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6.19

Register Auto Checksum diagnosis ....................................................................................................... 34

6.20

Sub-Link setting .................................................................................................................................... 35

6.20.1

Sub-Link 2-wire Set and Trigger mode (2-wire Normal mode) .................................................... 37

6.21

Sub-Link Watch Dog Timer................................................................................................................... 40

6.22

Sub-Link Interrupt detection ................................................................................................................. 41

6.23

GPIO setting .......................................................................................................................................... 42

6.23.1

Sub-Link Polling GPIO input/output ............................................................................................. 42

6.23.2

Register GPIO ............................................................................................................................... 44

6.24

Internal Error / status signal monitoring GPIO output .......................................................................... 45

6.25

Internal Error / status signal monitoring register ................................................................................... 46

6.26

Interrupt monitoring .............................................................................................................................. 47

6.27

Build-In Self-Test pattern generator (BIST) .......................................................................................... 49

6.28

Main-Link Field BET ............................................................................................................................ 51

6.29

Sub-Link Field BET operation and output from GPIO ......................................................................... 51

6.30

CMOS IO Input noise Filter .................................................................................................................. 52

6.31

CMOS output drive strength ................................................................................................................. 52

6.32

CKO reference clock buffer output ....................................................................................................... 53

6.33

Soft Reset .............................................................................................................................................. 54

6.34

Power On Sequence............................................................................................................................... 56

6.35

Lock / Re-Lock Sequence ..................................................................................................................... 57

7

Absolute Maximum Ratings .......................................................................................................................... 58

8

Recommended Operating Conditions............................................................................................................ 58

9Consumption Current .................................................................................................................................... 59

10

DC Specifications ...................................................................................................................................... 61

10.1

CMOS DC Specifications...................................................................................................................... 61

10.2

MIPI Receiver DC Specifications ......................................................................................................... 61

10.3

CML Transmitter DC Specifications ..................................................................................................... 62

10.4

CML Bi-directional Buffer DC Specifications ...................................................................................... 63

11

AC Specifications .......................................................................................................................................... 64
11.1

MIPI Receiver AC Specifications.......................................................................................................... 64

11.2

CML Transmitter AC Specifications ..................................................................................................... 64

11.3

CML B-directional Buffer AC Specifications ....................................................................................... 64

11.4

2-wire serial Master/Slave AC Specifications ....................................................................................... 65

12

Package...................................................................................................................................................... 67

13

Notices and Requests................................................................................................................................. 68

MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions.

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4

Pin Configuration

LOCKN

MSSEL

VDDIO

PDN0

TX0P

18

RD1N

TX1N

17

35

RCKP

TX1P

16

36

RCKN

TEST

15

37

RD0P

TCMN

14

38

RD0N

TCMP

13

39

RD2P

PDN1

12

40

RD2N

VDDB

11

GPIO2

1

2

3

4

5

6

7

8

9 10

GPIO3

GPIO1

41 EXPGND

GPIO0

34

VDDL

19

VDDL

RD1P

INT

TX0N

CKI

33

AIN

20

VDDIO

RD3N

SDA

VDDA

CKO

32

THCV241A

VDDOP

RD3P

VDDM

31

SCL

VDDM

30 29 28 27 26 25 24 23 22 21

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5

Pin Description
Pin Name
RD3P/N
RD1P/N
RCKP/N
RD0P/N
RD2P/N
TX0P/NTX1P/N

Pin #
31,32
33,34
35,36
37,38
39,40
18,19
16,17

type*
MI
MI
MI
MI
MI
CO
CO

TCMP/N

13,14

CB/B

SCL
SDA

29
28

B
B

PDN0

24

I

PDN1

12

I

TEST
CKI
CKO

15
5
3

I
I
O

LOCKN

21

I

GPIO0
GPIO1
GPIO2
GPIO3

7
8
9
10

B
B
B
B

MSSEL

22

I

AIN

27

I

INT

26

O

Description
MIPI lane3 differential data input
MIPI lane1 differential data input
MIPI differential clock inputs
MIPI lane0 differential data input
MIPI lane2 differential data input
V-by-One® HS lane0 High-speed CML signal output
V-by-One® HS lane1 High-speed CML signal output
TCMP/N (PDN1=1): CML Bi-directional Input/Output(Sub-Link).
NC (PDN1=0): Not Connected. Must be open.
2-w ire serial Master/Slave SCL
2-w ire serial Master/Slave SDA
Whole IC Pow er Dow n
0 : Pow er Dow n
1 : Normal Operation
Sub-Link Pow er Dow n
0 : Sub-Link Pow er Dow n
1 : Sub-Link Normal Operation
Test pin. Must be tied to Ground for normal operation.
Reference Clock Input
Reference Clock Output
LOCK detect input Negative polarity
If external LOCKN connection is used, it is supposed to beconnected to Rx LOCKN w ith a 30kΩ pull-up resistor.
GPIO0
GPIO1
GPIO2
GPIO3
MSSEL (PDN1=1): Sub-Link Master/Slave Select
0 : Sub-Link Master side(inside 2-w ire serial I/F is slave)
1 : Sub-Link Slave side(inside 2-w ire serial I/F is master)
Sub-Link Master is connected to HOST MCU.
HTPDN (PDN1=0): HoT Plug Detect input Negative polarity
Must be connected to Rx HTPDN w ith a 30kΩ pull-up resistor.
Select Slave Address
0 : 2w ire serial Address = 7'b000_1011
1 : 2w ire serial Address = 7'b011_0100
Interrupt signal output.
It must be connected w ith a pull-up resistor.
0 : Interrupt occurred
1 : Steady state
PLL Pow er supply Pin 1.2V
MIPI Pow er supply Pin 1.2V
Analog Pow er supply Pin 1.2V
Digital Pow er supply Pins 1.2V
Analog Pow er supply Pin 1.8~3.3V
IO Pow er supply Pin 1.8~3.3V
Exposed Pad Ground : Must be tied to Ground

VDDOP
2
P
VDDM
1,30
P
VDDA
20
P
VDDL
6,25
P
VDDB
11
P
VDDIO
4,23
P
EXPGND
41
G*type symbol
MI=MIPI Input, CO=CML Output
CB=CML Bi-directional input/output
B=1.8~3.3V CMOS Bi-directional input/output, I=1.8~3.3v CMOS Input, O=1.8~3.3v CMOS Output
P=Pow er, G=Ground

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6Functional Description

6.1 Functional Overview
THCV241A can receive MIPI CSI-2 video and transmit it to over 15m length. With High Speed CML SerDes,
high reliability and robustness encoding scheme and CDR (Clock and Data Recovery) architecture, the
THCV241A enables to transmit RAW/YUV/RGB/JPEG/Generic8bit data through Main-Link by single 100ohm
differential pair or 50ohm Coax cable with minimal external components. Maximum supported resolution ishorizontal active 3840 pixels format. In addition, the THCV241A has Sub-Link which enables bi-directionaltransmission of 2-wire serial interface signals, GPIO signals and also HTPDN/LOCKN signals for Main-Link
through the other 1-pair of CML-Line. The THCV241A system is able to watch peripheral devices and to control
them via 2-wire serial interface or GPIOs. They also can report interrupt events caused by change of GPIO inputs
and internal statuses such as CRC error.

6.2 Reference clock supply
Reference clock supply CKI is required since MIPI CSI-2 clock stream will not always be continuous.
CKI frequency examples are 24MHz, 27MHz and 37.125MHz.
To supply the same oscillator clock as CMOS sensor to THCV241A is recommended.
See Figure 1.
Physical layout artwork of oscillator clock trace is supposed to be designed to shorten stub branch as possible.

CMOS Sensor

THCV241A

CKO

CKI

Stub*

MCLK

*Stub branch of OSC clock trace
must be as short as possible forsignal integrity.

OSC

Figure 1. Reference clock supply basic method
Another alternative is to make use of THCV241A CKO internal clock buffer function.
CKO clock buffer may strengthen clock drive ability in order to compensate clock signal loss in large structure.
On the other hand, additional clock buffer may become another EMI emission source as trade-off.

CMOS Sensor

THCV241A

MCLK

CKO

CKI

can be long(good) large structure available(bad) rather high EMI emission

OSC

Figure 2. Reference clock supply clock buffer method (optional)

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6.3 MIPI input setting
Setting of MIPI input can be configurable by 2-wire access to internal register.
Lane0 of MIPI input must always be used regardless of configuration as an obligation.
Table 1. MIPI input setting
Addr(h)Bits

Registerw idthR/W

Description

Default

0x1025[0]

R_RX_PN_SW

1

R/W

1'h0

0x1026[7:6]

R_RX_LANE_SEL0

2

R/W

0x1026[5:4]

R_RX_LANE_SEL1

2

R/W

0x1026[3:2]

R_RX_LANE_SEL2

2

R/W

0x1026[1:0]

R_RX_LANE_SEL3

2

R/W

0x102C[0]

R_RX_CLKLANE_EN

1

R/W

0x102D[4]

R_RX_DATALANE_EN

1

R/W

0x102D[1:0]

R_RX_LANE_SEL_EN

2

R/W

MIPI P/N sw ap
MIPI Data Lane RX0P/RX0N pin input mapping/sw ap select
MIPI standard format lane# assignment used on RX0P/RX0N input
The same setting as R_RX_LANE_SEL1/2/3 is prohibited.
MIPI Data Lane RX1P/RX1N pin input mapping/sw ap select
MIPI standard format lane# assignment used on RX1P/RX1N input
The same setting as R_RX_LANE_SEL0/2/3 is prohibited.
MIPI Data Lane RX2P/RX2N pin input mapping/sw ap select
MIPI standard format lane# assignment used on RX2P/RX2N input
The same setting as R_RX_LANE_SEL0/1/3 is prohibited.
MIPI Data Lane RX3P/RX3N pin input mapping/sw ap select
MIPI standard format lane# assignment used on RX3P/RX3N input
The same setting as R_RX_LANE_SEL0/1/2 is prohibited.
MIPI Clock Lane Enable
0:Disable
1:Enable
MIPI Data Lane Enable
0:Disable
1:Enable, follow ing R_RX_LANE_SEL_EN
MIPI Valid Data Lane number select
00:1Lane (lane0 Enable)
01,10:2Lane (lane<1:0> Enable)
11:4Lane (lane<3:0> Enable)

2'h0

2'h1

2'h2

2'h3

1'h0

1'h0

2'h3

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6.4

HTPDN/LOCKN

Hot-Plug Function
HTPDN indicates Main-Link connect condition between Transmitter and Receiver. HTPDN of Transmitter side
is high when Receiver is not active or not connected. Then Transmitter can enter into power down mode. HTPDN
is set to Low by the Receiver when Receiver is active and connects to the Transmitter, and then Transmitter must
start up and transmit CDR training pattern for link training. HTPDN is open drain output at the receiver side.
Transmitter side needs Pull-up resistor.
There is an application option to omit HTPDN connection between Transmitter and Receiver. In this case,
HTPDN at Transmitter side should always be at Low.
Lock Detect Function
LOCKN indicates whether CDR PLL of Main-Link is in lock status or not. LOCKN at Transmitter input is set
to High by pull-up resistor when Receiver is not active or in CDR PLL training. LOCKN is set to Low by Receiver
when CDR lock is completed. After that the CDR training mode finishes and then Transmitter shifts to the normal
mode. LOCKN of Receiver is open drain. Transmitter side needs pull-up resistor.
When an application omits HTPDN, LOCKN signal should only be considered with HTPDN pulled low byReceiver.
Vcc(Tx side)
V-by-One®
HS Rx

THCV241A

V-by-One®
HS Rx

30kΩ

30kΩ

THCV241A

30kΩ

Vcc(Tx side)MSSEL(HTPDN)

HTPDN

MSSEL
(HTPDN)

HTPDN

LOCKN

LOCKN

LOCKN

LOCKN

With HTPDN connect

Without HTPDN connect

Figure 3. Physical wire connection for wired Hot-plug and Lock detect scheme
It will need same GND potential reference between transmitter and receiver device to connect HTPDN andLOCKN pins directly like above. HTPDN and LOCKN can also be transmitted via Sub-Link without physicalwire connection. Assignment can be configurable by 2-wire access to internal register.
Table 2.
Addr(h)Bits

Registerw idthHTPDN/LOCKN register
R/W

0x101D[1:0]

R_HTPDN_SEL

2

R/W

0x101E[5:4]

R_LOCKN0_SEL

2

R/W

0x101E[1:0]

R_LOCKN1_SEL

2

R/W

Description

Default

V-by-One® HS HTPDN assignment
00:Sub-Link at PDN1=1 / HTPDN pin input at PDN1=0,
01:Reserved,
10:forced Low (Must be set at V-by -One® HS Distribution Enable),
11:forced High
V-by-One® HS LOCKN for lane0 assignment
00:Sub-Link, 01:LOCKN pin input, 10:forced Low , 11:forced High
V-by-One® HS LOCKN for lane1 assignment
00:Sub-Link, 01:LOCKN pin input, 10:forced Low , 11:forced High

2'h0

2'h0
2'h0

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6.5 V-by-One® HS output setting
Setting of V-by-One® HS output format can be configurable by 2-wire access to internal register.
Table 3.
Addr(h)Bits

RegisterV-by-One® HS output format setting
w idthR/W

0x1000[0]

R_VX1_LANE

1

R/W

0x1001[6:4]

R_OUTPUT_FMT

3

R/W

0x1002[5]

R_HFSEL

1

R/W

0x1055[1:0]

R_BITMAP_SEL

2

R/W

Description

Default

V-by-One® HS output lane number setting
0:1lane1:2lanes
V-by-One® HS output format setting
000:Main-Link PRivate Format (MPRF)
001:V-by-One® HS Standard YUV422(16bit)/RAW8
010:V-by-One® HS Standard RGB888
011:V-by-One® HS Standard RGB565
100:V-by-One® HS Standard RAW10 Mode1
101:V-by-One® HS Standard RAW12 Mode1
110: V-by-One® HS Standard RAW10 Mode2
111: V-by-One® HS Standard RAW12 Mode2
V-by-One® HS HFSEL (High Freq. SELect) mode Enable
0:HF Mode Disable
1:HF Mode Enable
V-by-One® HS output data mapping select
00:MAP1, 01:MAP2, 10:MAP3, 11:MAP4

1'h1

3'h0

1'h0
2'h0

6.5.1 MPRF (Main-Link PRivate Format)
MPRF format encoding preserves original data packet input to THCV241A and output the data packet fromcounterpart V-by-One® HS receiver. The counterpart receiver must have installed MPRF format decoder like
THCV242 because MPRF is not standard format.
Output V-by-One® HS Byte Mode is 4Byte Mode.
Video formats: RAW8/10/12/14/16/20, YUV422/420, RGB888/666/565, JPEG, and User-defined generic 8-bit
are all supported with MPRF.

CMOS Sensor

Original
Data packet(format,payload, etc.)

THCV241A

Main-Link
MPRF
format

THCV242

Preserved
Data packet(format,payload, et c.)

Processor
In ECU orcontroller

Figure 4. MPRF (Main-Link PRivate Format)

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6.5.2 V-by-One® HS standard format
THCV241A output format capabilities as transmitter are shown as follows. D[31:0] indicates V-by-One® HS
standard version1.5 Packer packet definition. Data can be transmitted normally only when both transmitter andreceiver are set to the same available format. Some of the THCV241A format may not be supported by particularcounterpart receiver because THCV241A prepares multiple formats that suit to multiple receiver devices
alternatives.
Table 4.
R_OUTPUT_FMT
R_HFSEL
R_BITMAP_SEL
default V-by-One®HS Byte Mode

Format Name
Vx1HS std. Packer Packet ref.

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]V-by-One® HS 1lane output data mapping format 1/3

1
0
0
3

1
3

2
3

0
3

3
3

1
0
4

1
4

YUV422
Map1

YUV422
Map2

YUV422
Map3

RAW8

RAW8
Map4

YUV422HF
Map1

YUV422HF
Map2

RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)
0
0
0
0
0
0
0
0
RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)0000RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)0000Y[7](1st)
Y[6](1st)
Y[5](1st)
Y[4](1st)
Y[3](1st)
Y[2](1st)
Y[1](1st)
Y[0](1st)
Cb(U)[7]Cb(U)[6]Cb(U)[5]Cb(U)[4]Cb(U)[3]Cb(U)[2]Cb(U)[1]Cb(U)[0]Y[7](2nd)
Y[6](2nd)
Y[5(2nd)
Y[4](2nd)
Y[3](2nd)
Y[2](2nd)
Y[1](2nd)
Y[0](2nd)
Cr(V)[7]Cr(V)[6]Cr(V)[5]Cr(V)[4]Cr(V)[3]Cr(V)[2]Cr(V)[1]Cr(V)[0]Cb(U)[7]Cb(U)[6]Cb(U)[5]Cb(U)[4]Cb(U)[3]Cb(U)[2]Cb(U)[1]Cb(U)[0]Y[7](1st)
Y[6](1st)
Y[5](1st)
Y[4](1st)
Y[3](1st)
Y[2](1st)
Y[1](1st)
Y[0](1st)
Cr(V)[7]Cr(V)[6]Cr(V)[5]Cr(V)[4]Cr(V)[3]Cr(V)[2]Cr(V)[1]Cr(V)[0]Y[7](2nd)
Y[6](2nd)
Y[5(2nd)
Y[4](2nd)
Y[3](2nd)
Y[2](2nd)
Y[1](2nd)
Y[0](2nd)

Cb(U)[7]/Cr(V)[7] Y[7](1st)/Y[7](2nd)0
Cb(U)[6]/Cr(V)[6] Y[6](1st)/Y[6](2nd)0
Cb(U)[5]/Cr(V)[5] Y[5](1st)/Y[5](2nd)0
Cb(U)[4]/Cr(V)[4] Y[4](1st)/Y[4](2nd)0
Cb(U)[3]/Cr(V)[3] Y[3](1st)/Y[3](2nd)0
Cb(U)[2]/Cr(V)[2] Y[2](1st)/Y[2](2nd)0
Cb(U)[1]/Cr(V)[1] Y[1](1st)/Y[1](2nd)0
Cb(U)[0]/Cr(V)[0] Y[0](1st)/Y[0](2nd)000Y[7](1st)/Y[7](2nd)00Y[6](1st)/Y[6](2nd)00Y[5](1st)/Y[5](2nd)00Y[4](1st)/Y[4](2nd)00Y[3](1st)/Y[3](2nd)00Y[2](1st)/Y[2](2nd)00Y[1](1st)/Y[1](2nd)00Y[0](1st)/Y[0](2nd)Y[7](1st)/Y[7](2nd) Cb(U)[7]/Cr(V)[7] Cb(U)[7]/Cr(V)[7]Y[6](1st)/Y[6](2nd) Cb(U)[6]/Cr(V)[6] Cb(U)[6]/Cr(V)[6]Y[5](1st)/Y[5](2nd) Cb(U)[5]/Cr(V)[5] Cb(U)[5]/Cr(V)[5]Y[4](1st)/Y[4](2nd) Cb(U)[4]/Cr(V)[4] Cb(U)[4]/Cr(V)[4]Y[3](1st)/Y[3](2nd) Cb(U)[3]/Cr(V)[3] Cb(U)[3]/Cr(V)[3]Y[2](1st)/Y[2](2nd) Cb(U)[2]/Cr(V)[2] Cb(U)[2]/Cr(V)[2]
Y[1](1st)/Y[1](2nd) Cb(U)[1]/Cr(V)[1] Cb(U)[1]/Cr(V)[1]
Y[0](1st)/Y[0](2nd) Cb(U)[0]/Cr(V)[0] Cb(U)[0]/Cr(V)[0]THine Electronics, Inc.

Copyright©2023 THine Electronics, Inc.
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SC: E

THCV241A_Rev.2.11_E

Table 5.
R_OUTPUT_FMT
R_HFSEL
R_BITMAP_SEL
default V-by-One®HS Byte Mode

Format Name
Vx1HS std. Packer Packet ref.

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]V-by-One® HS 1lane output data mapping format 2/3

1
1
2
4

2
3

3
0
0
3

1
0
4

4
0
0
3

RAW8HF

RGB888

RGB565

RGB565HF

RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)

B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]

B[4]
B[3]
B[2]
B[1]
B[0]
0
0
0
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
0
0
R[4]
R[3]
R[2]
R[1]
R[0]
0
0
0

B[4] (1st)B[3] (1st)B[2] (1st)B[1] (1st)B[0] (1st)G[5] (1st)G[4] (1st)G[3] (1st)G[2] (1st)G[1] (1st)G[0] (1st)R[4] (1st)R[3] (1st)R[2] (1st)R[1] (1st)R[0] (1st)B[4] (2nd)B[3] (2nd)B[2] (2nd)B[1] (2nd)B[0] (2nd)G[5] (2nd)G[4] (2nd)G[3] (2nd)G[2] (2nd)G[1] (2nd)G[0] (2nd)R[4] (2nd)R[3] (2nd)R[2] (2nd)R[1] (2nd)R[0] (2nd)

1
0
4

1
2
4

RAW10

RAW10HF
Map1

RAW10HF
Map3

0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[1]
RAW[0]
RAW[9]
RAW[8]
RAW[7]
RAW[6]
RAW[5]
RAW[4]
RAW[3]
RAW[2]000000RAW[1] (1st)RAW[0] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)
0
0
0
0
0
0
RAW[1] (2nd)RAW[0] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)0000RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)
0
0
0
0
0
0
RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)00THine Electronics, Inc.

Copyright©2023 THine Electronics, Inc.
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SC: E

THCV241A_Rev.2.11_E

Table 6.
R_OUTPUT_FMT
R_HFSEL
R_BITMAP_SEL
default V-by-One®HS Byte Mode

Format Name
Vx1HS std. Packer Packet ref.

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]

5
0
0
3

V-by-One® HS 1lane output data mapping format 3/3
1
0
4

1
1
4

6
0
3

2
3

7
0
3

1
3

RAW12

RAW12HF
Map1

RAW12HF
Map2

RAW10HF2
Map1

RAW10HF2
Map3

RAW12HF2
Map1

RAW12HF2
Map2

0
0
0
0
0
0
0
0
0
0
0
0
RAW[3]
RAW[2]
RAW[1]
RAW[0]
RAW[11]
RAW[10]RAW[9]
RAW[8]
RAW[7]
RAW[6]
RAW[5]
RAW[4]0000RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)0000RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)0000RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)0000RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)00RAW[1] (1st)RAW[0] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)00RAW[1] (2nd)RAW[0] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)00RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)00RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)THine Electronics, Inc.

Copyright©2023 THine Electronics, Inc.
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THCV241A_Rev.2.11_E

TX0P/N V-by-One® HS lane0

R_OUTPUT_FMT
R_HFSEL
R_BITMAP_SEL

V-by-One® HS 2lane output data mapping format 1/3

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]1003YUV422
Map1
Cb(U)[7]Cb(U)[6]Cb(U)[5]Cb(U)[4]Cb(U)[3]Cb(U)[2]Cb(U)[1]Cb(U)[0]
0
0
0
0
0
0
0
0
Cr(V)[7]Cr(V)[6]Cr(V)[5]Cr(V)[4]Cr(V)[3]Cr(V)[2]Cr(V)[1]Cr(V)[0]13YUV422
Map2
Cr(V)[7]Cr(V)[6]Cr(V)[5]Cr(V)[4]Cr(V)[3]Cr(V)[2]Cr(V)[1]Cr(V)[0]
0
0
0
0
0
0
0
0
Cb(U)[7]Cb(U)[6]Cb(U)[5]Cb(U)[4]Cb(U)[3]Cb(U)[2]Cb(U)[1]Cb(U)[0]23YUV422
Map3
0
0
0
0
0
0
0
0
Y[7](1st)
Y[6](1st)
Y[5](1st)
Y[4](1st)
Y[3](1st)
Y[2](1st)
Y[1](1st)
Y[0](1st)
Cb(U)[7]Cb(U)[6]Cb(U)[5]Cb(U)[4]Cb(U)[3]Cb(U)[2]Cb(U)[1]Cb(U)[0]TX1P/N V-by-One® HS lane1

Table 7.

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Y[7] (1st)Y[6] (1st)Y[5] (1st)Y[4] (1st)Y[3] (1st)Y[2] (1st)Y[1] (1st)Y[0] (1st)
0
0
0
0
0
0
0
0
Y[7] (2nd)Y[6] (2nd)Y[5] (2nd)Y[4] (2nd)Y[3] (2nd)Y[2] (2nd)Y[1] (2nd)Y[0] (2nd)Y[7](2nd)
Y[6](2nd)
Y[5](2nd)
Y[4](2nd)
Y[3](2nd)
Y[2](2nd)
Y[1](2nd)
Y[0](2nd)
0
0
0
0
0
0
0
0
Y[7](1st)
Y[6](1st)
Y[5](1st)
Y[4](1st)
Y[3](1st)
Y[2](1st)
Y[1](1st)
Y[0](1st)

0
0
0
0
0
0
0
0
Y[7](2nd)
Y[6](2nd)
Y[5](2nd)
Y[4](2nd)
Y[3](2nd)
Y[2](2nd)
Y[1](2nd)
Y[0](2nd)
Cr(V)[7]Cr(V)[6]Cr(V)[5]Cr(V)[4]Cr(V)[3]Cr(V)[2]Cr(V)[1]Cr(V)[0]default V-by-One®HS Byte Mode

Format Name

RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)
0
0
0
0
0
0
0
0
RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)

3
3
RAW8
Map4
RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)0000RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)
0
0
0
0

1
0
4
YUV422HF
Map1
Y[7](1st)
Y[6](1st)
Y[5](1st)
Y[4](1st)
Y[3](1st)
Y[2](1st)
Y[1](1st)
Y[0](1st)
Cb(U)[7](1st)Cb(U)[6](1st)Cb(U)[5](1st)Cb(U)[4](1st)Cb(U)[3](1st)Cb(U)[2](1st)Cb(U)[1](1st)Cb(U)[0](1st)Y[7] (3rd)Y[6] (3rd)Y[5] (3rd)Y[4] (3rd)Y[3] (3rd)Y[2] (3rd)Y[1] (3rd)Y[0] (3rd)Cb(U)[7] (3rd)Cb(U)[6] (3rd)Cb(U)[5] (3rd)Cb(U)[4] (3rd)Cb(U)[3] (3rd)Cb(U)[2] (3rd)Cb(U)[1] (3rd)Cb(U)[0] (3rd)1
4
YUV422HF
Map2
Cb(U)[7](1st)Cb(U)[6](1st)Cb(U)[5](1st)Cb(U)[4](1st)Cb(U)[3](1st)Cb(U)[2](1st)Cb(U)[1](1st)Cb(U)[0](1st)Y[7](1st)
Y[6](1st)
Y[5](1st)
Y[4](1st)
Y[3](1st)
Y[2](1st)
Y[1](1st)
Y[0](1st)
Cb(U)[7] (3rd)Cb(U)[6] (3rd)Cb(U)[5] (3rd)Cb(U)[4] (3rd)Cb(U)[3] (3rd)Cb(U)[2] (3rd)Cb(U)[1] (3rd)Cb(U)[0] (3rd)Y[7] (3rd)Y[6] (3rd)Y[5] (3rd)Y[4] (3rd)Y[3] (3rd)Y[2] (3rd)Y[1] (3rd)Y[0] (3rd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)
0
0
0
0
0
0
0
0
RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)0000RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)0000Y[7] (2nd)Y[6] (2nd)Y[5] (2nd)Y[4] (2nd)Y[3] (2nd)Y[2] (2nd)Y[1] (2nd)Y[0] (2nd)
Cr(V)[7] (2nd)
Cr(V)[6] (2nd)
Cr(V)[5] (2nd)
Cr(V)[4] (2nd)
Cr(V)[3] (2nd)
Cr(V)[2] (2nd)
Cr(V)[1] (2nd)
Cr(V)[0] (2nd)Y[7] (4th)Y[6] (4th)Y[5] (4th)Y[4] (4th)Y[3] (4th)Y[2] (4th)Y[1] (4th)Y[0] (4th)Cr(V)[7] (4th)Cr(V)[6] (4th)Cr(V)[5] (4th)Cr(V)[4] (4th)Cr(V)[3] (4th)Cr(V)[2] (4th)Cr(V)[1] (4th)Cr(V)[0] (4th)Cr(V)[7] (2nd)
Cr(V)[6] (2nd)
Cr(V)[5] (2nd)
Cr(V)[4] (2nd)
Cr(V)[3] (2nd)
Cr(V)[2] (2nd)
Cr(V)[1] (2nd)
Cr(V)[0] (2nd)Y[7] (2nd)Y[6] (2nd)Y[5] (2nd)Y[4] (2nd)Y[3] (2nd)Y[2] (2nd)Y[1] (2nd)Y[0] (2nd)
Cr(V)[7] (4th)Cr(V)[6] (4th)Cr(V)[5] (4th)Cr(V)[4] (4th)Cr(V)[3] (4th)Cr(V)[2] (4th)Cr(V)[1] (4th)Cr(V)[0] (4th)Y[7] (4th)Y[6] (4th)Y[5] (4th)Y[4] (4th)Y[3] (4th)Y[2] (4th)Y[1] (4th)Y[0] (4th)

0
3
RAW8

THine Electronics, Inc.

Copyright©2023 THine Electronics, Inc.
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THCV241A_Rev.2.11_E

1
1
2
4

2
3

3
0
0
3

1
0
4

4
0
0
3

RAW8HF

RGB888

RGB565

RGB565HF

RAW10

TX0P/N V-by-One® HS lane0

R_OUTPUT_FMT
R_HFSEL
R_BITMAP_SEL

V-by-One® HS 2lane output data mapping format 2/3

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[7] (6th)RAW[6] (6th)RAW[5] (6th)RAW[4] (6th)RAW[3] (6th)RAW[2] (6th)RAW[1] (6th)RAW[0] (6th)RAW[7] (5th)RAW[6] (5th)RAW[5] (5th)RAW[4] (5th)RAW[3] (5th)RAW[2] (5th)RAW[1] (5th)RAW[0] (5th)B[7] (1st)B[6] (1st)B[5] (1st)B[4] (1st)B[3] (1st)B[2] (1st)B[1] (1st)B[0] (1st)G[7] (1st)G[6] (1st)G[5] (1st)G[4] (1st)G[3] (1st)G[2] (1st)G[1] (1st)G[0] (1st)R[7] (1st)R[6] (1st)R[5] (1st)R[4] (1st)R[3] (1st)R[2] (1st)R[1] (1st)R[0] (1st)B[4] (1st)B[3] (1st)B[2] (1st)B[1] (1st)B[0] (1st)000G[5] (1st)G[4] (1st)G[3] (1st)G[2] (1st)G[1] (1st)G[0] (1st)00R[4] (1st)R[3] (1st)R[2] (1st)R[1] (1st)R[0] (1st)000B[4] (1st)B[3] (1st)B[2] (1st)B[1] (1st)B[0] (1st)G[5] (1st)G[4] (1st)G[3] (1st)G[2] (1st)G[1] (1st)G[0] (1st)R[4] (1st)R[3] (1st)R[2] (1st)R[1] (1st)R[0] (1st)B[4] (3rd)B[3] (3rd)B[2] (3rd)B[1] (3rd)B[0] (3rd)G[5] (3rd)G[4] (3rd)G[3] (3rd)G[2] (3rd)G[1] (3rd)G[0] (3rd)R[4] (3rd)R[3] (3rd)R[2] (3rd)R[1] (3rd)R[0] (3rd)

TX1P/N V-by-One® HS lane1

Table 8.

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)RAW[7] (8th)RAW[6] (8th)RAW[5] (8th)RAW[4] (8th)RAW[3] (8th)RAW[2] (8th)RAW[1] (8th)RAW[0] (8th)RAW[7] (7th)RAW[6] (7th)RAW[5] (7th)RAW[4] (7th)RAW[3] (7th)RAW[2] (7th)RAW[1] (7th)RAW[0] (7th)B[7] (2nd)B[6] (2nd)B[5] (2nd)B[4] (2nd)B[3] (2nd)B[2] (2nd)B[1] (2nd)B[0] (2nd)G[7] (2nd)G[6] (2nd)G[5] (2nd)G[4] (2nd)G[3] (2nd)G[2] (2nd)G[1] (2nd)G[0] (2nd)R[7] (2nd)R[6] (2nd)R[5] (2nd)R[4] (2nd)R[3] (2nd)R[2] (2nd)R[1] (2nd)R[0] (2nd)B[4] (2nd)B[3] (2nd)B[2] (2nd)B[1] (2nd)B[0] (2nd)000G[5] (2nd)G[4] (2nd)G[3] (2nd)G[2] (2nd)G[1] (2nd)G[0] (2nd)00R[4] (2nd)R[3] (2nd)R[2] (2nd)R[1] (2nd)R[0] (2nd)000B[4] (2nd)B[3] (2nd)B[2] (2nd)B[1] (2nd)B[0] (2nd)G[5] (2nd)G[4] (2nd)G[3] (2nd)G[2] (2nd)G[1] (2nd)G[0] (2nd)R[4] (2nd)R[3] (2nd)R[2] (2nd)R[1] (2nd)R[0] (2nd)B[4] (4th)B[3] (4th)B[2] (4th)B[1] (4th)B[0] (4th)G[5] (4th)G[4] (4th)G[3] (4th)G[2] (4th)G[1] (4th)G[0] (4th)R[4] (4th)R[3] (4th)R[2] (4th)R[1] (4th)R[0] (4th)default V-by-One®HS Byte Mode

Format Name

0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[1] (1st)RAW[0] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)1
0
4
RAW10HF
Map1
0
0
0
0
0
0
RAW[1] (1st)RAW[0] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)
0
0
0
0
0
0
RAW[1] (3rd)RAW[0] (3rd)RAW[9] (3rd)RAW[8] (3rd)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)2
4
RAW10HF
Map3
0
0
0
0
RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)
0
0
0
0
0
0
RAW[9] (3rd)RAW[8] (3rd)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[1] (2nd)RAW[0] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)

0
0
0
0
0
0
RAW[1] (2nd)RAW[0] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)
0
0
0
0
0
0
RAW[1] (4th)RAW[0] (4th)RAW[9] (4th)RAW[8] (4th)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)0000RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)
0
0
0
0
0
0
RAW[9] (4th)RAW[8] (4th)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)00THine Electronics, Inc.

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Table 9.

TX0P/N V-by-One® HS lane0

5
0
0
3

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]

0
0
0
0
0
0
0
0
0
0
0
0
RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)1
04
RAW12HF
Map1
0
0
0
0
RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)0000RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)RAW[11] (3rd)RAW[10] (3rd)RAW[9] (3rd)RAW[8] (3rd)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)

TX1P/N V-by-One® HS lane1

R_OUTPUT_FMT
R_HFSEL
R_BITMAP_SEL

V-by-One® HS 2lane output data mapping format 3/3

V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]

0
0
0
0
0
0
0
0
0
0
0
0
RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)0000RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)0000RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)RAW[11] (4th)RAW[10] (4th)RAW[9] (4th)RAW[8] (4th)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)def ault V-by-One®HS Byte Mode

Format Name

RAW12

1
4
RAW12HF
Map2
0
0
0
0
RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)0000RAW[11] (3rd)RAW[10] (3rd)RAW[9] (3rd)RAW[8] (3rd)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)6
0
3
RAW10HF2
Map1
00
RAW[1] (1st)RAW[0] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)00RAW[1] (3rd)RAW[0] (3rd)RAW[9] (3rd)RAW[8] (3rd)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)2
3
RAW10HF2
Map3
RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)00RAW[9] (3rd)RAW[8] (3rd)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)
0
0

7
0
3
RAW12HF2
Map1
RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)RAW[11] (3rd)RAW[10] (3rd)RAW[9] (3rd)RAW[8] (3rd)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)1
3
RAW12HF2
Map2
RAW[11] (1st)RAW[10] (1st)RAW[9] (1st)RAW[8] (1st)RAW[7] (1st)RAW[6] (1st)RAW[5] (1st)RAW[4] (1st)RAW[3] (1st)RAW[2] (1st)RAW[1] (1st)RAW[0] (1st)RAW[11] (3rd)RAW[10] (3rd)RAW[9] (3rd)RAW[8] (3rd)RAW[7] (3rd)RAW[6] (3rd)RAW[5] (3rd)RAW[4] (3rd)RAW[3] (3rd)RAW[2] (3rd)RAW[1] (3rd)RAW[0] (3rd)0000RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)0000RAW[11] (4th)RAW[10] (4th)RAW[9] (4th)RAW[8] (4th)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)00RAW[1] (2nd)RAW[0] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)00RAW[1] (4th)RAW[0] (4th)RAW[9] (4th)RAW[8] (4th)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)00RAW[9] (4th)RAW[8] (4th)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)00RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)RAW[11] (4th)RAW[10] (4th)RAW[9] (4th)RAW[8] (4th)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[11] (2nd)RAW[10] (2nd)RAW[9] (2nd)RAW[8] (2nd)RAW[7] (2nd)RAW[6] (2nd)RAW[5] (2nd)RAW[4] (2nd)RAW[3] (2nd)RAW[2] (2nd)RAW[1] (2nd)RAW[0] (2nd)RAW[11] (4th)RAW[10] (4th)RAW[9] (4th)RAW[8] (4th)RAW[7] (4th)RAW[6] (4th)RAW[5] (4th)RAW[4] (4th)RAW[3] (4th)RAW[2] (4th)RAW[1] (4th)RAW[0] (4th)THine Electronics, Inc.

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6.5.3 V-by-One® HS output Byte mode
Setting of V-by-One® HS output Byte mode follows format setting or register control.
When V-by-One® HS Self Pattern Generator (BIST) is active, R_BISTEN=1:Enable, Byte mode is 3Byte
fixed.
Table 10.
Addr(h)Bits

RegisterV-by-One® HS output Byte mode setting
w idthR/W

0x1036[0]

R_COL_SEL

1

R/W

0x1037[5:4]

R_COL_MAN[1:0]

2

R/W

Description

Default

V-by-One® HS COL (COLor depth) Byte mode setting method
0:AUTO (COL_FMT defined by output format setting)
1:Manual (R_COL_MAN)
V-by-One® HS Manual Color Depth Select00 : Reserved
01 : 8bit (3Byte mode)
10 : 10bit (4Byte mode)
11 : Reserved

1'h0

2'h2

6.5.4 V-by-One® HS output Distribution mode
Output of V-by-One® HS lane0 is duplicated and distributed to lane1 output. When Distribution mode is
Enabled, R_HTPDN_SEL, R_LOCKN0_SEL and R_LOCKN1_SEL are supposed to be set properly.

Addr(h)0x1053Bits[0]

Table 11.

V-by-One® HS output Distribution mode setting

Registerw idthR_DIST_EN

1

R/W

Description

Default

R/W

V-by-One® HS Distribution mode Enable
0:Disable
1:Enable

1'h0

6.5.5 V-by-One® HS Low Radiation Emission or High Immunity Resistance mode
V-by-One® HS Low Radiation Emission and High Immunity Resistance mode are available.
Immunity resistance strength is HS (2’b11) > HS (2’b10).
Radiated emission level is HS (2’b11) > HS (2’b10).

Table 12.
Addr(h)0x101B

Bits

[5:4]

V-by-One® HS Low Radiation Emission or High Immunity Resistance mode setting
Registerw idthR_NHSEL

2

R/W

R/W

Description

Default

V-by-One® HS setting
00 : Reserved
01 : Reserved
10 : V-by-One® HS standard Low Radiation Emission mode
11 : V-by-One® HS standard High Immunity Resistance mode

2'h3

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6.5.6 V-by-One® HS output Odd/Even swap
V-by-One® HS Odd/Even pixel assignment to output lane is adjustable.

Addr(h)0x1052Bits[0]

Table 13.

V-by-One® HS output Odd/Even swap setting

Registerw idth

R_ML_OE_SWAP

1

R/W
R/W

Description
V-by-One® HS 1st Pixel Start Timing Select0:1st pixel assign on lane0
1:1st pixel assign on lane1

Default
1'h0

6.5.7 V-by-One® HS output Drivability
V-by-One® HS driver emphasis and strength controls are adjustable.
Table 14.
Addr(h)Bits

RegisterV-by-One® HS output Drivability setting
w idthR/W

0x1020[7:6]

R_ML0_PRE

2

R/W

0x1020[5:4]

R_ML1_PRE

2

R/W

0x1020[3:2]

R_ML0_DRV

2

R/W

0x1020[1:0]

R_ML1_DRV

2

R/W

Description[VbyOne Transmitter] Pre-Emphasis
・ w hen R_ML0_DRV=0
00:0%
10:100%・ w hen R_ML0_DRV=1
00:0%
01:50%[VbyOne Transmitter] Pre-Emphasis
・ w hen R_ML1_DRV=0
00:0%
10:100%・ w hen R_ML1_DRV=1
00:0%
01:50%[VbyOne Transmitter] Drive Strength Select00: VTOD=200mV
01: VTOD=300mV
10: VTOD=400mV[VbyOne Transmitter] Drive Strength Select00: VTOD=200mV
01: VTOD=300mV
10: VTOD=400mVDefault

2'h0

2'h0

2'h2

2'h2

6.5.8 V-by-One® HS output Low Frequency mode
V-by-One® HS Low Frequency Mode is available. For usage of Low Frequency mode, counterpart V-by-One®
receiver must have installed Low Frequency mode format decoder like THCV236-Q.
Table 15.
Addr(h)0x101B

Bits[0]RegisterV-by-One® HS Low Frequency Mode setting
w idthR_LFQEN

1

R/W
R/W

Description
V-by-One® HS Low FeqModeEnable
0:Normal
1:Low Frequency Mode

Default
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6.5.9 Target Pixel clock
Target pixel clock for transmission is defined by a formula below.
Relationship between used packet and byte mode packet transfer potential is determined by output format(from Table 4) and whether Auto or Manual Byte-mode setting is used or not in Byte-mode setting (Table 10).

[dmp] = MIPI Data-rate[nmp] = MIPI lane number[bmvx1] = V-by-One® HS Byte Mode[nvx1] = V-by-One® HS lane number[PCLK.target] = Pixel clock target for V-by-One® HS per lane = [F(target)]Total pixel data-rate = [dmp] x [nmp]= [PCLK.target] x [bmvx1] x8 xUsed packet in output format
Byte mode packet total

x [nvx1][dmp] x [nmp][PCLK.target] =[bmvx1] x8 x

6.6

Used packet in output format
Byte mode packet total= [F(target)]x [nvx1]

Blanking period restriction under low MIPI data-rate environment

First of all, horizontal blanking period must meet minimum required length as MIPI standard defines to change
MIPI data lane from Low Power mode to High Speed mode and from High Speed mode to Low Power mode.
In addition for THCV241A, when MIPI data-rate per lane is slower than 160Mbps, horizontal blanking period
length must meet below rule.

Another alternative is simply to use 160Mbps and higher MIPI data-rate because cases to use below 160Mbps
must be the cases of [nmp]=4 so that MIPI data-rate can be arranged to be higher by using [nmp]=1 or 2
configuration.

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THCV241A_Rev.2.11_E

6.7

PLL setting

PLL setting is required. For manual setting, R_PLL_SET_MODE is supposed to be set 1 (Manual mode) fromdefault value 0. PLL Manual mode setting set R_PLL_SETTING[47:0] is related with CKI frequency.
PLL Configuration
F(CKI)
10-40MHzF(VCO)
500-1300MHzPFD

1st Output Divider
x 1/OutDiv1
1-7

VCO

2nd Output Divider
x 1/OutDiv2
1-7

F(Out)
10-133.3MHz

FeedBack Divider
x 1/FBDiv
20-130Figure 5. Reference clock supply basic method

PLL_SETTING[47:0] must be selected proper to meet below constraints.
Table 16.
symbolF(CKI)FBDiv
OutDiv1
OutDiv2
F(VCO)
F(OUT)

DF

discription
CKI input frequency
FeedBack Divider value
1st Output Divider value (OutDiv1 must be >= OutDiv2)
2nd Output Divider value (OutDiv1 must be >= OutDiv2)
VCO frequency
PLL output pixel clock frequency

Allow ed error betw een F(target) vs F(OUT)

PLL constraints tablecondition
Hactive=< 1280pixels
and [dmp]x[nmp] < 500Mbps
1280 <Hactive=< 1920pixels
and [dmp]x[nmp] < 800Mbps
1920 <Hactive=< 3840pixels
and [dmp]x[nmp] <1500Mbps
otherw ise

min
10
20
1
1
500
10

typ
-

max
40
130
7
7
1300
133.3

unit
MHz
MHz
MHz

| R_SPREAD|

-

8

%

0

0

8

%

Pixel clock frequency made by PLL is calculated as below.

Actual Pixel clock, F(OUT) frequency must be equal or greater than ideal target Pixel clock, F(target) by 8%
accuracy as below formula for most cases.

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THCV241A_Rev.2.11_E

When transmitted camera image format horizontal active is rather large and total pixel data-rate is rather slow as
described in previous table condition, minimum allowed F(OUT) setting is not equal to F(target) if Spread
Spectrum function is activated. F is supposed to be more than absolute value of applied SSCG modulation rate,|R_SPREAD|, under the condition specified on PLL constraints table.

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THCV241A_Rev.2.11_E

Table 17.
Addr(h)Bits

Registerw idthR/W

0x100F[0]

R_PLL_SET_MODE

1

R/W

0x10110x10120x10130x10140x10150x10150x10150x10150x1016

[7:0]
[7:0]
[7:0]
[7:0]
[7]
[6:4]
[3]
[2:0]
[7:0]

R_PLL_SETTING[47:40]
R_PLL_SETTING[39:32]
R_PLL_SETTING[31:24]
R_PLL_SETTING[23:16]
R_PLL_SETTING[15]R_PLL_SETTING[14:12]
R_PLL_SETTING[11]R_PLL_SETTING[10:8]
R_PLL_SETTING[7:0]

8
8
8
8
1
3
1
3
8

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

PLL setting
Description
PLL setting mode
0:PLL Auto setting mode
1:PLL Manual setting mode
PLL setting value, Feedback Divider value (integer part)
PLL setting value, Feedback Divider value (decimal part MSB)PLL setting value, Feedback Divider value (decimal part)
PLL setting value, Feedback Divider value (decimal part LSB)
PLL setting value
PLL setting value, OutDiv1 (OutDiv1 must be >= OutDiv2)
PLL setting value
PLL setting value, OutDiv2 (OutDiv1 must be >= OutDiv2)
PLL setting value, Reserved (must be set to 8'h01)

Default
1'h0
8'h00
8'h00
8'h00
8'h00
1'h0
3'h0
1'h0
3'h0
8'h00

Below Table 18 is Look Up Table for typical cases.
Table 18.

PLL setting Look Up Table

index condition1
720p30fps RAW
2
3
720p30fps YUV422
4
720p60fps RAW
51080p30fps RAW6
720p60fps YUV422
71080p30fps YUV422
8
720p120fps RAW
91080p60fps RAW
10
720p120fps YUV422
111080p60fps YUV422
121080p120fps RAW
13
141080p120fps YUV422
15720p30fps RAW
16

input

output594Mbps x1lane

1lane MPRF

600Mbps x1lane

1lane MPRF

445.5Mbps x2lane

1lane MPRF

594Mbps x2lane

1lane MPRF

891Mbps x2lane

1lane MPRF

594Mbps x4lane

1lane MPRF

891Mbps x4lane

2lane MPRF

1200Mbps x4lane

2lane MPRF

594Mbps x1lane

1lane RAW12HF Map2

17720p30fps YUV422

600Mbps x1lane

1lane YUV422 Map1(4Byte)
forced 4Byte

18
19
20
21
22
23
24
25
26
27
28

720p60fps RAW
1080p30fps RAW
720p60fps YUV422
1080p30fps YUV422
720p120fps RAW
1080p60fps RAW
720p120fps YUV422
1080p60fps YUV422

445.5Mbps x2lane

1lane RAW12HF Map2

594Mbps x2lane

1lane YUV422 Map1(4Byte)
forced 4Byte

891Mbps x2lane

1lane RAW12HF Map2

594Mbps x4lane

1lane YUV422HF Map1

1080p120fps RAW

891Mbps x4lane

2lane RAW12HF Map2

1080p120fps YUV422

1200Mbps x4lane

2lane YUV422HF Map1

f_CKI (MHz)27
37.12524
27
37.12527
37.12527
37.12527
37.12527
37.12524
27
37.125

PLL[47:40]
0x18
0x15
0x1C
0x25
0x1B
0x21
0x18
0x21
0x18
0x2C
0x20
0x21
0x18
0x32
0x21
0x18

PLL[39:32]
0xC0
0x00
0x20
0x20
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[31:24]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[23:16]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[15:8]
0x66
0x76
0x66
0x66
0x66
0x64
0x64
0x44
0x44
0x44
0x44
0x44
0x44
0x44
0x66
0x66

PLL[7:0]
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01

24

0x19

0x00

0x00

0x00

0x44

0x01

27
37.12527
37.12527
37.12527
37.12527
37.125
24

0x21
0x18
0x2C
0x20
0x2C
0x20
0x2C
0x20
0x2C
0x20
0x32

0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

0x64
0x64
0x44
0x44
0x44
0x44
0x44
0x44
0x44
0x44
0x44

0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01

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THCV241A_Rev.2.11_E

6.8

PLL Auto setting function

PLL auto setting function is available in case all the following conditions are met.


V-by-One® HS output format setting (Address 0x1001) is MPRF.

F(CKI) is 37.125MHz or 27MHz or 24MHz.



MIPI input data-rate is equal to the integral multiple of F(CKI)

Under PLL auto setting function operation, it is sufficient only to control below resistors. No control on
R_PLL_SETTING[47:0] is required.
Table 19.

PLL Auto setting function control Resistors

Addr(h)Bits

Registerw idthR/W

0x100F[0]

R_PLL_SET_MODE

1

R/W

0x100E[7:6]

R_CKI_FREQ

2

R/W

0x100E[5:0]

R_MIPI_MULT

6R/W

0x1000[0]

R_VX1_LANE

1

R/W

0x1001[6:4]

R_OUTPUT_FMT

3

R/W

0x10020x102D[5][1:0]

R_HFSEL
R_RX_LANE_SEL_EN

1
2

R/W
R/W

Description
PLL setting mode
0:PLL Auto setting mode
1:PLL Manual setting mode
PLL Auto setting input frequency choice
2'h0: Reserved
2'h1: 37.125MHz
2'h2: 27MHz
2'h3: 24MHz
PLL Auto setting multiplying ratio MIPI data-rate vs. F(CKI)
Below formula must be met to application condition.
MIPI Data-rate = F(CKI) *(R_MIPI_MULT+1)
See other Table for detail description
Setting value 000:MPRF is required for PLL Auto setting function.
See other Table for detail description
See other Table for detail description
See other Table for detail description

Default
1'h0

2'h0

6'hF
1'h1
3'h0
1'h0
2'h3

If above PLL Auto setting control values are invalid and unmatched to application condition, C_PLL_SET_NG
indicator is asserted.
Table 20.

PLL Auto setting control invalid Indicator

Addr(h)Bits

Registerw idthR/W

0x112F[0]

C_PLL_SET_NG

1

R

Description
PLL Auto Setting control invalid indicator
0: PLL Auto Setting control valid or PLL Manual setting mode
1: PLL Auto Setting control invalid

Default-

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THCV241A_Rev.2.11_E

6.9

V-by-One® HS output data-rate

V-by-One® HS output data-rate is made of actual Pixel clock frequency.

At Low Frequency Mode, Data-rate is doubled.

Supported Data-rate is from 400Mbps to 4Gbps.

6.10 V-by-One® HS output Spread Spectrum
Spread Spectrum Clock Generation (SSCG) modulation is available to apply on V-by-One® HS output.

Addr(h)Bits

Table 21.

V-by-One® HS output Spread Spectrum settings

Registerw idthR/W

0x1010[7:4]

R_DIVVAL

4

R/W

0x1019[3:0]

R_SPREAD

4

R/W

0x101A[0]

R_DISABLE_SSCG

1

R/W

Description
SSCG modulation frequency setting
fmod = F(CKI) / (128*R_DIVVAL)
SSCG modulation rate setting
4'h0 : modulation rate =0,
4'h1 : modulation rate =+/-0.1%,
4'h2 : modulation rate =+/-0.2%,…,
4'h5 : modulation rate =+/-0.5%,…,
4'hF : modulation rate =+/-1.5%
SSCG modulation Enable/Disable setting
0:Enable
1:Disable

Default
4'h0

4'h3

1'h1

SSCG modulation frequency divider setting values, R_DIVVAL on Address 0x1010, to meet V-by-One® HS
standard 30kHz +/-0.5% are exemplified below.
Table 22.

V-by-One® HS output SSCG R_DIVVAL setting examples(MHz)
F(CKI)
37.12527
24(hex.)
R_DIVVAL
4'hC(0xC)
4'h8(0x8)
4'h8(0x8)(dec.)
R_DIVVAL
12
8
8

(kHz)
fmod
24.2
26.4
23.4

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THCV241A_Rev.2.11_E

6.11 V-by-One® HS CRC
V-by-One® HS transmission packet payload fault or error can be detected with CRC. THCV241A generates
and sends check value to receiver. For usage of CRC function, the counterpart V-by-One® receiver must haveinstalled CRC monitor like THCV242.
Table 23.

V-by-One® HS CRC setting

Addr(h)Bits

Registerw idthR/W

0x1054[0]

R_CRC_OFF

1

R/W

Description
V-by-One® HS CRC generator ON/OFF (ON default)
0:CRC output ON
1:CRC output OFF

Default
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THCV241A_Rev.2.11_E

6.12 MIPI Packet Header V-by-One® HS output bridge mode
MIPI PH(Packet Header) can be bridge to V-by-One® HS output following selected schemes.
“R_PHMODE=2’b01” setting on THCV236-Q connection is only supported where HFSEL=0 setting is applied
on THCV236-Q.

Table 24.
Addr(h)0x1001

Bits

[1:0]

Register

R_PHMODE

V-by-One® HS output MIPI Packet Header bridge setting
w idth2

R/W

Description

Default

V-by-One® HS output MIPI PH(Packet Header) timing setting
00:PH in normal data packet just after DE rise (THCV242-Q
default)
01:PH in CTL packet of blanking period till 1pixel before DE rise
10,11:no PH

R/W

2'h0

Pixel Clock@R_PHMODE = 2'b00
DE
DATA

PH

DATA

@R_PHMODE = 2'b01
DE
DATA

PH1

PH2

PH3 1pixel

DATA@R_PHMODE = 2'b10/11
DE
DATA

DATA

Figure 6. MIPI Packet Header V-by-One® HS output bridge timing alternative

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H
H
H
H
H
H
V
V

H
H
H
H
H
H
V
V

V

V

V

V

V

V

V

V

V

V

DID0

DID1

DID2

DID3

DID0

DID1

DID2

DID3

DID4

DID5

THCV236 D[0]THCV236 D[1]THCV236 D[2]THCV236 D[3]THCV236 D[4]THCV236 D[5]THCV236 D[6]V-by-One®HS_D[0]V-by-One®HS_D[1]V-by-One®HS_D[2]V-by-One®HS_D[3]V-by-One®HS_D[4]V-by-One®HS_D[5]V-by-One®HS_D[6]V-by-One®HS_D[7]

ECC0

ECC1

ECC2

ECC3

ECC4

ECC5

ECC6

ECC7

WC8

WC9

29

V

V

V

DID4

DID5

DID6

THCV236 D[7]V-by-One®HS_D[8]

WC10

28

V

V

V

V

DID6

DID7

THCV236 D[8]V-by-One®HS_D[9]

WC11

27

V

V

V

V

DID7

WC8

THCV236 D[9]V-by-One®HS_D[10]

WC12

26

V

V

V

V

WC8

WC9

THCV236 D[10]V-by-One®HS_D[11]

WC13

25

V

V

V

V

H

WC9

WC10

THCV236 D[11]V-by-One®HS_D[12]

WC14

WC15

24

V

V

H

H

WC10

WC11

THCV236 D[12]V-by-One®HS_D[13]V-by-One®HS_D[14]

WC0

23

V

H

H

H

WC11

WC12

THCV236 D[13]THCV236 D[14]V-by-One®HS_D[15]

22

H

H

H

H

WC12

WC13

WC14

THCV236 D[15]

21

H

H

H

H

WC13

WC14

WC0
WC15

WC1

WC2

20

H

H

H

H

H

WC0
WC15

V-by-One®HS_D[16]*V-by-One®HS_D[17]*

19

H

H

H

H

H

THCV236 D[16]*

THCV236 D[17]*

WC3

WC4

18

H

H

H

H

WC1

WC2

V-by-One®HS_D[18]*V-by-One®HS_D[19]*

17

H

H

H

DID0

WC1

WC2

THCV236 D[18]*

THCV236 D[19]*

WC5

WC6

16

V

H

H

H

DID0

DID1

WC3

WC4

V-by-One®HS_D[20]*V-by-One®HS_D[21]*

15

V

H

H

WC8

WC8

DID1

DID2

WC3

WC4

THCV236 D[20]*

THCV236 D[21]*

WC7

DID0

14

V

WC0

WC0

WC9

WC9

DID2

DID3

WC5

WC6

V-by-One®HS_D[22]*V-by-One®HS_D[23]*

DID1

13

V

WC1

WC1

WC10

WC10

DID3

DID4

WC5

WC6

THCV236 D[22]*

THCV236 D[23]*V-by-One®HS_D[24]*

DID2

DID3

DID4

DID5

DID6

12

V

WC2

WC2

WC11

WC11

DID4

DID5

WC7

THCV236 D[24]*V-by-One®HS_D[25]*V-by-One®HS_D[26]*V-by-One®HS_D[27]*V-by-One®HS_D[28]*V-by-One®HS_D[29]*

DID7

11

V

WC3

WC3

WC12

WC12

DID5

DID6

WC7

ECC0

THCV236 D[25]*

THCV236 D[26]*

THCV236 D[27]*

THCV236 D[28]*

THCV236 D[29]*V-by-One®HS_D[30]*

10

V

WC4

WC4

WC13

WC13

DID6

DID7

-

ECC1

ECC2

ECC3

ECC4

ECC5

THCV236 D[30]**CTL packet
V-by-One®HS_D[31]*

9

V

WC5

WC5

WC14

WC14

DID7

0

-

-

-

-

-

ECC6

THCV236 D[31]*

8

V

WC6

WC6

WC15

WC15

-

0

0

0

0

0

-

ECC7

7

V

WC7

WC7

0

-

-

-

-

-

-

0

-

THCV236
HFSEL=0

6

V

0

-

0

0

0

0

0

-

0

4byte

5

-

-

-

-

-

0

-

PH

4

V

0

-

0

-

0

0

-

-

0

3byte

3

0

0

-

-

4byte

PH1
3byte

2

-

0

-

4byte

PH2
3byte
MIPI PH
0
1

-

4byte

PH3
3byte

THCV241A_Rev.2.11_E

30
31

Vx1 PH

Figure 7. MIPI Packet Header V-by-One® HS output bridge bit mapping

6.13 MIPI Virtual Channel bridge

When MIPI PH(Packet Header) is bridged to V-by-One® HS output with described schemes above, MIPI

Virtual Channel information in PH is bridged to V-by-One® HS at the same time. Virtual Channel is supported.

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THCV241A_Rev.2.11_E

6.14 V-by-One® HS VSYNC generation
Setting of V-by-One® HS VSYNC output is configurable by 2-wire access on internal register.
Internally generated VSYNC (R_VS_MODE=1) follows Figure 8.
Table 25.
Addr(h)Bits

RegisterV-by-One® HS output VSYNC setting
w idthR/W

0x1002[3:2]

R_FS_FE_SYNCEN

2

R/W

0x1004[1]

R_VSYNC_POL

1

R/W

0x1007[3]

R_VS_MODE

1

R/W

0x1007[2:0]

R_VS_OFFSET

3

R/W

0x1008[7:0]

R_VS_WIDTH_PIX

8

R/W

0x1009[4:2]

R_VS_WIDTH_LINE

3

R/W

Description

Default

V-by-One® HS Vsync generation Enable at MIPI FS/FE(active only w hen R_VS_MODE=0)00:Vsync pulse at both FS and FE (THCV242-Q default)
01:Vsync pulse at FS only
10:Vsync pulse at FE only
11:no Vsync pulse at FS nor FE
V-by-One® HS Vsync polarity
0:High pulse (High active) (THCV242-Q default)
1:Low pulse (Low active)
V-by-One® HS VSYNC output timing mode
0:MIPI FS/FE timing direct use mode (THCV242-Q default)
1:internally generated timing mode
V-by-One® HS internally generated VSYNC offset
offset from FE = calculatedVS-HTOTAL x R_VS_OFFSET
V-by-One® HS internally generated Htotal setting
Generated Htotal:calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16
V-by-One® HS internally generated VSYNC pulse w idth
VSYNC pulse w idth = calculatedVS-HTOTAL x
R_VS_WIDTH_LINE

2'h0

1'h0

1'h0
3'h0
8'h00

3'h0

V-by-One® HS
PCLK

MIPI FE

Internal VSYNC
generation counter

Internally generated
V-by-One® HS VSYNC

FE

offset LINE 1

offset LINE 2

offset LINE m

VSYNC LINE 1

VSYNC LINE 2

VSYNC LINE n( For example, R_VSYNC_POL=0 )calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16 x PCLK

calculatedVS-HTOTAL x R_VS_OFFSET(=m)

calculatedVS-HTOTAL x R_VS_WIDTH_LINE(=n)

Figure 8. Internally generated VSYNC

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6.15 V-by-One® HS HSYNC generation
Setting of V-by-One® HS HSYNC output is configurable by 2-wire access on internal register.
Internally generated HSYNC in Vertical active period (R_HS_MODE=10/11) follows Figure 9.
Internally generated HSYNC in Vertical blanking period (R_HS_VB_EN=10/11) follows Figure 10.
Table 26.
Addr(h)Bits

RegisterV-by-One® HS output HSYNC setting
w idthR/W

0x1002[1:0]

R_LS_LE_SYNCEN

2

R/W

0x1004[0]

R_HSYNC_POL

1

R/W

0x1009[1:0]

R_HS_MODE

2

R/W

0x100A
0x100B

[4:0]
[7:0]

R_VACT_LINE[12:8]
R_VACT_LINE[7:0]

5
8

R/W
R/W

0x100C[1:0]

R_HS_VB_EN

2

R/W

0x100D[7:0]

R_HS_VB_NUM

8R/W

Description

Default

V-by-One® HS Hsync generation Enable at MIPI LS/LE(active only w hen R_HS_MODE=00, 01)
00:Hsync pulse at both LS and LE (THCV242-Q default)
01:Hsync pulse at LS only
10:Hsync pulse at LE only
11:no Hsync pulse at LS nor LE
V-by-One® HS Hsync polarity
0:High pulse (High active) (THCV242-Q default)
1:Low pulse (Low active)
V-by-One® HS HSYNC output timing mode00, 01:MIPI LS/LE timing direct use mode (THCV242-Q default)
10:internally generated timing mode1
11:internally generated timing mode2
V-by-One® HS Vactive line skip number MSB
V-by-One® HS Vactive line skip number LSB
V-by-One® HS HSYNC output in vertical blanking period setting
00, 01:no HSYNC output in Vblank
10:HSYNC output in Vblank, starting from FE
11:HSYNC output in Vblank, starting from FS, skipping Vactive
V-by-One® HS HSYNC output number in vertical blanking period

2'h0

1'h0

2'h0

5'h00
8'h00
2'h0

8'h00

V-by-One® HS
PCLK

MIPI long packet

MIPI long packet

V-by-One® HS
DE (Data Enable)

Internallygenerated
HSYNC mode1

R_HS_MODE=10 ( For example, R_HSYNC_POL=0 )Internallygenerated
HSYNC mode2

R_HS_MODE=11 ( For example, R_HSYNC_POL=0 )2 x PCLK

2 x PCLK

2 x PCLK

Figure 9. Internally generated HSYNC in Vertical active period

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THCV241A_Rev.2.11_E

R_HS_VB_EN=10
V-by-One® HS
PCLK

MIPI FE

Internal HSYNC
generation counter

FE

LINE 1 in Vblank

LINE 2 in Vblank

LINE k in Vblank( For example, R_HSYNC_POL=0 )( For example, R_HS_MODE=10 )Internally generated
V-by-One® HS HSYNC
calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16 x PCLK

calculatedVS-HTOTAL x R_HS_VB_NUM(=k) in V blanking period

Figure 10. Internally generated HSYNC in Vertical blanking period

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THCV241A_Rev.2.11_E

6.16 MIPI Short Packet V-by-One® HS output bridge mode
MIPI SP (Short Packet) can be bridge to V-by-One® HS output with the following schemes.
MIPI Short Packet V-by-One® HS output bridge mode is only supported when “R_BITMAP_SEL=2’b00(MAP1)” or “R_BITMAP_SEL=2’b11 (MAP4)”.
“R_VS_MODE=1’b0” and “R_FS_FE_SYNCEN=2’b00” setting is required to bridge both MIPI Frame Start
and Frame End Short Packet. “R_VSYNC_POL=1’b0” setting is required to connect THCV242.
THCV236-Q connection is only supported where HFSEL=0 setting is applied on THCV236-Q.

Pixel Clock@R_FS_FE_SYNCEN=00 / R_VS_MODE=0 / R_VSYNC_POL=0
Vsync
BYTE0

V
H

BYTE1
BYTE2

SP1
(FS1)

SP2
(FS2)

V
H
SP3
(FS3)

SP4
(FS4)

SP1
(FE1)

SP2
(FE2)

SP3
(FE3)

SP4
(FE4)

BYTE3

@R_FS_FE_SYNCEN=01 / R_VS_MODE=0 / R_VSYNC_POL=1
Vsync
BYTE0

V
H

BYTE1
BYTE2

SP1
(FS1)

SP2
(FS2)

V
H
SP3
(FS3)

SP4
(FS4)

SP1
(FE1)

SP2
(FE2)

SP3
(FE3)

SP4
(FE4)

BYTE3

Figure 11. MIPI Short Packet V-by-One® HS bridge timing

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ECC2
ECC1
ECC0
H
H
H
H
H
H
H

ECC2
ECC1
ECC0
H
H

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31/68
H
H
H
H
H

V
V
V
V
V

V
V
V
V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]

THCV236 D[4]THCV236 D[3]THCV236 D[2]THCV236 D[1]THCV236 D[0]V-by-One®HS_D[6]
THCV236 D[5]THCV236 D[6]

ECC0

ECC1

ECC2

ECC3

ECC4

ECC5

ECC6

ECC7

DATA8

30

V

V

V

V

V

V

V-by-One®HS_D[7]

THCV236 D[7]

29

V

V

V

V

V

V

V-by-One®HS_D[8]

THCV236 D[8]DATA9DATA10

28

V

V

V

V

V

H
V

V-by-One®HS_D[9]THCV236 D[9]

27

V

V

V

H
V

V-by-One®HS_D[10]THCV236 D[10]DATA11

DATA12

26

V

V

V

H
V

H

H

V-by-One®HS_D[11]THCV236 D[11]

25

V

V

V

H
V

H

H

V-by-One®HS_D[12]THCV236 D[12]DATA13

24

V

H
V

H

H

H

H

V-by-One®HS_D[13]THCV236 D[13]DATA14

23

V

H

H

H

H

H

V-by-One®HS_D[14]THCV236 D[14]DATA15

22

V

H

H

H

H

H

V-by-One®HS_D[15]THCV236 D[15]

DATA0

DATA1

21

H

H

H

H

H

H

V-by-One®HS_D[16]*

THCV236 D[16]*

20

H

H

H

H

H

H

V-by-One®HS_D[17]*

THCV236 D[17]*

DATA2

DATA3

19

H

H

H

H

DID0

DID1

V-by-One®HS_D[18]*

THCV236 D[18]*

18

H

H

H

H

DID0

DID1

V-by-One®HS_D[19]*

THCV236 D[19]*

DATA4

DATA5

17

H

H

H

DATA8

DATA9

DID2

DID3

V-by-One®HS_D[20]*

THCV236 D[20]*

16

H

DATA8

DATA9

DID2

DID3

V-by-One®HS_D[21]*

THCV236 D[21]*

DATA6

DATA7

15

H

DATA0

DATA1

DATA10

DATA11

DID4

DID5

V-by-One®HS_D[22]*

THCV236 D[22]*

14

DATA0

DATA10

DATA11

DID4

DID5

V-by-One®HS_D[23]*

THCV236 D[23]*

DID0

DID1

DID2

DID3

DID4

DID5

DID6

DID7

13

DATA1

DATA2

DATA3

DATA12

DATA13

DID6

DID7

V-by-One®HS_D[24]*

THCV236 D[24]*V-by-One®HS_D[27]*

THCV236 D[27]*V-by-One®HS_D[25]*V-by-One®HS_D[28]*

THCV236 D[28]*

THCV236 D[25]*V-by-One®HS_D[29]*

THCV236 D[29]*V-by-One®HS_D[26]*V-by-One®HS_D[30]*

THCV236 D[30]*

THCV236 D[26]**CTL packet
V-by-One®HS_D[31]*

THCV236 D[31]*

THCV236
HFSEL=0

12

DATA2

DATA3

DATA12

DATA13

DID6

DID7

0

0

0

0

0

0

0

0

4byte

11

V

ECC3

ECC3

DATA4

DATA5

DATA14

DATA15

SP1

10

DATA4

DATA5

DATA14

DATA15

-

-

-

-

-

-

-

-

3byte

9

V

ECC4

ECC4

DATA6

DATA7

0

0

0

0

0

0

0

0

4byte

8

H

ECC5

ECC5

DATA6

DATA7

SP2

7

V

ECC6

ECC6

-

-

-

-

-

-

-

-

3byte

6

H

ECC7

ECC7

0

0

0

0

0

0

0

0

4byte

5

-

-

-

-

-

-

-

-

SP3

4

V

0

0

-

-

0

-

0

0

-

0

0

-

-

0

-

3byte
mipi Short Packet
0
1
2
3

-

4byte

SP4
3byte

THCV241A_Rev.2.11_E

31

Vx1 Short Packet

Figure 12. MIPI Short Packet V-by-One® HS bridge bit mapping

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THCV241A_Rev.2.11_E

6.17 2-wire serial interface
6.17.1

2-wire serial I/F slave Device ID

To use GPIO (General Purpose Input/Output), fault/error detection, and interrupt function, 2-wire serial I/F
enables to access registers. AIN pin determines 2-wire slave Device ID setting.

Table 27.

2-wire serial I/F Device ID select by AIN pin

Pin Name

Pin #

type*

AIN

27

I

Description
Select Slave Address
0 : 2w ire serial Address = 7'b000_1011
1 : 2w ire serial Address = 7'b011_0100

As an additional method, 2-wire slave Device ID setting can be changed from default value by register setting.

Table 28.

2-wire serial I/F Device ID select by register setting

Sub-Link
Master Slave
Addr(h) Addr(h)BitsRegisterw idthR/W

0x0050 0x00D0[7:0]

R_2WIRE_SADR

8

RW

Masteror Slav e

Description
2WIRE slave device address setting[7]2WIRE slave device address control
0: 2WIRE slv device addr. is set by AIN pin
1: 2WIRE slv device addr. is set by follow ing register [6:0][6:0]2WIRE slave device address value for register control

Default

related

8'd0MSTHine Electronics, Inc.

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6.17.2

2-wire serial Read/Write access to local Register

HOST MPU can directly access THCV241A local register by 2-wire serial I/F.

THCV241A
Sub-Link Block

Sub-Link
Master2-wire
Slave

SCL
SDA

Host
MPU

Registe r

MSSEL = Use r Select

AIN = Use r SelectFigure 13. Host to THCV241A local register access configuration

Figure 14. 2-wire serial I/F write to THCV241A local register protocol

Figure 15. 2-wire serial I/F read to THCV241A local register protocol

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THCV241A_Rev.2.11_E

6.18 2-wire serial I/F Watch Dog Timer
2-wire Watch Dog Timer (WDT) is installed to monitor status.

Table 29.

2-wire WDT setting

Sub-Link
Master Slave
Addr(h) Addr(h)BitsRegisterw idthR/W

0x004B 0x00CB[4]

R_2WIRE_WD_EN

1

RW

0x004B 0x00CB[0]

R_2WIRE_WD_OFFSET

1

RW

0x004C 0x00CC[7:0]

R_2WIRE_WD_TIM

8

RW

Masteror Slav e

Description
Default
2-w ire WDT Enable
0:Disable
1'b1
1:Enable
2-w ire WDT offset time
1:11'd2047
1'd1
0:11'd1023
2-w ire WDT time = 64×{R_2WIRE_WD_TIM<7:0>+1}×{"2WIRE WDT
8'd255offset time"} × tOSC

relatedMS

MS
MS

6.19 Register Auto Checksum diagnosis
Register values checksum is continuously calculated as R_CKSUM_RVAL and checked compared to userdefined target, R_CKSUM_VAL. If any change occurs, it can be reported as interrupt.

Table 30.

Register Auto Checksum diagnosis control and monitoring

Sub-Link
Master Slave
Addr(h) Addr(h)BitsRegisterw idthR/W

0x0008 0x0088[0]

R_CKSUM_EN

1

RW

0x0009 0x0089[7:0]

R_CKSUM_TIM

8

RW

0x000A 0x008A
0x000B 0x008B

[7:0]
[7:0]

R_CKSUM_VAL
R_CKSUM_RVAL

8
8

RW
R

0x0060 0x00E0[4]

R_INT_CKSUM_ERR

1

R

0x0061 0x00E1[4]

R_INTM_CKSUM_ERR

1

RW

0x0062 0x00E2[4]

R_INTC_CKSUM_ERR

1

W

Masteror Slav e

Description
Internal Register AutoCheckSum Enable
0:Disable
1:EnableInternal Register AutoCheckSum check interval=1024×64×(R_CKSUM_TIM<7:0>+1) × tOSC
Internal Register AutoCheckSum expected target value
Internal Register AutoCheckSum read value
Interrupt factor: Internal register Checksum error
1: Interrupt (error is detected)
Interrupt mask: Internal register CheckSum error
0: Interrupt mask
Interrupt clear: Internal register CheckSum error
1: Interrupt clear

Default

related

1'b0

MS

8'd19

MS

8'd0
-

MS
MS

-

MS

1'b0

MS

-

MS

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THCV241A_Rev.2.11_E

6.20 Sub-Link setting
Sub-Link Master or Sub-Link Slave operation is selectable by MSSEL pin control.
Sub-Link Master control register address and Sub-Link Slave control register address are different even for thesame Sub-Link function register.
Sub-Link Master control register is from 0x0000 to 0x007F.
Sub-Link Slave control register is from 0x0080 to 0x00FF.
As a note, registers other than Sub-Link control register from 0x1000 have only one address for one function,
which is independent of Sub-Link operation as Master or Slave.

Sub-Link Master “2-wire Set&Trigger mode1” (R_SLINK_MODE setting) is compatible with THCV236-Q.
Sub-Link Polling interval is controllable from 1us to 800us, that may have relationships on fault/error
detection, interrupt, or other UART / GPIO transfer time designed on application. SSR (Sub-Link Status Read)
interval determines recovery quickness from 2-wire serial remote communication completion. SSR interval
effects only on Sub-Link Master “2-wire Set&Trigger mode1” (R_SLINK_MODE setting).

Table 31.

Sub-Link Master protocol basic setting

Sub-Link
Master Slave
Addr(h) Addr(h)BitsRegisterw idthR/W

0x0004-[1:0]

R_SLINK_MODE

2

RW

0x0010-[0]

R_SLINK_EN

1

RW

0x0014-[4]

R_SLINK_POL_EN

1

RW

0x0014-[1:0]

R_SLINK_POL_TIM_UP

2

RW

0x0015-[7:0]

R_SLINK_POL_TIM_DN

8

RW

0x0016-[4]

R_SLINK_SSR_EN

1

RW

0x0016-[1:0]

R_SLINK_SSR_TIM_UP

2

RW

0x0017-[7:0]

R_SLINK_SSR_TIM_DN

8

RW

Masteror Slav e

Description
Default
Sub-Link basic protocol setting as Sub-Link Master0: Reserved
1: 2-w ire Set&Trigger (Normal) mode1 (compatible w ith THCV236)
2: Reserved
2'd1
3: Reserved
Note: When THCV241A is used as Sub-Link Slave, this registersetting has no meaning. Counterpart Sub-Link Master setting
controls Sub-Link protocol including THCV241A as slave device.
Sub-link Enable
0:Sublink Disable
1'b0
1:Sublink Enable
Sublink Polling Enable
0:Disable
1'b1
1:Enable
Sublink Polling interval setting
2'd0Sublink Polling interval time=64×(256×R_SLINK_POL_TIM_UP<1:0>+R_SLINK_POL_TIM_DN<7:0>+1)×tOSC
8'd124*No Polling w hen R_SLINK_POL_TIM_UP=0 and
R_SLINK_POL_TIM_DN=0
Sublink SSR Enable
0:Disable
1'b1
1:Enable
Sublink SSR interval setting
2'd0Sublink SSR interval time=64×(256×R_SLINK_SSR_TIM_UP<1:0>+R_SLINK_SSR_TIM_DN<7:0>+1)×tOSC
8'd249*No SSR w hen R_SLINK_SSR_TIM_UP=0 and
R_SLINK_SSR_TIM_DN=0

related

M

M

M
M
M

M
M
M

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THCV241A_Rev.2.11_E

To use GPIO (General Purpose Input/Output) pin, fault/error detection and interrupt function, “2-wire
Set&Trigger mode1” enables remote register access. Sub-Link Master device has 2-wire serial slave block andcan connect to HOST MPU, Sub-Link Slave device has 2-wire serial master block and can connect to remote side
2-wire serial slave devices.
HOST MPU can access register of Sub-Link Master device, Sub-Link Slave device and remote side 2-wire serial
slave devices.

For “from remote THCV236-Q Sub-Link Master or from remote THCV242 Sub-Link mode1 or remote
THCV244 Sub-Link mode1 to THCV241A Sub-Link Slave” access, “0x00FE” /”R_WB_MSB” and“R_WA_MODE” Word Address and Bank setting is required at the beginning before any read access. “0x00FE”
Word Address write access from THCV236-Q, THCV242 or THCV244 is supposed to be divided into “0x00” and“0xFE” commands by 8bit Sub-Address restriction.

Table 32.
Sub-Link
Master Slave
Addr(h) Addr(h)Sub-Link Word Address control setting
Masteror Slav e

Bits

Registerw idthR/W-

0x00FE[6:4]

R_WB_MSB

3RW-

0x00FE[0]

R_WA_MODE

1

RW

Description
Default
Word Address Bank MSB setting on 1Byte Word-addr. acess fromremote Sub-Link Master (e.g. THCV236-Q)(active only w hen R_WA_MODE=1)
3'd1=3'b001:"Word Address MSB[15:8]" bank is "8'h00"
3'b0
3'd2=3'b010:"Word Address MSB[15:8]" bank is "8'h10"
3'd3=3'b011:"Word Address MSB[15:8]" bank is "8'h11"
others:Reserved
Word Address Byte number settingfrom remote Sub-Link Master
0:2Byte Word Address acess from remote Sub-Link Master
1'b0
1:1Byte Word Address acess from remote Sub-Link Master(THCV236-Q setting is "1")relatedS

S

Under “1Byte Word Address access” operation (0x00FE bit0=1’b1), 1Byte access to 0xFE has the same
meaning as 2Byte access to 0x00FE, being independent of “Word Address Bank MSB setting” (0x00FE
bit[6:4]). This procedure enables users to reset Word Address Bank MSB setting on 1Byte Word Address accessand Word Address Byte number setting itself.

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THCV241A_Rev.2.11_E

6.20.1

Sub-Link 2-wire Set and Trigger mode (2-wire Normal mode)

Sub-Link Master 2-wire Set&Trigger mode1 (R_SLINK_MODE setting) is compatible with THCV236-Q.

HOST MPU can access to Sub-Link Slave’s register via THCV241A as Sub-Link Master only by THCV241A
internal local register control and monitoring on 2-wire Set&Trigger mode1.

Sub-Link Slave Device

THCV241A as Su b-Link Master

Sub-Link Block

Sub-Link Block
Sub-Link
line

2-wireMaster

Sub-Link
Slave

Sub-Link
MasterSCL

2-wire
Slave

Host
MPU

SDA
INT

Registe r

Registe r

Interrupt signal

Trigge red acces s by Sub-Link Master
Access fro m/to HOS T

MSSEL=1

MSSEL=0

AIN = Use r S electFigure 16. Host MPU to Sub-Link Slave Register via THCV241A access configuration

HOST MPU can access to remote side 2-wire serial slave register via THCV241A as Sub-Link Master only by
THCV241A internal local register control and monitoring on 2-wire Set&Trigger mode1.

Sub-Link Slave Device

THCV241A as Su b-Link Master

Sub-Link Block2-wireSlave
Device#a

SCL
SDA

2-wireMaster

Sub-Link Block

Sub-Link
Slave

Sub-Link
line

Sub-Link
MasterSCL

2-wire
Slave

SDA

Host
MPU

INT

・
・

Registe r

2-wireSlave
Device#b
MSSEL=1

Registe r

Trigge red acces s by Sub-Link Master
Access fro m/to HOS T

MSSEL=0Interrupt signal

AIN = Use r SelectFigure 17. Host MPU to 2-wire slave devices connected to Sub-Link Slave via THCV241A access configuration

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THCV241A_Rev.2.11_E

In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial accessand Sub-Link Slave internal bus access or remote side 2-wire serial access.
R_2WIRE_CLKSEN (Sub-Link Master side register, 0x0042 bit0) selects whether 2-wire serial slave of SubLink Master perform clock stretching.
When R_2WIRE_CLKSEN = 1, Sub-Link Master device waits HOST MPU until Sub-Link Slave register accessor remote side 2-wire serial slave register access complete by clock stretching.
When R_2WIRE_CLKSEN = 0, Sub-Link Master device informs HOST MPU that Sub-Link Slave register
access or remote side 2-wire serial register access has completed by interruption (detectable on INT pin) without
clock stretching.

Figure 18. Sub-Link Master 2-wire slave clock stretching operation

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THCV241A_Rev.2.11_E

Table 33.

2-wire serial I/F Set& Trigger mode remote access control and monitoring local registers

Sub-Link
MasterMasterSlaveor Slav e

Addr(h) Addr(h)BitsRegisterw idthR/W

Default

related0x0030-[7:0]

R_2WIRE_DATA08RW2-w ire serial I/F remote w rite/read data #0

8'd0

M

0x0031-[7:0]

R_2WIRE_DATA1

8RW

2-w ire serial I/F remote w rite/read data #1

8'd0

M

0x0032-[7:0]

R_2WIRE_DATA28RW

2-w ire serial I/F remote w rite/read data #2

8'd0

M

0x0033-[7:0]

R_2WIRE_DATA38RW2-w ire serial I/F remote w rite/read data #3

8'd0

M

0x0034-[7:0]

R_2WIRE_DATA48RW

2-w ire serial I/F remote w rite/read data #4

8'd0

M

0x0035-[7:0]

R_2WIRE_DATA58RW2-w ire serial I/F remote w rite/read data #5

8'd0

M

0x0036-[7:0]

R_2WIRE_DATA68RW

2-w ire serial I/F remote w rite/read data #6

8'd0

M

0x0037-[7:0]

R_2WIRE_DATA78RW2-w ire serial I/F remote w rite/read data #7

8'd0

M

0x0038-[7:0]

R_2WIRE_DATA88RW2-w ire serial I/F remote w rite/read data #8

8'd0

M

0x0039-[7:0]

R_2WIRE_DATA98RW2-w ire serial I/F remote w rite/read data #9

8'd0

M

0x003A-[7:0]

R_2WIRE_DATA108RW

2-w ire serial I/F remote w rite/read data #10

8'd0

M

0x003B-[7:0]

R_2WIRE_DATA118

RW

2-w ire serial I/F remote w rite/read data #11

8'd0

M

0x003C-[7:0]

R_2WIRE_DATA128

RW

2-w ire serial I/F remote w rite/read data #12

8'd0

M

0x003D-[7:0]

R_2WIRE_DATA138

RW

2-w ire serial I/F remote w rite/read data #13

8'd0

M

0x003E-[7:0]

R_2WIRE_DATA148

RW

2-w ire serial I/F remote w rite/read data #14

8'd0

M

0x003F-[7:0]

R_2WIRE_DATA158RW

2-w ire serial I/F remote w rite/read data #15

8'd0

M

7'h00

M

1'b0

M

-

-

3'd0

M

4'd0

M

-

-

1'b0

M

-

M
-

-

S

8'd31

S

8'd31

S

0x0040-[7:1]

R_2WIRE_DEVADR

7

RW

0x0040-[0]

R_2WIRE_WR

1

RW

0x0041-[7]reserved

1-0x0041-[6:4]

R_2WIRE_WADR_BYTE

3

RW

0x0041-[3:0]

R_2WIRE_DATA_BYTE

4

RW

0x0042-[7:1]

reserved

7-0x0042-[0]

R_2WIRE_CLKSEN

1

RW

[7:1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:1]

reserved
R_2WIRE_START
reserved
reserved
reserved
reserved
reserved

7
1
8
8
8
8
7

W
-

0x00430x00430x00C8-0x00C8[0]

R_2WIRE_BUS_CLR

1

W

-

0x00C9[7:0]

R_2WIRE_SCL_HW

8

RW

-

0x00CA[7:0]

R_2WIRE_SCL_LW

8

RW

Description

2-w ire serial I/F remote access target device address.
if target=self addr.; access to Sub-Link Slave inside register,else; access to remote side 2-w ire serial Slave devices externallyconnected to Sub-Link slave
2-w ire serial I/F remote access w rite or read select
0:Write1:Read2-w ire serial I/F remote device's Sub Address (Word Address,
register address) Byte w idth select.
address Byte w idth=R_2WIRE_WADR_BYTE<2:0>+1
0 : 1Byte= 8bit Sub addr.(refgister addr.)
1 : 2Byte=16bit Sub addr.(refgister addr.)
4 : 5Byte=40bit Sub addr.(refgister addr.), etc.
2-w ire serial I/F remote access data Byte number
Byte Number = R_2WIRE_DATA_BYTE + 1(e.g. 0x2 for 3byte burst)[w rite rule]
R_2WIRE_WADR_BYTE+R_2WIRE_DATA_BYTE =< 'd16
[read rule]
R_2WIRE_DATA_BYTE=<'d16
2-w ire serial I/F local response clock stretching Enable
0: Sub-Link Master (2-w ire slave) No clock stretching
1: Sub-Link Master (2-w ire slave) clock stretching Enable*2-w ire Pass Through mode forces clock stretching Enable
2-w ire serial I/F remote access start trigger
2-w ire serial I/F remote side bus clear
Write 1: 2-w ire bus clear action triggered from Sub-Link Slave (2w ire master) to 2-w ire slave device connected to Sub-Link Slave.
This bit is automatically cleared into 0 after reset action. 0 is
alw ays read.
SCL High w idth [tHIGH] setting on Sub-Link Slave side.
Output SCL High w idth is defined as below .
16×{R_2WIRE_SCL_HW<7:0>+1} * tOSC
SCL Low w idth [tLOW] setting on Sub-Link Slave side.
Output SCL Low w idth is defined as below .
16×{R_2WIRE_SCL_LW<7:0>+1} * tOSC

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6.21 Sub-Link Watch Dog Timer
Sub-Link Watch Dog Timer (WDT) is installed to monitor status. When Sub-Link single transaction started but
was not normally ended in time, WDT report Interrupt event of “R_INT_SLINK_TMOUT”.

Table 34.

Sub-Link WDT setting

Sub-Link
Master Slave
Addr(h) Addr(h)0x0018 0x0098

Bits
[7:5]

Registerreserved

w idth3

R/W-

0x0018 0x0098[4]

R_SLINK_WD_EN

1

RW

0x0018 0x0098
0x0018 0x0098

[3:2]
[1:0]

reserved
R_SLINK_WD_TIM_UP

2
2

RW

0x0019 0x0099[7:0]

R_SLINK_WD_TIM_DN

8

RW

Masteror Slav e

Description
Sublink WDT Enable
0:Disable
1:Enable
Sublink WDT time parameter
Sublink WDT time =64×(256×R_SLINK_WD_TIM_UP<1:0> +R_SLINK_WD_TIM_DN<7:0>+1) ×tOSC

Default-

related
-

1'b1

MS

2'd0

MS

8'd187MS

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6.22 Sub-Link Interrupt detection
For fault/error and significant event detection, Sub-Link prepares mechanism of monitoring for several internal
status and interrupt notification. More than one selected factors are logically OR operated for INT pin output. At
the same time the OR operated result is informed from Sub-Link Slave to Sub-Link Master.

Detectable interrupts both on Sub-Link Master and Slave are as follows.


IC Internal event except Sub-Link

Internal register Checksum error

2-wire access time out error



Sub-Link CRC error



Sub-Link protocol error



Sub-Link access time out error
Detectable interrupts as Sub-Link Master are as follows.



Main-Link LOCKN transition

Main-Link HTPDN transition



Sub-Link Slave side factor

remote 2-wire access on Sub-Link end
Detectable interrupts as Sub-Link Slave are as follows.



Sub-Link Slave 2-wire master bus clear end



Sub-Link Slave 2-wire NACK detection

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6.23 GPIO setting
Setting of GPIO can be configurable by 2-wire access to internal register.
6.23.1

Sub-Link Polling GPIO input/output

Local GPIO input is continuously reflected to remote GPIO output via Sub-Link polling. Input pins becometarget of interrupt monitoring.
Table 35.
Addr(h)Bits

Registerw idthSub-Link Polling GPIO setting
R/W

0x103D[3:0]

R_GPIO_TYP

4

R/W

0x103E[3:0]

R_GPIO_OEN

4

R/W

0x103F[3:0]

R_GPIO_CMOSEN

4

R/W

Description

Default

GPIO Mode Select[3]: 0:GPIO3 Register Mode, 1:GPIO3 Sub-Link Polling[2]: 0:GPIO2 Register Mode, 1:GPIO2 Sub-Link Polling[1]: 0:GPIO1 Register Mode, 1:GPIO1 Sub-Link Polling*[0]: 0:GPIO0 Register Mode, 1:GPIO0 Sub-Link Polling**Sub-Link Polling is compatible w ith THCV236 GPIO Through mode
GPIO0-3 Input/Output Select[3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0
0:GPIO Output Mode
1:GPIO Input Mode
GPIO0-3 CMOS/OpenDrain Select(for GPIO Output Mode)[3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0
0:OpenDrain
1:CMOS

4'h0

4'hf

4'h0

As default setting with THCV236-Q as Sub-Link Master communication (THCV241A as Sub-Link Slave),
GPIO1 Sub-Link Polling bridges output from THCV236-Q-GPIO4 Through Mode and GPIO0 Sub-Link Polling
bridges output from THCV236-Q-GPIO3 Through Mode respectively.

As default setting with THCV242 or THCV244 as Sub-Link Master communication (THCV241A as Sub-Link
Slave), GPIO1/0 Sub-Link Polling bridges output from THCV242 or THCV244-GPIO Through Mode and
GPIO3/2 Sub-Link Polling bridges input to THCV242 or THCV244-GPIO Through Mode respectively.

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Polling GPIO Bridging data are sampled every Sub-Link polling, whose basic interval is controlled by register
R_SLINK_POL_TIM_UP/_DN. Remote 2-wire access may become long transaction and could lengthen
Through GPIO polling reflection interval.

Through GPIO input
to local Sub-Link device

Sub-Link Polling

Polling

Polling

Polling

Polling

Polling

Through GPIO output
from remote Sub-Link device
Sub-Link Polling interval

Figure 19. Host MPU to Sub-Link Slave Register via THCV241A access configuration

Remote UART bridge is supported with Sub-Link Polling GPIO input/output. Remote UART Tx and Rx bridge
baud rate is supposed to be designed against Sub-Link Polling interval to accommodate deterministic jitter
caused by intermittent Sub-Link communication timing.

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THCV241A_Rev.2.11_E

6.23.2

Register GPIO

GPIO input monitoring and output control are available with register. Input pins become target of interrupt
monitoring.
Table 36.
Addr(h)Bits

Register

Register GPIO setting and status monitoring
w idthR/W

0x103D[3:0]

R_GPIO_TYP

4

R/W

0x103E[7:4]

R_GPIO_OUT

4

R/W

0x103E[3:0]

R_GPIO_OEN

4

R/W

0x103F[3:0]

R_GPIO_CMOSEN

4

R/W

0x1121[7:4]

R_GPIO_IMON

4R

0x1121[3:0]

R_GPIO_INT_DETECT

4R

0x1122[3:0]

R_GPIO_INTC_DETECT

4W

Description

Default

GPIO Mode Select[3]: 0:GPIO3 Register Mode, 1:GPIO3 Sub-Link Polling[2]: 0:GPIO2 Register Mode, 1:GPIO2 Sub-Link Polling[1]: 0:GPIO1 Register Mode, 1:GPIO1 Sub-Link Polling*[0]: 0:GPIO0 Register Mode, 1:GPIO0 Sub-Link Polling**Sub-Link Polling is compatible w ith THCV236 GPIO Through mode
GPIO0-3 Output Data Register[3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0
GPIO0-3 Input/Output Select[3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0
0:GPIO Output Mode
1:GPIO Input Mode
GPIO0-3 CMOS/OpenDrain Select(for GPIO Output Mode)[3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0
0:OpenDrain
1:CMOS
GPIO0-3 Input Monitor Register[7]:GPIO3, [6]:GPIO2, [5]:GPIO1, [4]:GPIO0Interrput Signal for GPI[3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0
0:No Interrupt
1:Interrupt (detect for asserted or negated of GPI Input)
Interrupt Clear for GPI[3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO00:Interrupt No Clear
1:Interrupt Clear

4'h0

4'h0

4'hf

4'h0

-

-

-

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6.24 Internal Error / status signal monitoring GPIO output
Internal error or status signal can be monitored as GPIO output by register setting.

Table 37.
Addr(h)Bits

Internal Error / status signal monitoring GPIO output setting 1/2

Registerw idthR/W

0x10380x10380x10390x1039

[6:4]
[2:0]
[6:4]
[2:0]

R_GPIO_SEL0
R_GPIO_SEL1
R_GPIO_SEL2
R_GPIO_SEL3

3

R/W

0x105D
0x105D

[7:4]
[3:0]

R_ERR_SEL1
R_ERR_SEL2

4
4

R/W
R/W

Table 38.

Description

Default

GPIO0-3 Error / status output select3b'000:Normal
3b'001:R_ERR_SEL1(Internal Selected Error1)
3b'010:R_ERR_SEL2(Internal Selected Error2)
3b'011:R_EXT_ERR_SEL0(External Selected Error1)
3b'100:R_EXT_ERR_SEL1(External Selected Error2)
Others:Normal
Internal Selected Error1 output to GPIO and Sub-Link
Internal Selected Error2 output to GPIO and Sub-Link

3'h0

4'h0
4'h0

Internal Error / status signal monitoring GPIO output setting 2/2

Sub-Link
Master Slave
Addr(h) Addr(h)0x006E 0x00EE
0x006D 0x00ED

Bits
[7:4]
[3:0]

Register
R_SLINK_ERR_SEL1
R_SLINK_ERR_SEL0

w idth
4
4

R/W
RW
RW

Description
Sublink Polling to inform error signal select #1
Sublink Polling to inform error signal select #0

Default
4'd0
4'd0

relatedMSMS

0x006F 0x00EF[7:4]

R_EXT_ERR_SEL1

4

RW

Sub-Link operator Selected Error#1 output to GPIO

4'd0

MS

0x006F 0x00EF[3:0]

R_EXT_ERR_SEL0

4

RW

Sub-Link operator Selected Error#0 output to GPIO

4'd0

MS

Masteror Slav e

Table 39.

IC Internal selectable Error / status signal

R_ERR_SEL1/2[3:0]Error signal

4'b0000

reserved

4'b0001

MIPI CRC error

4'b0010MIPI ECC 1bit error

4'b0011MIPI ECC 2bit error

4'b0100

MIPI ID error (MIPI ID is not equal to Main-Link setting)4'b0101

MIPI SoT sequence not detected error

4'b0110MIPI SYNCCODE SoT 1bit error

4'b0111MIPI FRAMESYNC FS/FE position error

4'b1000

reserved

4'b1001

MIPI Control state error

4'b1010MIPI FS

4'b1011MIPI FE

4'b1100

reserved

4'b1101

reserved

4'b1110Main-Link Data Handle error

4'b1111

PLL auto configuration setting error

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Table 40.

IC External sub-link operator selectable Error / status signal

R_SLINK_ERR_SELn[3:0] (n=0,1)
R_EXT_ERR_SELn[3:0] (n=0,1)'h00

Assignment on Sub-Link Master(MSSEL=0)

Assignment on Sub-Link Slave(MSSEL=1)
R_ERR_SEL1'h01

R_ERR_SEL2'h02

R_SLINK_ERR_SEL0 of Sub-Link Slave

R_SLINK_ERR_SEL0 of Sub-Link Master'h03

R_SLINK_ERR_SEL1 of Sub-Link Slave

R_SLINK_ERR_SEL1 of Sub-Link Master'h04

R_INT_EXTERNAL'h05

R_INT_CKSUM_ERR'h06

R_INT_I2C_TMOUT

'h07

1'b0

'h08

R_INT_SLINK_PROTERR'h09

R_INT_SLINK_TMOUT'h0A

R_INT_LOCKN

1'b0

'h0B

R_INT_HTPDN

1'b0

'h0C

R_INT_SLAVESIDE

1'b0

'h0D

R_INT_EXTI2C_ACSEND

1'b0

'h0E

1'b0

R_INT_EXTI2CS_BUSCLR

'h0F

1'b0

R_INT_EXTI2CS_NACK

6.25 Internal Error / status signal monitoring register
Internal error or status signal can be monitored as register read value.
Error count register can be cleared by particular register write “1” access.
Error status register can be masked to “0” fixed by particular register appropriate write access.

Table 41.
ModuleInternal Error / status signal monitoring register

ERR / ERR_CNT

Main-Link

R_DHNDL_ERR

PLL
MIPI
MIPI
MIPI
Sub-Link

PLL_SET_NG
R_RX_CRC_ERR_CNT[15:0]
R_RX_ECC_ERR_CRCT_CNT[15:0]
R_RX_ECC_ERR_DBLE_CNT[15:0]
R_SLINK_FBETERR_NUM_*[15:0]

CLEAR
R_CRC_ERR_CNT_CLR
R_ECC_ERR_CRCT_CNT_CLR
R_ECC_ERR_DBLE_CNT_CLR
R_SLINK_FBETERR_CLR

MASK/EN/OFF
R_DHNDL_INT_MSK

Description
Main-Link Data Handle error
PLL auto configuration setting error
CRC error count by every Line
ECC1bit error count by every Line
ECC2bit error count by every Line
Sub-link Feald BET error count

R_PLL_SET_NG_MSK*H:Enable L:Disable, which is defferent polarity from other mask registers

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6.26 Interrupt monitoring
Interrupt (INT) detects occurrence of internal error or status signal and then, latch the detected state.
Interrupt factor can be cleared by particular register write “1” access.
Interrupt factor can be masked to “0” fixed by particular register appropriate write access.

Table 42.
Module
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
Main-Link
GPIO
Sub-Link
Sub-Link
Sub-Link
Sub-Link
Sub-Link
Sub-Link
Sub-Link
Sub-Link
Sub-Link
Sub-Link
Sub-Link

INT

Interrupt monitoring

CLEAR

MASK/EN/OFF

R_ERR_CRC

R_CRC_ERR_CLR

R_CRC_CMP_MSK

R_ERR_ECCCOR
R_ERR_ECCDBL
R_ERR_ID
R_ERR_SOTSYNC[3:0]
R_ERR_SYNCCODE[3:0]
R_ERR_FRAMESYNC[3:0]
R_ERR_CONTROL[4:0]
R_INT_FS[3:0]
R_INT_FE[3:0]
R_DHNDL_INT
R_GPIO_INT_DETECT[3:0]
R_INT_EXTERNAL
R_INT_CKSUM_ERR
R_INT_I2C_TMOUT
R_INT_SLINK_PROTERR
R_INT_SLINK_TMOUT
R_INT_LOCKN
R_INT_HTPDNR_INT_SLAVESIDER_INT_EXTI2C_ACSENDR_INT_EXTI2CS_BUSCLR
R_INT_EXTI2CS_NACK

R_ECC_CRCT_ERR_CLR
R_ECC_DOUBLE_ERR_CLR
R_ERR_ID_CLR
R_SOT_SYNC_HS_CLR[3:0]
R_SOT_SYNCCODE_CLR[3:0]
R_ERR_FR_SYNC_ON_CLR[3:0]
R_ERR_CTL_CLR[4:0]
R_INT_FS_ON_CLR[3:0]
R_INT_FE_ON_CLR[3:0]
R_DHNDL_INT_CLR
R_GPIO_INTC_DETECT[3:0]
R_INTC_EXTERNAL
R_INTC_CKSUM_ERR
R_INTC_I2C_TMOUT
R_INTC_SLINK_PROTERR
R_INTC_SLINK_TMOUT
R_INTC_LOCKN
R_INTC_HTPDNR_INTC_SLAVESIDER_INTC_EXTI2C_ACSENDR_INTC_EXTI2CS_BUSCLR
R_INTC_EXTI2CS_NACK

R_ECC1_CMP_MSK
R_ECC2_CMP_MSK
R_ERR_ID_MSK
R_ERR_SOT_HS_MSK_R[3:0]
R_RX_IGNORE_DERR[3:0]
R_ERR_FR_SYNC_MSK_R[3:0]
R_ERR_CTL_MSK[4:0]
R_INT_FS_MSK_R[3:0]
R_INT_FE_MSK_R[3:0]
R_DHNDL_INT_MSK
R_GPIO_INTM_DETECT[3:0]
R_INTM_EXTERNAL
R_INTM_CKSUM_ERR
R_INTM_I2C_TMOUT
R_INTM_SLINK_PROTERR
R_INTM_SLINK_TMOUT
R_INTM_LOCKN
R_INTM_HTPDNR_INTM_SLAVESIDER_INTM_EXTI2C_ACSENDR_INTM_EXTI2CS_BUSCLR
R_INTM_EXTI2CS_NACKDescription
MIPI CRC error
MIPI ECC 1bit error
MIPI ECC 2bit error
MIPI ID error (MIPI ID is not equal to Main-Link setting)
MIPI SoT sequence not detected error
MIPI SYNCCODE SoT 1bit error
MIPI FRAMESYNC FS/FE position error
MIPI Control state error
MIPI FSMIPI FE
Main-Link Data Handle error
GPIO input transition detect
IC Internal event except Sub-Link
Internal register Checksum error
2-wire access time out error
Sub-Link protocol error
Sub-Link access time out error
Main-Link LOCKN transition
Main-Link HTPDN transition
Sub-Link Slave side factor
remote 2-wire access on Sub-Link end
Sub-Link Slave 2-wire master bus clear end
Sub-Link Slave 2-wire NACK detection

As a register, interrupt detected state is “1” and cleared state is “0”. When multiple interrupt sources areactivated, the OR operated result is indicated as IC external INT pin output, which at the same time can be sent
to Sub-Link counterpart device.
As an external INT pin output, open drain output interrupt detected state is “Low” and cleared state is “Hi-Z”,
while INT pin CMOS push-pull output interrupt detected state is “High” and cleared state is “Low”.

Table 43.
Addr(h)0x1041Bits[0]Registerw idthR_INT_CMOSEN

1

INT pin output control
R/W
R/W

Description[IO] INT CMOS/OpenDrain Select0:OpenDrain
1:CMOS

Default
1'h0

INT interrupt function is supposed to be cleared before start monitoring any desired status because INT status
may have been changed before monitoring activation.

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For Sub-Link remote interrupt bridge, Sub-Link Master prepares “SLAVESIDE” interrupt factor monitoring
element. This Sub-Link SLAVESIDE interrupt monitoring element connected to THCV241A Sub-Link block of
THCV241A as Sub-Link Slave.
MIPI, Main-Link, GPIO and other modules of THCV241A are designed as separated module and not includedin Sub-Link Module so that R_INT_EXTERNAL factor must be set as “No mask” in order to report those MIPI,
Main-Link, GPIO and other Interrupt factor to remote Sub-Link Master.

THCV241A
MIP I
ModuleSub-Link Mo dule

Main-Link
ModuleGPIO
ModuleSub-Link MasterInte rrupt
han dling

R_INT_EXTERNAL

Sub-Link Block
Sub-Link
line

Sub-Link
Master2-wireSlave

R_INT_SLAVESIDEMSSEL=1

Host
MPU

Interrupt signal

Registe r

Inte rrupt monitor by Sub-Link Master
Access fro m/to HOST

SDA
INT

Registe r
Registe r

SCL

MSSEL=0

AIN = Use r SelectFigure 20. Interrupt configuration external of Sub-Link module.

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6.27 Build-In Self-Test pattern generator (BIST)
RGB888 3Byte mode pattern generator is available. Hsync width is 1 pixel fixed. Vsync width is 1 line fixed.
Generated pattern is transmitted on Main-Link. As of V-by-One® HS output format, R_OUTPUT_FMT registervalue is ignored and format is fixed to RGB888 when R_BISTEN = 1, Enabled.

Table 44.

V-by-One® HS Build-In Self-Test pattern generator (BIST) setting

Addr(h)Bits

Registerw idthR/W

0x1004[1]

R_VSYNC_POL

1

R/W

0x1004[0]

R_HSYNC_POL

1

R/W

0x105F[0]

R_BISTEN

1

R/W

0x1060[4:0]

R_BIST_PTN

5

R/W

0x1061[7:0]

R_GS_SEL_R

8

R/W

0x1062[7:0]

R_GS_SEL_G

8

R/W

0x1063[7:0]

R_GS_SEL_B

8

R/W

0x10640x10650x10660x1067

[3:0]
[7:0]
[3:0]
[7:0]

R_CURSOH[11:8]
R_CURSOH[7:0]
R_CURSOV[11:8]
R_CURSOV[7:0]

4
8
4
8

R/W
R/W
R/W
R/W

0x1068[1:0]

R_HACTIVE_V[9:8]2R/W

0x1069[7:0]

R_HACTIVE_V[7:0]8R/W

0x106A
0x106B

[2:0]
[7:0]

R_VACTIVE_V[10:8]
R_VACTIVE_V[7:0]

3
8

R/W
R/W

0x106C[1:0]

R_HBLANK_V[9:8]2R/W

0x106D[7:0]

R_HBLANK_V[7:0]8R/W

0x106E0x106F

[1:0]
[7:0]

R_VBLANK_V[9:8]
R_VBLANK_V[7:0]

2
8

R/W
R/W

0x1070[0]

R_HBP_V[8]1R/W

0x1071[7:0]

R_HBP_V[7:0]8R/W

0x1072[6:0]

R_VBP_V

7

R/W

Description
V-by-One® HS Vsync polarity
0:High pulse (High active) (THCV242-Q default)
1:Low pulse (Low active)
V-by-One® HS Hsync polarity
0:High pulse (High active) (THCV242-Q default)
1:Low pulse (Low active)
BIST Enable
0:Disable
1:Enable
BIST pattern select
00: Automatic pattern sw itching repetition from 01 to 0E
01~05: raster patterns
06~07: color bar patterns
08~0B: ramp patterns
0C: 16x16 pixel checker
0D: Frame
0E: Sub checker
0F: reserved
10: Frame2
11~16: checkers
17: Cursor
18~1F: reserved
BIST Gradient Setting Red
00:Black <=> FF:Red
BIST Gradient Setting Green
00:Black <=> FF:Green
BIST Gradient Setting Blue
00:Black <=> FF:Blue
BIST Cursor position on horizontal direction
BIST Cursor position on horizontal direction
BIST Cursor position on vertical direction
BIST Cursor position on vertical direction
BIST Hactive pixel number setting
Hactive pixel number = "R_HACTIVE_V" x4
BIST Hactive pixel number
Hactive pixel number = "R_HACTIVE_V" x4
BIST Vactive line number (must be even number)
BIST Vactive line number (must be even number)
BIST Hblank pixel number setting
Hblank pixel number = "R_HBLANK_V" x4
BIST Hblank pixel number
Hblank pixel number = "R_HBLANK_V" x4
BIST Vblank line number
BIST Vblank line number
BIST Hbackporch pixel number setting
Hbackporch pixel number = "R_HBP_V" x4
BIST Hbackporch pixel number setting
Hbackporch pixel number = "R_HBP_V" x4
BIST Vbackporch line number

Default
1'h0

1'h0

1'h0

5'h00

8'hff
8'hff
8'hff
4'h0
8'h00
4'h0
8'h00
2'h1
8'hE0
3'h4
8'h38
2'h0
8'h46
2'h0
8'h27
1'h0
8'h28
7'h10

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THCV241A_Rev.2.11_E

Automatic pattern switching BIST repetition is available.
Gradient setting only effects on particular patterns.
Cursor position can be set by “R_CURSOR_H”, “R_CURSOR_V” resistor.

Table 45.
BIST_PTN[4:0]Pattern

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F

Automatic sw itch BISTWhite rasterBlack rasterRed rasterGreen rasterBlue rasterHorizontal color bars
Vertical color bars
Horizontal gray ramp
Vertical gray ramp
Horizontal RGBW ramp
Vertical RGBW ramp
16×16 pi×el checker
Frame
Sub pixel checker
reserved

V-by-One® HS Build-In Self-Test (BIST) selectable patterns
Gradientsetting effect
○
○
×
○
○
○
○
○
×
×
×
×
○
○
○
×

Automaticsw itch order
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-

BIST_PTN[4:0]Pattern

10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F

Frame24×1 checker 1
4×1 checker 2
2×1 checker 1
2×1 checker 2
1×1 checker 1
1×1 checker 2
Cursorreserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

Gradientsetting effect
×
○
×
○
×
○
×
○
×
×
×
×
×
×
×
×

Automaticsw itch order-

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THCV241A_Rev.2.11_E

6.28 Main-Link Field BET
In order to help users to check validity of CML serial line (Main-Link and Sub-Link), THCV241A andparticular V-by-One® HS receiver have an operation mode in which they act as a bit error tester (BET). In MainLink Field BET mode, THCV241A internally generates test pattern which is then serialized onto the Main-Link
CML line. The counterpart particular receiver, that also has BET function mode, receives the data stream andchecks bit errors. The generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the CML
channel. As for the receiver, the internal test pattern check circuit gets enabled and reports result on a certain pin
or register.

Table 46.

V-by-One® HS Field BET pattern generator setting

Addr(h)Bits

Registerw idthR/W

0x1052[1]

R_ML_BETEN

1

R/W

Description
V-by-One® HS Main Filed-BET Enable
0： Normal Mode
1： Filed-BET Mode

Default
1'h0

6.29 Sub-Link Field BET operation and output from GPIOIn Sub-Link Field BET mode, Sub-Link Master device internally generates test pattern which is then serialized
onto the Sub-Link line. Sub-Link Slave device also has BET function mode. Sub-Link Slave device receives thedata stream and checks bit errors. Note that Sub-Link Slave device must be set this mode prior to Sub-Link
Master device. Pattern check result is output from BETOUT pin of the Sub-Link Slave device. The BETOUT pingoes LOW whenever bit errors occur, or it stays HIGH when there is no bit error.
LATEN enables latched result of once-error-detected. BETOUT/LATEN output pin is assigned according topriority GPIO0 > GPIO1 > GPIO2 > GPIO3 when the same Sub-Link Field BET MODE Signal overlap several
pins as register setting.

Addr(h)Bits

Table 47.

Sub-Link Field BET result GPIO output setting

Registerw idthR/W

0x1056[0]

R_SUB_BETEN

1

R/W

0x1057[7:0]

R_SUB_BETSEL

8

R/W

Description

Default

Sub-Link Filed-BET Enable
0： Normal Mode
1： Filed-BET Mode
Sub-Link Field-BET MODE Signal Select[7:6] 10 : GPIO3 BETOUT 01 : GPIO3 LATEN 11,00 : Don't Care
[5:4] 10 : GPIO2 BETOUT 01 : GPIO2 LATEN 11,00 : Don't Care
[3:2] 10 : GPIO1 BETOUT 01 : GPIO1 LATEN 11,00 : Don't Care
[1:0] 10 : GPIO0 BETOUT 01 : GPIO0 LATEN 11,00 : Don't Care

1'h0

8'h06

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THCV241A_Rev.2.11_E

6.30 CMOS IO Input noise Filter
IO Filter is available and applied default.

Table 48.
Addr(h)Bits

Registerw idthCMOS IO input noise filter
R/W

0x1048[3:0]

R_IOFLT_RANGE1

4

R/W

0x1049[3:0]

R_IOFLT_RANGE2

4

R/W

0x104A[3:0]

R_IOFLT_RANGE3

4

R/W

0x104B[3:0]

R_IOFLT_RANGE4

4

R/W

0x104C[3:0]

R_IOFLT_RANGE5

4

R/W

0x104D[3:0]

R_IOFLT_RANGE6

4

R/W

0x104E[3:0]

R_IOFLT_RANGE7

4R/W

0x104F[3:0]

R_IOFLT_RANGE8

4R/W

Description

Default

CMOS IO Input Signal Noise Fillter Setting for PDN1, MSSEL, AIN
0:No Filter
n:Filtering Glitch Signal w hen Pulse Width is Less thantOSC*n*16 (ns)
CMOS IO Input Signal Noise Fillter Setting for SCL, SDA
0:No Fillter
n:Filtering Glitch Signal w hen Pulse Width is Less thantOSC*n*2 (ns)
CMOS IO Input Signal Noise Fillter Setting for GPIO0
0:No Fillter
n:Filtering Glitch Signal w hen Pulse Width is Less thantOSC*n*2 (ns)
CMOS IO Input Signal Noise Fillter Setting for GPIO1
0:No Fillter
n:Filtering Glitch Signal w hen Pulse Width is Less thantOSC*n*2 (ns)
CMOS IO Input Signal Noise Fillter Setting for GPIO2
0:No Fillter
n:Filtering Glitch Signal w hen Pulse Width is Less thantOSC*n*2 (ns)
CMOS IO Input Signal Noise Fillter Setting for GPIO3
0:No Fillter
n:Filtering Glitch Signal w hen Pulse Width is Less thantOSC*n*2 (ns)
CMOS IO Input Signal Noise Fillter Setting for LOCKN
0:No Fillter
n:Filtering Glitch Signal w hen Pulse Width is Less thantOSC*n*2 (ns)
CMOS IO Input Signal Noise Fillter Setting for PDN0
0:No Fillter
n:Filtering Glitch Signal w hen Pulse Width is Less thantOSC*n*16 (ns)

4'h4

4'h2

4'h4

4'h4

4'h4

4'h4

4'h4

4'hF

6.31 CMOS output drive strength
CMOS output drive strength can be configurable.
Table 49.
Addr(h)Bits

Register

CMOS output drive strength setting

w idthR/W

0x1040[3:0]

R_GPIO_TDRV

4R/W

0x1047[6:0]

R_IO_DRV[7:0]8R/W

Description
GPIO0-3 CMOS IO Drive Strength Select[3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0
0: Normal Drive(4mA)
1: Strong Drive(8mA)
CMOS IO Drive Strength Select[6]:INT, [3]:CKO, [1]:SDA, [0]:SCL[5], [4], [2]:ReservedL
0: Normal Drive(4mA)
1: Strong Drive(8mA)

Default

4'h0

7'h00

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THCV241A_Rev.2.11_E

6.32 CKO reference clock buffer output
CKO reference clock buffer output can be configurable by 2-wire access to internal register.
Table 50.
Addr(h)0x1076Bits[6]Registerw idthR_CKOSTOP

1

CKO setting

R/W
R/W

Description
CKO output source select
0:CKI, 1: Low fix

Default
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THCV241A_Rev.2.11_E

6.33 Soft Reset
Soft Reset is available by 2-wire access to internal register.
PLL and V-by-One® HS initial statuses are reset state; therefore Soft Reset is supposed to be released inaccordance with appropriate sequence: PLL Soft Reset release => V-by-One® HS TX Soft Reset release.
Table 51.
Addr(h)Bits

Registerw idthSoft Reset register

R/W

0x1005[0]

R_PLL_SNRST

1

R/W

0x1006[0]

R_TX_SNRST

1

R/W

0x1021[0]

R_C_SNRST

1

R/W

0x1022[0]

R_DCLKSNRST

1

R/W

0x1023[0]

R_MCLKSNRST

1

R/W

0x10FF[7:0]

R_REGSNRST

8

R/W

Description

Default

Softw are Reset for PLL
0:Softw are Reset Active
1:Softw are Reset Release (PLL Normal Operation)
Softw are Reset for V-by-One® HS TX
0:Softw are Reset Active
1:Softw are Reset Release (Vx1HS TX Normal Operation)
MIPI CSI-2 Soft Reset
0:Reset1:Reset Release (MIPI CSI-2 Normal Operation)
Digital logic Clock Soft Reset
0:Reset1:Reset Release (Digital logic Clock Normal Operation)
MIPI Clock Soft Reset
0:Reset1:Reset Release (MIPI Clock Normal Operation)
Register Soft Reset
AA:Resetothers:Reserved

1'h0

1'h0

1'h1

1'h1

1'h1

8'h00

Also, change of PLL and V-by-One® HS parameters automatically cause Soft Reset without any touch on
R_PLL_SNRST nor R_TX_SNRST, whose temporary reset time length can be defined by R_PLL_CTERM and
R_TX_CTERM respectively.
Table 52.
Addr(h)Bits

Automatic Soft Reset of PLL and V-by-One® HS recovery time control
Registerw idthR/W

0x105B[7:0]

R_PLL_CTERM

8

R/W

0x105C[7:0]

R_TX_CTERM

8R/W

Description
PLL parameter change
automatic reset recovery time length
00 Disable(Disable Auto Soft Reset)
01 1*256*tOSC (typ.3.2us)
02 2*256*tOSC (typ.6.4us)
03 3*256*tOSC (typ.9.6us)：：
FE 254*256*tOSC (typ.812.8us)
FF 255*256*tOSC (typ.816us)
V-by-One® HS parameter change
automatic reset recovery time length
00 Disable(Disable Auto Soft Reset)
01 1*256*tOSC (typ.3.2us)
02 2*256*tOSC (typ.6.4us)
03 3*256*tOSC (typ.9.6us)：：
FE 254*256*tOSC (typ.812.8us)
FF 255*256*tOSC (typ.816us)

Default

8'h55

8'h55

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THCV241A_Rev.2.11_E

The registers that may trigger PLL automatic Soft Reset are as follows.

If R_PLL_SET_MODE=0,
R_CKI_FREQ
R_MIPI_MULT
R_VX1_LANE
R_OUTPUT_FMT
R_HFSEL
R_RX_LANE_SEL_EN

else if R_PLL_SET_MODE=1,
R_PLL_SETTING[47:0]
R_DIVVAL

on both R_PLL_SET_MODE=0 and R_PLL_SET_MODE=1,
R_SPREAD
R_DISABLE_SSCG

The registers that may trigger V-by-One® HS automatic Soft Reset are as follows.

R_NHSEL
R_LFQEN
R_ML0_PRE
R_ML1_PRE
R_ML0_DRV
R_ML1_DRV
R_COL_SEL
R_COL_MAN[1:0]
R_OUTPUT_FMT
R_HFSEL
R_BITMAP_SEL

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THCV241A_Rev.2.11_E

6.34 Power On Sequence
Power On Sequence must be controlled appropriate.
MIPI, PLL and V-by-One® HS block are reset state at power on default and require Reset Release.
. MIPI Soft Reset / PLL Soft Reset => V-by-One® HS Soft Reset is proper. See below detail.

VDDIO/VDDB(3.3V-1.8V)

t1

VDDL/VDDM/VDDA/VDDOP(1.2V)
t3

PDN0

Wait time before Register access is required after PDN=L => H
Initial Register setting is needed
t5

Register Access
Register Access Time REG(R_PLL_SNRST) Soft Reset must be released
t6 after all PLL setting parameters are completely written.

REG(R_PLL_SNRST)CKI(Ref Clock)tLT REG(R_TX_SNRST) Soft Reset must be released
after all Vx1HS TX setting paremeters written and PLL locked.

REG(R_VX1_SNRST)

tTPLL0TX0P/TX0N (,TX1P/TX1N)

To force REG(R_CKOSTOP) Low makes CKO pin start output

REG(R_RX_CKOSTOP)CKO

LP mode

RCKP/RCKN

HS modeREG(R_RX_DATALANE_EN)
REG(R_RX_CLKLANE_EN)MIPI Lane Enable are supposed to be activated at mipi LP mode timing.
Sequence should be from Data Lane (0x102D) to Clock Lane (0x102C).

Figure 21. Power On Sequence procedure

Table 53.

Power On Sequence specification

Symbolt1
t3
t5
t6

Parameter
3.3V to 1.2V
PDN0 Reset Rerease Time
Required w ait from PDN0=H to Register Access
Required w ait from CKI input to PLL Enable

Min
0
0
300
200

Typ
-

Max
-

Unit
us
us
us
us

tLT

Required w ait from PLL Lock Time to CML output

1000
F(CKI)--

us

tTPLL0V-by-One® HS Reset Release to CML Out Delay

-

-

250

us

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6.35 Lock / Re-Lock Sequence
Lock and re-lock sequence are as follows. V-by-One® HS automatically shifts into lock status from initial
status or unlock status caused by external noise under appropriate parameter set condition.

Figure 22. Lock Sequence

Figure 23. Re-Lock Sequence

Table 54.

Lock / Re-Lock Sequence specification

SymboltTNP0Parameter
LOCKN=H to Training pattern output delay

Min
-

Typ
-

Max
2

Unit
us

tTNP1

LOCKN=L to Data pattern output delay

-

-

1200
F(OUT)us

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THCV241A_Rev.2.11_E

7

Absolute Maximum Ratings
Table 55.

Absolute Maximum Ratings*

Parameter
Supply Voltage VDDH (VDDIO, VDDB)Supply Voltage VDD12 (VDDM, VDDOP, VDDL, VDDA)
LVCMOS Input Voltage
MIPI Input Voltage
CML Transmitter Output Voltage
CML Bi-directional buffer Input / Output Voltage
Storage Temperature Range
Junction temperature
Reflow Peak Temperature/Time*1 Max. must be below 4V at the same time
*2 Max. must be below 1.6V at the same time

Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-55
-

Typ
-

Max
4
1.6
VDDIO+0.3 *1
VDDM+0.3 *2
VDDA+0.3 *2
VDDB+0.3 *1
125125
260/10

Unit
V
V
V
V
V
V
degC
degC
degC /sec

 “Absolute Maximum Ratings” are values of safety limit for a device beyond which a device safety cannot be

guaranteed.
They do not imply that a device should be operated at these limits. The tables of “Recommended Operating
Conditions” specify conditions for device operation.

8

Recommended Operating Conditions
Table 56.
SymbolRecommended Operating Conditions
Parameter

VDDH

Supply Voltage (VDDIO, VDDB)

VDD12
Ta

Supply Voltage 1.2V (VDDM, VDDOP, VDDL, VDDA)
Operating Ambient Temperature

Condition
3.3V Drive
2.5V Drive
1.8V Drive
-

Min
3.0
2.0
1.7
1.1
-40

Typ
3.3
2.5
1.8
-

Max
3.6
3.0
2.0
1.3
105

Unit
V
V
V
V
degC

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THCV241A_Rev.2.11_E

9Consumption Current
Table 57.
SymbolICCS33
ICCS12ICCW33_1
ICCW12_1
ICCW33_2
ICCW12_2
ICCW33_3
ICCW12_3

Parameter
Pow er Dow n Supply Current

Consumption Current 1/2

Condition
PDN1=0, PDN0=0, VDDB=3.6V
PDN1=0, PDN0=0, VDDM=1.3V

Main-link : FHD 60Hz+HDRMPRF (RAW10)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 860Mbps x4Lane
V-by-One® HS = 2.16Gbps x2Lane

Main-link : FHD 60Hz+HDRMPRF (RAW10)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 1.2Gbps x4Lane
V-by-One® HS = 3.0Gbps x2Lane

Main-link : FHD 60Hz+HDRMPRF (RAW10)+Distribution
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 1.2Gbps x4Lane
V-by-One® HS = 4.0Gbps x2Lane

Min
-

Typ
0.04
8

Max
-

Unit
mA
mA

-

29.1

45

mA

-

120.5

208

mA

-

28.9

45

mA

-

139

226

mA

-

27.6

45

mA

-

143.8

228

mA

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Table 58.
SymbolICCW33_11
ICCW12_11
ICCW33_12
ICCW12_12
ICCW33_13
ICCW12_13
ICCW33_14
ICCW12_14
ICCW33_15
ICCW12_15
ICCW33_16
ICCW12_16
ICCW33_17
ICCW12_17
ICCW33_18
ICCW12_18
ICCW33_19
ICCW12_19
ICCW33_20
ICCW12_20
ICCW33_21
ICCW12_21
ICCW33_22
ICCW12_22

Parameter

Consumption Current 2/2
Condition

Main-link :720p 30fps
MPRF(RAW)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 594Mbps x1Lane
V-by-One® HS = 742.5Mbps x1Lane

Main-link :720p 30fps
MPRF(YUV422)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 600Mbps x1Lane
V-by-One® HS = 750Mbps x1Lane

Main-link :720p60fps
MPRF(RAW)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 445.5Mbps x2Lane
V-by-One® HS = 1113.75Mbps x1Lane

Main-link :1080p30fps
MPRF(RAW)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 445.5Mbps x2Lane
V-by-One® HS = 1113.75Mbps x1Lane

Main-link :720p60fps
MPRF(YUV422)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 594Mbps x2Lane
V-by-One® HS = 1485Mbps x1Lane

Main-link :1080p30fps
MPRF(YUV422)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 594Mbps x2Lane
V-by-One® HS = 1485Mbps x1Lane

Main-link :720p120fps
MPRF(RAW)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 891Mbps x2Lane
V-by-One® HS = 2227.5Mbps x1Lane

Main-link :1080p60fps
MPRF(RAW)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 891Mbps x2Lane
V-by-One® HS = 2227.5Mbps x1Lane

Main-link :720p120fps
MPRF(YUV422)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 594Mbps x4Lane
V-by-One® HS = 2970Mbps x1Lane

Main-link :1080p60fps
MPRF(YUV422)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 594Mbps x4Lane
V-by-One® HS = 2970Mbps x1Lane

Main-link :1080p120fps
MPRF(RAW)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 891Mbps x4Lane
V-by-One® HS = 2227.5Mbps x2Lane

Main-link :1080p120fps
MPRF(YUV422)
Sub-Link : active

PDN0=1, PDN1=1
MIPI = 1200Mbps x4Lane
V-by-One® HS = 3000Mbps x2Lane

Min

Typ

Max

Unit

-

27.9

45

mA

-

67.5

145

mA

-

30

45

mA

-

66.5

145

mA

-

30.5

45

mA

-

71.1

150

mA

-

30

45

mA

-

71.7

150

mA

-

28.8

45

mA

-

77.1

155

mA

-

28.5

45

mA

-

80.9

160

mA

-

30.1

45

mA

-

91.4

175

mA

-

30.7

45

mA

-

88.9

170

mA

-

28.2

45

mA

-

101

180

mA

-

29.5

45

mA

-

95.3

180

mA

-

28.6

45

mA

-

121.5

205

mA

-

29.6

45

mA

-

133.2

222

mA

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THCV241A_Rev.2.11_E

10 DC Specifications
10.1 CMOS DC Specifications
Table 59.
SymbolIIH
IIL

Parameter
LVCMOS Input Leak Current HighLVCMOS Input Leak Current Low

VIHIO

LVCMOS High Level Input Voltage

VILIO

LVCMOS Low Level Input Voltage

VOH
VOL

LVCMOS High Level Output Voltage
LVCMOS Low Level Output Voltage

CMOS DC Specifications
Condition
3.3V Drive
2.5V Drive
1.8V Drive
3.3V Drive
2.5V Drive
1.8V Drive-Min
2
0.70*VDDIO
0.65*VDDIO000
VDDIO-0.45
0

Typ
-

Max
10
10
VDDIO
VDDIO
VDDIO
0.8
0.30*VDDIO
0.35*VDDIO
VDDIO
0.45

Unit
uA
uA
V
V
V
V
V
V
V
V

10.2 MIPI Receiver DC Specifications
Table 60.
SymbolILEAK
Vcmrx(DC)
Vidth
Vidtl
Vihhs
Vilhs
Vterm-en
Zid
Vih
Vil

MIPI Receiver DC Specifications

Parameter
mipi D-PHY pin Leak Current

Condition
Pow erDow n

Min
-10

Typ
-

Max
10

Unit
uA

mipi D-PHY Voltage input common Rx

HS mode

70

200

330

mV

mipi D-PHY Voltage diff. input high thres.
mipi D-PHY Voltage diff. input low thres.
mipi D-PHY Single-end. input high limit
at HS mode
mipi D-PHY Single-end. input low limit
at HS mode
mipi D-PHY Single-ended thresholdfor HS termination enable
mipi D-PHY differential input impedance
mipi D-PHY Single-end input high thres.
mipi D-PHY Single-end input low thres.

HS modeHS mode

-70

-

70
-

mV
mV

HS mode

-

-

460

mV

HS mode

-40

-

-

mV

HS mode

-

-

450

mV

HS modeLP modeLP mode

80
550

100
-

125
880
-

ohm
mV
mV

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THCV241A_Rev.2.11_E

10.3 CML Transmitter DC Specifications

SymbolTable 61.

CML Transmitter DC Specifications

Parameter

Condition
R_ML*_DRV [1:0]=00
R_ML*_DRV [1:0]=01
R_ML*_DRV [1:0]=10
R_ML*_PRE[1:0]=00
R_ML*_PRE[1:0]=01
R_ML*_DRV [1:0]=00/01
R_ML*_PRE[1:0]=10
R_ML*_DRV[1:0]=00
R_ML*_PRE[1:0]=00
R_ML*_PRE[1:0]=01
R_ML*_PRE[1:0]=10
R_TX_SNRST=1
R_TX_SNRST=1
R_TX_SNRST=0
or PDN0=0
VDDA=1.20v

VTOD

CML Differential Mode Output VoltagePRE

CML Pre-emphasis level

VTOC

CML Common Mode Output Voltage

ITOZH
ITOZL

CML Output Leak Current HighCML Output Leak Current Low

ITOS

CML Output Short Circuit Current

Min
133
200
300
-

Typ
200
300
400
0

Max
267
400
500
-

Unit
mV
mV
mV
%

40

50

60

%

80

100

120

%

-10
-30

VDDA- VTOD
VDDA- 1.5*VTODVDDA- 2*VTOD
-

10
10

V
V
V
uA
uA

-60

-

-20

mA

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THCV241A_Rev.2.11_E

10.4 CML Bi-directional Buffer DC Specifications
Table 62.

CML Bi-directional Buffer DC Specifications

SymbolParameter

VBTH

CML Bi-Directional Buffer
Differential Input High Threshold

VBTL

VBIC

IBIH
IBIL

VBOD

VBOC

IBOZ

IBOS

RTERM

IDRIVE

Condition

Min

Typ

Max

Unit

R_BDCZ_HYS=0

-

-

50

mV

R_BDCZ_HYS=1

-

-

150

mV

-50

-

-

mV

-150

-

-

mV

-

VDDB-300

-

mV

-10

-

10

uA

-10

-

10

uA

200

300

400

mV

-

VDDB-300

-

mV

-10

-

10

uA

-

-30

-

mA

-

50

-

ohm

-

100

-

ohm

-

200

-

ohm

-

12

-

mA

-

6

-

mA

-

3

-

mA

CML Bi-Directional Buffer
R_BDCZ_HYS=0
Differential Input Low Threshold
R_BDCZ_HYS=1
R_BDCZ_TERM_**
CML Bi-Directional Buffer Input[1:0]= 2'b00
Terminated Common Voltage
R_BDCZ_DRIVE_**
DRIVE[1:0]= 2'b00
CML Bi-Directional Buffer
TCMP/N=VDD
Output Leak Current HighCML Bi-Directional Buffer
TCMP/N=0V
Output Leak Current Low
R_BDCZ_TERM_**[1:0]=2'b10
CML Bi-Directional Buffer
R_BDCZ_DRIVE_**
Differential Output Voltage[1:0]=2'b10
Diff. 100ohm terminated
R_BDCZ_TERM_**
CML Bi-Directional Buffer[1:0]=2'b00
Common Output Voltage
R_BDCZ_DRIVE_**[1:0]=2'b00
CML Bi-Directional Buffer
PDN1=0TRI-STATE Current
R_BDCZ_TERM_**
CML Bi-Directional Buffer[1:0]=2'b10
Output Short Circuit Current
R_BDCZ_DRIVE_**[1:0]=2'b11
R_BDCZ_TERM_TX/ RX[1:0]=2'b10
CML Bi-Directional Buffer
R_BDCZ_TERM_TX/ RX
Termination Registance[1:0]=2'b01
R_BDCZ_TERM_TX/ RX[1:0]=2'b00
R_BDCZ_DRIVE_TX/ RX[1:0]=2'b10
CML Bi-Directional Buffer
R_BDCZ_DRIVE_TX/ RX
Drive Current[1:0]=2'b01
R_BDCZ_DRIVE_TX/ RX[1:0]=2'b00

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THCV241A_Rev.2.11_E

11 AC Specifications
11.1 MIPI Receiver AC Specifications
Table 63.
SymbolUItSETUPtHOLDMIPI Receiver AC Specifications

Parameter
Unit Interval
Data to Clock Setup Time
Clock to Data Hold Time

Condition
-

Min
0.833
0.15*UI
0.15*UI

Typ
-

Max
12.5
-

Unit
ns
ps
ps

Max
150

Unit
ps

RDnP

RDnN
tSETUP

tHOLD

UI
RCKP

RCKN

Figure 24. MIPI Receiver setup and hold time at HS mode
11.2 CML Transmitter AC Specifications
Table 64.
SymboltTRF

CML Transmitter AC Specifications

Parameter
CML Tx Output Rise and Fall Time

Condition
-

Min
50

Typ
-

Figure 25. CML Transmitter tTRF
11.3 CML B-directional Buffer AC Specifications
Table 65.
SymboltBUI

CML B-directional Buffer AC Specifications

Parameter
Bi-Directional CML Buffer Unit Interval

Condition
REG0x0076/F6= 0x15

Min

Typ

Max

Unit

128.7

137.5

172.7

ns

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THCV241A_Rev.2.11_E

11.4 2-wire serial Master/Slave AC Specifications
Table 66.
SymbolfSCLtHD;STAtLOW
tHIGH

2-wire serial Slave AC Specifications (Sub-Link Master)tr

Parameter
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START
condition
Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals

tf

Fall time of both SDA and SCL signals

tSU;STAtHD;DATtSU;DATtSU;STO

Condition
-

Min
0.26
0.5
0.26

Typ
-

Max
1000
-

Unit
kHz
us
us
us

-

0.26

-

-

us

pull-up:2.5kΩ,
bus capacitance: 400pF
-

0
0
50
50
-

2*tOSC-

120(*1)

us
ns
ns
ns
ns

-

-

120

ns

0.26

-

-

ns

0.5

-

-

us

-

-

50

ns

300

-

-

us

Max
15.7

Unit
ns

-

us

-

us

-

us

Setup time for STOP condition
Bus free time betw een a STOPtBUFand START condition
Pulse w idth of spikes w hich must be
tSP
suppressed by the input filter(at R_IOFLT_RANGE 2:5)
Required w ait time from PDN0 hightPDS
to START condition*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.

Table 67.

2-wire serial Master AC Specifications (Sub-Link Slave)

SymboltOSC

Parameter
Cycle of internal oscillator clock

Condition
-

Min
11.7

tHD;STA

Hold time (repeated) START condition

-

-

tLOW

LOW period of the SCL clock

-

-

tHIGH

HIGH period of the SCL clock--

tHD;DATtSU;DATtr

Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals

Typ
12.5
(16×
R_I2C_SCL_HW+ 16) * tOSC
(16×
R_I2C_SCL_HW+ 16) * tOSC
(16×
R_I2C_SCL_HW+ 5) * tOSC
9*tOSC0--120(*1)

us
ns
ns
ns
ns

-

-

120

ns

0.26

-

-

ns

0
tLOW – 9 * tOSC

pull-up:2.5kΩ,tf
Fall time of both SDA and SCL signals
bus capacitance: 400pF
tSU;STO
Setup time for STOP condition*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.

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THCV241A_Rev.2.11_E

Figure 26. 2-wire serial interface timing diagram

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THCV241A_Rev.2.11_E

12 Package
0.90 Max
0.65
0.20
0.05 Max

5.00

5.00

1 PIN INDEXTOP VIEW

SIDE VIEWEXPOSED PAD OPENING

3.70
11

20
21

3.70

0.075
R

PIN1 ID
0.20 REXPOSED PAD OPENING

10

1
30
40

0.40

31
0.40

0.20

BOTTOM VIEW

Unit : mm

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THCV241A_Rev.2.11_E

13 Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note evenif errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE RELATINGTO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISING OUT OF THISPRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTES SUCCESSFULLY PROVED
BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE, HOWEVER, EVEN IN THE
AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR LOSS IF THE DISPUTE IS
CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability,
which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe design principles
such as redundant or error preventive design applied to the use of the product so as not to have our product cause any social or
public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you areencouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability whatsoever for
any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user for
any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user mustenter into a license agreement with THine or THine’s licensor to be granted of such license or right.

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