THAN0122_Rev.1.10_E

Application Note

THAN0122_Rev.1.10_E

THC63LVDM83E
Application Note
System Diagram and PCB Design Guide Line

Date
20120406
20120620

Copyright©2012 THine Electronics, Inc.

Revision
THAN0122_Rev.1.00_E
THAN0122_Rev.1.10_E

1

THine Electronics, Inc.

THAN0122_Rev.1.10_E

Contents
1. CMOS/TTL Data Timing Diagram

P.3

2. LVDS Data Timing Diagram

P.4

3. Example of System Diagram
1) 8bit CMOS/TTL Input2) 6bit CMOS/TTL Input

P.6
P.7

4. NOTE

P.8

5. Trace Example for BGA

P.9

6. PCB Design Guide Line for LVDS

P.10

Copyright©2012 THine Electronics, Inc.

2

THine Electronics, Inc.

THAN0122_Rev.1.10_E

1. CMOS/TTL Data Timing Diagram
HSYNC
DEDotCLK
R1x/G1x/B1x

#1

#2

#1#2

#3

#41022 #1023#1919 #1024
#1920
1918

#1023
#1920
#1919 #1024

TFT Panel(1024x 768)
(1920x1200)

Note :MSB

6Bit LSB
8Bit LSB

Copyright©2012 THine Electronics, Inc.

Red
R7R6R5R4R3R2R1R03

Green
G7
G6G5G4G3G2G1G0Blue
B7B6B5B4B3B2B1B0THine Electronics, Inc.

THAN0122_Rev.1.10_E

2. LVDS Data Timing Diagram

TCLKOUT(Differential)

Vdiff = 0V

Vdiff =0V

Tx+/x=A,B,C,D,E

Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0
Previous Pixel Data

Pixel Data

THC63LVDM83E Pixel Data Assign _ JEITA (6bit, 8Bit Application)
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3TC4
TC5TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD66Bit
R2
R3
R4
R5
R6
R7
G2
G3
G4G5G6G7
B2B3B4B5B6B7Hsync
Vsync
DE-8Bit
R2
R3
R4
R5R6R7G2G3G4G5G6G7B2B3B4B5B6B7Hsync
Vsync
DER0R1G0G1
B0B1
N/ANote : For 6Bit application use A to C channel and open TD+/- pin.

Copyright©2012 THine Electronics, Inc.

4

THine Electronics, Inc.

THAN0122_Rev.1.10_E

THC63LVDM83E Pixel Data Assign _VESA (6bit, 8Bit Application)
TA0
TA1
TA2
TA3
TA4
TA5
TA6TB0
TB1
TB2
TB3TB4
TB5
TB6
TC0TC1
TC2TC3TC4TC5TC6TD0TD1TD2TD3TD4TD5TD66Bit
R0R1R2R3R4R5G0G1G2G3G4G5B0B1B2B3B4B5Hsync
Vsync
DE-8Bit
R0R1R2R3R4R5G0G1G2G3G4G5B0B1B2B3B4B5Hsync
Vsync
DER6R7G6G7B6B7N/A

Note : For 6Bit application use A to C channel and open TD+/- pin.

Copyright©2012 THine Electronics, Inc.

5THine Electronics, Inc.

THAN0122_Rev.1.10_E

3. Example of System Diagram
1) 8 bit 3.3V-1.8V TTL/CMOS Input
THC63LVDM83E Setting : Falling edge / Normal swing / JEITA mapping
PCB Transmitter

PCB Receiver

VCC
F.BeadF.Bead

0.01uF
0.1uF

0.01uF
VCC
GND

Decupling Cap
X2 for 2 LVDS VCC

LVDS VCC
0.1uF

0.01uF/PDWN
R/F

PLL VCC
0.1uF

R1RS

100ohm pair cableor
PCB trace

R2CLKIN
R2
R3
R4
R5R6R7G2
G3G4G5G6G7B2B3B4B5B6B7HSYNC
VSYNC
DE
R0
R1G1
G0
B0B1

S ett ing
V CC
GND

S ett ing
VCC
GND
R10ohmNC (default)
3.3kohm

CLKIN
TA0TA1TA2TA3TA4TA5TA6
TB0TB1TB2TB3TB4TB5
TB6
TC0TC1TC2TC3TC4TC5TC6TD0TD1TD2TD3TD4TD5TD6TATA+

100ohmTBTB+

100ohm

TCTC+

100ohmTCLKTCLK+100ohm

TDTD+100ohm/P DWN
Normal Operat ion
Power Down

GND

LVDS Receiver
Circuit

GND

R/F
Input Clock Triggering Rising Edge
I nput Clock Triggering Falling E dge
R2NC
0ohm (default)
1.3kohm

COMS/TTL
3.3V
3.3V
1.8V

RS
LVDS=350mV
LVDS=200mV
LVDS=350mV

Note :zzzzzz

Regarding the /PDWN, please use switching if needed.
Regarding the R/F and RS pin, please select VCC level or GND level it depends onuser operation.
RS pin acts as VREF input pin when input voltage is set to half of high level signal input.
Example for Small Swing input (R1, R2) = (3.3kohm, 1kohm to 2.2kohm).
Please prepare the 100ohm pair cable or PCB pattern trace that is controlled with 100ohm for LVDS
signal.
Connect each Board GND
COMS/TTL input pin that not in use, it must be tied to GND.

Copyright©2012 THine Electronics, Inc.

6THine Electronics, Inc.

THAN0122_Rev.1.10_E2) 6 bit 3.3V-1.8V CMOS/TTL Input
THC63LVDM83E Setting : Falling edge / Normal swing / JEITA mapping
PCB Transmitter

PCB Receiver

VCC
F.BeadF.Bead

0.01uF
0.1uF

0.01uF
VCC
GND

Decupling Cap
X2 for 2 LVDS VCC

LVDS VCC
0.1uF

0.01uF/PDWN
R/F

PLL VCC
0.1uF

R1RS

100ohm pair cableor
PCB trace

R2CLKIN
R2R3
R4R5R6R7G2G3G4G5G6G7B2B3B4B5B6B7HSYNC
VSYNCDESetting
VCC
GNDSetting
VCC
GND
R10ohmNC (default)
3.3kohm

CLKIN
TA0TA1TA2TA3TA4TA5
TA6TB0TB1
TB2
TB3
TB4TB5
TB6TC0TC1TC2TC3TC4TC5TC6
TD0TD1TD2TD3TD4TD5TD6TATA+

100ohmTBTB+

100ohm

TCTC+

100ohmTCLKTCLK+
TDTD+

/PDWN
Normal Operat ion
Power Down

LVDS Receiver
Circuit

100ohm
OPEN
OPEN

GND

GND

R/ F
Input Clock Triggering Rising Edge
I nput Clock Triggering Falling Edge
R2NC
0ohm (default)
1.3kohm

CO MS/TTL
3.3V
3.3V
1.8V

RS
LVDS=350mV
LVDS=200mV
LVDS=350mVNote :zzzzzz

Regarding the /PDWN, please use switching if needed.
Regarding the R/F and RS pin, please select VCC level or GND level it depends onuser operation.
RS pin acts as VREF input pin when input voltage is set to half of high level signal input.
Example for Small Swing input (R1, R2) = (3.3kohm, 1kohm to 2.2kohm).
Please prepare the 100ohm pair cable or PCB pattern trace that is controlled with 100ohm for LVDS
signal.
Connect each Board GND
COMS/TTL input pin that not in use, it must be tied to GND.

Copyright©2012 THine Electronics, Inc.

7

THine Electronics, Inc.

THAN0122_Rev.1.10_E

4. Note4.1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.

4.2) GND Connection
Connect the each GND of the Board which THC63LVDM83E and Receiver on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.

4.3) Multi Drop Connection
Multi drop connection is not recommended.

TCLK+
THC63LVDM83E

Receiver IC
TCLKReceiver IC

4.4) Asynchronous useAsynchronous uses such as following systems are not recommended. If it’s not avoidable, please contact tomspsupport@thine.co.jp(for FAE mailing list)

CLKOUT
DATA
IC

TCLK+
THC63LVDM83E!

CLKOUTDATA

TCLK-

THC63LVDM83E

DATA
IC

DATA
CLKOUT

Receiver IC

IC

DATA

TCLK+
THC63LVDM83E

TCLK-!

CLKOUT
DATA

Receiver IC

TCLK+
TCLK-

CLKOUT

CLKOUT

THC63LVDM83E

Copyright©2012 THine Electronics, Inc.

TCLK+

IC

TCLK-

8

THine Electronics, Inc.

THAN0122_Rev.1.10_E

5. Trace Example for BGA

TOP VIEW
1234567A

TA6TA5TA4TA3TA2TA1TA0A

B

TB4TD3TD2TD1TD0TA-TA+

B

C

TB5TB0GND

VCC

RS

TB-

TB+C

D

TB6TB1GND

LVDS
VCC

LVDS
VCC

TC-TC+DE

TC0TB2GND

PLL
VCC

R/F

TCLK-

TCLK+

E

F

TC1TB3

TD4TD5TD6TD-

TD+

F

GTC2

TC3TC4

TC5TC6

CLKIN

/PWDN

G1234567

R0
R1R2R3
R4R5R6R7B0B1G0
G1G2
G3G4G5G6G7TA6TA5TA4TA3TA2TA1TA0TB4TD3TD2TD1TD0TA-TA+

TB5TB0GNDVCCRS

TB-TB+

TB6

TB1

GND

LVDS
VCC

LVDS
VCC

TC-TC+

TC0

TB2

GND

PLL
VCC

R/F

TCLK-

TCLK+

TC1
TC2

TB3
TC3

TD4TC4

TD5TC5TD6
TC6

TDCLKIN

TD+/PWDN

B2B3B4B5B6B7Copyright©2012 THine Electronics, Inc.

9

THine Electronics, Inc.

THAN0122_Rev.1.10_E

6. PCB Design Guide Line
General Guidelinez

Use 4 layers PCB (minimum).

z

Locate by-pass capacitors adjacent close to the device pins to a maximum extent.

zMake the loop minimum which is consist of Power line and GND line.

z

Use large GND plane.

z

Separate VDD power supply for each block via ferrite bead.

LVDS Tracez

Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector and cable) should be wellbalanced. (Keep all these differential impedance and the length of media as same as possible)z

Minimize the distance between traces of a pair (S1) to maximize common mode rejection. See following figure.

z

Place adjacent LVDS trace pair at least twice (>2 x S1) as far away as possible.

z

Avoid 90 degree bends and sharp angles.

z

Minimize the number of VIA on LVDS traces.

zMatch impedance of PCB trace, connector, cable and termination to minimize reflections (emissions) for cabledapplications (typically 100ohm differential mode characteristic impedance).

z

Place terminal resistor close to the Receiver pins to a maximum extent.

z

To place common mode choke coil is desired for EMI reduction.

S1> 2 x S1

GND+Signal

Copyright©2012 THine Electronics, Inc.

-Signal10+Signal-SignalTHine Electronics, Inc.

THAN0122_Rev.1.10_E

Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to thecustomer's design. We are not responsible for possible errors and omissions in this material. Please note if errors oromissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties thecontents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will beexempted from the responsibility unless it directly relates to the production process or functions of the product.
5. This product is presumed to be used for general electric equipment, not for the applications which require very highreliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control
equipment). Also, when using this product for the equipment concerned with the control and safety of thetransportation means, the traffic signal equipment, or various Types of safety equipment, please do it after
applying appropriate measures to the product.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently
redundant or error preventive design applied to the use of the product so as not to have our product cause anysocial or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods
under the Foreign Exchange and Foreign Trade Control Law.

THine Electronics, Inc.
sales@thine.co.jp

Copyright©2012 THine Electronics, Inc.

11

THine Electronics, Inc.