THC63LVD1022_Rev.1.03_E

THC63LVD1022
30Bit Color/150Mpps Dual-Link LVDS to LVCMOS converter

General Description･Medical Equipment Monitor

The THC63LVD1022 LVDS (Low Voltage Differential
Signaling) converter is designed to support pixel datatransmission between Host and Flat Panel Display up to
Full-HD 1080p resolutions.
The THC63LVD1022 receives dual channel LVDS data stream
and transmits LVTTL/LVCMOS data through Dual Pixel Link
Input / Single Link output conversion.
At a transmit data of 150Mpixel/sec, 30bits/pixel and 5bits oftiming and control data (HSYNC, VSYNC, DE) are received at
an effective rate of 525Mbps per LVDS channel.

Features･20MHz to 75MHz 30bits/pixel dual-Link LVDS input･Up to 150MHz 30bit s/pixel single port LVCMOS output･Operating Temperature Range : 0 to 85C
･LVDS input skew margin: ±400ps at 75MHz･Dual input / Single output mode [clkout = 2x clkin]･Output Enable / Disable mode supported･No Special Start-up Sequence Required･100pin TQFP Package･3.3V single voltage power supply･PLL requires no external components

Application･Compliant with RoHS and REACH･Security Camera / Industrial Camera･Medium and Small Size Panel･Tablet PC / Notebook PC･Multi Function Printer･Industrial Equipment

Block Diagram

Figure 1. Block Diagram

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Pin Diagram
THC63LVD1022

GND
VCC
B0
B1
B2
B3
GND
VCC
B4
B5
B6
CAP
GND
VCC
B7
B8
B9
GND
VCC
HSYNC
VSYNC
DE
CAP
GND
VCC

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

GND
VCC
R9
R8
R7
GND
VCC
TEST2
R6
R5
R4
CAP
GND
VCC
R3
R2
R1
R0
GND
VCC
MAP0
OE
CAP
GND
VCC

Figure 2. Pin Diagram

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Pin Description
Table 1. Pin Description
Pin Name
RA1+, RA1RB1+, RB1RC1+, RC1RD1+, RD1RE1+, RE1RCLK1+,RCLK1RA2+, RA2RB2+, RB2RC2+, RC2RD2+, RD2RE2+, RE2RCLK2+,RCLK2TEST, TEST2

Pin #
2, 1
4, 3
6, 5
10, 9
12, 11
8, 7
15, 1417, 1619, 1823, 2225, 2421, 2072, 43

OE

29

MLSB

71

MAP2 ~ 062, 55, 30

TypeDescription

LVDS 1st Link Data In.

LVDS
Input

LVDS Clock Input for 1st Link.

LVDS 2nd Link Data In.

LVDS Clock Input for 2nd Link.
Reserved
L: Normal Operation(Table. 10)
Output Enable
H: Normal Operation
L: Fix Output signals(Hold the previous logic
value)
Output bit order selection
H: MSB = 9 / LSB = 0
L: MSB = 0 / LSB = 9
Output color mapping selection
LVCMOS/TTL
Input

MAP0:1:2
HHH
HHL
HLH
HLL
LHH
LHL
LLH
LLL

DE
VSYNC
HSYNC
R9 ~ 0G9 ~ 0B9 ~ 0
CLKOUT
VCC
GND

CAP

97
96
95
48, 47, 46, 42, 41, 40, 36,
35, 34, 33
67, 66, 65, 61, 60, 59, 54,
53, 52, 51
92, 91, 90, 86, 85, 84, 81,
80, 79, 78
75
26, 31, 37, 44, 49, 56, 63,
70, 74, 77, 83, 89, 94, 100
13, 27, 32, 38, 45, 50, 57,
64, 69, 73, 76, 82, 88, 93,
99

Bch
B
G
G
R
B
R
B
B

Data Enable Output
Vsync Output
Hsync Output
LVCMOS/TTL
OutputPixel Data Output(Rch)
Pixel Data Output(Gch)Pixel Data Output(Bch)
Clock Output
Power Supply Pins-

28, 39, 58, 68, 87, 98

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Rch
R
R
B
B
G
G
R
R

RGB
Gch
G
B
R
G
R
B
G
G

Ground Pins

Decoupling cap.
External 0.1uF or more capacitancerequired.

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Absolute Maximum Ratings
Table 2. Absolute Maximum Rating
Min
-0.3
-0.3
-0.3
-55

Parameter
Supply Voltage (VCC)
LVCMOS/TTL Input Voltage
LVDS Input Pin
Junction Temperature
Storage Temperature

Max
+4.0
VCC + 0.3
VCC + 0.3
+125
+125

Unit
V
V
V
C
C

Recommended Operating Conditions
SymbolTa-

Table 3. Recommended Operating Conditions
ParameterMin
TypAll Supply Voltage
3.0
3.3
Operating Ambient Temperature
025
LVDS Input
20
Clock Frequency
LVCMOS Output
40
-

Max
3.6
+85
75
150

Unit
V
C
MHz

“Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics” specify conditions for device operation.
“Absolute Maximum Rating” values also include behavior of overshooting and undershooting.

Equivalent LVDS Input Schematic Diagram

CMP

min : 68K
typ : 124K
max : 243K

LVDS_InP

7.34KΩ

73.4KΩAMP
LVDS_InN
min : 68K
typ : 124K
max : 243K

Figure 3. LVDS Input Schematic Diagram

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Power Consumption
Table 4. Power Consumption
Over recommended operating supply and temperature range unless otherwise specified
SymbolParameter
Conditions
Typ*
Max
Unit
LVDS Receiver
Operating Current
139
mA
RL=100, CL=5pF, RCLK=75MHz
Gray Scale Pattern(Fig.4)IRCCW
LVDS Receiver
Operating Current
mA
RL=100, CL=5pF, RCLK=75MHz
Worst Case Pattern(Fig.5)* Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

CLKOUT
R0, G0, B0
R1, G1, B1
R2, G2, B2
R3, G3, B3
R4, G4, B4
R5, G5, B5
R6, G6, B6
R7, G7, B7
R8, G8, B8
R9, G9, B9Figure 4. Grayscale PatternFigure 5. Worst Case Pattern

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Electrical Characteristics
Table 5. LVCMOS/TTL DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
SymbolParameter
Conditions
Min
Typ*
Max
Unit
VIH
High Level Input Voltage
RS=VCC or GND
2.0
VCC
V
VIL
Low Level Input Voltage
RS=VCC or GND
GND
0.8
V
VOH
High Level Output Voltage
IOH=12mA(Data), 16mA(Clk)
2.4
V
VOL
Low Level Output Voltage
IOH=12mA(Data), 16mA(Clk)
0.4
V
IIL
Input Leakage Current
1
A
PD
Power Dissipation
0.46
W* Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

SymbolVIC

Table 6. LVDS Receiver DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Parameter
Conditions
Min
Typ*
Max
Unit
Differential Input Common Voltage
0.6
1.2
1.8
V

|VID|
VTH
VTL

Differential Voltage
Differential Input High Threshold
VIC = 1.2V
Differential Input Low Threshold
VIC = 1.2V
IINLVDSLVDS Input Current*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

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100
-100
-

-

600
100
20

mV
mV
mV
A

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Table 7. LVCMOS/TTL & LVDS Receiver AC Specifications
Over recommended operating supply and temperature range unless otherwise specified
SymbolParameter
Min
Typ
Max
Unit
RCLK1/2
13.3
50
tRCP
CLK Periodns
CLKOUT
6.6
25
tRCH
CLKOUT High Time
2/7 TRCP
4/7 TRCP
5/7 TRCPnstRCL
CLKOUT Low Time
5/7 TRCP
3/7 TRCP
2/7 TRCP
ns
tDOUT
LVCMOS Data OUT Period
6.6
25
ns
tRS
LVCMOS Data Setup to CLKOUT
2.0
4.6
ns
tRH
LVCMOS Data Hold to CLKOUT
2.0
4.6
ns
tSK
Receiver Skew Margin
-400
400
ps
tRIP1
Input Data Position0
- tSK
0
+ tSK
ns
tRIP0
Input Data Position1
tRCIP /7- tSKtRCIP /7
tRCIP /7+ tSKnstRIP6
Input Data Position2
2tRCIP /7- tSK
2tRCIP /7
2tRCIP /7+ tSKnstRIP5
Input Data Position3
3tRCIP /7- tSK
3tRCIP /7
3tRCIP /7+ tSKnstRIP4
Input Data Position4
4tRCIP /7- tSK
4tRCIP /7
4tRCIP /7+ tSKnstRIP3
Input Data Position5
5tRCIP /7- tSK
5tRCIP /7
5tRCIP /7+ tSKnstRIP2
Input Data Position6
6tRCIP /7- tSK
6tRCIP /7
6tRCIP /7+ tSK
nstRPLL
Phase Lock Loop Set
1ms* Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

AC Timing Diagrams
LVCMOS Output

Figure 6. CLKOUT Transmission Time

Figure 7. CLKOUT Period, High/Low Time, Setup/Hold Timing
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LVDS Input Data PositiontRCIP

RCLKx +

Vdiff = 0V

Vdiff = 0V

(Differential)
X = 1, 2

RAx +/-

RAx6 RAx5 RAx4 RAx3 RAx2 RAx1 RAx0

RBx +/-

RBx6 RBx5 RBx4 RBx3 RBx2 RBx1 RBx0

RCx +/-

RCx6 RCx5 RCx4 RCx3 RCx2 RCx1 RCx0

RDx +/-

RDx6 RDx5 RDx4 RDx3 RDx2 RDx1 RDx0

REx +/-

REx6 REx5

REx4 REx3

Previous Cycle

REx2 REx1 REx0

Current Cycle

Next Cycle

tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2

Figure 8. LVDS Input Data Position

Phase Lock Loop Set Time

RCLK+/2.0V

VCC

tRPLL

CLKOUT

VCC/2

Figure 9. PLL Lock Set Time

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LVDS Data Timing Diagram

Figure 10. LVDS Data Timing Diagram

Table 8. LVDS Input Data Mapping
LVDS Input Data Mapping (MLSB=High, MAP[2:0]=High)
LVDS
LVDS
Input Data
1st pix data
Input Data
2nd pix datastnd
(1 Pixel Data)(2 Pixel Data)
RA10
R4 (n)RA20
R4 (n+1)
RA11
R5 (n)RA21
R5 (n+1)
RA12
R6 (n)RA22
R6 (n+1)
RA13
R7 (n)RA23
R7 (n+1)
RA14
R8 (n)RA24
R8 (n+1)
RA15
R9 (n)RA25
R9 (n+1)
RA16
G4 (n)RA26
G4 (n+1)RB10
G5 (n)RB20
G5 (n+1)
RB11
G6 (n)RB21
G6 (n+1)
RB12
G7 (n)RB22
G7 (n+1)
RB13
G8 (n)RB23
G8 (n+1)
RB14
G9 (n)RB24
G9 (n+1)
RB15
B4 (n)RB25
B4 (n+1)
RB16
B5 (n)RB26
B5 (n+1)
RC10
B6 (n)RC20
B6 (n+1)
RC11
B7 (n)RC21
B7 (n+1)
RC12
B8 (n)RC22
B8 (n+1)
RC13
B9 (n)RC23
B9 (n+1)
RC14
HSYNC
RC24
RC15
VSYNC
RC25
RC16
DE
RC26
RD10
R2 (n)RD20
R2 (n+1)
RD11
R3 (n)RD21
R3 (n+1)
RD12
G2 (n)RD22
G2 (n+1)
RD13
G3 (n)RD23
G3 (n+1)
RD14
B2 (n)RD24
B2 (n+1)
RD15
B3 (n)RD25
B3 (n+1)
RD16
RD26
RE10
R0 (n)RE20
R0 (n+1)
RE11
R1 (n)RE21
R1 (n+1)
RE12
G0 (n)RE22
G0 (n+1)RE13
G1 (n)RE23
G1 (n+1)
RE14
B0 (n)RE24
B0 (n+1)
RE15
B1 (n)RE25
B1 (n+1)
RE16
RE26
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Output Disable Mode
Input Signal
OE
TEST
TEST2
MAP0
MAP1
MAP2
Other Input Signals

Table 9. Output Disable Mode Setting
Normal Mode Setting
Output Disable Mode Setting
H
L
L
H
L
L
X
H
X
H
X
H
X
X

Table 10. Output Disable Mode Signal Definition
Output Signal
Normal Mode
Output Disable Mode
B9
L
Normal Operation
Other Output Signals
Hi-Z

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Typical Connection

Figure 11. Typical Connection Diagram

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Notes
1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.

2) GND Connection
Connect each GND of the PCB which THC63LVD1022 and LVDS-Tx on it.
to place GND cable as close to LVDS cable as possible.

It is better for EMI reduction3) Multi Drop Connection
Multi drop connection is not recommended.

Figure 12. Multi Drop Connection4) Asynchronous use
Asynchronous using such as following system is not recommended.

Figure 13. Asynchronous Use

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Package

Figure 14. Package Diagram

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Reference of Land Pattern
CY1= 17.34

HD=16.000

e= 0.500

D= 14.00

Ttyp.=0.60
1.15

Gmin= 14.40

b= 0.200
Xmax=
0.370

Zmax= 16.70

Zmax/2
Unit : [mm]Figure 15. Reference of Land Pattern

The recommendation mounting method of THine device is reflow soldering.
The reference pattern is using the calculation result on condition of reflow soldering.

Notes
This land pattern design is a calculated value based on JEITA ET-7501.
Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity ofconnection, the density of mounting, and the solder paste used, etc… The optimal land pattern size changes
with these parameters. Please use the value shown by the land pattern as reference data.

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Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

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