THAN0060_Rev.1.50_E

Application Note

THAN0060-Rev.1.50_E

THCV215/THCV216 Application Note
System Diagram and PCB Design Guideline

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Contents
Contents................................................................................................................................................................... 2
Application Diagrams.............................................................................................................................................. 3
Dual/10bit(30bit per pixel) with Maximum Pre-emphasis ............................................................................. 3
Dual/8bit(24bit per pixel) without Pre-emphasis ............................................................................................ 4Single/8bit(24bit per pixel) without Pre-emphasis.......................................................................................... 5
Recommendations for Power Supply ...................................................................................................................... 6
Recommended Power Supply for THCV215................................................................................................... 6
Recommended Power Supply for THCV216................................................................................................... 7
Note ......................................................................................................................................................................... 8
PCB Layout Considerations .................................................................................................................................. 10

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Application Diagrams
Dual/10bit(30bit per pixel) with Maximum Pre-emphasis
Setting SDSEL HIGH places THCV215/THCV216 in the Dual Link mode.
Setting COL1 HIGH and COL0 LOW results in the 10bit mode (30bit per pixel.)
Setting PRE1 HIGH and PRE0 LOW maximizes the strength of pre-emphasis.

LVDS
Driver

THCV215
TLA0TLA0+TLB0TLB0+
TLC0TLC0+TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+TLB1TLB1+
TLC1TLC1+TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+

Power Down

*3

0.1mF

RX0n
RX0p

TX1n
TX1p

RX1n
RX1p

VDL
10kW

HTPDN
LOCKN

HTPDN
LOCKN

RLA0RLA0+RLB0RLB0+
RLC0RLC0+RLCLK0RLCLK0+
RLD0RLD0+RLE0RLE0+
RLF0- OPEN
RLF0+
RLA1RLA1+RLB1RLB1+
RLC1RLC1+RLCLK1RLCLK1+
RLD1RLD1+
RLE1RLE1+
RLF1- OPEN
RLF1+

PDN

PDN

SDSEL
COL1
COL0
PRE1
PRE0

SDSEL
COL1
COL0

TP

RDY

VDL

DRV1
DRV0
Reserved0

VDL
NC

0.1mF

TX0n
TX0p

LVDS
Receiver

100W

Power DownVDLSDSEL=H-> DualCOL1=H&COL0=L-> 10bit(30bpp)
PRE1=H&PRE0=L-> Pre-emphasis Max.
RDY=H indicates Rx
is powered up and its
Pll is locked to theincomming signals

THCV216VDL

SDSEL=H-> DualCOL1=H&COL0=L-> 10bit(30bpp)

Reserved1
Reserved2
Reserved3
VDH

*2

*3

Reserved1

0Ω

RS

TP

0Ω

NC

GND

*1
*2
*3

GND

indicates microstrip lines or cables with their differential characteristic impedance being 100ΩConnect GNDs of both Tx and Rx PCB
Field BET Operation. Please see the datasheet for details. ( THCV215-216_Rev.x.xx_E.pdf )Copyright© 2015, THine Electronics, Inc.

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Dual/8bit(24bit per pixel) without Pre-emphasis
Setting SDSEL HIGH places THCV215/THCV216 in the Dual Link mode.
Setting COL1 LOW and COL0 HIGH results in the 8bit mode (24bit per pixel.)
Setting PRE1 LOW and PRE0 LOW disables pre-emphasis.

LVDS
Driver

THCV215
TLA0TLA0+TLB0TLB0+
TLC0TLC0+TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+TLB1TLB1+
TLC1TLC1+TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+

Power Down

0.1mF

0.1mF

TX0n
TX0p

RX0n
RX0p

TX1n
TX1p

RX1n
RX1p

VDL
10kW

HTPDN
LOCKN

HTPDN
LOCKN

LVDS
Receiver

100W

RLA0RLA0+RLB0RLB0+
RLC0RLC0+RLCLK0RLCLK0+
RLD0RLD0+RLE0RLE0+
RLF0RLF0+
RLA1RLA1+RLB1RLB1+
RLC1RLC1+RLCLK1RLCLK1+
RLD1RLD1+
RLE1RLE1+RLF1RLF1+

PDN

PDN

SDSEL
COL1
COL0
PRE1
PRE0

SDSEL
COL1
COL0

OPEN
OPEN

OPEN
OPEN
Power DownVDLSDSEL=H-> DualCOL1=L&COL0=H-> 8bit(24bpp)
PRE1=L&PRE0=L-> No Pre-emphasis.
RDY=H indicates Rx
is powered up and its
Pll is locked to theincomming signals

TP

RDY

VDL

DRV1
DRV0
Reserved0

VDL*3

THCV216NC

VDL

SDSEL=H-> DualCOL1=L&COL0=H-> 8bit(24bpp)

Reserved1
Reserved2
Reserved3
VDH

*2

*3

Reserved1

0Ω

RS

TP

0Ω

NC

GND

*1
*2
*3

GND

indicates microstrip lines or cables with their differential characteristic impedance being 100ΩConnect GNDs of both Tx and Rx PCB
Field BET Operation. Please see the datasheet for details. ( THCV215-216_Rev.x.xx_E.pdf )Copyright© 2015, THine Electronics, Inc.

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Single/8bit(24bit per pixel) without Pre-emphasis
Setting SDSEL LOW places THCV215/THCV216 in the Single Link mode.
Setting COL1 LOW and COL0 HIGH results in the 8bit mode (24bit per pixel.)
Setting PRE1 LOW and PRE0 LOW disables pre-emphasis.

LVDS
Driver

THCV215
TLA0TLA0+TLB0TLB0+
TLC0TLC0+TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+TLB1TLB1+
TLC1TLC1+TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+

Power Down

0.1mF

0.1mF

TX0n
TX0p

RX0n
RX0p

TX1n
OPEN
TX1p

OPEN
or GND

RX1n
RX1p

VDL
10kW

HTPDN
LOCKN

HTPDN
LOCKN

LVDS
Receiver

100W

RLA0RLA0+RLB0RLB0+
RLC0RLC0+RLCLK0RLCLK0+
RLD0RLD0+RLE0RLE0+
RLF0RLF0+
RLA1RLA1+RLB1RLB1+
RLC1RLC1+RLCLK1RLCLK1+
RLD1RLD1+
RLE1RLE1+RLF1RLF1+

PDN

PDN

SDSEL
COL1
COL0
PRE1
PRE0

SDSEL
COL1
COL0

OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
Power DownVDLSDSEL=L-> Single
COL1=L&COL0=H-> 8bit(24bpp)
PRE1=L&PRE0=L-> No Pre-emphasis.
RDY=H indicates Rx
is powered up and its
Pll is locked to theincomming signals

TP

RDY

VDL

DRV1
DRV0
Reserved0

VDL*3

THCV216NC

VDL

SDSEL=L-> Single
COL1=L&COL0=H-> 8bit(24bpp)

Reserved1
Reserved2
Reserved3
VDH

*2

*3

Reserved1

0Ω

RS

TP

0Ω

NC

GND

*1
*2
*3

GND

indicates microstrip lines or cables with their differential characteristic impedance being 100W
Connect GNDs of both Tx and Rx PCB
Field BET Operation. Please see the datasheet for details. ( THCV215-216_Rev.x.xx_E.pdf )Copyright© 2015, THine Electronics, Inc.

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Recommendations for Power Supply

Separate all the power domains in order to avoid unwanted noise coupling between noisy digital andsensitive analog domains.
Use high frequency ceramic capacitors of 10nF or 0.1μF as bypass capacitors between power and groundpins. Place them as close to each power pin as possible.
Adding 4.7μF capacitors to PLL's power pins, along with the smaller bypass capacitors, is recommended.

Recommended Power Supply for THCV215

10nF

3.3V

1.8V

LAVDH
10uF

VDL
10uF
CAVDL
10uF
CPVDL
10uF
LPVDL
10uF

10nF

Copyright© 2015, THine Electronics, Inc.

LAGND 1LAVDH 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LAVDH 31
LAGND 32

THCV21564 LPVDL
63 LPGND
62
61
60
59
58
57
56
55 VDL54 GND
53 CAVDL
52 CAGND
51
50
49 CAGND
48
47
46 CAGND
45 CAVDL
44 CPGND
43 CPVDL
42
41
40
39
38
37
36 GND
35 VDL34 LPGND
33 LPVDL

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10nF

4.7uF

10nF

10nF

10nF

10nF

4.7uF

10nF

10nF

4.7uF

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Recommended Power Supply for THCV216

LPVDH
3.3V

10uF

4.7uF

10nF

LAVDH
10uF
VDL
1.8V

10uF
CAVDL

10nF

10uF
CPVDL0

4.7uF

10nF

10uF
10nF

CPVDL1
10uF

10nF

4.7uF

10nF

10nF

4.7uF

10nF

LPVDH 1
LPGND 2
3
4
5
6
7
VDL 8
GND 9
CPVDL0 10
CPGND0 11
CAVDL 12CAGND 13
14
15
CAGND 16
CAGND 17
18
19
CAGND 20CAVDL 21
CPGND1 22
CPVDL1 23
GND 24
VDL 25
26
27
28
29
30
LPGND 31
LPVDH 32

THCV21664 LAGND
63 LAVDH
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34 LAVDH
33 LAGND

10n
F

10n
F

Note
1) HTPDN/LOCKN connection between high VDD V-by-One® HS transmitter and THCV216

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When using THCV216 with high VDD V-by-One® HS transmitter, user have to take care of HTPDN/LOCKN
connection because THCV216 HTPDN/LOCKN output pins absolute maximum ratings are VDL+0.3V;
therefore high VDD pull-up at transmitter side can cause violation of usage. Users are supposed to connect
those HTPDN/LOCKN line between two devices with appropriate level-shifter configuration.
V-by-OneHS Tx side PCB

V-by-OneHS Rx side PCB
1.8V
3.3V
10kΩ

THCV216
G
D S

10kΩ
HTPDN

MOSFET(Vth<1.2V)
V-by-OneHS Transmitter(Ex. THCV217,THCV233)

1.8V
3.3V
10kΩ

1.8V Tolerant
Transistor
G
D S

10kΩ
LOCKN

MOSFET(Vth<1.2V)

2)LVDS input pin connection
When LVDS line is not drived from the previous device, the line is pulled up to 3.3V internally in
THCV215.This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose
operating condition is lower voltage power supply than 3.3V. This phenomenon may happen at power on phaseof the whole system including THCV215. One solution for this problem is PD=L control during no LVDS input
period because pull-up resistors are cut off at power down state.
If this situation is not avoidable and PD=L is hard to apply, there still is several remedy; therefore pleasecontact tomspsupport@thine.co.jp(for FAE mailing list)

LVDS Tx side PCB

LVDS Rx side PCB
VDD

Low VDD

THCV215
LVDS Txor
LVDS Tx
integrated
device
LVDS input bufferInternal circuit of THCV2153)Power On Sequence
Don’t input RCLK#+/- before THCV215 is on in order to keep absolute maximum ratings.
If it is not avoidable, please contact tomspsupport@thine.co.jp(for FAE mailing list)4)Unused LVDS input pins
First, select appropriate color depth with COL0,COL1 pins. If there are inevitably remained LVDS no input
pins which are originally active, tie them to GND.
Second, avoid the situation that LVDS input pins in use are open. You can use PDN=L control during no LVDS

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input period to cut off pulled-up resistors.
5)Cable Connection and Disconnection
Don’t connect and disconnect the LVDS cable, when the power is supplied to the system.
6)GND Connection
Connect the each GND of the PCB which Transmitter, Receiver and THCV215 on it. It is better for EMI
reduction to place GND cable as close to LVDS cable as possible.
7)Multi Drop Connection
Multi drop connection is not recommended. If it is not avoidable, please contact tomspsupport@thine.co.jp(for FAE mailing list)

TCLK1,2THCV216

LVDS RxTCLK1,2+
LVDS Rx

8)Multiple counterpart use
Multiple counterpart use such as following systems are not recommended. If it is not avoidable, please check if
Data Sheet p.15 tTISK spec can be kept or not and more further, please contact tomspsupport@thine.co.jp
CLKOUTDATAICLVDS Tx

RCLK1RCLK1+
RCLK2-

CLKOUT
DATA(for FAE mailing list)

LVDS Tx

THCV215

RCLK2+

Multiple counterpart use such as following systems are not recommended. If it is not avoidable, please contact tomspsupport@thine.co.jp
TCLK1TCLK1+
THCV216(for FAE mailing list)

CLKOUT
LVDS RxDATA

LVDS RxDATAIC

TCLK2TCLK2+9) Multiple device connection
HTPDN and LOCKN signals are supposed to be connected proper for their purpose like the following figure.
HTPDN should be from just one THCV216 to multiple Tx because its purpose is only ignition of all Tx.
LOCKN should be connected so as to indicate that all Rx CDR become ready to receive normal operation data.
LOCKN of Tx side can be simply split to multiple Tx.

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There could be other applicable circuits like ‘OR gate of LOCKN’, ‘npn transistor with resistors as inverter’, etc.
Also possible time difference of internal processing time (THCV215 tTCD and THCV216 tRDC) on multiple
data stream must be accommodated and compensated by the following destination device connected to multiple
THCV216, which may have internal FIFO.

THCV215

THCV216

HTPDN

HTPDN

LOCKN

LOCKN

Ex. synchronizedTime diff. comes up

THCV215

THCV216

HTPDN

HTPDN

LOCKN

LOCKN

clkin.1

clkout.1
FIFO

PDN
SourceDeviceDestination
Device

FIFO
clkin.2

clkout.2

PDN

Internal processing time tTCD

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Internal processing time tRDC

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PCB Layout Considerations








Use at least four-layer PCBs with signals, ground, power, and signals assigned for each layer. (Refer tofigure below.)
PCB traces for high-speed signals must be single-ended micorstirp lines or coupled microstrip lines whose
differential characteristic impedance is 100Ω.
Minimize the distance between traces of a differential pair (S1) to maximize common mode rejection andcoupling effect which works to reduce EMI(Electro-Magnetic Interference).
Route differential signal traces symmetrically.
Avoid right-angle turns or minimize the number of vias on the high speed traces because they usually cause
impedance discontinuity in the transmission lines and degrade the signal integrity.
Mismatch among impedances of PCB traces, connectors, or cables also caused reflection, limiting the
bandwidth of the high-speed channels.
Using common-mode filter on differential traces is desirable to reduce EMI. Pay attention on data-rate
driven noise. For example, if data-rate is 1.5Gbps, common mode choke coil of 1.5GHz common mode
impedance is desired to be high, while 1.5GHz differential impedance is low.

PCB Cross-sectional View
for Microstrip Lines> 3 x S1

S1

GND

> 3 x S1

GND

Layer1: Signals
Layer2: Ground
Layer3: Power
Layer3: Signals

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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply
to the customer's design. We are not responsible for possible errors and omissions in this material. Please
note if errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.

5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video
device, office automation device, communication device, consumer electronics, smartphone, featurephone, and amusement machine device. This product must not be used for applications that require
extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear
power control device, combustion chamber device, medical device related to critical care, or any kindof safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") inthis data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product otherthan the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent
that the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with acertain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged tohave sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems
necessary to support warranty for performance of this product. Except where mandated by applicablelaw or deemed necessary by THine based on the user’s request, testing of all functions and performanceof the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings ormalfunction, if pins of the product are shorted by such as foreign substance. The damages may cause asmoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.

THine Electronics, Inc.
sales@thine.co.jp

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