THCS253_Rev.1.30_E

THCS253
IOHA:B 8B10B Serial Transceiver

1.

2.

Features

The THCS253 is a transceiver IC with serializer
and deserializer on a single chip that aggregates 32bit GPIO and 2-wire serial interface signals andconverts them into two pairs of differential signals fortransmission and reception.
The THCS253 has two modes: SYNC mode and
ASYNC mode. In SYNC mode, the uplink anddownlink high-speed transmission signals operate
synchronously, driven by the reference clock signal
from the primary chip side. In ASYNC mode, theuplink and downlink high-speed transmission signals
operate asynchronously, driven by the clock signals
from both the primary and secondary chips. The
reference clock can be selected from either theinternal OSC clock or the external input clock.



By accessing internal registers via the 2-wire serialinterface, the 32-bit GPIO direction and output buffer
type can be customized for each pin.
The 8B10B encoding and decoding used in the
THCS253 provides high robustness, DC balanced
signals, and easy connection to optical/wirelesscommunication devices.
The built-in adaptive equalizer allows for flexible
cable selection, and the CML driver with preemphasis allows for even longer cable transmissions.







Up to 32-bit GPIOs
Internal oscillator mode requires no external
clock signal input
Uplink and downlink synchronous mode with
one-sided reference clock drive
Uplink and downlink asynchronous mode withboth side reference clocks driven
Output buffer selectable between open-drain andpush-pull
2-wire serial interface fast mode can be bridgedStandby mode for low-power operation
Adaptive equalizer supports high-loss
transmission media
8B10B encoding/decoding
Digital noise filters can be set for input andoutputError detection and notification
External reference clock frequency: 9-133.3MHz
Built-in spread spectrum clock generator
Single power supply operation: 1.7 V - 3.6 V
Operating ambient temperature range: -40°C to
85°C
Compliant with RoHS and REACH

3.

Overview












Block diagram
THCS253 (Primary Chip)

THCS253 (Secondary Chip)

REFEN

TXN
TXP

Rx
(Deserializer)

2-wire serial interface
SDA/SCL

LVCMOS I/O

RXN
RXP

RXP
RXN

Formatter2-wire serial interface
SDA/SCL

TXP
TXN

Tx
(Serializer)

GPIO D16/15･･D31/D0

Formatter

REFOUT

LVCMOS I/OGPIO D0/D31・・D15/D16

LDO

PLL
Tx
(Serializer)

SSCG

REFIN

Rx
(Deserializer)

OSC

GPIO D15/D16・・D0/D31
REFOUT
GPIO D31/0･･D16/D15
REFIN

PLL

LDO

SSCG

OSC
REFEN
SYNCEN

Copyright©2024 THine Electronics, Inc.

1/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

Contents
1.

Overview ......................................................................................................................................................... 1

2.

Features ........................................................................................................................................................... 1

3.

Block diagram ................................................................................................................................................. 1

4.

Pin configuration ............................................................................................................................................. 4

5.

Pin description ................................................................................................................................................. 5
5.1.

Pin setting and combination of chip mode .............................................................................................. 96.

Absolute maximum rating ............................................................................................................................. 10

7.

Recommended operatingconditions .............................................................................................................. 10

8.

Electrical characteristics ................................................................................................................................ 11
8.1.

Current consumption ............................................................................................................................. 11

8.2.

LVCMOS/Analog input DC specifications ........................................................................................... 13

8.3.

LVCMOS AC characteristics ................................................................................................................. 14

8.4.

CML DC characteristics ........................................................................................................................ 18

8.5.

CML AC characteristics ........................................................................................................................ 18

8.6.

2-wire serial interface DC/AC characteristics ....................................................................................... 229.

CML Line diagram ........................................................................................................................................ 23
9.1.

10.

CML input diagram ............................................................................................................................... 23
Function ..................................................................................................................................................... 24

10.1.

Function overview ............................................................................................................................. 24

10.2.

Power supply ..................................................................................................................................... 24

10.2.1.

Internal regulator output/input function (CAPOUT, CAPINA, CAPINP) .................................... 24

10.3.

Chip Operating state .......................................................................................................................... 25

10.4.

Chip operation mode ......................................................................................................................... 25

10.4.1.

Chip configuration ......................................................................................................................... 25

10.4.2.

Operating clock mode select.......................................................................................................... 26

10.4.3.

Operating clock select ................................................................................................................... 26

10.4.4.

Combination of operating modes .................................................................................................. 28

10.5.

Byte mode and frequency range ........................................................................................................ 31

10.6.

2-wire serial interface ........................................................................................................................ 32

10.6.1.

2-wire serial interface setting ........................................................................................................ 32

10.6.2.

Clock stretching ............................................................................................................................. 33

10.6.3.

Device Address .............................................................................................................................. 34

10.6.4.

2-wire serial controller / target register address space ................................................................... 35

10.6.5.

2-wire serial controller SCL frequency ......................................................................................... 35

Copyright©2024 THine Electronics, Inc.

2/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.6.6.

2-wire serial interface watch dog timer setting.............................................................................. 35

10.6.7.

THCS253 internal register access protocol via 2-wire serial interface.......................................... 36

10.6.8.

2-wire serial expander ................................................................................................................... 43

10.7.

Direction of GPIO ............................................................................................................................. 44

10.8.

IO configuration ................................................................................................................................ 46

10.8.1.

I/O digital noise filter .................................................................................................................... 46

10.8.2.

LVCMOS Output buffer type configuration .................................................................................. 48

10.8.3.

5V tolerant IO ................................................................................................................................ 49

10.8.4.

LVCMOS Output drive strength setting ........................................................................................ 49

10.8.5.

CML output swing voltage and pre-emphasis setting.................................................................... 49

10.9.

Clock configuration ........................................................................................................................... 50

10.9.1.

Sampling clock select .................................................................................................................... 50

10.9.2.

Clock edge select (RF_IN, RF_OUT) ........................................................................................... 51

10.10.

Spread spectrum clock generator and REFIN(pin) frequency ........................................................... 52

10.11.

PWM signal output function ............................................................................................................. 53

10.12.

CRC ................................................................................................................................................... 53

10.13.

Error detection and notification ......................................................................................................... 54

10.13.1.

READY signal ........................................................................................................................... 54

10.13.2.

INTN signal ............................................................................................................................... 54

10.14.

Standby mode: STANDBY(register)=1............................................................................................. 55

11.

Register map .............................................................................................................................................. 57

12.

Package...................................................................................................................................................... 61

13.

Reference land pattern ............................................................................................................................... 62

14.

Notices and Requests................................................................................................................................. 63

Copyright©2024 THine Electronics, Inc.

3/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

IDSEL1IDSEL0REFEN

RF_OUT / OSCSEL1

OE

D31 / D0

D30 / D1

D29 / D2

D28 / D3

D27 / D4

D26 / D5

D25 / D6

D24 / D7

VDD

D23 / D8

Pin configuration

SYNCEN

4.

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

SSEN 49

32 D22 / D9

QFN-64

DATA_WIDTH 50

31 D21 / D10

TEST2 51

30 D20 / D11

AVDD 52

29 D19 / D12

CAPOUT 53

28 D18 / D13

RXP 5427 D17 / D14

RXN 5526 D16 / D15(TOP VIEW)
65 EXPGND

CAPINA 56
TXN 5725 VDD
24 REFOUT

TXP 5823 REFIN

CAPINP 59

22 D15 / D16

INTN 60

21 D14 / D17

TEST1 61

20 D13 / D18

RESETN 62

19 D12 / D19

ENI2C 63

18 D11 / D20

CTSEL_I2C / FILTSEL1 64

17 D10 / D21
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

PSSEL

RF_IN / OSCSEL0

READY

SDA / OBUF

SCL / FILTSEL0

D0 / D31

D1 / D30

D2 / D29 / PWMOUT

D3 / D28

D4 / D27

D5 / D26

D6 / D25

D7 / D24

D8 / D23

D9 / D22

VDD

Copyright©2024 THine Electronics, Inc.

4/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

5.

Pin description

Pin Name
TXP
TXN
RXP
RXN
RESETN

No.
58
57
54
55
62

Type
CO
CO
CI
CI
IL

PSSEL

1
IL

SYNCEN

48

IL

REFEN

45
IL

DATAWIDTH

50
IL

ENI2C

63
IL

CTSEL_I2C/
FILTSEL164
IL

IDSEL046

IDSEL147

RF_IN/
OSCSEL0

2

IL
IL

IL

RF_OUT/OSECSEL1

44
IL

SDA/
OBUF

4

Copyright©2024 THine Electronics, Inc.

BL

Description
Differential P-ch output
Differential N-ch output
Differential P-ch input
Differential N-ch input
Chip reset
0: Chip reset
1: Chip operation
Chip mode select *Refer to SYNCEN
0: Primary chip mode
1: Secondary chip mode
Link mode selectWhen PSSEL=0 disable
When PSSEL=1 enable
0: AYNC mode
Driven by primary/secondary chip reference clocks
1: SYNC mode
Driven by primary chip reference clock
Reference clock select0: Internal oscillator clock
1: External reference clock
Transmission Data width selectPrimary and secondary DATAWIDTH should be set thesame.
*Refer to Table 8, Table 9, Table 19
2-wire serial interface permission
0: Disable
1: Enable
CTSEL_I2C：2-wire serial Controller / Target select0: 2-wire serial target（I2C controller device side）
1: 2-wire serial controller（I2C remote device side）
FILTSEL1：Digital noise filter setting*Refer to Table 21Table 22
2-wire serial interface device address select*Refer to Table 14
2-wire serial interface device address select*Refer to Table 14
RF_IN: Input clock edge select0: Falling edge
1: Rising edge
OSCSEL0: Internal oscillator clock select*Refer to Table 9
Output clock edge select0: Falling edge
1: Rising edge
OSCSEL1: Internal oscillator clock select*Refer to Table 9
SDA: SDA for 2-wire serial interface 0
OBUF: Output buffer type select0: Open-drain
1: Push-pull
5/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
SCL/
FILTSEL0

5

SSEN

49

BL

IL
OE

43
IL

REFIN
REFOUT
READY

23
24
3

B
O
B

INTN

60
BO

D0/D31, D1/D30,
D3/D286, 7,
9

D2/D29/PWMOUT

8

BT

BT
D4/D27, D5/D26,
D6/D25, D7/D24,
D8/D23, D9/D22
D10/D21, D11/D20,
D12/D19, D13/D18,
D14/D17, D15/D16,
D16/D15, D17/D14,
D18/D13, D19/D12,
D20/D11, D21/D10,
D22/D9, D23/D8,
D24/D7, D25/D6,
D26/D5, D27/D4
D28/D3, D29/D2,
D30/D1, D31/D0

10, 11,
12, 13,14, 15,17, 18,19, 20,21, 22,26, 2728, 29,30, 31,32, 33,35, 36,37, 3839, 40,41. 42TEST1TEST2CAPOUT
CAPINA
CAPINP
VDD

61
51
53
56
59
16, 25,
34
52
65

AVDD
EXPGND

B

BT
IL
AI
PWR
PWR
PWR
PWR
PWR
GND

SCL: SCL for 2-wire serial interface 0
FILSET0: Digital noise filter setting*Refer to Table 21, Table 22
Spread spectrum clock generator
0: SSCG PLL disable
1: SSCG PLL enable
Output enable
0: LVCMOS output Hi-Z
1: LVCMOS output enable
REFIN：External input clock
Pixel clock output
CML Link state
0: Unlock
1: LockInterrupt output *When READY=1
0: Error occurred
1: (Pull-up) : No Error
Primary chip mode data input and output / Secondary chipmode data input and output
Left side of "/" is in primary chip mode
Right side of "/" is in secondary chip mode
D2: Primary chip mode data input/output
D29: Secondary chip mode data input/output
PWMOUT: PWM output

Primary chip mode data input and output / Secondary chipmode data input and output
Left side of "/" is in primary chip mode
Right side of "/" is in secondary chip mode

Primary chip mode data input and output / Secondary chipmode data input and output
Left side of "/" is in primary chip mode
Right side of "/" is in primary chip mode
Shall be tied to Ground
Shall be tied to Ground
Decoupling capacitor Pin, 1.2V output
1.2V Analog power supply input
1.2V Analog power supply input
1.7-3.6V Digital power supply input for LVCMOS I/O
1.7-3.6V Analog power supply input for on-chip regulator
Exposed Pad Ground. Must be tied to the PCB groundplane through an array of via holes

Pin type definition
Analog Buffer

Copyright©2024 THine Electronics, Inc.

6/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
CO: CML Output buffer
CI: CML Input buffer
AI: Analog Input buffer
LVCMOS buffer
IL: Low speed schmitt trigger LVCMOS Input buffer
B: LVCMOS Bi-directional buffer
BO: Open-drain LVCMOS Bi-directional buffer
BL: Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer
BT: Low speed 5V tolerant LVCMOS Bi-directional bufferPower/Ground
PWR: Power supply
GND : Ground

Copyright©2024 THine Electronics, Inc.

7/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
Table 1 Primary chip mode pin sharingPinnumber1
45
63
register
2
44
4
5
64
8

Primary chip /Secondary chip
Sampling clock
2-wire serial（SDA/SCL）
PSSEL
REFEN
ENI2C
PWMEN
RF_IN/OSCSEL0
RF_OUT/OSCSEL1SDA/OBUF
SCL/FILTSEL0CTSEL_I2C/FILTSEL1
D2/D29/PWMOUT

Primary chip mode
Internal OSC

External input

DisableEnableEnableDisableEnableEnable000
OSCSEL0
OSCSEL1
OBUF
FILTSEL0FILTSEL1
D2/D2900
1｛0｝
OSCSEL0
OSCSEL1SDASCLCTSEL_I2C
D2/D29001｛1｝
OSCSEL0
OSCSEL1SDASCLCTSEL_I2CPWMOUT

0
1
0
RF_IN
RF_OUTOBUF
FILTSEL0FILTSEL1
D2/D29

0
1
1
｛0｝
RF_IN
RF_OUTSDASCLCTSEL_I2C
D2/D29

0
1
1
｛1｝
RF_IN
RF_OUTSDASCLCTSEL_I2CPWMOUT

Table 2 Secondary chip mode pin sharingPinnumber1
45
63
register
2
44
4
5
64
8

Primary
chip/Secondary chip
Sampling clock
2-wire serial（SDA/SCL）
PSSEL
REFEN
ENI2C
PWMEN
RF_IN/OSCSEL0
RF_OUT/OSCSEL1SDA/OBUF
SCL/FILTSEL0CTSEL_I2C/FILTSEL1
D2/D29/PWMOUT

Secondary chip mode
Internal OSC

External input

DisableEnableEnableDisableEnableEnable100
OSCSEL0
OSCSEL1
OBUF
FILTSEL0FILTSEL1
D2/D2910
1｛0｝
OSCSEL0
OSCSEL1SDASCLCTSEL_I2C
D2/D2910
1｛1｝
OSCSEL0
OSCSEL1SDASCLCTSEL_I2CPWMOUT

1
1
0
RF_IN
RF_OUTOBUF
FILTSEL0FILTSEL1
D2/D29

1
1
1
｛0｝
RF_IN
RF_OUTSDASCLCTSEL_I2C
D2/D29

1
1
1
｛1｝
RF_IN
RF_OUTSDASCLCTSEL_I2CPWMOUT

Setting value with brace (ex. {0}, {1}) requires register setting by 2-wire serial interface.
See following definition in each Tables.
Setting by Pin
Setting by register

Copyright©2024 THine Electronics, Inc.

8/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
5.1.

Pin setting and combination of chip mode

The following is a list of modes that can be combined between Primary chip and Secondary chip.
Table 3 Primary Chip / Secondary Chip list of pair combination

PSSEL=1 Secondary chi mode（Sec）

SYNCEN

0

REFEN

0

ENI2C

0

CTSEL_I2C
SYNCENREFENENI2CCTSEL_I2C
SYNCENREFENENI2CCTSEL_I2C
SYNCENREFENENI2CCTSEL_I2C
SYNCENREFENENI2CCTSEL_I2C
SYNCENREFENENI2CCTSEL_I2C
SYNCEN

0
0
1
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
1
1

REFEN

-

ENI2C

0

CTSEL_I2C
SYNCENREFENENI2CCTSEL_I2C
SYNCENREFENENI2CCTSEL_I2C

1
1
0
1
1
1

REFEN

ENI2C

CTSEL_I
2C

REFEN

ENI2C

CTSEL_I2C

REFEN

ENI2C

CTSEL_I2C

REFEN

ENI2C

CTSEL_I2C

REFEN

ENI2C

CTSEL_I2C

REFEN

ENI2C

CTSEL_I2C

PSSEL=0 : Primary chip mode（Pri）

0

0

-

0

1

0

0

1

1

1

0

-

1

1

0

1

1

1

Prohibition

Prohibition

Prohibition

Prohibition

Prohibition

Prohibition

Prohibition

N/A

Prohibition

Prohibition

Prohibition

N/A

Prohibition

ProhibitionPri

Prohibition

Prohibition
I2C_C
Pri

Prohibition

N/A

Prohibition

Prohibition

Prohibition

Copyright©2024 THine Electronics, Inc.

I2C_T

Sec

Prohibition

N/A
I2C_T

Prohibition

Sec

I2C_C

Prohibition

Prohibition

Prohibition

N/A

9/63

Prohibition

N/A

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

6.

Absolute maximum rating

Parameter
Supply voltage (VDD,AVDD)LVCMOS input voltage
LVCMOS output voltage
5V tolerant Bi-directional buffer input voltage
5V tolerant Bi-directional buffer output voltage
Open-drain output voltage
CML receiver input voltage
CML transmitter output voltage
Output current
Storage temperature
Junction temperature
Reflow peak temperature/time
θja (Junction to Ambient)Ψjt (Junction to Top of package)
Maximum power dissipation @+25°C

Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-50
-55
-

Typ
Max
4.0
VDD+0.3
VDD+0.3
VDD+2.5
VDD+2.5
4.0
CAPINA+0.3
CAPINP+0.3
50
125
125
260/1029.1 [*1]
1.1 [*1]
3.4[*1]

Unit
V
V
V
V
V
V
V
V
mA
°C
°C
°C/sec°C/W°C/W
W“Absolute maximum ratings” are those values beyond which the safety of the device cannot be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics” specify conditions for device operation.
*1: Thermal parameters are not guaranteed value. This value assists board and system level designers.

7.

Recommended operatingconditions
Parameter
Supply voltage (VDD,AVDD)
Operating ambient temperature

Copyright©2024 THine Electronics, Inc.

Min
1.7
-40

10/63

Typ
-

Max
3.6
85

Unit
V
°C

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

8.

Electrical characteristics

8.1.

Current consumption
SymbolIdd_w1

Idd_w2

Idd_w3

Idd_w4

Parameter
Normal mode current
Primary chip DATAWIDTH=H
32bit Input (Full toggle40MHz)
REFIN mode(80MHz)
Secondary chip
DATAWIDTH=H
32bit Output (Fulltoggle40MHz)
REFIN=80MHz
Normal mode current
Primary chip DATAWIDTH=H
27bit Input (Full toggle40MHz)
5bit Output (Fulltoggle40MHz)
REFIN=80MHz
Normal mode current
Secondary chip
DATAWIDTH=H
5bit Input (Full toggle40MHz)
27bit Output (Fulltoggle40MHz)
REFIN=80MHz
Normal mode current
Primary chip DATAWIDTH=H
10bitInput (Full toggle20MHz)
10bitOutput (Fulltoggle20MHz)
REFIN=80MHz
Normal mode current
Secondary chip
DATAWIDTH=H
10bitInput (Full toggle20MHz)
10bitOutput (Fulltoggle20MHz)
REFIN=80MHz
Normal mode current
Primary chip DATAWIDTH=H
16bitInput (Full toggle1MHz)
16bitOutput (Full toggle1MHz)
REFIN=80MHz
Normal mode current
Secondary chip
DATAWIDTH=H
16bitInput (Full toggle1MHz)
16bitOutput (Full toggle1MHz)
REFIN=80MHz

Copyright©2024 THine Electronics, Inc.

Type

Conditions

Min

Typ

Max

Unit

-

mA

-

mA

-

mA

-

mA

118
PWR

AVDD=3.3V
VDD=3.3V

197

126

PWR

AVDD=3.3V
VDD=3.3V

-

184

128

PWR

AVDD=3.3V
VDD=3.3V

-

128

114

PWR

AVDD=3.3V
VDD=3.3V

114

11/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

Idd_w5

Idd_w6

Idd_w7

Idd_w8

Idd_w9

Normal mode current
Primary chip DATAWIDTH=H
16bit Input (Full toggle1MHz)
16bit Output (Fulltoggle1MHz)
REFIN=40MHz
Normal mode current
Secondary chip
DATAWIDTH=H
16bit Input (Full toggle1MHz)
16bit Output (Fulltoggle1MHz)
REFIN=40MHz
Normal mode current
Primary chip DATAWIDTH=L
16bit Input (Full toggle1MHz)
16bit Output (Fulltoggle1MHz)
REFIN=80MHz
Normal mode current
Secondary chip
DATAWIDTH=L
16bit Input (Full toggle1MHz)
16bit Output (Fulltoggle1MHz)
REFIN=80MHz
Normal mode current
Primary chip DATAWIDTH=L
16bit Input (Fulltoggle66.67MHz)
16bit Output (Fulltoggle66.67MHz)
REFIN=133.34MHz
Normal mode current
Secondary chip
DATAWIDTH=L
16bit Input (Fulltoggle66.67MHz)
16bit Output (Fulltoggle66.67MHz)
REFIN=133.34MHz
Standby mode current
8bit Input(Full toggle6.25kHz)
Standby mode current
Secondary chip
DATAWIDTH=L
8bit Output(Fulltoggle6.25kHz)
Standby mode current
8bit Output(Fulltoggle6.25kHz)
Standby mode current
Secondary _DATAWIDTH=L
8bit Input(Full toggle6.25kHz)

Copyright©2024 THine Electronics, Inc.

85

PWR

AVDD=3.3V
VDD=3.3V

-

-

mA

-

mA

-

mA

-

mA

-

mA

85

87

PWR

AVDD=3.3V
VDD=3.3V

-

87

190

PWR

AVDD=3.3V
VDD=3.3V

-

190

7
PWR

AVDD=3.3V
VDD=3.3V

77PWR

AVDD=3.3V
VDD=3.3V

7

12/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
8.2.

LVCMOS/Analog input DC specifications
Symbol

VIH

Parameter

High level input voltage

Type
B,BT,
BO
IL,BL
B,BT,
BO

VIL

Low level input voltage
IL,BL
AI

VOH

High level output voltage

B,BT,
BL

B,BT,
BL
VOL

Low level output voltage

BO
IIH
IIL

Conditions
1.7V≦VDD<2.0V
2.0V≦VDD<3.0V
3.0V≦VDD≦
3.6V
1.7V≦VDD≦
3.6V
1.7V≦VDD<2.0V
2.0V≦VDD<3.0V
3.0V≦VDD≦
3.6V
1.7V≦VDD≦
3.6V
1.7V≦VDD≦
3.6V
1.7V≦VDD<2.0V
TTLDRV(register)={0}
IOH=-2mA
1.7V≦VDD<2.0V
TTLDRV(register)={1}
IOH=-4mA
2.0V≦VDD≦
3.6V
IOH=-4mA
1.7V≦VDD<2.0V
TTLDRV(register)={0}
IOL=2mA
1.7V≦VDD<2.0V
TTLDRV(register)={1}
IOL=4mA
2.0V≦VDD≦
3.6V
IOL=4mA
1.7V≦VDD≦
3.6V
IOL=2mA
VIN=VDD
VIN=0V

Input leak current HighIL
Input leak current Low
IL
Output leak current High in
B,BT,
IOZH
VIN=VDD
Hi-Z
BL,BO
Output leak current Low in
B,BT,
IOZL
VIN=0V
Hi-Z
BL,BO
AI: Analog Input buffer
IL: Low speed schmitt trigger LVCMOS Input buffer
B: LVCMOS Bi-directional buffer
BO: Open-drain LVCMOS Bi-directional buffer
BL: Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer
BT: Low speed 5V tolerant LVCMOS Bi-directional buffer

Copyright©2024 THine Electronics, Inc.

13/63

Min
0.65 VDD
0.70 VDD

Typ
-

Max
VDD
VDD

Unit
V
V

2.0

-

VDD

V

0.70 VDD

-

VDD

V

0
0

-

0.35 VDD
0.30 VDD

V
V

0

-

0.8

V

0

-

0.30 VDD

V

0-0.15 VDDV

VDD 0.30

-

VDD

V

VDD 0.45

-

VDD

V

VDD 0.45

-

VDD

V

0

-

0.30

V

0

-

0.45

V

0

-

0.45

V

0

-

0.27

V

-10
-10

-

10
10

uA
uA

-10

-

10

uA

-10

-

10

uA

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
8.3.

LVCMOS AC characteristics

SymbolParametertRSNRESETN low time

Conditions
-

Min

Typ

Max

Unit

3

-

-

us

10

-

66.6

ns

7.5

-

66.6

ns

12.5
0.35
tTCIP
0.35
tTCIP
2.0
25
2.5
2.0

-

ns

-

111
0.65
tTCIP
0.65
tTCIP
-

DATA_WIDTH(pin)=0tTCIP

REFIN period

1.7V≦VDD≦2.25V and
TTLDRV(register)={0}DATA_WIDTH(pin)=02.25V≦VDD≦3.6V or
TTLDRV(register)={1}
DATA_WIDTH（pin）=1

tTCH
tTCL

REFIN High time
REFIN Low time

Pin type: B

1.7V≦VDD≦3.6V
1.7V≦VDD<2.25V
2.25V≦VDD≦2.75V
2.75V<VDD≦3.6V

0.5 tTCIP
0.5 tTCIP

ns
ns
ns
ns
ns
ns

tTS

Data input setup to REFIN

Pin type:
BTtTH

Data input hold to REFIN

-

1.0

-

-

ns

tTPD

Power on to RESETN high
delay

-

0

-

-

ns

41.67

50

62.5

ns

20.84

25

31.25

ns

10.42

12.5

15.62

ns

tOSC

Internal oscillator clock
periodtDCP

Data sampling clock period

tFLTCK

Noise filter clock period
Input data to output data
delay

tTCD

tRCP

Note : Transmission delay
between primary andsecondary chips is notincluded.

OSCSEL1(pin)=0
OSCSEL0(pin)=0
OSCSEL1(pin)=1
OSCSEL0(pin)=0
OSCSEL1(pin)=1
OSCSEL0(pin)=1
REFEN(pin)=0

-

tOSC

-

ns

REFEN(pin)=1

-

tTCIP

-

ns

REFEN(pin)=0

10.42

12.5

15.62

ns

REFEN(pin)=1
Digital noise filter (in & out) disable
Refer to Table 21,Table 22
Digital noise filter (in & out) 4 taps
Refer to Table 21,Table 22
Digital noise filter (in & out) 8 taps
Refer to Table 21,Table 22
Digital noise filter (in & out) 16 taps
Refer to Table 21,Table 22

36.2
tDCP
46
tDCP
53.4
tDCP
68.1
tDCP

tTCIP

61.3
tDCP
73.7
tDCP
82.1
tDCP
100.5
tDCP

ns

-

ns
ns
ns
ns

REFOUT period
REFOUT high time

-

-

tDCP

-

ns

tRCH

-

-

0.5 tDCP

-

ns

tRCL

REFOUT low time--

0.5 tDCP

-

ns

tDOUT

Data output period

-

-

tDCP

-

ns

tRS

Data output setup to
REFOUT-

0.45 tDCP- 0.675

-

-

ns

tRH

Data output hold to
REFOUT-

0.45 tDCP- 2.175

-

-

ns

-

-

-

1

ms

-

0

-

10

ms

tRRDY
tNRDY

RESETN high to READY
high delay
STANDBY low to READY
high delay

Copyright©2024 THine Electronics, Inc.

14/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
SymboltSRDYtTLH

Parameter
STANDBY high to READY
high delay

Clock and data output low
to high transition time

Conditions

Min

Typ

Max

Unit

-

0

-

10

ms

Clock , TTLDRV(register)={0}

-

-

2.1

ns

-

-

4.2

ns

-

-

5.9

ns

-

-

1.1

ns

-

-

2.3

ns

-

-

3.0

ns

-

-

2.1

ns

-

-

4.3

ns

-

-

6.1

ns

-

-

1.1

ns

-

-

2.2

ns

-

-

3.0

ns

Data(Pin type=B) ,TTLDRV(register)={0}
Data(Pin type=BT) ,TTLDRV(register)={0}
Clock , TTLDRV(register)={1}
Data(Pin type=B) ,TTLDRV(register)={1}
Data(Pin type=BT) ,TTLDRV(register)={1}
Clock , TTLDRV(register)={0}tTHLClock and data output highto low transition time

Data(Pin type=B) ,TTLDRV(register)={0}
Data(Pin type=BT) ,TTLDRV(register)={0}
Clock , TTLDRV(register)={1}
Data(Pin type=B) ,TTLDRV(register)={1}
Data(Pin type=BT) ,TTLDRV(register)={1}

Copyright©2024 THine Electronics, Inc.

15/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
tTCIP
tTCH(RF=0)tTCL(RF=0)tTCL(RF=1)tTCH(RF=1)
RF=0

REFIN

VDD/2

VDD/2

VDD/2

RF=1
tTS

D0-D31

tTH

VDD/2

VDD/2

RD = 10Ω
Test Point

CL = 8pF

tRCP
tRCH(RF=0)tRCL(RF=0)tRCL(RF=1)tRCH(RF=1)
RF=0

REFOUT

VDD/2

VDD/2

VDD/2

RF=1
tRS

D31-D0

tRH

VDD/2

VDD/2

tDOUT

Copyright©2024 THine Electronics, Inc.

16/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
Primary chip mode Input
D0-D31DATA1Secondary chip mode Output
D31-D0

DATA2

DATA1

DATA3

DATA2

DATA3

tTCD
Secondary chip mode Input
D31-D0DATA1Primary chip mode Output
D0-D31

DATA2

DATA1

DATA3

DATA2

DATA3

tTCD

Copyright©2024 THine Electronics, Inc.

17/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
8.4.

CML DC characteristics

SymbolParameter

VTOD

CML differential output peak
to peak signal

PRE

CML pre-emphasis level

CML common mode output
voltage

VTOC

ITOH

CML output leak current
high

ITOS

CML output short current
CML differential input highthreshold
CML differential input low
threshold

VRTH
VRTL
IRIH

CML input leak current highIRIL

CML input short current low

IRRIH
IRRIL

CML input current high
CML input current low
CML differential input
resistance

RRIN

8.5.

Conditions
CMLDRV[1:0](register)={00}
CMLDRV[1:0](register)={01}(default)
CMLDRV[1:0](register)={10}PRE(register)={0} (default)PRE(register)={1}
CMLDRV[1:0](register)={00}PRE(register)={1}
CMLDRV[1:0](register)={01}

Min
266

Typ
400

Max
534

Unit
mVpp

400

600

800

mVpp

600
-

800
0

1000
-

mVpp
dB

-

6

-

dB

-

3.52

-

dB

PRE(register)={0} (default)-

1200 - 0.5
VTOD

-

mV

-

1200 - VTOD

-

mV

-

1200 - 0.75
VTOD

-

mV

-30

-

30

uA

-80

-

-

mA

-

-

-

50

mV

-

-50

-

-

mV

-10

-

10

uA

-10

-

10

uA

-6

-

2
-

mA
mA

80

100

120

Ω

PRE(register)={1}
CMLDRV[1:0](register)={00}PRE(register)={1}
CMLDRV[1:0](register)={01}RESETN(pin)=0
TXP/N(pin)=CAPINA(pin)RESETN(pin)=0
TXP/N(pin)=0V

RESETN(pin)=0
RXP/N(pin)=CAPINA(pin)RESETN(pin)=0
RXP/N(pin)=0V
RXP/N(pin)=CAPINA(pin)RXP/N(pin)=0V-

CML AC characteristics

SymboltTRF
tTPLL0tTPLL1tTNP0Parameter
CML output rise and fall time (20%80%)
RESETN=H to CML output delay
RESETN=L to CML output high fix
READY=L to training pattern output
delay

tTBIT

Output unit intervaltRBIT

Input unit interval

Copyright©2024 THine Electronics, Inc.

Conditions

Min

Typ

Max

Unit

-

50

-

150

ps

-

-

-

1
200

ms
ns

-

-

-

100

us

DATA_WIDTH(pin)=0
DATA_WIDTH(pin)=1-

250tDCP÷30tDCP÷50
-

2222

ns
ns
ps

18/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
75～200nF50Ω

75～200nF

50Ω

80%

80%

TXP

TXN

< 5mm

Vdiff = (TXP) - (TXN)
20%

20%

tTRF

tTRF

THCS253

THCS253

CAPINP

50Ω

50Ω

C=75～
200nF
TXP

C=75～
200nF
RXP

TXN

CML Receiver

RXN
Zdiff=100ohm
50Ω

50Ω

CML Transmitter

Vbias
GND

Copyright©2024 THine Electronics, Inc.

19/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
ASYNC mode
Training pattern output from the primary chip requires RESET=1 and REFIN frequency*1 input.
Training pattern output from the secondary chip requires RESET=1 and REFIN frequency*1 input as well as
training pattern receive from the primary chip.
*1: In internal oscillator clock mode with REFEN=0, RESET=1 only.
Primary Chip
VDD

REFIN

GPIO Inputs
D0-D31RESETNGPIO DatatTPDtTPLL0

tTNP1

tRRDY

READY

Training
pattern

TXP/N

GPIO Outputs
D31-D0Normalpattern

Training
pattern

Low

Valid GPIO

Hold

Low

Valid GPIO

Secondary Chip
VDD

REFIN

GPIO Inputs
D0-D31RESETNGPIO DatatTPDtTPLL0

tRRDY

READY

Training
pattern

TXP/N

GPIO Outputs
D31-D0tTNP1

Low

Copyright©2024 THine Electronics, Inc.

Normalpattern

Training
pattern

Hold

Valid GPIO

20/63

Valid GPIO

Low

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
SYNC mode
Primary Chip
VDD

REFIN

GPIO Inputs
D0-D31RESETNGPIO DatatTPDtTPLL0

tTNP1

tRRDY

READY

Training
pattern

TXP/N

GPIO Outputs
D31-D0Normalpattern

Training
pattern

Valid GPIO

Low

Hold

Low

Valid GPIO

Secondary Chip
VDD

GPIO Inputs
D0-D31RESETNGPIO DatatTPDtTPLL0

tRRDY

READY

Training
pattern

TXP/N

GPIO Outputs
D31-D0tTNP1

Low

Copyright©2024 THine Electronics, Inc.

Normalpattern

Training
pattern

Hold

Valid GPIO

21/63

Valid GPIO

Low

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
8.6.

2-wire serial interface DC/AC characteristics

Symbol
VIL
VIH

Parameter
Low level input voltage
High level input voltage

VOL

Low level output voltage

Ii
fSCL

Input current each I/O pin
SCL clock frequency
Setup time (repeated) START
condition
Hold time (repeated) START
condition

tSU;STAtHD;STAtLOW

Low period of the SCL clocktHIGH

High period of the SCL clock

tHD;DAT

Data hold time

tSU;DAT

Data setup time

tSU;STO

Setup time for STOP condition

tBUF
tr
tf

Bus free time between a STOP
and START condition
Rise time of both SDA and SCL
signals
Fall time of both SDA and SCL
signals

Condition
1.7V≦VDD≦3.6V
IOL=2mA
fSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHz-Min
00.7 VDD

Typ-Max
0.30 VDD
-

Unit
V
V

0.00

-

0.26

V

-10
0
0.26
0.6
0.46
0.8
0.5
1.3
0.26
0.6
0
50
100
0.26
0.6
0.5
1.3

-

+10
1000
-

uA
kHz
us
us
us
us
us
us
us
us
us
ns
ns
us
us
us
us

-

-

300

ns

-

-

300

ns

-

SDA
tLOW

tSU;DATtHD;STAtBUF

SCLtHD;STA

Copyright©2024 THine Electronics, Inc.

tHD;DAT tHIGH

tSU;STA

22/63

tSU;STO

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

9.

CML Line diagram

9.1.

CML input diagram

1UI=1/(serial data rate)

B
Y

C

A

D

E

F

X
X=0 UI

Copyright©2024 THine Electronics, Inc.

Y=0mV

X=1 UI

A
B
C
D

X[UI]
0.25
0.3
0.7
0.75

Y[mV]
0
50
50
0

E

0.7

-50

F

0.3

-50

23/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

10. Function
10.1. Function overview
The THCS253 integrates a high-speed CML serializer and deserializer on a single chip. It is capable ofaggregating and de-aggregating up to 32-bit parallel GPIO signals and a 2-wire serial interface with full-duplex
communication using two pairs of differential signals with a minimum of external components.
standby mode supports up to 8-bit low-speed GPIO signals and 2-wire serial interface.

Low-power

In addition, the internal

oscillator mode does not require an external clock generator such as a crystal oscillator. Two THCS253s (onepair) can be used to monitor and control peripheral devices via a 2-wire serial interface or GPIO. In the event of
a communication error, the GPIO signal is held and an interrupt signal is used to notify the user.

10.2. Power supply
10.2.1. Internal regulator output/input function (CAPOUT, CAPINA, CAPINP)
The internal regulator generates 1.2V (CAPOUT) for internal use only. Do not use for other external loads.
CAPOUT should be bypassed to GND with 10uF as a power supply pin; AVDD should be bypassed to GND with
10uF or more.
CAPINP and CAPINA supply the reference voltage for the internal analog circuitry. To reduce high frequency
noise, CAPINP/CAPINA should be bypassed to GND with 0.1uF as a power supply pin. CAPOUT, CAPINA and
CAPINP should be wired as shown in the figure below.

THCS253
10uF
Power
SupplyAVDDCAPOUT

>10uF

0.1uF
CAPINA
VDD

0.1uF
CAPINP

Figure 1 Connection of CAPOUT, CAPINA, CAPINP and decoupling capacitor

Copyright©2024 THine Electronics, Inc.

24/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.3. Chip Operating state
Basic operating states related to power consumption of the THCS253, such as reset, OE, and standby.
Table 4 Operating mode setting
Setting
ENI2C
STANDBY(pin)(register)

OE *1
(pin)

Operating mode

RESETN
(pin)

RESET

0

-

-

-

1

0

0

0

1

0

0

1

1

1

{0}

0

1

1

{0}

1

1

1

{1}

0

1

1

{1}

1

Normal operation(2-wire serial interface
Disable)Normal operation(2-wire serial interface
enable)StandbyDescription
Chip reset
2-wire serial interface disable
All outputs are Hi-Z
Normal operation
2-wire serial interface disable
All outputs are Hi-Z
Normal operation
2-wire serial interface disable
GPIO normal operation
Normal operation
2-wire serial interface enable
All outputs are Hi-Z
Normal operation
2-wire serial interface enable
GPIO normal operation
Low power consumption/low frequency
sampling rate operation
2-wire serial interface enable
GPIO 8bit Hi-Z
Low power consumption/low frequency
sampling rate operation
2-wire serial interface enable
GPIO 8bit low speed communication
Enable*1 When OVERRIDE_OEN(register) = {1} is selected, the OE(pin) state is disabled.

10.4. Chip operation mode
10.4.1. Chip configuration
The THCS253 has two modes, Primary chip mode and Secondary chip mode, which are selected by the PSSEL
pin. The THCS253 is connected and used in a pair of Primary chip mode t and Secondary chip mode.
Table 5 Primary chip and Secondary chip selection
PSSEL (pin)01Copyright©2024 THine Electronics, Inc.

Description
Primary chip mode
Secondary chip mode

25/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.4.2. Operating clock mode selectThe THCS253 selects synchronous or asynchronous operation of downstream and upstream by the SYNCEN pin
selection in the secondary chip mode.
Synchronous mode
The primary chip samples data by its own clock. The secondary chip samples data using the CDR (Clock Data
Recovery) clock generated by the deserializer, and the downstream and upstream operate synchronously.
Asynchronous mode
Data sampling is performed with the clocks of both Primary chip and Secondary chip, and downstream andupstream operate asynchronously.
Table 6 Downstream / Upstream synchronous setting
SYNCEN(pin) of Secondary chip
0
1

Description
Asynchronous mode : Operates at both clocks
Synchronous mode : Operates at the clock of the
primary chip

10.4.3. Operating clock selectTHCS253 allows selection of the clock used to input data sampling and drive the serializer/deserializer.
Table 7 Operating clock select
REFEN(pin)01

Description
Internal Oscillator Clock Mode：20M/40M/80MHz
External reference clock mode：9-133MHz

Figure 2 Clock Tree diagram of Primary chip

Copyright©2024 THine Electronics, Inc.

26/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

Figure 3 Clock Tree diagram of Secondary chip

Copyright©2024 THine Electronics, Inc.

27/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.4.4. Combination of operating modes
Transmit operation of the THCS253 is determined by the combination of the PSSEL, REFEN, and SYNCEN pins.
Down/Up Asynchronous mode(SYNCEN=0 of secondary chip)／External reference clock mode(REFEN=1)
Data sampling and driven by the REFIN input of each primary chip/secondary chip.
Different frequencies can be input to the Primary chip and Secondary chip.
Downstream and upstream can be taken and output synchronized to their respective REFIN inputs.
Primary chip

REFEN=1

SCL/SDACMLREFOUT
I/O

Tx

CML
Rx

Formatter

I/O

REFOUT

Formatter

D0/D31

2-wire serial I/F

2-wire serial I/F

Formatter

FormatterREFIN

D31/D0

Secondary chip
PLL

Rx

OSC

Tx

SYNCEN=0

PLL

D31/D0D0/D31REFIN
OSC

SCL/SDASYNCEN=0
REFEN=1

Figure 4 ASYNC_MODE / Ext.REF_MODE Block diagram
Down/Up Asynchronous mode(SYNCEN=0 of secondary chip)／Internal oscillator clockmode(REFEN=0)
Data sampling and driven by the internal oscillator clock of each primary chip/secondary chip.
Selectable from 20/40/80MHz by OSCSEL [1:0] pin setting.
Different frequencies can be selected for the internal oscillator of the Primary chip/Secondary chip.
All input data is asynchronous acquisition because of sampling by the internal oscillator. Output data is
synchronized with REFOUT.
Primary chip

REFOUT

Formatter

REFOUT
I/O

CML

Tx

Formatter

D31/D0CML

I/O

D0/D31

2-wire serial I/F

2-wire serial I/F

PLL

Formatter

Formatter

REFIN

SCL/SDA

PLL

Rx

OSC

Secondary chipRx

SYNCEN=0

Tx

REFEN=0

D31/D0D0/D31REFIN
OSC

SCL/SDASYNCEN=0
REFEN=0

Figure 5 ASYNC_MODE / Int.OSC_MODE Block diagram

Copyright©2024 THine Electronics, Inc.

28/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
Down/Up Asynchronous mode(SYNCEN=0 of secondary chip)／External reference clock mode(REFEN=1)
and Internal oscillator clock mode(REFEN=0)
Data sampling and driven by the REFIN input of either the Primary chip or the Secondary chip.
Either the primary chip/secondary chip is driven and sampled by the internal oscillator.
Selectable from 20/40/80MHz by OSCSEL [1:0] pin setting.
The external reference clock drive side can be synchronized with the REFIN input for take-up and output.
The internal oscillator drive side is all asynchronous acquisition. Output data is synchronized with REFOUT.
Primary chip

I/O

Tx

Formatter

I/O

D31/D0Tx

CML
Rx

REFOUTREFOUT
D31/D0Formatter

D0/D31

2-wire serial I/F
CML

Formatter

REFIN

SCL/SDA

PLL
Formatter

OSC

Secondary chipRx

REFEN=1
SYNCEN=0

D0/D31REFIN

2-wire serial I/F
PLL

SCL/SDASYNCEN=0OSC

REFEN=0

Figure 6 ASYNC_MODE / Ext.REF_MODE & Int.OSC_MODE Block diagram
Down/Up Synchronous mode(SYNCEN=1 of secondary chip)／External reference clock mode(REFEN=1)
Driven and data sampling only by REFIN to the primary chip. (Input to REFIN of the secondary chip is prohibited)
Secondary chip uses the clock regenerated by the receiver for data sampling and driving the transmitter.
Downlink take-up and output synchronized with REFIN input.
The uplink is asynchronous acquisition due to sampling with the CDR-generated clock.
Primary chip

Formatter

REFOUT
I/O

CML

Tx

REFOUT

Rx

Formatter

D31/D0CML

I/O

D0/D31

2-wire serial I/F

Formatter

Formatter

REFIN

SCL/SDA

PLL

Rx

OSC

Secondary chip

Tx

REFEN=1
SYNCEN=x

D31/D0D0/D31REFIN
SYNCEN=1

2-wire serial I/F

PLL

OSC

SCL/SDAREFEN=1

Figure 7 SYNC_MODE / Ext.REF_MODE Block diagram

Copyright©2024 THine Electronics, Inc.

29/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

Down/Up Synchronous mode(SYNCEN=1 of secondary chip)／Internal oscillator clock mode(REFEN=0)
It is sampled and driven by the built-in oscillator of the primary chip.
Selectable from 20/40/80MHz by OSCSEL [1:0] pin setting.
Secondary chip uses the clock regenerated by the receiver for data sampling and driving the transmitter.
All input data is asynchronous acquisition because of sampling by the internal oscillator. Output data is
synchronized with REFOUT.
Primary chip

REFOUT

Formatter

REFOUT
I/O

CML

Tx

Formatter

D31/D0CML

I/O

D0/D31

SCL/SDA2-wire serial I/F

Formatter

Formatter

REFIN

Secondary chip
PLL

Rx

OSC

Rx

SYNCEN=x

Tx

REFEN=0

D31/D0D0/D31REFIN
SYNCEN=1

2-wire serial I/F

PLL

OSC
REFEN=1

SCL/SDA

Figure 8 SYNC_MODE / Int.OSC_MODE Block diagram

Copyright©2024 THine Electronics, Inc.

30/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.5. Byte mode and frequency range
The THCS253 switches between transmitter and receiver operating byte modes (3 bytes or 5 bytes) by selecting
DATA_WIDTH (pin). The external reference clock frequency in each byte mode with REFEN (pin) = 1 and theoperating frequency with OSCSEL [1:0] (pin) setting when REFEN (pin) = 0 are shown below.
Table 8 DATAWIDTH select and external reference clock frequency range
DATA_WIDTH
(pin)
0
1

REFIN
frequency range
15 - 133MHz
9 - 80MHz

CML data rate
450Mbps - 4Gbps

Table 9 DATAWIDTH and OSCSEL[1:0] select
RF_OUT/OSCSEL1(pin)0

RF_IN/OSCSEL0
(pin)
0

0

1

1

0

1

1

Copyright©2024 THine Electronics, Inc.

DATA_WIDTH
(pin)
0
1
0
1
0
1
0
1

31/63

OSC
frequency
20MHz±20%40MHz±20%80MHz±20%

CML data rate
480Mbps - 720Mbps
800Mbps - 1200Mbps
960Mbps - 1440Mbps
1600Mbps - 2400Mbps
960Mbps - 1440Mbps
1600Mbps - 2400Mbps
1920Mbps - 2880Mbps
Prohibition

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.6. 2-wire serial interface
10.6.1. 2-wire serial interface setting
THCS253 has 2-wire serial interface (I2C: SDA/SCL)
Table 10 2-wire serial interface Setting
ENI2C(pin)0

I2C (SCL/SDA)
DisableEnableEnable12-wire serial controller/target can be selected independently from Primary chip / Secondary chip mode settings.
Table 11 2-wire serial interface controller / target selectCTSEL_I2C(pin)0
1

I2C mode
TargetController

Different accessible ranges
Table 12 2-wire serial interface accessible range

I2C

Primary chip register

Secondary chip register

Remote device register

Accessible

Accessible

Accessible

Figure 9 2-wire serial interface accessible range

Copyright©2024 THine Electronics, Inc.

32/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

Table 13 Combination of PSSEL(pin) and CTSEL_I2C(pin)Primary chip

Secondary chipInternal register access

Remote device
register access

1

2-wire target

2-wire controller

Cdv => Pch => Sch *Cdv => Pch => Sch => Rdv *2

2-wire controller

2-wire target

Pch <= Sch <= Cdv *Rdv <= Pch <= Sch <= Cdv *3

2-wire target

2-wire target

Cdv => Pch / Sch<= Cdv *Not allowed

4

2-wire controller

2-wire controller

Not allowed

Not allowed*Pch : Primary chip / Sch : Secondary chip / Cdv : Control device / Rdv : Remote device

10.6.2. Clock stretching
2-wire serial controller device connected to the THCS253 must support clock stretching.
Access from the 2-wire serial target (control device side) to the 2-wire serial controller (remote device side) of the
THCS253 involves a clock stretch every 8 bits.
Clock stretching period:(Internal latency of THCS253) + (WRITE time to remote device) + (Response time of remote device
ACK/READ data) [ns](tDCP x 70 + 350) + (I2C controller bit rate* x 8) + Response time of remote device [ns]*Can be set by I2CPERIOD [1:0] register (Default 100KHz)
Effective I2C frequency = 1 / (Clock stretching period +SCL period)
SDA

A ・・ ・・

2-wire-Write

Control device side
THCS253 2-wire serial target
SCL

Clock stretchingSDA

2-wire-Write・・・ ・

A ・・・ ・

Remote Device Side
THCS253 2-wire serial control
・・ ・・

SCL

Figure 10 Clock stretching of I2C communication

Copyright©2024 THine Electronics, Inc.

33/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.6.3. Device Address
To access the THCS253 registers, IDSEL1 (pin) and IDSEL0 (pin) must be set and the device address must be
selected. The device address must be set only on the 2-wire serial target set to CTSEL_I2C=0. The device address
set on IDSEL1 and IDSEL0 cannot be used as the device address of a remote device.
Table 14 Device ID setting
Setting
IDSEL1IDSEL0
(pin)
(pin)
0
0
0
1
1
0
1
1

Copyright©2024 THine Electronics, Inc.

Device address [6:0](HEX) / (BIN)
0x0B / 000_1011
0x34 / 011_0100
0x77 / 111_0111
0x65 / 110_0101

34/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.6.4. 2-wire serial controller / target register address space
The THCS253 identifies the 2-wire serial target (on the control device side) and the 2-wire serial controller (onthe remote device side). Burst access across the boundary between the 2-wire serial target (control device side)and the 2-wire serial controller (remote device side) is prohibited.
Table 15 Register address configuration
Register address

Description

0x00 - 0x7F
0x80 - 0xFF

2-wire serial target (Control device side)
2-wire serial controller (Remote device side)
Register

THCS253 I2C Target(Control device side)

0x00
0x7F

Same
Device ID

0x80
・
・
・

THCS253 I2C Controller(Remote device side)

Address・・・

CTSEL_I2C = 00xFF

CTSEL_I2C = 1

Figure 11 Register address mapping

10.6.5. 2-wire serial controller SCL frequency
2-wire serial controller chip with CTSEL_I2C=1 can set the SCL frequency in the register. The default is 100 kbps.
Table 16 2-wire serial bitrate setting
Register Address

Name

Description

0x26

I2CPERIOD

2-wire serial controller bit rate setting (SCL）
10,000 / I2CPERIOD kbps

10.6.6. 2-wire serial interface watch dog timer setting
The 2-wire serial interface of the THCS253 has a watchdog timer function that resets the internal state if
communication stops for some reason, such as an external factor, and the internal state continues to not advance.
The time until the watchdog timer is activated can be set in an internal register.
Table 17 2-wire serial interface watch Dog Timer setting
Register Address

bit

Name

Description

7:4

I2C_WDT_STBY

3:0

I2C_WDT

0x28

Copyright©2024 THine Electronics, Inc.

35/63

2-wire serial watch dog timer (standby)
0:Disable／50ms～1650s
2-wire serial watch dog timer (Normal mode)
Controller 0:Disable／0.0123ms - 403ms
Target 0:Disable／0.0246ms - 806ms

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.6.7. THCS253 internal register access protocol via 2-wire serial interface
The THCS253 2-wire serial interface protocol includes the following three types: (1) 2-wire serial target register
access, (2) 2-wire serial controller access, and (3) 2-wire serial remote device access.

(1) THCS253 2-wire serial target register accessFigure 12 2-wire serial target register accessS

Start condition

R

Read command

P

Stop condition

W

Write command

A

ACK

Access from 2-wire serial Controller of Control Device

NACK

Access from 2-wire serial Target of Remote Device

Repeated start condition

Access from THCS253

Sr

Single Byte write
Control Device SideS

THCS253
Device Address

W

Register
AddressA

A

A

Write Data

P

IDLE

Remote Device Side

Burst write
Control Device SideS

THCS253
Device Address

W

A

Register
Address

Write Data
1

A

A

・・・

A

Write Data
#

A

P

IDLE

Remote Device Side

Figure 13-1 2-wire serial target register access protocol

Copyright©2024 THine Electronics, Inc.

36/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
Single Byte read with repeated start command(0x0B / 0x34 / 0x77 / 0x65)

Control Device SideS

THCS253
Device Address

W

Returns data at the address indicated by the address pointer (0x00-0x7F)(0x00-0x7F)
Register
AddressA

A

THCS253
Device Address

Sr

A

R

P

Read Data

IDLE

Remote Device Side

Burst read with repeated start command(0x0B / 0x34 / 0x77 / 0x65)

Control Device SideS

THCS253
Device Address

Returns data at the address indicated by the address pointer (0x00-0x7F)(0x00-0x7F)
Register
Address

A

W

A

THCS253
Device Address

Sr

A

R

Read Data 1

A

Read Data 2

A

・・・

A

Read Data #

P

IDLE

Remote Device Side

Burst read with stop and start command(0x0B / 0x34 / 0x77 / 0x65)

Control Device SideS

THCS253
Device Address

Returns data at the address indicated by the address pointer (0x00-0x7F)(0x00-0x7F)
Register
Address

A

W

A

P

S

THCS253
Device Address

R

A

Read Data 1

A

Read Data 2

A

・・・

A

Read Data #

P

IDLE

Remote Device Side

Single Byte read without repeated start condition
Returns data at the address indicated by the address pointer (0x00-0x7F)(0x0B / 0x34 / 0x77 / 0x65)

Control Device SideS

THCS253
Device Address

A

R

P

Read Data1

IDLE

Remote Device Side

Burst read without repeated start condition(0x0B / 0x34 / 0x77 / 0x65)

Control Device SideS

THCS253
Device Address

R

A

Returns data at the address indicated by the address pointer (0x00-0x7F)
Read Data 1

A

Read Data 2

A・・・

Read Data #

P

IDLE

Remote Device Side

Figure 14 2-wire serial target register access protocol

Copyright©2024 THine Electronics, Inc.

37/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E(2) THCS253 2-wire serial controller register accessFigure 15 2-wire serial controller register accessS

Start condition

R

Read command

P

Stop condition

W

Write command

A

ACK

Access from 2-wire serial Controller of Control Device

NACK

Access from 2-wire serial Target of Remote Device

Repeated start condition

Access from THCS253

Sr

Single Byte write
Control Device SideS

THCS253
Device Address

A

W

Register
Address

Clock
StretchingA

Write DataCTSEL_I2C=1 chip

Clock
StretchingAP

CTSEL_I2C=1 chip

IDLE

Remote Device Side

Burst write
Control Device SideS

THCS253
Device Address

W

A

Register
Address

Clock
StretchingA

CTSEL_I2C=1 chip
IDLE

Remote Device Side

Write Data
1

Clock
Stretching

A

・・・

A

Write Data#CTSEL_I2C=1 chip

Clock
StretchingAP

CTSEL_I2C=1 chipSingle Byte read with repeated start command(0x0B / 0x34 / 0x77 / 0x65)

Control Device SideS

THCS253
Device Address

W

Returns data at the address indicated by the address pointer (0x80-0xFF)(0x80-0xFF)

A

Register
Address

Clock
StretchingA

Sr

THCS253
Device Address

CTSEL_I2C=1 chip

R

A

Clock
Stretching

Read DataAP

CTSEL_I2C=1 chip

IDLE

Remote Device Side

Figure 16 2-wire serial controller register access protocol

Copyright©2024 THine Electronics, Inc.

38/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
Burst read with repeated start command(0x0B / 0x34 / 0x77 / 0x65)

Control Device Side

THCS253
Device Address

S

Register
AddressA

W

Returns data at the address indicated by the address pointer (0x80-0xFF)(0x80-0xFF)
Clock
StretchingA

THCS253
Device Address

Sr

CTSEL_I2C=1 chip

A

R

Clock
StretchingA・・・

Read Data 1

CTSEL_I2C=1 chip

IDLE

Remote Device Side

Clock
Stretching

Read Data #ClockStretchingA

Read Data 2

A

CTSEL_I2C=1 chipA

P

CTSEL_I2C=1 chip
IDLE

Burst read with stop and start command(0x0B / 0x34 / 0x77 / 0x65)

Control Device Side

THCS253
Device Address

S

W

Returns data at the address indicated by the address pointer (0x80-0xFF)(0x80-0xFF)
Register
Address

A

A

Clock
Stretching

P

S

THCS253
Device Address

CTSEL_I2C=1 chip

R

IDLE

Remote Device Side

Read Data 1

CTSEL_I2C=1 chip

Clock
Stretching

A

・・・

Clock
StretchingA

Read Data #ClockStretchingA

Read Data 2

A

CTSEL_I2C=1 chipA

P

CTSEL_I2C=1 chip
IDLE

Single Byte read without repeated start condition(0x0B / 0x34 / 0x77 / 0x65)

Control Device SideS

THCS253
Device AddressRA

Cl ockStretching

Returns data at the address indicated by the address pointer (0x80-0xFF)
Read Data1

CTSEL_I2C=1 chip

A

P

IDLE

Remote Device Side

Burst read without repeated start condition(0x0B / 0x34 / 0x77 / 0x65)

Control Device SideS

THCS253
Device Address

R

A

Clock
Stretching

Returns data at the address indicated by the address pointer (0x80-0xFF)
Read Data 1

A

CTSEL_I2C=1 chip

Clock
Stretching

Read Data 2

CTSEL_I2C=1 chipA・・・

Read Data #CTSEL_I2C=1 chip

A

P

IDLE

Remote Device Side

Figure 17 2-wire serial controller register access protocol

Copyright©2024 THine Electronics, Inc.

39/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E(3) 2-wire serial remote device access. Note: Partially includes access to THCS253.

Figure 18 2-wire serial remote device accessS

Start condition

R

Read command

P

Stop condition

W

Write command

A

ACK

Access from 2-wire serial Controller of Control Device

NACK

Access from 2-wire serial Target of Remote Device

Repeated start condition

Access from THCS253

Sr

Single Byte write
Control Device SideS

Remote Device Side

Remote Device
Address

S

W

Clock Stretching

Remote Device
Address

W

Register
AddressA

SCL LowA

Clock Stretching

Register
AddressA

Write Data

SCL LowA

Clock Stretching

Write Data

A

A

P

SCL LowP

Burst write
Control Device SideS

Remote Device Side

Remote Device
Address

S

W

Clock Stretching

Remote Device
Address

W

Register
AddressA

SCL LowA

Clock Stretching

Register
AddressA

Write Data
1

SCL LowA

Clock Stretching

Write Data
1

A

A

・・・

・・・

A

Write Data#A

SCL Low

Clock Stretching

Write Data#AP

SCL LowAP

I2C detect write command
Neither THCS253 nor remote device

Control Device Side

Remote Device SideS

N/A Device
AddressS

W

N/A Device
Address

SCL
Low

Clock Stretching

W

SCL
Low

P

(0x0B / 0x34 / 0x77 / 0x65)

P

IDLE

IDLE

S

RemoteDevice Address

S

W

RemoteDevice Address

Clock Stretching

W

A

A

P

・・・

P

S

P

・・・

P

SCL Low

THCS253
Device Address

W

A

P

Pull-up

If the remote device side is NACK for the bridged device address,
THCS253 will issue its own stop condition to release the I2C target device.

Figure 19 2-wire serial remote device access protocol

Copyright©2024 THine Electronics, Inc.

40/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
Single Byte read with repeated start condition
Control Device SideS

Remote Device
Address

Remote Device SideS

Clock StretchingW

Remote Device
Address

SCL Low

A

W

Clock Stretching

Register
Address

A

Register
AddressA

Remote Device
AddressSr

SCL LowA

Clock Stretching

R

Remote Device
Address

Sr

A

A

R

SCL
Low

A

Read Data

SCL Low

Read Data

A

P

SCL
Low

P

Single Byte read without repeated start condition
Control Device SideS

Remote Device Side

Remote Device
AddressS

Clock Stretching

R

Remote Device
Address

A

R

A

SCL
Low

A

Read Data 1

SCL Low

Read Data 1

A

P

SCL
Low

P

Burst read with repeated start condition
Control Device SideS

Remote Device
Address

Remote Device SideSW

Clock Stretching

Remote Device
Address

SCL Low

A

W

Clock Stretching

Register
Address

A

Register
Address

Clock StretchingAA

SCL LowA

SCL Low

・・・

AS

Remote Device
AddressA

A

R

Clock Stretching

・・・

A

Clock Stretching

R

Remote Device
Address

Sr

Clock
StretchingA

Read Data 2

Read Data 2

Remote Device
AddressSr

SCL Low

Read Data 1

SCL
Low

A

Read Data #SCL Low

Read Data #A

Read Data 1

A

P

SCL
Low

P

Burst read with stop and start condition
Control Device SideS

Remote Device Side

Remote Device
AddressS

W

Remote Device
Address

Clock StretchingW

SCL Low

A

Register
Address

Clock Stretching

A

Clock Stretching

Register
Address

A

IDLE

P

SCL LowA

A

Read Data 2

Read Data 2

A

SCL LowP

Clock
Stretching

IDLE

・・・

A

Remote Device
AddressS

Clock Stretching

・・・

A

Clock StretchingR

Read Data #

A

R

A

Read Data #SCL LowA

SCL Low

Read Data 1

SCL
Low

A

A

Read Data 1

P

SCL
Low

P

Burst read without repeated start condition
Control Device Side

Remote Device SideS

Remote Device
AddressS

R

Remote Device
Address

Clock Stretching

R

A

A

Read Data 1

Read Data 1

SCL LowA

Clock
StretchingA

Read Data 2

Read Data 2

SCL LowA

Clock
StretchingA・・・

Clock Stretching

・・・

Figure 20 2-wire serial remote device access protocol

Copyright©2024 THine Electronics, Inc.

41/63

A

Read Data #Read Data #SCL Low

SCL
Low

A

A

P

SCL
Low

P

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
I2C detect read commandControl Device SideS

Remote Device
Address

Remote Device SideSR

Clock Stretching

Remote Device
AddressA

R

Read data fromremote deviceA

SCL Low

Read data fromremote device(0x0B / 0x34 / 0x77 / 0x65)
IDLE

THCS253
Device Address

S

Neither THCS253 nor remote device
Clock Stretching
N/A Device

IDLE

P

SCL
Low

A

Read Data from
THCS253

A

R

SCL
Low

A

S

IDLE

P

A

R

AddressN/A Device
Address

S

SCL
Low

A

R

SCL
Low

A

P

IDLE

IDLE

P

If the remote device side is NACK for the bridged device address,
THCS253 will issue its own stop condition to release the I2C target device.

P

IDLE

2Byte addressing device read with repeated start condition
Control Device SideS

Remote Device Side

Remote Device
AddressS

Clock StretchingW

Remote Device
Address

SCL Low

A

W

Regis ter
Addres s(MSB)

A

Regis ter
Addres s(MSB)

Remote Device
AddressSr

SCL Low

Sr

Clock Stretching

R

Remote Device
Address

SCL LowA

Clock Stretching

Register
Addres s(LSB)

A

A

R

Clock Stretching

Regis ter
Addres s(LSB)

A

SCL
Low

A

SCL Low

Read Data

SCL LowA

Read Data

A

A

P

SCL
Low

P

2Byte addressing device read with stop and start condition
Control Device Side

Remote Device SideS

Remote Device
AddressS

W

Remote Device
Address

Clock Stretching

W

A

Register
Address(MSB)SCL Low

A

IDLE

IDLE

S

Clock Stretching

Register
Address(MSB)

A

Remote Device
AddressR

S

Remote Device
Address

A

Register
Address(LSB)SCL Low

Clock Stretching

R

A

Clock Stretching

Register
Address(LSB)

A

42/63

A

Read Data

SCL LowIDLE

P

SCL LowA

Read Data

Figure 21 2-wire serial remote device access protocol

Copyright©2024 THine Electronics, Inc.

A

SCL
Low

A

IDLE

P

P

SCL
Low

P

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.6.8. 2-wire serial expander
The I2C_EXPAND (register) setting determines whether data transmission is performed through or used as an I2C
expander. When used as an I2C expander, the value set in GPIO_OUT_*(*...0~3) is output from the data pins.
The setting of GPIO_OBUF_*(*...0~3) is valid for the output buffer setting. Also, regardless of the I2C_EXPAND
setting, data input is stored in GPIO_IN_*(*...0~3) and can be checked by I2C read. The above functions areavailable only when I2C is used (ENI2C=1).
Table 18 GPIO type setting
Function

Register Name

GPIO
function selectI2C_EXPAND

Description
0: Through(Default)
1: I2C Expander

THCS253(2-wire target)

THCS253(2-wire controller)

GPIO_IN_0-3(reg)
Read fromI2C Master side
register

Data

Data
input

2-wireserialController

Tx

2-wireserialWrite toI2C Slave side
register2-wireserialTargetWrite toI2C Master side
registerDataoutput

1

0

Rx

1

GPIO_OUT_0-3(reg)

Read fromI2C Slave side
register

I2C_EXPAND (reg)

GPIO_OUT_0-3
(reg)
Rx

0

Data
output

Data
input

Tx

Data

GPIO_IN_0-3(reg)

I2C_EXPAND (reg)Figure 22 2-wire serial expander function

Copyright©2024 THine Electronics, Inc.

43/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.7. Direction of GPIO
When DATA_WIDTH (pin) = 0, the CML line data rate is 30 times the sampling clock rate.
When DATA_WIDTH (pin) = 1, the CML line data rate is 50 times the sampling clock rate.
*Primary chip and secondary chip DATAWIDTH should be set the same.
The flow from the primary chip transmitter output to the secondary chip receiver input is defined as downstream.
The flow from the secondary chip transmitter output to the primary chip receiver input is defined as upstream.
By setting OVERRIDE_OEN (register) to 1, the GPIO direction can be freely set for each pin.
A-1

A-2

B-1

B-2

0

0

1

1

OVERRIDE_OE(register)

0

1

0

1

CML data rate

D0/D31(pin)D1/D30(pin)D2/D29(pin)D3/D28(pin)D4/D27(pin)D5/D26(pin)D6/D25(pin)D7/D24(pin)D8/D23(pin)D9/D22(pin)D10/D21(pin)D11/D20(pin)D12/D19(pin)D13/D18(pin)D14/D17(pin)D15/D16(pin)D16/D15(pin)D17/D14(pin)D18/D13(pin)D19/D12(pin)D20/D11(pin)D21/D10(pin)D22/D9(pin)D23/D8(pin)D24/D7(pin)D25/D6(pin)D26/D5(pin)D27/D4(pin)D28/D3(pin)D29/D2(pin)D30/D1(pin)D31/D0(pin)External reference
clock mode
1/tTCIPx30
Internal oscillator
clock mode
1/tOSCx30

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

=> *2
=> *2
=> *2
=> *2
=> *2
=> *2
=> *2
=> *2
=> *2
=> *2
=> *2
=> *2
<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1
<= *2
<= *2
<= *2
<= *2
<= *2
<= *2
<= *2
<= *2
<= *2
<= *2
<= *2
<= *2

External reference
clock mode
1/tTCIPx50
Internal oscillator
clock mode
1/tOSCx50

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
<=
<=
<=
<=
<=

<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1

D31/D0(pin)D30/D1(pin)D29/D2(pin)D28/D3(pin)D27/D4(pin)D26/D5(pin)D25/D6(pin)D24/D7(pin)D23/D8(pin)D22/D9(pin)D21/D10(pin)D20/D11(pin)D19/D12(pin)D18/D13(pin)D17/D14(pin)D16/D15(pin)D15/D16(pin)D14/D17(pin)D13/D18(pin)D12/D19(pin)D11/D20(pin)D10/D21(pin)D9/D22(pin)D8/D23(pin)D7/D24(pin)D6/D25(pin)D5/D26(pin)D4/D27(pin)D3/D28(pin)D2/D29(pin)D1/D30(pin)D0/D31(pin)Data pin of secondary chip

Data pin of primary chip

Mode

Setting

Table 19 GPIO direction for each example
Use case
DATA_WIDTH(pin)“=>" is downstream (GPIO input to the primary chip is GPIO output from the secondary chip)“<=" is upstream (GPIO input to the secondary chip is GPIO output from the primary chip)“<=>" is a pin whose directionality can be selected one by one by internal register setting.
*1 The setting that contradicts the pin relationship between the primary chip and the secondary chip indicated by the pin
name is not allowed.
*2 In the case of Example A-2, "=>" and "<=" other than "<=>" must also be set in the register as shown in the table.

Copyright©2024 THine Electronics, Inc.

44/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
The following table shows the mapping between pins and registers that can be set by setting OVERRIDE_OEN(register) to 1.
Table 20 GPIO OEN_0-3(register) mapping
Controlled terminal mapping
Register Name

GPIO_OEN_0(register)

GPIO_OEN_1(register)

GPIO_OEN_2(register)

GPIO_OEN_3(register)

bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]

Copyright©2024 THine Electronics, Inc.

Description
Primary chip mode

Secondary chip mode

D0/D31(pin)D1/D30(pin)D2/D29(pin)D3/D28(pin)D4/D27(pin)D5/D26(pin)D6/D25(pin)D7/D24(pin)D8/D23(pin)D9/D22(pin)D10/D21(pin)D11/D20(pin)D12/D19(pin)D13/D18(pin)D14/D17(pin)D15/D16(pin)D16/D15(pin)D17/D14(pin)D18/D13(pin)D19/D12(pin)D20/D11(pin)D21/D10(pin)D22/D9(pin)D23/D8(pin)D24/D7(pin)D25/D6(pin)D26/D5(pin)D27/D4(pin)D28/D3(pin)D29/D2(pin)D30/D1(pin)D31/D0(pin)D31/D0(pin)D30/D1(pin)D29/D2(pin)D28/D3(pin)D27/D4(pin)D26/D5(pin)D25/D6(pin)D24/D7(pin)D23/D8(pin)D22/D9(pin)D21/D10(pin)D20/D11(pin)D19/D12(pin)D18/D13(pin)D17/D14(pin)D16/D15(pin)D15/D16(pin)D14/D17(pin)D13/D18(pin)D12/D19(pin)D11/D20(pin)D10/D21(pin)D9/D22(pin)D8/D23(pin)D7/D24(pin)D6/D25(pin)D5/D26(pin)D4/D27(pin)D3/D28(pin)D2/D29(pin)D1/D30(pin)D0/D31(pin)45/63

GPIO direction select{0} : Output{1} : Input

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.8. IO configuration
10.8.1. I/O digital noise filter
THCS253 has digital noise filters for GPIO input (CMOS input noise immunity) and output (CML line noise
immunity), and the digital noise filters can be set simultaneously by setting FILTSEL1 (pin) and FILTSEL0(pin). Each GPIO digital noise filter can be individually enabled by setting GPIO_I_FILTEN_0-3 (register) andGPIO_O_FILTEN_0-3 (register) with OVERRIDE_FILTEN (register)=1. The GPIO_I_FILTEN_0-3(register)and GPIO_O_FILTEN_0-3(register) settings enable each GPIO digital noise filter individually.
The digital filter is disabled until it is enabled by one of the above setting pins or registers.

The number of input/output filter tap can also be set by GPIO_I_FILTSET(register) andGPIO_O_FILTSET(register). The number of filter stages cannot be set for each pin individually.
The data width of (tap_num-1) tFLTCK or less is subject to filtering.
Table 21 Input digital noise filter setting
Setting
OVERRIDE_I_FIL
TEN(register){0}(default)

FILTSEL1(pin)

FILTSEL0
(pin)
0
1
0
1

0
1

GPIO_I_FILTEN_03(register)
-

{0}
{1}

-

{1}

Function

Filternumber of taps
(tap_num)

Digital noise filter
simultaneous setting

Disable4816

digital noise filter
disable（Table 23）
digital noise filter
enable（Table 23）

GPIO_I_FILTSET(register)Setting

Table 22 Output digital noise filter setting
Setting
OVERRIDE_O_FIL
TEN(register){0}(default)

FILTSEL1(pin)
0
1

FILTSEL0
(pin)
0
1
0
1

GPIO_O_FILTEN_0-3(register)
-

{0}
{1}

-

{1}

Copyright©2024 THine Electronics, Inc.

46/63

Function

Filternumber of taps
(tap_num)

Digital noise filter
simultaneous
Setting

Disable4
8
16

Digital noise filter
disable（Table 23）
Digital noise filter
enable（Table 23）

GPIO_O_FILTSET(register)THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
Table 23 GPIO_I_FILTEN_0-3(register) / GPIO_O_FILTEN_0-3(register) mapping
Controlled terminal mapping
Register name

GPIO_I_FILTEN_0(register)
GPIO_O_FILTEN_0(register)

GPIO_I_FILTEN_1(register)
GPIO_O_FILTEN_1(register)

GPIO_I_FILTEN_2(register)
GPIO_O_FILTEN_2(register)

GPIO_I_FILTEN_3(register)
GPIO_O_FILTEN_3(register)bit

Description
Primary chip mode

Secondary chip mode

D0/D31(pin)D1/D30(pin)D2/D29(pin)D3/D28(pin)D4/D27(pin)D5/D26(pin)D6/D25(pin)D7/D24(pin)D8/D23(pin)D9/D22(pin)D10/D21(pin)D11/D20(pin)D12/D19(pin)D13/D18(pin)D14/D17(pin)D15/D16(pin)D16/D15(pin)D17/D14(pin)D18/D13(pin)D19/D12(pin)D20/D11(pin)D21/D10(pin)D22/D9(pin)D23/D8(pin)D24/D7(pin)D25/D6(pin)D26/D5(pin)D27/D4(pin)D28/D3(pin)D29/D2(pin)D30/D1(pin)D31/D0(pin)D31/D0(pin)D30/D1(pin)D29/D2(pin)D28/D3(pin)D27/D4(pin)D26/D5(pin)D25/D6(pin)D24/D7(pin)D23/D8(pin)D22/D9(pin)D21/D10(pin)D20/D11(pin)D19/D12(pin)D18/D13(pin)D17/D14(pin)D16/D15(pin)D15/D16(pin)D14/D17(pin)D13/D18(pin)D12/D19(pin)D11/D20(pin)D10/D21(pin)D9/D22(pin)D8/D23(pin)D7/D24(pin)D6/D25(pin)D5/D26(pin)D4/D27(pin)D3/D28(pin)D2/D29(pin)D1/D30(pin)D0/D31(pin)

[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]

GPIO Input / output
digital noise filter{0}:Disable{1}:Enable

Table 24 Filter tap Setting
Register name

Description

GPIO_I_FILTSET(register)

Input digital noise filter setting
Number of filter tap(tap_num) = GPIO_I_FILTSET+1

GPIO_O_FILTSET(register)

Output digital noise filter setting
Number of filter tap (tap_num) = GPIO_I_FILTSET+1

Copyright©2024 THine Electronics, Inc.

47/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.8.2. LVCMOS Output buffer type configuration
The GPIO output buffer type can be selected between open-drain and push-pull.

All output pins can be switchedsimultaneously by OBUF (pin), or each pin can be set by GPIO_OBUF_0-3 (register) via 2-wire serial interface.
Table 25 Output buffer type configuration
ENI2C
(pin)

Setting
OBUF(pin)

Function

GPIO_OBUF_0-3(register)-

All output pins can be switched to open-drain
simultaneously
All output pins can be switched to push-pull
simultaneously{0}

Set each GPIO output buffer type to open-drain{1}

Set each GPIO output buffer type to push-pull

0
0
1

1

-

Table 26 GPIO_OBUF_0-3(register) mapping
Controlled terminal mapping
Register name

GPIO_OBUF_0(regis
ter)

GPIO_OBUF_1(regis
ter)

GPIO_OBUF_2(regis
ter)

GPIO_OBUF_3(register)

Description

Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]

Copyright©2024 THine Electronics, Inc.

Primary chip mode

Primary chip mode

D0/D31(pin)D1/D30(pin)D2/D29(pin)D3/D28(pin)D4/D27(pin)D5/D26(pin)D6/D25(pin)D7/D24(pin)D8/D23(pin)D9/D22(pin)D10/D21(pin)D11/D20(pin)D12/D19(pin)D13/D18(pin)D14/D17(pin)D15/D16(pin)D16/D15(pin)D17/D14(pin)D18/D13(pin)D19/D12(pin)D20/D11(pin)D21/D10(pin)D22/D9(pin)D23/D8(pin)D24/D7(pin)D25/D6(pin)D26/D5(pin)D27/D4(pin)D28/D3(pin)D29/D2(pin)D30/D1(pin)D31/D3(pin)D31/D0(pin)D30/D1(pin)D29/D2(pin)D28/D3(pin)D27/D4(pin)D26/D5(pin)D25/D6(pin)D24/D7(pin)D23/D8(pin)D22/D9(pin)D21/D10(pin)D20/D11(pin)D19/D12(pin)D18/D13(pin)D17/D14(pin)D16/D15(pin)D15/D16(pin)D14/D17(pin)D13/D18(pin)D12/D19(pin)D11/D20(pin)D10/D21(pin)D9/D22(pin)D8/D23(pin)D7/D24(pin)D6/D25(pin)D5/D26(pin)D4/D27(pin)D3/D28(pin)D2/D29(pin)D1/D30(pin)D0/D31(pin)48/63

GPIO output buffer typeselect{0}:open-drain{1}:push-pull

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.8.3. 5V tolerant IO
Primary chip and Secondary chip are each equipped with 8 5V withstand voltage IOs.
Primary Chip mode (PSSEL=0)

5V Tolerant I/O

Normal I/O

5V Tolerant I/OSecondary Chipmode (PSSEL=1)
Downstream

D0/D31
D1/D30D2/D29D3/D28
D4/D27...
D27/D4
D28/D3
D29/D2
D30/D1
D31/D0

TXP
TXN

RXP
RXN

RXN
RXP

TXN
TXP

D31/D0
D30/D1
D29/D2
D28/D3
D27/D4...
D4/D27
D3/D28
D2/D29D1/D30D0/D31

Upstream

Figure 23 5V tolerant IO

10.8.4. LVCMOS Output drive strength setting
The THCS253 can set the output drive strength of REFOUT, D0 (pin) - D31 (pin), and READY pin with the
TTLDRV (register). High drive setting is recommended when the reference clock frequency is 100 MHz or higher.
Table 27 LVCMOS output drive strength setting
Setting
TTLDRV(register)

Description{0}

Normal(default)

{1}

High

10.8.5. CML output swing voltage and pre-emphasis setting
The CML output driver pre-emphasis compensates for the loss of high-frequency signal due to long-distance or
high-speed transmission.

The CML output swing voltage and pre-emphasis can be set by setting CMLDRV(register) and CMLPRE (register).
Table 28 CML differential output and Pre-emphasis settings
Setting
CMLDRV [1:0](register)
{00}
{01}
{10}
{11}

CMLPRE(register)

CML differential
outputpeak to peakPre-emphasis

Description

{0}
{1}
{0}

400mVpp
400mVpp
600mVpp

0dB (0%)6dB (100%)0dB (0%)

Default{1}

600mVpp3.52dB (50%)-{0}800mVpp

0dB (0%)-{1}800mVpp

0dB (0%)

-

{0}
{1}

Copyright©2024 THine Electronics, Inc.

Prohibition
Prohibition

-

49/63

THine Electronics, Inc.

-

SC: E

THCS253_Rev.1.30_E
10.9. Clock configuration
10.9.1. Sampling clock selectPrimary chip selects either external reference clock sampling or internal oscillator clock sampling with REFEN(pin).
Secondary chip uses SYNCEN (pin) to select whether to operate synchronously with the primary chip clock or
asynchronously with the primary chip.

If SYNCEN = 0 for asynchronous operation, REFEN (pin) is used to

select external reference clock sampling or internal oscillator clock sampling.

When an external reference clock is used, the data sampling clock edge can be selected with RF_IN/OSCSEL0(pin). Similarly, the data output clock edge is selected by RF_OUT/OSCSEL1 (pin). When internal oscillator
clock sampling is selected by REFEN (pin) = 0, the internal oscillator clock frequency can be selected by
RF_OUT/OSCSEL1 (pin) and RF_IN/OSCSEL0 (pin).

Table 29 Sampling Clock and RF_OUT/OSCSEL1, RF_IN/OSCSEL0 Function
PSSEL
(pin)

SYNCEN
(pin)

REFEN
(pin)

REFIN
(pin)

Invalid0-Invalid1

Ext.
reference
clock

0

-

1

Ext.
referenceclock

Invalid-

Invalid-001

RF_OUT/OSCSEL1(pin)

RF_IN/OSCSEL0(pin)

Description

Int. OSC clock sampling frequency setting(OSCSEL1, OSCSEL0)

Sampling with internal oscillator clock
Frequency set by OSCSEL1 and OSCSEL0 (pin)Output data
clock edge setting
RF_OUT

Sampling with external reference clock

Output data
clock edge setting
RF_IN

Int. OSC clock sampling frequency setting(OSCSEL1, OSCSEL0)

Sampling with internal oscillator clock
Frequency set by OSCSEL1 and OSCSEL0 (pin)Output data
clock edge setting
RF_OUT

Sampling with external reference clock

Output data
clock edge setting
RF_IN

Invalid

Sampling with CDR clock1
Invalid

Invalid

Sampling with CDR clock

Table 30 OSC Clock Sampling Frequency and External Clock Input frequency
REFEN
(pin)

RF_OUT/OSCSEL1(pin)

RF_IN/OSCSEL0
(pin)

0

0

0

1

1

0

1

1

-

-

0

1

Copyright©2024 THine Electronics, Inc.

DATA_WIDTH
(pin)
0
1
0
1
0
1
0
1
0
1

50/63

OSC. frequency /Input frequency
20MHz±20%40MHz±20%80MHz±20%
15 - 133.3MHz
9 - 80MHz

CML data rate
480Mbps - 720Mbps
800Mbps - 1200Mbps
960Mbps - 1440Mbps
1600Mbps - 2400Mbps
960Mbps - 1440Mbps
1600Mbps - 2400Mbps
1920Mbps - 2880Mbps
Prohibition
0.45 - 4.0Gbps
0.45 - 4.0Gbps

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.9.2.

Clock edge select (RF_IN, RF_OUT)

When REFEN=1 (external reference clock is used), clock edge switching function is Enable.
The RF_IN/OSCSEL0 pin can be used to set the input data sampling edge when an external reference clock isused, and the RF_OUT/OSCSEL1 pin can be used to set the REFOUT output clock edge. The polarity of RF_IN
and RF_OUT is the clock edge that defines Setup/Hold timing.

When REFEN = 0, the RF_IN and RF_OUT pins are disabled and the clock edge cannot be switched. In this case,the device operates in Fall Edge mode.

Table 31 RF Function
Pin name

Description

RF_IN
RF_OUT

0 : Fall Edge (Default)
1 : Rise Edge

DATA

DATA

REFIN

REFOUT
RF_IN=1

RF_OUT=1

RF_IN=0

RF_OUT=0

Figure 24 RF_IN, RF_OUT Function

Copyright©2024 THine Electronics, Inc.

51/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.10. Spread spectrum clock generator and REFIN(pin) frequency
THCS253 enables spread spectrum clock output by enabling SSCG PLL with SSEN (pin). When 2-wire serialinterface is enabled (ENI2C=1), the modulation frequency and modulation rate of the spread spectrum clock canbe set.
When SYNCEN (pin) = 1, the spread spectrum clock is set only on the transmitter clock side of the primary chip.
When SYNCEN (pin) = 0, it can be multiplied to both primary and secondary chips.
Primary chip

Secondary chip
TX
(Serializer)

OSC

SSCG PLLREFINRX(DeSerializer)

REFEN

REFOUT
ENI2C

Reg

SDA/SSEN

SDA/SSENReg

TX(Serializer)

RX(DeSerializer)

ENI2C
REFOUT

SSCG PLL

REFIN
OSC

REFEN

Figure 25 Spread Spectrum Configuration

Table 32 Spread Spectrum Setting
Register nameSPREAD[4:0] (register)
FMOD[3:0] (register)

Description
Modulation rate setting Modulation rate = SPREAD
Modulation frequency setting

The modulation frequency of the spread spectrum clock is determined by the following formula.

Copyright©2024 THine Electronics, Inc.

52/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.11. PWM signal output function
The THCS253 can output PWM signals from the D2/D29/PWMOUT pins.
Access the PWMH [7:0] and PWML [7:0] registers via the 2-wire serial interface to set the L/H period in 256
steps, and enable PWMOUT with the PWMEN register.
PWM High period = 1/(80MHz±20%) x PWMH(0～255)[ns]
PWM Low period = 1/(80MHz±20%) x PWML(0～255)[ns]Except,When PWML = 0x00 and PWMH = 0x00, D2/D29/PWMOUT pin is fixed low.
When PWML = 0x00 and PWMH ≠ 0x01, D2/D29/PWMOUT pin is fixed high.

10.12. CRC
THCS253 adds CRC data (CRC8) to GPIO signals and during 2-wire serial communication to avoid outputting
abnormal data when bit errors occur. The CRC is inserted once every 4 sampling clocks when DATAWIDTH=1
and once every 6 sampling clocks when DATAWIDTH=0. The CRC data insertion is shown in the figure below.

CLK
Byte0

7:0

127:120

CRC[7:0]

Byte1

I2C

263:256

Byte2

CRC[7:0]

Byte3

125:128

383:376

I2C

Byte4

255:248

CR C[7:0]

I2C

391:384

Figure 26 CRC data when DATAWIDTH=1

CLK
Byte0

7:0

I2C

Byte1
Byte2

119:112

CR C[7:0]

CR C[7:0]

239:232

127:120I2C

247:240

Figure 27 CRC data when DATAWIDTH=0

Copyright©2024 THine Electronics, Inc.

53/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.13. Error detection and notification
10.13.1. READY signal
The THCS253 notifies with READY(pin) when the link between the Primary chip and the Secondary chip isestablished and data transmission and I2C transmission are possible. When the transmitter's PLL, receiver's CDR,
and SSCG PLL (when the spread spectrum clock is enabled) are locked and normal pattern transmission is enabled,
READY(pin)=H is displayed.
When there is no link error such as clock error or off-lock, the READY signal is output high, and data error isnotified from INTN (pin). When a link error is detected, READY (pin) goes low and enters the re-link-up sequence.
During the READY(pin)=L period, data transmission, 2-wire serial communication across devices (access tointernal registers of the chip set to the 2-wire serial interface controller with CTSEL_I2C=1, access to remotedevice registers) is prohibited. Access to the internal registers of the chip set to the 2-wire serial interface target(CTSEL_I2C=0) is possible. Notification from READY (pin) is possible for both Primary chip and Secondary
chip.
Table 33 Operation of READY(pin)
READY
(pin)
L
H

Description
Link not established.
Data transmit and receive is inhibited.
I2C access to chips other than the chip set to CTSEL_I2C=0 is prohibited.
Link established.
Data transmit and receive, I2C access available.

10.13.2. INTN signal
When the THCS253 detects errors in the CRC error check result on the CML line, it signals these as interrupt
causes through INTN (pin). INTN signal is a low active open drain output.
When the 2-wire serial interface is enabled and the interrupt register is enabled, the INTN (pin) transitions fromINTN (high) to low when an error that causes an interrupt occurs, and INTN (pin) = low is maintained until theinterrupt status register is cleared.
When the 2-wire serial interface is disabled, INTN (pin) = L when any interrupt factor occurs.

INTN (pin) = L

is output until the data error is cleared, and returns to INTN (pin) = H (pull-up) when the data error is cleared.

At

this time, the GPIO output signal updates the output data only when INTN (pin) = High, and holds the output
before the error occurs when INTN (pin) = Low.
The THCS253 detects CRC signals inserted in communication packets and notifies the user via INTN (pin).
There are two types of CRC signals: one is embedded in the downstream/upstream GPIO error detection byte andthe other is embedded in the 2-wire serial transmit/receive error detection byte.

Normally, the CRC for 2-wireserial transmission and reception is an invalid signal when 2-wire serial communication is not being used. However,
if noise is mixed in during transmission and the CRC data is corrupted, as it is during communication, a 2-wireserial communication CRC error may occur even if 2-wire serial communication is not being used.

Copyright©2024 THine Electronics, Inc.

54/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
10.14. Standby mode: STANDBY(register)=1
Standby mode is an operation mode that enables data transmission at low sampling rate and low power
consumption. The transition from normal mode to standby mode and from standby mode to normal mode isinitiated by STANDBY (register) access via 2-wire serial.

STANDBY(register) exists only on the 2-wire serial

target side with CTSEL_I2C=0. In standby mode, handshake communication is performed between the primarychip and secondary chip.

Operation can be selected between sampling and data transmission (polling) at intervals

set by STBY_CYCLE (register) and data transmission by detecting changes in the pins for standby mode or I2C
input.

A maximum of eight GPIO signals can be used for data transmission. The number and direction of thenumber of signals used are set by the STBY_NUM_DS (register) and STBY_NUM_US (register) of the primarychip. The number of pins in the downstream direction is set by STBY_NUM_DS (register) and the number ofpins in the upstream direction by STBY_NUM_US (register).

Upon entry into standby mode, if the link was

established in normal mode, the READY signal goes low once, and when handshake communication is established,
the READY signal goes high again to enable signal transmission. The interrupt status register (transmission error
generation interrupt, I2C interrupt, etc.) and INT are cleared during normal operation.

If the opposing device

exits from standby mode or power down after the READY signal goes high, the primary chip side detects no
response from the secondary chip and the secondary chip side detects a timeout in the request interval from theprimary chip and sets the READY signal low. The primary chip issues the first request command 1.5 ms (typ)after entering standby mode. The sampling interval for polling operation can be changed by setting the
STBY_CYCLE register on the primary chip side. No setting is required on the secondary chip side.
Table 34 Standby Mode Operation Select
STANDBY(register)
0
1

STBY_MODE(register)Ignore0(default)

Description
Normal operation
Only polling operation

1

Polling and external trigger operation

1

1

1

1

0

4

4

4

4

4

8

8

8

0

0

1

2

7

8

8

0

1

2

7

8

0

1

8

Down

Down

Down

Down

Down

Up

Down

Down

Down

Down

Down

Down

Down

Down

Up

Up

Up

Down

Down

Down

Down

Down

Down

Down

Down

Up

Up

Up

Down

Down

Down

Down

Down

Down

Down

Down

Up

Up

Up

Down

Down

Down

Down

Down

Down

Down

Down

Up

Up

Up

Up

Down

Down

Down

Up

Up

Up

Normalterminal
handling

Up
Up

Up

Down

Down

Down

Up

Up

Up

Up

Up

Up

Up

Down

Down

Down

Up

Up

Up

Up

Up

Up

Up

Down

Down

Down

D0/D31

D28/D3
D29/D2
D30/D1
D31/D0Normal terminal handlingD3/D28

Normal terminal handlingD2/D29

Normal terminal handlingD1/D30Up

Copyright©2024 THine Electronics, Inc.

55/63

Normalterminal
handling

1

Normal terminal
handling

0

Normal terminal handling

Table 35 STBY_NUM_DS, STBY_NUM_US vs Standby mode data pin state example
STBY_NUM_DS(register)
STBY_NUM_US(register)Up

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
Table 36 Output of normal data pin in standby mode
STBY_DOUT(register)0
1

Description
Hi-Z(Default)
Holds status before standby mode entry

Table 37 Standby Mode Sampling Rate Setting (Primary chip only)
Register
name

STBY_CYCLE(register)

Description
000：50ms
001：100ms(Default)
010：150ms
011：200ms
100：250ms
101：300ms
110：350ms
111：400ms
Values are Typical values. Guaranteed value is ±20% of theabove value due to OSC variation.

Table 38 Registers that need to be set in standby mode
Register Name

Primary chip

Secondary chip

STBY_DRVAs required

As required

STBY_NUM_DS

Required

Not Required

STBY_NUM_US

Required

Not Required

STBY_CYCLE

Required

Not Required

STBY_DOUT

As required

As required

STBY_MODEAs required

Prohibition

STANDBY

Required

Required

Copyright©2024 THine Electronics, Inc.

56/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

11. Register map
Targetaddress
(Hex)

0x00

0x01

Controller
address
(Hex)

0x80

-

Bit
#

R/W

Default（Hex）

Register name

3

R

-

STBY_READY

2

R

-

LINK_READY

0

R

-

INT

2

R/W

0

I2C_CRC

1

R/W

0

US_CRC

0

R/W

0

DS_CRC

2

R/W

0

I2C_CRC_EN

1

R/W

0

US_CRC_EN

0x02

-

0

R/W

0

DS_CRC_EN

0x03

0x83

0

R/W

0

Reserved

0x04

0x84

0

R/W

0

I2C_EXPAND

0x05
0x06
0x07
0x08

0x85
0x86
0x87
0x88

7:0
7:0
7:0
7:0

R
R
R
R

0x00
0x00
0x00
0x00

GPIO_IN_0
GPIO_IN_1
GPIO_IN_2
GPIO_IN_3

0x09

0x89

7:0

R/W

0x00

GPIO_OUT_0

0x0A

0x8A

7:0

R/W

0x00

GPIO_OUT_1

0x0B

0x8B

7:0

R/W

0x00

GPIO_OUT_2

0x0C

0x8C

7:0

R/W

0x00

GPIO_OUT_3

0x0D

0x8D

7:0

R/W

0xFF

GPIO_OEN_0

0x0E

0x8E

7:0

R/W

0xFF

GPIO_OEN_1

0x0F

0x8F

7:0

R/W

0xFF

GPIO_OEN_2

0x10

0x90

7:0

R/W

0xFF

GPIO_OEN_3

0x11

0x91

0

R/W

0

OVERRIDE_OEN

0x12

0x92

7:0

R/W

0xFF

GPIO_OBUF_0

0x13

0x93

7:0

R/W

0xFF

GPIO_OBUF_1

0x14

0x94

7:0

R/W

0xFF

GPIO_OBUF_2

0x15

0x95

7:0

R/W

0xFF

GPIO_OBUF_3

0x16

0x96

7:0

R/W

0x00

Reserved

0x17

0x97

7:0

R/W

0xFF

GPIO_I_FILTEN_0

0x18

0x98

7:0

R/W

0xFF

GPIO_I_FILTEN_1

Copyright©2024 THine Electronics, Inc.

57/63

Description
READY signal status in standby mode
0: READY=L or Normal mode
1: READY=H
READY signal status in normal mode
0: READY=L or standby mode
1: READY=H
INT status (INTN(pin) inversion)
0: No error
1: Error occurred
0: No error
1: 2-wire serial com error occurred
WRITE 1: Error clear
0: No error
1: Upstream error occurred
WRITE 1: Error clear
0: No error
1: Downstream error occurred
WRITE 1: Error clear
0: 2-wire serial come error interrupt enable
1: 2-wire serial come error interrupt disable
0: Upstream error interrupt enable
1: Upstream error interrupt disable
0: Downstream error interrupt enable
1: Downstream error interrupt disable
0 FixedI/O Expander mode
0: Disable（GPIO transceiver mode）
1: Enable
GPIO[7:0] input status monitor
GPIO[15:8]input status monitor
GPIO[23:16]input status monitor
GPIO[31:24]input status monitor
GPIO[7:0] output setting (Applicable only
to I/O expansion mode)
GPIO[15:8] output setting (Applicable only
to I/O expansion mode)
GPIO[23:16] output setting (Applicable
only to I/O expansion mode)
GPIO[31:24] output setting (Applicable
only to I/O expansion mode)
GPIO [7:0] direction select0:output 1:input
GPIO [15:8] direction select0:output 1:input
GPIO [23:16] direction select0:output 1:input
GPIO [31:24] direction select0:output 1:input
GPIO_OEN setting method select0: Input/output default values per use case
1: Register setting GPIO_OEN_0-3
GPIO [7:0] Output buffer type select0:Open Drain 1:Pushpull
GPIO [15:8] Output buffer typeselect0:Open Drain 1:Pushpull
GPIO [23:16] Output buffer typeselect0:Open Drain 1:Pushpull
GPIO [31:24] Output buffer typeselect0:Open Drain 1:Pushpull
Must be 0
GPIO [7:0] input digital noise filter
0:Disable 1:Enable
GPIO [15:8] input digital noise filter
0:Disable 1:Enable

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E
0x19

0x99

7:0

R/W

0xFF

GPIO_I_FILTEN_2

0x1A

0x9A

7:0

R/W

0xFF

GPIO_I_FILTEN_3

0x1B

0x9B

7:0

R/W

0x03

GPIO_I_FILTSET

0x1C

0x9C

0

R/W

0

OVERRIDE_I_FILTEN

0x1D

0x9D

7:0

R/W

0xFF

GPIO_O_FILTEN_0

0x1E

0x9E

7:0

R/W

0xFF

GPIO_O_FILTEN_1

0x1F

0x9F

7:0

R/W

0xFF

GPIO_O_FILTEN_2

0x20

0xA0

7:0

R/W

0xFF

GPIO_O_FILTEN_3

0x21

0xA1

7:0

R/W

0x03

GPIO_O_FILTSET

0x22

0xA2

0

R/W

0

OVERRIDE_O_FLTEN

0x23
0x24
0x25

0xA3
0xA4
0xA5

7:0
7:0
0

R
R
W

0x00
0x00
-

CRC_ERROR_COUNT[15:8]
CRC_ERROR_COUNT[7:0]
CRC_ERROR_COUNT_CLEAR

0x26

0xA6

7:0

R/W

0x64

I2CPERIOD

0x27

0xA7

7:0

R/W

0x64

Reserved

Copyright©2024 THine Electronics, Inc.

58/63

GPIO [23:16] input digital noise filter
0:Disable 1:Enable
GPIO[31:24] input digital noise filter
0:Disable 1:Enable
Input digital noise filter setting
Number of filter tap = GPIO_I_FILTSET+1
Input digital noise filter enable setting
method0: FILTSEL1(pin) and FILTSEL0(pin)1: GPIO_I_FILTEN_0-3(register)
GPIO[7:0] output digital noise filter
0:Disable 1:Enable
GPIO[15:8] output digital noise filter
0:Disable 1:Enable
GPIO[23:16] output digital noise filter
0:Disable 1:Enable
GPIO[31:24] output digital noise filter
0:Disable 1:Enable
Output digital noise filter setting
Number of filter tap =GPIO_O_FILTSET+1
Output digital noise filter enable setting
method0: FILTSEL1(pin) and FILTSEL0(pin)1: GPIO_I_FILTEN_0-3(register)
Number of CRC error (MSB 8bit)
Number of CRC error (LSB 8bit)
1 Write : CRC ERROR COUNT[15:0] clear
I2C Controller Bit Rate
10,000/I2CPERIOD kbps

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

0x28

0x29

7:4

R/W

0x6

I2C_WDT_STBY

3:0

R/W

0xF

I2C_WDT

4

R/W

0

STBY_DRV

3

R/W

0

CMLPRE

2:1

R/W

0x1

CMLDRV

0R/W

0TTLDRV

0xA8

0xA9

0x2A

0xAA

0

R/W

0

Reserved

0x2B

0xAB

4:0

R/W

0x05

SPREAD

0x2C

0xAC

2:0

R/W

0x6

FMOD

0x2D

0xAD

1
0

R/W
R/W

0
0

Reserved
Reserved

Copyright©2024 THine Electronics, Inc.

59/63

2-wire serial controller / target watch dog
timer (Standby)
0 : Watch dog timer disable
1: 50ms
2: 151ms
3: 352ms
4: 755ms
5: 1.56s
6: 3.17s
7: 6.39s
8: 12.8s
9: 25.7s
10: 51.5s
11: 103s
12: 206s
13: 412s
14: 825s
15 : 1650s
2-wire serial controller / target watch dog
timer (Normal operation)
Setting value of controller >= Setting valueof target
0: Watch dog timer disable
Controller
Target1:
0.0123ms
0.0246ms
2:0.0369ms
0.0738ms
3:0.0860ms
0.172ms
4:
0.184ms
0.368ms
5:0.381ms
0.762ms
6:0.774ms
1.55ms7:
1.56ms3.12ms8:3.13ms6.26ms9:6.28ms12.6ms
10: 12.6ms
25.2ms
11: 25.2ms
50.4ms
12: 50.3ms
101ms
13: 101ms
202ms
14: 201ms
402ms
15: 403ms
806ms
Standby mode CML differential output
voltage setting
0: 200mV 1: 300mV
Normal mode CML differential Preemphasis setting
0:0dB (default) 1: Depends on the
CMLDRV
Normal mode CML differential output
voltage setting
0x0: 200mV
0x1: 300mV
0x2: 400mV
0x3: Prohibition
LVCMOS output drive strength setting
0: Normal
1: HighMust be 0
SSCG modulation rate setting
Modulation rate = SPREAD * ±0.1%
Maximum ±0.5%
SSCG modulation frequency(fmod)Setting
Maximum 30kHz

Must be 0
Must be 0

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

0x2E

0xAE

7:0

R/W

0x00

PWMH

0x2F

0xAF

7:0

R/W

0x00

PWML

0x30

0xB0

0

R/W

0

PWM_EN

7:4

R/W

0x4

STBY_NUM_DS

3:0

R/W

0x4

STBY_NUM_US

0x31

0xB1

0x32

0xB2

2:0

R/W

0x1

STBY_CYCLE

0x33

0xB3

0

R/W

0

STBY_DOUT

0x34

0xB4

0

R/W

0

STBY_MODE

0x35
0x36

0xB6

0x37

0xB7

0x38
0x39
0x3A
0x3B
0x3C
0x3D

0xB8
0xB9
0xBA
0xBB
0xBC
0xBD

0
0
7:4
3:0
7:0
7:0
3:0
7:0
4:0
7:0

R/W
R/W
R
R
R/W
R/W
R/W
R
R
R/W

0
0
0
0
0x0F
0x1F
0x4
0
0
0x00

STANDBY
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Copyright©2024 THine Electronics, Inc.

60/63

PWMH period
0x00: When PWML=0x00, L fixed
0x01: H period 1 clock, (WhenPWML=0x00, H fixed)~
0xFF: H period 255 clock
PWML period
0x00: When PWML=0x00, L fixed, When
PWMH=0x01, H fixed.
0x01: H period 1 clock,~
0xFF: H period 255 clock
PWM output enable
Number of Standby mode downstream
GPIO setting: Maximum 0x8(0x9-0xF is considered 0x8)
*Set primary chip only
Number of Standby mode upstream GPIO
setting: Maximum 0x8(0x9-0xF is considered 0x8)
*Set primary chip onlyStandby mode polling period setting*Set primary chip only
0x0: 50ms
0x1: 100ms
0x2: 150ms
0x3: 200ms
0x4: 250ms
0x5: 300ms
0x6: 350ms
0x7: 400ms
Standby mode static GPIO output status*Set by primary chip/secondary chip
respectively
0: Hi-Z (default)
1: Holds status before standby mode
entryStandby mode hand shake com start
condition
0: Polling operation
1: Polling operation and external trigger
0: Normal operation 1: Standby
Must be 0
Must be 0
Must be 0
0x0F fixed
0x1F fixed
0x4 fixed
Must be 0
Must be 0
Must be 0

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

12. Package
ccc C

A
A2

D

E

A3
A1
0.10

C

1 PIN INDEXTOP VIEW

SIDE VIEW

D2

L

1.10

0.45

E2

1.10

SEATING
PLANE

b
1PIN INDEX
0.20R

e

L

BOTTOM VIEW

Unit mm
Symbol
A
A1
A2
A3
b
D
D2
E
E2
L
e
R
ccc

Items
Mounting HeightStandoffTerminal Width
Body Length
Exposed Length
Body Width
Exposed Width
Pitch
Coplanarity

Min.
0.18
5.90
5.90
0.35
0.09

Nom.
0.65
(0.20)
0.25
9.00 BSC
6.00
9.00 BSC
6.00
0.40
0.50 BSC
0.05

Max.
0.90
0.05
0.70
0.30
6.10
6.10
0.45
-

Figure 28 64-pin QFN package physical dimension

Copyright©2024 THine Electronics, Inc.

61/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

13. Reference land pattern

6.00

6.00

0.50

1.10

1.10

0.25

0.50

(Note)
Please carefully consider your SMT conditions (Material of substrate, Solder Composition, Reflow Condition and so on), and adjusts
the Land Pattern at your own risk.
If there is any inconsistency or conflict between the English and Japanese versions, the English version shall prevail.

Copyright©2024 THine Electronics, Inc.

62/63

THine Electronics, Inc.

SC: E

THCS253_Rev.1.30_E

14. Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

Copyright©2024 THine Electronics, Inc.

63/63

THine Electronics, Inc.

SC: E