THAN0084_Rev.3.30_E

Application Note

THAN0084_Rev.3.30_E

THC63LVD1027/THC63LVD1027D Application Note
Mode setting, System Diagram and PCB Design Guide

Date

RevisionContents

2008/12/03

Rev.1.00_E

New created

2010/03/03

Rev.1.10_E

Caution for LVDS line connection is added

2010/03/11

Rev.1.20_E

Some descriptions are altered.

2010/06/07

Rev.1.30_E

Some descriptions are altered.

2011/09/13

Rev.1.40_E

Some descriptions are altered.

2013/11/07

Rev.3.00_E

Some descriptions are altered.

2016/07/07

Rev.3.10_E

4.7nF capacitor is supposed to be placed on VDD.

2020/06/07

Rev.3.20_E

Modified for THC63LVD1027D

2020/10/28

Rev.3.30_E

Caution for RS/PD/MODE1/MODE0 connection

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Contents
1.Mode Setting ........................................................................................................ P.3
2.Signal Flow for Each Setting ............................................................................... P.3
3.Output Control / Fail Safe .................................................................................... P.4
4.Example of System Diagram................................................................................ P.5
5.Note ...................................................................................................................... P.9
6.PCB Design Guide Line ..................................................................................... P.11

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1. Mode Setting
Input/Output

MODE1

MODE0

(Input mode)(Output mode)

H: Single

H: Single

L: Dual

L: Dual

CLK in

L

L

Hi-z

L

L

Hi-z

H

L

CLK in

L

H

--

H

H

RCLK2+/-

Dual-In/Dual-Out(Fig.2-1, 3-1)
Distribution(Fig.2-2, 3-2)
Single-In/Dual-Out(Fig.2-3, 3-3)
Dual-In/Single-Out(Fig.2-4, 3-4)
Reserved

2. Signal Flow for Each Setting
Dual-In / Dual-Out
CLK
FrequencyfDistribution mode

RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-

TA1+/CLK
TB1+/Frequency
TC1+/f
TD1+/TE1+/DATA RateTCLK1+/f

CLK
FrequencyfTA2+/CLK
TB2+/Frequency
TC2+/fTD2+/TE2+/DATA RateTCLK2+/f

RA2+/RB2+/RC2+/RD2+/DATA Rate RE2+/f
RCLK2+/-

CLK
FrequencyfRA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-

Hi-z
Must beHi-zTA1+/CLK
TB1+/Frequency
TC1+/f
TD1+/TE1+/DATA RateTCLK1+/f

Same Data

RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/-

TA2+/CLK
TB2+/Frequency
TC2+/fTD2+/TE2+/DATA RateTCLK2+/f=TCLK1+/-=TCLK1+/-

Fig2-1

Fig2-2Single-In / Dual-Out

Dual-In / Single-Out

CLK
FrequencyfRA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-

TA1+/CLK
TB1+/Frequency
TC1+/f/2
TD1+/TE1+/DATA RateTCLK1+/f/2

CLK
FrequencyfRA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-

TA1+/CLK
TB1+/Frequency
TC1+/2f
TD1+/TE1+/DATA RateTCLK1+/2f

RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/-

TA2+/CLK
TB2+/Frequency
TC2+/f/2
TD2+/TE2+/DATA RateTCLK2+/f/2

CLK
FrequencyfTA2+/TB2+/TC2+/TD2+/TE2+/TCLK2+/-

Hi-z
Must beHi-z

RA2+/RB2+/RC2+/RD2+/DATA Rate RE2+/f
RCLK2+/-

Fig2-3Copyright©2020 THine Electronics, Inc.

Hi-z

Fig2-4

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3. Output Control / Fail Safe
THC63LVD1027/THC63LVD1027D(“THC63LVD1027(D)”) has a function to control output depending on
LVDS input condition.

PD

RCLK1+/-RCLK2+/-

OutputL**

All Hi-z

H

Hi-z

*

All Hi-z

H

CLK in

CLK inRefer to p.3 Mode Setting #H

CLK inHi-zRefer to p.3 Mode Setting #* : Don’t care
# : If a particular input data pair is Hi-z, the corresponding output data become L according to LVDS DC spec.
For fail-safe purpose, all LVDS input pins are connected to VDD via resistance for detecting state of Hi-z.
VDD

LVDS input bufferInternal circuit of THC63LVD1027(D)Copyright©2020 THine Electronics, Inc.

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4. Example of System Diagram
4.1) Dual-In/Dual-Out

100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm

RA1-

TA1-

RA1+

TA1+

RB1-

TB1-

RB1+

TB1+

RC1-

TC1-

RC1+

TC1+

RCLK1-TCLK1-RCLK1+TCLK1+

RD1-

TD1-

RD1+

TD1+

RE1-

TE1-

RE1+

TE1+

RA2-

TA2-

RA2+

TA2+

RB2-

TB2-

RB2+

TB2+

RC2-

TC2-

RC2+

TC2+

RCLK2-TCLK2-RCLK2+TCLK2+

RD2-

TD2-

RD2+

TD2+

RE2-

TE2-

RE2+

TE2+

100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm

*1

*1

GND

PCB(Transmitter)

VDD

*2

*2

220uF

10uF

VDD (Pin#4,29)

*4

RS

JP

GND

PCB(Receiver)

VDD

VDD

VCC(3.3V)
F.Bead

GND

GND

GND
VDD (Pin#36,61)

VDD*3
0.1uF for Pin4, Pin29 each
VDD

*3
0.1uF+4.7nF for Pin36, Pin61 each

GND

*4
PD

CAP

0.1uF

CAP
*4
MODE0
CAP
Exposed PAD GND

0.1uF

MODE1

*4

0.1uF

PCB(THC63LVD1027(D))*1 Connect each PCB GND with low impedance cable.

Fig3-1*3 Place de-coupling capacitors (0.1uF for all and parallel 4.7nF for Pin36/61) close to each VDD pin one by one.

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4.2) Distribution
THC63LVD1027(D)100ohm100ohm100ohm100ohm100ohm100ohm

Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z

RA1-

TA1-

RA1+

TA1+

RB1-

TB1-

RB1+

TB1+

RC1-

TC1-

RC1+

TC1+

RCLK1-TCLK1-RCLK1+TCLK1+

RD1-

TD1-

RD1+

TD1+

RE1-

TE1-

RE1+

TE1+

RA2-

TA2-

RA2+

TA2+

RB2-

TB2-

RB2+

TB2+

RC2-

TC2-

RC2+

TC2+

RCLK2-TCLK2-RCLK2+TCLK2+

RD2-

TD2-

RD2+

TD2+

RE2-

TE2-

RE2+

TE2+

100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm

GND

RS

JP

*2

*2

220uF

10uF

RB+
RCRC+
RCLK-

RD-

GND
LVCC
LGND
PVCC

RA+
RBRB+
RCRC+

F.BeadPGND
R/F
CLKOUT/PDWN
OERD+ RA6 - RA0
RB6 - RB0
RE- RC6 - RC0
RD6 - RD0
RE+ RE6 - RE0

RA-

VCC(3.3V)*3

7
7
7
7
7

0.001uF 0.1uF
VCC

VCC(3.3V)*3

GND
LVCC
LGND
PVCC

F.BeadPGND
R/F

RCLKRCLK+RD-

CLKOUT/PDWN
OERD+ RA6 - RA0
RB6 - RB0
RE- RC6 - RC0
RD6 - RD0
RE+ RE6 - RE0

7
7
7
7
7

GND

VDD

VDD

VDD

RB-

0.001uF 0.1uF
VCC

*1
GND

PCB(Transmitter)

F.Bead

RA+

RCLK+

*1
GND

VCC(3.3V)RA-

VDD (Pin#4,29)*5

GND
VDD (Pin#36,61)

VDD

0.1uF for Pin4, Pin29 each
VDD

*4
0.1uF+4.7nF for Pin36, Pin61 each

GND

*5

PD

CAP

0.1uF

CAP
*5
MODE0
CAP
Exposed PAD GND

0.1uF

MODE1

*5

PCB(Receiver)

*4

0.1uF

PCB(THC63LVD1027(D))*1 Connect each PCB GND with low impedance cable.
*2 Select the suitable value for the system.
Fig3-2*3 Supply voltage of THC63LVD104C is 3.3V(Typ).
*4 Place de-coupling capacitors (0.1uF for all and parallel 4.7nF for Pin36/61) close to each VDD pin one by one.
*5 Connect to VDD or PCB GND without resistor.
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4.3) Single-In/Dual-Out
THC63LVD1027(D)100ohm100ohm100ohm100ohm100ohm100ohm

Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z

RA1-

TA1-

RA1+

TA1+

RB1-

TB1-

RB1+

TB1+

RC1-

TC1-

RC1+

TC1+

RCLK1-TCLK1-RCLK1+TCLK1+

RD1-

TD1-

RD1+

TD1+

RE1-

TE1-

RE1+

TE1+

RA2-

TA2-

RA2+

TA2+

RB2-

TB2-

RB2+

TB2+

RC2-

TC2-

RC2+

TC2+

RCLK2-TCLK2-RCLK2+TCLK2+

RD2-

TD2-

RD2+

TD2+

RE2-

TE2-

RE2+

TE2+

100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm

*1

*1

GND

GND

PCB(Transmitter)

VDD

*2

*2

220uF

10uF

VDD (Pin#4,29)

*4

JP

GND

PCB(Receiver)

VDD

VDD

VCC(3.3V)
F.Bead

GND

RS

GND
VDD (Pin#36,61)

VDD*3
0.1uF for Pin4, Pin29 each
VDD

*3
0.1uF+4.7nF for Pin36, Pin61 each

GND

*4
PD

CAP

0.1uF

CAP
*4
MODE0
CAP
Exposed PAD GND

0.1uF

MODE1

*4

0.1uF

PCB(THC63LVD1027(D))*1 Connect each PCB GND with low impedance cable.
*2 Select the suitable value for the system.

Fig3-3*3 Place de-coupling capacitors (0.1uF for all and parallel 4.7nF for Pin36/61) close to each VDD pin one by one.
*4 Connect to VDD or PCB GND without resistor.

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4.4) Dual-In/Single-Out
THC63LVD1027(D)100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm100ohm

RA1-

TA1-

RA1+

TA1+

RB1-

TB1-

RB1+

TB1+

RC1-

TC1-

RC1+

TC1+

RCLK1-TCLK1-RCLK1+TCLK1+

RD1-

TD1-

RD1+

TD1+

RE1-

TE1-

RE1+

TE1+

RA2-

TA2-

RA2+

TA2+

RB2-

TB2-

RB2+

TB2+

RC2-

TC2-

RC2+

TC2+

RCLK2-TCLK2-RCLK2+TCLK2+

RD2-

TD2-

RD2+

TD2+

RE2-

TE2-

RE2+

TE2+

100ohm100ohm100ohm100ohm100ohm100ohm

Hi-z

Hi-z

Hi-z

Hi-z

Hi-z

Hi-z

*1

*1

GND

GND

PCB(Transmitter)

VDD

*2

*2

220uF

10uF

VDD (Pin#4,29)

*4

JP

GND

PCB(Receiver)

VDD

VDD

VCC(3.3V)
F.Bead

GND

RS

GND
VDD (Pin#36,61)

VDD

0.1uF for Pin4, Pin29 each
VDD

*3
0.1uF+4.7nF for Pin36, Pin61 each

GND

*4

PD

*3

CAP

0.1uF

CAP
*4
MODE0
CAP
Exposed PAD GND

0.1uF

MODE1

*4

0.1uF

PCB(THC63LVD1027(D))*1 Connect each PCB GND with low impedance cable.
Fig3-4*2 Select the suitable value for the system.
*3 Place de-coupling capacitors (0.1uF for all and parallel 4.7nF for Pin36/61) close to each VDD pin one by one.
*4 Connect to VDD or PCB GND without resistor.

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5. Note5.1) LVDS input pin connection
When LVDS line is not drived from the previous device, the line is pulled up to 3.3V internally in
THC63LVD1027(D). This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose
operating condition is lower voltage power supply than 3.3V. This phenomenon may happen at power on phase of thewhole system including THC63LVD1027(D). One solution for this problem is PD=L control during no LVDS input
period because pull-up resistors are cut off at power down state.
If this situation is not avoidable and PD=L is hard to apply, there still is several remedy; therefore please contact tomspsupport@thine.co.jp(for FAE mailing list)

LVDS Tx side PCB

LVDS Rx side PCB
VDD

Low VDD

THC63LVD1027(D)
LVDS Txor
LVDS Tx
integrated
device
LVDS input bufferInternal circuit of THC63LVD1027(D)5.2) Power On Sequence
Don’t input RCLK#+/- before THC63LVD1027(D) is on in order to keep absolute maximum ratings.
If it is not avoidable, please contact tomspsupport@thine.co.jp(for FAE mailing list)

5.3) Cable Connection and Disconnection
Don’t connect and disconnect the LVDS cable, when the power is supplied to the system.

5.4) GND Connection
Connect the each GND of the PCB which Transmitter, Receiver and THC63LVD1027(D) on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.

5.5) De-coupling capacitor
THC63LVD1027(D) requires appropriate de-coupling capacitor placement on VDD.
Especially, VDD pin 36 and pin 61 requires 0.1uF and 4.7nF capacitor parallel placement close to IC pins.

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5.6) Multi Drop Connection
Multiple counterpart use such as following systems are not recommended.

THC63LVD1027(D)TCLK1,2-

LVDS RxTCLK1,2+

LVDS Rx

5.7) Asynchronous use
Asynchronous use such as following systems are not recommended.
If it is not avoidable, please check if datasheet tCK12 spec can be kept or not and more further, please contact tomspsupport@thine.co.jp

CLKOUT
IC(for FAE mailing list)

LVDS Tx

RCLK1+/-LVDS Tx

RCLK2+/-DATAOUT
CLKOUT

THC63LVD1027(D)DATAOUT

Asynchronous use such as following systems are not recommended.
If it is not avoidable, please contact tomspsupport@thine.co.jp(for FAE mailing list)

CLKIN
TCLK1+/-LVDS Rx

DATAIN

THC63LVD1027(D)TCLK2+/-

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ICLVDS Rx

DATAIN

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6. PCB Design Guide Line
General Guideline
•
•
•
•
•

Use 4 layer PCB (minimum).
Locate by-pass capacitors close to the device pins to a maximum extent.
Make the loop minimum which is consist of Power line and Gnd line
Use large Gnd plane
Separate VDD power supply for each block via ferrite bead

LVDS Traces• Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector, and cable) should be wellbalanced.(Keep all these differential impedance and the length of media as same as possible.).

•
•
•
•
•

Minimize the distance between traces of a pair (S1) to maximize common mode rejection. See following figure.
Place adjacent LVDS trace pair at least twice (>2 x S1) as far away as possible.
Avoid 90 degree bends and sharp angles.
Minimize the number of VIA on LVDS traces.
Match impedance of PCB trace, connector, media (cable) and termination to minimize reflections (emissions) for
cabled applications (typically 100ohm differential mode characteristic impedance).

• Place terminal resister close to the Receiver pins to a maximum extent.
• To plase common mode choke coil is desired for EMI reduction.

S1> 2 x S1

GND
+SignalCopyright©2020 THine Electronics, Inc.

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THAN0084_Rev.3.30_E

Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to thecustomer's design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them
immediately.
3. This material contains THine’s copyright, know-how or other proprietary. Copying or disclosing to third parties thecontents of this material without THine’s prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, THine will be
exempted from the responsibility unless it directly relates to the production process or functions of the product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video device, officeautomation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine
device. This product must not be used for applications that require extremely high-reliability/safety such as aerospacedevice, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device
related to critical care, or any kind of safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of IATF16949 ("the Specified Product") in this data sheet. THine accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands
and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user andTHine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public
damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support
warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine
based on the user’s request, testing of all functions and performance of the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods
under the Foreign Exchange and Foreign Trade Act.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses.

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