Medium-term Management Plan Progress and
New Financial ModelMay 29, 2018
Toshiki Kawai
Representative Director, President & CEO

CORP IR / May 29, 20181

Forward Looking Statements
 Disclaimer regarding forward-looking statement
Forecast of TEL’s performance and future prospects and other sort of information published are made based on information
available at the time of publication. Actual performance and results may differ significantly from the forecast described here due tochanges in various external and internal factors, including the economic situation, semiconductor/FPD market conditions,
intensification of sales competition, safety and product quality management, and intellectual property-related risks.
 Processing of numbers
For the amount listed, because fractions are rounded down, there may be the cases where the total for certain account titles does
not correspond to the sum of the respective figures for account titles. Percentages are calculated using full amounts, before
rounding.
 Exchange risk
In principle, export sales of Tokyo Electron’s mainstay semiconductor and FPD production equipment are denominated in yen.
While some settlements are denominated in dollars, exchange risk is hedged as forward exchange contracts are made individuallyat the time of booking. Accordingly, the effect of exchange rates on profits is negligible.
 Disclaimer regarding IHS Markit data (Page 92, 95, 97)
The IHS Markit reports and information referenced herein (the "IHS Markit Materials") are the copyrighted property of IHS Markit Ltd. (“IHS Markit”) and represent data, research, opinions or
viewpoints published by IHS Markit, and are not representations of fact. The IHS Markit Materials speak as of the original publication date thereof (and not as of the date of this offering
document). The information and opinions expressed in the IHS Markit Materials are subject to change without notice and IHS Markit has no duty or responsibility to update the IHS Markit
Materials. Moreover, while the IHS Markit Materials reproduced herein are from sources considered reliable, the accuracy and completeness thereof are not warranted, nor are the opinions
and analyses which are based upon it. To the extent permitted by law, IHS Markit shall not be liable for any errors or omissions or any loss, damage or expense incurred by reliance on the
IHS Markit Materials or any statement contained herein, or resulting from any omission. No portion of the IHS Markit Materials may be reproduced, reused, or otherwise distributed in any
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IHS Markit and the IHS Markit globe design are trademarks of IHS Markit. Other trademarks appearing in the IHS Markit Materials are the property of IHS Markit or their respective owners.

 Disclaimer regarding Gartner data (Page 53, 54, 84)
All statements in this presentation attributable to Gartner represent Tokyo Electron’s interpretation of data, research opinion or viewpoints published as part of a syndicated subscription
service by Gartner, Inc., and have not been reviewed by Gartner. Each Gartner publication speaks as of its original publication date (and not as of the date of this presentation). The opinions
expressed in Gartner publications are not representations of fact, and are subject to change without notice.

CORP IR / May 29, 2018
FPD: Flat panel display

2

Today’s Key Messages
 Semiconductor production equipment market will continue to grow
Approaching $60B+ phase Making good progress in business development in focus areas
Outperform market growth Establish new financial model towards further growth
Aim for world class ROE and 30%+ operating margin in the medium- to long-term

CORP IR / May 29, 20183

FY2018 (April 2017-March 2018) Highlights
Net Sales andGross Profit Margin
1,200

Operating Income andOperating Margin

Net sales (¥B)
39.6%

Operating income (¥B)

40.2%

42.0%

Operating margin

24.9%
25.0%

40.3%
200

33.0%

14.4%

612.1

613.1

281.1

663.9

11.8%

15.0%

115.2
71.8

116.7

-3.3%

32.2




0.0%

0

FY'15

FY'16

FY'17

FY'18

FY'14

FY'15

77.8

5.0%

88.1

FY'14

204.3

80

155.6

5.3%

0

13.0%

10.0%

100

799.7

400

20.0%

17.6%

1,130.7

180

Net income attributable toowners of parent (¥B)
ROE
19.1%

19.5%
800

29.0%

30.0%

300

Gross profit margin

Net Income Attributable to
Owners of Parent and ROE

FY'16

FY'17

FY'18

-19.4

-20

FY'14

FY'15

FY'16

FY'17

FY'18

Net sales +41% YoY driven by the growth of the SPE* and FPD** market andexpansion of market share in focus areas
Operating income and net income attributable to owners of parent reached
new record highs

CORP IR / May 29, 2018 * SPE: Semiconductor production equipment** FPD: Flat panel display

4

FY2019 Financial Estimates(Billion yen)

FY2018(Actual)

FY2019 (Estimates)
H1

H2

Full year

Full year
YoY change

Net sales

1,130.7

690.0

710.0

1,400.0+23.8%

SPE
FPD

1,055.2
75.0

634.0
56.0

654.0
56.0

1,288.0
112.0+22.1%+49.2%

Gross profit

475.0

288.0

310.0

598.0

+122.9Gross profit margin

42.0%

41.7%

43.7%

42.7%

+0.7pts

SG&A expenses
Operating income

193.8
281.1

115.0
173.0

117.0
193.0

232.0
366.0

+38.1
+84.8

Operating margin

24.9%

25.1%

27.2%

26.1%

+1.2pts

Income before income taxes
Net income attributable toowners of parent

275.2

173.0

193.0

366.0

+90.7

204.3

128.0

142.0

270.0

+65.6

1,245.48

779.95-

1,645.20+399.72

Net income per share (Yen)

Expect to generate record high profits* for third consecutive year
CORP IR / May 29, 2018

* Net income attributable to owners of parent

5

Substantially Outperform Market Growth FY’18 results (compared to FY’17)⇒

TEL sales growth +41.4% (WFE* market growth** +37%)
Operating income growth +80.6%

 FY’19 estimate (compared to FY’18)⇒ TEL sales growth +23.8% (WFE market growth +15%)
Operating income growth +30.2%

Grow share in focus areas (etch, cleaning, ALD systems)* WFE (Wafer fab equipment): The semiconductor production process is divided into front-end production, in which circuits are formed on wafers and inspected, and back-end production, in
which wafers are cut into chips, assembled and inspected again. Wafer fab equipment refers to the production equipment used in front-end production and in wafer-level packaging production.
** WFE market growth rates are for the calendar year.

CORP IR / May 29, 20186

Medium-term Management Plan Progress

WFE*

FY’16
(Actual)FY’17(Actual)

FY’18(Actual)FY’19(Estimate)

Market size

$31B

$37B

$51B

$58B

Net sales¥663.9B¥799.7B

Operatingmargin

17.6%

19.5%

24.9%

26.1%

ROE

13.0%

19.1%

29.0%

-

¥1,130.7B ¥1,400.0B

FY’20
financial model
$42B
$45B
¥1,050.0B ¥1,200.0B
24%

26%

20-25%

Proceed according to plan in both strengthening competitiveness of
products and raising profitability* WFE (Wafer fab equipment): The semiconductor production process is divided into front-end production, in which circuits are formed on wafers and inspected, and back-end production, in
which wafers are cut into chips, assembled and inspected again. Wafer fab equipment refers to the production equipment used in front-end production and in wafer-level packaging production.
FY2016 (CY2015) market size does not include equipment for wafer-level packaging.

CORP IR / May 29, 2018

7

We Are Now at a Turning Point
World IP traffic

Data centric

Mobile centric
We are here

Computer centric
1970

1980

1990

2000

2010

2020

2030

With the spread of IoT technology the age of big data is beginning
CORP IR / May 29, 20188

Applications/services That Big Data Will Realize
Telemedicine

Smart cities
Smart grids

Smart mobility

Autonomous
driving

Smart fabs

Industrial robots

Demand for further technological evolution of semiconductors
CORP IR / May 29, 2018

9

Big Investment in the Cloud

Hyperscale data center*
construction boom

338 ➡ 628
CY2016

CY2021locations
Source: CISCO

 Continuing data growth (CAGR 27%**)
 Necessary to replace servers every 5 years* CISCO’s definition: Operator with annual revenue of over $1B from IaaS/PaaS, over $2B from SaaS, over $4B from internet, search and social networking, and over $8B in e-commerce/payment processing** Source: CISCO GCI2017.2 CAGR of data center traffic 2016-2021

Continued strong demand for memory
CORP IR / May 29, 201810

New Trend: Edge Computing

Cloud• Too much data to process quickly• Delay: Several hundred milliseconds

computingEdge• Processes data in realtime from nearby• Delay: Several
milliseconds

computing
Health platforms

Autonomous driving

Smart fabs

Market growth for services where delay is unacceptable

CORP IR / May 29, 2018

Leading-edge chips with high speed andlow power consumption are essential

11Rising Added-value in SPE
WFE investment (100k WSPM*, greenfield/TEL estimate)
DRAM

Logic

3D NAND

~$18B

~$7B

2Z

1X

1Y

~$7B

4X

6/7X

9X

14/16nm

10nm

7nm

Expanded business opportunities for SPE manufacturers on arrivalof new applications and rising level of technological difficulty
CORP IR / May 29, 2018

* WSPM: Wafer starts per month12

Higher Sophistication of Display Technologies
Color filter
LCD

Emissive
layer
TFT

TFT
Backlight

Increasing
screen size OLED
Increasing Design
resolution flexibility

LCD

OLED

TV:
FHD

4K

Mobile, VR:

300 ppi

8K1000 ppi

Edge bent Flexible
Flexible, edge bent, free format

Expanded business opportunities due to technological change
CORP IR / May 29, 2018

13

WFE Market Outlook
WFE market by application*

$58B

$61B

$62B

$63B

$51B
WLP

$37B

DRAM

Non-volatile memory
Logic foundry

Logic & others(MPU, AP, others)

CY'16

CY'17

CY'18*

CY'19*

CY'20*

CY'21** TEL estimate

WFE market approaching $60B+ phase
CORP IR / May 29, 201814

New Financial Model (FY2021)
WFE

Market size

$55B

$62B

Net sales¥1,500.0B¥1,700.0B

26.5%

28%

Operating marginROE

30-35%

Aim for a world class operating margin of 30%+in the medium- to long-term
CORP IR / May 29, 201815

Rationale for Revisions to Financial Model Business development in focus areas is making good progress, and achievementof the financial model announced in May 2017 is in sight Over the past year it has become widely recognized that the semiconductor
industry has entered a new growth stage on the expansion of new applications
that support social infrastructure such as AI and IoT
 On outlook for further growth in the semiconductor industry we have upwardly
revised our expected WFE market size to $62B in FY2021
 Even if WFE should shrink to $55B due to temporary market shifts, we will aspire
to a management structure that is able to flexibly respond to market shifts and tosecure net sales of ¥1,500.0B and an operating margin of 26.5%

Establish new financial model based on further market growth andopportunities for significant growth for TEL
16
CORP IR / May 29, 2018

Three Focus Areas for New Growth Opportunities
Create strong
Product
next-generation products
competitiveness

HigherResponsivenessBecome the best and to customers
productivity Constantly pursue higher
sole strategic partner

management efficiency

Make steady progress in Best Fit in New Market = “responding to diversity”
and achieve Best in Class, as stated in our 2015 medium-term
CORP IR / May 29, 201817

Highlights from the Past 3 Years (Initiatives to Date)
Product
competitiveness1. Reorganization of Development & Production Group– Established Process Integration Center (PIC)– Merged Yamanashi and Tohoku plants, established TEL Technology Solutions– Built new development building for etch systems(Scheduled for completion Sep. 2018)
Responsivenessto customers– Made systems intelligent through utilization of AI and IT

2. Established new account structure (Global Field Div.)
3. Reorganized business units (CTSPSBU, TFFBU)
Higherproductivity

4. Responded to increased production(etch, deposition and test systems)

5. Introduced new global HR systems
CORP IR / May 29, 201818

Further Promotion of Our 3 Focus Areas (Future Initiatives)
Product
competitiveness1. Promote development of technologies that leverage
TEL’s comprehensive strengths– Process integration technology that unites diverse technologies– Develop next generation platforms

2. Promote early stage joint development and evaluation
with customers
Responsivenessto customers

Higherproductivity

CORP IR / May 29, 2018

– Share roadmap for multi-generational technologies: shift collaboration“from dots to lines”– Expand onsite evaluation activity

3. Increase productivity and added-value using data and AI
4. Respond to growing China business5. Increase earnings in field solutions business6. Promote efficiency though launch of business reform project
7. Implement medium-term incentive plan
19

Field Solutions (FS)Business strategy

Field Solutions sales
WFE$62B

400¥340.0B
280.0

300

251.0
200

170.0
77.0

100
93.0

185.0

208.0

115.0

93.0

190.0
150.0

115.0

FY'16

FY'17

Used equipment
and modification

101.0

80.0

105.0

150.0

165.0

– Provide upgrades andremanufactured equipment that
handle new applications

 Contribute to improving customer
productivity
Parts and services– Provide added-value services using
remote connections

0
FY'15

 Respond to new customer needs
driven by IoT

FY'18

FY'19(E)FY’21(Target)(Installed base of 66,000 units)

Leverage our strengths as an equipment manufacturer toincrease earnings in both the used equipment/modificationand part/service segments
CORP IR / May 29, 201820

Response to Growth in China BusinessBusiness development in China
Opened Shanghai Office in 1998

 Expect China to comprise 30% of WFE (CY’20)– Customers planning 10-15 new plants (CY’18-CY’20)

 Capture high share and service businessthrough high value added products andcomprehensive support
 Build solid business base

DalianBeijing

Xi'an
Nanjing Wuxi

– Hiring of engineers going well (3x vs CY’16)– Enhance training centers

Chengdu

Hefei

Employees in China(Employees)

Wuhan

Shanghai
Kunshan

Xiamen1,000

Head OfficeShenzhen

Branch500

Manufacture
Service Site

0
FY'15

FY'16

FY'17

FY'18

FY'19

Steadily build business base in growing market
CORP IR / May 29, 201821

Increasing Development and Production Capabilities
 Miyagi plant (etch systems)– Began operations at new logistics building, plan to raise productivity through automation– New development building (plan to complete by September)– Double production capability (plan to begin operations from October) Yamanashi and Tohoku plants (deposition, gas chemical etch, test systems)– Decided to build new production buildings– Strengthen BCP* with high earthquake resistance* BCP: Business continuity plan

Miyagi plant

Yamanashi plant: approx. ¥13.0B construction
cost (Begin construction in January 2019,
completion scheduled for April 2020)

Tohoku plant: approx. ¥13.0B construction cost
(Begin construction in October 2018,
completion scheduled for September 2019)

Secure development and production capabilities
CORP IR / May 29, 2018
in line with further growth stage

22

TEL’s Sustainability (economic value × social value = corporate value creation)
 Going forward, continue to work to resolve social issues and contribute to theachievement of sustainable development goals (SDGs) through our businessactivities in accordance with the Ten Principles of the UN Global Compact and RBA*
code of conduct
Environment Climate change, water, biodiversity, environmental management
SocialHuman rights, employment and labor, health and safety, supply chain,
local communities

Governance Corporate governance, compliance, risk management

Continue to be a company trusted by all stakeholders
CORP IR / May 29, 2018 * RBA: Responsible business alliance23

Contributing to the Environment is a Key Strategy
Lower energy
consumptionof TEL products+

Manufactured devices
realize low power
consumption

Raises TEL’s value

Technological proposals that reduce environmental impact
create significant value
CORP IR / May 29, 201824

New Financial Model (FY2021)
WFE market
Market share(Billion yen)

FY2018(Actual)

FY2019(Estimates)

$51B
14%

$58B
15%

FY2021(Plan)
$55B
18%

$62B
18%

Net sales

1,130.7

1,400.0

1,500.0

1,700.0

SPE
FPD

1,055.2
75.0

1,288.0112.0

1,400.0100.01,600.0
100.0

Gross profit

475.0

598.0

650.0

745.0

Gross profit margin

42.0%

42.7%

43.3%

43.8%

SG&A expenses

193.8

232.0

252.0

269.0

SG&A expenses to sales ratio

17.1%

16.6%

16.8%

15.8%

Operating income

281.1

366.0

398.0

476.0

Operating margin

24.9%

26.1%

26.5%

28.0%

Net income attributable toowners of parent

204.3

270.0

292.0

348.0

18.1%

19.3%

19.5%

20.5%

Net profit margin

Increase corporate value through innovative technologies and groundbreaking proactive
solutions, raise efficiency and secure even higher profitability and resistance to market shifts
CORP IR / May 29, 201825

Gross Profit, SG&A Expenses (Sales ¥1,700.0B Model)
FY2018(Actual)

FY2019(Estimates)

FY2021(Plan)(Billion yen)
Growth rate
(FY’18-FY’21)

Gross profit

475.0

598.0

745.0

+57%

Gross profit margin

42.0%

42.7%

43.8%

+1.8pts

 Raise gross profit margin of core SPE, FPD products– Timely introduction of new products to an expanding market– Lower cost ratio through product quality improvements
FY2018(Actual)

FY2019(Estimates)

FY2021(Plan)(Billion yen)
Growth rate
(FY’18-FY’21)

SG&A expenses

193.8

232.0

269.0

+39%

SG&A expenses to sales ratio

17.1%

16.6%

15.8%

-1.3pts

 Proactively invest in growth areas while planning appropriate SG&A andR&D expenses
CORP IR / May 29, 201826

R&D Expenses, Capex Plan
(Billion Yen)

130.0-145.0

150
120.0

R&D expenses
100

97.1
81.5

73.2

78.6

FY'13

FY'14

71.3

76.2

FY'15

FY'16

83.8

50

0

FY'12

FY'17

FY'18

FY'19 (E)

FY'21
(Plan)(Billion Yen)

60

40

45.6

39.5
24.1

21.7

26.6

20

0

40.0-50.0
35.0-37.0

51.0

Depreciation

Capex

12.7

FY’12

FY’13

26.0

24.8

FY’14

20.8
13.1

FY’15

19.2

13.3

FY’16

20.6

17.8

FY’17

20.6

FY’18

FY’19 (E)FY’21
(Plan)

Conduct proactive investment towards further growth
CORP IR / May 29, 201827

Assets and Capital Efficiency (Sales ¥1,700.0B Model) Accounts receivable turnover

EPS and ROE

(Yen)
2,500
EPS

– Current: 52 days ⇒ Achieved target
2,000 Inventory turnover

29.0%

1,500

19.1%

– Current: 111 days ⇒ Target: 95 days
1,000

 ROE

30-35%

ROE

500

13.0%

1,245

702

461

– Current: 29% ⇒ Target: 30-35%
0

FY'16

FY'17

FY'18

FY'21
(Target)ROE = (Net income attributable to owners of parent/Average total equity) x 100

Maintain focus on assets and capital efficiency
CORP IR / May 29, 201828

Capital Policy, Shareholder Returns
 Approach to capital policy– While closely monitoring the business environment and our necessary cash balance, wewill strive to raise ROE through earnings maximization and by raising capital efficiency

 Approach to shareholder return policy (basically linked to performance)

Dividend payout ratio:

50%

Annual DPS of not less than ¥150
We will review our policy if the company does not generate net income for 2 consecutive fiscal years

We will flexibly consider share buybacks
No change in shareholder return policy
CORP IR / May 29, 201829

Summary Establish new financial model backgrounded by expected
growth in semiconductor and production equipment markets.
Aim for short, medium and long term growth Aim to increase sales beyond market growth rate throughstronger competitiveness of products and deeper cooperation
with customers Raise development efficiency and business productivity andsecure even higher profitability and resistance to market shifts
Aim for sustained growth in corporate value througha management base with global-standard strength
CORP IR / May 29, 201830

Evolving Semiconductor Device Application andthe Future of Process Technology
May 29, 2018
Akihisa Sekiguchi, Ph.D.
VP & GM, Deputy General Manager, Technology Strategy Division,
Advanced Semiconductor Technology Division, Global R&D

CORP IR / May 29, 201831

Outline Trends and issues in semiconductor process technology:
Mainstream devices (CMOS Logic, NAND, DRAM) Technology challenges deep dive: Logic devices

 Devices that may drive further growth of the WFE market in the future
autonomous driving enablers and AI
 Summary

CORP IR / May 29, 201832

Trends and Issues in Semiconductor Process Technology

CORP IR / May 29, 201833

Process Technology Issues for Major Semiconductor Devices
3D NAND

DRAM

Logic

Multi-layering & productivity

Enhancements from 1Y-1Z

5 & 3 nm development

High selectivity process
Realizing highly uniform
process suitable for 3D
structures

High aspect ratio process,enhanced precision andmaterial specific adaptation toachieve higher bit density

Precision patterning process
co-optimized for device design
and new materials

Drive collaboration in & out of the company to accelerate creation of
innovative process technologies
CORP IR / May 29, 201834

3D NAND Technical Issues
Tunnel oxide
Channel dep

2nd
tier

High-k dielectric,
Metallization

ONON etch

1st
tier

Staircase formation
Etch  Trim  Etch  Trim  …
Trim

Etch

Stress management& Multi-stacking

SiN removal

Channel formation& Cell gate stack
MLC etch
ONON etch

Isolation,
Metallization

Isolation/Source line formation

Multi Level
Contact formation

Logic
under Cell

Increasing number of layers requires a variety of new technical solutions
CORP IR / May 29, 201835

DRAM Technical Issues
High-k dielectric deposition

Cylinder(Present)

Scaling limit

From Al to Cu wiring

Needs higher-k and
Pillar lower leak current(Future)Source: TECHINSIGHTS

Higher capacitance  Higher dielectric constant
RC delay due to miniaturization  Introduction of logic Cu interconnects
CORP IR / May 29, 201836

Technology Challenges Deep Dive: Logic Devices

CORP IR / May 29, 201837

Device Scaling Trends
Nanowire FET

3D Architecture

FinFET

[nm]
1000

100

i-Line10

1
1990

Immersion ArF

ArF
KrF

180

130

Technology nodeLight source
1993

1996

1999

110

90

Scaling

65

45

32

EUV

22

14

Planar FET

2002

2005

2008

2011

2014

10

7

2017

5
2020

Poly gate

High-k/metal
gate

CORP IR / May 29, 2018

Complex 3D processes to realize N3
EUV slowly gets manufacturing adoption

38

Scaling Issue: Overlay
Step1:
Line/Space

Overlay error for every
exposure

iArF

Line

Too close

2

1

Space
Too far
Closer1
3

Self aligned multi patterning (SAMP)
with high etch and dep usage

Step2:Cut

3 masks
Lower yield

Multi-expo: (Litho + Etch) x n

EUV intro

EUV

Cut

Overlay error reduced

1
Cross sectionof a logic
structure

1

1
1
1 maskLELELE = (Litho-Etch)3(etch and dep usage reduced)

Single expo: (Litho + Etch) x 1

Higher yield

EUV reduces overlay error but SAMP is still in use
CORP IR / May 29, 201839

Logic FEOL/MOL Technology Roadmap
Node16-14 nm

10 nm

7 nm

5 nm

< 3.5 nmNanowire/Nanosheet FETFinFET

Transistor

Wrap around contact

Diamondshaped Epi
ContactW

Co and other materials

Scaling and performance enhancement concurrently requires structure,design and material changes, which makes integration challenging
CORP IR / May 29, 201840

Complexity of the Fabrication Processes for Logic Devices
Self-aligned contact (SAC)
Nanowire FET

Wrap around contact (WAC)

R. Coquand et al.,VLSI tech. 2013

Precise control in an atomic level

Applications
Courtesy of imec
Conventional patterning

FEOL

N+1

N+2

N+3

Patterning and hard mask

Nanowire FETMulti-color patterning

MOL

Patterning and hard mask
Contact structure (WAC)
New plug material (Ru)

BEOL

Patterning and hard mask
EUV productivity
Selective deposition

CommonPitch imbalance control
Known

Design and process technology co-optimization isa challenging integration issue
CORP IR / May 29, 2018

Unknown41

Major Semiconductor Devices: FinFET

FinFET formation alone is a complicated process
CORP IR / May 29, 201842

Challenges in Nanowire/Nanosheet Fabrication
FinFET

Dummy gate removal
High-k dielectric+ metal dep

Nanowire/Nanosheet FET
High-k dielectric+ metal dep

Oxide removal

Oxidation for rounding

SiGe removalby chemical dry etch

Dummy gate removal

Nanowire/Nanosheet formation is even more complicated than FinFET
CORP IR / May 29, 201843

New Semiconductor Devices CFET

Structural formation modelling and electrical simulation are now a must
CORP IR / May 29, 201844

Logic BEOL Technology Roadmap
Node16-14 nm

10 nm

7 nm

5 nm

Fully self-aligned via (FSAV)

Dual damascene

Self-aligned block(SAB)

Self-aligned via (SAV)

Patterning

Non SAV

Metallization< 3.5 nmSAV

Cu: ECD
Ta/TaN PVD

Cu

Replacement of Cu:
Ru, Co, CoAl

Estimated using IEDM, VL, IITC papers

Post Cu

TEL’s estimates using IEDM, VLSI symposium, IITC papers

Scaling and overlay issues require new integration schemes
CORP IR / May 29, 201845

R&D for Future Growth: Beyond Cu

Source: An Steegen, imec technology forum 2017

Line width reduction is pushing copper to its limits New material required
CORP IR / May 29, 2018

46

New Opportunities through Integration
Tactras™ Vigus™

Sp
Dp

Etch

Sp
Dp

Sn
Sn

Dn
Source: imec

EXPEDIUS™-i
Certas™

Cleaning
Dn

CFET (new structure)

CELLESTA™-i

Lithography

EXIM™

CLEAN TRACK™
LITHIUS Pro™ Z

Buried power rail (new material)
Source: Imec presentation at ISPD 2016

TELINDY PLUS™

Triase+™
NT333™

Deposition

Close integration between process equipment is a mustin order to propose solutions to realize further scaling
CORP IR / May 29, 2018 through new materials and structural solutions

47

Devices That May Drive Further Growth of the WFE Market
in the Future Autonomous Driving Enablers and AI

CORP IR / May 29, 201848

Autonomous Driving

https://blog.caranddriver.com/nhtsa-sides-with-google-officially-declares-autonomous-car-software-a-driver-sorta/

CORP IR / May 29, 2018

Semiconductor usage will increase
with the arrival of autonomous driving

49

Higher Automotive Functionality
Adaptivecruise control/LRR

Emergency breaking
Pedestrian detection
Collision avoidance

Lanedeparture
warning Hybrid vehicles use 2.5-3 times more semiconductor
devices compared to conventional gasoline vehicles
 Electric vehicles use even more than 2x

Traffic
sign
recognition

 With ADAS*, additional value add is $50-$100

Cross traffic assist

 Autonomous driving vehicles transit 6TB of data daily toData Centers

Park assist
by ultrasoundSurroundedview

Surroundedview

Park assist
by ultrasoundRear collision
warning

Park assist
Surrounded view
CORP IR / May 29, 2018••

ADAS today uses 6 cameras per vehicle
In the near future, ~10 per vehicleInterior, driver, passenger monitoring

AR/VR

Airbag control* ADAS: Advanced driver assistance system

Increase in semiconductor usage from conventional
gasoline, hybrid, electrical, to autonomous vehicles(not to mentions the infotainment data related adders)50

ADAS・Device Challenges for Autonomous Driving
 Viewing, Sensing camera

 LiDAR* cost

– Front 1-2, back1-3, CIS(Infrared laser scan in 3D)– In the future 10-12– High end LiDAR: ~few million yen– Higher pixel density– Motorless MEMS version will drive cost
below 50,000 yen– Faster image readout– Processing circuit

 mm radar Processor/Memory/ECU**– Higher resolution, wider angle– CPU under autonomous driving use a few KW– DRAM degradation under high temp (refresh cycle）– From SiGe to Si CMOS (~2019)– Integrated communication IC and micro controller(~2022)
$200
GaAs

SiGe
Si CMOSintegration

$50

2016

CORP IR / May 29, 2018

– Using auto temperature grade LPDDR4• High temp tolerant DRAM cell
• Error reduction circuit• Data/ECC*** transmission function– Flexible ECU development2025* LiDAR: Laser imaging detection and ranging ** ECU: Engine control unit *** ECC: Error correction code51Semiconductor Use Increase Due to Autonomous Driving
Mid-end board for autonomous driving

Semiconductor usage per vehicle
($)
3,000

GPU

GPU

2,000

900

1,000

150

1,100

330

0

Image of GPU size relative to the board
Source: McKinsey, USITC

Autonomous driving vehicles may use 10x (cost) in terms ofsemiconductors versus conventional gasoline vehicles
CORP IR / May 29, 2018

52

Semiconductor Sales AmountIndustrial app semiconductor CAGR 10.1%

Worldwide Semiconductor Sales Estimate
($B)
600

CAGR* (2017-2022)
502

500

470

493

4.3% 20%

497

520
15%

420
400

12.1%

346

10.0%

300

12.8%

Industrial

11.2%
9.8%

9.9% 10.1%

11.9%

9.3%

9.2%

Data Processing

12.4%

10.8%
9.9%

Military/Civil Aerospace

10%

ConsumerCommunication

9.6%

Automotive semiconductor CAGR

10.5%

Automotive

200

Automotive rate

5%

Industrial rate

100

0

0%
CY’16
2016 CY’17
2017 CY'18
2018 CY'19
2019 CY'20
2020 CY'21
2021 CY'22
2022
Source (Worldwide Semiconductor Forecast): Gartner, “Semiconductor Forecast
Database, Worldwide, 1Q18 Update”, 3 April 2018,
Charts/graphics created by Tokyo Electron based on Gartner research

Semiconductor market will continue to grow nicely in the future
CORP IR / May 29, 2018

* CAGR: Compound annual growth rate53Artificial Intelligence
Phenomenal growth rate of AI
Semiconductors

AI semiconductors

AI chip development intensifying

CAGR 67%

$1.2B
CY'17

$15.8B

CY'18

CY'19

CY'20

CY'21

CY'22

Source: Gartner Forecast: AI Neural Network Processing Semiconductor Revenue, Worldwide, 2018 , 11 January 2018
Charts/graphics created by Tokyo Electron based on Gartner research

AI devices expected to grow at an annualized rate of almost 70%
CORP IR / May 29, 2018

54

Motivation for AI Chip Development
 GPU (Graphics Processing Unit)– De facto standard for deep learning today– But energy consumption is high and requires additional cooling mechanism– For loosely linked neural networks, there is inefficiencies in computation• Some data centers use FPGAs listed below• New ASICs are being developed and further evolution is needed as an accelerator

 FPGA (field-programmable gate array)– Adapts to the various deep learning calculation models and circuits can be modified flexibly– But computation is relatively slow (clock frequency: tens of MHz - hundreds of MHz)
– Design hurdle is high and requires hardware knowledge Neuromorphic– New brain like architecture and device development is being accelerated to optimize AI application– Existing semiconductor processes and materials are thought to be compatible– Tokyo Electron Limited works with multiple partners to address AI development needs
CORP IR / May 29, 2018

55

WFE Outlook
WFE by application*

$58B

$61B

$62B

$63B

$51B
WLP

$37B

DRAM

Non-volatile memory
Foundry logic

Logic & others(MPU, AP and others)

CY'16

CY'17

CY'18*

CY'19*

CY'20*

CY'21** TEL estimate

New semiconductor devices will grow WFE market
over the medium- to long- term
CORP IR / May 29, 201856

Summary

CORP IR / May 29, 201857

Summary – Diversity of Semiconductor Technology
More than Moore

CMOS scaling

Functional diversification
Wire-bonding Homogeneous
Heterogeneous
3DI
DRAM
Flip-Chip
2.5D
NAND InFO
Si photonics
Cu/ULK
3D
NAND
Strained Si

KrF
ArF

High-k metal
ReRAM
gate
Arf-immersion
STT-MRAM
FinFET
DP/MP

Cu/ELK

Now

More
Moore

DSA,

Patterning

CORP IR / May 29, 2018

Nanowire FET
CFET

EUV

2017~

Advanced packaging(3DI/WLP)

Neuromorphic

NIL, EBDW

Logic with new material
new structure

Emerging
memory58

Devices That Have Made Today’s Technology Possible
MPU

CIS

Brain
Eye

NAND

DRAM

NAND

With new devices like AI and Neuromorphic chips joining the mix, the market willcontinue to grow synergistically with the communication system network growth 59

Bionics
Cybernetics

Neuromorphic

AI
AR/MR

VR
FinTechPC

MobileQuantum
computing

Cloud
Network
Data

Robotics
RPA

Autonomous
driving

Technology Evolution at a Glance60Coater/developer, Cleaning System Business Strategy
May 29, 2018
Seisu (Yoh) Ikeda
SVP & GM, Deputy General Manager, Business Division, General Manager, CTSPS BU

CORP IR / May 29, 201861

Coater/developer and Cleaning Systems Market Outlook
Single wafer
cleaning system
CELLESTA™-i

TEL’s coater/developer and cleaning
SAM* in WFE market
($B)
70

10%

58

60

61

62

6%

6%

63
Coater/developer
CLEAN TRACK™
LITHIUS Pro™ Z

51
50
40

30

6%

6%

6%

6%

37
4%

4%

4%

4%

4%

4%

Composition
ratio

Batch cleaning system
EXPEDIUS™-i

 Coater/developer

5%– Introduction of EUV lithography for mass production

Composition
ratio– Established regional offices in China and expanded
support for customers

20 Cleaning system
10
0

1.8
3.0

2.0
3.5

2.1
3.6

1.4
2.3
CY’16
CY’17
CY’18
CY’19
2016
2017
2018
2019
* SAM: Served available market

2.2
3.7

2.2
3.8

CY’20
CY’21
2020
2021
TEL estimate

Coater/developer
SAM– Growth in wet etch market for 3D NAND

0% Cleaning
SAM– Increased demand for bevel cleaning– Further demand for drying technology that prevents
pattern collapse accompanying miniaturization

Growth in coater/developer and cleaning systems markets on demand for
62
CORP IR / May 29, 2018
increasing density of semiconductor components

EUV: Approach and Results

Exposure tool
manufactures

Consortia

Materials
manufacturers
 Linking valuable data, customer needs, issues and information received through many collaborative
businesses with development
 Maintain 100% share in EUV in-line equipment market

Continue acceleration of further EUV development

CORP IR / May 29, 2018

63

Changing Issues in Introduction of EUV Mass Production(announced at EUVL Symposium)
Priority

2014

2015

2016

2017

1

Reliable source
operation with > 75%
availability

Reliable source
operation with > 85%
availability

Reliable source
operation with > 85%
availability

Resist resolution,
stochastics, and sensitivity
met simultaneously

2

Resist resolution,
sensitivity & LER* met
simultaneously

Resist resolution,
sensitivity & LER met
simultaneously

Resist resolution,
sensitivity & LER met
simultaneously

Reliable source > 250W
operation with > 90%
availability

3

Mask yield & defectinspection/review
infrastructure

Mask yield & defectinspection/review
infrastructure

Keeping mask defect free Keeping mask defect free4

Mask yield & defectKeeping mask defect free Keeping mask defect free inspection/review
infrastructure* LER: Line edge roughness

Mask yield & defectinspection/review
infrastructure

Source: 2017 EUVL Symposium Closing Remarks

Importance of resist performance and coater/developer technology
increasing within EUV process
64
CORP IR / May 29, 2018

Product Strategy for Coater/developers
 Promote unification of system platforms– Improve value for customers and unify developmentwith latest platform of LITHIUS Pro™ Z series

CLEAN TRACK™
LITHIUS Pro™ Z

CLEAN TRACK™
LITHIUS Pro™ AP

 Develop value-added products forminiaturization and 3D structures– Address 3D NAND wafer warpage

 Improve quality of service and efficiency throughuse of data and automation

3D NAND– Realize high-quality global support not reliant ontechnical skill of personnel

CORP IR / May 29, 201865

Growth of TEL’s Cleaning Business CY’17 market share: 25% (YoY+5pts, achieved medium-term plan early)
Market share

CY’15(Actual)CY’16(Actual)CY’17(Actual)Cleaning system

18%

20%

25%

・・・

CY’20
(Target)27%+– Expand sales of CELLESTA™ single wafer
cleaning system• Bevel cleaning*: Improved yield around extreme edge ofwafer• Post-etch cleaning for memory: improved productivity• Apply best known coater/developer methods to cleaningsystem businessPre-cleanBevel cleaning(single wafer cleaning system CELLESTA™ )Extreme edge of wafer(enlarged)

300mm
wafer

Wafer
Due to increasing number of films stacked on
wafer, films on a wafer’s extreme edge
become defects, affecting yield Share leading-edge technology and expertise by unifying
development– Expand sales of EXPEDIUS™ batch cleaning system• Contribute to improved productivity of 3D NAND
• Improve wet etch performance and contribute toenhanced yield* Bevel cleaning: process for removing unnecessary film from the outer part of the wafer
CORP IR / May 29, 2018

Post-clean

Wafer
Established leading positon in developing
equipment for accurate removal of film from awafer’s extreme edge, improving yield forcustomers
66

Evolving Devices: Issues and Factors Lowering Yield
 Increased impact on wafer edge due tomulti-layering

Multi-layering is increasing concern overfilm delamination from the wafer edge

– Concern over film delaminating from edge andwafer warpage

Wafer front-side
Wafer edge

 Impact of microscopic particle on device yieldin miniaturization– Increase of patterning processes– Increase of 3D structures

Increased influenceof particles

 Increased risk of pattern collapse inminiaturization– Increased difficulty in drying due to higher aspect ratio
of device structure

3D NAND:
Multi-layering

Even smaller particle
impacts device yield
Particle

Source: Intel Corporation
DRAM high aspectratio structure

Increased risk of pattern collapse
due to lower mechanical strength
High aspectratio structure

Capacitor

STI

Further increase of factors reducing yield for customers on
CORP IR / May 29, 2018progression of multi-layering and miniaturization

67

TEL’s Initiatives on Factors Affecting Lower Yield

Number of wet bevel cleaning processes*

Importance of bevel
cleaning process
expected to increase Increased impact on outer part of wafer due tomulti-layering– Contribute to improving factors that reduce yield
due to impact on wafer edge

2012 2013 2014 2015 2016 2017 2018 2019
Logic
NAND
DRAM * TEL estimate

 Impact of microscopic particle in miniaturization

Solid phase cleaning technology (TEL original)– Develop TEL original technologies enabling removalof microscopic particles and particles between patterns(Published at 2017 Electrochemical Society) Increased risk of pattern collapse in miniaturization– Develop drying technology which takes advantage of
TEL’s original surface modification technology, etc.

CORP IR / May 29, 2018

Current drying technology

New drying technology

Pattern collapse

Zero collapse

Aim to further increase share by contributing
to the improvement of yield for customers

68Summary Coater/developer: Maintain high share and raise value by continuing todifferentiate via technological development through collaborative activities inleading-edge technology sectors, especially EUV
 Coater/developer: Maintain high share and enhance our ability to support
customers in China, where the market is growing rapidly Cleaning system: Continue to differentiate via technological development,
focusing on processes where customers need a high level of technologicalsupport, such as improving yield Synergies: Raise efficiency of development and production by sharing BKM*
and promoting unification of development, production and management ofcoater/developer and cleaning systems* BKM: Best known method
CORP IR / May 29, 201869

Etch System Business Strategy
May 29, 2018
Yoshinobu Mitano
SVP & GM, General Manager, ES BU

CORP IR / May 29, 201870

Etch System Market Outlook
TEL’s etch SAM in WFE market*($B)
70* TEL estimate
58

60

61

62

Tactras™ Vigus™

63
30%

51
50

22%

22%

22%

23%

23%

20%
40

Composition
ratio
20%

37

30
20

10
0

7.4
CY’16
2016

11.1

13.0

13.7

14.0

14.3

CY’17
2017

CY’18
2018

CY’19
2019

CY’20
2020

CY’21
2021

10%
Etch
SAM
0%

Certas LEAGA™

Trends in etch technology
 Miniaturization of DRAM
– Increases in patterning and copper interconnect
processes
 Multi-layering of 3D NAND
– Higher ratio of HARC* process
 Miniaturization and greater structural complexity of logic– Increases in patterning processes, isotropic etch
* HARC (High aspect ratio contact) process: a process for forming deep holesthat requires advanced processing technology

Growth in etch system market due to increase in patterning processes
and greater structural complexity
71
CORP IR / May 29, 2018

Business Opportunities and Strategy
 Win share and raise profitability by leveraging technological advantage– DRAM: Win share in patterning process, etc. through productivity differentiation– NAND: Win share in new HARC process through technological differentiation– Logic:
・Leverage RLSA™ plasma silicon etch to drive sales growth in transistor periphery processes
・In contact processes, aim to increase share with atomic layer etch (ALE)・In 3D transistors, capture share with isotropic etch

 Grow sales through proactive development and investment in production
Market share

CY’15 (Actual)

CY’16 (Actual)

CY’17 (Actual)

Etch system

21%

23%

26%

・・・

CY’20 (Target)

30%+

Focus on HARC, patterning, 3D structure processes,
aim for 30%+ share by CY2020
CORP IR / May 29, 201872

Memory: Results and Initiatives
DRAM
 Capacitor process (HARC)

3D NAND HARC process
Interconnects

 Copper interconnects
process: Leveraged
knowledge of logic
to win share

Capacitor Differentiate with technology related toprocess accuracy, grew share in 6X/9X
generations, and aim to capture additional
processes in 12X
CY’18
CY’19
CY’20
6X/9X

9X

 Patterning: Realized
reduced costs forcustomers by combining etch steps

Simplify process

9X/12X

Multi-levelcontact

Word line
isolation (slit)

Channel(Memory hole)

DRAM: Won share in target areas, doubling share from 3 years ago
NAND: Won application from second customer in slit process.
CORP IR / May 29,Aim
2018 to leverage new technology to increase POR wins73

Logic: Focus Processes and Key Points
・Transistor periphery 3D structures

Logic

FinFET

Nanowire

Nanosheet

Interconnects

・Miniature contact process
SAC (Self-aligned contact)

Contact
Gate

Fin

STI

Key requirement
1. High SiN selectivity (less SiN loss)
2. Narrow slit etch capability

・Contact/interconnect process;more complex patterning

Leverage technological advantage in increasingly
CORP IR / May 29, 2018complex etch processes, respond to new needs

74Leading-edge Logic Initiative 1: Silicon Etch
Superior aspects of RLSA™ plasma etcher
in silicon etch

Faceting

Depth variation
Non-vertical form

RLSA™
plasma
プラズマエッチング装置
Tactras™
etcherRLSA™
Rectangle

Optimized Microwave

Process Performance

Typical ICP
etcherRLSA™ plasma BB

Gate

Fin

Transistor periphery 3D structures

Conventional
Microwave

Adoption of
new technology

Equal depth
Vertical shape

Stability and Productivity

In silicon etch, differentiate through processing performance and productivity
CORP IR / May 29, 201875

Leading-edge Logic Initiative 2: Highly Selective Etch
Conventional etch

Quasi-ALE*

Concept of Quasi-ALE
Self-aligned contact

Initial

SiO2Adsorption

SiN

FC film

SiO2

Si-ARC etch

Si
-ARC

Activation
Ar

+

+

Desorption+

SiN*ALE (Atomic layer etch): Highly selective etch technology at the atomic level

Aim to win share through rising demand for highly selective etch
CORP IR / May 29, 201876

Leading-edge Logic Initiative 3: Gas Chemical Etch
Broadening of applications for gas chemical etch
N+1
Min. Fin pitch

Si

SiGe

N+2
Min. Fin pitch

Si

FootingMin. Fin pitch

SiGe

Post dummy Si removal

Wet etch

N+3
Nanowire

Post gate oxide removal

Nanosheet

Post SiGe removal

Isotropic
SiGe etch

Isotropic
Ox etchGas chemical etch

No footing

Si/SiGe layer stackSi nanowire

Differentiate through isotropic selective etch technology needed for 3D transistors
CORP IR / May 29, 201877

Miyagi Plant: New Logistics Building and Module Assembly andShipping, New Development Building
Module: VTM**
Production start: Sep. 2018
Module: EFEM*
Production start: Jan. 2018

New Logistics
Building

Receiving

CORP IR / May 29, 2018

New development building
Scheduled completion: Sep. 2018
Total floor space: 11,700m2

Automatic
sorting

Automatic
shipping* VTM (Vacuum transfer module): Module that sends wafers to etch chamber** EFEM (Equipment front end module): Module that moves wafers from FOUP/load ports to VTM

78

Summary Expect continued growth in the etch system market driven by multi-layering of
3D NAND and increasing complexity in logic patterning Aim to raise profitability by focusing on TEL’s strengths in HARC, patterning,interconnects, achieving share of 30%+ in CY’20 through technologicaldifferentiation
 We will proactively invest towards further market growth

CORP IR / May 29, 201879

Deposition System Business Strategy
May 29, 2018
Shingo Tada
VP & GM, General Manager, Thin Film Formation BU

CORP IR / May 29, 201880

Deposition System Market Outlook
TELINDY PLUS™

TEL’s deposition SAM in WFE market*

($B)
70

20%
58

60

61

62

63
NT333™

51

Triase+™

50
40

37
9%

30

9%

10%

10%

10%

8%

20
10

9%

Composition
ratio

4.5

5.2

5.4

5.9

6.0

Deposition
SAM

($B)
6

Deposition SAM by application*

5

NAND

4
3

DRAM

2

2.8

1

0

CY’16
2016

CY’17
2017

CY’18
2018

CY’19
2019

CY’20
2020

CY’21
2021

0%

0
CY'15

Logic/Foundry
CY'16

CY'17

CY'18

CY'19

CY'20

CY'21

Miniaturization and evolving device structure are
driving growth of the high value-added deposition market
CORP IR / May 29, 2018

* TEL estimate

81

Business Opportunities and Strategy
 In areas where we already participate in the deposition market (ALD, CVD
and diffusion furnaces), introduce technology with high added value andoutperform market growth– introduce next generation thermal processing systems with higher productivity andcontrollability– Introduce new single wafer platform for cluster process Accelerate development of new materials, new applications– Evaluate new materials for metal deposition systems– Develop anisotropic deposition and selective growth process
Market share

CY’15 (Actual)

CY’16 (Actual)

CY’17 (Actual)

Deposition system

38%

37%

36%

・・・

CY’20 (Target)
40%+

Focus on high value added deposition processes,
aim for 40%+ share in CY2020
CORP IR / May 29, 201882

Approach to Deposition Market
ALD system

CVD system

 In semi-batch systems, make high quality film
required for miniaturization and shift to 3D
structure, and raise productivity
ALD system market

 Use our huge productivity advantage in batch
systems to differentiate in memory

 Achieve high quality metal deposition to
enable further miniaturization¥210.0B

CAGR >15%¥90.0B

Semi-batch ALD system
NT333™

CY'14 CY'15 CY'16 CY'17 CY'18 CY'19 CY'20
TEL estimate

Batch system
TELINDY PLUS™

Metal deposition system
Triase+™

Aim to grow profit through and new technology for further miniaturizationand next-generation semiconductors
CORP IR / May 29, 201883

Initiatives in the Deposition Market
ALD system

CVD system

ALD system
列1 (CY2017)
market share

YoY+2.4%pts

Single wafer CVD system
列1(CY2017)
market share

31.4%

33.8%

(No.1
ranked)(No. 2 ranked)

YoY+5.0%pts

Semi-batch ALD system
NT333™

Metal deposition system
Triase+™
TEL

OthersTEL

Others

Source: ALD system market share=Atomic layer deposition, Single wafer CVD system market share=Nontube LPCVD, Gartner, “Market Share: Semiconductor Wafer Fab Equipment, Worldwide, 2017”, 18 April 2018,
Chart created by Tokyo Electron based on Gartner research.

CORP IR / May 29, 2018

Focus on growing share in market segment
expanding due to miniaturization84

Dielectric Film Deposition Technology for High Aspect Ratio Structure
DRAM

3D NAND

High-k dielectric film

High-k dielectric film

Block oxide film
Charge trap film
Tunnel oxide film
Protective oxide

High productivity semi-batch ALD
ALD for high-k dielectric film
2.40

Source area

N2

Si precursor

Isolation by N2

O3

Oxidation area

Film density

ALD for high quality oxide film

Metal precursor

Oxidation

N2

film density (g/cm3)

Isolation by N2

2.30

2.26
2.22

2.22

2.20
2.10

2.09

2.00
#5

Modification

Gas injection
directly above wafer

Thermal DCS-HTO Thermal HQ oxide
oxide
furnace @ ALD oxide NT333 @furnace @ 780
deg.C
highdeg.C
temp. NT333 @ 400
low temp.
1000
400high deg.C
temp.
low deg.C
temp.

Realized high productivity deposition technology that forms high quality,
85
CORP IR / May 29, 2018
uniform dielectric film without pattern dependenceMetal Deposition Technology for High Aspect Ratio
DRAM

3D NAND
Bottom electrode deposition

Upper electrode deposition

ASFD：Advanced sequential flow depositionHigh throughputMinimizes chamber volume
High speed, high concentration gas
injection systemUniformity



Symmetrical gas flow design

Word line, contact barrier deposition

Φ30 nmAspect ratio = 40:1

Non-uniformity< 1.0% @ 1 sigma
Step coverage> 90%

Optimized deposition chamber design for ASFD provides
CORP IR / May 29, 2018high performance and high productivity

86

Deposition Systems: Striving for Further Growth
New platform Next generation thermal processing system– Introduce SLB* product with high productivity and efficiency

Tool
Matching
Optimum
Control– Adoption of new, high precision controller will contribute toenhance tool matching and increasing uptime* SLB: Super large batch New single wafer platform
Diagnostic– Smaller footprint, higher productivity– Enables diverse cluster processes

New platform

Expand market share in areas where we already participate in byincreasing productivity and responding to diverse process needs
CORP IR / May 29, 201887

Deposition Systems:
Initiatives Towards New Materials and Applications– Achieve low resistance withthin wire– Excellent gap fill capabilities

Resistivity[u ohm cm]

 Evaluation of new materials
for metal deposition systems

Resistivity ratio at thin film
TiN/Convetional W
TiN/ FFW
TiN/New Material

0

5

10

15

20

25

Thickness[nm] Develop anisotropic deposition andselective deposition– Achieving gap fill and bottom up processes
by using TEL’s unique deposition

technique
TEL/TEL

SiO2
AR:
8:1
CD:
43nm
Depth 331nm

Film formationin processing

Ge(SiGe)
AR:
~ 5:1
CD:
40nm
Depth 200nm

Gap fill

CORP IR / May 29, 2018

Afterformation

Expanding SAM through the development of
new applications for miniaturization

TEL/TEL

Bottom up88Augmenting Production System
New building at Yamanashi (Fujii) Plant

New building at Tohoku Plant• Construction start (scheduled): January 2019
• Completion (scheduled):April 2020
• Products: Single wafer deposition, gas
chemical etch, and test systems• Construction start (scheduled): October 2018
• Completion (scheduled):
September 2019 (First phase)
December 2020 (Second phase)• Products: Thermal processing systems

Expand production system, flexibly respond to future growth in demand
CORP IR / May 29, 201889

Summary Deposition market continues to expand, especially in memory
 Expand our market share in the fields of ALD, single wafer CVD and thermal
processing systems, by raising the competitiveness of our existing products
and introducing new products Start construction of new factory buildings in FY2019, increase production
capacity for sustainable growth

CORP IR / May 29, 201890

FPD Business Strategy
May 29, 2018
Tsuguhiko Matsuura
VP & GM, General Manager, FPD BUCORP IR / May 29, 201891

FPD Medium-term Plan($B)
25

FPD equipment market

20

Sales and operating margin(Billion yen)
120

25%

100

20%
15%

80
15

10%
60
5%

10
40
5

Strong TFT equipment
market

0
CY'15
CY'16
Coater/developer
AMOLED

CY'17
CY'18
Dry etch
CF, Cell, Others

CY'19
CY'20
TFT others

0%

20

-5%

0

-10%
FY'15

FY'16

FY'17
Sales

FY'18

FY'19

FY'21

Operating margin

Data based on IHS Markit, Technology Group, Display Supply Demand Equipment Tracker Q4 2017.
Results are not an endorsement of Tokyo Electron Limited. Any reliance on these results is at the third party’s
own risk. Visit technology.ihs.com for more details.

Progressing according to plan towards achieving
20% operating margin target in medium-term plan
CORP IR / May 29, 201892

Medium-term Plan Progress: Highlights
 Established our leading position in G10.5
 Introduced new Betelex™ platform etch system
 Expansion of PICP™* etch system going well

FPD coater/developer
ExcelinerTM

FPD plasma etch/ash system
ImpressioTM

FPD plasma etch/ash system
BetelexTM* PICP: Plasma source for producing extremely uniform high density plasma on substrate
CORP IR / May 29, 201893

Display Trends
Increasing screen size

OLED
Color filter

Emissive
layer

LCD
TFT

TFT

Backlight

LCD

OLED

Design flexibility

Increasing resolution
TV
FHD

Mobile, VR

4K
300 ppi

8K1000 ppi

Flexible, edge bent, free format

Technological change in displays increasing business opportunities
CORP IR / May 29, 201894

Business Opportunity: G10.5 Equipment Market
 Greater-than-expected growth in investment
 Maintain high market share through technological differentiation (large area
plasma control, air floating coater)
G10.5 TFT array equipment market

（$B）
20

Eight 65 inch TV panel substrate possible“65
3,370 mm

15

10

5

0
CY'16

CY'17

CY'18

CY'19

CY'20

Data based on IHS Markit, Technology Group, Display Supply Demand Equipment Tracker Q4 2017.
Results are not an endorsement of Tokyo Electron Limited. Any reliance on these results is at the third
party’s own risk. Visit technology.ihs.com for more details.

2,940 mm

Increased sales far beyond market growth bymeeting customers’ technological needs
CORP IR / May 29, 201895

Business Opportunity: Metal Oxide/LTPS
TFT arraya-Si

Metal Oxide

LTPS

Further new
needs

Representationof structure

Application

LCD TV
Monitor

OLED TV
TabletSmartphone(LCD/OLED)

Number of
masks

5

6-8

9-13

Dry etchprocesses

3a-Si, SiNx

3
SiO, SiNx~11
SiO, metal

Flexible displays＋2 processes

OLED process(G6 Half Size)＋3-4 processes

Number of etch processes increased
as more advanced technology sought
CORP IR / May 29, 201896

Business Opportunity: Growth of OLED TV Market
 Material utilization significantly more efficient than current evaporation method
 Companies improving functionality of ink(K units)
8,000

OLED TV

6,000

4,000

2,000

0
CY'16 CY'17 CY'18 CY'19 CY'20 CY'21

Inkjet printing system for manufacturing OLED planes
EliusTM 2500

Data based on IHS Markit, Technology Group, Display Long-Term Demand Forecast
Tracker Q4 2017. Results are not an endorsement of Tokyo Electron Limited. Any
reliance on these results is at the third party’s own risk. Visit technology.ihs.com for
more details.

Differentiate with inkjet printing system
towards growth in the OLED TV market

CORP IR / May 29, 201897

Summary
 Increase share and profitability in growing market, businessprogressing according to plan New medium-term plan FY2021 target: sales ¥100.0B, operating
margin over 20%

 For leading-edge production processes, focus on areas where wehave technological superiority– High performance PICP™ etch system– Etch system and coater/developer for G10.5 substrate– Inkjet printing system for OLED TVs
CORP IR / May 29, 201898

CORP IR / May 29, 201899