THCV231_THCV236_Rev.3.12_E

THCV231 and THCV236
SerDes transmitter and receiver with bi-directional transceiver

General Description

Features

The THCV231 and THCV236 are designed tosupport video data transmission between the host anddisplay.
THCV231
One high-speed lane can carry up to 14bits data at a
pixel clock frequency from 12MHz to 160MHz.
THCV236
One high-speed lane can carry up to 32bit data and3bits of synchronizing signals at a pixel clock
frequency from 6MHz to 160MHz by converting
RGB444 to YCbCr422.
The chipset, which has one high-speed data lane,
can transmit video data up to 1080p/60Hz.
The maximum serial data rate is 4.00Gbps/lane.













Data width selectable
Wide frequency range
AC coupling for high-speed lanes
CDR requires no external frequency reference
Wide range supply voltage from 1.7V to 3.6V
Additional spread spectrum on data stream
2-wire serial interface bridge function(400kbps)
Remote side GPIO control and monitoring
THCV231
QFN32 (5mm x 5mm) with exposed pad ground
THCV236
QFN64 (9mm x 9mm) with exposed pad ground
Compliant with RoHS and REACH

Block Diagram

Settings
2-wire I/F
SDA/SCL

Controls

RCMP
RCMN

OSC
LDO

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Controls

LVCMOS output

TCMP
TCMN

Formatter
YCbCr to RGB

RXP
RXN

Deserializer

TXP
TXN

CDR

Serializer

THCV236

PLL

Formatter

D11-D0
HSYNC
VSYNC
CLKIN

LVCMOS input

THCV231

D31-D0
HSYNC
VSYNC
DE
CLKOUT

Settings
2-wire I/F
SDA/SCLOSCCAPOUT
CAPINA
CAPINPLDOCAPOUT
CAPINA

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Contents Page
General Description .............................................................................................................................................. 1
Features .................................................................................................................................................................. 1
Block Diagram ....................................................................................................................................................... 1
Pin Configuration .................................................................................................................................................. 4
Pin Description ...................................................................................................................................................... 5
Pin Description for THCV231............................................................................................................................. 5
Pin Description for THCV236............................................................................................................................. 6
Functional Overview ........................................................................................................................................... 10
Functional Description ........................................................................................................................................ 10Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP) ............................................ 10Power Down (PDN1, PDN0, PDN) ................................................................................................................. 11
Pre-emphasis and Drive Select Function (THCV231 only) ......................................................................... 11
Permanent Clock Output (THCV236 only) .................................................................................................. 11
Spread Spectrum Clock Generator (SSCG).................................................................................................. 12
Data Enable ...................................................................................................................................................... 14
Hot-Plug Function ........................................................................................................................................... 15
Lock Detect Function ...................................................................................................................................... 15
Field BET Operation ....................................................................................................................................... 16
Data Width and Frequency Range Select Function ..................................................................................... 18
Data Mapping .................................................................................................................................................. 18
2-wire serial I/F Mode ..................................................................................................................................... 19
2-wire serial I/F Device ID setting ................................................................................................................ 19
2-wire serial I/F Clock Stretching ................................................................................................................. 19
Read/Write access to Sub-Link Master Register ........................................................................................... 21
Read/Write access to Sub-Link Slave Register ............................................................................................. 22
Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device............ 24
GPIO.............................................................................................................................................................. 28
Interruption .................................................................................................................................................... 30
Register Map ........................................................................................................................................................ 31
Absolute Maximum Ratings ............................................................................................................................... 40
Recommended Operating Conditions................................................................................................................ 40
Electrical Specification........................................................................................................................................ 40
LVCMOS DC Specification .............................................................................................................................. 40
CML DC Specification ...................................................................................................................................... 41
CML Bi-Directional DC Specification .............................................................................................................. 41

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Supply Current .................................................................................................................................................. 42
Switching Characteristics .................................................................................................................................. 42
AC Timing Diagrams and Test Circuits ............................................................................................................ 46
LVCMOS Input, Output Switching Characteristics .......................................................................................... 46
CML Output Switching Characteristics............................................................................................................. 47
CML Bi-directional Output Test Circuit ............................................................................................................ 48
Latency Characteristics ..................................................................................................................................... 49
Lock and Unlock Sequence ............................................................................................................................... 50
2-wire serial I/F Switching Characteristics ....................................................................................................... 51
GPIO Switching Characteristics ........................................................................................................................ 53
PCB Layout Guideline regarding VDD and AVDD for THCV236 ................................................................. 55
Package ................................................................................................................................................................. 56
Notices and Requests ........................................................................................................................................... 58

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Pin Configuration

HSYNC 25CAPOUT 26
TCMP 27
TCMN 28
TXP 29TXN 30
CAPINA 31
CAPINP 32

23

24

VSYNC
D11
22 D10
21 AVDD
20 D9
19 D8
18 D7
17 D6

THCV231 (QFN 32pin)

VDD
D5
14 D4
13 CLKIN
12 D3
11 D2
10 D1
9 D0
16
15

(TOP VIEW)
33 EXPGND

8

7

6

5

4

3

2

1

GPIO4
GPIO3
SCL
SDA
RF/BETOUT
TEST2
TEST1
PDN
33 D1434 D1335 D12

36 D11

37 D10

38 D9

39 D8

40 AVDD

41 VDD

42 D7

43 D6

44 D5

45 D4

46 D3

47 D2

48 VSYNC

THCV236 (QFN 64pin)
32 VDDVDD 49HSYNC 50
DE 51
D1 52
D0 53
HTPDN/SUBMODE 54
LOCKN/MSSEL 55
CAPOUT 56
RXN 57
RXP 58CAPINA 59
MAINMODE/RCMN 60
HFSEL/RCMP 61
RXDEFSEL 62
OE 63
BET 6431 D1530 D1629 D1728 D1827 D19(TOP VIEW)
65 EXPGND

26 CLKOUT
25 VDD24 D20
23 D21
22 D22
21 D2320 D24/GPIO3
19 D25/GPIO4
18 D2617 D27

16 VDD
15 D2814 D2913 D30
12 D3111 LATEN/SD3/AIN1/GPIO0
10 TTLDRV/SD2/AIN0/GPIO1
9 OUTSEL/SD1
8
COL1/SD0
7
COL0/INT/GPIO2
6
RF/BETOUT
5 TEST2
4 TEST1
3 LFSEL
PDN1
PDN0
2

1

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Pin Description
Pin Description for THCV231
Pin Name
TXP
TXN
TCMP
TCMN
GPIO4

Pin No.

Description
High-Speed CML Signal Output (Main-Link)
High-Speed CML Signal Output (Main-Link)
CML Signal Bidirectional Input/Output (Sub-Link)
CML Signal Bidirectional Input/Output (Sub-Link)
GPIO4 : General Purpose Input/Output.
When GPIO4 is used as Open-Drain Output, it must beconnected with a pull-up resistor to VDD.
When GPIO4 is used as push pull output, no external
component is required.
LATEN : Latch select when Field BET (Sub-Link)
0 : Forbidden
1 : Latched result
GPIO3
7
B
GPIO3 : General Purpose Input/Output.
When GPIO3 is used as Open-Drain Output, it must beconnected with a pull-up resistor to VDD.
When GPIO3 is used as push pull output, no external
component is required.
When Sub-Link Field BET mode, it must be connectedwith a pull-up resistor to VDD.
0 : Field BET pattern generator
1 : Field BET pattern checker
SCL
6B
SCL input/output for 2-wire serial I/F.
SDA
5B
SDA input/output for 2-wire serial I/F.
CLKIN
13
I
Clock Input
D11-D023,22,20-17,15,14,12-9
I
Pixel Data Input
HSYNC
25
I
HSYNC Input
VSYNC
24
I
VSYNC Input
RF/BETOUT 4
B
RF : Input Clock Triggering edge select. See Figure 17.
0 : Falling Edge
1 : Rising Edge
BETOUT : Field BET Result Output when Field BET
mode.
PDN
1
IL
Power Down
0 : Power Down
1 : Normal Operation
TEST2
3
I
Test pin. Must be tied to Ground for normal operation.
TEST1
2
IL
Test pin. Must be tied to Ground for normal operation.
CAPOUT
26
PWR Decoupling Capacitor Pin, 1.2V output.
CAPINA
31
PWR Reference Input for Analog Circuit. Must be tied to
CAPOUT.
CAPINP32
PWR Reference Input for Analog Circuit. Must be tied to
CAPOUT.
VDD
16
PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
AVDD
21
PWR 1.7-3.6V Analog Power Supply Pin for LDO
EXPGND33
GND Exposed Pad Ground. Must be tied to the PCB groundplane through an array of vias.
CO : CML Output buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , B : LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground
29
30
27
28
8

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Type
CO
CO
CB
CB
B

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Pin Description for THCV236
Pin NameRXP
RXN
HFSEL/RCMP

58
57
61

Pin No.

Type
CI
CI
CB/I

MAINMODE/
RCMN

60

CB/I

HTPDN/SUBMODE54

BO

LOCKN/
MSSEL

55

BO

LATEN/SD3/
AIN1/GPIO011

B

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Description
High-Speed CML Signal Input(Main-Link)
High-Speed CML Signal Input(Main-Link)
HFSEL : High Frequency Mode select when PDN1=0.
0 : High Frequency Mode Disable
1 : High Frequency Mode Enable
RCMP : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
MAINMODE : Setting V-by-One® HS Mode or Sync Free Modewhen PDN1=0
0 : V-by-One® HS Mode
1 : Sync Free Mode
RCMN : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
HTPDN : Hot Plug Detect Output when PDN1=0. Must beconnected to Tx HTPDN with 10kΩ pull-up resistor.
SUBMODE : Sub-Link Mode Select when PDN1=1.
0 : 2-wire serial I/F Mode (default No Clock Stretching mode)
1 : Low Speed Data Bridge Mode
Forbid setting 1 when connecting with THCV231.
LOCKN : Lock Detect Output when PDN1=0. Must be connected
to Tx LOCKN with 10kΩ pull-up resistor.
MSSEL : Sub-Link Master/Slave Select when PDN1=1.
0 : Sub-Link Master side(inside 2-wire serial I/F is slave)
1 : Sub-Link Slave side(inside 2-wire serial I/F is master)
Sub-Link Master is connected to HOST MPU.
Forbid setting 1 when connecting with THCV231.
LATEN : Latch select input under Field BET(Main-Link or SubLink).
0 : NOT Latched result
1 : Latched result
SD3 : Sub-Link Data Input/Output when PDN1=1 andSUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD3 is output.
When Sub-Link is Slave (MSSEL=1), SD3 is input.
AIN1 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 19.
GPIO0 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO0 is used as Open-Drain Output, it must be connectedwith a pull-up resistor to VDD.
When GPIO0 is used as push pull output or input, no external
component is required.

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TTLDRV/SD2/
AIN0/GPIO1

10B

OUTSEL/SD1

9B

COL1/SD08

B

COL0/INT/

7

B

26
12-15,17,18

O
O

GPIO2

CLKOUT
D31-D26

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TTLDRV : LVCMOS Output Drive Strength Select when
PDN1=0.
0 : Weak Drive Strength
1 : Normal Drive StrengthSD2 : Sub-Link Data Input/Output when PDN1=1 andSUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD2 is input.
When Sub-Link is Slave (MSSEL=1), SD2 is output.
AIN0 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 19.
GPIO1 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO1 is used as Open-Drain Output, it must be connectedwith a pull-up resistor to VDD.
When GPIO1 is used as push pull output or input, no external
component is required.
OUTSEL : Permanent Clock Output Enable when PDN1=0.
0 : Permanent Clock Output Disable
1 : Permanent Clock Output Enable
SD1 : Sub-Link Data Input/Output when PDN1=1.
When SUBMODE=0, SD1 is used as SCL input/output for 2-wireserial I/F, requires pull-up resistor to VDD.
When SUBMODE=1 and MSSEL=0, SD1 is input.
When SUBMODE=1 and MSSEL=1, SD1 is output.
COL1 : Color Space Converter Enable when PDN1=0 and
MAINMODE=0.
0 : Color Space Converter Disable
1 : Color Space Converter Enable
Data Width Setting when PDN1=0 and MAINMODE=1. See
Table 16.
SD0 : Sub-Link Data Input/Output when PDN1=1.
When SUBMODE=0, SD0 is used as SDA input/output for 2-wireserial I/F, requires pull-up resistor to VDD.
When SUBMODE=1 and MSSEL=0, SD0 is input.
When SUBMODE=1 and MSSEL=1, SD0 is output.
COL0 : Data Width Setting when PDN1=0. See Table 16.
INT : Interrupt signal output for Sub-Link when SUBMODE=0and MSSEL=0. It must be connected with a pull-up resistor to
VDD.
L : Interrupt occurred
H : Steady state
GPIO2 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO2 is used as Open-Drain Output, it must be connectedwith a pull-up resistor to VDD.
When GPIO2 is used as push pull output or input, no external
component is required.
Clock Output
Pixel Data Output

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D25/GPIO4

19

B

D24/GPIO3

20

B

D23-D021-24,27-31,3339,42-47,52,53
51
50
48
63

O

DE
HSYNC
VSYNC
OE

D25 : Pixel Data Output
GPIO4 : General Purpose Input/Output when SUBMODE=0,MSSEL=1 and RXDEFSEL=0.
When GPIO4 is used as Open-Drain Output, it must be connectedwith a pull-up resistor to VDD. When GPIO4 is used as push pull
output or input, no external component is required.
D24 : Pixel Data Output
GPIO3 : General Purpose Input/Output when SUBMODE=0,MSSEL=0 and RXDEFSEL=0.
When GPIO3 is used as Open-Drain Output, it must be connectedwith a pull-up resistor to VDD. When GPIO3 is used as push pull
output or input, no external component is required.
Pixel Data Output

DE Output
HSYNC Output
VSYNC Output
Output Enable
0 : LVCMOS Output Disable (Hi-Z) except for HTPDN,LOCKN when PDN1=0 and except for BETOUT when BET=1
1 : LVCMOS Output Enable
BET
64
IL
Field BET entry
0 : Normal Operation
1 : Field BET Operation
RF/BETOUT
6
B
RF : Output Clock Triggering edge select. See Figure 18.
0 : Falling Edge
1 : Rising Edge
BETOUT : Field BET Result Output
RXDEFSEL
62
I
Internal Register Default Setting Select. See Table 36, Table 37
0 : for THCV231
1 : for THCV235
LFSEL
3
I
Low Frequency mode select
0 : Low Frequency mode Disable
1 : Low Frequency mode Enable
Forbid setting 1 when connecting with THCV231.
PDN1
2
IL
Sub-Link Power Down
0 : Power Down. Main-Link setting by external pin
1 : Normal Operation. Main-Link Setting by 2-wire serial I/F
PDN0
1
IL
Main-Link Power Down
0 : Power Down
1 : Normal Operation
TEST2
5
I
Test pin. Must be tied to Ground for normal operation.
TEST1
4
IL
Test pin. Must be tied to Ground for normal operation.
CAPOUT56
PWR Decoupling Capacitor Pin, 1.2V output.
CAPINA59
PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.
VDD
49,41,32,25,16
PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
AVDD
40
PWR 1.7-3.6V Analog Power Supply Pin for LDO
EXPGND65
GND Exposed Pad Ground. Must be tied to the PCB ground planethrough an array of vias.
CI : CML Input buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer
B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground
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O
O
O
IL

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Table 1. Pin Sharing Description (THCV236)
Sub-Link State →Pin No.
2
54
55
64
62

Sub-Link
Master/Slave →PDN1
HTPDN/SUBMODELOCKN/MSSELBETRXDEFSEL

6

RF/BETOUT

7
8
9
10

COL0/INT/GPIO2
COL1/SD0
OUTSEL/SD1
TTLDRV/SD2/AIN0/GPIO1

11

LATEN/SD3/AIN1/GPIO0

20
19
54
55
60
62

D24/GPIO3
D25/GPIO4HTPDN/SUBMODELOCKN/MSSEL
MAINMODE/RCMN
HFSEL/RCMP

2-wire serial
I/F Mode
Master1
00
00
RF
BETOUT(*1)
INT
SD0(SDA)
SD1(SCL)AIN0
AIN1
LATEN(*2)
GPIO3(*3)
GPIO4(*3)
SUBMODE
MSSEL
RCMN
RCMP

*1 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output.
*2 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input.
*3 Through GPIO input is default on register setting

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Functional Overview
With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
the THCV231 and THCV236 enable transmission of 14bit data through Main-Link by single differential pair cablewith minimal external components. In addition, the THCV231 and THCV236 have Sub-Link which enables bidirectional transmission of 2-wire serial interface signals, GPIO signals and also HTPDN/LOCKN signals for
Main-Link through the other 1-pair of CML-Line. It does not need any external frequency reference such as a
crystal oscillator. The THCV231 - THCV236 system is able to watch peripheral devices and to control them via
2-wire serial interface or GPIOs. They also can report interrupt events caused by change of GPIO inputs andinternal statuses.

Functional Description
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)
An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can’t supply any other externalloads. Bypass CAPOUT to GND with 10uF.
CAPINP (THCV231 only) supplies reference voltage for internal PLL, and CAPINA supplies reference voltage
for any internal analog circuit. Bypass CAPINP/CAPINA to GND with 0.1uF to remove high frequency noise.
CAPOUT, CAPINA and CAPINP must be tied together.
Power supply AVDD is supposed to be stabilized with de-coupling capacitor and series noise filter (for example,
ferrite bead).
THCV236

THCV231
10uF
Power
SupplyAVDDCAPOUT

10uF
PowerSupplyAVDDCAPOUT

0.1uF

0.1uF
CAPINA

CAPINA

0.1uF
CAPINP

Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor

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Power Down (PDN1, PDN0, PDN)
PDN1, PDN0 and PDN turn off internal circuitry of Main-Link and Sub-Link separately.
Table 2. Power Down Setting(THCV231)
PDN
0
1

Operation
Both Main-Link and Sub-Link power down
Both Main-Link and Sub-Link active

Table 3. Power Down Setting(THCV236)
PDN1
0
0
1
1

PDN0
0
1
0
1

Operation
Both Main-Link and Sub-Link power down
Only Main-Link is active
Only Sub-Link is active
Both Main-Link and Sub-Link active

Pre-emphasis and Drive Select Function (THCV231 only)
Pre-emphasis can equalize severe signal degradation caused by long-distance or high-speed transmission. PRE
register selects the strength of pre-emphasis. CMLDRV register controls CML Main-Link output swing level. See
Table 4.

Table 4. Pre-emphasis and Drive Select function table
CMLDRV[1:0](reg)

ConditionPre-emphasis Level
0dB
400mV diff p-p
6dB
0dB
600mV diff p-p
3.5dB
800mV diff p-p
0dB
Forbidden

PRE
(reg)
0
1
0
1
*
*

00
01
10
11

Swing Level

Permanent Clock Output (THCV236 only)
When there is no input from Main-Link, the THCV236 will output internal oscillator clock from CLKOUT pin.
This function is controlled by OUTSEL pin or OUTSEL_ENABLE register and OUTSEL_SETTING register. See
Table 5.
Table 5. Permanent Clock Output function table (PDN1=1)
OUTSEL_ENABLE(reg)
0
1

OUTSEL_SETTING
(reg)
*
00
01
10
11

Output Clock
Frequency(*1)
80MHz40MHz(default)
20MHz
10MHz

*1 typical value

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THCV231_THCV236_Rev.3.12_E
Spread Spectrum Clock Generator (SSCG)
The THCV231 serial data output and the THCV236 parallel data and clock outputs are modulated byprogrammable SSCG. The THCV231 and THCV236 SSCG are enabled by only SSEN register. The modulation
rate and modulation frequency variation of output spread is controlled through the SSCG control registers on eachdevice. Do not enable spread spectrum for both the THCV231 and THCV236 at the same time.

Table 6. SSCG enable signal
Mode Entry Signal

Description

SSEN(reg)

0:SSCG Disable
1:SSCG Enable

When customer use the mode and frequency range shown in Table 7, register setting is required according toTable 8.

Table 7. Main-Link mode and frequency range requiring register setting
Mode Setting
MAINMODE
0
0
0
1
1
1
1
*1 Don’t care
*2 See Table 8

HFSEL
0
0
1
0
0
0
1

COL1
0
0
0
0
0
1

COL0
0
1
1
0
1
0

(*1)

(*1)

Freq.Range[MHz](SSCG Enable)
min
max
26.6
50
33.3
66.6
50
100
26.6
40
26.6
50
33.3
66.6
50
100

Register
Setting
(*2)

Case1
Case2
Case3
Case1
Case1
Case2
Case3

Table 8. SSCG register setting
Step
1
2
3
4

Register Address(HEX)
Sub-Link
Sub-Link
Master side
Slave side
0x70
0xF0
0x51 [5]0xD1 [5]
0x70
0xF0
0x76
0xF6
0x78
0xF8
0x7C
0xFC

Register Value(HEX)
Case3
Case1
Case2
THCV231
THCV236
0x00
0x1
0x01
0x02
0x02
0x01
0x3C
0x30
0x20
0x35
0x34
0x24

Description
Set 0 to PLL_SET_EN (reg)Set 1 to SSEN (reg)Set 0 to PLL_SET_EN (reg)Set PLL_SET0 (reg)Set PLL_SET1 (reg)Set PLL_SET2 (reg)Modulation frequency fmod can be determined by HFSEL and LFSEL settings, input clock frequency and FMOD
register setting (default value 0xD). Refer to following formula.

f mod f CLKSSCG
128  FMOD

fCLKSSCG is the frequency listed in Table 9 and Table 10.
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THCV231_THCV236_Rev.3.12_E

Table 9. fCLKSSCG (THCV231)
HFSEL
(reg)
0
1

fCLKSSCG(1/tTCIP)/2(1/tTCIP)/4

Table 10. fCLKSSCG (THCV236)
HFSEL

LFSEL

fCLKSSCG

0
1
*

0
0
1

(1/tRCP)/2(1/tRCP)/4
Forbidden Setting

Up to 0.5 % spread at the 30kHz modulation frequency is stable for most cases. In case of using out of this range,
verify at the actual system.

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THCV231_THCV236_Rev.3.12_E
Data Enable
V-by-One® HS mode operation (MAINMODE (pin)=0) are shown below. THCV231 HSYNC pin input is DE
signal.

Table 11 and related note shows requirements for DE. Video HSYNC signal may meet DE input

requirement.

HSYNC output of THCV236 under THCV231 V-by-One® HS mode operation is invalid.
THCV231

THCV236

D11-D0

1

Video Data
CONT

0

VSYNC

DE=1, D31-D0
DE=0, Low fixed
DE=1, VSYNC=Fixed
DE=0, VSYNC

VSYNC

DE (HSYNC pin input)

DE (DE pin output)

Figure 2. Conceptual Diagram of the Basic Operation of the Chipset in V-by-One® HS mode
THCV231
Input

tDEINT
tDEH

tDEL

CLKIN
(RF=1)

DE(HSYNC pin inut)

Low

High

High

Low

Low

High

Valid Data

Invalid

Invalid

Valid Data

Valid Data

Invalid

Invalid

Valid Data

Valid Data

Invalid

Invalid

Valid Data

VSYNC

D11-D0(MAINMODE=0)

THCV236
OutputtDEH

tDEL

CLKOUT(RF=1)DE(DE pin output)

Low

High

High

Valid Data

Keep the last dataof DE=L period

Keep the last dataof DE=L period

Valid Data

Valid Data

Low

Low

High

Valid Data

Valid Data

Keep the last dataof DE=L period

Low fixed

Low fixed

VSYNC

D11-D0

Low fixed

Valid Data

(MAINMODE=0)

Figure 3. Data and Synchronizing Signals Transmission Timing Diagram in V-by-One® HS mode
Table 11. DE Requirement
SymbolParametertDEH

DE=1 Duration

tDEL

DE=0 Duration

Condition
MAINMODE=0 and HFSEL=0
MAINMODE=0 and HFSEL=1
MAINMODE=1
MAINMODE=0 and HFSEL=0
MAINMODE=0 and HFSEL=1
MAINMODE=1Min
2×tTCIP
4×tTCIP

Typ
Max
*Note
Don’t care
2×tTCIP
4×tTCIP *Note
Don’t care

Unit
ns
ns
ns
ns

*Note: In V-by-One® HS Mode (MAINMODE=0) and High Frequency Mode (HFSEL=1), the period between rising edges of DE(tDEINT), high time of DE (tDEH) should always satisfy following equations.
tDEH = tTCIP*(2m) and tDEINT = tTCIP*(2n), m,n=2,3,4,5,6……

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THCV231_THCV236_Rev.3.12_E
Hot-Plug Function
HTPDN signal indicates connecting condition between the Transmitter and the Receiver. HTPDN of thetransmitter side is high when the Receiver is not active or not connected. Then the Transmitter can enter into thepower down mode. HTPDN is set to low by the Receiver when the Receiver is active and connects to theTransmitter, and then the Transmitter must start up and transmit CDR training pattern for link training.
HTPDN is transferred to the Transmitter via Sub-Link line. HOST MPU can confirm HTPDN state by reading
Sub-Link Master register (0x00 bit0 HTPDN).

Lock Detect Function
LOCKN indicates whether the receiver CDR PLL is in the lock state or not. LOCKN at the Transmitter input is
set to High when the Receiver is not active or at the CDR PLL training state. LOCKN is set to low by the Receiver
when CDR lock is done. Then the CDR training mode finishes and the Transmitter shifts to the normal operation.
LOCKN is transferred via Sub-Link line. HOST MPU can confirm LOCKN state by reading Sub-Link Masterregister (0x00 bit1 LOCKN).

THCV231

THCV236

V-by-One®HS
Main-Link
Transmitter

V-by-One®HS
Main-Link
ReceiverMain-Link

LOCKN,
HTPDN
2-wireserialMaster

Sub-Link
Slave

LOCKN,HTPDN
Sub-Link

Register2-wireserialSlave

Sub-Link
MasterSD1(SCL)
SD0(SDA)

Host
MPU

Register0x00
bit1:LOCKN
bit0:HTPDN

Sub-Link Block(Slave)Sub-Link Block(Master)

THCV231:Sub-Link Slave, THCV236:Sub-Link MasterFigure 4. HTPDN, LOCKN transmission route

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THCV231_THCV236_Rev.3.12_E
Field BET Operation
In order to help users to check validity of CML serial line (Main-Link and Sub-Link), the THCV231 and
THCV236 have an operation mode in which they act as a bit error tester (BET). In Main-Link Field BET mode,
the THCV231 internally generates a test pattern which is then serialized onto the Main-Link CML line. The
THCV236 also has BET function mode. The THCV236 receives the data stream and checks bit errors. The
generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the CML channel. As for the
THCV236, the internal test pattern check circuit gets enabled and reports result on a certain pin named BETOUT.
In Sub-Link Field BET mode, Sub-Link Master device internally generates test pattern which is then serialized
onto the Sub-Link CML line. Sub-Link Slave device also has BET function mode. Sub-Link Slave device receives
the data stream and checks bit errors. Note that Sub-Link Slave device must be set this mode prior to Sub-Link
Master device. Pattern check result is output from BETOUT pin of the Sub-Link Slave device. The BETOUT pingoes LOW whenever bit errors occur, or it stays HIGH when there is no bit error.
In Main-Link Field BET mode, user can select two kinds of check result, latched result or NOT latched result by
setting LATEN pin input. The latched result is reset by setting LATEN=0. In Sub-Link Field BET mode, only
latched result is available. In order to reset the latched result, once turn off the power and entry Sub-Link Field
BET from power on sequence. GPIO4 pin (THCV231) and LATEN/SD3/AIN1/GPIO0 pin (THCV236) function
as LATEN in Field BET mode (Main-Link or Sub-Link).

It is not possible to realize Main-Link Field BET and

Sub-Link Field BET at the same time.
Table 12. Main-Link Field BET Operation Settings
Register value with brace (e.g. {0},{1}) means default value.
PDN
(pin)
1

THCV231BET
BET_SEL(reg)(reg)
0xD3[1]
0xD3[0]
1

{0}

PDN0
(pin)

PDN1
(pin)

1

1

THCV236
BET_SEL
BET
(reg)
(pin)
0x53[0]
1

{0}

MSSEL
(pin)
0

LATEN
(pin)

Description0

Not Latched Result

1

Latched Result

Table 13. THCV236 Main-Link Field BET Result
BETOUT
L
H
Data inputs
are ignored

THCV231

CLKIN

Test Pattern
Generator

OutputBit Error Occurred
No Error
THCV236

Test Pattern
Checker

Main-Link

BET=1 BET_SEL=0(Register) (Register)0
1

RF/BETOUT
Test Point
for
Field BET

BET=1 BET_SEL=0 LATEN/SD3/AIN1/GPIO0 = 0 or 1
(Register)(Pin)

Figure 5. Main-Link Field BET Configuration

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THCV231_THCV236_Rev.3.12_E

Table 14. Sub-Link Field BET Operation Setup sequence
Register value with brace (e.g. {0},{1}) means default value.
Direction of Sub-Link Field BET Operation is THCV231 => THCV236.
THCV231BET
BET_SEL
Step
PDN
GPIO3
GPIO4
PDN0
(reg)
(reg)
(pin)
(pin)
(pin)
(pin)
0xD3[1]
0xD3[0]

PDN1
(pin)

BET
(pin)

THCV236
BET_SEL(reg)
0x53[0]

MSSEL
(pin)

LATEN
(pin)

Description

Initial

1

{0}

{0}

OutputOutput

0

1

0

{0}

0

1

1

↓

1

1

1

1

↓

↓

↓

↓

↓

↓

2

↓

↓

↓

↓

↓

↓

↓

↓

1

↓

↓

3

↓

↓

↓

↓

↓

↓

↓

↓

↓

1

↓

GPIO3 and 4 are connected withpull-up register to VDD.
THCV231
Sub-Link Field BET mode enable.
GPIO3 and 4 are switched to input.
THCV236
Set to Sub-Link Field BET mode.
THCV236
Set to Sub-Link Slave mode

4

↓

↓

↓

↓

↓

↓

↓

1

↓

↓

↓

THCV236 Field BET mode enable.

5

↓

↓

↓

0

↓

↓

↓

↓

↓

↓

↓

THCV231
Set to Sub-Link Master mode.

PDN1
(pin)

BET
(pin)

MSSEL
(pin)

LATEN
(pin)

Description

Direction of Sub-Link Field BET Operation is THCV236 => THCV231.
THCV231BET
BET_SEL
Step
PDN
GPIO3
GPIO4
PDN0
(reg)
(reg)
(pin)
(pin)
(pin)
(pin)
0xD3[1]
0xD3[0]

THCV236
BET_SEL(reg)
0x53[0]Initial

1

{0}

{0}

OutputOutput

0

1

0

{0}

0

-

1

↓

1

1

1

1

↓

↓

↓

↓

↓

-

2

↓

↓

↓

↓

↓

↓

↓

↓

1

↓

-

3

↓

↓

↓

↓

↓

↓

↓

1

↓

↓

-

GPIO3 and 4 are connected withpull-up register to VDD.
THCV231
Sub-Link Field BET mode enable.
GPIO3 and 4 are switched to input.
THCV236
Set to Sub-Link Field BET mode.
THCV236 Field BET mode enable.

Table 15. Sub-Link Slave device Sub-Link Field BET Result
BETOUT
L
H

OutputBit Error Occurred
No Error

THCV231

Test Pattern
Generator

OSC

GPIO4 (Pin)

THCV236

Sub-Link

BET=1 BET_SEL=1(Register) (Register)

Test Pattern
Checker

BET=1 BET_SEL=1(Pin)(Register)

GPIO3 (Pin)

THCV231

Test Pattern
Checker

RF/BETOUT
Test Point
for
Field BET

GPIO4=1(Pin)
GPIO3(Pin)

RF/BETOUT
Test Point
for
Field BETMSSEL (Pin)
LATEN/SD3/AIN1/GPIO0 =1

THCV236

Sub-Link

BET=1 BET_SEL=1(Register) (Register)

Test Pattern
Generator

OSC

BET=1 BET_SEL=1(Pin)(Register)

MSSEL (Pin)

Figure 6. Sub-Link Field BET Configuration

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THCV231_THCV236_Rev.3.12_E
Data Width and Frequency Range Select Function
The THCV231 and THCV236 support a variety of data width and frequency range. Frequency range is different
depending on the mode setting SSCG enable and disable setting. Refer to Table 16 for details.

Table 16. Main-Link Operation Mode SelectFreq.Range [MHz]
SSCG
SSCG
DisableEnable (*1)
min
max
min
max

Mode Setting
MAINMODE

HFSEL

COL1

COL0

0
0
0
0

*
0
0
1

1
0
0
0

*
0
1
0

0

1

0

1

1
1
1
1
1

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

1

1

0

1

1

1

1

0

1(*3)

1

1

1

100
133.3
70
160
30
40
75
70
160
70
160
70
160

15
20
50
70
12
15
20
50
70
50
70
50
70

26.6
33.3
50
70
26.6
26.6
33.3
50
70
50
70
50
70

100
133.3
70
160
60
75
100
70
160
70
160
70
160

Main-Link
CML
Bit Rate

Data Width
Data

Sync

x40
x30
-

12
12
-

2
2
-

x20

12

2

x50
x40
x30
-

14
14
14

x20

14

x15

10

Comment

Forbidden

Forbidden(*2)
Forbidden
Forbidden(*2)(*2)(*2) (*3)
(*3)

-

x15

8

2

*1 Note that register setting is required depending on the mode setting and used frequency range. See Table 7.
*2 Register setting is required. See Table 17.
*3 While Register MAINMODE setting = 1, however, behavior of this exceptional setting is V-by-One® HS Mode whose meaning is MAINMODE = 0.

Table 17. Register setting (HFSEL=1 and Frequency range is from 50MHz to 70MHz)
Step
1
2
3
4

Register Address(HEX)
Sub-Link
Sub-Link
Master side
Slave side
0x70
0xF0
0x51 [5]0xD1 [5]
0x70
0xF0
0x76
0xF6
0x78
0xF8
0x7C
0xFC

Register Value(HEX)THCV231

Description

THCV236
0x00
0x1
0x01

0x02

0x01
0x20
0x24

Set 0 to PLL_SET_EN (reg)Set 1 to SSEN (reg)Set 1 to PLL_SET_EN (reg)Set PLL_SET0 (reg)Set PLL_SET1 (reg)Set PLL_SET2 (reg)Data Mapping
Table 18. Data Mapping
MAINMODE
HFSEL
COL1
COL0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
HSYNC
VSYNC

0
0
0
0
D0/RAW4
D1/RAW5
D2/RAW6
D3/RAW7
D4/RAW8
D5/RAW9
D6/RAW10
D7/RAW11
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3
DE*2(HSYNC*3)
VSYNC

0
0
0
1
D0/RAW4
D1/RAW5
D2/RAW6
D3/RAW7
D4/RAW8
D5/RAW9
D6/RAW10
D7/RAW11
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3
DE*2(HSYNC*3)
VSYNC

0
1
0
1
D0/RAW4/YC0
D1/RAW5/YC1
D2/RAW6/YC2
D3/RAW7/YC3
D4/RAW8/YC4
D5/RAW9/YC5
D6/RAW10/YC6
D7/RAW11/YC7
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3
DE*2(HSYNC*3)
VSYNC

1
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11

1
0
0
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11

1
0
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11

1
1
0
1
D0/RAW4
D1/RAW5
D2/RAW6
D3/RAW7
D4/RAW8
D5/RAW9
D6/RAW10
D7/RAW11
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3

1
1
1
0
D0/YC0D1/YC1D2/YC2
D3/YC3
D4/YC4
D5/YC5
D6/YC6
D7/YC7-HSYNC*1

HSYNC*1

HSYNC*1

HSYNC*1

HSYNC*1

VSYNC*1

VSYNC*1

VSYNC*1

VSYNC*1

VSYNC*1

1
1
1
1
D0/RAW0/YC0
D1/RAW1/YC1
D2/RAW2/YC2
D3/RAW3/YC3
D4/RAW4/YC4
D5/RAW5/YC5
D6/RAW6/YC6
D7/RAW7/YC7
DE*2(HSYNC*3)VSYNC*1*1 Any signal as well as sync signal can be transmitted when MAINMODE=1.
*2 V-by-One®HS mode operation requires Data Enable (DE) signal rule. Refer to the related section.
*3 HSYNC signal can be assigned to Data Enable input when V-by-One® HS mode requirements are met.

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THCV231_THCV236_Rev.3.12_E
Sub-Link Mode Setting
2-wire serial I/F Mode
2-wire serial I/F Mode enables register access, using GPIO (General Purpose Input/Output) pin and interrupt
function. Sub-Link Master device has 2-wire serial slave block and can be connected to HOST MPU, Sub-Link
Slave device has 2-wire serial master block and can be connected to remote side 2-wire serial slave devices.
HOST MPU can access register of Sub-Link Master device, Sub-Link Slave device and remote side 2-wire serial
slave devices.

2-wire serial I/F Device ID setting
AIN1 and AIN0 pins determine Device ID setting of the THCV236. Only Sub-Link Master device has AIN1 and
AIN0 pin. AIN1 and AIN0 choose one of 4 addresses which give an identification address to the THCV236 under2-wire serial interface bus topology.

Table 19. 2-wire serial I/F Device ID select (Sub-Link Master device Only)
AIN1
0
0
1
1

AIN0
0
1
0
1

Device ID(7’h)
0x0B
0x34
0x77
0x65

2-wire serial I/F Clock Stretching
In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial accessand Sub-Link Slave internal bus access or remote side 2-wire serial access.
2WIRE_MODE (Sub-Link Master side register, 0x0F bit1-0) selects whether 2-wire serial slave of Sub-Link
Master perform clock stretching or not.
When 2WIRE_MODE = 00, Sub-Link Master device wait HOST MPU until Sub-Link Slave register access or
remote side 2-wire serial slave register access is completed by clock stretching.
When 2WIRE_MODE = 01, Sub-Link Master device informs HOST MPU that Sub-Link Slave register accessor remote side 2-wire serial register access has been completed by interruption (INT pin) without clock stretching.

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THCV231_THCV236_Rev.3.12_E

Figure 7. 2WIRE_MODE Operation

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THCV231_THCV236_Rev.3.12_E
Read/Write access to Sub-Link Master Register
HOST MPU can directly access Sub-Link Master’s register by 2-wire serial I/F.
Register address of Sub-Link Master is from 0x00 to 0x7F. See Register Map for more information.

Figure 8. Host to Sub-Link Master Register access configuration

Figure 9. 2-wire serial I/F write to Sub-Link Master register protocol

Figure 10. 2-wire serial I/F read to Sub-Link Master register protocol

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THCV231_THCV236_Rev.3.12_E
Read/Write access to Sub-Link Slave Register
HOST MPU can access to Sub-Link Slave’s register via Sub-Link Master by Sub-Link Master register settings.
Register address of Sub-Link Slave is from 0x80 to 0xFF. See Register Map for more information.

Figure 11. Host MPU to Sub-Link Slave Register access configuration

Table 20. Sub-Link slave register Write Procedure
Step

Description

R/W

Address

1

Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).

W

0x02 bit7

2

Set the data for Sub-Link Slave to write (Max 16byte).

W0x10-0x1F

W

0x20

W

0x21

Set Device ID of Sub-Link Master device.
3(Value corresponding to AIN1 and AIN0 setting. e.g.[AIN1,AIN0]=[0,0] → 7’h0B)
Set the byte number written to Sub-Link Slave (Max 16byte).

4(Byte number = register value + 1)
5

Set the start address of Sub-Link Slave register to write.

W

0x23

6

Write 1 to WR_START_8B. (Start write access to Sub-Link Slave register)W

0x25 (*1)

7

2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
-

-

(*2)

register access is completed.

7

When write access is completed, 2WIRE_ACS_END_INT register value become 1
and interrupt occurs (INT=H → L).

-

-

(*3)

8

If write access was normally ended, read value should be “0x1”.

R

0x02 bit7*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)

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THCV231_THCV236_Rev.3.12_E
Table 21. Sub-Link slave register Read Procedure
Step

Description

R/W

Address

1

Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).

W

0x02 bit7

W

0x20

W

0x22

Set Device ID of Sub-Link Master device.
2(Value corresponding to AIN1 and AIN0 setting. e.g. [AIN1,AIN0]=[0,0] → 7’h0B)
Set the byte number read from Sub-Link Slave(Max 16byte).

3(Byte number = register value + 1)
4

Set the start address of Sub-Link Slave register to read.

W

0x24

5

Write 1 to RD_START_8B. (Start read access to Sub-Link Slave register)W

0x26 (*1)

-

-

-

-

2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
6
register access is completed. When read access is completed, SCL is released and(*2)

read data is stored in Sub-Link Master register (Address 0x10-0x1F).
When read access is completed, read data is stored in Sub-Link Master register6(Address 0x10-0x1F) and 2WIRE_ACS_END_INT register value become 1 and(*3)

interrupt occurs (INT=H → L).

7

If read access was normally ended, read value should be “0x1”.

R

0x02

8

HOST MPU read data stored in Sub-Link Master register.

R

0x10-0x1F*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)

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THCV231_THCV236_Rev.3.12_E
Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device
HOST MPU can access to remote side 2-wire serial slave register via Sub-Link Master and Sub-Link Slave by
Sub-Link Master register settings. Sub-Link Slave has 2-wire serial master block. Up to 8 devices are connectableto 2-wire serial master of Sub-Link Slave device.

Figure 12. Host to 2-wire serial Slave devices connected to Sub-Link Slave device access configuration

Table 22. Remote side 2-wire serial slave register Write Procedure for 8bit register address
Step

Description

R/W

AddressW

0x04-0x0B

Set slave address of remote side 2-wire serial slave device (Low-order 7bits),1and enable this address (High-order 1bit).
2

Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).

W

0x02 bit7

3

Set the data for remote side 2-wire serial slave to write (Max 14byte).

W0x10-0x1D

W

0x20

W

0x21

W

0x23

W

0x25 (*1)

-

-

-

-

Set slave address of access target 2-wire serial slave (choose the value set in 0x044
0x0B[6:0]), and set 0 to 0x20 bit7.
Set the byte number written to remote side 2-wire serial slave (Max 14byte).
5(Byte number = register value + 1)
6

Set the start address of remote side 2-wire serial slave register to write.
Write 1 to WR_START_8B. (Start write access to remote side 2-wire serial slave

7
register)8

2-wire serial slave of Sub-Link Master perform clock stretching until remote side 2-(*2)

wire serial slave register access is completed.

8

When write access is completed, 2WIRE_ACS_END_INT register value become 1(*3)

and interrupt occurs (INT=H → L).

9

If wire access was normally ended, read value should be “0x1”.

R

0x02

10

Repeat from step2 to step9 if needed.

--*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)

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THCV231_THCV236_Rev.3.12_E
Table 23. Remote side 2-wire serial slave register Write Procedure for 16bit register address
Step

Description

R/W

AddressW

0x04-0x0B

Set slave address of remote side 2-wire serial slave device (Low-order 7bits),1and enable this address (High-order 1bit).
2

Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).

W

0x02 bit7

3

Set the data for remote side 2-wire serial slave to write (Max 14byte).

W0x10-0x1D

W

0x20

W

0x21

W

0x27

W

0x28

W

0x2B (*1)

-

-

-

-

Set slave address of access target 2-wire serial slave (choose the value set in 0x044
0x0B[6:0]), and set 1 to 0x20 bit7.
Set the byte number written to remote side 2-wire serial slave (Max 14byte).
5(Byte number = register value + 1)
Set the low-order bits([7:0]) of start address of remote side 2-wire serial slave register6
to write.
Set the high-order bits([15:8]) of start address of remote side 2-wire serial slave
7
register to write.
Write 1 to WR_START_16B. (Start write access to remote side 2-wire serial slave
8
register)
9

2-wire serial slave of Sub-Link Master perform clock stretching until remote side 2-(*2)

wire serial slave register access is completed.

9

When write access is completed, 2WIRE_ACS_END_INT register value become 1(*3)

and interrupt occurs (INT=H → L).

10

If write access was normally ended, read value should be “0x1”.

R

0x02

11

Repeat from step2 to step10 if needed.

--*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)

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THCV231_THCV236_Rev.3.12_E
Table 24. Remote side 2-wire serial slave register Read Procedure for 8bit register address
Step

Description

R/W

AddressW

0x04-0x0B

W

0x02 bit7

W

0x20

W

0x22

W

0x24

W

0x26 (*1)

-

-

-

-

Set slave address of remote side 2-wire serial slave device (Low-order 7bits),1and enable this address (High-order 1bit).
2

Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
Set slave address of access target 2-wire serial slave (choose the value set in 0x04-

30x0B)(Low-order 7bits), and set 0 to 0x20 bit7.
Set the byte number read from remote side 2-wire serial slave(Max 14byte).
4(Byte number = register value + 1)
5

Set the start address of remote side 2-wire serial slave register to read.
Write 1 to RD_START_8B. (Start read access to remote side 2-wire serial slave

6
register)2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
7
register access is completed. When read access is completed, SCL is released and(*2)

read data is stored in Sub-Link Master register (Address 0x10-0x1F).
When read access is completed, read data is stored in Sub-Link Master register7(Address 0x10-0x1F) and 2WIRE_ACS_END_INT register value become 1 and(*3)

interrupt occurs (INT=H → L).
8

If read access was normally ended, read value should be “0x1”.

R

0x02

9

HOST MPU read data stored in Sub-Link Master register.

R

0x10-0x1F

10

Repeat from step2 to step10 if needed.

--*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)

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THCV231_THCV236_Rev.3.12_E
Table 25. Remote side 2-wire serial slave register Read Procedure for 16bit register address
Step

Description

R/W

AddressW

0x04-0x0B

W

0x02 bit7

W

0x20

W

0x22

W

0x29

W

0x2A

W

0x2C (*1)

-

-

-

-

Set slave address of remote side 2-wire serial slave device (Low-order 7bits),1and enable this address (High-order 1bit).
2

Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
Set slave address of access target 2-wire serial slave (choose the value set in 0x04-

30x0B)(Low-order 7bits), and set 1 to 0x20 bit7.
4

Set the byte number read from remote side 2-wire serial slave(Max 14byte).
Set the low-order bits([7:0]) of start address of remote side 2-wire serial slave register5
to read.
Set the high-order bits([15:8]) of start address of remote side 2-wire serial slave register6
to read.
Write 1 to RD_START_16B. (Start read access to remote side 2-wire serial slave
7
register)2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
8
register access is completed. When read access is completed, SCL is released and(*2)

read data is stored in Sub-Link Master register (Address 0x10-0x1F).
When read access is completed, read data is stored in Sub-Link Master register8(Address 0x10-0x1F) and 2WIRE_ACS_END_INT register value become 1 and(*3)

interrupt occurs (INT=H → L).
9

If read access was normally ended, read value should be “0x1”.

R

0x02

10

HOST MPU read data stored in Sub-Link Master register.

R

0x10-0x1F

11

Repeat from step2 to step10 if needed.

--*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)

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THCV231_THCV236_Rev.3.12_E
GPIO
The GPIO pin provides up to 2-I/O ports and 2 types of GPIO are available (“Through GPIO” and “Programmable
GPIO”). All GPIO pins of THCV236 have another function if being set. See Table 27. GPIO type is selected by
GPIO_TYPE register (0x40(Sub-Link Master), 0xC0(Sub-Link Slave)). Programmable GPIO is available by all
GPIO pins. Through GPIO is available by only GPIO4 and GPIO3 pin. See Through GPIO section and
Programmable GPIO section about detail of respective GPIO type.

Table 26. GPIO TypeGPIO TypeThrough GPIO
Programmable GPIO

GPIO#
GPIO4
GPIO3

Available

Available

Table 27. GPIO setting of THCV236
Pin Name
D25/GPIO4
D24/GPIO3
COL0/INT/GPIO2TTLDRV/SD2/AIN0/GPIO1
LATEN/SD3/AIN1/GPIO0Function
Sub-Link Master
RXDEFSEL=0
GPIO4
GPIO3
INT
AIN0
AIN1

Through GPIO
Input to GPIO4 and GPIO3 of Sub-Link Master device is output from GPIO4 and GPIO3 of Sub-Link Slave
device respectively. Note that these GPIO signals can’t be transferred from Sub-Link Slave device to Sub-Link
Master device. It’s possible to confirm GPIO4 and GPIO3 input value to Sub-Link Master by register read (0x41
GPIOn_INPUT_MONITOR (n=4,3) ). Each GPIO output signal goes to Low when Sub-Link communication fails.
Sub-Link communication status can be observed by register read (0x82 bit2 COMERR_INT).

HOST
MPU

2-wireSerialI/F

THCV236(Sub-Link Master)
GPIO Input : Read 0x41 value

THCV231(Sub-Link Slave)

Sub-Link
Control Block

Sub-Link
Control Block

Register
ADR

GPIO4
GPIO3
(Input)

IO

Register

Name

Value

0x40 GPIOn_TYPE (n=4,3)ADR

10x41 GPIOn_INPUT_MONITOR (n=4,3)

GPIO
Iuput value

Name

Value

0xC0 GPIOn_TYPE (n=4,3)1

0xC1 GPIOn_INPUT_MONITOR (n=4,3)*0x42 GPIOn_OUT (n=4,3)*

0xC2 GPIOn_OUT (n=4,3)*

0x43 GPIO_IO_SEL(*1)

0xC3 GPIO_IO_SEL(*1)

0x46 GPIOn_OUTBUF_SEL (n=4,3)*

0xC6 GPIOn_OUTBUF_SEL (n=4,3)*

IO

GPIO4,
GPIO3(Output)
Pull-up forOpen Drain
Output(default)*1 See Table 28

Figure 13. Through GPIO

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THCV231_THCV236_Rev.3.12_E
Table 28. THCV231, THCV236(RXDEFSEL=0) Through GPIO register setting
GPIO
Input/Output
Number

Sub-Link
Master/Slave

DeviceGPIO4 , GPIO3
Input/Output Configuration(I:Input, O:Output)

Register Settings
GPIO Type

Input

Output

GPIO4

GPIO3

Address(HEX)

GPIO IO Direction

Value
(BIN)

Address
(HEX)

Value
(BIN)

THCV231

Slave

0

2

O

O

0xC0

XXX11XXX

0xC3

XXX00XXXTHCV236

Master

2

0

I

I

0x40

XXX11XXX

0x43

XXX11XXX

Programmable GPIO
Settings input/output and reading/writing are controlled by register settings in the Sub-Link Master. HOST MPU
commands register setting in the Sub-Link Master.

2-wireSerial
I/F

HOST
MPU

THCV236(Sub-Link Master)
GPIO Input: Read 0x41,0xC1 value

THCV231(Sub-Link Slave)

Sub-Link
Control Block

GPIO Output : Write 0x42,0xC2 value

Sub-Link
Control Block

Register

GPIO4
|
GPIO3
(Inputor
Output)ADR

Register

Name

Value

0x40 GPIOn_TYPE (n=4~3)

IO

0x42 GPIOn_OUT (n=4~3)

GPIO
Input Value
GPIO

0x46 GPIOn_OUTBUF_SEL (n=4~3)

00xC2 GPIOn_OUT (n=4~3)

Pull-up forOpen Drain
Output(defau lt)(*1)

0xC6 GPIOn_OUTBUF_SEL (n=4~3)

0 or 1IO

GPIO
Input Value
GPIO
Output Value

0xC3 GPIO_IO_SEL

(*1)

GPIO4
|
GPIO3
(Inputor
Output)Value

0xC1 GPIOn_INPUT_MONITOR (n=4~3)

Ouput Value

0x43 GPIO_IO_SEL

Name

0xC0 GPIOn_TYPE (n=4~3)00x41 GPIOn_INPUT_MONITOR (n=4~3)

Pull-up for
Op en Drain
Ou tput(default)

ADR

0 or 1*1 See Table 29,Table 30

Figure 14. Programmable GPIO
Register settings are required according to the number of GPIO used by customer. See Table 29 and Table 30.
When the number of GPIO used by customer is less than the value listed in Table 29 and Table 30, choose any
setting which includes that.

Table 29. THCV231 Programmable GPIO register setting
GPIO4 – GPIO3
Input/Output Configuration(I:Input, O:Output)

GPIO
Input/Output
Number

Sub-Link
Master/Slave

Slave

Register Settings
GPIO TypeGPIO IO Direction

Input

Output

GPIO4

GPIO3

Address
(HEX)

Value
(BIN)

Address
(HEX)

2
1
0

0
1
2

I
I
O

I
O
O

0xC0

XXX00000

0xC3

Value
(BIN)
XXX11XXX
XXX10XXX
XXX00XXX

Table 30. THCV236 Programmable GPIO register setting (RXDEFSEL=0)
Sub-Link
Master/Slave

MasterGPIO
Input/Output
NumberGPIO4 – GPIO0
Input/Output Configuration(I:Input, O:Output, -:Unavailable)

Register Settings
GPIO Type

Input

Output

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

Address
(HEX)

2
1
0

0
1
2

I
I
O

I
O
O

-

-

-

0x40

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GPIO IO Direction

Value
(BIN)

Address(HEX)

XXX00XXX

0x43

Value
(BIN)
XXX11XXX
XXX10XXX
XXX00XXX

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THCV231_THCV236_Rev.3.12_E
Interruption
INT pin outputs interrupt event indicator on Sub-Link Master side of the system. The INT signal is active low.
Being set by 2-wire serial interface, the THCV231 and THCV236 can monitor any changes of GPIO input pins,
Sub-Link communication statuses and internal statuses as an interrupt. About the way to make interruption occur
and the way to clear the interruption, see Table 32(Address 0x02, 0x03) and Table 33(Address 0x82, 0x83).

Figure 15. 2-wire serial I/F Interrupt to HOST access configuration

Table 31. Interrupt output
INTLH

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State
Interrupt occurred
Steady state

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THCV231_THCV236_Rev.3.12_E

Register Map
HOST MPU can set various operating conditions of the THCV231 and THCV236 through internal registers.
Sub-Link Master (2-wire serial slave) is connected to external HOST MPU (2-wire serial master).
Sub-Link Slave (2-wire serial master) is connected to external 2-wire serial slave devices.
Sub-Link Master device has address 0x00-0x7F, Sub-Link Slave device has address 0x80-0xFF. See Figure 16.

THCV231(Sub-Link Slave)

THCV236(Sub-Link Master)

0x80

0x00
・・・

・・・

Sub-Link Slave
Control Register

0x8F
0xC0
THCV231 GPIO
Control Register

Sub-Link

0xC6

2-wireserialI/F

THCV236 GPIO
Control Register

0x46
Reserved

・・・

・・・

・・・

Reserved

0x40
・・・

・・・

0xD0

HOST
MPU

Reserved

0x50
THCV231 Main-Link
Control Register

・・・

・・・

0xFC

THCV236 Main-Link
Control Register

0x7C
Reserved

・・・

・・・

Slave
Device#7

0x2C
Reserved

・・・

・・・

Slave
Device#02-wireserialI/F

Sub-Link Master
Control Register

Reserved

MSSEL = 0

Figure 16. Sub-Link Master/Slave device Register Address configuration

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THCV231_THCV236_Rev.3.12_E
Table 32. Sub-Link Master Control Register
Address
(Hex)

Bit#

R/W

Default
(Hex)

0x00

7:3

R

0x00

0x01

Register Name

Note

Reserved

2

R

0

INT

1

R

1

LOCKN

0

R

1

HTPDN

7:1

R

0x00

0

RW

0

SFTRST

7RW

02WIRE_ACS_END_INT

6

RW

0

LOCKN_INT

5

RW

0

HTPDN_INT

4R

0SLAVESIDE_INT

0x02

0x03

Description

3

R

0

GPIO_INT

2RW

0COMERR_INT

1

RW

0

2WIRE_TIMEOUT_INT

0

RW

0

SLINK_TIMEOUT_INT

7

R

(*2)

2WIRE_ACS_END_INT_ENABLE

6

RW

0

LOCKN_INT_ENABLE

5

RW

0

HTPDN_INT_ENABLE

4

RW

0

SLAVESIDE_INT_ENABLE

3

RW

0

GPIO_INT_ENABLE

2

RW

0

COMERR_INT_ENABLE

1

RW

0

2WIRE_TIMEOUT_INT_ENABLE

0

RW

0

SLINK_TIMEOUT_INT_ENABLE*1

These registers are always active independent of Interrupt permission register.

*2

When No clock stretching mode, the value is 1 fixed, otherwise 0 fixed

Copyright©2023 THine Electronics, Inc.

-

Interrupt condition
0: Steady state
1: Interrupt occurred(INT output =L)
V-by-One® HS lock status
0: Locked (LOCKN=L)
1: Unlocked
V-by-One® HS plug status
0: Connected (HTPDN=L)
1: Not connected or Rx inactive
Reserved
Sub-Link soft reset
Write 1: Sub-Link reset
Automatically cleared into 0 after reset action. 0 is always read.
Cause of interrupt access completion to register of Sub-Link Slave or
Remote side 2-wire serial Slave device
0: Access incomplete
1: Access complete
Any write action: clear this bit into 0
Cause of interrupt LOCKN
0: No change on lock status ever
1: Lock status has once changed
Any write action: clear this bit into 0
Cause of interrupt HTPDN
0: No change on plug status ever
1: Plug status has once changed
Any write action: clear this bit into 0
Cause of interrupt Sub-Link Slave side
0: No interrupt at Sub-Link Slave ever
1: Interrupted at Sub-Link Slave once
This bit is cleared when cause of interrupt register at Sub-Link Slave(0x82) is cleared.
Cause of interrupt Sub-Link Master GPIO
0: No change in Master GPIO inputs ever
1: Master GPIO inputs have once changed.
This bit is cleared when GPIOn_INPUT_MONITOR (n=4~0) register(0x41) is read.
Cause of interrupt Sub-Link communication Error
0: No communication error on Sub-Link ever
1: Communication error on Sub-Link once happened
Any write action: clear this bit into 0
Cause of interrupt 2-wire serial time out
0: 2-wire serial access in time ever
1: 2-wire serial access has once had time out
Any write action: clear this bit into 0
Cause of interrupt Sub-Link time out
0: Sub-Link access in time ever
1: Sub-Link has once had time out
Any write action: clear this bit into 0
0: "2WIRE_ACS_END_INT" is blocked to take interrupt action
1: "2WIRE_ACS_END_INT" is allowed to take action on INT output
0: "LOCKN_INT" is blocked to take interrupt action
1: "LOCKN_INT" is allowed to take action on INT output
0: "HTPDN_INT" is blocked to take interrupt action
1: "HTPDN_INT" is allowed to take action on INT output
0: "SLAVESIDE_INT" is blocked to take interrupt action
1: "SLAVESIDE_INT" is allowed to take action on INT output
0: "GPIO_INT" is blocked to take interrupt action
1: "GPIO_INT" is allowed to take action on INT output
0: "COMERR_INT" is blocked to take interrupt action
1: "COMERR_INT" is allowed to take action on INT output
0: "2WIRE_TIMEOUT_INT" is blocked to take interrupt action
1: "2WIRE_TIMEOUT_INT" is allowed to take action on INT output
0: "SLINK_TIMEOUT_INT" is blocked to take interrupt action
1: "SLINK_TIMEOUT_INT" is allowed to take action on INT output

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-

-

(*1)

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THCV231_THCV236_Rev.3.12_E
Address
(Hex)
0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C
0x0D
0x0E

0x0F

0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20

0x21

0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D-0x3F

*3

Bit#

R/W

Default(Hex)

Register Name

Description

Note

0: Value in "2WIRE_DEV_ADDR_0" is inactive
7RW
0
2WIRE_DEV_ADDR_0_ENABLE
1: Value in "2WIRE_DEV_ADDR_0" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_0
Remote side 2-wire serial Slave Device Address #0
0: Value in "2WIRE_DEV_ADDR_1" is inactive
7RW
0
2WIRE_DEV_ADDR_1_ENABLE
1: Value in "2WIRE_DEV_ADDR_1" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_1
Remote side 2-wire serial Slave Device Address #1
0: Value in "2WIRE_DEV_ADDR_2" is inactive
7RW
0
2WIRE_DEV_ADDR_2_ENABLE
1: Value in "2WIRE_DEV_ADDR_2" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_2
Remote side 2-wire serial Slave Device Address #2
0: Value in "2WIRE_DEV_ADDR_3" is inactive
7RW
0
2WIRE_DEV_ADDR_3_ENABLE
1: Value in "2WIRE_DEV_ADDR_3" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_3
Remote side 2-wire serial Slave Device Address #3
0: Value in "2WIRE_DEV_ADDR_4" is inactive
7RW
0
2WIRE_DEV_ADDR_4_ENABLE
1: Value in "2WIRE_DEV_ADDR_4" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_4
Remote side 2-wire serial Slave Device Address #4
0: Value in "2WIRE_DEV_ADDR_5" is inactive
7RW
0
2WIRE_DEV_ADDR_5_ENABLE
1: Value in "2WIRE_DEV_ADDR_5" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_5
Remote side 2-wire serial Slave Device Address #5
0: Value in "2WIRE_DEV_ADDR_6" is inactive
7RW
0
2WIRE_DEV_ADDR_6_ENABLE
1: Value in "2WIRE_DEV_ADDR_6" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_6
Remote side 2-wire serial Slave Device Address #6
0: Value in "2WIRE_DEV_ADDR_7" is inactive
7RW
0
2WIRE_DEV_ADDR_7_ENABLE
1: Value in "2WIRE_DEV_ADDR_7" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_7
Remote side 2-wire serial Slave Device Address #7
7:0
RW
0x00
Reserved
7:0
R
0x00
Reserved
7:2
R
0x00
Reserved
1:0
RW
0x0
Reserved. Must be 0
7:2
R
0x00
Reserved
00: clock stretching mode
01: No clock stretching mode
1:0
RW
0x1
2WIRE_MODE
10: Reserved (Forbidden)
11: Reserved (Forbidden)
7:0
RW
0x00
2WIRE_DATA0
2-wire serial I/F Write/Read Data #0
7:0
RW
0x00
2WIRE_DATA1
2-wire serial I/F Write/Read Data #1
7:0
RW
0x00
2WIRE_DATA2
2-wire serial I/F Write/Read Data #2
7:0
RW
0x00
2WIRE_DATA3
2-wire serial I/F Write/Read Data #3
7:0
RW
0x00
2WIRE_DATA4
2-wire serial I/F Write/Read Data #4
7:0
RW
0x00
2WIRE_DATA5
2-wire serial I/F Write/Read Data #5
7:0
RW
0x00
2WIRE_DATA6
2-wire serial I/F Write/Read Data #6
7:0
RW
0x00
2WIRE_DATA7
2-wire serial I/F Write/Read Data #7
7:0
RW
0x00
2WIRE_DATA8
2-wire serial I/F Write/Read Data #8
7:0
RW
0x00
2WIRE_DATA92-wire serial I/F Write/Read Data #9
7:0
RW
0x00
2WIRE_DATA10
2-wire serial I/F Write/Read Data #10
7:0
RW
0x00
2WIRE_DATA11
2-wire serial I/F Write/Read Data #11
7:0
RW
0x00
2WIRE_DATA12
2-wire serial I/F Write/Read Data #12
7:0
RW
0x00
2WIRE_DATA13
2-wire serial I/F Write/Read Data #13
7:0
RW
0x00
2WIRE_DATA14
2-wire serial I/F Write/Read Data #14
7:0
RW
0x00
2WIRE_DATA15
2-wire serial I/F Write/Read Data #15
Remote side 2-wire Slave device's Register Address bit width select7RW
02WIRE_ADR_SEL
0: 8bit Register Address
1: 16bit Register Address
6:0
RW
0x00
2WIRE_TARGET_DEV_ADR
2-wire serial I/F Access Target Device Address setting
7:4
R
0x0
Reserved
2-wire serial I/F Write Request Byte Number for both 8bit and 16bit Register
3:0
RW
0x0
WR_REQ_BYTE
Address device. Byte Number = register value + 1 (e.g. 0x2 for 3byte burst)
7:4
R
0x0
Reserved
2-wire serial I/F Read Request Byte Number for both 8bit and 16bit Register
3:0
RW
0x0
RD_REQ_BYTE
Address device. Byte Number = register value + 1 (e.g. 0x2 for 3byte burst)
2-wire serial I/F Write Start Register Address for 8bit Register Address
7:0
RW
0x00
WR_START_ADR_8B
device2-wire serial I/F Read Start Register Address for 8bit Register Address
7:0
RW
0x00
RD_START_ADR_8B
device7:1
R
0x00
Reserved
0
RW
0
WR_START_8B
2-wire serial I/F Write Access Start Trigger for 8bit Register Address device
7:1
R
0x00
Reserved
0
RW
0
RD_START_8B
2-wire serial I/F Read Access Start Trigger for 8bit Register Address device
2-wire serial I/F Write Start Register Address(Low-order bits = [7:0]) for 16bit
7:0
RW
0x00
WR_START_ADR_16B_0
Register Address device
2-wire serial I/F Write Start Register Address(High-order bits = [15:8]) for
7:0
RW
0x00
WR_START_ADR_16B_1
16bit Register Address device
2-wire serial I/F Read Start Register Address(Low-order bits = [7:0]) for 16bit
7:0
RW
0x00
RD_START_ADR_16B_0
Register Address device
2-wire serial I/F Read Start Register Address(High-order bits = [15:8]) for
7:0
RW
0x00
RD_START_ADR_16B_1
16bit Register Address device
7:1
R
0x00
Reserved
0
RW
0
WT_START_16B
2-wire serial I/F Write Access Start Trigger for 16bit Register Address device
7:1
R
0x00
Reserved
0
RW
0
RD_START_16B
2-wire serial I/F Read Access Start Trigger for 16bit Register Address device
7:0
R
0x00
Reserved
Assignment of 2-wire serial slave device address connected to Sub-Link Slave outside

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THCV231_THCV236_Rev.3.12_E
Table 33. Sub-Link Slave Control Register
Address
(Hex)
0x80

0x81

Bit#

R/W

7:0
7:1

R
R

Defaul
t
(Hex)
0x00
0x00

0

RW

0

7:6

R

0x0

5

RW

0

2WIRE_RST_END_INT

4

RW

0

2WIRE_NACK_INT

3

R

0

GPIO_INT

2RW

0COMERR_INT

1

RW

0

2WIRE_TIMEOUT_INTSLINK_TIMEOUT_INT

Name

2WIRE_RST

0x82

0x83

0x84
-0x8B
0x8C

0x8D

0x8E
0x8F
0x90
-0xBF
*1

0

RW

0

7:6

R

0x0

5

RW

0

2WIRE_RST_ENABLED_INT_ENABL
E

4

RW

0

2WIRE_NACK_INT_ENABLE

3

RW

0

GPIO_INT_ENABLE

2

RW

0

COMERR_INT_ENABLE

1

RW

0

2WIRE_TIMEOUT_INT_ENABLE

0

RW

0

SLINK_TIMEOUT_INT_ENABLE

7:0

R

0x00

7

R

0

6:0

RW

0x2D

7

R

0

6:0

RW

0x37

7:2
1:0
7:2
1:0

R
RW
R
RW

0x00
0x0
0x00
0x1

7:0

R

0x00

Not
e

Description
Reserved
Reserved
2-wire serial I/F reset
Write 1: 16 pulse SCL signal is sent to 2-wire serial slave device
connected to Sub-Link Slave.
This bit is a remedy against SDA=L, 2-wire serial stuck condition.
Automatically cleared into 0 after reset action.0 is always read.
Reserved
Cause of interrupt 2-wire serial reset done
0: Normal operation
1: 2-wire serial reset signal has all finished
Any write action: clear this bit into 0
Cause of interrupt 2-wire serial Slave NACK
0: No NACK from remote side 2-wire serial slave ever
1: NACK from remote side 2-wire serial slave once comeAny write action: clear this bit into 0
Cause of interrupt Sub-Link Slave GPIO
0: No change in Slave GPIO inputs ever
1: Slave GPIO inputs have once changed.
This bit is cleared when GPIOn_INPUT_MONITOR (n=4,3) register(0xC1) is read.
Cause of interrupt Sub-Link communication Error
0: No communication error on Sub-Link ever
1: Communication error on Sub-Link once happened
Any write action: clear this bit into 0
Cause of interrupt 2-wire serial time out
0: 2-wire serial access in time ever
1: 2-wire serial access has once had time out
Any write action: clear this bit into 0
Cause of interrupt Sub-Link time out0: Sub-Link access in time ever
1: Sub-Link has once had time out
Any write action: clear this bit into 0
Reserved
0: "2WIRE_RST_END_INT" is blocked to be reported to Master Side.
1: "2WIRE_RST_END_INT" is allowed to be reported to Master Side.
0: "2WIRE_NACK_INT" is blocked to be reported to Master Side.
1: "2WIRE_NACK_INT" is allowed to be reported to Master Side.
0: "GPIO_INT" is blocked to be reported to Master Side.
1: "GPIO_INT" is allowed to be reported to Master Side.
0: "COMERR_INT" is blocked to be reported to Master Side.
1: "COMERR_INT" is allowed to be reported to Master Side.
0: "2WIRE_TIMEOUT_INT" is blocked to be reported to Master Side.
1: "2WIRE_TIMEOUT_INT" is allowed to be reported to Master Side.
0: "SLINK_TIMEOUT_INT" is blocked to be reported to Master Side.
1: "SLINK_TIMEOUT_INT" is allowed to be reported to Master Side.
Reserved

SCL_W_H

SCL_W_L

-

-

-

-

-

-

-

-

(*1)

-

Reserved
SCL High width [tHIGH] setting. Output SCL High width is defined as
below.
((SCL_W_H + 1) * 8 + 8) * tOSC
Reserved
SCL Low width [tLOW ] setting. Output SCL Low width is defined as
below.
((SCL_W_L + 1) * 8 + 8) * tOSC
Reserved
Reserved. Must be 0
Reserved
Reserved
Reserved-

Interrupt signal from Sub-Link Slave is reported to Sub-Link Master as Cause of interrupt Sub-Link Slave Side (0x02 bit4 SLAVESIDE_INT).

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THCV231_THCV236_Rev.3.12_E
Table 34. THCV231 GPIO Control Register Map
Address (Hex)Sub-Link Slave
0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7-0xCF
*1
*2
*3
*4

Bit#

R/W

7:5

R

Defaul
t
(Hex)
0x0

4

RW

1

GPIO4_TYPE

3

RW

1

GPIO3_TYPE

2:0
7:5
4
3
2:0
7:5
4
3
2:0
7:5

R
R
R
R
R
R
RW
RW
RW
R

0x0
0x0
0
0
0x0
0x0
0
0
0x0
0x0

4:3

RW

0x0

2:0
7:5

RW
R

0x7
0x0

4

RW

1

GPIO4_FILT_ENABLE

3

RW

1

GPIO3_FILT_ENABLE

2:0
7:5

RW
R

0x7
0x0

4

RW

1

GPIO4_INT_ENABLE

3

RW

1

GPIO3_INT_ENABLE

2:0
7:5

RW
R

0x7
0x0

4

RW

0

GPIO4_OUTBUF_SEL

3

RW

0

GPIO3_OUTBUF_SEL

Name

GPIO4_INPUT_MONITOR
GPIO3_INPUT_MONITOR

GPIO4_OUTGPIO3_OUT

GPIO_IO_SEL

Description
Reserved
GPIO4 type select0: Programmable GPIO
1: Through GPIO
GPIO3 type select0: Programmable GPIO
1: Through GPIO
Reserved
Reserved
GPIO4 input value
GPIO3 input value
Reserved
Reserved
GPIO4 output value setting
GPIO3 output value setting
Reserved
Reserved
GPIO input/output direction setting
See Table 28, Table 29 and Table 30
Reserved
Reserved
GPIO4 input filter enable
0: Disable
1: Enable
GPIO3 input filter enable
0: Disable
1: Enable
Reserved
Reserved
GPIO4 interrupt enable
0: Disable
1: Enable
GPIO3 interrupt enable
0: Disable
1: Enable
Reserved
Reserved
GPIO4 output buffer select0: GPIO4 is open-drain output
1: GPIO4 is push pull output
GPIO3 output buffer select0: GPIO3 is open-drain output
1: GPIO3 is push pull output
Reserved
Reserved

Note
-

(*1)

(*2)
-

(*3)

-

(*4)

-

-

2:0
RW
0x0
7:0
R
0x00
Active only when GPIO is set as input port.
Active only when GPIO type is set as "Programmable GPIO" and set as output port.
Filter eliminates input glitch shorter than tOSC/2.
GPIO input transition is counted as GPIO_INT(0x82 bit3).

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THCV231_THCV236_Rev.3.12_E
Table 35. THCV231 Main-Link Control Register Map
Address (Hex)Sub-Link Slave
0xD0

0xD1

0xD2
0xD3

0xD4
0xD5-0xEC
0xED
0xEE
0xEF
0xF0

0xF1
-0xF5
0xF6

Bit#

R/W

Default
(Hex)

7

RW

1

MAINMODE

6

RW

1

HFSEL

5

RW

0

COL1

4

RW

1

COL0

3

RW

0

PRE

2:1

RW

0x2

CMLDRV

0
7:6

RW
R

0
0x0

5

RW

0

SSEN

4:0

RW

0x05

SPREAD

7:4
3:0
7:2

R
RW
R

0x0
0xD
0x00

FMOD

1

RW

0

BET

0

RW

0

BET_SEL

7
6:0
7:0
7:3
2:0
7:1
0
7:0
7:2
1

R
RW
RW
R
RW
R
RW
R
R
RW

0
0x3E
0x00
0x00
0x1
0x00
1
0x00
0x00
0

0

RW

0

7:0

R

0x00

Name

PLL_SET_EN

7:6
R
0x0
5:0
RW
0xXX
PLL_SET0
0xF7
7:4
R
0x0
3:0
RW
0x0
0xF8
7:0
RW
0xXX
PLL_SET1
0xF9-0xFB
7:0
RW
0x00
0xFC
7:6
R
0x0
5:0
RW
0xXX
PLL_SET2
0xFD-0xFF
7:0
RW
0xXX
*1
See Table 4*2
SSEN=1 and SPREAD=0 setting is forbidden*3
See Table 8, Table 17

Copyright©2023 THine Electronics, Inc.

Description

Note

MAINMODE setting
0: V-by-One® HS Mode
1: Sync Free Mode
HFSEL setting
0: High Frequency Mode Disable
1: High Frequency Mode Enable
COL1 setting
Data Width Setting. See Table 16.
COL0 setting
Data Width Setting. See Table 16.
PRE setting
0: Pre-Emphasis Disable
1: Pre-Emphasis Enable
CMLDRV setting
00: 400mV diff p-p
01: 600mV diff p-p
10: 800mV diff p-p
11: Reserved (Forbidden)
Reserved
Reserved
SSEN setting
0: SSCG Disable
1: SSCG Enable
SSCG modulation depth setting
Spread depth = ±SPREAD x 0.1% (Center Spread)
Reserved
SSCG Modulation Frequency Setting
Reserved
Field BET Mode Enable setting
0: Normal Mode
1: Field BET Operation
Main-Link / Sub-Link Field BET Mode select0: Main-Link Field BET Mode
1: Sub-Link Field BET Mode
Reserved
Reserved. Must be default setting.
Reserved
Reserved
Reserved
Reserved
Reserved. Must be 1
Reserved
Reserved
Reserved. Must be 0
SSCG PLL setting register Enable
1: Enable
0: Disable

-

-

(*1)

-

(*2)

-

-

Reserved-

Reserved-

SSCG PLL setting(*3)

Reserved
Reserved. Must be default setting.
SSCG PLL setting
Reserved. Must be default setting.
Reserved
SSCG PLL setting
Reserved. Must be default setting.

-

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THCV231_THCV236_Rev.3.12_E
Table 36. THCV236 GPIO Control Register Map
Address (Hex)Sub-Link
Master
0x40

0x41

0x42

0x43

0x44

0x45

*1
*2
*3
*4
*5

Bit#

R/W

Default
(Hex)

7:5

R

0x0

4

RW

1

GPIO4_TYPE

3

RW

1

GPIO3_TYPE

2

R

0

GPIO2_TYPE

1

R

0

GPIO1_TYPE

GPIO0_TYPE

Name

0

R

0

7:5
4
3
2
1
0
7:5
4
3
2
1
0
7:5
4
3
2:0
7:5

R
R
R
R
R
R
R
RW
RW
RW
RW
RW
R
RW
RW
RW
R

0x0
0
0
0
0
0
0x0
0
0
0
0
0
0x0

4

RW

1

GPIO4_FILT_ENABLE

3

RW

1

GPIO3_FILT_ENABLE

2

RW

1

GPIO2_FILT_ENABLE

1

RW

1

GPIO1_FILT_ENABLE

0

RW

1

GPIO0_FILT_ENABLE

7:5

R

0x0

4

RW

1

GPIO4_INT_ENABLE

3

RW

1

GPIO3_INT_ENABLE

2

RW

1

GPIO2_INT_ENABLE

1

RW

1

GPIO1_INT_ENABLE

0

RW

1

GPIO0_INT_ENABLE

(*3)
(*3)

Description

GPIO4_INPUT_MONITOR
GPIO3_INPUT_MONITOR
GPIO2_INPUT_MONITOR
GPIO1_INPUT_MONITOR
GPIO0_INPUT_MONITOR
GPIO4_OUTGPIO3_OUTGPIO2_OUTGPIO1_OUT
GPIO0_OUT

GPIO_IO_SEL

0x7
0x0

Note

Reserved
GPIO4 type select0: Programmable GPIO
1: Through GPIO
GPIO3 type select0: Programmable GPIO
1: Through GPIO
GPIO2 type select0: Programmable GPIO
0 Fix
GPIO1 type select0: Programmable GPIO0 Fix
GPIO0 type select0: Programmable GPIO
0 Fix
Reserved
GPIO4 input value
GPIO3 input value
GPIO2 input value
GPIO1 input value
GPIO0 input value
Reserved
GPIO4 output value setting
GPIO3 output value setting
GPIO2 output value setting
GPIO1 output value setting
GPIO0 output value setting
Reserved

-

-

-

-

-

(*1)

-

(*2)

-

GPIO input/output direction setting
See Table 28, Table 29 and Table 30-

Reserved
GPIO4 input filter enable
0: Disable
1: Enable
GPIO3 input filter enable
0: Disable
1: Enable
GPIO2 input filter enable
0: Disable
1: Enable
GPIO1 input filter enable
0: Disable
1: Enable
GPIO0 input filter enable
0: Disable
1: Enable
Reserved
GPIO4 interrupt enable
0: Disable
1: Enable
GPIO3 interrupt enable
0: Disable
1: Enable
GPIO2 interrupt enable
0: Disable
1: Enable
GPIO1 interrupt enable
0: Disable
1: Enable
GPIO0 interrupt enable
0: Disable
1: Enable

-

(*4)

-

(*5)

Active only when GPIO is set as input port.
Active only when GPIO type is set as "Programmable GPIO" and set as output port.
Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0 , RXDEFSEL=0 → default value is 1.
Filter eliminates input glitch shorter than tOSC/2.
GPIO input transition is counted as GPIO_INT(0x02 bit3).

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THCV231_THCV236_Rev.3.12_E

Address (Hex)Sub-Link
Master

Bit#

R/W

Default
(Hex)

0x46

7:5

R

0x0

4

RW

0

GPIO4_OUTBUF_SEL

3

RW

0

GPIO3_OUTBUF_SEL

2

RW

0

GPIO2_OUTBUF_SEL

1

RW

0

GPIO1_OUTBUF_SEL

0

RW

0

GPIO0_OUTBUF_SEL

7:0

R

0x00

0x47
-0x4F

Copyright©2023 THine Electronics, Inc.

Name

Description

Note

Reserved
GPIO4 output buffer select0: GPIO4 is open-drain output
1: GPIO4 is push pull output
GPIO3 output buffer select0: GPIO3 is open-drain output
1: GPIO3 is push pull output
GPIO2 output buffer select0: GPIO2 is open-drain output
1: GPIO2 is push pull output
GPIO1 output buffer select0: GPIO1 is open-drain output
1: GPIO1 is push pull output
GPIO0 output buffer select0: GPIO0 is open-drain output
1: GPIO0 is push pull output

-

-

-

-

-

Reserved

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THCV231_THCV236_Rev.3.12_E
Table 37. THCV236 Main-Link Control Register Map
Address (Hex)Sub-Link
Master
0x50

0x51

0x52
0x53

0x54
0x55
-0x6C
0x6D

0x6E
0x6F
0x70

0x71
-0x75
0x76
0x77
0x78
0x79
-0x7B
0x7C
0x7D
-0x7F
*1
*2
*3
*4

Bit#

R/W

Default
(Hex)

7

RW

(*1)

MAINMODE

6

RW

(*1)

HFSEL

5

RW

0

COL1

4

RW

(*1)

COL0

3
2:1

RW
RW

0
0x0

Name

Description

Note

0

RW

0

7:6

R

0x0

5

RW

0

SSEN

4:0

RW

0x05

SPREAD

7:4
3:0
7:2
1

R
RW
R
RW

0x0
0xD
0x00
0

0

RW

0

7
6:0

R
RW

0
0x3E

MAINMODE setting
0: V-by-One® HS Mode
1: Sync Free Mode
HFSEL setting
0: High Frequency Mode Disable
1: High Frequency Mode Enable
COL1 setting
when MAINMODE =0
0: Color Space Converter Disable
1: Color Space Converter Enable
when MAINMODE =1
Data Width Setting. See Table 16.
COL0 setting
Data Width Setting. See Table 16.
Reserved
Reserved
TTLDRV setting
0: Weak Drive Strength
1: Normal Drive Strength
Reserved
SSEN setting
0: SSCG Disable
1: SSCG Enable
SSCG modulation depth setting
Spread depth = ±SPREAD x 0.1% (Center Spread)
Reserved
SSCG Modulation Frequency Setting
Reserved
Reserved
Main-Link / Sub-Link Field BET Mode select0: Main-Link Field BET Mode
1: Sub-Link Field BET Mode
Reserved
Reserved. Must be default setting.

7:0

RW

0x0

Reserved

7:3

R

0x00

2

RW

0

OUTSEL_ENABLE

1:0

RW

0x1

OUTSEL_SETTING

7:1
0
7:0
7:2
1

R
RW
R
R
RW

0x00
1
0x00
0x00
0

0

RW

0

7:0

R

0x00

Reserved

7:6
5:0
7:4
3:0
7:0

R
RW
R
RW
RW

0x0
0x00
0x0
0x0
0xXX

Reserved

7:0

R

7:6
5:0
7:0

TTLDRVFMOD

BET_SEL

PLL_SET_EN

-

-

-

-

(*2)

-

Reserved
Permanent Clock Output Enable setting
0: Permanent Clock Output Disable
1: Permanent Clock Output Enable
Permanent Clock Frequency setting
00: 80MHz (Clock Period : tOSC)
01: 40MHz (Clock Period : tOSC/2)
10: 20MHz (Clock Period : tOSC/4)
11: 10MHz (Clock Period : tOSC/8)
Reserved
Reserved. Must be 1
Reserved
Reserved
Reserved. Must be 0
SSCG PLL setting register Enable
1: Enable
0: Disable

-

(*3)

-

PLL_SET0SSCG PLL setting

(*4)

-

PLL_SET1

Reserved
Reserved. Must be default setting.
SSCG PLL setting

(*4)

0x00

Reserved. Must be default setting.

-

R
RW

0x0
0xXX

Reserved

R

0xXX

PLL_SET2-

SSCG PLL setting(*4)

Reserved. Must be default setting.

-Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0 , RXDEFSEL=0 → default value is 1.
SSEN=1 and SPREAD=0 setting is forbidden
Described value is typical value. It has variation in the range from min spec value to max spec value of tOSC.
See Table 8, Table 17

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THCV231_THCV236_Rev.3.12_E

Absolute Maximum Ratings
Table 38. Absolute Maximum Ratings
Parameter
Supply Voltage(VDD,AVDD)LVCMOS Input Voltage
LVCMOS Output Voltage
LVCMOS Bi-directional buffer Input Voltage
LVCMOS Bi-directional buffer Output Voltage
Open-Drain Output Voltage
CML Receiver Input Voltage
CML Transmitter Output Voltage
CML Bi-directional buffer Input Voltage
CML Bi-directional buffer Output Voltage
Output Current
Storage temperature
Junction temperature
Reflow Peak Temperature/Time
Maximum Power Dissipation THCV231@+25°C
Maximum Power Dissipation THCV236@+25°C

Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-50
-55
-

Typ
-

Max
4.0
VDD+0.3
VDD+0.3
VDD+0.3
VDD+0.3
4.0
CAPINA+0.3
CAPINA+0.3
VDD+0.3
VDD+0.350125
125
260/10
3.2
4.0

Unit
V
V
V
V
V
V
V
V
V
V
mA
°C
°C
°C/sec
W
W

Typ
-

Max
3.6
105

Unit
V
°C

Recommended Operating Conditions
Table 39. Recommended Operating Condition
Parameter
Supply Voltage(VDD,AVDD)
Operating Ambient Temperature

Min
1.7
-40

Electrical Specification
LVCMOS DC Specification
Table 40. LVCMOS DC Specification
Symbol
VIH

Parameter
High Level Input Voltage

Pin Type
I
IL,B

VIL

Low Level Input Voltage

I
IL,B

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

O,B
O,B
BO

IIH
IIL
IOZH
IOZL

Input Leak Current High
Input Leak Current Low
Output Leak Current Highin Hi-Z State
Output Leak Current Low in
Hi-Z State

Copyright©2023 THine Electronics, Inc.

I,IL
I,IL

Condition
VDD=1.7-2.0V
VDD=2.0-3.0V
VDD=3.0-3.6V
VDD=1.7-3.6V
VDD=1.7-2.0V
VDD=2.0-3.0V
VDD=3.0-3.6V
VDD=1.7-3.6V
VDD=1.7-3.6V
IOH=-4mA
VDD=1.7-3.6V
IOL=4mA
VDD=1.7-3.6V
IOL=2mA
VIN=VDD
VIN=0VMin
0.65×VDD
0.70×VDD
2.0
0.70×VDD
0
0
0
0

Typ
-

Max
VDD
VDD
VDD
VDD
0.35×VDD
0.30×VDD
0.8
0.30×VDD

Unit
V
V
V
V
V
V
V
V

VDD-0.45

-

VDD

V

0

-

0.45

V

0

-

0.2

V

-10

-

10
-

uA
uA

O,B,BO

VIN=VDD

-

-

10

uA

O,B,BO

VIN=0V

-10

-

10

uA

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THCV231_THCV236_Rev.3.12_E
CML DC Specification
Table 41. CML DC Specification(THCV231)
SymbolParameterVTOD

CML Differential Output VoltagePRE

CML Pre-emphasis LevelVTOC

CML Common Mode
Output Voltage

ITOH
ITOS

CML Output Leak Current HighCML Output Short Current

Condition(*1)
CMLDRV[1:0]=00
CMLDRV[1:0]=01
CMLDRV[1:0]=10
PRE=0
PRE=1,CMLDRV[1:0]=00
PRE=1,CMLDRV[1:0]=01
PRE=0
PRE=1,CMLDRV[1:0]=00
PRE=1,CMLDRV[1:0]=01
PDN=0,TXP/N=CAPINA
PDN=0,TXP/N=0V

Min
Typ
Max
133
200
267
200
300
400
300
400
500
0
100
50
CAPINA-VTOD
CAPINA-2×VTOD
CAPINA-1.5×VTOD
-30
30
-80
-

Unit
mV
mV
mV
%
%
%
mV
mV
mV
uA
mA

*1 PRE and CMLDRV[1:0] are registers.

Table 42. CML DC Specification(THCV236)
Symbol
VRTH
VRTL
IRIH
IRIL
IRRIH
IRRIL
RRIN

Parameter
CML
Differential
Input
High
Threshold
CML
Differential
Input
High
Threshold
CML Input Leak Current HighCML Input Leak Current Low
CML Input Current HighCML Input Current Low
CML Differential Input ResistanceCondition
-

Min

Typ

Max

Unit

-

-

50

mV

-50

-

-

mV

-10
-10
-6
80

100

10
10
2
120

uA
uA
mA
mA
Ω

Condition

Min

Typ

Max

Unit

-

-

-

150

mV

-

-150

-

-

mV

xCMP/N=VDD(x=T,R)

-10

-

10

uA

xCMP/N=0V(x=T,R)

-10

-

10

uA

Transmitter State
Receiver State

37.5
150

50
200

62.5
250

Ω
Ω

RDIFF=400Ω

300

-

660

mV

-

-

VDD0.3

-

V

-10

-

10

uA

PDN0=0,RXP/N=CAPINA
PDN0=0,RXP/N=0V
RXP/N=CAPINA
RXP/N=0V-

CML Bi-Directional DC Specification
Table 43. CML Bi-Directional DC Specification
Symbol
VBTH
VBTL
IBIH
IBIL
RTERM
VBOD
VBOC
IBOZ

Parameter
Bi-Directional Buffer Differential
Input High Threshold
Bi-Directional Buffer Differential
Input Low Threshold
Bi-Directional Buffer
Output Leak Current HighBi-Directional Buffer
Output Leak Current Low
Bi-Directional Buffer
Termination Resistance
Bi-Directional Buffer
Differential Output Voltage
Bi-Directional Buffer
Common Output Voltage
Bi-Directional Buffer TRI-STATE
Current

Copyright©2023 THine Electronics, Inc.

PDN=0(THCV231)
PDN1=0(THCV236)

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Supply Current
Table 44. Supply Current(THCV231)
SymbolITCCWParameter
Transmitter Supply Current

ITCCS

Transmitter Power Down Supply
Current

Condition(*1)
PDN=1, HFSEL=1
PDN = 0All Inputs = Fixed 0 or 1
Typical value is under 25 °C

Min
-

Typ
-

Max
115

Unit
mA

-

2.5

20

mA

Min

Typ

Max

Unit

-

-

220

mA

-

2.5

20

mA

*1 HFSEL is a register.

Table 45. Supply Current(THCV236)
SymbolParameter

IRCCW

Receiver Supply Current

IRCCS

Receiver Power Down Supply
Current

Condition
Cload=8pF,
PDN0=1,PDN1=1,HFSEL=1
PDN0 = 0 and PDN1 =0
All Inputs = Fixed 0 or 1
Typical value is under 25 °C

Switching Characteristics
Table 46. Switching Characteristics (THCV231)
Symbol
tTBIT
tTRF
tTCIP
tTCH
tTCL

Parameter
Unit Interval
CML Output Rise and Fall Time
(20%-80%)
CLKIN Period
CLKIN High Time
CLKIN Low Time

tTS
tTH
tTPD

Data Input Setup to CLKIN
Data Input Hold to CLKIN
Power On to PDN High DelaytTCD

Input Clock to Output Data
Delay

tTPLL0tTPLL1
tTNP0
tTNP1

PDN High to CML Output Delay
PDN Low to CML Output HighFix Delay
LOCKN High to Training
Pattern Output Delay
LOCKN Low to Data Pattern
Output Delay

Condition(*1)
-

Min
250

Typ
-

Max
1666

Unit
ps

-

50

-

150

ps

See Table 16

1000/Freq.Range[MHz]0.35×tTCI
0.65×tTCI
0.5×tTCIP
P
P
0.35×tTCI
0.65×tTCI
0.5×tTCIP
P
P
2.0
1.0
0
-

ns

56×tTCIP-

65×tTCIP

ns

109×tTCIP-

132×tTCIP

ns

-

-

10

ms

-

-

-

20

ns

-

-

-

10

ms

-

-

-

10

ms

MAINMODE=1,
HFSEL=0
MAINMODE=1,
HFSEL=1
-

ns
ns
ns
ns
ns

*1 MAINMODE and HFSEL are registers.

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THCV231_THCV236_Rev.3.12_E
Table 47. Switching Characteristics (THCV236)
Symbol
tRBIT
tRCP
tRCH
tRCL
tDOUT
tRPD
tRDC
tRHPD0tRHPD1tRPLL0tRPLL1tRLCK0tRLCK1tROSC0tROSC1tROSC2tRStRH

Parameter
Unit Interval
CLKOUT Period
CLKOUT High Time
CLKOUT Low Time
Data Output Period
Power On to PDN0
High Delay
Input Data to Output
Clock Delay
PDN0 High to
HTPDN Low Delay
PDN0 Low to
HTPDN High Delay
Training Pattern
Input to LOCKNLow Delay
PDN0 Low to
LOCKN High Delay
LOCKN Low to Data
Output Delay
LOCKN High to Data
Output Stop Delay
PDN0 High toPermanent Clockoutput Delay
LOCKN Low toPermanent Clockoutput Low Delay
LOCKN High toPermanent Clockoutput Delay
Data Output Setup
to CLKOUT
Data Output Hold to
CLKOUTtTLH

Clock, Data Output
Low to High
Transition TimetTHL

Clock, Data Output
High to Low
Transition Time

Condition
See Table 16
-

Min
Typ
Max
250
1666
1000/Freq.Range[MHz]tRCP/2tRCP/2
tRCP
-

Unit
ps
ns
ns
ns
ns

0

-

-

ns

61×tRCP116×tRCP-

70×tRCP
140×tRCP

ns
ns

-

-

-

10

ms

-

-

-

50

us

-

-

-

10

ms

-

-

-

10

us

-

-

-

5

ms

-

-

-

10

us

OUTSEL=1

-

-

5

ms

OUTSEL=1

-

-

1

ms

OUTSEL=1

-

-

10

us

-

0.45×tRCP-0.65

-

-

ns

-

0.45×tRCP-0.65

-

-

ns

-

-

2.0
3.5
0.8
1.9
2.4
4.4
1.0
2.2

ns
ns
ns
ns
ns
ns
ns
ns

MAINMODE=1,HFSEL=0
MAINMODE=1,HFSEL=1

Clock , TTLDRV=0
Data , TTLDRV=0
Clock , TTLDRV=1
Data , TTLDRV=1
Clock , TTLDRV=0
Data , TTLDRV=0
Clock , TTLDRV=1
Data , TTLDRV=1

Table 48. CML Bi-Directional Switching Characteristics
SymboltBUI
tBRF
tBPJTXtBPJRX

Parameter
Bi-Directional Buffer Unit Interval
Bi-Directional Buffer
Rise and Fall Time(20%-80%)
Bi-Directional Buffer
Transmitter Period Jitter Accuracy(peak to peak)
Bi-Directional Buffer
Receiver Period Jitter Tolerance(peak to peak)

Copyright©2023 THine Electronics, Inc.

Condition
-

Min
80

Typ
100

Max
120

Unit
ns

-

150

-

1000

ps

-

-

-

1

ns

-

8

-

-

ns

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THCV231_THCV236_Rev.3.12_E
Table 49. 2-wire serial slave AC Timing (Sub-Link Master device)
SymbolfSCLtHD;STAtLOWtHIGHtHD;DATtSU;DATtrtf
tSU;STAtSU;STO
tBUF
tSP
tPDS

Parameter
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals(pull-up resistor:2.5kΩ,bus capacitance:400pF)
Setup time for START condition
Setup time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes which must be suppressed by the input
filterRequired wait time from PDN1 high to START condition

Min
0.6
1.3
0.6
20
500
100
-

Typ
9×tOSC-Max
400
300(*1)

Unit
kHz
us
us
us
us
ns
ns
ns
ns

-

-

300

ns

0.6
0.6
1.3

-

-

us
us
us

-

-

50

ns

2

-

-

ms

Max
15.625

Unit
ns

-

us

-

us

*1 Adjust Pull-up resistor and bus capacitance to meet the spec value.

Table 50. 2-wire serial master AC Timing (Sub-Link Slave device)
SymboltOSC

Parameter
Cycle of internal oscillator clock

tHD;STA

Hold time (repeated) START condition

-

tLOW

LOW period of the SCL clock

-

tHIGH

HIGH period of the SCL clock-

tHD;DATtSU;DATtrtf
tSU;STOtBUF

Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals(pull-up resistor:2.5kΩ, bus
capacitance:400pF)
Setup time for STOP condition
Bus free time between a STOP and START
condition

Min
10.417-us

20
31×tOSC
100
-

Typ
12.5
(SCL_W_H × 8 – 3)
× tOSC((SCL_W_L + 1) × 8 + 8)
× tOSC((SCL_W_H + 1) × 8 +8)
× tOSC
9×tOSC-

300(*1)

us
ns
ns
ns
ns

-

-

300

ns

-

386×tOSC

-

ns

4.7

-

-

us

*1 Adjust Pull-up resistor and bus capacitance to meet the spec value.

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THCV231_THCV236_Rev.3.12_E
Table 51. 2-wire serial interface transaction wait time
Symbol
tWSSR
tRSSR
tWRS
tRPW
tRRS
tRPR
tSSEP

Parameter
Write access completion time to Sub-Link Slaveregister
Read access completion time to Sub-Link SlaveregisterWrite start to Remote side Start Condition
generating time
Remote side Stop Condition generating to Writeaccess completion time
Read start to Remote side Start Condition
generating time
Remote side Stop Condition generating to Read
access completion time

Min

Typ

Max

Unit

-

-

110

us

-

-

90

us

-

-

65

us

-

-

300

us

-

-

65

us

-

-

300

us

Depending on characteristics of 2-wireserial slave devices connected to SubLink Slave

Sub-Link Slave External processing timeus

Table 52. Sub-Link control switching characteristics (2-wire serial I/F Mode)
SymboltPVM
tPVS
tTGPIO
tIVM
tIRM
tIVS
tIRS
tPS
tPH

Parameter
Programmable GPIO output at Sub-Link Master data valid
Programmable GPIO output at Sub-Link Slave data valid
Through GPIO delay
Sub-Link Master interrupt valid
Sub-Link Master interrupt reset delay
Sub-Link Slave interrupt valid
2WIRE_MODE=00
Sub-Link Slave interrupt reset delay
2WIRE_MODE=01
Programmable GPIO input data setup
Programmable GPIO input data hold

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Min
10000×(1/fSCL)
0

Typ
-

Max
0
110
280
90
0
300
300
0
-

Unit
us
us
us
us
us
us
us
us
us
us

THine Electronics, Inc.

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THCV231_THCV236_Rev.3.12_E

AC Timing Diagrams and Test Circuits
LVCMOS Input, Output Switching Characteristics

Figure 17. LVCMOS Input Switching Timing Diagrams

Figure 18. LVCMOS Output Switching Timing Diagrams

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THCV231_THCV236_Rev.3.12_E
CML Output Switching Characteristics

Figure 19. CML Output Switching Characteristics

Figure 20. CML Buffer Equivalent Circuit

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THCV231_THCV236_Rev.3.12_E
CML Bi-directional Output Test Circuit

Figure 21. Bi-directional CML VBOD/VBOC Test Circuit

Figure 22. Bi-directional CML Switching Timing Diagram and Test Circuit

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THCV231_THCV236_Rev.3.12_E
Latency Characteristics

Figure 23. THCV231 Latency

Figure 24. THCV236 Latency

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THCV231_THCV236_Rev.3.12_E
Lock and Unlock Sequence

Figure 25. THCV231 Lock/Unlock Sequence

VDD

tRPD

PDN0

HTPDN

tRHPD1

Register(0x00 bit0)tRHPD0CDR
Training
pattern

RXP/N

ALN
Training
pattern

LOCKN

NormalpatterntRLCK0Register(0x00 bit1)

tRPLL1tRLCK1tRPLL0
Pixel Clock

CLKOUT(OUTSEL=0)

Permanent Clock(Internal OSC Clock)(OUTSEL=1)

D11-D0HSYNC,VSYNC

Low

Low

Permanent Clock(Internal OSC Clock)

Invalid
Clock

Valid
Clock

tROSC1
tOSC/N(N=1,2,4,8)(*1)
Low

Low

Pixel ClocktROSC0
CLKOUT

Valid
Clock

Invalid
Clock

Low

Low

tROSC2
InValid
Data

Valid Data

InValid Data

*1 N depends on setting of OUTSEL_SETTING register (0x6D bit1,0). See Register Map (Table 36)

Figure 26. THCV236 Lock/Unlock Sequence

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THCV231_THCV236_Rev.3.12_E
2-wire serial I/F Switching Characteristics

Figure 27. 2-wire serial interface Timing Diagram

Figure 28. Write access completion time to Sub-Link Slave register

Figure 29. Read access completion time to Sub-Link Slave register

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THCV231_THCV236_Rev.3.12_E

Figure 30. Write access completion time to Remote side 2-wire serial slave register

Figure 31. Read access completion time to Remote side 2-wire serial slave register

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THCV231_THCV236_Rev.3.12_E
GPIO Switching Characteristics

Figure 32. Through GPIO delay

Figure 33. Programmable GPIO input timing at Sub-Link Master side

Figure 34. Programmable GPIO output timing at Sub-Link Master side

Figure 35. Programmable GPIO output timing at Sub-Link Slave side

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THCV231_THCV236_Rev.3.12_E

Figure 36. GPIO input and other interrupt event timing at Sub-Link Master side

Figure 37. GPIO input and other interrupt event timing at Sub-Link Slave side
(Clock Stretching Mode)

Read Data of 0xC1 (Data_A)(Sub-Link Slave’s Register)
2-wire serial I/F(Sub-Link Master side)...

Write 1
to 0x26

GPIO4~0 Input port
(Sub-Link Slave side)A

Write to 0x82
(Sub-Link Slave’s Register)Write
to 0x02

A

Write 1
to 0x25

...

A

Write
to 0x02A

Data_A

Internal Interrupt Event(Sub-Link Slave side)

INT of
Sub-Link Master

tIVS

tIRS

tIVS

tIRS

Figure 38. GPIO input and other interrupt event timing at Sub-Link Slave side
(No-Clock Stretching Mode)

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THCV231_THCV236_Rev.3.12_E

PCB Layout Guideline regarding VDD and AVDD for THCV236
When power is supplied from reverse side layer to AVDD, place ferrite bead between through-hole and
AVDD/VDD pins (Good Example1, 2). If it is needed to set ferrite beads on reverse side, set GND-through-hole
between AVDD and VDD, and separate the distance as possible (Example). Don’t set through-holes next to eachother between ferrite beads and AVDD/VDD pins (Bad Example).
Good Example 1

Good Example 2

ExampleBad Example

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THCV231_THCV236_Rev.3.12_E

Package

Unit : mm
Figure 39. 32-pin QFN package physical dimension

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THCV231_THCV236_Rev.3.12_E

Unit : mm
Figure 40. 64-pin QFN package physical dimension

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THCV231_THCV236_Rev.3.12_E

Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

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