NOTICETHCV242 is not recommended for new designs.
THCV242A is recommended.

THCV242_ Rev.2.11_E

THCV242
SerDes receiver with bi-directional transceiver

1.

General Description

3.

2.

Features

MIPI CSI-2 with 1,2 or 4-lane output
MIPI D-PHY supports 80Mbps~1.2Gbps
MIPI Virtual channel supported
Video formats: RAW8/10/12/14/16/20,
YUV422/420, RGB888/666/565, JPEG, Userdefined generic 8-bit
V-by-One® HS 400Mbps~4Gbps x2lane
V-by-One® HS standard version1.5
Video stream switch and copy/distribution
Frame sync remote supply scheme for multiple
camera stream synchronization
Wide range IO voltage from 1.7V to 3.6V
2-wire serial interface 1Mbps bridge function
Remote GPIO/UART control and monitoring
Error detection including CRC and notification
QFN64 9x9mm 0.5mm pitch Exp-pad package






THCV242 is designed to support 1080p60 2Mpixel
uncompressed video data over 15m 100ohm
differential STP or single-end 50ohm Coaxial cablewith 4 in-line connectors between camera andprocessor by V-by-One® HS.
THCV242 supports a MIPI CSI-2. Each CSI-2 datalane can transmit up to 1.2Gbps/lane. Virtual channel
is supported. MIPI 2nd port output supports data
copy and distribution.
One high-speed V-by-One® HS lane can transmit up
to 1080p60fps. The maximum serial data rate is
4Gbps/lane. 2nd input lane supports HDR large
amount of data or camera switch experience.
THCV242 is capable to control and monitor remotecamera module from MPU via GPIO or 1Mbps 2wire serial interface.
Several fault and error detection function including
CRC provides hardware functional safety design.







Block Diagram
MIPI CSI-2
Data Tx 4-lane
Clock Tx 2-port

THCV242

MTX0P

V-by-One® HS
Main-Link
Rx 2-lane

MTX0N
MTX1P

RX0P

Sub-Link 2-lane

CSI2 / Formatter

RX1N

Deserializer

RX1P

MTX1N
MTXCLK0P
MTXCLK0N
MTX2P
MTX2N
MTX3P

CDR

RX0N

MTX3N

RCM0P
MTXCLK1P

RCM0N

MTXCLK1N
Settings
RCM1P
RCM1N

Controls

GPIO
2-wireserial I/F

OSC

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THCV242_ Rev.2.11_E
Contents page
1.

General Description ......................................................................................................................................... 1

2.

Features ........................................................................................................................................................... 1

3.

Block Diagram ................................................................................................................................................ 1

4.

Pin Configuration ............................................................................................................................................ 4

5.

Pin Description ................................................................................................................................................ 5

6.

Functional Description .................................................................................................................................... 6
6.1.

Functional Overview ............................................................................................................................... 6

6.2.

V-by-One® HS ........................................................................................................................................ 6
V-by-One® HS input setting ........................................................................................................... 6
MPRF (Main-Link PRivate Format) ............................................................................................... 7
V-by-One® HS standard format ...................................................................................................... 8
Link Status (HTPDN/LOCKN) ..................................................................................................... 12

6.3.

Local, Remote and Remote Slave Register Programming .................................................................... 14
2-wire serial I/F slave Device ID ................................................................................................... 14
2-wire serial Read/Write access to local Register.......................................................................... 15
2-wire serial I/F Watch Dog Timer ................................................................................................ 16
Sub-Link setting ............................................................................................................................ 17
Sub-Link 2-wire Read/Write access to remote Register ................................................................ 18
6.3.5.1.

Sub-Link 2-wire Set and Trigger mode ................................................................................. 18

6.3.5.2.

Sub-Link 2-wire Pass Through mode .................................................................................... 21

Sub-Link transaction time accuracy Improvement ........................................................................ 24
6.4.

GPIO setting .......................................................................................................................................... 25
Register GPIO ............................................................................................................................... 26
Through GPIO ............................................................................................................................... 27
GPIO as secondary 2-wire port ..................................................................................................... 28

6.5.

MIPI ...................................................................................................................................................... 29
Deserializer and CSI-2 Formatter .................................................................................................. 29
6.5.1.1.

PLL setting ............................................................................................................................ 29

6.5.1.2.

Video stream switch and copy/distribution............................................................................ 31

Header/Packet/Sync Pre-processing .............................................................................................. 32
MIPI output setting ........................................................................................................................ 33
MIPI CSI-2 Virtual Channel .......................................................................................................... 35
Multiple camera synchronization Frame Vsync supply ................................................................ 36
6.6.

Status monitoring, Interrupt and Error Detection .................................................................................. 38
Internal Error / status signal monitoring pin output....................................................................... 38

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THCV242_ Rev.2.11_E
Internal Error / status signal monitoring register ........................................................................... 41
Interrupt monitoring ...................................................................................................................... 42
Register Auto Checksum diagnosis ............................................................................................... 43
6.7.

Power On Sequence............................................................................................................................... 44

6.8.

Lock / Re-Lock Sequence ..................................................................................................................... 45

7.

Absolute Maximum Ratings .......................................................................................................................... 46

8.

Recommended Operating Conditions............................................................................................................ 46

9.

Consumption Current .................................................................................................................................... 47

10.

DC Specifications ...................................................................................................................................... 48

10.1.

CMOS DC Specifications.................................................................................................................. 48

10.2.

CML Receiver DC Specifications ..................................................................................................... 48

10.3.

MIPI Transmitter DC Specifications ................................................................................................. 49

10.4.

CML Bi-directional Buffer DC Specifications .................................................................................. 50

11.

AC Specifications ...................................................................................................................................... 51

11.1.

General AC Specifications .................................................................................................................... 51

11.2.

CML Receiver AC Specifications ......................................................................................................... 51

11.3.

MIPI Transmitter AC Specifications ..................................................................................................... 51

11.4.

CML B-directional Buffer AC Specifications ....................................................................................... 51

11.5.

2-wire serial Slave AC Specifications ................................................................................................... 51

12.

Package...................................................................................................................................................... 52

13.

Notices and Requests................................................................................................................................. 53

MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions.

Copyright©2023 THine Electronics, Inc.

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THCV242_ Rev.2.11_E

VDDIO1

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

INT1

INT0

AIN1

AIN0

SDA

SCL

VDDIO1

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

Pin Configuration

48
ERR0

49

32 EXTSYNC

ERR1

50

31

PDN

30

VDDPLLTHCV242VDDCORE 51
VDDRX

52

29

VDDTX

RX0N

53

28

MTX3P

RX0P

54

27

MTX3N

VSSRX

55

26

MTX1P

RX1N

56

25

MTX1N

RX1P

57

VDDRX

58

23 MTXCLK0N

RSVDL0

59

22

MTX0P

RSVDL0

60

21

MTX0N

VSSRX

61

20

MTX2P

RSVDL0

62

19

MTX2N

RSVDL0

63

VDDRX

64

(TOP VIEW)
65 EXPGND

24 MTXCLK0P●

18 MTXCLK1P

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16
VDDTX

VDDCORE 15

8
RSVDL2RSVDL2 14

7
RSVDL2RSVDT1L2 13

6
RCM1P

RSVDT2H2 12

5
RCM1N

VDDIO2 114
RCM0P

RSVDL2 10

3
RCM0N

Copyright©2023 THine Electronics, Inc.

92
VDDIO2VDDCORE 1

17 MTXCLK1N

RSVDL2

4.

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THCV242_ Rev.2.11_E

5.

Pin Description
Pin Name
RX0P/N
RX1P/N
RCM0P/N
RCM1P/N
MTX0P/N
MTX1P/NMTX2P/N
MTX3P/NMTXCLK0P/N
MTXCLK1P/N
RSVDT1L2
RSVDT2H2

Pin #54, 5357, 564, 3
6, 5
22, 21
26, 2520, 1928, 2724, 2318, 17
13
12

type*
CI
CI
CB
CB
MO
MO
MO
MO
MO
MO
I2
I2

PDN

31

I1

AIN1

37

I1

AIN0

36

I1

SCL
SDA
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

34
35
40
41
42
43
44
45
46
47

B
B
B
B
B
B
B
B
B
B

INT0

38

O

INT1

39

O

Description
V-by-One® HS Input lane0
V-by-One® HS Input lane1
CML Bi-directiona Input/Output (Sub-Link).
CML Bi-directiona Input/Output (Sub-Link).
MIPI differential data outputs lane0
MIPI differential data outputs lane1
MIPI differential data outputs lane2
MIPI differential data outputs lane3
MIPI differential clock outputs lane0
MIPI differential clock outputs lane1
Reserved Pin, Must be tied to ground for normal operation.
Reserved pin. Must be tied to VDDIO2 for normal operation.
Pow er Dow n (User Pow er On Reset control must be reuiquired.)
0: Pow er Dow n Mode
1: Normal Operation
Device Address Setting for 2-w ire Serial Interface[AIN1:AIN0]=00: ID=7'h0B[AIN1:AIN0]=01: ID=7'h34[AIN1:AIN0]=10: ID=7'h77[AIN1:AIN0]=11: ID=7'h65
2-w ire Serial Interface clock line
2-w ire Serial Interface data line
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
Interrupt signal output.
It must be connected w ith a pull-up resistor.
0 : Interrupt occurred
1 : Steady state

ERR0
49
O
Internal Error / status signal monitoring output
ERR1
50
O
Internal Error / status signal monitoring output
EXTSYNC
32
B
External Sync input/output for multiple camera syncronization
RSVDL059, 60, 62, 63
I0
Reserved Pins, Must be tied to ground for normal operation.
RSVDL27, 8, 9, 10, 14
I2
Reserved Pins, Must be tied to ground for normal operation.
VDDIO133, 48P
Pow er Supply for CMOS I/O
VDDIO22,11P
Pow er Supply for Sub-Link I/O
VDDCORE
1,15,51
P
Pow er Supply for Digital Circuit
VDDRX
52,58,64P
Pow er Supply for Analog Circuit
VSSRX
55,61
G
GND for Analog Circuit
VDDTX
16,29
P
Pow er Supply for Analog Circuit
VDDPLL30
P
Pow er Supply for Analog Circuit
EXPGND
65
G
Exposed GND Pad*type symbol ; MO=MIPI Output, CI=CML Input, CB=CML Bi-directional input/output
I0=1.2V CMOS Input, I1=1.8~3.3V VDDIO1 domain CMOS Input, I2=1.8~3.3V VDDIO2 domain CMOS Input
O=1.8~3.3V VDDIO1 domain CMOS Output, B=1.8~3.3V VDDIO1 domain CMOS Bi-directional input/output
P=Pow er, G=Ground

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THCV242_ Rev.2.11_E

6.

Functional Description

6.1.

Functional Overview

THCV242 can receive CML video signal transmitted over 15m length and encode it to MIPI CSI-2 format. With
High Speed CML SerDes, high reliability and robustness encoding scheme and CDR (Clock and Data Recovery)architecture, the THCV242 enables to receive RAW/YUV/RGB/JPEG/Generic8bit data through Main-Link bysingle 100ohm differential pair or 50ohm Coax cable with minimal external components. In addition, THCV242
has Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO signals and also
HTPDN/LOCKN signals for Main-Link through the other 1-pair of CML-Line. The THCV242 system is able towatch remote devices and to control them via 2-wire serial interface or GPIOs. They also can report interrupt
events caused by change of remote device statuses and internal statuses such as CRC error.

6.2.

V-by-One® HS
V-by-One® HS input setting

Setting of V-by-One® HS input format can be configurable by 2-wire access to internal register.

Table 1. V-by-One® HS input format settingAdr0x10 10bit[7:6]

Register Name
R_MLNK_NHSEL0

width R/W
2
R/W

Description
init
2'h2 V-by-One® Main-Link Mode Select (for LINK0)0x10 10[5:4]

R_MLNK_COL0

2

R/W

2'h1

0x10 12[4]

R_RGB565_ON_L0

1

R/W

1'b0

0x10 12[3:0]

R_VX1_LANE_FMT0

4

R/W

4'h0

0x10 14[7:6]

R_VRZ_NHSEL1

2

R/W

2'h2

0x10 14[5:4]

R_VRZ_COL1

2

R/W

2'h1

Copyright©2023 THine Electronics, Inc.

00 : Reserved
01 : Reserved
10 : V-by-One® HS standard mode
11 : Reserved
V-by-One® Main-Link Byte Mode Select (for LINK0)00 : Reserved
01 : 8bit (3Byte mode)
10 : 10bit (4Byte mode)
11 : Reserved
Main-Link Input Data Format Setting2(This register could use only w hen R_VX1_LANE_FMT0=0x1)
0: RGB888
1: RGB565
Main-Link Input Data Format Setting
0: MPRF
1: RGBxxx
2,3,4,5,6: YUV422 (NormalYU1,NormalYU2,NormalYU3,DemuxYU1,DemuxYU2)
7,8,9: RAW8 (NormalR081,NormalR082,DemuxR081)
10,11,12: RAW10 (NormalR101,DemuxR101,DemuxR102)
13,14,15: RAW12 (NormalR121,DemuxR121,DemuxR122)
V-by-One® Main-Link Mode Select (for LINK1)
00 : Reserved
01 : Reserved
10 : V-by-One® HS standard mode
11 : Reserved
V-by-One® Main-Link Byte Mode Select (for LINK1)
00 : Reserved
01 : 8bit (3Byte mode)
10 : 10bit (4Byte mode)
11 : Reserved

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THCV242_ Rev.2.11_E
MPRF (Main-Link PRivate Format)
MPRF format encoding preserves original data packet input to V-by-One® HS transmitter and output the data
packet from THCV242. The counterpart transmitter must have installed MPRF format decoder like THCV241
because MPRF is not standard format.
Input V-by-One® HS Byte Mode is 4Byte Mode.
Video formats: RAW8/10/12/14/16/20, YUV422/420, RGB888/666/565, JPEG, and User-defined generic 8-bit
are all supported with MPRF.

CMOS Sensor

Original
Data packet(format,payload, etc.)

THCV241

Figure 1.

Copyright©2023 THine Electronics, Inc.

Main-Link
MPRF
format

THCV242

Preserved
Data packet(format,payload, et c.)

Processor
In ECU orcontroller

MPRF (Main-Link PRivate Format)

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THCV242_ Rev.2.11_E
V-by-One® HS standard format
THCV242 input format capabilities as receiver are shown as follows. D[31:0] indicates V-by-One® HS standard
version1.5 UnPacker packet definition. Data can be transmitted normally only when both transmitter and receiverare set to the same available format. Some of the THCV242 format may not be supported by particular counterparttransmitter because THCV242 prepares multiple formats that suit to multiple transmitter devices alternatives.

Table 2. V-by-One® HS input data mapping format 1/4
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]RGB888
0
0
0
0
0
0
0
0
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]

Copyright©2023 THine Electronics, Inc.

Normal Mode1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]Normal Mode2
0
0
0
0
0
0
0
0
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]

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YUV422
Normal Mode3
0
0
0
0
0
0
0
0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
0
0
0
0
0
0
0
0
Cb[7]/Cr[7]Cb[6]/Cr[6]Cb[5]/Cr[5]Cb[4]/Cr[4]Cb[3]/Cr[3]Cb[2]/Cr[2]Cb[1]/Cr[1]Cb[0]/Cr[0]Demux Mode1
Y[7](1st pixel)
Y[6](1st pixel)
Y[5](1st pixel)
Y[4](1st pixel)
Y[3](1st pixel)
Y[2](1st pixel)
Y[1](1st pixel)
Y[0](1st pixel)
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Y[7](2nd pixel)
Y[6](2nd pixel)
Y[5](2nd pixel)
Y[4](2nd pixel)
Y[3](2nd pixel)
Y[2](2nd pixel)
Y[1](2nd pixel)
Y[0](2nd pixel)
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]

Demux Mode2
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Y[7](1st pixel)
Y[6](1st pixel)
Y[5](1st pixel)
Y[4](1st pixel)
Y[3](1st pixel)
Y[2](1st pixel)
Y[1](1st pixel)
Y[0](1st pixel)
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Y[7](2nd pixel)
Y[6](2nd pixel)
Y[5](2nd pixel)
Y[4](2nd pixel)
Y[3](2nd pixel)
Y[2](2nd pixel)
Y[1](2nd pixel)
Y[0](2nd pixel)

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THCV242_ Rev.2.11_E

Table 3. V-by-One® HS input data mapping format 2/4
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW8
Normal Mode2
0
0
0
0
0
0
0
0
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)
0
0
0
0
0
0
0
0
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)

Normal Mode1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)

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Demux Mode1
RAW[7] (2nd pixel)
RAW[6] (2nd pixel)
RAW[5] (2nd pixel)
RAW[4] (2nd pixel)
RAW[3] (2nd pixel)
RAW[2] (2nd pixel)
RAW[1] (2nd pixel)
RAW[0] (2nd pixel)
RAW[7] (1st pixel)
RAW[6] (1st pixel)
RAW[5] (1st pixel)
RAW[4] (1st pixel)
RAW[3] (1st pixel)
RAW[2] (1st pixel)
RAW[1] (1st pixel)
RAW[0] (1st pixel)
RAW[7] (4th pixel)
RAW[6] (4th pixel)
RAW[5] (4th pixel)
RAW[4] (4th pixel)
RAW[3] (4th pixel)
RAW[2] (4th pixel)
RAW[1] (4th pixel)
RAW[0] (4th pixel)
RAW[7] (3rd pixel)
RAW[6] (3rd pixel)
RAW[5] (3rd pixel)
RAW[4] (3rd pixel)
RAW[3] (3rd pixel)
RAW[2] (3rd pixel)
RAW[1] (3rd pixel)
RAW[0] (3rd pixel)

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THCV242_ Rev.2.11_E

Table 4. V-by-One® HS input data mapping format 3/4
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW10
Demux Mode1
0
0
0
0
0
0
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](1st pixel)
RAW[2](1st pixel)
0
0
0
0
0
0
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)

Normal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[1]
RAW[0]
RAW[9]
RAW[8]
RAW[7]
RAW[6]
RAW[5]
RAW[4]
RAW[3]
RAW[2]

10/53

Demux Mode2
0
0
0
0
0
0
0
0
0
0
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](1st pixel)
RAW[2](1st pixel)
00RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E

Table 5. V-by-One® HS input data mapping format 4/4
Format Name
Vx1HS std. Packer Packet ref.
V-by-One®HS_D[31]V-by-One®HS_D[30]V-by-One®HS_D[29]V-by-One®HS_D[28]V-by-One®HS_D[27]V-by-One®HS_D[26]V-by-One®HS_D[25]V-by-One®HS_D[24]V-by-One®HS_D[23]V-by-One®HS_D[22]V-by-One®HS_D[21]V-by-One®HS_D[20]V-by-One®HS_D[19]V-by-One®HS_D[18]V-by-One®HS_D[17]V-by-One®HS_D[16]V-by-One®HS_D[15]V-by-One®HS_D[14]V-by-One®HS_D[13]V-by-One®HS_D[12]V-by-One®HS_D[11]V-by-One®HS_D[10]V-by-One®HS_D[9]V-by-One®HS_D[8]V-by-One®HS_D[7]V-by-One®HS_D[6]V-by-One®HS_D[5]V-by-One®HS_D[4]V-by-One®HS_D[3]V-by-One®HS_D[2]V-by-One®HS_D[1]V-by-One®HS_D[0]Copyright©2023 THine Electronics, Inc.

RAW12
Demux Mode10000RAW[3](1st pixel)
RAW[2](1st pixel)
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[11](1st pixel)
RAW[10](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
0000RAW[3](2nd pixel)
RAW[2](2nd pixel)
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[11](2nd pixel)
RAW[10](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)

Normal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW[3]
RAW[2]
RAW[1]
RAW[0]
RAW[11]
RAW[10]RAW[9]
RAW[8]
RAW[7]
RAW[6]
RAW[5]
RAW[4]

11/53

Demux Mode2
0
0
0
0
0
0
0
0
RAW[3](1st pixel)
RAW[2](1st pixel)
RAW[1](1st pixel)
RAW[0](1st pixel)
RAW[11](1st pixel)
RAW[10](1st pixel)
RAW[9](1st pixel)
RAW[8](1st pixel)
RAW[7](1st pixel)
RAW[6](1st pixel)
RAW[5](1st pixel)
RAW[4](1st pixel)
RAW[3](2nd pixel)
RAW[2](2nd pixel)
RAW[1](2nd pixel)
RAW[0](2nd pixel)
RAW[11](2nd pixel)
RAW[10](2nd pixel)
RAW[9](2nd pixel)
RAW[8](2nd pixel)
RAW[7](2nd pixel)
RAW[6](2nd pixel)
RAW[5](2nd pixel)
RAW[4](2nd pixel)

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
Link Status (HTPDN/LOCKN)
Hot-Plug Function
HTPDN indicates Main-Link connect condition between Transmitter and Receiver. HTPDN of Transmitter side
is high when Receiver is not active or not connected. Then Transmitter can enter into power down mode. HTPDN
is set to Low by the Receiver when Receiver is active and connects to the Transmitter, and then Transmitter must
start up and transmit CDR training pattern for link training. HTPDN is open drain output at the receiver side.
Transmitter side needs Pull-up resistor.
There is an application option to omit HTPDN connection between Transmitter and Receiver. In this case,
HTPDN at Transmitter side should always be at Low.

Lock Detect Function
LOCKN indicates whether CDR PLL of Main-Link is in lock status or not. LOCKN at Transmitter input is set
to High by pull-up resistor when Receiver is not active or in CDR PLL training. LOCKN is set to Low by Receiver
when CDR lock is completed. After that the CDR training mode finishes and then Transmitter shifts to the normal
mode. LOCKN of Receiver is open drain. Transmitter side needs pull-up resistor.
When an application omits HTPDN, LOCKN signal should only be considered with HTPDN pulled low byReceiver.

THCV242

V-by-One®
HS Tx

30kΩ

Vcc
(Tx side)30kΩ

V-by-One®
HS Tx

30kΩ

Vcc
(Tx side)

THCV242

HTPDN

ERRy
(HTPDN)

HTPDN

HTPDN

LOCKN

ERRx
(LOCKN)

LOCKN

ERRx
(LOCKN)

With HTPDN connect

Figure 2.

Without HTPDN connect

Physical wire connection for wired Hot-plug and Lock detect scheme

It will need same GND potential reference between transmitter and receiver device to connect HTPDN andLOCKN pins directly like above. HTPDN and LOCKN can also be transmitted via Sub-Link without physicalwire connection. Assignment can be configurable by 2-wire access to internal register.

Copyright©2023 THine Electronics, Inc.

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THCV242_ Rev.2.11_E

Table 6. HTPDN/LOCKN register
Addr(h)bit

0x0019[7:4] ReservedL

Register Name

width
4

[3:2] R_LOCKN_LN1_SEL

2[1:0] R_LOCKN_LN0_SEL

2

Copyright©2023 THine Electronics, Inc.

R/W

Description

Default

RW Must be set 0
Sub-Link Lane1 LOCKN/HTPDN scheme of releted Main-Link select
0:LOCKN1
1:LOCKN0 | LOCKN1
RW 2:Reserved
3:1'b0 (Forced LOCKN/HTPDN=Low)*LOCKN1=LOCKN signal of V-by-One(R) HS Lane1=RX1P/RX1N*HTPDN of the same lane as above set LOCKN lane is used
Sub-Link Lane0 LOCKN/HTPDN scheme of releted Main-Link select
0:LOCKN0
1:LOCKN0 | LOCKN1
RW 2:Reserved
3:1'b0 (Forced LOCKN/HTPDN=Low)*LOCKN0=LOCKN signal of V-by-One(R) HS Lane0=RX0P/RX0N*HTPDN of the same lane as above set LOCKN lane is used

13/53

4'd0

2'd0

2'd0

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
6.3.

Local, Remote and Remote Slave Register Programming
2-wire serial I/F slave Device ID

To use basic functions, initialization, GPIO (General Purpose Input/Output), fault/error detection, and interrupt
function, 2-wire serial I/F enables to access registers. AIN<1:0> pin determines 2-wire slave Device ID setting.

Table 7. 2-wire serial I/F Device ID select by AIN pin
AIN1

37

I1

AIN0

36

I1

Device Address Setting for 2-w ire Serial Interface[AIN1:AIN0]=00: ID=7'h0B[AIN1:AIN0]=01: ID=7'h34[AIN1:AIN0]=10: ID=7'h77[AIN1:AIN0]=11: ID=7'h65

As an additional method, 2-wire slave Device ID setting can be changed from default value by register setting.

Table 8. 2-wire serial I/F Device ID select by register setting
Addr(h)0x0030bit

Register Name

[7:0] R_2WIRE_SADR

width

8

Copyright©2023 THine Electronics, Inc.

R/W

Description

Default

2WIRE slave device address setting[7]2WIRE slave device address control
RW 0: 2WIRE slv device addr. is set by AIN<1:0> pin
1: 2WIRE slv device addr. is set by following register [6:0][6:0]2WIRE slave device address value for register control

8'd0

14/53

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
2-wire serial Read/Write access to local Register
HOST MPU can directly access THCV242 local register by 2-wire serial I/F.

THCV242
Sub-Link Block

Sub-Link
Master2-wire
Slave

SCL
SDA

Host
MPU

Registe r

AIN<1:0> = Use r S electFigure 3.

Host to THCV242 local register access configuration

Figure 4.

2-wire serial I/F write to THCV242 local register protocol

Figure 5.

2-wire serial I/F read to THCV242 local register protocol

Copyright©2023 THine Electronics, Inc.

15/53

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SC: E

THCV242_ Rev.2.11_E
2-wire serial I/F Watch Dog Timer
2-wire Watch Dog Timer (WDT) is installed to monitor status.

Table 9. 2-wire WDT setting
Addr(h)

bit

width

R/W

0x003B[7:5] reserved

3

-

[4]

1

0x003C

Register Name

R_2WIRE_WD_EN[3:1] reserved

3

[0]

1

R_2WIRE_WD_OFFSET[7:0] R_2WIRE_WD_TIM

8

Copyright©2023 THine Electronics, Inc.

Description

Default

2WIRE WDT Enable
RW 0:Disable
1:Enable- 2WIRE_WDT_OffsetTime
RW 1:11'd2047
0:11'd1023
RW 2WIRE WDT_time=64×{R_2WIRE_WD_TIM<7:0>+1}×{2WIRE_WDT_OffsetTime}×tOSC

16/53

1'b1
1'd1
8'd255THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
Sub-Link setting
THCV242 has Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO
signals and also HTPDN/LOCKN signals for Main-Link. THCV242 is Sub-Link Master and connectable to SubLink Slave device such as THCV241.
Sub-Link Polling interval is controllable from about 20us to 800us, that may have relationships on fault/error
detection, interrupt, or other UART / GPIO transfer time designed on application. SSR (Sub-Link Status Read)
interval determines recovery quickness from 2-wire serial remote communication completion. SSR interval
effects only on Sub-Link Master “2-wire Set&Trigger mode1” (R_SLINK_MODE setting).

Table 10. Sub-Link Master protocol basic setting
Addr(h)

bit

width

R/W

0x0004[7:3] reserved

5-[2:0] R_SLINK_MODE

3

RW[7:4] R_SLINK_EN

4

RW[3:0] R_SLINK_POL_EN

4

RW[7:4] R_SLINK_SSR_EN

4

RW[3:0] R_SLINK_WD_EN

4

RW[7:5] reserved

3

-

[4]

1

RW

0x00100x00110x001A

Register Name

R_SLINK_POL_OFSET_EN[3:2] reserved2[1:0] R_SLINK_POL_TIM_UP

20x001B[7:0] R_SLINK_POL_TIM_DN

80x001C[7:2] reserved[1:0] R_SLINK_SSR_TIM_UP

620x001D[7:0] R_SLINK_SSR_TIM_DN

8-

Description

Default

Sub-Link basic protocol setting as Sub-Link Master
1: 2-wire Set&Trigger (Normal) mode1
3: 2-wire Pass Through mode1
0,2,4,5,6,7: Reserved
Sub-Link Enable[7] Reserved[6] Reserved[5] 0:Lane1 Disable, 1:Lane1 Enable[4] 0:Lane0 Disable, 1:Lane0 Enable
Sub-Link Polling Enable[3] Reserved[2] Reserved[1] 0:Lane1 Disable, 1:Lane1 Enable[0] 0:Lane0 Disable, 1:Lane0 Enable
Sub-Link SSR Enable[7] Reserved[6] Reserved[5] 0:Lane1 Disable, 1:Lane1 Enable[4] 0:Lane0 Disable, 1:Lane0 Enable
Sub-Link WDT Enable[3] Reserved[2] Reserved[1] 0:Lane1 Disable, 1:Lane1 Enable[0] 0:Lane0 Disable, 1:Lane0 Enable
Sub-Link Polling Offset Enable
0:Disable
1:Enable, Polling time phase of each lanes are shifted as below
lane1 offset from lane0: Sub-Link Poling interval x 1/4

3'd1

4'd0

4'hF

4'hF

4'hF

1'b0

-

-

RW Sub-Link Polling interval setting (min. 0x018, about 20us)
Sub-Link Polling interval time=64×(256×R_SLINK_POL_TIM_UP<1:0>
RW +R_SLINK_POL_TIM_DN<7:0>+1)×tOSC*No Polling when R_SLINK_POL_TIM_UP=0 and R_SLINK_POL_TIM_DN=0- RW Sub-Link SSR interval setting
Sub-Link SSR interval time=64×(256×R_SLINK_SSR_TIM_UP<1:0>
RW +R_SLINK_SSR_TIM_DN<7:0>+1)×tOSC*No SSR when R_SLINK_SSR_TIM_UP=0 and R_SLINK_SSR_TIM_DN=0

2'd0
8'd1242'd0
8'd249To use GPIO (General Purpose Input/Output) pin, fault/error detection and interrupt function, “2-wire
Set&Trigger mode1”, “2-wire Pass Through mode1” enables remote register access. THCV242, Sub-Link Masterdevice has 2-wire serial slave block and can connect to HOST MPU. On the other hand, the counterpart Sub-Link
Slave device has 2-wire serial master block and can connect to remote side 2-wire serial slave devices.
HOST MPU can access register of Sub-Link Master device, Sub-Link Slave device and remote side 2-wire serial
slave devices.

Copyright©2023 THine Electronics, Inc.

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THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
Sub-Link 2-wire Read/Write access to remote Register
6.3.5.1.

Sub-Link 2-wire Set and Trigger mode

HOST MPU can access to Sub-Link Slave’s register via THCV242 as Sub-Link Master only by THCV242
internal local register control and monitoring on 2-wire Set&Trigger mode1.

Sub-Link Slave Device

THCV242 as S ub-Link Master

Sub-Link Block

Sub-Link Block
Sub-Link
line

2-wireMaster

Sub-Link
Slave

Sub-Link
MasterSCL

2-wire
Slave

Host
MPU

SDA
INT

Registe r

Registe r(MSSEL=1)

Interrupt signal

Trigge red acces s by Sub-Link Master
Access fro m/to HOS T

Figure 6.

AIN<1:0> = Use r S electHost MPU to Sub-Link Slave Register via THCV242 access configuration

HOST MPU can access to remote side 2-wire serial slave register via THCV242 as Sub-Link Master only by
THCV242 internal local register control and monitoring on 2-wire Set&Trigger mode1.

Sub-Link Slave Device

THCV242 as S ub-Link Master

Sub-Link Block2-wireSlave
Device#a

SCL
SDA

2-wireMaster

Sub-Link Block

Sub-Link
Slave

Sub-Link
line

Sub-Link
MasterSCL

2-wire
Slave

SDA

Host
MPU

INT

・
・

Registe r

2-wireSlave
Device#b(MSSEL=1)

Figure 7.

Registe r

Trigge red acces s by Sub-Link Master
Access fro m/to HOS T

Interrupt signal

AIN<1:0> = Use r S electHost MPU to remote 2-wire slave devices via THCV242 access configuration

Copyright©2023 THine Electronics, Inc.

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SC: E

THCV242_ Rev.2.11_E

In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial accessand Sub-Link Slave internal bus access or remote side 2-wire serial access.
R_2WIRE_CLKSEN (Sub-Link Master side register, 0x0042 bit0) selects whether 2-wire serial slave of SubLink Master perform clock stretching.
When R_2WIRE_CLKSEN = 1, Sub-Link Master device waits HOST MPU until Sub-Link Slave register accessor remote side 2-wire serial slave register access complete by clock stretching.
When R_2WIRE_CLKSEN = 0, Sub-Link Master device informs HOST MPU that Sub-Link Slave register
access or remote side 2-wire serial register access has completed by interruption (detectable on INT pin) without
clock stretching.

Figure 8.

Copyright©2023 THine Electronics, Inc.

Sub-Link Master 2-wire slave clock stretching operation

19/53

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E

Table 11. 2-wire serial I/F Set& Trigger mode remote access control and monitoring local registers
Addr(h)

bit

width

R/W

0x00D00x00D1
0x00D20x00D30x00D40x00D50x00D6
0x00D7
0x00D80x00D90x00DA
0x00DB
0x00DC
0x00DD
0x00DE
0x00DF[7:0] R_2WIRE_DATA0[7:0] R_2WIRE_DATA1[7:0] R_2WIRE_DATA2[7:0] R_2WIRE_DATA3[7:0] R_2WIRE_DATA4[7:0] R_2WIRE_DATA5[7:0] R_2WIRE_DATA6[7:0] R_2WIRE_DATA7[7:0] R_2WIRE_DATA8[7:0] R_2WIRE_DATA9[7:0] R_2WIRE_DATA10[7:0] R_2WIRE_DATA11[7:0] R_2WIRE_DATA12[7:0] R_2WIRE_DATA13[7:0] R_2WIRE_DATA14[7:0] R_2WIRE_DATA15

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

0x00E0[7:1] R_2WIRE_DEVADR

7

RW

[0]

R_2WIRE_WR

1

RW

[7]

reserved

1-[6:4] R_2WIRE_WADR_BYTE

3

RW[3:0] R_2WIRE_DATA_BYTE

4

RW[7:1] reserved

7

-

[0]

1

RW

[7:2] reserved

6-[1:0] R_2WIRE_RD_LANE_SEL

2

RW[7:2] reserved

4-[1:0] R_2WIRE_WR_LANE_SEL

4

RW[7:1] reserved[0] R_2WIRE_START

71

W

0x00E1

0x00E20x00E30x00E40x00E5

Register Name

R_2WIRE_CLKSEN

Copyright©2023 THine Electronics, Inc.

Description

Default

2-wire serial I/F remote write/read data #0
2-wire serial I/F remote write/read data #1
2-wire serial I/F remote write/read data #2
2-wire serial I/F remote write/read data #3
2-wire serial I/F remote write/read data #4
2-wire serial I/F remote write/read data #5
2-wire serial I/F remote write/read data #6
2-wire serial I/F remote write/read data #7
2-wire serial I/F remote write/read data #8
2-wire serial I/F remote write/read data #9
2-wire serial I/F remote write/read data #10
2-wire serial I/F remote write/read data #11
2-wire serial I/F remote write/read data #12
2-wire serial I/F remote write/read data #13
2-wire serial I/F remote write/read data #14
2-wire serial I/F remote write/read data #15
2-wire serial I/F remote access target device address.
if target=self addr.; access to Sub-Link Slave inside register,else; access to remote side 2-wire serial Slave devices externally connected to Sub-Link slave
2-wire serial I/F remote access write or read select
0:Write1:Read2-wire serial I/F remote device's Sub Address (Word Address, register address) Byte width select.
address Byte width=R_2WIRE_WADR_BYTE<2:0>+1
0 : 1Byte= 8bit Sub addr.(refgister addr.)
1 : 2Byte=16bit Sub addr.(refgister addr.)
4 : 5Byte=40bit Sub addr.(refgister addr.), etc.
2-wire serial I/F remote access data Byte number
Byte Number = R_2WIRE_DATA_BYTE + 1 (e.g. 0x2 for 3byte burst)[write rule] R_2WIRE_WADR_BYTE+R_2WIRE_DATA_BYTE < 'd16
[read rule] R_2WIRE_DATA_BYTE<'d16
2-wire serial I/F local response clock stretching Enable
0: Sub-Link Master (2-wire slave) No clock stretching
1: Sub-Link Master (2-wire slave) clock stretching Enable*2-wire Pass Through mode forces clock stretching Enable
Sub-Link transaction read lane select0: Lane0 Sub-Link read
1: Lane1 Sub-Link read
2,3: Reserved
Sub-Link transaction write lane select[1] 0: Lane1 Disable, 1:Lane1 Enable[0] 0: Lane0 Disable, 1:Lane0 Enable*Only active when R_SLINK_MODE=4'd0 or 4'd1
2-wire serial I/F remote access start trigger

20/53

8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
7'h00

1'b0
-

3'd0

4'd0
1'b0
2'd0
4'hF
-

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
6.3.5.2.

Sub-Link 2-wire Pass Through mode

Sub-Link Master 2-wire Pass Through mode1 can bridge original local 2-wire commands to remote side
basically with no logical change.
2-wire Pass Through mode1 uses 2-wire slave clock stretching scheme at local Sub-Link Master side. Host
MCU 2-wire master must be no problem with clock stretching wait from 2-wire slave.

Sub-Link Slave side processing protocol “Divided write/read” scheme divides 2-wire commands into
determined data Byte groups. Each data Byte groups are sent separately on remote side. Burst write/read accesstarget Sub-Address (Word-Address) is interpreted so that subsequent Sub-Address (Word-Address) from 2nd
group is automatically and properly incremented. As shown below, remote side 2-wire accesses are independent
each other by determined Byte, which are defined in R_2WIREPT_WA_BYTE and
R_2WIREPT_DATA_BYTE at R_2WIREPT1_PASS_MODE[1]=1.

Divided w rite access at R_2WIREPT1_PASS_MODE[1]=1 (case: 1Byte Word Addres s and 16Byte burs t 2-w ire w rite w ith R_2WIREPT_WA_BYTE=3'd1 and R_2WIREPT_DATA_BYTE=4'd8)

SP

ACK

…

WD15

Figure 9.

ACK+W: Write command indicator

WD9

WD：Write Data

AD：Word Address

ACK

SID：Slave Address（Device Address)

ACK：Acknow ledge

WD8

SP：Stop Condition

ST：Start Condition

ACK[ list of abbreviations ]

AD' *

ST

Bus Free

SID+W

SP

ACK

…

WD7

ACK

WD1

WD0

AD

ACK

ACK

ST

Bus FreeRemote 2-w ire line

SID+W

Sub-Link Slave side

Bus Free2-wire Pass Through mode1 Sub-Link Slave command Divided scheme

On address processing protocol “Assigned address & rename”, THCV242 2-wire slave respond only to 2-wiredevice address defined in R_2WIREPT1_PASS_ADRxy1 (x=Lane0 or Lane1, y=0/1/2/3) for remote Pass
Through operation. Otherwise, 2-wire commands are ignored except THCV242 itself address. The device address
can be renamed before remote send. The counterpart Sub-Link Slave internal register access is available with
R_2WIREPT1_PASS_ADRINx (x=Lane0 or Lane1) setting.
On address processing protocol “All Through”, THCV242 2-wire slave respond basically all 2-wire device
address for remote Pass Through operation except THCV242 itself address. Additionally, Defined addresses in
R_2WIREPT2_NOPASS_ADRxz (x=Lane0 or Lane1, z=0/1/2/3/4/5/6/7) can be ignored by THCV242.

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Table 12. 2-wire serial I/F Pass Through mode remote access setting 1/2
Addr(h)

bit

width

R/W

0x0031[7:2] reserved

6-[1:0] R_2WIREPT_MODE

2

RW

[7]

1

-

[6:4] R_2WIREPT_WA_BYTE

3

RW[3:0] R_2WIREPT_DATA_BYTE

4

RW

0x0040[7:0] R_2WIREPT1_PASS_ADR000

8RW

0x0041[7:0] R_2WIREPT1_PASS_ADR001

8RW

0x0042[7:0] R_2WIREPT1_PASS_ADR010

8RW

0x0043[7:0] R_2WIREPT1_PASS_ADR011

8RW

0x0044[7:0] R_2WIREPT1_PASS_ADR020

8RW

0x0045[7:0] R_2WIREPT1_PASS_ADR021

8RW

0x0046[7:0] R_2WIREPT1_PASS_ADR030

8RW

0x0047[7:0] R_2WIREPT1_PASS_ADR031

8RW

0x0048[7:0] R_2WIREPT2_NOPASS_ADR00

8RW

0x0049[7:0] R_2WIREPT2_NOPASS_ADR01

8RW

0x004A[7:0] R_2WIREPT2_NOPASS_ADR02

8RW0x004B[7:0] R_2WIREPT2_NOPASS_ADR03

8RW

0x004C[7:0] R_2WIREPT2_NOPASS_ADR04

8RW

0x004D[7:0] R_2WIREPT2_NOPASS_ADR05

8RW

0x004E[7:0] R_2WIREPT2_NOPASS_ADR06

8RW

0x004F[7:0] R_2WIREPT2_NOPASS_ADR07

8RW

0x0050[7:0] R_2WIREPT1_PASS_ADRIN08

RW

0x0032

Register Name

reserved

Copyright©2023 THine Electronics, Inc.

Description

Default

2WIRE Pass Through mode setting[1]Pass Through processing protocol on Sub-Link Slave
0:Reserved
1:Divided write & Divided read** (available with 2-wire Pass Through mode1)**:Transaction address and data Byte number is set as R_2WIREPT_WA_BYTE and
R_2WIREPT_DATA_BYTE.
[0]Pass Through 2WIRE device addrress processing
0:Address rename (rule as R_2WIREPT1_PASS_ADRxy0/1. x is Lane0or1, y=<3:0>)
1:All Through (exception definition of address to ignore as
R_2WIREPT2_NOPASS_ADRxz. x is Lane0or1, z=<7:0>)
2WIRE Pass Through Divided write/read Sub-Address (Word Address) Byte number setting,
being active only at R_2WIREPT1_PASS_MODE[1]=1
Byte Number = R_2WIREPT_WA_BYTE + 1 (e.g. 0x1 for 2Byte Sub-Address)*R_2WIREPT_WA_BYTE + R_2WIREPT_DATA_BYTE < 14 is required.
2WIRE Pass Through Divided write/read data Byte number per one transaction setting,
being active only at R_2WIREPT1_PASS_MODE[1]=1
Byte Number = R_2WIREPT_DATA_BYTE + 1 (e.g. 0x2 for 3Byte per transaction)*R_2WIREPT_WA_BYTE + R_2WIREPT_DATA_BYTE < 14 is required.
2WIRE Pass Through received "before rename" address for Lane0 #0,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through "after renamed" address to send for Lane0 #0,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through received "before rename" address for Lane0 #1,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through "after renamed" address to send for Lane0 #1,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through received "before rename" address for Lane0 #2,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through "after renamed" address to send for Lane0 #2,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through received "before rename" address for Lane0 #3,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through "after renamed" address to send for Lane0 #3,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through ignore address /otherwise All Through fror Lane0 #0,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane0 #1,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane0 #2,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane0 #3,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane0 #4,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane0 #5,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane0 #6,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane0 #7,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through counterpart Sub-Link Slave internal access dedicated address for Lane0,
being active only at R_2WIREPT_MODE[0]=0.

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-

2'd0

3'd0

4'd0

8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0

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THCV242_ Rev.2.11_E

Table 13. 2-wire serial I/F Pass Through mode remote access setting 2/2
Addr(h)bit

0x0060[7:0] R_2WIREPT1_PASS_ADR100

Register Name

width
8

RW

0x0061[7:0] R_2WIREPT1_PASS_ADR101

8RW

0x0062[7:0] R_2WIREPT1_PASS_ADR110

8RW

0x0063[7:0] R_2WIREPT1_PASS_ADR111

8RW

0x0064[7:0] R_2WIREPT1_PASS_ADR120

8RW

0x0065[7:0] R_2WIREPT1_PASS_ADR121

8RW

0x0066[7:0] R_2WIREPT1_PASS_ADR130

8RW

0x0067[7:0] R_2WIREPT1_PASS_ADR131

8RW

0x0068[7:0] R_2WIREPT2_NOPASS_ADR108RW0x0069[7:0] R_2WIREPT2_NOPASS_ADR118RW

0x006A[7:0] R_2WIREPT2_NOPASS_ADR128RW0x006B[7:0] R_2WIREPT2_NOPASS_ADR138RW0x006C[7:0] R_2WIREPT2_NOPASS_ADR148RW0x006D[7:0] R_2WIREPT2_NOPASS_ADR158RW0x006E[7:0] R_2WIREPT2_NOPASS_ADR168RW

0x006F[7:0] R_2WIREPT2_NOPASS_ADR178RW0x0070[7:0] R_2WIREPT1_PASS_ADRIN1

8

RW

Copyright©2023 THine Electronics, Inc.

R/W

Description

Default

2WIRE Pass Through received "before rename" address for Lane1 #0,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through "after renamed" address to send for Lane1 #0,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through received "before rename" address for Lane1 #1,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through "after renamed" address to send for Lane1 #1,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through received "before rename" address for Lane1 #2,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through "after renamed" address to send for Lane1 #2,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through received "before rename" address for Lane1 #3,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through "after renamed" address to send for Lane1 #3,
being active only at R_2WIREPT_MODE[0]=0.
2WIRE Pass Through ignore address /otherwise All Through fror Lane1 #0,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane1 #1,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane1 #2,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane1 #3,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane1 #4,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane1 #5,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane1 #6,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through ignore address /otherwise All Through fror Lane1 #7,
being active only at R_2WIREPT_MODE[0]=1.
2WIRE Pass Through counterpart Sub-Link Slave internal access dedicated address for Lane1,
being active only at R_2WIREPT_MODE[0]=0.

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8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0
8'd0

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THCV242_ Rev.2.11_E
Sub-Link transaction time accuracy Improvement
Sub-Link Polling timing can be controllable by GPI input. All Sub-Link lane transaction timing can bearranged.

Table 14. Sub-Link transaction time accuracy control
Addr(h)

bit

width

R/W

0x0016[7:6] reserved

Register Name2-

[5:4] R_POL_TIM_CLR_EN

2

[3]

1

reserved[2:0] R_GPI_TRG_SEL

3

Description

Default-

Polling Timer Clear/Mask Enable
0:Disable
RW 1:Polling Timer Clear by GPI mode Enable
2:Polling Timer Mask by GPI mode Enable
3:Disable- Polling Timer Clear/Mask GPI select
RW 0:GPI0、1:GPI1、2:GPI2、3:GPI3、4:GPI4、5:GPI5、6:GPI6、7:GPI7*Only 0and1 are available at 2-wire mode1 (R_SLINK_MODE[1:0]=2'd1)

2'd0

3'd0

Polling Timer Clear
Trigger GPI

Polling IntervalOne
polingCleared new
Polling Interval

Polling Interval

Sub-Link Master
Polling transaction
to all Sub-Link lanes
Ignored previous
Polling Interval

Polling Timer Mask
Trigger GPI

Polling IntervalOne
polingCleared new
Polling Interval

Polling Interval

Sub-Link Master
Polling transaction
to all Sub-Link lanes
Ignored previous
Polling Interval

Ignored previous
Polling Interval

Figure 10. Sub-Link transaction time accuraty control

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THCV242_ Rev.2.11_E
6.4.

GPIO setting

Setting of GPIO can be configurable by 2-wire access to internal register.

Table 15. GPIO setting 1/2
Adr0x10 01

bit[7:4]

Register Name
R_GPIO7_MODE

width
4

R/W
R/W

init
4'h0 GPIO7 I/O Mode0x10 01[3:0]

R_GPIO6_MODE

4

R/W

4'h0

0x10 02[7:4]

R_GPIO5_MODE

4

R/W

4'h0

0x10 02[3:0]

R_GPIO4_MODE

4

R/W

4'h0

0x10 03[7:4]

R_GPIO3_MODE

4

R/W

4'h0

0x10 03[3:0]

R_GPIO2_MODE

4

R/W

4'h0

Copyright©2023 THine Electronics, Inc.

Description

0:Disable
1:Programable GPO (Output Low )2:Programable GPO (Output High)
3:Through GPI Mode
4:Through GPO Mode
5:Second 2WIRE Mode (SCL)
6:Second 2WIRE Mode (SDA)
7~F:Reserved
GPIO6 I/O Mode
0:Disable
1:Programable GPO (Output Low )2:Programable GPO (Output High)
3:Through GPI Mode
4:Through GPO Mode
5:Second 2WIRE Mode (SCL)
6:Second 2WIRE Mode (SDA)
7~F:Reserved
GPIO5 I/O Mode
0:Disable
1:Programable GPO (Output Low )2:Programable GPO (Output High)
3:Through GPI Mode
4:Through GPO Mode
5:Second 2WIRE Mode (SCL)
6:Second 2WIRE Mode (SDA)
7~F:Reserved
GPIO4 I/O Mode
0:Disable
1:Programable GPO (Output Low )2:Programable GPO (Output High)
3:Through GPI Mode
4:Through GPO Mode
5:Second 2WIRE Mode (SCL)
6:Second 2WIRE Mode (SDA)
7~F:Reserved
GPIO3 I/O Mode
0:Disable
1:Programable GPO (Output Low )2:Programable GPO (Output High)
3:Through GPI Mode
4:Through GPO Mode
5:Second 2WIRE Mode (SCL)
6:Second 2WIRE Mode (SDA)
7~F:Reserved
GPIO2 I/O Mode
0:Disable
1:Programable GPO (Output Low )2:Programable GPO (Output High)
3:Through GPI Mode
4:Through GPO Mode
5:Second 2WIRE Mode (SCL)
6:Second 2WIRE Mode (SDA)
7~F:Reserved

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THCV242_ Rev.2.11_E

Table 16. GPIO setting 2/2
Adr0x10 04

0x10 04

bit
[7:4]

[3:0]

Register Name
R_GPIO1_MODE

R_GPIO0_MODE

width
4

4

R/W
R/W

init
4'h0 GPIO1 I/O Mode

R/W

0:Disable
1:Programable GPO (Output Low )2:Programable GPO (Output High)
3:Through GPI Mode
4:Through GPO Mode
5:Second 2WIRE Mode (SCL)
6:Second 2WIRE Mode (SDA)
7~F:Reserved
4'h0 GPIO0 I/O Mode
0:Disable
1:Programable GPO (Output Low )2:Programable GPO (Output High)
3:Through GPI Mode
4:Through GPO Mode
5:Second 2WIRE Mode (SCL)
6:Second 2WIRE Mode (SDA)
7~F:Reserved

Description

Register GPIO
GPIO output control are available with register.

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THCV242_ Rev.2.11_E
Through GPIO
Local GPIO input is continuously reflected to remote GPIO output via Sub-Link polling. Bridging data aresampled every Sub-Link polling, whose basic interval is controlled by register R_SLINK_POL_TIM_UP/_DN.
Remote 2-wire access may become long transaction and could lengthen Through GPIO polling reflection interval.
Through GPIO input
to local Sub-Link device

Sub-Link Polling

Polling

Polling

Polling

Polling

Polling

Through GPIO output
from remote Sub-Link device
Sub-Link Polling interval

Figure 11. Through GPIO bridge sampling
As default setting with THCV231 as Sub-Link Slave communication (THCV242 as Sub-Link Master), GPIO1
Sub-Link Polling bridges input to THCV231-GPIO4 Through Mode and GPIO0 Sub-Link Polling bridges input
to THCV231-GPIO3 Through Mode respectively.
As default setting with THCV241 as Sub-Link Slave communication (THCV242 as Sub-Link Master), GPIO0/1
are dedicated to GPI to Sub-Link Lane0. GPIO2/3 are dedicated to GPI to Sub-Link Lane1. GPIO2/3 are also
dedicated to GPO from selected Sub-Link Lane.
THCV242
U pstream
GPIO1/GPIO0
GPIO3/GPIO2

THCV241 0

Lane0

U pstream
GPIO1/GPIO0

THCV241 1

GPIO1/GPIO0

Downstream

Lane1

GPIO3/GPIO2

D ownstream

GPIO3/GPIO2

GPIO3/GPIO2
R_RES_GP[3/2]_LN_SEL

Figure 12. Through GPIO via Sub-Link transaction assignment with THCV241
Remote UART bridge is supported with Sub-Link Through GPIO input/output. Remote UART Tx and Rx
bridge baud rate is supposed to be designed against Sub-Link Polling interval to accommodate deterministic
jitter caused by intermittent Sub-Link communication timing.

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THCV242_ Rev.2.11_E
GPIO as secondary 2-wire port
GPIO port can be secondary 2-wire port, which can accommodate dual 2-wire access from two processors.

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THCV242_ Rev.2.11_E
6.5.

MIPI
Deserializer and CSI-2 Formatter
6.5.1.1.

PLL setting

PLL setting is required. PLL setting set R_PLL_SETTING[47:0] is related with Main-Link data-rate.
PLL Configuration
F(Main-Link input)
15-100MHz

F(VCO)
500-1300MHz

Reference Divider
x 1/RefDiv
1-7

PFD

F(PFD)
15< MHz

1st Output Divider
x 1/OutDiv1
1-7

VCO

2nd Output Divider
x 1/OutDiv2
1-7

F(MIPI output)
80-1200MHz

FeedBack Divider
x 1/FBDiv
20-130Figure 1 Reference clock supply basic method
PLL_SETTING[47:0] must be selected proper to meet below constraints.
Table 1 PLL constraints

symboldiscription
F(IN) PLL input pixel clock frequency
RefDiv Reference Divider value
FBDiv FeedBack Divider value
OutDiv1 1st Output Divider value (OutDiv1 must be >= OutDiv2)
OutDiv2 2nd Output Divider value (OutDiv1 must be >= OutDiv2)F(PFD) PFD frequency
F(VCO) VCO frequency
F(OUT) PLL output pixel clock frequency

min
10
1
20
1
1
10
500
80

typ
-

max unit
133.3 MHz
7
130
7
7
MHz
1300 MHz
1200 MHz

Pixel clock frequency made by PLL is calculated as below.
[PCLK.input] = Pixel clock recovered on V-by-One® HS per lane = [F(Main-Link input)] = F(IN)[F(Main-Link input)] = Main-Link data-rate per lane / (Byte mode x 8 x 10/8)

MIPI data-rate per lane (Mbps) = [F(MIPI output)] (MHz)= MIPI High Speed mode data-rate per lane

F(VCO) =[PCLK.output] = [F(MIPI output)] =[F(MIPI output)][F(Main-Link input)]=[F(Main-Link input)] x [FBDiv][RefDiv][F(Main-Link input)] x [FBDiv][RefDiv] x [OutDiv1] x [OutDiv2]= F(OUT)[FBDiv][RefDiv] x [OutDiv1] x [OutDiv2]MIPI High Speed mode DDR output clock per lane = [F(MIPI output)] / 2 (MHz)Copyright©2023 THine Electronics, Inc.

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THCV242_ Rev.2.11_E

Table 2 PLL settingAdr0x10 210x10 220x10 220x10 230x10 230x10 230x10 230x10 240x10 25
0x10 26

bit
[7:0]
[7:3]
[2:0]
[7]
[6:4]
[3]
[2:0]
[7:0]
[7:0]
[7:0]

Register Name
R_PLL_SETTING[47:40]
R_PLL_SETTING[39:35]
R_PLL_SETTING[34:32]
R_PLL_SETTING[31]R_PLL_SETTING[30:28]
R_PLL_SETTING[27]
R_PLL_SETTING[26:24]
R_PLL_SETTING[23:16]
R_PLL_SETTING[15:8]
R_PLL_SETTING[7:0]

width
8
5
3
1
3
1
3
8
8
8

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

init
8'h0
5'h0
3'h0
1'h0
3'h0
1'h0
3'h0
8'h0
8'h0
8'h0

Description
PLL setting value, Feedback Divider value (integer part)
PLL setting value (Must be set 0)
PLL setting value, Ref erence Divider value
PLL setting value (Must be set 0)
PLL setting value, OutDiv1 (OutDiv1 must be >= OutDiv2)
PLL setting value (Must be set 0)
PLL setting value, OutDiv2 (OutDiv1 must be >= OutDiv2)
PLL setting value, Feedback Divider value (decimal part MSB)PLL setting value, Feedback Divider value (decimal part)
PLL setting value, Feedback Divider value (decimal part LSB)

PLL setting must fulfill below frequency ratio rule.
Table 3 PLL frequency ratio rule
FormatMPRF
RGB888
YUV422 Normal
YUV422 Demux
RAW8 Normal
RAW8 Demux
RAW10 Normal
RAW10 Demux
RAW12 Normal
RAW12 Demux[F(MIPI output)] / [F(Main-Link input)]frequency ratio
1*[Main-Link input lane#]*4*8/ [MIPI output lane#]
3/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]
2/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]
1*[Main-Link input lane#]*4*8/ [MIPI output lane#]
2/4*[Main-Link input lane#]*4*8/ [MIPI output lane#]
1*[Main-Link input lane#]*4*8/ [MIPI output lane#]
10/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]
20/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]
12/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]
24/32*[Main-Link input lane#]*4*8/ [MIPI output lane#]

Below Table is Look Up Table example for typical cases.
Table 4 PLL setting Look Up Table example
index condition1
720p30fps RAW3
720p30fps YUV422
4
720p60fps RAW
51080p30fps RAW6
720p60fps YUV422
71080p30fps YUV422
8
720p60fps YUV422
9720p120fps RAW
101080p60fps RAW
11
720p120fps YUV422
121080p60fps YUV422
131080p120f ps RAW
15
720p30fps RAW
17
720p30fps YUV422
18
720p60fps RAW
191080p30fps RAW
20
720p60fps YUV422
211080p30fps YUV422

Main-Link input
742.5Mbps 1lane MPRF
750Mbps 1lane MPRF

MIPI output
594Mbps x1lane
600Mbps x1lane

1.114Gbps 1lane MPRF

445.5Mbps x2lane

1.485Gbps 1lane MPRF

594Mbps x2lane

1.485Gbps 1lane MPRF

594Mbps x2lane x2

2.2275Gbps 1lane MPRF

891Mbps x2lane

2.97Gbps 1lane MPRF

594Mbps x4lane

2.2275Gbps 2lane MPRF
990Mbps 1lane RAW12 Demux
1.6Gbps 1lane YUV422 Normal

891Mbps x4lane
594Mbps x1lane
640Mbps x1lane

1.485Gbps 1lane RAW12 Demux 445.5Mbps x2lane
2.97Gbps 1lane YUV422 Normal 594Mbps x2lane

Copyright©2023 THine Electronics, Inc.

Distribution
off
off
off
off
off
off
on
off
off
off
off
off
off
off
off
off
off
off

F(MLINK in)
18.562518.75
27.84375
27.84375
37.12537.12537.12555.6875
55.6875
74.25
74.25
55.687524.75
40
37.12537.125
74.25
74.25

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F(VCO)
1188
1200
891
891
1188
1188
1188
891
891
1188
1188
891
594
640
891
891
1188
1188

F(MIPI out)
594
600
445.5
445.5
594
594
594
891
891
594
594
891
594
640
445.5
445.5
594
594

PLL[47:40]
0x40
0x40
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x20
0x18
0x20
0x30
0x30
0x20
0x20

PLL[39:32]
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x02
0x02
0x02
0x02
0x02
0x01
0x02
0x02
0x02
0x02
0x02

PLL[31:24]
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x11
0x11
0x21
0x21
0x11
0x11
0x11
0x21
0x21
0x21
0x21

PLL[23:16]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[15:8]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

PLL[7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

THine Electronics, Inc.

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THCV242_ Rev.2.11_E
6.5.1.2.

Video stream switch and copy/distribution

Setting of data stream handling can be configurable by 2-wire access to internal register.
Table 17. Data stream handling setting
Address

bitRegister Name

R/W

Initial0x1501

[7:5]

-

-

3'b000[4:0】

R_MODE_NO

R/W

5'b0000_0

Description
Reserved
Main-Link input data stream handling mode number
5'd0,1,2,3,8,10,11 are available. Others: reserved

Table 18. Data stream handling mode
Handling
R_MODE_NO
5'd0
5'd1
5'd2
5'd3
5'd8
5'd10
5'd11

Input
Camera111
11(2port)2
2

Distribution
DisableEnableDisableEnableDisable-Copyright©2023 THine Electronics, Inc.

Output port Output sw ap
1
2
1
2
1
2
2

DisableEnable

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Input
Main-Link_0 Main-Link_1
Cam A
Cam A
Cam B
Cam B
Cam A
Cam A
Cam A
Cam B
Cam A
Cam B

OutputMIPI_0
Cam A
Cam A
Cam B
Cam B
Cam A
Cam A
Cam B

MIPI_1
Cam A
Cam B
Cam B
Cam A

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
Header/Packet/Sync Pre-processing
Setting of Header, Packet and Sync pre-processing can be configurable by 2-wire access to internal register.
Settings of Header, Packet and Sync pre-processing exist for each Main-Link input lanes respectively.
Table 19. Header/Packet/Sync pre-processing setting for Main-Link Lane0 example
Address

bitRegister Name

R/W

Initial0x1100

[7:1]

-

-

7'h00

Reserved[0]

R_VX1_PH_EN0

R/W

1'b0

Main-Link Lane0 Input MIPI Packet Header intake
1'b0: Packet Header from Main-Link Lane0 not used
1'b1: Packet Header from Main-Link Lane0 input
Reserved

0x11010x11020x11030x11040x11050x11060x1107

[7:1]

-

-

7'h00

[0]

R_VX1_CRC_EN0

R/W

1'b0

[7:1]

-

-

7'h00

[0]

R_VX1_SP_EN0

R/W

1'b0

[7:1]

-

-

7'h00

[0]

R_VX1_VVALID_MODE0

R/W

1'b0

[7:1]

-

-

7'h00

[0]

R_VX1_VSYNC_POL0

R/W

1'b0

[7:0]

R_VX1_WC_LOW0

R/W

8'h00

[7:0]

R_VX1_WC_UP0

R/W

8'h00

[7:0]

R_VX1_DATAID0

R/W

8'h00

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Description

Main-Link Lane0 Input CRC intake
1'b0: CRC from Main-Link Lane0 not used
1'b1: CRC from Main-Link Lane0 input
Reserved
Main-Link Lane0 Input MIPI Short Packet intake
1'b0: Short Packet from Main-Link Lane0 not used
1'b1: Short Packet from Main-Link Lane0 input
Reserved
Main-Link Lane0 to MIPI VVALID generation mode
1'b0: mode1 (available with THCV241)
1'b1: mode2 (FS/FE generation from VSYNC)
Reserved
Main-Link Lane0 VSYNC intake polarity
1'b0: Low active / VSYNC=Low pulse
1'b1: High active / VSYNC=High pulse
Main-Link Lane0 to MIPI Word Count (LSB 8bit)
manual setting (Only active when R_VX1_PH_EN=0)
Main-Link Lane0 to MIPI Word Count (MSB 8bit)
manual setting (Only active when R_VX1_PH_EN=0)
Main-Link Lane0 to MIPI Data ID manual setting(Only active when R_VX1_PH_EN=0)

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
MIPI output setting
Setting of MIPI output can be configurable by 2-wire access to internal register.
Table 20. MIPI output setting 1/2
Addressbit

0x1600

[7:5]
[4:0]

Register Name

R/W

InitialDescription--

3'b000Reserved

R_ANALOG

R/W

5'h00

[4] MIPI Power Down
0: Power Down
1: Normal operation[3] MIPI Soft Reset
0: Reset
1: Normal operation[2] ReservedL: Must be set 0[1] ReservedH: Must be set 1[0] ReservedL: Must be set 00x1602[7:0]

R_TX_LANE_SEL0

R/W

8'b1110_0100 MIPI Tx Lane assignment select (SWAP)[7:6]Lane3, [5:4]Lane2, [3:2]Lane1,[1:0]Lane0
2'b00:1st Byte output
2'b01:2nd Byte output
2'b10:3rd Byte output
2'b11:4th Byte output*On 2port output configuration, 3rd and 4th
Byte are 2nd PORT1*On 2port 1lane output configuration, 1st and3rd Byte are used

0x1603

[7:1]

-

-

7'h00

Reserved[1:0]

R_TX_LANE_SEL1

R/W

2'b00

MIPI 2port output 2nd PORT1 select(Select 3rd Byte assigned 2nd PORT1 TX lane)

0x1605

[7]

-

-

[6:0]

R_LANE_EN

R/W

1'b0

Reserved

7'b0101_011 [6:5] MIPI Data lane Enable[6] Data PORT1 / 0:OFF, 1:ON
[5] Data PORT0 / 0:OFF, 1:ON
[4:3] MIPI CLK lane Enable[4] CLK lane1 / 0:OFF, 1:ON
[3] CLK lane0 / 0:OFF, 1:ON
[2:0] MIPI Configuration
3'b000:1PORT1LANE
3'b001:1PORT2LANE
3'b010:Reserved
3'b011:1PORT4LANE
3'b100:2PORT1LANE
3'b101:2PORT2LANE
3'b110:Reserved
3'b111:Reserved

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THCV242_ Rev.2.11_E

Table 21. MIPI output setting 2/2
Address

bitRegister Name

R/W

Initial0x1606

[7]

-

-

1'b0

[6:0]

R_MODE_SET

R/W

Description
Reserved

7'b100_0000 [6] ReservedH: Must be set 1[5:4] ReservedL: Must be set 0[3:2] HBLANK CLK OFF[3] HBLANK CLK OFF PORT1
0:OFF (HS clock off and go into LP at HBlank)
1:ON (HS clock continuously on at HBlank)[2] HBLANK CLK OFF PORT0
0:OFF (HS clock off and go into LP at HBlank)
1:ON (HS clock continuously on at HBlank)[1:0] CLK_NOT_STOP[1] CLK_NOT_STOP PORT1
0:OFF (HS clock off at VBlank)
1:ON (HS clock permanently on)[0] CLK_NOT_STOP PORT0
0:OFF (HS clock off at VBlank)
1:ON (HS clock permanently on)"7'b100_1100" is typical usage

0x1609[7:0]

R_TX_CLK_PREPARE0

R/W

8'd4

CLK lane PrePare period setting PORT00x160a[7:0]

R_TX_CLK_ZERO0

R/W

8'h1d

CLK lane ZERO period setting PORT00x160b[7:0]

R_TX_CLK_TRAIL0

R/W

8'h07

CLK lane TRAIL period setting PORT00x160c[7:0]

R_TX_CLK_PRE0

R/W

8'h02

CLK lane PRE period setting PORT00x160d[7:0]

R_TX_CLK_POST0

R/W

8'h0c

CLK lane POST period setting PORT00x160e[7:0]

R_TX_THS_EXIT0

R/W

8'h0b

Data lane EXIT period setting PORT00x160f[7:0]

R_TX_TLPX0

R/W

8'h05

Data lane TLPX period setting PORT00x1610[7:0]

R_TX_THS_PREPARE0

R/W

8'h04

Data lane Prepare period setting PORT00x1611[7:0]

R_TX_THS_ZERO0

R/W

8'h10

Data lane ZERO period setting PORT00x1612[7:0]

R_TX_THS_TRAIL0

R/W

8'h07

Data lane TRAIL period setting PORT00x1614[7:0]

R_TX_CLK_PREPARE1

R/W

8'h04

CLK lane PrePare period setting PORT1

0x1615[7:0]

R_TX_CLK_ZERO1

R/W

8'h1d

CLK lane ZERO period setting PORT1

0x1616[7:0]

R_TX_CLK_TRAIL1

R/W

8'h07

CLK lane TRAIL period setting PORT1

0x1617[7:0]

R_TX_CLK_PRE1

R/W

8'h02

CLK lane PRE period setting PORT1

0x1618[7:0]

R_TX_CLK_POST1

R/W

8'h0c

CLK lane POST period setting PORT1

0x1619[7:0]

R_TX_THS_EXIT1

R/W

8'h0b

Data lane EXIT period setting PORT1

0x161a[7:0]

R_TX_TLPX1

R/W

8'h05

Data lane TLPX period setting PORT1

0x161b[7:0]

R_TX_THS_PREPARE1

R/W

8'h04

Data lane Prepare period setting PORT1

0x161c[7:0]

R_TX_THS_ZERO1

R/W

8'h10

Data lane ZERO period setting PORT1

0x161d[7:0]

R_TX_THS_TRAIL1

R/W

8'h07

Data lane TRAIL period setting PORT1

0x161f

[7:4]

-

-

2'b00

Reserved[3:0]

R_REQ_SEL

R/W

4'h0

MIPI Tx Lane PORT assignment[3]Lane3, [2]Lane2, [1]Lane1, [0]Lane0
0:PORT0
1:PORT1

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THCV242_ Rev.2.11_E

MTX0P/N and MTX2P/N can be assigned to be MIPI 2nd port (port1).

THCV242

28

MTX3P

27

MTX3N

26

MTX1P

25

MTX1N

24 MTXCLK0P
23 MTXCLK0N
22

MTX0P

MIPI Tx

21

MTX0N

available

20

MTX2P

2nd port1

19

MTX2N

data pins

18 MTXCLK1P

2nd port1 clock

17 MTXCLK1N

2nd port1 clock

Figure 13. MIPI 2nd port available pins

Setting of MIPI 2port output examples are shown below.
Table 22. MIPI 2port output setting example
lane3
[7:6]
01
01
00
01
01
00

R_TX_LANE_SEL0
lane2 lane1 lane0
[5:4]
[3:2]
[1:0]
11
10
11
11
10
11

00
00
01
00
00
01

10
11
10
10
11
10

R_TX_LANE_SEL1
port1 select
[1:0]
00
10
00
00
10
00

R_LANE_EN
port enable clk enable
[6:5]
[4:3]
11
11
11
11
11
11
other settings

11
11
11
11
11
11

config
[2:0]

lane3
[3]

101
101
101
100
100
100

0
0
0
0
0
0

R_REQ_SEL
lane2 lane1
[2]
[1]
1
1
1
1
1
1

MIPI Physical pin order output assignment
lane0
lane2
MTXCLK0P/N
MTX0P/NMTX2P/N

lane0
[0]

lane3
MTX3P/N

lane1
MTX1P/N

1
1
1
1
1
1

port0 2nd Byte
port0 2nd Byte
port0 1st Byte
No output
No output
port0 1st Byte

port0 1st Byte
port0 1st Byte
port0 2nd Byte
port0 1st Byte
port0 1st Byte
No output

0
0
0
0
0
0

port0 clock
port1 1st Byte
port0 clock
port1 2nd Byte
port0 clock
port1 1st Byte
port0 clock
port1 1st Byte
port0 clock
No output
port0 clock
port1 1st Byte
forbidden

port1 2nd Byte
port1 1st Byte
port1 2nd Byte
No output
port1 1st Byte
No output

MTXCLK1P/N
port1 clock
port1 clock
port1 clock
port1 clock
port1 clock
port1 clock

MIPI CSI-2 Virtual Channel
MIPI Virtual Channel (VC) is supported. When MIPI PH(Packet Header) is intake from V-by-One® HS input,
MIPI Virtual Channel information in PH is also bridged from V-by-One® HS at the same time. Virtual Channel
information can be intake from Main-Link input and properly applied on MIPI Packet Header by selectableregister setting.

Copyright©2023 THine Electronics, Inc.

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SC: E

THCV242_ Rev.2.11_E
Multiple camera synchronization Frame Vsync supply
Frame VSYNC can be supplied from THCV242 to Sub-Link Slave GPO.
EXTSYNC input or internally generated VSYNC become supply source. Settings are configurable by 2-wireaccess to internal register. When internal VSYNC is selected, generated VSYNC is not only sent to remote SubLink Slave but also output from EXTSYNC pin.

Internal VSYNC uses two clock source, internal oscillator clock and video pixel clock from Main-Link input. At
the beginning of internal VSYNC generation operation, oscillator clock is used to supply VSYNC. After MainLink video source is received stable, internal VSYNC generation source is switched to video pixel clock fromselected Main-Link input. When Main-Link video pixel clock input is lost, internal VSYNC generator again uses
internal oscillator clock until Main-Link video pixel clock input is regained.

Table 23. Multiple camera synchronization Frame Vsync supply setting 1/2
Adr0x10 070x10 07

bit
[7:4]
[3:0]

Register Name
reserved
R_EXTSYNC_MODE

width
4
4

R/W
R/W

init
4'h0 EXTSYNC I/O Mode

Description-

0:Disable
1:Normal Mode (Controlled by Sub-Link Register)2~F: Reserved

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THCV242_ Rev.2.11_E

Table 24. Multiple camera synchronization Frame Vsync supply setting 2/2
Addr(h)

bit

width

R/W

Description

Default

0x0020[7:5] reserved

3

-

-

[4]

1

RW

[3:2] reserved2-[1:0] R_VS_MODE

2

RW[7:5] reserved[4] ReservedL[3:1] reserved

3
1
3

RW
-

[0]

R_VS_POL

1

RW

[7]

reserved

1-[6:4] R_VS_GPI_SEL

3

RW[3:2] ReservedL2RW[1:0] R_VS_LANE_SEL

2

RW

0x0023[7:4] reserved[3:0] R_VSOSC_LINE_UP

4
4

RW

0x0024[7:0] R_VSOSC_LINE_DN

8

RW

0x0025[7:0] R_VSOSC_WIDTH

8

RW

0x0026[7:4] reserved[3:0] R_VSOSC_TIM_UP

4
4

RW

0x0027[7:0] R_VSOSC_TIM_DN

8

RW

0x0028[7:2] reserved

6-[1:0] R_VS_PCLK_SEL

2

RW

0x0029[7:4] reserved[3:0] R_VSP_LINE_UP

4
4

RW

0x002A[7:0] R_VSP_LINE_DN

8RWInternal VSYNC supply Phase Shift Enable (R_VS_MODE=2'd2)
0:Disable
1:Enable, Sub-Link phase of each lanes are shifted as below
lane1 offset from lane0:
R_VS_PHASE_WIDTH
multiple camera synchronization Frame VSYNC supply mode setting
0: Disable
1: External VSYNC from EXTSYNC to remote camera supply
2: Internal VSYNC to remote camera supply and EXTSYNC pin output supply
3: DisableMust be set 0
Internal VSYNC supply polarity (R_VS_MODE=2'd2)
0: Active Low negative polarity at Vertical blanking pulse
1: Active High positive polarity at Vertical blanking pulse
Frame VSYNC supply mode Sub-Link GPI assignment bit on applied Sub-Link port
0:GPI0、1:GPI1、2:GPI2、3:GPI3、4:GPI4、5:GPI5、6:GPI6、7:GPI7*only GPI0 or GPI1 are available for 2-wire Set&Trigger mode1 and 2-wire Pass Through mode1
Must be set 0
Frame VSYNC supply target Sub-Link port[0]:Sub-Link port0; 0:no supply, 1:Frame VSYNC supply[1]:Sub-Link port1; 0:no supply, 1:Frame VSYNC supply
Internal VSYNC clock number / line by oscillator setting
Internal VSYNC clock number / line by oscillator = (256×R_VSOSC_LINE_UP<3:0>+R_VSOSC_LINE_DN<7:0>+1)×tOSC*Clock / line is 1 when R_VSOSC_LINE_UP=0 and R_VSOSC_LINE_DN=0
Internal VSYNC pulse width line number by oscillator settingLine Number = R_VSOSC_WIDTH + 1 (e.g. 0x0 for 1line)
Internal VSYNC pulse interval line number by oscillator setting
Internal VSYNC pulse interval line number by oscillator = (256×R_VSOSC_TIM_UP<3:0>+R_VSOSC_TIM_DN<7:0>+1)×tOSC*Interval line is 2 when R_VSOSC_TIM_UP=0 and R_VSOSC_TIM_DN=0
Internal VSYNC generation base pixel clock domain select0: CLK_I from Main-Link Lane0
1: CLK_I from Main-Link Lane1
2: Reserved
3: ReservedInternal VSYNC clock number / line by base pixel clock setting
Internal VSYNC clock number / line by base pixel clock = (256×R_VSP_LINE_UP<3:0>+R_VSP_LINE_DN<7:0>+1)×CLK_I*Clock / line is 1 when R_VSP_LINE_UP=0 and R_VSP_LINE_DN=0*For setting or reset of this register, R_VS_MODE is supposed to be Disable
Internal VSYNC pulse width line number by base pixel clock settingLine Number = R_VSP_WIDTH + 1 (e.g. 0x0 for 1line)*For setting or reset of this register, R_VS_MODE is supposed to be Disable
Internal VSYNC pulse interval line number setting
Internal VSYNC pulse interval line number = (256×R_VSP_TIM_UP<3:0> +R_VSP_TIM_DN<7:0>+1)
Internal VSYNC pulse interval frame period by base pixel clock = (256×R_VSP_TIM_UP<3:0>+R_VSP_TIM_DN<7:0>+1) x (256×R_VSP_LINE_UP<3:0> +R_VSP_LINE_DN<7:0>+1)×CLK_I*Interval line is 2 when R_VSP_TIM_UP=0 and R_VSP_TIM_DN=0*For setting or reset of this register, R_VS_MODE is supposed to be Disable

0x00210x0022

Register Name

R_VS_PHASE_EN

0x002B[7:0] R_VSP_WIDTH

8

RW

0x002C[7:4] reserved[3:0] R_VSP_TIM_UP

4
4

RW

0x002D[7:0] R_VSP_TIM_DN

8

RW

0x002E[7:0] R_VS_PHASE_WIDTH

80x002F[7:0] reserved

8

Copyright©2023 THine Electronics, Inc.

VSYNC Phase shift difference = =16×R_VS_PHASE_WIDTH<7:0>×CLK_I
RW *Phase shift difference is 16 xCLK_I as exception when R_VS_PHASE_WIDTH=0*For setting or reset of this register, R_VS_PHASE_EN is supposed to be Disable
- -

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1'b0
-

2'd0

1'b0
1'b0
3'd0
2'd0
2'd0
4'd0
8'd15
8'd4
4'd0
8'd15
-

2'd0

4'd0
8'd15

8'd4
4'd0

8'd15

8'd1
-

THine Electronics, Inc.

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THCV242_ Rev.2.11_E
6.6.

Status monitoring, Interrupt and Error Detection
Internal Error / status signal monitoring pin output

Internal error or status signal can be monitored as external ERR0/ERR1 pin output by register setting.

Table 25. Internal Error / status signal monitoring ERR0/ERR1 pin output settingAdr0x10 05bit[7:4]

Register Name
R_ERR1_MODE

width
4

R/W
R/W

0x10 05[3:0]

R_ERR0_MODE

4

R/W

0x10 0C
0x10 0D

[7:0]
[7:0]

R_ERR1_SEL
R_ERR0_SEL

8
8

R/W
R/W

init
4'h0 ERRR1 I/O Mode

Description

0:Disable
1:OpenDrain Output Mode
2:Push/Pull Output Mode
3~F:Reserved
4'h0 ERRR0 I/O Mode
0:Disable
1:OpenDrain Output Mode
2:Push/Pull Output Mode
3~F:Reserved
8'h0 ERR1 Pin Signal Select8'h0 ERR0 Pin Signal SelectTable 26. IC Internal selectable Error / status signal 1/3
R_ERR1/0_SEL[7:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F

Error signal
0 Fixed
1 FixedVx1_LOCKN_ALL
Vx1_HTPDN_ALL
Vx1_FBETOUT_LATCH_ALL
Vx1_FBETOUT_REAL_ALL
Vx1_PERR_ALL
MLINK_CRCERR_ALL
Vx1_CLOCKSTP_ALL
MLINK_VDSK_OK_ALL
MLINK_VDSK_NG_ALL
MLINK_DSHNDLRERR_ALL
Reserved
SLINK_PERR_ALL
SLINK_TMOUT_ALL
SLINK_FBETOUT
Vx1_LOCKN0
Vx1_LOCKN1Reserved
Reserved
Vx1_HTPDN0
Vx1_HTPDN1
Reserved
Reserved
Vx1_BETOUT_LATCH0
Vx1_BETOUT_LATCH1
Reserved
Reserved
Vx1_BETOUT_REAL0
Vx1_BETOUT_REAL1
Reserved
Reserved

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Description

OR operated of all operating lanes
OR operated of all operating lanes
OR operated of all operating lanes
OR operated of all operating lanes
OR operated of all operating lanes, protocol error
OR operated of all operating lanes
clock stop detector of all lanes
Vsync synchronization OK flag of all lanes
Vsync synchronization NG flag of all lanes
Data Stream Handler Error of all lanes
OR operated of all operating lanes, protocol error
OR operated of all operating lanes, time out error
OR operated of all operating lanes
lane0
lane1

lane0
lane1

lane0
lane1

lane0
lane1

THine Electronics, Inc.

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THCV242_ Rev.2.11_E

Table 27. IC Internal selectable Error / status signal 2/3
R_ERR1/0_SEL[7:0]
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F

Description
lane0, protocol error
lane1, protocol error

Error signal
Vx1_PERR0
Vx1_PERR1
Reserved
Reserved
MLINK_CRCERR0
MLINK_CRCERR1Reserved
Reserved
MLINK_VSYNC0MLINK_VSYNC1Reserved
Reserved
MLINK_HSYNC0MLINK_HSYNC1Reserved
Reserved
MLINK_DE0
MLINK_DE1
Reserved
Reserved
MLINK_CLK0
MLINK_CLK1
Reserved
Reserved
MIPI_BYTECLKOSCCLK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Copyright©2023 THine Electronics, Inc.

lane0
lane1

lane0
lane1

lane0
lane1

lane0
lane1

lane0
lane1

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THCV242_ Rev.2.11_E

Table 28. IC Internal selectable Error / status signal 3/3
R_ERR1/0_SEL[7:0]
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B

Error signal
MLINK_FS0
MLINK_FS1
Reserved
Reserved
MLINK_FE0
MLINK_FE1
Reserved
Reserved
MLINK_VDSK_NG0
MLINK_VDSK_NG1
Reserved
Reserved
TOP_CKSUM_ERR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SLINK_PERR0SLINK_PERR1
Reserved
Reserved
SLINK_TMOUT0SLINK_TMOUT1
Reserved
Reserved

Copyright©2023 THine Electronics, Inc.

Description
lane0, Frame Start
lane1, Frame Start

lane0, Frame End
lane1, Frame End

lane0, Vsync synchronization NG flaglane1, Vsync synchronization NG flagregister checksum error

lane0, protocol error
lane1, protocol error

lane0, time out error
lane1, time out error

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THCV242_ Rev.2.11_E
Internal Error / status signal monitoring register
Internal error or status signal can be monitored as register read value.
Error count register can be cleared by particular register write “1” access.

Table 29. Internal Error / status signal monitoring register 1/2
Addr(h)

bit

width

R/W

0x00F1[7:1] reserved

Register Name

7

-

[0]

R_SLINK_FBETERR_CLR

1

W

0x00F2[7:0] R_SLINK_FBETERR_NUM_UP

8R

0x00F3[7:0] R_SLINK_FBETERR_NUM_DN

8R

Description

Default

Sub-Link FieldBET error count clear
1: Clear
Sub-Link FieldBET error count parameter
Sub-Link FieldBET error count =256×R_SLINK_FBETERR_NUM_UP<7:0>＋R_SLINK_FBETERR_NUM_DN<7:0>-

Table 30. Internal Error / status signal monitoring register 2/2
Adr0x17 4F

0x17 50
0x17 51
0x17 52
0x17 53
0x17 58
0x17 59
0x17 5A
0x17 5B

Register Name
R_MLINK_CRC_ERRCLR[3:0]

R_MLINK_BET_ERRCLR

4

W

-

[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]

MLINK0_CRC_ERRNUM[15:8]
MLINK0_CRC_ERRNUM[7:0]
MLINK1_CRC_ERRNUM[15:8]
MLINK1_CRC_ERRNUM[7:0]
MLINK0_BET_ERRNUM[15:8]
MLINK0_BET_ERRNUM[7:0]
MLINK1_BET_ERRNUM[15:8]
MLINK1_BET_ERRNUM[7:0]

8
8
8
8
8
8
8
8

R
R
R
R
R
R
R
R

-

Copyright©2023 THine Electronics, Inc.

width R/W
4
W

Description
init- Main-Link CRC Error Counter Clear

bit
[7:4]

1:ClearMain-Link BET Error Counter Clear
1:ClearMain-Link(Lane0) CRC Error Number (Upper Byte)
Main-Link(Lane0) CRC Error Number (Low er Byte)
Main-Link(Lane1) CRC Error Number (Upper Byte)
Main-Link(Lane1) CRC Error Number (Low er Byte)
Main-Link(Lane0) BET Error Number (Upper Byte)
Main-Link(Lane0) BET Error Number (Low er Byte)
Main-Link(Lane1) BET Error Number (Upper Byte)
Main-Link(Lane1) BET Error Number (Low er Byte)

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THCV242_ Rev.2.11_E
Interrupt monitoring
Interrupt (INT1/0) detects occurrence of internal error or status signal and then, latch the detected state.
Interrupt factor can be cleared by particular register* write “1” access. (*They are indicated as “R_INTC_*”)Interrupt factor can be masked to “0” fixed by particular register appropriate write access.
INT interrupt function is supposed to be cleared before start monitoring any desired status because INT status
may change at power on condition and THCV242 internal boot up procedure.
Table 31. Interrupt monitoring
Register

Address

R_INTR_MLRX

0x1710/0x1718

R_INTR_MODE
R_INTR_DSHNDLR

0x1711/0x1719R_INTR_FMT
0x1712/0x171A

R_INTR_CSI

0x1713/0x171B

0x1714/0x171C0x1715/0x171D
R_INTR_BDC2Q

0x1716/0x171E

Copyright©2023 THine Electronics, Inc.

bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
6
5
4
3
2
1
0
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0

Description
Reserved
Reserved
MAINLINKRX protocol error for Lane1
MAINLINKRX protocol error for Lane0
Reserved
Reserved
MAINLINKRX LOCKN=L to H detection for Lane1
MAINLINKRX LOCKN=L to H detection for Lane0
Vsync synchronization OK flag of all lanes
All MAINLINKRX LOCKN=H detection
Data Stream Handler Distribution error
Data Stream Handler error
Reserved
Reserved
MAINLINKRX CRC error for Lane1
MAINLINKRX CRC error for Lane0
MIPI CSI-2 ULPS END signal PORT1
MIPI CSI-2 ULPS END signal PORT0
MIPI CSI-2 general error
MIPI CSI-2 EOT error for CLK Lane1
MIPI CSI-2 EOT error for CLK Lane0
MIPI CSI-2 SOT error for Data Lane3
MIPI CSI-2 SOT error for Data Lane2
MIPI CSI-2 SOT error for Data Lane1
MIPI CSI-2 SOT error for Data Lane0
Internal Register AutoCheckSum error flag
All Interrption Clear to remote Sub-Link slave complete flag
Reserved
Reserved
Sub-Link Slave side 2-wire access complete flag for Lane1
Sub-Link Slave side 2-wire access complete flag for Lane0
Reserved
Reserved
Sub-Link Slave side interrupt detection flag for Lane1
Sub-Link Slave side interrupt detection flag for Lane0
Reserved
Reserved
Sub-Link protocol error for Lane1
Sub-Link protocol error for Lane0
Reserved
Reserved
Reserved
Reserved

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SC: E

THCV242_ Rev.2.11_E

As a register, interrupt detected state is “1” and cleared state is “0”. When multiple interrupt sources areactivated, the OR operated result is indicated as IC external INT1/0 pin output.
As an external INT1/0 pin output, open drain output interrupt detected state is “Low” and cleared state is “HiZ”, while INT1/0 pin CMOS push-pull output interrupt detected state is “Low” and cleared state is “High”.

Table 32. INT1/0 pin output controlAdr0x10 06bit[7:4]

0x10 06[3:0]

Register Name
R_INT1_MODE

width
4

R_INT0_MODE

4

R/W
R/W

init
4'h0 INT1 I/O Mode

Description

R/W

0:Disable
1:OpenDrain Output Mode
2:Push/Pull Output Mode
3~F:Reserved
4'h0 INT0 I/O Mode
0:Disable
1:OpenDrain Output Mode
2:Push/Pull Output Mode
3~F:Reserved

INT1/0 interrupt function is supposed to be cleared before start monitoring any desired status because INT1/0
status may have been changed before monitoring activation.

Register Auto Checksum diagnosis
Register values checksum is continuously calculated as R_CKSUM_RVAL.

Table 33. Register Auto Checksum diagnosis control and monitoring
Addr(h)

bit

width

R/W

0x0008[7:1] reserved

Register Name

7

-

[0]

R_CKSUM_EN

10x0009[7:0] R_CKSUM_TIM

80x000A
0x000B[7:0] R_CKSUM_VAL[7:0] R_CKSUM_RVAL

8
8

Copyright©2023 THine Electronics, Inc.

Description

Default

Internal Register AutoCheckSum Enable
RW 0:Disable
1:EnableInternal Register AutoCheckSum check interval
RW=1024×64×(R_CKSUM_TIM<7:0>+1) × tOSC
RW Internal Register AutoCheckSum expected target value
R Internal Register AutoCheckSum read value

43/53

1'b0
8'd19
8'd0
-

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
6.7.

Power On Sequence

Power On Sequence must be controlled appropriate.
For Power On Reset, PDN input must be low at the moment when VDDCORE (VDD12) reach operating
condition voltage. As a note, PDN pin itself does not belongs to VDDCORE (VDD12) but to VDDIO1 (VDDH).
PDN Power On Reset control is mandatory.
MIPI, PLL and V-by-One® HS block are reset state at power on default and require Reset Release.
V-by-One® HS Soft Reset / PLL Soft Reset => MIPI Soft Reset is proper. See below detail.

Operating Condition min.

VDDH
(3.3V~1.8V domain)
t1

Operating Condition min.

VDD12
(1.2V domain)

t2

t11

VIH
VIL

PDN
2-wireSCL/SDATHCV242settings

Sub-Link slave
IC settings

Sub-Link
RCMP/N

THCV242
PowerON

2-wire accessprohibited
2-wire remote
access prohibited

2-wire remote access

Polling

V-by-One®HS Rx
Soft reset

Pollingt3

V-by-One®HS
Rx HTPDN
V-by-One®HS
Rx LOCKN
V-by-One®HS
Rx RX*N/P

t12
Hi-Z

Training Pattern

Normal Pattern

PLL
soft reset
MIPI Tx
soft reset

t6

MIPI Tx
TXN/P

Hi-Z

MIPI LP11

NormalOperation

Figure 14.

HS-modePower On Sequence procedure

Table 34. Power On Sequence specification
symbol
t1
t2
t11
t3
t12
t6

discription
Required w ait
from VDD33 assert to VDD12 assert
Required w ait
from Pow er On to PDN High control
Required w ait
from PDN High to Register AccessTime of V-by-One®HS Rx soft reset Highto HTPDN Low
Time of Training Pattern Input
to LOCKN Low
Time of V-by-One®HS Normal operation input
to MIPI normal operation output

min

typ

max

unit

0

-

-

us

1000

-

-

us

300

-

-

us

-

-

10

us

-

-

980

us

-

-

50+
1frameus

The first MIPI output from Power On waits vertical blanking period and starts output; therefore, MIPI normal
operation may be hold for maximum 1frame, which depends on used video format.

Copyright©2023 THine Electronics, Inc.

44/53

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THCV242_ Rev.2.11_E
6.8.

Lock / Re-Lock Sequence

Lock and re-lock sequence are as follows. V-by-One® HS automatically shifts into lock status from initial
status or unlock status caused by external noise under appropriate parameter set condition.

THCV242 LOCK Sequence
THCV242 RXnP/RXnN (n=0,1)

CDR Training

ALN Training

Normal Operationt12
THCV242 LO CKN

OnepolingPolling Interval
THCV242 (Sub-Link Master)
polling (worst. case)

LO CKN=H

Main-Link Tx LO CKN=Low
to Data pattern output delay

LOCKN=Lt6

THCV242 MTXmP/MTXmN(m=0,1,2,3)

MIPI LP11

Figure 15.

NormalOperation

Normal Operation

Lock Sequence

THCV242 Re-LOCK Sequence
THCV242 LO CKNPolling Interval
THCV242 (Sub-Link Master)
polling (worst. case)

LO CKN=L

One
polingPolling Interval

LOCKN=HLO CKN=H

One
polingMain-Link Tx LO CKN=Low
to Data pattern output delay

LO CKN=L

t12
THCV242 RXnP/RXnN (n=0,1)

Normal output

CDR Training

ALN Training

Normal Operation

Main-Link Tx LO CKN=H toTraining pattern output delayt13
THCV242 MTXmP/MTXmN(m=0,1,2,3)

NormalOperation

t6B
MIPI LP11

MIPI LP11

Figure 16.

NormalOperation

Normal Operation

Re-Lock Sequence

Table 35. Lock / Re-Lock Sequence specification
symbolt13
t6B

discription
Time of LOCKN=H
to MIPI Stand-by LP11 output
Time of V-by-One®HS Normal operation re-input
to MIPI normal operation re-output

Copyright©2023 THine Electronics, Inc.

45/53

min

typ

max

unit

-

-

98

us

-

-

50

us

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E

7.

Absolute Maximum Ratings
Table 36. Absolute Maximum Ratings*

Parameter
Supply Voltage (VDDIO1,VDDIO2)
Supply Voltage (VDDCORE,VDDRX,VDDTX,VDDPLL)LVCMOS Input Voltage (1.2V domain)
LVCMOS Input Voltage (VDDIO1 domain)
LVCMOS Output Voltage
LVCMOS Bi-directional buffer Input Voltage
LVCMOS Bi-directional buffer Output Voltage
LVCMOS Input Voltage (VDDIO2 domain)
CML Receiver Voltage
MIPI Transmitter Voltage
CML Bi-directional buffer Input Voltage
CML Bi-directional buffer Output Voltage
Output Current
Storage Temperature
Junction Temperature
Reflow Peak Temperature/time
Maximum Pow er Dissipation @ +25℃
*1 Max. must be below 4V at the same time
*2 Max. must be below 1.6V at the same time

min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-30
-55
-

typ.
-

max.
4
1.6
VDDRX+0.3 *2
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO1+0.3 *1
VDDIO2+0.3 *1
VDDRX+0.3 *2
VDDTX+0.3 *2
VDDIO2+0.3 *1
VDDIO2+0.3 *1
30
125
125
26
3.9

Unit
V
V
V
V
V
V
V
V
V
V
V
V
mA
degC
degC
degC/secW “Absolute Maximum Ratings” are values of safety limit for a device beyond which a device safety cannot be

guaranteed.
They do not imply that a device should be operated at these limits. The tables of “Recommended Operating
Condition” specify conditions for device operation.

8.

Recommended Operating Conditions
Table 37. Recommended Operating Conditions
SymbolParameter

VDDH

Supply Voltage (VDDIO1, VDDIO2)

VDD12
Ta

Supply Voltage 1.2V (VDDCORE, VDDRX, VDDTX, VDDPLL)
Operating Ambient Temperature

Copyright©2023 THine Electronics, Inc.

46/53

Condition
3.3V Drive
2.5V Drive
1.8V Drive
-

Min
3.0
2.0
1.7
1.1
-40

Typ
3.3
2.5
1.8
-

Max
3.6
3.0
2.0
1.3
105

Unit
V
V
V
V
degC

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E

9.

Consumption Current
Table 38. Consumption Current at Power Down
SymbolICCS33
ICCS12

Parameter
Pow er Dow n Supply Current

Condition
PDN=0, VDDH=3.6V
PDN=0, VDD12=1.3V

Min
-

Typ
0.1
8

Max
-

Unit
mA
mA

Min
-

Typ
16
32
14
27

Max
20
38
17
32

Unit
mA
mA
mA
mA

Table 39. Consumption Current of VDDH
SymbolICCWH_33_1
ICCWH_33_2
ICCWH_18_1
ICCWH_18_2

Parameter
VDDIO1/2=3.3V
VDDIO1/2=1.8V

Condition
Sub-Link 1lane active
Sub-Link 2lane active
Sub-Link 1lane active
Sub-Link 2lane active

Table 40. Consumption Current of VDD12

SymbolIccw12_01
Iccw12_02
Iccw12_157

port.in# port.out#

1

1

2

Iccw12_03
Iccw12_04
Iccw12_05

1

Iccw12_06
Iccw12_07
Iccw12_08

2

Iccw12_09
Iccw12_10
Iccw12_11

video format

input

quasi-1080p low fps

400Mbps x1lane

quasi-1080p high fps
720p30fps RAW
720p30fps YUV422
720p60fps RAW
1080p30fps RAW
720p60fps YUV422

4Gbps x2lane selected742.5Mbps x1lane
1Gbps x1lane

output
320Mbps x1lane
80Mbps x4lane
800Mbps x4lane
594Mbps x1lane
600Mbps x1lane

1.11375Gbps x1lane

445.5Mbps x2lane

1080p30fps YUV422

1080p60fps RAW
1

Iccw12_13

1080p60fps YUV422

Iccw12_15

Iccw12_B12

1

Iccw12_B13
Iccw12_31
Iccw12_33
Iccw12_34
Iccw12_35

Iccw12_37
Iccw12_38
Iccw12_39
Iccw12_402
Iccw12_412

22891Mbps x2lane
445.5Mbps x4lane
594Mbps x4lane

2.97Gbps x1lane

2

Iccw12_153

Iccw12_36

2.2275Gbps x1lane

720p120fps YUV422

Iccw12_14

594Mbps x2lane
594Mbps x2lane x2port Dist.

720p120fps RAW

1

Iccw12_12

1.485Gbps x1lane

1188Mbps x2lane
1188Mbps x2lane x2port Dist.

1080p120fps RAW
1080p120fps YUV422
720p30fps RAW
720p30fps YUV422
720p60fps RAW
1080p30fps RAW
720p60fps YUV422
1080p30fps YUV422
720p120fps RAW
1080p60fps RAW
720p120fps YUV422
1080p60fps YUV422

Copyright©2023 THine Electronics, Inc.

2.2275Gbps x2lane
3Gbps x2lane
742.5Mbps x1lane x2port
750Mbps x1lane x2port

891Mbps x4lane
1200Mbps x4lane
594Mbps x1lane x2port
600Mbps x1lane x2port

1.11375Gbps x1lane x2port

445.5Mbps x2lane x2port

1.485Gbps x1lane x2port

594Mbps x2lane x2port

2.2275Gbps x1lane x2port

891Mbps x2lane x2port

2.97Gbps x1lane x2port

1188Mbps x2lane x2port

47/53

min.
-

typ.
49
49
177
60
64
65
65
75
75
89
93
95
85
98
100
113
135
149
184
89
90
102
102
120
121
151
153
184
188

max.
111
109
251
123
126
128
128
139
139
158
160
161
150
165
166
184
224
238
276
148
148
165
164
186
186
219
226
258
266

Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E

10. DC Specifications
10.1. CMOS DC Specifications

Table 41. CMOS DC Specifications
SymbolIIH
IIL

Parameter
LVCMOS Input Leak Current HighLVCMOS Input Leak Current Low

VIH

LVCMOS High Level Input Voltage

VIL

LVCMOS Low Level Input Voltage

VOH

LVCMOS High Level Output Voltage

VOL

LVCMOS Low Level Output Voltage

Condition
VDDIOx=3.3V
VDDIOx=2.5V
VDDIOx=1.8V
VDDIOx=3.3V
VDDIOx=2.5V
VDDIOx=1.8V
VDDIOx=3.3V
VDDIOx=2.5V
VDDIOx=1.8V-

Min
2
0.70*VDDIO
0.65*VDDIO000
VDDIO-0.6
VDDIO-0.5
VDDIO-0.45
0

Typ
-

Max
10
10
VDDIO
VDDIO
VDDIO
0.8
0.30*VDDIO
0.35*VDDIO
VDDIO
VDDIO
VDDIO
0.45

Unit
uA
uA
V
V
V
V
V
V
V
V
V
V

min.
-50

typ.
-

max.
50
-

Unit
mV
mV

-

-

±15

uA

-

-

±15

uA

-4.6
80

100

1.6
120

mA
mA
ohm

10.2. CML Receiver DC Specifications

Table 42. CML Receiver DC Specifications
SymbolVRTH
VRTL

Parameter
CML Differential Input High Threshold
CML Differential Input Low Threshold

IRIH

CML Input Leak Current HighIRIL

CML Input Leak Current Low

IRRIH
IRRIL
RRIN

CML Input Current HighCML Input Current Low
CML Differential Input Resistance

Copyright©2023 THine Electronics, Inc.

Condition
PDN=L,
RXP/N=1.2V
PDN=L,
RXP/N=GND
RXP/N=1.2V
RXP/N=GND-

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THCV242_ Rev.2.11_E
10.3. MIPI Transmitter DC Specifications

Table 43. MIPI Transmitter DC Specifications
SymbolITIL
ITIH
VTCMTX|VTOD|VTOHHSVTOHLP
VTOLLP
ZTOLP

Parameter
Input Leak Current Low
Input Leak Current HighHS-mode statics Common-mode Voltage
HS-mode Differential Voltage
HS-mode High Level Output Voltage
LP-mode High Level Output Voltage
LP-mode Low Level Output Voltage
LP-mode Output Impedance

Copyright©2023 THine Electronics, Inc.

Condition
PDN=0
PDN=0
ZID=80~125ohm
ZID=100ohm
ZID=100ohm
-

49/53

min.
-10
-10
160
150
1.1
-0.05
120

typ.
200
200
-

max.
10
10
240
260
350
1.3
0.05
-

Unit
uA
uA
mV
mV
mV
V
V
ohm

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E
10.4. CML Bi-directional Buffer DC Specifications

Table 44. CML Bi-directional Buffer DC Specifications
SymbolParameter

VBTH

CML Bi-Directional Buffer
Differential Input High Threshold

VBTL

VBIC

IBIH
IBIL

VBOD

VBOC

IBOZ

RTERM

IDRIVE

Condition

Min

Typ

Max

Unit

R_BDCZ_HYS=0

-

-

50

mV

R_BDCZ_HYS=1

-

-

150

mV

-50

-

-

mV

-150

-

-

mV

-

VDDB-300

-

mV

-10

-

10

uA

-10

-

10

uA

200

300

400

mV

-

VDDB-300

-

mV

-10

-

10

uA

-

50

-

ohm

-

100

-

ohm

-

200

-

ohm

-

12

-

mA

-

6

-

mA

-

3

-

mA

CML Bi-Directional Buffer
R_BDCZ_HYS=0
Differential Input Low Threshold
R_BDCZ_HYS=1
R_BDCZ_TERM_**
CML Bi-Directional Buffer Input[1:0]= 2'b00
Terminated Common Voltage
R_BDCZ_DRIVE_**
DRIVE[1:0]= 2'b00
CML Bi-Directional Buffer
TCMP/N=VDD
Output Leak Current HighCML Bi-Directional Buffer
TCMP/N=0V
Output Leak Current Low
R_BDCZ_TERM_**[1:0]=2'b10
CML Bi-Directional Buffer
R_BDCZ_DRIVE_**
Differential Output Voltage[1:0]=2'b10
Diff. 100ohm terminated
R_BDCZ_TERM_**
CML Bi-Directional Buffer[1:0]=2'b00
Common Output Voltage
R_BDCZ_DRIVE_**[1:0]=2'b00
CML Bi-Directional Buffer
PDN1=0TRI-STATE Current
R_BDCZ_TERM_TX/ RX[1:0]=2'b10
CML Bi-Directional Buffer
R_BDCZ_TERM_TX/ RX
Termination Registance[1:0]=2'b01
R_BDCZ_TERM_TX/ RX[1:0]=2'b00
R_BDCZ_DRIVE_TX/ RX[1:0]=2'b10
CML Bi-Directional Buffer
R_BDCZ_DRIVE_TX/ RX
Drive Current[1:0]=2'b01
R_BDCZ_DRIVE_TX/ RX[1:0]=2'b00

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THCV242_ Rev.2.11_E

11. AC Specifications
11.1. General AC Specifications
Table 45. General AC Specifications
SymboltDLParameter
Data Latency

Condition
MainLink 1Gbps
Data stream
handling mode1

Min

Typ

Max

Unit

Typ.-98

16000

Typ.+98

ns

typ.
-

max.
2500
4

Unit
ps
Gbps

typ.
-

max.
12.5
1200

Unit
ns
Mbps

Typ
137.5

Max
172.7

Unit
ns

Max
15.7
1000

Unit
ns
kHz

11.2. CML Receiver AC Specifications
Table 46. CML Receiver AC Specifications
SymboltRBITParameter

Condition-

Unit Interval

min.
250
0.4

11.3. MIPI Transmitter AC Specifications
Table 47. MIPI Transmitter AC Specifications
SymboltTBITParameter
Tx Unit Interval

Conditions
-

min.
0.833
80

11.4. CML B-directional Buffer AC Specifications
Table 48. CML B-directional Buffer AC Specifications
SymboltBUIParameter
Bi-Directional CML Buffer Unit Interval

Condition
-

Min
128.7

11.5. 2-wire serial Slave AC Specifications
Table 49. 2-wire serial Slave AC Specifications (Sub-Link Master)
SymboltOSC
fSCL

Parameter
Cycle of internal oscillator clock
SCL clock frequency

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Condition
-

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Min
11.7
-

Typ
12.5
-

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SC: E

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0.65

0.9 MAX

1.10

0.45

6.00

9.0

12. Package

THine Electronics, Inc.

SC: E

THCV242_ Rev.2.11_E

13. Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

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