Journal of Robotics, Networking and Artificial Life, Vol. 4, No. 1 (June 2017) 58–61___________________________________________________________________________________________________________A Multistage Heuristic Tuning Algorithm for an Analog Silicon Neuron Circuit
Ethan Green

Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba,
Meguro-ku, Tokyo, 153-8505, Japan
Takashi Kohno

Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba,Meguro-ku, Tokyo, 153-8505, Japan
E-mail: green@sat.t.u-tokyo.ac.jp, kohno@sat.t.u-tokyo.ac.jp
www.u-tokyo.ac.jp

Abstract
This research looks at an ultra-low power subthreshold-operated silicon neuron circuit designed with qualitative
neuronal modeling. One technical challenge to future implementation of such circuits is parameter tuning—aproblem stemming from temperature sensitivity of subthreshold-operated MOSFETs and the uniqueness of
individual circuits in a neuronal network due to transistor variation. This research proposes a fully automatedparameter tuning algorithm that combines two heuristic approaches to search for appropriate circuit parameters
over a range of temperatures. The algorithm can tune the circuit to behave as a Class I or Class II neuron.
Keywords: neuromorphic engineering, analog VLSI, silicon neurons

semiconductor field-effect transistors (MOSFETs) intheir subthreshold regime4.
The large number of circuit parameter voltages, thetemperature sensitivity of subthreshold-operated
MOSFETs, and the problem of transistor variation
among circuits of equivalent design means that effective
parameter tuning to achieve consistent neuron-likedynamics is a significant challenge. A parameter tuningalgorithm that addresses these issues will be necessary
for future implementation of these circuits in large scale
networks.
This research is inspired by positive results in [5] inwhich the Differential Evolution (DE) algorithm wasused to tune the parameter voltages of a conductancebased silicon neuron circuit. The DE algorithm is anevolutionary algorithm which begins with random
solution vectors, in this case vectors of circuit parameter
voltages, evaluates their performance with a costfunction, and passes on elements of vectors with good
performance to the next generation6.

1. Introduction
Analog silicon neurons, electronic circuits that mimic
the electrophysiological characteristics of neuronalcells, may in the future be used as fundamental building
blocks of neuromorphic technologies like brain-mimetic
computers. These circuits operate in continuous time,
consume low power, and are expected to be
implemented in massively parallel networks that are
fundamentally different from digital transistor logic
circuits1. The circuit used in this research is an ultra-low
power analog silicon neuron designed with thetechniques of qualitative modeling—an approach whichseeks to reduce the complexity of ionic conductancemodels by describing the same dynamics with fewer
variables2. Such a model allows for replication of a wide
variety of spiking dynamics in neuronal cells, including
Class I and Class II in Hodgkin’s classification3, with aless complex low power circuit. Power consumption isfurther reduced by operating the circuit’s metal-oxide-Copyright © 2017, the Authors. Published by Atlantis Press.
This is an open access article under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
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Journal of Robotics, Networking and Artificial Life, Vol. 4, No. 1 (June 2017) 58–61___________________________________________________________________________________________________________Table 1. Spectre Circuit Parameters (x=v,n)Circuit Spectre Parameter
Function
fx(v)
gx(v)
r(n)
Iax𝐶𝑛In [7], we presented a script which pairs the Spectre
circuit simulator with optimization algorithms toautomatically search for optimum circuit parameter
voltages over a range of temperatures. Two heuristic
approaches were used to improve upon a previous trialand-error based tuning method. In this paper, we present
a multistage tuning algorithm which combines those
two heuristic methods with consideration given to their
merits and drawbacks, and adds an additional pretuning
stage to make the algorithm completely automated. Our
new algorithm eliminates the need for trial-and-error,
only requires input of benchmark characteristics, andcan tune the circuit to behave as a Class I or Class II
neuron over a range of temperatures.

= 𝑓𝑣 (𝑣) − 𝑔𝑣 (𝑣) + 𝐼𝑎𝑎 − 𝑟(𝑛) + 𝐼stim(2)

Our algorithm requires the user to input the benchmark
circuit characteristics: the nullcline structure, circuit
behavior detailed in Sec. 3.3, and current-voltage curvesof the Iax and r(n) circuits (x=v,n) at 27°C. The user thenselects the target temperature that circuit parameter
voltages are generated for.
Circuit simulations were conducted in the Cadence
software environment with the Spectre circuit simulator
on two X5570 processors (2.9 GHz, 8 threads).

The silicon neuron circuit is divided into a v-block andan n-block which each integrate the currents fromtransconductance circuit components over a capacitor.
Variables v and n represent membrane potential andabstracted ionic activity and are coded by subtracting
the voltage over their respective capacitors from Vdd.
The system equations are as follows:𝑑𝑑= 𝑓𝑛 (𝑣) − 𝑔𝑛 (𝑣) + 𝐼𝑎𝑎 − 𝑟(𝑛)3. Multistage Parameter Tuning Algorithm

2. Circuit Description

𝑑𝑑𝑑𝑑scaling
offsetscaling
scaling
scalingfine tuning

The current-voltage relationships for fx(v), gx(v) (x=v,n),
and r(n) are sigmoidal curves. A detailed description ofthese circuits is given in [2]. Iax (x=v,n) aretransconductance amplifiers used as constant current
sources and Istim is an externally applied stimulus
current. Transconductance amplifiers TAV and TAN use
a voltage clamp method to draw the nullclines—curves
on which the system equations equal zero—which areused to describe the dynamics of the silicon neuron8. Alltransistors in the silicon neuron circuit are operated intheir subthreshold regime, yielding desirable
exponential current-voltage characteristics and power
consumption as low as 3 nW.

Fig. 1. Block diagram of silicon neuron circuit, reprinted from[7]

𝐶𝑣

𝑑𝑑

fx_Vb
fx_Vdlt
gx_Vm
rn_Vm
Iax_Vb
Iax_Vin3.1. Stage I: Pretuning
As listed in Table 1, parameter voltages Iax_Vb and
rn_Vm scale the current-voltage characteristics of the Iaxand r(n) circuits (x=v,n). The first stage of the algorithm
uses Differential Evolution to find the optimum value ofthese parameters at the target temperature. The costfunction is the mean absolute difference of the currentvoltage curve resulting from a given parameter to the(1)59Journal of Robotics, Networking and Artificial Life, Vol. 4, No. 1 (June 2017) 58–61___________________________________________________________________________________________________________behavior, suggesting the need for an additional tuningstage.

current-voltage curve of the circuit with benchmark
settings at 27°C.
1𝑓(𝑥) ≜ ∑𝑘𝑖=1|𝐼𝑖 (𝑥) − 𝑏𝑖 |(3)𝑘3.3. Stage III: Tuning transient behavior

x is the parameter value for a given simulation; Ii(x)represents each point on the current-voltage curve
yielded by a given parameter value; bi represents eachcorresponding point on the benchmark curve; and v = 0
V when k = 1 and v = 1 V when k = 101. For each ofthese three circuits the DE algorithm is used once,requiring about 1.5 minutes and 130 iterations.

The final stage of the algorithm uses rn_Vm from StageI and gv_Vm, fn_Vb, and Iax_Vin (x=v,n) from Stage II
as the center of a 5 × 5 search space by adding +/– 0.5and +/–1 mV to each of these five parameter values. A
brute force approach is then used to evaluate each of the55 = 3125 combinations of parameters in this search
space by running transient simulations of the circuit.
The circuit is then subjected to 5 and 10 pA sustained
stimuli and the spiking frequency is evaluated using
data from an 800 ms time period.
The cost function evaluates each parameter set bycalculating the magnitude of the difference vector
between these two simulated circuit behaviors j(x) andtheir benchmark values b, a vector calculated fromsimulation results with a parameter set which yields
typical Class I behavior at 27°C.

3.2. Stage II: Nullcline tuning
The second stage of the algorithm uses the DEalgorithm to tune the nullclines to match the benchmark
nullclines at 27°C in the range of 250–500 mV for ClassI and 300–450 mV for Class II. Spectre simulations ofthe silicon neuron circuit’s nullcline mode are run with
the input being a vector of circuit parameters. The
parameters for Class I are gv_Vm, fx_Vb, and Iax_Vin(x=v,n). The parameters for Class II are gv_Vm, fn_Vb,
and Iax_Vin (x=v,n). The roles of these parameters arelisted in Table 1. gn_Vm and the scaling factors for theIax circuits from the pretuning stage are kept constant,and fv_Vb is kept constant in Class II mode. The r(n)circuit is set to zero in the nullcline mode and is notdirectly evaluated.
The cost function is the magnitude of the vector of
the mean absolute differences of the v and n nullclines
from their respective benchmark nullclines.
𝑔(𝐱) ≜2𝑘17.91
𝐛=��36.87(5)5 pA stimulus response7.5 pA stimulus response𝐣(𝐱) = ��,
10 pA stimulus response
12.5 pA stimulus response

022.08
𝐛=��
30.21
35.3
(6)

Class II neurons are characterized by the sudden
onset of periodic spiking when subject to an adequately
strong sustained stimulus. The cost function in Class IImode evaluates a vector of the circuit’s frequency
response to 5, 7.5, 10, and 12.5 pA sustained stimuli. b
again was calculated from simulation results with aparameter set which results in typical Class II behavior
at 27°C.

2

��1 ∑𝑘𝑖=1|𝑣𝑖 (𝐱) − 𝑏𝑖 |� + �1 ∑𝑘𝑖=1|𝑛𝑖 (𝐱) − 𝑐𝑖 |� (4)𝑘

5 pA stimulus response�,
10 pA stimulus responseℎ(𝐱) ≜ ‖𝐣(𝐱) − 𝐛‖𝐣(𝐱) = �vi(x) and ni(x) represent the points on the output v and nnullcline curves for parameter settings x; bi and ci
represent the corresponding points on the benchmark v
and n nullclines at 27°C; v = 250 V when k = 1 and v =500 V when k = 151 for Class I; and v = 300 V when k= 1 and v = 450 V when k = 151 for Class II.
Differential Evolution for this stage of the algorithm
typically requires 16 thousand nullcline mode
simulations and 8 hours of calculation time.
As reported in [7], the DE algorithm accurately
replicated the benchmark nullclines at a variety oftemperatures, but did not yield accurate transientStage III concludes with a polishing step whichinterpolates the optimum parameter set between theelements of the original search space. The entire stage
requires about 4 hours of calculation time to run all thetransient circuit simulations. Increasing the search space
exponentially increases calculation time, thus
illustrating the need for nullcline tuning in Stage II.

60

Journal of Robotics, Networking and Artificial Life, Vol. 4, No. 1 (June 2017) 58–61___________________________________________________________________________________________________________Table 2. Algorithm results with benchmark behavior highlighted in grey. “X” indicates non-neuron-like behavior
and “D” indicates decaying response.
Class IClass II

4.

Temperature (°C)
Ith(pA)
5 pA response (Hz)10 pA response (Hz)5 pA response (Hz)
7.5 pA response (Hz)10 pA response (Hz)12.5 pA response (Hz)

2X
X
X0
22.0
29.535.1

7
289.5
17.91
36.87
0
D
30.3
35.3

12248.5
17.91
36.87
0
D
30.6
35.4

17202
17.91
36.87
0
D
30.8
35.5

22164.5
17.91
36.87
0D
30.6
35.4

27
172.0
17.91
36.87
0
22.1
30.2
35.3

32
147.5
17.91
36.87
0
22.1
30.1
35.4

37
145.5
17.91
36.87
0
22.1
30.2
35.3

42
147.0
17.91
36.87
00
0
0

47
148.5
17.91
36.87
000
0

This algorithm could also be effective in dealing
with issues of transistor variation in a network of siliconneurons, since it can find unique parameter sets which
may yield similar nullcline structure among individual
members of a network. Future silicon neuron circuits
may be designed with on-chip feedback mechanisms
which automatically adjust parameter voltages based on
the results of a tuning algorithm.

Results

The algorithm was run in Class I and Class II modes for
2° to 47°C in 5° steps and the results are listed in Table
2. For Class I, the circuit displayed behavior closest to
the benchmark in the range of 7° to 47°C. 2° did notyield neuron-like behavior. The threshold current Ith isthe minimum current required for a 500 µs pulse
stimulus to generate an action potential. The thresholdcurrent ranged from 289.5 to 145.5 pA and descendedroughly as temperature increased. Class II does notexhibit threshold-like behavior so this category was notrecorded.
In Class II mode, transient behavior nearly identicalto the benchmark was observable for 32° and 37°C. At
7°, 12°, and 22°C the 10 pA and 12.5 pA sustained
stimuli induced spiking at a similar frequency to thebenchmark, but the 7.5 pA response decayed after a few
iterations. A simplified version of the algorithm which
does not contain the Iax_Vb tuning step in Stage I
yielded behavior nearly identical to the benchmark at22°, suggesting that slight modifications to thealgorithm may improve the decaying problem for 7–22°C.

Acknowledgements
This study was supported by JST PRESTO and CREST,and VDEC, the University of Tokyo in collaboration
with Cadence Design Systems, Inc.
References
1. S. Brink, et al., “A learning-enabled neuron array IC
based upon transistor channel models of biologicalphenomenon,” IEEE Transaction Biomedical Circuitsand Systems, vol. 7, no. 1, pp. 71-81, Feb. 2013.
2. T. Kohno and K. Aihara, “A Qualitative-Modeling-Based
Low-Power Silicon Nerve Membrane,” Electronics,Circuits, and Systems (ICECS), IEEE, pp. 199-202,
December, 2014.
3. A. Hodgkin, “The local electric changes associated withrepetitive action in a non-medullated axon,” The Journalof Physiology, 107, 2, pp. 165-181, March, 1948.
4. S. Liu, et al., Analog VLSI: Circuits and Principles, MITPress, 2002.
5. F. Grassia, et al., “Tunable neuromimetic integratedsystem for emulating cortical neuron models,” Frontiersin Neuroscience, vol. 5, article 134, December, 2011.
6. K. Price and R. Storn, Differential Evolution: A PracticalApproach to Global Optimization, Springer, 2005.
7. E. Green and T. Kohno, “Two Heuristic Approaches toParameter Tuning for an Analog Silicon Neuron Circuit,”2016 International Symposium on Nonlinear Theory andIts Applications, pp. 194-197, November, 2016.
8. J. Rinzel and B. Ermentrout, “Analysis of Neural
Excitability and Oscillations,” Methods in Neuronal
Modeling, Massachusetts Institute of Technology, pp.
251-291, 1998.

5. Discussion
The multistage heuristic tuning algorithm considers themerits and drawbacks of the DE algorithm-based
nullcline tuning and brute force transient tuning
approaches as noted in [7] and combines them into a
hybrid approach which in simulation can effectively
tune the silicon neuron circuit to behave as a Class I or
Class II neuron over a range of temperatures. The next
step will be to implement a version of this algorithmwith the actual silicon neuron circuit using LabVIEW orPython.

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