Tokyo Electron IR Day
October 12, 2021

CORP IR / October 12, 2021

1

Forward Looking Statements
 Disclaimer regarding forward-looking statements
Forward-looking statements with respect to TEL’s business plan, prospects and other such information are based on
information available at the time of publication. Actual performance and results may differ significantly from thebusiness plan described here due to changes in various external and internal factors, including the economic
situation, semiconductor/FPD market conditions, intensification of sales competition, safety and product quality
management, intellectual property-related risks, and impacts from COVID-19.
 Processing of numbers
For the amount listed, because fractions are rounded down, there may be the cases where the total for certain
account titles does not correspond to the sum of the respective figures for account titles. Percentages are calculatedusing full amounts, before rounding.
 Exchange risk
In principle, export sales of Tokyo Electron’s mainstay semiconductor and FPD production equipment are
denominated in yen. While some settlements are denominated in dollars, exchange risk is hedged as forward
exchange contracts are made individually at the time of booking. Accordingly, the effect of exchange rates on profits
is negligible.

FPD: Flat panel display
CORP IR / October 12, 2021

2

Agenda
1. Opening

14:30-14:35

2. Presentation

14:35-16:45– Aiming to Be a Truly Excellent Company– Supply Chain Initiatives for the Environment– Technology Trends and TEL’s Business Opportunities<Break, 10 minutes>– Challenges and Solutions for Advanced EUV Resist Process Technology– Latest Technological Challenges and TEL’s Activities in Etch
– TEL’s Approach to Next Generation Film Deposition Technology

3. Q&A

CORP IR / October 12, 2021

16:45-17:30

3

Aiming to Be a Truly Excellent Global Company​
October 12, 2021
Toshiki Kawai
Representative Director, President & CEO

CORP IR / October 12, 2021

4

Current World Situation

COVID-19 pandemic
Frequent natural disasters due to climate change
Geopolitical and human rights issues

Severe impact on people’s lives
CORP IR / October 12, 2021

5

The Shape of a New Era

IoT AR/VR/MR AI
5G CLOUD
Semiconductors, essential for information and communication
technologies, are conspicuously important
CORP IR / October 12, 2021

6

Trends Toward the Future

Digital (ICT/DX)× Green (decarbonization)

ICT: Information and Communication Technology
DX: Digital Transformation

The world is currently pushing firmly ahead with implementing ICT and DX, ​as well as taking action to realize a carbon-free society​in order to build a strong and resilient society in which ​economic activities do not stop under any circumstances
7
CORP IR / October 12, 2021

Market Structure of Digitalization
Smartening across industries

Autonomous driving

Smart cities

Smart factories

Smart agriculture

ICT industry
Semiconductors

Digital infrastructure

Smart healthcare

Video/music streaming,
mobile apps, cloud services,mobile communication services, etc.

Data centers, 5G network, mobile devices, etc.

Semiconductors“Key in industry and society”

Semiconductor
production equipment

Semiconductors are a critical infrastructure
at the core of our social system
CORP IR / October 12, 2021

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Outlook for the Semiconductor Market
US$ trillion$1 trillion

1.2
1.0
Products (electronic devices)

Value (services)

0.8

0.6

$440.4 billion(2020)

Data center

0.4
Smartphone

0.2

PC

Services forindustry
Services for consumers

0.0
1990

2000

2010

2020

2030

Source: 1990~2020 (WSTS),
2021~2030 (IBS, April 2021）

To more than double in the next ten years
CORP IR / October 12, 2021

9

WFE* Market
US$ billion
1,000
100
800
80
600
60

ICT・DX・
Decarbonization

400
40
200
20
0

1990

2000

2010

2020

2030

Source: VLSI Research (1990~2020)

Market being driven by technological innovation for
ICT, DX and decarbonization
CORP IR / October 12, 2021

* WFE (Wafer fab equipment): Wafer fab equipment refers to the production equipment used in
front-end production and in wafer-level packaging production.

10

WFE Market Trends

Product
Market fluctuates withappearance of newtechnologies anddemandProduct +Value

Background to changes in
the market trend

High level and phased
continuous market
growth

1. From
From productproduct toto productproduct ++ value
value
1.

Marketsize

2. Diversification
Diversification ofof applications
applications
2.
3. Continued
Continued innovation
innovation inin3.
semiconductor technology
technology
semiconductor
4. Increased
Increased market
market visibility
visibility
4.

Past

Present

Future

WFE market transitioning to a new growth phase
CORP IR / October 12, 2021

11

High expectations for semiconductors
and production equipment market
TEL’s role and responsibilities will growfurther toward the future

CORP IR / October 12, 2021

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Corporate
Philosophy

We strive to contribute to the developmentof a dream-inspiring society throughour leading-edge technologies and reliable
service and support.

CORP IR / October 12, 2021

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Practicing Our Corporate Philosophy (Creating Shared Value)

Applying our expertise developed as an industry leading
equipment manufacturer and using all management
resources – including our employees who both create andfulfill company values – we will contribute to realizing“Digital x Green” society through the pursuit oftechnological innovation in semiconductors
We will strive to expand profits in the medium to longterm and continuously enhance our corporate value
to make people around TEL “Happy”
CORP IR / October 12, 2021

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Integrated Report Published in August 2021

Report covering TEL’s initiatives toachieve medium- to long-term profit
growth and continuous improvement ofcorporate value

CORP IR / October 12, 2021

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Important and Priority Material Issues
Create strong
next-generation products

Product
competitivenessBe the sole
strategic partner

Customer
Higherresponsiveness productivity

Continually improve
operational efficiency

Management foundation
CORP IR / October 12, 2021

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Leveraging Strengths
Major products and market position

No.1

Only One
Have products in 4 sequential Deposition Coater/processes
developer

Etch

Cleaning

Products with the world’s
No. 1 or No.2 market share

1位 2位 2位 1位 1位 1位 2位 1位
Coater/developer

Cleaning

Plasma Gas chemical Diffusion Batch
Metal Prober
etch
etch
furnace deposition deposition

Annual increase by about

100%
Market share ofcoater/developer for EUVLCORP IR / October 12, 2021

No.1
Coater/developer

EUV
lithography

Worldwide install base4,000 units

Industry’s largest install base78,000 units

17

Aggressive Investment in R&D
Change in R&D Investment
400 billion yen
300 billion yen

 Have product lineup that drives semiconductor techinnovation
 Align tech roadmap spanning multiple generations withcustomers Offer optimal solutions for customers’ both existing andupcoming lines through technical support

Achieve high hit rate in productdevelopment
FY'17 FY'18 FY'19 FY'20 FY'21 FY'22 FY'23 FY'24 FY'25

Forecast

Contribute to realizing “Digital x Green” society
by creating technologies that only TEL can provide
CORP IR / October 12, 2021

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Building a Structure Ready for Business Expansion

Tohoku plant
new production building

Yamanashi plant
new production building

Jul. 2020: began operation

Aug. 2020: began operation

Miyagi plant
May 2021: acquisition ofplant site

Building a structure for stable supply to respond to
rapidly increasing demand for semiconductors
CORP IR / October 12, 2021

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Building a Stable Supply Chain
Supply Chain Management

Miyagi Technology Innovation Center(Construction completed Sep. 2021）

STQA: Supplier Total Quality Assessment
CSR and BCPAssessment
Investigation of conflict minerals,
environmental laws and regulations, etc.

Support continuous industry growth throughcollaboration with partner companies
CORP IR / October 12, 2021

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E

S

G

Value Chain Sustainability Initiatives
CORP IR / October 12, 2021

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Global Initiatives
Sustainable Development Goals (SDGs)

Participation in International Initiatives

Clarify initiatives through business bymateriality and deploy company-wide

Signed the UN Global Compact, joined the Responsible
Business Alliance (RBA), endorsed the Task Force on
Climate-related Financial Disclosures (TCFD)

External Evaluation on our ESG Initiatives
Highly rated by evaluation organizations around the world

Tokyo Electron supports the SDGs

CORP IR / October 12, 2021

東京エレクトロン株式会社のMSCI指数への組み入れ、およびMSCIのロゴ、商標、
サービスマークまたは指数名の使用は、MSCIまたはその関係者による東京エレク
トロン株式会社の後援、推薦またはプロモーションではありません。MSCI指数は
MSCIの独占的財産です。MSCI指数の名前およびロゴはMSCIまたはその関係会社の商標またはサービスマークです。

22

Environmental Approach
Innovation in
Semiconductor

Contribute to higher
performance and lower
energy consumption

Product and Operation

Supply Chain

Medium-term environmental goals for 2030
CO2 emissions reduction targets

Pursue “Digital × Green” society
throughout the supply chain

Facilities

Products

30%

reduction

Per wafer(vs. 2018)70%

Environmental Co-Creation by Material, Process andSubcomponent Solutions

reductionof total emissions (vs. 2018)

Best Products・Best Technical Service

Ratio of renewableenergy 100%

Environmental
PerformanceStrengthen initiatives throughout our business andsupply chain toward realization of a carbon-free society
CORP IR / October 12, 2021

23

World Class Safety
TCIR (The number of workplace incident per 200,000 work hours)
Need
Improvement!

2.5
Semi. Material maker average
Semi. device maker average

2.0

Good Safety
Program

TCIR: total case incident rate

Semi. equipment maker average

1.5

Semi. Device maker company A
Semi. Device maker company B

Strong Safety
ProgramWorld Class
Safety1.0

Peer company C
Peer company D

0.5

FY’21 TEL Results

0.27
0.0

'07

'08

'09

'10

'11

'12

'13

'14

'15

'16

'17

'18

'19

Source: U.S. Bureau of Labor Statistics, or
figures announced by each company (all except
TEL use the calendar year)

Aiming for zero incidents
CORP IR / October 12, 2021

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Corporate growth is about people
Employees both create and fulfill
company values
TEL Values as
Code of Conduct

Motivation-oriented
Management

Diversity &Inclusion

Business

3Gs
Global・Generation・Gender

CORP IR / October 12, 2021

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TEL Values as Code of Conduct
Pride

Challenge

Ownership

Teamwork

Awareness

We take pride in providing
high-value products andservices.

We accept the challenge ofgoing beyond what others
are doing in pursuing ourgoal of becoming number
one globally.

We will keep ownership in
mind as we think things
through, and engage inthorough implementationin order to achieve ourgoals.

We respect each other’s
individuality and we placea high priority on
teamwork.

We must have awarenessand accept responsibility
for our behavior as
respectful members ofsociety.

We offer our customers
cutting-edge technologicalproducts, along with thehighest level of quality andtechnical service, in the
pursuit of total customer
satisfaction.
We consider profit to be an
important measure of value
in our products and services.

We view changes asopportunities and respond tothem flexibly and positively.
We are tolerant of failure andconsider it important to learn
from the process and results.

We always have anawareness of problems andtackle challenges withenthusiasm and a sense of
responsibility.
We make decisions quickly
and do what we consider tobe the best course of action.

We create a workplace with
an open atmosphere andpositive communication.
We establish relationships oftrust with our business
partners in order to facilitate
mutual growth.

We strictly comply with laws
and regulations and the rulesof society.
We give top priority to safety,
health and the global
environment.
We strive to become acompany that local
communities hold in highesteem.

CORP IR / October 12, 2021

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Human Rights

Global Reach

Employees

Suppliers

76 sites in
18 countries & regions

Approx.
15,000Approx.
1,000

Contribute to developing a dream-inspiring society byemphasizing a way of thinking that respects humanrights based on a high ethical standard
throughout the supply chain
CORP IR / October 12, 2021

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Further Increasing Corporate Value

OffenceAchieve world-classoperating margin and
ROE of over 30%＆

DefenseOffence Safety
 Quality
 Compliance Engagement
 Risk management& Security
Product
competitiveness

Customer
Responsiveness

Higherproductivity

Business

ESG
Indispensable to business sustainability

CORP IR / October 12, 2021

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Semiconductors/FPD = Future

Creating technologies that the world has
never seen
Continue to take on challenges and evolve

CORP IR / October 12, 2021

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Aiming to Be a Truly
Excellent Global Company
CORP IR / October 12, 2021

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Supply Chain Initiatives for the Environment
October 12, 2021
Sumie Segawa
Vice Division GM, Corporate Innovation Division

CORP IR / October 12, 2021

31

Supply Chain Initiative Focused on the Environment

Environmental Co-Creation by Material, Process and Subcomponent Solutions

Infinity

Color gradation

Represents the sustainable use of resources andenergy, and relationships with lasting relationship withstakeholders

Represents the ongoing reforms to reduce
environmental burdens via co-creation with partnercompanies in business activities

Important initiatives for realizing the “Digital × Green” society
CORP IR / October 12, 2021

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Background 1: Disasters Caused by Climate Change

Multiple unprecedented natural disasters are occurring around the worldand environmental consciousness is rising
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Background 2:
Trend of Environmental Conventions and Regulations
Responding to increasing
environmental regulations
Carbon neutral
declaration
EU REACH
RoHS/WEEE
Kyoto Protocol

Paris Agreement

Stockholm Convention
Montreal Protocol
Clean Air Act

1950

Emissions regulations

Muskie Act (auto emission regulations)

Basic Pollution Control Act

Basic Environment Act

Nature Conservation Act

1970

1980

Kigali Amendment

1990

2000

2010

2020

Proactive response is essential to ensure sustainability of business activities
CORP IR / October 12, 2021

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Background 3: TEL’s Duty as an Industry Leader
Digital (ICT / DX)×Green (decarbonization)

TEL will assertively drive the industry toward a sustainable society
CORP IR / October 12, 2021

35

E-COMPASS Mission / Vision / Values
MissionAim to reduce the environmental impact on the Earth by raising the green
performance of the microelectronics industry through collaboration with andencouragement of the entire supply chain

VisionWork with leading-edge environmental technology throughout the supply
chain to co-create a sustainable and prosperous future where humans andnature co-exist

ValuesProvide microelectronics manufacturing and equipment technologies withexcellent green performance, regulatory compliance, and reduced
environmental impact from operations

Pursue the “Digital × Green” society
We strive to contribute to the development of a dream-inspiring society
through our leading-edge technologies and reliable service and support
CORP IR / October 12, 2021

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Activities of E-COMPASS
Activities
Partnership strengthening

Environmentally hazardous
substances-free equipment

Development of equipmentwith proactive
environmental performance

Delivering environmental
friendly products

Production technology
innovation byenvironmental technology

Results
Pursuing sustainability
throughout the industry

Reducing environmental burden throughout the supply chain
and promoting innovations in environmental technology
CORP IR / October 12, 2021

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Activity 1: Partnership Strengthening for Reducing CO2 Emissions

409kt
Scope 3 upstream

Purchased goods and services
Capital goods

211kt

Not from our Group

5,813kt

186kt
Scope 1,2

Own emissions

Scope 3downstream

Indirect emissions fromelectricity use andheat purchase
Scope 2
kt

157

162kt

Fuel- and energy-related activities

14kt

Direct emissions
from fuel and gas use
Scope 1kt

29

Others 22kt

Upstream

Not from our GroupUse of sold products
Downstream
transportation anddistribution

5,668kt

143kt

End-of-life treatment ofsold products

2kt

Downstream
CO2 emissions across the value chain

Raising green performance of the semiconductor industry
through collaboration with and encouragement of the entire supply chain
to reduce environmental impact on the Earth
CORP IR / October 12, 2021

38

Case Study:
Initiatives to Reduce Environmental Impact in Supply Logistics
Shifting from truck to rail transport

Efforts to reduce packaging materials

TEL plants (Miyagi, Kumamoto prefectures) ⇔ Partnercompanies (Kansai region)

Cardboard box reduction: approx. 14,000/year
CO2 emissions reduction: 10.6t-CO2/year

162t CO2 emissions reduction①Reduced bubble wrap usage
Bubble wrap

Plastic trays

SealerMiyagi②Reduced cardboard box usage
Disposablecardboard boxes

Kumamoto

Foldable
containers

Specialized plastic
boxes

Specialized net
containers

Started with cargo from partner companies in
Kansai area in FY2013
Plan to expand to cargo from Kyushu region
this fiscal year

Reducing supply chain CO2 emissions through modal shifts and packaging reform
CORP IR / October 12, 2021

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Activity 2: Environmentally hazardous substances-free equipment
Build relationships of trust with stakeholders
by providing products that can be used safely long-term

Establish supply chain that provides products with minimal environmental impact
CORP IR / October 12, 2021

40

Case Study:
Identifying Future Trends and Establishing Alternative Methods
Proactively identifying substances of concern for adverse effects on the environment and human health,work with partner companies to determine alternatives and reduce environmental impact
Understanding
futureregulations

Identify substances of concern for adverse
effects on the environment- Proactive response based on leading EU / US policy andregulatory trends

Examiningalternative
methods

Technological cooperation with partner companies

Emissions
reduction
initiatives

Co-creation with suppliers

Equipment free of environmentallyhazardous substances- Evaluation/adoption of materials free of environmentallyhazardous substances- Implement alternatives through technological innovation- Pursue methods to maximize resources and minimize
the release of hazardous substances to the environment

Promoting reduction of environmental impacts throughidentifying future trends and technological innovation
CORP IR / October 12, 2021

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Activity 3:
Development of equipment with proactive environmental performance
In addition to safety and performance specifications,
set environmental performance as a core, we will provide more value-add productsStandardization of environmental specifications

Performance

Safety Environment

Accelerate technological innovation in multiple fields

EnergyWater
resources

Chemical
substances

Accelerating technological innovation utilizing equipmentwith environmental performance as new competitive edge
CORP IR / October 12, 2021

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Miyagi Technology Innovation Center
Began operating a technology innovation center with the aim ofinnovation in next generation production technology
 Driving development of innovative production
technology that improves the performance, quality
and lead time of TEL products
 Promoting collaboration as a location forfacilitating co-creation with partner companies Accelerating the development of environmental
technologies focused on the future

Accelerating further evolution of manufacturing equipment
through co-creation with partner companies
CORP IR / October 12, 2021

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Pursuing Further Partnerships
Corporate Philosophy“We strive to contribute to the development of a dream-inspiring society
through our leading-edge technologies and reliable service and support”
Pursue “Digital × Green” society throughout the supply chain

Environmental Co-Creation by Material, Process andSubcomponent Solutions

Best Products・Best Technical Service
Environmental
Performance

Accelerating global activities in pursuit of a wide range of partner companies
and seed technologies
CORP IR / October 12, 2021

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Technology trends and TEL’s business opportunities
October 12, 2021
Akihisa Sekiguchi, Ph.D.
Deputy GM, Corporate Innovation Division

CORP IR / October 12, 2021

45

Overview Composition of market, semiconductor market, data processing and growth– Warm up– Accelerating Data Creation through data launching platforms, communication & Analytical Intelligence(AI, Quantum)

 Future device evolution and R&D trends– System integration– Device, design, technology co-optimization, and hybrid devices

 Current status and direction of logic, memory and CIS technology– Continuation of scaling but with higher technical hurdles– Alternative solutions, innovation needed but fundamentally evolution of current tool lineup covers

 Summary
CORP IR / October 12, 2021

46

Composition of Market, Semiconductor Market,
Data Processing and Growth

CORP IR / October 12, 2021

47

Evolution of Automobiles

CC BY-SA 4.Source:
ModelTMitch https://en.wikipedia.org/wiki/File:1925_Ford_Model_T_touring.jpg

The advantage of the Ford Model T is that it works even without the use of semiconductors
CORP IR / October 12, 2021

48

Evolution of Automobiles as a Technology Platform
Semiconductors• Logic: CPU, GPU, controller, AI• Memory: NAND, DRAM
• Sensors: CIS, radar, vision, LIDAR• Power: convertors, regulators, generators• Communication: 5G• Displays: projectors, panels
Material• Body: lighter composite, recyclable
Communication and Decision Making• Local vs. networked

Autonomous driving cars are already at the core of the technology platform
CORP IR / October 12, 2021

49

Evolution of Communication Networks

Accelerationof 5G

5G (cloud) and edge (local) data processing are indispensable for
CORP IR / October 12, 2021 autonomous driving cars to become more widespread50

Evolution of Servers and Accelerators

Source: Shutterstock

Cloud evolution is also essential for processing ever-growing data
CORP IR / October 12, 2021

51

In-vehicle Semiconductors

WorkingmemoryAI & Data
processing

StoragememoryImage
sensing

Platform (PF) needs drive system evolution
CORP IR / October 12, 2021

52

The Abundance of Advanced Semiconductors Found in Smartphones

WorkingmemoryAI & Data
processing

StoragememoryImage
sensing

Smartphones still the representative portable and mobile platform
CORP IR / October 12, 2021

53

Internet of People

WorkingmemoryAI & Data
processing

StoragememoryImage
sensing

A tech platform by which even humans equip themselves with sensors,
CPUs and comms systems
CORP IR / October 12, 2021

54

Internet of Animals? ...Bio-logging Technology

WorkingmemoryAI & Data
processing

StoragememoryImage
sensing

A by-product of the pet boom amid the coronavirus pandemic
CORP IR / October 12, 2021

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Future Device Evolution and R&D Trends

CORP IR / October 12, 2021

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Previously Mentioned Trends Coming in the Next 10 Years
Customization
AI System

Moore’s Law
Logic
DRAM
NAND

ServerNetwork

Hyper-Mass
IoT Devices
Sensors

Response to diversifying applications
CORP IR / October 12, 2021

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Roadmap for the Next 10 Years
Customization
SDTCO*2
AI System

Moore’s Law
PPACx*1

Extending scaling
Logic
DRAM
NAND

ServerNetwork

Hyper-Mass
LegacyIoT Devices
Sensors

Development of SDGs-compatible technology for incorporation into diversifying applications
CORP IR / October 12, 2021

*1 PPACx: Power performance area cost, x*2 SDTCO: System design technology co-optimization

58

Advances in System Integration
Logic: More transistors

2D shrink

DTCO

New structure

BEOL: More layers including memory
Accelerator
Cores

On-chip
SRAM

BEOL memory*
Low latency, Random access,(non-volatile)

CORP IR / October 12, 2021

Memory: More bytes of DRAM, NAND

2D shrink

New structure

More stack

System Integration: More options

Off-chip DRAM

*eDRAM, MRAM,
RRAM, FeRAM etc.

59Advances in System Integration: Logic
2D shrink

New structure

ShrinkDTCOContact PlugContact Over Active Gate
Standard Gate Contact

Miniaturization, optimization of design and technology, advances in fabrication, 3D-ification
CORP IR / October 12, 2021

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Advances in System Integration: Memory
2D shrinkMore stackShrinkNew structure

Toward miniaturization, new structure memory, and 3D stacking
CORP IR / October 12, 2021

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Advances in System Integration: BEOL

Accelerator
Cores

On-chip
SRAM

Off-chip DRAM

BEOL memory*
Low latency, Random access,(non-volatile)*eDRAM, MRAM, RRAM, FeRAM etc.

Multi-layered interconnect with built-in memory element
CORP IR / October 12, 2021

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Semiconductor Devices: Direction of BEOL Memory Development

Current
Soft Magnet

Tunnel Barrier

eDRAM

Top Electrode
Phase Change Material
Oxide
Isolation

Swiching
Switching
RegionregionTop Electrode
Metal
Oxide

Drain

SourceOxygen Ion

ChannelFilament
OxygenVacancy

Ferroelectric Layer

Pinned Magnet

Bottom Electrode

Bottom Electrode

Bottom Gate

STT-MRAM

PCM

RRAM

FeRAM

Various forms of memory have been developed and can be usedin accordance with their intended purpose
CORP IR / October 12, 2021

63

Multi-functional Devices: Neural Processing Unit
*Neural Processing unit

Prime

GPU
CPU

GPU

Efficiency

NPU*

Performance

System throughput / Watt

CPU
NPU

4G/5G Modem

ISP 5.0

LPDDR 4X

UFS 3.0

HiFi Audio

4K HDR Video

Security Engine

Taskse.g., Leading edge mobile SoC

Performance improvements, miniaturization and reduced energy
through the expansion of optimized functional blocks
CORP IR / October 12, 2021

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Advances in System Integration: More Options
Source: TEL estimates

DeviceCIS

3D NAND

Stacking

Sensor+ DRAM
+ Logic

Cell + Peri

HBM
(w/ Bump)

W-W

W-W

D-W

Fusion(Permanent)

Fusion(Permanent)

Cu to Cu
HybridCu to Cu
Hybrid3μm

4μm

BonderType
Wafer THK

DRAM

Logic

HBM
(Bump-less)

Cell + Peri
W-W

Temporary(Bonding /De-bonding)
10μm

Backside PDN

Logic + SRAM
Cell

Logic + I/O + RF

W-W

W-W/D-W

D-W

Fusion(Permanent)

Fusion(Permanent)

Cu to Cu Hybrid
3μm

2μm

3D Hybrid

Temporary &FusionCu to Cu
HybridOx to Ox1μm

2μm~1μm

2μm

R&D

R&D

R&D

Bump

+

DRAM Cell
Bump-less

Structure
Peri. CMOS wafer

Source: H. Tsugawa,Sony (IEDM2017)

Status

HVM

R&D~MP

Source: Sakui, TIT(CICC2019)

Source: Sakui, TIT(CICC2019)

HVM

R&D

R&D

System integration techniques also optimized via PPACx
CORP IR / October 12, 2021

65

Roadmap for the Next 10 Years
Customization
SDTCO
AI System

Moore’s Law
PPACx

Extending scaling
Logic
DRAM
NAND

ServerNetwork

Hyper-Mass
LegacyIoT Devices
Sensors

Development of SDGs-compatible technology for incorporation into diversifying applications
CORP IR / October 12, 2021

66

Correlation b/w Environmental KPIs and Technology Node Migration
Observations






Performance is still improving node-over-nodebut at a reduced rate (delay)
Area scaling is being achieved but slowing beyond IN7(~ Foundry 5nm)
Technology node still drives reduction in manufacturing
energy per device
Cost of manufacturing is still declining
Water usage is still declining

Conclusion

Advancing technology nodes contributes towards SDGs
But slowing pace of reduction implies that further innovationis needed Working on advanced node devices contributes to SDGs
Graph courtesy of imec

Advanced technology development is directly linked to the SDGs
CORP IR / October 12, 2021

67

Development Trends for Key Devices

CORP IR / October 12, 2021

68

Semiconductor Devices: Direction of Development
Logic

NAND

DRAM

Through miniaturization withstructural changes

Through high stacking

Through miniaturization

Through miniaturization

Through new structures

Through new structures,new materials

・Lowered cost per transistor
・Lower power consumption・Higher speed

・Lower cost per bit

・Lower cost per bit
・Lower power consumption・Higher speed

・Lower cost per bit
CORP IR / October 12, 2021

CIS

・Increased number of pixels
・Higher speed

・Greater image quality

69

Logic Trends and Business Opportunities

CORP IR / October 12, 2021

70

Advances in Smartphone CPUs
Product Year

2014

2020

Tech. Node

20nm

5nm

Transistor

Last Gen. Planar

4th Gen. FinFET

Adv. Litho

ArFi

EUV

Die Size

89mm2

88mm2

Transistor#

2B

CPU Cores#

2

GPU Cores#

4

NPU Cores#

N/A

L2/L3 Cache

5MB

×5.9

11.8B
6

New architecture
Many cores
New function

4
16

×5.6

28MB
Source: Wikipedia

With advances in transistor fabrication, materials and lithography,
can improve integration by increasing transistor numbers, expanding functions, etc.
CORP IR / October 12, 2021

71

Advances in GPU (Operational Accelerator)
Product Year

2016

2020

Tech. Node

16nm

7nm

Transistor

1st Gen. FinFET+

3rd Gen. FinFET

Adv. Litho

ArFi

ArFi

Die Size

610mm2826mm2

Transistor#

15.3B

FP32 Cores#

3584

×3.5

54.2B
6912

New architecture
Many cores
New function

FP64 Cores#

1792

INT32 Cores#

N/A

L2/L3 Cache

5.440MB

3456
6912

×11.3

61.696MB
Source: Wikipedia

Number of transistors increasing in HPC too, visible trend toward expansion of functions
Higher integration also sought
CORP IR / October 12, 2021

72

Advances in Logic Integration Density
Pitch shrink
Key enablers

Shrink

EUV patterning
Small area gap fillingHigh selective etch
Pattern collapse free drying

Further advances in lithography, etch, thin film depositionand cleaning technologies needed for miniaturization
CORP IR / October 12, 2021

73

Advances in Logic Integration Density
Design Technology Co-optimization: DTCO
① Cell height scaling: Fin depopulation, Metal track# reduction

Key enablers






ShrinkNarrow, straight etch
Loading free recess etch
Fin capping to prevent oxidation
Low resistance silicide, metal② Cell width scaling: Single Diffusion Break, Contact Over Active Gate etc.
Contact PlugContact Over Active Gate
Standard Gate ContactKey enablers

Small hole, trench etch
Low stress gap fillingMulti-color films for etch
High selective etch

Further advances in process technology for DTCO sought
CORP IR / October 12, 2021

74

Logic Technology Roadmap*Assume new knob will be created in each node**Single Diffusion Break, ***Self Align Gate Contact

Year of HVM(20k/month)

2018

2020

2022

2024

2026

2028

2030

Node

N7

N5

N3

N2

N1.4

N1

N0.7

3~2 Fin

2 Fin

2~1 Fin

GAA NS

Forksheet

CFET

2nd Gen. CFET

Poly pitch (PP)

56

48

45

42

39

36

33

Min. MP [nm]

40

28

22

20

18

16

12

Cell height (CH)240 (2Fin)

210 (2Fin)

176 (2Fin)

120 (NS)

90 (NS)

64 (CFET)

48 (CFET)

Density (a.u.)
PP x CH x DTCO*

1

1.73(vs. N7)

1.53(vs. N5)

1.81(vs. N3)

1.65(vs. N2)

1.75(vs. N1.4)

1.67(vs. N1.0)

Heterogeneous
channel2D material

DeviceScaling booster

EUV
SDB**
High m channel

SAGC***
Dipole eWF

Backside PDN

Source: iedm 2020[1], IRDS2020 with TEL’s update[1] imec, S. B. Samavedam et al.

Aiming for 1.6-1.8x increase in logic density along with pitch scaling, DTC and scaling booster
CORP IR / October 12, 2021

75

GAA Nanosheet Device (Gate All Around Nanosheet)Lay down

FinFET

Nanosheet

Patterning defined Fin width: 3s 1.1nm*

Si EPI thickness defined sheet thickness: 3s 0.4nm**Source: SC Song (Qualcomm) et al. VLSI 2019

Improved controllability of channel width by nanosheet structure, increased channel width
through stacking  Low leak, high on current
CORP IR / October 12, 2021

76

GAA Device Process Flow
FinFETGAA FET

Source: TEL

TEL’s wafer fab equipment is essential for creating complex GAA structures
CORP IR / October 12, 202177

2 nm GAA Technology

Cross section TEM of 2nm GAA device courtesy of IBM Research

TEL’s wafer fab equipment is essential for creating complex GAA structures
CORP IR / October 12, 2021

78

GAA Related Process Modules
Mold stack & Etch

Inner spacer
Gate spacer

Nanosheet release

Replacement gate

Inner spacer

Si/SiGe

Sac film

STI Liner
・SiGe/Si: Defect free, Uniform EPI・Trench etch: Vertical profile
・STI Liner: Prevent oxidation
・STI OX: Low temp.
・STI recess: Loading less・Fin recess: Vertical profile
・Indent etch: Loading less・Inner spacer dep: Low-k (k<5)
・Inner spacer etch: High selective

・Full channel etch: High selective

・Reliability Si etch: High selective
・Advanced drying: Collapse free・Sac film: Conformal
・WFM/Dipole film: Conformal
・WFM/Dipole etch: High selective

Source: TEL

Offering new solutions for critical modules in nanosheet devices
CORP IR / October 12, 2021

79

GAA Related Process Modules
Mold stack & Etch

Inner spacer

Nanosheet release

Replacement gate

R. Ritzenthaler (imec) et al., iedm 2018

N. Loubet (IBM) et al., iedm 2019

N. Loubet (IBM) et al., iedm 2019

Source: TEL・SiGe/Si: Defect free, Uniform EPI・Trench etch: Vertical profile
・STI Liner: Prevent oxidation
・STI OX: Low temp.
・STI recess: Loading less・Fin recess: Vertical profile
・Indent etch: Loading less・Inner spacer dep: Low-k (k<5)
・Inner spacer etch: High selective

・Full channel etch: High selective

・Reliability Si etch: High selective
・Advanced drying: Collapse free・Sac film: Conformal
・WFM/Dipole film: Conformal
・WFM/Dipole etch: High selective

Key points are preventing oxidation of Si/SiGe trench, high selectivity andprecisely controllable SiGe etch, and preventing pattern collapse
CORP IR / October 12, 2021

80

Miniaturization: EUV Lithography Technology Challenges
PerformanceLine : LER, Pinching, Bridge

Stochastic noise

Pinching

ArF

EUV

ArF

EUV

BridgeHole : L-CDU, Kissing, Missing• The number of EUV photons is only 1/14 compared to ArF at the same dose.
• Photon absorption of EUV resist is lower than that of ArF resist.
• These cause large edge roughness, resulting in one of the sources ofpattern defects.

Kissing

Missing

Source: S. Morikita, et al., Tokyo Electron Miyagi(DPS2018)

Resist stack and etching co-optimization necessary
for realizing high productivity, precise control and low defects
CORP IR / October 12, 2021

81

Global Development Facilities

TEL Magnetic Solutions (Ireland)
Imec (Belgium)
CEA-Leti (France)(As of June 1, 2021)

TEL Manufacturing andEngineering of America

TEL Technology
Center, America

TEL Technology
Center Korea

CNSE
BRIDG
Tokyo Electron Technology Solutions
Tokyo Electron Kyushu
Tokyo Electron Miyagi
National Institute of Advanced Industrial
Science and Technology

IME(Singapore)

Tokyo Electron Development Sites
Consortiums

CORP IR / October 12, 2021

TEL Technology
Center, Taiwan

82

15 nm Pitch L/S Fabrication Using EUV SADP
Demonstrated on TEL tools

Litho Pitch: 30nm
CDSEM CG6300
512*512/250k

Lithography

Trilayer + Plasma
Treatment

Tone Inversion

MandrelSEMP

CD: 14.7nm
LER: 2.25nm

CD: 16.1nm
LER: 2.0nm

CD: 15.6nm
LER: 1.89nm

CD: 10.6nm
LER: 1.71nm

CD: 7.7nm
LER: 1.57nm-11%Source: Eric Liu et al., TEL Technology Center,
America SPIE 2021 Advance Lithography

-24%

-30%
Achieve industry-leading 15 nm pitch line and space pattern
CORP IR / October 12, 2021

83

Back End: Wafer Bonding and Thinning Technology for CFET
CFET
Upside down(Top tier wafer)

Wafer bonding Wafer thinning Top transistor
process

Low distortion wafer-to-wafer bonding technology and substrate film thinning technology
are necessary for scaling booster technology
CORP IR / October 12, 2021

84

Back End: Wafer Bonding and Thinning Technology for BSPDN
Backside PDN
BEOL(Front side)

Wafer bonding

Upside down

BEOL
(Back side)

Wafer thinning

Low distortion wafer-to-wafer bonding technology and substrate film thinning technology
are necessary for scaling booster technology
CORP IR / October 12, 2021

85

Back End Advances: Bonding

3D integration drives device hybridization
CORP IR / October 12, 2021

86

DRAM Trends and Business Opportunities

CORP IR / October 12, 2021

87

DRAM Structure and Process Flows

Source: TELHigh aspect ratio structure is fabricated with sophisticated patterning technology
CORP IR / October 12, 2021

88

Advances in DRAM for Smartphones
Product Year

2014

2020

Tech. Node

25nm

1ynm

DDR

LPDDR3LPDDR4X

Data Rate

1.333Gbpps

4.266Gbpps

Capacity

1GB(4Gb ×2)

×4 or 6

4GB or 6GB(8Gb or 12Gb×4)
Source: Wikipedia

DRAM

DRAM

Logic

Logic

Package substrate

Integrated Fan-Out

Flip Chip Package on Package

With the increase in data handling volumes, packaging has advancedwith expanded capacity, accelerated processing and further integration
CORP IR / October 12, 2021

89

GPU (Operational Accelerator) and HBM DRAM
Product Year

2016

2020

Capacity

16GB HBM2

×5(HBM2×4)

80GB HBM2e(HBM2e×6)
Source: Wikipedia

HBM

GPU

HBM
Si Interposer• RDL• Passive devices

Package substrate

Cu micro-bump

C4 bump

Data volumes are also increasing in HPC, driving packaging advanceswith increased integration, higher capacity and faster processing
CORP IR / October 12, 2021

90

DRAM Technology Roadmap
Source: TEL estimatesYear of HVM(20k/month)2020

F* [nm]

16

2021

2022
15~14

2023
13~12

2024

2025
12~11

2026

2027~28≦10<102029~30

6F2
3D

Cell / Peri.
layout*Feature size: STI hp along WL = STI hp / COS(21o)Patterning

193i SAQP, DP (+ EUV)

Pillar cap. A.R.

>40

Capacitor

ZAZ CIP

>45

>50

>55

M. Popovici (imec) et al. IEDM 2018
Schematic by TEL>60

Alternative: STO etc. TiN
Ru
STO
Ru
TiN

Poly SiON
Peri. CMOS

High-k Metal Gate
FinFET

CORP IR / October 12, 2021

91

Key Modules in 3D DRAM
Stack formation

CMOS wafer bonding to enable CbA
CbA

Cell Transistor formation
Capacitor formation
Currently evaluating multiple options
CORP IR / October 12, 2021

92

NAND Trends and Business Opportunities

CORP IR / October 12, 2021

93

Advances in 3D NAND Bit Density

Source: TEL

Reduced device footprint achieved by allocating logic under memory
CORP IR / October 12, 2021

94

NAND Technology Roadmap
Source: TEL estimatesYear of HVM(20k/month)

2020

Stack

128L

16x~19xL(176)

22x~25xL(240)

28x~32xL(304)

35x~4xxL(368)

41x~45xL
(440)

5xxL
(512)

1 or 222

2

2 or 33

3 or 4

Vertical pitch 50~55nm

45~55nm40~50nm35~45nm35~45nm35~45nm35~40nm

7~8mm

8.5~10.5mm

10~12.5mm

11~14mm

13.5~17mm

16~20.5mm

18.5~21mm(~1.6x/3years)
Tier

Memoryheight

2021

2022

2023

Poly Si grain CIP

Channel

2024

2025

2026

2027

2028

2029

incl. MILC Si

WL metal

W

W

W

Mo

Mo

Mo

Mo

#of memory
holes b/w slits

9

9

9~24

14~24

19 or 24

19 or 24

19 or 24

Peri. CMOS

Under arrayor Next array

Under array

Under arrayor Bonding

Under arrayor Bonding

Under arrayor Bonding

Under arrayor Bonding

Under arrayor Bonding(In general)

2030

VerticalPitch#of memory holes b/w slits
CORP IR / October 12, 2021

Tier

Vertical pitch95

3D NAND Technology Challenges and Solutions
HARC

Replacement gate: WL

Channel Si

Peri. CMCO bonding

Cell
Bonding
CMOS

Current

Potential

・HARC etch: Pluralization of each・SiN wet etch: High selective
process (multi-level contact/slit/channel, ・Advanced drying: Collapse freeetc.)
・Mo CVD: Low R WL metal

・CVD Si CIP: Large grain size

・Cu hybrid bonding EPI like

Source: TEL

Processing technology advances essential for enabling further high value-add in NAND devices
CORP IR / October 12, 2021

96

CIS Trends and Business Opportunities

CORP IR / October 12, 2021

97

CIS Has Expanded Sensor Functions With Onboard AI
Image sensor

Applications

AI

×

=

Hybridization of devices is progressing and creating further added-value
CORP IR / October 12, 2021

98

CIS Technology Challenges and Solutions
Wafer bonding:
3D stacked BSI

Deep Trench Isolation:
Pixel scaling

Capacitor:
Global Shutter

Cu Hybrid Bonding

H. Kim (Samsung) et al. ISSCC 2020 Data edit by TEL

・Wafer level Cu to Cu hybrid bonding

・Si deep trench etch: High A.R. etch

・Poly Si gap-fill: Depo-Etch-Depo for void free fill

Jae-kyu Lee (Samsung) et al. ISSCC 2020

Schematic by TEL・Capacitor etch

・Dielectric deposition
・Metal deposition

Increased importance of bonding technology, as well as etch and thin film deposition technology
CORP IR / October 12, 2021

99

Summary

CORP IR / October 12, 2021

100

Raising Added-value in SPE
WFE investment (100k WSPM*, greenfield/TEL estimates)
DRAM

Logic

3D NAND

~$21B

~$9B

~$9B

1Y

1Z

1a

1b

9X

12X

17X

2XX

7nm

5nm

3nm

2nm

Expanding business opportunities for SPE manufacturers on arrivalof new applications and rising level of technological difficulty
CORP IR / October 12, 2021

* WSPM: Wafer starts per month101

Summary Market demands are becoming more complex
 To meet these needs, the evolution of devices is accelerating, including
multifunctional devices
 Most of the multifunctionalization can be covered by existing process and systemtechnologies, but technological evolution is also essential
 Technology development must be undertaken in alignment with environmental
issues (SDGs)
 Development of advanced devices leads directly to the SDGs
 TEL's process development is conducted on a worldwide basis, and the company isstrongly promoting the development of leading-edge devices through global
collaboration both internally and externally Specific examples will be included in the following business unit announcements
CORP IR / October 12, 2021

102

Challenges and solutions foradvanced EUV resist process technology
October 12, 2021
Keiichi Akiyama
VP & General Manager, CTSPS BU

CORP IR / October 12, 2021

103

CLEAN TRACK™ LITHIUS Pro™ Z EUV Coater/Developer for EUV
LITHIUS Pro™ Z released in 2012 (Total shipment > 1600 systems)

Releasing new EUV CAR/MOR compatible features

High Reliability
100% market share in in-line coater/developer for EUV

High Productivity
Maximizes EUV exposure tool performanceHigh Versatility
LITHIUS Pro™ Z EUV
Total shipment > 100 systems

Applicable to Metal Oxide Resists and underlayers in
addition to Chemically Amplified Resists

The LITHIUS Pro™ Z platform, which has a long track record of mass production for exposure
tools with a variety of light sources, ensures high reliability and high productivity for EUV
exposure tools. Also offers high versatility for next generation EUVCORP IR / October 12, 2021

104

EUV Lithography Technology Roadmap in Logic
High volume
production year

2020

2022

2024

2026

2028

2030

Node

5 nm

3 nm

2 nm

1.4 nm1 nm

0.7 nm2 Fin

2~1 Fin

GAA NS

Forksheet

CFET

2nd Gen. CFET

Minimum metal pitch
[nm]

28

22

20

18

16

12

EUV patterningtechnology

EUV MP

EUV MP

EUV MP

EUV MP
high-NA EUVResistCAR

CAR (＋MOR)

CAR (＋MOR)

CAR＋MOR

Device

EUV MP
EUV MP
high-NA EUV MP high-NA EUV MP
CAR＋MORCAR＋MOR

CAR: Chemically Amplified Resist, MOR: Metal Oxide Resist, MP: Multi-patterning

Enhancing versatility of coater/developer to respond to future EUV lithography technologies
including MOR and high-NA EUVCORP IR / October 12, 2021

105

Forecast of EUV CAR/MOR Application Layer Counts in Logic Device
100%

MOR

50%

CAR

0%
2 nm

1.4 nm

1 nm

Logic device generation

0.7 nm

NA0.55 MOR
NA0.33 MOR
NA0.55 CAR
NA0.33 CAR
MOR: Metal Oxide Resist
CAR: Chemically Amplified Resist

TEL estimates

MOR ratio is gradually rising, but CAR ratio remains high.
Our coater/developer achieves high versatility by handling MOR and CAR in one system.
Technologies for high-NA (NA0.55) lithography are under development as it isexpected to increase application
CORP IR / October 12, 2021

106

EUV Lithography Process Roadmap and Challenges
Line pitch (nm)

34

32

30

28

26

24

22

20

Hole pitch (nm)

42

40

38

36

34

32

30

22

Trend of EUV
exposureequipment andresist technology

RLS trade off

0.33 NA EUV

0.55 NA EUV (High-NA EUV: Higher resolution)

Chemically Amplified Resist (CAR)
Metal Oxide Resist (MOR)
Defects induced by variation in EUV
lithography

Issue of securing required resist film thickness

Sensitivity (S)BridgePinching

Post-etch
resist damage

Resolution (R)CD Variation(L: Line Edge
Roughness)

Missing

Kissing

P. De Bisschop, Proc. SPIE, 10957-10 (2019)

CORP IR / October 12, 2021

Challenges
for Thinning
Resist Film

Resist line
collapse

Resist pillar
collapse

Residue inside hole

Challenges for
Thickening
Resist Film
107

EUV Lithography Process Roadmap and Challenges
Line pitch (nm)

34

32

30

28

26

24

22

20

Hole pitch (nm)

42

40

38

36

34

32

30

22

Trend of EUV
exposureequipment andresist technology

RLS trade off

0.33 NA EUV

0.55 NA EUV (High-NA EUV: Higher resolution)

Chemically Amplified Resist (CAR)
Metal Oxide Resist (MOR)
Defects induced by variation in EUV
lithography

Issue of securing required resist film thickness

Sensitivity (S)BridgePinching

Post-etch
resist damage

Resolution (R)CD Variation(L: Line Edge
Roughness)

Missing

Kissing

P. De Bisschop, Proc. SPIE, 10957-10 (2019)

CORP IR / October 12, 2021

Challenges
for Thinning
Resist Film

Resist line
collapse

Resist pillar
collapse

Residue inside hole

Challenges for
Thickening
Resist Film
108

Solution Example for CAR Technology Mass Production Challenge:
Technology to Prevent Collapse of Extremely Miniaturized Resist Line Patterns in
Wet Development
Example of 28 nm pitch 14 nm line formation with 38 nm resist film thickness
EUV exposure dose

Resist Collapse
Existing post
従来の現像後development rinse
リンスプロセス
process
Resist CD (nm)レジスト寸法
(nm)

14.0

13.4

12.5

11.7

No Resist Collapse

New post
新規現像後
development rinse
リンスプロセス
process
Resist CD (nm)レジスト寸法（nm)

14.0

13.1

12.4

11.8

New technology
prevents patterncollapse even at
11.8 nm pattern size

New post-development rinse technology prevents pattern collapse for high aspect ratio CAR,
realizing wide margin for high volume production process
CORP IR / October 12, 2021

109Solution Example for CAR Technology Mass Production Challenge:
Nanohole Formation Through Optimization of Lithography and Etch Technology
Issue of Residue
Inside Hole

36 nm pitch 18 nm hole
Dense contact hole patterning
After lithography

After etch

46 nm pitch 23 nm hole
13 nm contact hole patterning
After lithography

After etch

Removal of Residue
Inside Hole by Etch

Source: imec

18 nm hole size

Source: imec

20 nm hole size

Size expansion

Source: TEL

23 nm hole size

Source: TEL

13 nm hole size

Size reduction

Resolving issue of residue from resist development by optimization
through integrating EUV lithography and etch process technologies
CORP IR / October 12, 2021

110

EUV Lithography Process Roadmap and Challenges
Line pitch (nm)

34

32

30

28

26

24

22

20

Hole pitch (nm)

42

40

38

36

34

32

30

22

Trend of EUV
exposureequipment andresist technology

RLS trade off

0.33 NA EUV

0.55 NA EUV (High-NA EUV: Higher resolution)

Chemically Amplified Resist (CAR)
Metal Oxide Resist (MOR)
Defects induced by variation in EUV
lithography

Issue of securing required resist film thickness

Sensitivity (S)BridgePinching

Post-etch
resist damage

Resolution (R)CD Variation(L: Line Edge
Roughness)

Missing

Kissing

P. De Bisschop, Proc. SPIE, 10957-10 (2019)

CORP IR / October 12, 2021

Challenges
for Thinning
Resist Film

Resist line
collapse

Resist pillar
collapse

Residue inside hole

Challenges for
Thickening
Resist Film
111

Solution Example for MOR Technology Mass Production Challenge:
Introduction of Newly Developed Post Exposure Bake (PEB) Oven for MOR
32 nm pitch 16 nm line
Increased sensitivity
through PEB process
54.3

EUV exposure(mJ/cm2)

50
40

25% EUV exposure
dose reduction

40.5

30
20
10

2.4

2.4

Maintain line width variation

0

5
4.5
38% exposure 4
reduction
3.5
3
33.4
2.5
2.6
2
1.5
1
0.5
0

Line width variation
(nm)

60

High-precision resist thickness
control through new PEB oven

Measures against metal
contamination using new PEB oven

+0.50nm-0.50nmPEB Process Condition
EUV sensitivity > 20% (<40 mJ/cm2)

Resist uniformity of ~0.2 nm within wafer

Low metal contamination<1E10 atoms/cm2

Newly developed MOR-compatible PEB oven enables process for mass production
CORP IR / October 12, 2021

112

Solution Example for MOR Technology Mass Production Challenge:
Newly Developed Wet Development Technology
36 nm pitch 18 nm pillar for DRAM (after lithography)
Resist film thickness: 22 nm

Resist collapse with existingdevelopment technology

Local CD
uniformity (3 σ)= 1.52 nm
Existing wet
development
technology
Source: TEL

Source: TEL

Source: TEL

CD 18.0 nm

16.8 nm15.1 nm

EUV exposure 99.5 mJ/cm2

93.5 mJ/cm2

86.0 mJ/cm2

Local CD
uniformity (3 σ)= 1.47 nm

New wet development technology
prevents resist collapse

Newlydevelopedwetdevelopment
technology
Source: TEL

Source: TEL

Source: TEL

CD 18.0 nm

16.7 nm15.2 nm

EUV exposure 75.5 mJ/cm2

69.5 mJ/cm2

66.5 mJ/cm2

New wet development technology prevents resist collapse,
reduces EUV exposure dose by 25% and decreases thickness variations
CORP IR / October 12, 2021

113

Solution Example for MOR Technology Mass Production Challenge:
Module Solution Integrated with Etch
Roughness after etch

Bridge defect after etch

30 nm pitch 15 nm line

32 nm pitch 16 nm line

Electric characteristics data
30 nm pitch 15 nm line interconnects pattern
1 mm length macro

Line CD=13.4 nm1
Single Bridge2
Large Bridge

Line CD=15.7 nm

Line CD=15.1 nm

3

4

5
FM

Blockedpattern/ Multi
bridgeDark FM bridging
Openpattern= defects
due to resist
Short pattern = defects due to resist pinching

EUV exposure dose
Source: TEL
Source: TEL

After etch LWR <1.8 nm(imec standard SEM recipe)

Bridge defect density DD: < 0.1 /cm2

Achieved almost 100% yield on test pattern

MOR enabled low defects, low roughness and high yield at device mass production level
CORP IR / October 12, 2021

114

MOR Wet Resist Process and Dry Resist Process Cost Comparison
Resist Process Cost Comparison
Threefold cost difference
Post drydevelopment
contamination
removal process

Dry development
Post exposure bake
Post CVD metal
contamination
removal process

Resist coating,Bake,
Development

CVD deposition

MOR wet resist process:Wet coating +Wet development

Dry resist process:
CVD deposition +Dry development

Dry film deposition and dry
development process CoO
is around three times higher thanfor wet coating and development
TEL estimates

MOR wet resist process is superior to dry resist process (CVD＋dry development)
not only in terms of operational advantages including cost, TAT, queue time management,
equipment footprint and power consumption, but the wet process also
demonstrates superior data in terms of process performance
CORP IR / October 12, 2021

115

EUV Lithography Process Roadmap and Challenges
Line pitch (nm)

34

32

30

28

26

24

22

20

Hole pitch (nm)

42

40

38

36

34

32

30

22

Trend of EUV
exposureequipment andresist technology

RLS trade off

0.33 NA EUV

0.55
NA(High-NA
EUV (高NA
EUV：高解像度化）
0.55 NA
EUV
EUV:
Higher resolution)

Chemically Amplified Resist (CAR)
Metal Oxide Resist (MOR)
Defects induced by variation in EUV
lithography

Issue of securing required resist film thickness

Sensitivity (S)BridgePinching

Post-etch
resist damage

Resolution (R)CD Variation(L: Line Edge
Roughness)

Missing

Kissing

P. De Bisschop, Proc. SPIE, 10957-10 (2019)

CORP IR / October 12, 2021

Challenges
for Thinning
Resist Film

Resist line
collapse

Resist pillar
collapse

Residue inside hole

Challenges for
Thickening
Resist Film
116

Preparing for High-NA EUV Generation:
Working with Partners to Address Challenges

Inline coater/developer into
high-NA EUV exposure tool
Plan to build nano patterningtechnology with high-NA EUV
in cooperation with
imec and ASML

CORP IR / October 12, 2021

https://www.tel.com/news/topics/2021/20210608_001.html

117Preparing for High-NA EUV Generation:
Demonstration of Nano Patterning with MOR
After lithography

24 nm pitch 12 nm line
After lithography
Resist film 20 nm
ResistAfter etch

After etch

EUV
exposure
pattern

Intermediate layer

Underlayer

Source: imec

SiO2
TiN
SiO2

Source: imec

CD (nm)

12.7

12.1

LER (nm)

2.13

1.56

LWR (nm)

2.88

1.94
imec standard SEM recipe, demo with NA0.33

Wet development achieves 12 nm line pattern without collapse
with roughness (LER/LWR) of less than 2 nm
CORP IR / October 12, 2021

118

Summary Realize new technology for EUV utilizing
Chemically Amplified Resist (CAR) by the synergies
between lithography and etch Introduce Metal Oxide Resist (MOR) technology
for mass production.
Achieve high performance/low cost process.
Perform both CAR and MOR in one system
 Toward high-NA EUV lithography technology,
collaborate with partners and provide
leading-edge coater/developer process solutions
for the mass production of future generationsof devices
CORP IR / October 12, 2021

CLEAN TRACK™ LITHIUS Pro™ Z EUV

119

Latest technological challenges and TEL’s activities in etch
October 12, 2021
Isamu Wakui
VP & General Manager, ES BU

CORP IR / October 12, 2021

120

Etch System Strategy
 HARC process– 3D NAND (multi-level contact, word line isolation), DRAM (capacitor):
Continue to differentiate through process performance and productivity– 3D NAND (channel): Launch new systems that candifferentiate by providing both precise process controllability
and even higher productivity

Multi-levelcontact

 Patterning process– DRAM: Differentiate with reduced manufacturing costs
for customers through process control and combining
etch steps

Word line
isolation (slit)– Logic: Differentiate through integration of etch and deposition
technologies

ChannelIsotropic etchinterconnects

 Interconnect/contact process– Apply knowledge cultivated in logic to DRAM

Capacitor

 Gas chemical etch process– Create a new market through plasma assist technology
CORP IR / October 12, 2021

Source: N. Loubet, et al., Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET

Nanosheet image:Courtesy of IBM
121

Business Opportunities in Memory
Aspect ratio 70:1

3D NAND

DRAM
Interconnects

MLC
2nd
tier

Contact
Staircase
Capacitor

1st
tier

STI

BitlineBuried gate

Word line isolation(Slit)

Channel(Memory hole)

Diameter 100 nm

Respond to growing dry etch business opportunities in NAND/DRAM
・Etch performance that corresponds with higher aspect ratios
・Contribution to improvement of customers’ productivity
CORP IR / October 12, 2021

122Multi-layering in Memory
NAND

DRAM

10 μm

New structure

Total height

8 μm
6 μm
4 μm

2 μm
0 μm
2D

3x

4x

6x

9x

1xx

Beyond next gen.

Layer counts

TEL estimates

Etch market growing due to continuing 3D multi-layering
CORP IR / October 12, 2021

123

Challenges in High Aspect Ratio Dielectric Etch
DRAM

a
b
c

3D NAND

Capacitor

ChannelSlit

Multi-level contact

Selectivity to mask

Mask etch rate:
a=b=cANecking / Clogging

B
BowingDielectric etch rate:
A>B>C
Bottom CD

C

Etch time

Selectivity: A/a > B/b > C/cDistortion / Bending

Selectivity to metal layer

Depth loadingCDvariation

CORP IR / October 12, 2021

124

Solution Aspect Ratio Etch
90°

θ

Ion

Results of TEL’s technology:
 Precise process control forhigh aspect ratio etch

90°

θ

+

+

Mask

 Improved etch rate due toreduced depth loadingθEtch layer

Ion penetrates deeply

Realize higher aspect ratio etch process through TEL’s original
ion angular distribution control technology
CORP IR / October 12, 2021

125

Enhancing Productivity
Features of the EpisodeTM UL Flexible layout– Select flexibly from 4 to 12 chambers

 Space saving– Significantly reduced footprint per chamber

 Smart tool
– Autonomous process control throughbig data analysis

FLEXIBLE LAYOUTSPACE SAVING

Introduction of new platform (for both memory and logic)
contributes to enhancing productivity
CORP IR / October 12, 2021

SMART TOOL

126

Business Opportunities in Logic

Interconnects

FinFET

GAA*1 Nanosheet

Self-aligned Contact

Contact

Gate
Fin

STI
*1 GAA: Gate all around*2 SAMP: Self-aligned multiple patterning*3 PDN: Power delivery network

SAMP*2

Backside PDN*3

Respond to changes in device manufacturing and EUV lithography for further scaling
CORP IR / October 12, 2021

127

Etch for EUV Lithography
Pattern after EUV lithography

Challenges in etch for EUV

Pinching

BridgeKissing

Missing Large defects and variationcompared with ArF
Source: S. Morikita, et al., Tokyo Electron Miyagi (DPS2018)

 Extremely thin, low resistance to plasma
Effect of dry etch on EUV resist

Compensation by etch technology
becomes important
CORP IR / October 12, 2021

128

Etch Solution toward EUV Lithography Combining deposition and etch to improvevariation

TEL’s initiatives
 Improve post-lithography variation
by repeating deposition and etch processes

cycle

InitialAfter etch

 Improve mask selectivity by leaving filmon resist Leverage collaborations with imec and
ASML and realize patterning solutions
for high NA generation

Improved selectivity by deposition on resist
followed by plasma treatment
Post lithography

Post dep treatment

Combining deposition and etching to improve variation and etch selectivity
CORP IR / October 12, 2021

129

Initiative for GAA Nano Sheet Structures
Nano Sheet process challenges:

Si/SiGe cavity etch

SiGe Release Uniformity in rectangle shape Mitigation of roughness/residue
on patterned surface
SiGe

TEL’s initiative: Gas chemical etch
 High etch selectivity
 High uniformity
 Residue removal/decreased roughness
Source: N. Loubet, et al., IBM, TEL Technology Center, America (IEDM2019)

Leveraging the advantages of gas chemical etch tocontribute to leading-edge processes
CORP IR / October 12, 2021

130

Enhancement of Development and Production Capabilities
Completed Miyagi Technology Innovation Center on September 22, 2021
 Lab area with partner companies
 Open innovation area

 Customer training centerTokyo Electron Miyagi’s Miyagi Technology
Innovation Center

Create innovative technologies and enhance production capabilities
through co-creation with partner companies
CORP IR / October 12, 2021

131

Role of Miyagi Technology Innovation Center
For continuing to provide customers with the finest products and services
FIL

PIL

TC

Futuretech Incubation Lab

Production Innovatech Lab

Training Center

Create innovative equipment tech

Production technology innovation

Provide world-class training

Higher efficiency, lower environmental impact
tech, low lead time tech, etc.

Next generation production technologies uniting
DX and machine assembly

Raise on-site capabilities for customers
and TEL

Promote factory-wide production technology innovation
CORP IR / October 12, 2021

132

Summary Driven by 3D NAND and patterning, a continued high level of investment in
the etch equipment market is expected Continue technological innovation for both the memory and logic in responseto changes in devices and customer needs
 Work to increase development and production capabilities toward further
market growth

CORP IR / October 12, 2021

133

TEL’s Approach to Next Generation Film Deposition Technology
October 12, 2021
Hiroshi Ishida
VP & General Manager, TFF BU

CORP IR / October 12, 2021

134

Ultra-thin Film Dielectric Process for Nano Sheet FET
Solution for thin film formation in high aspect ratio narrow spaces

Ultra-thin film dielectric film deposition
for nano sheet

Dielectric characteristics
Dielectric constant

SiC

SiBN

BN
Low

Dielectric
constant

SiN
7.0

Gate spacer
SiBCN

3.9

SiO2

SiCN
SiBN

Insulation between
source/drain and gate,
control of doping, etc.

BN, BCN

SiN
1.4

2.0

Refractive index

Inner spacer

Support sheet withequal interval
Dielectric isolation

Reduce leak currents from Si channel tosilicon substrate

Our batch furnaces provide the high quality and ultra-thin dielectric film
required in nano sheet formation
CORP IR / October 12, 2021

135

Dielectric Film Application Map: Gapfill in Narrow Spaces, Ultra-thin Film Formation
300 °CSiN(k ~ 7.5)

400 °C

500 °C

Single wafer
PECVD(under FS*)

Example ofdep-etch-dep
processes

600 °CTELINDY PLUS™ IRad™
Deposition/etch fusion
process
TEL/TEL

Lowdielectric
constantmaterial(k < 4.5)

High
Example offilm
formation
inhibition
technology

Ultra lowdielectric
constantmaterial(k < 3.0)

H2 radical

Low

Single wafer
PECVD(under FS*)TELINDY PLUSTM IRadTM

20 nm

Thickness/film quality/
coverage, integration

TELINDY PLUS™ IRad™
Adoption of new materials(under FS*)

Expanding product lineup for high quality ultra-thin dielectric film
CORP IR / October 12, 2021

*FS: Feasibility study

136Film Formation in Narrow Spaces Utilizing Semi-batch ALD
Response to challengers in 3D-NAND multi-layer stacking

Bowing(Bottleneck formation)

Void(gapfill defects)

Plasma ALD SiO2

Realize total seamlessness withcombination of film formation
inhibition and ALD

Semi-batch ALD realizes both high productivity and excellent gapfill performance
though multiple continuous processes
CORP IR / October 12, 2021

137

Scaling by Silicon Deposition: New Approach
Cost efficient solution for erosion in fin formation by batch process
Fin formation

STI formation

Sacrificial film by Epi

Chemicals cause erosion

STI formation

Realize target pattern

Opportunity for new process tosolve fin erosion

Realize new process by batch deposition through the combination with pre-cleaning
CORP IR / October 12, 2021

138

Scaling by Silicon (Si/SiGe) Deposition: Solution for Cost Reduction
Batch deposition to solve the cost challenge of multilayering by epitaxial deposition
 Logic Nano Sheet: Epi for SiGe/Si multilayering Logic Backside PDN: Epi for SiGe for etch stop layer and boron doped Si Future DRAM: Epi for SiGe/Si stack

Aiming to expand the application for batch deposition
integrated with pre-clean feature
CORP IR / October 12, 2021

139

Deuterium Annealing for Enhancing Device Reliability
Improving electrical characteristics and reliability of film in collaboration with customers
by utilizing batch furnaces with high productivity
Modification mechanism

D2

D2

HD
HD

Blocking Oxide
N-D

Charge Trap

N-D
N-D
N-D

Tunnel Oxide

N-H
NN-

N-D
N-D
N-H
N-D N-H
N-H

N-H
N-

N-

N-H

N-H bonding within tunnel oxide film is deteriorated through electric stress caused by write/erase
Improve anti-deterioration by replacing N-H bonding with N-D bonding

Realizing process condition suited to D2 processes using ultra-large batch
CORP IR / October 12, 2021

140

Technology for Surface Modification with PlasmaContribute to process preciseness and device reliability by film modification throughlow temperature plasma process
Application example

Modification from SPAi

Chemical resistance

Filling SiO2

Wet etch amounts (A)3000

wo anneal

2500
2000

SPA anneal
1500
1000

500

SPA w RF bias
anneal00

Impurity within the dielectric film formed
during the flowable CVD are removed by
the thermal oxidization process

5

10

15
20
25
Wet etch time (min)3035

Need low-temperature film modification process for the devices with low temperature resistance

Improve film quality by supplying low electron temperature, high density radicals
CORP IR / October 12, 2021

141

Technology for Surface Modification with UV Light
Improve film quality of ultra-thin film by irradiating the surface to be deposited with UV light

UVRF process

Improved film quality, interface controllability
GIXR measurement

RF Process

UV Process
Objective: Ultra-thin oxide film
formation
Process: UV lamp + O2 gas flow
Gas: O2UV Lamp: ON

Objective: Oxide film nitridation
Process: Radical Flow + N2 gas flow

Deterioration
layer(surface)

Interface

SiO2 layer

Si
layer

UV O2

TEM
HfSiO
IL SiO2

Gas: N2

O* O* O*TEM observations
DHF last

N* N* N* N*

Si sub.

RFG: ON
SiON
Si

SiO2
Si

〇 Thermal Ox 10A〇 Thermal Ox 8A● UV O2 16A

HfSiO
thickness

2.3 nm

2.3 nmIL SiO2
thickness

0.9 nm

0.6 nmExpanding application for gate dielectric film etc.,with its ultra-thin film controllability and high film quality
CORP IR / October 12, 2021

142

Hard Mask Module Solutions
Aim to achieve improved LCDU* through collaboration across BUs and products
Film Property*LCDU：Local CD Uniformity

EXIMTM

Film quality

Seek optimal
solution!

Chemical resistance
Adhesion Ｋ value
Material Composition ratio
Conv.

Stress Crystallinity
Temperature

Etching
performance
Selectivity
Bowing
LCDU

Bending Loading
Chemistry Ion Energy
Temperature
Frequency
Pulse
CORP IR / October 12, 2021

Removalperformance

CIP1

CIP2 New HM

Mold Etch

Bevel Strip

New Hard Mask

Chemical

Selectivity
DamageTactras™ Vigus™

ChemicalTemperature
SchemeSiO2
TEL/TELCELLESTATM-i

1,500 nm-thick143

Summary What is being sought from deposition technology in next generation devices
is undergoing increasing diversification

 Despite high degree of difficulty, solutions to cost are always being sought
 TEL constantly aims for optimal solutions in both performance and cost frommultiple products/technologies
 Combining pre-process, etch and modification treatment with deposition tooffer technological solutions

 Expand collaboration across BUs and between products

CORP IR / October 12, 2021

144

Notice
You may not copy or disclose to any third party
without prior written consent with TEL.
Tokyo Electron

CORP IR / October 12, 2021

145

CORP IR / October 12, 2021

146