LCWS2019 (Sendai)

SOFIST, an SOI based pixel
sensor for the ILC
SOFIST: SOI Fine measurement of Space and Time
Kazuhiko Hara
University of Tsukuba,Tomonaga Center for the History of the Universe
T. Tsuboyama, Y.Arai, I. Kurachi, S. Ono*, Takayanagi, M. Togawa (KEK),
K. Hara, S. Iwanami, H. Murayama (U. Tsukuba),
M. Yamada (TMCIT),
T. Li (Tohoku U.),M. Ikebe (Hokkaido U.),M. Motoyoshi (Tohoku Micro Tec Co., Ltd.),
and the SOIPIX collaboration*now at SONY Co.LtdVertexing at the ILC••••

Spatial resolution near the IP better than 3 µm
Material budget below 0.15% X0/layer
Low-power ASICs (~50mW/cm2)+gas-flow cooling
The first layer located at a radius of ≥ 1.6 cm- Pixel occupancy not exceeding a few %- Radiation: TID<1kGy/y, NIEL<1011 n/cm2/y

Occupancy /(20µm)2/train and the efficiencies (vs #memories)
at the innermost layer<1ms• We choose SOI monolithic, pixel size 20x20 µm
numbers are scaled from study of Mori (Tohoku U, master thesis)- store data during the train, readout them inmade for (5µm)2 FPCCD, 2014, using Guinea Pig+Mokka
between trains
0.75x1034/cm2/s @0.25TeV?
- 3 memories each for the signal charge and1.8x1034/cm2/s @0.5TeV
arrival time
3.6x1034/cm2/s @1 TeV⇒ SOFIST (SOI fine measurements of space and time)
2/21

SOI monolithic sensor
Monolithic sensor using silicon-on-insulator (SOI) technology: Lapis 0.20µm FD-SOI
Pixel nodes (in handle Si) are electrically connected to readout circuit (SOI layer) through small vias
fabricated in a conventional LSI process.

8 µmMIM cap

50-500 µm
p-Fz, n-Cz
Charged Particle

Advantages of SOI Monolithic Sensor- Bonded wafer (SmartCutTM) - sensors can be fully depleted- Commercial CMOS process is used to fabricate SOI detector- Extremely Low material budget (can thin down to 50 µm)- Easy to embed circuits on top of BOX- Low parasitic capacitance, FETs fully isolated- Very good compatibility with 3D stacking

3/21

SOFIST layout
Ultimate layout to fit inthe ILD vertex geometry

4/21

SOFIST on-pixel circuit
Separation in 3DBoth circuits are in
one chip, otherwise

Multiple memories: dead-time less data store possible
Timestamp data: distinguish hits associating to individual events- separation of beam bunches (554ns) is ideal, but separation O(1us) would help a lot
Readout all memory data (charge and time) in a column by one ADC

5/21

SOFIST in development
Ver. 1

Ver. 2

Ver. 3

Ver. 4

2016/20172017/20182018/20192018/2020

Wafer

SOI

DSOI

DSOI

DSOI

Pixel size (µm x µm)

20x20

25x25

30x30

20x20

#Charge memories

2033#Time stamp memories

0233Chip size (mm x mm x µmt)

3x3x500

4.5x4.5x75

6x6x300

4.5x4.5x300

Spatialcolumn ADC

Timecolumn ADC
zero-suppr.

Bothcolumn ADC

Both**
column ADC
3D

Produced /Tested*

Notes* Yearly test beam activities at FNALThis year is planned for SOFISTv4** timestamp function is not testable due to mis-match of
the readout and sensor wafer types

6/21

SOFIST-v1 spatial resolution
SOFIST#2(BPW16x16)

SOFIST#1(BPW14x14)
Residual X: 4

140
120

Residual X

Residual X: 5
h_resx_4
Entries1784

Mean
Std Devχ2 / ndf

0.15032.795

Constant
Mean
Sigma

100

Eventsplots are for “black case”

Eventse lsxipµm
20x20

SOFIST residual to FPIX track (s_track~0.57/0.65µm)
Bias=130V (~500um depletion) =>15V (~200µm depletion)
Readout: external 12-b ADCs =>on-chip 8-b column ADCs

200

12.1 / 9139.5 ± 5.8

1800.2746 ± 0.0553

1601.504 ± 0.054

60
4020Entries

2401

Mean
Std Dev
χ2 / ndf

0.1677

Constant

2.721
12.58 / 9227.7 ± 7.60.1668 ± 0.0386

Mean
Sigma

1401.50 ± 0.05 µm
1.57 ± 0.08 µm
1.58 ± 0.05 µm

80h_resx_5
2201.367 ± 0.035

1.37 ± 0.04 µm
1.49 ± 0.06 µm
1.33 ± 0.03 µm

120100806040200−15−10−5050−151015
Residual X [um]−10−5Residual Y

Entries

1784

140

Mean
Std Dev
χ2 / ndf

0.01972
2.825

120Constant

100

Mean
Sigma

S/N~300 (130V)~120 (15V)

16.79 / 9148.5 ± 6.40.1282 ± 0.0481
1.378 ± 0.048

1.38 ± 0.05 µm
1.55 ± 0.08 µm
1.54 ± 0.04 µm

806040200−1551015
Residual X [um]Residual Y: 5
h_resy_4

EventsEvents

Residual Y: 41600

h_resy_5240

Entries

2202002401

Mean− 0.1204

Std Dev2.694

χ 2 / ndf

11.4 / 9180

Constant

160

Mean0.06111 ± 0.03750

Sigma

1.348 ± 0.035

140231.2 ± 7.9

1.35 ± 0.04 µm
1.38 ± 0.05 µm
1.32 ± 0.03 µm

1201008060
4020−10−5051015
Residual Y [um]0−15−10−5051015
Residual Y [um]7/21

Sensors with O(1um) spatial resolutions
Spatial resolution improves with S/N as charge-weighted mean position calculation
Mostly SOI sensors in this competition
World record is 0.65µm achieved by FPIX 8um
INT4(17um)

DEPFET(24um)

SOFISTv1 (20um)
tracking error subtracted
h correction (calculation)
FPIX (8um)

FPIX residuals including tracking error
K. Hara et al., PoS(Vertex 2017)035 pdf
8/21

e lsxipµm
25x25

SOFIST-2 Time stamp resolution

SOFISTv2 for timing study thinned to 75 um

Chip-B [us]Timestamp correlation of two sensors in a beam

rampramp
timestamp

ext. 12-b ADC

Combinatorial
background due toother particles in thesame beam gate
500
Chip-A [us]Beam gate(500us) simulates
the ILC beam train

Test-in
σ=1.55us
Beam gate (500us)
ILC beam structure

9/21

SOFIST-2 zero-suppression logic
Response to b-ray (time data)

full scan

Digitised column data are examined and only hit pixels are stored in FIFO
Total scan time= AD conv. ~5 us/colmn(64) x columns(64)~320usvs 340us measured @25MHz clock
Zero-suppr. (whites are not R/O)
10/21

Time (us)3Beam-tested and under final evaluation
Laser_Hit

Laser_Hit

Time (us)1.38usIntrinsic~ 1.14 us
Calibration uncertainty~0.8us

0280 285 290 295 300 305 310 315 320

20406080100120140160

180815525
298.8
Std Dev
1.408
2c / ndf
4381 / 14
Constant2.335e+05 ± 3.216e+02
Mean
298.7 ± 0.0
Sigma1.382 ± 0.001

2200
280 285 290 295 300 305Entri310es 315 320
Mean200´10

Laser_Hit
Entries
815525
Mean
298.3
Std Dev
1.254
2c / ndf
2461 / 82
Constant2.625e+05 ± 3.712e+02
Mean
298.2 ± 0.0
Sigma
1.144 ± 0.001

1.14us

50

100

150

2002503´1020 40

20 4060 80 100 120x60 80 100 120x

TimeData2D(bottom-left) Repeatability of the ADCs (converted to us)
to 5000 pulses for all the illuminated pixels(bottom-right) Same but calibrations using simple linear
functions was used for ADC to time conversion
00

2040

60

80

100

12000

20406080100120ADC

270280

290

300

310

320

330

0200

400

600

800

1000

1200

TimeData2D
Entries 16384
Mean x 19.8
Mean y 48.69
Std Dev x 10.51
Std Dev y 11.75

AnalogData2D
Entries 16384
Mean x 56.44
Mean y 46.11
Std Dev x 27.98
Std Dev y 10.58

e lsxip
SOFIST Ver.time
3x30µm30charge
ADC

Laser_Hit

AnalogData2D

SOFIST-3: time resolution w/ laserTime resolution of SOFISTv3 was investigated by injecting
pulsed IR laser with fixed delay times

11/21

yy

250

300

350

400

450

Time (us)2hit clusters: time difference
IP15
sigma = 2.19 us2.639⁄ 2 = 1.87 us
0-20 -15 -10 -5 0 5 10 15 202040

60

80

100

120

140

160

0-20 -15 -10 -5 0 5 10 15 20

Entries2628
Mean0.05326
Std Dev2.036
c2 / ndf
18.96 / 18
Constant
546.8 ± 13.4
Mean 0.03099 ± 0.03723
Sigma
1.897 ± 0.028

residual_Time_IP11_IP15_2
Entries
1122
Mean
1.159
Std Dev
2.82
c2 / ndf
16.54 / 18
Constant
167 ± 6.2
Mean
1.209 ± 0.080
Sigma
2.639 ± 0.058

residual_Time_IP11_IP15_2

5 10 15 20100200300

400500Cluster_residual

Cluster_residual

IP11
sigma = 1.90 us

0-20 -15 -10 -5 050

100

150

200

Cluster_residual
Entries2364
Mean0.004451
Std Dev
2.297
c2 / ndf
20.21 / 20
Constant
426.7 ± 11.0
Mean 0.01177 ± 0.04522
Sigma
2.187 ± 0.034

Cluster_residual

SOFIST-3: time resolution in TB
Time resolution of SOFISTv3 evaluated from timedifference of two sensors

Time (us)Time resolution <2us is demonstrated from test beam data
12/21

SOFIST-4: 1st 3D stacked
SOIPIX sensor
SOFIST Ver. 3

SOFIST Ver. 4
Lower chip

Upper chip

Comp20 µm

AVdd

AGnd

SignalBeam-tested and under final evaluation

CompAVdd

AGnd

Signal13/21

SOFIST-4

3D stacking

3D stacking of SOI chips (chip-on-chip)→Electronics circuits in two chips are fused using cylindrical microbumps to extend the circuit functionality in limited space

Tohoku MicroTech
Pixel size: 20 x 20 μm
Under bump metal: 4 x 4 μm
Cylinder bump: 3 μmφUpperLowerchipSensor

2 bumps + 2/2 for power&return

14/21

Process flow of Au cylindrical bump
Key Technology : inverse-tapered photoresist& low incident-angle Au sputtering

Processed by T-MicroBump Resistance

Au Cone Shape Bump

0.3~0.4W/connection
Cross section of junction

15/21

Response to b source#pixels

ADC
16/21µ-bond yield by b source
#Hits
#Hits

50k event accumulation

Pixel ADCnoisy
No hit# bond failures : (2~4) of 102 × 102
𝒈𝒐𝒐𝒅 𝒃𝒐𝒏𝒅𝒔~𝟗𝟗. 𝟗𝟔%

Bump bondfailure
Genuine channels
Preamp failure

VOUTVSF

1717/21

Concepts for chip-on-chip connections
In the case of SOI chips …
Si

Back Side
Upper
Chip

BOX
Metal
LayersFront Side
Metal
Layers

Lower
Chip

BOX
High R-Si

Note: Renesas’ 65 nm TB-SOI and ST’s 28 nm TB-SOI
also utilize “through BOX via” technology

Etch down Si andpads are placedfor WB:
Relatively thick(150-200nm) BOXof Lapis helps
terminate etchingas required
Inject epoxy forreinforcement

Typical concepts for electricalconnections between front andback sides
Back Side
Through Silicon Via (TSV)size ~5 µm, complicatedThrough BOX Via (TBV)
Oursize ~0.3 µm, simple technology

Front SideCu-Cu direct bonding (SAB)
require quite flat surfaceµ-Bump Cu/Ni/SnAgIn
Au (cone, cylinder)oxidation-resistant metal
18/21

Advantages of SOI micro-bump bonding• Requirement on the surface flatness is moderate, as the height of the cylinders
can be self adjusted by deformation: a few µm tolerance.
cf. Cu-on-CU 3D• Soft cylindrical gold bumps result in high-connection yield, as shown.
• No TSV , but Through BOX via (TVB) are processed in the SOI CMOS circuit
processes. Fine TVB (0.3um) can be fabricated..
cf. TSV 3D
Si• Relatively thick BOX (150-200nm) easies top
silicon removal etching process• Upper chip: Only CMOS circuit below SiO2 remains.
- The remaining thickness is about 8 µm.

• Circuit chip has SiO2 layers on both sides:
stacking can be further repeatedSOI and 3D are in very good compatibility

High R-Si

19/21

Rad-hardness of adhesive glue
Upper Chip Peeled Portion

Proton irradiation : 400 kGy(5×1014 cm-2 in 1 MeV neutron equivalent)

Before irradiation

After irradiation

No obvious damage was observed
even though the dose level is threshold to create Si displacement defects.
An test chip from process condition tuning was evaluated. The upper chip had some peeled edges but still good enough to evaluate glue damage.

- Color difference is due to lighting

20/21

3D design tool• Virtuoso with dedicated rule files.
• Virtual layers are automatically generated between upper and lower chips that unify
the chips geometrically and logically.
• DRC (design rule check) and LVS (layout versus schematic) can be applied for thewhole pixel system.

3D can be designed as for conventional SOI
MET5 (upper)
Upper-tierport

PV (upper)： VIA
ZC1 (upper)： Bump

Upper chip
LayoutSpecial VIA Gen.

Layout

DRC, LVS

LVS1(Virtual connect)

DRC, LVS

ZC5 (upper)： Bump ID
ZC6 (lower)：Bump ID
Lower-tierport

ZC1 (lower)： Bump

Lower chip

Stacking

Special
DRC/LVS rule

Stacking

Unified
DRC＆LVS2

Dummy Gen.

PV (lower)： VIA
MET5 (lower)

21/21

Summary• In the past 7 years, we have been developing SOFIST for the ILC vertex tracker• Excellent performance has been demonstrated on the spatial and timestamp resolutions,verifying superiority of SOFIST as a deadtime-less device recording timestamp at O(1us) precision
over the ILC train duration. Column ADCs, sensor thinning to 50um have also been verified.
• 3D stacking allows to keep the pixel size small (20x20um). SOI is in very good compatibility to the3D stacking.
However, to adopt SOFIST to the ILC vertex- Power consumption needs to be lowered. As the demonstrated detector performance is wellwithin the requirements, compromise of the preamplifier speed (hence power) is foreseen.
- Periphery circuits to analog power-off in between trains, to transfer digitized data, and etc., withmicro-channel cooling incorporated are to be investigated.
- have a full size chip
Acknowledgements:
JSPS Grant-in-Aid for Scientific Research on Innovative Areas (No. 25109006) 2013-2017
Japan/US Cooperation Program in the Field of High Energy Physics 2016, 2018-2019
FTBF- FNAL test beam facility
CYRIC (Tohoku U) for proton irradiation
VDEC (U Tokyo) in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Mentor Graphics, Inc.

22/21

Lapis is the closest foundry to ILC
T-Micro is in Sendai
Proton irradiation at Tohoku U

ILC
LAPIS semiconductor

Tohoku Microtech

https://mapandnews-japan.com/mapsearch_touhoku.html

BackupPower dissipation
Current SOFIST: preamp + NMOS SFs: (2.75 uA) x 64 x 64 pixels x 1.8 V ~ 13mW ⇒0.86W/full chip⇒126W/146chips
or 138mW/cm2
We started investigating ALPIDE type low power preamp**Comparison of preamp characteristics
Parameters

SOFIST

ALPIDE for SOI*

Preamp Gain

40 μV/e-~4 mV/e-Sensor capacitance

34 fF

3 fF

Pixel power

2.75 μA/cell

80 nA/cell*50um depletion*i_reset 0.2nA

From TDRCMOS 600W⇒10W by 2% duty cycle – air cooling
FPCCD 35W inside the cryostat (50um CFRP sheets) – two-phase CO2 cooling
DEPFET – air coolingFor 10W for the entire barrel（S~1600cm2) ⇒6.3mW/cm2 ?
25/21

3D stacking (1) TSV• For the commercial image sensors, the first trial is to move theperipheral circuits to the second chip and stacked by using TSV, throughsilicon via.

LogicMemoryPixelPixelMemory
L og ic• This is not an answer for HEP. We have to increase the performance ofcircuit in each pixel. Pixel-by-pixel connection is necessary.
• Parallel data processing.
• Low power operation thanks to minimum parasitic capacitance.

3D stacking methods (2)Direct Bonding Interconnect• Two wafers are prepared.
• The bonding surface is flattened andcleaned.
• Aligned and attached. Applysuitable pressure and heat for thediffusion bonding of pads.
• SiO2 surfaces is also fused, resulting
in the stable structure.
• Widely used for the mass
production of high-end image
sensors.

From the slide of Valerio Re,
Vertex2018