TOKYO ELECTRON ANNUAL REPORT 2018

PAGE9CONTENTS

To Our Stakeholders

Business Overview
and Financial Highlights

Innovation Drives the Evolutionof Semiconductors

Review of Operations
and Business OutlookInterview with the CEO

Corporate Governance

Financial Section
Investor Information

Innovation Drives the Evolution of Semiconductors

Innovation Drives the Evolution of Semiconductors

Semiconductor Production—A History of Innovation
In 1965, Dr. Gordon Moore, one of Intel’s founders, made aprescient observation that eventually became Moore’s Law.
Six years later, Intel released the world’s first commercial
microprocessor, the Intel 4004. Over the following half century, through repeated technological innovation, semiconductor performance has continued to improve, with steadily
higher circuit density realizing improved performance, suchas increased capacity, speed and power efficiency.
Figure 1 illustrates the evolution of logic devices since
2000. In early planar poly-gates, strained silicon technology
was introduced to improve channel mobility. Later, high-k1/
metal gate technologies were introduced to reduce current
leakage that arose due to miniaturization. To enhance patternfidelity, circuit design transitioned from 2D layouts to combinations of simpler 1D layouts (Figure 2). As miniaturization
continued beyond 45 nm, multiple patterning technologies
were developed to compensate for the limits of lithography
resolution, and FinFET structures were adopted to reduce
short-channel effects. Going forward, with the advent of
5-nm technology and beyond, logic devices are expected toevolve into nanowire structures. In memory devices, the useof capacitors and transistors with 3D structures in DRAM
have driven continued miniaturization, and the switch fromplanar NAND flash memory to 3D NAND has sidestepped thelimits of miniaturization (Figure 3).
Through the combination of new designs and materials
and the creation of new production methods, semiconductors have continued to evolve. Today, production technology
is approaching the physical limits of miniaturization, at theatomic level. The world’s first commercial microprocessor,
manufactured with 10-micron technology, contained
approximately 2,300 transistors per chip. In contrast, thelatest mass-produced chips—products of 14-nm technology—boast well over a billion transistors per chip. The gate
length on these chips is approximately 20 nm, and thewidth of the fins (the channels) is just 8 nm. Going forward,
each successive technology node will entail miniaturization
by a few nanometers, or the size of ten or so atoms.
Manufacturing such devices will require atomic-level control.
1 High-k: High dielectric constant film

Technological Barriers toMiniaturization
Miniaturization in semiconductor production is now facing
new hurdles. The first of these is photolithography resolution, a challenge that has emerged in recent years. Until now,
miniaturization has advanced by using shorter wavelength
light sources in exposure equipment to increase resolution.
Today, however, the shortest wavelength available for use
in mass production is 193 nm, more than 20 times the width

Figure 1. The Evolution of Logic Device Transistor Structures

Planar poly-gates
Structure diagrams

Planar metal gates(45 nm and beyond)

FinFET(22 nm and beyond)Nanowire (5 nm and beyond)

To solve these challenges, a number of breakthrough­production technologies are beginning to emerge.

A ­well-known example, which is already widely used in mass
production, is multiple patterning technology. This approach
uses process technologies—such as deposition, lithography,etch and cleaning—to supplement the resolution of exposure equipment. Patterns with several times the density
achievable by the lithography resolution can now be formedby employing the litho-etch method, in which lithography
and etch processes are performed repeatedly, or selfaligned patterning, in which repeated deposition and etchprocesses are performed after lithography. These technologies are expected to see continued application in coming
technology nodes. In addition, technology known as selfaligned block (SAB), which increases tolerance for placement variance in lithography, is currently being developed.
By taking advantage of differences in etch selectivity bymaterial, this technology is expected to enable the processing only of the desired materials without the need for
improved performance from exposure equipment.
To realize these patterning technologies, the further
refinement of production technologies for each unit process
is indispensable. These include atomic layer etch (ALE) andatomic layer deposition (ALD), which control etching anddeposition at the atomic level (Figure 4), as well as drying
technologies to prevent pattern collapse caused by cleaning chemicals. In addition, the unit processes that give thebest performance individually do not always achieve thehighest yields when combined. This means that integration
technology, aimed at optimizing unit processes to one

Figure 2. The Evolution of Logic Device Circuit Design

Figure 3. The Evolution of NAND Flash Memory

the aforementioned fins. The use of immersion lithography
technology, in which exposure is conducted in a liquid medium with a high refractive index, helps to improve resolution,but even this is insufficient to achieve the desired results.
On top of this, aligning photomasks and wafers duringpatterning is also a challenge. In the latest logic and DRAM
devices, transistors and other logic circuit elements are not
only small, but arranged in complex configurations. If exposure alignment is off by a distance of just ten or so atoms,
the densely arranged circuit elements will be interconnectedinaccurately, leading to declines in processing precision.
Furthermore, at high-volume manufacturing sites, noisethat always has a certain probability of occurring is becoming
a more pronounced issue. The errors caused by such noise
might not be problematic when lithography and etch processes are conducted just once. However, when lithography andetch processes are conducted multiple times on the samelayer, these errors accumulate, leading to reduced yield. As
miniaturization advances, these three challenges are expected
to become even more serious. Solving them will be crucial toadvancing to the 5-nm technology node and beyond.

Breakthroughs inProduction Technology

2D layout
One unit cell
(SEM image)

1D layout
One unit cell
(SEM image)

Planar NAND flash(down to 15 nm)

Cross section(SEM image)3D NAND flash
T. Ghani, et al.,
IEDM 2003

K. Mistry, et al.,
IEDM 2007

C. Auth, et al.,VLSI tech. 2012

R. Coquand et al.,VLSI tech. 2013

Devices evolved through changes in transistor materials and structure.
Manufacturing requires atomic-level production technology.

One atomIllustrations of devices viewed from directly above
SEM image source: Kelin J. Kuhn, IEDM 2007

Miniaturization continued
by changing to simpler, 1D layouts.

The method of increasing density changed
from planar miniaturization to vertical stacking.

TOKYO ELECTRON ANNUAL REPORT 2018

PAGE

10CONTENTS

Business Overviewand Financial Highlights

To Our Stakeholders

Review of Operations
and Business Outlook

Interview with the CEO

Innovation Drives the Evolutionof Semiconductors

Corporate Governance

Financial Section
Investor Information

Innovation Drives the Evolution of Semiconductors

Innovation Drives the Evolution of Semiconductors

another, will only grow more important. Tokyo Electron
provides equipment for a wide range of processes.
Leveraging this strength, we are beginning to aggressively
develop and offer integration technology solutions.

In addition to pattering technologies, EUV, a new type oflight source for lithographic exposure, is approaching commercialization. In particular, the use of EUV in litho-etch
processes (as explained above) is expected to reduce theFigure 4: Atomic Layer Etch (ALE) and Atomic Layer Deposition (ALD)

ALE

ALD

A gas is adsorbed to the wafer surface, then the excess gas ispurged and the adsorbed gas is reacted with another substanceto etch the exposed atomic layer of the wafer. This process isrepeated as many times as necessary.

A gas is adsorbed to the wafer surface, then the excess gas ispurged and the adsorbed gas is reacted with another substanceto deposit an atomic layer on the wafer. This process is repeated as many times as necessary.

number of masks needed per layer, reducing placement
error and thereby increasing yields (Figure 5).
Tokyo Electron is working with exposure equipment­suppliers, consortia and other partners to develop coater/developers for EUV lithography. We report our progress
every year at SPIE Advanced Lithography, the world’s­largest lithography conference, as we strive toward theadoption of EUV in mass production in the semiconductor
industry. The combination of patterning technologies andEUV is now pushing miniaturization toward the 5-nm
technology node and beyond.

Purge
Surfacemodification(a)
Next cycle

ALEt2(b)Ligandexposure
Reaction

AI(CH3) 3 pulse

H2 O pulse

Thermal/Purge
Release(d)Beyond Miniaturization

Repeatcycle
N times2	TS Böscke, et al., “Ferroelectricity in hafnium oxide thin films,” Applied Physics Letters 99, 102903(2011)

Purge(c)Colin T. Carver, et al., ECS J. Solid State Sci. Technol.
2015 volume 4, issue 6, N5005-N5009; doi: 10.1149/2.0021506jss

excel in performing complex calculations on large volumesof information and are expected to be adopted in data
center servers and similar electronics.
These new devices can only be commercialized throughthe application of existing semiconductor production
technologies. Tokyo Electron is focusing not just on ways
to continue miniaturization, but also on the technologies
that will be required for continued evolution over the longterm. In addition to our independent R&D initiatives, weare beginning to build an ecosystem for collaboration withconsortia, academia and other equipment and material
suppliers around the world. By creating new production
technologies, Tokyo Electron will contribute to the continued evolution of semiconductors.

Säynätjoki 8 May 2012, SPIE Newsroom.
DOI: 10.1117/2.1201204.004218

Column 01
Types of Multiple Patterning Technology
Multiple patterning technologies are broadly divided into litho-etchcontacts to connect transistors and wiring, vias to bridge the spaces

methods, in which lithography and etch processes are performed

between wiring, cuts to break lines formed by self-aligned multiple

repeatedly on the same layer, and self-aligned patterning methods,

patterning, and blocks to fill spaces. Self-aligned multiple pattern-in which repeated deposition and etch processes are performed

ing, meanwhile, is useful for reducing the pitch of periodic line-after lithography. Litho-etch methods enable patterning density

space patterns. These techniques achieve patterning equivalent toequivalent to that achievable based on the resolution of thetwice the lithography resolution when performed once, and four

lithography equipment multiplied by the number of litho-etchtimes the lithography resolution when performed twice, which isrepetitions. This approach is well suited for reducing the pitch (thewhy these approaches are referred to as double patterning (SADP)

distance between features) of masks, such as those for formingand quadruple patterning (SAQP), respectively.

Having reached the atomic level, semiconductor miniaturization is gradually approaching its physical limits.
Nevertheless, semiconductor performance will continue toimprove. Going forward, technological innovation will continue to advance in forms other than miniaturization.
In memory devices, ferroelectric memory (FeRAM) has
been seen as a promising new type of memory sinceresearch on scalable ferroelectric materials was publishedin 2011.2 In logic devices, research has begun into neuromorphic computers that employ new architectures known
as non-von Neumann as well as quantum computers,
which utilize quantum-mechanical phenomena.
Neuromorphic computers require less energy to send electric signals than conventional devices. Because of thisproperty, they are expected to reduce the power consumption of devices and be particularly suited to wearables
and small IoT-related electronics. Quantum computers

Figure 5. The Advantages of EUV Lithography in Litho-Etch
Multiple Patterning Processes
Conventional multiple exposure: (Litho + Etch) × n times2113

Each exposure
process creates
placement variance
Decreased yield

Ex: n=3 times

Single exposure using EUV: (Litho + Etch) × 1
1111

Placement varianceeliminated
Increased yield

Column 02

Litho-etch multiple patterning: Limited use of etch and deposition

Neuromorphic Computers
Neuromorphic computers are made by building chips that contain circuits
Lithography 1

Contact hard mask etch 1

Lithography 2

Contact hard mask etch 2

Lithography 3

Contact hard mask etch 3

that mimic human brain cells—neurons. When trained, these artificial
Synapseneurons create synapses as they connect to one another, eventually

Self-aligned multiple patterning (SAMP): Performing etch/deposition numerous times
1pp
2 SADP

1p4

forming a neural network. Compared with conventional semiconductor
SAQP

devices, such chips are expected to be more energy efficient. Moreover,Neuron

if one neuron fails, its operation can instead be performed by another ofMandrel A etch

Sidewall deposition 1

Sidewall etch back 1

Hard mask etch

Mandrel B etch

Sidewall deposition 2

Sidewall etch back 2

the many neurons on the chip, making these chips highly reliable.

Conceptual illustration of a neural network