東海大学紀要情報通信学部
vol.3,No1,2010,pp.19-24

論文

ASIC16bitCPU ㍸⇙݆‫ ݦܬܥ‬PBL ݉᣼ಏᒜቡከ োၽ*1

।㏮ ៖Ꮩ*1⬤൨஖ሦ*1ᴫᰟ ሦᐓ*2

Effectiveness of PBL in ASIC16bitCPU Ddevelopment
byRyotaRyota
YAMAZAKI,KAMIKAGE,
KatunaoToraguti
TORAGUTI
Naohiko
SHIMIZU
YamazakiTosihiro
㤇Tosihiro
Kamikage㤇Katunao
㤇andand
NaohikoShimizu(receivedMay
2010 && accepted
accepted on6,62010)(receivedon onMay
㤉88,
㤇2010
on AugustAugust㤉㤇2010)

Abstract
Experiment on a CPU system development is a good method to learn the detail of the software behavior㤇and it is required in recent years
with popularity of the programmable logic㤉But the development requests learners a broad area of knowledge that cannot be acquired in theusual lectures㤉Therefore㤇we selected the PBL(Project-Based Learning) for the development to get the knowledge of the covering area㤉

We executed the education program for the students who have the fundamental knowledge of the computer science to propose the system
exhibiting at the ASIC design contest of PARTHENON society㤉The proposition of the system is excellent method to learn the foundationof the development and the principle of the CPU for students㤉

Keywords: ASIC design contest㤇PARTHENON㤇PBL(Project-Based Learning)㤇CPU system development learning‫ޜߏ߂ߏހ‬: ASIC ‫ޛތޙ߆ކ߆ݷމޚ‬㤇‫߆ޡޙ޾ޤ‬㤇PBL(ު߀‫)ރ߆ޞߏ޼ߎޜތߏެߎޛނݺދ‬㤇CPU ‫⇙㍸޳ޙތފ‬ᆟ❍‫ݦܨ݂ܧ݃ܮݦܬ‬㤉ᤓⷮ៶݆‫ ݦܬܥ‬PBL ݉∦⇡݊ CPU ‫ޙތފ‬1.

޳㍸⇙݆‫݁ܟܥ‬፷ྷ݆‫ݦܝ݂݃ܮݦܬ݆ܿ⿅ݭ⹀⊳ݦܺݪ‬㤉݊ܳ‫݆ݜ‬CPU ‫⇙㍸޳ޙތފ‬ᆟ❍݊‫݉ݵݺݹޛިސ‬᣷‫◩ݝ‬చ೗ܲܺẙ݉

3.

ᆟ❍݆᣼ಏ݂‫ݥܝ‬㤇ު߀‫ܧތݷޣޚ޾ީޱ޼ރ‬ᢘ൓ܲღ‫ݦܟ݁ݜ‬と፪݂݊ᑙ㓼݉ᆟ❍݂‫ݦܝ‬㤉CPU ‫⇙㍸޳ޙތފ‬ᆟ❍݉แ㔩ẙ݃

ASIC ‫݉ޛތޙ߆ކ߆ݷމޚ‬᪜ⴎ
16bitCPU ൓‫ܟⱓݭ⇙㍸݉޼ݷޤ߆ކݎ‬㤇ⷮ⁊ංᗣᐴ᳢݉⻉㑒ܲ݁㤇CPU ㍸⇙݊ⴗ᫶‫ܧ‬ၺ‫ܪܨ‬㤇ᆟ❍‫ܧ‬㑅ܲ‫ܡⵐ݃ܟ‬ẙ‫ܭܝܧ‬౹݃෉৮ఁ⁊ᡸ㍾‫ܡ⑼ݭ‬㤉ⴗᇇ݃ܲ݁ CPU ‫݊޶ޔނޙހߏݵ‬㤇‫ݦݧݤ‬㤉ܸ‫݂ܮ‬㤇ᗤ۸݊ CPU ‫݉⇙㍸޳ޙތފ‬ൎ❩݃݅‫ޙ߆ކݦ‬෉৮ߎ‫␬ތ޿ޜݵ݉ޒߏޚ‬㍾‫ݭ‬చ㑄ܲܺ‫ނޙހߏݵޜߏޣߏޢ‬‫ޛތ‬᫯ᵺ޵‫⃱ܧ޾ޚ‬ᔺܰ‫ݦܟ݁ݧ‬Ὤᇇ㒋๻మ᳀ತᲆ৑‫ޡޙ޾ޤ‬‫ݥܝ݂޶ޔ‬㤇1 ߂ߏ‫ ޜ‬1 ‫ݦܝ݂߆ފޱޜߏ߂݉ތ޿ޜݵ‬㤉ၤ៪݊߆⋌␩਒݉ ASIC ‫ ޛތޙ߆ކ߆ݷމޚ‬1) ‫ܧ‬ᆟ❍݆ボܲܺ㔩ᤩ݂޴޵޽।݉ 1 Ωམ‫ݤܦ‬㓺݆ᦾ◍ܰ‫ݦݧ‬ၺྷၤ៪݉ a ‫ ݤܦ‬z ‫݂ݙ‬‫ܣ❩݃ݦܝ‬ョᙁܲܺ㤉ASIC ‫ⴗ݉ޛތޙ߆ކ߆ݷމޚ‬ᇇ݆ᐺ‫ފܟ‬݃㤇㎈៪Ꮦ៪݉ arg ‫ݦݧܰ⵳ܧ‬㤉ၤ៪݆݊ᴧᆔ‫݂ܧ݃ܮݦܬܿݭ‬‫݂݃ܮܡⱓݭ⇙㍸޳ޙތ‬㤇‫݆޳ޙތފ‬ᬝ⟼శ㏚‫ܬܦݭ‬㤇CPU ᫂‫ܨ‬㤇ㅢద a[i] ݊㤇a ‫ ݤܦ‬i Ωམ݉޴޵޽।݉૎‫ܴⱩݭ‬㤉㎈៪݊៬ᗣ㤇‫޳ޙތފ‬᫂ᗣ‫ݭ‬ഌ◓೗ܲᆟ❍݆ボܲܺⴗ᫶݉㍸⇙‫ݦܣⱓܧ‬㤉៪ྌ‫ܦ‬㤇void ྌ݉ foo ݃‫ܡܟ‬㎈៪ඇ 1 ܻܿ‫ܧܬ‬ᇇ✶݂‫ܨ‬㤇ቁᘄᗤ ۸ ݊ ‫ ⇙ ㍸ ޳ ޙ ތ ފ‬ᆟ ❍ ᠘ ᲆ ݃ ܲ ݁ 㤇PBL(Project-Basedၤ៪݊ᆕདܲ݅‫ܟ‬㤉৲Ꮦ៪݊ arg ‫ݭ‬㤌ܻܿ‫ܬ‬੕⃱݂‫ܨ‬㤉᷀ⓝ݂݊Learning) ‫ܟ⃱ݭ‬㤇অ݆ᆟ⃩㍾݂แ㔩᛿⹍‫ܲݭ‬㤇ⵁ᱋᠘ᲆ݉᛿

+㤇−㤇<㤇>㤇>=㤇<=㤇==㤇++㤇−− ‫ܧ‬㤇᫂៶݂݊ while㤇if㤇ᧈ‫ݭ‬៟ฆ‫ݭ‬඘‫ݜ‬னฆ݂ⱓܾܺ㤉৯॥, ࿧දܴ‫ݦ‬㤉else㤇for㤇return㤇halt ‫ܧ‬మ⃱൴⟼݂‫ݦܝ‬㤉݅‫ܥ‬㤇halt ᇋⱓᡸ݆݊ު߀‫ݦܴުޖޛތݭވޖގ‬㤉‫ޛތޙ߆ކ‬ህᦞ៪૎݆݊㤇ᇋⱓᡸ㍾2.

CPU ‫ ⇙㍸޳ޙތފ‬PBL ݉Ὤᑒ݃∦⇡݅‫݆ݎݤ‬ᇋⱓ‫∬݉ߏށ޾ޠݻ‬খ፩ཥ‫ݭ‬੕⃱ܴ‫ݦ‬㤉CPU ‫ ⇙㍸޳ޙތފ‬PBL ݊㤇㍸⇙ު߀‫ݭތގ‬ᇋ⽞݂‫ܨ‬㤇㍸⇙ᘍ4.

㓺‫݂ݮ⽪ݭ‬㤇แ㔩᛿⹍‫ⵁݤܦ‬᱋‫݂ݙ‬ज़⺻ܲ݁൝‫ݦݜ◸ݥ‬మẙ‫ܝܧ‬‫ݦ‬㤉㍸⇙‫ݭ‬ᇋ⽞ܴ‫݂݃ܮݦ‬㤇ᆟ❍݉∦᫯‫ݭ‬ᗣᥟὣ݆‫ܾ݁ݣ‬ᡐ⌚݆ᇋ᠚ヅ⏣㍸⇙ᘍ㓺‫ݥܺܝ݆ݛ⽪ݭ‬㤇‫ܵݙ‬னฆ݉࿇⍋⊳⹀‫ܺܲⶸ⌚ݭ‬㤉ܸܴ‫ݦܨ݂ܧ݃ܮݦ‬㤉‫ܺݙ‬㤇㍸⇙ᘍ㓺‫݂݃ܮݛ⽪ݭ‬㤇CPU ⵱ⵖ݆݉ᐴ㤇㍸⇙‫ݜܳ݊ݭ‬㤇CPU ‫݉޳ޙތފ‬᛿ᧈ‫ܾܺⱓݭ‬㤉CPU ‫ތފ‬ᑙⴎ݅ CPU ݉᫂ᗣ‫ݟ‬ತ਽㤇‫݆ⵖ⵱޼ݷޤ߆ކ‬ᑙⴎ݅‫޼ީ߆ގݵ‬‫ ⇙㍸޳ޙ‬PBL ݉ᇋ᠚ᤋ㍾݊ギ 1 ༛㤇ᛎ᪈ᡸ㍾‫ݭ‬㤔㤋చ݃ܲ݁ 10‫޳ލ޽އ޾ݵ݉޼ݷޤ߆ކݟ⹀⊳݉ޜߏކ‬㤇‫݆ⵖ⵱޳ޙތފ‬ᑙⴎ᣻ ∼2 ᣻‫ܾܺⱓ݂ݙ‬㤉ভଚ៟⟓݃ܲ݁㤇CPU ᤓ਴݃‫޼ݷޤ߆ކ‬݅ⷮ⁊ංᗣ݉⊳⹀‫ݭ‬ᆟ‫ܨ݂ܧ݃ܮݑ‬㤇CPU ‫݆⇙㍸޳ޙތފ‬ᑙⴎ݉ᆟ❍‫ ݭ‬2 ߉᣻㍾݃ܲ㤇᣷న݉ギ݆แ㔩᛿⹍݉⹍ⷮ‫ܟⱓݭ‬㤇ᮀ݅፷ྷ݆‫ݦܨ݂ܧ݃ܮݦݧⵃ݆⹀⊳ݦܺݪ‬㤉ܰ‫݆ݤ‬㤇แ㔩᛿⹍‫ܦ‬݉ギ݂แ㔩ⵁ᱋݉⹍ⷮ‫ܾܺⱓݭ‬㤉‫ܵݙ‬㤇10 ᣻݊ CPU ᤓ਴݉ᆟ‫ⵁݤ‬᱋‫݂ݙ‬ൎ౼❫⢅⿅݂൝‫ݜܺݦݜ◸ݥ‬㤇⢅⇙⇡݆⊳⹀‫݆ܿ⿅ݭ‬❍‫ܟⱓݭ‬㤇CPU ‫ݭ޳ޙތފ‬ᇋ㐑݆ತ‫޳ޙތފ݂݃ܮܴܦ‬ತ਽‫ݭ‬ᆟ‫ݎ‬㤇ᐅ‫݉޳ޙތފ‬แ㔩ẙ݄݆݅ܿ‫ܺܲⷮ⹍݁ܟ‬㤉‫޼ݷޤ߆ކ‬*1 ᔄ࿧⁊ጔᆟㄫ ‫⇙㍸ݵݺݹޛިސ‬ጔᆟ⏀ 4 ፪⃩݉៉⣠਺མ‫ܧ݃ܮݦܝܧ‬పᡐ݂ܲܺ݉ 11 ᣻‫݉޼ݷޤ߆ކ݊ݤܦ‬*2 情報通信学部組込みソフトウェア工学科教授ᔄ࿧⁊ጔᆟㄫ ‫⇙㍸ݵݺݹޛިސ‬ጔᆟ⏀ ៟ᛎ-1-− 19 −

ASIC16bitCPU 開発における PBL の有効性‫݆ޜߏކ‬แ㔩‫ܺܲⴕ⇙ݭ݃ܮݦܝܧ‬㤉⒜ 4 ギ݊⢅చ݂❩‫ݵܺܣ‬ᆟ❍‫ݭ‬னฆ݂ღ‫ݜ‬㤇‫݉݁ܟ݆ܿ޳ޙތފ޾ݷޤ߆ކ‬ᆟ❍݃‫ތފ‬‫៉݉޳ޙ‬⣠਺མ݆ܿ‫ܾܺⱓݭⷮ⹍݉݁ܟ‬㤉12 ᣻݊ᆟ⃩݉⟼౹݆‫⃩݁ܲ޾ݷޤ߆ކ݃ޜߏކ޼ީ߆ގ‬ᗣܰ‫ޜߏކ޼ީ߆ގݵܺݧ‬ං‫ݭުߏ޾ރ݁ܶݪ‬਽‫ݥ‬ᤓᦾ⇡݅‫݆⇙㍸޳ޙތފ‬൝‫ܻݮ◸ݥ‬㤉1‫ݭ‬᯳⿶ܲ㤇޿‫਺݆ޒތދ‬చ݅ᣯ‫ܨ‬ず‫݄݉݅ݦܟ݁ݧݪⱓܧݚ‬ள਴᣻݊ CPU ‫޳ޙތފ‬൓‫ܧ޳ޙތފ޼ݷޤ߆ކݎ‬ᆺᗣ݂ܲܺ݉ᩚ⵻

⇡݅แ㔩‫ܧ‬చ‫ݥܦ‬㤇৙ᐴ݉‫៉޼ݷޤ߆ކ‬⣠݉᠘㇇‫ܧ‬᱋ᇇܲܺ㤉‫ܾܺⱓݭ‬㤉ܲ‫ܲܦ‬ᩚ⵻‫ܡⱓݭ‬।݂ⷮ⁊ංᗣ݆แ㔩‫݂ܾ݉ܺܝܧ‬2 ᣻݆݊ PARTHENON ⷮ⁊ංᗣᩚ⵻‫៉݉޳ޙތފ‬⣠‫ܾܺⱓݭ‬㤉

4.3(Table1)10 ᣻ 11 ᣻݂᱋ᇇܲܺ৙ᐴ݉᠘㇇‫ݭ‬ク‫݆݊ݦݜ‬ᡸ㍾‫݅ݥ⼲ܧ‬

Table1 Execution process

OctoberNovember
DecemberJanuary
February‫݆ުߏ޾ރ‬చ‫⇙㍸݉݁ݧܦ‬‫ܣ❩݃ܟ‬㤇12 ᣻݊ൎ౼ᆟ⃩‫ ݭ‬CPU ⵱ⵖᙔᐅ‫ݷޤ߆ކ݃ުߏ޾ރ‬޼ᙔᐅ‫݆ުߏ޾ރ‬చ‫ܺܬ‬㤉⒜ 1 ギ݊ᆟ❍ヅ⏣݆݁᱋ᇇܲܺ᠘㇇

The composition of SN/X is understood㤉
Making to the pipeline is scheduled㤉Simulation on the desk㤉
Finding of data hazard problem㤉
Understanding of yacc and lex㤉Find the problem of the register㤉The member is grouped into CPU and the compiler㤉
Parthenon Veriﬁcation㤉
Completion of each pipeline㤉
Improvement of logic synthesis tool㤉Veriﬁcation of system㤉݆ܲܺ‫ܟܧ‬㤇CPU ൓‫៉݉޼ݷޤ߆ކݎ‬⣠‫ܾܺⱓݭ‬㤉‫ܺݙ‬㤇CPU⵱ⵖ݊ު޿ި‫ތނޖݶ‬౼ⓝ໔㤇‫៉޼ݷޤ߆ކ‬⣠݆݊ perl ⵐⷄ݆ܿ‫ܧ⹀⊳݉݁ܟ‬ᑙⴎ݂‫ܧ݃ܮݦܝ‬చ‫ݥܦ‬㤇⒜ 2 ギ݊ᙔᐅ‫ߏ޾ރ‬ު‫݉݃ܯ‬ᆟ❍‫ܾܺⱓݭ‬㤉⒜ 3 ギ݊‫៉݉޳ޙތފ‬⣠݃ᣬ݅‫៉ݦ‬⣠ẙ݉⹍ⷮ‫ܟⱓݭ‬㤇৙ᐴ㤇‫ ݉ܦܿܪܟ‬CPU ޵‫ݭ޾ޚ‬਽‫ݥ‬㤇ܸ‫ܹݧ‬‫ݧ‬ᩚ⵻‫ܾ݁ⱓݭ‬㤇‫☂ܟݣ‬ᥟ݉ὣ‫ݭ‬ᛠ⃱ܴ‫ܺܲ݃݃ܮݦ‬㤉⒜ 4 ギ݊ᩚ⵻‫݆ݜܺܡⱓݭ‬㤇‫␩⋌߆ޡޙ޾ޤ‬਒‫ݤܦ‬᛿੮ܰ‫⁊ⷮݦܟ݁ݧ‬ංᗣ‫ۿ޾ߏޗ‬PARTHENON‫݉܀‬੕⃱᠘ᲆ‫ܺݔⷜݭ‬㤉‫ܺݙ‬㤇‫߆ކ‬‫ݭ⇙㍸޼ݷޤ‬ᙔᐅܲ݁‫ݦܟ‬ᆟ݆⃩‫ݥݣ‬㤇‫៉޼ݷޤ߆ކ‬⣠ヅ⏣݆݁෉৮‫ݭޜߏކ‬ᣬ݆ᴵ‫݉݃ݦܶݤ‬࿧ද‫ݥܝܧ‬㤇ܸ݉ᆟ⃩‫ݭ‬অሠ݃ܲ݁㤇࿧ද݆࿇݀‫ܾܺⱓݭ⇙㍸޼ݷޤ߆ކܺܟ‬㤉

4.1

4.4CPU(SN/X) ‫݉݁ܟ݆ܿ޳ޙތފ‬ᆟ❍ತ਽ᩚ⵻

1 ᣻݉⒜ 1 ギ݊ 2 ᯝ㤇3 ᯝ㤇4 ᯝ‫ ݉߆ݷ޼ުݷޤ‬CPU ޵‫޾ޚ‬ᐅު߀‫ ݭޛނݺދ‬10 ᣻݆ღ‫ܺݜ‬ᯝ㐇݂݊㤇ᆟ⃩݉ CPU ㍸⇙਽‫ܧݥ‬ᆺবܲ㤇‫ ݊޼ݷޤ߆ކ‬11 ᣻݉∦᫯‫៉ݦܣ⼢ݭ‬⣠‫ݧܰ݅ܧ‬݆㎈ܴ‫⹀⊳ݦ‬㤇൓‫ޛތޙ߆ކݎ‬᫯ᵺ CPU:SN/X2) 3) ݆ܿ‫݉݁ܟ‬݁‫ܺܟ‬㤉‫݂ܮܮ‬㤇ⷮ⁊ංᗣᩚ⵻‫݆݁޾ߏޗ‬ᩚ⵻‫ܾܺⱓݭ‬㤉‫ܾ݃ݝ‬⊳⹀‫ܧ‬ẽ‫ܾܺܦ‬㤉ܸ݉ܺ‫ݜ‬㤇‫ ݊ܵݙ‬SN/X ‫ݭ޳ޙތފ‬ತ‫ܮܴܦ‬‫ݝ‬⣠‫☂ܟ‬ᥟ‫ݭ‬ᐼ‫ ܺݧݤ‬2 ᯝ‫ ߆ݷ޼ުݷޤ‬CPU ݉੕⃱‫ݭ‬᱋ᇇܲܺ݃‫ݤܦ‬ღ‫ݜ‬ゔᮀᰓ݀‫ܲⷮ⹍ݭ݃ܮܺܟ‬㤇৙ᐴ݉៉⣠ẙ݉ൎ❩݃ܲܺ㤉⒜ 1 ギ݊৙ᐴ݉‫ܲⶢ݁ܟ݆݄ܿ݅޾ߏ޸ދބތ‬ං‫ܟ‬㤇⒜ 2‫ܧ‬㤇ヅോ݉‫ޛތޙ߆ކ‬ൎ౼❫݉‫ݥݣ޳ޙތފ‬౽ܾ݁‫ܧ݃ܮݦܟ‬చ޼‫ݭޜߏކ‬ತ‫ܺܲܦ‬㤉‫ ܾ݁ݣ݆ݧܮ‬SN/X ݉᫂ᗣ㤇CPU ݉࿇ᤓⷮ⁊ංᗣ‫݆޾ߏޗ‬ᤓ‫ޛތޙ߆ކ‬ህᦞ࿇ᵺ݆݊ᑙⴎ݉ẽ‫޾ߏ޾ܟ‬ൎ౼❫݉⻔᠂ 4) 5) ‫߆ݷ޼ުݷޤݤܦ‬೗‫݋ܣⱓݭ‬ᠸ‫ܧ݃ܮݦ݅ܪ‬‫⁊݂ⷮ݊ݙ‬ංᗣ‫݉޾ߏޗ‬ৠ◸‫ܧܺݔⷜݭݚ‬㤇៉⣠݂‫⊳݄݉ݖݦܨ‬‫ݥܦ‬㤇৙ᐴ݉ᣬ݅‫៉ݦ‬⣠݉⹍ⷮ‫ݭ‬⒜ 2 ギ݆ⱓܾܺ㤉⹍ⷮ݉☂ᥟ㤇ギ݊ SN/X ݉ತ਽‫ݜܺݦܴⵁ⁊ݭ‬㤇ᚂሠ❫݃ர݆ᤜ।݂‫ީ߆ގݵ‬‫ܧ‬ボ⃱ܰ‫ܧ݃ܮݦܟ݁ݧ‬చ‫ݥܦ‬㤇৙ᐴ݉៉⣠ẙ݃ܲܺ㤉⒜ 4 ギ⇡݅᫂ᗣ‫ܺܨ݂ܧ݃ܮݦܴⵁ⁊ݭ‬㤉⒜ 3 ギ݊ヅോ݉‫ޛތޙ߆ކ‬⹀݊ᐼ‫ܾܺܦ݅ݧݤ‬㤉చ‫ܾܺܦ‬㤉⒜ 4 ギ‫݆݂ݙ‬ൎ౼❫ඁ⢅‫݉݁ܟ݆ܿ߆ݷ޼ުݷޤܧ‬ⷜᦞ‫ܟⱓݭ‬㤇‫߆ݷ޼ުݷޤ‬೗ܲܺ SN/X ݉ತ਽‫ݭ‬ᚂሠ❫݃ர݆ᤜ

4.5।݂‫ݭޜߏކ޼ީ߆ގݵ‬ゅܾ݁⁊ⵁܲܺ㤉‫ުݷޤܾ݁ݣ݆ݧܮ‬޼‫៉݉߆ݷ‬⣠ẙ݃ܲ݁‫݉ޜߏމޢޒߏޚ‬༛レ‫ݟ‬༛⽘ⴗ᫶݉⚘ሡᣬ݅‫៉ݦ‬⣠

2 ᣻݉⒜ 1 ギ݊ⷮ⁊ංᗣ‫݉޾ߏޗ‬ৠ◸‫ܺܲⵁ⁊݁ܟ݆ܿݚ‬ᆟ‫ݎݣܥ‬යᤋ݉⊹⚘݄݅‫ܧ‬చ‫ݥܦ‬㤇⹍ⷮ‫ݤܦ‬৙ᐴ݉ CPU ៉⣠݉᠘⃩‫ܧ‬ன਴݆⷏ᡐ‫ܾܺⱓݭ‬㤉⒜ 2 ギ݆ⷮ⁊ංᗣ‫៉݉޾ߏޗ‬⣠‫ݭ‬㇇‫ܧ‬᱋ᇇܲܺ㤉ⱓ‫ܟ‬㤇ⷮ⁊ංᗣ‫ܧ޾ߏޗ‬ᆺᗣܲܺ㤉‫݉޳ޙތފ‬ᩚ⵻‫☂ܾܺⱓݭ‬ᥟ㤇ヅോ݉‫ޛތޙ߆ކ‬ൎ౼❫‫ݦܣ⼢ݭ‬ᒜ⟼݆ニܲ݁‫߀ުݜܺܺܟ‬4.2‫◶ݭޛނݺދ‬বܰܶ㤇ᆺᗣ෺݃ܲ݁‫Ⲽݭޛ߆޴޸ހޜ‬਽ܲ᛿఑‫ݭ‬‫݉݁ܟ݆ܿ޳ޙތފ޾ݷޤ߆ކ‬ᆟ❍ⱓܾܺ㤉SN/X ‫ ݂݉ܺܟ݆ܿ⿅݊⹀⊳݉݁ܟ݆ܿ޳ޙތފ‬11 ᣻݆݊‫ކ‬߆‫݉݁ܟ݆ܿ޼ݷޤ‬ᆟ❍‫ݭ‬ღ‫ܺݜ‬㤉‫ ݊޼ݷޤ߆ކ‬yacc ݃ lex ݃C ݂᫂ᗣܰ‫ݥܥ݁ݧ‬㤇㒋ፆ݆Ⳃ㐸݂݅݉㤇‫޾ݷޤ߆ކ݊ܵݙ‬ತ਽݉ⵁᥕ‫ݭ‬னฆ݂ⱓ‫ܟ‬, ܸ݉।݂៉⣠݉਺མ݆ܿ‫ܲⶢ݁ܟ‬ං‫ܮܡ‬

݃݃ܲܺ. ⒜ 1 ギ݊‫݉޼ݷޤ߆ކ‬ၺ‫݅ܦݙ‬᫂ᗣ݆ܿ‫ݔⷜ݁ܟ‬㤇⒜2 ギ݊ᇋ㐑݆ᚂሠ❫݃ர݆ᤜ।݂‫ܾܺⱓݭ޾ݷޤ߆ކ݉ޜߏކ‬㤉‫݉޼ݷޤ߆ކܾ݁ݣ݆ݧܮ‬᫂ᗣ݆ܿ‫ܧⵁ⁊݉݁ܟ‬ク‫ݚ‬㤇ᆟ⃩ආၓ‫ܧ‬៟‫ܣ‬ං‫݉⇙㍸ܾ݁ݣ݆݃ܮܡ‬࿇∟‫ݭ‬༯‫ܺݜ‬㤉⒜ 3 ギ݄݊݉‫ݣ‬‫៉݆ܡ‬⣠‫ݭ‬౼‫݋ݧܣ‬ᒜ⟼‫ܧ‬උ।ܴ‫ܲⷮ⹍ݭܦ݉ݦ‬㤇‫޼ީ߆ގݵ‬-2-− 20 −山崎亮太・上陰敏弘・虎口克尚・清水尚彦

5.

Consumption energy [uW/MHz]
7917.6ᗣᥟὣ

5 ߉᣻㍾݉ CPU ㍸⇙ᆟ❍ᤋ㍾‫ ݥݪ◶ܧ‬ASIC ‫ޙ߆ކ߆ݷމޚ‬Four step pipline&Normal SN/X‫݆ޛތ‬఑෺ܴ‫ ݦ‬CPU ‫ܧ޳ޙތފ‬ᆺᗣܲܺ㤉৯㏘݆৙༛݉ PBLᆟ❍ヅ⏣݆݁অ݆‫៉޳ޙތފ‬⣠‫ܾܺⱓݭ‬ẙ‫ݦܭܝݭ‬㤉

5680.95.1CPU ‫޶ޔނޙހߏݵ‬‫݂ޛތޙ߆ކ‬ህᦞܰ‫ߏށ޾ޠݻݦݧ‬ᡸ㍾␑݊ᇋⱓ‫៪ނޖ߀ނ‬᯳݃੟㎈઄݆‫ݜܺݦܝ‬㤇‫݉៪ނޖ߀ނ‬ూᴵ݆‫ݥݣ‬ᴵ‫݂ܧ݃ܮܴݤ‬45.8816‫ݦܨ‬㤉ܸ‫݉߆ݷ޼ުݷޤ݂ܮ‬᫂─݃㤇෉৮‫៉݉ޛޖގ‬⣠‫ܟⱓݭ‬㤇‫ݭ៪ނޖ߀ނ‬ూᴵܴ‫ߏށ޾ޠݻ݂݃ܮݦ‬ᡸ㍾␑‫ݭ‬ᴵ‫݆݃ܮܴݤ‬16074

ܲܺ㤉‫ܺݙ‬㤇ൎ౼ᆟ⃩݊ᆟㄫ㤎፪݂⃩‫ݥܝ‬㤇CPU ⵱ⵖ݆㎈ܴ‫ݦ‬⊳⹀݊ẽ‫ܟ‬㤇ܸ݉ܺ‫ݜ‬ષ۸݉⟼౹݆‫ܾ݁ݣ‬᣷ボ݅‫݉߆ݷ޼ުݷޤ‬26216

ᩚ⵻㤇౼ⓝ໔݉ၤᣬ㤇෉৮‫៉݉ޛޖގ‬⣠㤇ⷮ⁊ංᗣ݉៉⣠‫ݭ‬ౝ‫ݥ‬

Number of clocks [clock]ᚖ‫ݥ‬㤇ષ۸݉⁊ⵁ‫ݟ‬ᗣᥟ‫ݭ‬ன਴݆⊳‫݂ⷮ݃ܮݦܶݤ‬ẙㆹⳂ݉ẽ㗑‫ݭ‬ᴵ‫ܲݤ‬ಏ

5.1.1

63.6
Cycle [nS]

Consumption energy [uW/MHz]⇡݅‫޳ޙތފ‬ன਴݉៉⣠‫ܾܺⱓݭ‬㤉

Three step pipline&Normal SN/X

SN/X ݉‫߆ݷ޼ުݷޤ‬೗

SN/X ݊ި‫( ޔޖݺ‬IF)㤇ᇋⱓ (EX)㤇޴޵޽‫( ތގނݵ‬ME) ݉ 3

5702.9‫ݥܝ݂ⵖ⵱ދߏޙތ‬㤇෉৮݊ゔᮀᇋⱓܰ‫ނޖ߀ނݜܺݦܟ݁ݧ‬5680.9៪‫ܧ‬᯳⿶⇡ၱ‫ܾܺܦ‬㤉‫ ݉ܮ‬SN/X ‫߆ݷ޼ުݷޤݭ‬೗ܲⴕᛜ‫ܬ‬। 1‫ ނޖ߀ނ‬1 ෉৮݉ᇋⱓ‫ܟⱓݭ‬㤇ၺፌ݅‫݉៪ުޖޙތ‬ూᴵ݆‫ݦݣ‬᣷ၺゾᎼᡸ㍾݉⊹⚘‫ܾܺⱓݭ‬㤉‫ܺݙ‬㤇‫߆ݷ޼ުݷޤ݉ܦܿܪܟ‬޵‫ݭ޾ޚ‬਽‫ݥ‬ᒜ⟼ⶍੳ‫ܟⱓݭ‬㤇ܸ݉ॻ݂‫☂݅⎶୻ݝ‬ᥟ‫ݭ‬ᯃܲܺ 2‫ݭⵖ⵱ދߏޙތ‬ᛠ⃱ܲܺ㤉(Table2㤇Fig1)

12522

58.0425

Table2 Each pipeline comparison beforee it modiﬁes it

Four step pipeline
Three step pipeline
Two steps Pipelline
Normal SN/X

Number of clocks(sort)
16074
12522
9014
26216

Consumption energy{ µ W/MHz }7917.65702.95002.95680.1

Cycle{nS}
45.881658.042562.9483
63.6

26216

Performanceorder3214

63.6

Number of clocks [clock]

Cycle [nS]

Consumption energy [uW/MHz]

Two step pipline&Normal SN/X
5.1.2

Parallel Preﬁx Adder㤃ॷదު޿ި‫ތނޖݶ‬౼ⓝᬝ㤄݉ၤᣬ

5680.9౼ⓝᬝ‫ݭ‬ၤᣬܴ‫ݥܺܝ݆ݦ‬㤏ܿ݉౼ⓝᬝ݉‫ݔⷜݭޒߏޚ‬㤇ܸ

5002.9݉ॻ‫◞ݤܦ‬ᆎ៪݃ァᎇ݉வ݈ං‫ܧܟ‬ᤓ਴݉⵱ⵖ݆ボܲ݁‫݃ݦܟ‬❩‫ ݁ܣ‬Han-Carlson Adder(Fig2) ‫ݭ‬ᇋⲛܴ‫݆ܺܲ݃ܮݦ‬㤉Han-Carlson Adder ݊◾⃸ܴ‫◞ݦ‬ᆎ‫ܧ‬፩ཥ⇡݂஧౹ܰ‫ݦݧ‬૎‫߆޼ޣܧ‬9014‫ތ‬⣠‫݂݉ݦݧܰ⃸◾ܪ‬㤇㑒౹‫ݭ‬ᘷ‫⏣ݦܝܿܿܣ‬ᎇ݉ァᎇ‫ܧ‬ᐼ‫ݧݤ‬‫݃ݦ‬ప᠐ܲܺ㤉౼ⓝᬝ݉శ਽݊༛⽘݃◞ᆎ݉Ꮡ‫ݭ‬எ݆ܲ݁ SFL

62.9483݂ⱓܾܺ㤉(Fig2) ݆‫݁ܟܥ‬ᤓ਴݂⃱‫݊ߏ޽޶ހܟ݅ܟ‬ూ㏨ܲ݁

26216‫ݦܝ‬㤃᣷।ਮަ‫݉ޛޖ‬ూ㏨㤄㤉ު޿ި‫ތނޖݶ‬᷀ⓝ‫ܺܝ݆ܡⱓݭ‬‫ݥ‬㤇૎‫ ݭ‬P ݃ G ݆చ‫ⵖ݁ܬ‬ⓝܴ‫ ݦ‬Pg ޵‫ॷݭ޾ߏ޸ދ‬ద݆ܲܺ㤉

Number of clocks [clock]63.6Cycle [ns]Fig1 Each pipeline comparison beforee it modiﬁes-3-− 21 −

ASIC16bitCPU 開発における PBL の有効性

xyPg

xyPg

xyPg

xyPgxyPgx
Pg

yx

yx

Pg

yPg

xyx

Pg

yPg

xyx

Pg

yx

Pg

*

*

*

*

*

*

*

*

*

*

*

C

*

*

*

CCCCCyx

Pg

yx

Pg

yFA

5.2C‫޼ݷޤ߆ކ‬‫␩⋌߆ޡޙ޾ޤ‬਒݉᛿੮ܴ‫݊޼ݷޤ߆ކݦ‬㤇ᰮ⃱⇡݅⵱ⵖܾ݃݅݁‫ݜܺݦܟ‬㤇‫ⴗ݉ޛތޙ߆ކ‬ᇇ݆᣷‫ݝ‬ං‫ܡݣݦ݅݃ⵖ⵱ܡ‬᫋۸݅៉⣠‫ܾܺⱓݭ‬㤉‫ܵݙ‬㤇ᠳᆕ݉‫⃩ܧ޼ݷޤ߆ކ‬ᗣܴ‫߆ގݵݦ‬ީ޼‫݉ޜߏކ‬ᤜ।‫ܡⱓݭރޖޣޚ‬র݂‫ⴗ݉ޛތޙ߆ކ‬ᇇ݆‫ܟܥ‬݁਺చ݅ㄫచ‫ݭ‬ᙏ఑ܲܺ㤉ܸ݉ᡸ㤇‫ܧ޼ݷޤ߆ކ‬੕⃱ܲ݅‫ܟ‬१ⴎ݅෉৮‫ݭ‬ూ㏨‫ܟⱓݭ‬㤇CPU ‫෉݉޶ޔނޙހߏݵ‬৮‫݉ޛޖގ‬ၤᣬCCCCCC‫ܾܺⱓݭ‬㤉‫ܺݙ‬㤇ఁ⁊ᒜ⟼‫ݭ‬උ।ܰܶ‫ݦ‬ゅ౼෉৮‫ܣ❩ݭ‬㤇ᇋⲛ‫ݭ‬Cܲܺ㤉ܸ݉ᐴ㤇‫ݥݣ‬ሢ݅‫⃩ݭޜߏކ޼ީ߆ގݵܟ‬ᗣܴ‫ކ݆ܡݣݦ‬߆‫៉ݭ޼ݷޤ‬⣠ܲܺ㤉᣷ᐴ݆㤇‫⃩݁ܲ޾ݷޤ߆ކ‬ᗣܰ‫߆ގݵܺݧ‬
S

S

S

SS

S

S

S

S

S

S

SS

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

SS

ީ޼‫ݤܦޜߏކ‬㤇ᣬ݆਺చ݅‫ݭޜߏކ‬ూ㏨ܴ‫ݭޛު޽ނތݦ‬਽ᗣܴ‫݂݃ܮݦ‬ᇋⱓ‫ݭ៪ނޖ߀ނ‬ూᴵܲܺ㤉

S

Fig2 Composition of adding machine

5.1.3

5.2.1ఁ⁊ᡸ㍾ཥ⒯೗‫݉ޜߏކ޼ީ߆ގݵ‬᣷ボ೗‫݁ܲ޾ݷޤ߆ކ‬਽‫݂݊ݙݙ݉ޜߏކ޼ީ߆ގݵܺݧݤ‬㤇਺చ݅

2 ᯝ‫݂݊ⵖ⵱߆ݷ޼ުݷޤ‬㤇EX ‫݆ދߏޙތ‬ఁ⁊‫ܧ‬㐰ॻܲ݁ܲld ෉৮‫ܧ‬ၱ‫ݦܝܪ‬㤉ܸ‫ݭݧ‬ూ㏨ܴ‫݆ݜܺݦ‬㤇Perl ‫݁ܟ⃱ݭ‬㤇‫ގݵ‬‫ܟݙ‬㤇᣷ၺゾᎼᡸ㍾‫ܧ‬Ꮌ‫☂ݦݎ‬ᥟܾ݃݅݁ܲ‫݂ܾ݉ܺݙ‬㤇යᤋ݉߆ީ޼‫݉ޜߏކ‬᣷ボ೗‫ܾܺⱓݭ‬㤉᣷ボ೗݉᠘ᲆ݃ܲ݁݊㤇ၺ‫ܪܨ‬⊹⚘೗‫ܾܺⱓݭ‬㤉EX ‫ޜߏކޚ݂݊ދߏޙތ‬ఁ⁊㤇޿‫ݤܦޒތދ‬చ‫݁ܬ‬㤍ܿ݉ఁ⁊‫ݦܟܾ݁ⱓݭ‬㤉㤌ܿ‫݊ݜ‬㤇‫ޜߏކ޼ީ߆ގݵ‬।݉१ⴎ݅ ld ෉৮݉ూ㏨‫ ܡⱓݭ‬ld ෉৮ూ㏨ఁ⁊݂㤇㤍ܿ‫݊ݜ‬㤇ᤵ݉૎݉෈‫ݎ‬఑ܲ㤇෈‫ݎ‬఑ܲܺ૎݆࿇݀‫෉ܪ‬৮݉ᇋⱓ㤇ᇋⱓ☂ᥟ݉޿‫݉ݓޒތދ‬ᣯ‫ܨ‬ず‫ݚ‬㤇‫ݚⷐ݉޽޵޴ޒߏޚ‬ᣯ‫ܨ‬㤃ⷮ⁊ゾᎼ =৹చቯ݂$0 ޿‫ݭޒތދ‬੕⃱ܴ‫݉ޜߏކ݆ܡݣݦ‬᣷ボ೗‫ܡⱓݭ‬$00㤄㤇చቯᡸ݉ᮀ‫ݎ෈݉ދߏޙތ‬఑ܲ‫ݭ‬ᇋⱓܲ݁‫ܺܟ‬㤉IF ‫෉݂݊ދߏޙތ‬৮޴޵޽㤃ⷮ⁊ゾᎼ = 0㤄‫෉ݤܦ‬৮݉Ꮦ‫ܨ‬఑ܲ㤇PC ‫ޛ߆ݹݾ݉ݓ‬౼ⓝ㤇ᮀ݉ IF ‫ݎ෈݉ދߏޙތ‬఑ܲ㤇EX ‫ތ‬‫ݎ෈݉ދߏޙ‬఑ܲ‫ݭ‬ᇋⱓܲ݁‫ݥܥ‬㤇IF ‫ ݊ދߏޙތ‬EX ‫ދߏޙތ‬ၤᜇఁ⁊݂‫ݦܝ‬㤉(ﬁg4)

Start
Load the assembler code
to the array "Buf"᯳݃‫ݔ‬ఁ⁊ᡸ㍾‫ܟ⊹ܧ‬㤉ɓ EX ‫݂ދߏޙތ‬ᇋⱓܲ݁‫ݦܟ‬ఁ⁊݉‫ܼܡ‬㤇‫ޜߏކޚ‬ఁ⁊݊ IF‫݂ދߏޙތ‬ᇋⱓܲ݁‫ݜܺܟ݅ܲ⃩⇙݊ޜߏމޢݝ‬㤇IF ‫ދߏޙތ‬Variable i = 0݂‫ޜߏކޚ‬ఁ⁊‫ݭ‬ᇋⱓ݂‫݆ܲܡݣݦܨ‬㤇ఁ⁊ᡸ㍾݉ཥ⒯೗݆‫ݦݣ‬᣷ၺゾᎼᡸ㍾݉⊹⚘೗‫ܾܺⱓݭ‬㤉‫޿߆ݷ޼ުݷޤܾ݁ݣ݆ݧܮ‬‫៉݉ޒތދ‬⣠‫ܧ‬൴⟼݆݅‫ݥ‬㤇‫ޜߏކޚ‬ఁ⁊݆‫ݥݣ‬१ⴎܾ݃݅ܺ෉

I < The all number of lines৮ަ‫݉ޛޖ‬ూ㏨݃㤇ూ㏨ㄫచ‫ޜߏކޚݓ‬૎‫ݚ◸ݭ‬ず‫ܾݣ݆݃ܮݛ‬᳢݁⻉㑒౹݉⟉ၺ೗‫ݭ‬༛レܲܺ㤉(Fig.3)

False
Process to delete the instruction "ld"

Processingtime
IF stage

IFEX stage

ID

EX

Process to convert "$0"
RW

Outout "Buf[i]"Improvedi++

Processingtime
IF stage
EX stage

IFEX

TrueEndFig4 Flow of assembler code optimization

IDRWld ෉৮ూ㏨ఁ⁊݊㤇‫ݭޜߏކ޼ީ߆ގݵ‬᣷న‫ݤܦ‬㤌ⱓܵܿⷐ‫ݚ‬఑ܲ㤇ld ෉৮‫݃ݦܬܿⴕݭ‬㤇⒜㤌Ꮦ៪݉޿‫ ܧޒތދ‬ld ෉৮‫ݣ‬IF :processing time of instruction fetch
ID :processing time of instruction decode
EX :processing time of execution
RW :processing time of register writing‫݆౅ݥ‬੕⃱ܰ‫݂ݙⱓݦܟ݁ݧ‬㤌ⱓܵܿᘁ‫ݦ‬㤉ܸ݉ᡸ㤇ld ෉৮݉⒜㤎Ꮦ៪݂‫ܧޒތދ޿ݦܝ‬ఫ݉෉৮݂⒜㤌Ꮦ៪ܾ݃݅݁‫ܟ݅ܟ‬‫ݭܦ‬ప᠐ܲ㤇⒜ज़Ꮦ៪ܾ݃݅݁‫ܟ݅ܟ‬ᡸ݆㤇ld ෉৮‫ݭ‬ూ㏨ܴ‫ݦ‬㤉

Fig3 Change in processing time$0 ၤᜇఁ⁊݊㤇‫ݭޜߏކ޼ީ߆ގݵ‬᣷న‫ݤܦ‬㤌ⱓܵܿⷐ‫ݚ‬఑ܲ㤇bz ෉৮‫݃ݦܬܿⴕݭ‬㤇ज़ܿ౅݉ⱓ‫ܧ‬㤎ܿ݉Ꮦ៪‫ݭ‬ᑙⴎܴ݃-4-− 22 −山崎亮太・上陰敏弘・虎口克尚・清水尚彦‫ ݦ‬R ᐐᏑ݉෉৮ܻܾܺᡸ㤇෉৮݃ bz ෉৮݉⒜㤌Ꮦ៪‫ݭ‬$0 ݆ၤᣬܴ‫ݦ‬㤉

5.3

5.5ᠶ‫݃޳ޙތފ‬᠓‫݉݃޳ޙތފ‬᯳⿶‫݁ܟܥ݆ޛތޙ߆ކ‬ᒜ⟼ⶍੳ࿇ᵺ݂‫ߏށ޾ޠݻݦܝ‬ᡸ㍾␑‫ݭ‬PARTHENON ‫޳ޙތފ‬⃱‫݁ܟ‬᯳⿶‫ܾܺⱓݭ‬㤉

PARTHENON ‫ ݉޳ޙތފ‬AUTO ‫⁊݆ⷮ݁ޜ߆ޱކ‬ංᗣ‫ܾⱓݭ‬ܺ㤉AUTO ‫݊ޜ߆ޱކ‬㤇༛⽘݉᣷ボ೗‫ ݆ݜܺܡⱓݭ‬DEMO ޼‫ݷ‬ᇋⱓᡸ㍾݉∬খ፩ཥ૎ T [s] ݊㤇√
T = A × B × D[s]݊ⷮ⁊༛⽘݉┵™೗‫ܧܡⱓݭ‬㤇┵™೗‫◞݃ܡⱓݭ‬ᆎ݉ᴵሢ݆ሒ݂ܲ‫ݦܝ‬㤉‫ܺݙ‬㤇ᇋⱓ‫∬݉ߏށ޾ޠݻ‬খ፩ཥ૎ E[J] ݊㤇݁᣷ၺゾᎼᡸ㍾݊ဠ౼ܴ‫ݦ‬㤉ܲ‫ߏށ޾ޠݻܲܦ‬ᡸ㍾␑݆݊᣷ၺ
ゾᎼᡸ㍾‫ܧ‬ၺ‫ܪܨ‬㎈઄ܲ݁‫݂݉ݦܟ‬㤇᠓ⴗ݆ ons ‫ݭޛު޽ނތ‬ᇋ(2)



E = T × (P/D)[J]ⱓܲ݅‫ݭ޽޼ީݷ޼ܟ‬਽ᗣܲᇋⱓܴ‫݂݃ܮݦ‬᣷ၺゾᎼᡸ㍾݉⊹ܲܺ‫ܾ݁ܧ‬㤇‫ߎߏށ޾ޠݻ‬ᡸ㍾␑ M [J ߎs] ݊㤇⚘‫ݭ‬༫ܾܺ㤉

5.4(1)ީ޼޽݆‫ ݦܬܥ‬ons ‫ݭޛު޽ނތ‬ᇋⱓܲ݁‫ݦܟ‬㤉ons ‫ޛު޽ނތ‬(3)



M =T ×E៉⣠ᐴ݉ತ਽ᩚ⵻៉⣠݉☂ᥟ᳢݃ܲ݁⻉㑒౹݉ၺፌ݅ᴵሢ݊ẽ‫ܧܾܺܦ‬㤇᣷ၺゾ৯॥݉ު߀‫݂޳޼ރ‬ತ਽ᩚ⵻‫ܟⱓݭ‬㤇ᮨፆ݆ತ਽‫ܮݦݧܰܧ‬Ꮌᡸ㍾݊ၺ‫ܪܨ‬ᴵሢܲܺ㤉݃‫ܺܲⶸ⌚ݭ‬㤉ܰ‫ⷔ݆ݤ‬㔩ު߀‫޳޼ރ‬৯ၮ‫ݝ‬ᮨፆ݆ತ਽ܴ‫ܮݦ‬ܰ‫ⶍ݆ݤ‬ੳᏑ݆‫݁ܟܥ‬᳢⻉㑒౹‫ܧ‬㤌খ݆ሒܲ㤇᣷ၺゾᎼᡸ㍾‫ܧ‬݃‫݆ݜܺݦܴⶸ⌚ݭ‬᠓݆ܺತ਽ᩚ⵻⃱ު߀‫ݭ޳޼ރ‬਽‫ݥ‬ᩚ⵻‫ݭ‬㤍খ݂ⵖⓝܰ‫ߏށ޾ޠݻ݂݉ݦܟ݁ݧ‬ᡸ㍾␑݊ၺ‫ܪܨ‬ᴵሢܲ݁ⱓܾܺ㤉ᩚ⵻‫☂ܾܺⱓݭ‬ᥟ‫ݝݧܵܟ‬ᮨፆ݆ತ਽ܲ݁‫ݭ݃ܮݦܟ‬‫ݦܟ‬㤉⌚ⶸܲܺ㤉(Fig5㤇Fig6)ᗤ ۸ ݉ ⵱ ⵖ ܲ ܺ CPU ‫ ߏ ށ ޾ ޠ ݻ ݉ ޳ ޙ ތ ފ‬ᡸ ㍾ ␑ ݊• ுፀఁ⁊ⷔ㔩ު߀‫( ޳޼ރ‬recur.sc)• ‫ⷔޛߏސ޾ީޣ‬㔩ު߀‫( ޳޼ރ‬sort.sc)

1:
n=20;
2:
for(i=0; i<n; i++) z[i]=n-i;
3:
4:
5:
6:
7:
8:
9:
10:


for(i=0; i<n-1; i++)for(j=n-1; j>i; j−−)if(z[j]<z[j-1]) {w=z[j];
z[j]=z[j-1];z[j-1]=w;}
halt;

Fig5 ‫ⷔޛߏސ޾ީޣ‬㔩ު߀‫( ޳޼ރ‬sort.sc)


1:
2:
3:
4:
5:
6:


0.0962[J·s] ݂‫ݥܝ‬㤇‫ޛތޙ߆ކ‬᫯ᵺ޵‫ߏށ޾ޠݻ݉޾ޚ‬ᡸ㍾Fig7)

Table3 Comparison of numbers of clocks”recur.sc” Number of clocks
347
155

Before SN/X
After SN/X

”sort.sc” Number of clocks
26216
3985

Table4 Comparison of performances

Before SN/X
After SN/X

int foo(arg) {if(arg<2) return arg;
else return foo(arg-2)+foo(arg-1);}
foo(10);halt;

Fig6 ுፀఁ⁊ⷔ㔩ު߀‫( ޳޼ރ‬recur.sc)

␑ 3.06[J·s] ݉ 31.8 હ݉ᒜ⟼උ।‫ݭ‬ᇋ⁃ܲܺ㤉(Table3㤇Table4㤇Power consumption[ µ W/MHz ]5680.15074.5



Delay time[nS]
63.6
30.69

Energy time product[j·s]3.06
0.0962

Cycle [nS]
63.6

30.69



Number of clocks(recur.sc) [clock]347

5074.5155

5680.1
Consumption energy [ uW/MHz]

3985

26216
Number of clocks(sort.sc) [clock]Fig7 Flow of assembler code optimization-5-− 23 −ASIC16bitCPU 開発における PBL の有効性

ᐅ PBL ݂݊㤇‫ॴ݉ݵݺݹޜߏޢߎݵݺݹޛިސ‬㒎‫ݭ‬ज़ܿ݉ު6.

߀‫݂݃ܮܡⱓݭޛނݺދ‬ᇋ⁃ܲܺ㤉ܲ‫ܲܦ‬㤇৙༛݉ CPU ‫ޙތފ‬❩ᇼ

޳㍸⇙ PBL ݂݊㤇CPU ‫ݥݣݭ⇙㍸޳ޙތފ‬ᆟ❍උ‫ݜܺݦܴ݆ܬ‬5 ߉᣻㍾݉ CPU ㍸⇙ PBL ݉☂ᥟ㤇ᆟܼ⃩ܺ݊ CPU ‫޳ޙތފ‬݆ᠳᆕ݉ CPU ‫៉݉޳ޙތފ‬⣠‫ܧܾܺⱓݭ‬㤇ᐅ PBL ‫ܾܺⱓݭ‬ᆟತ਽‫ݝ‬చ‫ܵݤܦ‬㤇‫ݭ޳ޙތފ‬ತ‫ܺܟ݁ܲܦ‬ᡸ᯳݃‫ݔ‬㤇ު߀‫ނݺދ‬݉ᔺⴕ‫ܧ‬఑ܺ㤉‫݉ܮ‬݆᫋ᆟ⃩‫ܧ‬㤇⊳⹀㤇ᘭⱘ‫ܬৣ݆⿅ݭ‬㤇ᣬ݆⢅⃩݉ᔺⴕ݂݊㤇ᮀ݊⢅చニ݂ज़‫ ݤܦ‬CPU ‫݃ܟܺܲ⇙㍸޳ޙތފ‬㍸⇙݉࿇⍋⟼౹‫ܺܬ݆ܿ⿅ݭ‬㤉ܸ‫݊ݧ‬㤇10 ᣻݉ᯝ㐇݂݊ CPU ݉অ⇡݆ CPU ‫݃ܟܺܟⱓݭ⇙㍸޳ޙތފ‬ᒕ‫ܦ݃ܮܾ݆ܺ݅ܡݣܡ‬‫◶ޛ‬বᡸ‫⏷៪݆݂ݙ‬㔸݉‫⃱ݭ޳ޙތފ‬ᔺܲ݁‫ޤ߆ކݟ݃ܮܺܟ‬‫ ݤ‬CPU ‫ ݦܬܥ݆⇙㍸޳ޙތފ‬PBL ݊᣼ಏܻ݃చ‫ܾܺܦ‬㤉‫޼ݷ‬൓‫⁊ⷮݎ‬ංᗣ݉ጔၾ‫ݤܦ‬ਠ‫ݦܣ‬㤉CPU ‫ ݁ܟܥ݆⇙㍸޳ޙތފ‬PBL ݊㤇ᆟܼ⃩ܺ݉␑᪐⇡݅⹍ⷮ‫ݭ‬અܲ㤇⢅‫ݤ‬᛿ᧈܲܺ៉⣠݄݅แ㔩‫ⵁݔⷜݭ‬᱋ܴ‫ݥݣ݆݃ܮݦ‬7.

CPU ‫ݭ⹀⊳݉޳ޙތފ‬ᐼ‫ܺܨ݂ܧ݃ܮݦ‬㤉
PBL ᆟ❍݉ᗣᥟ݃ܲ݁ᆟܼ⃩ܺ݉⵱ⵖܲܺ CPU ‫ݻ݉޳ޙތފ‬⸠いᤓ⋌␩݊㤇PARTHENON ⋌␩਒অତ݉ ASIC ‫ޙ߆ކ߆ݷމޚ‬‫ߏށ޾ޠ‬ᡸ㍾␑݊ 0.0962[J·s] ݂‫ޛތޙ߆ކݥܝ‬᫯ᵺ޵‫ݻ݉޾ޚ‬‫ݭޛތ‬অ㔩݆ܲ݁ⱓܾܺ㤉‫݉ܮ‬᫋݅ᬝ਒‫ܺܟܻܺܟ݁ܬܡݝݭ‬‫ߏށ޾ޠ‬ᡸ㍾␑ 3.06[J·s] ݉ 31.8 હ݉ᒜ⟼උ।‫ݭ‬ᇋ⁃ܲܺ㤉‫ݧܮ‬

PARTHENON ⋌␩਒݆ᴟ‫ܪ‬ᕈ⸠‫ܴݙܲܺܟ‬㤉݊ CPU ᤓ਴݃‫޼ݷޤ߆ކ‬㤇ܸܲ݁㤇ⷮ⁊ංᗣ‫ ݉޳ޙތފ‬3 ܿ݉៉⣠‫ݥܝ݂ݜܾܺܺܝܧ‬㤇ᆟ⃩‫ܧ‬೻చ݆ܸ‫ܲⵁ⁊ݭݤݧ‬㤇CPU‫☂ܺܲⵁ⁊ݭ⇙㍸޳ޙތފ‬ᥟ݂‫ݦܝ‬㤉ள਴⇡݆ CPU ‫ ⇙㍸޳ޙތފ‬PBL ‫ݭ‬ゝܲ㤇݄‫ܧ⹀⊳ܾܺⵐܡ‬ൎ❩៶Ὴ1) ‫␩⋌߆ޡޙ޾ޤ‬਒ɬ, ASIC ‫ޛތޙ߆ކ߆ݷމޚ‬ɭ㤇http://www-⿅݆ܿ‫ܦܺܟ‬৯॥݆੟݆‫ݦܭܝ‬㤉

lab09.kuee.kyoto-u.ac.jp/parthenon/contest/index.html (ൎ Ở2009-10-7)2) ᴫᰟሦᐓ,ɬ‫݉ⵖ⵱ޒߏ޸ާ߆ކ‬࿇⍋⊳⹀ɭ㤇IP ARCH㤉Inc㤇
http://www.ip-arch.jp (ൎỞ 2009-10-7)3) ᴫᰟሦᐓ,ɬ‫݉ⵖ⵱ޒߏ޸ާ߆ކ‬࿇⍋⊳⹀-‫ߎݵݺݹޜߏޢ‬ɓ੟ 1CPU ᤓ਴‫៉ݭ‬⣠ܴ‫ݥܺܝ݆ݦ‬㤇⁃ད݉ CPU ݂݊ᑙܵ੕‫ܟ݁ݧݪ‬‫ݦ‬ᘭⱘ݂‫ܨ݂ܧ݃ܮݦݧⵃ݆߆ݷ޼ުݷޤݦܝ‬㤇ܸ݉☂ᥟ CPU஻ㄫ݉ᾉᕤユ⏚‫ܲⵁ⁊ݭ‬㤇៉⣠‫ݭ‬౼‫ܺܨ݂ܧ݃ܮݦܣ‬㤉‫ ܺݙ‬CPU‫݃ⵖ⵱݉޼ݷޤ߆ކߎ޶ޔނޙހߏݵ‬ᇋⲛ-ɭ㤇PP.206㤇ர⑝݉ HDL ⵣほ݆ velirog ‫ݥݣ‬㙒ਮ޿ެ޾݉⵱ⵖⵐⷄ݂‫ ݦܝ‬SFL ‫ݭ‬఑Ὃ㤇2003㤉

⃱‫݂݃ܮݦܟ‬㤇‫ⵣݵݺݹޜߏޢ‬ほⵐⷄ݉࿇ᤓ⇡݅ⵣほ᠘Ꮡ‫݆⿅ݭ‬4) ⫭⃷ᮬ㤇ቡᤓሡၽㄝ㤇ၺㆽᴠज़ᤅ㤇᫦൨ᙡ฀㤇೘ዧഉ฀ɬ, ܼ‫ܣ‬݉‫ݪ‬ɭ
㤇⒜ 34 ༛‫␩⋌߆ޡޙ޾ޤ‬਒㤇Vol34㤇PP.81∼88㤇2009㤉ৣ‫ܺܨ݂ܧ݃ܮݦܬ‬㤉5) ਒Ჰၺᆟ, শ೻ወ❎ज़, ඃ⃷፭Ⲧ,ɬ‫ݥܲ݋ݤܝ‬ɭ㤇⒜ 34 ༛‫ޤ‬੟2޾‫␩⋌߆ޡޙ‬਒㤇Vol34㤇PP.55∼64㤇2009㤉‫៉ݭ޼ݷޤ߆ކ‬⣠ܴ‫ݥܺܝ݆ݦ‬㤇‫݅ܡݣ݄݉ܧ޼ݷޤ߆ކ‬ৠ◸‫ݚ‬݂‫ݭޜߏކތߏސ‬ၤᜇܲ݁‫ܲⵁ⁊ݭܦݦܟ‬㤇‫⁊݉ⷄⵐ޼ީ߆ގݵ‬ⵁ‫ݝ‬ᴟ‫ܺݜ‬㤉‫ܺݙ‬㤇‫݉޼ݷޤ߆ކ‬ၺㄫచ݂ C ⵐⷄ‫݁ݧݤܟ⃱ܧ‬‫ݤܦ݃ܮܺܟ‬㤇C ⵐⷄ݉⁊ⵁ‫ݝ‬ᴟ‫ܾܺݙ‬㤉

-6-− 24 −