Journal of Robotics, Networking and Artificial Life, Vol. 2, No. 4 (March 2016), 238-242

An FPGA-based cortical and thalamic silicon neuronal network
Takuya Nanami

School of Engineering, The University of Tokyo
Tokyo, JapanTakashi Kohno

Institute of Industrial Science, The University of Tokyo
Tokyo, Japan

Abstract
A DSSN model is a neuron model which is designed to be implemented efficiently by digital arithmeticcircuit. In our previous study, we expanded this model to support the neuronal activities of several corticaland thalamic neurons; Regular spiking, fast spiking, intrinsically bursting and low-threshold spike. In thispaper, we report our implementation of this expanded DSSN model and a kinetic-model-based silicon
synapse on an FPGA device. Here, synaptic efficacy was stored in block RAMs, and external connection
was realized based on a bus that conform to the address event representation. We simulated our circuit by theXilinx Vivado design suit.
Keywords: silicon neuronal network, neuron model, FPGA, cortex, thalamus.

1.

Introduction

Silicon neuronal networks can simulate neuronal activity
with low power consumption and in high speed. They arethought to be a promising way to realize an extremely
large-scale network comparable to the human brain in
future. The Field-Programmable Gate Array (FPGA)
devices are commonly used for silicon neuronal networks
because they can implement user-designed circuits withlow cost. Many silicon neuronal networks on an FPGA
can run at a higher speed than the biological real-time[1][2]. For example, a fully-connected 1024-neuron
network that is 100 times the real-time speed has been
implemented on a single Virtex-5 FPGA [3]. Thomas et al.
adopted the Izhikevich (IZH) model that can simulate
various types of neuronal activities with theircorresponding parameter sets. Li et al. [4] constructed anauto-associative memory with 256 fully connected digital
spiking silicon neuron (DSSN) models on an FPGA. The
DSSN model [5] is an qualitative neuronal model
designed for efficient implementation by efficiently in adigital arithmetic circuit. This model is a non-I&F-basedmodel and can realize several neuronal activities
including Class I and II in the Hodgkin’s classification[6]. This model can reproduce the gradient response inClass II neurons [7], because it does not abbreviate thecalculation of the spiking process. Due to a trade-off
between the reproducibility of neuronal activity andcomputational efficiency, diversified neuronal models areused in silicon neuronal networks. For example, theionic-conductance models can reproduce a neuronal
activity accurately but consumes excessive computational
resources in large-scale implementations. On the other

Published by Atlantis Press
Copyright: the authors
238

Takuya Nanami, Takashi Kohno

hand, neuronal models that approximate a spiking processby resetting of the state variables (integrate-and-fire(I&F) -based models), such as the LIF, exponential I&F
model [8], adaptive exponential I&F model [9] and IZH
models, can be implemented at low computational cost.
However, it has reduced reproducibility of complex
neuronal activities. For instance, these models assume
fixed maximum membrane potentials during the spikeprocess, whereas these potentials are non-uniform in thenervous system.
In our previous research [10], we expanded the DSSN
model to cover cortical and thalamic neuron classes,
including regular spiking (RS), fast spiking (FS),low-threshold spike (LTS) and intrinsically bursting (IB).
We confirmed that the model behaves in the same way as
the ionic-conductance model [11] in response to various
magnitude of step input in each neuron classes.
In this paper, we designed digital arithmetic circuit for
the DSSN model on an FPGA. We simulated our circuiton Xilinx Vivado design suit. The remainder of this paper
is organized as follows. Section 2 introduces our neuronmodel and details of its implementation. The simulation
result is shown in Section 3. Section 4 summarizes thework and suggests ideas for future.

Av

Bx 1.00101001
×1× 2−3× 2−5× 2−8v_v0nx 0.0011111 (= 0.01 – 0.0000001)
× 2−2

× −2−7v_v0p

Cv_v

v_v0nv_v0p
v_v1nv_v1p
v_v2nv_v2p

v_vv
v_n
v_q
v_u
v_cuv

MUX

MUX

2. 1 DSSN model
The DSSN model is a qualitative neuronal model.
It is designed so that diverse neuronal activities with
fixed point Euler method. Given appropriate parameter
sets, this model can reproduce various neuron classes
including regular spiking (RS), fast spiking (FS),intrinsically busting (IB), and low-threshold spike (LTS).
The model is given by𝑑𝑑 ∅(𝑢)(𝑓(𝑣) − 𝑛 − 𝑞 + 𝐼0 + 𝐼𝑠𝑠𝑠𝑠 ),
=𝑑𝑑
𝜏
𝑑𝑑 1
= (𝑔(𝑣) − 𝑛),𝑑𝑑 𝜏v_v

vnext

Fig.1 Block diagram of the v-circuit. Symbols ×, + and MUXmean a multiplier, adder, multiplexer, respectively.
(A)
Multiplication realized by shift operation and adder. (B) Add
operation of the differential equation of v. (C) Correct 𝑣𝑖𝑖 arechosen by multiplexer depending on v and u.

𝑑𝑑 𝜀= (ℎ(𝑣) − 𝑞),𝑑𝑑 𝜏𝑑𝑑𝑑𝑑𝜀= 1 (𝑣 − 𝑣0 − 𝛼𝛼),𝜏∅0∅(u) = �∅1∅2𝑓(𝑣) ≡ �MUXMUX

2. Methods

𝑔(𝑣) ≡ �(𝑢 < 𝑟𝑢0 )(𝑟𝑢0 < 𝑢 < 𝑟𝑢1 )(𝑟𝑢1 < 𝑢),2

𝑎𝑓𝑓 �𝑣 − 𝑏𝑓𝑓 � + 𝑐𝑓𝑓
2

𝑎𝑓𝑓 �𝑣 − 𝑏𝑓𝑓 � + 𝑐𝑓𝑓
2

𝑎𝑔𝑔 �𝑣 − 𝑏𝑔𝑔 � + cgn
2

𝑎𝑔𝑔 �𝑣 − 𝑏𝑔𝑔 � + 𝑐𝑔𝑔

𝑎ℎ𝑛 (𝑣 − 𝑏ℎ𝑛 )2 + chnℎ(𝑣) ≡ �2𝑎ℎ𝑝 �𝑣 − 𝑏ℎ𝑝 � + 𝑐ℎ𝑝(𝑣 < 0)(𝑣 ≥ 0),�𝑣 < 𝑟𝑔 ��𝑣 ≥ 𝑟𝑔 �,(𝑣 < 𝑟ℎ )(𝑣 ≥ 𝑟ℎ ),where v denotes the membrane potential, and n and q are
the fast and slow variables, respectively, that abstractly
describe the activity of the ion channels. The slow
variable q controls the slow dynamics of the neuronal
activity and has a key role to realize spike-frequency
adaptation and burst firing. Variable u is the slowest thatmodifies the structure of the fast subsystem comprising v
and n. If sustained stimulus to the fast subsystem is taken
as a bifurcation parameter, a saddle-node bifurcation isobserved in the RS, FS, and LTS modes, and ahomoclinic - loop bifurcation in the IB mode. The
parameter I_0 is a bias constant and I_stim represents theinput stimulus. The other parameters determine thedynamical properties of the model. All of the variables
and constants in this qualitative model are purely
abstracted and have no dimension.

Published by Atlantis Press
Copyright: the authors
239

An FPGA-based cortical andFig. 2 The architecture of 16 fully-connected network. The
network is composed of 16 DSSN, 16 silicon synapse, and an
accumulator unit

The model is solved by the Euler’s method ( ∆t =0.0001). We developed differential equations for efficient
implementation. The equations of the circuit forcalculation of v are
𝑣next = 𝑣_𝑣𝑣 + 𝑣_𝑣 + 𝑣_𝑛 + 𝑣_𝑞 + 𝑣_𝐼 + 𝑣_𝑐,𝑣_𝑣𝑣𝑖𝑖 = 𝑣2 ∙ �∆𝑡 ∙ 𝑎𝑓𝑓 ∙ ∅𝑖 /𝜏�,𝑣_𝑣𝑖𝑖 = 𝑣 ∙ �∆𝑡 ∙ 𝑏𝑓𝑓 ∙ 𝑎𝑓𝑓 ∙ ∅𝑖 /𝜏 + 1�,𝑣_𝑞𝑖𝑖 = 𝑞 ∙ (−∆𝑡 ∙ ∅𝑖 /𝜏),𝑣_𝐼𝑖𝑖 = 𝐼stim ∙ (∆𝑡 ∙ ∅𝑖 /𝜏),𝑣_𝑐𝑖𝑖 = ∆𝑡 ∙ (𝑏𝑔𝑔 ∙ 𝑏𝑔𝑔 ∙ 𝑎𝑔𝑔 + 𝑐𝑔𝑔 )/𝜏,
when
when
when
when
when
when

16 silicon synapse units and 16 accumlator units and anAER decoder.
We adopted the silicon synapse circuit in [4] based on
the kinetic synapse model [12].The equations are givenby𝑑𝐼𝑠𝛼(1 − 𝐼𝑠 )=�−𝛽𝐼𝑠𝑑𝑑([𝑇] = 1)([𝑇] = 0)

where, 𝐼𝑠 represent the post-synaptic current and thevalue of [T] is 1 when the membrane potential of thepresynaptic neuron is over the threshold (0). This silicon
synapse unit costs 1 multiplexer and 2 adders, and it
requires 2 clocks by a step.

𝑣_𝑛𝑖𝑖 = 𝑛 ∙ (−∆𝑡 ∙ ∅𝑖 /𝜏),𝑣_𝑥0𝑛
⎧ 𝑣_𝑥0𝑝
⎪
⎪
𝑣_𝑥1𝑛
𝑣_x =
⎨𝑣_𝑥1𝑝⎪⎪ 𝑣_𝑥2𝑛⎩𝑣_𝑥2𝑝Fig. 3 The architecture of external connection. This module has

𝑢 < 𝑟𝑢0 and 𝑣 > 0,𝑟𝑢0 < 𝑢 < 𝑟𝑢1 and 𝑣 > 0,𝑟𝑢1 < 𝑢 and 𝑣 > 0,𝑢 < 𝑟𝑢0 and 𝑣 > 1,𝑟𝑢0 < 𝑢 < 𝑟𝑢1 and 𝑣 > 1,𝑟𝑢1 < 𝑢 and 𝑣 > 1,for 𝑥 = 𝑣𝑣, 𝑣, 𝑛, 𝑞, 𝐼, and 𝑐.

where, i denotes 0, 1, or 2 and j denotes n or p. In these,
equations, we can calculate a product of parameters inadvance and store it as a constant value. Themultiplication of a variable and a parameter is realized byshifters and adders (Fig.1(A)). To reduce the number ofadders, coefficient was approximated by the sum of2^(-x); x denotes arbitrary integer number. Multiplier
circuit is used once in an Euler’s method’s step for
calculation of v^2. v_ij are screened by the multiplexer
depending on the value of v and u (Fig. 1(C)). We
constructed n-circuit and q-circuit in the same way. The
DSSN unit consumes 1 multiplier and 4 multiplexers. The
numbers of adders are 35, 33, 60, and 88 for RS, FS, LTS,and IB classes.

2.2 Circuit architecture
Our circuit is composed of 16 fully-connected neurons
and external input from an address event representation(AER)–basedstimulus
receivermodule.
Thefully-connected neuronal network consumes 16 DSSN
and 16 silicon synapse units and an accumlator unit
comprising 1 multiplier and 1 adder and an 18kb blockrandom access memory that stores synaptic weights (Fig.
2). The synapse units calculate postsynaptic input
depending on the 1-bit signal that denotes whether themembrane potential v of the pre-synaptic DSSN is over
the threshold or not. The accumlator unit calculates
weighted sum of the post-synaptic input. The 𝐼stim iscalculated as follows.

Published by Atlantis Press
Copyright: the authors
240

16𝑗𝑖
𝐼stim = 𝐶0 � 𝑤𝑖𝑖 𝐼𝑠 + 𝐼𝑒𝑖
𝑗=1

Takuya Nanami, Takashi Kohno

assumption that a clock correspond to 10 ns. We represent
all variables and synaptic weights using 18-bit signed
fixed point with 14-bit fractions.

Fig .4 Waveforms generated by the DSSN unit of RS (a), FS (b),LTS (c, d), IB (e). Excitable step inputs rise at t = 0.1 (a-c,e).
inhibitory step inputs are provided from t = 0.2 to t = 1.0 (d).

where i and j are the indices of the post- and pre- synaptic
neurons respectively, and 𝐼𝑒𝑖 denotes an external input tothe i th neuron, respectively. The parameter 𝑐0 is acoefficient to scale 𝐼stim into an appropriate range.
The units for the external connection is composed of 16
silicon synapse units and 16 accumulator units and an
AER decoder (Fig.3). AER decoder receives 14-bit input
signal by a clock. First 12-bit of input signal specifies anaddress of 4096 synapses by AER decoder. Next 1-bit
represents rising or trailing of the pulse input, and thevalue of the bit is stored in the register corresponding to
the specified address. Therefore, we can assigne input
pulse having an arbitrary length. Last 1-bit is an enable
signal.
Synaptic weights are loaded from the 16 18kb blockrandom access memory. A synapse unit updates 256
post-synaptic current depending on the decoded input
signal at each ∆t step, and the accumulator unit
calculates an weighted sum of the post-synaptic inputs.
256𝐼𝑒𝑖 = 𝑐1 � 𝑤𝑖𝑖 𝐼𝑠𝑘𝑘=1

where i and k are the indices of the neurons andsynapses, respectively. The parameter 𝑐1 is a coefficient
to scale 𝐼𝑒𝑖 into an appropriate range.
In our system, a ∆t step corresponds to 1024 clocks,
and 1024 input signals are acceptable by 1 step. TheDSSN unit require 10000 steps to simulate a second, andit runs 10 times faster than real-time under theFig.5 Raster plots of the spikes in the network. Neurons are RS(Neuron ID = 0-3), FS (4-7), LTS (8-11), IB (12-15).

3. ResultHere, we show the waveforms generated by the DSSN
unit in response to external stimulus inputs. Figure 4(a)shows the waveform of the RS class that is a most typicalneuron class in the cortex. A characteristic behavior ofthis class is spike-frequency adaptation; that is, the spikefrequency decreases over time in response to a constantstimulation input. On the other hand, FS neurons fire withalmost constant frequency (Fig.4(b)). LTS neurons
exhibit periodic firing in reaction to excitable inputstimulus (Fig.4(c)) and generate a burst firing just after
the termination of a sufficient hyperpolarizing stimulus(Fig.4(d)). IB neurons generate the bursting at the onsetof a stimulus, then continue to spiking (Fig. 4(e)).
Figure 5 shows raster plots of the spikes in the network.
We applied 12-bit signal correspond to each neuron byrotation and evoked spike, and additional spikes wereevoked by the inner connection. Synaptic weights wereassigned randomly.
4. Conclusion
In this paper, we constructed digital circuit of the DSSNmodel that supports four cortical and thalamic neuronclasses. The implemented circuit could generate activities
qualitatively comparable to the ionic-conductance modelfor each neuron class. It consumed only 1 multiplier for
calculation of an Eular’s Method’s step, which is an
expensive module in an FPGA. We confirmed thebehavior of a network of 16 fully-connected DSSNs thatcan receive stimuli via 4096 synapses. Each synapse iscontrolled by 12-bit input signal through an AER
decoder.

Published by Atlantis Press
Copyright: the authors
241

An FPGA-based cortical andOur previous study implemented the DSSN model that
supports the Class I and Class II in the Hodgkin’sclassification. We expect the circuit constructed in thiswork will be a basis for digital silicon neuronal networks
that can support a wide variety of neuronal activities
more elaborately than the I&F-based circuits.
In future works, we will implement the DSSN modelthat supports the square-wave bursting and elliptic
bursting which were already realized by software
simulation. Larger-scale network will also be pursued.
Acknowledgement

This work was supported by JSPS Grant-in-Aid for scientific
Exploratory Research Number 25240045.

Reference
1. R. K. Weinstein and R. H. Lee. Architectures for

2.

3.

4.

high-performance fpga implementations of neural models.
J. Neural Eng, 3(1):21–34, 2006.
M. J. Pearson, A. G. Pipe, B. Mitchinson, K. Gurney, C.
Melhuish, I. Gilhespy, and M. Nibouche. Implementing
spiking neural networks for real-time signal-processing
and control applications: A
model-validated fpgaapproach. IEEE Transactions on Neural Networks,
18(5):1472–1487, 2007.
D. B. Thomas and W. Luk. Fpga accelerated simulation ofbiologically plausible spiking neural networks. In K. L.
Pocek and D. A. Buell, editors, FCCM, pages 45–52. IEEE
Computer Society, 2009
J. Li, Y. Katori, and T. Kohno. An fpga-based siliconneuronal network with selectable excitability siliconneurons. Frontiers in neuroscience, 6(183), 2012.

5.

T. Kohno and K. Aihara. Digital spiking silicon neuron:
Concept and behaviors in gj-coupled network. Proceedingsof International Symposium on Artificial Life and Robotics
2007, 2007.
6. A. L. Hodgkin. The local electric changes associated withrepetitive action in a non-medullated axon. The Journal ofphysiology, 107(2):165–181, Mar. 1948
7. X.-J. Wang and J. Rinzel. Oscillatory and bursting
properties of neurons. In M. A. Arbib, editor, The
Handbook of Brain Theory and Neural Networks, pages
835–840. MIT Press, MA, 2nd edition, 2003.
8. N. Fourcaud-Trocmé, D. Hansel, C. van Vreeswijk, and N.
Brunel, How spike generation mechanisms determine theneuronal response to fluctuating inputs, J. Neurosci.,
23(37):11628 –11640, 2003.
9. R. Brette and W. Gerstner. Adaptive ExponentialIntegrate-and-Fire Model as an Effective Description ofNeuronal Activity. J. Neurophysiol., 94:3637–3642, 2005.
10. T. Nanami and T. Kohno. Simple cortical and thalamic
neuron models for digital arithmetic circuit implementation.
In preparation.
11. M. Pospischil, M. Toledo-Rodriguez, C. Monier, Z.
Piwkowska, T. Bal, Y. Fregnac, H. Markram, and A.
Destexhe. Minimal hodgkin-huxley type models fordifferent classes of cortical and thalamic neurons.
Biological Cybernetics, 99(4-5):427–441, 2008.
12. Alain Destexhe, Zachary F. Mainen, and Terrence J.
Sejnowski. Kinetic Models of Synaptic Transmission. in:
Methods in Neuronal Modeling, Edited by Koch, C. andSegev, I. (2nd Edition) MIT Press, Cambridge, 1998

Published by Atlantis Press
Copyright: the authors
242