APPLICATION NOTE
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MOSFET Gate Drive Requirements and Initial
Parameter Set Solution with the NCV7544,
NCV7546 and NCV7547 Half-bridge Pre-drivers
AND90124/D
Introduction

In practice, a MOSFET’s gate input capacitances arecharged via programmable currents and timer intervals. The
gate charge parameters are obtained directly from the target
MOSFET product’s datasheet.
The high−side MOSFET’s gate charge/discharge isdeveloped in three phases as shown in Figure 1:
I. a turn−on (turn−off) pre−charge phase;
II. a turn−on (turn−off) slew phase;
III. a turn−on (turn−off) overdrive phase.
The low−side MOSFET’s gate charge/discharge (notshown in the diagram) is developed in a single ‘phase’.
The figure is adapted to the familiar idealized totalgate−source charge curve as found in MOSFET datasheets,with the orange curve representing the high−side
MOSFET’s gate voltage VGHX vs. gate charge QG and theblue curve representing the high−side MOSFET’s source
voltage VHBX vs. gate charge QG. Because the high−side
MOSFET is configured as a (large−signal) source follower,
the gate and source voltages are changing together.

The NCV7544, NCV7546, and NCV7547 are a family of
FLEXMOS™ products for controlling half−bridgeconnected MOSFETs in automotive actuator applications.
These multichannel pre−drivers feature a charge−based gate
drive topology that utilizes programmable charge/discharge
currents and timers in order to tailor switching performance
to a particular MOSFET’s gate charge parameters.
This application note describes the various elements of thegate drive topology along with a series of analyticalsolutions for successful pairing of the pre−driver and
MOSFETs while preserving the products’ embedded
protection and EMI−reducing slope control functionality.
Gate Drive Principle

The gate charge principle is based on the well−known
capacitor charge relationship given by
Q + C @ dv + i @ dt

© Semiconductor Components Industries, LLC, 2022

January, 2022 − Rev. 0(eq. 1)1

Publication Order Number:AND90124/D

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Figure 1. Idealized Gate Charge Evolution
High−side MOSFET Charge(Once tSLEW is determined, a dynamic VDS
overload detection1 delay time tDLYX can be selectedfrom a range of values such that tDLYX > tSLEW. The
same tDLYX value is used for both rising and fallingslope dynamic VDS detection delay, and 3x thetDLYX value is used for static VDS detection delay.)III. In the overdrive phase, the gate continues to be
charged via the selected ISRX value up to the drive
voltage compliance value of the current source,
VPDHX. After a delay time tTIMEOUT, the ISRX
current is reduced to a steady−state holding current2
IGHX_SS. The amount of overdrive charge QG(OD) isdetermined from the MOSFET datasheet values
QGS, QGD, and QG(TOT, 10V):

Referring to Figure 1, the high−side MOSFET’s gatecharge is developed in the following phase sequence.
I. In the turn−on or rising slope pre−charge phase, QGS
is supplied to develop gate voltage to just below thevalue needed to support a particular drain current(e.g. VGS1). QGS is constructed using one of a rangeof rising slope pre−charge currents IPRCX_R andtimer values tPRCX so thatQ GS + I PRCX_R

t PRCX(eq. 2)The same tPRCX value is used for both the rising andfalling pre−charge phases.
II. In the slew phase, QGD is supplied to increase thegate voltage up to the ‘plateau’ voltage VGS1 where
it remains nearly constant with respect to the
MOSFET’s source as the source voltage rises at aconstant rate. A target slope−time value tSLEW −which represents the time required to transition
through the plateau − is constructed using the target
MOSFET’s datasheet QGD value and one of a rangeof rising/falling slope currents ISRX so thatt SLEW +Q G(OD) + k HS(Q G(TOT, 10V) * Q GS * Q GD);
k HS +(10 * V GS(ID))(eq. 4)

The time required for the overdrive charge to beaccumulated is given byt OD_R +

Q GD
I SRX

(V PDHX * V GS(ID))(eq. 3)

1. Not available in the NCV7547 product.
2. The holding current functionality applies only to the high−side pre−driver.

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Q GD(OD)I SRX(eq. 5)

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The turn−on time interval tTURN−ON_HS is comprised of
the sum of the time intervals for each phase:

The turn−off time interval tTURN−OFF_HS is comprised of
the sum of the time intervals for each phase:t TURN*OFF_HS + t PRCX ) t SLEW ) t OD_F +t TURN*ON_HS + t PRCX ) t SLEW ) t OD_R ++ t PRCX )

1
I SRX

(Q GD ) Q GD(OD))+ t PRCX )(eq. 6)t PRCX(eq. 7)

Low−side MOSFET Charge

The low−side MOSFET’s gate charge and discharge
phase is developed via a 4x multiple of the same value ofslew current ISRX as is chosen for the high−side slew phase.
The turn−on and turn−off time intervals are determined by
the ISRX current and the MOSFET’s total gate charge so that

II. The falling slope slew phase is ideally identical to therising slope slew phase. QGD is removed via thesame magnitude of current ISRX at the same rate as
the rising slope so thatt FALL + t RISE + t SLEW +

Q GD
I SRX

(eq. 8)t ON ⎢OFF_LS +I. In the overdrive phase, the gate continues to bedischarged via the selected ISRX value down to thedrive voltage compliance limit of the current sink.
The amount of turn−off overdrive charge to be
removed is the same QGS as supplied in the turn−on
pre−charge phase. so the time required for theremaining charge to be removed ist OD_F +k LS +Q G(TOT, 10V)

k LS
4

I SRX

,

(V PDLX * V GS(ID))(10 * V GS(ID))(eq. 11)

where VPDLX is the drive voltage compliance value of thelow−side current source/sink.

Q GS
I SRX

(eq. 10)where tPRCX and ISRX are the same values as selected for therising slope, and tSLEW and tOD_R are dependent uponcharge current ISRX and the MOSFET’s QGD and QGDS gatecharge values.
The overall timing and drive current selections tPRCX,tDLYX, IPRCX_R, and ISRX must be chosen carefully in orderto optimize switching slope vs. MOSFET switching powervs. EMI trade−offs and to prevent false dynamic VDS
overload detection events. The turn−on and turn off
pre−charge selections should be chosen to avoid DQGS
overshoot at turn−on in order to minimize EMI, and to avoid
DQGD undershoot at turn−off to prevent shoot−through withthe low−side MOSFET.

where tPRCX and ISRX are selected from a defined range ofvalues, and tSLEW and tOD_R are dependent upon charge
current ISRX and the MOSFET’s QGD and QGD(OD) gatecharge values.
The high−side MOSFET’s gate discharge is developed byreversing the sequence of gate charge phases.
III. In the turn−off or falling slope pre−charge phase,
QG(OD) is removed to reduce gate voltage to justabove the value needed to support a particular draincurrent (e.g. VGS1). QG(OD) is constructed using oneof a range of falling slope pre−charge currents
IPRCX_F and the same tPRCX value used as for therising pre−charge phase
Q G(OD) + I PRCX_F

1(Q ) Q GS)I SRX GD

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PWM Input Deglitch

Two types of adaptive de−glitch are provided, with the‘type 2’ scheme resulting in a shorter tPWM_DGL2 time tofacilitate duty ratios closer to 100% in some cases. Witheither de−glitch type, a state change at the PWMx input must
be maintained for at least as long as the tPWM_DGL time inorder for the change to be propagated to the gate pre−driver.

The high−side and low−side MOSFET switching can bedone via SPI or can be synchronized to an external signal via
PWMx inputs as shown in Figure 2 below. When switching
via PWM, an adaptive de−glitch buffer is used to:• synchronize the external signal to the logic core clock;• de−glitch the signal using combinations of the selected
tBLANKX, tPRCX, and tDLYX timer values

Figure 2. Adaptive De−glitch Timing− Type 1 and Type 2

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Timing Constraints

so analysis of the PWM signal path delay and the resulting
timing constraints are considered next.
In Figure 3 below, I(GHX) or I(GLx) charge/turn−oncurrents prefixed with ‘−’ are sourced out of the GHx or GLx
pin and shown in red. Discharge/turn−off sink currents are
prefixed with ‘+’ are shown in green.

The evolution of the high−side or low−side gatecharge/discharge sequence is synchronized to either the SPI
signal path or the PWMx input signal path. While each path
has propagation delays, the PWM signal path is used whencontrolling the average voltage at the HBx switching node,

Figure 3. Adapted Internal Gate Drive Timing
Low−side Turn−off, High−side Turn−on

and 3 tDLYX respectively, are started along with slew current
ISRX. The same values selected for tDLYX and for ISRX areused for all relevant tDLYX and ISRX (tSLEW) timing
intervals.
The dynamic and static blanking timers run concurrently,
but the dynamic blanking timer is the focus in this analysis
because the expectation is that the slew phase is completed
before the end of the dynamic VDS blanking interval so that

Referring to Figure 3, turn−off of the low−side gate drive
is synchronized to the de−glitched internal signal
PWMx_DGL and begins at the rising edge of PWMx_DGL
where a non−overlap timer tBLANK is started. The
expectation is that the low−side MOSFET’s gate will befully discharged before turn−on of the high−side MOSFET
begins at the end of the tBLANK interval. The same value
selected for tBLANK is used for all relevant tBLANK timing
intervals shown in the diagram.
Turn−on of the high−side gate drive begins at the end of
the tBLANK time interval where the high−side MOSFET
pre−charge timer tPRCX is started along with the tTIMEOUT
limit timer. The same value selected for tPRCX is used for all
relevant tPRCX timing intervals.
At the end of the pre−charge interval, the high−side VDS
overload dynamic and static blanking detect timers, tDLYX

t DLYX u t SLEW

(eq. 12)This result makes clear that the value of tDLYX chosen forthe dynamic VDS blanking interval is dependent upon theselected value slew current ISRX and the MOSFET’sgate−drain charge QGD. The requirement of equation 12
ensures that the dynamic overload detection function ispreserved.

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While the PWMx_DGL signal remains in the ‘1’ state,
overdrive charge QG(OD) continues to accumulate via theselected ISRX value. Since the falling slope/turn−off
pre−charge current IPRC_F is chosen to deplete theaccumulated overdrive charge, the minimum high−side‘ON’ time needs to account for this condition by replacing
tDLYX with tSLEW + tOD_R. If this is not accounted for, theturn−off pre−charge current will be much larger than that
required to deplete the lower accumulated charge if ‘ON’time is constructed instead using tDLYX, and the turn−offslope can be abrupt due to pre−charge overshoot.
The previously defined turn−on time intervaltTURN−ON_HS (Equation 6) is modified here to include thetBLANK interval so that the minimum high−side ‘ON’ timetON(MIN_HS) is defined ast ON(MIN_HS) + t BLANK ) t PRCX ) t SLEW ) t OD_R

the time interval tTURN−OFF_HS (Equation 10) required todeplete the remaining gate charge, which is dependent upon
the ISRX, QGD, and QGS values.
At the end of the second blanking interval, the low−sidedynamic VDS overload time interval tDLYX is started. The
expectation is that the low−side turn−on is completed before
the end of the tDLYX interval (previously dimensioned
according to the slew current ISRX as selected to satisfy thehigh−side turn−on requirements) such that the following
condition tDLYX > tON|OFF_LS (Equation 11) is satisfied forthe low−side MOSFET:t DLYX u(eq. 13)Turn−off of the high−side gate drive begins at the fallingedge of PWMx_DGL where a first tBLANK time interval isstarted. This first blanking interval provides symmetry withrespect to the rising and falling edges of the PWMx_DGL
signal.
At the end of the first blanking interval, the high−side
pre−charge tPRCX time interval is started along with a second
tBLANK non−overlap time interval. The expectation is thatthe high−side MOSFET’s gate will be fully discharged
before turn−on of the low−side MOSFET begins at the endof the second tBLANK interval so that at turn−off of thehigh−side (refer to Figure 3) we have QG(OD) = QGS so thatI SRXt ON(MIN_LS) + 2(eq. 15)t BLANK ) t DLYX

(eq. 16)

PWM Limitations

When all of the gate drive parameters (tPRCX, IPRCX_R,
IPRCX_F, ISRX, tDLYX, tBLANKX) have been selected, anestimate of the allowable PWM frequency and duty ratios
can be made. PWM limitations based on timing
requirements and charge pump loading include:• the type of adaptive de−glitch selected and the resulting
tPWM_DGL value;• the minimum high−side and low−side ‘ON’ timeintervals, tON(MIN_HS) and tON(MIN_LS) respectively;• the capability of the particular pre−driver product’s
charge pump.
Construction of the PWM period is as shown in Figure 4.

(Q GD ) Q GS)
I SRX

4

Since the low−side drive current is 4 times the selected
ISRX value, it is assured that the low−side MOSFET will befully on by the end of the tDLYX interval, assuming the same
MOSFET types are used for both high−side and low−sideswitches. The minimum low−side ‘ON’ time tON(MIN_LS) is
defined as

High−side Turn−off, Low−side Turn−ont BLANK u t TURN*OFF_HS u t PRCX )Q G(TOT, 10V)

k LS

(eq. 14)This result makes clear that the value of tBLANK chosen
for the non−overlap blanking interval is dependent upon theselected rising/falling pre−charge time interval tPRCX plus

Figure 4. PWM Period Construction
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The de−glitched input signal PWMx_DGL is comprisedof combinations of the same tBLANKX, tPRCX, and tDLYX
timer values that are used for constructing the respectivehigh−side and low−side ‘ON’ time intervals.
A state change at the PWMx input must be maintained forat least as long as the tPWM_DGL time in order for that change
to be propagated internally to the gate pre−driver. For eithertON(MIN_HS) or tON(MIN_LS), and for both tPWM_DGL1 andtPWM_DGL2 de−glitch types, this leads to the boundary
condition requirementt ON(MIN_HS⎢LS) u t PWM_DGL

The first requirement of equation 19 must be met for thehigh−side MOSFET to just begin its turn−on sequence while
the second requirement of equation 20 must be similarly met
for the low−side MOSFET to just begin its turn−on
sequence. Failure to meet the first requirement will result in
no energy being delivered to the load. Failure to meet thesecond requirement will result in stored load energy being
passively recirculated in the low−side MOSFET’s body
diode instead of the active RDS(ON) of its channel resistancewhich can result in increased power dissipation.

(eq. 17)

Charge Pump Loading

In a half−bridge topology, energy is delivered to the load
during the high−side MOSFET ‘ON’ time, and energy is(actively) recirculated in the load during the low−side
MOSFET ‘ON’ time. The achievable duty ratio ‘D’ withfrequency fPWM(MAX) = 1/TPWM(MIN) is determined withrespect to the high−side ‘ON’ time via the minimum
high−side ‘ON’ time and minimum low−side ‘ON’ timevalues:f PWM(MAX)t ON(MIN_HS) v D v 1 * (f PWM(MAX)In addition to the PWM timing requirements, charge
pump loading needs to be considered so that the charge
pump’s capability is not exceeded. An analysis based onenergy stored in a capacitor provides an estimate of the total
steady−state average gate charge QG(TOT_SS) the charge
pump could support3:
Q G(TOT_SS) + 2

t ON(MIN_LS))

Using tON(MIN_HS) to set the lower duty ratio boundensures that the minimum high−side ‘ON’ time is satisfied,
while using tON(MIN_LS) to set the upper duty ratio boundensures that the minimum low−side ‘ON’ time is satisfied.
Referring to Figure 4, it can be seen that each of theinternal high−side GHx and low−side GLx signals aredelayed by a multiple of the tBLANK blanking time interval.
The delay, which is needed in order to prevent ashoot−through (or cross−conduction) hazard between thehigh−side and low−side MOSFETs, imposes a further set ofboundary condition requirements:t BLANK

D (MAX) v 1 * (f PWM

2

f PWM

Ǔ

(eq. 21)Pre−driver Parameter Solution Example

The following worked example is offered as a method forconstructing a pre−driver and target MOSFET initial
parameter solution set. The method is applicable to each of
the NCV7544/46/47 family devices. An onsemi
NVMFS5C460NL 40 V/4.5 mW/78 A logic−level device ischosen as a target MOSFET for the example.
A table of gate parameters (Figure 5) and a total gatecharge curve (Figure 6) from the NVMFS5C460NL4
datasheet are shown below.

(eq. 19)t BLANK)I CP(DC) * I DC

where IDC is any static loading current (e.g. bleed resistancesetc.), and ICP(DC) is the steady−state charge pump current
specified in the pre−driver product’s datasheet. The PWM
frequency may be the datasheet recommended maximum
value (25 kHz) or any lower target value.

(eq. 18)

D (MIN) w f PWM

ǒ(eq. 20)

Figure 5. NVMFS5C460NL Datasheet – MOSFET Gate Parameters

3. Since the analysis goal is to determine the steady state gate charge supplied by the charge pump, discharge of the gate is not considered here.
4. onsemi product datasheet publication order number NVMFS5C460NL/D, February, 2017 − Rev. 2

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Figure 6. NVMFS5C460NL Datasheet – MOSFET Total Gate Charge Curve

The MOSFET’s gate charge parameters QGS, QGD, and
QG(TOT) at VGS = 10 V will be used for the solution. The gatecharge curve characterizes typical device behavior at theparticular operating point as given for the gate chargeparameters – i.e. VGS = 10 V, VDS = 20 V, and ID = 35 A.
Other operating points will result in different values for thegate charges since QGS will vary with ID as VGS(ID) varies,
while QGD and QG(TOT) will vary as VDS varies. An
assumed slew time tSLEW = 1 ms will be targeted. The
example solutions assume nominal conditions and do nottake into account component tolerances or environment
effects.

VGS(ID) = VGP are taken directly from the MOSFET
datasheet, and the VPDHX value directly from the pre−driverdatasheet giving
Q G(OD) +(10 * 3.3) V(23 * 4.7 * 3.0) nC + 12.8 nC

Applying this result to equation 7 gives
Q PRC_F + Q QG(OD) + I PRCX_F

t PRCX + 12.8 nC

Both the rising and falling pre−charge phases use the sametime interval tPRCX while suitable values for the charge anddischarge currents need to be selected to match the target
MOSFET’s respective QGS and QG(OD) requirements
without significant overshoot or undershoot.
The pre−driver products’ datasheets provide the available
pre−charge time and current parameters, which are used toconstruct pre−charge solutions from the following tables foreach of the rising slope (Table 1, QPRC_R = 4.7 nC) andfalling slope (Table 2, QPRC_F = 12.8 nC) targets.

Rising and Falling Pre−charge Solutions

The rising pre−charge requirement QPRC_R is taken
directly from the MOSFET datasheet QGS value and applied
to equation 2:
Q PRC_R + Q GS + I PRCX_R(8.9 * 3.3) V

t PRCX + 4.7 nC

The falling pre−charge requirement QPRC_F is evaluated
via equation 4. The values QG(TOT, 10V), QGS, QGD, andTable 1. RISING SLOPE PRE−CHARGE SOLUTIONS

Pre−charge Rise Current IPRC_R (mA): I_PCRx[2:0]
1.50

5.25

8.63

tPRC (ns)

12.38

16.50

20.25

24.00

28.13

Turn−on/Rise Pre−charge QPRC_R (nC)

100

0.15

0.53

0.86

1.24

1.65

2.03

2.40

2.81

200

0.30

1.05

1.73

2.48

3.30

4.05

4.80

5.63

300

0.45

1.58

2.59

3.71

4.95

6.08

7.20

8.44

400

0.60

2.10

3.45

4.95

6.60

8.10

9.60

11.25

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Table 2. FALLING SLOPE PRE−CHARGE SOLUTIONS
Pre−charge Fall Current IPRC_F (mA): I_PCFx[2:0]
28.88

35.63

tPRC (ns)

42.00

48.38

2.89

200

5.78

7.13

8.40

300

8.66

10.69

12.60

400

11.55

14.25

16.80

19.35

3.56

4.20

4.84

67.88

74.63

5.51

6.15

6.79

7.46

9.68

11.03

12.30

13.58

14.93

14.51

16.54

18.45

20.36

22.39

22.05

24.60

27.15

29.85

Two potential solutions for each of the rising/fallingpre−charge intervals are selected from the tables (shaded
cells):
1. rising slope pre−charge, target QGS = 4.7 nC:
a. tPRCX = 200 ns, IPRC_R = 24.0 mA,
QGS = 4.80 nC
b. tPRCX = 300 ns, IPRC_R = 16.5 mA,
QGS = 4.95 nC
2. falling slope pre−charge, target QG(OD) = 12.8 nC:
a. tPRCX = 200 ns, IPRC_F = 61.5 mA,
QG(OD) = 12.3 nC
b. tPRCX = 300 ns, IPRC_F = 42.0 mA,
QG(OD) = 12.6 nC
Defining the relative magnitude DQG(%) as the ratio of achosen solution QG(CHOSEN) value to a target QG(TARGET)
value givesǒ

Q G(CHOSEN)Q G(TARGET)

Ǔ

*1

100%

t SLEW_F +DQ G(OD)(300ns) +12.6* 1 + * 1.6%
12.8

I SRX

+ 3.5 nC

Since the value chosen for tSLEW applies to both rising andfalling slopes, the larger of the resulting QSLEW_R or
QSLEW_F values (3.5 nC > 2.9 nC) drives the solution for an
appropriate value ISRX needed to satisfy the target tSLEW
time.
For this worked example, an assumed target slew timetSLEW = 1 ms is targeted. Using the larger QSLEW_F
computed value and rearranging equation 23 yields
I SRX +Q SLEW_Ft SLEW+

3.5 nC
1 ms+ 3.5 mA

The pre−driver products’ datasheets provide the available
ISRX slew current parameters together with a range ofrepresentative QGD values which are used to construct aslew time solution from those given in Table 3 below5.

Q SLEW_R
I SRX(eq. 25)

Q SLEW_F + Q GD " DQ G(OD) + 3.0 nC ) (12.8 * 12.3) nC +Any DQG charge overshoot/surplus or undershoot/deficit
will affect the target slew time solution, which is determinedby the slew current ISRX and the target MOSFET’s datasheet
QGD charge in the ‘plateau’ region, plus or minus any
pre−charge surplus or deficit. Modifying equation 3
accounts for this effect so that+(eq. 24)+ 2.9 nC

Rising and Falling Slew Solution

Q GD " DQ GS

I SRX

Q SLEW_R + Q GD " DQ GS + 3.0 nC ) (4.7 * 4.8) nC +Similarly, evaluating the two falling slope solutions for
relative DQG(OD) overshoot and undershoot gives
12.3* 1 + * 3.9%;
12.8

Q SLEW_F

Evaluating the numerators of equation 23 and equation 24
with the MOSFET’s datasheet target QGD requirement andthe respective DQG magnitude values as defined via
equation 25 yields(eq. 22)

4.95* 1 + ) 5.3%
4.70

DQ G(OD)(200ns) +

I SRX

+

DQ G + Q G(TARGET) * Q G(CHOSEN)

4.80
DQ GS(200ns) +* 1 + ) 2.1%;
4.70
DQ GS(300ns) +Q GD " DQ G(OD)

The choice of a dynamic VDS overload delay time tDLYX
with respect to tSLEW also needs to be considered so that thetiming constraint of Equation 12 tDLYX > tSLEW is not
violated.
Since a single value for tDLYX applies to both rising andfalling slopes, a better choice for a pre−charge solution set
is provided via solutions QGS = 4.80 nC (1.a) and QG(OD) =12.3 nC (2.a) as these are more closely matched in terms of
their relative DQG magnitudes (i.e. +2.1% and −3.9%
respectively).
Defining the signed magnitude of DQG as the difference
between the target value QG(TARGET) and the chosen
solution value QG(CHOSEN) gives

Evaluating the two rising slope solutions via equation 22
for relative DQGS overshoot (+%) and undershoot (−%)
gives

t SLEW_R +61.50

Turn−off/Fall Pre−charge Fall QPRC_F (nC)100

DQ G(%) +55.13(eq. 23)

5. From the table it can be seen that if a unit charge value QGD = 1 nC is used together with a slew current value, the result is a unit slew time
ms/nC that can be used to scale the slew time via the actual target QGD value.

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Table 3. RISING/FALLING SLOPE SLEW SOLUTIONS
Rising/Falling Slope Slew Current ISRX (mA): SR_CTRL[2:0]
1.50

2.25

3.38

5.25

7.88

11.63

17.25

25.50

Target MOSFET QGD (nC)

Slew Time tSLEW (ms)
1.00

0.67

0.44

0.30

0.19

0.13

0.09

0.06

0.04

2.00

1.33

0.89

0.59

0.38

0.25

0.17

0.12

0.08

3.00

2.00

1.33

0.89

0.57

0.38

0.26

0.17

0.12

4.00

2.67

1.78

1.18

0.76

0.51

0.34

0.23

0.16

5.00

3.33

2.22

1.48

0.95

0.63

0.43

0.29

0.20

6.00

4.00

2.67

1.78

1.14

0.76

0.52

0.35

0.24

7.00

4.67

3.11

2.07

1.33

0.89

0.60

0.41

0.27

8.00

5.33

3.56

2.37

1.52

1.02

0.69

0.46

0.31

9.00

6.00

4.00

2.66

1.71

1.14

0.77

0.52

0.35

Choosing ISRX = 3.38 mA and substituting this value into
equation 23 givest SLEW_F +Q SLEW_F
I SRX+

3.5 nC
3.38 mA

Using the IPRCX value chosen to construct the tSLEW
solution now allows a tBLANK solution to be constructed via
equation 14. Substituting the values for tPRCX and QSLEW_F,
and the target MOSFET’s QGS value together with thechosen ISRX solution yields:+ 1.04 mst BLANK u t PRCX )Dynamic VDS Delay Time and Blanking Time Selection

Having determined a solution for tSLEW, a dynamic VDS
overload delay time can be selected from the values in
Figure 7 below6. A value of tDLYX = 1.20 ms is chosen for
dynamic VDS delay, which satisfies the tDLYX > tSLEW
timing constraint of equation 12 (i.e. 1.20 ms > 1.04 ms) andprovides a 15.4% margin:ǒ

1.20 ms
1.04 msǓ*1(Q SLEW_F ) Q GS)I SRXt BLANK u 200 ns )(3.5 ) 4.7) nC
3.38 mA

u 2.63 ms

A blanking time tBLANK = 3.0 ms is chosen from thepre−driver products’ datasheets (Figure 7) which satisfies
the timing constraint of equation 14 (i.e. 3.0 ms > 2.63 ms)
and provides a 14.1% margin:ǒ

100% + 15.4%

3.0 ms
2.63 msǓ*1

100% + 14.1%

6. The T_DLYX[3:0] values in Figure 7 include the adjustment for tSYNC (50 ns typ.) as noted in the products’ datasheet.

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10AND90124/D

Figure 7. Dynamic VDS Detection Delay and Blanking Time Values − Datasheet Selections
Minimum ‘ON’ Time Solutions

t PWM_DGL2 + t PRCX ) t DLYXThe solutions for the high−side and low−side minimum‘ON’ time intervals, defined respectively by equation 13 forthe high−side (with tOD_R expanded via equation 5 andtSLEW replaced by tSLEW_R and expanded via equation 23),and defined by equation 16 for the low side, can now be
evaluated by substituting the values for the indicatedparameters into those equations:t ON(MIN_HS) + t BLANK ) t PRCX )ǒt ON(MIN_HS) + 3.0 ) 0.2 )Evaluating these two equations by substituting thenecessary parameters yields:
t PWM_DGL1 + t BLANKX ) t PRCX ) t DLYXt PWM_DGL1 + (3.0 ) 0.2 ) 1.2) ms + 4.40 ms

t PWM_DGL2 + (0.2 ) 1.2) ms + 1.40 ms

t ON(MIN_LS) + 2

t BLANK ) t DLYXt ON(MIN_LS) + 2

3 ms ) 1.2 ms + 7.20 msǓ

ms + 7.84 ms
eq. 13eq. 16Note the relative symmetry of the high−side and low−sideminimum ‘ON’ time intervals.
PWM Deglitch Timet ON(MIN_HS) u t PWM_DGL1; 7.84 ms u 4.40 ms

Two types of adaptive deglitch time tPWM_DGL intervals
are defined in the pre−driver products’ datasheets, and they
are re−stated here as tPWM_DGL1 and tPWM_DGL2
respectively for type 1 and type 2:t PWM_DGL1 + t BLANKX ) t PRCX ) t DLYX

eq. 27

With either de−glitch type, a state change at the PWMx
input must be maintained for at least as long as thetPWM_DGL time in order for the change to be propagated to
the gate pre−driver. Referring to Figure 4 it can be seen thatthe de−glitch is applied to both the rising and falling edgesof the PWMx input signal and so applies a symmetrical timedelay between the external and internal signals.
Evaluating the minimum ‘ON’ time values obtained via
equation 13 and equation 16 vs. the boundary condition
requirement of equation 17 by substituting the result
obtained via equation 26 yields:

I SRX

3.38 mA

eq. 26t PWM_DGL2 + t PRCX ) t DLYX(Q SLEW_R ) Q GD(OD))(2.9 ) 12.8) nC(eq. 27)t ON(MIN_LS) u t PWM_DGL1; 7.20 ms u 4.40 ms

eq. 17Since tDGL1 > tDGL2, the boundary condition requirement
is satisfied for both the high−side and the low−sideminimum ‘ON’ times using either de−glitch type.

(eq. 26)

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AND90124/D
PWM Duty Ratio Solutions

order of 10x to 20x of the PWM period. The inductor’s‘self−resistance’ can be dimensioned according to:

The duty ratio ‘D’ achievable with period TPWM (orfrequency fPWM) is bounded by the minimum high−side andlow−side ‘ON’ time values as defined via equation 18.
Rearranging equation 18 gives solution forms for thebounded values of ‘D’:
D w f PWM(MAX)t ON(MIN_HS)

7.84 ms

D v 1 * (25 kHz

7.20 ms)

eq. 28

100% w 82.0%

eq. 29For seat positioning applications, 23% duty may be low
enough for minimum motor torque, but 79% might be too
low for peak torque loads. Assuming a minimumfPWM(MIN) = 15 kHz value (which is typically the upper
limit of human hearing) and substituting yields
D w 15 kHz

7.84 ms

D v 1 * (15 kHz

100% w 11.8%

7.20 ms)

eq. 28

100% v 89.2%

eq. 29If power dissipation in the low−side MOSFET is not aconcern, then passive recirculation may be allowed and the
maximum achievable duty ratio may be extended via
equation 20 so that
D (MAX) v 1 * (f PWM

2

D (MAX) v 1 * (15 kHz

t BLANK)2

3.0 ms)100% v 91.0%

eq. 20Charge Pump Loading vs fPWM

Finally, having determined the allowable PWM timing
requirements, charge pump loading needs to be considered
so that the charge pump’s capability is not exceeded. For
example, evaluating ICP(DC) = 15 mA and fPWM = 15 kHz
and assuming zero static load IDC gives
Q G(TOT_SS) + 2

ǒI CP(DC) * I DC

Q G(TOT_SS) + 2000 nC

f PWM

Ǔ

+2

ǒ

Ǔ

(15 * 0) mA
15 kHz

L LOADf PWM

10(eq. 30)

The NCV7544, NCV7546, and NCV7547 N−MOSFET
pre−drivers provide selectable charge and discharge
currents that are used together with a MOSFETs’ gate chargeparameters7 to construct controlled switching slopes. The
drive strategy can help minimize EMI and provides a means
for faster overload response via dynamic overload
detection8. The high−side drivers provide the selected drive
currents in a phased sequence of pre−charge, slew, andoverdrive intervals, while the low−side drivers provide drive
current within a single interval.
The pre−charge interval is constructed using a fixed timer
and a range of pre−charge currents to match a target
MOSFET’s gate−source charge QGS. The slew interval is
the time during which the high−side MOSFET’sgate−source voltage V(GHx, HBx) transitions through a‘plateau’ region, where it’s gate and source are moving at thesame rate. The desired slew time for both the rising andfalling HBx switching is constructed using a range of slew
currents and the MOSFET’s gate−drain charge QGD. The
overdrive interval is constructed (or rather defined) by thesame current as in the slew interval and the MOSFET’s total
gate charge QG(TOT) at VGS = 10 V, minus the sum of the
QGS and QGD charges.
A dynamic VDS overload detection delay time is usedmatch the slew time to a range of selectable delay times sothat the detection window opens at the expected point on thehigh−side or low−side MOSFET’s turn−on slope. In the caseof the high−side, the delay time is started at the end of thepre−charge time. In the case of the low−side, the delay timeis started concurrent with the drive current. The switchingnode voltage is compared with the appropriate overload
detection threshold at the end of the delay time.
Ideally, the time needed for the high−side MOSFET totransition through the slew interval is the same for both therising and falling slopes. However, while the samepre−charge time is applied to both slopes, the interval’s
charge and discharge currents are selected based on how
much gate charge must be added or removed to optimize theswitching slope, and can cause variation between the risingand the falling slew time which may lead to dynamic
overload ‘nuisance faults’. Due to the finite number ofpre−charge solutions, the resulting undershoot or overshootmay cause an abrupt initial step in the turn−on or turn−offslope (pre−charge overshoot) or a shoot−through hazard
between the high−side and low−side MOSFETs (pre−charge
undershoot).

(eq. 29)

100% w 19.6%

v R LOAD v

Summary

Using the recommended fPWM(MAX) = 25 kHz value in the
products’ datasheets and substituting the values computedfor tDGL1 and respectively tON(MIN_HS) and tON(MIN_LS)
into equation 28 and equation 29 gives
D w 25 kHz

f PWM

20

(eq. 28)t ON(MIN_LS))

D v 1 * (f PWM(MAX)

L LOADeq. 21This QG(TOT_SS) result is allocated, according to therespective MOSFETs’ gate charge requirements, among thenumber of channels in the application expected toconcurrently operate in PWM mode.
Test Bench LoadAs a final note, to properly model and observe the slope
behavior of the high−side MOSFET – in particular thefalling slope – on a test bench, an inductive test load needs
to be used so that a ‘continuous’ load current (i.e. stable
operating point) is provided. The load tau should to be on the

7. The MOSFET’s gate charge parameters vary as a function of its temperature, drain current ID, and drain voltage VDS.
8. Dynamic overload detection available only with the NCV7544 and NCV7546 products.

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AND90124/D
The products support concurrent PWM operation ofmultiple channels within a specific product’s charge pumpcapability, and within the frequency and duty ratio
limitations imposed by the various timing interval solutions
as constructed for a particular target MOSFET.

A symmetrical adaptive de−glitch timer embedded in each
PWM input’s signal path provides the benefits of reduced
actuator random torque jitter and assured proper operationof the dynamic VDS overload protection function.

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