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AND9813/D
Electric Vehicle OBC
System Design and
Simulation Using Power
Moduleswww.onsemi.com

SUMMARY
The on−board charger (OBC) market is growing rapidly as thedemand for battery powered electric vehicles is increasing worldwide.
An OBC system is composed of AC−DC converter with power factor
correction (PFC) cascaded with a DC−DC converter to control power
delivery to the battery. Typically, a two−phase interleaved PFC iscoupled with an LLC DC−DC for the 3.3 kW charger.
ON Semiconductor has developed a series of power modules withexcellent electrical and thermal performance to enable high efficiency
chargers with high power density. In this Application Note, we
demonstrate detailed OBC design and analysis with the use of two
such power modules (FAM65CR51DZ1 PFC and FAM65HR51DS1
H−Bridge). Through detailed circuit simulation, we demonstrate theperformance of these modules in the on−board charger system.

APPLICATION NOTE(a) Bottom View

INTRODUCTION TO OBC
Figure 1 shows the common package used for both the
FAM65CR51DZ1 and FAM65HR51DS1 modules, and Figure 2
illustrates the block diagram of the typical OBC system. The PFC
block is composed of AC power grid (85−265 Vac) input, input filter,
bridge rectifier and boost converter. The DC/DC converter blockincludes two−phase H−bridge, LLC tank, isolation transformer, output
bridge rectifier, and output filter.

(b) Top View (Y−Form)PFC Block in General

The PFC block draws AC input current that is in phase with the AC
input voltage to maximize the power factor (PF) and minimize grid
harmonic distortion. In the ideal case, the power factor is maintained atunity without harmonic distortion. With typical control, the PFC stage
can hold 0.97 > PF > 1.0 for the OBC system.
AC Input
Bridge

FAM65CR51DZ1/2
L_boost_ph1(c) Top View (L−Form)

Figure 1. FAM65CR51DZ1 Module

D_boost_ph1

Q3

L_boost_ph2

Isolation
Lres Transfofrmer

D_boost_ph2

Q4

_

Q2

Gate−Q2PFC Control

Load

LLC Tank

85– 265Vac_rms

Gate−Q1

Lo

Q5

Q1

Vac

DC/DC Output
Bridge

FAM65HR51DS1/2

Q6

Circuit
Lmag

CDC_link
Cres

Gate−Q3, Q6

Np Ns

Gate−Q4, Q5
DC/DC (LLC)
Control

Figure 2. Typical OBC System Block Diagram© Semiconductor Components Industries, LLC, 2018

January, 2019 − Rev. 1

1

Publication Order Number:
AND9813/D

AND9813/D
The PFC circuit can be designed to operate in continuous
current mode (CCM) or critical current mode (CRM) basedon the inductor current waveform in the boost converter
circuit. In high power applications such as the OBC for EVs,
the CCM topology is commonly used to minimize thecurrent ripple and maximize the system efficiency. In the
CCM PFC, the switch (MOSFET) in the boost converter has
a fixed switching frequency with variable duty cycle(on−time), whereas the CRM PFC has variable switchingfrequency with fixed on−time. This characteristic of CRM
makes the design of the PFC components more complicated,
requiring a dedicated input EMI filter circuit due to the highcurrent ripple. Although the CRM PFC has an advantage in
reduced switching losses owing to its zero current switching,
this advantage is canceled by higher conduction losses thanthat of the CCM PFC. Since the CCM PFC has a fixedswitching frequency, power factor is higher than CRM PFC,
typically by 0.2% to 0.3% and this leads to higher PFC
efficiency. Figure 3 shows the phase matching between
input voltage and current in the lower grid where PF is 98%,
and an example waveform of the inductor current in the
boost converter operating in CCM PFC mode. By contrast,
Figure 4 shows the inductor current in CRM PFC.
Figure 5 represents the currents in the two phaseinterleaved boost converter and Figure 6 shows the effect ofinterleaving in the CCM PFC circuit. In a two phaseinterleaved boost converter, the two inductor currents areout of phase by 180° and the ripple in each inductor current
is cancelled partially at the summing node.

Figure 4. Boost Inductor Current in CRM PFC

In CCM PFC, duty cycle is continuously changing andmaximum ripple reduction occurs when the duty cycle (D)is 0.5 as seen in Figure 7. Equation 1 below represents thecurrent ripple reduction ratio, K(D), in a two−phaseinterleaved boost converter.

iL _Boost Ph B
iin
From
BridgeRectifier

LBoost_Ph-B
LBoost_Ph-A

iL _Boost Ph A

CBus

Ro
iout−PFC

Figure 5. Two−phase Current Interleaving Circuit

K(D) +

I interleaved
1 * 2·D+, D t 0.5
I L_boost
1*D
2·D * 1+
, D w 0.5
D

(eq. 1)

Where:
IL_boost: Amplitude of the phase current ripple
Iinterleaved: Amplitude of the phase current ripple

Also, interleaving can reduce the total boost inductorenergy consumption. In a single phase boost converter,
energy stored in the inductor is:

Figure 3. Phase Matching between Input
Voltage and Current in a CCM PFC

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AND9813/D
E L_boost +

1 2
Li
2

pre−charge circuit necessary to control in−rush current was
not considered in the simulation.

(eq. 2)

In a two phase interleaved boost converter, total inductorenergy isƪ ǒǓƫ

1
E L_interleaved + 2· ·L i
2
2

2

1
+ Li 2
4

Table 1. DESIGN SPECIFICATION OF PFC BLOCKAC Input Voltage

85 – 265 Vrms, 50 − 60 Hz

PFC Output Voltage

390 – 400 VDC

Rated Power

3.3 kW

Inductor Current Ripple<25% @ Rated Power

Output Voltage Ripple

2% of Output at 120 Hz

Switching Frequency

65 kHz(eq. 3)

Therefore, interleaving brings a reduction in the size of theinductor and consequently reduced current ripple in the
output capacitor.

AC Power and Bridge
RectifierPower Stage: Boost Converter

V o_sense

LBoost_2
LBoost_1

R1

Pre−Charging Diode

Cout

Rout

VAC

+
Vo

−
R2

Current
sense

Figure 6. Current Ripple Reduction in Two−phase
Interleaved Boost PFC Circuit

Rectified
AC Input
sense

PWM &
Gate Drive

Multiplier

Vo_error−+

Output Voltage
sense

Vref

PFC Controller

Figure 8. PFC Circuit Including Controller

Major Components in PFC BlockPFC Boost Inductor
The inductance of the boost inductor can be determined by
the amount of current ripple and the switching frequency as
below:
L boost +Figure 7. Ripple Reduction in PFC Boost Inductor
Current by Interleaving(Ripple is Minimized at D = 0.5)

ǒ

Ǔ

Ǹ2 ·v
v 2ac_min
ac_min
1
·
· 1*
· 1
V out
%ripple P out
f sw(eq. 4)

By putting the design specifications (Table 1) into theEquation (2) above,
L boost +PFC Block Design Specification
Table 1 gives the design specification of 3.3 kW PFC
circuit block and Figure 8 illustrates the PFC circuit block
diagram including AC power grid, input rectifier bridge, andcontrol circuit used in the PFC system simulation. TheǒǓǸ2 ·85v
rms
1 (85v rms) 2
1·
W· 1 *
·
3300
0.25
400 V
65·10 3 Hz

+ 130.3 HIn the simulation circuit, 150 H inductor with 20 m of
ESR was applied.

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AND9813/D
Output Capacitor
The value of the output capacitor is determined by the PFC
output voltage, the rated power of PFC and capacitor
hold−up time. Suppose the PFC output voltage should not
fall below 300 V during a single AC line cycle period (e.g.,
16.7 msec for 60 Hz), the hold−up time, thold = 16.7 msec and
Vout_min = 300 V. Assuming Vout = 400 V, the output
capacitor size can be determined as below [1]:
C out w

2·P out_max·t holdV 2out * V 2out_min

B+

P out_max+ Ǹ2 ·

Q1

Q2

AC 1

Q1 GG
(Q1 Gate)

Q1 S
Q2 GG

+ 1.575 mF(Q2 Gate)

Q2 S

Figure 9. FAM65CR51DZ1 PFC Module
Block Diagram

Input Rectifier DiodeThe bridge rectifier must be able to handle the AC input
current peak defined as:
·v ac_min·PF

D2

AC 2

In the simulation, a 2.0 mF capacitor with 10 nH ESL wasapplied.

i in_ac_max + Ǹ2 ·D1

In the module, ON Semiconductor 3rd generation Super
Junction (SJ) MOSFET die are used for the main boost
converter switches. Two different sizes of the die (51 m die
and 80 m) are available. Table 2 shows the electricalcharacteristics of the MOSFET die in FAM65CR51DZ1
module.
Since the PFC boost converter experiences hardswitching, the MOSFET parameters should be optimized tohave low switching loss along with low thermal impedance.
As seen from Table 2, the 3rd generation of 650 V SJMOSFETs have: 1) low Qg that enables the fast switching,2) small Coss resulting in low switching loss, and 3) low
thermal resistance compared to major competitor parts.

3300W+ 40.4 A
0.98·85v rms·0.98

  target PFC efficinecy
In the simulation, 1000 V − 80 A ON Semiconductor
UltraFast diode model RURG80100 was applied,considering the necessary voltage margin.
Boost Converter MOSFET and diodeFAM65CR51DZ1 modules were developed specially for
multi−phase interleaved boost converter operation,
composed of a pair of MOSFET die and series−connected
diodes to form a two−phase interleaved PFC circuit asshown in the Figure 9.

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AND9813/D
DC/DC (LLC) Converter in Generalbecause it is composed of resonant inductor, resonantcapacitor and magnetizing inductance of the isolationtransformer. The square waveform from the DC/DC
switching block (full bridge or half bridge) becomes an“almost−sinusoidal” signal through the LLC tank circuit,which is transferred to the isolation transformer. The
transformer isolates the primary switching block from thesecondary load side to prevent the propagation of
conductive EMI noise and protect against a short circuit on
the load side.

Figure 10 represents a DC/DC converter block in anelectric vehicle OBC. The PFC output voltage is fed into the
DC/DC converter input. This input waveform is not a pureDC signal, but includes 120 Hz AC ripple from the PFC
block. The DC/DC converter modulates the input waveformto generate a square pulse waveform. Typically, the DC/DC
converter has a half bridge or full bridge circuit with LLC
resonant topology to minimize the switching loss by zerovoltage switching (ZVS). The LLC tank circuit follows theDC switching block. The resonant tank circuit is named LLC

Table 2. ELECTRICAL CHARACTERISTICS OF MOSFET DIE IN FAM65CR51DZ1 MODULE
Typical ValueUnits

VDS (Q1–Q2)

SymbolDrain to Source Voltage

650

V

VDS (Q1–Q2)Gate to Source Voltage±20V

ID (Q1–Q2)

Drain Current Continuous (Tc = 25°C, VGS = 10 V)

33

A

Drain Current Continuous (Tc = 100°C, VGS = 10 V)

23

A

Drain to Source Breakdown Voltage

650

V

Coss

Output Capacitance (VDS = 400V, VGS = 0 V and fsw = 1 MHz)

100

pF

Qg

Total Gate Charge

126

nC

RDS(ON)ON−Resistance of the MOSFET die

51

m

R_JC

Junction to Case Thermal Resistance

0.66

°C/W

R_JS

Junction to Heatsink Thermal Resistance

1.2

°C/W

BVDSS (Q1–Q2)Parameter

TJ

Maximum Junction Temperature−55 to 150°C

TC

Maximum Case Temperature−40 to 125

°C

TSTG

Storage Temperature−40 to 125°C

Table 3. BOOST CONVERTER DIODE (ISL9R1560) CHARACTERISTICS
SymbolTypical Value

Units

VRRM

Peak Repetitive Reverse Voltage

Parameter

600

V

VRWM

Working Peak Reverse Voltage

600

V

VR

DC Blocking Voltage

600

V

IF(AV)

Average Rectified Forward Current Tc = 25°C

15

A

IFSM

Non−Repetitive Peak Surge Current (Half Wave 1 Phase 60 Hz)

45

A

IRR

Reverse Recovery Current (IF = 15 A, dIF/dt = 200 A/sec, VR = 390 V)

5.0

A

TJ

Maximum Junction Temperature−55 to 175°CTC

Maximum Case Temperature−40 to 125

°C

TSTG

Storage Temperature−40 to 125

°C

EAVL

Avalanche Energy (1A, 40 mH)

20

mJ

QRR

Reverse Recovery Charge (IF =15 A, dIF/dt = 800 A/sec, VR = 390 V)

390

nC

TRR

Reverse Recovery Time (IF =15 A, dIF/dt = 800 A/sec, VR = 390 V)

52

nsec

S

Softness Factor tb/ta (IF = 15 A, dIF/dt = 800 A/sec, VR = 390 V)

1.36

−

R_JC

Junction to Case Thermal Resistance

1.98

°C/W

R_JS

Junction to Heatsink Thermal Resistance

2.97

°C/W

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5AND9813/D
will not be discussed further. In this application note, LLC
full bridge converter circuit with average current mode
control is implemented to evaluate the performance of theFAM65HR51DS1full−bridge module, including switching
behavior, power loss, and efficiency.

In most cases, the turns−ratio of the transformer, Nsec/Npri
is higher than unity to operate across a wide range of output(battery) voltages. On the secondary side, the transformer
output signal is rectified by the bridge rectifier circuit andfinally becomes the DC power delivered to the HV battery.
Isolation
Transformer

+
From
PFC

LLC H − Bridge
Converter

OutputBridgeRectifier

LLC Resonant Tank Circuit Analysis
Figure 12 shows the simplified LLC resonant converter
circuit and equivalent secondary side signal processing
block diagram. The LLC resonant tank circuit is composedof resonant inductor, Lr, resonant capacitor, Cr and thetransformer magnetizing inductance, Lmag. As seen from
Figure 12(a), the input voltage of the LLC resonant circuit
is a squarewave alternating between the positive andnegative value of DC input voltage of the full−bridge
converter block. Assuming only the fundamental frequency
component of the input voltage is used to transfer energy
from the primary side to the secondary side of the isolationtransformer, the First Harmonic Approximation (FHA)
method can be applied to perform the analysis of an LLC
resonant circuit avoiding complex analytical method [4].
In Figure 12(b), the primary side is replaced by an AC
current source model. Since the average value of |iac(t)| isequal to the DC output current, Io, iac(t) can be represented
as in equation (5).

OutputFilterFigure 10. OBC DC/DC Converter Block Diagram

Figure 11 shows the full−bridge LLC converter circuitwith current mode control. Input voltage is supplied from the
PFC block between 390 V ~ 400 V. The output voltage isdetermined by the HV battery, typically 220 V~450 V. In the
DC/DC converter stage, the largest portion of power loss isgenerated in the MOSFET switches and reduction ofswitching loss of the MOSFET is a critical factor ina converter design. As the size of the die increases,
conduction loss decreases with lower RDS(ON) value, but at
the same time, increased switching loss reduces the benefit
of using large die. Using smaller die can bring reduced
switching loss but increases conduction loss, and may
produce higher junction temperature due to the higher
thermal impedance. For those reasons, applying larger
MOSFET die in the LLC topology is justified owing to thezero voltage switching (ZVS) during the turn−on switchingtransient. Currently, LLC converter topology is the mostviable choice to use the ZVS characteristics.
In a conventional full−bridge converter, the two diagonal
MOSFETs form a switching pair sharing the same gate drive
signal with duty cycle of 50%. The two pairs have 180°
phase difference. As an alternative, the phase−shifted fullbridge topology can be implemented without the LC
resonant tank circuit, enabling natural ZVS through thefree−wheeling of the body diode, and control is also simpler
than that of the LLC topology. However, in the OBC
application, system efficiency is critical and excessive
power loss from the body diode free−wheeling becomes a
hurdle to achieve the target efficiency. Therefore, thephase−shifted full bridge topology is in general not used for
OBC systems, but is mainly used in HV to LV DC/DC
converters where efficiency is not the highest priority.
In terms of control, either the peak current mode control
or average current mode control method may be used to set
the charging current in accordance with the HV battery
charging state. Here, the DC/DC converter control method

i ac(t) +·I 0sin(2f swt)
2(eq. 5)Using the FHA method, vac(t) can be approximated by thefundamental component of the squarewave VP(t) as theEquation (6).
V P(t) + V 0 : if sin(2f swt) w 0
V P(t) + * V 0 : if sin(2f swt) t 0(eq. 6)

Therefore,
4V 0
v ac(t) + V P_f0(t) +  sin(2f swt)
where
V P_f0(t) + Fundamental frequency conponent of V P(t)(eq. 7)

The ac equivalent resistance, rac, can be obtained using
iac(t) and vac(t).
r ac +v ac(t) 8 V 0
8· ·+ 2 R0i ac(t)  2 I 0(eq. 8)

Considering the transformer turns ratio n = Npri/Nsec, theactual AC equivalent load resistance seen from the primaryside is given by Equation 9.
r ac +

8·n 2
R
2 0

(eq. 9)Using this AC equivalent resistance, the AC equivalentcircuit for the entire LLC converter can be obtained as
illustrated in Figure 13.

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AND9813/D
Full-Bridge Converter

Lin

Lo

Output Bridge Rectifier

Current
sense

LLC Tank Circuit

VDC_in

Q3

Q1

Cin1

Cin2

Lr

Isolation
Transfofrmer
Np Ns

Co2

Co1

L_mag

Load

Cr

Q2

Q4

Q1 Q2

Slope Compensation

Q3 Q4

Current sense
R_sense1

Error
Amplifier-

PWM

Gate Drive

+ +

+

VRef

-

Vout_sense+

R_sense2

Figure 11. Full−Bridge LLC Converter Circuit with Current Mode Control

Lr
D1

D1

D3

Io

D3

Npri : Nsec

From Full-Bridge
ConverterCoRo

iac(t)Vo-

Vac(t)

Co

Ro

Vo

-

-

V_in

D2

+

+

+
Lmag

D4

D2

D4

Cr

(a)

(b)

Figure 12. (a) Simplified LLC Circuit and (b) Equivalent Model Replacing Primary Side with AC Current Source

Figure 13. AC Equivalent Circuit for
LLC Resonant Converter

Figure 14. Two Port Network Model of FHA
Resonant Circuit

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7AND9813/D
The quality factor, Q, of the resonant tank circuit in
Figure 13 is defined as given in Equation (10).
ǸL rńVrQ+

n 2·R 0+

Table 4 shows an example of the design parameters in an
LLC converter. These parameters are applied in our 3.3 kW
LLC converter demonstration hardware and thecorresponding simulation work.

r ac
n 2·R 0wheren+Table 4. DESIGN PARAMETERS FOR 3.3 kW LLC
FULL−BRIDGE CONVERTER

N pri

Component

Designation

Value

Converter DC Input Voltage

Vin_DC390−400 V

Converter DC Output Voltage

Vout_DC250−450 V

Switching Frequency

fsw

100−150kHz

Resonant Frequency

fres

100 kHzResonant Inductor

Lr

25 H

N sec

N 2pri8
r ac + 2 · 2 ·R 0
 N secV0
R0 +I0(eq. 10)

The resonant tank gain is the magnitude of the transfer
function of the AC equivalent circuit and defined as inEquation 11.

Resonant Capacitor

Cr

100 nFnV P_f0(t)V o_ac(t)sin(2f swt)4+
+  V 0·2 V · sin(2f t)
V in*res_f0(t)V in*res_f0(t)sw in2n·V 0+(eq. 11)
V in

Magnetizing InductanceLmag

125 H

Transformer Turns Ratio

n = Npri /
Nsec

0.8

Inductance Ratio

m = Lmag / Lr

5

Alternatively, the LLC resonant tank circuit can be
defined by its transfer function H(s) and input impedanceZin(s) using a two port network model as shown in Figure 14.

Normalized Frequency

f1 = fsw / fres1 – 1.55

M+

H(s) +In the LLC converter circuit designed according toTable 4, Q varies from 2.217 to 0.629 as the output load
varies. Figure 15 shows the LLC converter gain variation
with the change in the output load. As the output load getsheavier, the peak gain point shifts closer to to the resonant
point and the peak gain approaches unity. Figure 16
illustrates the LLC gain characteristics at the 3.3 kW load
point. In the figure, the power transfer operation is divided
into two regions: ZVS Region 1 and ZVS Region 2. During
the power transfer operation (I_Lr > I_Lmag), themagnetizing inductor is being charged and it does notparticipate in the resonance operation. In this power transfer
mode, the resonant frequency, fres is defined as:2
V ac(s)
1 n ·r ac ø sL mag+ n·
Z in(s)V in*res_f0(s)where(eq. 12)
V in*res_f0(s)1) sL r ) n 2r ac ø sL mag
sC r
In Equation 12, the term, n2 · rac is the effective resistive
Z in(s) +I res(s)+load reflected to the primary side of the transformer.
The term “Normalized Voltage Conversion Ratio” or“Voltage Gain” M(fsw) is defined as:2Ǹ2v ac(t)⎪rms V0
M(f sw) + n· ø H(j2F sw) ø+ n·+ n·
Ǹ2
V in*res_f0(t)⎪rms
 V in2n·V 0+V in(eq. 13)f res_0 +(eq. 14)After some comprehensive work using theEquations 10−14, the voltage gain can be described asa function of the quality factor Q, inductance ratio(m = Lr/Lmag) and normalized frequency, f1 as shown inEquation 15. [2] [4]M(Q, m, f 1) +f 21·(m * 1)

Ǹ(m·f21 * 1) ) f21·(f21 * 1)2·(m * 1)2·Q2(eq. 16)

ZVS is accomplished in both Region 1 and Region 2. In
Region 2, the switching frequency is lower than the resonant
frequency and the converter gain is higher than unity.
Therefore, the converter is operated in boost mode. In
Region 1, the LLC converter is working in buck mode. The
switching frequency is higher than the resonant frequency,
and the LLC gain is lower than the unity.

From Equation 13, the input−to−output DC/DC voltage
conversion ratio becomes:
V0
1+
M(f sw)2n
V in

12 ǸL r·Cr

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AND9813/D
negative) and returns back to the body diode of the MOSFET
in the other phase leg to achieve ZVS turn−on.
The gate drive signal is applied at some point in this period
as seen from Figure 18. One thing to observe is that as theswitching period Ts = 1/fsw ends before the resonant current
completes its own period, Tr =1/fres, the MOSFET has
a hard−switched turn−off and the secondary side rectifier
diodes experience hard commutation as seen in Figure 19.
By design optimization of the LLC tank circuit, turn−offtransient current of the MOSFET can be minimized,
resulting in near zero current switching condition (ZCS).

Figure 15. LLC Converter Gain Variation in
Accordance with the Load Shift

Figure 17. Typical Waveforms in LLC Full−Bridge
Converter (fsw = 125 kHz, fres = 100 kHz)
Figure 16. LLC Converter Gain Variation in
Accordance with the Load Shift

The two ZVS operating regions are explained in detailbelow.
ZVS Region 1
Figure 17 shows the typical waveforms in the LLC
converter operating in the ZVS Region 1. In this region, theswitching frequency fsw is set higher than the resonant
frequency, fres, and power is transferred from the primaryside to the secondary side of the transformer until the end ofeach switching period. The magnetizing inductor current,
I_Lmag is a part of the resonant inductor current, I_Lr andjust charges the magnetizing inductor, Lmag. Therefore,
Lmag is not involved in the resonant operation. The primaryside transformer current, I_TXR_Pri = I_Lr – I_Lmag isdelivered to the secondary side. At the end of power delivery
operation, I_Lr changes its direction (di/dt becomes

Figure 18. ZVS Operation: Gate Drive Signal isEngaged during the Body Diode Conduction(VDS  0 V)

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9AND9813/D
ZVS Region 2
Figure 20 shows the LLC converter waveforms in ZVS
region 2. In this region, the switching frequency fsw is lower
than the resonant frequency and each switching period
includes the freewheeling period Tfw and, in this region,
I_Lmag ≈ I_Lr. In this period, resonant operation includes
discharging of the magnetizing inductance and the resonantcurrent returns back to the converter since the MOSFET
channel is still open. During the freewheeling operation, thepower in the primary side of the transformer is nottransferred to the secondary side and generates additional
conduction loss in the MOSFET. In this period, a second
resonant frequency, fres_1 is defined as given in Equation 17.
f res_1 +12 Ǹ(L r ) L mag)·Cr

MOSFET Module for the LLC Converter
Figure 21 shows the circuit diagram and pin−out
configration of ON Semiconductor’s FAM65HR51DS1
H−bridge module. The module was specifically designed fora full−bridge LLC DC/DC on−board charger (OBC). Eachhalf−bridge is composed of two series connected MOSFET
die (totem pole). The MOSFET die in the FAM65HR51DS1
module are identical with the ones used in the
FAM65CR51DZ1 module and, likewise, two different sizesof die (51 m and 82 m) are available. The module has ahigh voltage snubber capacitor across the DC link for noise
suppression and is qualified per AECQ101 and conforms to
AQG324 guidelines. In the LLC converter application,
MOSFET turn−off switching loss is dominant compared tothe conduction loss. The simulation results for the 3.3 kW
OBC system show that the 82 m (smaller) die gives a bit
higher efficiency than 51 m die due to the smallerswitching loss. But, certainly the 51 m die has better
thermal performance due to the lower thermal resistance.
Tables 5 and 6 represent the electrical specifications andelectrical characteristics of the 51 m MOSFET die appliedin FAM65HR51DS1 module.

(eq. 17)B+
Q1 GG(Q1 Gate)

Q1 SS

Csnub

Q1

Q3

Q1_G*

(Q1 sense)

Q3 GG
Q3 SS
AC 1
AC 2

Q2

Q4

Q2 GG
Q2 SS
Q4 GG
Q4 SS
B−

Figure 19. Secondary side rectifier diode hardcommutation during the MOSFET turn−off transient

(a)

(b)
Figure 21. FAM65HR51DS1 H−bridge Module (a)Circuit Diagram and (b) Pin−out Definition
Figure 20. Secondary Side Rectifier Diode Hard
Commutation During the MOSFET Turn−off Transient

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10AND9813/D
OBC SIMULATION USING FAM65CR51DZ1 AND FAM65HR51DS1 PSPICE SIMULATION MODEL
combined into the PFC simulation block. The LLC
full−bridge converter, isolation transformer, secondary side
bridge rectifier and output filter circuit forms the separate
DC/DC converter simulation block. The OBC systemefficiency is obtained by multiplying the efficiency of the
PFC block by the DC/DC converter block efficiency.
Through the simulation, the junction temperature, TJ, wasassumed 90°C in the normal case and 110°C in the worst
case simulation.
Finally, the performance of FAM65CR51DZ1 andFAM65HR51DS1 modules were compared to those of
discrete MOSFETs by applying them in the same circuit
used in the module simulation. The simulation results revealthat the OBC with FAM65CR51DZ1 and FAM65HR51DS1
modules has higher system efficiency than the OBC withdiscrete MOSFET devices due to lower switching loss of themodule.

The 3.3 kW on−board charger described has been
simulated to project the performance of theFAM65CR51DZ1 PFC module and the FAM65HR51DS1
H−bridge module at several operating points, including theworst case (Pout = 3.52 kW, Vout = 220 V, Iout = 16 A,
Tcase = 110°C). The two−phase interleaved boost PFC
topology and LLC full−bridge converter topology wereapplied in this system simulation as well as in bench test
experiments. SIMETRIX v8.1 was used as the simulation
platform. Ansys Q3D−based pSpice parasitic packagemodel and the MOSFET die model were used to simulate
both FAM65CR51DZ1 and FAM65HR51DS1 modules.
The power loss of the two modules and the major
components in the OBC system were estimated throughsimulation and system efficiency was calculated based onthese component power losses. AC input power source,
bridge rectifier circuit, and the boost PFC circuit wereTable 5. ELECTRICAL SPECIFICATION FOR THE 51 mW SJ MOSFET DIE IN FAM65HR51DS1 MODULE
SymbolParameter

Conditions

Min

Typ

Max

Unit

BVDSS

Drain−to−Source Breakdown Voltage

ID = 1 mA, VGS = 0 V

650

−

−

V

VGS(th)Gate to Source Threshold Voltage

VGS = VDS, ID = 3.3 mA

3.0

−

5.0

V

RDS(ON)

Q1 – Q4 MOSFET On Resistance

VGS = 10V,ID = 20A

−

44

51

m

RDS(ON)

Q1 – Q4 MOSFET On Resistance

VGS = 10 V, ID = 20 A, TJ = 150°C

−

79

−

m

gFS

Forward Transconductance

VDS = 20 V, ID = 20 A

−

30

−

s

IGSS

Gate−to−Source Leakage Current

VGS = ±20 V, VDS = 0 V

−100

−

+100

nA

IDSS

Drain−to−Source Leakage Current

VDS = 650 V, VGS = 0 V

−

−

10

A

Table 6. ELECTRICAL CHARACTERISTICS FOR THE SF3 51mW MOSFET DIE IN FAM65HR51DS1 MODULE
SymbolParameters

Conditions

Min

Typ.

Max

Unit

Ciss

Input Capacitance

−

4864

−

pF

Coss

Output Capacitance

VDS = 400 V
VGS = 0 V
f = 1 MHz

−

109

−

pF

Crss

Reverse Transfer CapacitanceCoss(eff)

Effective Output Capacitance

−

16

−

pF

VDS = 0 to 520 V
VGS = 0 V

−

652

−

pF

Rg

Gate Resistancef = 1 MHz

−

2

−



Qg(tot)Total Gate Charge

−

123

−

nC

Qgs

Gate to Source Gate Charge

VDS = 380 V
ID = 20 A
VGS = 0 to 10 V

−

37.5

−

nC

Qgd

Gate to Drain “Miller” Charge

−

49

−

nC

Note, this page is held separate so that the remainder of theformatting will remain the same. If these two tables don’t

make up most of a page, more formatting will need to be
done.

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11

AND9813/D
Simulation Software

Simetrix v.8.1 software was used to estimate the power
loss of the major components in 3.3 kW OBC system and theresulting OBC system efficiency. Simetrix is a non−linear
mixed−signal circuit simulator. The software is based on the
SPice programing language developed by the CAD/IC
group of UC Berkeley and the XSPice from CS & IT
Laboratory at the Georgia Institute of Technology.
The software features: 1) fully integrated hierarchicalschematic editor, simulator graphical post−processor, 2) fast
convergence for both DC transient analysis, 3) support for
BSIM3 & BSIM4, 4) Monte Carlo analysis including
tolerance specification, 5) easy SPice model importing 6)
various measurement probe functions including voltage,current and device power. Simetrix includes the Simplis
simulator, which achieves much faster simulation speed
than Simetrix in a switching circuit simulation. Simplis
characterizes the complete system as a cyclical sequence of
linear circuit topologies to accomplish this. Simplis gives
fast and reliable results in a linear steady state analysis or AC
analysis. However, given that the non−linear behavior of theswitching MOSFET and diode is the critical factor to beanalyzed, Simetrix is the right tool for the transient analysisof the power converter circuit. Even though Simetrix is usedas the main tool for the OBC system simulation, the model
importing process for Cadence PSpice is also described inthesection
Package
Simulation
Model
for
FAM65CR51DZ1 and FAM65HR51DS1 Modules since
PSpice is a popular alternative to Simetrix. Cadence PSpiceis frequently used for the device level simulation and
Simetrix is favored in a system level circuit simulation. The
Ansys Q3D−based parasitic package model can be imported
into either PSpice or Simetrix without any modification inaccordance with a user’s preferred simulation platform.

Figure 22. An example of Q3D image to extract theparasitic R, L and C components

(b)

(a)

(c)

Figure 23. (a) Q3D−extracted FAM65CR51DZ1 andFAM65HR51DS1 Parasitic Package Model,(b) 3−pin Electrical Spice Simulation Model, and5−pin Electro−thermal Spice Simulation Model

The FAM65CR51DZ1 and FAM65HR51DS1 module
package model netlists are written in SPice programing
language. The source files are compiled by the various
simulation software tools and they create their own
representation of the package models. The source file of the
package simulation model has either “.LIB” or “.TXT” typeof file extension. Cadence PSpice uses typically “.LIB” fileextension whereas Ansys Simplorer and Simetrix uses bothtypes of the file extension. Next, Cadence PSpice andSimetrix step−by−step instructions are given to explain how
to create the simulation model from the original source fileof the Q3D package model.

Package Simulation Model for FAM65CR51DZ1 andFAM65HR51DS1 Modules

Figure 22 shows an example of 3D image of the physicalconnections between the device in a module (source) andouter pins (sink). Ansys Q3D analyzes the module structure
in 3D space and extracts the R, L and C parasitic components
between all the sink and source nodes. Table 7 shows anexample of Q3D−based parasitic R and L values computedfor the module. Once a source file (netlist) is created basedon the Q3D analysis result, the circuit simulation tool
imports the sorce file and generates the package simulation
model as shown in Figure 23(a).

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AND9813/D
Table 7. FAM65HR51DS1 CAA PARASITIC R, L C VALUES EXTRACTED FROM ANSYS Q3D ANALYSIS(VALUES ARE EMBEDDED IN THE Q3D PACKAGE SIMULATION MODEL)
Sink

SourceDC ResistanceAC Inductance @20 KHz

Capacitance, pF

AC1

SRC_Q1S

1.161612.92280.734

SRC_Q2D

0.62705

14.579SRC_Q3S

1.191213.133

SRC_Q4D

0.62058

14.921

SRC_Cap2

0.56135

10.968SRC_Q2S

1.024614.257AC2

BM80.01367.536

SRC_Q4S

1.0501

15

SRC_Cap1

0.418028.0862

SRC_Q1D

0.410167.2403

SRC_Q3D

0.67266

13.103

Q1_Gate

SRC_Q1G

3.17848.70282.3192

Q1_Sense

SRC_Q1SS

3.61188.792

2.4423

BP

94.311Q2_Gate

SRC_Q2G

13.65123.4664.7489Q2_Sense

SRC_Q2SS

11.72219.8895.4937

Q3_Gate

SRC_Q3G

4.6801

9.40252.5984

Q3_Sense

SRC_Q3SS

4.2057102.5047

Q4_Gate

SRC_Q4G

10.81122.332

6.0436

Q4_Sense

SRC_Q4SS

10.55818.6395.3266www.onsemi.com
13

AND9813/D
Cadence PSpice
1. Open the Model Editor in the directory as[Cadence 17.x/Product Utilities/PSpice
Utilities/Model Editor]
2. In Model Editor utility screen in Figure 24, open
the “.LIB” simulation file by clicking “File”→“Open”
3. In the Model List window, click each sub circuit
file name; the file opens in the main window
4. Click File menu → Click Export to Part Library:
sub window for part creation pops up → click“OK” in the sub window; file compilation starts
and completes
5. Repeat the process 3) and 4) until all the sub
circuit files are compiled
6. The PSpice simulation model for
FAM65CR51DZ1 and FAM65HR51DS1 package
will be created in the Capture part library as shown
Figure 23(a). The symbol file having fileextension, “.OLB” will be created in the same
directory where the original “.LIB” file exists
7. Include the created “.OLB” file in the PSpicelibrary window using “Add Library” function in
PSpice main simulation window as Figure 25
8. If “.OLB” is already available along with original“.LIB” file, it means that the original “.LIB” file
was already compiled successfully. You can skip
the above process and directly go to the process 7)

Figure 25. pSpice Main Simulation Window and
Library Window

SIMETRIX
1. Simetrix software uses either “.LIB” type or“.TXT” type of model file
2. Open the main Simetrix and drag and drop themodel file into the commend shell window in
Figure 26 and then the sub−window appears
asking to install the simulation model
3. Click “OK” in the sub−window, then thesimulation model symbol is generated as seen in
Figure 23(a)4. You can find the package simulation model in “Alluser Models” window from the “Place menu”(Place → From Model Library → All user
Models)Figure 24. Model Editor Window is Divided into
Model List sub−window and Main Program Window
Figure 26. Main Screen of Simetrix Simulationwww.onsemi.com
14

AND9813/D
Figure 27 shows the FAM65HR51DS1 H−Bridge module
schematic diagram and corresponding PSpice package
simulation model extracted from Ansys Q3D. The Spicepackage model includes all the parasitic R, L, and C
components between the sink nodes (actual module pin−out)and the source nodes (internal circuit components). Since
the package model does not include the MOSFET dies, thedie−only model for individual MOSFET should beconnected externally as shown in Figure 30 and Figure 31.
Therefore, a die−only model is required along with apackage model in order to run the simulation. Two types of
die−only model can be chosen based on the purpose of asimulation. For an electrical performance evaluation, athree−pin electrical model is used and for an electro−thermal
simulation, the five pin electro−thermal model is used. Two
different types of thermal simulations are possible. The first
type is to estimate the junction temperature when the casetemperature is set to a fixed point as shown in Figure 28. In
this case, “Tcase” port becomes the temperature input sourceand “TJ” port works as output port connected to a highresistance (1 M) load, whose voltage potential represents
junction temperature.
The second type of thermal simulation is to fix thejunction temperature at a certain point and measure theperformance of the MOSFETs including power loss andRDS(on)(TJ). In this case, a constant temperature source isconnected to the TJ port and the Tcase port is shorted to the
TJ port as shown in Figure 29.
B+
Q1 GG

(Q1 Gate)

Q1 SS

Q1_D*

Q1
Q1_G*

Q2 GG
Q2 SS
Q4 GG

(a)

Q3_S*

Q2_D*

Q2

Figure 28. Connection of Electro−thermal Die−onlyModel to Measure (a) MOSFET and (b) DIODE
Loss−dependent Junction Temperature, TJ

Q3_D*

Q3 GG
Q3 SS
AC 1
AC 2

(b)

Q3

Q1_S*

(Q1 sense)

(a)

Q4_D*

Q4
Q4_G*

Q2_G*
Q2_S*

(b)

Q4_S*

Q4 SS
B−

(a)

(b)

Figure 27. FAM65HR51DS1 H−Bridge(a) Schematic and (b) pSpice Package Model Pin−out

Figure 29. Connection of Electro−thermal Die−onlyModel to Measure the Performance of (a) MOSFET
and (b) DIODE at Fixed TJ Conditionwww.onsemi.com
15

AND9813/D
OBC System Simulationa frequency sweep, depending on the application
environment. Generally, the gate loop and power switching
loop oscillations occur in the frequency range of 1to20 MHz. Hence, a 1 MHz excitation signal is used to extract
the parasitic inductance and capacitance values.
The analysis setup is very important in the electricalcircuit simulation because the convergence, accuracy, andsimulation speed are determined by this setup. In Simetrix,
there are three critical parameters to specify: max/min time
step, integration method and convergence option.

Figure 30 shows the simulation circuit for LLC
full−bridge converter using the Q3D−extracted Spicepackage model of FAM65HR51DS1 full−bridge module.
The gate, drain and source connection points for each
MOSFET are provided using the twelve outer pins of the
package model and the four “die−only” MOSFET models
are connected externally to represent the total
FAM65HR51DS1 module. The values of parasitic R, L, andC components can be determined from Q3D analyses using

Table 8. SIMULATION CONDITIONS FOR PFC AND DC/DC (LLC) CONVERTER BLOCK
System Block

Vin_rms

Tj

Fsw

Vout

Iout

Pout

PFC

220 V

90°C

65 kHz400 VDC

3.5 A

1.4 kW

110 V

90°C

4.5 A

1.8 kW

220 V

90°C

6A

2.4 kW

220 V

90°C

8.25 A

3.3 kW

220 V

110°C

8.8 A

3.52 kW

400 VDC

90°C

DC/DC Converter

110°C

139 kHz

400 VDC

3.5 A

1.4 kW

154 kHz360 VDC5A

1.8 kW

144 kHz360 VDC

6.7 A

2.4 kW

141 kHz

400 VDC

8.25 A

3.3 kW

151 kHz

220 VDC

16 A

3.52 kWPFC Inductor

L = 150 H, ESR = 20 m

Resonant L, C

L_resonant = 25 H (ESR = 10 m) C_resonant = 100 nF

Transformer

L_Pri = 125 H, ESR_Pri = 20 m, ESR_sec = 30 m

3. Under the [Simulator] menu in the menu bar
window, the user can choose various convergence
options by clicking the [Convergence Options]sub−menu. For instance, when the message “Noconvergence in transient analysis” pops up, theuser can change the iteration mode from thedefault [Normal Mode] to [Extended Precision]
first, then [Advanced Iteration] or [Extended/quad
precision]. These options improve the convergenceat the expense of simulation speed without losing
simulation accuracy. Also, there are additional
convergence improvement options including[Absolute current tolerance] and [Circuitmodifiers] options. [Convergence Options] menu
window includes the explanation on the setting of
those options

1. Max/min time step defines the time resolution for
the transient analysis. Users can adjust the time
resolution directly using manual input orconveniently using the default setup. Since thedefault setup proceeds with the adaptive
convergence method, it is convenient to use thedefault setup in normal transient analysis. In caseof device characterization simulation, user should
set up the time resolution based on referencematerial such as the datasheet of the device
2. In a transient analysis, the user can choose
between trapezoidal integration method and gear
integration method. In case of simulating aresonant circuit such as LLC converter, gear
integration introduces a numerical damping effectthat causes the resonant circuit to decay more
rapidly than it should and for this reason,
trapezoidal integration method should be selected
for the transient analysis of the power converter
circuits

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AND9813/D
OBC System Simulation Condition
The simulations were carried out for the PFC block and
DC/DC (LLC) converter block separately. In the simulation,
the power losses of the components were measured in thesteady state condition excluding the startup transient period.
The efficiency of each function block was measured first andthe total OBC system efficiency was obtained at each power
level by multiplying the PFC block efficiency by the DC/DC
converter efficiency. Because of the complexity of thesimulation circuit of the PFC and DC/DC blocks,
convergence problems could be encountered if both stages
were simulated togeter. Table 8 represents the simulation
condition for PFC and LLC converter circuits at each of thefive operating points. Figures 30 and 31 illustrate
respectively the simulation block diagram of the PFC and
DC/DC with the parasitic package model and the die−only
MOSFET models.

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AND9813/D
OBCシステムのシミュレーションFigure 30. PFC Circuit Simulation Block Diagram using FAM65CR51DZ1 PFC Module and 5−pin Electro−thermal
Die−only MOSFET Model: TJ was set to 90°C using External Temperature Source

Figure 31. LLC Converter Circuit Simulation Block Diagram using FAM65HR51DS1 H−bridge Module and 3−pinElectrical Die−only MOSFET Model: Tj was set to 90°C in the Simulation Setup Option

In the simulation, the performance of theFAM65CR51DZ1 and FAM65HR51DS1 modules wascompared to that of discrete MOSFETs by comparing theindividual power loss and the system efficiency. Figures 32
to 34 illustrate respectively the efficiency of the PFC,
DC/DC, and the entire OBC system at each operating point.

System Simulation Results
Table 9 shows the OBC system simulation results. Systemefficiency was calculated based on Equation 18.
E OBC + E PFC

E DCńDC +P out_PFC

P out_DCńDC

P in_PFC

P in_DCńDC

100%(eq. 18)

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18

AND9813/D
Figure 34 implies that the OBC with module solution gives
95% or higher efficiency except at the worst case conditions.
Comparing to the actual bench evaluation test result in
Figure 35, the efficiency obtained from the simulation isvery close to the bench evaluation data with the difference
within ±0.2%. This validates the simulation data to beconsistent and reliable.
Figures 36 and 37 show the power loss distribution in the
PFC and DC/DC. The results reveal that the OBC with
FAM65CR51DZ1 PFC module and FAM65HR51DS1
H−bridge module has clearly higher efficiency compared to
the OBC with discrete SJ MOSFET devices due to the lower
switching loss of the two modules. This lower switching loss
is enabled by the lower parasitic inductance and resistanceof the modules. Figure 36 indicates that the power loss of the
AC input bridge dominates over all other components in the
PFC block. Figure 32 shows that the efficiency of the PFC
block is higher than 97.5% through the main operating range
with 220 Vac input. Therefore, OBC system efficiency ismainly determined by the efficiency the DC/DC stage.
Figure 37 indicates that the power loss from the four
MOSFETs in the full−bridge converter is the critical factor
to determine the efficiency of the DC/DC. In the DC/DC
stage, the power loss of the four MOSFETs accounts for 57%
of the total power consumption. Also, Figures 36 and 37
suggest the designer should focus on reduction of power loss
from the AC input bridge and MOSFET switching loss from
DC/DC converter to increase the OBC efficiency.
Implementation of the bridgeless PFC including a totem
pole topology would be the most effective way to minimize
the power loss from the AC input rectifier. In the DC/DC
converter block, all the operating points are above theresonate point and consequently the majority of the
MOSFET switching loss occurs during the turn−offtransient, because turn−on loss is very low due to the ZVS
operation. Ideally, ZCS can be achieved for the turn−offtransient when the operating point is exactly on the resonant
point. In this case, MOSFET turn−on loss would be
minimized. As long as the operating point of the LLC
converter is located above the resonant point, thehard−switched turn−off is inevitable and the design
optimization of the converter block, including thetransformer and the LLC resonant circuit, is necessary to
reduce the turn−off switching loss.

Figure 32. PFC Block Efficiency at each Operating
Points: at 1.8 kW Power, Vac_in = 110 vrms (Worst
Case) and Vac_in = 220 vrms at all other Points

Figure 33. DC/DC (LLC) Converter Block Block
Efficiency: at 3.52 kW, Vout = 220 V Iout = 16 A
(Worst Case)

Figure 34. OBC System Efficiency with WCS at
1.8 kW and 3.52 kW

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AND9813/D

Figure 35. OBC Efficiency Measured from Bench Test using FAM65CR51DZ1 PFC Module and FAM65HRDS1
H−bridge Module

Table 9. EFFICIENCY SIMULATION RESULTS FOR 3.3 kW OBC SYSTEMOBC Power

1.4 kW

1.8 kW

2.4 kW

3.3 kW

3.52 kW(Worst Cace in DC/DC)

Switching Device

Efficiency [%]
PFC

DC/DC

OBC Total

FAM65CR51DZ1 andFAM65HR51DS1−51 m Die

98

96.7

94.8

NTHL040N65 (TO247)

97.8

96.2

94.1

NTHL082N65 (TO247)

98

96.5

94.6

FAM65CR51DZ1 andFAM65HR51DS1−51 m Die

96

96.4

92.5

NTHL040N65 (TO247)

95.3

95.1

90.6

NTHL082N65 (TO247)

95.6

95.8

91.6

FAM65CR51DZ1 andFAM65HR51DS1−51 m Die

97.8

97

94.9

NTHL040N65 (TO247)

97.6

96.3

94

NTHL082N65 (TO247)

97.9

96.6

94.6

FAM65CR51DZ1 andFAM65HR51DS1−51 m Die

98

97.3

95.4

NTHL040N65 (TO247)

97.8

96.6

94.5

NTHL082N65 (TO247)

97.9

96.6

94.6

FAM65CR51DZ1 andFAM65HR51DS1−51 m Die

98

93.8

91.9

NTHL040N65 (TO247)

97.8

90.3

88.3

NTHL082N65 (TO247)

98

91.6

89.8

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AND9813/D

Figure 36. Power Loss Distribution
in PFC Function Block

Figure 37. Power Loss Distribution in DC/DC
Converter Function Block

References[4] S. De Simone, C. Adragna, C. Spini, G. Gattavari,“Design−oriented steady−state analysis of LLC
resonant converters based on FHA”, PowerElectronics, Electrical Drives, Automation Motion,
2006[5] SPEEDAM 2006. International Symposium, May,
23rd − 26th, 2006 Page(s): 200 – 207[1] “Power Factor Correction Converter Design with
FAN6982”, ON Semiconductor Application Note,
AN−6982 Rev. 1.0.1, November 26th 2014[2] S. De Simone, C. Adragna, C. Spini, “Design
guideline for magnetic integration in LLC resonant
converters”, Power Electronics, Electrical Drives,
Automation Motion, 2008. SPEEDAM 2008.
International Symposium, May, 11th – 13th, 2008,
pp. 950 – 957[3] Hangseok Choi, “Half−Bridge LLC Resonant
Converter Design Using FSFR−Series Fairchild
Power Switch”. ON Semiconductor Application
Note, AN−4151, Rev. 1.0.2October 10th, 2014

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