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onsemi andand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
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Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.

DATA SHEET
www.onsemi.com

eFuse, 4 Channel,
60 V, 2.5 A
WQFN16, 6x5
CASE 510CM

MARKING DIAGRAMSXXXX = Specific Device CodeA
= Assembly Location
WL = Wafer Lot
YY= YearWW = Work Week

Features• 4 Independent Channels with 2.5 A Current Capability Each
• Power Device Thermally Protected for Each Channel• No External Current Shunt Required• Active−High Digital Enable Pin• Open−Drain Common Fault Pin• Adjustable Overcurrent Limit for All Channels• Adjustable Turn−on Time Control• NIV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable• These Devices are Pb−Free and are RoHS Compliant

VOUT1

VOUT3

VIN1

VIN3

GND

VOUT4

GND

VOUT2

ILIM

VIN4

dvdt

VIN2

FAULT

• Automotive Body Control Modules• Power Distribution Box• Automotive Zonal Controllers• Load/Harness Protection• Automotive Low−Medium Power Loads• General Purpose High−Side Load Switch• Power Amplifier Protection• Motor Drive Protection• Telecomm Equipment• 8 V to 60 V Industrial

June, 2024 − Rev. 2

EN3

EN1

PIN CONNECTIONS

Typical Applications© Semiconductor Components Industries, LLC, 2021

XXXXXXXXXXXXAWLYWW

XXXXXXXXXXXXXXXXAWLYYWWEN2The NIS/NIV3071 is a 4−channel, 60 V, 2.5 A per channel eFuse
which protects downstream loads from output shorts, overloads andovercurrent events. Each channel is in a high−side configuration, andis independently controlled by its corresponding enable pins. The
NIS/NIV3071 communicates status via a common active−low fault
pin. This eFuse features an internal soft start delay, trip time control,
and an adjustable current limit setting common to all channels. The
NIS3071 is well suited for industrial and telecom applications while
the NIV3071 is for automotive applications.

WQFNW16, 6x5
CASE 512AN

EN4NIS3071, NIV3071

ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.

1

Publication Order Number:
NIS3071/D

NIS3071, NIV3071
Table 1. PIN FUNCTION DESCRIPTION
Pin

Function

Description

1

OUT1

Output voltage for channel 1

2

IN1

Input voltage for channel 1

3

IN2

Input voltage for channel 2

4

OUT2

Output voltage for channel 2

5

FAULT

Active Low Open−Drain FAULT pin (Pull up to 5 V, 3.3 V or 1.8 V external logic supply with 15 kW
resistor)

6

dvdt

Turn−on Time/inrush current control (connect capacitor to ground to control output slew rate)

7

ILIM

Connect RLIM resistor to GND to set current limit for all channels

8

GND

Ground9

OUT4

Output voltage for channel 4

10

IN4

Input voltage for channel 4

11

IN3

Input voltage for channel 3

12

OUT3

Output voltage for channel 3

13

EN4

Channel 4 Enable, Active High, Internal Pull−up

14

EN3

Channel 3 Enable, Active High, Internal Pull−up

15

EN2

Channel 2 Enable, Active High, Internal Pull−up

16

EN1

Channel 1 Enable, Active High, Internal Pull−up

PAD

GND

GroundTable 2. ABSOLUTE MAXIMUM RATINGS AND THERMAL RATINGS
RatingSymbol

Value

Unit

IN1,2,3,4 Pins Input Voltage, operating, steady−state(VINx, VOUTx to GND, Note 1)

VIN(Max)−0.3 to 60

V

Absolute Maximum Transient voltage on IN1,2,3,4 pins (Note 2)

VIN(Tran)

65

V

Maximum DC voltage on EN pin

VEN(Max)−0.3 to 6

V

Thermal Resistance, Junction−to−Air
JEDEC JESD51−5
JEDEC JESD51−7
0.5 in2 copper (Note 3)

qJA

Thermal Resistance, Junction−to−Lead

qJL

0.5

°C/W

Operating Junction Temperature Range (Note 4)

TJ−40 to 150°C

Non−operating Junction Temperature Range

TJ−50 to 155°C

Lead Temperature, Soldering (10 sec)

TL

260

°C

ESD Human Body Model ANSI/ESDA/JEDEC JS−001 Class 2

ESDHBM

2.0

kV

ESD Charged Device Model AEC Standard Q100−01 (JESD22−C101E)

ESDCDM

1.0

kV

32.1
56.8
24.0

°C/W

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package.
2. Transient Voltage pulse duration ≤ 100 ms.
3. Based on thermal models using the NIS/NIV3071 EVB.
4. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than maximum
ratings for extended periods of time.

www.onsemi.com
2

NIS3071, NIV3071
Table 3. ELECTRICAL CHARACTERISTICS(Unless otherwise noted: VIN = 48 V, CIN = 100 mF, COUT = 100 mF, dV/dt pin open, RLIM = 20 kW, TA = 25°C)
SymbolCharacteristics

Min

Typ

Max

Unit

POWER FETON Resistance per channel, TJ = 25°C

RDS(ON)80

92

ON Resistance per channel, TJ = 150°C

RDS(ON)

135

155

Continuous Current per channel (TA = 100°C, single channel)

ID(Cont)

2.5*

A

Off State Leakage per channel (VIN = 48 V, VEN = 0 V)

IOFF

1.0

mA

Shutdown Temperature

TSD

175

°C

Thermal Hysteresis (Decrease in die temperature for turn on)

THyst

27

°C

Minimum Settable Current Limit (RLIM = 130 kW) MTW3, MTW4 versions

ITH(Min)

0.5

A

Minimum Settable Current Limit (RLIM = 300 kW) MTW5, MTW6 versions

ITH(Min)

0.2

A

Maximum Settable Current Limit (RLIM = 62 kW) MTW5, MTW6 versions

ITH(Max)

1.0

A

mW

THERMAL LATCHOVERCURRENT PROTECTION

Threshold Current Level (RLIM = 30 kW)

ITH

Circuit Breaker Current Level

ICB

1.9

2 x ITH

2.0

2.1

A
A

Circuit Breaker Response Time

tCB

6

ms

Overcurrent Trip Timer

tTRIP

1.5

Undervoltage Lockout Level Rising

VUVLO

5.0

Undervoltage Lockout Hysteresis

UVLOhyst

0.3

tUVLO

5.0

Output On Delay Time (CIN = 100 mF, COUT = none, VIN = 48 V) (Note 5)tDLY(On)350

ms

Turn−On Time (CIN = 100 mF, COUT = none, VIN = 48 V, Cdvdt = none) (Note 5)tRAMP(On)

1.5

ms

ms

UNDERVOLTAGE LOCKOUT

Undervoltage Lockout Response Time(Time from Vin reaching UVLO to enabling/disabling)

6.0

7.0

V
V

10

ms

TURN−ON TIME

LOGIC INPUT/OUTPUT
LOW Level Input; EN

VIL

HIGH Level Input; EN

VIH

LOW Level Output; FAULT, 0.5 mA

VOL

Output Sink Current; FAULT

0.4
1.2

V

IOL

EN Sink Ground Current; EN (VIN = 48, ENx = 0 V)

IEN(sink)

EN Pull−up Current (EN = 5 V)

IEN(pull−up)

V

0.3

V

0.5

mA

3

mA
1

mA

TOTAL DEVICE CURRENTOff State Bias Current (All channels Off)Ibias(Off)

85

175

mA

On State Bias Current (All channels On, No Load)

Ibias(On)

850

1200

mA

Ibias(On,Max)

5.0

On State Bias Current (All channels On, 2.5 A load per channel)

mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.
*Application is to have RqJA ≤ 14°C/W when driving 2.5 A on each channel.
5. 1 A load connected to output.

www.onsemi.com
3

NIS3071, NIV3071
Current Limit

IN1

OUT1
Charge Pump

ThermalShutdown

SoftStart

ThermalShutdown

SoftStart

Current Limit

IN2

OUT2
Charge Pump
Current Limit

IN3

OUT3
Charge Pump

ThermalShutdown

SoftStart

ThermalShutdown

SoftStart

Current Limit

IN4

OUT4
Charge Pump

ILIM
dvdt

FAULT
GND

EN1
EN2
EN3
EN4

Control

Figure 1. Block Diagram

Figure 2. Application Diagrams

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4

NIS3071, NIV3071
APPLICATIONS INFORMATION
Basic Operationa Figures 9, 10 and 11. It is recommended to use a ceramicor other low leakage capacitor.

The NIS/NIV3071 is an eFuse with four self−protectedchannels in a high−side configuration. It contains circuits tomonitor the output current and die temperature for eachchannel independently.
Once the input voltage is applied to any INx pin, thedevice will apply the input voltage to the load connected to
OUTx pin based on the restrictions of the controlling
circuits. It is also possible to operate this eFuse with
common inputs and common outputs, thus paralleling thechannels for higher total output current. When a channel is
not in use connect the INx and ENx pins to ground.
Each channel of the device will remain on as long as thetemperature of the channel FET does not exceed the 175°C
limit that is programmed into the chip.
The overcurrent protection circuit will allow for a load todraw the current for that channel within the allowable
overcurrent limit defined by ITH and ICB. If the load current
in one channel exceeds limits defined by ITH and ICB it willsubsequently turn off, while other channels can continue thenormal operation.
An internal charge pump provides bias for the gate voltageof the internal power FET structures and also for the current
limit circuit. The remainder of the control circuitry operates
between the input voltage at INx pins and ground.

Enable

The active high Enable pins provides a digital interface tocontrol the state of the channels. When ENx pin is pulled low
by external circuitry, the specific channel will be turned off.
When ENx pin is driven high or left floating, thecorresponding channel is enabled. In applications with highinductances on the output, it is recommended to pull the ENx
pins high. Protection circuits such as the overcurrent limit
function override the function of the enable pin. The EN pin
has an internal high impedance pull−up resistor.
Fault

The FAULT pin is an open−drain active low pin signaling
the system controller about an overcurrent event on any of
the channels. If a thermal shutdown or overcurrent trip timer
runout event occurs, the FAULT pin will be pulled low. Afterthe fault is cleared the pin will be floating or pulled up by an
external pull−up resistor. The pin can be left unconnected if
not used.
Table 4. FAULT PIN TRUTH TABLE
Condition

Overcurrent Protection

The Overcurrent protection circuit monitors the load
current and allows the load to draw current as long as its levelis within an allowable overcurrent range defined by ITH and
ICB. The ITH is the overcurrent limit set by the RLIM resistor,
and ICB is a circuit breaker level which is 2x of ITH; as longas the load is drawing current not exceeding the ICB level the
FET is on, if the current level exceeds the ICB level the FET
is turned off for that specific channel. If during theovercurrent mode the internal temperature for the channel
FET exceeds the threshold level, that specific channel will
be shut off. Additional device options offer a overcurrent
trip timer which starts counting right after the load current
exceeds the ITH level, once the predetermined amount oftime has elapsed the channel will be shut off. Examples ofa typical operation for such scheme is shown in Figure 4.
Figure 5 shows typical values of ITH with respect to the
RLIM resistor.

Fault Pin Status(With external pull up)

Thermal Shutdown

Low

ICB Overcurrent EventLow

ITH Overcurrent Event(t > tTrip)

Low

Normal Operation

High

Input < UVLO

High

Thermal Protection

The NIS/NIV3071 series device includes an independentinternal temperature sensing circuit for each channel thatsenses the temperature of the power FETs on the die. If the
FET temperature reaches 175°C for any of the channels, thedevice will shut down that specific channel while otherchannels will continue normal operation. The disabledchannel will be automatically turned on once the channel
FET temperature has been reduced by 27°C. (for auto−retry
version, latched version must be reset) The thermal limit has
been set high intentionally, to increase the trip time duringhigh power transient events. It is not recommended tooperate this device above 150°C in normal operating
conditions.

Turn−on Time Control

The Turn−on Time circuit brings the output voltage up
under a linear controlled rate in order to limit peak inrush
current. The default ramp time is approximately 1.5 ms. Thiscan be modified by adding an external capacitor at the dvdt
pin.
The diagram showing the typical turn−on time and enable
delay is shown in Figure 3. The value of capacitor connected
to dvdt pin defines the tRAMP(On) turn on times as shown inTransient Protection

In the event of a short circuit or overcurrent fault, thedevice will interrupt the flow of current by becoming an
open circuit. If there is inductance in the system, specificallywww.onsemi.com
5

NIS3071, NIV3071
on the input or output pins of the eFuse, the resulting
transients could exceed the datasheet maximum voltage
ratings. Input inductance will generate a positive voltage
spike on the INx pin(s) and output inductance will generatea negative voltage spike on the OUTx pin(s). Someapplications may require large inductances on the input or

output, in such a case a Transient Voltage Suppressor (TVS)
can placed between the input and ground pins and a Schottky
diode can be placed between the output and ground pins tomaintain the datasheet absolute maximum voltage ratings.
Additionally, capacitors can be used to help absorb
transients as well.

Figure 3. Turn On Delay and Turn−on Timewww.onsemi.com
6

NIS3071, NIV3071

t1: Current is above ITH (but below ICB); tTRIP counter is started.
t2: Current goes below ITH before tTRIP timer expires. tTRIP counter is reset and normal operation continues.
t3: Current is above ITH (but below ICB); tTRIP counter is started. Note that the load continues to draw current as long as it is below ICB and device remains
below the thermal shutdown temperature (TSD).
t4: Device begins shut down due to A) tTRIP timer has expired, OR B) device has reached the thermal shutdown temperature (TSD). FAULT pin is pulled low.
t5: Device shuts down in tTSD after t4.
t6: Device is restarted when temperature is reduced by 27°C (Auto−Retry version only; Latched version will require manual restart with EN pin).
t7: Device output has been shorted (or a severe current overload condition).
t8: Device Output current has exceeded ICB. The device is immediately shut down within the ICB shutdown time tCB. FAULT pin is pulled low.
t9: Device restarts after auto−retry time is exceeded (Auto−Retry only, Latch version will require a manual restart with EN).
Note: dotted line shows device remains off for latched version (until restarted using EN pin).

Figure 4. Overcurrent Protection Diagram

2000

14

1800
1600

10

ITH AND ICB, (mA)ITH AND ICB, (A)

12

8
6
ICB

4
2

1400
1200
1000
800

ICB

600
400

Max load current
per channel 2.5 A
0
0
10
20

ITH

ITH

200
30

40

50

0

60

50

100

150

200

250

RLIM, (kW)RLIM, (kW)Figure 5. Current Limit Setting vs. RLIM
(MT3, MT4 versions)Figure 6. Current Limit Setting vs. RLIM
(MT5, MT6 versions)www.onsemi.com
7300

NIS3071, NIV3071
9

7

1600

6

1400

5
ITH @ RLIM 15 kW

4

ICB @ RLIM 30 kW

3

ITH @ RLIM 30 kW

2

0
−40

0

20

40

60

80

ICB @ RLIM 200 kW
ICB @ RLIM 240 kW
ICB @ RLIM 300 kW

600

100

ITH @ RLIM 100 kW
ITH @ RLIM 150 kW
ITH @ RLIM 200 kW

ITH @ RLIM 300 kW
ITH @ RLIM 240 kW
0−40 −200
20 40 60 80 100 120 140 160

120

TJ, JUNCTION TEMPERATURE (°C)

TJ, JUNCTION TEMPERATURE (°C)

Figure 7. Junction Temperature vs. ITH & ICB(MT3, MT4 versions)Figure 8. Junction Temperature vs. ITH & ICB(MT5, MT6 versions)35
VIN 48 V

25

30

20

TURN−ON TIME (ms)

VIN 36 V
VIN 24 V

15
10
VIN 12 V

VIN 48 V
VIN 36 V

25

VIN 24 V

20
15
10

5

VIN 12 V

5
0

20

40
60
Cdvdt, CAPACITANCE (pF)

80

0

100

0

Figure 9. Turn−on Time vs. Cdvdt Capacitanceat TJ = −405C

20

40
60
Cdvdt, CAPACITANCE (pF)40

VIN 48 V

35

VIN 36 V30

VIN 24 V

25
20
15

VIN 12 V

10
5
0

0

20

80

100

Figure 10. Turn−on Time vs. Cdvdt Capacitanceat TJ = 255C

45

TURN−ON TIME (ms)TURN−ON TIME (ms)ICB @ RLIM 150 kW

800

30

0

ITH @ RLIM 62 kW

1000

200

ITH @ RLIM 62 kW−20

ICB @ RLIM 100 kW

1200

400

ICB @ RLIM 62 kW

1

ICB @ RLIM 62 kW

1800

ICB AND ITH, (mA)ICB AND ITH, (A)2000

ICB @ RLIM 15 kW

8

40
60
Cdvdt, CAPACITANCE (pF)

80

100

Figure 11. Turn−on Time vs. Cdvdt Capacitanceat TJ = 1255C

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8

NIS3071, NIV3071

Ch1: VIN
Ch2: VOUT
Ch3: VEN

Ch1: VIN
Ch2: VOUT1
Ch3: VEN
Ch4: VOUT2

Figure 12. Turning on a Single Output with EN Pin

Figure 13. Turning on a Single Output with the EN
Pin While Another Output Pin is On

Ch1: VIN
Ch2: VOUT
Ch3: VFAULT

Ch1: VIN
Ch2: VOUT1
Ch3: VFAULT
Ch4: VOUT2

Figure 14. Turning on a Single Output with the Input
Voltage (EN pin pull−up or floated)

Figure 15. Turning on a Single Output with the Input
Voltage While Another Output is On (EN pin pull−up
or floated)

Ch1: VIN
Ch2: VOUT
Ch3: VEN

Ch1: VIN
Ch2: VOUT
Ch3: VEN

Figure 16. Turn On with EN Pin with Cdvdt OpenFigure 17. Turn On with EN Pin with Cdvdt 56 pF

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9

NIS3071, NIV3071

Ch1: VIN
Ch2: VOUT
Ch3: IOUT
Ch4: VFAULT

Ch1: VIN
Ch2: VOUT
Ch3: IOUT
Ch4: VFAULT

Figure 18. ITH Overcurrent Event on Latching Device

Figure 19. ITH Overcurrent Event on Auto−retry
DeviceCh1: VIN
Ch2: VOUT
Ch3: IOUT
Ch4: VFAULT

Ch1: VIN
Ch2: VOUT
Ch3: IOUT
Ch4: VFAULT

Figure 20. ICB Overcurrent Event on Latching Device

Figure 21. ICB Overcurrent Event on Auto−retry
DeviceCh1: VIN
Ch2: VOUT
Ch3: IOUT
Ch4: VFAULT

Ch1: VIN
Ch2: VOUT
Ch3: IOUT
Ch4: VFAULT

Figure 22. Short Circuit Event on Latching Device

Figure 23. Short Circuit Event on Auto−retry Device

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10

NIS3071, NIV3071

Ch1: VIN
Ch2: VOUT1
Ch3: IOUT1
Ch4: VOUT2

Ch1: VIN
Ch2: VOUT1
Ch3: IOUT1
Ch4: VOUT2

Figure 24. ITH Overcurrent Event While Another
Output is On

Figure 25. ICB Overcurrent Event While Another
Output is On

ORDERING INFORMATION
Shutdown Version

Package

Shipping†

NIS3071MT3TWG

Latch

WQFN16 5x6 mm(Pb−Free)5000 / Tape & Reel

NIS3071MT4TWG

Auto−RWQFN16 5x6 mm(Pb−Free)5000 / Tape & Reel

NIS3071MTW3TWG

Latch

WQFN16 5x6 mm(Pb−Free)(Wettable Flank)

5000 / Tape & Reel

NIS3071MTW4TWG

Auto−RWQFN16 5x6 mm(Pb−Free)(Wettable Flank)

5000 / Tape & Reel

NIV3071MTW3TWG*

Latch

WQFNW16 5x6 mm(Pb−Free)(Wettable Flank)

5000 / Tape & Reel

NIV3071MTW4TWG*

Auto−RWQFNW16 5x6 mm(Pb−Free)(Wettable Flank)

5000 / Tape & Reel

NIS3071MTW5TWG

Latch

WQFN16 5x6 mm(Pb−Free)(Wettable Flank)

5000 / Tape & Reel

NIS3071MTW6TWG

Auto−RWQFN16 5x6 mm(Pb−Free)(Wettable Flank)

5000 / Tape & Reel

NIV3071MTW5TWG*

Latch

WQFNW16 5x6 mm(Pb−Free)(Wettable Flank)

5000 / Tape & Reel

NIV3071MTW6TWG*

Auto−RWQFNW16 5x6 mm(Pb−Free)(Wettable Flank)

5000 / Tape & Reel

Part Number†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAPCapable.

www.onsemi.com
11MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONSWQFN16 5x6, 1.05P
CASE 510CMISSUE ODATE 14 JUN 2019

GENERICMARKING DIAGRAM*XXXXXXXXXXXXXXXXAWLYYWWDOCUMENT NUMBER:DESCRIPTION:XXXX = Specific Device CodeA
= Assembly Location
WL = Wafer Lot
YY= YearWW = Work Week

98AON08122H
WQFN16 5x6, 1.05P*This information is generic. Please refer todevice data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

onsemi andare trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONSWQFNW16 5x6, 1.05P
CASE 512AN
ISSUE ODATE 30 JUL 2021

GENERICMARKING DIAGRAM*XXXXXXXXXXXXAWLYWW
XXXX = Specific Device CodeA
= Assembly Location
WL = Wafer Lot
Y= YearWW = Work Week

DOCUMENT NUMBER:DESCRIPTION:*This information is generic. Please refer todevice data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.

98AON36459H
WQFNW16 5x6, 1.05P

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

onsemi andare trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2021

www.onsemi.com

onsemi,, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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