Whitepaper

Addressing floating inputs
in digital systems

In the normal operations of a digital system, the input toany digital device within is clearly defined - it is either one
or zero. There are however interface cases where outputs
may be disabled that can result in floating inputs.

Consider a situation of 8, 16, 32 or 64 CMOS inputs, arranged ina bus. Typically, any of a number of drivers may control this input
bus. But in some cases, such as low power modes, none of theactive drivers are engaged by the overall system. Uncontrolled,
the voltage present at an input is determined by random,
unpredictable factors, not defined by the design of the overallsystem. That uncontrolled input is said to float.
Random events may unpredictably bring the floating input
voltage up to a point that the device will interpret as a one,or down to the point that the device will interpret as a zero.
This will cause output switching, a high current event that
may cause supply or ground bounce. As input thresholds aredependent upon supply the floating input may cause theoutput to switch back to its previous state. In the worst casethe floating input may cause output oscillation, which will
effect correct operation and cause excessive power dissipation.

Bus-hold circuitry eliminates floating inputs
Figure 1 is a representation of the input to a CMOS digitalcomponent. If VI is solidly one, the NMOS transistor on
the bottom switches on, and the PMOS transistor on thetop switches off. This switches the output to ground, oran output of digital zero. If VI is solidly zero, the opposite
happens, and the output is switched to VCC, or digital one.
VCCVIΔICC

Figure 1 - CMOS input buffer

When VI floats — it isn’t one or zero - both the NMOS andPMOS transistors may operate in their linear ranges, allowing
current ICC to flow through both transistors. When the input
floats above or below the input threshold the switching andpossible oscillation described previously may occur.

A solution to prevent this is to employ a bus hold circuit thatcan latch in the last input state presented at the device’sinput pin. Thus, even if the input would otherwise float, that
input is held to its previous value. Figure 2 shows a CMOS
input with bus hold cell.
VCC

InputpinSo, substituting values:		
RPULL-UP = (VCC – V TH) / IBHLO		RPULL-UP = (3.0 – 1.4) / 500 x 10 -6		
RPULL-UP = 3200 ΩPull-down resistor
For a pull-down resistor, the formula is:		
RPULL-DOWN = (V TH) / IBHHO)
A similar calculation yields 2800 ΩFigure 3 shows a typical bus-hold characteristic and load linesof different pull-up resistor values.

bus-hold cell

CMOS input buffer

Figure 2 - CMOS input with bus hold cell

The bus hold circuitry is a latch which requires a minimum
current to switch states, so floating inputs will not cause
switching or excessive power dissipation. Only a solid one
or zero will cause it to switch. Thus, even when the input
floats, the overall output stays at the value mandated by thepreviously defined input of one or zero.

For values less than 8k Ω there is no intersection of the load
line with bus-hold line, so no issue in pulling up an initial low
state input to high state. For larger resistor values the loadline intersects the bus-hold line and this intersection point
becomes the maximum voltage level to which the bus-hold ispulled from low, the input is never switching to high beyond
this point.
3.6k Ω
Typical bus-hold1000

10k Ω pull-up resistor

5k ΩCalculating resistor values
Let’s take the case of a pull-up resistor. The formula used tocalculate its value is:		
RPULL-UP = (VCC – V TH) / IBHLO
VCC is the value of the device’s power supply. We will assume,for this example that the device is supplied at 3.0 V.
V TH is a function of VIH, the input voltage that the device will
always recognize as a one, and VIL, the voltage that thedevice will always recognize as zero:		
V TH = (VIH + VIL) / 2						If VIH is 2.0 V and VIL is 0.8 V
V TH = (2.0 + 0.8) / 2
V TH = 1.4V

IBHLO is the bus hold LOW overdrive current. It can be foundin the Nexperia datasheet for the device (e.g. 500 μA).

8k Ω pull-up resistor

Hold current (μA)

Pull-up or pull-down resistors for a solid start up
The bus hold input is a solution to ensuring defined inputs at
all times. At power-up the bus hold cell (latch) may containeither a one or a zero. When a system first powers on, thesystem may require that the input of a device must start off
with a one or alternatively start off with a zero. The solution
might either be a pull-up resistor from VCC to enforce an inputof one, or a pull-down resistor to enforce an input of zero.

800

3.6k Ω pull-up resistor

60010k Ω

40000

1.0

1.8

2.5

3.5Output voltage (V)Figure 3 - Typical bus hold characteristic and resistor load lines

Availability of the bus-hold feature
The bus-hold feature is standard on all of Nexperia’s LVT(Low Voltage Technology) and ALVT (Advanced Low-Voltage
BiCMOS Technology) bus-interface products. This includes
all 8- and 16-bit buffers, inverters, drivers, flip-flops, latches/registered drivers, level shifters/translators, and transceivers.
On other Nexperia families, the bus-hold feature is indicatedby the addition of an “H” in the product number. Examples
are 74LVCH245 instead of 74LVC245 and 74AVCH2T45 insteadof 74AVC2T45).

© 2019 Nexperia B.V.
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nexperia.com

5k Ω pull-up resistor

8k Ω

Date of release:
September 2019