SFF specifications are available at http://www.snia.org/sff/specifications
or ftp://ftp.seagate.com/sff

This specification was developed by the SFF Committee prior to it
becoming the SFF TA (Technology Affiliate) TWG (Technical Working
Group) of SNIA (Storage Networking Industry Association).

The information below should be used instead of the equivalent herein.
POINTS OF CONTACT:
Chairman SFF TA TWG
Email: SFF-Chair@snia.org

If you are interested in participating in the activities of the SFF TWG, themembership application can be found at:
http://www.snia.org/sff/join
The complete list of SFF Specifications which have been completed or are currently
being worked on can be found at:
http://www.snia.org/sff/specifications/SFF-8000.TXT
The operations which complement the SNIA's TWG Policies & Procedures to guide the SFF
TWG can be found at:
http://www.snia.org/sff/specifications/SFF-8032.PDF
Suggestions for improvement of this specification will be welcome, they should besubmitted to:
http://www.snia.org/feedback

Information Speciﬁcation

INF-8077i, Revision 4.5

SFF Committee documentation may be purchased in hard copy or electronic form.
SFF speciﬁcations are available at ftp://ftp.seagate.com/sff

SFF Committee
INF-8077i
10 Gigabit Small Form Factor Pluggable Module
Revision 4.5 August 31, 2005

Secretariat: SFF Committee
Abstract: This speciﬁcation deﬁnes the electrical, management, and mechanical interfaces of the XFP module. The
module is a hot pluggable small footprint serial-to-serial data-agnostic multirate optical transceiver, intended tosupport Telecom (SONET OC-192 and G.709 “OTU-2”) and Datacom applications (10 Gb/s Ethernet and 10 Gb/s
Fibre Channel). Nominal data rates range from 9.95 Gb/s, 10.31 Gb/s, 10.52 Gb/s, 10.70 Gb/s, and the emerging
11.09 Gb/s. The modules support all data encodings for these technologies. The modules may be used to implement single mode or multi-mode serial optical interfaces at 850 nm, 1310 nm, or 1550 nm. The XFP module design
may use one of several different optical connectors. An adaptable heatsink option allows a single module design tobe compatible with a variety of hosts.
Support: This document was adopted by the XFP MSA and is provided to the SFF for distribution and as a source
document for related SFF projects.
Documentation: This document has been prepared according to the guidelines and agreements of the XFP MSA.
The XFP MSA has the stated intention of encouraging broad and rapid industry adoption of the speciﬁcation. The
XFP speciﬁcation and the technologies it uses may be offered to formal standards bodies to further support the
adoption of the speciﬁcation.

POINTS OF CONTACT:Technical Editor:
Ali Ghiasi
Broadcom Corporation
3151 Zanker RoadSan Jose, CA 95134
Voice: (408) 922-7423
EMail: aghiasi@broadcom.com

XFP Chair:
Robert Snively
Brocade Communication Systems, Inc.
1745 Technology Drive
San Jose, CA 95110
Voice: (408) 487-8135
EMail: rsnively@brocade.com

SFF Chair
I. Dal Allan
14426 Black Walnut Court
Saratoga, CA 95070
Voice: (408) 867-6630
Fax: (408) 867-2115
Email: endlcom@acm.org
XFP (10 Gbit pluggable module)

SFF Page i

Information Speciﬁcation

INF-8077i, Revision 4.5

EXPRESSION OF SUPPORT BY MANUFACTURERS
The SFF Committee does not require expressions of support for documents accepted as informational.
The user's attention is called to the statements of intellectual property rights and copyright in the XFP speciﬁcation,
page ii. By distribution of this Speciﬁcation, no position is taken with respect to the validity of these statements or ofany patent rights in connection therewith. The XFP adopter’s agreement, available from XFP Promoters, contains
agreements with respect to intellectual property rights and other rights and responsibilities.

SFF Committee information
If you are not a member of the SFF Committee, but you are interested in participating, the following principles havebeen reprinted here for your information.

PRINCIPLES OF THE SFF COMMITTEEThe SFF Committee is an ad hoc group formed to address storage industry needs in a prompt manner. Whenformed in 1990, the original goals were limited to deﬁning de facto mechanical envelopes within which disk drives
can be developed to ﬁt compact computer and other small products.
In November 1992, the SFF Committee objectives were broadened to encompass other areas which needed similar attention, such as pinouts for interface applications, and form factor issues on larger disk drives. SFF is a forum
for resolving industry issues that are either not addressed by the standards process or need an immediate solution.
Documents created by the SFF Committee are expected to be submitted to bodies such as EIA (Electronic Industries Association) or an ANSI Accredited Standards Committee. They may be accepted for separate standards, orincorporated into other standards activities.
The principles of operation for the SFF Committee are not unlike those of an accredited standards committee.
There are 3 levels of participation:- Attending the meetings is open to all, but taking part in discussions is limited to member companies, or
those invited by member companies- The minutes and copies of material which are discussed during meetings are distributed only to those who
sign up to receive documentation.
- The individuals who represent member companies of the SFF Committee receive documentation and voteon issues that arise. Votes are not taken during meetings, only guidance on directions. All voting is by letter
ballot, which ensures all members an equal opportunity to be heard.
Material presented at SFF Committee meetings becomes public domain. There are no restrictions on the open
mailing of material presented at committee meetings. In order to reduce disagreements and misunderstandings,
copies must be provided for all agenda items that are discussed. Copies of the material presented, or revisions if
completed in time, are included in the documentation mailings.
The sites for SFF Committee meetings rotate based on which member companies volunteer to host the meetings.
Meetings have typically been held during the INCITS T10 weeks. The meetings of the SFF Special Subject Working Group on Transceivers have typically been held during INCITS T11 weeks.
The funds received from the annual membership fees are placed in escrow, and are used to reimburse ENDL for
the services to manage the SFF Committee.

XFP (10 Gbit pluggable module)

SFF Page ii

Information Speciﬁcation

INF-8077i, Revision 4.5

SFF Membership and Subscription application
Membership includes voting privileges on SFF Specs under development.
CD_Access Electronic documentation contains:- Minutes for the year-to-date plus all of last year
- Email trafﬁc for the year-to-date plus all of last year
- The current revision of all the SFF Speciﬁcations, as well as any previous revisions distributed during
the current year.
Meeting documentation contains:- Minutes for the current meeting cycle.
- Copies of Speciﬁcations revised during the current meeting cycle.
Each electronic document mailing obsoletes the previous mailing of that year e.g. July replaces May. To build
a complete set of archives of all SFF documentation, retain the last SFF CD_Access mailing of each year.
Name: __________________________________ Title: _________________________
Company: ______________________________________________________________
Address: ______________________________________________________________________________________________________________________________________
Phone: ____________________________ Fax: ________________________________
Email: _________________________________________________________________
Please register me with the SFF Committee for one year.
___ Voting Membership w/Electronic documentation$2,160___ Voting Membership w/Meeting documentation$1,800___ Non-voting Observer w/Electronic documentation$660 U.S.

$760 Overseas___ Non-voting Observer w/Meeting documentation$300 U.S.

$400 Overseas

Check Payable to SFF Committee for $_________ is Enclosed
Please invoice me for $_________ on PO #: ___________________
MC/Visa/AmX______________________________________ Expires_________
Mail, FAX, or E-mail to:
SFF Committee
14426 Black Walnut Ct.
Saratoga, CA 95070

XFP (10 Gbit pluggable module)

408-867-6630
408-867-2115Fx
endlcom@acm.org

SFF Page iii

Information Speciﬁcation

INF-8077i, Revision 4.5

Foreword for SFF documents
When 2 1/2" diameter disk drives were introduced, there was no commonality on external dimensions e.g. physicalsize, mounting locations, connector type, connector location, between vendors.
The ﬁrst use of these disk drives was in speciﬁc applications such as laptop portable computers in which space
was at a premium and time to market with the latest machine was an important factor. System integrators worked
individually with vendors to develop the packaging. The result was wide diversity, and with space being such amajor consideration in packaging, it was not possible to replace one vendor's drive with a competitive product.
The desire to reduce disk drive sizes to even smaller dimensions such as 1.8" and 1.3" made it likely that devices
would become even more constrained in dimensions because of a possibility that such small devices could be
inserted into a socket, not unlike the method of retaining semiconductor devices.
The problems faced by integrators, device suppliers, and component suppliers led to the formation of an industry
ad hoc group to address the marketing and engineering considerations of the emerging new technology in disk
drives. After two informal gatherings on the subject in the summer of 1990, the SFF Committee held its ﬁrst meeting in August.
During the development of the form factor deﬁnitions, other activities were suggested because participants in the
SFF Committee faced problems other than the physical form factors of disk drives. In November 1992, the members approved an expansion in charter to address any issues of general interest and concern to the storage industry. The SFF Committee became a forum for resolving industry issues that are either not addressed by thestandards process or need an immediate solution.
At the same time, the principle was adopted of restricting the scope of an SFF project to a narrow area, so that the
majority of documents would be small and the projects could be completed in a rapid timeframe. If proposals are
made by a number of contributors, the participating members select the best concepts and uses them to develop
speciﬁcations which address speciﬁc issues in emerging storage markets.
Those companies which have agreed to support a documented speciﬁcation are identiﬁed in the ﬁrst pages of each
SFF Speciﬁcation. Industry consensus is not an essential requirement to publish an SFF Speciﬁcation because it isrecognized that in an emerging product area, there is room for more than one approach. By making the documentation on competing proposals available, an integrator can examine the alternatives available and select the product that is felt to be most suitable.
Suggestions for improvement of this document will be welcome. They should be sent to the SFF Committee, 14426
Black Walnut Ct, Saratoga, CA 95070. The suggestions should additionally be sent to the XFP Chair and Technical
Editor.
The development work on this speciﬁcation was done by the XFP Group, an industry MSA.

XFP (10 Gbit pluggable module)

SFF Page iv

Information Speciﬁcation

INF-8077i, Revision 4.5

SFF Speciﬁcations
There are several projects active within the SFF Committee. At the date of printing, document numbers had been
assigned to the following projects. The status of Speciﬁcations is dependent on committee activities.
F = Forwarded

The document has been approved by the members for forwarding to a formal standards
body.

P = Published

The document has been balloted by members and is available as a published SFF Speciﬁcation.

A = Approved
C = Canceled

The document has been approved by ballot of the members and is in preparation as an
SFF Speciﬁcation.
The project was canceled, and no Speciﬁcation was Published.

D = Development

The document is under development at SFF.

E = Expired

The document has been published as an SFF Speciﬁcation, and the members voted
against re-publishing it when it came up for annual review.

e = electronic

Used as a sufﬁx to indicate an SFF Speciﬁcation which has Expired but is still available inelectronic form from SFF e.g. a speciﬁcation has been incorporated into a draft or published standard which is only available in hard copy.

i = Information

The document has no SFF project activity in progress, but it deﬁnes features in developing
industry standards. The document was provided by a company, editor of an accredited
standard in development, or an individual. It is provided for broad review (comments to theauthor are encouraged).

s = submitted The document is a proposal to the members for consideration to become an SFF Speciﬁcation.

Spec #
SFF-8000
INF-8001i
INF-8002i
SFF-8003
SFF-8004
SFF-8005
SFF-8006
SFF-8007
SFF-8008
SFF-8009

Rev
E
E
E
E
E
E
E
E
4.1

List of Speciﬁcations as of March 3, 2003
SFF Committee Information
44-pin ATA (AT Attachment) Pinouts for SFF Drives
68-pin ATA (AT Attachment) for SFF Drives
SCSI Pinouts for SFF Drives
Small Form Factor 2.5" Drives
Small Form Factor 1.8" Drives
Small Form Factor 1.3" Drives
2mm Connector Alternatives
68-pin Embedded Interface for SFF Drives
Unitized Connector for Cabled Drives

SFF-8010
INF-8011i
SFF-8012
SFF-8013
SFF-8014
SFF-8015

E
E
3.0
E
C
E

Small Form Factor 15mm 1.8" Drives
ATA Timing Extensions for Local Bus
4-Pin Power Connector Dimensions
ATA Download Microcode Command
Unitized Connector for Rack Mounted Drives
SCA Connector for Rack Mounted SFF SCSI Drives

XFP (10 Gbit pluggable module)

SFF Page v

Information Speciﬁcation

INF-8077i, Revision 4.5

Spec #
SFF-8016
SFF-8017
SFF-8018
SFF-8019

Rev
C
E
E
E

List of Speciﬁcations as of March 3, 2003
Small Form Factor 10mm 2.5" Drives
SCSI Wiring Rules for Mixed Cable Plants
ATA Low Power Modes
Identify Drive Data for ATA Disks up to 8 GB

INF-8020i
INF-8028i
SFF-8029

E
E
E

ATA Packet Interface for CD-ROMs- Errata to SFF-8020 Rev 2.5- Errata to SFF-8020 Rev 1.2

SFF-8030
SFF-8031
SFF-8032
INF-8033i
INF-8034i
INF-8035i
INF-8036i
INF-8037i
INF-8038i
INF-8039i

1.8
1.5
E
E
E
E
E
E
E

SFF Committee Charter
Named Representatives of SFF Committee Members
SFF Committee Principles of Operation
Improved ATA Timing Extensions to 16.6 MBs
High Speed Local Bus ATA Line Termination Issues
Self-Monitoring, Analysis & Reporting Technology
ATA Signal Integrity Issues
Intel Small PCI SIG
Intel Bus Master IDE ATA Speciﬁcation
Phoenix EDD (Enhanced Disk Drive) Speciﬁcation

SFF-8040
SFF-8041
SFF-8042
SFF-8043
SFF-8045
SFF-8046
SFF-8047
SFF-8048
SFF-8049

1.2
C
C
E
4.5
E
C
C
E

25-pin Asynchronous SCSI Pinout
SCA-2 Connector Backend Conﬁgurations
VHDCI Connector Backend Conﬁgurations
40-pin MicroSCSI Pinout
40-pin SCA-2 Connector w/Parallel Selection
80-pin SCA-2 Connector for SCSI Disk Drives
40-pin SCA-2 Connector w/Serial Selection
80-pin SCA-2 Connector w/Parallel ESI
80-conductor ATA Cable Assembly

INF-8050i
INF-8051i
INF-8052i
SFF-8053
SFF-8054
INF-8055i
SFF-8056
SFF-8057
SFF-8058
SFF-8059

1.0
E
E
5.5

Bootable CD-ROM
Small Form Factor 3" Drives
ATA Interface for 3" Removable Devices
GBIC (Gigabit Interface Converter)
Automation Drive Interface Connector
SMART Application Guide for ATA Interface
50-pin 2mm Connector
Unitized ATA 2-plus Connector
Unitized ATA 3-in-1 Connector
40-pin ATA Connector

SFF-8060
SFF-8061
SFF-8062
SFF-8065

1.1
1.1

E
C
E
E
E

C

XFP (10 Gbit pluggable module)

SFF Committee Patent Policy
Emailing drawings over the SFF Reﬂector
Rolling Calendar of SSWGs and Plenaries
40-pin SCA-2 Connector w/High Voltage
SFF Page vi

Information Speciﬁcation

INF-8077i, Revision 4.5

Spec #
SFF-8066
SFF-8067
INF-8068i
SFF-8069

Rev
C
3.0
1.0
E

List of Speciﬁcations as of March 3, 2003
80-pin SCA-2 Connector w/High Voltage
40-pin SCA-2 Connector w/Bidirectional ESI
Guidelines to Import Drawings into SFF Specs
Fax-Access Instructions

INF-8070i
SFF-8072
SFF-8073
INF-8074i
SFF-8075
SFF-8076
INF-8077i
SFF-8078
SFF-8080
SFF-8082
INF-8090i

1.3
1.2
C
1.0
1.0
3.0

5.4

ATAPI for Rewritable Removable Media
80-pin SCA-2 for Fibre Channel Tape Applications
20-pin SCA-2 for GBIC Applications
SFP (Small Formfactor Pluggable) Transceiver
PCI Card Version of SFP Cage
SFP Additional IDs
XFP
XFP-E
ATAPI for CD-Recordable MediaLabeling of Ports and Cable Assemblies
ATAPI for DVD (Digital Video Data)

SFF-8101
SFF-8110
SFF-8111
SFF-8120

C
C
1.3
2.6

3 Gbs and 4 Gbs Signal Characteristics
5V Parallel 1.8" drive form factor
1.8" drive form factor (60x70mm)
1.8" drive form factor (78x54mm)

SFF-8200e
SFF-8201e
SFF-8212e
SFF-8221
SFF-8222
SFF-8223
SFF-8225

1.1
1.3
1.2
2.0
1.1
0.4
C

2 1/2" drive form factors (all of 82xx family)
2 1/2" drive form factor dimensions
2 1/2" drive w/SFF-8001 44-pin ATA Connector
Pre-Aligned 2.5" Drive >10mm Form Factor
2.5" Drive w/SCA-2 Connector
2.5" Drive w/Serial Attachment Connector
2.5" Single Voltage Drive

SFF-8300
SFF-8301
SFF-8302e
SFF-8323
SFF-8332e
SFF-8337e
SFF-8342e
INF-8350i

1.2
1.4
1.1
0.4
1.2
1.2
1.3
6.1

3 1/2" drive form factors (all of 83xx family)
3 1/2" drive form factor dimensions
3 1/2" Cabled Connector locations
3 1/2" drive w/Serial Attachment Connector
3 1/2" drive w/80-pin SFF-8015 SCA Connector
3 1/2" drive w/SCA-2 Connector
3 1/2" drive w/Serial Unitized Connector
3 1/2" Packaged Drives

SFF-8400
SFF-8410
SFF-8411
SFF-8412
SFF-8415
SFF-8416

C
16.1

VHDCI (Very High Density Cable Interconnect)
High Speed Serial Testing for Copper Links
High Speed Serial Testing for Backplanes
HSOI (High Speed Optical Interconnect) Testing
HPEI (High Performance Electrical Interconnect)
HPEI Measurement of Bulk Cable

E

12.1
4.1
0.1

XFP (10 Gbit pluggable module)

SFF Page vii

Information Speciﬁcation

INF-8077i, Revision 4.5

Spec #

Rev

List of Speciﬁcations as of March 3, 2003

SFF-8420
SFF-8421
SFF-8422
SFF-8423
SFF-8424
SFF-8425

11.1
2.4
C
C

HSSDC-1 Shielded Connections
HSSDC-2 Shielded Connections
FCI Shielded Connections
Molex Shielded Connections
Dual Row HSSDC-2 Shielded Connections
Single Voltage Drives

SFF-8430
SFF-8441
SFF-8451
SFF-8452
SFF-8453

4.1
14.1
10.1
3.1

MT-RJ Duplex Optical Connections
VHDCI Shielded Conﬁgurations
SCA-2 Unshielded Connections
Glitch Free Mating Connections for Multidrop Aps
Shielded High Speed Serial connectors

SFF-8460
SFF-8470
SFF-8471
SFF-8472
INF-8475i

1.2
2.5
C
9.3
2.2

HSS Backplane Design Guidelines
Multi Lane Copper Connector
ZFP Multi Lane Copper Connector
Diagnostic Monitoring Interface for Optical Xcvrs
XPAK Small Formfactor Pluggable Receiver

SFF-8480
SFF-8482
SFF-8483

2.1
0.0
C

HSS (High Speed Serial) DB9 Connections
Internal Serial Attachment Connector
External Serial Attachment Connector

SFF-8500e
SFF-8501e
SFF-8508e
SFF-8523
SFF-8551
SFF-8572
SFF-8610

1.1
1.1
1.1
0.4
3.2
C
C

5 1/4" drive form factors (all of 85xx family)
5 1/4" drive form factor dimensions
5 1/4" ATAPI CD-ROM w/audio connectors
5 1/4" drive w/Serial Attachment Connector
5 1/4" CD Drives form factor
5 1/4" Tape form factor
SDX (Storage Device Architecture)

Document Sources
Copies of ANSI standards or proposed ANSI standards may be purchased from Global Engineering.
15 Inverness Way East
Englewood
CO 80112-5704

800-854-7179 or 303-792-2181
303-792-2192Fx

Copies of SFF Speciﬁcations are available by joining the SFF Committee as an Observer or Member or by download at ftp://ftp.seagate.com/sff
14426 Black Walnut Ct.
Saratoga
CA 95070
XFP (10 Gbit pluggable module)

408-867-6630x303
408-867-2115Fx

SFF Page viii

XFP Rev 4.5

August 31, 2005

(10 Gigabit Small Form Factor Pluggable Module)
XFP Revision 4.5
Review Revision

Copyright © 2002-2005 by XFP Promoters
See copyright notice for restrictions.

Technical Editor:

XFP Chair:

Ali Ghiasi

Robert Snively

Broadcom Corporation

Brocade Communication Systems, Inc.

3151 Zanker Road

1745 Technology Drive

San Jose, CA 95134

San Jose, CA 95110

Voice:(408) 922-7423

Voice (408) 487-8135

EMail: aghiasi@broadcom.com

EMail: rsnively@brocade.com

XFP Rev 4.5

August 31, 2005

XFP Legal Disclaimer
This speciﬁcation has been formally adopted by the XFP Promoters. Changes to the document may bemade to correct any errata in the speciﬁcation, including clariﬁcations and other changes. Verify that you areusing the latest revision of the speciﬁcation by visiting the XFP web-site at www.xfpmsa.org.
The promoters of the XFP speciﬁcation, Broadcom Corporation, Brocade Communications Systems, Inc.,
Ciena Corporation, Emulex Corporation, Finisar Corporation, JDS Uniphase Corporation, Innovation CoreSEI, Inc., Maxim Integrated Products, Tyco Electronics Corporation, and Velio Communication (“XFP Promoters”), and many contributors, collaborated to develop a speciﬁcation for a 10 Gigabit small foot print
pluggable module. The promoters stated a wish to encourage broad and rapid industry adoption of the speciﬁcation. This speciﬁcation is the result of such collaboration. The XFP speciﬁcation may be offered to formal
standards bodies to further support the adoption of the speciﬁcation.
THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDINGANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULARPURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATIONOR SAMPLE. THE XFP PROMOTERS DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OF INFORMATION IN THIS SPECIFICATION. IN NO EVENT SHALL THE XFP PROMOTERS, CONTRIBUTORS OR ADOPTERS BE
LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, EXEMPLARY, PUNITIVE, OR CONSEQUENTIAL
DAMAGES, INCLUDING, WITHOUT LIMITATION, LOST PROFITS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
This speciﬁcation may contain, and sometimes even require the use of, intellectual property owned byothers. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted
herein, except as indicated in the following copyright notice. Rights to certain of such intellectual property
may be provided by the XFP Promoters Agreement, XFP Adopters Agreement and the XFP Contributors
Addendum.

XFP Copyright Notice
Copyright by XFP Promoters in accordance with XFP Promoters. XFP Promoters are Broadcom Corporation, Brocade Communications Systems, Inc., Ciena Corporation, Emulex Corporation, Finisar Corporation,JDS Uniphase Corporation, Innovation Core SEI, Inc., Maxim Integrated Products, Tyco Electronics Corporation, and Velio Communication. All rights are reserved except that a license is hereby granted to copy andreproduce this speciﬁcation, in unmodiﬁed form only, for fee-free distribution or for use internal to the organization copying the speciﬁcation.

XFP Identiﬁcation of defects
If errors are identiﬁed in this speciﬁcation, please notify the chair and editor identiﬁed on the ﬁrst page.
Please provide a clear identiﬁcation of the error, the text of any proposed correction, and a justiﬁcation or
explanation of the correction.

Page x

Copyright © 2002-2005 by XFP PromotersXFP Rev 4.5

August 31, 2005

XFP Publication History

Revision
NumberDescription

Date

0.1

Initial Publication of Document, Preliminary

3/27/020.5

First full draft

4/11/02

0.7

Second full draft

5/23/02

0.8

Third full draft

6/21/02

0.9

Pre-Public Release 0

7/15/02

0.91

Pre-Public Release 1

7/16/02

0.92

1st-Public Release

7/19/02

0.93

Pre-Meeting Editing Draft

8/21/020.95

Internal draft

09/21/02

0.99

2nd pre-Public Release10/31/02

1.0

Pre-Ratification Draft

12/2/022.0

Adoption Draft

12/16/02

3.0

Adopted Specification

3/3/03

3.1

Modified Copyright Statement

4/02/03

4.0

Adopted Specification. Updated CRC R/W, Updated Designations, and Updated Registers Nomenclature

4/13/04

4.1

I2C Errata, S-parameters adjustment, Annex E3, Correcting mixed mode equation ofAnnex C4, Annex for BER 1E-15, address role over

4/20/05

4.5

Non-EQJ Jitter definition, Annex E3, and Bail Color.

8/31/05

Page xi

Copyright © 2002-2005 by XFP PromotersXFP Rev 4.5

August 31, 2005

XFP Foreword
The XFP Promoters, Broadcom Corporation, Brocade Communications Systems, Inc., Ciena Corporation, Emulex Corporation, Finisar Corporation, Innovation Core SEI, Inc. (a Sumitomo ElectricCompany), JDS Uniphase Corporation, Maxim Integrated Products, Tyco Electronics Corporation,
Velio Communication, and many contributors gathered together to develop a speciﬁcation for a 10
Gigabit small foot print pluggable module. The Promoters stated a wish to encourage broad andrapid industry adoption of the speciﬁcation. The XFP speciﬁcation may be offered to formal standards bodies to further support the adoption of the speciﬁcation. The XFP Promoters and Contributors solicited technical review and contributions to the XFP speciﬁcation among many component,
module, and system designers and manufacturers to assure that it meets a broad variety of requirements.
Signed agreements exist among the promoters and between the promoters and contributors thatallowed them to carry forward these activities in a manner that encouraged rapid development,
open sharing of technology, and the timely resolution of disagreements. The agreements further
explained and protected the rights of both promoters and contributors. Similar agreements protect
the rights of adopters of the speciﬁcation.
Organizations may become adopters of the XFP speciﬁcation by contacting any XFP Promoter andrequesting the necessary forms and following the required procedures.

XFP Contributors

Aeluros

Marvell Semiconductor, Inc.

Agere Systems

Mathstar, Inc.

Agilent Technologies, Inc.

McDataAlcatel Optronics

MergeOptics GmbH

AMCC

Micrel Semiconductor, Inc.

Ample Communications

Mindspeed Technologies

Analog Devices, Inc.

Mitsubishi Electric

ASIP, Inc.

Modulight, Inc.

ASTRI

Molex, Inc.

AtricaNEC Corporation

AtricaNEL Corporation

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Avalon Photonics, Ltd.

NTTBig Bear Networks

OEpic, Inc.

Cortina Systems

OpNext

EMC Corporation

Optical Communication Products, Inc.

Emcore Corporation

Optium Corporation

Force 10 Networks, Inc.

OptoIC Technology

Foxconn Electronics, Inc.

Picolight, Inc.

Fourte’ Design and Development

PMC-Sierra

FujitsuPrimarion

Gennum Corporation

Phyworks Limited

GTRAN, Inc.

Qlogic, Inc.

HARTING Electro-Optics

Quake Technologies

Hitachi Cable America, Inc.

RF Micro Devices

Industrial Technology Research InstituteSamsung Electronics Company, Ltd.

Inﬁneon Technologies

Sigma-Links, Inc. (an OKI and Fujikura joint venture)Inﬁnera Corporation

Silicon Bridge, Inc.

Intel Corporation

Spirent Communications

I-TECH Corporation

Stratos Lightwave, Inc.

KeyEye Communications

Sun MicroSystems, Inc.

Kodeos Communications

Vitesse Semiconductor Corporation

Lattice Semiconductor Corporation

Wuhan Telecommunication Devices Co.

LSI Logic Corporation

Xilinx, Inc.

Luminent, Inc. (an MRV Communications Com-

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XFP Acknowledgments

The XFP members would like to acknowledge and thank Dr. Ali Ghiasi for his tremendous effort
and diligence in editing this speciﬁcation.
The members would like to thank Dr. Lew Aronson and Mr. Ed Bright for writing the Management
and Mechanical chapters. In addition, they would like to thank Mr. Tom Lindsay for the jitter Appendix, Dr. Piero Bradley for jitter section, Mr. Lawrence Williams for the XFI Channel Simulationand Modeling and the Optimum Via Appendix, Mr. Henrik Johansen for the compliance test boards
Appendix, Mr. Steve Silverman for the power supply section, Mr. Gary Heitkamp for the Thermal
Appendix, Mr. Randy Clark for the 2-Wire Protocol, Mr. Ron Miller for the TDR Appendix, and Dr.
Stefanos Sidiropoulos for the VPS section.
The members would also like to thank Mr. Robert Snively for skillfully steering the MSA, as without
him we could not have achieved our goal.
Special thanks are due to all those who attended the meetings and made contributions, as this document is a collection of their work.

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REVISON 4.5

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XFP Table of Contents
Chapter 1:
1.1
1.2

High Speed Electrical Specification XFI.............................................. 16

XFI ASIC/SerDes Transmitter Output Speciﬁcations at A (Informative)............................21
XFI ASIC/SerDes Receiver Input Speciﬁcations at D (Informative)..................................23

XFI Host System Speciﬁcation ........................................................................................... 26
3.7.1

XFP MSAPower Noise Output..........................................................................................................11
Power Noise Susceptibility................................................................................................12
Host Filtering ....................................................................................................................13

Introduction ......................................................................................................................... 16
XFI Applications Deﬁnition.................................................................................................. 16
XFI Termination and DC Blocking....................................................................................... 17
XFI Jitter Deﬁnitions............................................................................................................ 19
XFI Compliance Channel.................................................................................................... 19
XFI ASIC/SerDes Speciﬁcation .......................................................................................... 21
3.6.1
3.6.2

3.7

Mod_NR..............................................................................................................................6
Mod_DeSel .........................................................................................................................6Interrupt ..............................................................................................................................7
TX_DIS ...............................................................................................................................7
Mod_ABS............................................................................................................................7
RX_LOS..............................................................................................................................7
P_Down/RST ......................................................................................................................7
2.4.7.1 Power Down Function ............................................................................................7
2.4.7.2 Reset Function.......................................................................................................7
2.4.7.3 Module Behavior during Power Down and Reset ..................................................8

ESD .................................................................................................................................... 15

Chapter 3:
3.1
3.2
3.3
3.4
3.5
3.6

.......................................................................... 3

Low Speed Electrical Speciﬁcations ..................................................................................... 9
Timing Requirement of Control and Status I/O................................................................... 10
XFP Power Requirement .................................................................................................... 11
2.7.1
2.7.2
2.7.3

2.8

XFP Electrical Interface

Introduction ........................................................................................................................... 3
General Requirements.......................................................................................................... 3
XFP Host Connector Deﬁnition............................................................................................. 3
Low Speed Electrical Hardware Pins.................................................................................... 6
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7

2.5
2.6
2.7

.................................................................... 1

Introduction ........................................................................................................................... 1.............................................................................. Requirements on Press announcements2

Chapter 2:
2.1
2.2
2.3
2.4

Scope of XFP specification

XFI Host Transmitter Output Speciﬁcations at B...............................................................26

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REVISON 4.5

3.7.2

3.8

Chapter 4:

Chapter 5:
5.0.1

XFP 2-Wire Interface Protocol.............................................................. 42

Packet Error Checking ......................................................................................................46
XFP Memory Address Counter (Read and Write Operations)..........................................46
Read Operations (Current Address Read) .......................................................................47
Read Operations (Random Read) ....................................................................................47
Read Operations (Sequential Read).................................................................................49
Read Operation Packet Error Checking............................................................................50
Write Operations (Byte Write)...........................................................................................51
Write Operations (Sequential Write) .................................................................................52
Write Operation Packet Error Checking ............................................................................53
Write Operations (Acknowledge Polling) ..........................................................................54

Management interface.......................................................................... 55

Applicable Documents ......................................................................................................57

Description of Lower Memory Map: Control Functions, Diagnostics, Table Access ........... 58
Identiﬁer .............................................................................................................................. 59
Signal Conditioner Control.................................................................................................. 59
2-Wire Serial Interface Checksum ...................................................................................... 61
Table Selection and Password Entry (Table 44).................................................................. 61
Basic Monitoring Functions ................................................................................................ 62
Optional Variable Power Supply (VPS) Control .................................................................. 64
System BER Reporting....................................................................................................... 67
Wavelength Control ............................................................................................................ 67
FEC Control ........................................................................................................................ 68
Interrupt System Logic........................................................................................................ 69
5.11.1XFP MSA

Optional Synchronous CMU Clock ...................................................................................40

Introduction ......................................................................................................................... 42
XFP 2-Wire Timing Diagram............................................................................................... 42
Memory Transaction Timing................................................................................................ 44
Device Addressing and Operation ...................................................................................... 45
Read/Write Functionality .................................................................................................... 46
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11

Telecom Module................................................................................................................38
Datacom Module...............................................................................................................39

Reference Clock Speciﬁcations .......................................................................................... 40
3.10.1

4.1
4.2
4.3
4.4
4.5

XFI Module Transmitter Input Speciﬁcations at B’ ............................................................32
XFI Module Receiver Output Speciﬁcations at C’.............................................................35

Signal Conditioner .............................................................................................................. 38
3.9.1
3.9.2

3.10

XFI Host Receiver Input Speciﬁcations at C.....................................................................28

XFI Module Speciﬁcations .................................................................................................. 32
3.8.1
3.8.2

3.9

August 31, 2005

General Control and Status Bits .......................................................................................70

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REVISON 4.5

5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
5.25
5.26
5.27
5.28
5.29
5.30
5.31
5.32
5.33
5.34
5.35
5.36
5.37
5.38
5.39
5.40
5.41
5.42
5.43
5.44
5.45
5.46
5.47

Timing for Soft Control and Status Functions ..................................................................... 71
Description of Upper Memory Map Table 00h – Future Diagnostics Functions.................. 81
Description of Upper Memory Map Table 01h – Serial ID Memory Map ............................ 81
Identiﬁer .............................................................................................................................. 82
Extended Identiﬁer.............................................................................................................. 83
Connector ........................................................................................................................... 83
Interface Speciﬁcation ........................................................................................................ 84
Encoding............................................................................................................................. 86
BR, Minimum ...................................................................................................................... 87
BR, maximum ..................................................................................................................... 87
Length (Standard single mode ﬁber)-km ............................................................................ 87
Length (Extended Bandwidth 50 mm Multimode Fiber)...................................................... 87
Length (50 um Multimode Fiber)......................................................................................... 88
Length (62.5 um Multimode Fiber)...................................................................................... 88
Length (Copper).................................................................................................................. 88
Device Technology.............................................................................................................. 89
Vendor name ...................................................................................................................... 90
CDR Support ...................................................................................................................... 90
Vendor OUI ......................................................................................................................... 90
Vendor PN .......................................................................................................................... 91
Vendor Rev ......................................................................................................................... 91
Laser Wavelength ............................................................................................................... 91
Laser Wavelength Tolerance............................................................................................... 91
Maximum Case Temperature.............................................................................................. 92
CC_BASE ........................................................................................................................... 92
Power supply requirements ................................................................................................ 93
Vendor SN .......................................................................................................................... 93
Date Code........................................................................................................................... 94
Diagnostic Monitoring Type................................................................................................. 94
Enhanced Options .............................................................................................................. 95
Auxiliary Monitoring ............................................................................................................ 96
CC_EXT.............................................................................................................................. 97
Vendor Speciﬁc ID Field ..................................................................................................... 97
Description of Upper Memory Map Table 02h – User EEPROM Data................................ 97
Description of Upper Memory Map Tables 03h – 7Fh Vendor Speciﬁc Functions.............. 97
Description of Upper Memory Map Tables 80h – FFh Reserved........................................ 97

Chapter 6:
6.1

XFP MSA

August 31, 2005

Mechanical and Board definition......................................................... 98

Introduction ......................................................................................................................... 98

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REVISON 4.5

6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10

XFP Datums and Component Alignment............................................................................ 99
XFP Transceiver Package Dimensions ............................................................................. 101
Mating of XFP Transceiver PCB to XFP Electrical Connector .......................................... 103
Host Board Layout ............................................................................................................ 106
Insertion, Extraction and Retention Forces for XFP Transceivers .................................... 107
Color Coding and Labeling of XFP Transceivers .............................................................. 108
Bezel and EMI Gasket Design for Systems Using XFP Transceivers............................... 109
XFP Connector Mechanical Speciﬁcations....................................................................... 111
XFP Cage Assembly Dimensions..................................................................................... 113
6.10.1
6.10.26.10.36.10.4

6.11
6.12
6.13
6.14

August 31, 2005

XFP Cage Housing .........................................................................................................113
XFP Cage Rear EMI Gaskets.........................................................................................114
6.10.2.1XFP Upper Rear EMI Gasket ............................................................................114
6.10.2.2Lower Rear EMI Gasket ....................................................................................114
6.10.2.3XFP Intermediate Rear Cage EMI Gasket (Finger Stock) .................................114
XFP Cage Front Cage EMI Gasket (Finger Stock) .........................................................114
XFP Front Flange ...........................................................................................................115

XFP Heat Sink Clip Dimensions ....................................................................................... 117
An Example XFP Heat Sink.............................................................................................. 118
Environmental and Thermal.............................................................................................. 119
Dust/EMI Cover ................................................................................................................ 119

Appendix A: Application Reference Model
A.1
A.2
A.3
A.4

A.5

............................................................. 120

ASIC/SerDes Compliance Testing........................................................................ 120
Host System Compliance Testing......................................................................... 121
XFP Module Compliance Testing ......................................................................... 121
HOST SYSTEM COMPLIANCE TEST BOARD ................................................... 123
A.4.1 Host System Compliance Board Material and Layer Stack-up ................. 123
A.4.2 Host System Compliance Test Board Partlist............................................ 124
A.4.3 Schematic of Host System Compliance Test Board.................................. 125
A.4.4 Gerber ﬁle and S parameter measurements............................................. 126
XFP MODULE COMPLIANCE TEST BOARD ..................................................... 126
A.5.1 XFP Module Board Material and Layer Stack-up ...................................... 127
A.5.2 XFP Module Compliance Board Partlist.................................................... 128
A.5.3 Schematic of the XFP Compliance Test Board ......................................... 129
A.5.4 Gerber ﬁles and Measured S-Parameters................................................. 130

Appendix B: XFI Channel Measurements and Modeling
B.1
B.2
B.3

XFP MSA....................................... 131

System Overview ................................................................................................. 131
Design Guideline .................................................................................................. 133
Using System Simulation for Channel Modeling .................................................. 133

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REVISON 4.5

August 31, 2005

Appendix C: Differential S-Parameters and TDR
C.1
C.2
C.3
C.4

Choosing S-Parameters vs TDR .......................................................................... 137
Differential Impedance ......................................................................................... 138
4 Port Single-Ended S-Parameter Deﬁnition ........................................................ 139
2 Port Mixed Mode Differential S-Parameter Deﬁnition ........................................ 139

Appendix D: Optimum Via Design
D.1
D.2
D.3
D.4

.................................................... 137........................................................................... 142

Vias ...................................................................................................................... 142
Single-ended Vias ................................................................................................ 142
Differential Vias .................................................................................................... 144
GSSG Differential Vias ......................................................................................... 146

Appendix E: Jitter Methodology and Measurement
E.1
E.2
E.3

E.4
E.5
E.6
E.7

Eye Mask Compliance.......................................................................................... 149
Non-EQJ Jitter Eye Mask ..................................................................................... 151
Stress Eye Test for RX Tolerance Testing ............................................................ 152
E.3.1 Introduction ............................................................................................... 152
E.3.2 Test equipment.......................................................................................... 152
E.3.3 Types of jitter ............................................................................................. 152
E.3.4 Calibration ................................................................................................. 153
E.3.5 Testing....................................................................................................... 154
Jitter Peaking Speciﬁcations and Measurements................................................. 154
AC Common Mode Test ....................................................................................... 156
Termination Mismatch .......................................................................................... 157
Power supply noise testing methodology ............................................................. 158
E.7.1 Power Supply Noise compliance ............................................................... 158
E.7.2 Power Supply Noise Methodology ............................................................ 158
E.7.3 Power Supply Noise Methodology ............................................................ 158

Appendix F: XFI Implementation for BER 1E-15
F.1

XFP MSA.......... 160

XFI Electrical Implementation for BER 1E-15 ...................................................... 160
F.1.1 XFI ASIC/SerDes Transmitter Output Jitter Speciﬁcations at A for BER 1E-15
161
F.1.2 XFI ASIC/SerDes Receiver Input Jitter Speciﬁcations at D for BER 1E-15161
F.1.3 XFI Host Transmitter Output Jitter Speciﬁcations at B for BER 1E-15 ...... 162
F.1.4 XFI Host Receiver Input Jitter Speciﬁcations at C for BER 1E-15 ............ 162
F.1.5 FI Module Transmitter Input Jitter Speciﬁcations at B’ for BER 1E-15 ...... 163
F.1.6 XFI Module Receiver Output Jitter Speciﬁcations at C’ for BER 1E-15 .... 163

Appendix G: Module Thermal Testing
G.1............................................... 149..................................................................... 164

Module Thermal Power Classes........................................................................... 164

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REVISON 4.5

G.2
G.3

XFP MSA

August 31, 2005

Thermal Test Recommendation ........................................................................... 164
Thermal Test Conﬁguration .................................................................................. 165

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REVISON 4.5

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XFP List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36

XFP MSA

Module Electrical Pin Deﬁnition ...................................................................................5
Low speed control and sense signals, electronic characteristics....................................9
Timing Parameters for XFP Management ...................................................................10XFP Power Supply.......................................................................................................14
XFI Supported Data Rates ...........................................................................................16
XFI Loss Budget ..........................................................................................................19
Host Board Conﬁguration ............................................................................................21
XFI ASIC/SerDes Transmitter Output Electrical Speciﬁcations at A .........................22
XFI ASIC/SerDes Transmitter Output Jitter Speciﬁcations at A ................................22
XFI ASIC/SerDes Receiver Electrical Input Speciﬁcations at D ................................24
XFI ASIC/SerDes Receiver Input Jitter Speciﬁcations at D........................................24
XFI Host Transmitter Output Electrical Speciﬁcations at B.......................................27
XFI Host Transmitter Output Jitter Speciﬁcations at B...............................................27
XFI Host Receiver Input Electrical Speciﬁcations at C...............................................29
XFI Host Receiver Input Jitter Speciﬁcations at C ......................................................29
XFI Module Transmitter Input Electrical Speciﬁcations at B’ ....................................33
XFI Module Transmitter Input Jitter Speciﬁcations at B’ ...........................................33
XFI Module Receiver Output Electrical Speciﬁcations at C’......................................36
XFI Module Receiver Output Jitter Speciﬁcations at C’ .............................................36
XFP Telecom Module Transmitter Requirement.........................................................38
XFP Telecom Module Receiver Requirement .............................................................39
XFP Datacom Module Transmitter Requirement ........................................................39
XFP Datacom Module Receiver Requirement.............................................................39
Reference Clock Speciﬁcations ...................................................................................40
Optional Reference Clock Speciﬁcations ....................................................................41
XFP 2-Wire Timing Speciﬁcations ..............................................................................43
XFP Memory Speciﬁcations ........................................................................................44
Single Byte Writable Memory Blocks.........................................................................44
Multiple Byte Writable Memory Blocks .....................................................................44
XFP Device Address....................................................................................................46
Lower Memory Map ....................................................................................................58
Identiﬁer values Byte 128 ............................................................................................59
VPS Fields ...................................................................................................................65
Signal Conditioner Control Field.................................................................................71
Alarm and Warning Thresholds ...................................................................................72
BER Control Fields......................................................................................................73

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REVISON 4.5

Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74

XFP MSA

August 31, 2005

Wavelength Control Fields...........................................................................................73
FEC Control Fields ......................................................................................................73
Latched Interrupt Flag Fields.......................................................................................74
Interrupt Masking Bits .................................................................................................76
A/D Values ...................................................................................................................78
General Control/Status Bits .........................................................................................79
Packet Error Checking .................................................................................................80
Password and Table Select Entry Bytes .......................................................................80
I/O Timing for Soft Control & Status Functions .........................................................80
Serial ID: Data Fields - Page 01h ................................................................................81
Extended Identiﬁer values Byte 129 ............................................................................83
Connector values Byte 130 ..........................................................................................84
Transceiver codes.........................................................................................................85
Encoding Support Byte 139 .........................................................................................86
Device Technology (Value of lower 4 bits of Byte 147)..............................................89
Transmitter Technology (Value of top 4 bits of Byte 147) ..........................................89
CDR Support Byte 164 ................................................................................................90
Power Supply Related Fields .......................................................................................93
Date Code.....................................................................................................................94
Diagnostic Monitoring Type ........................................................................................95
Enhanced Options ........................................................................................................95
Auxiliary A/D Types Byte 222 ....................................................................................96
Auxiliary Input Types ..................................................................................................96Deﬁnition of Datums....................................................................................................99
Insertion, Extraction, and Retention Forces...............................................................108
Host System Compliance Test Board Part List..........................................................124
XFP Module Compliance Test Board Part List .........................................................128
Optimized differential via geometry for 100 mil and 62 mil thick PCB ...................145
Four alternative GSSG via dimension........................................................................147
Noise Amplitude for XFP power supplies (Nominal) ...............................................159
Host Board Interconnect for BER 1E-15 ...................................................................160
XFI ASIC/SerDes Transmitter Output Jitter Speciﬁcations at A for BER 1E-15 .....161
XFI ASIC/SerDes Receiver Input Jitter Speciﬁcations at D for BER 1E-15 ............161
XFI Host Transmitter Output Jitter Speciﬁcations at B for BER 1E-15....................162
XFI Host Receiver Input Jitter Speciﬁcations at C ....................................................162
XFI Module Transmitter Input Jitter Speciﬁcations at B’ for BER 1E-15’...............163
XFI Module Receiver Output Jitter Speciﬁcations at C’ for BER 1E-15..................163
Environmental Test Conditions..................................................................................166

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REVISON 4.5

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XFP List Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41

XFP MSA

Host PCB XFP Pinout Top View .................................................................................4Power Noise Requirement ..........................................................................................12
Example of Host Board Supply Filtering Network.....................................................13
Application Reference Model .....................................................................................17
XFI Termination and AC Coupling ............................................................................18
Channel Transfer Model .............................................................................................20
XFI ASIC/SerDes Transmitter Differential Output Compliance Mask at A..............23
XFI ASIC/SerDes Receiver Differential Input Compliance Mask.............................25
XFI ASIC/SerDes Receiver Input Telecom Sinuosidal Jitter Tolerance....................25
XFI ASIC/SerDes Receiver Input Datacom Sinuosidal Jitter Tolerance ...................26
XFI Host Transmitter Differential Output Compliance Mask at B ............................28
XFI Host Receiver Differential Input Compliance Mask at C ...................................30
XFI Host Receiver Telecom Input Sinuosidal Jitter Tolerance ..................................31
XFI Host Receiver Input Datacom Sinuosidal Jitter Tolerance..................................31
XFI Module Transmitter Differential Input Compliance Mask at B’.........................34
XFI Module Transmitter Input Telecom Sinuosidal Jitter Tolerance.........................34
XFI Module Transmitter Input Datacom Margin Mask .............................................35
XFI Module Receiver Differential Output Compliance Mask at C’...........................37
XFP Timing Diagram ................................................................................................42
XFP Current Address Read Operation........................................................................47
XFP Random Read .....................................................................................................49
Sequential Address Read Starting at XFP Current Address .......................................49
Sequential Address Read Starting with Random XFP Read ......................................50
XFP Read Operation Packet Error Checking..............................................................51
XFP Write Byte Operation..........................................................................................52
XFP Sequential Write Operation ................................................................................52
XFP Write Operation Packet Error Checking.............................................................53
2-wire Serial Digital Diagnostic Memory Map ..........................................................56
XFP Mechanical Components ....................................................................................98
XFP Datum Alignment, Depth .................................................................................100
Drawing of XFP Transceiver, Part 1.........................................................................101
Drawing of XFP Transceiver, Part 2.........................................................................102
Recommended Pattern Layout for XFP Printed Circuit ...........................................104
XFP Transceiver Electrical Pad Layout....................................................................105
XFP Host Board Mechanical Layout........................................................................106
XFP Detail Host Board Mechanical Layout, Detail Z..............................................107
Recommended Single Sided Bezel Design...............................................................110
Recommended Double Side Mounting Bezel Design ..............................................111
XFP Transceiver Connector Illustration ...................................................................112
XFP Cage Components.............................................................................................113
XFP Cage Assembly .................................................................................................116

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REVISON 4.5

Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73

XFP MSA

August 31, 2005

XFP Heat Sink Clip ..................................................................................................117
XFP Heat Sink ..........................................................................................................118
Dust/EMI Cover........................................................................................................119
ASIC/SerDes Compliance Test Board......................................................................120
Host System Compliance Test Diagram ...................................................................121
XFP Module Compliance Test Diagram...................................................................122
Host System compliance Test Board ........................................................................123
Schematic of Host System Compliance Test Board .................................................125
XFP Module Compliance test Board ........................................................................126
Schematic of the XFP Compliance Test Board ........................................................129
XFI Electrical Channel Definition ............................................................................131
PCB Board Stack up .................................................................................................132
System model for the XFI Channel. .........................................................................134
Comparison of simulated and measured differential s11..........................................135
Comparison of simulated and measured differential s21..........................................135
Measured and simulated eye diagram for the XFP channel ....................................136
4 Port DUT................................................................................................................139
Differential 2 Port DUT ............................................................................................139
Single-ended via with electrical path between adjacent layers leaves an open-circuit stubcausing poor impedance match..................................................................................143
Preferred method for trace routing with vias. Routing the electrical path from the top layer
to a layer near or on the opposite side of the board minimizes the open-circuited stub.143
Simulated return loss (s11)) ......................................................................................144
Differential via geometry a 100mil multilayer PCB.................................................145
S-parameters for optimized via structures with dimensions given in Table 1. (a) 100 mil thick
PCB. (B.) 62 mil thick board. ....................................................................................146
GSSG via structure ...................................................................................................147
Extracted s-parameters for the four alternative GSSG via........................................148
Eye Template Alignment ..........................................................................................150
Eye mask measurement setup - block diagram.........................................................150
Eye mask measurement setup - block diagram.........................................................151
AC Termination Mismatch Measurement ................................................................157
Power Supply Ripple Setup ......................................................................................159
Airflow vs Inlet Air Temperature .............................................................................166
Heat Sink Drawing for Module Thermal Testing .....................................................167

Page xxiv

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REVISON 4.5

Scope of XFP speciﬁcation

August 31, 2005

1
2
3
4
5
6
This speciﬁcation deﬁnes the electrical, management, and mechanical in- 7
terfaces of the XFP module. The module is a hot pluggable small footprint 8
serial-to-serial data-agnostic multirate optical transceiver, intended to9
support Telecom (SONET OC-192 and G.709 “OTU-2”) and Datacom applications (10 Gb/s Ethernet and 10 Gb/s Fibre Channel). Nominal data 10
rates range from 9.95 Gb/s, 10.31 Gb/s, 10.52 Gb/s, 10.70 Gb/s, and the 11
emerging 11.09 Gb/s. The modules support all data encodings for these 12
technologies. The modules may be used to implement single mode or13
multi-mode serial optical interfaces at 850 nm, 1310 nm, or 1550 nm. The 14
XFP module design may use one of several different optical connectors
15
5.17. An adaptable heatsink option allows a single module design to be16
compatible with a variety of hosts.
17
18
The XFP speciﬁcation includes the following information:
19• XFP reference model and description 3.2
20
Chapter 2: XFP Electrical Interface , Low Speed Electrical Interface 21•
22• Chapter 3: High Speed Electrical Speciﬁcation XFI , High speed 10
23
Gb/s serial electrical speciﬁcation (XFI)• Chapter 4: XFP 2-Wire Interface Protocol , XFP 2-Wire Interface Pro- 24
25
tocol• Chapter 5: Management interface , Management and diagnostic in- 26
27
terface28
Chapter 6: Mechanical and Board deﬁnition , Mechanical interface,•
including guides, EMI shields, module retention, cooling, and electri- 29
30
cal connector.
31• Appendixes providing implementation and measurement sugges32
tions.
33• Appendix A: Application Reference Model
34• Appendix B: XFI Channel Measurements and Modeling35• Appendix C: Differential S-Parameters and TDR
36
37• Appendix D: Optimum Via Design
38• Appendix E: Jitter Methodology and Measurement
39• Appendix G: Module Thermal Testing
40
41
42

CHAPTER 1: SCOPE OF XFP SPECIFICATION

1.1 INTRODUCTIONXFP MSA

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REVISON 4.5

Scope of XFP speciﬁcation

August 31, 2005

1.2 REQUIREMENTS ON PRESS ANNOUNCEMENTS

1
All press announcements specifying XFP compliant modules and compo- 2
nents shall include the following text to identify the origin of the XFP spec- 3
iﬁcation.
4
5
The XFP is a development activity promoted by Broadcom Corporation, 6
Brocade Communications Systems, Inc., Emulex Corporation, Finisar
7
Corporation, JDS Uniphase Corporation, Innovation Core SEI, Inc.,
Maxim Integrated Products, Ciena Corporation, Tyco Electronics Corpo- 8
9ration, Velio Communication, and many contributors.
10
11
12
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

1
2
3
4
5
2.1 INTRODUCTION
6The XFI “Ziffy” is the high speed serial electrical interface for XFP mod- 7
ules with a nominal baudrate of 9.95-11.1 Gb/s. XFI connects a serial
89.95-11.1 Gb/s SerDes to a module over 300mm of improved FR41 mate- 9
rial or up to 200mm of standard FR4 with one connector. The electrical in10
terface is based on high speed low voltage AC coupled logic with a11nominal differential impedance of 100 Ω. The XFP module could be an
12Electrical-to-Optical or an Electrical-to-Electrical device.
13
The XFP modules and the host system are hot-pluggable. The module or 14
the host system shall not be damaged by unexpected insertion or removal 15of the module.
16
17
18
19
2.2 GENERAL REQUIREMENTS
20
All electrical speciﬁcations shall be met over the entire speciﬁed range of21
power supplies given in section 2.7.
22
All XFP electrical speciﬁcations apply over the Environmental and
23
Thermal range described in section 6.13. If an extended operating range 24
is speciﬁed by the module vendor (see 5.35), then the electrical speciﬁca- 25
tions apply over this extended operating range.
26
27
28
29
2.3 XFP HOST CONNECTOR DEFINITION
30
The XFP host connector is based on a 0.8 mm pitch 30 position rightangle connector 6.9. Host PCB pin assignment is given by Figure 1 and 31
pin deﬁnition are listed in Table 1. All XFP compliance points are deﬁned 32
using this connector. An improved version of this connector will be avail- 33
able from Tyco and possibly from other sources. It is recommended that 34
host systems use the new improved connector for better signal integrity 35
and EMI.
36
37
38
39
40
1. Standard FR4 has a typical loss tangent of 0.022, where improved FR4 such 41
as Nelco 4000-13 has a typical loss tangent of 0.016.
42

CHAPTER 2: XFP ELECTRICAL INTERFACEXFP MSA

Page 3Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

16
17
18
19

TOWARD
ASIC

August 31, 2005

GND

15

RX_LOS

14

MOD_NR

13

MOD_ABS

12

SDA

11

SCL

10

VCC3

9

VCC3

8

GND

7

VCC5

6

TX_DIS

5

INTERRUPT

4

MOD_DESEL

3

VEE5

2

GND

1

GND
RDRD+
GND

20

VCC2

21

P_DOWN/RST

22

VCC2

23
24
25
26
27
28
29
30

GND

TOWARDBEZELREFCLK+REFCLKGND
GND
TDTD+
GND

Figure 1 Host PCB XFP Pinout Top View

XFP MSA

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XFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

Table 1 Module Electrical Pin Deﬁnition
Pin

Logic

SymbolName/Description

1

GND

Module Ground

2

VEE5

Optional -5.2V Power Supply

Note
1

3

LVTTL-I

Mod_DeSel

Module De-select; When held low allows module to respond to 2-wire serial interface

4

LVTTL-O

Interrupt

Interrupt; Indicates presence of an important condition which can be read over the 2-wireserial interface

5

LVTTL-I

TX_DISTransmitter Disable; Turns off transmitter laser output

6

VCC5

+5V Power Supply

7

GND

Module Ground

8

VCC3

+3.3V Power Supply

9

VCC3

+3.3V Power Supply

2

1

10

LVTTL-I/O

SCL

2-Wire Serial Interface Clock2

11

LVTTL-I/O

SDA

2-Wire Serial Interface Data Line

2

12

LVTTL-O

Mod_Abs

Indicates Module is not present. Grounded in the Module

2

13

LVTTL-O

Mod_NR

Module Not Ready; Indicating Module Operational Fault

2

14

LVTTL-O

RX_LOS

Receiver Loss Of Signal Indicator

2

15

GND

Module Ground

1

16

GND

Module Ground

1

17

CML-O

RD-

Receiver Inverted Data Output

18

CML-O

RD+

Receiver Non-Inverted Data Output

19

GND

Module Ground

1

20

VCC2

+1.8V Power Supply

3

P_Down/RSTPower down; When high, requires the module to limit power consumption to 1.5W or
below. 2-Wire serial interface must be functional in the low power mode.

21

LVTTL-I

Reset; The falling edge initiates a complete reset of the module including the 2-wireserial interface, equivalent to a power cycle.
22

VCC2

+1.8V Power Supply

3

23

GND

Module Ground

1

24

PECL-I

RefCLK+

Reference Clock Non-Inverted Input, AC coupled on the host board

25

PECL-I

RefCLK-

Reference Clock Inverted Input, AC coupled on the host board

26

GND

Module Ground

1

27

GND

Module Ground

1

28

CML-I

TD-

Transmitter Inverted Data Input

29

CML-I

TD+

Transmitter Non-Inverted Data Input

GND

Module Ground30

1

1. Module ground pins Gnd are isolated from the module case and chassis ground within the module.
2. Shall be pulled up with 4.7K-10Kohms to a voltage between 3.15V and 3.45V on the host board.
3. The 1.8 V power supply can be optionally programmed to voltages lower than 1.8 V in modules supporting the variable power supply.

XFP MSA

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XFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

2.4 LOW SPEED ELECTRICAL HARDWARE PINS

2.4.1 MOD_NR

2.4.2 MOD_DESELXFP MSA1
In addition to the 2-wire serial interface the XFP module has the following 2
3
low speed pins for control and status:
4• Mod_NR
56• Mod_DeSel
7• Interrupt
8• TX_DIS
9• Mod_ABS
10• RX_Los
11
12• P_Down/RST.
13
14
15
The Mod_NR is an output pin that when High, indicates that the module 16
has detected a condition that renders transmitter and or receiver data in- 17
valid, shall consist of logical OR of the following signals:
18
19• Transmit Signal Conditioner Loss of Lock20
• Transmitter Laser Fault
21
22• Receiver Signal Conditioner Loss of Lock
Other conditions deemed valuable to the detection of fault may be added 23
24
to the Mod_NR.
25
The Mod_NR output pin is an open collector and must be pulled to26
Host_Vcc on the host board.
27
28
29
The Mod_DeSel is an input pin. When held Low by the host, the module30
responds to 2-wire serial communication commands. The Mod_DeSel al31
lows the use of multiple XFP modules on a single 2-wire interface bus.
When the Mod_DeSel pin is “High”, the module shall not respond to or ac- 32
knowledge any 2-wire interface communication from the host. Mod_DeSel 33
pin must be pulled to VCC3 in the module.
34
35
In order to avoid conﬂicts, the host system shall not attempt 2-wire inter- 36
face communications within the Mod_DeSel assert time after any XFP
37
modules are deselected. Similarly, the host must wait at least for the pe38
riod of the Mod_DeSel deassert time before communicating with the39
newly selected module. The assertion and de-assertion periods of different modules may overlap as long as the above timing requirements are 40
met.
41
42
Page 6

Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

2.4.3 INTERRUPT

1Interrupt is an output pin. When “Low”, indicates possible module opera- 2
tional fault or a status critical to the host system. The Interrupt pin is an 3
open collector output and must be pulled up to Host_Vcc the host board. 4
5
2.4.4 TX_DIS
6
TX_DIS is an input pin. When TX_DIS is asserted High, the XFP module 7transmitter output must be turned off. The TX_DIS pin must be pulled up 8
to VCC3 in the XFP module.
910
2.4.5 MOD_ABS
11
Mod_ABS is pulled up to Host_Vcc on the host board and grounded in the
12
XFP module. Mod_ABS is then asserted “High” when the XFP module is13
physically absent from a host slot.
14
15
2.4.6 RX_LOS
16
The RX_LOS when High indicates insufﬁcient optical power for reliable
signal reception. The RX_LOS pin is an open collector output and must 17
be pulled up to Host_Vcc on the host board.
18
19
2.4.7 P_DOWN/RST20This is a multifunction pin for module Power Down and Reset. The
21
P_Down/RST pin must be pulled up to VCC3 in the XFP module.
22
23
24
25
2.4.7.1 POWER DOWN FUNCTION
The P_Down pin, when held High by the host, places the module in the 26
standby (Low Power) mode with a maximum power dissipation of 1.5W. 27
This protects hosts which are not capable of cooling higher power mod- 28
ules which may be accidentally inserted.
29
30
The module’s 2-wire serial interface and all laser safety functions must be 31
fully functional in this low power mode. During P_Down, the module shall32
still support the completion of reset Interrupt, as well as maintain function33
ality of the variable power supply as described in section 5.7.
34
35
36
2.4.7.2 RESET FUNCTION37
The negative edge of P_Down/RST signal initiates a complete module
38
reset.
39
40
41
42
XFP MSA

Page 7

Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

2.4.7.3 MODULE BEHAVIOR DURING POWER DOWN AND RESET

1During execution of a reset (t_init) or while held in Power Down mode, a 2
3
module may be unable to determine the correct value for Mod_NR and
RX_LOS. These outputs as well as all interrupt related ﬂags, except com- 4
pletion of Reset ﬂag, shall be disregarded by the host. When the module 5
completes a Reset and is not in Power Down mode, the module must rep6
resent the correct value of both signals on its outputs before posting acompletion of reset interrupt to the host (see Table 39, bit 0 register ad- 7
8dress 84).
9
At no time shall a module cause spurious assertion of the Interrupt pin. 10
11
When a host initially applies power to a module with the P_Down/RST
12signal asserted, a module comes up in power down mode. The module
13
shall only assert the Interrupt signal pin to inform the host it has completed
a reset. The completion of reset ﬂag (see Table 39, bit 0 register address 1484) shall be the only interrupt source ﬂag set during power down mode. 15
16
The host is expected to clear this interrupt before releasing the modulefrom the power down mode. The transition from power down mode to17normal mode will trigger a reset of the module and result in a 2nd module 18
reset and a 2nd reset completion interrupt to the host
19
20
21
22
23
24
25
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34
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37
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39
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

2.5 LOW SPEED ELECTRICAL SPECIFICATIONS

1
Low speed signaling is based on Low Voltage TTL (LVTTL) operating at 2
Vcc3 at a nominal supply of (3.3V ± 5%). Hosts shall use a pull-up resistor 3
connected to a host_Vcc of +3.3 volts (3.15 to 3.45 volts) on the 2-wire in- 4
terface SCL (clock), SDA (Data), and all low speed status outputs.
5
6
The XFP low speed electrical speciﬁcations are given in Table 2. This
7
speciﬁcation ensures compatibility between host bus masters and XFP
8
SCL/SDA lines and compatibility with I2C.
9
10
.
11
Table 2 Low speed control and sense signals, electronic characteristics
12
13
Parameter
Symbol
Min.
Max.
Unit
Conditions
14
VOL
0.0
0.40
V
Rpullup pulled to host_Vcc, measured at
15
host
side
of
connector.
I
(max)
=
3
mA
XFP Interrupt, Mod_NR,
OL
16
RX_LOS
host_Vcc - 0.5
host_Vcc + 0.3
V
Rpullup pulled to host_Vcc, measured at
VOH
17
host side of connector.
18
VIL
-0.3
0.8
V
Rpullup pulled to VCC3,measured at XFP
19side of connector. IIL(max) = -10 uA
XFP TX_Dis,20
P_Down/RST
2.0
VCC3 + 0.3
V
Rpullup pulled to VCC3, measured at XFP
VIH
21
side of connector. IIH(max) = 10 uA
22
0.0
0.40
V
Rpullup1 pulled to host_Vcc, measured atVOL23
host side of connector. IOL(max) = 3 mA
XFP SCL and SDA
24
host_Vcc - 0.5
host_Vcc + 0.3
V
Rpullup1 pulled to host_Vcc, measured at
VOH
25
host side of connector.
26
VIL
-0.3
Vcc3*0.3
V
Rpullup1 pulled to Host_VCC, measured at
27
XFP side of connector. IIL(max) = -10 uA
XFP SCL and SDA
28
Vcc3*0.7
VCC3 + 0.5
VRpullup1 pulled to Host_VCC, measured at
VIH
29
XFP side of connector. IIH(max) = 10 uA
30
Il
-10
10
µA
Leakage Current
31
Capacitance for XFP SCL
Ci
14pF
10pF for XFP IC I/O pin,32
and SDA I/O Pin
4 pF for XFP PCB trace
33
100
pF
At 400 KHz, 3.0 Kohms Rp, max
34
At 100 KHz, 8.0 Kohms Rp, max
Total bus capacitive load
Cb
35
for SCL and for SDA
400pF
At 400 KHz, 0.80 Kohms Rp, max
36
At 100 KHz, 2.0 Kohms Rp, max
37
1. For combinations of Rpullup (Rp), bus capacitance and speed, see Philips I2C speciﬁcation revision 2.1, ﬁgures 39 and 44. Rise and38
fall time measurement levels are deﬁned in the XFP management interface ac electrical speciﬁcations. Active bus termination may be
used by the host in place of a pullup resistor, as described in the Philips I2C speciﬁcation
39
40
41
42

XFP MSA

Page 9Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

2.6 TIMING REQUIREMENT OF CONTROL AND STATUS I/OParameter
TX_DIS
assert time
TX_DIS
negate time
Time to initialize

Interrupt assert delay

Interrupt negate delay
P_Down/RST assert delay
Mod_NR assert delay

Mod_NR negate delay

P-Down reset time
RX_LOS assert delay

RX_LOS negate delay

XFP MSA1
The timing requirements of control and status I/O are deﬁned inTable 3. 2
3Table 3 Timing Parameters for XFP Management
45
Symbol
Min.
Max.
Unit
Conditions
6
t_off
10
µsec
rising edge of TX_DIS to fall of output signal
7
below 10% of nominal
8
t_on
2
msec
Falling edge of TX_DIS to rise of output sig9
nal above 90% of nominal
10
t_init300
msec
From power on or hot plug after supply meet- 11
ing Table 4 or from falling edge of
12
P_Down/RST.
13Interrupt_on
200
msec
From occurrence of the condition triggering
14Interrupt
15Interrupt_off
500µsec
From clear on read Interrupt ﬂags
16
P_Down/RST_on
100µsec
From Power down initiation
1718
Mod_nr_on
1
msec
From Occurrence of fault to assertion of
MOD_NR
19
20
Mod_nr_off
1
msec
From clearance of signal to negation of
MOD_NR
21
22
10
µsec
Min length of P-Down assert to initiate reset23
t_loss_on
100µsec
From Occurrence of loss of signal to assertion
24of RX_LOS25
t_loss_off
100µsec
From Occurrence of presence of signal to26
negation of RX_LOS
27
The 2-wire serial bus timing is described in Chapter 4: XFP 2-Wire Inter- 28
face Protocol .
29
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REVISON 4.5

XFP Electrical Interface

August 31, 2005

2.7 XFP POWER REQUIREMENTThe XFP host has 3 power supplies +1.8 V, +3.3 V, +5.0 V and an optional-5.2 V supply. The +1.8 V and +3.3 V supplies have two designated power
pins in the connector for each power supply rail. The +5 V and -5.2 supplies have one designated power pin each. The maximum continuous or
peak current carrying capacity for each connector pin is 500 mA.
The host system may alter the VCC2 supply to a voltage level lower thatthe nominal +1.8 V value. This mode of operation is optional and can besupported by modules and hosts that strive to meet lower power/current
requirements. Modules supporting this optional lower power mode must
be backwards compatible with modules and hosts supporting only 1.8 V
on VCC2, i.e. modules implementing these optional modes must be able
to operate normally with a voltage of +1.8 V applied on their VCC2 pins(albeit with higher power dissipation). For more details see section 5.7.
XFP module maximum power dissipation must meet one of the followingclasses:•

Power Level 1 modules – Up to 1.5 W•

Power Level 2 modules – Up to 2.5 W•

Power Level 3 modules – Up to 3.5 W•

Power Level 4 modules – Greater than 3.5 W

To avoid exceeding system power supply limits and cooling capacity, themodule may be placed in the power down mode by pulling pin 21 High.
This guarantees module operating in Low Power mode with maximum
power dissipation of ≤ 1.5W.
A host board together with XFP module(s) forms an integrated powersystem. The host supplies stable power to the module. The module limits
electrical noise coupled back into the host and limits inrush charge/current
during hot plug insertion.
All speciﬁcations shall be met at the maximum power supply current. No
power sequencing of the power supplies is required of the host system.

2.7.1 POWER NOISE OUTPUT
To limit wide band noise power, the host system and module shall eachmeet a maximum of 2% peak-peak noise when measured with a 1MHz
low pass ﬁlter. In addition, the host system and the module shall eachmeet a maximum of 3% peak-peak noise when measured with a highpass ﬁlter from 1MHz-10 MHz.

XFP MSA

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XFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

1
2
3
4
5
6
7
The XFP module is tested with a high quality power supply connected
through the sample ﬁlter Figure 3. Voltage is measured at the host side of 8
the XFP connector, between the sample host ﬁlter network and the XFP. 9
The module must pass this test in all operating modes. This test ensures 10
the module will not couple excessive noise from inside the module back11
onto the host board.
12
13
14
2.7.2 POWER NOISE SUSCEPTIBILITY
15
A module will meet all electrical requirements and remain fully operational 16
in the presence of noise on all voltage inputs. The recommended suscep- 17
tibility test is to sweep a sinuosidal waveform on each voltage input, with 18
peak amplitude as described in Figure 2. This test applies at minimum
19
and maximum DC setpoint levels. It is also desirable for a module and20
host to each tolerate a degree of random or semi-random noise on allvoltage pins simultaneously, but the characteristics of this noise are be- 21
22yond the scope of this document.
23
24
25
5
26
27
4
28
29
30
3
31
32
2
33
34
1
35
36
37
38
1.0
10000.0
1000.0
100.0
10.0
39
Frequency (KHz)
40
Figure 2 Power Noise Requirement
4142
Noise as a% of VCC/VEE (peak-peak)

The XFP port on a host board is tested with a resistive load in place of the
XFP module, each voltage rail at maximum current supported by the host.
Voltage is measured at the module side of the XFP connector. The test is
performed with all other portions of the host board/system active. Hosts
with multiple XFP modules shall test ports one at a time, with active XFPs
in all the remaining ports.

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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

1
2
3
2.7.3 HOST FILTERING
4
The example host board power supply ﬁltering shown in Figure 3 will5
meet the noise ﬁltering requirements in most systems. Other ﬁltering
6
implementations or local regulation may be used to meet the power noise
7
output requirements described in section 2.7.1.
8
Any voltage drop across a ﬁlter network on the host is counted against9
the Host DC setpoint accuracy speciﬁcation in Table 4. For this reason, 10
the example ﬁlter illustrated in Figure 3 may not be appropriate for a host11
powering multiple XFPs and/or other host components from a shared
12
voltage supply.
13
14
15
16
17
Host Board
18
Host +5V
4.7uH
VCC5
19
20
22uf
0.1uf
0.1 uf21
22
Host +3.3V
4.7uH
VCC3
23
0.1uf
24
22uf
0.1 uf
XFP Module25
4.7uH
Host +1.8V
VCC2
26
27
22uf
0.1uf
0.1 uf28
29
Optional Host -5.2V 4.7uH
VEE5
30
22uf
0.1uf
0.1 uf
31
32
33
Figure 3 Example of Host Board Supply Filtering Network
34
35
36
37
38
39
40
41
42
XFP Connector

For power supply noise susceptibility testing and methodology see E.7.

XFP MSA

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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP Electrical Interface

August 31, 2005

Table 4 XFP Power Supply
Parameters

SymbolConditions

Min

Max

Units

VCC5 (5V)/VEE5 (-5.2V) Pin
Power Supply Noise including Ripple [peak-to-peak]

VCC5/VEE5

see 2.7.1

Host DC set point accuracy

%
-5

+5

%

Module Maximum Current Inrush

Note 10.5

AModule current ramp rate

Note 1

100

mA/µs

2.5

W

0.25

W

Maximum Power for the +5 and -5.2V Rail
Maximum Power for the +5 and -5.2V Rail During Power Down

Note 2

Host Bulk bypass capacitance for the module

Note 322

uF

VCC3 (3.3V) RailPower Supply Noise including Ripple [peak-to-peak]VCC3

see 2.7.1

Host DC set point accuracy

%
-5

+5

%

Module Maximum Current Inrush

Note 10.75

AModule current ramp rate

Note 1

100

mA/µs

2.5

W

1

W

Maximum Power for the +3.3V Rail
Maximum Power for the +3.3V Rail During Power Down

Note 2

Host Bulk bypass capacitance for the module

Note 322

uF

VCC2 (1.8V) RailPower Supply Noise including Ripple [peak-to-peak]VCC2

see 4, 2.7.1

Host DC set point accuracy

%
-5

+5

%

Module Maximum Current Inrush

Note 1

1A

Module current ramp rate

Note 1

100

mA/µs

1.8

W

1

W

Maximum Power for the 1.8V Rail
Maximum Power for the 1.8V Rail During Power Down

Note 2

Host Bulk bypass capacitance for the module

Note 322

uF

1. Modules which present a small capacitive load to the host during hotplug ( C ≤ 300nF ) are exempt from the inrush current requirements
since they limit the total in rush charge.
2. Maximum module power dissipation shall not exceed 1.5 W.
3. Host provides bulk capacitance to suppress low frequency noise inside the XFP module. Host and module must each implement appropriate high frequency bypass to independently meet the noise requirement deﬁned in section 2.7.1.
4. VCC2 can be optionally programmed to voltages less than 1.8V in modules supporting the Variable Power Supply 5.7.

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XFP Speciﬁcation
REVISON 4.5

2.8 ESDXFP MSAXFP Electrical Interface

August 31, 2005

1
The XFP module and host XFI pins (High Speed Pins) shall withstand 500 2
3
V electrostatic discharge based on Human Body Model per JEDECJESD22-A114-B.
4
5
The XFP module and all host pins with exception of the XFI pins (High6
Speed Pins) shall withstand 2KV electrostatic discharge based on Human
7
Body Model per JEDEC JESD22-A114-B.
8
The XFP module shall meet ESD requirement given in EN61000-4-2, cri- 9
terion B test speciﬁcation such that units are subjected to 15KV air dis- 10
charges during operation and 8KV direct contact discharges to the case. 11
12
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

1
2
3
4
5
3.1 INTRODUCTION
6
XFI signaling is based on high speed low voltage logic, with nominal 100 7
Ohms differential impedance and AC coupled in the module. XFI was de- 8
veloped with the primary goal of low power and low Electro-Magnetic-In9
terference (EMI). To satisfy this requirement the nominal differential signal
10levels are 500 mV p-p with edge speed control to reduce EMI.
11
12
3.2 XFI APPLICATIONS DEFINITION
13
The application reference model for XFI, which connects a high speed
ASIC/SERDES to the XFP module is shown in Figure 4. The XFI interface 14
is designed to support SONET OC-192, IEEE.Std-802.3ae, 10GFC and 15
G.709(OTU-2) applications. The SERDES is required to meet the applica- 16
tion requirements for jitter generation and transfer when interfaced with a 17
compliant XFP module through an XFP compliant channel. Modules or18
hosts designed only for 10 Gigabit Ethernet or 10GFC are not required to19meet more stringent Telecom jitter requirements. XFI supported data
rates are listed in Table 5. XFP compliant module are not required to sup- 20
21
port all the rates listed in Table 5 in simultaneously.
22
23
24
Table 5 XFI Supported Data Rates
25
Standard
Description
Nominal Bit Rate
Units
26
27
OC-192/SDH-64
SONET
9.95
Gigabaud
28
IEEE std-802.3ae
10 Gb/s Ethernet LAN PHY
10.31
Gigabaud
29
INCITS/T11 Project 1413-D
10GFC
10.52
Gigabaud30
ITU G.709(OTU-2)
OC-192 Over FEC
10.70
Gigabaud
31
32
Emerging
10Gb/s Ethernet Over G.709
11.09
Gigabaud
33
34
35
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39
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CHAPTER 3: HIGH SPEED ELECTRICAL SPECIFICATION XFIXFP MSA

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REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

1
2
3
4
Connector
5
XFP Module
D
C’ C
6
*
7
RX
8
DriverCaps
ASIC/SerDes
9
*
10
TX
11
B’
A
B
12
* Signal Conditioner
13
14
Host Board
15
Figure 4 Application Reference Model
16
17
18
XFI Compliance points are deﬁned as the following:
19• A: SerDes transmitter output at ASIC/SerDes package pin on a DUT 20
board 3.6 and A.1
21• B: Host system SerDes output across the host board and connector 22
at the Host Compliance Test Card 3.7.1 and A.2
23• B’: XFP transmitter input across the Module Compliance Test Board 24
25
3.8.1 and A.3.
26
• C: Host system input at the Host Compliance Test Card input 3.7.2
27
and A.2
28• C’: XFP module output across the Module Compliance Test Board
29
3.8.2 and A.3.
30
• D: ASIC/SerDes input package pin on the DUT board 3.6.2 and A.1.
31
ASIC/SerDes compliance points are informative.
32
33
34
35
3.3 XFI TERMINATION AND DC BLOCKINGThe XFI link requires nominal 100 Ω differential source and load termina- 36
tions on both the host board and the module. The XFI terminations shall 37
provide both differential and common mode termination to effectively ab- 38
sorb differential and common mode noise and reﬂections as described: 39
40
41
42
XFP MSA

Page 17

Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIASIC/SerDes – Table 8 and Table 1012• Host – Table 12 and Table 143• Module – Table 17 and Table 18.
4
All XFI transmitters and receivers are AC coupled. XFP modules shall in5
corporate blocking capacitors on all XFI lines as shown in Figure 5. Resistor Rp and Rn each have a nominal 50 Ω value, together forming 100 Ω 6
differential input. Some implementation may also use a resistor Rt from 7
8
the common point to the termination voltage.
9
XFI differential reference impedance for driver, transmission line, and re- 10
ceivers are deﬁned as 100 Ohms. XFI common mode reference imped- 11
ance for driver, transmission lines, and receivers are speciﬁed as 25
12
Ohms.
13
14
15
16
17
HOST BOARD
18
ASIC/SerDes
XFP Module
19
XFI Transmitter
20
XFI Receiver21
Rp
Capacitor
22
Rt
23
Rp
C’ C
D
Rn
24
Rn
25
Capacitor
26
XFI Receiver27
XFI Transmitter
28
Capacitor
Rp
29
Rt
Rp
30
A
B’ B
Rn
31
Rn
Capacitor
32
Capacitor
33
Reference Clock34
35
XFI CONNECTOR
36
37
Figure 5 XFI Termination and AC Coupling
38
39
40
41
42
Rt

Rt

•

August 31, 2005

XFP MSA

Page 18

Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

3.4 XFI JITTER DEFINITIONS

1The XFI total jitter (TJ) consists of Random Jitter (RJ), Duty Cycle Distor- 2
3tion (DCD), Periodic Jitter (PJ), and Inter symbol Interference (ISI). For
4general jitter deﬁnitions and properties please see MJSQ1.
5
XFI deﬁnes the term non-EQJ jitter which helps in the deﬁnition of links 6with receive equalization. non-EQJ jitter is related to jitter components de- 7
ﬁned in MJSQ by the following relationship:
8910
˙ + PJ ) .
non – EQJ = TJ – ISI = ( RJ + DCD
11
12
13
14
15
3.5 XFI COMPLIANCE CHANNEL16
The XFI compliance channel consists of PCB traces, Vias, and the XFP 17
connector 6.9. The PCB traces differential impedance is recommended to 18
meet 100 ±10Ω.
1920
The XFI channel has a loss budget of 9.6 dB allocated as shown in Table
21
6. Due to rounding, actual budgets may be slightly different than 9.6 dB.
22
23
Table 6 XFI Loss Budget
24
Parameter
SymbolConditions
Max
Units
25
1
Channel Loss Including Connector
at 5.5 GHz
6.0
dB
26
27
Channel Crosstalk and Reﬂection Margin
3.6
dB
28
Total Channel Loss
9.6
dB
29
1. Loss allocated to the connector is 0.5 dB at 5.5 GHz.
30
31
Βased on measurement and simulation of compliance channel, the worst
32
case channel transfer SDD21 shall meet:
33
34
SDD21 ( dB ) = ( – 0.1 – 0.78 × f – 0.74 × f )
35
36
37
38
where the variable f (frequency) unit is in GHz. The above equation is
speciﬁed in terms of two ports S-parameters assuming the channel meets 39
40
1. Information Technology - Fibre Channel - Methodologies for Jitter and Signal 41
Quality Speciﬁcation - MJSQ, Project 1316-DT/Rev 14, June 9, 2004.
42
XFP MSA

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REVISON 4.5

High Speed Electrical Speciﬁcation XFI

0

SDD21 (dB)

-2

-4

-6

-8
-10
0

XFP MSA

August 31, 2005

XFI return loss, therefore differential coupling effects may be neglected for 1
insertion loss S21. Please see Appendix C: for differential measurements 2and conversions.
3
4
5
The above equation is valid from 250MHz to 7 GHz. An approximate dia- 6
7gram is shown in Figure 6.
8
9
10
11
12
Example of a Compliant Channel
1314Min. Allowed
15
Channel Transfer
16
17
18
19
20
21
7
1
2
3
4
5
6
8
9
22
Frequency (GHz)23
24
Figure 6 Channel Transfer Model
25
26
The channel transfer model is given by two port S-parameters SDD21 in 27
Figure 6. Detailed descriptions of two port and 4 port measurements and 28
conversions are provided in Appendix C:.
29
30
Architectural Note31
For loosely coupled symmetrical structures, differential SDD21 may be 32
33
approximated by direct measurement of S21.
34
35
36
The XFI compliance channel must meet a differential return loss of 10 dB 37
from 1MHz-7500MHz. For frequencies in the range of 7.5 to 15 GHz
38
channel return loss is given by:
39
40
f
SDD11 ( dB ) = 10 – 25Log  -------
41
10  7.5
42Page 20

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REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

where variable f (frequency) is in GHz.

1
2
3
4
A host board meeting the Channel Transfer Model given by Figure 6 may
be implemented with Microstrip or Stripline. A list of common host board 5
conﬁgurations with maximum recommended host PCB trace lengths are 6
7
listed in Table 7.
8
Table 7 Host Board Conﬁguration
9
10
Trace Width
Trace Length
Type
Material
Loss Tan
Copper (oz)
11
(mm)
(mm)
12
Microstrip
4000-6
0.3
0.025
1
200
13
4000-13
0.3
0.016
1
300
14
15
Stripline
4000-6
0.125
0.025
1/2
150
16
4000-13
0.125
0.016
1/2
200
17
18
19
20
Architectural Note21
Use of lossy materials or ﬁner traces may be beneﬁcial for short chan- 22
nels since they introduce additional attenuation, which in turn, improves 23
Return Loss.
24
25
26
27
3.6 XFI ASIC/SERDES SPECIFICATION
28
XFI ASIC/SerDes speciﬁcations are informative. XFI ASIC/SerDes Trans- 29
mitter speciﬁcations at compliance point A are given in 3.6.1. XFI30
ASIC/SerDes Receiver speciﬁcations at compliance point D are given in31
3.6.2.
32
33
3.6.1 XFI ASIC/SERDES TRANSMITTER OUTPUT SPECIFICATIONS AT A (INFORMATIVE)The XFI driver is based on low voltage high speed driver logic with a nom- 34
inal differential impedance of 100 Ω. The XFI transmitter electrical speci- 35
ﬁcations at compliance point A are given in Table 8. The source must
36
provide both differential and common mode termination for quality signal 37
termination and low EMI.
38
39
Return loss at A is measured with the SerDes on a DUT board as shown40
in A.1.
41
42
XFP MSA

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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Table 8 XFI ASIC/SerDes Transmitter Output Electrical Speciﬁcations at A
Parameter - A

SymbolConditions

Reference Differential Impedance

Zd

See Figure 5

Termination Mismatch∆RM

See E.6, Figure 5

DC Common Mode Voltage

Vcm0

Output Rise and Fall time (20% to 80%)tRH, tFH

24

Output AC Common Mode Voltage

Min

Typ

Units
Ω

100
5

%

3.6

V
ps

See E.5

Differential Output Return Loss 1

Max

15

mV (RMS)

0.05-0.1 GHz

20

dB

0.1-7.5 GHz

10dB

7.5-15 GHz

see 2

0.1-15 GHz

6

SDD22

Common Mode Output Return Loss 2

SCC22

dB

1. Return Loss given by equation SDD22(dB)= 10 - 16.6 Log10(f/7.5), with f in GHz.
2. Common mode reference impedance is 25 Ω. Common Mode Return Loss helps absorb reﬂections and noise for EMI.

Transmitter jitter speciﬁcations are listed in Table 9. Figure 7 gives thecompliance eye mask.

Table 9 XFI ASIC/SerDes Transmitter Output Jitter Speciﬁcations at A
Transmitter - A

SymbolConditions

Determinstic Jitter

DJ

Total Jitter

TJ

Eye Mask

Max

Units

See E.1, 1

0.15

UI (p-p)

See E.1, 1

0.30

UI (p-p)

X1

0.15

UI

Eye Mask

X2

0.4

UI

Eye Mask

Y1

Eye Mask

Y2

Jitter Generation for Telecom Applications

Min

Typ

180

50KHz to 8 MHz
see 2

mV
385

mV

6.5

mUI (RMS)

1. In loop timing mode, includes jitter that transfers through the ASIC from the receiver during any valid operational input
conditions.
2. Measured with a ﬁlter with 50 KHz high-pass cutoff desinged frequency and 8 MHz low pass cut off frequency. The ﬁlter rolls off
at least for one decade on each side of the passband with -20 dB/Dec. Does not apply to a host designed with Optional Synchronous
CMU clock, when used in conjunction with a Synchronous CMU module 3.10.1.

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XFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Absolute Amplitude

Y2
Y1
0
-Y1
-Y2

0.0 X1X2

1-X2

1-X1 1.0

Normalized Time (UI)

Figure 7 XFI ASIC/SerDes Transmitter Differential Output
Compliance Mask at A

3.6.2 XFI ASIC/SERDES RECEIVER INPUT SPECIFICATIONS AT D (INFORMATIVE)XFI receiver electrical speciﬁcations are given in Table 10 and measured
at compliance point D. The return loss at D is measured with the SerDes
on a DUT board A.1. Receiver input impedance is 100 Ohms differential.
The load must provide differential termination and minimize differential tocommon mode conversion for high quality signal termination and low EMI,
as given by Table 10.

XFP MSA

Page 23

Copyright © 2002-2005 by XFP MSA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
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XFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Table 10 XFI ASIC/SerDes Receiver Electrical Input Speciﬁcations at D
Parameter - D

SymbolConditions

Reference Differential Impedance

Zd

See Figure 5

Termination Mismatch∆ZM

See E.6, Figure 5

5%

See E.525mV (RMS)AC Common Mode Voltage

Differential Input Return Loss

Min

Typ

Max

Units
Ω

100

0.05-0.1 GHz

20

dB

0.1-7.5 GHz

10dB

7.5-15 GHz

see 1

SDD11

Common Mode Input Return Loss2

SCC11

0.1-15 GHz

6dB

Differential to Common Mode Input
Conversion2

SCD110.1-15 GHz

12dB

1. Return Loss given by equation SDD11(dB)= 10 - 16.6 Log10(f/7.5), with f in GHz C.4.
2. Common mode reference impedance is 25 Ω. SCD11 relates to conversion of differential to common mode and the associatedgeneration of EMI C.4

The XFI jitter speciﬁcations at reference D are listed in Table 11 and thecompliance mask is shown in Figure 8. Only a compliant transmitter
passing through the XFI channel is guaranteed for interoperablity.

Table 11 XFI ASIC/SerDes Receiver Input Jitter Speciﬁcations at D
Receiver- D

SymbolConditions

Total Jitter

TJ

Total non-EQJ Jitter

Min

Typ

Max

Units

See E.1, E.2

0.65

UI (p-p)

See E.1, E.2

0.45

UI (p-p)Sinusoidal Jitter Tolerance

SJ

E.3

see 1

Eye Mask

X1

Note 20.325

Eye Mask

Y1

Eye Mask

Y2

55
Note 3

UI
mV

525

mV

1. Sinuosidal jitter tolerance for Telecom and Datacom respectively given by Figure 9 and Figure 10.
2. Mask coordinate X1=0.225 if total non-EQJ jitter is measured.
3. Out of 525 mV, 100 mV is allocated for multiple reﬂection.

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Copyright © 2002-2005 by XFP MSA

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XFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Sinuosidal Jitter Tolerance (UIp-p)

Absolute Amplitude

1
2
3
4
5
Y2
6
7
Y1
8
0
9
-Y1
10
11
-Y2
12
13
0.0
1-X1
14
1.0
X1
15
Normalized Time (UI)
16
Figure 8 XFI ASIC/SerDes Receiver Differential Input Compliance
17
Mask
18
19
An XFI receiver for Telecom (SONET OC-192 and G. 709 “OTU-2”) appli- 20
cations must meet jitter tolerance given by Figure 9 with the addition of
21
input jitter given by Table 11. An XFI receiver for Datacom (Ethernet
22
802.3ae or Fibre Channel 10GFC) must meet the jitter tolerance given by
23
Figure 10 with the addition of random and deterministic jitter given by
24
Table 11.
25
26
27
15.2
28
-20dB/Dec
29
30
31
1.7
32
33
34
35
0.17
36
0.05
37
38
0.01E-3
27.2
17.9E-3
4
2E-3
0.4
8
80
39
Frequency (MHz)40
41
Figure 9 XFI ASIC/SerDes Receiver Input Telecom Sinuosidal Jitter
42

XFP MSA

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REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

1
2
3
4
5
6
0.2
1.13x  ------- + 0.1 , f in MHz
 f

7
8
-20dB/Dec
9
10
11
12
0.17
13
14
0.05
15
27.2
0.04
4
8
80
16
Frequency (MHz)17
18
Figure 10 XFI ASIC/SerDes Receiver Input Datacom Sinuosidal Jitter 19
Tolerance
20
21
22
3.7 XFI HOST SYSTEM SPECIFICATION
23
XFI Host system transmitter speciﬁcations at compliance point B are
24
given in 3.7.1. XFI Host system receiver speciﬁcations at compliance25
point C are given in 3.7.2.
26
27
28
3.7.1 XFI HOST TRANSMITTER OUTPUT SPECIFICATIONS AT B
29
30
XFI Host transmitter electrical speciﬁcations are given in Table 12 andmeasured at compliance point B.
31
32
33
34
35
36
37
38
39
40
41
42
Sinuosidal Jitter Tolerance (UIp-p)

Tolerance

XFP MSA

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REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

1
2
Table 12 XFI Host Transmitter Output Electrical Speciﬁcations at B
3
4
Parameter - B
SymbolConditions
Min
Typ
Max
Units
5
Reference Differential Impedance
Zd
100
Ω
6
Termination Mismatch∆ZM
See E.6, Figure 5
5%7
8
DC Common Mode Voltage
Vcm
0
3.6
V
9
Output AC Common Mode Voltage
See E.525mV (RMS)
100.05-0.1 GHz
20
dB
11
Differential Output Return Loss
SDD22
12
0.1-5.5 GHz
8dB
13
5.5-12 GHz
see 1
14
Common Mode Output Return Loss2
SCC22
0.1-12 GHz
3
dB
15
16
1. Return Loss given be equation SDD22(dB)= 8 - 20.66 Log10(f/5.5), with f in GHz.
2. Common mode reference impedance is 25 Ω. Common Mode Input return loss helps absorb reﬂections and noise reducing EMI.
17
18
The XFI jitter speciﬁcations at reference point B are listed in Table 13 and 19
the compliance mask is shown in Figure 11. Only a compliant transmitter
20
passing through the XFI channel is guaranteed for interoperablity.
21
22
Table 13 XFI Host Transmitter Output Jitter Speciﬁcations at B
23
Receiver- B
SymbolConditions
Min
Typ
Max
Units
24
1,
25
Total Jitter
TJ
See E.1
0.61
UI
26
Total non-EQJ Jitter 1
See E.1, E.2
0.41
UI
27
Eye Mask
X1
see 2
0.305
UI
28
29
Eye Mask
Y1
60
mV
30
Eye Mask
Y2
see 3
410
mV
31
Jitter Generation at B Telecom Applications
50KHz-8MHz, see 4
7mUI (RMS)
32
33
1. In loop timing mode, includes jitter that transfers through ASIC from the receiver during any valid operational input conditions.
2. . Mask cordinate X1=0.205 if total non-EQJ jitter is measured.
34
3. Out of 410 mV, 25 mV is allocated for multiple reﬂection.
35
4. Measured with a ﬁlter with 50 KHz high-pass cutoff desinged frequency and 8 MHz low pass cut off frequency. The ﬁlter rolls
36
off at least for one decade on each side of the passband with -20 dB/Dec. Does not apply to a host designed with Optional
37
Synchronous CMU clock, when used in conjunction with a Synchronous CMU Signal Conditioner module see 3.10.1.
38
39
40
41
42
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REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Absolute Amplitude

1
2
3
4
5
Y2
6
7
Y1
8
0
9
-Y1
10
11
-Y2
12
13
0.0
1-X1
14
1.0
X1
15
Normalized Time (UI)
16
Figure 11 XFI Host Transmitter Differential Output Compliance Mask
17
at B
18
19
20
3.7.2 XFI HOST RECEIVER INPUT SPECIFICATIONS AT C
The XFI Host receiver electrical speciﬁcations at compliance point C are 21
given in Table 14. The load must provide differential termination and min- 22
imize differential to common mode conversion for quality signal termina- 23
tion and low EMI, as given in Table 14.
24
25
Return loss at compliance point C is measured with the Host Test Board
26
plugged into the host as shown in A.2.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

1
2
Table 14 XFI Host Receiver Input Electrical Speciﬁcations at C
3
4
Parameter - C
SymbolConditions
Min
Typ
Max
Units
5
Reference Differential Impedance
Zd
See Figure 5100Ω
6
Termination Mismatch∆ZM
See E.6, Figure 55%78
Source to Sink DC Potential Difference
Vcm
0
3.6
V
9
Input AC Common Mode Voltage
See E.515mV (RMS)
10
Input Rise and Fall time (20% to 80%)tRH, tFH
24
ps
11
12
0.05-0.1 GHz
20
dB
13
Differential Input Return Loss
SDD11
0.1-5.5 GHz
8
dB
14
15
5.5-12 GHz
see 1
16
Common Mode Return Loss 2
SCC11
0.1-12 GHz
3
dB
17
18
Differential to Common Mode Conversion 2
SCD11
0.1-12 GHz
10dB
19
1. Return Loss given be equation SDD11(dB)= 8 - 20.66 Log10(f/5.5), with f in GHz C.4.
20
2. Common mode reference impedance is 25 Ω. SCD11 and SCC11 help minimize generated EMI C.4.
21
22
Transmitter jitter speciﬁcations are listed in Table 15. Figure 12 gives the23
host compliance eye mask.
24
25
26
Table 15 XFI Host Receiver Input Jitter Speciﬁcations at C
27
28
Transmitter - C
SymbolConditions
Min
Typ
Max
Units
29
Determinstic JitterDJ
See E.1
0.18
UI (p-p)30
Total Jitter
TJ
See E.1
0.34
UI (p-p)31
32
Sinusoidal Jitter Tolerance
SJ
E.3
see 1
33
Eye Mask
X1
0.17
UI
34
35
Eye Mask
X2
0.42
UI
36
Eye Mask
Y1
170
mV
37
38
Eye Mask
Y2
see 2
425
mV
39
1. Sinuosidal jitter tolerance for Telecom and Datacom respectively given by Figure 13 and Figure 14.
40
2. Out of 425 mV, 25 mV is allocated for multiple reﬂections.
41
42
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High Speed Electrical Speciﬁcation XFIAbsolute Amplitude

XFP Speciﬁcation
REVISON 4.5

XFP MSA

August 31, 2005

1
2
3
4
5
Y2
6
Y1
7
8
0
9
10
-Y1
11
-Y2
12
13
14
0.0 X1
1-X2 1-X1 1.0
X215
Normalized Time (UI)
16
Figure 12 XFI Host Receiver Differential Input Compliance Mask at C 17
18
19
The XFI receiver for Telecom (SONET OC-192 and G. 709 “OTU-2”) ap20
plications must meet the jitter tolerance with the addition of deterministic
21
and random jitter given by Table 15. The XFI receiver for Datacom(Ethernet 802.3ae or Fibre Channel 10GFC) Host must meet jitter toler- 22
23
ance given by Figure 14 with the addition of deterministic and random
jitter given by Table 15.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Page 30

Copyright © 2002-2005 by XFP MSA

High Speed Electrical Speciﬁcation XFI

Sinuosidal Jitter Tolerance (UIp-p)

XFP Speciﬁcation
REVISON 4.5

August 31, 2005

15.2

-20dB/Dec

1.7

0.17
0.05
0.01E-3

2E-3

17.9E-38

4
0.4
Frequency (MHz)

27.2

80

Sinuosidal Jitter Tolerance (UIp-p)

Figure 13 XFI Host Receiver Telecom Input Sinuosidal Jitter
Tolerance

0.2
1.13x  ------- + 0.1 , f in MHz
 f

-20dB/Dec

0.17
0.05
0.04

4
Frequency (MHz)

8

27.2

80

Figure 14 XFI Host Receiver Input Datacom Sinuosidal Jitter
Tolerance

XFP MSA

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Copyright © 2002-2005 by XFP MSA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

XFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

3.8 XFI MODULE SPECIFICATIONS

1
XFI Module Transmitter speciﬁcations at compliance point B’ are given in 2
3
3.8.1. XFI Module Receiver speciﬁcations at compliance point C’ aregiven in 3.8.2.
4
5
6
7
3.8.1 XFI MODULE TRANSMITTER INPUT SPECIFICATIONS AT B’
8The XFI module transmitter electrical speciﬁcations are given in Table 16,
9measured at compliance point B’ as shown in A.3. The receiver input impedance is 100 Ohms differential. The load must provide differential ter- 10
mination and minimize differential to common mode conversion for quality 11
12signal termination and low EMI, as given in Table 16.
13
The XFI jitter speciﬁcations at reference point B’ are listed in Table 17 and 14
the compliance mask is shown in Figure 15. Only a compliant transmitter 15
passing through the XFI channel is guaranteed for interoperability.
16
17
Return loss at compliance point B’ is measured with the Module Test
18
Board plugged into the host as shown in A.3.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Table 16 XFI Module Transmitter Input Electrical Speciﬁcations at B’Parameter - B’

SymbolConditions

Reference Differential Input Impedance

Zd

See Figure 5

Termination Mismatch∆ZM

See E.6, Figure 5

Source to Sink DC Potential Difference

Vcm

Input AC Common Mode Voltage

Differential Input Return Loss

Min

Typ

Max

Ω

100

0
See E.5

Units

5

%

3.6

V

25

mV (RMS)

0.05-0.1 GHz

20

dB

0.1-5.5 GHz

8dB

5.5-12 GHz

see 1

SDD11

Common Mode Input Return Loss2

SCC11

0.1-12 GHz

3dB

Differential to Common Mode Conversion2

SCD110.1-12 GHz

10dB

1. Return Loss given be equation SDD11(dB)= 8 - 20.66 Log10(f/5.5), with f in GHz C.4.
2. Common mode reference impedance is 25 Ω. Differential to common mode conversion relates to generation of EMI C.4.

Table 17 XFI Module Transmitter Input Jitter Speciﬁcations at B’Receiver- B’

SymbolConditions

Total Non-EQJ Jitter

0.41

Total Jitter

Min

Typ

Max

Units

See E.1, E.2

0.41

UI (p-p)

TJ

See E.1, E.2

0.61

UI (p-p)Sinusoidal Jitter Tolerance

SJ

E.3

see 1

Eye Mask

X1

see 2

0.305

Eye Mask

Y1

Eye Mask

Y2

60
see 3

UI
mV

410

mV

1. Sinuosidal jitter tolerance for Telecom and Datacom respectively given by Figure 16 and Figure 17.
2. Mask cordinate X1=0.205 if total non-EQJ jitter is measured.
3. Out of 410 mV, 50 mV is allocated for multiple reﬂection.

XFP MSA

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Copyright © 2002-2005 by XFP MSA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

XFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Sinuosidal Jitter Tolerance (UIp-p)

Absolute Amplitude

1
2
3
4
5
Y2
6
7
Y1
8
0
9
-Y1
10
11
-Y2
12
13
0.0
1-X1
14
1.0
X1
15
Normalized Time (UI)
16
Figure 15 XFI Module Transmitter Differential Input Compliance17
Mask at B’
18
19
XFI Module for Telecom (SONET OC-192 and G. 709 “OTU-2”) applica- 20
tions must meet the jitter tolerance given by Figure 16 with addition of
21
input jitter given by Table 17. The XFI Module for Datacom (Ethernet
22
802.3ae and Fibre Channel 10GFC) must meet the jitter tolerance given
23
by Figure 17 with the addition of random and deterministic jitter given in
24
Table 17.
25
26
27
15.2
28
29
-20dB/Dec
30
1.7
31
32
33
34
0.17
35
36
0.05
37
38
0.01E-3
4.08
17.9E-3
2E-3
0.12
80
39
Frequency (MHz)40
Figure 16 XFI Module Transmitter Input Telecom Sinuosidal Jitter 41
Tolerance
42

XFP MSA

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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Sinuosidal Jitter Tolerance (UIp-p)

1
2
3
4
5
6
7
8
1.5
9
10
11
12
13
0.05
14
15
0.01E-3
4
40E-3
0.13
80
16
Frequency (MHz)17
18
Figure 17 XFI Module Transmitter Input Datacom Margin Mask
19
20
21
3.8.2 XFI MODULE RECEIVER OUTPUT SPECIFICATIONS AT C’
22
The XFI transmitter electrical speciﬁcations at compliance point C’ are23
given in Table 18. The source must provide differential termination andcommon mode termination for quality signal termination and low EMI, as 24
25
given in Table 18.
26
Return loss at C’ is measured with the module on a Module Compliance 27
Test Board A.3.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
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REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

1
2
Table 18 XFI Module Receiver Output Electrical Speciﬁcations at C’
3
4
Parameter - C
SymbolConditions
Min
Typ
Max
Units
5
Reference Differential Output Impedance
Zd
See Figure 5100Ω
6
Termination Mismatch∆ZM
See E.6, Figure 5
5%7
8
DC Common Mode Potential
Vcm
0
3.6
V
9
Output AC Common Mode Voltage
See E.515mV (RMS)
10
Output Rise and Fall time (20% to 80%)tRH, tFH
24
ps
11
12
0.05-0.1 GHz
20
dB
13
Differential Output Return Loss
SDD22
0.1-5.5 GHz
8
dB
14
15
5.5-12 GHz
see 1
dB
16
Common Mode Output Return Loss 2
SCC22
0.1-12 GHz
3
dB
17
18
1. Differential Return Loss given be equation SDD22(dB)= 8 - 20.66 Log10(f/5.5), with f in GHz C.4.
2. Common mode reference impedance is 25 Ω. Common Mode Output Return Loss helps absorb reﬂection and noise improving
19
EMI C.4.
20
21
Transmitter jitter speciﬁcations are listed in Table 19. Figure 18 gives the22compliance eye mask.
23
24
25
Table 19 XFI Module Receiver Output Jitter Speciﬁcations at C’
26
27
Transmitter - C
SymbolConditions
Min
Typ
Max
Units
28
Determinstic JitterDJ
See E.1, 1
0.18
UI (p-p)29
30
Total Jitter
TJ
See E.1, 1
0.34
UI (p-p)
31
Eye Mask
X1
0.17
UI
32
33
Eye Mask
X2
0.42
UI
34
Eye Mask
Y1
170
mV
35
36
Eye Mask
Y2
425
mV
37
1. Includes jitter transfered from the optical receiver during any valid operational input condition.
38
39
40
41
42
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REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

1
2
3
4
Y2
5
Y1
6
7
0
8
9
-Y1
10
-Y2
11
12
13
0.0 X1
1-X2 1-X1 1.0
X214
Normalized Time (UI)
15
Figure 18 XFI Module Receiver Differential Output Compliance Mask 16
at C’
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

Absolute Amplitude.

XFP MSA

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REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

3.9 SIGNAL CONDITIONER

1The XFI Signal Conditioner is an active device that overcomes host board 2
and connector signal degradations by reshaping, regenerating, and atten- 3
uating jitter. The XFP module shall include a Signal Conditioner based on 4
CDR (Clock Data Recovery) technology for complete regeneration. An
5optional CMU (Clock Multiplier Unit) based regenerator, which requires a 6
clean frequency locked clock provided by the host XFI interface, is deﬁned
7
as well.
89The telecom XFI signal conditioner must meet SONET OC-192 andG.709 (OTU-2) speciﬁcations, while the datacom signal conditioner must 10
meet IEEE 802.3ae and 10 GFC speciﬁcations. The following sections de- 11
ﬁne the signal conditioner for each application. A common signal condi- 12
tioner meeting telecom and datacom speciﬁcations is desirable, but not
13
mandatory.
14
15
16
3.9.1 TELECOM MODULEThe XFP Telecom module must meet SONET OC-192 per GR-253 and G. 17
18709 (OTU-2) requirements.
19
The XFP Telecom module transmitter shall meet the requirements of both 20
SONET GR-253 and Table 20.
21
22
Table 20 XFP Telecom Module Transmitter Requirement
23
Module Transmitter B’SymbolConditions
Min
Typ
Max
Units
24
25
Jitter Transfer Bandwidth
BW
PRBS 2^31-1 Data, see 1
8MHz26
Jitter Peaking
Frequency <120 KHz
0.03
dB
27
see 2
28
Frequency >120 KHz
1
dB
29
see 3
30
Module Jitter Generation at Optical
Measured 50KHz-80MHz
10mUI (RMS)
31
Outputsee 4
100
mUI (p-p)
32
1. OC-192/SDH-64 Sinusoidal Jitter Tolerance Mask
33
34
2. Only required for loop timing, see E.4.
35
3. Does not apply to the optional CMU mode, see E.4.
36
4. In the CDR mode the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter from 50KHz-8 MHz Table 13. In CMU mode it isassumed that worst case phase noise given by Table 25. Jitter generation of an optical transmitter must include jitter that transfers
37
from the host during any valid operational conditions.
38
39
40
41
42
XFP MSA

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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

The XFP Telecom modules receiver shall meet the requirements of both 1
SONET GR-253 and Table 21.
2345Table 21 XFP Telecom Module Receiver Requirement
6
Module Transmitter C’
SymbolConditions
Min
Typ
Max
Units
7
8
Jitter Transfer Bandwidth
BW
PRBS 2^31-1 Data, see 1
8MHz
9Jitter Peaking
Frequency <120 KHz
0.03
dB
10
see 2
11
Frequency >120 KHz
1dB
12
1. OC-192/SDH-64 Sinusoidal Jitter Tolerance Mask
13
14
2. Only required for loop timing, see E.4.
15
16
17
3.9.2 DATACOM MODULE18
XFP Datacom module shall meet IEEE 802.3ae and 10 GFC requirement, 19
in addition to the requirements given in Table 20 and Table 21.
20
21
Table 22 XFP Datacom Module Transmitter Requirement
22
23
Module Transmitter B’SymbolConditions
Min
Typ
Max
Units
24
Jitter Transfer Bandwidth
BW
PRBS 2^31-1 Data or Scram8
MHz
25
bled 64B/66B, see 1
26
Jitter Peaking
Frequency >50 KHz
1dB
27
1. Based on IEEE 802.3ae Clause 52 Sinuosidal Jitter Tolerance Mask Figure 52-4.
28
29
30
31
Table 23 XFP Datacom Module Receiver Requirement
32
Module Transmitter C’
SymbolConditions
Min
Typ
Max
Units
33
Jitter Transfer Bandwidth
BW
PRBS 2^31-1 Data
8
MHz
34
or Scrambled 64B/66B, see 1
35
Jitter Peaking
Frequency >50 KHz
1
dB
36
37
1. Based on IEEE 802.3ae Clause 52 Sinuosidal Jitter Tolerance Mask Figure 52-4.
38
39
40
41
42
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

3.10 REFERENCE CLOCK SPECIFICATIONS

1
The host system shall supply a reference clock to the XFP module with a 2
frequency of +/-100 PPM of Baudrate/64 with speciﬁcations listed in Table 3
24. The Signal Conditioners in the XFP module may use the reference4
clock for VCO centering. The reference clock is intended for VCO cen5
tering so jitter requirements are intentionally relaxed to allow implementa- 6
tion ﬂexibility on the host board.
78
910
Table 24 Reference Clock Speciﬁcations
11
Parameter
SymbolConditions
Min
Typ
Max
Units
12
Clock Differential Input impedance
Zd
80
100
120
Ω
13
14
Differential Input Clock Amplitude (p-p)
AC Coupled PECL
640
1600
mV
15
Reference Clock Duty Cycle
40
60
%
16
17
Reference Clock Rise/Fall Time
Tr/Tf
20%-80%
200
1250
ps
18
Reference Clock Frequency
f0
Baud1/64
MHz
19
20
RMS Jitter Random Jitterσ
Up to 100 MHz
10
ps
21
Reference Clock Frequency Tolerance
∆f
-100
100
PPM
22
1. Reference clock frequency is not locked to the data frequency and may deviate by ∆f.
23
24
25
26
3.10.1 OPTIONAL SYNCHRONOUS CMU CLOCK27
The host system may optionally supply a synchronous reference clock to 28
the XFP module, with frequency exactly equal to the Baudrate/64 ac29
cording to the speciﬁcations listed in Table 25. The transmitter Signal Con30
ditioners in the XFP module may use the synchronous clock to retime the
31
data.
32
In order to select Optional Synchronous CMU clock, bit 0 of Byte 1, in the 33
two wire interface Table 34 must be set high. A CDR based module may 34
be used in conjunction with a synchronous clock from the host see 5.3. 35
36
Architectural Note3738
In applications where the Host System uses the XFP module in the op39
tional CMU mode, the Host must provide a synchronous low phase40
noise clock.
41
42
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

High Speed Electrical Speciﬁcation XFIAugust 31, 2005

Table 25 Optional Reference Clock Speciﬁcations
Parameter
Clock Differential Input impedance

SymbolConditions

Zd

Differential Input Clock Amplitude (p-p)

AC Coupled PECL

Reference Clock Duty Cycle
Reference Clock Rise/Fall Time

Tr/Tf

20%-80%

Reference Clock Frequency

f0

see 1

CMU Reference Clock Skew

TD

Baud2

Single Side Band Phase Noise

Min

Typ

Max

Units

80

100

120

Ω

640

1600

mV

40

60

%

1250

ps

200
Baud1/64
-10

MHz
+10

UI

@1KHz

-85

dBc/
Hz

@10KHz-108@100KHz

-128

@1MHz

-138

@10MHz-138

1. Reference clock frequency is exactly 1/64 of the Baudrate.
2. A UI deﬁned by the serial Baudrate.

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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

CHAPTER 4: XFP 2-WIRE INTERFACE PROTOCOL

4.1 INTRODUCTION
Low speed signaling is based on Low Voltage TTL (LVTTL) operating at
Vcc3 at a nominal supply of (3.3V ± 5%). Hosts shall use a pull-up resistor
connected to a host_Vcc of +3.3 volts (3.15 to 3.45 volts) on the 2-wireinterface SCL (clock) and SDA (Data) signals. Detailed electrical speciﬁcation are given in section 2.5.
Nomenclature for all registers more than 1 bit long are MSB-LSB.

4.2 XFP 2-WIRE TIMING DIAGRAM
XFP is positioned to leverage 2-wire timing (Fast Mode devices) to alignthe use of related cores on host ASICs. XFP 2-wire bus timing is shownin Figure 19. XFP AC speciﬁcations are given in Table 26.
tHIGH

tR

tF

SCL
tLOW
tHD,STAtSU,STAtSU,DATtHD,DATtSU,STOtF

tR

SDA InSTARTReSTARTSTOPSDA Out

Figure 19 XFP Timing Diagram

Before initiating a 2-wire serial bus communication, the host shall provide
setup time (Host select_setup - table 26) on the Mod_DeSel line of all
modules on the 2-wire bus. The host shall not change the Mod_DeSel line

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XFP Speciﬁcation
REVISON 4.5

Parameter
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width HighTime bus free before new transmission can start
START Hold Time
START Set-up Time
Data In Hold Time
Data In Set-up Time
Input Rise Time (100kHz)
Input Rise Time (400kHz)
Input Fall Time (100kHz)
Input Fall Time (400kHz)
STOP Set-up Time
Host Supplied Module DeSelect Setup Time
Host Supplied Module DeSelect Hold Time

Aborted sequence - bus release

XFP MSAXFP 2-Wire Interface Protocol

August 31, 2005of any module until the 2-wire serial bus communication is complete and 1
the hold time requirement (Host_select_hold - Table 26) is satisﬁed.
2
3
The 2-wire serial interface address of the XFP module is 1010000X (A0h).
4
In order to allow access to multiple XFP modules on the same 2-wire serial bus, the XFP pinout includes a Mod_DeSel or module deselect pin. 5This pin (which is pulled high or deselected in the module) must be held 6
low by the host to select the module of interest and allow communication 7
over the 2-wire serial interface. The module must not respond to or accept 82-wire serial bus instructions unless it is selected.
9
10
11
12
Table 26 XFP 2-Wire Timing Speciﬁcations
13
Symbol
Min.
Max.
Unit
Conditions
14
15
fSCL
0
400
kHz
16
tLOW
1.3
µs
17
tHIGH
0.6
µs
18
19
tBUF
20
µs
Between STOP and START
20
21
tHD,STA
0.6µs
22tSU,STA
0.6µs
23tHD,DAT0µs
24tSU,DAT
0.1
µs
25
26
tR,1001000
ns
From (VIL,MAX - 0.15) to (VIH,MIN + 0.15)
27
tR,400300
ns
From (VIL,MAX - 0.15) to (VIH,MIN + 0.15)
28
tF,100300
ns
From (VIH,MIN + 0.15) to (VIL,MAX - 0.15)
29
tF,400300
ns
From (VIH,MIN + 0.15) to (VIL,MAX - 0.15)30
31tSU,STO
0.6µs
32
Host_select_setup
2
ms
Setup time on the select lines before start of a33
host initiated serial bus sequence34
Host_select_hold10µs
Delay from completion of a serial bus
35
sequence to changes of transceiver select status
36
37
Deselect_Abort2
ms
Delay from a host asserting Mod_DeSel (atany point in a bus sequence), to the XFP mod- 38
ule releasing SCL and SDA
39
40
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

4.3 MEMORY TRANSACTION TIMINGXFP memory transaction timings are given in Table 27. Single Byte writable memory
blocks are given in Table 28. Multiple Byte writable memory blocks are given in Table
29.

Table 27 XFP Memory Speciﬁcations
Parameter

SymbolSerial Interface Clock Holdoff“Clock Stretching”

Complete Single or Sequential
Write

Max.

Unit

Conditions

T_clock_hold

500

µs

Maximum time the XFP module may hold the
SCL line low before continuing with a read or
write operation

tWR

40

ms

Complete (up to) 4 Byte Write

cycles

70 °C

Endurance (Write Cycles)

Min.

50 k

Table 28 Single Byte Writable Memory Blocks
Byte Address

Volatile or NV

Description

1

V

Signal Conditioner Control Register

110

V

General Control Bits

118

V

Packet Error Checking Control

127

V

Table Select Byte

Table 29 Multiple Byte Writable Memory Blocks

XFP MSA

Byte Address# Bytes

Volatile or NV

72-73

2

V

Wavelength Control Registers

76-77

2

V

FEC Control Registers

88-93

6

V

Interrupt Masking Bits

119-122

4

V

Password Change Entry

123-126

4

V

Password Entry

128-255

128

NV

Table 02h – Customer Writable

Page 44

Description

Copyright © 2002-2005 by XFP MSA

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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

4.4 DEVICE ADDRESSING AND OPERATION

1
Serial Clock (SCL): The host supplied SCL input to XFP transceivers is 2
3
used to positively edge clock data into each XFP device and negative
clock data out of each device. The SCL line may be pulled low by an XFP 4
module during clock stretching.
5
6
Serial Data (SDA): The SDA pin is bi-directional for serial data transfer.
7This pin is open-drain or open-collector driven and may be wire-ORed8
with any number of open-drain or open collector devices.
9
Master/Slave: XFP transceivers operate only as slave devices. The host 10
must provide a bus master for SCL and initiate all read/write communica- 11
tion.
12
13
Device Address: Each XFP is hard wired at the device address A0h. See
XFP MSA Chapter 5: Management interface for memory structure within 14
15
each transceiver.
16
Multiple Devices per SCL/SDA: While XFP transceivers are compatible 17
with point-to-point SCL/SDA, they can also be paralleled on a single
18
SCL/SDA bus by using the XFP Mod_DeSel line. See section 2.4.2 and 19
Table 26 for more information.
20
Clock and Data Transitions: The SDA pin is normally pulled high with an 21
22
external device. Data on the SDA pin may change only during SCL low
time periods. Data changes during SCL high periods indicate a START or 23
STOP condition. All addresses and data words are serially transmitted to 24
and from the XFP in 8-bit words. Every byte on the SDA line must be 8- 25
bits long. Data is transferred with the most signiﬁcant bit (MSB) ﬁrst.
26
27
START Condition: A high-to-low transition of SDA with SCL high is a
28
START condition, which must precede any other command.
29
STOP Condition: A low-to-high transition of SDA with SCL high is a30
STOP condition.
31
32
Acknowledge: After sending each 8-bit word, the transmitter releases the33
SDA line for one bit time, during which the receiver is allowed to pull SDA
low (zero) to acknowledge (ACK) that it has received each word. Device 34
address bytes and write data bytes initiated by the host shall be acknowl- 35
edged by XFP transceivers. Read data bytes transmitted by XFP trans- 36
ceivers shall be acknowledged by the host for all but the ﬁnal byte read, 37
for which the host shall respond with a STOP instead of an ACK.
38
39
Memory (Management Interface) Reset: After an interruption in protocol, power loss or system reset the XFP management interface can be 40
reset. Memory reset is intended only to reset the XFP transceiver man- 41
42

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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

agement interface (to correct a hung bus). No other transceiver function- 1
ality is implied.
231) Clock up to 9 cycles.
42) Look for SDA high in each cycle while SCL is high.
563) Create a START condition as SDA is high7
Device Addressing: XFP devices require an 8 bit device address word
following a start condition to enable a read or write operation. The device 89address word consists of a mandatory one zero sequence for the ﬁrst
seven most signiﬁcant bits Table 30. This is common to all XFP devices. 10
11
Table 30 XFP Device Address
12
13
1
0
1
0
0
0
0
R/W
14
MSB
LSB
15
The eighth bit of the device address is the read/write operating select bit. 16
A read operation is initiated if this bit is set high and a write operation is 17
18
initiated if this bit is set low. Upon compare of the device address (with
Mod_DeSel in the low state) the XFP transceiver shall output a zero
19(ACK) on the SDA line to acknowledge the address.
20
21
22
23
4.5 READ/WRITE FUNCTIONALITY
24
25
26
4.5.1 PACKET ERROR CHECKING
27
In addition to the basic I2C read/write functionality, all XFP modules shallsupport packet error checking deﬁned in the sections below. The packet 28
29
error checking system may be enabled or disabled by the host system,
30
and will default to being disabled on power-up or reset. Packet error
checking allows the host system to conﬁrm the validity of any read data 31
including the address from which the read originated. Packet error
32
checking also allows the XFP module to determine the validity of write
33
data and to reject write commands with errors. Finally, the host may use
34
the system to determine if a write communication was successful. All
packet error checking operations involve the calculation of a CRC-8 value 35
36
by the module and host. The CRC-8 value is the cyclical redundancy
check as deﬁned in the SMBUS 2.0 standard.
37
38
4.5.2 XFP MEMORY ADDRESS COUNTER (READ AND WRITE OPERATIONS)39
XFP devices maintain an internal data word address counter containing 40
the last address accessed during the latest read or write operation, incre- 41
mented by one. The address counter is incremented whenever a data42
XFP MSA

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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

word is received or sent by the transceiver. This address stays valid be- 1
tween operations as long as XFP power is maintained. The address “roll 2
over” during read and write operations is from the last byte of the 128 byte 3
memory page to the ﬁrst byte of the same page.
4
In order to read both the lower page and currently selected upper page, 5at least two read operations must be performed, one with start address of 6
ZERO and another with start address of 128. A single 256-byte read op- 7
eration with start address of ZERO would contain the 128 bytes of the8lower page twice, instead of the lower page followed by the currently se- 9
lected upper page.
10
11
12
13
4.5.3 READ OPERATIONS (CURRENT ADDRESS READ)
A current address read operation requires only the device address read 14
word (10100001) be sent, Figure 20. Once acknowledged by the XFP, the 15
current address data word is serially clocked out. The host does not re- 16
spond with an acknowledge, but does generate a STOP condition once 17
the data word is read.
18
19< ---- XFP ADDRESS 20
-->
21
HOST
S M
L R
N S
22
T S
S E
A T
A B
B A
C O
23
R
D
K P
24
T
25
1 0 1 0 0 0 0 1 0 x x x x x x x x 1
26
XFP
A M
L
C S
S
27
K B
B
28
<------ DATA WORD ------>
29
30
Figure 20 XFP Current Address Read Operation
31
32
33
4.5.4 READ OPERATIONS (RANDOM READ)
A random read operation requires a “dummy” write operation to load in the 34
target byte address Figure 21. This is accomplished by the following se- 35
quence: The target 8-bit data word address is sent following the device
36
address write word (10100000) and acknowledged by the XFP. The host 37
then generates another START condition (aborting the dummy write
38
without incrementing the counter) and a current address read by sending
39
a device read address (10100001). The XFP acknowledges the device
address and serially clocks out the requested data word. The host does 40
41
42
XFP MSA

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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

not respond with an acknowledge, but does generate a STOP condition
once the data word is read.

XFP MSA

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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

1
2
3
< ---- XFP ADDRESS <--- MEMORY ADDRESS< ---- XFP ADDRESS -->
-->
-->
4
5
HOST
S M
L W
M
L
S M
L R
N S
T S
S R
S
S
T S
S E
A T 6
A B
B
B
B
A B
B A
C O
R
I
R
D
K P 7
T
T
T
8
E
9
1 0 1 0 0 0 0 0 0 x x x x x x x x 0
1 0 1 0 0 0 0 1 0 x x x x x x x x 1
10
L
A M
A
XFP
A
11
S
C S
C
C
B
K B
K
K
12
<------ DATA WORD ------>
13
14
Figure 21 XFP Random Read
15
16
17
4.5.5 READ OPERATIONS (SEQUENTIAL READ)
18
Sequential reads are initiated by either a current address read Figure 22
19
or a random address read Figure 23. To specify a sequential read, thehost responds with an acknowledge (instead of a STOP) after each data 20
word. As long as the XFP receives an acknowledge, it shall serially clock 21
out sequential data words. The sequence is terminated when the host re- 22
sponds with a NACK and a STOP instead of an acknowledge.
23
24
25
26
< ---- XFP ADDRESS 27
-->
HOST
S M
L R
A
A
N S 28
T S
S E
C
C
A T
29
A B
B A
K
K
C O
R
D
K P 30T
31
1 0 1 0 0 0 0 1 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 1
32
XFP
A M
L
M
L
M
L
33
C S
S
S
S
S
S
K B
B
B
B
B
B
34
<---- DATA WORD n ----><---- DATA WORD n+1 --<---- DATA WORD n+x --35->->
36
Figure 22 Sequential Address Read Starting at XFP Current Address 37
38
39
40
41
42
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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

1
2
3
< ---- XFP<--- MEMORY< ---- XFP
ADDRESS --->ADDRESS -->ADDRESS --->
4
L W
M
L
S M
L R
A
A
N S
H S M
S R
S
S
T S
S E
C
C
A T 5
O T S
B I
B
B
A B
B A
K
K
C O
S A B
R
T
R
D
K P 6
T T
E
T
7
1 0 1 0 0 0 0 0 0 x x x x x x x x 0
1 0 1 0 0 0 0 1 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 1
8
A
A
A M
L
M
L
M
L
X
9
C
C
C S
S
S
S
S
S
F
K
K
K B
B
B
B
B
B
P
10
<---- DATA WORD n<---- DATA WORD<---- DATA WORD
11---->
n+1 ---->
n+x ---->
12
Figure 23 Sequential Address Read Starting with Random XFP Read 13
14
15
4.5.6 READ OPERATION PACKET ERROR CHECKING
16
For packet error checking, the host shall begin with the XFP device Ad- 17
dress and Starting Memory Address, followed by the number of bytes to 18
be read. The XFP CRC-8 calculation requires an explicit starting memory 19
address be incorporated as the ﬁrst byte processed by the algorithm, fol20
lowed by the number of bytes to be read, and ﬁnally all data bytes. Afterthe host reads the required number of bytes, the CRC-8 value will be sent 21
by the XFP module. The host will follow with NACK and STOP to complete 22
the READ operation. XFP read operation with packet error checking is il- 23
lustrated in Figure 24. The CRC-8 value is calculated on the starting
24
memory address (MSB ﬁrst) followed by the number of bytes and the25
Read Bytes in the order they are sent. The host may then verify the CRC26
8 value and reject the read if the CRC-8 value does not correspond to thereceived data and desired Read address. Note the XFP address itself is 27
28
not included in the CRC-8 calculation.
29
Only reads of 1-128 bytes are supported. Any transaction that does not 30
follow the protocol described in this section will result in an unpredictable 31
response from the module when PEC is enabled.
32
33
34
35
36
37
38
39
40
41
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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

1
2
3
< ---- XFP<----- MEMORY< ---- Number of< ---- XFP
ADDRESS --->ADDRESS ---->BYTES ---->ADDRESS --->
4
H S M
L W
M
L
M
L
S M
L R
5
O T S
S R
S
S
S
S
T S
S E
S A B
B I
B
B
B
B
A B
B A
6
T R
T
R
D
T
E
T
7
1 0 1 0 0 0 0 0 0 x x x x x x x x 0 x x x x x x x x 0
1 0 1 0 0 0 0 1 0 x x x x x x x x 8
9
X
A
A
A
A M
L
F
C
C
C
C S
S 10
P
K
K
K
K B
B
11
<---- DATA WORD 1 --12
->
13
14
15
H
A
A
N S
16
O
C
C
A T
S
K
K
C O
17
T
K P
18
x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 1
19
X M
L
M
L
M
L
F S
S
S
S
S
S
20
P B
B
B
B
B
B
21
<---- DATA WORD n-1<----- DATA WORD n --<----- CRC-8 ---->
22
---->
->
23
Figure 24 XFP READ OPERATION PACKET ERROR CHECKING
24
25
26
4.5.7 WRITE OPERATIONS (BYTE WRITE)
27
A write operation requires an 8-bit data word address following the device 28
address write word (10100000) and acknowledgement Figure 25. Upon
29
receipt of this address, the XFP shall again respond with a zero (ACK) toacknowledge and then clock in the ﬁrst 8 bit data word. Following the re- 30
ceipt of the 8 bit data word, the XFP shall output a zero (ACK) and the host 31
master must terminate the write sequence with a STOP condition for the 32
write cycle to begin. If a START condition is sent in place of a STOP con- 33
dition (i.e. a repeated START per the I2C speciﬁcation) the write is aborted 34
and the data received during that operation is discarded. Upon receipt of 35
the proper STOP condition, the XFP enters an internally timed write cycle, 36tWR, to internal memory. The XFP disables it’s management interface
37
input during this write cycle and shall not respond or acknowledge subse38
quent commands until the write is complete. Note that I2C “Combined
39
Format” using repeated START conditions is not supported on XFP write
40
commands.
41
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XFP 2-Wire Interface Protocol

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1
2
< ---- XFP ADDRESS <--- MEMORY ADDRESS<-------- DATA WORD ----3
-->
-->
->
4
S
L
M
L
M
L W
HOST
S M
T 5
S
S
S
S
S R
T S
O
B
B
B
B
B I
A B
P 6
T
R
E
T
7
1 0 1 0 0 0 0 0 0 x x x x x x x x 0 x x x x x x x x 0
8
9
XFP
A
A
A
C
C
C
10
K
K
K
11
12
13
Figure 25 XFP Write Byte Operation
14
15
4.5.8 WRITE OPERATIONS (SEQUENTIAL WRITE)
16
17
XFP’s shall support up to a 4 sequential byte write without repeatedly
sending XFP address and memory address information. A “sequential”
18
write is initiated the same way as a single byte write, but the host master 19
does not send a stop condition after the ﬁrst word is clocked in. Instead,
20
after the XFP acknowledges receipt of the ﬁrst data word, the host can
21transmit up to three more data words. The XFP shall send an acknowledge after each data word received. The host must terminate the sequen- 22
tial write sequence with a STOP condition or the write operation shall be 23
aborted and data discarded. Note that I2C “combined format” using re24
peated START conditions is not supported on XFP write commands.”
25
26
.
27
28
< ---- XFP<--- MEMORY<------ DATA<------ DATA WORD 2<------ DATA<------ DATA29ADDRESS --->ADDRESS -->WORD 1 ------>------>
WORD 3 ------>
WORD 4 ------>
H S M
L W
M
L
M
L
M
L
M
L
M
L
S 30
O T S
S R
S
S
S
S
S
S
S
S
S
S
T
31
S A B
B I
B
B
B
B
B
B
B
B
B
B
O
T R
T
P 32
T
E
33
1 0 1 0 0 0 0 0 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0
34
X
A
A
A
A
A
A
35
F
C
C
C
C
C
C
P
K
K
K
K
K
K
36
37
38
Figure 26 XFP Sequential Write Operation
39
40
41
42
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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

4.5.9 WRITE OPERATION PACKET ERROR CHECKING

H
O
S
T

X
F
P

H
O
S
T

X
F
P

1
All types of Write operations will use the same packet error checking tech- 2
3nique (when enabled) as follows.
4
The form of the write transfer for packet error checking will include the5number of bytes to be transferred as shown in Figure 27. After the host 6
transmits the 1 to 4 Bytes of data Write operation and receives an ACK
7from the module, as in normal Write operation the host will further trans8
mitted a CRC-8 value. The CRC-8 value is calculated based on thestarting memory address followed by the number of bytes and then the 1 9
to 4 Bytes in the order they are transmitted. Following the CRC-8 value, 10
the host will transmit a dummy byte: CAB (CRC Add-on Byte).
1112< ---- XFP ADDRESS<--- MEMORY<--- NUMBER OF<------ DATA WORD 1 --<------ DATA WORD 2 --13--->
ADDRESS -->BYTES--->
--->
--->
14
S M
L W
M
L
M
L
M
L
M
L
15
T S
S R
S
S
S
S
S
S
S
S
A B
B I
B
B
B
B
B
B
B
B
16
R
T
T
E
17
1 0 1 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 0 0 0 x x 0 x x x x x x x x 0 x x x x x x x x C
18
o
n 19
t
. 20
21
A
A
A
A
C
C
C
C
22
K
K
K
K
23
24
<------ DATA WORD 3 --<------ DATA WORD 4 --<------ CRC-8 VALUE --<------ CAB ------>
--->
--->
--->
25
26
M
L
M
L
M
L
M
L
S
S
S
S
S
S
S
S
S
T
27
B
B
B
B
B
B
B
B
O
P
28
0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x ** XFP Responds with an
29
ACK (0) if CRC-8 is
CORRECT and a NACK
A
A
A
A
30
(1) if the CRC-8 isC
CCC
INCORRECT.
K
K
K
K
31
32
33
Figure 27 XFP Write Operation Packet Error Checking
34
35
36
The XFP module will calculate the validity of the received Write data andAddress based on the CRC-8. If the CRC-8 data is correct, the write will 37
be accepted and the module will respond to the CAB with an ACK after 38
39which the host will issue a STOP. If the CRC-8 data is incorrect, themodule shall reject the write and respond with a NACK after which the40
host will issue a STOP.
41
42

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REVISON 4.5

XFP 2-Wire Interface Protocol

August 31, 2005

A CRC-8 should not be appended to a Dummy Write used in a Random
Read since the subsequent Read will conﬁrm the address in its CRC8.Only writes of 1-4 bytes are supported. Any transaction that does notfollow the protocol described in this section will result in an unpredictable
response from the module when PEC is enabled

1
2
3
4
5
6
4.5.10 WRITE OPERATIONS (ACKNOWLEDGE POLLING)
7
Once the XFP internally timed write cycle has begun (and inputs are being
ignored on the bus) acknowledge polling can be used to determine when 8
the write operation is complete. This involves sending a START condition 910followed by the device address word. Only if the internal write cycle iscomplete shall the XFP respond with an acknowledge to subsequent com- 11
mands, indicating read or write operations can continue.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
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REVISON 4.5

Management interface

August 31, 2005

1
2
3
4
5
This chapter deﬁnes the operation of the XFP 2-wire serial interface which6
is used for serial ID, digital diagnostics, and certain control functions. The
72-wire serial interface is mandatory for all XFP modules. It is modeled
largely after the digital diagnostics monitoring interface proposed for the 89
SFP and GBIC optical transceivers and deﬁned in SFF draft document
SFF-8472 Rev 9.3, which in turn is an extension of the original serial ID 10
systems deﬁned for the GBIC and SFP transceivers. One major differ11
ence, however, is that the memory structure is changed to use a single 2- 12
wire interface address.
13
The structure of the memory map is shown in Figure 28. The normal 256 14
15
Byte I2C address space is divided into lower and upper blocks of 128
16
Bytes. The lower block of 128 Bytes is always directly available and isused for the diagnostics and control functions described in this document 17that must be accessed repeatedly. One exception to this is that the stan- 18
dard module identiﬁer Byte deﬁned in the GBIC and SFP is located in Byte
19
0 of the memory map (in the diagnostics space) to allow software devel20
oped for multiple module types to have a common branching decision
point. This Byte is repeated in the Serial ID section so that it also appears 21
22
in the expected relationship to other serial ID bits.
23
Multiple blocks of memories are available in the upper 128 Bytes of the 24
address space. These are individually addressed through a table select 25
Byte which the user enters into a location in the lower address space.
26
Thus, there is a total available address space of 128 * 256 = 32Kbytes in27
this upper memory space.
28
29
The upper address space tables are used for less frequently accessed
functions such as serial ID, user writable EEPROM, reserved EEPROM 30
and diagnostics and control spaces for future standards deﬁnition, as well 31
as ample space for vendor speciﬁc functions. These are allocated as fol32
lows:
33
34
• Table 00h: Reserved for future diagnostic and control functions
35• Table 01h: Serial ID EEPROM
36• Table 02h: User writable EEPROM
37• Table 03h – 7Fh:Vendor speciﬁc functions
38
39• Table 80h – FFh:Reserved
40
41
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REVISON 4.5

128-

Reserved
for Future
Diagnostic
Functions

255

Table 00h

XFP MSAManagement interface

August 31, 2005

The details of each memory space are described in the sections that1
follow. All 2-Wire registers are read with bit 7 the MSB ﬁrst. Nomenclature 2
for all registers more than 1 bit long are MSB-LSB.
34562-Wire Serial Address
71010000X (A0H)
08
9Digital10Diagnostic
11
Functions
12
118
13
119-122
4 Byte Password Change
14126
4 Byte Password Entry
15
16
Page Select Byte Entry
127
17
18
19
20
21
12812812812822
23
XFP MSA
User
Vendor24
Serial ID
EEPROM
SpeciﬁcReserved
25
Data
Data
Functions
26
223
27
224- Vendor Speciﬁc
28
ID Data
255
255
255
255
29
Table 01h
Table 02h
Table 03h-7FhTable 80h-FFh30
31
Figure 28 2-wire Serial Digital Diagnostic Memory Map
32
33
The memory structure also provides for an optional password entry loca- 34
tion in the lower memory space that may be used to protect vendor in35
ternal functions or user writable memory. Passwords shall not be required 36
to read any serial ID or diagnostics information in the lower memory ad- 37
dress space or in Tables 00h – 02h. Nor shall passwords be required to38
write any controls deﬁned in the digital diagnostic functions described in39
this document. Passwords may be used by vendors to control write access to MSA deﬁned read only data for factory setup, or to OEMs to limit 40
write access in the User EEPROM Table (02h). Finally, passwords may be 41
42
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REVISON 4.5

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August 31, 2005

used to control read or write access to the vendor speciﬁc tables 03h –
7Fh.

1
2
3
Separate Passwords value ranges will be deﬁned for host vendor pass4
words and module vendor passwords to prevent accidental writing into
critical module control areas by the host vendor. Details are deﬁned in 5.5. 5
6
Note: Unless speciﬁcally noted, all informative ID ﬁelds must be ﬁlled out. 7
Using a value of 0 to indicate a ﬁeld is unspeciﬁed (as is common in the 8
SFP deﬁnition) is not permitted.
9
10
11
12
5.0.1 APPLICABLE DOCUMENTS
13
Digital Diagnostic Monitoring Interface for Optical Transceivers SFF doc14
ument number: SFF-8472, rev. 9.3 August 4, 2002.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
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REVISON 4.5

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August 31, 2005

5.1 DESCRIPTION OF LOWER MEMORY MAP: CONTROL FUNCTIONS, DIAGNOSTICS, TABLE ACCESS

1
The lower 128 Bytes of the 2-wire serial bus address space is used to ac- 2
cess a variety of measurements and diagnostic functions, to implement a 3
set of control functions, and ﬁnally to select which of the various upper4
memory map tables are accessed on subsequent reads. This portion of 5
the address space is always directly addressable and thus is chosen for 6
diagnostics and control functions that may need to be repeatedly ac7
cessed.
8
Table 31 shows the general memory map of the lower 128 Byte address 9
10
space.
11
12
13
Table 31 Lower Memory Map
14
Byte Address
Description
15
16
0
Identiﬁer (1 Byte)
17
1
Signal Conditioner Control
18
2-57
Threshold Values used for Alarm and Warning Flags
19(56 Bytes)
20
58-59
Optional VPS Control Registers(2 Byte)
21
22
60-69
Reserved (10 Bytes)
23
70-71
BER Reporting
24
72-75
Wavelength Control Registers (4 Bytes)
25
76-79
FEC control Registers (4 Bytes)
26
27
80-95
Flags and Interrupt Control (16 Bytes)
28
96-109A/D readout (14 Bytes)
29
110-111
General Control/Status bits (2 Bytes)
30
112-117
Reserved (6 Bytes)
31
32
118
Serial Interface Read/Write Error Checking (1 Bytes)
33
119-122
Password Change Entry Area (Optional) (4 Bytes)
34
123-126
Password Entry Area (optional) (4 Bytes)
35
36
127
Page Select Byte
37
38
39
40
41
42

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REVISON 4.5

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August 31, 2005

5.2 IDENTIFIER

1
Byte 0 of the lower memory map contains the module identiﬁer value. The 2
identiﬁer value speciﬁes the physical device described by the serial ID in- 3
formation. This value is also included in the serial ID data table (01h). The 4
deﬁned identiﬁer values are shown in Table 32. The XFP transceiver
5
should use identiﬁer 06h.
678Table 32 Identiﬁer values Byte 128
9
10
Value
Description of Physical Device
1100h
Unknown or unspeciﬁed
12
13
01h
GBIC
14
02h
Module/connector soldered to motherboard
15
03h
SFP
16
17
04h
300 pin XBI
1805h
XENPAK
19
06h
XFP
20
07h
XFF
21
22
08h
XFP-E
23
09h
XPAK
24
0Ah
X2
25
0Ah-7Fh
Reserved
26
27
80h-FFh
Vendor speciﬁc
28
29
30
5.3 SIGNAL CONDITIONER CONTROL
31
The XFP MSA deﬁnes two modes of transmitter signal conditioner opera- 32
tion. The default mode, which must be included in all XFP implementa33
tions, uses a REFCLK which need not be synchronous with the data and 34
with relatively loose jitter requirements. This mode is generally intended 35
for Clock and Data Recovery techniques for retiming the transmitter data.
36
An optional mode is deﬁned whereby the host system provides a synchronous REFCLK with relatively tight frequency and jitter requirements. This 37
mode is intended to allow the use of a Clock Multiplication (CMU) based 38
retiming scheme. The electrical requirements for these modes are deﬁned 39
in Section 3.10.
40
41
42
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REVISON 4.5

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In order to select between these modes in modules which implement
1
both, a control bit is deﬁned in Byte 1, bit 0, as shown in Table 34. This bit 2
shall power up with a value of 0 corresponding to the default asynchro3
nous clock mode. The host system may switch the XFP module to the syn4chronous clock mode by writing a value of 1 into this bit.
5
An identiﬁer bit indicating the availability of this capability is deﬁned in the 67
Serial ID Page in Byte 221, Bit 0 Page 01h. XFP modules not implementing the optional REFCLK mode shall not have a writable bit in this lo- 8
cation and should report a value of 0 when read.
910
In order to accommodate signal conditioner devices with limited tuning
11
range, host system shall inform the XFP module of the data rate. The
12
data rate is written into the upper 4 bits of Byte 01h. The value to beentered are given by:
13
14
Byte 01h[bits 7-4] = INT((Data Rate(Gb/s) - 9.5)/0.2))
1516This covers a range of 9.5-12.5 Gb/s. Thus for example, for 10.3 Gb/s, Bits
17
7-4 are 0100b.
18
19
The signal conditioner may optionally support two different loopback
modes which may be useful for various diagnostics needs.
20
21
The ﬁrst of these modes is known as XFI Loopback. In this mode, which 22
is set by writing a 1 into Bit 1 of Byte 1 of the lower memory map, data
23
input on the TX pins of the XFP module are retimed and output on the RX
pins of the module. Optical data is not transmitted or received when in the 24
XFI Loopback mode. This control bit will power up and reset to 0 resulting 25
26
in normal operation.
27
The second loopback mode is known as Lineside Loopback. In this mode, 28
which is set by writing a 1 into Bit 2 of Byte 1 of the lower memory map,
29
data received on the XFP module receiver is retimed and output on optical30transmitter. This optical data is not present on the electrical interface inthis mode. This control bit will power up and reset to 0 resulting in normal 31
32
operation.
33
Support for these loopback modes is indicated in the serial ID memory34
map in Byte 164 (CDR Support). Simultaneous operation of both loop35
back modes are not supported.
36
37
38
39
40
41
42
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REVISON 4.5

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August 31, 2005

5.4 2-WIRE SERIAL INTERFACE CHECKSUM

1
XFP modules shall support selectable packet error checking. Packet error 2
checking is deﬁned in Section 4.5.6 and 4.5.9. Packet error checking is 3
enabled by setting Bit 0 of Byte 118 to 1 (see Table 43), and disabled by 4
setting it to 0. Bit 0 will default to 0 on power-up or reset.
5678
5.5 TABLE SELECTION AND PASSWORD ENTRY (TABLE 44)
9
Access to information in the various upper memory address tables is pro10
vided by the use of a Table Select Byte in Byte 127 of the lower memory
map. The Table Select Byte is both readable and writable and shall default 11
on power-up or reset to 01h [Serial ID memory space]. The user may write 12
13other table numbers into Byte 127 before subsequent read/writes into
those spaces. The current Table Select Byte value will be retained until
14
power down, reset, or rewritten by host.
15
16
If the host attempts to write a table select value which is not supported in
17
a particular module, the table select byte will revert to 01h.
18
Bytes 123-126 are reserved for an optional password entry function. The 19
Password entry bytes are write only and will be retained until power down, 20
reset, or rewritten by host.
21
22
This function may be used to control read/write access to vendor speciﬁc
23
tables 03h – 7Fh. Additionally, module vendors may use this function to
implement write protection of Serial ID and other MSA read only informa- 24
tion. Passwords may be supplied to and used by Host manufacturers to 25
26
limit write access in the User EEPROM Table (02h).
27
Password access shall not be required to access MSA deﬁned data in the 28
lower memory space or in Tables 00h – 02h. Note that multiple module29
manufacturer passwords may be deﬁned to allow selective access to read30
or write to various sections of memory as allowed above.
31
Host manufacturer and module manufacturer passwords shall be distin- 32
guished by the high order bit (bit 7, Byte 123). All host manufacturer pass- 33
words shall fall in the range of 00000000h to 7FFFFFFFh, and all module 34
manufacturer passwords in the range of 80000000h to FFFFFFFFh. Host 35
manufacturer passwords shall be initially set to 00001011h in new mod36
ules. Host manufacturer passwords may be changed by writing a new
37
password in Bytes 119-122 when the correct current Host manufacture
password has been entered in 123-126, with the high order bit being ig- 38
39
nored and forced to a value of 0 in the new password.
40
The password entry ﬁeld shall be set to 00000000h on power up and41
reset.
42
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REVISON 4.5

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August 31, 2005

5.6 BASIC MONITORING FUNCTIONS

1
The basic measured quantities are transceiver temperature, TX bias cur- 2
rent, TX output power, received optical power, and two additional quanti- 3
ties which are deﬁned in Byte 222 of the Serial ID table (Table 01h).
4
5
Measured parameters are reported in 16 bit data ﬁelds, i.e., two concate- 6
nated bytes. These are shown in Table 41. The 16 bit data ﬁelds allow for
7
wide dynamic range. This is not intended to imply that a 16 bit A/D system
is recommended or required in order to achieve the accuracy goals stated 8
below. The width of the data ﬁeld should not be taken to imply a given level 9
10of precision. It is conceivable that the accuracy goals herein can beachieved by a system having less than 16 bits of resolution. It is recom- 11
mended that any low-order data bits beyond the system’s speciﬁed accu- 12
racy be ﬁxed at zero. Overall system accuracy and precision will be vendor
13
dependent.
14
To guarantee coherency of the diagnostic monitoring data, the host is re- 15
quired to retrieve any multi-byte ﬁelds from the diagnostic monitoring data 16
structure (IE: Rx Power MSB – byte 104, Rx Power LSB – byte 105) by the 17
use of a single two-byte read sequence across the 2-wire serial interface. 18
19
The transceiver is required to insure that any multi-byte ﬁelds that are up20
dated with diagnostic monitoring data (IE: Rx Power MSB – byte 104, Rx
Power LSB – byte 105) must have this update done in a fashion that guar- 21
antees coherency and consistency of the data. In other words, the update 22of a multi-byte ﬁeld by the transceiver must not occur such that a partially 23
updated multi-byte ﬁeld can be transferred to the host. Also, the trans24
ceiver shall not update a multi-byte ﬁeld within the structure during the25
transfer of that multi-byte ﬁeld to the host, such that partially updated data
26
would be transferred to the host.
27
Accuracy requirements speciﬁed below shall apply to the operating signal 28
range speciﬁed in the relevant standard. The manufacturer’s speciﬁcation 29
should be consulted for more detail on the conditions under which the ac- 30
curacy requirements are met.
31
32
Measurements are calibrated over vendor speciﬁed operating tempera33
ture and voltage and should be interpreted as deﬁned below. Alarm and34
warning threshold values should be interpreted in the same manner as
35real time 16 bit data.
36• Internally measured transceiver temperature. Represented as a 1637
bit signed twos complement value in increments of 1/256 degrees
38
Celsius valid between –40 and +125C. Temperature accuracy is ven39
dor speciﬁc but must be better than +/-3 degrees Celsius over speci40
ﬁed operating temperature and voltage. Please see vendor
41
42

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REVISON 4.5

Management interface

•

•

•

•

•

XFP MSA

August 31, 2005

speciﬁcation for details on location of temperature sensor. Tempera- 1
ture in degrees Celsius is given by the signed two’s complement val- 2
ue with LSB equal to 1/256 C.
3
Measured TX bias current in µA. Represented as a 16 bit unsigned
4
integer with the current deﬁned as the full 16 bit value (0 – 65535)
5with LSB equal to 2 µA, yielding a total measurement range of 0 to
6
131 mA. Accuracy is vendor speciﬁc but must be better than +/-10%
7of the manufacturer’s nominal value over speciﬁed operating temper8
ature and voltage.
9
Measured TX output power in mW. Represented as a 16 bit unsigned
integer with the power deﬁned as the full 16 bit value (0 – 65535) with 10
11
LSB equal to 0.1 µW, yielding a total measurement range of 0 to
12
6.5535 mW (~ -40 to +8.2 dBm). Data is assumed to be based on
measurement of laser monitor photodiode current. It is factory cali13
brated to absolute units using the most representative ﬁber output
14
type. Accuracy is vendor speciﬁc but must be better than +/- 2dBover 15
speciﬁed temperature and voltage. Reported measurement values
16
must maintain +/-1dB relative accuracy over the speciﬁed tempera17
ture and voltage range over the life of the product into a ﬁxed mea18
surement system.Data is not valid when the transmitter is disabled.
Measured RX received optical power in mW. Value can represent ei- 19
20
ther average received power or OMA depending upon how bit 3 ofbyte 220 (Table 01h) is set. Represented as a 16 bit unsigned integer 21
with the power deﬁned as the full 16 bit value (0 – 65535) with LSB
22equal to 0.1 µW, yielding a total measurement range of 0 to 6.5535
23mW (~ -40 to +8.2 dBm). Absolute accuracy is dependent upon the 24
exact optical wavelength. For the vendor speciﬁed wavelength, accu25
racy shall be better than +/-2 dB over speciﬁed temperature and volt26
age. This accuracy shall be maintained for input power levels up to
the lesser of maximum transmitted or maximum received optical pow- 27
28
er per the appropriate standard. It shall be maintained down to theminimum transmitted power minus cable plant loss (insertion loss or 29
passive loss) per the appropriate standard. Absolute accuracy be30
yond this minimum required received input optical power range is
31
vendor speciﬁc. Reported measurement values must maintain +/32
1dB relative accuracy over the above received power range andspeciﬁed temperature and voltage ranges over the life of the product 33
34
using a ﬁxed test source ﬁber.
Up to two Auxiliary Measurements may be implemented by the ven- 35
dor. The auxiliary monitoring channels, if any, are deﬁned in Byte 222 36
of Table 01h. That table also details the units which should be used in 37
reporting the corresponding values.
38
Internally measured transceiver supply voltage. Represented as a 16 39
bit unsigned integer with the voltage deﬁned as the full 16 bit value (0 40– 65535) with LSB equal to 100 µVolt, yielding a total measurement 41
range of 0 to +6.55 Volts. Practical considerations to be deﬁned by
42
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transceiver manufacturer will tend to limit the actual bounds of the
supply voltage measurement. Accuracy is vendor speciﬁc but must
be better than ±3% of the manufacturer’s nominal value over speciﬁed operating temperature and voltage.

12
3
4
Each A/D quantity has a corresponding high alarm, low alarm, high5
warning and low warning threshold. These factory-preset values allow the 6user to determine when a particular value is outside of “normal” limits as
7determined by the transceiver manufacturer. It is assumed that thesevalues will vary with different technologies and different implementations. 8
These values are stored in read-only memory in Bytes 2 – 57 as shown in 9
10
Table 35.
11
The values reported in the Alarm and Warning Thresholds area may be 12
typical values at some chosen nominal operating conditions and may be
13
temperature compensated or otherwise adjusted when setting warning14
and/or alarm ﬂags. Any compensation or adjustment is vendor speciﬁc
15
and completely optional. If temperature compensation or other adjust16
ment takes place, the corresponding alarm and warning ﬂags may not
match the result of a comparison performed by the host using the reported 17
Auxiliary Measurement diagnostic data and thresholds.
18
19
A set of alarm and warning ﬂags are implemented. The ﬂags are latched
20
and detailed in the Interrupt Control Descriptions. These ﬂags indicate
when the various monitored quantities are above or below the thresholds. 21
For users who do not wish to set their own threshold values or read the 22
values in locations 2 - 57, the ﬂags alone can be monitored. Two ﬂag types 23
are deﬁned:
24251) Alarm ﬂags associated with transceiver temperature, supply voltage,
26
TX bias current, TX output power and received optical power as well as
reserved locations for future ﬂags. Alarm ﬂags indicate conditions likely to 27
28
be associated with a faulty link and cause for immediate action.
292) Warning ﬂags associated with transceiver temperature, supply voltage, 30
TX bias current, TX output power and received optical power as well as 31
reserved locations for future ﬂags. Warning ﬂags indicate conditions out- 32
side the normally guaranteed bounds but not necessarily causes of imme33
diate link failures. Certain warning ﬂags may also be deﬁned by the
manufacturer as end-of-life indicators (such as for higher than expected 34
35bias currents in a constant power control loop).
36
5.7 OPTIONAL VARIABLE POWER SUPPLY (VPS) CONTROL
37
38
To facilitate the power/current savings of deep-submicron CMOS processes, the XFP speciﬁcation deﬁnes modules that optionally support a 39
VCC2 supply lower than 1.8-V. These modules are intended for use in40
systems employing a variable power supply (VPS). In the default mode, 41
which must be included in every XFP compliant implementation, the42
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August 31, 2005

module is supplied and can operate normally with a 1.8-V voltage on its
VCC2 pins.

1
2
3
An XFP module might include a discrete or integrated regulator, which
4supplies the CMOS ICs with a voltage lower than 1.8-V by stepping down
the VCC2 supply. The module powers up in the default mode of operation 5
6capable of operating normally with 1.8-V on the VCC2 pins.
7
In the ﬁrst optional mode (“operational LV regulator mode”) the regulator 8
is still operational but the host system supplies the module with a VCC2 9voltage lower than +1.8-V. In the second optional mode (“bypassed regu- 10
lator mode”) the regulator is bypassed and the CMOS ICs are connected11
directly to the VCC2 pins of the module. Serial ID Byte 221 (Table 01h),
bit 7 indicates if optional VPS is implemented. VPS control registers are 12
13
located in Bytes 58-59 as deﬁned in the Table 33.
1415
16
Table 33 VPS Fields
17
18
Byte
Bit
Name
Description
19
58
7-4
Lowest Voltage Supported with an Operational LV
Read Only
20
Regulator
See Note 1, 2
21
58
3-0
Voltage Supplied on the VCC2 Pins.
Read Write. Powers up to 0000b.
22
See Note 1.
23
59
7-4
Voltage Supported with a Bypassed Regulator.
Read Only.
24
See Note 1.
25
59
3-1
Reserved
2627
59
0Regulator bypass mode0b = Mode disabled. Powers up to 0b.
1b = Mode enabled
28
29
1. The values in these ﬁelds are unsigned 4-bit binary integers (INT[3:0]. To translate to absolute voltage use: V[absolute] = (1.8 V)(INT[3:0])*(0.1-V).
30
2. Any XFP compliant module supporting the optional LV regulator mode should be operational with any power supply voltage between
31
1.8 V and the value signiﬁed on Byte58, Bits 7-4.
32
33
34
35
Modules which implement an optional voltage mode must monitor the36
VCC2 rail as part of the Auxiliary Monitoring described in sections 5.42. 37
38
When a host selects one of the optional voltage modes, the module will39
automatically adjust the appropriate threshold and alarm register values
40
described in Table 35. The module will issue an Interrupt if the Vcc2
41
voltage is ever outside the acceptable range.
42
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REVISON 4.5

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When a host selects one of the optional voltage modes, power and current 1
requirements of the module should scale at least linearly with voltage (this 2
assumption is made to simplify the speciﬁcation - in most cases power3
savings will be larger than linear). Implementing these optional modes en4
ables a module to fall into two classes of power dissipation according to
the mode of operation. However, when a module is switched to one of the 5optional modes it will not change the values in Table 54. The host can use 6
the default values in Table 54 to calculate the minimum power savings of 7
the optional modes.
89
All voltage setting changes should take place when the module is in the 10
low power, stand-by mode (i.e. P_Down pin is held high). The 2-wire serial
11
bus and XFP interface signals must remain fully functional during voltage
setting changes, and the falling edge of P_Down should not reset these 12
13changes. To achieve the lowest power operation under any condition a14
host supporting an optional voltage mode should hold the P_Down pinhigh on empty module sockets.
15
16
To enable the “operational LV regulator mode” the following sequence
17
must occur:
18
19
1. Host sets the module into the stand-by mode by holding the
P_Down/RST pin asserted. During stand-by mode the module trans- 20
mitter should be disabled.
21
2. Host reads the content of Byte 58 and 59 to determine the most de- 22
sirable setting for VPS and changes the voltage on VCC2 pins of the 23
XFP connector.
24
25
3. Host then writes Bits 3-0 of Byte58 to indicate the new voltage and26
module updates settings in Table 35.
4. When P_Down is de-asserted module veriﬁes the voltage on VCC2 27
is within range. If voltage is within range, module enables all circuitry 28
29
within the module and resumes with normal operation. If voltage is
not within range, module sets the appropriate voltage monitoring In- 30
terrupt bit to inform the host and asserts Mod_NR.
31
To enable the “bypassed regulator mode” the host should follow the se- 32
quence described above, with the only difference that bit 0 of Byte 59 is 33
written to 1b in step 3.
34
35
To return the module to the default mode (VCC2=1.8-V) the host must as36
sert P_Down and return the R/W ﬁelds of Bytes 58 and 59 to their default
37
values.
38
In modules that implement both optional modes the value written in Byte 39
58 takes precedence over the value written in Byte 59, i.e. if both of Byte 40
58, bits 3-0 and Byte 59, bit 0 are non-zero the module will be in “opera- 41
tional LV regulator mode”.
42
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REVISON 4.5

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Two identiﬁer bits indicating the availability of these optional modes are 1
deﬁned in the Serial ID Page in Byte 221, Bits 3-4 Page 01h. Bit 4 corre- 2
sponds to the availability of the “operational LV regulator mode”. Bit 3 cor- 3
responds to the availability of the “bypassed regulator mode”. XFP
4modules not implementing these optional modes will return 0 from these5locations as well as from all ﬁelds of bytes 58-59.
67
8
5.8 SYSTEM BER REPORTING
9
A host system implementing a forward error correction device can report 10
receive BER. The 2-Wire host management interface can transfer FEC re- 11
ported BER data to the XFP module. The module may use this information 12
to improve system BER. Implementation of BER Reporting functions is in- 13
dicated in Serial ID Byte 220 (Table 01h), bit 4. Control registers are lo14
cated in Bytes 70 and 71 (see Table 36).
15
Byte 70 requests the desired level of BER from the XFP module. Byte 71 16
reports the FEC actual BER to the XFP module. The data format for Byte 17
70 it is given by:
18
19
20
21
Byte ( 70 ( MSB – 4bits ) )– [ Byte ( 70 ( LSB – 4bits ) ) ]22
BER = ----------------------------------------------------------- ×10
16
23
24
Similarly for byte 71 is given by:
25
26
27
28
Byte ( 71 ( MSB – 4bits ) )– [ Byte ( 71 ( LSB – 4bits ) ) ]29
BER = ----------------------------------------------------------- ×10
1630
31
MSB-Octet is the decimal value of the 4 MSB bits. LSB-Octet is the dec- 32
imal value of the 4 LSB bits. If byte 71 reports Hexadecimal value of 4C 33
then the BER would be 0.25x10E-12.
34
35
36
37
5.9 WAVELENGTH CONTROL
38
This section of memory includes registers (Table 37) that allow the imple39
mentation of a wavelength tunable XFP module. Implementation of
wavelength tunability is indicated in Serial ID Byte 221 (Table 01h), bit 1. 40
Bytes 72-73 are used to input the desired wavelength setpoint in the same 41
42
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REVISON 4.5

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format described for XFP center wavelength in the Serial ID Byte 186-187(units of 0.05 nm). For a wavelength tunable module, the serial ID Bytes
for wavelength and tolerance will deﬁne the allowed tuning range. Inputs
to tuning control bytes 72-73 which are outside this range will be clippedto the allowed tuning range as deﬁned in the serial ID tuning range.

5.10 FEC CONTROLXFP MSA12345
Bytes 74 and 75 are optional monitor values that can be used to report the 6measured error between the actual wavelength and the entered setpoint. 7
It is a 16 bit signed 2’s complement value in units of 0.005. Thus:
89Reported Error [Bytes 74,75] =(Meas. Wavelength – Setpoint [Bytes
1072,73])*(0.005nm)
11
12
Finally, the latched ﬂag in Byte 85 bit 5 may be used to report a wave13
length error exceeding the manufacturer’s tolerance, and this condition
may be conﬁgured by the user as an interrupt trigger as described in the 14
Interrupt control section below.
15
16
17
18
19
In some forward error correction schemes, the host system may optimize
20
the sensitivity of an optical link or minimize the error rate by adjusting thephase and amplitude threshold for data quantization in the limiting ampli- 21
22
ﬁer section of the module receive path. Implementation of FEC control
functions is indicated in Serial ID Byte 221 (Table 01h), bit 2. Control reg- 23
isters are located in Bytes 76 and 77 (see Table 38).
24
25
Byte 76 is used to set the amplitude threshold of receive path quantiza- 26
tion. It is a 2's complement 7 bit value (-128 - +127), where the threshold27
is given by:
28
29
Amplitude Threshold = 50% + [Byte(76)/256] *100%
30
31
Similarly, Byte 77 is used to set the phase point in the eye diagram for
32
quantization, and is set in terms of unit interval relative to the eye center:
33
Phase setpoint = 0.5 UI + [Byte(77)/256] UI
34
35
36
37
38
39
40
41
42
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REVISON 4.5

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5.11 INTERRUPT SYSTEM LOGIC

1The XFP implements a real time hardware Interrupt pin (see 2.4) to alert 2
the host system to any condition outside normal operating conditions. In- 3
terrupt system logic may be triggered and latched by a set of ﬂags. These 4
include:5
6• Alarm and Warning ﬂags as described in the section on Basic Moni7
toring Functions. These correspond to monitored quantities going
8
outside factory programmed threshold values.
9• Flags corresponding to basic module status conditions including:
1011
12
TX_NR:
Any condition leading to invalid data on the 13
TX path
14
15
TX_Fault
Laser fault condition (same as TX_Fault in
SFP and GBIC)
16
17
TX CDR Unlocked:
Unlocked:Loss of Lock of TX side CDR
18
RX_NR:
Any condition leading to invalid data on the 19
RX path20
21
RX_LOS:
RX Loss of Signal (mirroring hardware
22
output pin)23
RX_CDR Unlocked: Unlocked:Loss of Lock of RX side CDR
24
25
MOD_NR:
Module Not Ready (mirroring hardware
26
output pin)27
• Flag indicating completion of the XFP Module Reset (as initiated by 28
29
power up or P_Down/RST pin)30
• Flags corresponding to optional extended capabilities including:31• APD Supply Fault
32• TEC Fault
33
34• Wavelength Unlocked Condition
35
36
Existence of any of these conditions shall lead to a latched ﬂag. These
ﬂags are located in Bytes 80 – 87 and are detailed in Table 39.
37
38
The presence of any 1 values in Bytes 80 – 87 will assert the hardware 39
Interrupt output pin (active low). When the Interrupt pin alerts the host40
system to a latched ﬂag condition, the host may query the latched ﬂag bitsin Bytes 80 – 87. The latched ﬂags are cleared on the read of the corre- 41
42

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REVISON 4.5

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sponding Byte. Thus a read of all Bytes from 80 – 87 can be used to reset 1
all latched ﬂags and deassert the hardware Interrupt output pin.
23
Because of the bytewise nature of the 2-wire serial bus reads, it is not pos4
sible to clear individual ﬂag bits. It is recommended that all latched ﬂag
5bits be read and cleared in the same operation.
6
The host system may control which ﬂags result in an Interrupt by setting 7
high individual bits from a set of masking bits in Bytes 88-95, and de8
scribed in Table 40. A 1 value in a masking bit prevents the assertion of 9
the hardware Interrupt pin by the corresponding latched ﬂag bit.
10
11
Masking bits should be volatile and startup with all unmasked (masking
12bits 0).
13
Hardware Interrupt Pin = Logical NOR of all (Latched Flag Bit AND 14
NOT Masking Bit)
15
16
The mask bits may be used to prevent continued interruption from on17
going conditions, which would otherwise continually reassert the hard18
ware Interrupt pin.
19
20
5.11.1 GENERAL CONTROL AND STATUS BITS
In order to allow virtually complete operation of the XFP module via the 2- 21
wire serial interface, a set of control and status bits are provided to mirror 22
the operation of key status and control pins. These are provided in Bytes 23
110-111 and are detailed in Table 42. All status bits except soft bits in this 24
set are dynamic (not latched)25
26
The bits fall into three categories:
27
28• Bits mirroring hardware status lines: TX-DIS, MOD_NR,
29
P_Down/RST, Interrupt, RX_LOS• Bits providing more speciﬁc information: TX_NR, RX_NR, TX and RX 30
31
CDR Loss of Lock, and TX Fault.
• A set of read/write bits which can be used to implement the optional 32
33“soft” control of TX-Disable and the Power-Down functions. (Described fully in Table 42). Availability of this option is deﬁned in Byte 34
221 (Table 01h).
35
36
37
38
39
40
41
42
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REVISON 4.5

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5.12 TIMING FOR SOFT CONTROL AND STATUS FUNCTIONS

Byte

Bit

1

7-4
3
2

1

0

XFP MSA

1
Detail timing for soft control and status functions are described in Table 45 2
3
accessible with the 2-wire Serial interface Chapter 4:.
4
5
6
Table 34 Signal Conditioner Control Field
7
Name
Description
8
9
Data Rate Control
Data Rate=9.5Gb/s + 0.2 * Value
10
Reserved
11
Lineside Loopback
0b=Normal Operation
12
1b=Loopback Module Optical Input to Output
13
14
XFI Loopback
0b=Normal Operation
1b=Loopback Module XFI Input to Output
15
16
Signal Conditioner Control
0b = Normal Asynchronous REFCLK mode17
1b = Optional Synchronous REFCLK mode
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
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REVISON 4.5

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August 31, 2005.

Table 35 Alarm and Warning Thresholds

XFP MSA

Address# Bytes

Name

02-03

2

Temp High Alarm

MSB at low address

04-05

2

Temp Low Alarm

MSB at low address

06-07

2

Temp High Warning

MSB at low address

08-09

2

Temp Low Warning

MSB at low address

10-17

8

Reserved A/D Flag Thresholds

Reserved A/D Flag Thresholds

18-19

2

Bias High Alarm

MSB at low address

20-21

2

Bias Low Alarm

MSB at low address

22-23

2

Bias High Warning

MSB at low address

24-25

2

Bias Low Warning

MSB at low address

26-27

2

TX Power High Alarm

MSB at low address

28-29

2

TX Power Low Alarm

MSB at low address

30-31

2

TX Power High Warning

MSB at low address

32-33

2

TX Power Low Warning

MSB at low address

34-35

2

RX Power High Alarm

MSB at low address

36-37

2

RX Power Low Alarm

MSB at low address

38-39

2

RX Power High Warning

MSB at low address

40-41

2

RX Power Low Warning

MSB at low address

42-43

2

AUX 1 High Alarm

MSB at low address

44-45

2

AUX 1 Low Alarm

MSB at low address

46-47

2

AUX 1 High Warning

MSB at low address

48-49

2

AUX 1 Low Warning

MSB at low address

50-51

2

AUX 2 High Alarm

MSB at low address

52-53

2

AUX 2 Low Alarm

MSB at low address

54-55

2

AUX 2 High Warning

MSB at low address

56-57

2

AUX 2 Low Warning

MSB at low address

Page 72

Description

Copyright © 2002-2005 by XFP MSA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
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Table 36 BER Control Fields
Byte

Bit

Name

Description

70

All

Acceptable BER

Acceptable BER Reported by the FEC to the Module

71

All

Actual BER

Actual BER Reported by the FEC to the Module

Table 37 Wavelength Control Fields
Byte

Bit

Name

Description

72 - 73

All

Wavelength Set MSB

User input of Wavelength setpoint. (Units of 0.05 nm)

74 - 75

All

Wavelength Error LSB

Monitor of Current Wavelength Error (Units of
0.005nm) [Signed 2’s complement value]

Table 38 FEC Control Fields

XFP MSA

Byte

Bit

Name

76

All

Amplitude Adjustment

Relative amplitude of receive quantization threshold

77

All

Phase Adjustment

Phase of receive quantization relative to 0.5 UI.

78-79

All

Reserved

Page 73

Description

Copyright © 2002-2005 by XFP MSA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
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Table 39 Latched Interrupt Flag Fields

XFP MSA

Address

# Bit

Name

80

7

L- Temp High Alarm

Latched high Temperature alarm.

80

6

L- Temp Low Alarm

Latched low Temperature alarm.

80

5Reserved

80

4

Reserved

80

3

L- TX Bias High Alarm

Latched high TX Bias alarm.

80

2

L- TX Bias Low Alarm

Latched low TX Bias alarm.

80

1

L- TX Power High Alarm

Latched high TX Power alarm.

80

0

L- TX Power Low Alarm

Latched low TX Power alarm.

81

7

L- RX Power High Alarm

Latched high RX Power alarm.

81

6

L- RX Power Low Alarm

Latched low RX Power alarm.

81

5

L- AUX 1 High Alarm

Latched high AUX1 monitor alarm.

81

4

L- AUX 1 Low Alarm

Latched low AUX1 monitor alarm.

81

3

L- AUX 2 High Alarm

Latched high AUX2 monitor alarm.

81

2

L- AUX 2 Low Alarm

Latched low AUX2 monitor alarm.

81

1

Reserved

81

0

Reserved

82

7

L- Temp High Warning

Latched high Temperature warning.

82

6

L- Temp Low Warning

Latched low Temperature warning.

82

5Reserved

82

4

Reserved

82

3

L- TX Bias High Warning

Latched high TX Bias warning.

82

2

L- TX Bias Low Warning

Latched low TX Bias warning.

82

1

L- TX Pow. High Warning

Latched high TX Power warning.

82

0

L- TX Pow. Low Warning

Latched low TX Power warning.

83

7

L- RX Pow. High Warning

Latched high RX Power warning.

83

6

L- RX Pow. Low Warning

Latched low RX Power warning.

83

5

L- AUX 1 High Warning

Latched high AUX1 monitor warning.

83

4

L- AUX 1 Low Warning

Latched low AUX1 monitor warning.

83

3

L- AUX 2 High Warning

Latched high AUX2 monitor warning.

83

2

L- AUX 2 Low Warning

Latched low AUX2 monitor warning.

83

1

Reserved

Page 74

Description

Copyright © 2002-2005 by XFP MSA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
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Table 39 Latched Interrupt Flag Fields

XFP MSA

Address

# Bit

Name

83

0

Reserved

84

7

L- TX_NR

Latched TX_NR Status

84

6

L- TX_Fault

Latched Laser Fault condition.
Generated by laser safety system.

84

5

L- TX CDR not Locked

Latched TX CDR Loss of Lock84

4

L- RX_NR

Latched RX_NR Status

84

3

L- RX_LOS

Latched mirror of RX_LOS pin (Receiver lossof optical signal)

84

2

L- RX CDR not Locked

Latched RX CDR Loss of Lock84

1

L- MOD_NR

Latched Mirror of MOD_NR pin

840

L- Reset Complete

Latched Reset Complete Flag

85

7

L- APD Supply Fault

Latched APD Supply Fault

85

6

L- TEC Fault

Latched TEC Fault

85

5

L- Wavelength Unlocked

Latched Wavelength Unlocked Condition

85

4-0

Reserved

86

7

L-VCC5 High Alarm

VCC5 High Alarm Flag

86

6

L-VCC5 Low Alarm

VCC5 Low Alarm Flag

86

5

L-VCC3 High Alarm

VCC3 High Alarm Flag

86

4

L-VCC3 Low Alarm

VCC3 Low Alarm Flag

86

3

L-VCC2 High Alarm

VCC2 High Alarm Flag

86

2

L-VCC2 Low Alarm

VCC2 Low Alarm Flag

86

1

L-Vee5 High Alarm

Vee5 High Alarm Flag

86

0

L-Vee5 Low Alarm

Vee5 Low Alarm Flag

87

7

L-VCC5 High Warning

VCC5 High Warning Alarm Flag

87

6

L-VCC5 Low Warning

VCC5 Low Warning Flag

87

5

L-VCC3 High Warning

VCC3 High Warning Flag

87

4

L-VCC3 Low Warning

VCC3 Low Warning Flag

87

3

L-VCC2 High Warning

VCC2 High Warning Flag

87

2

L-VCC2 Low Warning

VCC2 Low Warning Flag

87

1

L-Vee5 High Warning

Vee5 High Warning Flag

87

0

L-Vee5 Low Warning

Vee5 Low Warning Flag

Page 75

Description

Copyright © 2002-2005 by XFP MSA

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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
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August 31, 2005.

Table 40 Interrupt Masking Bits

XFP MSA

Address

# Bit

Name

88

7

M- Temp High Alarm

Masking bit for high Temperature alarm.

886M- Temp Low Alarm

Masking bit for low Temperature alarm.

88

5

Reserved

88

4

Reserved

88

3

M- TX Bias High Alarm

Masking bit for high TX Bias alarm.

882

M- TX Bias Low Alarm

Masking bit for low TX Bias alarm.

88

1

M- TX Power High Alarm

Masking bit for high TX Power alarm.

880M- TX Power Low Alarm

Masking bit for low TX Power alarm.

897

M- RX Power High Alarm

Masking bit for high RX Power alarm.

89

6M- RX Power Low Alarm

Masking bit for low RX Power alarm.

895

M- AUX 1 High Alarm

Masking bit for high AUX1 monitor alarm.

894M- AUX 1 Low Alarm

Masking bit for low AUX1 monitor alarm.

893

M- AUX 2 High Alarm

Masking bit for high AUX2 monitor alarm.

892M- AUX 2 Low Alarm

Masking bit for low AUX2 monitor alarm.

89

1

Reserved

89

0

Reserved

90

7

M- Temp High Warning

Masking bit for high Temperature warning.

90

6

M- Temp Low Warning

Masking bit for low Temperature warning.

90

5

Reserved

90

4

Reserved

90

3

M- TX Bias High Warning

Masking bit for high TX Bias warning.

90

2

M- TX Bias Low Warning

Masking bit for low TX Bias warning.

90

1

M- TX Pow. Hi Warning

Masking bit for high TX Power warning.

900

M- TX Pow. Low Warning

Masking bit for low TX Power warning.

91

7

M- RX Pow. Hi Warning

Masking bit for high RX Power warning.

91

6

M- RX Pow. Low Warning

Masking bit for low RX Power warning.

91

5

M- AUX 1 High Warning

Masking bit for high AUX1 monitor warning.

91

4

M- AUX 1 Low Warning

Masking bit for low AUX1 monitor warning.

91

3

M- AUX 2 High Warning

Masking bit for high AUX2 monitor warning.

91

2

M- AUX 2 Low Warning

Masking bit for low AUX2 monitor warning.

Page 76

Description

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5
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7
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10
11
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17
18
19
20
21
22
23
24
25
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28
29
30
31
32
33
34
35
36
37
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Table 40 Interrupt Masking Bits

XFP MSA

Address

# Bit

Name

91

1

Reserved

91

0

Reserved

92

7

M- TX_NR

Masking bit for TX_NR Status

92

6

M- TX_Fault

Masking bit for Laser Fault condition.

92

5

M- TX CDR not Locked

Masking bit for TX CDR Loss of Lock

92

4

M- RX_NR

Masking bit for RX_NR Status

92

3

M- RX_LOS

Masking bit for mirror of RX_LOS pin(Receiver optical loss of signal)

92

2

M- RX CDR not Locked

Masking bit for RX CDR Loss of Lock92

1

M- MOD_NR

Masking bit for Mirror of MOD_NR pin

920

M- Reset Complete

Masking bit for Reset Complete Flag

93

7

M- APD Supply Fault

Masking bit for APD Supply Fault

93

6

M- TEC Fault

Masking bit for TEC Fault

93

5

M- Wavelength Unlocked

Masking bit for Wavelength Unlocked Condition

93

4-0

Reserved

94

7

M-VCC5 High Alarm

VCC5 High Alarm Flag

94

6

M-VCC5 Low Alarm

VCC5 Low Alarm Flag

94

5

M-VCC3 High Alarm

VCC3 High Alarm Flag

94

4

M-VCC3 Low Alarm

VCC3 Low Alarm Flag

94

3

M-VCC2 High Alarm

VCC2 High Alarm Flag

94

2

M-VCC2 Low Alarm

VCC2 Low Alarm Flag

94

1

M-Vee5 High Alarm

Vee5 High Alarm Flag

94

0

M-Vee5 Low Alarm

Vee5 Low Alarm Flag

95

7

M-VCC5 High Warning

VCC5 High Warning Alarm Flag

95

6

M-VCC5 Low Warning

VCC5 Low Warning Flag

95

5

M-VCC3 High Warning

VCC3 High Warning Flag

95

4

M-VCC3 Low Warning

VCC3 Low Warning Flag

95

3

M-VCC2 High Warning

VCC2 High Warning Flag

95

2

M-VCC2 Low Warning

VCC2 Low Warning Flag

95

1

M-Vee5 High Warning

Vee5 High Warning Flag

95

0M-Vee5 Low Warning

Vee5 Low Warning Flag

Page 77

Description

Copyright © 2002-2005 by XFP MSA

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REVISON 4.5

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August 31, 2005

Table 41 A/D Values
Byte

Bit

Name

Description

Converted analog values. Calibrated 16 bit data.
96

All

Temperature MSB

97

All

Temperature LSB

98-99

All

100

All

TX Bias MSB

101

All

TX Bias LSB

102

All

TX Power MSB

103

All

TX Power LSB

104

All

RX Power MSB

105

All

RX Power LSB

106

All

AUX 1 MSB

107

All

AUX 1 LSB

108

All

AUX 2 MSB

109

All

AUX 2 LSBXFP MSAInternally measured module temperature.

Reserved
Internally measured TX Bias Current.

Measured TX output power.

Measured RX input power.

Auxiliary measurement 1 deﬁned in Byte 222 Page 01h

Auxiliary measurement 2 deﬁned in Byte 222 Page 01h

Page 78

Copyright © 2002-2005 by XFP MSA

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XFP Speciﬁcation
REVISON 4.5

Management interface

Byte

Bit

110

7

110

6

110

5

110

4

110

3

110

2

110

1

110

0

111

7

111

6

111

5

111

4

111

3

111

2-0

XFP MSA

August 31, 2005

1
2
Table 42 General Control/Status Bits
3
4
Name
Description
5
TX Disable State
Digital state of the TX Disable Input Pin. Updated within 100msec of change
6on pin.
7
Soft TX Disable
Optional read/write bit that allows software disable of laser. Writing '1' dis8
ables laser. Turn on/off time is 100 msec max from acknowledgement of
9
serial byte transmission. This bit is “OR”d with the hard TX_DISABLE pinvalue. Note, per SFP MSA TX_DISABLE pin is default enabled unless
10
pulled low by hardware. If Soft TX Disable is not implemented, the trans11
ceiver ignores the value of this bit. Default power up value is 0.
12
MOD_NR State
Digital state of the MOD_NR Pin. Updated within 100msec of change on
13
pin.
14
P_Down State
Digital state of the P_Down Pin. Updated within 100msec of change on pin.
15
Soft P_Down
Optional read/write bit that allows the module to be placed in the power
16
down mode. This is identical to the P_Down hardware pin function except
17that it does not initiate a system reset.
18
Interrupt
Digital state of the Interrupt output pin.
19
RX_LOS
Indicates Optical Loss of Signal (per relevant optical link standard). Updated
20
within 100msec of change on pin.
21
Data_Not_Ready
Indicates transceiver has achieved power up and A/D data is ready. Bit
22
remains high until data is ready to be read at which time the device sets the23
bit low.
24
TX_NR State
Identiﬁes Not Ready condition as speciﬁc to the TX path
25
TX_Fault State
Identiﬁes Laser fault condition (Generated by laser safety system)
26
27
TX_CDR not Locked
Identiﬁes Loss of Lock in TX path CDR
28
RX_NR State
Identiﬁes Not Ready condition as speciﬁc to the TX path
29
RX_CDR not Locked
Identiﬁes Loss of Lock in RX path CDR
30
Reserved
31
32
33
The Data_Not_Ready bit is high during module power up and prior to the 34
ﬁrst valid A/D reading. Once the ﬁrst valid A/D reading occurs, the bit is 35
set low until the device is powered down. The bit must be set low within 1 36
second of power up.
37
38
39
40
41
42
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

Management interface

August 31, 2005

Table 43 Packet Error Checking
Byte

Bit

Name

118

0

Error Checking

118

7-1

Reserved

Description
0 b = Disable Packet Error Checking
1b = Enable Packet Error Checking (see Section 4.5.6 and 4.5.9).

Table 44 Password and Table Select Entry Bytes
Byte

Bit

Name

Description

119-122All

New Password Entry

Location of Entry of New Optional Password

123-126

All

Password Entry

Location for Entry of Optional Password

127

All

Table SelectEntry Location for Table Select Byte

Table 45 I/O Timing for Soft Control & Status Functions
Parameter

Symbol

Min

Max

Unit

Conditions

ms

Time from TX_DIS bit set 1 until optical output falls below 10% of nominal

TX_DISABLE assert time

t_off

100

TX_DISABLE deassert time

t_on

100

ms

Time from TX_DISABLE bit cleared1 until
optical output rises above 90% of nominal

P_Down assert time

T_Pdown

100

ms

Time from P_Down bit set1 until module dissipation falls below 1.5W

P_Down deassert time

T_Pup

300

ms

Time from P_Down bit cleared1 until module
returns to normal operation.

RX_LOS assert time

t_los_on

100msTime from RX_LOS state to RX_LOS bit set

RX_LOS deassert time

t_los_off

100

msTime from non-LOS state to RX_LOS bit
cleared

MOD_NR assert time

t_NR_on100

ms

Time from TX_NR or RX_NR state to corresponding bit set

MOD_NR deassert time

t_NR_off

100

ms

Time from non-TX_NR or RX_NR state tocorresponding bit set

Analog parameter data readyt_data1000

ms

From power on to data ready, bit 0 of byte 110
set

1. Measured from falling clock edge after stop bit of write transaction.

XFP MSA

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REVISON 4.5

Management interface

August 31, 2005

5.13 DESCRIPTION OF UPPER MEMORY MAP TABLE 00H – FUTURE DIAGNOSTICS FUNCTIONS
Table 00h is reserved for future diagnostics functions.

5.14 DESCRIPTION OF UPPER MEMORY MAP TABLE 01H – SERIAL ID MEMORY MAP
The serial ID memory map located in Table 01h in the upper address
space is used for read only identiﬁcation information.

Table 46 Serial ID: Data Fields - Page 01h
AddressSize(Bytes)Name

Description
Base ID Fields

128

1

Identiﬁer

Type of serial transceiver (see Table 32)

1291Ext. Identiﬁer

Extended identiﬁer of type of serial transceiver (see Table 47)

1301Connector

Code for connector type (see Table 48)

138-1318

Transceiver

Code for electronic compatibility or optical compatibility(see Table 49)

1391

Encoding

Code for serial encoding algorithm (see Table 50)

1401BR-MinMinimum bit rate, units of 100 MBits/s.

141

1

BR-MaxMaximum bit rate, units of 100 MBits/s.

142

1

Length(SMF)-km

Link length supported for SMF ﬁber in km

143

1

Length (E-50µm)

Link length supported for EBW 50/125 µm ﬁber, units of 2 m

144

1

Length (50 µm)

Link length supported for 50/125 µm ﬁber, units of 1 m

145

1Length (62.5 µm)

Link length supported for 62.5/125 µm ﬁber, units of 1 m

146

1

Length (Copper)

Link length supported for copper, units of 1m

147

1

Device Tech

Device technology (see Table 51, Table 52)

163-148

16

Vendor name

XFP vendor name (ASCII)

164

1

CDR Support

CDR Rate Support (see Table 53)

167-165

3

Vendor OUIXFP vendor IEEE company ID

183-168

16

Vendor PN

Part number provided by XFP vendor (ASCII)

185-1842

Vendor rev

Revision level for part number provided by vendor (ASCII)

187-186

2

Wavelength

Nominal laser wavelength (Wavelength = value / 20 in nm)

XFP MSA

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August 31, 2005

Table 46 Serial ID: Data Fields - Page 01h

AddressSize(Bytes)

189-188

2

190

1

191

1

195-1924

211-19616219-212

8

220

1

221

1

222

1

223

1

255-224

32

5.15 IDENTIFIERXFP MSA

1
2
3
Name
Description
4
Wavelength Tolerance
Guaranteed range of laser wavelength (+/- value) from Nominal wave5
length. (Wavelength Tol. = value/200 in nm)
6
Max Case Temp
Maximum Case Temperature in Degrees C.
7
8
CC_BASE
Check code for Base ID Fields (addresses 120-190)
9
Extended ID Fields
10Power Supply
Power supply current requirements and max power dissipation
11(see Table 54)
12
Vendor SN
Serial number provided by vendor (ASCII)
13
14
Date code
Vendor's manufacturing date code (see Table 55)
15
Diagnostic Monitoring Type
Indicates which type of diagnostic monitoring is implemented (if any)
16
in the transceiver (see Table 56)
Bit 1, 0 Reserved
17
18
Enhanced Options
Indicates which optional enhanced features are implemented (if any) inthe transceiver (see Table 57)
19
20
Aux Monitoring
Deﬁnes quantities reported by Aux. A/D channels (see Table 58 Table
59)
21
22
CC_EXT
Check code for the Extended ID Fields (addresses 192 to 222)
23
Vendor Speciﬁc ID Fields
24
25
Vendor Speciﬁc
Vendor Speciﬁc EEPROM
26
27
28
29
Byte 0 of the lower memory map contains the module identiﬁer value. The 30
identiﬁer value speciﬁes the physical device described by the serial ID in31
formation. This value is also included in the serial ID data table (01h). The
32
deﬁned identiﬁer values are shown in Table 32. The XFP transceiver
33
should use identiﬁer 06h.
34
35
36
37
38
39
40
41
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Page 82

Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

5.16 EXTENDED IDENTIFIER

5.17 CONNECTORXFP MSAManagement interface

August 31, 2005

1
2
The extended identiﬁer value provides additional information about the3basic transceiver types Table 47.
4This ﬁeld existed in the GBIC speciﬁcation to identify the various module 5
deﬁnitions. These deﬁnitions do not apply to the XFP. The space is used 6
to identify whether the transceiver contains a CDR function and identiﬁes
7
its power dissipation class it belongs. The ﬁeld also identiﬁes whether a
CLEI identiﬁer code is present in Table 02h of the memory map (see Sec- 8
9tion 5.45)
10
11
12
Table 47 Extended Identiﬁer values Byte 129
13
14
Bit
Description of device type15
7-6
00: Power Level 1 Module (1.5 W max. power dissipation.)
16
01: Power Level 2 Module (2.5W Max)17
10: Power Level 3 Module (3.5W max. power dissipation.)18
11: Power Level 4 Module (>3.5W max. power dissipation.)
19
5
0: Module with CDR function
20
1: Non-CDR version of XFP
21
4
0: TX Ref Clock Input Required
22
1: TX Ref Clock Input Not Required23
3
0: No CLEI code present in Table 02h
24
1: CLEI code present in Table 02h
25
2-0
Reserved
26
27
28
29
30
The Connector value indicates the external connector provided on the in- 31
terface. This value shall be included in the serial data. The deﬁned con32
nector values are shown in Table 48. Note that some connectors in thistable are mechanically incompatible with the XFP dimensions. This full list 33
is included for compatibility with GBIC and SFP standards in the selection 34
35
of potential future connector codes.
36
37
38
39
40
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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

Management interface

August 31, 2005

1
2
Table 48 Connector values Byte 13034Register
Description of connector
500h
Unknown or unspeciﬁed
6
01h
SC
7
8
02h
Fibre Channel Style 1 copper connector
903hFibre Channel Style 2 copper connector
1004h
BNC/TNC
1105h
Fibre Channel coaxial headers
12
13
06h
FiberJack
14
07h
LC
15
08h
MT-RJ
16
09h
MU
17
18
0Ah
SG
19
0Bh
Optical pigtail
20
0C-1FhReserved
2122
20h
HSSDC II
23
21h
Copper Pigtail
24
22h-7Fh
Reserved
25
80-FFhVendor speciﬁc
26
27
28
29
5.18 INTERFACE SPECIFICATION
30
The following bit signiﬁcant indicators deﬁne the electronic or optical inter- 31
faces that are supported by the transceiver Table 49. At least one bit shall 32
be set in this ﬁeld. This table is not backward compatible with the33
GBIC/SFP serial ID deﬁnition.
34
35
36
37
38
39
40
41
42
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Page 84

Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

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August 31, 2005

Table 49 Transceiver codes
Addr

Bit

Description of transceiverAddr

10 Gigabit Ethernet Compliance

Description of transceiver

SONET/SDH Codes - Interconnect

131

7

10GBASE-SR

135

7

I-64.1r

131

6

10GBASE-LR

135

6

I-64.1

131

5

10GBASE-ER

135

5

I-64.2r

131

4

10GBASE-LRM

135

4

I-64.2

131

3

10GBASE-SW

135

3

I-64.3

131

2

10GBASE-LW

135

2

I-64.5131

1

10GBASE-EW

135

1

Reserved

131

0

Reserved

135

0

Reserved

10 Gigabit Fibre Channel Compliance

SONET/SDH Codes – Short Haul

132

7

1200-MX-SN-I

136

7

S-64.1132

6

1200-SM-LL-L136

6

S-64.2a132

5Extended Reach 1550 nm

1365S-64.2b132

4Intermediate Reach 1300 nm FP

136

4

S-64.3a132

3

Reserved

136

3

S-64.3b132

2

Reserved

1362

S-64.5a132

1

Reserved

1361

S-64.5b132

0

Reserved

136

0

Reserved

10 Gigabit Copper Links

SONET/SDH Codes – Long Haul

133

7

Reserved

137

7

L-64.1

133

6

Reserved

137

6

L-64.2a133

5

Reserved

137

5

L-64.2b133

4

Reserved

137

4

L-64.2c133

3

Reserved

137

3

L-64.3

133

2

Reserved

1372

G.959.1 P1L1-2D2

133

1

Reserved

137

1

Reserved

133

0

Reserved

137

0

Reserved

Lower Speed Links
134

XFP MSA

Bit

7

SONET/SDH Codes – Very Long Haul

1000BASE-SX / 1xFC MMF

Page 85138

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REVISON 4.5

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August 31, 2005

Table 49 Transceiver codes

5.19 ENCODING

XFP MSA

Addr

Bit

134

6

134

5

134

4

134

3

134

2

134

1

134

0

1
2
Description of transceiver
Addr
Bit
Description of transceiver
3
4
1000BASE-LX/1xFC SMF
138
6
V-64.2b5
2xFC MMF
138
5
V-64.36
2xFC SMF
138
4
Reserved
7
OC 48-SR
138
3
Reserved
89OC-48-IR
138
2
Reserved
10
OC-48-LR
138
1
Reserved
11
Reserved
138
0
Reserved
12
13
14
15
16
17
The encoding bits indicate the serial encoding mechanisms that are sup- 18
ported by the particular transceiver. A one in a given bit position indicates 19
support of that encoding mechanism. The deﬁned encoding support bits 20
are shown in Table 50.
21
2223
Table 50 Encoding Support Byte 139
24
25
Bit
Description of encoding mechanism
26
7
64B/66B
27
28
6
8B10B
29
5
SONET Scrambled
30
4
NRZ
31
3
RZ
32
33
2
Reserved
34
1
Reserved
35
0Reserved
36
37
38
39
40
41
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Page 86

Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

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August 31, 2005

5.20 BR, MINIMUM

1
The minimum bit rate (BR, minimum) is speciﬁed in units of 100 Megabits 2
per second, rounded off to the nearest 100 Megabits per second. The bit 3
rate includes those bits necessary to encode and delimit the signal as well 4
as those bits carrying data information. A value of 0 indicates that the min- 5
imum bit rate is not speciﬁed and must be determined from the transceiver 6
technology. The actual information transfer rate will depend on the en7
coding of the data, as deﬁned by the encoding value. Speciﬁc CDR rate
8
support is indicated in Byte 164.
9105.21 BR, MAXIMUM
The maximum bit rate (BR, maximum) is speciﬁed in units of 100 Mega- 11
bits per second, rounded off to the nearest 100 Megabits per second. The 12
bit rate includes those bits necessary to encode and delimit the signal as 13
well as those bits carrying data information. A value of 0 indicates that the 14
maximum bit rate is not speciﬁed and must be determined from the trans- 15
ceiver technology. The actual information transfer rate will depend on the16
encoding of the data, as deﬁned by the encoding value. Speciﬁc CDR rate
17
support is indicated in Byte 164.
18
19
5.22 LENGTH (STANDARD SINGLE MODE FIBER)-KM
20
This value speciﬁes the link length that is supported by the transceiver
while operating in compliance with the applicable standards using single 21
mode ﬁber. The value is in units of kilometers. A value of 255 means that 22
the transceiver supports a link length greater than 254 km. A length ﬁeld 23
value of 0 for XFP modules indicates that the length should be the oper- 24
ating length speciﬁed by the supported standard Table 49.
25
26
27
28
5.23 LENGTH (EXTENDED BANDWIDTH 50 ΜM MULTIMODE FIBER)
29
This value speciﬁes the link length that is supported by the transceiver
while operating in compliance with the applicable standards using 2000 30
31
MHz*km (850nm) extended bandwidth 50 micron core multimode ﬁber.
The value is in units of 2 meters. A value of 255 means that the transceiver 32
supports a link length greater than 508 m. A length ﬁeld value of 0 for XFP 33
modules indicates that the length should be the operating length speciﬁed 34
by the supported standard Table 49.
35
36
37
38
39
40
41
42
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Page 87

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REVISON 4.5

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August 31, 2005

5.24 LENGTH (50 UM MULTIMODE FIBER)

1
2
This value speciﬁes the link length that is supported by the transceiver3
while operating in compliance with the applicable standards using 500
MHz*km (850 and 1310nm) 50 micron core multimode ﬁber. The value is 4
in units of meters. A value of 255 means that the transceiver supports a 5link length greater than 254 m. A length ﬁeld value of 0 for XFP modules 6
indicates that the length should be the operating length speciﬁed by the7
supported standard Table 49.
8
9
10
11
5.25 LENGTH (62.5 UM MULTIMODE FIBER)
12This value speciﬁes the link length that is supported by the transceiver
13
while operating in compliance with the applicable standards using 200
MHz*km (850 nm) / 500 MHz*km (1310 nm) 62.5 micron core multimode 14
ﬁber. The value is in units of meters. A value of 255 means that the trans- 15
ceiver supports a link length greater than 254 m. A length ﬁeld value of 0 16
for XFP modules indicates that the length should be the operating length17
speciﬁed by the supported standard Table 49.
18
19
20
21
5.26 LENGTH (COPPER)
22
This value speciﬁes the minimum link length that is supported by thetransceiver while operating in compliance with the applicable standards 23
using copper cable. The value is in units of meters. A value of 255 means 24that the transceiver supports a link length greater than 254 meters. A
25
value of zero means that the transceiver does not support copper cables 26
or that the length information must be determined from the transceiver27
technology. Further information about the cable design, equalization, andconnectors is usually required to guarantee meeting a particular length re- 28
quirement. This also speciﬁes the total cable length of copper cable as- 29
semblies with integrated XFP’s.
30
31
32
33
34
35
36
37
38
39
40
41
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REVISON 4.5

5.27 DEVICE TECHNOLOGYXFP MSAManagement interface

August 31, 2005

1
This byte contains information about the laser, detector and any cooling 2technology. The deﬁned identiﬁer values are shown in Table 51 and Table 3
52.
4
5
6
Table 51 Device Technology (Value of lower 4 7
8bits of Byte 147)
9Bits
Description of physical device
10
11
7-4
Transmitter technology (see Table 52)
123
0: No wavelength control
13
1: Active wavelength control
142
0: Uncooled transmitter device
15
1: Cooled transmitter161
Detector Type17
0: PIN detector
18
1: APD detector
190
0: Transmitter not Tunable20
1: Transmitter Tunable21
22
23
Table 52 Transmitter Technology (Value of top 4 24
25
bits of Byte 147)
26
Value
Description of physical device
27
28
0000b
850 nm VCSEL
290001b1310 nm VCSEL
300010b1550 nm VCSEL
310011b1310 nm FP
32
33
0100b
1310 nm DFB
34
0101b1550 nm DFB
35
0110b1310 nm EML
36
0111b1550 nm EML
37
38
1000b
Copper or others
391111b-1001b Reserved
40
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REVISON 4.5

5.28 VENDOR NAME

5.29 CDR SUPPORT5.30 VENDOR OUIXFP MSAManagement interface

August 31, 2005

1
The vendor name is a 16 character ﬁeld that contains ASCII characters, 2
left-aligned and padded on the right with ASCII spaces (20h). The vendor 3
name shall be the full name of the corporation, a commonly accepted ab- 4
breviation of the name of the corporation, the SCSI company code for the 5
corporation, or the stock exchange code for the corporation. At least one 6of the vendor name or the vendor OUI ﬁelds shall contain valid serial data.
78910The nominal XFP design has CDR technology on both the transmit and 11
receive path. Individual XFP devices may or may not support all the stan- 12
dard 10G bit rates. This Byte indicates which rates are supported by the 13
CDR. A value of 0 indicates no CDR support. Table 53 deﬁnes the CDR 14
support bits.
15
16This Byte is also used to indicate which if any of the loopback modes are17
supported. A 1 in bit 0 indicates that XFI loopback is supported (controlled
by the bits listed in Table 34). A 1 in bit 1 indicates that lineside (optical to 18
19
optical) loopback is supported.
20
21
22
Table 53 CDR Support Byte 164
23
24
Bits
Description of physical device
25
7
CDR support for 9.95 Gb/s
26
6
CDR support for 10.3 Gb/s
27
28
5
CDR support for 10.5 Gb/s
29
4
CDR support for 10.7 Gb/s
30
3
CDR support for 11.1 Gb/s
31
2
Reserved32
33
1
Lineside Loopback Mode Supported
34
0
XFI Loopback Mode Supported
35
36
37
38
The vendor organizationally unique identiﬁer ﬁeld (vendor OUI) is a 3-byte 39
ﬁeld that contains the IEEE Company Identiﬁer for the vendor. A value of 40
all zero in the 3-byte ﬁeld indicates that the Vendor OUI is unspeciﬁed.
41
42
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1
2
5.31 VENDOR PN
3
The vendor part number (vendor PN) is a 16-byte ﬁeld that contains ASCII 4
characters, left-aligned and padded on the right with ASCII spaces (20h), 5
deﬁning the vendor part number or product name. A value of all zero in 6
the 16-byte ﬁeld indicates that the vendor PN is unspeciﬁed.
789105.32 VENDOR REV
11
The vendor revision number (vendor rev) is a 2-byte ﬁeld that contains
ASCII characters, left-aligned and padded on the right with ASCII spaces 12(20h), deﬁning the vendor’s product revision number. A value of all zero in 13
the 2-byte ﬁeld indicates that the vendor PN is unspeciﬁed.
14
15
16
17
5.33 LASER WAVELENGTH
18
Nominal transmitter output wavelength at room temperature. 16 bit value 19
with byte 186 as high order byte and byte 187 as low order byte. The laser
20
wavelength is equal to the 16 bit integer value divided by 20 in nm (unitsof 0.05nm). This resolution should be adequate to cover all relevant wave- 21
22lengths yet provide enough resolution for all expected DWDM applications. For accurate representation of controlled wavelength applications, 23
this value should represent the center of the guaranteed wavelength24
range.
25
26
27
28
5.34 LASER WAVELENGTH TOLERANCE
29
The guaranteed +/- range of transmitter output wavelength under all
normal operating conditions. 16 bit value with byte 188 as high order byte 30
and byte 189 as low order byte. The laser wavelength is equal to the 16 31
32
bit integer value divided by 200 in nm (units of 0.005nm). Thus, the following two examples:
33
34
35
36
Example 1:
37
10GBASE-LR Wavelength Range = 1260 to 1355 nm
38
39Nominal Wavelength in Bytes 186 - 187 = 1307.5 nm.
Represented as INT(1307.5 nm * 20) = 26150 = 6626h
40
41
42
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Wavelength Tolerance in Bytes 188 - 189 = 47.5nm.
Represented as INT(47.5 nm * 200) = 9500 = 251Ch

Example 2:
ITU-T Grid Wavelength = 1534.25 nm (195.4 THz) with 0.236 nm ( 30
GHz) Tolerance
Nominal Wavelength in Bytes 186 - 187 = 1534.25 nm.
Represented as INT(1534.25nm * 20) = 30685 = 77DDh
Wavelength Tolerance in Bytes 188 - 189 = 0.236 nm.
Represented as INT(0.236 nm * 200) = 47 = 002Fh

5.35 MAXIMUM CASE TEMPERATURE
Allows speciﬁcation of a maximum case temperature other than the MSA
standard of 70C. Maximum case temperature is an 8-bit value in Degrees
C.

5.36 CC_BASE
The check code is a one byte code that can be used to verify that the ﬁrst
64 bytes of serial information in the XFP is valid. The check code shall be
the low order 8 bits of the sum of the contents of all the bytes from byte
128 to byte 190, inclusive.

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REVISON 4.5

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5.37 POWER SUPPLY REQUIREMENTS
Bytes 192-195 contain information on the maximum current requirementof each of the four power supplies, as well as the maximum power dissipation of the modules. This information allows system vendors to do more
careful power supply and thermal dissipation management. The data
format for this information is described in Table 54

Table 54 Power Supply Related Fields
data address

bits

Description of Fields

192

7-0

Maximum Power Dissipation
Max power is 8 bit value * 20 mW.

193

7-0

Maximum Total Power Dissipation in Power Down Mode
Max Power is 8 bit value * 10 mW.

194

7-4

Maximum current required by +5V Supply.
Max current is 4 bit value * 50 mA. [500 mA max]

194

3-0

Maximum current required by +3.3V Supply.
Max current is 4 bit value * 100 mA.

195

7-4

Maximum current required by +1.8V Supply
Max current is 4 bit value * 100 mA.

195

3-0

Maximum current required by -5.2V Supply.
Max current is 4 bit value * 50 mA. [500 mA max]

5.38 VENDOR SN
The vendor serial number (vendor SN) is a 16 character ﬁeld that contains
ASCII characters, left-aligned and padded on the right with ASCII spaces(20h), deﬁning the vendor’s serial number for the transceiver. A value ofall zero in the 16-byte ﬁeld indicates that the vendor SN is unspeciﬁed.

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5.39 DATE CODE1
The date code is an 8-byte ﬁeld that contains the vendor’s date code in 2
ASCII characters. The date code is mandatory. The date code shall be in 3
the format speciﬁed by Table 55.
45Table 55 Date Code
6
7
Data Address
Description of ﬁeld
8212-213ASCII code, two low order digits of year. (00 = 2000).
9214-215ASCII code, digits of month (01 = Jan. through 12 = Dec.)
1011216-217ASCII code, day of month (01 - 31)
12
218-219
ASCII code, vendor speciﬁc lot code, may be blank
13
14
15
16
5.40 DIAGNOSTIC MONITORING TYPE
17
“Diagnostic Monitoring Type” is a 1 byte ﬁeld with 8 single bit indicators
18
describing how diagnostic monitoring is implemented in the particular19transceiver. Bit indicators are detailed in Table 56.
20
Digital diagnostic monitors received power, transmitted power, bias cur- 21
rent, supply voltage, and temperature. Additionally, alarm and warning
22
thresholds must be written as speciﬁed in this document at locations 02 –23
57 (see Table 35). Auxiliary monitoring ﬁelds are optional extensions to
24
Digital Diagnostics
25
Unlike the system described in SFF-8472, the XFP digital diagnostics def- 26
inition does not allow for the possibility of “external calibration”. All digital 27
diagnostic values must be internally calibrated and reported in the units 28
deﬁned in this document.
29
30
Bit 3 indicates whether the received power measurement represents average input optical power or OMA. If the bit is set, average power is mon- 31
32
itored. If it is not, OMA is monitored.
33
34
35
36
37
38
39
40
41
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2
Table 56 Diagnostic Monitoring Type3
4
Data Address
Bits
Description
5
220
7-5
Reserved
6220
4Module Respond to FEC BER
7
0= No BER Support, 1=BER Support
8
220
3
Received power measurement type
9
0 = OMA, 1 = Average Power
10
11
220
2
Reserved
12
220
1- 0
Reserved
13
14
15
5.41 ENHANCED OPTIONS
16“Enhanced Options” is a 1 byte ﬁeld with 8 single bit indicators which de- 17
scribe the optional digital control and diagnostic features implemented in 18
the transceiver, as well as optional operating modes (see Table 57).
19
20
The optional digital controls are the Soft TX Disable and Power down func21
tions which allow the functions to be actuated via the 2-wire serial control
22
bus.
23
The optional operating modes indicate the ability of the module to perform 24
active FEC and wavelength tunability functions, as well as the ability to
25
support the optional Synchronous REFCLK mode.
26
27
.
28
29
Table 57 Enhanced Options
30
Data Address
Bits
Description
31
32
221
7
Module Supports Optional VPS
33
221
6
Optional Soft TX_DISABLE implemented
34
221
5
Optional Soft P_down implemented
35
36
221
4
Supports VPS LV regulator mode
37
221
3
Supports VPS bypassed regulator Mode
38
221
2
Active FEC control functions implemented
39
221
1
Wavelength tunability implemented
40
41
221
0
Optional CMU Support Mode42
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REVISON 4.5

5.42 AUXILIARY MONITORINGXFP MSAManagement interface

August 31, 2005

1
This standard deﬁnes two ﬂexible auxiliary A/D monitoring channels. This 23Byte, deﬁned in Table 58 and Table 59 describes which quantities aremonitored by each auxiliary A/D channel.
45Table 58 Auxiliary A/D Types Byte 222
67
Bits
A/D Input
8
7-4
Aux A/D Input 1 (see Table 59)
93-0
Aux A/D Input 2 (see Table 59)
10
11
12
13
Table 59 Auxiliary Input Types
14
Value
Description of physical device
15
16
0000b
Auxiliary monitoring not implemented
170001b
APD Bias Voltage
18(16 bit value is Voltage in units of 10 mV)
190010b
Reserved
200011b
TEC Current (mA)
21
(16 bit value is Current in units of 100 uA)
22
0100b
Laser Temperature
23(Same encoding as module temperature)
24
0101b
Laser Wavelength25(same Encoding as Bytes 186-187)
260110b+5V Supply Voltage
27(Encoded as described in section 5.6)
28
0111b
+3.3V Supply Voltage
29(Encoded as described in section 5.6)30
1000b
+1.8V Supply Voltage
31(Encoded as described in section 5.6)
32
1001b
-5.2V Supply Voltage
33(Absolute Value Encoded as primary Voltage Monitor)
34
1010b+5V Supply Current
35(16 bit Value is Current in 100 uA)
36
1101b+3.3V Supply Current
37(16 bit Value is Current in 100 uA)
38
1110b+1.8V Supply Current
39(16 bit Value is Current in 100 uA)
40
1111b-5.2V Supply Current
41(16 bit Value is Current in 100 uA)
42
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2
5.43 CC_EXT
3
The check code is a one byte code that can be used to verify that the ﬁrst 4
31 bytes of extended serial information in the XFP is valid. The check5
code shall be the low order 8 bits of the sum of the contents of all the bytes 6
from byte 192 to byte 222, inclusive.
789
10
5.44 VENDOR SPECIFIC ID FIELD
11
Bytes 224-255h of Table 01h may be used for Vendor Speciﬁc ID func12
tions.
13
14
5.45 DESCRIPTION OF UPPER MEMORY MAP TABLE 02H – USER EEPROM DATA
Table 02h is provided as user writable EEPROM. The host system may 15
read or write this memory for any purpose. If bit 3 of Table 01h Byte 129 16
is set, however, the ﬁrst 10 bytes of Table 02h [128-137h] will be used to 17
store the CLEI code for the module.
18
19
20
21
5.46 DESCRIPTION OF UPPER MEMORY MAP TABLES 03H – 7FH VENDOR SPECIFIC FUNCTIONS
22
Tables 03h-7Fh are reserved for Vendor Speciﬁc functions.
23
24
25
26
5.47 DESCRIPTION OF UPPER MEMORY MAP TABLES 80H – FFH RESERVED
27
Tables 80h-FFh are reserved.
28
29
30
31
32
33
34
35
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3
4
5
6
The mechanical components deﬁned in this section are illustrated in
7
Figure 29. The module, clip and connector dimensions are constant for all 8
applications. While the bezel, cage assembly, EMI gasket and heat sink9
can be designed and/or adjusted for the individual application.
10
11
The relatively small form factor of the XFP module combined with an
12
adaptable heatsink option allows host system design optimization ofmodule location, heatsink shape/dimension/ﬁns design, and airﬂow con- 13
trol. The module can be inserted and removed from the cage with the heat 14
sink and clip attached.
15
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Figure 29 XFP Mechanical Components
42

CHAPTER 6: MECHANICAL AND BOARD DEFINITION

6.1 INTRODUCTIONXFP MSA

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6.2 XFP DATUMS AND COMPONENT ALIGNMENT

1
A listing of the datums for the various components is contained in Table 2
60 The alignments of some of the datums are noted. The relationship of 3
the Transceiver, Cage, and Connector relative to the Host Board and4
Bezel is illustrated in Figure 30 by the location of the key datums of each 5of the components.
6
7
Table 60 Deﬁnition of Datums
8
9
Datum
Description
Figure #10A
Host Board Top Surface
Figure 35
11
B
Back surface of bezel (See Section 6.8)
Figure 37 & Figure 38
12
1CDistance between Connector alignment post thru holes on host board
Figure 36
13
14
D
Hard stop on transceiver 2
Figure 31
15
E
Width of transceiver 1
Figure 31
16
F
Height of transceiver housing
Figure 31
17
1
18
GWidth of transceiver pc board
Figure 33
19
H
Leading edge of transceiver pc board
Figure 33
20
J
Top surface of transceiver pc board
Figure 33
21
K
Host Board thru hole #1 to accept Connector alignment post 2
Figure 35 & Figure 36
22
2
23
L
Host Board thru hole #2 to accept Connector alignment post
Figure 35 & Figure 36
24
M
Width of bezel cut out 1
Figure 37 & Figure 38
25
N
Connector alignment pin 2
Figure 39
26
P
Width of inside of cage at EMI gasket (when fully compressed) 1
Figure 41
27
28
R
Height of inside of cage at EMI gasket (when fully compressed)
Figure 41
29
S
Seating plane of cage on host board
Figure 41
30
T
Hard stop on cage 2
Figure 41
31
U
Length of opening at top of cage to accept heat sink Datum Z
Figure 41
32
33
V
Length of clip
Figure 42
34
W
Surface of keep out area that clip contacts on heat sink
Figure 43
35
X&Y
Host board horizontal and depth datums established by customers’ ﬁducials
Figure 35
36
37
Z
Length of boss on heat sink that ﬁts inside of cage Datum U
Figure 43
38
AA
Width of heat sink surface that ﬁts into clip 1
Figure 43
39
1. Centerlines of datums C, E, G, M, P and AA are aligned on the same vertical axis
40
2. Datums D, K, L, N and T are aligned when assembled (see Figure 30)
41
42

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Figure 30 XFP Datum Alignment, Depth

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6.3 XFP TRANSCEIVER PACKAGE DIMENSIONS

1
A common mechanical outline is used for all XFP transceivers. The pre- 2
ferred method of removing the transceiver from the cage assembly is by 3
a bail type actuation method. The package dimensions for the XFP trans- 4
ceiver is deﬁned in Figure 31 and Figure 32.
5
6
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Figure 31 Drawing of XFP Transceiver, Part 1
42

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REVISON 4.5

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Figure 32 Drawing of XFP Transceiver, Part 2

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6.4 MATING OF XFP TRANSCEIVER PCB TO XFP ELECTRICAL CONNECTOR

1The XFP transceiver contains a printed circuit board that mates with the 2
XFP electrical connector. The pads are designed for a sequenced mating: 3
4• First mate – ground contacts
56• Second mate – power contacts
7• Third mate – signal contacts
8
The design of the mating portion of the transceiver printed circuit board isillustrated in Figure 33 and the electrical pad layout is illustrated in Figure 9
34. The recommended contact pad plating for the printed circuit board is 10
110.38 micrometers minimum gold over 1.27 micrometers minimum thicknickel.
12
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Figure 33 Recommended Pattern Layout for XFP Printed Circuit

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Figure 34 XFP Transceiver Electrical Pad Layout

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August 31, 2005

6.5 HOST BOARD LAYOUT
Host board should be laid out in accordance with the speciﬁc connector
Mfg. speciﬁcations. A typical host board mechanical layout for attaching
the XFP Connector and Cage System is shown in Figure 35 and Figure
36. The location of the pattern can vary relative datums selected by thecustomers. Location of the pattern on the host board is application speciﬁc. See section 6.8 for further details.

Figure 35 XFP Host Board Mechanical Layout

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Figure 36 XFP Detail Host Board Mechanical Layout, Detail Z

6.6 INSERTION, EXTRACTION AND RETENTION FORCES FOR XFP TRANSCEIVERS
The requirement for insertion forces, extraction forces and retention
forces are speciﬁed in Table 61.

Architecture Note
The XFP cage and module design combination must ensure excessive
force applied to a cable does not damage the XFP cage. If any part isdamaged by excessive force, it should be the cable or the media
module and not the cage which is part of the host system.

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Table 61 Insertion, Extraction, and Retention Forces
3
4
Measurement
Minimum
Maximum
Units
Comments
5
XFP transceiver insertion
040
Newtons
6
XFP transceiver extraction
030
Newtons
7
8
XFP transceiver retention
90
N/A
Newtons
No damage to transceiver below
90N
910
Cage retention (Latch strength)180
N/A
Newtons
No damage to the latch below 180N
11
Cage retention in Host Board
133
N/A
Newtons
Force to be applied in a vertical
12
direction with no damage to the
cage.
13
14
Insertion / removal cycles, connec100
N/A
cycles
tor/cage15
16
Insertion / removal cycles, XFP
50
N/A
cyclesTransceiver
17
18
19
20
6.7 COLOR CODING AND LABELING OF XFP TRANSCEIVERS
21
An exposed feature of the XFP transceiver (a feature or surface extending
22
outside of the bezel) shall be color coded as follows:23• Beige for 850nm
2425• Blue for 1310nm
26• White for 1550nm APD Receiver27• Red for 1550nm non-APD Receiver28
Each XFP transceiver shall be clearly labeled. The complete labeling29
need not be visible when the XFP transceiver is installed and the bottom 30of the device is the recommended location of the label. Labeling shall in31
clude:
32
33• Appropriate manufacturing and part number identiﬁcation
34• Appropriate regulatory compliance labeling35• A manufacturing traceability code
36
Also the label should include clear speciﬁcation of the external port char- 37
acteristics such as:
38
39
40
41
42
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1
2
• Required ﬁber characteristics
3• Operating data rate
4
• Interface standards supported
5• Link length supported.
6
The labeling shall not interfere with the mechanical, thermal and EMI fea- 7tures.
8910
11
6.8 BEZEL AND EMI GASKET DESIGN FOR SYSTEMS USING XFP TRANSCEIVERS
12
Host enclosures that use XFP devices should provide appropriate clear13
ances between the XFP transceivers to allow insertion and extraction
without the use of special tools and a bezel enclosure with sufﬁcient me- 14
15
chanical strength. For most systems a nominal centerline to centerline
spacing of 23.5 mm (0.925”) is sufﬁcient. See Figure 37 and Figure 38 for 16
the recommended bezel designs. Figure 37 illustrates the single sided
17
mounting and Figure 38 illustrates the double sided mounting method.
18
The minimum recommended host board thickness for double sided
19
mounting of the assemblies is 3.0 mm minimum.
20
21
There are many options for a bezel EMI gasket that functions as a seal
between the bezel and the front of the cage. The design of the bezel EMI 22
gasket and the materials used for the gasket are application speciﬁc. The 23
preferred method is to fasten the gasket to the back of the bezel with a24pressure sensitive adhesive. Assembly of the host board to the bezel will 25
compress the gasket to the recommended range speciﬁed by the bezel
26
EMI gasket manufacturer. The surface in the back of the bezel that is incontact with the bezel EMI gasket must be low resistance and connected 27
28
to ground.
29
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XFP MSA

Optical wavelength

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REVISON 4.5

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August 31, 2005

The gasket thickness after compression can be calculated as follows:1
2
GT = BKL - 56.3 ± 0.2mm.
34Where:
5
6• GT is gasket thickness in the compressed state.
7• BKL is the distance from the back of the bezel Datum B to the centerline of Datums K & L. See Figure 35 and Figure 36 (Note: dimension 8
9from front of bezel to centerline of Datums K & L must not exceed
1061.7mm, see Figure 30).
11
• The 56.3 ± 0.2mm dimension is the distance from the front of the
12cage to the hard stop, Datum T. See Figure 41.
The XFP transceiver insertion slot should be clear of nearby moldings and 13
covers that might block convenient access to the latching mechanisms, 14
15
the XFP transceiver, or the cables connected to the XFP transceiver.
16
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Figure 37 Recommended Single Sided Bezel Design
35
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REVISON 4.5

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Figure 38 Recommended Double Side Mounting Bezel Design
20
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22
6.9 XFP CONNECTOR MECHANICAL SPECIFICATIONS
23
The XFP Connector is a 30-contact, right angle surface mount connector 24
and available from several manufacturers1. An example connector such 25
as 788862-2 manufactured by Tyco is shown in Figure 39. Newer versions 26of this connector are available from Tyco, Molex, and Harting with im27
proved electrical performance.
28
29
30
31
32
33
34
35
36
37
38
1. 788862C (Standard PT) and 1367500-1 (New Improved PT Version), Mfg. by 39
Tyco Electronics, www.tycoelectronics.com.
40
Parecon 30 Mfg. by Harting-Electro-Optics, www.Harting-Electro-Optics.com.
4174441, Mfg. by Molex Inc., www.molex.com.
42
XFP MSA

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REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

Figure 39 XFP Transceiver Connector Illustration

XFP MSA

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REVISON 4.5

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August 31, 2005

1
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6.10 XFP CAGE ASSEMBLY DIMENSIONS
3
The Cage Assembly requires EMI shielding capability for both front and 4
back portions of the cage along with providing guidance for the connector, 5retention of the transceiver and features for heat sink attachment. The lo6
cation of the EMI gaskets for a reference design is illustrated in Figure 40
and a description of each EMI gasket is described in the sections below. 7
8The dimensional requirements for the cage are illustrated in Figure 41.
9
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Figure 40 XFP Cage Components
29
30
31
32
6.10.1 XFP CAGE HOUSING
33
The metal cage has compliant leads for assembly to the host board. The 34
cage material is copper alloy and the recommended plating options are: 35
36• Tin-lead plate 2.54 micrometers minimum over copper ﬂash
37
• Tin plate 2.54 micrometers minimum over 0.76 micrometers mini- 38
mum nickel
39
or the equivalent materials.
40
41
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REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

6.10.2 XFP CAGE REAR EMI GASKETS
The purpose of the rear EMI Gaskets is to block any emissions that are
emanating from the rear of the transceiver and carry them to chassis
ground in the Host Board by directly contacting the transceiver.

6.10.2.1 XFP UPPER REAR EMI GASKETThe Upper Rear EMI Gasket is fastened to the rear inside surface of thecage with pressure sensitive adhesive. The recommended material forthis gasket is conductive foam.

6.10.2.2 LOWER REAR EMI GASKETThe Lower Rear EMI Gasket is fastened to the bottom of the cage andcontacts the bottom surface of the transceiver skirt. The recommended
material for this gasket is a conductive elastomer.
6.10.2.3 XFP INTERMEDIATE REAR CAGE EMI GASKET (FINGER STOCK)The Intermediate Rear EMI Gasket is fastened to the bottom of the cageand simultaneously contacts the transceiver and Host Board. The preferred design is illustrated as a series of metal springs consisting of acopper alloy material. The recommended plating options are:•Tin-lead plate 2.54 micrometers minimum over copper ﬂash•

Tin plate 2.54 micrometers minimum over copper ﬂash•

or equivalent materials.

6.10.3 XFP CAGE FRONT CAGE EMI GASKET (FINGER STOCK)The purpose of the Front EMI Gasket is to create a seal between thetransceiver and the inside surface of the cage. The preferred design is illustrated as a series of metal springs that are fastened to the front of thecage and held in place by the front ﬂange. The Front EMI Gasket material
is copper alloy and the recommended plating options are:

XFP MSA

•

Tin-lead plate 2.54 micrometers minimum over copper ﬂash•

Tin plate 2.54 micrometers minimum over copper ﬂash•

or equivalent materials.

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REVISON 4.5

6.10.4 XFP FRONT FLANGEXFP MSA

Mechanical and Board deﬁnition

August 31, 2005

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The purpose of the front ﬂange is to provide a ﬂat surface to contact the 5
Bezel EMI Gasket (customer supplied) that is mounted on the back side
6of the bezel. It also serves as a collar to retain the Front EMI Gasket andto provide strength to the cage housing. The front ﬂange material is zinc 7
8alloy and the recommended plating options are:9
• Tin-lead plate 2.54 micrometers minimum over copper ﬂash
10
• Tin plate 2.54 micrometers minimum over 0.76 micrometers mini- 11
mum nickel
12
13
or equivalent materials.
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REVISON 4.5

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Figure 41 XFP Cage Assembly
XFP MSA

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XFP Speciﬁcation
REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

6.11 XFP HEAT SINK CLIP DIMENSIONSThe heat sink clip is deﬁned in Figure 42. When fastened to the cage, theclip will provide a minimum force of 5 Newtons at the interface of the heatsink and XFP transceiver. The clip is designed to permit a heat sink to befastened to the cage and to expand slightly during transceiver insertion inorder to maintain a contact force between the transceiver and heat sink.
.

Figure 42 XFP Heat Sink Clip

XFP MSA

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XFP Speciﬁcation
REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

1
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6.12 AN EXAMPLE XFP HEAT SINK
3
The heat sink is illustrated in Figure 43. Critical dimensions to insure that 4
the heat sink will be compatible with the Heat Sink Clip are deﬁned. The 5
conﬁguration of the ﬁns or posts is application speciﬁc along with the out- 6
side envelope. The heat sink includes a beveled edge which “rides up”
the leading edge of the transceiver as the transceiver is inserted into the 7
cage assembly. The recommended material for the heat sink is aluminum 8
and the surface treatment for the transceiver contacting surface can be 9
anodizing or nickel plating.
10
.
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Figure 43 XFP Heat Sink
38
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40
41
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XFP MSA

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REVISION 4.5

August 31, 2005

6.13 ENVIRONMENTAL AND THERMALThe XFP module electrical speciﬁcations shall be met at least from 0-70
degree C case temperature with an altitude range 0-3km.
The system designer is responsible for ensuring the maximum temperatures do not exceed requirements of IEC 60950 section 4.5.1 and table
4B. If case temperatures of the transceiver, cage, or heatsink exceed 70C,
appropriate labeling must be attached per table 4B note 6.
See Appendix G: for recommended test parameters and guidelines usedin characterization of module thermal performance.

6.14 DUST/EMI COVER
In order to prevent contamination of the internal components and to optimize EMI performance, it is recommended that a Dust/EMI Cover be inserted into cage assemblies when no transceiver is present. See Figure
44 for the recommended design. During installation, the front ﬂange on
the cover shall be seated against the front surface of the bezel to prevent
dust from entering the equipment. The conductivity of the materials
chosen for the Dust/EMI Cover to be sufﬁcient to block EMI emissions.

Figure 44 Dust/EMI CoverXFP MSA

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XFP Speciﬁcation
REVISION 4.5

Application Reference Model

August 31, 2005

1
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5
Application reference model deﬁnes a set of overlapping compliance and6measurements point to validate components and system. The reference
7
model objective are:8
9
• Satisfy the need for interoperablity at the electrical level.
10• Allow for independent validation of host board, Module, and11
ASIC/SerDes.
12
A.1 ASIC/SERDES COMPLIANCE TESTING
13
ASIC/SerDes transmitter and receiver are tested on a DUT board Figure
14
45 with minimum trace length to avoid degradation due to traces1. The
15compliance point are as the following:
16
17• A: the ASIC/SerDes Output. The applicable measurements are:18
• Eye Mask
19
• Output Jitter
20• Return Loss S22.
21
• D: the ASIC/SerDes Input. The applicable measurement are:22
23
• Input stress sensitivity
24• Jitter tolerance25• Return Loss S11.
26
27
28
29
30
D
31
SignalGenerator
32
Trace Length
ASIC/SerDes
33
10mm-40mm
Oscilloscope
34
35
A
36
DUT Board
37
38
Figure 45 ASIC/SerDes Compliance Test Board
39
40
1. DUT board may use superior material to eliminate excess loss, but theconstruction should be manufacturable by standard PCB process. Trace length 41
are recommended to be shorter than 40 mm and greater than 10mm.
42

APPENDIX A: APPLICATION REFERENCE MODELXFP MSA

Page 120

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REVISION 4.5

Application Reference Model

August 31, 2005

A.2 HOST SYSTEM COMPLIANCE TESTING

1
Host system transmitter and receiver are tested by inserting a Host Test 2
Board1 Figure 46 in place of the XFP module. The compliance point are 3
4
as the following:5• B: Host system Output. The applicable measurements are:6
7
• Eye Mask
8
• Output Jitter9• Return Loss S22.
10
• C: Host system Input. The applicable measurements are:11
• Input amplitude
1213• Jitter tolerance
14• Return Loss S11.
15
16
17
C
Connector
18
Signal19
Generator
20
ASIC/SerDes
Host Test Board
21
22
Oscilloscope
23
24
B
25
Host Under Test
26
Figure 46 Host System Compliance Test Diagram
27
28
29
A.3 XFP MODULE COMPLIANCE TESTING30
XFP modules are validated by testing them with a Module Compliance31
Test Board2 Figure 47 with 30 position XFP connector. The compliance
32
points are as the following:
33
34• B’: Host system Output. The applicable measurement are:35
• Input stress sensitivity
36• Jitter tolerance
37• Return Loss S11.
38
1. Host Test Board is a passive or active device that can be inserted in place of 39
the XFP module with negligible signal alteration.
40
2. Module Compliance Test Board is test board with XFP 30 position connector 41
and 10 mm-40mm of traces on low loss dielectric material.
42
XFP MSA

Page 121

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REVISION 4.5

Application Reference Model•

August 31, 2005

C: XFP module output. The applicable measurements are:•

Eye Mask•

Jitter output•

Return Loss S22.

C’ Connector
Oscilloscope

SignalGenerator

Trace Length
10mm-40mm

XFP Module Under TestB’
XFP Module Compliance Test Board
Figure 47 XFP Module Compliance Test Diagram

XFP MSA

Page 122

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XFP Speciﬁcation
REVISION 4.5

Application Reference Model

August 31, 2005

A.4 HOST SYSTEM COMPLIANCE TEST BOARD
Testing compliance to speciﬁcations in a high-speed system is delicate
and requires thorough consideration. The measurement point must be
low impedance and in many cases high impedance probing is prohibited
and would result in unreliable results. Using a common Host Test Board
that allows predictable, repeatable and consistent results among systemvendors will help to assure consistency and true compliance in the testingof Host Systems. Host Compliance board provided courtesy of Intel Corporation.

Figure 48 Host System compliance Test Board

A.4.1 HOST SYSTEM COMPLIANCE BOARD MATERIAL AND LAYER STACK-UP
Test board stack-up based on Nelco Roger3003/ FR4-6 with six layer
shown below.
1. LayerPrimary Side

0.010" Rogers 3003
2. Layer

Ground

0.006" FR4-6 Prepreg
3. Layer

Signal 1

0.008" FR-4 Laminate
4. Layer

Signal 2

0.006" FR4-6 Prepeg
5. LayerPower0.010" Rogers 3003
6. Layer

XFP MSA

Page 123

Secondary Side

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REVISION 4.5

Application Reference Model

August 31, 2005

Host System based on Roger3003 help reduce PCB loss, alternatively a 1
short FR4-6 terminated in coaxial cable may be used.
2
3
4
5
A.4.2 HOST SYSTEM COMPLIANCE TEST BOARD PARTLIST
6The host system compliance test board part list is given below.
7
8
Table 62 Host System Compliance Test Board Part List
9
Qty
RefDesValue
Description
10
11
4
C1, C2, C3, C4, C5, C6, C7, C8
100nF
Capacitor Ceramic SMA 0603 10% 16V X7R
12
3
DS1, DS2, DS7
SMA LED Green
13
4
DS3, DS4, DS5, DS6
SMA LED Blue
14
15
1
J1
Non Component (30 Poled XFP Edge Connector)
16
1
J2
Molex Square Pin Header with friction lock 3 pin pitch 2.54 mm
172
J3, J4,
SMA Connector Edge SMD
18
4
J5, J6, J7, J8
SMA Connector Straight on RPC footprint, short center pin
19
20
1
Q1
General Purpose Silicon NPN BJT
213
R1, R2, R3
100R
Resistor SMD 0603 5%
22
3
R4, R7, R8
1K
Resistor SMD 0603 5%
23
1
R5
10R
Resistor SMD 0603 5%
24
25
1
R9
10K
Resistor SMD 0603 5%
26
1
S1
Dil SMD switch 4x2 pol spacing 1.27mm
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
XFP MSA

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REVISION 4.5

Application Reference Model

August 31, 2005

A.4.3 SCHEMATIC OF HOST SYSTEM COMPLIANCE TEST BOARD

Figure 49 Schematic of Host System Compliance Test BoardXFP MSA

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REVISION 4.5

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A.4.4 GERBER FILE AND S PARAMETER MEASUREMENTS

1
2
Please see http://www.xfpmsa.org.
3
4
5
A.5 XFP MODULE COMPLIANCE TEST BOARD
6
The Module Compliance Test Board allows predictable, repeatable and 7
consistent results among Module vendors and will help to assure consis- 8
tency and true compliance in the testing of modules. Module Compliance9
Test provided courtesy of Intel Corporation.
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Figure 50 XFP Module Compliance test Board
38
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REVISION 4.5

Application Reference Model

August 31, 2005

A.5.1 XFP MODULE BOARD MATERIAL AND LAYER STACK-UP
XFP module compliance test board based on a four layer Rogers 3003 /FR4-6 material shown below:
1. LayerPrimary Side

0.010" Rogers 3003
2. Layer

Ground

0.040" FR4-6 Prepreg
3. LayerPower0.010" Rogers 3003
4. Layer

XFP MSA

Page 127

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REVISION 4.5

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A.5.2 XFP MODULE COMPLIANCE BOARD PARTLISTComponent part list for the XFP compliance test board is given below.

Table 63 XFP Module Compliance Test Board Part List
Qty

RefDesValue

Description

4

C3, C4, C10, C14

22µF

Capacitor Tantalum SMD B 10% 10V

10C5, C6, C7, C8, C9, C11, C12,

100 nF

Capacitor Ceramic SMA 0603 10% 16V X7R

2

C16, C17

2.2µF

Capacitor Tantalum SMD B 10% 10V2

CR1, CR2

General Purpose Silicon Rectiﬁer SMD Diode3

DS1, DS2, DS3, DS4

SMA LED RED

4J1, J2, J6, J8

SMA Connector Straight on RPC footprint, short center pin

2

J3, J4,

SMA Connector Edge SMD

1J6

30 Pos XFP Right Angle SMD Host Connector with 0.8 mm Pitch

1

J7

Terminal Block PCB 3 Way

1J9

Molex Square Pin Header with friction lock 3 pin pitch 2.54 mm pin

4

L1, L2, L3, L4

1

PT1

4

R1, R3, R5, R6

10K

Resistor SMD 0603 5%2

R9, R120R

Resistor SMD 0603 5%

1

R13

560R

Resistor SMD 0603 5%

1

R14

150R

Resistor SMD 0603 5%

2

R15, R16

100R

Resistor SMD 0603 5%

2

R17, R18

300R

Resistor SMD 0603 5%

2

R19, R20

10K

Resistor SMD 0603 5%

4

R2, R4, R7, R8100R

Resistor SMD 0603 5%5

TP1, TP2, TP3, TP4, TP5

Test pin 1mm Black

1

U1

74HCT04 Hex Inverting Gates SMD

2

U2, U3

1.5A Low Dropout Positive Regulator SMD

1

S1

Dil SMD switch 4x2 pol spacing 1.27mm

4.7µF

Inductor SMD 2220 4.7 µH 10%
XFP Cage for 30 Position PT Connector

Optional Components

2

C1, C2

100nF

Capacitor Ceramic SMA 0603 10% 16V X7R

2

R10, R11

330R

Resistor SMD 0603 5%1

Y1

XFP MSA

155.52 Crystal Oscillator (XO) Small SMD

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A.5.3 SCHEMATIC OF THE XFP COMPLIANCE TEST BOARD

Figure 51 Schematic of the XFP Compliance Test BoardXFP MSA

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XFP Speciﬁcation
REVISION 4.5

Application Reference Model

August 31, 2005

A.5.4 GERBER FILES AND MEASURED S-PARAMETERS

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Please see http://WWW.xfpmsa.org.

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REVISION 4.5

XFI Channel Measurements and ModelingAugust 31, 2005

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This Appendix provides design guidelines for the high-speed electrical in- 7
terfaces found in XFP applications. A fundamental feature of the XFP
8speciﬁcation is that the electrical transceiver ASIC is positioned on the9system (Host) printed circuit board (PCB) rather than within the opticaltransceiver module. Figure 52 depicts a typical system block diagram of 10
an end-to-end electrical channel for XFP applications. The block diagram 11
includes a transceiver board that exists within the XFP module, a 30-pin 12
hot swappable connector, a host board, and a BGA package. Although13
most host board designers will not have any direct control over the trans- 14
ceiver ASIC BGA package, it is nevertheless important to mention that the15
package can be simulated, designed, and included in channel simulations16
at 10Gb/s speeds.
17
Simulations and measurements of this electrical channel are discussed to 18
provide guidelines on XFI design. Broadcom Corporation provided the19transceiver board, host board, and electrical measurements; ASAT pro- 20
vided the BGA package model; Ansoft Corporation performed simula21
tions.
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Figure 52 XFI Electrical Channel Deﬁnition
42

APPENDIX B: XFI CHANNEL MEASUREMENTS AND MODELING

B.1 SYSTEM OVERVIEW

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REVISION 4.5

XFI Channel Measurements and ModelingAugust 31, 2005

Figure 53 depicts the stack up for the Broadcom reference board. Total
1
board thickness is 36mils and the board material is Nelco FR4-13 with εr 2
= 4.0 and a loss tangent of 0.016. All traces are 1/2 oz. copper.
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Figure 53 PCB Board Stack up
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REVISION 4.5

XFI Channel Measurements and ModelingAugust 31, 2005

B.2 DESIGN GUIDELINE

1• Keep differential pair traces on the same side of the PCB to minimize 2
3
impedance discontinuities.
4• When routing differential pairs, keep the trace length identical be5
tween the two traces. Differences in trace lengths translate directly
6
into signal skew and can give rise to common mode reﬂections.
7• Eliminate/reduce stub lengths of traces and vias.
8• Reduce, if not eliminate, vias to minimize impedance discontinuities.
9
Remember that vias and their clearance holes in the power/groundplanes can cause impedance discontinuities in nearby signals. Keep 10
11vias away from traces by 10 times the trace width if possible, 2.5
times as a minimum.
12
13• Use rounded corners rather than 90 or 45-degree corners.
• Keep signal traces far from other signals that might couple noise into 14
15
the signals. A good rule of thumb is that “far” means ten times the16width of the trace.
• Do not route digital signals from other circuits across the area of the 1718transmitter and receiver.
• Do not cut up the power or ground planes in an effort to steer current 19
20
paths. This usually produces more noise, not less. Furthermore,place vias and clearances so as to maintain the integrity of the plane. 21
Groups of vias spaced closely together often overlap clearances that 22
can form a large hole in the plane. Return currents are forced around 23
the holes, increasing loop area and therefore, EMI emissions.
24
•
25
26
B.3 USING SYSTEM SIMULATION FOR CHANNEL MODELING
27
Figure 54 depicts the system simulator model for the XFP channel of
Figure 52 including the transceiver board traces, the Tyco connector, and 28
the host board traces. S-parameter models that were computed from the 29
circuit and electromagnetic simulations are cascaded to allow evaluation 30
of end-to-end system performance.
31
32
Figure 55 and Figure 56 contain comparisons of the simulated and measured differential s-parameters for SDD11 and SDD21, respectively. Al- 33
though differences between the simulated and measured are observed 34(especially for SDD11), it is clear that the simulations have accurately de- 35
picted the trends for the overall system response.
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REVISION 4.5

XFI Channel Measurements and ModelingAugust 31, 2005

Figure 54 System model for the XFI Channel.

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REVISION 4.5

XFI Channel Measurements and ModelingAugust 31, 2005

Figure 55 Comparison of simulated and measured differential s11

Figure 56 Comparison of simulated and measured differential s21
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REVISION 4.5

XFI Channel Measurements and ModelingAugust 31, 2005

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Figure 57 Measured and simulated eye diagram for the XFP channel 22
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REVISION 4.5

Differential S-Parameters and TDR

August 31, 2005

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C.1 CHOOSING S-PARAMETERS VS TDR
6
S-Parameters measured with a Vector Network Analyzer (VNA) provide a 7
good match to the frequency and time response, but do not correlate to 8
the location of discontinuity.
9
TDR response can isolate location of discontinuity from the measured re- 10
11sponse and allow isolation of signal integrity issues.
12
Advantage of VNA:
13
14
• Most accurate method of modeling passive networks
15• High BW >50GHz
16
17
Advantages of TDR:
18
• Isolate signal integrity location
19• Immediate view of DUT while measuring
20
21• Intuitive display in anticipating eye pattern problems.
22
Disadvantage of VNA
23
24• 4-port VNA required or conversion from two ports
25• Measurement time
26
Disadvantage of TDR
27
28• Not very accurate to provide spatial information29• Accuracy decreases as frequency increases due to reduced pow30
er in high frequency components.
31• Using averaging of many pulses to reduce effective noise, a prac32
tical limit to usage is between 10 Ghz and 20 Ghz.
33
• TDR must be converted to S-parameters by FFT with tools such34
as: Tektronix IPA or NIST(free US govt) TDNACal
35
The choice between TDR and VNA should be made based on availability
36
of equipment and tools as well as accuracy required.
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APPENDIX C: DIFFERENTIAL S-PARAMETERS AND TDR

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REVISION 4.5

Differential S-Parameters and TDR

August 31, 2005

C.2 DIFFERENTIAL IMPEDANCE
Stripline and microstrip transmission lines are transverse electromagnetic(TEM) and quasi-TEM structures, respectively. Waves that propagate onthese structures have propagation constants that are predominantly linearwith frequency and hence phase velocities that are nearly constant withfrequency. In isolation, these lines exhibit a single-ended characteristic
impedance, phase velocity, and attenuation. As a pair of these lines are
moved closer together, coupling occurs that signiﬁcantly alters the transmission line parameters and makes possible the propagation of differential and common-mode guided waves.
The odd-mode differential impedance observed on a symmetrical differential pair is twice the single-ended impedance of each individual line
minus the mutual impedance due to electromagnetic coupling. Strong
coupling between the conductors forming a balanced differential pair will
lower the differential impedance. In contrast, the differential impedance ofa loosely coupled pair appears as the sum of the two individual singleended impedances. This is shown explicitly in the following equation

Z diff = ( Z 11 – Z 12 + Z 22 – Z 21 )For symmetrical structures may be given by

Z diff = 2 ⋅ ( Z 11 – Z 12 ) = 2 ⋅ ( Z 22 – Z 21 )
where

Z =

Z 11 Z 12
Z 21 Z 22

Zdiff may is also given by

Z diff = 2 ⋅ Z odd
where Zodd is the odd impedance. Similarly the common mode impedance may be given by:

Z cm = 0.5 ⋅ Z even

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XFP Speciﬁcation
REVISION 4.5

Differential S-Parameters and TDR

August 31, 2005

where Zeven is the even impedance.

12
C.3 4 PORT SINGLE-ENDED S-PARAMETER DEFINITION3
Any 4 terminal device may be deﬁned as the ratio of two normalized power 4
wave (the response divided by the stimulus). A block diagram of a 4 port 5
device is shown in Figure 58.
6
7
8
Port 1
Port 2
9
10
DUT
11Port 3
Port 412
13
14
Figure 58 4 Port DUT
15
16
The 4 port S-Parameter matrix is given below.
17
18
19
Stimulus Ports
20
21
S 11 S 12 S 13 S 14
22
23
Sxy = Response S 21 S 22 S 23 S 24
24
S 31 S 32 S 33 S 34
Port25
S 41 S 42 S 43 S 4426
27
28
C.4 2 PORT MIXED MODE DIFFERENTIAL S-PARAMETER DEFINITION29
The single ended S-parameters are deﬁned as voltages and currents in 30
reference to ground. In the case of a 2 Port Differential DUT, differential
31
and common mode voltages and currents are deﬁned for each balanced
32
port. A block diagram of a two port differential mixed mode is shown in33
Figure 59.
34
35
36
37
DUT
Port 1
Port 238
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40
41
Figure 59 Differential 2 Port DUT
42
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REVISION 4.5

Differential S-Parameters and TDR

August 31, 2005

The mixed-mode differential S-Parameters can be organized similar to the 1
single ended S-Parameters. The mixed mode differential S-matrix con2
sists of common mode and differential responses. The 2 Port Differential 3
S-Parameters (Mixed-Mode) are given below:
4
5
6
7
8
Common Mode toDifferential Mode toDifferential-Mode
Common-Mode
Differential
Mode
Differential Mode
9
Stimulus
Stimulus
Conversion
Response
10
Port 1 Port 2
Port 1
Port 21112
Differential Port 1
SDD11
SDD12
SDC11
SDC12
Mode
13
Response
Port 2 SDD21 SDD22 SDC21 SDC22
14
Smn =
• •
15
Port 1 SCD11 SCD12 SCC11 SCC12
CommonMode
16Port 2 SCD21 SCD22 SCC21 SCC22
Response
17
18
19
Differential Mode to
Common Mode to20
Common Mode
Common Mode21
Conversion
Response
22
23
The differential mode to differential mode performance, SDDxx, are the 24
pure differential mode operation. If differential coupling is small, then the 25
differential mode parameters are reduced to a 2-port single ended S-pa- 26
rameters. The differential mode to common mode conversion, SCDxx,
27should ideally be equal to Zero with perfect symmetry as it relates to the 28
generation of EMI. The common mode stimulus to differential mode con- 29
version, SDCxx, indicates susceptibility of a device to EMI and should be30
ideally zero. Common mode stimulus to common mode response indicate
31
performance of the device under common mode.
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REVISION 4.5

Differential S-Parameters and TDR

August 31, 2005

The mixed mode differential S-Parameters may be written in terms of the 1
two port single ended S-Parameters as the following:
2
3
4
5
6
7
S 11 – S31 – S13 + S 33 S 12 – S 32 – S14 + S 34 S11 – S 31 + S 13 – S 33 S 12 – S 32 + S 14 – S 34 8
9
mn 1 S 21 – S 41 – S 23 + S43 S22 – S 42 – S 24 + S 44 S 21 – S 41 + S 23 – S43 S 22 – S 42 + S 24 – S 44
S=10
2 S 11 + S 31 – S 13 – S33 S12 + S32 – S 14 – S 34 S11 + S 31 + S 13 + S33 S 12 + S32 + S 14 + S34
11
S 21 + S 41 – S 23 – S43 S22 + S42 – S 24 – S 44 S21 + S 41 + S 23 + S43 S 22 + S42 + S 24 + S44 12
13
14
15
A commonly available two ports Vector Network Analyzer with standard 16
calibration technique and the above relationship can be used to test for 17
compliance to the XFI channel. If a 4 port VNA is available then the differ- 18
ential and common mode parameters can be measured directly.
19
20
SDD21 is given by:
21
22
23
1
SDD21 = --- ( S21 – S 41 – S23 + S43 )
24
2
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26
27
28
If the differential channels is symmetrical, then:29
30
S21 = S43, S41 = S23, S12 = S34, S14 = S32, S11 = S33, S22 = S44
31
In a typical application where the channel meets the XFI speciﬁcation for 32
differential return loss SDD21 can be approximated by the single ended 33
S-Parameter:
34
35
36
37
SDD21 ≅ ( S21 – S41 ) ≅ S 21.
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REVISION 4.5

Optimum Via Design

August 31, 2005

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Via structures allow PCB designers to route circuit traces between layers 7of a multilayer board. Vias may be particularly useful to transition from the 8pins of a BGA or connector down to stripline traces within a host or trans9
ceiver board. The most common and inexpensive via structure is the socalled through-hole via. A through-hole via is manufactured by drilling all 10
the way through the PCB followed by a plating process. The plating pro- 11
12cess provides electrical continuity to top and buried traces by virtue of
signal pads located on the desired layers. Alternatives to the through-hole 13
via are the blind via and the back-drilled via. Although these alternatives 14
may provide higher performance, it is generally believed that most XFP
15
adopters will use the lower cost through-hole via for volume manufac16
turing.
17This section examines single-ended and differential through-hole vias for 18
XFI implementation. Guidelines are provided for trace routing and for par- 19
ticular via dimensions.
20
21
22
23
24
Figure 60 depicts a single-ended through-hole via that provides a transition from the top layer to the next adjacent layer in a 16-layer PCB. Only 25
26that portion of the via between the adjacent layers is used for electricalpath. The remaining portion provides an electrically short open-circulated 27
transmission line stub. The additional reactance that results tends to lower 28
the characteristic impedance and hence causes reﬂections. A much
29
better approach is to route traces as shown in Figure 61. By transitioning 30
from the top layer to a layer near or on the opposite side of the board min31
imizes the size of the open circulated stub and hence minimizes electrical32
reﬂections.
33
Full-wave, 3D electromagnetic simulations were performed using Ansoft 34
High Frequency Structure Simulator (Ansoft HFSS™). The simulations
35
were used to evaluate the relative performance of via structures with and 36
without open-circulated stubs. Figure 62 is a plot of the extracted s-pa37
rameters for transitions from the top layer to various layers of a 16-layer
38
PCB. The red curve is for trace routing from the top to the bottom layer
39
and yields the best performance (lowest reﬂections).
40
41
42

APPENDIX D: OPTIMUM VIA DESIGN

D.1 VIAS

D.2 SINGLE-ENDED VIAS

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REVISION 4.5

Optimum Via Design

August 31, 2005

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Figure 60 Single-ended via with electrical path between adjacent 17
layers leaves an open-circuit stub causing poor impedance match.
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Figure 61 Preferred method for trace routing with vias. Routing theelectrical path from the top layer to a layer near or on the opposite side of 35
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REVISION 4.5

Optimum Via Design

August 31, 2005

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21
Figure 62 Simulated return loss (s11))
22
23
24
Because the XFI interface is differentially signaled, vias are generally ex- 25
pected to occur in pairs. These differential vias are used to route signals 26
from top layer microstrip traces down to buried stripline traces. Figure 63 27
shows a differential via geometry with a pair of via structures traversing
28
through several power and ground planes on a 100mil thick multilayer
PCB. Critical dimensions are the via diameter (drill size), pad diameter, 29
gap between the pad and the ground/power plane cutout, and via pitch. 30
Fullwave 3D electromagnetic simulations were performed to identify di- 31
mensions that would minimize reﬂections and provide the best signal ﬁ- 32
delity. The tunable parameters are the via pitch and gap as illustrated in 33
the Figure 64.
34
35
Two board thicknesses were considered for the simulations: a 100 mil
thick board and a 62 mil thick board. A parametric sweep of via pitch and 36
gap revealed that the best performance was achieved using the dimen- 37
38
sions outlined in Table 64. Interestingly, the dimensions for both board
thicknesses are identical. This can be explained by considering the via
39
structure as a transmission line with propagation along the dimension per- 40
pendicular to the PCB plane. It is intuitive that this transmission line
41
42
the board minimizes the open-circuited stub.

D.3 DIFFERENTIAL VIAS

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REVISION 4.5

Optimum Via Design

August 31, 2005

should have a uniform cross-section that is independent of the length ofthe line (board thickness).

Figure 63 Differential via geometry a 100mil multilayer PCB.

Table 64 Optimized differential via geometry for 100 mil and 62 mil thick PCBParameter

XFP MSAGap (mm)

Via Pitch (mm)Drill Size (mm)Pad Diameter (mm)

100 mil Board

0.52

0.8

0.3

0.56

62 mil Board

0.52

0.8

0.3

0.56

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XFP Speciﬁcation
REVISION 4.5

Optimum Via Design(a) 100 mil

August 31, 2005(b) 62 mil

Figure 64 S-parameters for optimized via structures withdimensions given in Table 1. (a) 100 mil thick PCB. (B.) 62 mil thickboard.

D.4 GSSG DIFFERENTIAL VIAS
An improvement to the traditional differential via is to utilize a groundsignal-signal-ground (GSSG) geometry. The GSSG differential via consists of four single-ended vias as shown in Figure 65. The two inner vias
are the differential signal lines and the outer two vias are ground returnlines. Although differential signaling generally provides for all return pathcurrents, the GSSG geometry can support common-mode signals with awell-controlled return current path. Any common-mode signals that get
coupled or generated can propagate through the via (rather than being
scattered) and along the transmission line to the receiver where it is terminated.
Critical dimensions for the GSSG geometry are via diameter (drill size),
pad diameter, gap between the pad and the ground/power plane cutout,
via pitch, and via-to-ground via. With the additional conductors of the
GSSG structure, there are more tunable parameters that can be used toprovide optimal performance. Fullwave 3D electromagnetic simulations
were performed to optimize the geometry on a 62-mil stack up. Table 65
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XFP Speciﬁcation
REVISION 4.5

Optimum Via Design

Gap (mm)
0.32
0.32
0.52
0.52

XFP MSA

August 31, 2005

provides four alternative GSSG via dimension combinations that provide 1
acceptable performance.
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22
Figure 65 GSSG via structure
23
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25
26
Table 65 Four alternative GSSG via dimension
27
28
Via-To_Ground
Via Pitch (mm)Drill Size (mm)Pad Diameter (mm)
(mm)
29
30
1.0
0.7
0.3
0.56
31
1.0
1.0
0.3
0.56
32
0.8
0.7
0.3
0.56
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34
0.8
1.0
0.3
0.56
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REVISION 4.5

Optimum Via Design(a)S11XFP MSA

August 31, 2005

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20
(B)S2121
Figure 66 Extracted s-parameters for the four alternative GSSG via 22
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REVISION 4.5

Jitter Methodology and Measurement

August 31, 2005

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2
3
4
5
6
This annex describes requirements for determining eyemask compliance. 7
Mask templates and coordinates are given in the appropriate subclauses 8
in clause 2.
910• Compliance is to be assured during system operation. However,measurements with patterns such as PRBS23 or a valid 10GBASE-R 11
or 10GBASE-W or OC192c or STM-64 signal are likely to give similar 12
results.
13• During test, both transmit and receive paths must be active to include 14
the effects of crosstalk. Trafﬁc in the other direction (than the one be- 15
ing tested) must use a asynchronous clock
16
17• Compliance at higher rates can qualify for lower rates, however the
opposite is not allowed.
18• Testing may include guard banding, extrapolation, or other methods, 19
but must ensure that mask violations do not occur at a rate above 1E- 20
12.
21
22
• The eye template is to be measured differentially.
23• If AC coupling is used, the 3dB corner frequency shall be set sufﬁ24
ciently low to avoid adding baseline wander into the measurement.
25• All loads are speciﬁed at 100 ±5 Ω differential.
26• Zero “0” and One “1” on the unit interval scale are to be determined27
by the eye crossing means measured at the average value (zerovolts) of the eye pattern, as illustrated in Figure 67. The average val- 28
29
ue might not be at the jitter waist.
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42

APPENDIX E: JITTER METHODOLOGY AND MEASUREMENT

E.1 EYE MASK COMPLIANCE

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REVISION 4.5

Jitter Methodology and Measurement

August 31, 2005

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2
3
+Vpk
4
5
0
6
Data Eye
78-Vpk
9
Zero Crossing
10
Histogram
11
12
Template Alignment
13
0 UI
14
1 UI
15
Figure 67 Eye Template Alignment
16
17
18
19
20
21
Oscilloscope
+Data
22
Data
23
DUT
24
25
Trigger
26
CRU
27
28
29
Figure 68 Eye mask measurement setup - block diagram.
30
A clock recovery unit (CRU) should be used to trigger the scope for mask 31
measurements as shown in Figure 68. It should have a high frequency
32
corner bandwidth of 4 MHz and a slope of –20 dB/decade with maximum 33
peaking of 0.1 dB.
34
35
36
37
38
39
40
41
42
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REVISION 4.5

Jitter Methodology and Measurement

August 31, 2005

E.2 NON-EQJ JITTER EYE MASKDUT

XFP MSA

1
Compliance point B and D are required to have bounded non-EQJ jitter. 2
This test guarantees that the total jitter is not overwhelmed by the DCD 3
and random jitter. The setup is similar to the standard eye mask measure- 4
ment but the eye is measured with and without the inverse channel ﬁlter. 5
The block diagram of the measurement is shown in Figure 69.
6
7
8
9
10
11
EQ Filter
Oscilloscope
12
+Data
13
- Data14
15
Trigger
16
CRU
17
18
19
Figure 69 Eye mask measurement setup - block diagram.
20
21
EQ Filter is based on the inverse response of the channel, where thechannel is speciﬁed in section 3.5. An approximate EQ ﬁlter may be con- 22
structed with following characteristics:
23
24
25
26
fl + if
27
H ( f ) = ----------------fu + if
28
29
Where:
ﬂ=2.5 GHz
fu=5 GHz
30
31
32
In addition the ﬁlter must meet:
33• SDD21 accuracy must meet ± 1dB from 1MHz to 10 GHz.
34
• SDD11 > 20 dB from 1MHz to 10 GHz
35
36• Differential Skew <5 ps
Alternatively the waveform may be captured and the above ﬁlter response 37
may be applied by post processing. It is also expected some time in the 38
future there will be Time Interval Analyzer (TIA), which can measure the 39
non-EQJ jitter directly.
40
41
42
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REVISION 4.5

Jitter Methodology and Measurement

August 31, 2005

E.3 STRESS EYE TEST FOR RX TOLERANCE TESTING
E.3.1 INTRODUCTION

E.3.2 TEST EQUIPMENT

E.3.3 TYPES OF JITTERXFP MSA

1
2
3
This clause provides guidance for jitter tolerance testing at compliance
points B’, C, and D with input jitter and vertical eye closure as speciﬁed 4
5respectively in Table 17, Table 15, and Table 11 as given in Chapter 3:.
6
The applied jitter combines ISI (equalizable portion of jitter) and non-EQJ 7
jitter (non-equalizable portions of jitter). The receiver under test shall tol- 8
erate an additional sinuosidal jitter (SJ) term as deﬁned by the appropriate
9
Telecom and/or Datacom requirements in this document.
10
11
MJSQ1 and OIF CEI2 both provide further information on deﬁnitions,12
setups, calibration and methods for jitter tolerance testing.
13
14
15
16
Beyond calibrated jitter and eye closure properties, the test source should 17
be within the requirements for common mode voltages, return loss, etc. 18that are given in Chapter 3:. Return loss of the test source should be near
19
ideal.
20
Jitter generation mechanisms can be based on phase modulation at the 21
clock source or pattern generator input or output. Any approach that mod- 22
ulates or creates the appropriate levels and frequencies of the jitter com- 23
ponents is acceptable.
24
25
An RF attenuator or output amplitude control of the test source may be re26
quired to set the vertical eye opening of the stressed eye.
27
28
29
30
The XFP speciﬁcation allows variation and freedom in allocation and31
types of jitter within the bounds given in Table 17, Table 15, and Table 11. 32
As such, there is no single tolerance test setup than can fully represent all 33
the possibilities. However, some considerations are given below.
34
non-EQJ jitter can include duty cycle distortion (DCD), random jitter (RJ), 35
and periodic jitter (PJ). Non-EQJ jitter is uncorrelated to the primary data 363738
1. Information Technology - Fibre Channel - Methodologies for Jitter and Signal
39
Quality Speciﬁcation - MJSQ, Project 1316-DT/Rev 14, June 9, 2004.
2. Optical Internetworking Forum - IA # OIF-CEI-02.0 - Common Electrical I/O 40(CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps and 11G+
41
bps I/O, February 28th, 2005
42
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REVISION 4.5

E.3.4 CALIBRATIONXFP MSA

Jitter Methodology and Measurement

August 31, 2005

stream with exception of the DCD and so cannot be equalized by the re- 1
ceiver under test. It can exhibit a wide spectrum.
2
3
Noticeable amounts of DCD are rare at compliance points B’, C, and D. If
4
DCD is used for compliance testing, it should not exceed 0.05 UI pk-pk.
5
DCD can be viewed when transmitting a repeating 1010 pattern.
6
Moderate amounts of RJ are possible at compliance points B’, C, and D, 7
typically attributable to the clock source and/or a CMU. Large amounts of 8
RJ are not common, though, and so if RJ is used for compliance testing, 9
the following advice is given:
1011• the RJ magnitude should not exceed 0.2 UI pk-pk (at 1E-12 probabil12
ity);13• the RJ should be ﬁltered with a 10 MHz high-pass ﬁlter to reduce
14
sensitivity to variations in CDR tracking;15• the upper cutoff frequency for the RJ should be at least 80 MHz.
16
Single frequency PJ is sinuosidal jitter, and can be considered as another 17
form of non-EQJ jitter. However, single frequency PJ is not common in
18
normal operation and is harsh as a form of non-EQJ jitter for compliance19
testing at B’, C, and D. If single frequency PJ is used, its frequency(s)should be generally above the tracking bandwidth of the CDR of the port 20
being tested. Note - this use of sinuosidal jitter is in addition and should 21
not to be confused with the SJ tolerance mask templates speciﬁed in the 22
document.
23
24
A versatile option for PJ is to employ multi-tone jitter created by a PRBS
25
generator. PRBS jitter has a distributed spectrum and can be low-pass ﬁltered to produce a more normal probability density function (pdf) for non- 26
27
EQJ jitter. MJSQ and CEI have more information on this approach.
28
To create non-EQJ & ISI jitter, a section of PCB is recommended to emu- 29
late the behaviors expected in an application. The length and construction 30
details are left to the user, but when completed, the required values for
31
Total Jitter and non-EQJ jitter should be satisﬁed. Coaxial cable typically32
exhibits a different response, both in magnitude and phase.
33
34
35
36
The signal should be calibrated differentially through a standard compli- 37
ance test ﬁxture (see Appendix A:) and into standard instrumentation38
loads. If complementary single-ended signals are used, be sure they are 39
carefully matched in both amplitude and phase.
40
41
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REVISION 4.5

Jitter Methodology and Measurement

August 31, 2005

Except for sinuosidal jitter, all calibration should use a single pole highpass jitter ﬁlter with -3 dB frequency at 4 MHz.

1
2
3
The jitter is deﬁned at a probability level of 1E-12, consistent with the re4quirements of Annex E.1. To calibrate the jitter, methods given in MSJQ
and CEI are recommended. Given random jitter and the nature of the long 5
test patterns, low probability jitter events may be present. A technique that 6
can accurately measure low probability events is recommended to avoid 7
an overly stressful test condition.
8
9
The vertical eye opening is deﬁned at a probability level of 1E-12, consis- 10
tent with the requirements of Annex E.1. Like jitter, low probability vertical11
closure may be present, and if not accurately measured and accounted
12
for in calibration, could lead to an overly stressful test condition.
13
14
15
E.3.5 TESTING
16
Operate the system with the appropriate data pattern for the application - 17
SONET, 10G Ethernet, 10GFC, or G.709 then test applicable compliance 18
points B’, C, or D.
19
All signals and reference clocks that operate during normal operation shall 20
be active during the test including the other signal path in the duplex pair. 21
The other signal path shall be asynchronous and up to the maximum al- 22
lowable differential PPM value given in the appropriate protocol speciﬁca- 23
tions.
24
25
Apply the SJ tolerance masks, at each SJ tolerance frequency verify that26
the DUT provides a BER of at least 1E-12 at the applicable compliance27
points B’, C, or D.
28
2930
E.4 JITTER PEAKING SPECIFICATIONS AND MEASUREMENTS
31
In Section 3.9 of the XFP MSA, module jitter peaking speciﬁcations are 32
given for datacom and telecom modules for both the receiver and trans- 33
mitter paths. In the case of telecom modules to be used for looptiming
34
based regenerator applications, the jitter peaking below 120 KHz is limited
35
to 0.03 dB for both receiver and transmitter. This last speciﬁcation is derived from the need for the overall system jitter peaking to be kept below 36
37
0.1 dB for regenerator applications. While these requirements are be38
lieved to be practical for existing signal conditioner and module optics
technology, veriﬁcation of this performance presents considerable difﬁcul- 39
ties due to limitations of current measurement equipment. This annex de- 40
scribes these difﬁculties and suggests alternative characterization
41
42
XFP MSA

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REVISION 4.5

Jitter Methodology and Measurement

August 31, 2005

techniques to be used until appropriate measurement equipment becomes available.

12
3
Equipment exists today to do jitter transfer measurements on devices with4
electrical inputs and electrical outputs as well as for equipment with optical inputs and outputs. This type of equipment is able to achieve high ac- 5
6curacy by calibrating measurements against measurements made with
the instrument looped back to itself. Making an equivalent measurement 7of a device with electrical input and optical output, or vice versa, is more 8
problematic. Even if an instrument can make such a measurement, its ac- 9
curacy would probably be limited to far worse than 0.03 dB because a di- 10
rect input to output calibration would not be possible.
11
In order to do an electrical-to-optical or optical-to-electrical jitter transfer 12
13measurement with high accuracy, a reference optical receiver or trans14
mitter with well-characterized jitter transfer characteristics is required.
Such a reference device could be used to provide a reference calibration 15
measurement against which to compare the device under test in a system 16
conﬁgured to perform an electrical-to-optical or optical-to-electrical mea17
surement. Alternatively, a reference receiver could be used to convert the
optical output of a device under test to electrical allowing a precision elec- 18
19trical-to-electrical measurement of the combination from which thetransfer characteristics of the reference receiver could be subtracted. Sim- 20
ilarly, a reference transmitter could be used to stimulate an optical receiver 21
path under test. At this writing, such well-characterized reference trans- 22
mitters and receivers are not commercially available.
23
24
There are several means by which host system and module manufacturers can verify the required performance needed to meet the overall sys- 25
tems requirements. (Examples are given for the difﬁcult 0.03 dB peaking 26
27case, but the same logic applies to the 1 dB peaking requirement for
datacom modules).
28
29
5. Overall System Measurement
30
Host system manufacturers can qualify modules for jitter peaking by 31
measuring them in the desired ﬁnal system environment. A module
32
under test can be placed in the target host system and the overall
33
system optical-to-optical jitter transfer can be measured by placing thesystem in a looptiming loopback mode (which should be below 0.1 dB 34
35
at 120 KHz or less). For further accuracy, the host system’s jitter36
peaking can be separately measured and subtracted from the total
measurement to approximate the module’s total transmit and receive 37
path peaking which should be less than 0.06 dB below 120 kHz. This 38
measurement can be achieved by measuring the system’s electrical to 39
electrical jitter peaking by substituting a host compliance test coupon
40
for the module under test.
41
42
XFP MSA

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REVISION 4.5

Jitter Methodology and Measurement

August 31, 2005

6. Module Total Jitter Peaking Measurement

1
A useful, but not complete measurement can be made of the module 2
3
jitter peaking directly by testing the module with the optical output
looped back using an electrical-to-electrical jitter peaking test, or by 4looping the electrical output back to the transmitter input and per5
forming an optical to optical measurement. In this case a measure of 6
the sum of the transmit and receive path peaking is made. This should
7
be less than 0.06 dB below 120 KHz, though this still allows for the8
possibility that either the receive or transmit paths are greater than
9
0.03 dB.
10
7. Measurement of Module Signal Conditioner
11
It is expected that the low frequency jitter transfer characteristics of an 12
13
XFP module will be dominated by the signal conditioners in thetransmit and receive paths. While not a useful module compliance test, 14
a module manufacturer can determine likely module jitter peaking per- 15
formance by separately characterizing the performance of the signal 16
conditioners used in the modules under likely worst-case conditions.
17
Such measurements should be done with the signal conditioners in a18
test environment as similar as possible to that of the ﬁnal module.
These measurements do have the advantage that they can be used to 19
20
separately characterize the module receive and transmitter paths.
21
While none of the above techniques is a perfect substitute to a direct com- 22
pliance test of module jitter peaking, they probably provide a reasonable
23
alternative until appropriate test equipment is developed.
24
25
26
E.5 AC COMMON MODE TEST27
To minimize generation of common mode noise and associated EMI, XFI 28
limits the maximum common mode voltage at the compliance point. The 29
common mode voltage is measured by subtracting the differential output 30
on the scope. The RMS value are calculated by applying the Histogram 31
function to the common mode signal. Common mode measurement are
32
speciﬁed for the following test point:
33
34• A 15 mV RMS - Output
35• B 25 mV RMS - Output
36• C’ 15 mV RMS - Output
37• D 25 mV RMS - Input.
38
39
40
41
42
XFP MSA

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Copyright © 2002-2005 by XFP MSAXFP Speciﬁcation
REVISON 4.5

E.6 TERMINATION MISMATCH

Test Frequency

XFP MSA

Mechanical and Board deﬁnition

August 31, 2005

1
2
Termination mismatch is deﬁned as the difference between the complimentary Rp and Rn resistors as shown in Figure 5. Measuring termination 3
4
mismatch through an AC coupling capacitor requires access to the IC.
Termination mismatch is deﬁned as:
5
6
7
R p – Rn
8
∆Z M = 2 × ------------------- × 100
R p + Rn
9
10
Alternatively, the termination mismatch can be measured by applying a 1112
low frequency test tone to the differential inputs as shown in Figure 70.
The test frequency must be high enough to overcome the high pass ef- 13
fects of the AC coupling capacitor. Low frequency termination mismatch 14
is then given by:
15
16
17
I p – I n R diff + 100
18∆Z M = 2 × ----------------- ⋅ --------------------------- ⋅ 100
I p + InR diff19
20
21
where Ip and In are the current ﬂowing in to the XFI port as shown in
22
Figure 70.
23
24
25
26
27
XFI Port
28
Ip
Capacitor
Rp
29
Rt50Ω 0.5%30
50Ω 0.5%31
Rn
32
Capacitor
In
33
34
35
36
37
Figure 70 AC Termination Mismatch Measurement
38
39
40
41
42
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REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

E.7 POWER SUPPLY NOISE TESTING METHODOLOGY12
3
E.7.1 POWER SUPPLY NOISE COMPLIANCE
4
The module is speciﬁed to tolerate 2% of broadband noise amplitude on 5
the power supply at frequencies up to 1 MHz, then 3% for frequencies up 6
to 10Mhz. This methodology covers test methods to assure compliance 7
to the XFP speciﬁcation.
8
9
10
11
E.7.2 POWER SUPPLY NOISE METHODOLOGY
In this test noise is injected to the power supply rail from a function gen- 12
erator generating a sine wave. The noise measurement set up is shown 13
14
in Figure 71. The noise is AC coupled into the test board and the DC
power is coupled in through an inductor to keep the noise from sinking into 15
the power supply. The inductor should be optimized for maximum noise at 16
the test point over all frequencies tested. The amplitude should be mea17
sured at the connector on the test board with the module plugged in. Thisassures the noise induced into the module is ﬁltered within the module re- 18
gardless of amount of test board decoupling. The required amplitude of 19
the noise signal generator will vary from different test boards due to de- 20
coupling and layout differences. The typical noise amplitudes are listed in 21
Table 66. The worst case system noise is with the module plugged into the 22
socket while achieving the desired amount of noise.
23
24
25
26
E.7.3 POWER SUPPLY NOISE METHODOLOGY
Tests for power supply noise compliance should include optical receiver 27
sensitivity, which can be measured with SONET GR-253 or IEEE802.3ae 28
methodologies. Also optical transmitter jitter with a worst-case electrical 29
eye as an input (Table 13) should be measured. Transmitter jitter testing 30
can be done with IEEE802.3ae eyemask and Tpd measurements, or
31
SONET GR-253 jitter generation measurements. Testing should look at32
the difference of these parameters with and without the noise present.
The noise source frequency should be varied from 0 to 10Mhz to deter- 33
mine if any frequency causes a parameter to fall out of the speciﬁcation 34
limit. In all cases, the parameters measured should pass the optical stan- 35
dards with the noise present over all frequencies speciﬁed.
36
37
38
39
40
41
42
XFP MSA

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REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

Function Generator
SinewaveDC
Block

Ground
XFP
Test
Board

Power Supply
DC Voltage

Toriodal Inductor

Test Point at
Connector

Figure 71 Power Supply Ripple Setup

Table 66 Noise Amplitude for XFP power supplies (Nominal)

XFP MSAPower Supply

0-1 MHz (2%)

1-10 MHz (3%)

5.0V

100mV

150mV

3.3V

66mV

99mV

1.8V

36mV

54mV

-5.2V

104mV

156mV

Page 159

Copyright © 2002-2005 by XFP MSA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

XFP Speciﬁcation
REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

1
2
3
4
5
F.1 XFI ELECTRICAL IMPLEMENTATION FOR BER 1E-15
6This Appendix describes a method to implement BER 1E-15 over XFI
7electrical interface and does not apply to optical link BER. To actually8
meet BER 1E-15 over XFI channel signiﬁcant additional care and longer
9
testing would be required to guarantee operation, which is beyond the10scope of the MSA.
11
12
Starting with XFI electrical speciﬁcations of section 3.6, BER 1E-15 or
better can be implemented by:
13
14• Reduce the transmitter output jitter in conjunction with receiver jit15
ter tolerance (Incompatible with standard XFI components)
16• Reduce the interconnect jitter budget (Compatible with standard 17
XFI components)
18
XFP MSA implementation for BER of 1E-15 is based on reducing the in- 19
terconnect jitter budget. XFP MSA implementation relies upon by re20
ducing the interconnect trace length by 20% as listed in Table 67.
21
Please use jitter tables in this Annex to implement XFI channel for BER 22
1E-15. These tables are replacement for associated jitter tables in Section 23
3.6. Jitter table in this Annex are adjusted in the following fashion to24
achieve BER 1E-15 and maintain compatibility with standard XFI speciﬁ- 25
cations:
26
27• Output jitter values are increased by adjusting for Q of 16 (BER28
1E-15) but the total jitter is the same as section 3.6 for Q of 14
29(BER 1E-12).
30• Receiver input jitter values are reduced by adjusting for Q of 16(BER 1E-15) but the total jitter is the same as section 3.6 for Q of 31
32
14 (BER 1E-12).
33
Table 67 Host Board Interconnect for BER 1E-15
34
35
Trace Width
Trace Length
Type
Material
Loss Tan
Copper (oz)
(mm)
(mm)
36
37
Microstrip
4000-6
0.3
0.025
1
160
38
4000-13
0.3
0.016
1
240
39
Stripline
4000-6
0.125
0.025
1/2
120
40
41
4000-13
0.125
0.016
1/2
160
42

APPENDIX F: XFI IMPLEMENTATION FOR BER 1E-15

XFP MSA

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REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

F.1.1 XFI ASIC/SERDES TRANSMITTER OUTPUT JITTER SPECIFICATIONS AT A FOR BER 1E-15

1Table 68 is replacement forTable 9 XFI ASIC/SerDes Transmitter Output 2
3
Jitter Speciﬁcations at A.
4
Table 68 XFI ASIC/SerDes Transmitter Output Jitter Speciﬁcations at A for BER 1E-15 5
6Transmitter - A
SymbolConditions
Min
Typ
Max
Units
7
Determinstic Jitter for Q of 16
DJ
See E.1, 1
0.15
UI (p-p)8
Total Jitter for Q of 16
TJ
See E.1, 1
0.321
UI (p-p)
910
Eye Mask
X1
0.161
UI
11
Eye Mask
X2
0.4
UI
12
13
Eye Mask
Y1
180
mV
14
Eye Mask
Y2
385
mV
15
16
Jitter Generation for Telecom Applications
50KHz to 8 MHz
6.5
mUI (RMS)
17
see 2
18
1. In loop timing mode, includes jitter that transfers through the ASIC from the receiver during any valid operational input
19
conditions.
2. Measured with a ﬁlter with 50 KHz high-pass cutoff desinged frequency and 8 MHz low pass cut off frequency. The ﬁlter rolls off
20
at least for one decade on each side of the passband with -20 dB/Dec Does not apply to a host designed with Optional Synchronous21
CMU clock, when used in conjunction with a Synchronous CMU module 3.10.1.
22
23
F.1.2 XFI ASIC/SERDES RECEIVER INPUT JITTER SPECIFICATIONS AT D FOR BER 1E-15
24
Table 69 is replacement forTable 11 XFI ASIC/SerDes Receiver Input
25
Jitter Speciﬁcations at D.
26
27
Table 69 XFI ASIC/SerDes Receiver Input Jitter Speciﬁcations at D for BER 1E-15
28
Receiver- D
SymbolConditions
Min
Typ
Max
Units
29
30
Total Jitter for Q of 16
TJ
See E.1, E.2
0.65
UI (p-p)31
Total non-EQJ Jitter for Q of 161
See E.1, E.2
0.45
UI (p-p)32
Sinusoidal Jitter Tolerance
SJ
E.3
see 2
33
34
Eye Mask
X1
Note 30.325
UI
35
Eye Mask
Y1
55
mV
36
37
Eye Mask
Y2
Note 4525mV
38
1. Total Jitter less ISI.
39
2. Sinuosidal jitter tolerance for Telecom and Datacom respectively given by Figure 9 and Figure 10.
40
3. Mask coordinate X1=0.225 if total non-EQJ jitter is measured.
41
4. Out of 525 mV, 100 mV is allocated for multiple reﬂection.
42
XFP MSA

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REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

F.1.3 XFI HOST TRANSMITTER OUTPUT JITTER SPECIFICATIONS AT B FOR BER 1E-15

1
2
Table 70 is replacement forTable 13 XFI Host Transmitter Output Jitter
3
Speciﬁcations at B.
4
Table 70 XFI Host Transmitter Output Jitter Speciﬁcations at B for BER 1E-15
5
6Receiver- B
SymbolConditions
Min
Typ
Max
Units
7
Total Jitter for Q of 161,
TJ
See E.1
0.61
UI
8
1
Total non-EQJ Jitter for Q of 16
See E.1, E.2
0.41
UI
9
10
Eye Mask
X1
see 2
0.305
UI
11
Eye Mask
Y1
60
mV
12
Eye Mask
Y2
see 3
410
mV
13
14
Jitter Generation at B Telecom Applications
50KHz-8MHz, see 4
7mUI (RMS)
15
1. In loop timing mode, includes jitter that transfers through ASIC from the receiver during any valid operational input conditions.
16
2. Mask cordinate X1=0.205 if total non-EQJ jitter is measured.
17
3. Out of 410 mV, 25 mV is allocated for multiple reﬂection.
18
4.Measured with a ﬁlter with 50 KHz high-pass cutoff desinged frequency and 8 MHz low pass cut off frequency. The ﬁlter rolls off
19
at least for one decade on each side of the passband with -20 dB/Dec. Does not apply to a host designed with Optional Synchronous
CMU clock, when used in conjunction with a Synchronous CMU Signal Conditioner module see 3.10.1.
20
21
22
23
F.1.4 XFI Host Receiver Input JITTER SPECIFICATIONS AT C FOR BER 1E-15
24
Table 71 is replacement forTable 15 XFI Host Receiver Input Jitter Speci25
ﬁcations at C.
26
27
Table 71 XFI Host Receiver Input Jitter Speciﬁcations at C
28
Transmitter - C
SymbolConditions
Min
Typ
Max
Units
29
Determinstic JitterDJ
See E.1
0.18
UI (p-p)30
31Total Jitter for Q of 16
TJ
See E.1
0.363
UI (p-p)32
Sinusoidal Jitter Tolerance
SJ
E.3
see 1
33
34
Eye Mask
X1
0.181
UI
35
Eye Mask
X2
0.42
UI
36
37
Eye Mask
Y1
170
mV
38
Eye Mask
Y2
see 2
425
mV
39
40
1. Sinuosidal jitter tolerance for Telecom and Datacom respectively given by Figure 13 and Figure 14.
41
2. Out of 425 mV, 25 mV is allocated for multiple reﬂections.
42
XFP MSA

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REVISON 4.5

Mechanical and Board deﬁnition

August 31, 2005

F.1.5 FI Module Transmitter Input Jitter Speciﬁcations at B’ FOR BER 1E-15
Table 72 is replacement forTable 16 XFI Module Transmitter Input Electrical Speciﬁcations at B’.

Table 72 XFI Module Transmitter Input Jitter Speciﬁcations at B’ for BER 1E-15’
Receiver- B’

SymbolConditions

Total Non-EQJ Jitter for Q of 161

0.41

Total Jitter for Q of 16

Min

Typ

Max

Units

See E.1, E.2

0.41

UI (p-p)

TJ

See E.1, E.2

0.61

UI (p-p)Sinusoidal Jitter Tolerance

SJ

E.3

see 2

Eye Mask

X1

see 2

0.305

Eye Mask

Y1

Eye Mask

Y2

60

UI
mV

see 3

410

mV

1. Sinuosidal jitter tolerance for Telecom and Datacom respectively given by Figure 16 and Figure 17.
2. Mask cordinate X1=0.205 if total non-EQJ jitter is measured.
3. Out of 410 mV, 50 mV is allocated for multiple reﬂection.

F.1.6 XFI Module Receiver Output Jitter Speciﬁcations at C’ FOR BER 1E-15
Table 73 is replacement forTable 19 XFI Module Receiver Output Jitter
Speciﬁcations at C’.

Table 73 XFI Module Receiver Output Jitter Speciﬁcations at C’ for BER 1E-15
Transmitter - C

SymbolConditions

Determinstic Jitter

DJ

Total Jitter for Q of 16

TJ

Eye Mask

Min

Typ

Max

Units

See E.1, 1

0.18

UI (p-p)

See E.1, 1

0.363

UI (p-p)

X1

0.181

UI

Eye Mask

X2

0.42

UI

Eye Mask

Y1

Eye Mask

Y2

170

mV
425

mV

1. Includes jitter transfered from the optical receiver during any valid operational input condition.

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XFP Speciﬁcation
REVISON 4.5

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G.1 MODULE THERMAL POWER CLASSES
6
7
XFP has four possible power classes:
8910• Power Level 1 modules – Up to 1.5 W
11• Power Level 2 modules – Up to 2.5 W
12• Power Level 3 modules – Up to 3.5 W
13• Power Level 4 modules – Greater than 3.5 W
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The module vendor is responsible to identify the power level of their mod- 16
ule to the system designer.
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G.2 THERMAL TEST RECOMMENDATION
19
The purpose of this appendix is to provide guidance to XFP module designers in creating a standard test environment for simulation and/or ac- 20
21tual testing. It allows for “one” initial means of communication between
22
module designers and system users.
23
XFP is designed with an adaptable approach to thermal management al- 24
lowing use of a single module design in a wide variety of host25
environments. The tests described in this appendix focus on a module’s
26
thermal performance within a deﬁned system level environment. Host
system designs will often optimize one or more of the following parame- 27
ters to achieve lower XFP case temperatures: module spacing, heatsink 28
shape/length/width/ﬁn design, and airﬂow direction/mixing.
29
30
The tests deﬁned in this appendix are intended to be easy to produce by 31
module manufacturers. For example, the number of modules on a host32
card has been limited to 4 and a heat sink has been deﬁned for thistesting. Module manufacturers may choose to provide additional test data 33of their module in customer speciﬁc applications that may have more or 34
35
less modules, other heat sinks, or environments.
36
Substantial variations in module thermal performance can occur de37
pending on system level design. This appendix does not guarantee
38
system level performance, as each system will be designed independentof this document per the end user system requirements. It is the respon- 39
sibility of the system designer to ensure the thermal characteristics meet 40
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APPENDIX G: MODULE THERMAL TESTINGXFP MSA

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their individual system needs. All characterization results presented in this 1appendix are intended as examples only.
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G.3 THERMAL TEST CONFIGURATION
6
There are two unique system environments anticipated for XFP trans7
ceivers. One environment is a PCI envelope with limited vertical space,minimal airﬂow, and 1-2 transceivers (System A). In this envelope sufﬁ- 8
cient space is not available for a cage mounted heat sink. A second envi- 910ronment has more vertical space and forced airﬂow across a larger
number of transceivers (system B)
11
12
Information presented by the module vendor in relation to this document
13
should be obtained from a 'conﬁned or ducted ﬂow' described as:
1415• A duct deﬁned by the host board on the bottom, a plane above16
the host board Table 74, the host board bezel, and a verticalplane 81 mm from the host board bezel.
17• PCB host board should have no copper content between planes 18
19
except for grounding of the cage.
• An insulated duct housing with poor thermal conduction must be 20
21
used i.e. a plastic.
22• Dimensions of system should allow for 4 modules on 23.5 mm
23
spacing.
• For the multiple module conﬁgurations, it is assumed that the test 24
25
conditions drawn for module 1, will be duplicated for module n.
26
i.e. the cage conﬁguration.
27• Multiple modules will be adjacent to one another with no gaps
28
from empty module slots.
29• The test chamber will be clear of obstruction for 30cm after the30
outlet.
31• A steady state should be obtained to take measurements.
32• A blower mounted so that the direction of airﬂow is side to side.
33• Case temperature measurements points may be proprietary and 34
vary from one module design to the next. Module vendors should 35
identify these to the end user for veriﬁcation in the system level36
environment.
37• Airﬂow should be characterized using a calibrated hot wire ane38
mometer placed at the airﬂow inlet
39• Thermocouples should be used to measure case temperatures. 40• An example of measurement data is shown in Figure 72.
41
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REVISON 4.5

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Inlet Air Temp (C)12
34
Max Allowable Conditions for Operation
Example of Module Temperature vs Air Flow
5
(Shall conform to IEC 60950-1)
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65
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60
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55
9
50
10
Module 1
11
Module 2
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Module 4
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40
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35
14
30
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25
0.5
1
1.5
2
2.5
3
17
18
Airflow (m/s)
1920
Figure 72 Airﬂow vs Inlet Air Temperature
21
22• Identical module types will be expected to be characterized I.E.
23
no mix of 850nm,1310nm, or 1550nm is mandated.
24• When undergoing thermal evaluation, transceivers should output 25
bi-directional data using a PRBS 231-1 data pattern.
26• Other measurement data provided is at the discretion of the ven- 27
dor.
28• The system should provide uniform airﬂow across the vent open- 29
ing and be of constant volume airﬂow.
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31
The test conditions for system A and system B are deﬁned Table 74.
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Table 74 Environmental Test Conditions
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36
Parameter
System A (PCI application)
System B (Switch application)
37
Number of modules
1 or 2
1,2,4
38
Inlet air temperature
5˚C to 50˚C
5˚C to 40˚C
39
40
Altitude
Sea Level3000 m41
Air Humidity
40% to 60%
40% to 60%
42
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REVISON 4.5

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Table 74 Environmental Test Conditions
Parameter

System A (PCI application)

System B (Switch application)

Minimum air ﬂow

100 lfm

100 lfm

Maximum air ﬂow

200 lfm

500 lfm

Free air space

14.5 mm

19 mm

No cage heat sink

Optional

MSA recommends cage
mounted heat sink

For test purposes, the MSA recommended heat sink should be used to provide
a consistent test methodologyFigure 73.

Figure 73 Heat Sink Drawing for Module Thermal Testing

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