SFF specifications are available at http://www.snia.org/sff/specifications
or ftp://ftp.seagate.com/sff

This specification was developed by the SFF Committee prior to it
becoming the SFF TA (Technology Affiliate) TWG (Technical Working
Group) of SNIA (Storage Networking Industry Association).

The information below should be used instead of the equivalent herein.
POINTS OF CONTACT:
Chairman SFF TA TWG
Email: SFF-Chair@snia.org

If you are interested in participating in the activities of the SFF TWG, themembership application can be found at:
http://www.snia.org/sff/join
The complete list of SFF Specifications which have been completed or are currently
being worked on can be found at:
http://www.snia.org/sff/specifications/SFF-8000.TXT
The operations which complement the SNIA's TWG Policies & Procedures to guide the SFF
TWG can be found at:
http://www.snia.org/sff/specifications/SFF-8032.PDF
Suggestions for improvement of this specification will be welcome, they should besubmitted to:
http://www.snia.org/feedback

** Information Specification **INF-8438i Rev 1.0

SFF Committee documentation may be purchased in hard copy or electronic form
SFF specifications are available at ftp://ftp.seagate.com/sff_________________________________________________________________

SFF-8436 QSFP+ was developed to update this specification_________________________________________________________________SFF Committee
INF-8438i Specification for
QSFP (Quad Small Formfactor Pluggable) Transceiver
Rev 1.0
Secretariat:

November 2006

SFF Committee

Abstract: This specification describes the QSFP (Quad Small Formfactor Pluggable)
Transceivers developed by the MSA (Multiple Source Agreement) group. The following
companies participated in the MSA:
Avago Technologies
Beam Express
Emcore Fiber Optics
EmulexFiberxon
FinisarForce10 Networks
Helix AGJDS Uniphase
McDATA
Merge Optics

Molex
OpnextOptical Communication Products
Picolight
QLogicReflex Photonics
The Siemon Company
Tyco Electronics
Xloom Communications
Zarlink Semiconductor

This Information Specification was not developed or endorsed by the SFF Committee
but was submitted for distribution on the basis that it is of interest to thestorage industry.
The copyright on the contents remains with the contributor.
Contributors are not required to abide by the SFF patent policy. Readers areadvised of the possibility that there may be patent issues associated with an
implementation which relies upon the contents of an 'i' specification.
SFF accepts no responsibility for the validity of the contents.
POINTS OF CONTACT:
Scott Kipp
Technical Editor
McDATA
4 McDATA Parkway
Broomfield CO 80021

I. Dal Allan
Chairman SFF Committee
14426 Black Walnut Court
Saratoga
CA 95070

720-558-3452
scott.kipp@mcdata.com

408-867-6630
endlcom@acm.org

QSFP (Quad Small Formfactor Pluggable) Transceiver

** Information Specification **INF-8438i Rev 1.0

EXPRESSION OF SUPPORT BY MANUFACTURERS
The following member companies of the SFF Committee voted in favor of thisindustry specification.
AMCC
Amphenol
Avago
Emulex
FCI
Fujitsu CPA
Hewlett Packard
Hitachi GST
JDS Uniphase
Molex
Picolight
Samsung
Sun Microsystems
Tyco
Vitesse Semiconductor
The following member companies of the SFF Committee voted to abstain on thisindustry specification.
Clariphy
Comax
Cortina Systems
Foxconn
SeagateQSFP (Quad Small Formfactor Pluggable) Transceiver

** Information Specification **INF-8438i Rev 1.0
SFF COMMITTEEThe SFF Committee is an industry group. The membership of the committee since its
formation in August 1990 has included a mix of companies which are leaders acrossthe industry.
When 2 1/2" diameter disk drives were introduced, there was no commonality on
external dimensions e.g. physical size, mounting locations, connector type,connector location, between vendors.
The first use of these disk drives was in specific applications such as laptop
portable computers and system integrators worked individually with vendors todevelop the packaging. The result was wide diversity, and incompatibility.
The problems faced by integrators, device suppliers, and component suppliers led
to the formation of the SFF Committee as an industry ad hoc group to address themarketing and engineering considerations of the emerging new technology.
During the development of the form factor definitions, other activities weresuggested because participants in the SFF Committee faced more problems than thephysical form factors of disk drives. In November 1992, the charter was expanded
to address any issues of general interest and concern to the storage industry.
The SFF Committee became a forum for resolving industry issues that are either
not addressed by the standards process or need an immediate solution.
Those companies which have agreed to support a specification are identified in
the first pages of each SFF Specification. Industry consensus is not an essential
requirement to publish an SFF Specification because it is recognized that in an
emerging product area, there is room for more than one approach. By making the
documentation on competing proposals available, an integrator can examine thealternatives available and select the product that is felt to be most suitable.
SFF Committee meetings are held during T10 weeks (see www.t10.org), and SpecificSubject Working Groups are held at the convenience of the participants. Materialpresented at SFF Committee meetings becomes public domain, and there are no
restrictions on the open mailing of material presented at committee meetings.
Most of the specifications developed by the SFF Committee have either been
incorporated into standards or adopted as standards by EIA (Electronic Industries
Association), ANSI (American National Standards Institute) and IEC (International
Electrotechnical Commission).
Suggestions for improvement of this specification will be welcome. They should besent to the SFF Committee, 14426 Black Walnut Ct, Saratoga, CA 95070.

QSFP (Quad Small Formfactor Pluggable) Transceiver

** Information Specification **INF-8438i Rev 1.0

The complete list of SFF Specifications which have been completed or are
currently being worked on by the SFF Committee can be found at:
ftp://ftp.seagate.com/sff/SFF-8000.TXT
If you wish to know more about the SFF Committee, the principles which guide theactivities can be found at:
ftp://ftp.seagate.com/sff/SFF-8032.TXT
If you are interested in participating or wish to follow the activities of the
SFF Committee, the signup for membership and/or documentation can be found at:www.sffcommittee.com/ie/join.html
or, the following application can be submitted.
Name: ____________________________ Title: __________________________
Company: ______________________________________________________________
Address: ____________________________________________________________________________________________________________________________
Phone: ____________________________ Fax: ____________________________
Email: ______________________________________________________________
Please register me with the SFF Committee for one year.
___ Voting Membership w/Electronic documentation$ 2,160___ Voting Membership w/Meeting documentation$ 1,800___ Non-voting Observer w/Electronic documentation$$

660 U.S.
760 Overseas___ Non-voting Observer w/Meeting documentation$$

300 U.S.
400 Overseas

Check Payable to SFF Committee for $_________ is Enclosed
Please invoice me for $_________ on PO #: ___________________
MC/Visa/AmX______________________________________SFF Committee
14426 Black Walnut Ct
Saratoga CA 95070

Expires_________

408-867-6630
endlcom@acm.org

QSFP (Quad Small Formfactor Pluggable) TransceiverQuad Small Form-factor Pluggable (QSFP)Transceiver Specification
Revision 1.0

QSFP Chair and Editor
Scott Kipp
McDATA Corporation
4 McDATA Parkway
Broomfield, CO 80021
Voice: 720-558-3452
Fax: 720-558-8999
scott.kipp@mcdata.com

QSFP Secretary
Alex Ngi
Helix AG
Seefeldstrasse 45
CH-8008 Zurich
Switzerland
Voice: (41) 44-260-2434
Fax: (41) 44-260-2433
an@helix.ch

This is the final released draft of this specification.

QSFP Public Specification

1

Legal Disclaimer
The promoters of the QSFP specification revision 0.96 (“QSFP MSA GROUP”), andmany contributors, collaborated to develop a specification for a Multi-channel small footprint pluggable module. The promoters stated a wish to encourage broad and rapid
industry adoption of the specification.
This version is the result of such collaboration. In the future the QSFP specification may
be offered to more formal standards bodies to further support the adoption of thespecification.
THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIESWHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY
WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION ORSAMPLE. THE QSFP PROMOTERS DISCLAIM ALL LIABILITY, INCLUDING LIABILITY
FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OF
INFORMATION IN THIS SPECIFICATION. IN NO EVENT SHALL THE QSFPPROMOTERS, CONTRIBUTORS OR ADOPTERS BE LIABLE FOR ANY DIRECT,INDIRECT, SPECIAL, EXEMPLARY, PUNITIVE, OR CONSEQUENTIAL DAMAGES,INCLUDING, WITHOUT LIMITATION, LOST PROFITS, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
This specification may contain, and sometimes even require the use of intellectual
property owned by others. No license, express or implied, by estoppel or otherwise, toany intellectual property rights is granted herein, except that a license is hereby granted
to copy and reproduce this specification for internal use only.

QSFP Public Specification2

Revision History
REVISION

RELEASE DATECHANGE

0.1

October 25, 2004

First Draft

0.2

November 25, 2004

Second Draft

0.3

December 9, 2004

Third Draft

0.4

February 24, 2005

Fourth Draft

0.5

March 5, 2005

fifth Draft

0.6

June 20, 2005

Mechanical Clause

0.61

June 27, 2005

Electrical and Mechanical Clauses

0.62

August 4, 2005

Electrical, mechanical Clauses, Layout

0.63

September 27, 2005

Electrical specification improvements

0.64

February 2, 2006

Electrical specification improvements, changed
cage specification, finished memory map

0.70

March 1, 2006

Reorganization of mechanical clauses to specify
module only. Completed Memory Map.

0.75

May 17, 2006

Changes made due to letter ballot review. Allchanges are documented in the comment database and major changes were regarding
LPMode_Reset pin, Packet Error Checking,removed Appendix A and filled in missing
details.

0.80

June 28, 2006

Mechanical changes made due to letter ballot
review. Changes due to review of Draft 0.75.

July 18, 2006

Mechanical changes made due to letter ballot
review of Revision 0.8. Management Section
reorganized in page, byte order and Rate Selectexplanation improved.

0.90

July 25, 2006

Minor changes made due to letter ballot review
of Revision 0.85. Rate Select explanation
improved and length of module outside of cage
extended by 5 mm.

0.95

August 1, 2006

Editorial changes to make this a public draft.

0.96

November 15, 2006

Changes due to public review. LPMode_Resetpin was converted to ResetL and LPMode pins.
Mechanical clarifications to connector, moduleand cage.

1.0

December 1, 2006

Minor editorial changes due to review of Draft
0.96.

0.85

QSFP Public Specification

3

Table of Contents

Page

1 Contact Information for Member Companies..............................................................................................................9
1.1 Acknowledgement of Contributors..................................................................................................................10
2 Scope..........................................................................................................................................................................11
3 Electrical Specification........... ...................................................................................................................................14
3.1 Electrical Connector......... ...............................................................................................................................143.1.1 Low Speed Electrical Hardware Pins.......... ..........................................................................................17
3.1.2 Low Speed Electrical Specification.......................................................................................................18
3.1.3 High Speed Electrical Specification.......... ............................................................................................19
3.2 Power Requirements......... ...............................................................................................................................193.2.1 Host Board Power Supply Filtering.......... ............................................................................................20
3.3 ESD..................................................................................................................................................................21
4 Mechanical and Board Definition..............................................................................................................................22
4.1 Introduction......................................................................................................................................................22
4.2 QSFP Datums and Component Alignment......................................................................................................23
4.3 QSFP Transceiver Mechanical Package Dimensions......................................................................................24
4.3.1 Mating of QSFP Transceiver PCB to QSFP Electrical Connector........................................................27
4.4 Host PCB Layout.............................................................................................................................................28
4.4.1 Insertion, Extraction and Retention Forces for QSFP Transceivers......................................................29
4.5 Color Coding and Labeling of QSFP Transceivers......... ................................................................................30
4.6 Bezel for Systems Using QSFP Transceivers..................................................................................................31
4.7 QSFP Electrical Connector Mechanical......... .................................................................................................32
4.8 Individual QSFP Cage Assembly......... ...........................................................................................................33
4.8.1 QSFP Heat Sink Clip Dimensions.........................................................................................................35
4.8.2 QSFP Heat Sink Dimensions.................................................................................................................36
4.8.3 Light Pipes.............................................................................................................................................37
4.9 Dust / EMI Cover............................................................................................................................................37
4.10 Optical Interface......... ...................................................................................................................................37
5 Environmental and Thermal........... ...........................................................................................................................39
5.1 Thermal Requirements.....................................................................................................................................39
6 Management Interface........... ....................................................................................................................................40
6.1 Introduction......................................................................................................................................................40
6.2 Timing Specification......... ..............................................................................................................................40
6.2.1 Introduction.......... .................................................................................................................................40
6.2.2 Management Interface Timing Specification.......... ..............................................................................40
6.2.3 Serial Interface Protocol.......... ..............................................................................................................40
6.3 Memory Interaction Specifications..................................................................................................................426.3.1 Timing for Soft Control and Status Functions.......... ............................................................................43
6.4 Device Addressing and Operation......... ..........................................................................................................44
6.5 Read/Write Functionality.................................................................................................................................45
6.5.1 QSFP Memory Address Counter (Read AND Write Operations).........................................................45
6.5.2 Read Operations (Current Address Read).......... ...................................................................................46
6.5.3 Read Operations (Random Read).......... ................................................................................................46
6.5.4 Write Operations (BYTE Write).......... .................................................................................................47

QSFP Public Specification

46.5.5 Write Operations (Sequential Write).....................................................................................................48
6.5.6 Write Operations (Acknowledge Polling).......... ...................................................................................48
6.6 QSFP Memory Map.........................................................................................................................................48
6.6.1 Lower Memory Map..............................................................................................................................50
6.6.2 Upper Memory Map Page 00h.......... ....................................................................................................59
6.6.3 Upper Memory Map Page 01h.......... ....................................................................................................68
6.6.4 User Writable and Vendor Specific Memory.......... ..............................................................................68
6.6.5 Upper Memory Page 03h.......................................................................................................................69

QSFP Public Specification5

List of Figures

Page

1. Application Reference Model ..................................................................................................................................13
2. QSFP Transceiver Pad Layout .................................................................................................................................14
3. Example QSFP Host Board Schematic ....................................................................................................................16
4. Recommended Host Board Power Supply Filtering ................................................................................................20
5. QSFP Module Rendering .........................................................................................................................................22
6. QSFP Datum Alignment, Depth ..............................................................................................................................24
7. Drawing of QSFP Transceiver (Part 1 of 2) ............................................................................................................25
8. Drawing of QSFP Transceiver (Part 2 of 2) ............................................................................................................26
9. Pattern Layout for QSFP Printed Circuit Board ......................................................................................................27
10. QSFP Host PCB Mechanical Layout .....................................................................................................................28
11.QSFP Host PCB Mechanical Layout, Detail Z .......................................................................................................29
12. Recommended Bezel Design .................................................................................................................................31
13. QSFP Transceiver Electrical Connector Illustration ..............................................................................................32
14. QSFP Electrical Connector Specification ..............................................................................................................32
15. Cage and Optional Heat Sink Design (exploded view) .........................................................................................33
16. 1-by-1 cage .............................................................................................................................................................34
17. QSFP Heat Sink Clip .............................................................................................................................................35
18. QSFP Heat Sink ....................................................................................................................................................36
19. Dust / EMI Cover ...................................................................................................................................................37
20. QSFP Optical Receptacle and Channel Orientation ..............................................................................................38
21. QSFP Timing Diagram ..........................................................................................................................................40
22. QSFP Device Address ............................................................................................................................................45
23. QSFP Current Address Read Operation ................................................................................................................46
24. QSFP Random Read ..............................................................................................................................................46
25. Sequential Address Read Starting at QSFP Current Address ................................................................................47
26. Sequential Address Read Starting with Random QSFP Read ...............................................................................47
27. QSFP Write Byte Operation ..................................................................................................................................47
28. QSFP Sequential Write Operation .........................................................................................................................48
29. QSFP Memory Map ...............................................................................................................................................49

QSFP Public Specification

6

List of Tables

Page

1.

Multimode Fiber Applications............................................................................................................................122.

Singlemode Fiber Applications ..........................................................................................................................123.

Pin Function Definition ......................................................................................................................................15

4.

Power Mode Truth Table ....................................................................................................................................19

5.

Low Speed Control and Sense Signals ...............................................................................................................19

6.

Power Supply Specification................................................................................................................................21

7.

Power Budget Classification...............................................................................................................................22

8.

Definition of Datums ..........................................................................................................................................24

9.

Insertion, Extraction and Retention Forces.........................................................................................................30

10.

Temperature Classification of Module Case ......................................................................................................39

11.

QSFP 2-Wire Timing Specifications ..................................................................................................................4112.

QSFP Memory Specification ..............................................................................................................................42

13.

Single Byte Writable Memory Block .................................................................................................................42

14.

Multiple Byte Writable Memory Block..............................................................................................................42

15.

I/O Timing for Soft Control and Status Functions .............................................................................................43

16.

I/O Timing for Squelch and Disable...................................................................................................................44

17.

Lower Memory Map Page A0h ..........................................................................................................................50

18.

Status Indicators..................................................................................................................................................50

19.

Channel Status Interrupt Flags............................................................................................................................51

20.

Module Monitor Interrupt Flags .........................................................................................................................51

21.

Channel Monitor Interrupt Flags ........................................................................................................................52

22.

Module Monitoring Values.................................................................................................................................53

23.

Channel Monitoring Values................................................................................................................................54

24.

Control Bytes ......................................................................................................................................................55

25.

IntL Masking Bits for Module and Channel Status Interrupts............................................................................56

26.

Functionality of RxN_Rate_Select with Extended Rate Selection.....................................................................57

27.

Definition of Application Select (Bytes 89 to 92) ..............................................................................................57

28.

Detailed Description of Control Mode (Bytes 89 to 92, bit 7 and 6)) ................................................................58

29.

Serial ID: Data Fields .........................................................................................................................................59

30.

Identifier Values .................................................................................................................................................60

31.

Extended Identifier Values .................................................................................................................................60

32.

Connector Values................................................................................................................................................61

33.

Transceiver Values .............................................................................................................................................62

34.

Encoding Values .................................................................................................................................................63

35.

Extended RateSelect Compliance Tag Assignment............................................................................................63

36.

Description of Device Technology .....................................................................................................................64

37.

Transmitter Technology......................................................................................................................................64

38.

Extended Transceiver Code Values ....................................................................................................................65

39.

Option Values .....................................................................................................................................................66

40.

Date Codes ..........................................................................................................................................................67

41.

Diagnostic Monitoring Type...............................................................................................................................67

QSFP Public Specification

7

42.

Enhanced Options (byte 221)) ............................................................................................................................67

43.

Application Select Table (Page 01) ....................................................................................................................68

44.

Application Code Structure ................................................................................................................................68

45.

Upper Memory Map Page 03h............................................................................................................................69

46.

Module and Channel Thresholds ........................................................................................................................69

47.

Optional Channel Controls .................................................................................................................................70

48.

Channel Monitor Masks......................................................................................................................................71

QSFP Public Specification

8

1 Contact Information for Member Companies
Company
Avago Technologies
350 West Trimble Road MS
90TH
San Jose, CA 95131
Beam Express
910 E California Street
Sunnyvale, CA 94085
Emcore Fiber Optics
5314 Connemara Drive NE
Rochester, MN 55906
Emulex Corp.
Fiberxon
FinisarForce10 Networks, Inc.
1440 McCarthy Blvd
San Jose, CA 95035
Helix AG
Seefeldstrasse 45
Zurich, Switzerland CH-8008
JDS Uniphase Corp

Representative
Jugnu Ojha

Contact Information
Jugnu.ojha@avagotech.com
Tel: 408-435-4270

Kenneth P.
JacksonKenneth_Jackson@emcore.com
Tel: 505-349-0922

Hossein
Hashemihossein.hashemi@emulex.com

Helena Feng
Stephen Nelson
Michael Laudon

helena.feng@fiberxon.com
stephen.nelson@finisar.com
michael@force10networks.com

Alex Ngi

an@helix.ch
Tel: 41-44-260-24-34
Fax: 41-44-260-24-33
david.lewis@jdsu.com
Tel: 408-546-5448
scott.kipp@mcdata.com
Tel: 720-558-3452
Fax 720-558-8999
jens.fiedler@mergeoptics.com

David Lewis

McDATA Corporation
4 McDATA Parkway
Broomfield, CO 80021
Merge Optics

Scott Kipp

Molex Incorporated
2222 Wellington Court
Lisle, IL 60532
Opnext Inc.
940 Auburn Ct.
Fremont, CA 94538
Optical Communication
Products, Inc.

Jay Neer

Picolight Inc.
1480 Arthur Avenue
Louisville, CO 80027
Qlogic Inc.
6321 Bury Drive
Eden Prairie, MN 55346
Reflex Photonics
550 Sherbrooke West
Suite 680, West Tower
Montreal, Quebec
Canada H3A 1B9Mike Dudek

Mike.dudek@picolight.com
Tel: 303-530-3189 x7533

Mark Owen

mark.owen@qlogic.com
Tel: 952-908-2326

Tomas Maj

tmaj@reflexphotonics.com
Tel: 514-842-5179
Fax: 514-842-8142

QSFP Public Specification

Jens Fiedler

Josef C. Berger

Kirk Bovill

jneer@molex.com
Tel: 561-447-2907x3889
Fax 561-447-2908
jberger@opnext.com
Tel: 310-301-6710
Fax 310-305-1609
KBovill@ocp-inc.com
Tel: 818 251-7183

9

Company
The Siemon Company
101 Siemon Co. Drive
Watertown, CT 06795
Tyco Electronics
3101 Fulling Mill Road M/S:
128-083
Middletown, PA 17057
Xloom Communications Inc.
11 Derech Hashalom
Tel Aviv, Israel 67892
Zarlink Semiconductor AB
Bruttovägen 1, Box 520SE175 26, Järfälla, Sweden

Representative Contact Information
Olindo Savi
Olindo_savi@siemon.com
Tel: 860-945-4246
Fax: 860-945-5871
Ed Bright
ejbright@tycoelectronics.com
Tel: 717-592-6041
Fax: 717-986-3410
DubravkoBabicdbabic@etanvie.com

Marco Ghisoni

Marco.ghisoni@zarlink.com
Tel : 46 (0)8 580 24 500
Fax: 46 (0)8 580 20 110

1.1 Acknowledgement of Contributors
The MSA would like to acknowledge the hard work of the major contributors to this standard. The cage andtransceiver design was spearheaded by Ed Bright who has contributed successfully to many transceiver
designs. Jay Neer and KC Simonson contributed the connector design and confirmed many of the cage andtransceiver designs. Phil McClay designed the Memory Map and Kannan Raj proposed the Serial ID clausesof the draft. Mike Dudek was very active in reviewing all aspects of the design and John Petrilla contributed tomany areas as well - particularly doing thorough reviews of the later drafts. Jerry Malagrino oversaw thethermal simulations of the modules and cages. Many others contributed to the specification as well.
Jens Fiedler edited and chaired the QSFP for the first seven drafts of the MSA and has been the webmasterfor www.qsfpmsa.org. Alex Ngi contributed as the secretary and wrote the Rate Select sections andcontributed regularly to the memory map.

QSFP Public Specification

10

2 Scope
The scope of this Specification covers the following items:a) electrical interfaces (including pinout for data, control, status, configuration and test signals) and theelectrical connector and recommended host PCB layout requirementsb) management interfaces encompassing features from the current SFP MSA and includes specificmulti-data rate and multi-protocol implementationsc) optical interfaces (including the optical connector receptacle and mating fiber optic connector plugand recommended breakout cable assembly.) The optical specifications are left to the applicablestandards for each protocol.
d) mechanical including package outline with latching detail and optical connector receptacle detail,electrical connector mechanical details for both the transceiver and host PCB halves, front panel
cut-out recommended dimensions and a mis-plugging solution to prevent damage from related XFP
modules and cagese) thermal requirements (case temperatures)f) electromagnetic interference (EMI) requirements (including necessary shielding features to seal the
OEM chassis front panel cutout with and without the QSFP module installed in the cage.)g) electrostatic discharge (ESD) requirements solely to the extent disclosed with particularity in theSpecifications where the sole purpose of such disclosure is to enable products to operate, connect orcommunicate as defined within the Specifications.
The overall package dimensions shall conform to the indicated dimensions and tolerances, and the mounting
features shall be located such that the products are mechanically interchangeable with the rail and connector
system. In addition, the overall dimensions and mounting requirements for the rail and connector system on acircuit board shall be configured such that the products are mechanically and electrically interchangeable, andthe overall dimensions and insertion requirements for the optical connector and corresponding fiber optic
cable plug shall be such that the products are mechanically and optically interchangeable.
The electrical and optical specifications shall be compatible with those enumerated in the ITU-T
Recommendation G.957 (STM-1, STM-4 and STM-16), Telcordia Technologies GR-253-CORE (OC-3, OC-12
and OC-48), Ethernet- IEEE 802.3-2005 (Fast Ethernet and Gigabit Ethernet), InfiniBand Architecture
Specifications (SDR and DDR) or Fibre Channel-PI-2 (1GFC, 2GFC and 4GFC). Electrical and opticalspecifications may be compatible with standards under development such as Fibre Channel-PI-3 and Fibre
Channel-PI-4.
The specific implementation and internal design of the module is entirely at the discretion of each Participant
and is not covered by the Specifications. The Participants recognize that their products may not be identical,
but need only meet the criteria shown in the Specifications to assure interoperation and interchangeability.
Each Participant acknowledges the Specifications will provide a common solution for combined four-channel
fiber optic ports that support SONET/SDH and/or Ethernet and/or Fibre Channel specifications. This MSA
encompasses transceiver design(s) capable of supporting multimode and single mode applications for
operation covering the transmission rates and distances noted below. Other standards covering higher data
rates and/or longer distance options are not part of this agreement but may be supported. A QSFP module
may support applications in Table 1 and Table 2 that are supplied for reference only.

QSFP Public Specification

11

Table 1 — Multimode Fiber Applications

Fiber TypeCore Diameter/
Distance MHZ*km
2km
MM 62.5/200
300m
MM 62.5/200275m
MM 62.5/200
220m
MM 62.5/160
150m
MM 62.5/200
75m
MM 62.5/20070m
MM 62.5/200
50m
MM 62.5/200
550m
MM 50/500
500m
MM 50/400
500m
MM 50/500
300m
MM 50/500
150m
MM 50/500
125m
MM 50/500
75m
MM 50/500
860m
MM 50/2000
500m
MM 50/2000
270m
MM 50/2000
200m
MM 50/2000
150m
MM 50/2000

IEEE 802.3
Fast
Gigabit
Ethernet
Ethernetx

Fibre Channel-FC-PI-2

InfiniBand

1GFC

SDR

2GFC

4GFC

DDR

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Table 2 — Singlemode Fiber Applications

Distance
2km
10km
15km
40km

Fiber
Type
SM
SM
SM
SM

Fibre Channel IEEE 802.3
FC-PI-2
ITU-T G.957
InfiniBand
Fast
Gigabit
Ethernet Ethernet 1GFC 2GFC 4GFC STM1 STM4 STM16 SDR 4x-LX DDR
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

QSFP Public Specification

12

An Application Reference Model, see Figure 1, shows the high-speed data interface between an ASIC
(SerDes) and the QSFP module. Only one data channel of the interface is shown for simplicity.
Figure 1 — Application Reference Model
Host Board(Only one channel shown for simplicity)

ASIC (SerDes)

A

B'

B

Rx 1
Rx 2
Rx Out p
Rx

Rx Out n

QSFP Module
Tx In pTx In nTx

Optical Connector/Port(Optical Interface)C'

Module Card Edge (HostInterface)D

Host Edge Card Connector

C

Rx 3
Rx 4

Tx 4
Tx 3
Tx 2
Tx 1

QSFP compliance and reference points are as follows:
A: Host ASIC transmitter output at ASIC package pin on a DUT board – Reference point
B: Host ASIC transmitter output across the Host Board and Host Edge Card connector at the Module
Card Edge interface - Reference point
B’: Host ASIC transmitter output across the Host Board at Host Edge Card Connector - Compliance
point
C: QSFP receiver output at the Module Card Edge Interface - Reference point
C’: QSFP receiver output at Host Edge Card Connector - Compliance point
D: QSFP receiver output at Host ASIC package receiver input pin on a DUT board– Reference point

QSFP Public Specification13

3 Electrical Specification
This clause contains pin definition data for the QSFP transceiver. The pin definition data is generic for gigabit-per-second datacom applications such as Fibre Channel and Gigabit Ethernet and SONET/ATM applications.
Compliance Points for high-speed signal electrical measurements are defined in Figure 1. Compliance Points
for all other electrical signals are at comparable points at the host edge card connector.

3.1 Electrical Connector
Figure 2 shows the signal symbols and contact numbering for the QSFP module edge connector. The diagramshows the module PCB edge as a top and bottom view. There are 38 pins intended for high speed, low speed
signals, power and ground connections. Table 3 provides more information about each of the 38 pins.
For EMI protection the signals to the connector should be shut off when the QSFP transceiver is removed.
Standard board layout practices such as connections to Vcc and GND with Vias, use of short and equal-length
differential signal lines, use of microstrip-lines and 50 Ohm terminations are recommended. The chassis
ground (case common) of the QSFP module is isolated from the module’s circuit ground, GND, to provide theequipment designer flexibility regarding connections between external electromagnetic interference shields
and circuit ground, GND, of the module.
Figure 2 — QSFP Transceiver Pad Layout
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

GND
TX1n
TX1p
GND
TX3n
TX3p
GND
LPMode
Vcc1
VccTx
IntL
ModPrsL
GND
RX4p
RX4n
GND
RX2p
RX2n
GND

Top Side
Viewed from Top

QSFP Public Specification

Card Edge

1
2
3
4
5
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7
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31
32
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34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

GND
TX2n
TX2p
GND
TX4n
TX4p
GND
ModSelL
ResetL
VccRx
SCL
SDA
GND
RX3p
RX3n
GND
RX1p
RX1n
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Bottom Side
Viewed from Bottom

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Table 3 — Pin Function Definition

Pin Logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
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29
30
31
32
33
34
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36
37
38

Symbol

GND
CML-I
Tx2n
CML-I
Tx2p
GND
CML-I
Tx4n
CML-I
Tx4p
GND
LVTTL-I
ModSelL
LVTTL-I
ResetLVcc RxLVCMOS-I/O SCLLVCMOS-I/O SDA
GND
CML-O
Rx3p
CML-O
Rx3n
GND
CML-O
Rx1p
CML-O
Rx1n
GND
GND
CML-O
Rx2n
CML-O
Rx2p
GND
CML-O
Rx4n
CML-O
Rx4p
GND
LVTTL-O
ModPrsL
LVTTL-O
IntL
Vcc Tx
Vcc1
LVTTL-I
LPMode
GND
CML-I
Tx3p
CML-I
Tx3n
GND
CML-I
Tx1p
CML-I
Tx1n
GND

Description
GroundTransmitter Inverted Data Input
Transmitter Non-Inverted Data Input
GroundTransmitter Inverted Data Input
Transmitter Non-Inverted Data Input
GroundModule Select
Module Reset+3.3 V Power supply receiver
2-wire serial interface clock
2-wire serial interface data
GroundReceiver Non-Inverted Data Output
Receiver Inverted Data Output
GroundReceiver Non-Inverted Data Output
Receiver Inverted Data Output
GroundGroundReceiver Inverted Data Output
Receiver Non-Inverted Data Output
GroundReceiver Inverted Data Output
Receiver Non-Inverted Data Output
GroundModule Present
Interrupt+3.3 V Power supply transmitter+3.3 V Power Supply
Low Power Mode
GroundTransmitter Non-Inverted Data Input
Transmitter Inverted Data Input
GroundTransmitter Non-Inverted Data Input
Transmitter Inverted Data Input
GroundPlug
Sequence
1
3
3
1
3
3
1
3
3
2
3
3
1
3
3
1
3
3
1
1
3
3
1
3
3
1
3
3
2
2
3
1
3
3
1
3
3
1

Notes
1

1

1

2

1

1

1
1

1

1

2
2
1

1

1

Note 1: GND is the symbol for signal and supply (power) common for the QSFP module. All arecommon within the QSFP module and all module voltages are referenced to this potential unlessotherwise noted. Connect these directly to the host board signal-common ground plane.
Note 2: Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and shall beapplied concurrently. Requirements, defined for the host side of the Host Edge Card Connector,
are listed in Table 6. Recommended host board power supply filtering is shown in Figure 4. Vcc Rx,
Vcc1and Vcc Tx may be internally connected within the QSFP transceiver module in any
combination. The connector pins are each rated for a maximum current of 500 mA.

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Figure 3 shows an example of a complete QSFP host PCB schematic with connections to SerDes and control
ICs.
Figure 3 — Example QSFP Host Board Schematic
To other QSFP modules

Vcc_host=3.3 V

4.7k to 10k ohm
4.7k to 10k ohm

4.7k to 10k ohm

MicroController

ModPrsL
SCL
SDA

4.7k to 10k ohm

PLD/PALModSelL
ResetLIntL
LPModeRx Los <1:4>

22 uF

Rx Rate <1:4>

Tx Fault <1:4>

Vcc RxTx Disable <1:4>

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2
3
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0.1 uF

GND.01uF

Tx Data Bus
100 ohm

ProtocolIC

100 ohm

Rx Data Bus
100 ohm

100 ohm

Vcc_host=3.3 V

0.1 uF

1uH

22 uF

1uH

Rx1p

.01uF

Rx1n

.01uF

Rx2p

.01uF

Rx2n

.01uF

Rx3p

.01uF

Rx3n

.01uF

Rx4p

.01uF

Quad
TIA
&
Limiting
Amplifier

Rx4n

Quad
SERDES
IC

.01uF

1uH

Tx4p

.01uF

Tx4n

.01uF

Tx3p

.01uF

Tx3n

.01uF

Tx2p

.01uF

Tx2n

.01uF

Tx1p

.01uF

100 ohm

100 ohm

100 ohm

100 ohm

Tx1n
Vcc TxNote: Decoupling capacitor
values are informative andvary depending on applications

22 uF

0.1 uF

Quad
Laser
Driver

GND

Note: VCC1 connection may
be connected to VccTx or
VccRx provided the applicable
derating of the maximum
current limit is used.

Vcc1
22 uF

0.1 uFGND

QSFP Module
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3.1.1 Low Speed Electrical Hardware Pins
In addition to the 2-wire serial interface the module has the following low speed pins for control and status:
a)
b)
c)
d)
e)

ModSelL
LPModeResetL
ModPrsL
IntL

3.1.1.1 ModSelL
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communicationcommands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. Whenthe ModSelL is “High”, the module shall not respond to or acknowledge any 2-wire interface communicationfrom the host. ModSelL signal input node must be biased to the “High” state in the module.
In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the
ModSelL de-assert time after any QSFP modules are deselected. Similarly, the host must wait at least for theperiod of the ModSelL assert time before communicating with the newly selected module. The assertion andde-asserting periods of different modules may overlap as long as the above timing requirements are met.
3.1.1.2 ResetL
The ResetL pin must be pulled to Vcc in the QSFP module. A low level on the ResetL pin for longer than theminimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings totheir default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL
pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module
inidicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the
Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module should post thiscompletion of reset interrupt without requiring a reset.
3.1.1.3 LPModeThe LPMode pin shall be pulled up to Vcc in the QSFP module. This function is affected by the LPMode pin
and the combination of the Power_over-ride and Power_set software control bits (Address A0h, byte 93 bits
0,1).
The module has two modes a low power mode and a high power mode. The high power mode operates in oneof the four power classes.
When the module is in a low power mode it has a maximum power consumption of 1.5W. This protects hoststhat are not capable of cooling higher power modules, should such modules be accidentally inserted.
The modules 2-wire serial interface and all laser safety functions must be fully operational in this low power
mode. The module shall still support the completion of reset interrupt in this low power mode.
If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate a power consumption greater than 1.5W
and the module is in low power mode it must reduce its power consumption to less than 1.5W while still
maintaining the functionality above. The exact method of accomplishing low power is not specified, however it
is likely that either the Tx or Rx or both will not be operational in this state.
If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate that its power consumption is less than
1.5W then the module shall be fully functional independent of whether it is in low power or high power mode.
The Module should be in low power mode if the LPMode pin is in the high state, or if the Power_ over-ride bit
is in the high state and the Power_set bit is also high. The module should be in high power mode if the
LPMode pin is in the low state, or the Power_over-ride bit is high and the Power_set bit is low. Note that thedefault state for the Power_over-ride bit is low.

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A truth table for the relevant configurations of the LPMode and the Power_over-ride and Power_set are shownin Table 4.
Table 4 — Power Mode Truth Table
LPMode1
0
X
X

Power_Over-ride Bit
0011Power_set Bit
X
X
1
0

Module Power Allowed
Low Power
High Power
Low Power
High PowerAt Power up, the Power_over-ride and Power_set bits shall be set to 0.
3.1.1.4 ModPrsL
ModPrsL is pulled up to Vcc_Host on the host board and grounded in the module. The ModPrsL is asserted“Low” when inserted and deasserted “High” when the module is physically absent from the host connector.
3.1.1.5 IntL
IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to the hostsystem. The host identifies the source of the interrupt using the 2-wire serial interface.The IntL pin is an open
collector output and must be pulled to host supply voltage on the host board.
3.1.2 Low Speed Electrical Specification
Low speed signaling other than SCL and SDA is based on Low Voltage TTL (LVTTL) operating at Vcc. Vcc
refers to the generic supply voltages of VccTx, VccRx, Vcc_host or Vcc1. Hosts shall use a pull-up resistor
connected to Vcc_host on each of the 2-wire interface SCL (clock), SDA (data), and all low speed status
outputs.The SCL and SDA is a hot plug interface that may support a bus topology. During module insertion or
removal, the module may implement a pre-charge circuit which prevents corrupting data transfers from othermodules that are already using the bus.
NOTE 1 - Timing diagrams for SCL and SDA are included in Clause 6.2.2.

The QSFP low speed electrical specifications are given in Table 5. This specification ensures compatibility
between host bus masters and the 2-wire interface.
Table 5 — Low Speed Control and Sense Signals
Parameter
SCL and SDA
SCL and SDA
Capacitance for SCL
and SDA I/O pin

Symbol
VOL
VOH
VIL
VIH

Min
0
Vcc - 0.5
-0.3
Vcc*0.7

Max
0.4
Vcc + 0.3
Vcc*0.3
Vcc + 0.5

Unit
V
V
V
V

Ci

14

pF

Cb

100

pF

200

pF

Total bus capacitive
load for SCL and SDA
LPMode, Reset and
ModeSelL

ModPrsL and IntLQSFP Public Specification

VIL
VIH

-0.3
2

0.8
VCC + 0.3

V
V

VOL

0

0.4

V

VOH

VCC - 0.5 VCC + 0.3

Condition
IOL(max) = 3.0 mA

3.0 k Ohms Pullup
resistor, max
1.6 k Ohms Pullup
resistor, max| Iin | </= 125 uA for
0V < Vin < Vcc
Iol = 2.0 mA

V

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3.1.3 High Speed Electrical Specification
3.1.3.1 Rx(n)(p/n)Rx(n)(p/n) are QSFP module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 Ohm differential lines thatshould be terminated with 100 Ohm differentially at the Host ASIC(SerDes). The AC coupling is inside the
QSFP module and not required on the Host board. When properly terminated, the single-ended voltage swing
will be between 170 mV to 800 mV and the differential voltage swing (absolute value) will be between 340
mVpp to 1600 mVpp.
Output squelch for loss of optical input signal, hereafter Rx Squelch, is required and shall function as follows.
In the event of the optical signal on any channel becoming equal to or less than the level required to assert
LOS, then the receiver data output for that channel shall be squelched or disabled. In the squelched or
disabled state output impedance levels are maintained while the differential voltage swing shall be less than
50 mVpp.
In normal operation the default case has Rx Squelch active. Rx Squelch can be deactivated using Rx
Squelch Disable through the 2-wire serial interface. Rx Squelch Disable is an optional function. For specificdetails refer to Clause 6.6.5.2.
3.1.3.2 Tx(n)(p/n)Tx(n)(p/n) are QSFP module transmitter data inputs. They are AC-coupled 100 Ohm differential lines with 100
Ohm differential terminations inside the QSFP module. The AC coupling is inside the QSFP module and not
required on the Host board. The inputs will accept single-ended voltage swings between 250 mV to 800 mVand differential voltage swings between 500 mVpp to 1600 mVpp (absolute value). For best EMI results,
single-ended swings between 250 mV and 600 mV and differential voltage swings between 500 mVpp to 1200
mVpp (absolute value) are recommended.
Output squelch, hereafter Tx Squelch, for loss of input signal, hereafter Tx LOS, is an optional function.
Where implemented it shall function as follows. In the event of the differential, peak-to-peak electrical signal
on any channel becomes equal to or less than 50 mVpp, then the transmitter optical output for that channel
shall be squelched or disabled and the associated TxLOS flag set.
Where squelched, the transmitter OMA shall be less than or equal to -26 dBm and when disabled thetransmitter power shall be less than or equal to -30 dBm. For applications, e.g. Ethernet, where the transmitter
off condition is defined in terms of average power, disabling the transmitter is recommended and for
applications, e.g. InfiniBand, where the transmitter off condition is defined in terms of OMA, squelching thetransmitter is recommended.
In module operation, where Tx Squelch is implemented, the default case has Tx Squelch active. Tx Squelch
can be deactivated using Tx Squelch Disable through the 2-wire serial interface. Tx Squelch Disable is an
optional function. For specific details refer to Clause 6.6.5.2.

3.2 Power Requirements
The power supply has three designated pins, Vcc Tx, Vcc1, and Vcc Rx, in the connector. Vcc1 is used tosupplement Vcc Tx or Vcc Rx at the discretion of the module vendor. Power is applied concurrently to thesepins.
Since different classes of modules exist with pre-defined maximum power consumption limits, it is necessary
to avoid exceeding the system power supply limits and cooling capacity when a module is inserted into asystem designed to only accommodate lower power modules. It is recommended that the host, through the
management interface, identify the power consumption class of the module before allowing the module to go
into high power mode.
A host board together with the QSFP module(s) forms an integrated power system. The host supplies stable
power to the module. The module limits electrical noise coupled back into the host system and limits inrush
charge/current during hot plug insertion.

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All specifications shall be met at the maximum power supply current. No power sequencing of the power
supply is required of the host system since the module sequences the contacts in the order of ground, supply
and signals during insertion.
3.2.1 Host Board Power Supply Filtering
The host board should use the power supply filtering shown in Figure 4.
Figure 4 — Recommended Host Board Power Supply Filtering

1uH
Vcc Tx
0.1 uF

22 uF

GND

Vcc_host =3.3 Volt

1uH
Vcc Rx
0.1 uF22 uF

0.1 uF

22 uF

GND

1uH
Vcc1
0.1 uF

22 uF

GND

QSFP Module

Any voltage drop across a filter network on the host is counted against the host DC set point accuracy
specification. Inductors with DC Resistance of less than 0.1 Ohm should be used in order to maintain therequired voltage at the Host Edge Card Connector.
The specification for the power supply is shown in Table 6.
Table 6 — Power Supply Specification
ParameterMin

Vcc
Vcc set point accuracy
Power Supply Noise
including ripple
Module Maximum Current
Inrush with LPMode Pinasserted
Module Maximum Current
Inrush with LPMode Pindeasserted
Module Current Ramp RateQSFP Public Specification

Nominal

Max

3.3
-5

Unit
V

5

%

50

mV

0.55

A

1.3

A

100

mA/uS

Condition
Measured at Vcc Tx, Vcc Rx and
Vcc1.
Measured at Vcc Tx, Vcc Rx and
Vcc1.
1 kHz to frequency of operation
measured at Vcc_host.

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Power levels associated with classifications of modules is shown in Table 7.
Table 7 — Power Budget Classification
Power Level
1
2
3
4

Max Power (W)
1.5
2
2.5
3.5

In general, the higher power classification level is associated with higher data rates and longer reach. The
system designer is responsible for ensuring that the maximum temperature does not exceed the casetemperature requirements.

3.3 ESD
The module and all pins shall withstand 500V electrostatic discharge based on Human Body Model per
JEDEC JESD22-A114-B.
The module shall meet ESD requirements given in EN61000-4-2, criterion B test specification such that when
installed in a properly grounded cage and chassis the units are subjected to 15KV air discharges during
operation and 8KV direct contact discharges to the case.

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4 Mechanical and Board Definition
4.1 Introduction
The overall transceiver module defined in this clause is illustrated in Figure 5. The module and connector
dimensions described in this clause are constant for all applications. The bezel, cage assembly, heat sink, andclip can be designed and/or adjusted for the individual application.
Figure 5 — QSFP Module Rendering

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4.2 QSFP Datums and Component Alignment
A listing of the datums for the various components is contained in Table 8. The alignments of some of thedatums are noted. The relationship of the Transceiver, Cage, and Connector relative to the Host Board andBezel is illustrated in Figure 6 by the location of the key datums of each of the components. In order to reducethe complexity of the drawings, all dimensions are considered centered unless otherwise specified.
Table 8 — Definition of Datums
Datum
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
V
W
X&Y
Z
AA
BB
CC

Description
Host Board top surface
Centerline of bezel**Distance between Connector terminal thru holes on host board*Hard stop on transceiver**Width of transceiver
Height of transceiver housing**Width of transceiver pc board
Leading edge of signal contact pads on transceiver pc board
Top surface of transceiver pc board*Host Board thru hole #1 to accept connector guide post
*Host Board thru hole #2 to accept connector guide post**Width of bezel cut out
Connector alignment pin**Width of inside of cage at EMI gasket (when fully compressed)
Height of inside of cage at EMI Gasket (when fully compressed)
Seating Plane of cage on host board*Hard stop on cage
Length of heat sink clip
Seating Surface of the heat sink on the cage
Host board horizontal and depth datums established by customers’
fiducials**Width of heat sink surface that fits into clip**Connector slot width
Seating plane of cage on host board
Length of boss on heat sink that fits inside of the cage

*Datums D, K, L, N, and T are aligned when assembled (see Figure 6)**Centerlines of datums AA C, E, G, M, P and Z are aligned on the same vertical axis

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Figure 6 — QSFP Datum Alignment, Depth

4.3 QSFP Transceiver Mechanical Package Dimensions
A common mechanical outline is used for all QSFP transceivers. The preferred method of removing thetransceiver from the cage assembly is by a bail type actuation method. The module shall provide a means to
self-lock with the cage upon insertion. The package dimensions for the QSFP transceiver are defined in
Figure 7 and Figure 8. The dimensions that control the size of the transceiver that extends outside of the cageare listed as maximum dimensions per Note 1 and Note 6 in Figure 7.

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Figure 7 — Drawing of QSFP Transceiver (Part 1 of 2)

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Figure 8 — Drawing of QSFP Transceiver (Part 2 of 2)

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4.3.1 Mating of QSFP Transceiver PCB to QSFP Electrical Connector
The QSFP transceiver contains a printed circuit board that mates with the QSFP electrical connector. The
pads are designed for a sequenced mating:First mate – ground contacts
Second mate – power contacts
Third mate – signal contacts
The pattern layout for the QSFP Printed Circuit Board is shown in Figure 9.
Figure 9 — Pattern Layout for QSFP Printed Circuit BoardQSFP Public Specification

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4.4 Host PCB Layout
A typical host board mechanical layout for attaching the QSFP Connector and Cage System is shown in
Figure 10 and Figure 11. Location of the pattern on the host board is application specific. See Clause 4.6 fordetails on the location of the pattern relative to the bezel.
Figure 10 — QSFP Host PCB Mechanical Layout

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Figure 11 — QSFP Host PCB Mechanical Layout, Detail Z

4.4.1 Insertion, Extraction and Retention Forces for QSFP Transceivers
The requirement for insertion forces, extraction forces and retention forces are specified in Table 9. The QSFP
cage and module design combinations must ensure excessive force applied to a cable does not damage the
QSFP cage or host connector. If any part is damaged by excessive force, it should be the cable or media
module and not the cage or host connector which is part of the host system.
Table 9 — Insertion, Extraction and Retention Forces
Measurement
QSFP transceiver insertionQSFP transceiver extraction
QSFP transceiver retention
Cage retention (Latch strength)
Cage retention in Host Board

Min
0
0
90
180
114

Max
40
30
N/A
N/A
N/A

Units
N
N
N
N
N

Insertion / removal cycles,
100
connector/cage
Insertion / removal cycles, QSFP 50
Transceiver

N/A

Cyc.

N/A

Cyc.

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Comments

No damage to transceiver below 90N
No damage to latch below 180N
Force to be applied in a vertical direction,
no damage to cage
Number of cycles for the connector andcage with multiple transceivers.
Number of cycles for an individualtransceiver.

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4.5 Color Coding and Labeling of QSFP Transceivers
An exposed feature of the QSFP transceiver (a feature or surface extending outside of the bezel) shall becolor coded as follows:
Beige for 850nm
Blue for 1310nm
White for 1550nm
Each QSFP transceiver shall be clearly labeled. The complete labeling need not be visible when the QSFPtransceiver is installed and the bottom of the device is the recommended location for the label. Labeling shall
include:Appropriate manufacturing and part number identification
Appropriate regulatory compliance labeling
A manufacturing trace ability code
Also the label should include clear specification of the external port characteristics such as:
Optical wavelength
Required fiber characteristics
Operating data rate
Interface standards supported
Link length supported
The labeling shall not interfere with the mechanical, thermal or EMI features.

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4.6 Bezel for Systems Using QSFP Transceivers
Host enclosures that use QSFP devices should provide appropriate clearances between the QSFPtransceivers to allow insertion and extraction without the use of special tools and a bezel enclosure with
sufficient mechanical strength. See Figure 12 for the recommended bezel designs. The minimum
recommended host board thickness for belly-to-belly mounting of the assemblies is 2.2mm minimum.
Applications with host boards less than 2.2 mm minumum will require module dimensions of less than 1.6 mm
shown with Note 1 of Figure 7.
The front surface of the cage assembly passes through the bezel. If EMI spring fingers are used, they makecontact to the inside of the bezel cutouts. If an EMI gasket is used, it makes contact to the inside surface of thebezel. To accept all cage designs, both bezel surfaces must be conductive and connected to chassis ground.
The recommended basic dimension from the bezel centerline to Datum K and Datum L (See Figure 6 andFigure 12) on the Host board is 43.8mm nominal. The total tolerance can be calculated as follows:+/- tolerance = 1/2 (bezel thickness) + 0.3mm
For example, a bezel thickness of 1.6mm will have a bezel centerline tolerance of +/- 1.1mm.
The dimension of 43.8 +/- 1.1mm would apply from the Centerline of the bezel to Datums K and L.
The QSFP transceiver insertion slot should be clear of nearby moldings and covers that might block
convenient access to the latching mechanisms, the QSFP transceiver, or the cables connected to the
QSFP transceiver.
Figure 12 — Recommended Bezel Design

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4.7 QSFP Electrical Connector Mechanical
The QSFP Connector is a 38-contact, right angle surface mount connector and is shown in Figure 13. The
mechanical specification for the connector is shown in Figure 14.
Figure 13 — QSFP Transceiver Electrical Connector Illustration

Figure 14 — QSFP Electrical Connector Specification

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4.8 Individual QSFP Cage Assembly
An exploded view of a complete 1-by-1 assembly is shown schematically in Figure 15.
Figure 15 — Cage and Optional Heat Sink Design (exploded view)

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The detailed drawing for the cage assembly is shown in Figure 16.
Figure 16 — 1-by-1 cageQSFP Public Specification

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4.8.1 QSFP Heat Sink Clip Dimensions
The heat sink clip defined in Figure 17 is for reference only. The design of the heat sink clip, heat sink andfeatures on the cage assembly are vendor specific and not defined in this document. When fastened to thecage, the clip will provide a minimum force of 5 Newtons at the interface of the heat sink and QSFPtransceiver. The clip is designed to permit a heat sink to be fastened into the clip then assembled to the cage
and to expand slightly during transceiver insertion in order to maintain a contact force between the transceiverand heat sink.
Figure 17 — QSFP Heat Sink ClipQSFP Public Specification

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4.8.2 QSFP Heat Sink Dimensions
The heat sink illustrated in Figure 18 is for reference only. Critical dimensions to ensure that the heat sink will
be compatible with the Heat Sink Clip are defined. The configuration of the fins or posts is application specificalong with the outside envelope. The heat sink includes a beveled edge which “rides up” the leading edge ofthe transceiver as the transceiver is inserted into the cage assembly. The recommended material for the heatsink is aluminum and the surface treatment for the transceiver contacting surface can be anodizing or nickel
plating.
Figure 18 — QSFP Heat Sink

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4.8.3 Light Pipes
The use of light pipes to indicate status of the transceiver is application specific.

4.9 Dust / EMI CoverIn order to prevent contamination of the internal components and to optimize EMI performance, it isrecommended that a Dust/EMI Cover be inserted into the cage assembly when no transceiver is present. See
Figure 19 for the recommended design. During installation, the front flange on the cover shall be seatedagainst the front surface of the bezel to prevent dust from entering the equipment. The conductivity of thematerials should be chosen for the Dust/EMI Cover to block EMI emissions.
Figure 19 — Dust / EMI Cover

4.10 Optical Interface
The QSFP optical interface port shall receive a female MPO receptacle as specified in IEC 61754-7. Aligned
key (Type B) MPO patchcords should be used to ensure alignment of the signals between the modules.
TIA-568 has standardized an aligned key patchcord. The transmit / receive convention is detailed in Figure 20.
If the optical connector is orientated such that the keying feature of the MPO receptacle is on the top, thenfibers are numbered left to right as 12 through 1 looking into the receptacle.
The four fiber positions on the left (fibers 12, 11, 10, 9) are used for the optical transmit signals (Channel 1
through 4). The fiber positions on the right (fibers 4, 3, 2, 1) are used for the optical receive signals (Channel 4
through 1).
The central four fibers (5, 6, 7, 8) may be physically present.

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Figure 20 — QSFP Optical Receptacle and Channel Orientation

Fiber Number: 12 11 10 9 ...... 4 3 2 1Transmit Channels: 1 2 3 4Receive Channels:

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5 Environmental and Thermal
5.1 Thermal Requirements
The QSFP module shall operate within one or more of the case temperatures ranges defined in Table 10. The
temperature ranges are applicable between 60m below sea level and 1800m above sea level, (Ref. NEBS
GR-63) utilizing the host systems designed airflow.
Table 10 — Temperature Classification of Module Case
Class

Case Temperature Range

Standard

0 through 70C

Extended-5 through 85C

Industrial-40 through 85C

QSFP is designed to allow for up to 16 adjacent transceivers, ganged and/or belly-to-belly, with theappropriate thermal design for cooling / airflow. (Ref. NEBS GR-63)

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6 Management Interface
6.1 Introduction
A management interface, as already commonly used in other form factors like GBIC, SFP, and XFP, isspecified in order to enable flexible use of the transceiver by the user. The specification has been changed inorder to adopt the use of a multi-channel transceiver. Some timing requirements are critical especially for a
multi-channel device, so the interface speed has been increased.

6.2 Timing Specification
6.2.1 Introduction
Low speed signaling is based on Low Voltage CMOS (LVCMOS) operating at Vcc. Hosts shall use a pull-up
resistor connected to a Vcc_host on the 2-wire interface SCL (clock) and SDA (Data) signals. Detailed
electrical specification is given in Clause 3.1.2. Nomenclature for all registers more than 1 bit long is
MSB-LSB.
6.2.2 Management Interface Timing Specification
In order to support a multi-channel device a higher clock rate for the serial interface is considered. The timing
requirements are shown in Figure 21 and specified in Table 11.
QSFP is positioned to leverage 2-wire timing (Fast Mode devices) to align the use of related cores on host
ASICs. This clause closely follows the XFP MSA specification.
Figure 21 — QSFP Timing Diagram

Before initiating a 2-wire serial bus communication, the host shall provide setup time (Host_select_setup Table 11) on the ModSelL line of all modules on the 2-wire bus. The host shall not change the ModSelL line ofany module until the 2-wire serial bus communication is complete and the hold time requirement(Host_select_hold - Table 11) is satisfied. The 2-wire serial interface address of the QSFP module is
1010000X (A0h). In order to allow access to multiple QSFP modules on the same 2-wire serial bus, the QSFP
pinout includes a ModSelL or module select pin. This pin (which is pulled high or deselected in the module)
must be held low by the host to select the module of interest and allow communication over the 2-wire serialinterface. The module must not respond to or accept 2-wire serial bus instructions unless it is selected.
6.2.3 Serial Interface Protocol
The module asserts LOW for clock stretch on SCL.

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6.2.3.1 Management Timing Parameters
The timing parameters for the 2-Wire interface to the QSFP module are shown in Table 11.
Table 11 — QSFP 2-Wire Timing Specifications
Parameter
Clock Frequency

SymbolfSCL

Min
0Clock Pulse Width Low

tLOW

1.3

us

Clock Pulse Width High

tHIGH

0.6

us

Time bus free before
new transmission can
start

tBUF

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us

START Hold Time

tHD,STA

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us

START Set-up TimetSU,STA

0.6

us

Data In Hold TimetHD,DAT0us

Data In Set-up TimetSU,DAT

0.1

us

Input Rise TimetR,400(400kHz)
Input Fall Time (400kHz) tF,400

Max
400

Unit
kHz

300

ns

300

ns

STOP Set-up TimetSU,STOModSelL Setup Time

Host_sele 2
ct_setup

ms

ModSelL Hold Time

Host_sele 10
ct_holdus

Aborted sequence - bus Deselect_ 2
releaseAbort

ms

QSFP Public Specification

0.6

Conditions

Between STOP and START

From (VIL,MAX - 0.15) to(VIH,MIN + 0.15)
From (VIH,MIN + 0.15) to(VIL,MAX - 0.15)

usSetup time on the select lines
before start of a host initiatedserial bus sequence
Delay from completion of aserial bus sequence to changesof transceiver select status
Delay from a host de-asserting
ModSelL (at any point in a bus
sequence),to the QSFP module
releasing SCL and SDA

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6.3 Memory Interaction Specifications
QSFP memory transaction timings are given in Table 12. Single byte writable memory blocks are given in
Table 13. Multiple byte writable memory blocks are defined in Table 14.
Table 12 — QSFP Memory Specification
Parameter
Serial Interface Clock
Holdoff "Clock Stretching"Symbol
T_clock_holdComplete Single or
Sequential Write
Endurance (Write Cycles)

tWR

Min

50 k

Max
500

Unit
us

40

ms

Conditions
Maximum time the QSFP
module may hold the SCL line
low before continuing with aread or write operation
Complete (up to) 4 Byte Write

cycles70 C

oTable 13 — Single Byte Writable Memory Block
Page
A0h
A0h
A0h
A0h

Address
86
87
88
127

Volatile or NonVolatile
Volatile
Volatile
Volatile
Volatile

Description
Control Register
Rx Rate select register
Tx Rate select register
Page Select Byte

Table 14 — Multiple Byte Writable Memory Block
Address
89-92
100-106
119-122123-126128-255
225-241242-253# Bytes
4
7
4
4
128
16
12

QSFP Public Specification

Volatile /NonVolatile
Volatile
Volatile
Volatile
Volatile
Non-Volatile
Volatile
Volatile

Description
Application select per channel
Module Mask
Password Change Entry Area (Optional)
Password Entry Area (Optional)
User Writable memory - Page 02h
Vendor Specific Channel Controls - Page 03h
Channel Monitor Masks - Page 03h

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6.3.1 Timing for Soft Control and Status Functions
Timing for QSFP soft control and status functions are described in Table 15.
Table 15 — I/O Timing for Soft Control and Status Functions
Parameter
Initialization Time

Symbolt_init

Max
2000

Unit
ms

Reset Init Assert Timet_reset_init2

usSerial Bus Hardware
Ready Timet_serial

2000

ms

Time from power on until module responds todata transmission over the 2-wire serial bus

Monitor Data ReadyTime
Reset Assert Timet_data2000

mst_reset2000

ms

LPMode Assert Time

ton_LPMode

100

us

IntL Assert Time

ton_IntL

200

ms

IntL Deassert Time

toff_IntL

500

us

Rx LOS Assert Time

ton_los

100

ms

Tx Fault Assert Time

ton_Txfault

200

ms

Flag Assert Time

ton_flag200

msTime from power on to data not ready, bit 0 of
Byte 2, deasserted and IntL asserted
Time from rising edge on the ResetL pin until3
the module is fully functional
Time from assertion of LPMode (Vin:LPMode =Vih) until module power consumption enters
Power Level 1
Time from occurrence of condition triggering
IntL until Vout:IntL = Vol
4
Time from clear on read operation of
associated flag until Vout:IntL = Voh. This
includes deassert times for Rx LOS, Tx Fault
and other flag bits.
Time from Rx LOS state to Rx LOS bit set(value = 1b) and IntL asserted
Time from Tx Fault state to Tx Fault bit set(value = 1b) and IntL asserted
Time from occurrence of condition triggering flagto associated flag bit set (value = 1b) and IntL
asserted

Mask Assert Time

ton_mask

100

ms

Time from mask bit set (value = 1b) until
associated IntL assertion is inhibited

Mask Deassert Time

toff_mask

100

ms

Application or Rate
Select Change Timet_ratesel

100msTime from mask bit cleared (value = 0b) until
associated IntlL operation resumes
Time from change of state of Application or Rate
1
Select bit until transmitter or receiver bandwidth
is in conformance with appropriate specification

100

ms

Power_over-ride or
ton_Pdown
Power-set Assert Time

Conditions
2
Time from power on , hot plug or rising edge of3
Reset until the module is fully functional This
time does not apply to non-Power Level 0
modules in the Low Power State.
A Reset is generated by a low level longer thanthe minimum reset pulse time present on the
ResetL pin.
2

2

1

1

1

Time from P_Down bit set (value = 1b) until
module power consumption enters Power Level1

1
toff_Pdown
300
ms
Power_over-ride orTime from P_Down bit cleared (value = 0b) until
3Power-set Deassert
the module is fully functional
Time
Note 1. Measured from falling clock edge after stop bit of write transaction.

Note 2. Power on is defined as the instant when supply voltages reach and remain at or above theminimum level specified in Table 6.
Note 3. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted. The
module should also meet optical and electrical specifications.
Note 4. Measured from falling clock edge after stop bit of read transaction.

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Squelch and disable timings are defined in Table 16.
Table 16 — I/O Timing for Squelch and Disable
Parameter
SymbolRx Squelch Assert Time ton_Rxsq

Max
80

Unit
us

Conditions
Time from loss of Rx input signal until thesquelched output condition is reached. See
clause 3.1.3.1.
Time from resumption of Rx input signals until
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Rx Squelch Deassert
Time

toff_Rxsq

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Time from loss of Tx input signal until thesquelched output condition is reached. See
clause 3.1.3.2.

Tx Squelch Deassert
Time

toff_Txsq

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Time from resumption of Tx input signals until
normal Tx output condition is reached. See
clause 3.1.3.2.

Tx Disable Assert Time ton_txdis

100

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Time from Tx Disable bit set (value = 1b) until
optical output falls below 10% of nominal

Tx Disable Deassert
Time

toff_txdis

400

ms

Time from Tx Disable bit cleared (value = 0b)
until optical output rises above 90% of nominal

Rx Output Disable
Assert Time

ton_rxdis

100

ms

Time from Rx Output Disable bit set (value =11b) until Rx output falls below 10% of nominal

Rx Output Disable
Deassert Time

toff_rxdis

100

ms

1

1

Time from Rx Output Disable bit cleared (value1= 0b) until Rx output rises above 90% of
nominalSquelch Disable Assert ton_sqdis
100msThis applies to Rx and Tx Squelch and is the1Timetime from bit set (value = 1b) until squelch
functionality is disabled.
Squelch Disable
toff_sqdis
100msThis applies to Rx and Tx Squelch and is the1
Deassert Timetime from bit cleared (value = 0b) until squelch
functionality is enabled.
Note 1. Measured from falling clock edge after stop bit of write transaction.

6.4 Device Addressing and Operation
Serial Clock (SCL): The host supplied SCL input to QSFP transceivers is used to positive-edge clock data into
each QSFP device and negative-edge clock data out of each device. The SCL line may be pulled low by an
QSFP module during clock stretching.
Serial Data (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain or
open-collector driven and may be wire-ORed with any number of open-drain or open collector devices.
Master/Slave: QSFP transceivers operate only as slave devices. The host must provide a bus master for SCL
and initiate all read/write communication.
Device Address: Each QSFP is hard wired at the device address A0h. See Clause 6.6 for memory structure
within each transceiver.
Multiple Devices per SCL/SDA: While QSFP transceivers are compatible with point-to-point SCL/SDA, they
can share a single SCL/SDA bus by using the QSFP ModSelL line. See Clause 3.1.1.1,Clause 3.1.2 andTable 3 for more information.

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Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods. Data changes during SCL high periods indicate a START or
STOP condition. All addresses and data words are serially transmitted to and from the QSFP in 8-bit words.
Every byte on the SDA line must be 8-bits long. Data is transferred with the most significant bit (MSB) first.
START Condition: A high-to-low transition of SDA with SCL high is a START condition, which must precede
any other command.
STOP Condition: A low-to-high transition of SDA with SCL high is a STOP condition.
Acknowledge: After sending each 8-bit word, the transmitter releases the SDA line for one bit time, during
which the receiver is allowed to pull SDA low (zero) to acknowledge (ACK) that it has received each word.
Device address bytes and write data bytes initiated by the host shall be acknowledged by QSFP transceivers.
Read data bytes transmitted by QSFP transceivers shall be acknowledged by the host for all but the final byte
read, for which the host shall respond with a STOP instead of an ACK.
Memory (Management Interface) Reset: After an interruption in protocol, power loss or system reset the
QSFP management interface can be reset. Memory reset is intended only to reset the QSFP transceivermanagement interface (to correct a hung bus). No other transceiver functionality is implied.
1) Clock up to 9 cycles.
2) Look for SDA high in each cycle while SCL is high.
3) Create a START condition as SDA is highDevice Addressing: QSFP devices require an 8-bit device address word following a start condition to enable aread or write operation. The device address word consists of a mandatory sequence for the first seven mostsignificant bits in Figure 22. This is common to all QSFP devices.
Figure 22 — QSFP Device Address
1

0

1

0

0

MSB

0

0 R/W
LSB

The eighth bit of the device address is the read/write operating select bit. A read operation is initiated if this bit
is set high and a write operation is initiated if this bit is set low. Upon compare of the device address (withModSelL in the low state) the QSFP transceiver shall output a zero (ACK) on the SDA line to acknowledge theaddress.

6.5 Read/Write Functionality
6.5.1 QSFP Memory Address Counter (Read AND Write Operations)QSFP devices maintain an internal data word address counter containing the last address accessed during
the latest read or write operation, incremented by one. The address counter is incremented whenever a data
word is received or sent by the transceiver. This address stays valid between operations as long as QSFP
power is maintained. The address “roll over” during read and writes operations is from the last byte of the
128-byte memory page to the first byte of the same page.

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6.5.2 Read Operations (Current Address Read)
A current address read operation requires only the device address read word (10100001) be sent, see Figure
23. Once acknowledged by the QSFP, the current address data word is serially clocked out. The host does not
respond with an acknowledge, but does generate a STOP condition once the data word is read.
Figure 23 — QSFP Current Address Read Operation<-- QSFP ADDR -->

N S
L R
H S M
A T
S E
O T S
C O
B A
S A B
K P
D
T R
T
1 0 1 0 0 0 0 1 0 x x x x x x x x 1
L
A M
Q
S
C S
S
B
K B
F
P
<---DATA WORD--->6.5.3 Read Operations (Random Read)
A random read operation requires a “dummy” write operation to load in the target byte address as shown in
Figure 24. This is accomplished by the following sequence: The target 8-bit data word address is sent
following the device address write word (10100000) and acknowledged by the QSFP. The host then generates
another START condition (aborting the dummy write without incrementing the counter) and a current address
read by sending a device read address (10100001). The QSFP acknowledges the device address and seriallyclocks out the requested data word. The host does not respond with an acknowledge, but does generate a
STOP condition once the data word is read.
Figure 24 — QSFP Random Read<-- QSFP ADDR --><--MEMORY ADDR->

S
W
H T
R
OA M
L I
M
L
S R S
S T
S
S
T T B
B E
B
B
1 0 1 0 0 0 0 0 0x x x x x x x x 0
Q
S
A
A
F
C
C
P
K
K

<QSFP ADDR->

S
T
AM
RS
T B

R
N S
L E
A T
S A
C O
B D
K P
1 0 1 0 0 0 0 1 0x x x x x x x x 1
A M
C S
K B

L
S
B

<DATA WORD n-->6.5.3.1 Read Operations (Sequential Read)
Sequential reads are initiated by either a current address read Figure 25 or a random address read Figure 26.
To specify a sequential read, the host responds with an acknowledge (instead of a STOP) after each data

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word. As long as the QSFP receives an acknowledge, it shall serially clock out sequential data words. The
sequence is terminated when the host responds with a NACK and a STOP instead of an acknowledge.
Figure 25 — Sequential Address Read Starting at QSFP Current Address<QSFP ADDR>
S
HT
OA M
S RS
T T B

R
L E
S A
B D

A
C
K

NS
A T
CO
K P

A
C
K

1 0 1 0 0 0 0 1 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 1

Q
S
F
P

A M
CS
K B

L
S
B

<DATA W ORD n>

M
S
B

L
S
B

<DATA W ORD n+1>

M
S
B

L
S
B

<DATA W ORD n+x>

Figure 26 — Sequential Address Read Starting with Random QSFP Read<-- QSFP ADDR -->

S
H T
OA M
S R S
T T B

<-MEMORY ADDR>

W
R
L I
S T
B E

M
S
B

<-- QSFP ADDR -->

S
T
A M
R S
T B

L
S
B

1 0 1 0 0 0 0 0 0x x x x x x x x 0
Q
S
F
P

A
C
K

A
C
K

R
L E
S A
B D

A
C
K

N S
A T
C O
K P

A
C
K

1 0 1 0 0 0 0 1 0x x x x x x x x 0x x x x x x x x 0x x x x x x x x 1
A M
C S
K B

L
S
B

<DATA WORD n>

M
S
B

L
S
B

<DATA WORD n+1>

M
S
B

L
S
B

<DATA WORD n+x>6.5.4 Write Operations (BYTE Write)
A write operation requires an 8-bit data word address following the device address write word (10100000) andacknowledgement, see Figure 27. Upon receipt of this address, the QSFP shall again respond with a zero(ACK) to acknowledge and then clock in the first 8-bit data word. Following the receipt of the 8-bit data word,
the QSFP shall output a zero (ACK) and the host master must terminate the write sequence with a STOP
condition for the write cycle to begin. If a START condition is sent in place of a STOP condition (i.e. a repeated
START per the 2-wire interface specification) the write is aborted and the data received during that operation
is discarded. Upon receipt of the proper STOP condition, the QSFP enters an internally timed write cycle, tWR,
to internal memory. The QSFP disables it’s management interface input during this write cycle and shall not
respond or acknowledge subsequent commands until the write is complete. Note that 2-wire interface“Combined Format” using repeated START conditions is not supported on QSFP write commands.
Figure 27 — QSFP Write Byte Operation<-- QSFP ADDR --><-MEMORY ADDR-><-- DATA W ORD -->

S
W
H T
S
R
M
OA M
L
M
L
L I
T
S
S R S
S
S
S
S T
O
P
B
T T B
B
B
B
B E
1 0 1 0 0 0 0 0 0x x x x x x x x 0x x x x x x x x 0
Q
S
A
A
A
F
C
C
C
K
P
K
K

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6.5.5 Write Operations (Sequential Write)
QSFP’s shall support up to a 4 sequential byte write without repeatedly sending QSFP address and memory
address information as shown in Figure 28. A “sequential” write is initiated the same way as a single byte
write, but the host master does not send a stop condition after the first word is clocked in. Instead, after the
QSFP acknowledges receipt of the first data word, the host can transmit up to three more data words. The
QSFP shall send an acknowledge after each data word received. The host must terminate the sequential write
sequence with a STOP condition or the write operation shall be aborted and data discarded. Note that 2-wireinterface “combined format” using repeated START conditions is not supported on QSFP write commands.
Figure 28 — QSFP Sequential Write Operation<- QSFP ADDR ->
S
H T
OA M
S R S
T T B

<MEMORY ADDR>

W
R
L I
S T
B E

M
S
B

<--DATA WORD 1->

L
S
B

M
S
B

<--DATA WORD 2->

L
S
B

M
S
B

<--DATA WORD 3->

L
S
B

M
S
B

<-DATA WORD 4-->

L
S
B

M
S
B

S
T
O
P

L
S
B

1 0 1 0 0 0 0 0 0x x x x x x x x 0x x x x x x x x 0x x x x x x x x 0x x x x x x x x 0x x x x x x x x 0
Q
S
F
P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

6.5.6 Write Operations (Acknowledge Polling)
Once the QSFP internally timed write cycle has begun (and inputs are being ignored on the bus) acknowledge
polling can be used to determine when the write operation is complete. This involves sending a START
condition followed by the device address word. Only if the internal write cycle is complete shall the QSFP
respond with an acknowledge to subsequent commands, indicating read or write operations can continue.

6.6 QSFP Memory Map
This subclause defines the Memory Map for QSFP transceiver used for serial ID, digital monitoring andcertain control functions. The interface is mandatory for all QSFP devices. The interface has been designed
largely after the XFP MSA as defined in INF-8077i Rev.4.0. The memory map has been changed in order toaccommodate 4 optical channels and limit the required memory space. The single address approach as usedin XFP using paging for provision of more less time critical memory content is used in order to enable time
critical interactions between host and transceiver.
The structure of the memory is shown in Figure 29. The memory space is arranged into a lower, single page,address space of 128 bytes and multiple upper address space pages. This structure permits timely access toaddresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID
information and threshold settings, are available with the Page Select function. The structure also provides
address expansion by adding additional upper pages as needed. For example, in Figure 29 upper pages 01
and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02
provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. See
Table 39 for details regarding declaration of optional upper pages 01 and 02.

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The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order toenable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has beenasserted, the host can read out the flag field to determine the effected channel and type of flag.
Figure 29 — QSFP Memory Map
2-wire serial address, 1010000x (A0h)"
0
2
3
21
22
33
34
81
82
85
86
97
98
99
100
106
107
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123
126
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127

Page 00
128
191
192
223
224
255

Base ID Fields
Extended ID
Vendor Specific ID

ID and status
Interrupt Flags
Module Monitors
Channel Monitors
Reserved
Control
Reserved
Module and Channel Mask
Reserved(3 Bytes)(19 Bytes)(12 Bytes)(48 Bytes)(4 Bytes)(12 Bytes)(2 Bytes)(7 Bytes)(12 Bytes)

Password Change Entry
Area (Optional)(4 Bytes)

Password Entry Area
(Optional)(4 Bytes)

Page Select Byte

(1 Bytes)

Page 01 (Optional)(64 Bytes)

128
128

(32 Bytes)

129
129

(32 Bytes)

130
131
132
133

CC_APPSAST Table Length (TL)
Application Code Entry 0
Application Code Entry 1

Page 02 (Optional)(1 Bytes)

255

254

Application Code Entry TL

User EEPROM Data

(128 Bytes)

128
175

Module Threshold(48 Bytes)(1 Bytes)176(2 Bytes)

224(2 Bytes)

226 Vendor Specific Channel (16 Bytes)
Controls
241

223
225

242

other entries

255

128

Page 03253(2 Bytes)

254
255

Channel Threshold
Reserved

Channel Monitor Masks
Reserved(48 Bytes)(2 Bytes)(12 Bytes)(2 Bytes)

In order to allow access to multiple QSFP transceivers on the same 2-wire serial interface, the QSFP pinout
includes a ModSelL pin which allows the host to select the respective transceiver for interaction. See Clause
3.1.1.1 for details on ModSelL and Clause 3.1.2 for details of the 2-Wire serial interface.
Note: Unless specifically noted, all informative ID fields must be filled out. Using a value of 0 to indicate a field
is unspecified (as is common in the SFP definition) is not permitted. Reserved memory locations are to be
filled with logic zeros in all bit locations for reserved bytes, and in reserved bit locations for partially specified
byte locations as described in this clause.
APPLICABLE DOCUMENTS
Digital Diagnostic Monitoring Interface for Optical Transceivers SFF document number: SFF-8472, rev. 9.5
June 1, 2004.

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6.6.1 Lower Memory Map
The lower 128 bytes of the 2-wire serial bus address space, see Table 17, is used to access a variety ofmeasurements and diagnostic functions, a set of control functions, and a means to select which of the various
upper memory map pages are accessed on subsequent reads. This portion of the address space is always
directly addressable and thus is chosen for monitoring and control functions that may need to be repeatedlyaccessed. The definition of Identifier field is the same as page 00h Byte 128.
Table 17 — Lower Memory Map
Byte Address
0
1-2
3-21
22-33
34-81
82-85
86-97
98-99
100-106
107-118
119-122123-126
127

Description
Identifier (1 Byte)
Status (2 Bytes)
Interrupt Flags (19 Bytes)
Module Monitors (12 Bytes)
Channel Monitors (48 Bytes)
Reserved (4 Bytes)
Control (12 Bytes)
Reserved (2 Bytes)
Module and Channel Masks (7 Bytes)
Reserved (12 Bytes)
Password Change Entry Area (optional) (4 Bytes)
Password Entry Area (optional) (4 Bytes)
Page Select Byte

Type
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write

6.6.1.1 Status Indicator Bits
The Status Indicators are defined in Table 18.
Table 18 — Status Indicators
Byte Bit
1
All
2
7
6
5
4
3
2
1
0

Name
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IntL
Digital state of the IntL interrupt output pin.
Data_Not_ Indicates transceiver has not yet achieved power up and monitor data is
Ready
not ready. Bit remains high until data is ready to be read at which timethe device sets the bit low.

The Data_Not_Ready bit is high during module power up and prior to a valid suite of monitor readings. Once
all monitor readings are valid, the bit is set low until the device is powered down.

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6.6.1.2 Interrupt Flags
A portion of the memory map (Bytes 3 through 21), form a flag field. Within this field, the status of LOS and Tx
Fault as well as alarms and warnings for the various monitored items is reported. For normal operation anddefault state, the bits in this field have the value of 0b. For the defined conditions of LOS, Tx Fault, moduleand channel alarms and warnings, the appropriate bit or bits are set, value = 1b. Once asserted, the bits
remained set (latched) until cleared by a read operation that includes the affected bit or reset by the ResetL
pin.
The Channel Status Interrupt Flags are defined in Table 19.
Table 19 — Channel Status Interrupt Flags
Byte
3

4

5

Bit
7
6
5
4
3
2
1
0
7-4
3
2
1
0
All

Name
L-Tx4 LOS
L-Tx3 LOS
L-Tx2 LOS
L-Tx1 LOS
L-Rx4 LOS
L-Rx3 LOS
L-Rx2 LOS
L-Rx1 LOS
Reserved
L-Tx4 Fault
L-Tx3 Fault
L-Tx2 Fault
L-Tx1 Fault
Reserved

Description
Latched TX LOS indicator, channel 4 (Optional)
Latched TX LOS indicator, channel 3 (Optional)
Latched TX LOS indicator, channel 2 (Optional)
Latched TX LOS indicator, channel 1 (Optional)
Latched RX LOS indicator, channel 4
Latched RX LOS indicator, channel 3
Latched RX LOS indicator, channel 2
Latched RX LOS indicator, channel 1
Latched TX fault indicator, channel 4
Latched TX fault indicator, channel 3
Latched TX fault indicator, channel 2
Latched TX fault indicator, channel 1

The Module Monitor Interrupt Flags are defined in Table 20.
Table 20 — Module Monitor Interrupt Flags
Byte
6

7

8

Bit
7
6
5
4
3-0
7

Name
L-Temp High Alarm
L-Temp Low Alarm
L-Temp High Warning
L-Temp Low Warning
Reserved
L-Vcc High Alarm

Description
Latched high temperature alarm
Latched low temperature alarm
Latched high temperature warning
Latched low temperature warning

6

L-Vcc Low Alarm

Latched low supply voltage alarm

5

L-Vcc High Warning

Latched high supply voltage warning

4

L-Vcc Low Warning

Latched low supply voltage warning

3-0

Reserved

All

Reserved

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The Channel Monitor Interrupt Flags are defined in Table 21.
Table 21 — Channel Monitor Interrupt Flags
Byte
9

10

11

12

13-14
15-16
17-18
19-20
21

Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
All
All
All
All
All

Name
L-Rx1 Power High Alarm
L-Rx1 Power Low Alarm
L-Rx1 Power High Warning
L-Rx1 Power Low Warning
L-Rx2 Power High Alarm
L-Rx2 Power Low Alarm
L-Rx2 Power High Warning
L-Rx2 Power Low Warning
L-Rx3 Power High Alarm
L-Rx3 Power Low Alarm
L-Rx3 Power High Warning
L-Rx3 Power Low Warning
L-Rx4 Power High Alarm
L-Rx4 Power Low Alarm
L-Rx4 Power High Warning
L-Rx4 Power Low Warning
L-Tx1 Bias High Alarm
L-Tx1 Bias Low Alarm
L-Tx1 Bias High Warning
L-Tx1 Bias Low Warning
L-Tx2 Bias High Alarm
L-Tx2 Bias Low Alarm
L-Tx2 Bias High Warning
L-Tx2 Bias Low Warning
L-Tx3 Bias High Alarm
L-Tx3 Bias Low Alarm
L-Tx3 Bias High Warning
L-Tx3 Bias Low Warning
L-Tx4 Bias High Alarm
L-Tx4 Bias Low Alarm
L-Tx4 Bias High Warning
L-Tx4 Bias Low Warning
Reserved
Reserved
Reserved
Reserved
Reserved

Description
Latched high RX power alarm, channel 1
Latched low RX power alarm, channel 1
Latched high RX power warning, channel 1
Latched low RX power warning, channel 1
Latched high RX power alarm, channel 2
Latched low RX power alarm, channel 2
Latched high RX power warning, channel 2
Latched low RX power warning, channel 2
Latched high RX power alarm, channel 3
Latched low RX power alarm, channel 3
Latched high RX power warning, channel 3
Latched low RX power warning, channel 3
Latched high RX power alarm, channel 4
Latched low RX power alarm, channel 4
Latched high RX power warning, channel 4
Latched low RX power warning, channel 4
Latched high TX bias alarm, channel 1
Latched low TX bias alarm, channel 1
Latched high TX bias warning, channel 1
Latched low TX bias warning, channel 1
Latched high TX bias alarm, channel 2
Latched low TX bias alarm, channel 2
Latched high TX bias warning, channel 2
Latched low TX bias warning, channel 2
Latched high TX bias alarm, channel 3
Latched low TX bias alarm, channel 3
Latched high TX bias warning, channel 3
Latched low TX bias warning, channel 3
Latched high TX bias alarm, channel 4
Latched low TX bias alarm, channel 4
Latched high TX bias warning, channel 4
Latched low TX bias warning, channel 4
Reserved channel monitor flags, set 3
Reserved channel monitor flags, set 4
Reserved channel monitor flags, set 5
Reserved channel monitor flags, set 6

6.6.1.3 Module Monitors
Real time monitoring for the QSFP module include transceiver temperature, transceiver supply voltage, andmonitoring for each transmit and receive channel. Channel monitoring functions are described in Clause
6.6.1.4.
Measured parameters are reported in 16-bit data fields, i.e., two concatenated bytes. These are shown in
Table 22. The 16 bit-data fields allow for wide dynamic range. This is not intended to imply that a 16-bit A/D
system is recommended or required in order to achieve the accuracy goals stated below. The width of thedata field should not be taken to imply a given level of precision. It is conceivable that the accuracy goals
herein can be achieved by a system having less than 16 bits of resolution. It is recommended that any
low-order data bits beyond the system’s specified accuracy be fixed at zero. Overall system accuracy andprecision will be vendor dependent.

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To guarantee coherency of the diagnostic monitoring data, the host is required to retrieve any multi-byte fields
from the diagnostic monitoring data structure by the use of a single two-byte read sequence across the 2-wireserial interface. The transceiver is required to insure that any multi-byte fields that are updated withdiagnostic monitoring data must have this update done in a fashion that guarantees coherency andconsistency of the data. In other words, the update of a multi-byte field by the transceiver must not occur suchthat a partially updated multi-byte field can be transferred to the host. Also, the transceiver shall not update amulti-byte field within the structure during the transfer of that multi-byte field to the host, such that partially
updated data would be transferred to the host.
Accuracy requirements specified below shall apply to the operating signal range specified in the relevant
standard. The manufacturer’s specification should be consulted for more detail on the conditions under which
the accuracy requirements are met.
Measurements are calibrated over vendor specified operating temperature and voltage and should beinterpreted as defined below. Alarm and warning threshold values should be interpreted in the same manneras real time 16-bit data.
Internally measured transceiver temperature are represented as a 16-bit signed twos complement value inincrements of 1/256 degrees Celsius, yielding a total range of –128C to +128C that is considered valid
between –40 and +125C. Temperature accuracy is vendor specific but must be better than ±3 degrees
Celsius over specified operating temperature and voltage. Please see vendor specification for details on
location of temperature sensor.
Internally measured transceiver supply voltage are represented as a 16-bit unsigned integer with the voltage
defined as the full 16 bit value (0 – 65535) with LSB equal to 100 uVolt, yielding a total measurement range of
0 to +6.55 Volts. Practical considerations to be defined by transceiver manufacturer will tend to limit the actual
bounds of the supply voltage measurement. Accuracy is vendor specific but must be better than ±3% of the
manufacturer’s nominal value over specified operating temperature and voltage.
Table 22 — Module Monitoring Values
Byte
22
23
24-25
26
27
28 - 33

Bit
All
All
All
All
All
All

Name
Temperature MSB
Temperature LSB
Reserved
Supply Voltage MSB
Supply Voltage LSB
Reserved

Description
Internally measured module temperature

Internally measured module supply voltage

6.6.1.4 Channel Monitoring
Real time channel monitoring is for each transmit and receive channel and includes optical input power andTx bias current. Module monitoring functions are described in Clause 6.6.1.3.
Measurements are calibrated over vendor specified operating temperature and voltage and should beinterpreted as defined below. Alarm and warning threshold values should be interpreted in the same manneras real time 16-bit data. Table 23 defines the Channel Monitoring.
Measured TX bias current is in mA and are represented as a 16-bit unsigned integer with the current definedas the full 16 bit value (0 – 65535) with LSB equal to 2 uA, yielding a total measurement range of 0 to 131 mA.
Accuracy is vendor specific but must be better than ±10% of the manufacturer’s nominal value over specified
operating temperature and voltage.
Measured RX received optical power is in mW and can represent either average received power or OMA
depending upon how bit 3 of byte 220 (upper memory page 00h) is set. Represented as a 16 bit unsigned
integer with the power defined as the full 16 bit value (0 – 65535) with LSB equal to 0.1 uW, yielding a total
measurement range of 0 to 6.5535 mW (~-40 to +8.2 dBm). Absolute accuracy is dependent upon the exact
optical wavelength. For the vendor specified wavelength, accuracy shall be better than ±3 dB over specified
temperature and voltage. This accuracy shall be maintained for input power levels up to the lesser ofmaximum transmitted or maximum received optical power per the appropriate standard. It shall be

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maintained down to the minimum transmitted power minus cable plant loss (insertion loss or passive loss) per
the appropriate standard. Absolute accuracy beyond this minimum required received input optical power
range is vendor specific.
Table 23 — Channel Monitoring Values

Byte
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50-57
58-65
66-73
74-81

Bit
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All

Name
Rx1 Power MSB
Rx1 Power LSB
Rx2 Power MSB
Rx2 Power LSB
Rx3 Power MSB
Rx3 Power LSB
Rx4 Power MSB
Rx4 Power LSB
Tx1 Bias MSB
Tx1 Bias LSB
Tx2 Bias MSB
Tx2 Bias LSB
Tx3 Bias MSB
Tx3 Bias LSB
Tx4 Bias MSB
Tx4 Bias LSB

QSFP Public Specification

Description
Internally measured RX input power, channel 1
Internally measured RX input power, channel 2Internally measured RX input power, channel 3
Internally measured RX input power, channel 4Internally measured TX bias, channel 1
Internally measured TX bias, channel 2Internally measured TX bias, channel 3
Internally measured TX bias, channel 4
Reserved channel monitor set 3
Reserved channel monitor set 4
Reserved channel monitor set 5
Reserved channel monitor set 6

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6.6.1.5 Control Bytes

Control Bytes are defined in Table 24.
Table 24 — Control Bytes
Byte
86

Bit Name
Description
7-4 Reserved
1
3
Tx4_Disable
Read/write bit that allows software disable of transmitters.
1
2
Tx3_Disable
Read/write bit that allows software disable of transmitters.
11
Tx2_Disable
Read/write bit that allows software disable of transmitters.
10
Tx1_Disable
Read/write bit that allows software disable of transmitters.
87
7
Rx4_Rate_SelectSoftware Rate Select, Rx channel 4 msb (Optional)
6
Rx4_Rate_SelectSoftware Rate Select, Rx channel 4 lsb (Optional)
5
Rx3_Rate_SelectSoftware Rate Select, Rx channel 3 msb (Optional)
4
Rx3_Rate_SelectSoftware Rate Select, Rx channel 3 lsb (Optional)
3
Rx2_Rate_SelectSoftware Rate Select, Rx channel 2 msb (Optional)
2
Rx2_Rate_SelectSoftware Rate Select, Rx channel 2 lsb (Optional)
1
Rx1_Rate_SelectSoftware Rate Select, Rx channel 1 msb (Optional)
0
Rx1_Rate_SelectSoftware Rate Select, Rx channel 1 lsb (Optional)
88
7
Tx4_Rate_SelectSoftware Rate Select, Tx channel 4 msb (Optional)
6
Tx4_Rate_SelectSoftware Rate Select, Tx channel 4 lsb (Optional)
5
Tx3_Rate_SelectSoftware Rate Select, Tx channel 3 msb (Optional)
4
Tx3_Rate_SelectSoftware Rate Select, Tx channel 3 lsb (Optional)
3
Tx2_Rate_SelectSoftware Rate Select, Tx channel 2 msb (Optional)
2
Tx2_Rate_SelectSoftware Rate Select, Tx channel 2 lsb (Optional)
1
Tx1_Rate_SelectSoftware Rate Select, Tx channel 1 msb (Optional)
0
Tx1_Rate_SelectSoftware Rate Select, Tx channel 1 lsb (Optional)
89
All Rx4_Application_SelectSoftware Application Select per SFF-8079, Rx Channel 4 (Optional)
90
All Rx3_Application_SelectSoftware Application Select per SFF-8079, Rx Channel 3 (Optional)91
All Rx2_Application_SelectSoftware Application Select per SFF-8079, Rx Channel 2 (Optional)
92
All Rx1_Application_SelectSoftware Application Select per SFF-8079, Rx Channel 1 (Optional)
93
2-7 Reserved
931Power_set
Power set to low power mode. Default 0.
930Power_over-ride
Override of LPMode signal setting the power mode with software.
94
All Tx4_Application_SelectSoftware Application Select per SFF-8079, Tx Channel 4 (Optional)
95
All Tx3_Application_SelectSoftware Application Select per SFF-8079, Tx Channel 3 (Optional)
96
All Tx2_Application_SelectSoftware Application Select per SFF-8079, Tx Channel 2 (Optional)
97
All Tx1_Application_SelectSoftware Application Select per SFF-8079, Tx Channel 1 (Optional)
98-99 All Reserved
1. Writing “1” disables the laser of the channel.

If software Rate Select is not implemented, the transceiver ignores the value of Rate Select bits. The registers
read all “0”s upon power-up.
6.6.1.6 Module and Channel Masks

The host system may control which flags result in an interrupt (IntL) by setting high individual bits from a set ofmasking bits in bytes 100-104 for module flags, and bytes 242-253 of page 03h for channel flags. These aredescribed in Table 25 and Table 48. A 1 value in a masking bit prevents the assertion of the hardware IntL pinby the corresponding latched flag bit. Masking bits are volatile and startup with all unmasked (masking bits 0).
The mask bits may be used to prevent continued interruption from on-going conditions, which would otherwise
continually reassert the hardware IntL pin.

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Byte
100

Bit
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6
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101
7-4
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102
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103
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6
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105-106 All

Table 25 — IntL Masking Bits for Module and Channel Status Interrupts
Name
Description
M-Tx4 LOS
Masking bit for TX LOS indicator, channel 4 (Optional)
M-Tx3 LOS
Masking bit for TX LOS indicator, channel 3 (Optional)
M-Tx2 LOS
Masking bit for TX LOS indicator, channel 2 (Optional)
M-Tx1 LOS
Masking bit for TX LOS indicator, channel 1 (Optional)
M-Rx4 LOS
Masking bit for RX LOS indicator, channel 4
M-Rx3 LOS
Masking bit for RX LOS indicator, channel 3
M-Rx2 LOS
Masking bit for RX LOS indicator, channel 2
M-Rx1 LOS
Masking bit for RX LOS indicator, channel 1
Reserved
M-Tx4 Fault
Masking bit for TX fault indicator, channel 4
M-Tx3 Fault
Masking bit for TX fault indicator, channel 3
M-Tx2 Fault
Masking bit for TX fault indicator, channel 2
M-Tx1 Fault
Masking bit for TX fault indicator, channel 1
Reserved
M-Temp High Alarm
Masking bit for high Temperature alarm
M-Temp Low Alarm
Masking bit for low Temperature alarm
M-Temp High Warning
Masking bit for high Temperature warning
M-Temp Low Warning
Masking bit for low Temperature warning
Reserved
M-Vcc High Alarm
Masking bit for high Vcc alarm
M-Vcc Low Alarm
Masking bit for low Vcc alarm
M-Vcc High Warning
Masking bit for high Vcc warning
M-Vcc Low Warning
Masking bit for low Vcc warning
Reserved
Reserved

6.6.1.7 Rate SelectRate Select is an optional control used to limit the receiver bandwidth for compatibility with multiple data rates(most likely Fibre Channel). In addition, rate selection allows the transmitter to be fine tuned for specific data
rate transmissions.
The transceiver may:a) Provide no support for rate selectionb) Rate selection using extended rate selectc) Rate selection with application select tables
6.6.1.7.1 No Rate Selection Support

When no rate selection is supported, (page 00h, byte 221, bits 2 and 3) have a value of 0 and Options (page00h, byte 195, bit 5) have a value of 0. Lack of implementation does not indicate lack of simultaneouscompliance with multiple standard rates. Compliance with particular standards should be determined fromTransceiver Values (See Table 33).
6.6.1.7.2 Extended Rate Selection

When (page 00h, byte 221, bits 2 and 3) have the values of 0 and 1 respectively and at least one of the bits inthe Extended Rate Compliance byte (page 00h, byte 141) have a value of one, the module supports extended
rate select. Extended rate selection has reserved two bits per channel in the Rxn_Rate_Select and two bits
per channel in the Txn_Rate_Select to denote up to four rates. Table 26 defines the functionality when bit 0 of
byte 141 is 1. All other values of Extended Rate Compliance byte are reserved.

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Table 26 — Functionality of xN_Rate_Select with Extended Rate Selection
xN_Rate_Selectmsb Value0

xN_Rate_Selectlsb Value
0

0

1

1

0

1

1

Description
Optimized for data rates less than
2.2Gb/s
Optimized for data rates from 2.2 up
to 6.6Gb/s
Optimized for 6.6 Gb/s data rates andabove
Reserved

6.6.1.7.3 Rate Selection Using Application Select Tables

Application Select maximizes compatibility with SFF-8079 Part 2 for transceivers that are SFF-8472
compliant.
When the Rate Select declaration bits (page 00h, byte 221, bits 2 and 3) have the values of 1 and 0
respectively, the Application Select method defined in Page 01h is used (see Clause 6.6.3).
The host reads the entire application select table on page 01h to determine the capabilities of the transceiver.
The host controls each channel separately by writing a Control Mode and Table Select (TS) byte to bytes
89-92 and bytes 94-97. The bits of the Rx_Application Select and the Tx_Application Select registers aredefined in Table 27.
Table 27 — Definition of Application Select (Bytes 89 to 92 and Bytes 94 to 97))
7
6
5
4
3
Control Mode Table Select, TS

2

1

0

Control Mode defines the application control mode. Table Select selects module behavior from the AST
among 63 possibilities (000000 to 111110). Note that (111111) is invalid.
Table 28 — Detailed Description of Control Mode
Bit 7

Bit 6

Function

0

0
Don't
care

Extended rate selection

Address 87, 88 Control
lsb and msb are used according to
declaration bits.

Application SelectIgnored

1

Table Select Control
IgnoredField points toapplication

Default values for control mode is 0,0 and is volatile memory.
6.6.1.8 Password Entry and change

Bytes 119-126 are reserved for an optional password entry function. The Password entry bytes are write only
and will be retained until power down, reset, or rewritten by host. This function may be used to control read/
write access to vendor specific page 02h. Additionally, module vendors may use this function to implement
write protection of Serial ID and other QSFP read only information. Passwords may be supplied to and usedby Host manufacturers to limit write access in the User EEPROM Page 02h.
Password access shall not be required to access QSFP defined data in the lower memory page 00h or inupper pages 00h, 02h and 03h. Note that multiple module manufacturer passwords may be defined to allow
selective access to read or write to various sections of memory as allowed above.
Host manufacturer and module manufacturer passwords shall be distinguished by the high order bit (bit 7,
byte 123). All host manufacturer passwords shall fall in the range of 00000000h to 7FFFFFFFh, and all
module manufacturer passwords in the range of 80000000h to FFFFFFFFh. Host manufacturer passwords
shall be initially set to 00001011h in new modules.
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Host manufacturer passwords may be changed by writing a new password in bytes 119-122 when the correct
current Host manufacture password has been entered in 123-126, with the high order bit being ignored andforced to a value of 0 in the new password.
The password entry field shall be set to 00000000h on power up and reset.

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6.6.2 Upper Memory Map Page 00h

Page 00h consists of the Serial ID and is used for read only identification information. The Serial ID is divided
into the Base_ID Fields, Extended ID Fields and Vendor Specific ID Fields. The format of the Serial ID
Memory Map is shown in Table 29.
Table 29 — Serial ID: Data Fields
Size (Bytes)
Address
Base_ID Fields
1
128
1
129
1
130
8
131-138
1
139
1
140

Name

Description of Base ID Field
Identifier Type of serial transceiver
Extended identifier of serial transceiver
Code for connector type
Code for electronic compatibility or optical compatibility
Code for serial encoding algorithm
Nominal bit rate, units of 100 MBits/s.
Tags for Extended RateSelect compliance
Link length supported for SMF fiber in km

141

1

Identifier
Ext. Identifier
Connector
Transceiver
Encoding
BR, nominal
Extended RateSelectCompliance142

1

Length(SMF)143

1

Length (E-50µm)

Link length supported for EBW 50/125 µm fiber, units of 2 m

144

1

Length (50 µm)

Link length supported for 50/125 µm fiber, units of 1 m

145

1Length (62.5 µm)

Link length supported for 62.5/125 µm fiber, units of 1 m

146
147
148-163164
165-167
168-183
184-185
186-187

1
1
16
1
3
16
2
2

Length (Copper)
Device Tech
Vendor name
Extended Transceiver
Vendor OUI
Vendor PN
Vendor rev
Wavelength

Link length supported for copper, units of 1m
Device technology
QSFP vendor name (ASCII)
Extended Transceiver Codes for InfiniBand
QSFP vendor IEEE company ID
Part number provided by QSFP vendor (ASCII)
Revision level for part number provided by vendor (ASCII)
Nominal laser wavelength (Wavelength = value / 20 in nm)

188-1892

Wavelength Tolerance

Guaranteed range of laser wavelength (+/- value) from Nominal
wavelength.(Wavelength Tol. = value/200 in nm)

1901

Max Case Temp

Maximum Case Temperature in Degrees C.

CC_BASE

Check code for Base ID Fields (addresses 128-190)

Options

Rate Select, TX Disable, TX Fault, LOS

1
191
Extended ID Fields
4192-195
196-211212-219

16
8

Vendor SN
Date code

Serial number provided by vendor (ASCII)
Vendor's manufacturing date code

2201

Diagnostic MonitoringType
Enhanced Options
Reserved
CC_EXT

Indicates which type of diagnostic monitoring is implemented (ifany) in the transceiver. Bit 1, 0 Reserved
Indicates which optional enhanced features are implemented in
the transceiver.
Reserved
Check code for the Extended ID Fields (addresses 192-222)

Vendor SpecificVendor Specific EEPROM

1
221
1
222
1
223
Vendor Specific ID Fields
32
224-255

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6.6.2.1 Identifier (Address 128)

The identifier value specifies the physical device described by the serial information. This value shall be
included in the serial data. The defined identifier values are shown in Table 30. The QSFP transceiver shalluse the identifier 0Ch.
Table 30 — Identifier Values

Value
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh-7Fh
80-FFhDescription of Physical Device
Unknown or unspecified
GBIC
Module/connector soldered to motherboard
SFP transceiver
300 pin XBI
XENPAK
XFP
XFF
XFP-E
XPAK
X2
DWDM-SFPQSFPReserved
Vendor specific6.6.2.2 Extended Identifier (Address 129)

The extended identifier provides additional information about the basic transceiver types such as whether thetransceiver contains a CDR function and identifies the power consumption class it belongs to.
Table 31 — Extended Identifier Values
Bit
7-6

5
4
3-0

Description of device type
00: Power Class 1 Module (1.5 W max. power consumption)
01: Power Class 2 Module (2.0 W max. power consumption)
10: Power Class 3 Module (2.5 W max. power consumption)
11: Power Class 4 Module (3.5 W max. power consumption)
Reserved
0: No CLEI code present in Page 02h
1: CLEI code present in Page 02h
Reserved

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6.6.2.3 Connector (Address 130)

The Connector value indicates the external connector provided on the interface. This value shall be includedin the serial data. The defined connector values are shown in Table 32. Note that 01h – 0Bh are not QSFP
compatible, and are included for compatibility with other standards.

Value
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
OD-1Fh20h
21h
22h
23h-7Fh
80-FFhTable 32 — Connector Values
Description of Connector
Unknown or unspecifiedSC
Fibre Channel Style 1 copper connector
Fibre Channel Style 2 copper connector
BNC/TNC
Fibre Channel coaxial headers
FiberJack
LC
MT-RJ
MU
SG
Optical pigtail
MPO
Reserved
HSSDC II
Copper Pigtail
RJ45
Reserved
Vendor specific

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6.6.2.4 Transceiver (Address 131-138)

The following bit significant indicators define the electronic or optical interfaces that are supported by the
QSFP transceiver. At least one bit shall be set in this field. For Fibre Channel QSFPs, the Fibre Channel
speed, transmission media, transmitter technology, and distance capability shall all be indicated.
Table 33 — Transceiver Values
Address

Bit

Description of Transceiver Data

10 Gigabit Ethernet Compliance Codes
131
7
Reserved131
6
10GBase-LRM
131
5
10GBase-LR
131
4
10GBASE-SR
131
3-0
Reserved
SONET Compliance Codes
132
7-4
Reserved
132
3
Reserved132
2
OC 48, long reach132
1
OC 48, intermediate reach132
0
OC 48, short reach133
7
Reserved
133
6
OC 12, single mode long reach133
5
OC 12, single mode inter. reach133
4
OC 12, single mode short reach133
3
Reserved
133
2
OC 3, single mode long reach133
1
OC 3, single mode inter. Reach
133
0
OC3, single mode short reach
Gigabit Ethernet Compliance Codes
134
7-4
Reserved
134
3
1000BASE-T
134
2
1000BASE-CX
134
1
1000BASE-LX
134
01000BASE-SX
Fibre Channel link length
135
7very long distance (V)135
6short distance (S)1355Intermediate distance (I)135
4Long distance (L)135
3Medium (M)Fibre Channel transmitter technology
135
2
Reserved
135
1
Longwave laser (LC)135
0Electrical inter-enclosure (EL)136
7Electrical intra-enclosure
136
6
Shortwave laser w/o OFC (SN)136
5Shortwave laser w/ OFC (SL)136
4Longwave laser (LL)136
0-3
Reserved
Fiber Channel transmission media
137
7
Twin Axial Pair (TW)137
6Shielded Twisted Pair (TP)137
5
Miniature Coax (MI)137
4Video Coax (TV)137
3Multi-mode, 62.5m (M6)137
2Multi-mode, 50m (M5)137
1Multi-mode, 50um (OM3)137
0Single Mode (SM)
Fibre Channel Speed
138
71200 MBytes/Sec
138
6
800 MBytes/Sec
138
5
Reserved
138
4
400 MBytes/Sec
138
3
Reserved138
2
200 MBytes/Sec
138
1
Reserved
138
0
100 MBytes/Sec

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25
26
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29
30
31
32
33
34
35
36
37
38
39
40
41
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43
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45
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47
48
49

6.6.2.5 Encoding (Address 139)

The encoding value indicates the serial encoding mechanism that is the nominal design target of the particular
QSFP transceiver. The value shall be contained in the serial data. The defined encoding values are shown in
Table 34.
Table 34 — Encoding Values
Code
00h
01h
02h
03h
04h
05h
06h
07h - FFh

Description of encoding mechanism
Unspecified
8B10B
4B5B
NRZ
SONET Scrambled
64B66B
Manchester
Reserved

6.6.2.6 BR, nominal (Address 140)

The nominal bit rate (BR, nominal) is specified in units of 100 Megabits per second, rounded off to the nearest
100 Megabits per second. The bit rate includes those bits necessary to encode and delimit the signal as wellas those bits carrying data information. A value of 0 indicates that the bit rate is not specified and must be
determined from the transceiver technology. The actual information transfer rate will depend on the encodingof the data, as defined by the encoding value.
6.6.2.7 Extended RateSelect Compliance (Address 141)

The Extended RateSelect Compliance field is used to allow a single QSFP transceiver the flexibility to comply
with single or multiple Extended RateSelect definitions. A definition is indicated by presence of a “1” in thespecified bit tag position. If exclusive, non-overlapping bit tag definitions are used, Page 00h, byte 141 willallow compliance to 8 (1-8) distinct multi-rate definitions.
Table 35 — Extended RateSelect Compliance Tag Assignment
Address Bits
141
7-1

Description
Reserved

141

QSFP Rate Select Version 1. This functionality
is different from SFF-8472 and SFF-8431.

0Further details of the use of this field can be found in Clause 6.6.1.7.
6.6.2.8 Length (Standard SM Fiber)-km (Address 142)

Addition to EEPROM data from original GBIC definition. This value specifies the link length that is supportedby the QSFP transceiver while operating in compliance with the applicable standards using single mode fiber.
Supported link length is as specified in the SFF 8074i standard. The value is in units of kilometers. A value ofzero means that the transceiver does not support single mode fiber or that the length information must be
determined from the transceiver technology.
6.6.2.9 Length (OM3) (Address 143)

This value specifies the link length that is supported by the QSFP transceiver while operating in compliancewith the applicable standards using 2000 MHZ*km (850 nm) extended bandwidth 50 micron core multimodefiber. The value is in units of 2 meters. A value of zero means that the transceiver does not support OM3 fiberor that the length information must be determined from the transceiver technology.

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6.6.2.10 Length (OM2) (Address 144)

This value specifies the link length that is supported by the QSFP transceiver while operating in compliancewith the applicable standards using 500 MHz*Km (850 nm and 1310 nm) 50 micron multi-mode fiber. The
value is in units of 1 meter. A value of zero means that the transceiver does not support OM2 fiber or that thelength information must be determined from the transceiver technology.
6.6.2.11 Length (OM1) (Address 145)

This value specifies the link length that is supported by the QSFP transceiver while operating in compliancewith the applicable standards using 200 MHz*Km (850 nm) and 500 MHz*Km (1310 nm) 62.5 micron
multi-mode fiber. The value is in units of 1 meter. A value of zero means that the transceiver does not support
OM1 fiber or that the length information must be determined from the transceiver technology.
6.6.2.12 Length (Copper) (Address 146)

This value specifies the minimum link length that is supported by the QSFP transceiver while operating incompliance with the applicable standards using copper cable. The value is in units of 1 meter. Supported link
length is as specified in the SFF 8074i standard. A value of zero means that the transceiver does not support
Copper or that the length information must be determined from the transceiver technology. Further information
about the cable design, equalization, and connectors is usually required to guarantee meeting a particularlength requirement.
6.6.2.13 Device Tech (Address 147)

The technology used in the device is described in Table 36 and Table 37. The top 4 bits of the Device Techbyte describe the device technology used. The lower four bits (bits 7-4) of the Device Tech byte are used todescribe the transmitter technology.
Table 36 — Description of Device Technology

Bits
7-4
3
2
1
0

Description of physical device
Transmitter technology
0: No wavelength control
1: Active wavelength control
0: Uncooled transmitter device
1: Cooled transmitter
0: PIN detector
1: APD detector
0: Transmitter not tuneable
1: Transmitter tuneable

Table 37 — Transmitter Technology

Value
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1111b-1001b

QSFP Public Specification

Description of physical device
850 nm VCSEL
1310 nm VCSEL
1550 nm VCSEL
1310 nm FP
1310 nm DFB
1550 nm DFB
1310 nm EML
1550 nm EML
Copper or others
Reserved

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6.6.2.14 Vendor Name (Address 148-163)

The vendor name is a 16 character field that contains ASCII characters, left-aligned and padded on the rightwith ASCII spaces (20h). The vendor name shall be the full name of the corporation, a commonly acceptedabbreviation of the name of the corporation, the SCSI company code for the corporation, or the stock
exchange code for the corporation. At least one of the vendor name or the vendor OUI fields shall containvalid serial data.
6.6.2.15 Extended Transceiver Codes (Address 164)

The Extended Transceiver Codes define the electronic or optical interfaces for InfiniBand that are supportedby the QSFP transceiver as shown in Table 38.
Table 38 — Extended Transceiver Code Values
Address

Bit

InfiniBand Compliance Codes
164
7-6
164
5
164
4
164
3
164
2
164
1
164
0

Description of Transceiver Data
Reserved
IB 4X 850 nm
IB 4X Copper Active
IB 4X Copper Passive
QDR Speed (10 Gb/s)
DDR Speed (5.0 Gb/s)
SDR Speed (2.5 Gbps)

6.6.2.16 Vendor OUI (Address 165-167)

The vendor organizationally unique identifier field (vendor OUI) is a 3-byte field that contains the IEEE
Company Identifier for the vendor. A value of all zero in the 3-byte field indicates that the Vendor OUI isunspecified.
6.6.2.17 Vendor PN (Address 168-183)

The vendor part number (vendor PN) is a 16-byte field that contains ASCII characters, left aligned and paddedon the right with ASCII spaces (20h), defining the vendor part number or product name. A value of all zero in
the 16-byte field indicates that the vendor PN is unspecified.
6.6.2.18 Vendor Rev (Address 184-185)

The vendor revision number (vendor rev) is a 2-byte field that contains ASCII characters, left aligned andpadded on the right with ASCII spaces (20h), defining the vendor’s product revision number. A value of all
zero in the field indicates that the vendor Rev is unspecified.
6.6.2.19 Wavelength (Address 186-187)

Nominal transmitter output wavelength at room temperature. 16 bit value with byte 186 as high order byte andbyte 187 as low order byte. The laser wavelength is equal to the 16 bit integer value divided by 20 in nm (unitsof 0.05nm). This resolution should be adequate to cover all relevant wavelengths yet provide enoughresolution for all expected DWDM applications. For accurate representation of controlled wavelength
applications, this value should represent the center of the guaranteed wavelength range.
6.6.2.20 Wavelength Tolerance (Address 188-189)

The guaranteed +/- range of transmitter output wavelength under all normal operating conditions. 16 bit value
with byte 188 as high order byte and byte 189 as low order byte. The laser wavelength is equal to the 16 bit
integer value divided by 200 in nm (units of 0.005nm). Thus, the following two examples:
Example 1:
10GBASE-LR Wavelength Range = 1260 to 1355 nm
Nominal Wavelength in bytes 186 - 187 = 1307.5 nm.
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Represented as INT(1307.5 nm * 20) = 26150 = 6626h
Wavelength Tolerance in bytes 188 - 189 = 47.5nm.
Represented as INT(47.5 nm * 200) = 9500 = 251Ch
Example 2:
ITU-T Grid Wavelength = 1534.25 nm (195.4 THz) with 0.236 nm ( 30 GHz) Tolerance
Nominal Wavelength in bytes 186 - 187 = 1534.25 nm.
Represented as INT(1534.25nm * 20) = 30685 = 77DDh
Wavelength Tolerance in bytes 188 - 189 = 0.236 nm.
Represented as INT(0.236 nm * 200) = 47 = 002Fh
6.6.2.21 Max Case Temp (Address 190)

Allows specification of a maximum case temperature other than the QSFP standard of 70C. Maximum casetemperature is an 8-bit value in Degrees C.
6.6.2.22 CC_BASE (Address 191)

The check code is a one byte code that can be used to verify that the first 64 bytes of serial information in the
QSFP transceiver is valid. The check code shall be the low order 8 bits of the sum of the contents of all thebytes from byte 128 to byte 190, inclusive.
6.6.2.23 Options (Address 192-195)

The bits in the option field shall specify the options implemented in the QSFP transceiver as described inTable 39.
Table 39 — Option Values
Address
192-193
194
194
194
194
194
195
195

bit
7-0
7-4
3
2
1
0
7
6

Description of option
Reserved
Reserved
Rx_Squelch Disable implemented, coded 1 if implemented, else 0
Rx_Output Disable capable: coded 1 if implemented, else 0.
Tx Squelch Disable implemented: coded 1 if implemented, else 0
Tx Squelch implemented: coded 1 if implemented, else 0
Memory page 02 provided: coded 1 if implemented, else 0.
Memory page 01 provided: coded 1 if implemented, else 0.

195
195
195

5
4
3

RATE_SELECT is implemented. If the bit is set to 1 then active control of the rate select bitsin the upper memory table is required to change rates. If the bit is set to 0, no control of therate select bits in the upper memory table is required. In all cases, compliance with multiple
rate standards should be determined by Transceiver Codes in Bytes 132, 133, 134 and 135
of Page 00h.
TX_DISABLE is implemented and disables the serial output.
TX_FAULT signal implemented, coded 1 if implemented, else 0

195
195
195

2
1
0

Tx Squelch implemented to reduce OMA coded 0,implemented to reduce Pave coded 1.
Loss of Signal implemented, coded 1 if implemented, else 0
Reserved

6.6.2.24 Vendor SN (Address 196-211)

The vendor serial number (vendor SN) is a 16-character field that contains ASCII characters, left aligned andpadded on the right with ASCII spaces (20h), defining the vendor’s serial number for the QSFP transceiver. A
value of all zero in the 16-byte field indicates that the vendor SN is unspecified.
6.6.2.25 Date Code (Address 212-219)

The date code is an 8-byte field that contains the vendor’s date code in ASCII characters. The date code is
mandatory. The date code shall be in the format specified by Table 40.

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Table 40 — Date Codes

Address
212-213214-215
216-217
218-219

Description of field
ASCII code, two low order digits of year. (00 = 2000).
ASCII code, digits of month (01 = Jan through 12 = Dec)
ASCII code, day of month (01 - 31)
ASCII code, vendor specific lot code, may be blank

6.6.2.26 Diagnostic Monitoring Type (Address 220)

“Diagnostic Monitoring Type” is a 1-byte field with 8 single bit indicators describing how diagnostic monitoringis implemented in the particular QSFP transceiver. Bit indicators are shown in Table 41.
Digital Diagnostic Monitors monitor received power, bias current, supply voltage and temperature.
Additionally, alarm and warning thresholds must be written as specified in this document. Auxiliary monitoring
fields are optional extensions to Digital Diagnostics.
All digital monitoring values must be internally calibrated and reported in the units defined in this document.
Bit 3 indicates whether the received power measurement represents average input optical power or OMA. If
the bit is set, average power is monitored. If not, OMA is monitored.
Table 41 — Diagnostic Monitoring Type

Address
220
220
220
220
220

Bits
7-5
4
3
2
1-0

Description
Reserved
Module Respond to FEC BER, 0 = No BER Support, 1=BER Support
Received power measurement type, 0 = OMA, 1 = Average Power
Reserved
Reserved

6.6.2.27 Enhanced Options (Address 221)

The format of the Enhanced Options byte are shown in Table 42. The use of the Enhanced Options field isdefined in Clause 6.6.1.7. The state where the Rate Select declaration bits both have a value of 1 is reserved
and should not be used.
Table 42 — Enhanced Options (byte 221))
Address
221
221

Bit
7-4
3

221

2

221

1-0

Description
Reserved
Rate Selection Declaration: When this declaration bit is 0, the module does not support rate
selection. When this declaration bit is 1, rate selection is implemented using Extended Rate
Selection. See 6.6.1.7.2.
Application Select Table Declaration. When this declaration bit is 1, the module supports rate
selection using application select table mechanism. When this declaration bit is 0, the module
does not support application select and page 01 does not exist.
reserved

6.6.2.28 CC_EXT (Address 223)

The check code is a one-byte code that can be used to verify that the first 32 bytes of extended serial
information in the QSFP transceiver is valid. The check code shall be the low order 8 bits of the sum of thecontents of all the bytes from byte 192 to byte 222, inclusive.
6.6.2.29 Vendor Specific (Address 224-255)

This area may contain vendor specific information, which can be read from the QSFP Transceiver. The data isread only. Bytes 224-255 of Page 00h may be used for Vendor Specific ID functions.

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6.6.3 Upper Memory Map Page 01h

The format of Page 01h is defined in Table 43.
Table 43 — Application Select Table (Page 01)
Byte
128

Bit range
7-0

Name of Field
CC_APPS

129
129

7,6
5-0

Reserved
AST Table Length, TL

130, 131

7-0, 7-0

Application code 0…

Other table entries

130+2*TL, 7-0, 7-0
131+2*TLApplication code TL

Description
Check code for the AST; the check code shall be thelow order 8 bits of the sum of the contents of all thebytes from byte 129 to byte 255, inclusive.
A 6-bit binary number, TL, specifies how many
application table entries are defined in bytes 130-255
addresses. TL is valid between 0 (1 entry) and 62 (fora total of 63 entries).
Definition of first application supported

Definition of last application supported

Table 44 — Application Code Structure
7
6
reserved

Low order Byte
5
4
3
2
1
category0

76High order Byte
5432
variant

1

0

6.6.4 User Writable and Vendor Specific Memory

Page 02 is optionally provided as user writable EEPROM. The host system may read or write this memory forany purpose. If bit 4 of Page 00 byte 129 is set, however, the first 10 bytes of Table 02h, bytes128-137 will be
used to store the CLEI code for the module.

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6.6.5 Upper Memory Page 03h

The upper memory map page 03h contains module thresholds, channel thresholds and masks, and optional
channel controls. These are shown in Table 45 and described in detail in Clause 6.6.1, Clause 6.6.1.6 andClause 6.6.1.4.
Table 45 — Upper Memory Map Page 03h
Byte Address
128-175
176-223224-225
226-239240-241242-253
254-255

Description
Module Thresholds (48 Bytes)
Channel Thresholds (48 Bytes)
Reserved (2 Bytes)
Vendor Specific Channel Controls (14 Bytes)
Optional Channel Controls (2 Bytes)
Channel Monitor Masks (12 Bytes)
Reserved (2 Bytes)

Type
Read-Only
Read-Only
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write

6.6.5.1 Module and Channel Thresholds

Each monitor value has a corresponding high alarm, low alarm, high warning and low warning threshold.
These factory-preset values allow the user to determine when a particular value is outside of “normal” limits asdetermined by the transceiver manufacturer. It is assumed that these values will vary with different
technologies and different implementations. These values are stored in read-only memory in bytes 128-223
of the upper memory page 03h as shown in Table 46.
The values reported in the Alarm and Warning Thresholds area may be typical values at some chosen
nominal operating conditions and may be temperature compensated or otherwise adjusted when setting
warning and/or alarm flags. Any threshold compensation or adjustment is vendor specific and optional. Referto the vendor’s data sheet for use of alarm and warning thresholds.
Table 46 — Module and Channel Thresholds
Address
128-129130-131132-133
134-135
136-143
144-145
146-147
148-149
150-151
152-175
176-177
178-179180-181182-183
184-185
186-187
188-189
190-191
192-199200-207
208-215
216-223# Bytes
2
2
2
2
8
2
2
2
2
14
2
2
2
2
2
2
2
2
8
8
8
8

Name
Temp High Alarm
Temp Low Alarm
Temp High Warning
Temp Low Warning
Reserved
Vcc High Alarm
Vcc Low Alarm
Vcc High Warning
Vcc Low Warning
Reserved
RX Power High AlarmRX Power Low AlarmRX Power High Warning
RX Power Low Warning
TX Bias High Alarm
TX Bias Low Alarm
TX Bias High Warning
TX Bias Low Warning
Reserved
Reserved
Reserved
Reserved

QSFP Public Specification

Description
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
Reserved thresholds for channel parameter set 3
Reserved thresholds for channel parameter set 4
Reserved thresholds for channel parameter set 5
Reserved thresholds for channel parameter set 6

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6.6.5.2 Optional Channel Controls

Upper Memory Page Control Bits are defined in Table 47.
Table 47 — Optional Channel Controls
Byte
240

241

Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0

Name
Rx4_SQ_Disable
Rx3_SQ_Disable
Rx2_SQ_Disable
Rx1_SQ_Disable
Tx4_SQ_Disable
Tx3_SQ_Disable
Tx2_SQ_Disable
Tx1_SQ_Disable
Rx4_Output_Disable
Rx3_Output_Disable
Rx2_Output_Disable
Rx1_Output_Disable
Reserved
Reserved
Reserved
Reserved

Description
Rx Squelch Disable, channel 4 (optional)
Rx Squelch Disable, channel 3 (optional)
Rx Squelch Disable, channel 2 (optional)
Rx Squelch Disable, channel 1 (optional)
Tx Squelch Disable, channel 4 (optional)
Tx Squelch Disable, channel 3 (optional)
Tx Squelch Disable, channel 2 (optional)
Tx Squelch Disable, channel 1 (optional)
Rx Output Disable, channel 4 (optional)
Rx Output Disable, channel 3 (optional)
Rx Output Disable, channel 2 (optional)
Rx Output Disable, channel 1 (optional)

Squelch and output control functionality is optional; if implemented, squelch and output disable is controlled
for each channel using bytes 240 and 241 of page 03h. Squelch is normally operational as described in
Clause 3.1.3, High Speed Electrical Specification. Writing a “1” in the Squelch Disable register (byte 240,
page 03h) disables the squelch for the associated channel. Writing a “1” in the Output Disable register (byte241, page 03h) squelches the output of the associated channel. When a “1” is written in both registers for achannel, the associated output is disabled. The registers read all “0”s upon power-up.

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6.6.5.3 Channel Monitor Masks

The Masking Bits for the Channel Monitor Functions are defined in Table 48.
Table 48 — Channel Monitor Masks

Byte
242

243

244

245

246-247248-249
250-251
252-253

Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
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6
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2
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All
All
All
All

Name
M-Rx1 Power High Alarm
M-Rx1 Power Low Alarm
M-Rx1 Power High Warning
M-Rx1 Power Low Warning
M-Rx2 Power High Alarm
M-Rx2 Power Low Alarm
M-Rx2 Power High Warning
M-Rx2 Power Low Warning
M-Rx3 Power High Alarm
M-Rx3 Power Low Alarm
M-Rx3 Power High Warning
M-Rx3 Power Low Warning
M-Rx4 Power High Alarm
M-Rx4 Power Low Alarm
M-Rx4 Power High Warning
M-Rx4 Power Low Warning
M-Tx1 Bias High Alarm
M-Tx1 Bias Low Alarm
M-Tx1 Bias High Warning
M-Tx1 Bias Low Warning
M-Tx2 Bias High Alarm
M-Tx2 Bias Low Alarm
M-Tx2 Bias High Warning
M-Tx2 Bias Low Warning
M-Tx3 Bias High Alarm
M-Tx3 Bias Low Alarm
M-Tx3 Bias High Warning
M-Tx3 Bias Low Warning
M-Tx4 Bias High Alarm
M-Tx4 Bias Low Alarm
M-Tx4 Bias High Warning
M-Tx4 Bias Low Warning
Reserved
Reserved
Reserved
Reserved

QSFP Public Specification

Description
Masking bit for high RX Power alarm, channel 1
Masking bit for low RX Power alarm, channel 1
Masking bit for high RX Power warning, channel 1
Masking bit for low RX Power warning, channel 1
Masking bit for high RX Power alarm, channel 2
Masking bit for low RX Power alarm, channel 2
Masking bit for high RX Power warning, channel 2
Masking bit for low RX Power warning, channel 2
Masking bit for high RX Power alarm, channel 3
Masking bit for low RX Power alarm, channel 3
Masking bit for high RX Power warning, channel 3
Masking bit for low RX Power warning, channel 3
Masking bit for high RX Power alarm, channel 4
Masking bit for low RX Power alarm, channel 4
Masking bit for high RX Power warning, channel 4
Masking bit for low RX Power warning, channel 4
Masking bit for high TX Bias alarm, channel 1
Masking bit for low TX Bias alarm, channel 1
Masking bit for high TX Bias warning, channel 1
Masking bit for low TX Bias warning, channel 1
Masking bit for high TX Bias alarm, channel 2
Masking bit for low TX Bias alarm, channel 2
Masking bit for high TX Bias warning, channel 2
Masking bit for low TX Bias warning, channel 2
Masking bit for high TX Bias alarm, channel 3
Masking bit for low TX Bias alarm, channel 3
Masking bit for high TX Bias warning, channel 3
Masking bit for low TX Bias warning, channel 3
Masking bit for high TX Bias alarm, channel 4
Masking bit for low TX Bias alarm, channel 4
Masking bit for high TX Bias warning, channel 4
Masking bit for low TX Bias warning, channel 4
Reserved channel monitor masks, set 3
Reserved channel monitor masks, set 4
Reserved channel monitor masks, set 5
Reserved channel monitor masks, set 671