NOIP1SN5000APYTHON 5.0/2.0 MegaPixels
Global Shutter CMOS
Image Sensors
Featureswww.onsemi.com• Data Output Options♦ P1−SN/SE/FN: 8 LVDS Data Channels♦ P3−SN/SE: 4 LVDS Data Channels• Size Options♦ PYTHON 2000: 1920 x 1200 Active Pixels, 2/3” Optical Format♦ PYTHON 5000: 2592 x 2048 Active Pixels, 1” Optical Format• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with

In-pixel CDS• Monochrome (SN), Color (SE) and NIR (FN)
• Zero Row Overhead Time Mode Enabling Higher Frame Rate
• Frame Rate at Full Resolution, 8 LVDS Data Channels(P1−SN/SE/FN only)♦ 100/85 frames per second @ 5 MP (Zero ROT/Non−Zero ROT)
♦ 230/180 frames per second @ 2 MP (Zero ROT/Non−Zero ROT)
Figure 1. PYTHON 5000
♦ 255/200 frames per second @ Full HD (Zero ROT/Non−Zero ROT)
• On-chip 10-bit Analog-to-Digital Converter (ADC)
Description• Eight/Four/Two/One LVDS High Speed Serial Outputs
The PYTHON 2000 and PYTHON 5000 image sensors• Random Programmable Region of Interest (ROI)
utilizehigh sensitivity 4.8 mm x 4.8 mm pixels that support
Readout
low noise “pipelined” and “triggered” global shutter readout• Serial Peripheral Interface (SPI)
modes. The sensors support correlated double sampling• Automatic Exposure Control (AEC)(CDS) readout, reducing noise and increasing dynamic• Phase Locked Loop (PLL)
range.
The sensor has on-chip programmable gain amplifiers and• High Dynamic Range (HDR) Modes Possible
10-bit A/D converters. The integration time and gain
• Dual Power Supply (3.3 V and 1.8 V)parameters can be reconfigured without any visible image• −40°C to +85°C Operational Temperature Range
artifact. Optionally the on-chip automatic exposure control• 84-pin LCC and 128−pad LGA
loop (AEC) controls these parameters dynamically. The• Power Dissipation
image’s black level is either calibrated automatically or can♦ 1.45 W (P1−SN/SE/FN, 8 LVDS, NZROT)
be adjusted by adding a user programmable offset.
♦ 915 mW (P1−SN/SE/FN, P3−SN/SE, 4 LVDS,
A high level of programmability using a four wire serial
NZROT)
peripheral interface enables the user to read out specific♦ 520 mW (P1−SN/SE/FN, P3−SN/SE, 2 LVDS,
regions of interest. Up to sixteen regions can be
NZROT)
programmed, achieving even higher frame rates.
♦ 370 mW (P1−SN/SE/FN, P3−SN/SE, 1 LVDS,
The image data interface of the P1−SN/SE/FN devices
NZROT)
consists of eight LVDS lanes, facilitating frame rates up to• These Devices are Pb−Free and are RoHS Compliant
100 frames per second in Zero ROT mode for the PYTHON
5000. Each channel runs at 720 Mbps. A separate
Applications
synchronization channel containing payload information is• Machine Vision
provided to facilitate the image reconstruction at the• Motion Monitoring
receiving end.
• Security
The P3−SN/SE devices are the same as the P1−SN/SE/FN• Intelligent Traffic Systems (ITS)
but with only four of the eight LVDS data channels enabled,facilitating frame rates of 45 frames per second in Non Zero
ROT (NZROT) for the PYTHON 5000.
© Semiconductor Components Industries, LLC, 2016

November, 2016 − Rev. 3

1

Publication Order Number:
NOIP1SN5000A/D

NOIP1SN5000A

ORDERING INFORMATIONPart Number

Description

Package

PYTHON 5000
84−pin LCC

NOIP1SN5000A−QDI

5 MegaPixel, Monochrome

NOIP1SE5000A−QDI

5 MegaPixel, Bayer ColorNOIP1FN5000A−QDI

5 MegaPixel, Monochrome with enhanced NIR

NOIP1SN5000A−QTI

5 MegaPixel, Monochrome, Protective Film

NOIP1SE5000A−QTI

5 MegaPixel, Bayer Color, Protective Film

NOIP1FN5000A−QTI

5 MegaPixel, Monochrome with enhanced NIR, Protective Film

NOIP3SN5000A−QDI

5 MegaPixel, 4 LVDS Outputs, Monochrome

NOIP3SE5000A−QDI

5 MegaPixel, 4 LVDS Outputs, Bayer Color

NOIP3SN5000A−QTI

5 MegaPixel, 4 LVDS Outputs, Monochrome, Protective Film

NOIP3SE5000A−QTI

5 MegaPixel, 4 LVDS Outputs, Bayer Color, Protective Film

NOIP1SN5000A−LTI

5 MegaPixel, Monochrome, Protective Film

NOIP1SE5000A−LTI

5 MegaPixel, Bayer Color, Protective Film

NOIP1FN5000A−LTI

5 MegaPixel, Monochrome with enhanced NIR, Protective Film

NOIP3SN5000A−LTI

5 MegaPixel, 4 LVDS Outputs, Monochrome, Protective Film

NOIP3SE5000A−LTI

5 MegaPixel, 4 LVDS Outputs, Bayer Color, Protective Film

128−pad LGAPYTHON 2000
84−pin LCC

NOIP1SN2000A−QDI

2 MegaPixel, Monochrome

NOIP1SE2000A−QDI

2 MegaPixel, Bayer ColorNOIP1FN2000A−QDI

2 MegaPixel, Monochrome with enhanced NIR

NOIP1SN2000A−QTI

2 MegaPixel, Monochrome, Protective Film

NOIP1SE2000A−QTI

2 MegaPixel, Bayer Color, Protective Film

NOIP1FN2000A−QTI

2 MegaPixel, Monochrome with enhanced NIR, Protective Film

NOIP1SN2000A−LTI

2 MegaPixel, Monochrome, Protective Film

NOIP1SE2000A−LTI

2 MegaPixel, Bayer Color, Protective Film

NOIP1FN2000A−LTI

2 MegaPixel, Monochrome with enhanced NIR, Protective Film

128−pad LGA

The P1−SN/SE/FN base part references the mono, color and NIR enhanced versions of the 8 LVDS interface; the P3−SN/SE
base part references the mono and color version of the 4 LVDS interface. More details on the part number coding can be foundat http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF
Package Mark for LCC−84 Pin Package

Line 1: NOIPyxx RRRRA where y is either “1” for 8 LVDS Outputs, “3” for 4 LVDS Outputs.
where xx denotes mono micro lens (SN) or color micro lens (SE) or NIR micro lens (FN)RRRR is the resolution (5000), (2000)
Line 2: −QDI (LCC−84 without protective film), −QTI (LCC−84 with protective film)
Line 3: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date code
Package Mark for LGA−128 Pad Package

Package Side 1: NOIPyxxRRRRA−LTI where y is either “1” for 8 LVDS Outputs, “3” for 4 LVDS Outputs.
where xx denotes mono micro lens (SN) or color micro lens (SE)RRRR is the resolution (5000), (2000)−LTI (LGA−128 with protective film)
Package Side 2: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date codewww.onsemi.com
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NOIP1SN5000A
SPECIFICATIONSKey Specifications
Table 2. NOMINAL ELECTRO−OPTICAL
SPECIFICATIONS

Table 1. GENERAL SPECIFICATIONS (Note 1)
Parameter

Specification

Pixel TypeIn−pixel CDS. Global shutter pixel architecture

Shutter Type

Pipelined and triggered global shutter

Frame Rate
Zero ROT/
Non−Zero ROT
Mode

P1−SN/SE/FN:
PYTHON 2000: 230/180 fps
PYTHON 5000: 100/85 fps
P3−SN/SE: NA/45 fps

Master Clock

P1−SN/SE/FN, P3−SN/SE:
72 MHz when PLL is used,
360 MHz (10-bit) / 288 MHz (8-bit) when
PLL is not used

Windowing

Parameter

16 Randomly programmable windows.
Normal, sub-sampled and binned readout
modes

Specification

Active Pixels

PYTHON 5000: 2592 (H) x 2048 (V)PYTHON 2000: 1984 (H) x 1264 (V)Pixel Size

4.8 mm x 4.8 mm

Conversion Gain

0.096 LSB10/e-, 140 mV/e-

Temporal Noise< 10.7 e- (Non−Zero ROT, 1x gain)< 9.4 e- (Non−Zero ROT, 2x gain)

Responsivity at 550 nm

7.5 V/lux.s

Parasitic Light
Sensitivity (PLS)<1/5000

Full Well Charge

10000 e-ADC Resolution(Note 1)10-bit, 8-bit

Quantum Efficiency
at 550 nm

57%

LVDS Outputs

P1−SN/SE/FN: 8/4/2/1 data + sync + clock
P3−SN/SE: 4/2/1 data + sync + clock

Pixel FPN

< 1.55 LSB10 (Non−Zero ROT)
< 1.35 (Zero−ROT)

Data Rate

P1−SN/SE/FN:
8 x 720 Mbps (10-bit) /8 x 576 Mbps (8-bit)
P3−SN/SE/FN:
4 x 720 Mbps (10−bit)

PRNU< 10 LSB10 on half scale response of
525 LSB10

MTF

66% @ 535 nm − X-dir & Y-dir

Pixel Storage Node Leakage(PSNL) @ 20°C
(t_int = 30 ms)

300 LSB10/s, 2800 e-/s

Dark Signal @ 20°C

9.3 e-/s, 1.0 LSB10/s

Dark Current Doubling
Temperature

5.2°C

Dynamic Range

60 dB

Signal to Noise Ratio(SNR max)

40 dB

Power Dissipation(10−bit mode)

Package Type

P1−SN/SE/FN:
1.45 W (8 data channels)
P1−SN/SE/FN, P3−SN/SE:
915 mW (4 data channels)
P1−SN/SE/FN, P3−SN/SE:
520 mW (2 data channels)
P1−SN/SE/FN, P3−SN/SE:
370 mW (1 data channel)
84-pin LCC, 128-pad LGA

Table 3. RECOMMENDED OPERATING RATINGS (Note 2)
SymbolTJ

Description
Operating junction temperature range

Min

Max

Unit

−40

85

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

Table 4. ABSOLUTE MAXIMUM RATINGS (Notes 3 and 4)
Min

Max

Unit

ABS (1.8 V supply group)

Symbol

ABS rating for 1.8 V supply group

Parameter

–0.5

2.2

V

ABS (3.3 V supply group)

ABS rating for 3.3 V supply group

–0.5

4.3

V

TS

ABS storage temperature range

−40

+150

°C

85

%RH

ABS storage humidity range at 85°C
Electrostatic discharge (ESD)

LU

Human Body Model (HBM): JS−001−2012

2000

Charged Device Model (CDM): EIA/JESD22−C101, Class C1

500

Latch−up: JESD−78

100

V

mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The ADC is 11−bit, down−scaled to 10−bit. The PYTHON uses a larger word−length internally to provide 10−bit on the output.
2. Operating ratings are conditions in which operation of the device is intended to be functional.
3. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
4. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and canabsorb moisture if the sensor is placed in a high % RH environment.

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NOIP1SN5000A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8 and 9)
Parameter

Description

Min

Typ

Max

Units

3.3

3.4

V

Power Supply Parameters − P1 − SN/SE/FN (ZROT)(Note: All ground pins (gnd_18, gnd_33 and gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33

Supply voltage, 3.3 V

Idd_33Current consumption 3.3 V supply

vdd_18Supply voltage, 1.8 V

Idd_18Current consumption 1.8 V supply

vdd_pix

Supply voltage, pixel

Idd_pix

Current consumption pixel supply

10

Ptot

Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V

1.45

Pstby_lp

Power consumption in low power standby mode

Popt

Power consumption at lower pixel rates

3.2

355
1.8

1.7

mA
1.9

140
3.3

3.25

V
mA

3.35

V
mA
W

50

mW

Configurable

Power Supply Parameters − P3 − SN/SE (NZROT)(Note: All ground pins (gnd_18, gnd_33 and gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33

Supply voltage, 3.3 V

Idd_33Current consumption 3.3 V supply (4/2/1 LVDS)

vdd_18Supply voltage, 1.8 V

Idd_18Current consumption 1.8 V supply (4/2/1 LVDS)

vdd_pix

Supply voltage, pixel

Idd_pix

Current consumption pixel supply (4/2/1 LVDS)

5

Ptot

Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
4 LVDS, NZROT
2 LVDS, NZROT
1 LVDS, NZROT

915
520
370

Pstby_lp

Power consumption in low power standby mode

Popt

Power consumption at lower pixel rates

3.2

3.3

3.4

215
1.7

1.8

1.9

105
3.25

3.3

V
mA
V
mA

3.35

V
mA
mW

50

mW

Configurable

I/O − P1−SN/SE/FN, P3−SN/SE (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed
fserdata

Data rate on data channels
DDR signaling − 4 data channels, 1 synchronization channel

720

Mbps

fserclock

Clock rate of output clock
Clock output for mesochronous signaling

360

MHz

Vicm

LVDS input common mode level

1.8

V

Tccsk

Channel to channel skew (Training pattern should be used to correct
per channel skew)

50

ps

0.3

1.25

Clock Specifications − P1−SN/SE/FN, P3−SN/SE
fin

Input clock rate when PLL used

72

MHz

fin

Input clock when LVDS input used

360

MHz

tidc

Input clock duty cycle when PLL used

55

%

tj

Input clock jitter

20

ps

fspi

SPI clock rate when PLL used

10

MHz

ratspi (=fin/fspi)

10−bit (8 LVDS channels), PLL used − P1−SN/SE/FN only

6

10−bit (4 LVDS channels), PLL used1210−bit (2 LVDS channels), PLL used24

10−bit (1 LVDS channel), PLL used

48

10−bit (8 LVDS channels), LVDS input used30

10−bit (4 LVDS channels), LVDS input used

60

45

50

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it isrecommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this highimpedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON5000 available at CISP extranet for detailed acceptance criteria specifications.
9. For power supply management recommendations, please refer to Application Note AND9158.

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NOIP1SN5000A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8 and 9)
Parameter

Description

Min

Typ

Max

Units

Clock Specifications − P1−SN/SE/FN, P3−SN/SE
ratspi (=fin/fspi)

10−bit (2 LVDS channels), LVDS input used120

10−bit (1 LVDS channel), LVDS input used240

8−bit (8 LVDS channels), PLL used68−bit (4 LVDS channels), PLL used128−bit (2 LVDS channels), PLL used24

8−bit (1 LVDS channel), PLL used

48

8−bit (8 LVDS channels), LVDS input used24

8−bit (4 LVDS channels), LVDS input used

48

8−bit (2 LVDS channels), LVDS input used

96

8−bit (1 LVDS channel), LVDS input used

192

Frame Specifications − P1−SN/SE/FN
Maximum
Non−Zero ROT

Zero ROT

Units

fps_roi1

Xres x Yres = 2592 x 2048

85

100

fps

fps_roi2

Xres x Yres = 2048 x 2048

100

130

fps

fps_roi3

Xres x Yres = 1920 x 1200

180

230

fps

fps_roi4

Xres x Yres = 1920 x 1080

200

255

fps

fps_roi5

Xres x Yres = 1600 x 1200

205

275

fps

fps_roi6

Xres x Yres = 1024 x 1024

395

480

fps

fps_roi7

Xres x Yres = 1280 x 720

390

550

fps

fps_roi8

Xres x Yres = 800 x 600

620

985

fps

fps_roi9

Xres x Yres = 640 x 480

855

1450

fps

fps_roi10

Xres x Yres = 512 x 512

890

1555

fps

fps_roi11

Xres x Yres = 256 x 256

2065

2830

fps

fps_roi12

Xres x Yres = 544 x 20

7980

10345

fps

fpix

Pixel rate (8 channels at 72 Mpix/s)

576

576

Mpix/sFrame Specifications − P3−SN/SE
Maximum (Non−Zero ROT)
4 LVDS

2 LVDS

1 LVDSUnits

fps_roi1

Xres x Yres = 2592 x 2048

45

25

10

fps

fps_roi2

Xres x Yres = 2048 x 2048

55

30

15

fps

fps_roi3

Xres x Yres = 1920 x 1200

100

55

25

fps

fps_roi4

Xres x Yres = 1920 x 1080

110

60

30

fps

fps_roi5

Xres x Yres = 1600 x 1200

115

60

30

fps

fps_roi6

Xres x Yres = 1024 x 1024

195

105

55

fps

fps_roi7

Xres x Yres = 1280 x 720

230

125

65

fps

fps_roi8

Xres x Yres = 800 x 600

385

220

115

fps

fps_roi9

Xres x Yres = 640 x 480

550

320

175

fps

fps_roi10

Xres x Yres = 512 x 512

590

350

190

fps

fps_roi11

Xres x Yres = 256 x 256

1590

990

580

fps

fps_roi12

Xres x Yres = 544 x 20

6260

4340

2690

fps

fpix

Pixel rate (8 channels at 72 Mpix/s)

288

144

72

Mpix/s

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it isrecommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this highimpedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON5000 available at CISP extranet for detailed acceptance criteria specifications.
9. For power supply management recommendations, please refer to Application Note AND9158.

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NOIP1SN5000A
Color Filter Array

The PYTHON color sensors are processed with a Bayer RGB color pattern as shown in Figure 2. Pixel (0,0) has a red filter
situated to the bottom left.

Y

Gb
Gr

X

pixel (0;0)

Figure 2. Color Filter Array for the Pixel Array

Quantum Efficiency

Figure 3. Quantum Efficiency Curves

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NOIP1SN5000A
Ray Angle and Microlens Array Information

versus photodiode position will cause a tilted angle of peak
photoresponse, here denoted Chief Ray Angle (CRA).
Microlenses and photodiodes are aligned with 0 shift andCRA in the center of the array, while the shift and CRA
increases radially towards its edges, as illustrated by
Figure 6.
The purpose of the shifted microlenses is to improve theuniformity of photoresponse when camera lenses witha finite exit pupil distance are used. In the standard versionof Python 5000, the CRA varies nearly linearly with distancefrom the center as illustrated in Figure 7, with a corner CRA
of approximately 5.4 degrees. This edge CRA is matchinga lens with exit pupil distance of ~80 mm.

Normalized Response

An array of microlenses is placed over the CMOS pixel
array in order to improve the absolute responsivity of thephotodiodes. The combined microlens array and pixel arrayhas two important properties:
Angular Dependency of Photoresponse of a Pixel
The photoresponse of a pixel with microlens in the centerof the array to a fixed optical power with varied incidence
angle is as plotted in Figure 4, where definitions of angles
fx and fy are as described by Figure 5.
Microlens Shift across Array and CRA
The microlens array is fabricated with a slightly smaller
pitch than the array of photodiodes. This difference in pitch
creates a varying degree of shift of a pixel’s microlens withregards to its photodiode. A shift in microlens position

Incidence Angle fx, fy[degrees deviation from normal]
Note that the Photoresponse Peaks near Normal Incidence for Center Pixels

Figure 4. Center Pixel Photoresponse to a Fixed Optical Power with Incidence Angle Varied along fx and fy

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NOIP1SN5000A

Figure 5. Definition of Angles Used in Figure 4

Center Pixel(aligned)

Edge Pixel(with shift)

The center axes of the microlens and the photodiode coincide for the center pixels. For the edge pixels,
there is a shift between the axes of the microlens and the photodiode causing a Peak Response Incidence
Angle (CRA) that deviates from the normal of the pixel array.

Figure 6. Principle of Microlens Shift

6

CRA [degrees]

5
4
3
2
1
0
0

2

4

6

Distance from center [mm]Figure 7. Variation of Peak Responsivity Angle (CRA)
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88

NOIP1SN5000AOVERVIEW
Figures 8 gives an overview of the major functional blocks of the PYTHON sensor.
Image Core

Row Dec od er

Image Core Bias

Pixel Array

Column Structure

Automatic
Exposure
Control(AEC)

16 Analog channels
Analog Front End (AFE)
16 x 10 bit
Digital channels

Control &Registers
Clock
Distribution

Data Formatting
8 x 10 bit
Digital channels

Re set

LVDS ClockInput

SPI Interface

CMOS Clock
Input

Serializers & LVDS Interface

LVDS
Receiver
External Trigger s

PLL

8/4/2/1 LVDS Channels
1 LVDS Sync Channel
1 LVDS Clock Channel

Figure 8. Block Diagram
Image Core

LVDS Clock Receiver

The image core consists of:• Pixel Array• Address Decoders and Row Drivers• Pixel Biasing
The PYTHON 5000 pixel array contains 2592 (H) x
2048 (V) readable pixels with a pixel pitch of 4.8 mm.
The PYTHON 2000 image array contains 1984 (H) x
1264 (V) readable pixels, inclusive of 32 pixels on each side
to allow for reprocessing or color reconstruction.
The sensors use in−pixel CDS architecture, which makes
it possible to achieve a low noise read out of the pixel arrayin global shutter mode with the function of the row drivers
is to access the image array to reset or read the pixel data. The
row drivers are controlled by the on−chip sequencer and canaccess the pixel array.
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when therow drivers select a pixel line for readout.

The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 360 MHz in 10−bit modeand 288 MHz in 8−bit mode. The clock input needs to beterminated with a 100 W resistor.
All pixels of one image row are stored in the column
sample−and−hold (S/H) stages. These stages store both thereset and integrated signal levels.
The data stored in the column S/H stages is read out
through 16 parallel differential outputs operating at afrequency of 36 MHz. At this stage, the reset signal andintegrated signal values are transferred into an
FPN−corrected differential signal. A programmable gain of
1x, 2x, or 4x can be applied to the signal. The column
multiplexer
also
supports
read−1−skip−1
andread−2−skip−2 mode. Enabling this mode increases theframe rate, with a decrease in resolution.

Phase Locked Loop

Bias Generator

Column Multiplexer

The bias generator generates all required reference
voltages and bias currents used on chip. An external resistorof 47 kW, connected between pin IBIAS_MASTER and
gnd_33, is required for the bias generator to operateproperly.

The PLL accepts a (low speed) clock and generates therequired high speed clock. Optionally this PLL can bebypassed. Typical input clock frequency is 72 MHz.

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NOIP1SN5000A
Analog Front End

clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system−level image reconstruction.

The AFE contains 16 channels, each containing a PGA
and a 10−bit ADC.
For each of the 16 channels, a pipelined 10−bit ADC isused to convert the analog image data into a digital signal,
which is delivered to the data formatting block. A black
calibration loop is implemented to ensure that the black levelis mapped to match the correct ADC input level.

Channel Multiplexer

The P1−SN/SE/FN LVDS channel multiplexer provides
a 8:4, 8:2 and 8:1 feature, in addition to utilizing all 8 output
channels.
The P3−SN/SE LVDS channel multiplexer provides a 4:2
and 4:1 feature, in addition to utilizing all 4 output channels.

Data Formatting

The data block receives data from two ADCs andmultiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passingdata.
A frame synchronization data block transmits
synchronization codes such as frame start, line start, frame
end, and line end indications.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at thereceiving end.

Sequencer

The sequencer:• Controls the image core. Starts and stops integrationand control pixel readout.
• Operates the sensor in master or slave mode.
• Applies the window settings. Organizes readouts so that
only the configured windows are read.
• Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at thecorrect time, without corrupting image data.
• Starts up the sensor correctly when leaving standby
mode.

Serializer and LVDS Interface

The serializer and LVDS interface block receives theformatted (10−bit or 8−bit) data from the data formatting
block. This data is serialized and transmitted by the LVDS
output driver.
In 10−bit mode, the maximum output data rate is
720 Mbps per channel. In 8−bit mode, the maximum output
data rate is 576 Mbps per channel.
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output

Automatic Exposure Control

The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.

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NOIP1SN5000A
OPERATING MODES
Global Shutter Mode

The PYTHON 2000 and PYTHON 5000 operates inpipelined or triggered global shutter modes. In this mode,light integration takes place on all pixels in parallel,
although subsequent readout is sequential. Figure 9 shows
the integration and readout sequence for the global shutter
mode. All pixels are light sensitive at the same period oftime. The whole pixel core is reset simultaneously and after
the integration time all pixel values are sampled together on
the storage node inside each pixel. The pixel core is read outline by line after integration. Note that the integration andreadout can occur in parallel or sequentially. The integration
starts at a certain period, relative to the frame start.

Figure 9. Global Shutter Operation
Pipelined Global Shutter Mode

Overhead Time (ROT). Figure 10 shows the exposure andreadout time line in pipelined global shutter mode.

In pipelined global shutter mode, the integration andreadout are done in parallel. Images are continuously readand integration of frame N is ongoing during readout of theprevious frame N−1. The readout of every frame starts witha Frame Overhead Time (FOT), during which the analog
value on the pixel diode is transferred to the pixel memory
element. After the FOT, the sensor is read out line per line
and the readout of each line is preceded by the Row
ResetN

Integration Time
Handling
Readout
Handling

FOT

Master Mode
The PYTHON 2000 and PYTHON 5000 operate inpipelined or triggered global shuttering modes. In this mode,light, the integration time is set through the register interface
and the sensor integrates and reads out the images
autonomously. The sensor acquires images without any userinteraction.

Exposure Time N

FOT

Readout Frame N-1

Reset
N+1

FOT

Exposure Time N+1

Readout Frame N

FOT

FOT

ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
É
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
É

ROT

Line Readout

Figure 10. Pipelined Shutter Operation in Master Modeof reset and integration starts. The integration continues
until the user or system deasserts the external pin. Upon afalling edge of the trigger input, the image is sampled and thereadout begins. Figure 11 shows the relation between theexternal trigger signal and the exposure/readout timing.

Slave Mode
The slave mode adds more manual control to the sensor.
The integration time registers are ignored in this mode andthe integration time is instead controlled by an external pin.
As soon as the control pin is asserted, the pixel array goes out

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NOIP1SN5000A
External Trigger
Integration Time
Handling
Readout
Handling

Reset
N

FOT

Exposure Time N

FOT

Readout N−1

Reset
N+1

FOT

Exposure T im e N+1

FOT

Readout N

FOT

ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉ

ROT

Line Readout

Figure 11. Pipelined Shutter Operation in Slave Mode

Triggered Global Shutter Mode

The triggered global shutter mode can also be controlled
in a master or in a slave mode.
Master ModeIn this mode, a rising edge on the synchronization pin isused to trigger the start of integration and readout. The
integration time is defined by a register setting. The sensor
autonomously integrates during this predefined time, after
which the FOT starts and the image array is readout
sequentially. A falling edge on the synchronization pin does
not have any impact on the readout or integration andsubsequent frames are started again for each rising edge.
Figure 12 shows the relation between the external trigger
signal and the exposure/readout timing.
If a rising edge is applied on the external trigger before theexposure time and FOT of the previous frame is complete,
it is ignored by the sensor.

In this mode, manual intervention is required to control
both the integration time and the start of readout. After the
integration time, indicated by a user controlled pin, theimage core is read out. After this sequence, the sensor goesto an idle mode until a new user action is detected.
The three main differences with the pipelined global
shutter mode are:
• Upon user action, one single image is read.
• Normally, integration and readout are done
sequentially. However, the user can control the sensor
in such a way that two consecutive batches areoverlapping, that is, having concurrent integration andreadout.
• Integration and readout is under user control through anexternal pin.
This mode requires manual intervention for every frame.
The pixel array is kept in reset state until requested.

No effect on falling edge

External Trigger
Integration Time
Handling

Reset
N

Exposure Time N

FOT

Reset
N+1

Exposure Time N+1

FOT

Readout N

FOT

Register Controlled

Readout
Handling

FOT

Readout N-1

FOT

ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
É

ROT

Line Readout

Figure 12. Triggered Shutter Operation in Master Mode

FOT starts. The analog value on the pixel diode istransferred to the pixel memory element and the image
readout can start. A request for a new frame is started when
the synchronization pin is asserted again.

Slave Mode
Integration time control is identical to the pipelined
shutter slave mode. An external synchronization pin
controls the start of integration. When it is de−asserted, thewww.onsemi.com
12

NOIP1SN5000A
Non−Zero and Zero Row Overhead Time (ROT) Modes

ROT is done while the image row is readout. The actual ROT
can thus be longer, however the perceived ROT will be
shorter (‘overhead’ spent per line is reduced).
The integration time and gain parameters can bereconfigured without any visible image artifact in Normal
ROT mode. Column−level offset corrections are required in
Zero ROT mode. Refer to Column−Level Image Correction
application note in the PYTHON Developer’s Guide
AND9362/D available at the Image Sensor Portal.
This operation mode can be used for two reasons:• Reduced total line time.
• Lower power due to reduced clock−rate.

In pipelined global shutter mode, the integration andreadout are done in parallel. Images are continuously readout and integration of frame N is ongoing during readout ofthe previous frame N−1. The readout of every frame starts
with a Frame Overhead Time (FOT), during which theanalog value of the pixel diode is transferred to the pixel
memory element. After the FOT, the sensor is read out line
by line and the readout of each line is preceded by a Row
Overhead Time (ROT) as shown in Figure 13.
In Reduced/Zero ROT operation mode (refer toFigure 14), the row blanking and kernel readout occur inparallel. This mode is called reduced ROT as a part of the

(

FOT

)

ROT
ys

Readout
ys

ROT
ys+1

Readoutys

ROT
ye

ReadoutyeValid Data

Figure 13. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with
Non−Zero ROT Readout.

(

FOT

)

ROT
ys
(blanked out)

ROT
ys+1
Readoutys

ROT
ye
Readout
ye−1

ROT
dummy
ReadoutyeValid Data

Figure 14. Integration and Readout Sequence of the Sensor operating in Pipelined Global Shutter Mode with
Zero ROT Readout.

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NOIP1SN5000A
SENSOR OPERATION
Flowchart

Figure 15 shows the sensor operation flowchart. The sensor has six different ‘states’. Every state is indicated with the oval
circle. These states are Power off, Low power standby, Standby (1), Standby (2), Idle, Running.
Power OffPower Down
Sequence

Power Up Sequence

Low-Power Standby

Disable Clock Management
Part 1

Poll Lock Indication(only when PLL is enabled)Standby (1)Enable Clock Management - Part 2(First Pass after Hard Reset)

Intermediate Standby

Required Register
UploadStandby (2)Sensor (re-)configuration(optional)

Soft Power-Down
Soft Power-Up

Sensor (re-)configuration(optional)

Idle

Disable Sequencer

Enable Sequencer

Running

Sensor (re-)configuration(optional)

Figure 15. Sensor Operation Flowchart

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14

Assertion of reset_n Pin

Enable Clock Management - Part 2(Not First Pass after Hard Reset)

Disable Clock Management
Part 2

Enable Clock Management - Part 1

NOIP1SN5000A
Sensor Statesclock input

Low Power Standby

In low power standby state, all power supplies are on, butinternally every block is disabled. No internal clock is
running (PLL / LVDS clock receiver is disabled).
All register settings are set to their default values (seeTable 37).
Only a subset of the SPI registers is active for read/write
in order to be able to configure clock settings and leave thelow power standby state. The only SPI registers that should
be touched are the ones required for the ‘Enable ClockManagement’ action described in Enable ClockManagement − Part 1 on page 16

reset_nvdd_18vdd_33

vdd_pix

SPI Upload> 10us> 10us> 10us> 10us> 10usFigure 16. Power Up Sequence

Standby (1)In standby state, the PLL/LVDS clock receiver is running,but the derived logic clock signal is not enabled.

Enable Clock Management − Part 1

The ‘Enable Clock Management’ action configures theclock management blocks and activates the clock generationand distribution circuits in a pre−defined way. First, a set ofclock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation modeof the sensor.
Table 6 shows the SPI uploads to be executed to configure
the sensor for P1−SN/SE/FN, P3−SN/SE 10−bit serial
mode, with the PLL, and all available LVDS channels.
Note that the SPI uploads to be executed to configure thesensor for other supported modes (P1−SN/SE/FN 8−bit
serial,...) are available to customers under NDA at the
ON Semiconductor Image Sensor Portal.
If the PLL is not used, the LVDS clock input must be
running.
It is important to follow the upload sequence listed inTable 6.

Standby (2)In standby state, the derived logic clock signal is running.
All SPI registers are active, meaning that all SPI registers
can be accessed for read or write operations. All other blocks
are disabled.
Idle

In the idle state, all internal blocks are enabled, except thesequencer block. The sensor is ready to start grabbing
images as soon as the sequencer block is enabled.
Running

In running state, the sensor is enabled and grabbing
images. The sensor can be operated in global master/slavemodes.
User Actions: Power Up Functional Mode Sequences

Use of Phase Locked Loop

Power Up Sequence

If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detectcircuit detects if the clock is stable. When complete, this is
flagged in a status register.
Check the PLL_lock flag 24[0] by reading the SPI
register. When the flag is set, the ‘Enable ClockManagement− Part 2’ action can be continued. When PLL
is not used, this step can be bypassed as shown in Figure 15
on page 14.

Figure 16 shows the power up sequence of the sensor. The
figure indicates that the first supply to ramp−up is the
vdd_18 supply, followed by vdd_33 and vdd_pix
respectively. It is important to comply with the describedsequence. Any other supply ramping sequence may lead tohigh current peaks and, as consequence, a failure of thesensor power up.
The clock input should start running when all supplies arestabilized. When the clock frequency is stable, the reset_n
signal can be de−asserted. After a wait period of 10 ms, thepower up sequence is finished and the first SPI upload canbe initiated.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input(lvds_clock_inn/p) in case the PLL is bypassed.

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NOIP1SN5000A
Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #Address

Data

Description

P1−SN/SE/FN, P3−SN/SE 10−bit mode with PLL
2

1

2

32

0x0000

Monochrome sensor

0x0001

Color sensor

0x7004

Configure clock management P1−SN/SE/FN only

0x7014

Configure clock management P3−SN/SE only

0x0000Configure clock management

3

20

4

17

0x2113

Configure PLL

5260x2280Configure PLL lock detector

627

0x3D2D

Configure PLL lock detector

780x0000

Release PLL soft reset

8160x0003

Enable PLL

Enable Clock Management − Part 2

The next step to configure the clock management consistsof SPI uploads which enables all internal clock distribution.

The required uploads are listed in Table 7. Note that it isimportant to follow the upload sequence listed in Table 7.

Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #Address

Data

Description

P1−SN/SE/FN, P3−SN/SE 10−bit mode with PLL
190x0000

Release clock generator soft reset2320x7006

Enable logic clock for P1−SN/SE/FN only

0x7016

Enable logic clock for P3−SN/SE only

3

34

0x0001

Enable logic block

Required Register Upload

In this phase, the ‘reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed

and may cause the sensor to malfunction. The required
uploads are listed in Table 8.

Table 8. REQUIRED REGISTER UPLOADS
Upload #Address

P1−SN/SE/FN 10−bit
mode with PLL(8 LVDS NZROT)P3−SN/SE 10−bit
mode with PLL(4 LVDS NZROT)

1410x08540x08542

420x02000x02003

430x000C

0x000C

465

0x48CB

0x48CB

566

0x53C80x53C4667

0x86880x4544768

0x00850x00858690x08880x08489700x44110x44111071

0x97880x97881172

0x33300x333012

128

0x47140x4714131290x80010x800114

1710x10020x100215175

0x00800x0080

16

176

17

177

0x04000x040018

192

0x000C

0x000C

19

193

0x4E00

0x2C0020

194

0x02E40x02E421

197

0x01040x010422

199

0x01960x017423200

0x08040x080424

201

0x00B10x006025

204

0x01E1

0x01E126

207

0x00000x000027

208

0xA100

0xA10028

211

0x0E490x0E3929

215

0x111F0x111F

30

216

0x7F00

0x7F0031219

0x00200x002032

220

0x24340x243233

224

0x3E170x3E17www.onsemi.com
16

0x00E60x00E6

NOIP1SN5000A
Upload #Address

P1−SN/SE/FN 10−bit
mode with PLL(8 LVDS NZROT)P3−SN/SE 10−bit
mode with PLL(4 LVDS NZROT)

Upload #Address

P1−SN/SE/FN 10−bit
mode with PLL(8 LVDS NZROT)P3−SN/SE 10−bit
mode with PLL(4 LVDS NZROT)

34

227

0x00000x000071416

0xC8000xC80035

250

0x20810x208172417

0xCC0A

0xCC0A

36

256

0xA100

0xA10073418

0xC8060xC80637257

0x00000x000074419

0xC8000xC80038

258

0x07FF

0x07FF75

420

0x00300x003039384

0xC8000xC80076421

0x21790x217540

385

0xFB1F

0xFB1F77422

0x20710x2071

41

386

0xFB1F

0xFB1F78423

0x00710x0071

42387

0xFB12

0xFB1279424

0x107F0x107C

43388

0xF9120xF91280425

0x10790x0071

44389

0xF9020xF90281426

0x00710x003145

390

0xF8040xF80482427

0x00310x01B2

46

391

0xF0080xF00883428

0x01B40x21B547392

0xF1020xF10284429

0x21B90x20B1

48

393

0xF30F

0xF30F85

430

0x20B10x00B1

49394

0xF30F

0xF30F

86431

0x00B1

0x10BC50

395

0xF30F

0xF30F

87

432

0x10BF

0x00B1

51

396

0xF30F

0xF30F

88

433

0x10B90x003052

397

0xF30F

0xF30F

89

434

0x00B10x003053

398

0xF30F

0xF30F90435

0x00300x207554

399

0xF1020xF10291436

0x00300x2071

55

400

0xF0080xF00892437

0x20790x0071

56

401

0xF24A

0xF24A93438

0x20710x107C57

402

0xF2640xF26494439

0x00710x0071

58

403

0xF226

0xF22695

440

0x107F0x0031

59

404

0xF021

0xF02196441

0x10790x01B260

405

0xF0020xF00297442

0x0071

0x21B561406

0xF40A

0xF40A98443

0x0031

0x20B1

62407

0xF0050xF00599444

0x01B40x00B1

63

408

0xF20F

0xF20F

100

445

0x21B90x10BC

64

409

0xF20F

0xF20F

101

446

0x20B10x00B1

65

410

0xF20F

0xF20F

102447

0x00B10x003066

411

0xF20F

0xF20F

103

448

0x10BF

67412

0xF0050xF005104449

0x10B968413

0xEC050xEC05105

450

0x00B169414

0xC8010xC801

106451

0x003070415

0xC8000xC800

NOTE: Register uploads for other supported operation modes canbe accessed at the Image Sensor Portal on MyON.

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NOIP1SN5000A
Soft Power Up

During the soft power up action, the internal blocks areenabled and prepared to start processing the image data

stream. This action exists of a set of SPI uploads. The soft
power up uploads are listed in Table 9.

Table 9. SOFT POWER UP REGISTER UPLOADS
Upload #Address

Data

Description

P1−SN/SE/FN, P3−SN/SE 10−bit mode with PLL (P1−SN/SE/FN in ZROT, P3−SN/SE in NZROT)
1

100x0000

Release soft reset state2320x7007

Enable analogue clock P1−SN/SE/FN only

0x7017

Enable analogue clock P3−SN/SE only

364

0x0001

Enable biasing clock

4

400x0003

Enable column multiplexer

5480x0001

Enable AFE

668

0x0085

Enable LVDS bias

772

0x3337

Enable charge pump8

1120x0007

Enable LVDS transmitters

Enable Sequencer

The ‘Enable Sequencer’ action consists of a set of register
uploads. The required uploads are listed in Table 10.

During the ‘Enable Sequencer’ action, the frame grabbing
sequencer is enabled. The sensor starts grabbing images in
the configured operation mode. Refer to Sensor States on
page 15.
Table 10. ENABLE SEQUENCER REGISTER UPLOADS
Upload #Address

Data

1

192

0x080D

User Actions: Functional Modes to Power Down Sequences
Disable Sequencer

During the ‘Disable Sequencer’ action, the frame
grabbing sequencer is stopped. The sensor stops grabbing
images and returns to the idle mode.

The ‘Disable Sequencer’ action consists of a set of register
uploads. as listed in Table 11.

Table 11. DISABLE SEQUENCER REGISTER UPLOAD
Upload #Address

Data

1

192

0x080CSoft Power Down

During the soft power down action, the internal blocks are
disabled and the sensor is put in standby state to reduce thecurrent dissipation. This action exists of a set of SPI uploads.
The soft power down uploads are listed in Table 12.

Table 12. SOFT POWER DOWN REGISTER UPLOADS
Upload #Address

Data

Description

P1−SN/SE/FN, P3−SN/SE 10−bit mode with PLL (P1−SN/SE/FN in ZROT, P3−SN/SE in NZROT)
11120x0000

Disable LVDS transmitters2720x3330

Disable charge pump3

48

0x0000

Disable AFE

4400x0000

Disable column multiplexer

5640x0000

Disable biasing clock6

32

0x7006

Disable analogue clock P1−SN/SE/FN only

0x7016

Disable analogue clock P3−SN/SE only

0x0999

Soft reset

710

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NOIP1SN5000A

Disable Clock Management − Part 2

The ‘Disable Clock Management’ action stops theinternal clocking to further decrease the power dissipation.

This action can be implemented with the SPI uploads asshown in Table 13.

Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #Address

Data

Description

P1−SN/SE/FN, P3−SN/SE 10−bit mode with PLL
1

32

2

34

3

9

0x7004

Disable logic clock P1−SN/SE/FN only

0x7014

Disable logic clock P3−SN/SE only

0x0000

Disable logic blocks

0x0009

Soft reset clock generator

Disable Clock Management − Part 1

The ‘Disable Clock Management’ action stops theinternal clocking to further decrease the power dissipation.

This action can be implemented with the SPI uploads asshown in Table 14.

Table 14. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #Address

Data

Description

P1−SN/SE/FN, P3−SN/SE 10−bit mode with PLL
1

80x0099

Soft reset PLL2

160x0000

Disable PLLPower Down Sequence

Figure 17 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is inreset before the clock input stops running. Otherwise, theinternal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies isfirst vdd_pix, second vdd_33, and finally vdd_18. Any othersequence can cause high peak currents.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input(lvds_clock_inn/p) in case the PLL is bypassed.

clock input

reset_nvdd_18vdd_33

vdd_pix> 10us> 10us> 10us> 10usFigure 17. Power Down Sequence

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NOIP1SN5000A
Sensor Reconfiguration

Sensor Configuration

During the standby, idle, or running state several sensor
parameters can be reconfigured.
• Frame Rate and Exposure Time: Frame rate andexposure time changes can occur during standby, idle,
and running states by modifying registers 199 to 203.
Refer to page 30−32 for more information.
• Signal Path Gain: Signal path gain changes can occur
during standby, idle, and running states by modifying
registers 204/205. Refer to page 37 for more
information.
• Windowing: Changes with respect to windowing canoccur during standby, idle, and running states. Refer toMultiple Window Readout on page 28 for more
information.
• Subsampling: Changes of the subsampling mode canoccur during standby, idle, and running states bymodifying register 192. Refer to Subsampling on
page 29 for more information.
• Shutter Mode: The shutter mode can only be changed
during standby or idle mode by modifying register 192.
Reconfiguring the shutter mode during running state is
not supported.

This device contains multiple configuration registers.
Some of these registers can only be configured while thesensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible todistinguish the register set that can cause corrupted images(limited number of images containing visible artifacts) fromthe set of registers that are not causing corrupted images.
These three categories are described here.
Static Readout Parameters

Some registers are only modified when the sensor is notacquiring images. reconfiguration of these registers while
images are acquired can cause corrupted frames or eveninterrupt the image acquisition. Therefore, it isrecommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
shown in Table 15 should not be reconfigured during image
acquisition. A specific configuration sequence applies forthese registers. Refer to the operation flow and startup
description.

Table 15. STATIC READOUT PARAMETERS
Group

Addresses

Description

Clock generator

32

Configure according to recommendation

Image core40

Configure according to recommendation

AFE

48

Configure according to recommendation

Bias

64–71

Configure according to recommendation

Charge Pump

72

Configure according to recommendation

LVDS

112

Configure according to recommendation

192 [6:1]

Operation modes are: • triggered_mode• slave_mode

Sequencer mode selection
All reserved registers

Keep reserved registers to their default state, unless otherwise described in the recommendation

Dynamic Configuration Potentially Causing Image
Artifacts

image containing visible artifacts. A typical example of acorrupted image is an image which is not uniformly
exposed.
The effect is transient in nature and the new configuration
is applied after the transient effect.

The category of registers as shown in Table 16 consists ofconfigurations that do not interrupt the image acquisition
process, but may lead to one or more corrupted images
during and after the reconfiguration. A corrupted image is an

Table 16. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group

Addresses

Description

Black level configuration

128–129
197[12:8]

Reconfiguration of these registers may have an impact on the black−level
calibration algorithm. The effect is a transient number of images with incorrect black levelcompensation.

Sync codes

129[13]
116–126

Incorrect sync codes may be generated during the frame in which these registers are modified.

Datablock test configurations

144, 146–150

Modification of these registers may generate incorrect test patterns duringa transient frame.

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NOIP1SN5000A
Dynamic Readout Parameters

shown in Table 17. Some reconfiguration may lead to one
frame being blanked. This happens when the modification
requires more than one frame to settle. The image is blanked
out and training patterns are transmitted on the data and sync
channels.

It is possible to reconfigure the sensor while it is acquiring
images. Frame related parameters are internallyresynchronized to frame boundaries, such that the modified
parameter does not affect a frame that has already started.
However, there can be restrictions to some registers as
Table 17. DYNAMIC READOUT PARAMETERS
Group

Addresses

Description

Subsampling/binning

192[7]
192[8]

Subsampling or binning is synchronized to a new frame start.

ROI configuration

195
256–303

A ROI switch is only detected when a new window is selected as the active window(reconfiguration of register 195). reconfiguration of the ROI dimension of the active window does notlead to a frame blank and can cause a corrupted image.

Exposure
reconfiguration

199−203

Exposure reconfiguration does not cause artifact. However, a latency of one frame is observed unlessreg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode (master).

204

Gains are synchronized at the start of a new frame. Optionally, one frame latency can be incorporated
to align the gain updates to the exposure updates(refer to register 204[13] − gain_lat_comp).

Gain reconfiguration

Freezing Active Configurations

them for the coming frames. The freezing of the active setof registers can be programmed in the sync_configuration
registers, which can be found at the SPI address 206.
Figure 18 shows a reconfiguration that does not use thesync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
Figure 19 shows the usage of the sync_configuration
settings. Before uploading a set of registers, thecorresponding sync_configuration is de−asserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to thecoming frame boundaries. As seen in the figure, this ensuresthat the uploads performed at the end of frame N+2 and thestart of frame N+3 become active in the same frame (frame
N+4).

Though the readout parameters are synchronized to frameboundaries, an update of multiple registers can still lead toa transient effect in the subsequent images, as someconfigurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possiblethat the reconfiguration of multiple registers spans over twoor even more frames. To avoid inconsistent combinations,freeze the active settings while altering the SPI registers by
disabling synchronization for the corresponding
functionality before reconfiguration. When all registers are
uploaded, re−enable the synchronization. The sensor’s
sequencer then updates its active set of registers and uses
Time Line

Frame NFrame N+1 Frame N+2 Frame N+3

Frame N+4

SPI Registers
Active Registers

Figure 18. Frame Synchronization of Configurations (no freezing)

Time Line

Frame NFrame N+1 Frame N+2 Frame N+3 Frame N+4

sync_configuration

This configuration is not taken into
account as sync_register is inactive.

SPI Registers
Active Registers

Figure 19. reconfiguration Using Sync_configuration

NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 18 lists the several sync_configuration possibilities along with the respective registers being
frozen.
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NOIP1SN5000A
Table 18. ALTERNATE SYNC CONFIGURATIONS
Group

Affected Registers

Description

sync_black_lines

black_lines

Update of black line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.

sync_exposure

mult_timer
fr_length
exposure

Update of exposure configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.

sync_gain

mux_gainsw
afe_gainUpdate of gain configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.

sync_roi

roi_active0[15:0]
subsamplingbinning

Update of active ROI configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. reconfiguration ofactive windows is not gated by this setting.

Window Configuration

Black Calibration

The sensor automatically calibrates the black level foreach frame. Therefore, the device generates a configurable
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface canbe configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’when setting the black level target to ‘0’.
The black level is calibrated for the 16 columns containedin one kernel. This implies 16 black level offsets are
generated and applied to the corresponding columns.
Configurable parameters for the black−level algorithm arelisted in Table 19.

Global Shutter Mode

Up to 16 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined byregisters 256 to 303. Each window can be activated ordeactivated separately using register 195. It is possible toreconfigure the inactive windows while the sensor isacquiring images.
Switching between predefined windows is achieved by
activation of the respective windows. This way a minimum
number of registers need to be uploaded when it is necessary
to switch between two or more sets of windows. As an
example of this, scanning the scene at higher frame rates
using multiple windows and switching to full frame capture
when the object is tracked. Switching between the twomodes only requires an upload of one register.

Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Address

Register Name

Description

Black Line Generation
197[7:0]

black_lines

This register configures the number of black lines that are generated at the start of a frame. At least one
black line must be generated. The maximum number is 255.
Note: When the automatic black−level calibration algorithm is enabled, make sure that this register isconfigured properly to produce sufficient black pixels for the black−level filtering.
The number of black pixels generated per line is dependent on the operation mode and window configurations:
Each black line contains 162 kernels.

197[12:8]

gate_first_line

A number of black lines are blanked out when a value different from 0 is configured. These blanked outlines are not used for black calibration. It is recommended to enable this functionality, because the firstline can have a different behavior caused by boundary effects. When enabling, the number of blacklines must be set to at least two in order to have valid black samples for the calibration algorithm.

129[0]

auto_blackcal_enable

Internal black−level calibration functionality is enabled when set to ‘1’. Required black level offset compensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black−level calibration functionality is disabled. It is possible to apply an
offset compensation to the image pixels, which is defined by the registers 129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide
external statistics and, optionally, calibrations.

129[9:1]

blackcal_offset

Black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_enable is set to ‘0’. The sign of the offset is determined by register 129[10] (blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is disabled.

129[10]blackcal_offset_dec

Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set to ‘1’, theblack calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.

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NOIP1SN5000A
Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Address

Register Name

Description

Black Line Generation
128[10:8]

black_samples

The black samples are low−pass filtered before being used for black level calculation. The more samples are taken into account, the more accurate the calibration, but more samples require more blacklines, which in turn affects the frame rate.
The effective number of samples taken into account for filtering is 2^ black_samples.
Note: An error is reported by the device if more samples than available are requested (refer to register
136).

Black Level Filtering Monitoring
136

blackcal_error0

An error is reported by the device if there are requests for more samples than are available (each bit
corresponding to one data path). The black level is not compensated correctly if one of the channels
indicates an error. There are three possible methods to overcome this situation and to perform a correct
offset compensation:• Increase the number of black lines such that enough samples are generated at the cost of increasing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determination (refer toregister 128).
• Disable automatic black level calibration and provide the offset via SPI register upload. Note thatthe black level can drift in function of the temperature. It is thus recommended to perform the offset
calibration periodically to avoid this drift.

NOTE: The maximum number of samples taken into account for black level statistics is half the number of kernels.

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NOIP1SN5000A
Serial Peripheral Interface

first. The sck clock is passed through to the sensor
as indicated in Figure 20. The sensor samples thisaddress data on a rising edge of the sck clock(mosi needs to be driven by the system on thefalling edge of the sck clock).
3. The tenth bit sent by the master indicates the typeof transfer: high for a write command, low for aread command.
4. Data transmission:- For write commands, the master continues
sending the 16−bit data, most significant bit first.
- For read commands, the sensor returns the data on
the requested address on the miso pin, mostsignificant bit first. The miso pin must be sampled
by the system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
5. When data transmission is complete, the systemdeselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Note that the maximum frequency for the SPI interface
scales with the input clock frequency, bit depth and LVDS
output multiplexing as described in Table 5.
Consecutive SPI commands can be issued by leaving atleast two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling thess_n pin high.

The sensor configuration registers are accessed throughan SPI. The SPI consists of four wires:• sck: Serial Clock• ss_n: Active Low Slave Select• mosi: Master Out, Slave In, or Serial Data In• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by themaster (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 20 shows the communication protocol for read andwrite accesses of the SPI registers. The PYTHON sensor
uses 9−bit addresses and 16−bit data words.
Data driven by the system is colored blue in Figure 16,
while data driven by the sensor is colored yellow. The datain grey indicates high−Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosisampling); green markers indicate sampling points for thesystem (miso sampling during read operations).
The access sequence is:
1. Select the sensor for read or write by pulling down
the ss_n line.
2. One SPI clock cycle after selecting the sensor, the9−bit address is transferred, most significant bit

SPI − WRITE
ss_nt_sckss

tsck

t_sssck

sck
ts _mos i

mosi

A8

th_mosi
A7

..

..

..

A1

A0

`1'

D15

D14

..

..

..

..

D1

D0

miso

SPI − READ
ss_nt_sssck

t_scksstsck

sck
ts_mosimosi

A8

th_mosi
A7

..

..

..

A1

A0

`0'

ts _miso

miso

D15

th_miso
D14

..

..

Figure 20. SPI Read and Write Timing Diagram

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..

..

D1

D0

NOIP1SN5000A
Table 20. SPI TIMING REQUIREMENTS
Group

Addresses

Description

Units
ns

tsck

sck clock period

100 (*)

tsssckss_n low to sck rising edge

tsck

ns

tsckss

sck falling edge to ss_n high

tsck

ns

ts_mosi

Required setup time for mosi

20nsth_mosi

Required hold time for mosi

20

nsts_miso

Setup time for miso

tsck/2−10nsth_miso

Hold time for miso

tsck/2−20

ns

tspi

Minimal time between two consecutive SPI accesses (not shown in figure)2 x tsck

ns*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/fSPI. See text for more information on SPI clock frequency restrictions.

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NOIP1SN5000A
IMAGE SENSOR TIMING AND READOUT
Global Shutter Mode

exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
NOTE: The start of the exposure time is synchronized tothe start of a new line (during ROT) if the
exposure period starts during a frame readout.
As a consequence, the effective time during
which the image core is in a reset state isextended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to readout all lines. If
this is not the case, the exposure time is extended untilall (active) lines are read out.
• Alternatively, it is possible to specify the frame timeand exposure time. The sensor automatically calculates
the required reset time. This mode is enabled by the
fr_mode register. The frame time is specified in theregister fr_length.

Pipelined Global Shutter (Master)

The integration time is controlled by the registers
fr_length[15:0] and exposure[15:0]. The mult_timer
configuration defines the granularity of the registers
reset_length and exposure and is read as number of system
clock cycles.
The exposure control for (Pipelined) Global Master modeis depicted in Figure 21.
The pixel values are transferred to the storage node during
FOT, after which all photo diodes are reset. The reset stateremains active for a certain time, defined by the reset_lengthand mult_timer registers, as shown in the figure. Note thatmeanwhile the image array is read out line by line. After thisreset period, the global photodiode reset condition isabandoned. This indicates the start of the integration or

Frame N

Exposure State

FOT

Readout

FOT

Reset

Frame N+1

Integrating

FOT

Reset

Integrating

FOT

FOT
FOT

Image Array Global Reset
reset_lengthxmult_timer

exposurexmult_timer= ROT= Readout= Readout Dummy Line (blanked)

Figure 21. Integration Control for (Pipelined) Global Shutter Mode (Master)www.onsemi.com
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NOIP1SN5000A
Triggered Global Shutter (Master)

exposure and mult_timer, as in the master pipelined global
mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 22.

In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger0 pin. The
exposure or integration time is defined by the registers
Frame N

Exposure State

FOT

Reset

Integrating

FOT

Reset

Integrating

FOT(No effect on falling edge)

trigger0
Readout

Frame N+1

FOT

FOT

FOT

Image Array Global Resetexposure x mult_timer= ROT= Readout= Readout Dummy Line (blanked)

Figure 22. Exposure Time Control in Triggered Shutter Mode (Master)

the pixel storage node and readout of the image array. In
other words, the high time of the trigger pin indicates theintegration time, the period of the trigger pin indicates theframe time.
The use of the trigger during slave mode is shown in
Figure 23.

Notes:• The falling edge on the trigger pin does not have any
impact. Note however the trigger must be asserted forat least 100 ns.
• The start of the exposure time is synchronized to thestart of a new line (during ROT) if the exposure period
starts during a frame readout. As a consequence, theeffective time during which the image core is in a reset
state is extended to the start of a new line.
• If the exposure timer expires before the end of readout,
the exposure time is extended until the end of the lastactive line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger canbe initiated after a rising edge on monitor0).

Notes:• The registers exposure, fr_length, and mult_timer are

not used in this mode.
• The start of exposure time is synchronized to the startof a new line (during ROT) if the exposure period starts
during a frame readout. As a consequence, the effective
time during which the image core is in a reset state isextended to the start of a new line.
• If the trigger is de−asserted before the end of readout,
the exposure time is extended until the end of the lastactive line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger canbe initiated after a rising edge on monitor0).

Triggered Global Shutter (Slave)

Exposure or integration time is fully controlled by meansof the trigger pin in slave mode. The registers fr_length,
exposure and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer toFrame N

Exposure State

FOT

Reset

Frame N+1

Integrating

FOT

Reset

Integrating

FOT

trigger0
Readout

FOT

FOT

FOT

Image Array Global Reset= ROT= Readout= Readout Dummy Line (blanked)

Figure 23. Exposure Time Control in Global−Slave Modewww.onsemi.com
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NOIP1SN5000A
ADDITIONAL FEATURES
Multiple Window Readout

The PYTHON 2000 and PYTHON 5000 sensor supports
multiple window readout, which means that only theuser−selected Regions Of Interest (ROI) are read out. This
allows limiting data output for every frame, which in turnallows increasing the frame rate. In global shutter mode, up
to eight ROIs can be configured.

y1_endROI 1

y0_endy1_start
ROI 0

Window Configuration

Figure 24 shows the four parameters defining a region ofinterest (ROI).

y0_start

y-end
x0_start

x0_endx1_start

x1_endFigure 25. Overlapping Multiple Window
Configuration

ROI 0

The sequencer analyses each line that needs to be read out
for multiple windows.

y-startRestrictions

The following restrictions for each line are assumed forthe user configuration:• Windows are ordered from left to right, based on theirx−start address:

x-start x-end

Figure 24. Region of Interest Configuration

x_start_roi(i) v x_start_roi(j) AND• x−start[7:0]x_end_roi(i) vx_end_roi(j)x−start defines the x−starting point of the desired window.
The sensor reads out 16 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x−start
position is also 16 pixels for no sub sampling. The value
configured in the x−start register is multiplied by 16 to findthe corresponding column in the pixel array.
• x−end[7:0]This register defines the window end point on the x−axis.
Similar to x−start, the granularity for this configuration is
one kernel. x−end needs to be larger than x−start.
• y−start[9:0]
The starting line of the readout window. The granularityof this setting is one line, except with color sensors where it
needs to be an even number.
• y−end[9:0]The end line of the readout window. y−end must be
configured larger than y−start. This setting has the same
granularity as the y−start configuration.
Up to eight windows can be defined, possibly (partially)
overlapping, as illustrated in Figure 25.

Where j > i

Processing Multiple Windows

The sequencer control block houses two sets of counters
to construct the image frame. As previously described, they−counter indicates the line that needs to be read out and isincremented at the end of each line. For the start of the frame,
it is initialized to the y−start address of the first window andit runs until the y−end address of the last window to be readout. The last window is configured by the configuration
registers and it is not necessarily window #15.
The x−counter starts counting from the x−start address of
the window with the lowest ID which is active on theaddressed line. Only windows for which the current
y−address is enclosed are taken into account for scanning.
Other windows are skipped.
Figure 26 illustrates a practical example of aconfiguration with five windows. The current position of theread pointer (ys) is indicated by a red line crossing the imagewww.onsemi.com
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NOIP1SN5000A
array. For this position of the read pointer, three windows
need to be read out. The initial start position for the x−kernel
pointer is the x−start configuration of ROI1. Kernels arescanned up to the ROI3 x−end position. From there, thex−pointer jumps to the next window, which is ROI4 in thisillustration. When reaching ROI4’s x−end position, the readpointer is incremented to the next line and xs is reinitialized
to the starting position of ROI1.
Notes:• The starting point for the readout pointer at the start ofa frame is the y−start position of the first active
window.
• The read pointer is not necessarily incremented by one,but depending on the configuration, it can jump in
y−direction. In Figure 26, this is the case when reaching
the end of ROI0 where the read pointer jumps to they−start position of ROI1
• The x−pointer starting position is equal to the x−start
configuration of the first active window on the current
line addressed. This window is not necessarily window#0.
• The x−pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to thestart of the next window.
• Each window can be activated separately. There is norestriction on which window and how many of the 16
windows are active.

ROI 2

ys

ROI 3

ROI 4

ROI 1

ROI 0

Figure 26. Scanning the Image Array with Five
Windows
Subsampling

Subsampling is used to reduce the image resolution. This
allows increasing the frame rate. Two subsampling modes
are supported: for monochrome and NIR enhanced sensors(P1−SN/FN and P3−SN) and color sensors (P1−SE andP3−SE).
Monochrome Sensors

For monochrome sensors, the read−1−skip−1
subsampling scheme is used. Subsampling occurs both in x−
and y− direction.
Color Sensors

For color sensors, the read−2−skip−2 subsampling
scheme is used. Subsampling occurs both in x− and y−
direction. Figure 27 shows which pixels are read and which
ones are skipped.

Figure 27. Subsampling Scheme for Monochrome and Color Sensors
Binning

NOTES:
1. Register 194[13:12] needs to be configured to 0x0
for 2x2 pixel binning and to 0x1 for 2x1 binning.
Binning occurs only in x direction.
2. Binning in y-direction cannot be used in
combination with pipelined integration andreadout. The integration time and readout timeshould be separated in time (do not coincide).

Pixel binning is a technique in which different pixels
belonging to a rectangular bin are averaged in the analog
domain. Two−by−two pixel binning is available with themonochrome and NIR enhanced image sensors (P1−SN/FN
and P3−SN). This implies that two adjacent pixels areaveraged both in column and row. Binning is configurable
using a register setting. Pixel binning is not supported on
PYTHON 2000 and PYTHON 5000 (P1−SE and P3−SE)color option and in Zero ROT mode.

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NOIP1SN5000A
Reverse Readout in Y−direction

channels. Using this function, one may for instance use thedevice with sync+clock+8 data channels. Enabling thechannel multiplexing is done through register 32[5:4]. The
default value of 0 disables all channel multiplexing. Higher
values sets higher degree of channel multiplexing. The
channels that are used per degree of multiplexing are shownin Table 5. The unused data channels are powered down andwill not send any data.

Reverse readout in y−direction can be done by asserting
reverse_y (reg 194[8]). The reference for y_start and y_end
pointers is reversed.
Channel Multiplexing

The PYTHON 2000 and PYTHON 5000 image sensors
contains a function for channel multiplexing the output

Table 21. LVDS DATA OUTPUT CHANNELS USED WITH CHANNEL MULTIPLEXING# outputs

PYTHON 2000 / PYTHON 5000 − LVDS Channels

8 channels

Ch 0

Ch 1

Ch 2

4 channels

Ch 0

Ch 2

2 channels

Ch 0

Ch 2

1 channel

Ch 0

Ch 3

Ch 4

Ch 5

Ch 6

Ch 4

Ch 7

Ch 6

Register 32[5:4]
Data

Register 211
Data

0

0x0E491

0x0E392

0x0E2930x0E19

1. P1−SN/SE/FN supports 8, 4, 2, 1 LVDS outputs while P3−SN/SE supports 4, 2, 1 LVDS outputs.
2. Use P3−SN/SE bias uploads for P1−SN/SE/FN when operating in mux mode.

Table 22. BIAS UPLOADS FOR P1−SN/SE/FN AND P3−SN/SE
Bias Uploads

Address

mux 8:8

mux 8:4

mux 8:2

mux 8:1

reg_mux_image_core_config1

41

0x08540x08540x08540x0854

reg_mux_image_core_config2

420x02030x02030x02030x0203reg_mux_image_core_config3

430x000C

0x000C

0x000C

0x000C

reg_bias_configuration

65

0x48CB

0x48CB

0x48CB

0x48CB

reg_bias_afe_bias

66

0x53C80x53C4

0x53C20x53C1

reg_bias_mux_bias

67

0x86880x45440x23220x1211

reg_bias_lvds_bias

680x00850x00850x00850x0085

reg_bias_adc_bias

69

0x08880x08480x08280x0818reg_bias_imc_bias

700x44110x44110x44110x4411

reg_cp_configuration

72

0x33370x33370x33370x3337www.onsemi.com
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NOIP1SN5000A
Multiple Slope Integration

To increase the dynamic range of the sensor, a second
slope is applied in the dual slope mode (green curve). The
sensor has the same responsivity in the black as for a single
slope, but from ‘knee point 1’ on, the sensor is lessresponsive to incoming light. The result is that the saturation
point is at a higher light power level.
To further increase the dynamic range, a third slope can beapplied, resulting in a second knee point.
Refer to section Global Shutter Mode on page 26 forgeneral notes applicable to the global shutter operation andmore particular to the use of the trigger0 pin.

‘Multiple Slope Integration’ is a method to increase thedynamic range of the sensor. The PYTHON supports up to
three slopes.
Figure 28 shows the sensor response to light when thesensor is used with one slope, two slopes, and three slopes.
The X−axis represents the light power; the Y−axis shows thesensor output signal. The kneepoint of the multiple slope
curves are adjustable in both position and voltage level.
It is clear that when using only one slope (red curve), thesensor has the same responsivity over the entire range, until
the output saturates at the point indicated with ‘single slope
saturation point’.
output1023‘kneepoint 2’

slope 3slope 1slope 2‘kneepoint 1’

0

light
single slope
saturation point

dual slope
saturation point

triple slope
saturation point

Figure 28. Multiple Slope Operation
Kneepoint Configuration (Multiple Slope Reset Levels)

dual_slope_enable and triple_slope_enable and their values
are defined by the registers exposure_ds and exposure_ts.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.
Figure 29 shows the frame timing for pipelined mastermode with dual and triple slope integration and
fr_mode = ‘0’ (fr_length representing the reset length).
In triggered master mode, the start of integration is
initiated by a rising edge on trigger0, while the falling edge
does not have any relevance. Exposure duration anddual/triple slope points are defined by the registers.

The kneepoint reset levels are configured by means of
DAC configurations in the image core. The dual slope
kneepoint is configured with the dac_ds configuration,
while the triple slope kneepoint is configured with the
dac_ts register setting. Both are located on address 41.
Multiple Slope Integration in “Master Mode” (Pipelinedor Triggered)

In master mode, the time stamps for the double and triple
slope resets are configured in a similar way as the exposure
time. They are enabled through the registers

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NOIP1SN5000A

Figure 29. Multiple Slope Operation in Master Mode for fr_mode = ‘0’ (Pipelined)
Slave Mode

initiates the triple slope reset sequence. Rising edges on
trigger1 and trigger2 do not have any impact.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.

In slave mode, the register settings for integration control
are ignored. The user has full control through the trigger0,
trigger1 and trigger2 pins. A falling edge on trigger1
initiates the dual slope reset while a falling edge on trigger2

Figure 30. Multiple Slope Operation in Slave Mode
Black Reference

pixel data is transmitted over the usual output interface,
while the regular image data is compensated (can bebypassed).
On the output interface, black lines can be seen as aseparate window, however without Frame Start and Ends
(only Line Start/End). The Sync code following the LineStart and Line End indications (“window ID”) contains theactive window number, which is 0. Black reference data isclassified by a BL code.

The sensor reads out one or more black lines at the start ofevery new frame. The number of black lines to be generated
is programmable and is minimal equal to 1. The length of theblack lines depends on the operation mode. The sensor
always reads out the entire line (162 kernels), independentof window configurations.
The black references are used to perform black calibrationand offset compensation in the data channels. The raw black

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NOIP1SN5000A
Signal Path Gain

Digital Gain Stage

Analog Gain Stages

The digital gain stage allows fine gain adjustments on thedigitized samples. The gain configuration is an absolute 5.7
unsigned number (5 digits before and 7 digits after thedecimal point).

Referring to Table 23, several gain settings are available
in the analog data path to apply gain to the analog signal
before it is digitized.
The moment a gain reconfiguration is applied andbecomes valid can be controlled by the gain_lat_comp
configuration.
With ‘gain_lat_comp’ set to ‘0’, the new gain
configurations are applied from the very next frame.
With ‘gain_lat_comp’ set to ‘1’, the new gain settings are
postponed by one extra frame. This feature is useful when
exposure time and gain are reconfigured together, as an
exposure time update always has one frame latency.
Table 23. SIGNAL PATH GAIN STAGES
Analog Gain Non−Zeroand Zero ROT

Address

Gain Setting

204[12:0]

0x01E1

1

204[12:0]

0x00A1

1.6

204[12:0]

0x0021

2

204[12:0]

0x0083

2.6

204[12:0]

0x0085

3.2

204[12:0]

0x0081

4

204[12:0]

0x0086

5.3

204[12:0]

0x0082

8

NOTE: The sensor performance specifications are tested at unity
gain. Analog gain above 2x affects noise performance.
All other gain settings shown in this table are tested forsensor functionality.

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NOIP1SN5000A
Automatic Exposure Control

AEC
Statistics

Requested Illumination Level(Target)Total Gain

Requested Gain
Changes

The exposure control mechanism has the shape of ageneral feedback control system. Figure 31 shows the highlevel block diagram of the exposure control loop.

AEC
FilterAEC
Enforcer
Integration Time
Analog Gain (Coarse Steps)
Digital Gain (Fine Steps)

Image Capture

Figure 31. Automatic Exposure Control Loop

Three main blocks can be distinguished:• The statistics block compares the average of thecurrent image’s samples to the configured target value
for the average illumination of all pixels• The relative gain change request from the statistics
block is filtered through the AEC Filter block in thetime domain (low pass filter) before being integrated.
The output of the filter is the total requested gain in thecomplete signal path.
• The enforcer block accepts the total requested gain anddistributes this gain over the integration time and gainstages (both analog and digital)

calculated illumination and the target illumination thestatistics block requests a relative gain change.
Statistics Subsampling and Windowing
For average calculation, the statistics block willsub−sample the current image or windows by taking every
fourth sample into account. Note that only the pixels read out
through the active windows are visible for the AEC. In thecase where multiple windows are active, the samples will beselected from the total samples. Samples contained in aregion covered by multiple (overlapping) window will betaking into account only once.
It is possible to define an AEC specific sub−window onwhich the AEC will calculate it’s average. For instance, thesensor can be configured to read out a larger frame, while theillumination is measured on a smaller region of interest, e.g.
center weighted as shown in Table 24.

The automatic exposure control loop is enabled byasserting the aec_enable configuration in register 160.
NOTE: Dual and Triple slope integration is notsupported in conjunction with the AEC.
AEC Statistics Block

The statistics block calculates the average illumination of
the current image. Based on the difference between the
Table 24. AEC SAMPLE SELECTION
Register

Name

Description

192[10]roi_aec_enable

When 0x0, all active windows are selected for statistics calculation.
When 0x1, the AEC samples are selected from the active pixels contained in the region of interest defined by roi_aec

253−255

roi_aec

These registers define a window from which the AEC samples will be selected when roi_aec_enable is asserted.
Configuration is similar to the regular region of interests.
The intersection of this window with the active windows define the selected pixels. It is important that this window at least
overlaps with one or more active windows.

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NOIP1SN5000A
AEC Filter Block

Target Illumination
The target illumination value is configured by means ofregister desired_intensity as shown in Table 25.

The filter block low−pass filters the gain change requests
received from the statistics block.
The filter can be restarted by asserting the restart_filter
configuration of register 160.

Table 25. AEC TARGET ILLUMINATIONCONFIGURATIONAEC Enforcer Block

Register

Name

Description

161[9:0]

desired_intensity

Target intensity value, on 10−bit scale.
For 8−bit mode, target value is configured
on desired_intensity[9:2]

The enforcer block calculates the four different gain
parameters, based on the required total gain, thereby
respecting a specific hierarchy in those configurations.
Some (digital) hysteresis is added so that the (analog) sensor
settings don’t need to change too often.
Exposure Control Parameters
The several gain parameters are described below, in theorder in which these are controlled by the AEC for large
adjustments. Small adjustments are regulated by digital gain
only.
• Exposure TimeThe exposure is the time between the global image array
reset de−assertion and the pixel charge transfer. The
granularity of the integration time steps is configured by themult_timer register.
NOTE: The exposure_time register is ignored when the
AEC is enabled. The register fr_length defines
the frame time and needs to be configured
accordingly.
• Analog Gain
The sensor has two analog gain settings. Typically the
AEC shall only regulate the first stage.
• Digital Gain
The last gain stage is a gain applied on the digitizedsamples. The digital gain is represented by a 5.7 unsigned
number (i.e. 7 bits after the decimal point). While the analog
gain steps are coarse, the digital gain stage makes it possible
to achieve very fine adjustments.

Color Sensor
The weight of each color can be configured for color
sensors by means of scale factors. Note these scale factor are
only used to calculate the statistics in order to compensate
for (off−chip) white balancing and/or color matrices. The
pixel values itself are not modified.
The scale factors are configured as 3.7 unsigned numbers(0x80 = unity). Refer to Table 26 for color scale factors. For
mono sensors, configure these factors to their default value.
Table 26. COLOR SCALE FACTORS
Register

Name

Description

162[9:0]

red_scale_factor

Red scale factor for AEC statistics

163[9:0]

green1_scale_factor

Green1 scale factor for AEC
statistics

164[9:0]

green2_scale_factor

Green2 scale factor for AEC
statistics

165[9:0]

blue_scale_factor

Blue scale factor for AEC statistics

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NOIP1SN5000A
AEC Control Range

AEC Update Frequency

The control range for each of the exposure parameters canbe pre−programmed in the sensor. Table 27 lists the relevant
registers.
Table 27. MINIMUM AND MAXIMUM EXPOSURE
CONTROL PARAMETERS

As an integration time update has a latency of one frame,
the exposure control parameters are evaluated and updated
every other frame.
Note: The gain update latency must be postpone to matchthe integration time latency. This is done by asserting thegain_lat_comp register on address 204[13].

Register

Exposure Control Status Registers

Name

Description

168[15:0]

min_exposure

Lower bound for the integration time
applied by the AEC

169[1:0]min_mux_gain

Lower bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x0 = 1x0x1 = 2x169[3:2]

min_afe_gain

Lower bound for the second stage
analog amplifier.
This stage has only one
configuration with the following
approximative gain:
0x0 = 1.00x

169[15:4]

min_digital_gain

max_exposure

Upper bound for the integration time
applied by the AEC

171[1:0]

max_mux_gain

Upper bound for the first stage analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x0 = 1x0x1 = 2x171[15:4]

max_afe_gain

max_digital_
gain

Table 28. EXPOSURE CONTROL STATUS REGISTERS

Lower bound for the digital gainstage. This configuration
specifies the effective gain in 5.7
unsigned format

170[15:0]

171[3:2]

Configured integration and gain parameters are reported
to the user by means of status registers. The sensor provides
two levels of reporting: the status registers reported in the
AEC address space are updated once the parameters arerecalculated and requested to the internal sequencer. The
status registers residing in the sequencer’s address space on
the other hand are updated once these parameters are taking
effect on the image readout. Refer to Table 28 reflecting the
AEC and Sequencer Status registers.

Register

Name

Description

AEC Status Registers

Upper bound for the second stage
analog amplifierThis stage has only one
configuration with the following
approximative gain:
0x0 = 1.00x
Upper bound for the digital gainstage. This configuration
specifies the effective gain in 5.7
unsigned format

184[15:0]

total_pixels

Total number of pixels taken into accountfor the AEC statistics.

186[9:0]

averageCalculated average illuminationlevel for the current frame.

187[15:0]

exposure

AEC calculated exposure.
Note: this parameter is updated at theframe end.

188[1:0]

mux_gain

AEC calculated analog gain
(1st stage)
Note: this parameter is updated at theframe end.

188[3:2]

afe_gain

AEC calculated analog gain
(2st stage)
Note: this parameter is updated at theframe end.

188[15:4]

digital_gain

AEC calculated digital gain
(5.7 unsigned format)
Note: this parameter is updated at theframe end.

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NOIP1SN5000A
Table 28. EXPOSURE CONTROL STATUS REGISTERS
Register

Name

Description

Sequencer Status Registers
242[15:0]

mult_timer

mult_timer for current frame
Note: this parameter is updated once ittakes effect on the image.

243[15:0]

reset_length

Image array reset length for thecurrent frame.
Note: this parameter is updated once ittakes effect on the image.

244[15:0]

exposure

Exposure for the current frame.
Note: this parameter is updated once ittakes effect on the image.

245[15:0]

exposure_ds

Dual slope exposure for the current
frame. Note this parameter is not controlled by the AEC.
Note: this parameter is updated once ittakes effect on the image.

246[15:0]

exposure_ts

Triple slope exposure for thecurrent frame. Note this parameter is notcontrolled by the AEC.
Note: this parameter is updated once ittakes effect on the image.

247[4:0]

mux_gainsw

1st stage analog gain for the current
frame.
Note: this parameter is updated once ittakes effect on the image.

247[12:5]

afe_gain

2st stage analog gain for the current
frame.
Note: this parameter is updated once ittakes effect on the image.

248[11:0]

db_gain

Digital gain configuration for the current
frame (5.7 unsigned
format).
Note: this parameter is updated once ittakes effect on the image.

248[12]

dual_slope

Dual slope configuration for thecurrent frame
Note 1: this parameter is updated once ittakes effect on the image.
Note 2: This parameter is notcontrolled by the AEC.

248[13]

triple_slope

Triple slope configuration for the current
frame.
Note 1: this parameter is updated once ittakes effect on the image.
Note 2: This parameter is notcontrolled by the AEC.

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NOIP1SN5000A
Mode Changes and Frame Blanking

summarized in the following table for the sensor’s image
related modes.
NOTE: Major mode switching (i.e. switching between
master, triggered or slave mode) must be
performed while the sequencer is disabled(reg_seq_enable = 0x0).

Dynamically reconfiguring the sensor may lead tocorrupted or non-uniformilly exposed frames. For somereconfigurations, the sensor automatically blanks out theimage data during one frame. Frame blanking isTable 29. DYNAMIC SENSOR RECONFIGURATION AND FRAME BLANKING
Configuration

Corrupted
Frame

Blanked Out
Frame

Notes

Shutter Mode and Operation
triggered_mode

Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.

slave_mode

Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.

subsampling

Enabling: No
Disabling: Yes

Configurable

Configurable with blank_subsampling_ss register.

binning

No

Configurable

Configurable with blank_subsampling_ss register

NoNo

mult_timer

No

No

Latency is 1 frame

fr_length

No

No

Latency is 1 frame

exposure

No

No

Latency is 1 frame

mux_gainsw

No

No

Latency configurable by means of gain_lat_comp register

afe_gainNo

No

Latency configurable by means of gain_lat_comp register.

db_gain

No

No

Latency configurable by means of gain_lat_comp register.

roi_active

See Note

No

Windows containing lines previously not read out may lead to corrupted
frames.

roi*_configuration*

See Note

No

Reconfiguring the windows by means of roi*_configuration* may lead tocorrupted frames when configured close to frame boundaries.
It is recommended to (re)configure an inactive window and switch theroi_active register.
See Notes on roi_active.

black_samples

No

No

If configured within range of configured black lines

auto_blackal_enable

See Note

No

Manual correction factors become instantly active when
auto_blackcal_enable is deasserted during operation.

blackcal_offset

See Note

No

Manual blackcal_offset updates are instantly active.

No

No

Impacts the transmitted CRC

bl_0

No

No

Impacts the Sync channel information, not the Data channels.

img_0

No

No

Impacts the Sync channel information, not the Data channels.

crc_0

No

No

Impacts the Sync channel information, not the Data channels.

tr_0

No

No

Impacts the Sync channel information, not the Data channels.

Frame Timing
black_lines
Exposure Control

Gain

Window/ROIBlack Calibration

CRC Calculation
crc_seed
Sync Channel

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NOIP1SN5000A
Temperature Sensor

Calibration using one temperature point

The PYTHON has an on−chip temperature sensor which
returns a digital code (Tsensor) of the silicon junction
temperature. The Tsensor output is a 8−bit digital countbetween 0 and 255, proportional to the temperature of thesilicon substrate. This reading can be translated directly toa temperature reading in °C by calibrating the 8−bit readout
at 0°C and 85°C to achieve an output accuracy of ±2°C. The
Tsensor output can also be calibrated using a single
temperature point (example: room temperature or theambient temperature of the application), to achieve an
output accuracy of ±5°C.
Note that any process variation will result in an offset in
the bit count and that offset will remain within ±5°C over thetemperature range of 0°C and 85°C. Tsensor output digitalcode can be read out through the SPI interface.

The temperature sensor resolution is fixed for a given typeof package for the operating range of 0°C to +85°C andhence devices can be calibrated at any ambient temperatureof the application, with the device configured in the mode ofoperation.
Interpreting the actual temperature for the digital code
readout:

The formula used is
TJ = R (Nread − Ncalib) + Tcalib
TJ = junction die temperature
R = resolution in degrees/LSB (typical 0.75 deg/LSB)
Nread = Tsensor output (LSB count between 0 and 255)
Tcalib = Tsensor calibration temperature
Ncalib = Tsensor output reading at Tcalib

Output of the temperature sensor to the SPI:

Monitor Pins

tempd_reg_temp<7:0>: This is the 8−bit N count readout
proportional to temperature.

The internal sequencer has two monitor outputs (monitor0
and monitor1) that can be used to communicate the internal
states from the sequencer. A three−bit register configures theassignment of the pins as shown in Table 30.

Input from the SPI:

The reg_tempd_enable is a global enable and this enables
or disables the temperature sensor when logic high or logic
low respectively. The temperature sensor is reset or disabled
when the input reg_tempd_enable is set to a digital low state.

Table 30. REGISTER SETTING FOR THE MONITOR SELECT PIN
monitor_select [2:0]192 [13:11]

monitor pin

0x0

monitor0
monitor1

‘0’
‘0’

0x1

monitor0
monitor1

Integration TimeROT Indication (‘1’ during ROT, ‘0’ outside)

0x2

monitor0
monitor1

Integration Time
Dual/Triple Slope Integration (asserted during DS/TS FOT sequence)

0x3

monitor0
monitor1

Start of x−Readout Indication
Black Line Indication (‘1’ during black lines, ‘0’ outside)

0x4

monitor0
monitor1

Frame Start Indication
Start of ROT Indication

0x5

monitor0
monitor1

First Line Indication (‘1’ during first line, ‘0’ for all others)
Start of ROT Indication

0x6

monitor0
monitor1

ROT Indication (‘1’ during ROT, ‘0’ outside)
Start of X−Readout Indication

0x7

monitor0
monitor1

Start of X−readout Indication for Black Lines
Start of X−readout Indication for Image Lines

Description

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NOIP1SN5000ADATA OUTPUT FORMATThe frame format in 10−bit mode is explained by exampleof the readout of two (overlapping) windows as shown in
Figure 32(a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top.
Figure 32 indicates that, after the FOT is completed, thesensor reads out a number of black lines for black calibration
purposes. After these black lines, the windows areprocessed. First a number of lines which only includes
information of ‘ROI 0’ are sent out, starting at position
y0_start. When the line at position y1_start is reached, anumber of lines containing data of ‘ROI 0’ and ‘ROI 1’ aresent out, until the line position of y0_end is reached. From
there on, only data of ‘ROI 1’ appears on the data output
channels until line position y1_end is reached
During read out of the image data over the data channels,
the sync channel sends out frame synchronization codes
which give information related to the image data that is sent
over the four data output channels.
Each line of a window starts with a Line Start (LS)indication and ends with a Line End (LE) indication. Theline start of the first line is replaced by a Frame Start (FS);the line end of the last line is replaced with a Frame End
indication (FE). Each such frame synchronization code isfollowed by a window ID (range 0 to 7). For overlapping
windows, the line synchronization codes of the overlapping
windows with lower IDs are not sent out (as shown in theillustration: no LE/FE is transmitted for the overlapping partof window 0).
NOTES: In Figure 32, only Frame Start and Frame End
Sync words are indicated in (b). CRC codes arealso omitted from the figure.

The PYTHON 2000 and PYTHON 5000 image sensors
are available in two LVDS output configuration,
P1−SN/SE/FN and P3−SN/SE. The P1−SN/SE/FN
configuration utilizes eight LVDS output channels together
with an LVDS clock output and an LVDS synchronization
output channel. The P3−SN/SE configuration consists offour LVDS output channels together with an LVDS clock
output and an LVDS synchronization output channel.
P1−SN/SE/FN, P3−SN/SE: Interface Version
LVDS Output Channels

The image data output occurs through eight LVDS datachannels where a synchronization LVDS channel and an
LVDS output clock signal synchronizes the data.
Referring to Table 21, the eight data channels on the
P1−SN/SE/FN option are used to output the image data only,
while on the P3−SN/SE option, four data channel channels
are utilized. The sync channel transmits information about
the data sent over these data channels (includes codesindicating black pixels, normal pixels, and CRC codes).
8−bit / 10−bit Mode

The sensor can be used in 8−bit or 10−bit mode.
In 10−bit mode, the words on data and sync channel havea 10−bit length. The output data rate is 720 Mbps.
In 8−bit mode, the words on data and sync channel havean 8−bit length, the output data rate is 576 Mbps.
Note that the 8−bit mode can only be used to limit the data
rate at the consequence of image data word depth. It is notsupported to operate the sensor in 8−bit mode at a higher
clock frequency to achieve higher frame rates. The
P1−SN/SE/FN option supports 10−bit/8−bit in
ZROT/NZROT mode, while the P3−SN/SE option supports
10−bit NZROT mode only.

For additional information on thesynchronization codes, please refer to PYTHON
Image Sensor Family Developer’s Guide
AND9362/D.

Frame Format

The frame format in 8−bit mode is identical to the 10−bit
mode with the exception that the Sync and data word depth
is reduced to eight bits.

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NOIP1SN5000A

y1_endROI 1

y0_endy1_start
ROI 0

y0_start

x0_start

x0_endx1_start

x1_end(a)Integration Time
Handling
Readout
Handling

FOT

É
É
B
L

Reset
N

Exposure Time N

FOT

Readout Frame N-1
ROI
1

ROI 0

FS0

FS1

FOT

FE1

Reset
N+1

É
É
B
L

Exposure Time N+1

FOT

Readout Frame N
ROI
1

ROI 0

FS0

FS1

FOT

FE1

(b)
Figure 32. P1−SN/SE/FN, P3−SN/SE: Frame Sync Codes

Figure 33 shows the detail of a black line readout during global or full−frame readout.
Sequencer
Internal State

FOT

ROT

ROT

black

line Ys

ROT

ROTline Ys+1

line Yedata channels
sync channel

data channels

Training

sync channelTR

Training

LSBL

timeslot0timeslot
1

BL

BL

BL

timeslot157

BL

timeslot
158

BL

LE

CRC

timeslot
159

CRC
timeslotTR

Figure 33. P1−SN/SE/FN, P3−SN/SE: Time Line for Black Line Readout

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NOIP1SN5000A
Figure 34 shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.
Sequencer
Internal State

FOT

ROT

black

ROT

line Ys+1

ROTline Ysline Ye

ROT

data channels
sync channel

data channels

Training

sync channelTR

TrainingFS

ID

timeslot
Xstart

IMG

IMG

IMG

timeslot
Xstart + 1

IMG

timeslot
Xend - 2

IMG

IMG

timeslot
Xend - 1

ID

LE

CRC

timeslot
Xend

TR

CRC
timeslot

Figure 34. P1−SN/SE/FN, P3−SN/SE: Time Line for Single Window Readout (at the start of a frame)

Figure 35 shows the detail of the readout of a number of lines for readout of two overlapping windows.
Sequencer
Internal State

FOT

ROT

ROT

black

line Ys

ROT

ROTline Ys+1

line Yedata channels
sync channel

data channels

Training

sync channelTR

Training

LS

IDM

IMG

IMG

LS

timeslot
XstartM

IDN

IMG

IMG

IMG LE

timeslot
XstartN

IDN

CRC

TR

timeslot
XendN

Figure 35. P1−SN/SE/FN, P3−SN/SE: Time Line Showing the Readout of Two Overlapping Windows
Frame Synchronization for 10−bit Mode

active at the same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.

Table 31 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable) for 10−bit mode. If more than one window isTable 31. FRAME SYNCHRONIZATION CODE DETAILS FOR 10−BIT MODE
Sync Word Bit
Position

Register
Address

Default Value

9:7

N/A

0x5

Frame start (FS) indication

9:7

N/A

0x6

Frame end (FE) indication

9:7

N/A

0x1

Line start (LS) indication

Description

9:7

N/A

0x2

Line end (LE) indication

6:0

117[6:0]

0x2A

These bits indicate that the received sync word is a frame synchronization code. The value is programmable by a register setting

number, ranging from 0 to 15, indicating the active window.
If more than one window is active for the current cycle, thehighest window ID is transmitted.

Window Identification
Frame synchronization codes are always followed by a
4−bit window identification (bits 3:0). This is an integer

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NOIP1SN5000A(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 32.

Data Classification Codes
For the remaining cycles, the sync channel indicates thetype of data sent through the data links: black pixel data

Table 32. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 10−BIT MODE
Sync Word Bit
Position

Register Address

Default Value

9:0

118 [9:0]

0x015

Black pixel data (BL). This data is not part of the image. The black pixel data is usedinternally to correct channel offsets.

9:0

119 [9:0]

0x035

Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the image).

9:0

125 [9:0]

0x059

CRC value. The data on the data output channels is the CRC code of the finished image data line.

9:0

126 [9:0]

0x3A6

Training pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.

Description

Frame Synchronization in 8−bit Modeand not sent out. Table 32 shows the structure of the frame
synchronization code, together with the default value, as
specified in SPI registers. The same restriction foroverlapping windows applies in 8−bit mode.

The frame synchronization words are configured using
the same registers as in 10−bit mode. The two leastsignificant bits of these configuration registers are ignored

Table 33. FRAME SYNCHRONIZATION CODE DETAILS FOR 8−BIT MODE
Sync Word Bit
Position

Register Address

Default Value

7:5

N/A

0x5

Frame start (FS) indication

7:5

N/A

0x6

Frame end (FE) indication

7:5

N/A

0x1

Line start (LS) indication

Description

7:5

N/A

0x2

Line end (LE) indication

4:0

117 [6:2]

0x0A

These bits indicate that the received sync word is a frame synchronization code.
The value is programmable by a register setting.

Data Classification Codes
BL, IMG, CRC, and TR codes are defined by the sameregisters as in 10−bit mode. Bits 9:2 of the respective
configuration registers are used as classification code withdefault values shown in Table 34.

Window Identification
Similar to 10−bit operation mode, the frame
synchronization codes are followed by a window
identification. The window ID is located in bits 5:2 (all otherbit positions are ‘0’). The same restriction for overlapping
windows applies in 8−bit mode.

Table 34. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 8−BIT MODE
Sync Word Bit
Position

Register Address

Default Value

7:0

118 [9:2]

0x05

Black pixel data (BL). This data is not part of the image. The black pixel data is usedinternally to correct channel offsets.

7:0

119 [9:2]

0x0D

Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the image).

7:0

125 [9:2]

0x16

CRC value. The data on the data output channels is the CRC code of the finished image data line.

7:0

126 [9:2]

0xE9Training Pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.

Description

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NOIP1SN5000A
Training Patterns on Data Channels

In 10−bit mode, during idle periods, the data channels
transmit training patterns, indicated on the sync channel by
a TR code. These training patterns are configurable

independent of the training code on the sync channel asshown in Table 35.

Table 35. TRAINING CODE ON SYNC CHANNEL IN 10−BIT MODE
Sync Word Bit
Position

Register Address

Default
Value

[9:0]

116 [9:0]

0x3A6

Description
Data channel training pattern. The data output channels send out the training pattern, which can be
programmed by a register setting. The default value of the training pattern is 0x3A6, which is identicalto the training pattern indication code on the sync channel.

In 8−bit mode, the training pattern for the data channels isdefined by the same register as in 10−bit mode, where thelower two bits are omitted; see Table 36.
Table 36. TRAINING PATTERN ON DATA CHANNEL IN 8−BIT MODE
Data Word Bit
Position

Register Address

Default
Value

[7:0]

116 [9:2]

0xE9

Description
Data Channel Training Pattern (Training pattern).

Cyclic Redundancy Codeat the start of a new line and updated for every (valid) data
word received. The CRC seed is configurable using the
crc_seed register. When ‘0’, the CRC is seeded by all−‘0’;when ‘1’ it is seeded with all−‘1’.
In 8−bit mode, the polynomial is x8 + x6 + x3 + x2 + 1.
The CRC seed is configured by means of the crc_seed
register.
NOTE: The CRC is calculated for every line. Thisimplies that the CRC code can protect lines frommultiple windows.

At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channeltransmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are notincluded in the calculation.
The sync channel is not protected. A special character(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
The polynomial in 10−bit operation mode isx10 + x9 + x6 + x3 + x2 + x + 1. The CRC encoder is seeded

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44

NOIP1SN5000A
Data Order for P1−SN/SE/FN, P3−SN/SE

Figure 36 indicates how the kernels are organized. The firstkernel (kernel [0, 0]) is located in the bottom left corner(front view on top of the package). The data order of thisimage data on the data output channels depends on thesubsampling mode.

To read out the image data through the output channels,
the pixel array is organized in kernels. The kernel size issixteen pixels in x−direction by one pixel in y−direction. The
data order in 8−bit mode is identical to the 10−bit mode.

kernel(161,2047)

pixel array

ROI
kernel(x_start,y_start)kernel
(0,0)

0

1

2

3

13

14

15

Figure 36. Kernel Organization in Pixel Array − Top View

• P1−SN/SE/FN, P3−SN/SE: Subsampling Disabled

Figure 37 shows how a kernel is read out over the eight
output channels. For even positioned kernels, the kernels areread out ascending, while for odd positioned kernels the data
order is reversed (descending).

♦ 8 LVDS Output Channels (P1−SN/SE/FN only)
The image data is read out in kernels of 16 pixels in
x−direction by one pixel in y−direction. One data channel
output delivers two pixel values of one kernel sequentially.

kernel N−2

kernel N−1

kernel N

kernel N+1

3

4

11

12

13

14

15

pixel # (odd kernel)

15

14

13

12

11

4

3

2

1

0

MSB

LSB

MSB

channel #7

2channel #6

1channel #1

0channel #0

pixel # (even kernel)

LSB
Note: The bit order is always MSB first10−bit10−bitFigure 37. P1−SN/SE/FN: 8 LVDS Data Output Order when Subsampling is Disabled

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45

NOIP1SN5000A♦ 4 LVDS Output Channels
Figure 38 shows how a kernel is read out over the four
output channels. For even positioned kernels, the kernels are
kernel N−2

kernel N−1

read out ascending but in pair of even and odd pixels, while
for odd positioned kernels, the data order is reversed(descending − in pair of even and odd pixels).

kernel N

kernel N+1

3

4

6

5

7

8

10

9

11

12

14

13

15

pixel # (odd kernel)

15

13

14

12

11

9

10

8

7

5

6

4

3

1

2

0

MSB

LSB

MSB

channel #6

1channel #4

2channel #2

0channel #0

pixel # (even kernel)

LSB
Note: The bit order is always MSB first10−bit10−bitFigure 38. P1−SN/SE/FN, P3−SN/SE: 4 LVDS Data Output Order when Subsampling is Disabled♦ 2 LVDS Output Channels
Figure 39 shows how a kernel is read out over 2 output
channels. Each group of four adjacent channels is
multiplexed on to one channel. For even positioned kernels,
kernel N−2

kernel N−1

the kernels are read out in an ascending order but in sets offour even and four odd pixels, while for odd positioned
kernels the data order is reversed (descending and in sets offour odd and four even pixels).

kernel N

kernel N+1

2

4

6

1

3

5

7

8

10

12

14

9

11

13

15

pixel # (odd kernel)

15

13

11

9

14

12

10

8

7

5

3

1

6

4

2

0

MSB

LSB

10−bitchannel #4

0channel #0

pixel # (even kernel)

MSB

LSB

10−bitNote: The bit order is always MSB first

Figure 39. P1−SN/SE/FN, P3−SN/SE: 2 LVDS Data Output Order when Subsampling is Disabled

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46

NOIP1SN5000A♦ 1 LVDS Output Channel
Figure 40 shows how a kernel is read out over 1 output
channel. Eight adjacent channels are multiplexed into one
channel. For even positioned kernels, the kernels are readkernel N−2

kernel N−1

out ascending but in sets of 8 even and 8 odd pixels, while
for odd positioned kernels the data order is reversed(descending − in sets of 8 odd and 8 even pixels).

kernel N

kernel N+1

0

2

4

6

8

10

12

14

1

3

5

7

9

11

13

15

pixel # (odd kernel)

15

13

11

9

7

5

3

1

14

12

10

8

6

4

2

0

channel #0

pixel # (even kernel)

MSB

MSB

LSB

LSB
Note: The bit order is always MSB first10−bit10−bitFigure 40. P1−SN/SE/FN, P3−SN/SE: 1 LVDS Data Output Order when Subsampling is Disabled• P1−SN/FN, P3−SN: Subsampling on Monochrome

Only the pixels at the even pixel positions inside that kernel
are read out.
♦ 8 LVDS Output Channels (P1−SN/FN only)
Figure 41 shows the data order for 8 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the‘no−subsampling’ readout described in previous section.

26

6

24

8

22

10

20

12

18

14

16

channel #7

4

kernel N+1

channel #5

28

channel #4

2

kernel N

channel #3

30channel #1

0channel #0

pixel #

kernel N−1

channel #2

kernel N−2

channel #6

SensorDuring subsampling on a monochrome sensor, every
other pixel is read out and the lines are read in aread-1-skip-1 manner. To read out the image data with
subsampling enabled on a monochrome sensor, twoneighboring kernels are combined to a single kernel of
32 pixels in the x−direction and one pixel in the y−direction.

Figure 41. P1−SN/FN: Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Monochrome
Sensor

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47

NOIP1SN5000A

2

30

28

4

6

kernel N

26

24

8

kernel N+1

10channel #2

0channel #0

pixel #

kernel N−1

22

20

12

14

channel #4

kernel N−2

even/odd kernel numbers, as opposed to the‘no−subsampling’ readout described in previous section.

18

16

channel #6♦ 4 LVDS Output Channels
Figure 42 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for

Figure 42. P1−SN/FN, P3−SN: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor♦ 2 LVDS Output Channels
Figure 43 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for

0

2

4

6

30

28

kernel N

26

24

8

kernel N+1

10

12channel #0

pixel #

kernel N−1

14

22

20

18

16

channel #4

kernel N−2

even/odd kernel numbers, as opposed to the‘no−subsampling’ readout described in previous section.

Figure 43. P1−SN/FN, P3−SN: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor♦ 1 LVDS Output Channel
Figure 44 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order forkernel N−202

kernel N−1

4

6

8

10

kernel N

12

14

30

kernel N+1

28

26

24

22

20

18

16

channel #0

pixel #

even/odd kernel numbers, as opposed to the‘no−subsampling’ readout described in previous section.

Figure 44. P1−SN/FN, P3−SN: Data Output Order for 1 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor

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48

NOIP1SN5000A• P1−SN/FN, P3−SN: Binning on Monochrome Sensor

kernels are combined to a single kernel of 16 pixels in thex−direction and one pixel in the y−direction. Only the pixels
0, 1, 4, 5, 8, 9, … 28, 29 are read out.
♦ 8 LVDS Output Channels (P1−SE only)
Figure 45 shows the data order for 8 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the‘no−subsampling’ readout described in previous section.

During subsampling on a color sensor, lines are read in aread-2-skip−2 manner. To read out the image data with
subsampling enabled on a color sensor, two neighboring

4

25

5

24

8

21

9

20

12

channel #5

28

kernel N+1

channel #4

1

kernel N

channel #2

29channel #1

0channel #0

pixel #

kernel N−1

channel #3

kernel N−2

17

13

16

channel #7• P1−SE, P3−SE: Subsampling on Color Sensor

channel #6

The output order in binning mode is identical to thesubsampled mode.

Figure 45. P1−SE: Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Color Sensor♦ 4 LVDS Output Channels
Figure 46 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for

29

28

4

5

25

24

8

kernel N+1

9

21

20

12

13

17

16

channel #6

1

kernel N

channel #2

0channel #0

pixel #

kernel N−1

channel #4

kernel N−2

even/odd kernel numbers, as opposed to the‘no−subsampling’ readout described in previous section.

Figure 46. P1−SE, P3−SE: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Color Sensor♦ 2 LVDS Output Channels
Figure 47 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for

0

1

4

5

29

28

kernel N

25

24

8

channel #0

pixel #

kernel N−1

kernel N+1

9

12

13

21

20

17

16

channel #4

kernel N−2

even/odd kernel numbers, as opposed to the‘no−subsampling’ readout described in previous section.

Figure 47. P1−SE, P3−SE: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a Color Sensor

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49

NOIP1SN5000A♦ 1 LVDS Output Channel
Figure 48 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order forkernel N−201

kernel N−1

4

5

8

9

kernel N

12

13

29

kernel N+1

28

25

24

21

20

17

16

channel #0

pixel #

even/odd kernel numbers, as opposed to the‘no−subsampling’ readout described in previous section.

Figure 48. P1−SE, P3−SE: Data Output Order for 1 LVDS Output Channel in Subsampling Mode on a Color Sensor

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50

NOIP1SN5000A
REGISTER MAP
The table below represents the register map for theNOIP1xx5000A part. Deviating default values for theNOIP1xx2000A sensor are mentioned between brackets(“[ ]”).

Table 37. REGISTER MAP
Address
OffsetAddress

Default(Hex)

Default

chip_id

0x503220530

Chip ID

id

0x503220530

Chip ID

reserved

0x0001[0x0101]

1[257]

Reserved[3:0]

reserved

0x1

1

Reserved[9:8]

resolution

0x0 [0x1]

0 [1]Sensor Resolution‘0’: PYTHON 5000
‘1’: PYTHON 2000

[11:10]reserved

0x0

0Reserved

chip_configuration

0x00000Chip General Configuration

[0]

color

0x0

0

Colour/Monochrome Configuration‘0’: Monochrome‘1’: Color[3:2]

glob_config

0x00

Sensor pinout configuration[15:4]

reserved

0x000

0Reserved

Bit Field

Register Name

Description

Type

Chip ID [Block Offset: 0]0

0[15:0]

1

2

1

2

StatusStatusRW

Reset Generator [Block Offset: 8]018soft_reset_pll

0x0099153

PLL Soft Reset Configuration[3:0]

pll_soft_reset

0x9

9

PLL Reset
0x9: Soft Reset Stateothers: Operational[7:4]

pll_lock_soft_reset

0x9

9

PLL Lock Detect Reset
0x9: Soft Reset Stateothers: Operational

soft_reset_cgen

0x0009

9Clock Generator Soft Resetcgen_soft_reset

0x9

9Clock Generator Reset
0x9: Soft Reset Stateothers: Operational

soft_reset_analog

0x09992457

Analog Block Soft Reset[3:0]

mux_soft_reset

0x9

9Column MUX Reset
0x9: Soft Reset Stateothers: Operational[7:4]

afe_soft_reset

0x9

9

AFE Reset
0x9: Soft Reset Stateothers: Operational[11:8]

ser_soft_reset

0x9

9Serializer Reset
0x9: Soft Reset Stateothers: Operational

9
[3:0]

2

10

RW

RW

RW

PLL [Block Offset: 16]
0

1

16

power_down

0x0004

4

PLL Configuration

[0]

pwd_n

0x0

0

PLL Power Down‘0’: Power Down,‘1’: Operational[1]enable0x00

PLL Enable‘0’: disabled,‘1’: enabled[2]

bypass0x1

1

PLL Bypass‘0’: PLL Active,‘1’: PLL Bypassed

reserved

0x2113

8467

Reserved

reserved

0x13

19

Reserved

17[7:0]

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51

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

Bit Field

Register Name

Default(Hex)

Default

Description[12:8]

reserved

0x1

1

Reserved[14:13]

reserved

0x1

1

ReservedType

I/O [Block Offset: 20]
020

config1

0x00000

IO Configuration[0]

clock_in_pwd_n

0x0

0Power down Clock Input[9:8]

reserved

0x0

0Reserved[10]

reserved

0x0

0Reserved

pll_lock

0x00000

PLL Lock Indication

lock

0x0

0

PLL Lock Indication

reserved

0x22808832

ReservedRW

PLL Lock Detector [Block Offset: 24]
0

24
[0]

2

3

26
[7:0]

reserved

0x80

128

Reserved[10:8]

reserved

0x2

2

Reserved[14:12]

reserved

0x2

2

Reserved

reserved

0x3D2D

15661

Reserved[7:0]

reserved

0x2D

45

Reserved[15:8]

reserved

0x3D

61

Reserved

27

StatusRW

RW

Clock Generator [Block Offset: 32]
032

config00x0004

4

Clock Generator Configuration[0]

enable_analog

0x00

Enable analogue clocks‘0’: disabled,‘1’: enabled[1]enable_log

0x00

Enable logic clock‘0’: disabled,‘1’: enabled[2]

select_pll

0x1

1

Input Clock Selection‘0’: Select LVDS clock input,‘1’: Select PLL clock input[3]

adc_mode

0x00

Set operation mode of CGEN block‘0’: divide by 5 mode (10−bit mode),‘1’: divide by 4 mode (8−bit mode)

[5:4]

mux

0x0

0

Multiplex Mode

[11:8]

reserved

0x0

0Reserved[14:12]

reserved

0x0

0Reserved

config00x00000

Clock Generator Configuration

enable0x0

0Logic General Enable Configuration‘0’: Disable‘1’: Enable

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

image_core_config0

0x0000

0

Image Core Configuration

imc_pwd_n

0x0

0Image Core Power Down‘0’: powered down,‘1’: powered up

RW

General Logic [Block Offset: 34]
0

34
[0]

0

38
[15:0]

1

39[15:0]RW

RW

RW

Image Core [Block Offset: 40]
0

40
[0]

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52

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
Offset12

3

Address

Bit Field

Register Name

Default(Hex)

Default

Description[1]

mux_pwd_n

0x0

0Column Multiplexer Power Down‘0’: powered down,‘1’: powered up[2]

colbias_enable

0x00Bias Enable‘0’: disabled‘1’: enabled

image_core_config1

0x0B5A

2906

Image Core Configuration[3:0]

dac_ds0xA

10Double Slope Reset Level[7:4]

dac_ts0x5

5

Triple Slope Reset Level41[10:8]

reserved

0x3

3

Reserved[12:11]reserved

0x1

1

Reserved[13]

reserved

0x0

0Reserved[14]

reserved

0x0

0Reserved[15]

reserved

0x0

0Reserved

42

reserved

0x0001

1

Reserved[0]

reserved

0x1

1

Reserved[1]

reserved

0x0

0Reserved[6:4]

reserved

0x0

0Reserved[10:8]

reserved

0x0

0Reserved[15:12]

reserved

0x0

0Reserved

reserved

0x00000Reserved[0]

reserved

0x0

0Reserved[1]

reserved

0x0

0Reserved[2]

reserved

0x0

0Reserved

43[3]

reserved

0x0

0Reserved[6:4]

reserved

0x0

0Reserved[7]

reserved

0x0

0Reserved[15:8]

reserved

0x0

0Reserved

power_down

0x00000

AFE Configuration

pwd_n

0x0

0

Power down for AFE’s‘0’: powered down,‘1’: powered up

power_down

0x00000Bias Power Down Configuration

pwd_n

0x0

0

Power down bandgap‘0’: powered down,‘1’: powered up

configuration

0x888B

34955

Bias Configuration[0]

extres0x1

1

External Resistor Selection‘0’: internal resistor,‘1’: external resistor[3:1]

reserved

0x5

5

Reserved[7:4]

reserved

0x8

8

Reserved[11:8]

reserved

0x8

8

Reserved[15:12]

reserved

0x8

8

Reserved

Type

RW

RW

RW

AFE [Block Offset: 48]
0

48
[0]

RW

Bias [Block Offset: 64]
0

64
[0]

1

2

65

66

reserved

0x53C821448

Reserved[3:0]

reserved

0x8

8

Reserved[7:4]

reserved

0xC

12

Reserved

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53

RW

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

Bit Field[14:8]

3

4

5

6

7

67

Default(Hex)

Default

reserved

0x53

83

Reserved

Register Name

Description

reserved

0x888834952

Reserved[3:0]

reserved

0x8

8

Reserved[7:4]

reserved

0x8

8

Reserved[11:8]

reserved

0x8

8

Reserved[15:12]

reserved

0x8

8

Reserved68

lvds_bias

0x0088136

LVDS Bias Configuration[3:0]

lvds_ibias

0x8

8

LVDS Ibias[7:4]

lvds_iref

0x8

8

LVDS Iref

reserved

0x08882184

Reserved[3:0]

reserved

0x8

8

Reserved[7:4]

reserved

0x8

8

Reserved[11:8]

reserved

0x8

8

Reserved

69

70

reserved

0x888834952

Reserved[3:0]

reserved

0x8

8

Reserved[7:4]

reserved

0x8

8

Reserved[11:8]

reserved

0x8

8

Reserved[15:12]

reserved

0x8

8

Reserved

reserved

0x888834952

Reserved

reserved

0x888834952

Reserved71[15:0]

Type

RW

RW

RW

RW

RW

Charge Pump [Block Offset: 72]
072

configuration

0x22208736

Charge Pump Configuration[0]trans_pwd_n

0x00

PD Trans Charge Pump Enable‘0’: disabled,‘1’: enabled[1]

resfd_calib_pwd_n

0x00

FD Charge Pump Enable‘0’: disabled,‘1’: enabled[2]

sel_sample_pwd_n0x0

0Select/Sample Charge Pump Enable‘0’: disabled‘1’: enabled[6:4]

reserved

0x2

2

Reserved[10:8]

reserved

0x2

2

Reserved[14:12]

reserved

0x2

2

Reserved

RW

Charge Pump [Block Offset: 80]
0

1

80

reserved

0x00000Reserved[1:0]

reserved

0x0

0Reserved[3:2]

reserved

0x0

0Reserved[5:4]

reserved

0x0

0Reserved[7:6]

reserved

0x0

0Reserved[9:8]

reserved

0x0

0Reserved

reserved

0x8881

34945

Reserved

reserved

0x8881

34945

Reservedenable0x00000Temperature Sensor Configuration

enable0x0

0Temperature Diode Enable‘0’: disabled,‘1’: enabled81[15:0]RW

RW

Temperature Sensor [Block Offset: 96]
0

96
[0]

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54

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
Offset1

Address

Bit Field

Register Name

Default(Hex)

Default

Description[1]

reserved

0x0

0Reserved[2]

reserved

0x0

0Reserved[3]

reserved

0x0

0Reserved[4]

reserved

0x0

0Reserved[5]

reserved

0x0

0Reserved[13:8]

offset0x0

0Temperature Offset (signed)

temp

0x00000Temperature Sensor Status

temp

0x00

0

Temperature Readout

reserved

0x00000Reserved

reserved

0x0

0Reserved

97
[7:0]

Type

StatusTemperature Sensor [Block Offset: 104]0

104
[15:0]

1

2

105

reserved

0x00000Reserved[1:0]

reserved

0x0

0Reserved[6:2]

reserved

0x0

0Reserved[7]

reserved

0x0

0Reserved[9:8]

reserved

0x0

0Reserved[14:10]reserved

0x0

0Reserved[15]

reserved

0x0

0Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

106[15:0]

3

107

4

108

5

109

[15:0][15:0][15:0]
6110[15:0]

7111[15:0]RW

RW

StatusStatusStatusStatusStatusStatusSerializers / LVDS / IO [Block Offset: 112]0

112

power_down

0x00000

LVDS Power Down Configuration[0]

clock_out_pwd_n

0x0

0Power down for Clock Output.
‘0’: powered down,‘1’: powered up[1]

sync_pwd_n

0x0

0Power down for Sync channel‘0’: powered down,‘1’: powered up[2]

data_pwd_n

0x0

0Power down for data channels (4 channels)‘0’: powered down,‘1’: powered up

trainingpattern

0x03A6934

Data Formating − Training Patterntrainingpattern

0x3A6

934

Training pattern sent on Data channels duringidle mode. This data is used to perform wordalignment on the LVDS data channels.

sync_code00x002A

42

LVDS Power Down Configuration

frame_sync_0

0x02A

42

Frame Sync Code LSBs − Even kernels

RW

Sync Words [Block Offset: 116]
4

116
[9:0]

5

117
[6:0]

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55

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

6

118
[9:0]

7

119
[9:0]

8

120
[9:0]

9

121
[6:0]

10

122
[9:0]

11

123
[9:0]

12

124
[9:0]

13

125

14

126

15

127

Default(Hex)

Default

sync_code1

0x001521

Data Formating − BL Indication

bl_0

0x015

21

Black Pixel Identification Sync Code − Evenkernelssync_code2

0x003553

Data Formating − IMG Indication

img_0

0x035

53

Valid Pixel Identification Sync Code − Evenkernelssync_code3

0x002537

Data Formating − IMG Indication

ref_0

0x025

37

Reference Pixel Identification Sync Code −Even kernels

sync_code4

0x002A

42

LVDS Power Down Configuration

frame_sync_1

0x02A

42

Frame Sync Code LSBs − Odd kernels

sync_code50x001521

Data Formating − BL Indication

bl_1

0x015

21

Black Pixel Identification Sync Code − Odd
kernelssync_code6

0x003553

Data Formating − IMG Indication

img_1

0x035

53

Valid Pixel Identification Sync Code − Odd
kernelssync_code7

0x002537

Data Formating − IMG Indication

ref_1

0x025

37

Reference Pixel Identification Sync Code −Odd kernels

sync_code8

0x005989

Data Formating − CRC Indication

crc

0x059

89

CRC Value Identification Sync Code

sync_code9

0x03A6934

Data Formating − TR Indication

tr

0x3A6

934

Training Value Identification Sync Codereserved

0x02AA

682

Reserved

reserved

0x2AA

682

Reserved

blackcal

0x400816392

Black Calibration Configuration

Bit Field

[9:0]

[9:0]

[9:0]

Register Name

Description

Type
RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Data Block [Block Offset: 128]
0

1

128
[7:0]

black_offset

0x08

8

Desired black level at output[10:8]

black_samples

0x00Black pixels taken into account for black calibration.
Total samples = 2**black_samples[14:11]reserved

0x8

8

Reserved[15]

crc_seed

0x0

0

CRC Seed‘0’: All−0‘1’: All−1

general_configuration

0x0001

1Black Calibration and Data Formating
Configuration[0]

auto_blackcal_enable

0x1

1

Automatic blackcalibration is enabled when 1,
bypassed when 0[9:1]

blackcal_offset

0x00

0

Black Calibration offset used when auto_black_cal_en = ‘0’.

[10]

blackcal_offset_dec

0x0

0

blackcal_offset is added when 0, subtracted
when 1129[11]

reserved

0x0

0Reserved[12]

reserved

0x0

0Reserved[13]

8bit_mode

0x0

0

Shifts window ID indications by 4 cycles.
‘0’: 10 bit mode,‘1’: 8 bit mode[14]

ref_mode

0x00Data contained on reference lines:‘0’: reference pixels‘1’: black average for the corresponding datachannelwww.onsemi.com
56

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

Bit Field
[15]

2

8

130

139

12

140

15

Reserved

1

Reserved[1]

reserved

0x1

1

Reserved[2]

reserved

0x1

1

Reserved[3]

reserved

0x1

1

Reserved[4]

reserved

0x0

0Reserved[8]

reserved

0x0

0Reserved

blackcal_error00x00000Black Calibration Status

blackcal_error[15:0]

0x00000Black Calibration Error. This flag is set when
not enough black samples are available.
Black Calibration shall not be valid. Channels
0−16

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0xFFFF

65535

Reserved

reserved

0xFFFF

65535

Reserved[15:0][15:0]
141[15:0]
16

144

17

145

18

146

test_configuration

0x00000Data Formating Test Configuration[0]

testpattern_en

0x00

Insert synthesized testpattern when ‘1’[1]

inc_testpattern

0x0

0

Incrementing testpattern when ‘1’, constant
testpattern when ‘0’[2]

prbs_en0x0

0Insert PRBS when ‘1’[3]

frame_testpattern

0x0

0

Frame test patterns when ‘1’, unframed testpatterns when ‘0’[4]

reserved

0x0

0Reserved

reserved

0x00000Reserved[15:0]

19

Enable black calibration on reference lines‘0’: Disabled‘1’: Enabled

0x1[15:0]

1300x000F[15:0]

11

0x0

reserved

137

138

ref_bcal_enable

Description

reserved

136

10

Default[0][15:0]

9

Default(Hex)

Register Name0

Reserved

test_configuration00x0100256

Data Formating Test Configuration[7:0]

testpattern0_lsb

0x00

0

Testpattern used on datapath #0 when
testpattern_en = ‘1’.
Note: Most significant bits are configured inregister 150.

[15:8]

testpattern1_lsb

0x01

1

Testpattern used on datapath #1 when
testpattern_en = ‘1’.
Note: Most significant bits are configured inregister 150.

test_configuration1

0x0302

770

Data Formating Test Configuration

testpattern2_lsb

0x02

2

Testpattern used on datapath #2 when
testpattern_en = ‘1’.
Note: Most significant bits are configured inregister 150.

147
[7:0]

reserved

www.onsemi.com
57

Type

RW

StatusStatusStatusStatus

RW

RW

RW

RW

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

Bit Field[15:8]

20

21

22

26

148

Default

testpattern3_lsb

0x03

3

Testpattern used on datapath #3 when
testpattern_en = ‘1’.
Note: Most significant bits are configured inregister 150.

Description

test_configuration2

0x05041284

Data Formating Test Configuration[7:0]

testpattern4_lsb

0x04

4

Testpattern used on datapath #4 when
testpattern_en = ‘1’.
Note: Most significant bits are configured inregister 150.

[15:8]

testpattern5_lsb

0x05

5

Testpattern used on datapath #5 when
testpattern_en = ‘1’.
Note: Most significant bits are configured inregister 150.

test_configuration3

0x0706

1798

Data Formating Test Configuration[7:0]

testpattern6_lsb

0x06

6

Testpattern used on datapath #6 when
testpattern_en = ‘1’.
Note: Most significant bits are configured inregister 150.

[15:8]

testpattern7_lsb

0x07

7

Testpattern used on datapath #7 when
testpattern_en = ‘1’.
Note: Most significant bits are configured inregister 150.

test_configuration16

0x00000Data Formating Test Configuration[1:0]

testpattern0_msb

0x0

0

Testpattern used when testpattern_en = ‘1’[3:2]

testpattern1_msb

0x0

0

Testpattern used when testpattern_en = ‘1’[5:4]

testpattern2_msb

0x0

0

Testpattern used when testpattern_en = ‘1’[7:6]

testpattern3_msb

0x0

0

Testpattern used when testpattern_en = ‘1’[9:8]

testpattern4_msb

0x0

0

Testpattern used when testpattern_en = ‘1’

149

150

[11:10]

testpattern5_msb

0x0

0

Testpattern used when testpattern_en = ‘1’[13:12]

testpattern6_msb

0x0

0

Testpattern used when testpattern_en = ‘1’[15:14]

testpattern7_msb

0x0

0

Testpattern used when testpattern_en = ‘1’

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved

reserved

0x00000Reserved154[15:0]

27

Default(Hex)

Register Name

155
[15:0]

Type

RW

RW

RW

RW

RW

AEC [Block Offset: 160]
0

1

2

160

configuration

0x001016

AEC Configuration[0]

enable0x0

0

AEC Enable[1]

restart_filter

0x0

0Restart AEC filter[2]

freeze0x0

0Freeze AEC filter and enforcer gains[3]

pixel_valid

0x00Use every pixel from channel when 0, every
4th pixel when 1[4]

amp_pri

0x1

1

Column amplifier gets higher priority than AFE
PGA in gain distribution if 1. Vice versa if 0

intensity

0x60B824760

AEC Configuration[9:0]

desired_intensity

0xB8

184

Target average intensity[15:10]reserved

0x018

24

Reserved

red_scale_factor

0x0080128

Red Scale Factor

red_scale_factor

0x80

128

Red Scale Factor
3.7 unsigned

161

162
[9:0]

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58

RW

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress3

163

Bit Field

[9:0]
4

164
[9:0]

5

165
[9:0]

6

166
[15:0]

7

167

8

168

9

169

12

13

14

Green1 Scale Factor

green1_scale_factor

0x80

128

Green1 Scale Factor
3.7 unsigned

green2_scale_factor

0x0080128

Green2 Scale Factor

green2_scale_factor

0x80

128

Green2 Scale Factor
3.7 unsigned

blue_scale_factor

0x0080128

Blue Scale Factor

blue_scale_factor

0x80

128

Blue Scale Factor
3.7 unsigned

reserved

0x03FF

1023

Reserved

reserved

0x03FF

1023

Reserved

2048

Reserved

0

Reserved[3:2]

reserved

0x0

0Reserved[15:4]

reserved

0x080

128

Reserved

min_exposure

0x0001

1Minimum Exposure Time

min_exposure

0x0001

1Minimum Exposure Time

min_gain

0x08002048

Minimum Gain

[1:0]

min_mux_gain

0x00

Minimum Column Amplifier Gain

[3:2]

min_afe_gain

0x00

Minimum AFE PGA Gain

[15:4]

min_digital_gain

0x080

128

Minimum Digital Gain
5.7 unsigned

max_exposure

0x03FF

1023

Maximum Exposure Time

max_exposure

0x03FF

1023

Maximum Exposure Time

max_gain

0x100D

4109

Maximum Gain

[1:0]

max_mux_gain

0x1

1

Maximum Column Amplifier Gain

[3:2]

max_afe_gain

0x3

3

Maximum AFE PGA Gain

[15:4]

max_digital_gain

0x100

256

Maximum Digital Gain
5.7 unsigned

reserved

0x0083131

Reserved[7:0]

reserved

0x083

131

Reserved[13:8]

reserved

0x00

0Reserved[15:14]

reserved

0x0

0Reserved

reserved

0x2824

10276

Reserved[7:0]

reserved

0x024

36

Reserved[15:8]

reserved

0x028

40

Reserved

reserved

0x2A96

10902

Reserved[3:0]

reserved

0x6

6

Reserved[7:4]

reserved

0x9

9Reserved[11:8]

reserved

0xA

10

Reserved[15:12]

reserved

0x2

2

Reserved

reserved

0x0080128

Reserved

reserved

0x080

128

Reserved

reserved

0x0100256

Reserved

reserved

0x100

256

Reserved

173

174

176

128

0x0

172

16

0x00800x0800171

175

green1_scale_factor

Description

reserved

170

15

Default

reserved[15:0]
11

Default
(Hex)

[1:0]

[15:0]

10

Register Name

[9:0]

[9:0]

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59

Type
RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

17

177

18

178

19

179

Default(Hex)

Default

reserved

0x0100256

Reserved

reserved

0x100

256

Reserved

reserved

0x0080128

Reserved

reserved

0x080

128

Reserved

reserved

0x00AA

170

Reserved

reserved

0x0AA

170

Reserved

reserved

0x0100256

Reserved

reserved

0x100

256

Reserved

reserved

0x0155341

Reserved

reserved

0x155

341

Reserved

total_pixels0

0x00000

AEC Status

total_pixels[15:0]

0x00000Total number of pixels sampled for Average,
LSB

total_pixels1

0x00000

AEC Status

total_pixels[23:16]

0x0

0

Total number of pixels sampled for Average,
MSB

average_status

0x00000

ASE Status[9:0]

average

0x000

0

AEC Average Status[12]

avg_locked

0x0

0

AEC Average Lock Status

exposure_status

0x00000

ASE Status

exposure

0x00000

AEC Expsosure Status

gain_status

0x00000

ASE Status[1:0]

mux_gain

0x0

0

AEC MUX Gain Status[3:2]

afe_gain

0x0

0

AEC AFE Gain Status[15:4]

digital_gain

0x000

0

AEC Digital Gain Status
5.7 unsigned

Bit Field

[9:0]

[9:0]

[9:0]
20

180
[9:0]

21

181
[9:0]

24

184
[15:0]

25

185
[7:0]

26

186

27

187

28

188

[15:0]

29

189

Register Name

Description

reserved

0x00000Reserved[12:0]

reserved

0x000

0Reserved[13]

reserved

0x0

0Reserved

general_configuration

0x00000

Sequencer General Cofniguration[0]

enable0x00Enable sequencer‘0’: Idle,‘1’: enabled[1]

reserved

0x0

0Reserved[2]

zero_rot_enable

0x0

0

Zero ROT mode Selection.
‘0’: Non−Zero ROT,
‘1’: Zero ROT’

[3]

reserved

0x0

0Reserved[4]

triggered_mode

0x00

Triggered Mode Selection (Snapshot Shutter
only)‘0’: Normal Mode,‘1’: Triggered Mode[5]

slave_mode

0x00

Master/Slave Selection (Snapshot Shutter
only)‘0’: master,‘1’: slave[6]

nzrot_xsm_delay_
enable0x00Insert delay between end of ROT and start ofreadout in Non−Zero ROT readout mode if ‘1’.
ROT delay is defined by register xsm_delay

Type
RW

RW

RW

RW

RW

StatusStatusStatusStatusStatusStatusSequencer [Block Offset: 192]
0192

www.onsemi.com
60

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
Offset12

Address

Bit Field

Register Name

Default(Hex)

Default

Description[7]

subsampling

0x00Subsampling mode selection‘0’: no subsampling,‘1’: subsampling[8]

binning

0x0

0

Binning mode selection‘0’: no binning,‘1’: binning[10]

roi_aec_enable

0x00

Enable windowing for AEC Statistics.
‘0’: Subsample all windows‘1’: Subsample configured window[13:11]monitor_select0x0

0Control of the monitor pins

[14]

reserved

0x0

0Reserved[15]

sequence0x00

Enable a sequenced readout with different
parameters for even and odd frames.

delay_configuration

0x00000

Sequencer delay configuration[7:0]

reserved

0x00

0Reserved[15:8]

xsm_delay

0x00

0Delay between ROT end and X−readout(Non−Zero ROT and Zero ROT mode)
Delay between ROT end and X−readout(Normal ROT mode withnzrot_xsm_delay_enable = ‘1’)

integration_control

0x00E4228

Integration Control[0]

dual_slope_enable

0x00

Enable Dual Slope[1]

triple_slope_enable

0x00

Enable Triple Slope[2]

fr_mode0x1

1

Representation of fr_length.
‘0’: reset length‘1’: frame length[3]

reserved

0x0

0Reserved[4]

int_priority

0x00Integration Priority‘0’: Frame readout has priority over integration‘1’: Integration End has priority over frame
readout[5]

halt_mode

0x1

1

The current frame will be completed when thesequencer is disabled and halt_mode = ‘1’.
When ‘0’, the sensor stops immediately whendisabled, without finishing the current frame.

[6]

fss_enable

0x1

1

Generation of Frame Sequence Start Sync
code (FSS)‘0’: No generation of FSS‘1’: Generation of FSS[7]

fse_enable

0x1

1

Generation of Frame Sequence End Sync
code (FSE)‘0’: No generation of FSE‘1’: Generation of FSE[8]reverse_y0x00Reverse readout‘0’: bottom to top readout‘1’: top to bottom readout[9]

reserved

0x0

0Reserved[11:10]subsampling_mode

0x00

Subsampling mode
0x0: Subsampling in x and y (VITA
compatible)
0x1: Subsampling in x, not y
0x2: Subsampling in y, not x
0x3: Subsampling in x an y

[13:12]

binning_mode

0x00

Binning mode
0x0: Binning in x and y (VITA compatible)
0x1: Binning in x, not y
0x2: Binning in y, not x
0x3: Binning in x an y[14]

reserved

0x0

0Reserved[15]

reserved

0x0

0Reserved

193

194

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61

Type

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

3

195

Default(Hex)

Default

roi_active0_0

0x0001

1

Active ROI Selection

roi_active0

0x01

1

Active ROI Selection[0] Roi0 Active[1] Roi1 Active...
[15] Roi15 Active

reserved

0x00000Reserved

reserved

0x00000Reserved

black_lines

0x0102258

Black Line Configuration[7:0]

black_lines

0x02

2

Number of black lines. Minimum is 1.
Range 1−255[12:8]

gate_first_line

0x1

1

Blank out first lines
0: no blank
1−31: blank 1−31 lines

reserved

0x00000Reserved

reserved

0x000

0Reserved

mult_timer00x0001

1

Exposure/Frame Rate Configuration

mult_timer00x0001

1Mult Timer
Defines granularity (unit = 1/PLL clock) of
exposure and reset_length

fr_length00x00000

Exposure/Frame Rate Configuration

fr_length00x0000

0

Frame/Reset length
Reset length when fr_mode = ‘0’,
Frame Length when fr_mode = ‘1’
Granularity defined by mult_timer

exposure0

0x00000

Exposure/Frame Rate Configuration

exposure0

0x00000

Exposure Time
Granularity defined by mult_timer

exposure_ds0

0x00000

Exposure/Frame Rate Configuration

exposure_ds0

0x00000

Exposure Time (Dual Slope)
Granularity defined by mult_timer

exposure_ts0

0x00000

Exposure/Frame Rate Configuration

exposure_ts0

0x00000

Exposure Time (Triple Slope)
Granularity defined by mult_timer

Bit Field[15:0]

4

196

5

197

[15:0]

6

198

7

199

[11:0][15:0]

8200[15:0]

9201[15:0]

10202[15:0]

11203[15:0]

12

204

13

205

14

206

Register Name

Description

gain_configuration0

0x01E3483

Gain Configuration[4:0]

mux_gainsw0

0x03

3

Column Gain Setting[12:5]

afe_gain0

0xF

15

AFE Programmable Gain Setting[13]

gain_lat_comp

0x00

Postpone gain update by 1 frame when ‘1’ tocompensate for exposure time updates
latency.
Gain is applied at start of next frame if ‘0’

digital_gain_
configuration00x0080128

Gain Configuration

db_gain0

0x080

128

Digital Gain

sync_configuration

0x037F

895

Synchronization Configuration[0]

sync_rs_x_length

0x1

1

Update of rs_x_length will not be sync’ed atstart of frame when ‘0’[1]

sync_black_lines

0x1

1

Update of black_lines will not be sync’ed atstart of frame when ‘0’[2]

sync_dummy_lines

0x1

1

Update of dummy_lines will not be sync’ed atstart of frame when ‘0’[3]

sync_exposure

0x1

1

Update of exposure will not be sync’ed at startof frame when ‘0’[4]

sync_gain

0x1

1

Update of gain settings (gain_sw, afe_gain)
will not be sync’ed at start of frame when ‘0’[11:0]

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62

Type
RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
Offset15

Address

Bit Field

1

Update of roi updates (active_roi) will not be
sync’ed at start of frame when ‘0’[6]sync_ref_lines

0x1

1

Update of ref_lines will not be sync’ed at startof frame when ‘0’[8]blank_roi_switch

0x1

1

Blank first frame after ROI switching[9]

blank_
subsampling_ss

0x1

1

Blank first frame after subsampling/binningmode switching‘0’: No blanking‘1’: Blanking[10]

exposure_sync_
mode

0x0

0

When ‘0’, exposure configurations are sync’ed
at the start of FOT. When ‘1’, exposure configurations sync is disabled (continuously
syncing). This mode is only relevant for
Triggered snapshot − master mode, where theexposure configurations are sync’ed at thestart of exposure rather than the start of FOT.
For all other modes it should be set to ‘0’.
Note: Sync is still postponed if
sync_exposure=‘0’.

ref_lines

0x00000Reference Line Configuration

ref_lines

0x00

0

Number of Reference Lines
0−255

roi_active0_1

0x0001

1

Active ROI Selection

roi_active1

0x01

1

Active ROI Selection[0] Roi0 Active[1] Roi1 Active...
[15] Roi15 Active

x_resolution

0x00A2[0x007C]

162
[124]

Sequencer Status

x_resolution

0x000A2[0x007C]

162
[124]

Sensor x resolution

y_resolution

0x0800[0x04F0]2048[1264]

Sequencer Status

y_resolution

0x0800[0x04F0]2048[1264]

Sensor y resolution

mult_timer_status

0x00000

Sequencer Status

mult_timer

0x00000Mult Timer Status (Master Snapshot Shutter
only)

reset_length_status

0x00000

Sequencer Status

reset_length

0x00000

Current Reset Length (not in Slave mode)

exposure_status

0x00000

Sequencer Status

exposure

0x00000

Current Exposure Time (not in Slave mode)

exposure_ds_status

0x00000

Sequencer Status

exposure_ds

0x00000

Current Exposure Time (not in Slave mode)

exposure_ts_status

0x00000

Sequencer Status

exposure_ts

0x00000

Current Exposure Time (not in Slave mode)

207

228

240

241
[12:0]

50

242[15:0]

51

243[15:0]

52

244

53

245

54

246

[15:0][15:0][15:0]
55

56

Description

0x1

[7:0]
49

Default

sync_roi

[7:0]

48

Default
(Hex)

[5]

[7:0]
36

Register Name

247

gain_status

0x00000

Sequencer Status[4:0]

mux_gainsw

0x00

0

Current Column Gain Setting[12:5]

afe_gain

0x00

0Current AFE Programmable Gain

digital_gain_status

0x00000

Sequencer Status[11:0]

db_gain

0x000

0Digital Gain[12]

dual_slope

0x00Dual Slope Enabled[13]

triple_slope

0x00

Triple Slope Enabled248

www.onsemi.com
63

Type

RW

RW

StatusStatusStatusStatusStatusStatusStatusStatusStatusNOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

61

253

62

Default(Hex)

Default

roi_aec_
configuration00x00000

AEC ROI Configuration[7:0]

x_start

0x00

0

AEC ROI X Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’)[15:8]

x_end

0x00

0

AEC ROI X End Configuration (used for AEC
statistics when roi_aec_enable=‘1’)

roi_aec_
configuration1

0x00000

AEC ROI Configuration

y_start

0x00000

AEC ROI Y Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’)

roi_aec_
configuration2

0x00000

AEC ROI Configuration

y_end

0x00000

AEC ROI Y End Configuration (used for AEC
statistics when roi_aec_enable=‘1’)

roi0_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi0_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi0_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

roi1_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi1_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi1_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

Bit Field

254[12:0]

63255[12:0]

Register Name

Description

Type
RW

RW

RW

Sequencer ROI [Block Offset: 256]
0

256

1

257

2

258

3

259

[12:0][12:0]

4

260

5

261

[12:0][12:0]
6

7262

roi2_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi2_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi2_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration263[12:0]

8264[12:0]

910265

roi3_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi3_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi3_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

roi4_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi4_configuration1

0x00000

ROI Configuration266[12:0]

11267[12:0]

12

13

268

269

www.onsemi.com
64

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

Bit Field[12:0]

14270[12:0]

15

16

271

19

23

279

24

280

26

282

x_end

0xA1

161

X End Configuration

roi5_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi5_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

roi6_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi6_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi6_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

roi7_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi7_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi7_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

roi8_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi8_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi8_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration[12:0][12:0]
27

28

283

roi9_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi9_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi9_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration284[12:0]

29285[12:0]

30

31

Y End Configuration[15:8][12:0]281

ROI Configuration

2047

X Start Configuration[12:0]

25

2047

0x7FF

ROI Configuration[12:0]

278

0x07FFy_end

0[12:0]

22

roi4_configuration2

41216

275

277

Y Start Configuration

0x00

274

21

0

0xA100273

276

0x0000x_start272

20

y_startDescription

roi5_configuration0[12:0]
18

Default[7:0][12:0]
17

Default(Hex)

Register Name286

roi10_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configurationroi10_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration287[12:0]

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65

Type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

NOIP1SN5000A
Table 37. REGISTER MAP
Address
OffsetAddress

32

288

33

289

Register Name

Default(Hex)

Default

roi10_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

roi11_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi11_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi11_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

roi12_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi12_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi12_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration

Bit Field[12:0]

34

290

35

291

36

292

[12:0][12:0]

37

293

38

294

[12:0][12:0]
3940

295

roi13_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi13_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi13_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration296[12:0]

41297[12:0]

42

43

298

roi14_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configuration

roi14_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configuration

roi14_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configurationroi15_configuration0

0xA10041216

ROI Configuration[7:0]

x_start

0x00

0

X Start Configuration[15:8]

x_end

0xA1

161

X End Configurationroi15_configuration1

0x00000

ROI Configuration

y_start

0x00000

Y Start Configurationroi15_configuration2

0x07FF

2047

ROI Configuration

y_end

0x7FF

2047

Y End Configuration299[12:0]

44300[12:0]

45

46

301

302
[12:0]

47

Description

303[12:0]

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66

Type
RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

NOIP1SN5000A
Selectable Pin−Out

Table 38. ALTERNATIVE PIN OUT OPTIONSThe PYTHON sensor has a built−in possibility to routesome of the internal signals to different pads at the side of thechip.
The pin−out is controlled by glob_config in thechip_configuration register, located at address 2. The two
possible pin outs in the 84 pin package are listed in Table 38.
By default, 0x3 setting is selected.

128−padLGA

8

D4

glob_config = 0x1

doutn1clock_outn

doutp1clock_outp

9D5

clock_outn

doutn114

G4

clock_outp

doutp1

15

G5

syncn

doutn6

29

H4

syncp

doutp630

H5doutn6

syncn

35

L4

doutp6

syncp

36

L5

www.onsemi.com
67

84−pinLCC

glob_config = 0x3

NOIP1SN5000A
Pin List

TIA/EIA−644−A Standard and the CMOS I/Os have 3.3 V
signal level. Table 39 and Table 40 show the pin list for the
LCC−84 and LGA−128 packages respectively.

The PYTHON 2000 and PYTHON 5000 image sensors
are available in LVDS output configuration (P1−SN/SE/FN,
P3−SN/SE). The LVDS I/Os comply to theTable 39. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LCC−84 PINS
Package Pin No.

Pin Name

I/O Type

Direction

Description1

vdd_33

Supply

2

nc

3

mosi

CMOS

Input

SPI Master Out − Slave In

4

miso

CMOS

Output

SPI Master In − Slave Out

5

sck

CMOS

Input

SPI Input Clock6

gnd_18Supply1.8 V Ground7

vdd_18Supply1.8 V Supply

8

doutn1

LVDS

Output

LVDS Data Output Channel #1 (Negative), Not connected for P3−SN/SE

9

doutp1

LVDS

Output

LVDS Data Output Channel #1 (Positive), Not connected for P3−SN/SE

10

doutn0

LVDS

Output

LVDS Data Output Channel #0 (Negative)

11

doutp0

LVDS

Output

LVDS Data Output Channel #0 (Positive)

12nc

3.3 V Supply
No connect

No connect

13

nc

14

clock_outn

LVDS

OutputNo connect
LVDS Clock Output (Negative)

15

clock_outp

LVDS

Output

LVDS Clock Output (Positive)

16

doutn2

LVDS

Output

LVDS Data Output Channel #2 (Negative)

17

doutp2

LVDS

Output

LVDS Data Output Channel #2 (Positive)

18

doutn3

LVDS

Output

LVDS Data Output Channel #3 (Negative), Not connected for P3−SN/SE

19

doutp3

LVDS

Output

LVDS Data Output Channel #3 (Positive), Not connected for P3−SN/SE20

gnd_18SupplySupply 1.8 V Ground21

vdd_18SupplySupply 1.8 V Supply

22nc

No connect23

vdd_33

SupplySupply 3.3 V Supply

24

gnd_33

SupplySupply 3.3 V Ground25

doutn4

LVDS

Output

LVDS Data Output Channel #4 (Negative)

26

doutp4

LVDS

Output

LVDS Data Output Channel #4 (Positive)

27

doutn5

LVDS

Output

LVDS Data Output Channel #5 (Negative), Not connected for P3−SN/SE

28

doutp5

LVDS

Output

LVDS Data Output Channel #5 (Positive), Not connected for P3−SN/SE

29

syncn

LVDS

Output

LVDS Sync Channel Output (Negative)

30

syncp

LVDS

Output

LVDS Sync Channel Output (Positive)31nc

No connect

32

nc

33

doutn7

LVDS

OutputNo connect
LVDS Data Output Channel #7 (Negative), Not connected for P3−SN/SE

34

doutp7

LVDS

Output

LVDS Data Output Channel #7 (Positive), Not connected for P3−SN/SE

35

doutn6

LVDS

Output

LVDS Data Output Channel #6 (Negative)

36

doutp6

LVDS

Output

LVDS Data Output Channel #6 (Positive)37

vdd_33

SupplySupply 3.3 V Supply

38

gnd_33

SupplySupply 3.3 V Ground39

gnd_18SupplySupply 1.8 V Ground40

vdd_18Supply41

lvds_clock_inn

LVDS

Input

LVDS Clock Input (Negative)

42

lvds_clock_inp

LVDS

Input

LVDS Clock Input (Positive)43nc

Supply 1.8 V Supply

No connect

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68

NOIP1SN5000A
Table 39. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LCC−84 PINS
Package Pin No.

Pin Name

I/O Type

Direction44

clk_pll

CMOS

Input

Description

45

vdd_18Supply1.8 V Supply

46

gnd_18SupplySupply 1.8 V Ground47

ibias_master

AnalogMaster Bias Reference

48

nc

49

vdd_33

Supply3.3 V Supply

50

gnd_33

Supply3.3 V Ground51

nc

No connect

52

nc

No connect

53

nc

No connect

54

nc

No connect

55

nc

No connect

56

nc

No connect

Reference Clock Input for PLL

No connect57

vdd_pix

SupplyPixel Array Supply

58

gnd_colpc

SupplyPixel Array Ground

59

nc

60

vdd_pix

SupplyNo connect
Pixel Array Supply

61

gnd_colpc

SupplyPixel Array Ground62

gnd_33

Supply3.3 V Ground63

vdd_33

Supply3.3 V Supply

64

nc

65

gnd_colpc

SupplyNo connect
Pixel Array Ground66

vdd_pix

SupplyPixel Array Supply

67

gnd_colpc

SupplyPixel Array Ground68

vdd_pix

SupplyPixel Array Supply

69

nc

70

trigger0

CMOS

Input

Trigger Input #0

71

trigger1

CMOS

Input

Trigger Input #1

72nc

No connect

73

nc

No connect74

nc

No connect75

nc

No connect

76

nc

77

trigger2

78
79

No connect

No connect
CMOS

Input

Trigger Input #2

monitor0

CMOS

OutputMonitor Output #0

vdd_33

SupplySupply 3.3 V supply

80

gnd_33

SupplySupply 3.3 V Ground81

monitor1

CMOS

OutputMonitor Output #1

82

reset_n

CMOS

Input

Sensor Reset (Active Low)

Input

SPI Slave Select.

83

ss_n

CMOS

84

gnd_33

SupplySupply 3.3 V Groundwww.onsemi.com
69

NOIP1SN5000A
Table 40. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad No

Pin Name

I/O Type

Direction

Description

A1

gnd

SupplySupply Ground

A2

gnd

SupplySupply GroundA3nc

No connection

A4nc

No connection

A5nc

No connection

A6nc

No connection

A7nc

No connection

A8nc

No connection

A9nc

No connection

A10

nc

No connection

A11

nc

No connection

A12

nc

No connection

A13

gnd

SupplySupply Ground

A14

gnd

SupplySupply Ground

B1

gnd

SupplySupply Ground

B2

gnd

SupplySupply Ground

B3

gnd

SupplySupply Ground

B4

gnd

SupplySupply Ground

B5

gnd

SupplySupply Ground

B6

gnd

SupplySupply Ground

B7

gnd

SupplySupply Ground

B8

gnd

SupplySupply Ground

B9

gnd

SupplySupply Ground

B10

gnd

SupplySupply Ground

B11

gnd

SupplySupply Ground

B12

gnd

SupplySupply Ground

B13

gnd

SupplySupply Ground

B14

gnd

SupplySupply Ground

C1

nc

C2

gnd

SupplyNo connection

C3

gnd

SupplyC4

doutn0

LVDS

Output

LVDS Data Output Channel #0 (Negative)

C5

doutp0

LVDS

Output

LVDS Data Output Channel #0 (Positive)

C6

sck

CMOS

Input

SPI Input Clock

C7

mosi

CMOS

Input

SPI Master Out − Slave In

C8

ss_n

CMOS

Input

SPI Slave Select.

C9

reset_n

CMOS

Input

Sensor Reset (Active Low)

C10

monitor1

CMOS

OutputMonitor Output #1

OutputMonitor Output #0

Supply Ground
Supply GroundC11

monitor0

CMOS

C12

gnd

SupplySupply Ground

C13

gnd

SupplySupply Ground

C14

nc

No connection

D1nc

No connection

D2

gnd

SupplySupply GroundD3

vdd_18SupplySupply 1.8 V Supply

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70

NOIP1SN5000A
Table 40. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad No

Pin Name

I/O Type

Direction

Description

D4

doutn1

LVDS

Output

LVDS Data Output Channel #1 (Negative), Not connected for P3−SN/SE

Output

LVDS Data Output Channel #1 (Positive), Not connected for P3−SN/SE

D5

doutp1

LVDS

D6

vdd_18Supply

D7

miso

CMOS

D8

gnd

SupplySupply GroundD9

vdd_33

SupplySupply 3.3 V Supply

D10

vdd_33

SupplyD11

trigger2

CMOS

Input

Trigger Input #2

D12

trigger1

CMOS

Input

Trigger Input #1

D13

gnd

SupplyD14nc

No connection

E1nc

No connection

E2

gnd

SupplyE3

vdd_18SupplyE4doutn2

LVDS

Output

LVDS Data Output Channel #2 (Negative)

E5

doutp2

LVDS

Output

LVDS Data Output Channel #2 (Positive)

E6

gnd

SupplySupply Ground

E7

gnd

SupplySupply Ground

E8

gnd

SupplySupply Ground

E9

gnd

SupplySupply Ground

E10

gnd

SupplySupply Ground

E11

gnd

SupplySupply GroundE12

trigger0

CMOS

E13

gnd

SupplyE14ncSupply 1.8 V Supply
Output

SPI Master In − Slave Out

Supply 3.3 V Supply

Supply Ground

Supply Ground
Supply 1.8 V Supply

Input

Trigger Input #0
Supply GroundNo connection

F1

nc

F2

gnd

SupplyNo connection
Supply GroundF3

vdd_18SupplySupply 1.8 V Supply

F4

doutn3

LVDS

Output

LVDS Data Output Channel #3 (Negative), Not connected for P3−SN/SE

F5

doutp3

LVDS

Output

LVDS Data Output Channel #3 (Positive), Not connected for P3−SN/SE

F6

nc

No connection

F7nc

No connection

F8nc

No connection

F9

nc

F10

gnd

SupplyNo connection
Supply GroundF11

gnd_colpc

Supplypc Supply Pixel Array GroundF12

vdd_pix

SupplySupply Pixel Array Supply

F13

gnd

SupplySupply Ground

F14

nc

No connection

G1nc

No connection

G2

gnd

SupplySupply GroundG3

vdd_18SupplySupply 1.8 V Supply

G4

clock_outn

LVDS

Output

LVDS Clock Output (Negative)

G5

clock_outp

LVDS

Output

LVDS Clock Output (Positive)

G6nc

No connection

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71

NOIP1SN5000A
Table 40. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad No

Pin Name

I/O Type

Direction

Description

G7nc

No connection

G8nc

No connection

G9nc

No connection

G10

gnd

SupplySupply GroundG11

gnd_colpc

Supplypc Supply Pixel Array GroundG12

vdd_pix

SupplySupply Pixel Array Supply

G13

gnd

SupplySupply Ground

G14

nc

No connection

H1

nc

H2

gnd

SupplyNo connectionH3

vdd_33

Supply

H4

syncn

LVDS

Output

LVDS Sync Channel Output (Negative)

H5

syncp

LVDS

Output

LVDS Sync Channel Output (Positive)

H6nc

No connection

H7nc

No connection

H8nc

No connection

H9nc

No connection

H10

gnd

SupplySupply Ground

Supply Ground
Supply 3.3 V Supply

H11

gnd

SupplySupply GroundH12

vdd_33

SupplySupply 3.3 V Supply

H13

gnd

SupplySupply Ground

H14

nc

No connection

J1nc

No connection

J2

gnd

SupplySupply GroundJ3

vdd_18SupplySupply 1.8 V Supply

J4

doutn4

LVDS

Output

LVDS Data Output Channel #4 (Negative)

J5

doutp4

LVDS

Output

LVDS Data Output Channel #4 (Positive)

J6nc

No connection

J7nc

No connection

J8nc

No connection

J9

nc

J10

gnd

SupplyNo connection
Supply GroundJ11

gnd_colpc

Supplypc Supply Pixel Array GroundJ12

vdd_pix

SupplySupply Pixel Array Supply

J13

gnd

SupplySupply Ground

J14

nc

No connection

K1

nc

No connection

K2

gnd

SupplyK3

vdd_18SupplyK4

doutn5

LVDS

Output

LVDS Data Output Channel #5 (Negative), Not connected for P3−SN/SE

K5

doutp5

LVDS

Output

LVDS Data Output Channel #5 (Positive), Not connected for P3−SN/SE

K6

gnd

SupplySupply Ground

K7

gnd

SupplySupply Ground

K8

gnd

SupplySupply Ground

K9

gnd

SupplySupply Ground

Supply Ground
Supply 1.8 V Supply

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72

NOIP1SN5000A
Table 40. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad No

Pin Name

I/O Type

Direction

Description

K10

gnd

SupplySupply GroundK11

gnd_colpc

Supplypc Supply Pixel Array GroundK12

vdd_pix

SupplySupply Pixel Array Supply

K13

gnd

SupplySupply Ground

K14

nc

No connection

L1nc

No connection

L2

gnd

SupplySupply GroundL3

vdd_18SupplySupply 1.8 V Supply

L4

doutn6

LVDS

Output

LVDS Data Output Channel #6 (Negative)

L5

doutp6

LVDS

Output

LVDS Data Output Channel #6 (Positive)

L6

vdd_18SupplyL7

lvds_clock_inp

LVDS

L8

gnd

SupplySupply Ground

Supply 1.8 V Supply
Input

LVDS Clock Input (Positive)

L9

gnd

SupplySupply Ground

L10

gnd

SupplySupply GroundL11

vdd_33

SupplySupply 3.3 V Supply

L12

gnd

SupplySupply Ground

L13

gnd

SupplySupply Ground

L14

nc

No connection

M1nc

No connection

M2

gnd

SupplySupply Ground

M3

gnd

SupplySupply GroundM4

doutn7

LVDS

Output

LVDS Data Output Channel #7 (Negative), Not connected for P3−SN/SE

Output

LVDS Data Output Channel #7 (Positive), Not connected for P3−SN/SE

M5

doutp7

LVDS

M6

vdd_33

SupplyM7

lvds_clock_inn

LVDS

Input

LVDS Clock Input (Negative)

M8

clk_pll

CMOS

Input

Reference Clock Input for PLL

M9

vdd_18SupplySupply 1.8 V Supply

Supply 3.3 V Supply

M10

gnd

SupplySupply GroundM11

ibias_master

AnalogMaster Analog Master Bias Reference

M12

gnd

SupplySupply Ground

M13

gnd

SupplySupply Ground

M14

nc

N1

gnd

SupplySupply Ground

N2

gnd

SupplySupply Ground

N3

gnd

SupplySupply Ground

N4

gnd

SupplySupply Ground

N5

gnd

SupplySupply Ground

N6

gnd

SupplySupply Ground

N7

gnd

SupplySupply Ground

N8

gnd

SupplySupply Ground

N9

gnd

SupplySupply Ground

N10

gnd

SupplySupply Ground

N11

gnd

SupplySupply Ground

N12

gnd

SupplySupply GroundNo connection

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NOIP1SN5000A
Table 40. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad No

Pin Name

I/O Type

Direction

Description

N13

gnd

SupplySupply Ground

N14

gnd

SupplySupply Ground

P1

gnd

SupplySupply Ground

P2

gnd

SupplySupply GroundP3nc

No connection

P4nc

No connection

P5nc

No connection

P6nc

No connection

P7nc

No connection

P8nc

No connection

P9nc

No connection

P10

nc

No connection

P11

nc

No connection

P12

nc

P13

gnd

SupplyNo connection
Supply Ground

P14

gnd

SupplySupply Groundwww.onsemi.com
74

NOIP1SN5000A
Package Drawing

NOTE: Unless noted otherwise, all dimensions represent nominal values.

Figure 49. Package Drawing for the 84−pin LCC Package

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75

NOIP1SN5000A

Figure 50. Package Drawing for the 128−pad LGA Package

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NOIP1SN5000A
Table 41. MECHANICAL SPECIFICATION FOR LCC−84 PINS AND LGA−128 PADS
ParameterDie(with Pin 1 to the left
center)Glass Lid Specification

Description

Min

Die thickness
Die Size

Typ

Max

Units

725

mm

14.7 x 14.25mm2

Die center, X offset to the center of package

−50

0

50

Die center, Y offset to the center of the package

−50

0

50

mm

Die position, tilt to the Die Attach Plane

−1

0

1

deg

Die rotation accuracy (referenced to die scribe and leadfingers on package on all four sides)

−1

0

1

deg

mm

Optical center referenced from die/package center (X−dir) PYTHON 5 MP

−231.38mm

Optical center referenced from die/package center (X−dir) PYTHON 2 MP−154.58mm

Optical center referenced from die/package center (Y−dir)
PYTHON 5 MP / 2 MP

1697.17mm

Distance from bottom of the package to top of the die surface

1.145

Distance from top of the die surface to top of the glass lid

0.745

XY size

1.25

1.405

mm

1.13

1.495

mm

19 x 19

Thickness

0.45

Spectral response range

400

Transmission of glass lid (refer to Figure 53)

0.55

mm
0.65

mm

1000

nm

92

%

Glass Lid Material

D263 Teco

Mechanical ShockJESD22−B104C; Condition G

2000

g

Vibration

JESD22−B103B; Condition 1

2000

Hz

Mounting Profile

Reflow profile according to J−STD−020D.1

CTE

Coefficient of Thermal expansion of the LCC Package
Coefficient of Thermal expansion of the LGA Package

260

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77

7.6
7.1

°C
mm/°C

NOIP1SN5000A
Table 42. OPTICAL CENTER INFORMATION FOR THE PYTHON 5000/2000 IN LCC−84 PINS AND LGA−128 PADSPYTHON5000
References*

PYTHON2000

X (mm)Y (mm)

D1

0

D2

14700

D3
D4
Die Center

CD

Active Area Coordinates

Die Outer Coordinates

Active Area Center

X (mm)Y (mm)

14250

0

14250

14250

14700

14250

14700

0

14700

0

0

0

0

0

7350

7125

7350

7125

A1

878.6313756.57

878.6313756.57

A213358.63

13756.57

13358.63

13756.57

A313358.63

3887.77

13358.63

3887.77A4

878.633887.77878.633887.77AA

7118.638822.177195.438822.17

Pitch

4.8

4.8

4.8

4.8

# Pixels

2600

2056

2600

2056

# Dummy

8

8

616

792

# Active Pixels

2592

2048

1984

1264

Act_A1897.8313737.37

2433.8311855.77

Act_A213339.43

13737.37

11957.03

11855.77

Act_A313339.43

3906.9711957.03

5788.57

Act_A4897.833906.97

2433.835788.57*Refer to Figure 51 below.

Figure 51. Optical Center Information for PYTHON 5000/2000 for LCC−84 Pins and LGA−128 Pads

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78

NOIP1SN5000A
Packing and Tray Specification

The PYTHON packing specification with ON Semiconductor packing labels is packed as follows:
Table 43. PACKING AND TRAY INFORMATION FOR P1−SN/SE/FN, P3−SN/SE
Package Size (mm)Package
LCC−84 pin
LGA−128 pin

Tray

Restraint

Box

LengthWidthThickness*

Tray

Quantity / Tray

Strap

Bag

Tray Quantity

19

19

2.58

KS−870541

42

Rubberband

Double bagged using
MBB and pink ESD bag

5 trays + 1 covertray*Includes package, glass and glue attach thickness.
NOTE: Cover paper to be placed on the top tray.

Figure 52. Packing and Tray Configurationwww.onsemi.com
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NOIP1SN5000A
Glass Lid

As shown in Figure 53, no infrared attenuating color filter
glass is used. A filter must be provided in the optical path
when
color
devicesareused(source:
http://www.pgo−online.com).

The PYTHON 2000 and PYTHON 5000 sensor uses a
glass lid without any coatings. Figure 53 shows thetransmission characteristics of the glass lid.

Figure 53. Transmission Characteristics of the Glass Lid
Protective Film Option (−QTI Versions)

For certain size and speed options, the sensor can bedelivered with a protective foil that is intended to be
removed after assembly. The dimensions of the foil are as
illustrated in Figure 54 with the tab aligned towards one
corner of the package as illustrated in Figure 55.
Figure 55. Location of the Pull Tab in Reference to
LCC−Pin 1 and LGA−Pad A1

Figure 54. Dimensions of the Tape

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NOIP1SN5000A
SPECIFICATIONS AND USEFUL REFERENCES
Useful References

The following references are available to customers under
NDA at the ON Semiconductor Image Sensor Portal:• Product Acceptance Criteria• Product Qualification Report• PYTHON Developer’s Guide AND9362/D

For information on ESD and cover glass care andcleanliness, please download the Image Sensor Handlingand Best Practices Application Note (AN52561/D) fromwww.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) fromwww.onsemi.com.
For information on Standard terms and Conditions ofSale, please download Terms and Conditions fromwww.onsemi.com.
For information on acronyms and a glossary of terms
used, please download Image Sensor Terminology(TND6116/D) from www.onsemi.com.

Material Composition is available at:
http://www.onsemi.com/PowerSolutions/MaterialCompos
ition.do?searchParts=PYTHON5000

Return Material Authorization (RMA)

Refer to the ON Semiconductor RMA policy procedure at
http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn
alysis.pdf

ON Semiconductor andare trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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NOIP1SN5000A/D