JAERI-Conf

95-021

PA42
Analog Processor for Emittance Monitor in SPring-S Linac
K.Yanagida, Y.Itoh, H.Yoshikawa, T.Hori, S.Suzuki, A.Mizuno, H.Sakaki,T.Taniuchi, A.Kuba, T.Okada, M.Kodera and H.Yokomizo
JASRI-JAERI-RIKEN SPring-8 Project Team
SPring-8, Kamigori-cho, Ako-gun, Hyogo-ken, 678-12, Japan
Abstract
The analog processor for the emittance monitor inthe SPring-8 linac is composed of a charge sensitive
amplifier with gain control, a sample/hold circuit and anisolation circuit. The charge sensitive amplifier detectspulsed charge from the wire scanner. The sample/holdcircuit maintains the signal to which can be accepted by
an ND converter on VME computer. It is designed as
1V/pC, 0.1 V/pC or 1V/nC. The linear region wasmeasured as -5V-5V of output. Fluctuation of output for
200 seconds was -1.5mV of 1c:r. However voltage drift
was observed for 150 hours. But this is acceptable for
emittance measurement.
1. Introduction

Fig. 1 Photograph of the analog processor.

Profile monitors are generally used for emittancemeasurement. There are many kinds of profile monitors
for example a wire scanner, a scintillation screen, anOTR monitor and so on. In the SPring-8 linac, a wire
scanner is employed for the emittance monitor [1]. Whenan electron beam impinges on the wire, secondary
emission charge and the bremsstrahlung are generated.
Both are proportional to the charge of incident electronbeam. An analog processor which detects the secondary
emission charge is employed for the emittance monitor
in the SPring-8 linac. However the efficiency ofsecondary emission charge from incident charge isreported as 6-7% for total surface at 30MeV-1GeV.
Because of this low efficiency, a high gain charge
sensitive amplifier is required. The analog processor hasa sensitivity of lV/pC nominally. The minimum charge
is expected as ~0.01pC/pulse at the positron mode (lnswidth and lOrnA peak current). Therefore the minimum
signal output is expected as ~lOmV. The fluctuation ofoutput signal is must be comparable (-lOmV of 6c:r) tomeasure the positron beam profile.
Because an ND converter on VME computer only
acquires DC voltage, the output signal of the charge
sensitive amplifier is processed to DC voltage by asample/hold circuit.
2. Composition of Analog Processor
The analog processor is mounted on a print circuitboard (see Fig. 1). The main components are a charge
sensitive amplifier (CS-507, CLEAR-PULSE), asample/hold IC (AD1154, ANALOG DEVICES), anadjusting circuit and an isolation circuit. The block
diagram is shown in Fig. 2.
Two diodes (PAD1, SILICONIX) are used for input
protection. The PADl is a low leak diode which has
specification of <lpA leak current. When the voltage
exceeds over ±6V at the input of CS-507, the extra
charge is bypassed though the diode.

The CS-507 is a hybrid IC which has a sensitivity of
1V/pC, nominally i.e. the built-in feedback capacitance
Cf of 1pF. In order to release the charge on the feedback
capacitor a resistance of WOOMQ is also attached inparallel with the capacitor. The time constant ofrelaxation becomes lms. The sensitivity can be changed
by attaching external feedback capacitors. Thesensitivities are designed as lV/pC (Cf-lpF, high gainmode), O.lV/pC (Cf-10pF, medium gain mode) andlV/nC (Cf-lOOOpF, low gain mode). Of course eachtime constant of relaxation is designed as -lms. The
sensitivity can be changed by remote control. An MOSFET is used as input stage in the CS-507. It has offset
voltage of --0.5V nominally. Therefore the offset
voltage appears on the CS-507 output.
The AD1154 works to make a DC voltage from thepulsed signal of the CS-507. The appropriate external
trigger is required for sampling.
The adjusting circuit adjusts sensitivity to designed
one and offset at the output of analog processor. The
adjustable range is designed as 0.88-1.54. The reason forexceeding of 54% is to compensate the increase of
feedback capacitance due to the stray capacitance. This
stray capacitance will be a problem especially for thehigh gain mode.
The isolation circuit breaks the ground inductor loop.
When the ground line is connected to the vacuum
chamber by two or more route, a ground inductor loop isconstructed. If the impedance of the loop is small, aground current flows. A ground current degrades the SINratio. If a ground current of lOnA flows, a voltage oflOV {high gain mode) emerges on the DC output. In theSPring-8 linac there are two isolation points. One is in
the analog processor and the other is an isolation
amplifier in the ND converter on VME computer. Theisolation method in the analog processor is described
below. The DC voltage from the AD1154 is converted to- 144-JAERI-Conf 95-021

4.-..20>......,~1080 ~-100>3-;---12V':::'z;:1~1~oo-1o100

50Time (~sec)

50Time~sec)

100III

1...---------------~

1...----~---------,

I

CS-507----

0 ,--.--.,--..-,....----.-__,..---,>._.

...:sg.
0 -1

I

=Ib

I
.._I~

ll'l

Sampling Point
rnu -2o.!.-'--~~~-=-z---"--;\3.--'--74 -----!5:IsolatedITime(ms)Fig. 2 Block diagram of analog processor.
frequency by the PLL circuit. Then the frequency istransferred through an isolation transformer to thesecond PLL circuit. Finally the frequency is restored to a
DC voltage by the second PLL circuit.

region will be extended to -10V-+5V of DC outputif
further adjustment will be performed. The sensitivity andthe offset voltage are calculated by the curve fitting in
the linear region. These measured characteristics aresummarized in Table 1.

3. Examination of Analog Processor

10 rr~~~~~~~~~~~~~~~->

The analog processor was adjusted and examinedusing a simulated pulse. An appropriate reference
capacitor Ci. lOpF, lOOpF or O.OlJlF, was connected tothe input of the analog processor. When a step voltage
Vi was applied, a corresponding charge -CiVi wasgenerated on the reference capacitor. At the same time
the charge flowed into the analog processor. This means
the charge of CiVi was transferred to the feedback
capacitor of the charge sensitive amplifier. Fig. 3 shows
the CS-507 outputs when various charges were applied.
Due to the charge CiVi on the feedback capacitor, theCS-507 generated the voltage of ci '1. However the....

'-'==g.
0 0I0't;'ltnu-5-1002345Time (ms)Crcharge was released exponentially through the resister.
Once the exponential curve was obtained, the peakvoltage would be calculated by the curve fitting as thevalue at t=O. Fig. 4, Fig. 5 and Fig. 6 show the peakvoltage of CS-507 output when the various charges wereapplied. The variation of DC output is also plotted. Theregion where the output is proportional to the input
within ±1% is named linear region. The linear region
was measured as -5V-+5V of DC output. The linear

5Fig. 3 CS-507 output when the simulated charge isapplied from -lOpe to lOpe by lpC step.
The fluctuation (standard deviation) of DC output for
200 second (100 samples) was measured as shown inFig. 7. The correlation between the input charge and thestandard deviation means that this fluctuation wascaused by the PLL circuit. The average is -1.5mV (lcr).

- 145 ~

JAERI-Conf 95-021

This value can be acceptable to measure the positron
beam profile.
Fig. 8 shows the fluctuation for 150 hours. Each data
was acquired in different run. the maximum differenceof CS-507 output is -3.5mV. On the other hand themaximum difference of DC output is -85mV. The
sample/hold circuit and the isolation circuit may beaffected by room temperature drift.
10~-r~~rT~~~~~~~~~~-,--~---~

o o·· t> .....

5~............

• DCOutputo CS-507--DC Output Fitting········· CS-507 Fitting

0-5-105. Reference[1] K.Yanagida, et al., "Emittance Monitor for SPring-8Linac." in Proc. of 1994 Linear Ace. Conf.,
Tsukuba, Japan, Aug. 1994, pp. 920-922.
Table 1Measured data of sensitivit , offset and linearit
OutputLinearSensitivity. Offset ofGain
Re ionDC Ou ut
NACS-507-6-+ 10Hih=~0

acceptable to measure the positron beam profile.
However the fluctuation for 150 hours is rather large.
This means that measurement must be performed in few
minutes. The linear region is -5V-+5V of DC output.
This can be extended to -5V-+10V.

L..L__._.....__..a......JL.....L--L.._._.a.....l__.___.__.......__.I...-L_.__._..___....:>.I-10-50510Input Charge (pC)
Fig. 4 Linearity curves of high gain mode for CS-507
output and DC output.
10 ~--r"~T"""""T--r"""T"""~--r~....--.~_,_..,.....,--,-""T"""l•DC Outputo CS-507--DC Output Fitting········• CS-507 Fitting5~

Low
DC Output
Low.... 0&c5 -5•0s>s 2.5

IJ•:;j·s:I:U ........
.... 2-50050100

Input Charge (pC)
Fig. 5 Linearity curves of medium gain mode for CS-507
output and DC output.

~&"081.5

Jg

rn'O 0.50 L.....l.--'-~--'-_._.__.._._~__._.....__~_._~~

10 ~--r-~r-r--r-~~--~~~--~~~-10• DCOutput
0 CS-507--DC Output Fitting········· CS-507 Fitting

5HighGain
Medium Gain
Low Gain-50510Input Charge (a.u.)
Fig. 7 Standard deviation of DC output.
CS-507--5-10

L.....l._.__._..._,__.__._.__.._.__._.__.._.__,__.__.._._~-10-5

0510Input Charge (nC)
Fig. 6 Linearity curves of low gain mode for CS-507
output and DC output.

-600>e........
r-- -650
0It;\rnu -700

DC Output-750 .___.___.___.__.___.__,__..__.___.__,___.__.___.__,__, -100

4. Conclusion
The analog processor achieved as designed
characteristics. The fluctuation for 200 second can be050

100150Time (h)Fig. 8 Time evolution of CS-507 output and DC output
for 150 hours.