Nuclear Instruments and Methods in Physics Research A 650 (2011) 129–135

Contents lists available at ScienceDirect

Nuclear Instruments and Methods inPhysics Research A
journal homepage: www.elsevier.com/locate/nima

Development of n-in-p silicon planar pixel sensors and ﬂip-chip modules
for very high radiation environments
Y. Unno a,n, Y. Ikegami a, S. Terada a, S. Mitsui a, O. Jinnouchi f, S. Kamada b, K. Yamamura b, A. Ishida b,
M. Ishihara b, T. Inuzuka b, K. Hanagaki e, K. Hara g, T. Kondo a, N. Kimura h, I. Nakano d, K. Nagai g,
R. Takashima c, J. Tojo a, K. Yorita haHigh Energy Accelerator Research Organization (KEK)/The Graduate University for Advanced Studies (SOKENDAI), Japan
Hamamatsu Photonics K.K., Japanc
Department of Education, Kyoto University of Education, Japand
Department of Physics, Okayama University, Japane
Department of Physics, Osaka University, Japanf
Department of Physics, Tokyo Institute of Technology, Japang
Institute of Pure and Applied Sciences, University of Tsukuba, JapanhResearch Institute for Science and Engineering, Waseda University, Japanba r t i c l e i n f oabstract

Available online 8 January 2011

In this paper we present R&D of n-in-p pixel sensors, aiming for a very high radiation environment up
to a ﬂuence of 1016 neq/cm2. To fabricate these sensors, two batches with different mask sets were
employed: the ﬁrst resulted in pixel sensors compatible with the ATLAS pixel readout frontend chipcalled FE-I3, and the second in FE-I3 and a new frontend chip, FE-I4, compatible sensors; small diodes
were employed to investigate the width from the active diode to the dicing edge and the guard rings.
Tests involving the diodes showed that the strong increase of leakage current was attributed to theedge current when the lateral depletion zone reaches the dicing edge and the lateral depletion along
the silicon surface was correlated with the ‘ﬁeld’ width. The onset was observed at a voltage of 1000 V
when the width was equal to  400 mm. The pixel sensors that were diced at a width of 450 mm could
successfully maintain a bias voltage of 1000 V. Hybrid ﬂip-chip pixel modules with dummy and real
chips were also fabricated. Lead (PbSn) solder bump bonding proved to be successful. However,lead-free (SnAg) solder bump bonding requires further optimization.
& 2011 Elsevier B.V. All rights reserved.

Keywords:
SiliconSensorPixel
p-typen-in-pRadiation tolerant
Bump bonding

1. Introduction
A characteristic case of a very high radiation environment is
the Large Hadron Collider (LHC) and the future Super LHC (SLHC).
While the ATLAS experiment [1] at the LHC collects proton
collision data of approximately 700 fb  1, the inner detector (ID)is exposed to an integrated particle ﬂuence of  2  1014 and3  1015 (1-MeV neutron equivalent (neq))/cm2, including asafety factor of 1.5 for the luminosity, at distances (R) of 30 cm(microstrip detectors) and 5 cm (pixel detectors) from the collision point, respectively. LHC is planned to be upgraded to SLHCwith the ultimate aim to maximize its research capabilities by achieving one order of magnitude higher luminosity ( 1035 cm  2 s  1)
and an integrated luminosity of 3000 fb  1. By including a safety
factor of 2 for the integrated luminosity, the inner detector of SLHCnCorresponding author.
E-mail address: yoshinobu.unno@kek.jp (Y. Unno).

0168-9002/$ - see front matter & 2011 Elsevier B.V. All rights reserved.
doi:10.1016/j.nima.2010.12.191

is then expected to be exposed to ﬂuencies of  1  1015 and 2  1016 neq/cm2 at distances of 30 and 5 cm, respectively. Itshould be noted that the ﬂuence of neutrons dominates that ofother charged particles at RZ25 cm.
Over the past year, R&D efforts for highly radiation tolerant
silicon microstrip sensors have been made on n-in-p microstrip
sensors [2,3] and many were reported in conferences [4,5]. Our
recent fabrications were miniature sensors of 1 cm  1 cm andlarge area sensors of 9.75 cm  9.75 cm using 6-in. (150 mm
diameter) wafers made of p-type ﬂoat-zone (FZ) material with athickness of 320 mm at Hamamatsu Photonics K.K. (HPK) [6].
These include an innovative design for n-in-p sensors thatpromises a signiﬁcantly enhanced leakage current performance
without breakdown (onset of microdischarge) up to a voltage of1000 V [7,8]; extensive testing of radiation damage expected with
proton and neutron ﬂuencies is up to 1015 1-MeV neq/cm2[9,10], and as an example of usage, single- and double-sided
prototype modules fabricated on the basis of large area n-in-p
sensors [11,12].

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Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 650 (2011) 129–135

By utilizing the achievements obtained in the strip sensors, wehave fabricated n-in-p pixel sensors with a goal of R&D efforts
to develop a device that can operate under particle ﬂuences
Z1016 neq/cm2, and a bias voltage up to 1000 V in order toachieve enhanced charge collection capabilities than charge trapping in the bulk of silicon wafers heavily damaged by radiation.
An additional aim is to address the ‘charge multiplication’ effectthat is observed in heavily damaged silicon sensors whose
thickness is as small as 150 mm under bias voltages as high as1000 V [13]. Another goal of R&D is to evaluate the required
width from the end of the active diode to the dicing edge in orderto minimize the insensitive area.

2. R&D of n-in-p sensors
Two batches of 6-in. wafers were processed using different mask
sets. The ﬁst mask set (batch/wafer #1), as shown in Fig. 1(a), wascomposed of pixel sensors in a section named as parts 1–29, among
which the numbers between 12 and 16 and between 26 and 29
were the ones compatible with the pixel readout frontend chipcalled FE-I3 [14] of ATLAS pixel detector. The second mask set(batch/wafer #2) is shown in Fig. 1(b). This mask was composed ofpixel sensors compatible with FE-I3 and a new much larger pixel
readout frontend FE-I4 [15] chips: FE-I3 and FE-I4 single-chipcompatible (parts number 1–7 and 34–39), FE-I4 double-chipcompatible (28–33), FE-I3 quad-chip compatible pixel sensors(40–42), together with other various pixel sensors. The small squareparts at the perimeter in both mask sets were diodes used for the
study of effects of the sensors’ slim edges and the guard rings.
In batch #1, pixel sensors and diodes were processed in p- andn-type wafers to make n-in-p and p-in-n samples. The nominal
thickness of the wafers was 320 mm, while a number of n-type
wafers were thinned down to the thickness of 200 mm. The
resistivities of p-type and n-type wafers were  7 and  4 kO cm,
respectively. The isolation of n+ pixels of the n-in-p pixel sensors
was achieved by a p-stop structure with a concentration of
4  1012 Boron ions/cm2. From batch #1, FE-I3 single-chip compatible pixel sensors were used later for bump bonding and in atest beam (see Section 4.1). The pixel structure (polysiliconbiasing and a ‘common-type’ p-stop structure) used for the test
beam is shown in Fig. 1(c).

Fig. 1. Layout of the mask sets: (a) batch/wafer #1, FE-I3 compatible pixel sensors (parts number 12–16, 26–29) and with various pixel designs (the rest of 1–29);(b) batch/wafer #2, FE-I3 compatible sensors (1–7), FE-I4 double-chip compatible sensors (28–33), FE-I4 single-chip compatible sensors (34–39), and FE-I3 quad-chipcompatible sensors (40–42). The small square parts at the perimeter are diodes, which have been added for the study of effects of the sensor’s slim-edge and the multiple
guard rings; (c) a pixel structure with a polysilicon bias resistor and a common p-stop structure in batch #1; (d) biasing and isolation structures for pixel sensors in batch #2,
4-to-1 PT combined with a common p-stop isolation (top-left), individual p-stop structure (top-middle), p-spray (top-right) isolation, polysilicon bias with common p-stop
isolation (bottom-left), individual p-stop (bottom-middle) and p-spray isolation (bottom-right).

Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 650 (2011) 129–135

In batch #2, the outer dimensions of the FE-I4 pixel sensors
leave the possibility of dicing them at 360, 450, 600, 750, and1011 mm nominally along the longitudinal-pixel side edges. Eachpixel’s structure is a combination of n-side isolation and biasing
substructures as shown in Fig. 1(d). The n-side isolation wasachieved by either common or individual p-stops of a concentration of 4  1012 ions/cm2 or p-sprays of 2  1012 ions/cm2. The
biasing structure was made of punch-through structures orpolysilicon resistors including punch-through structures having 4 pixels per one bias dot (4-to-1 PT) or one pixel to one dot (1-to-1 PT).
Only p-type wafers were processed. The nominal thickness of eachwafer was 320 mm and a number of wafers were being thinned down
to 150 mm.
Studies on different kinds of punch-through structures were
performed in the past [16]. In order to reduce potentially lessefﬁcient area resulting from the bias dot in each pixel, we
introduced one bias dot at the corner of 4 pixels (4-to-1 PT) andpolysilicon biasing (Fig. 1(d): top ﬁgure for the 4-to-1 PT with thecommon, individual, and p-spray isolation). Alternatives based onpolysilicon resistors are shown in the bottom ﬁgures for all
different isolation structures. It should be noted that in the caseof 4-to-1 PT structures, the gap between two adjacent pixel
implants is 20 mm in both the common p-stop and the p-spray
isolations. In the case of polysilicon resistors, the gaps are 24 and20 mm, respectively. On the other hand, in the case of individual
p-stop isolation the gaps are wider, 30 and 34 mm in the 4-to-1
and in the polysilicon resistor, respectively. The requirement of
not having a signiﬁcant signal distribution to the neighbor pixels
within a typical shaping time of 25 ns leads to a lower limit of theinter-pixel resistance of 1 MO [16]. Thus, the polysilicon biasingof 2.7 MO in the batch/wafer #2 is sufﬁcient and could be agood stable solution. The main features of wafers and pixel
sensors are summarized in Table 1.

Table 1Main features of wafers and sensors.
Silicon wafer diameter
Type
Orientation
Resistivity (bulk type)
Thickness
ThinnedSilicon sensors exploiting the depleted volume inside thesilicon wafer require extra edge space so that the depleted
volume is conﬁned away from the dicing edge. As this extra edge
space is an insensitive volume, there is increasing interest to
minimize this space. In order to investigate the required spacesystematically, we fabricated ‘slim-edge’ diodes of various edge
widths.
In our design, the edge termination is achieved with only two
guard rings, one close to the active diode and another at the
dicing edge. The layout of such a diode and a schematic diagram
for the width deﬁnition are shown in Fig. 2. Both p + and n +implantations in the guard ring at the dicing edge were preparedirrespective of the bulk material. In the subsequent measurements, either n-bulk/n+ edge or p-bulk/p+ edge samples wereused. The thicknesses of the n-bulk material were 320 mm (W5)and 200 mm (W7, 13), where the names in the parentheses are forthe wafers’ identiﬁcation. The thickness of the p-bulk sample was
320 mm (W3). The total edge width, from the edge of the diode to
the dicing edge, ranged between 80 and 640 mm, and between
280 and 1011 mm, in the n- and p-bulk materials, respectively.
The leakage current as a function of bias voltage for various
p-bulk samples is shown in Fig. 3. A strong increase of leakage
current was observed in the narrow width samples at lower bias
voltages, which can be attributed to the increase of edge current
when the lateral depletion zone reaches the dicing edge.
In Fig. 4, relationship between
ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃtotal edge width and thepthesquare root of the onset voltage ( Vbias ) at the strong increase of

6-in. (150 mm)
FZ (high grade)o1 0 04
 7 (p),  4 (n) kOcm
320 mm (nominal)
200 mm (n-type), 150 mm (p-type)

FE-I3 compatible pixel sensor: single-chip
Sensor dimensions
10.5 mm  10.0 mm
Pixel dimensions
50 mm  400 mma
Number of pixels
164  18 ¼2952
FE-I4 compatible pixel sensor: single-chip
Sensor dimensions
18.7 mm  20.9 mmb
Pixel dimensions
50 mm  250 mm
Number of pixels
336  80 ¼26,880
FE-I4 compatible pixel sensor: double-chip
Sensor dimensions
18.7 mm  41.3 mmb
Pixel dimensions
50 mm  250 mm
Number of pixels
336  160 ¼53,760
n + pixel isolation:
p-stop(common or individual)
p-spray
Bias structures:
Punch-throughPolysiliconParts no.:4  1012 ions/cm2
2  1012 ions/cm2

4-to-1 or 1-to-1
 1 MO (batch #1),  2.7 MO (batch #2)
4-to-1 PT

p-stop (common)#2-1#2–28,-29,-34#2–40
p-stop (individual)#2-2#2–30,-31,-35#2–41

3. Results
3.1. Slim-edge diodes

131

p-sprayab#2-3#2–32,-33,-36#2–42

1-to-1 PT

Polysilicon#1–13,-27#2–4#1–15,-29
#2–6
#2–37

#1–12,-26#2–5#1–14,-28
#2–7
#2–38

#2–39

Outermost pixels are 600 mm long.
In the case that the edge width is 450 mm.

leakage current is summarized in p-bulk/p+ edge samples (toppanel) and in n-bulk/n+ edge samples (bottom panel). In bothpanels, a near-linear dependence of the onset voltage on the totaledge width p
is ﬃﬃﬃﬃﬃﬃﬃﬃﬃ
observed.
The onset voltage reached the value ofﬃ
1000 V (i.e., Vbias of 31.6 V) when the total edge width was equal
to 400 mm, irrespective of the bulk material or its thickness.
From the linear dependence of the square root of the bias voltage
on total edge width, we concluded that the onset voltage and thetotal edge width were deﬁned by the laterally depleted volume
along the surface of silicon wafer.

3.2. Guard rings
The guard rings are implemented in the context of the edge
termination for high voltage operation [16]. Recently, investigations have been made in the context of reducing the insensitiveedge space [17]. Our next step was to systematically investigate
the role of the guard rings in the edge space. For this purpose,samples of small diodes were fabricated by varying the number ofguard rings (1–3 GR), the total width of the guard rings (N, M, W),
and the width of the edge implantation. The layouts of themultiple guard rings are shown in Fig. 5.

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Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 650 (2011) 129–135

Fig. 4. Square root of bias voltage as measured at the strong increase of leakage
current as a function of total edge width. The letter‘N’ﬃ or ‘P’ in the legend indicatespﬃﬃﬃﬃﬃﬃﬃﬃﬃ
the bulk material. The data point at 1000 V (i.e., Vbias of 31.6 V) indicates that thestrong increase of leakage current is above 1000 V.

along the ‘ﬁeld’ surface of silicon wafer was the fundamental
factor of deﬁning the edge space and the surface implantation
was shortening the silicon surface owing to its characteristic low
resistivity.
3.3. FE-I4 double-chip compatible pixel sensor
Fig. 2. An example of slim-edge diodes (4 mm  4 mm) with a narrowededge width.

Fig. 3. Strong increase of leakage current observed in the slim-edge diodes as afunction of bias voltage. In the legend, ‘nnn’ following W3 (W3-nnn) denotes thetotal edge width of the sample.

The onset voltage of strong increase of leakage current wasmeasured in the n-bulk/p+ edge samples. In n-bulk/n+ edge
samples where the edge space was as large as 1000 mm, the onset
could not be observed for bias voltages up to 1000 V.
In analyzing the data, we used the ‘ﬁeld’ width as deﬁned by
the width of the surface without implantation (see Fig. 2). The
relation between the total ‘ﬁeld’ width and the square root of theonset voltage of strong increase of leakage current of the guard
ring samples is shown in Fig. 6. Shown together with this is therelation of the n-bulk/p+ edge samples in the ‘slim-edge’ diodes.
From the linear relation, we concluded that lateral depletion

The typical leakage current dependence on bias voltage (I–V)
applied to the FE-I4 double-chip compatible n-in-p pixel sensors
with a 4-to-1 PT biasing structure is shown in Fig. 7. The sensor
was 320 mm thick and the total edge width was equal to 450 mm.
The n-side isolation was of either a common p-stop (COM) or anindividual p-stop (IND) structure with a p-concentration of
4  1012 ions/cm2 (P4), or a p-spray structure with a concentration of 2  1012 ions/cm2 (R2).
The COM-P4 and IND-P4 samples exhibited excellent I–V
characteristics, while the onset of microdischarge was notobserved for voltages up to 1000 V. On the contrary, increase ofleakage current was observed in the R2 samples at a signiﬁcantly
lower voltage. We attributed this difference to the higher electricﬁeld at the contact of the n+ pixel and p+ spray and possible
microscopic defects at the edge of the n+ pixel implantation.
It should be noted that the level of saturation of the leakage
current in the area of  3.3 cm2 was equal to 4 nA/cm2, whichis consistent with the level of saturation of leakage current of 7 nA/cm2 observed in a small diode of  0.04 cm2 (see Fig. 3). This
fact supports that the leakage current is proportional to the sensor
area and 4-to-1 PT biasing to each pixel is successfully working.
In samples of FE-I3 single-chip compatible p-in-n pixel sensors
thinned down to 200 mm, the onset of microdischarge was notobserved for voltages up to 1000 V.
3.4. Irradiation
Selected samples from batch #1 were irradiated with 70-MeV
protons generated from the AVF cyclotron at CYRIC, Japan [18].
A batch of samples was irradiated to a ﬂuence of 5  1012, 1  1013,
1  1014, 1  1015, or 1  1016 neq/cm2 separately, stacked in an areaof  8 cm   2 cm on an irradiation board. Owing to the highcurrent of the cyclotron, 1.5 h was required to reach ﬂuence values
as high as 1015 neq/cm2 and approximately 8 h was required toreach 1016 neq/cm2, while the beam current was limited to 800 nA.

Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 650 (2011) 129–135

133

Fig. 5. Diodes with multiple guard rings with both varying number of guard rings and widths.

Fig. 6. Square root of bias voltage as observed at the strong increase of leakage
current as a function of ‘ﬁeld width’ in the n-bulk material with a p + edge
implantation.

Fig. 7. Typical leakage current-bias voltage behavior of FE-14 double-chipcompatible n-in-p pixel sensors; 4-to-1 PT, common (COM-P4) and individual(IND-P4) p-stop with 4  1012 ions/cm2 and p-spray (R2) with 2  1012 ions/cm2,
diced along the longitudinal edge at 450 mm.

These series of measurement and their analysis are still ongoing andthe results will be reported elsewhere.

4. Bump bonding of pixel sensors at HPK
The bump bonding technology for developing ‘hybrid’ pixel
modules was veriﬁed with dummy and real chips. The dummy

chips with aluminum patterns produce a daisy chain that passes
through all bump-bonding pads. A probe pad was made in a loopof every two rows of pixel pads and cumulative and differential
resistances were measured. HPK has experimented with two
different types of solder bumps, lead (PbSn) and lead-free (SnAg),
and has been optimizing the fabrication process.

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Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 650 (2011) 129–135

4.1. PbSn solder bump bonding

4.2. AgSn solder bump bonding

One of the issues with solder bump bonding is the ‘underbump metallization’ (UBM), which is done either by electroplating or electroless-plating. On the ﬁrst dummy chips, electroplating UBM and PbSn solder bump deposition were applied at
IZM [19]. The UBM and PbSn solder deposition developed at
IZM not only ensure that the PbSn solder bumps are compatible
with FE-I3 chips with the solder bumps by IZM, but also are welldeveloped processes, which were carried out at high yield in the
ATLAS pixel modules.
The ﬂip-chip assembly was carried out at HPK. A number ofdummy chips were joined (bump-bonded) to make ﬂip-chip (FC)modules: FE-I3 or FE-I4 single-chip or quad-chip compatible FCs.
A typical proﬁle of the daisy chain resistance in the case of FE-I4
single-chip dummy FCs is shown in Fig. 8 (a), where it is clearlyseen that no open or little, if not none, shorted bumps exist, while
the resistance is equal to  0.14 O per bump. Subsequently, one of
the sample FCs underwent thermal cycling (10 times) between
30 and + 50 1C with a ramp-up/down time of 30 min. Still, no
opening of the bump bonds was observed.
Further FC samples were fabricated by HPK by applying
electroless-plating UBM on dummy and pixel sensors as a lowcost alternative to electroplating. Peel testing of the FC samples ofdummy chips revealed  50% of fractures in the solder bumps and50% at the boundary between UBM and the chips, which was
an evidence of uniform mechanical strength over the bump
structures.
A few FE-I3 single-chip compatible real n-in-p pixel sensors
with the electroless-plating UBM were bump-bonded with thereal FE-I3 chips and evaluated with the use of a test beam. A preliminary result showed that a good tracking efﬁciency of  99%
over the full sensor area was obtained, which means that thebump yield was  100% [20].

As the electronics industry is moving towards lead-freesolders, HPK also has fabricated FC samples, with AgSn solder
bumps and electroless-plating UBM, both of which were createdby HPK. The peel strength was found to be satisfactorily high andfractures were  50% in solder bumps and  50% at the boundary.
The typical proﬁle of the daisy chain resistance for a FE-I4 singlechip compatible dummy FC is shown in Fig. 8 (b). No opening or
little shortening of the solder bumps was observed, but theresistance varied and reached such high values as 15 kO per
solder bump. The resistance was found to decrease to o1 O perbump once a voltage of a few volts was applied to the daisy chain.
This result implies the existence of a thin insulating layer, whose
removal is currently being investigated.
4.3. Bumpless bonding at HPKIn the search for further low-cost bump bonding technology
for future use, we are looking into ‘bumpless’ bonding, particularly the development of a ‘thermal compression’ techniqueallowing an electrode of gold or copper to be fused while being
compressed at a temperature of 100–200 1C. It should be notedthat the chip-to-wafer bonding is of greater value than wafer-towafer bonding because of the difference in the wafer size andmore importantly the difference in yield for readout chips andpixel sensors. The technology will be evaluated when it becomes
available in the near future.

5. Summary
In our attempt to develop a state-of-the-art n-in-p silicon
microstrip sensor suitable for very high radiation environments,
e.g., under conditions of a ﬂuence of 1016 neq/cm2 that is expected
near the collision point in the upgraded LHC, we fabricated n-in-p
pixel sensors in two batches of different mask sets: batch #1
mainly for the pixel sensors that was compatible with the pixel
readout frontend chip called FE-I3 of ATLAS pixel detector, andbatch #2 for FE-I3 and FE-I4 compatible sensors, along with small
diodes used to evaluate the effects of the edge width and theguard rings.
Tests on the effects of the edge width and the guard rings
showed that the strong increase of leakage current was attributed
to the edge current when the lateral depletion zone reaches the
dicing edge and the lateral depletion along the surface of siliconwafer was correlated with the ‘ﬁeld’ width. For both p- and n-bulk
wafers used in this study, the strong increase of leakage current
was observed at a voltage of 1000 V when the total edge width
was equal to  400 mm. Pixel sensors diced at 450 mm could
successfully maintain a bias voltage of 1000 V.
Hybrid ﬂip-chip pixel modules were fabricated with dummy
and real chips that were bump-bonded at HPK. The lead (PbSn)
solder bump bonding was successful. The real FE-I3 single-chip
ﬂip-chip modules were tested in a test beam successfully. Leadfree (SnAg) solder bumps were created with relatively highresistance, possibly due to the formation of a thin insulating
layer, whose removal is currently under investigation.

Acknowledgments

Fig. 8. Typical cumulative (diamonds, left vertical axis) and loop resistance of two
rows (squares, right vertical axis) of a daisy chain of bump-bonded dummy chips:(a) with PbSn solder bumps and (b) with SnAg solder bumps.

This research was partially supported by the Grant-in-Aid for
Scientiﬁc Research (A) (Grant no. 20244038) and Research (C)(Grant no. 20540291) by Japan Society for the Promotion of
Science and the Grant-in-Aid for Scientiﬁc Research on Priority

Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 650 (2011) 129–135

Area (Grant no. 20025007) by the Japanese Ministry of Education,
Culture, Sports, Science and Technology.
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