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Nuclear Instruments and Methods inPhysics Research A
journal homepage: www.elsevier.com/locate/nima

Noise evaluation of silicon strip super-module with ABCN250 readoutchips for the ATLAS detector upgrade at the High Luminosity LHC
K. Todome a,c,n, O. Jinnouchi a,c, A. Clark b,c, G. Barbier b,c, F. Cadoux b,c, Y. Favre b,c,
D. Ferrere b,c, S. Gonzalez-Sevilla b,c, G. Iacobucci b,c, D. La Marra b,c, E. Perrin b,c, M. Weber b,c,
Y. Ikegami d,c, K. Nakamura d,c, Y. Takubo d,c, Y. Unno d,c, R. Takashima e,c, J. Tojo f,c, T. Kono g,c,
K. Hanagaki h,d,c, M. Hirose a,c, Y. Homma a,c, S. Sato a,c, K. Hara i,j,c, K. Sato i,j,caDepartment of Physics, Tokyo Institute of Technology, Ookayama 2-12-1, Meguro-ku, Tokyo 152-8551, Japan
DPNC, University of Geneva, CH-1211 Geneva 4, Switzerland
Solid State Div., Hamamatsu Photonics K.K., 1126-1, Ichino-cho, Higashi-ku, Hamamatsu-shi, Shizuoka 435-8558, Japand
Institute of Particle and Nuclear Study, KEK, Oho 1-1, Tsukuba, Ibaraki 305-0801, Japane
Department of Science Education, Kyoto University of Education, Kyoto 612-8522, Japanf
Department of Physics, Faculty of Science, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka 819-0395, Japang
Ochadai Academic Production, Ochanomizu University, 2-1-1, Otsuka, Bunkyo-ku, Tokyo 112-8610, Japanh
Department of Physics, Osaka University, Machikaneyama-cho 1-1, Toyonaka-shi, Osaka 560-0043, Japani
Institute of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Ibaraki 305-8751, JapanjCenter for Integrated Research in Fundamental Science and Engineering, University of Tsukuba, Tsukuba, Ibaraki 305-8571, Japanbc

art ic l e i nf o

a b s t r a c t

Article history:
Received 4 December 2015
Received in revised form
5 March 2016
Accepted 7 March 2016

Toward High Luminosity LHC (HL-LHC), the whole ATLAS inner tracker will be replaced, including thesemiconductor tracker (SCT) which is the silicon micro strip detector for tracking charged particles. In
development of the SCT, integration of the detector is the important issue. One of the concepts ofintegration is the “super-module” in which individual modules are assembled to produce the SCT ladder.
A super-module prototype has been developed to demonstrate its functionality. One of the concerns
in integrating the super-modules is the electrical coupling between each module, because it may increase
intrinsic noise of the system. To investigate the electrical performance of the prototype, the new Data
Acquisition (DAQ) system has been developed by using SEABAS. The electric performance of the supermodule prototype, especially the input noise and random noise hit rate, was investigated by using
SEABAS system.
& 2016 Elsevier B.V. All rights reserved.

Keywords:
ATLAS
Upgrade inner tracker
Strip module
HybridDC–DC converter
Noise
SEABAS

1. Introduction
The Large Hadron Collider (LHC) at CERN is the world's highest
energy particle accelerator. In order to signiﬁcantly increase theintegrated luminosity during one additional decade, the High
Luminosity LHC (HL-LHC) project is already planned. At the HLLHC, the instantaneous luminosity will be improved by at least afactor of ﬁve (up to 5  1034 cm  2 s  1 ). ATLAS is one of the general purpose detectors of the LHC, and it will be upgraded for its
operation at the HL-LHC. For the upgrade, the current innernCorresponding author at: Department of Physics, Tokyo Institute of Technology,
Ookayama 2-12-1, Meguro-ku, Tokyo 152-8551, Japan.
E-mail address: todome@hep.phys.titech.ac.jp (K. Todome).

tracking detectors of ATLAS will be replaced by an all silicon-based
tracker [1].
The SemiConductor Tracker (SCT) is one of the sub-systems of
the ATLAS inner tracker and consists of silicon micro-strip detector
modules [2]. The SCT will be upgraded for the HL-LHC. To evaluate
the performance, prototypes of each elements have beendeveloped.
One of the integration concepts for the upgraded strip detector isthe “super-module”. In the super-module concept, a SCT ladderconsists of individual double-sided silicon micro-strip modulesaligned on the support frames. Each double-sided strip module is a
top–bottom symmetric object composed of two silicon micro-strip
sensors glued back-to-back to a central Thermo-Pyrolitical-Graphite(TPG) baseboard and hybrids with readout ASICs bridged on the top

http://dx.doi.org/10.1016/j.nima.2016.03.018
0168-9002/& 2016 Elsevier B.V. All rights reserved.

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Fig. 1. Super-module prototype populated with eight double-sided strip modules.

of the sensors. Since each module is electrically and thermallydecoupled, the detector can be stable in the operation.
A super-module prototype has been developed to demonstrate
its electrical functionality (Fig. 1) [3]. One of the concerns for the
integration is to try to avoid any electrical coupling between
modules, as this may increase the intrinsic noise of the system. To
investigate the electrical performance of the prototype, a new dataacquisition system has been developed by using a multi-purpose
DAQ board called SEABAS [4]. In this paper, the electrical performance of the super-module prototype as measured with the
SEABAS system is described.
2. The system setup
2.1. The super-module prototype
The super-module prototype (see Fig. 1) consists of 8 doublesided silicon micro-strip modules, 16 BCC boards, 2 Super-Module
Boards, 32 DC–DC power converters, 2 sets of three types of bus
tapes and cooling pipes. These electrical components are mounted
on an aluminum support structure.
ATLAS07 [5] is the new radiation-tolerant strip sensor used forthe super-module prototype. ATLAS07 is produced in 6-in. wafers
by Hamamatsu Photonics. The sensor has a n-on-p structure andits dimension is about 10  10 cm2. The sensor contains four rowsof 1280 strips each with a single strip dimension of
2.38 cm  74.5 μm. The super-module prototype shown in Fig. 1
has more than 80,000 strip channels in total.
The signals from a sensor are processed by the ATLAS Binary
Chip Next 250 (ABCN250) [6] readout ASICs produced in 250 nm
CMOS technology. An ABCN250 chip has 128 readout channels,
and the chips are mounted in two columns of ten on the hybrid(Fig. 2). The ABCN250 ampliﬁes the signals from a sensor andoutputs a binary hit information at 40 or 80 MHz clock frequency.
The Buffer Control Chip (BCC) distributes operation signals
from the data acquisition system to two columns of ten ABCN250s
and multiplexes their output signals at 80 or 160 MHz. Two BCCs
are mounted on a BCC board which is an interface board between
two hybrids and the bus service tapes.
The low-voltage required to power the ABCN250s is provided
by SM01C DC–DC converters [7]. Each converter supplies a ﬁxed

Fig. 2. Picture of a hybrid containing 20 ABCN250 readout chips.

output voltage of 2.5 V by dropping the input voltage of 12 V
provided externally through the low-voltage bus.
Three different types of bus tapes have been produced at CERN
and used in the super-module prototype. A data bus distributes
the common LVDS signals to control both BCCs and ABCN250s, andit receives each multiplexed data stream coming from up to 16
BCCs. A high-voltage bus supplies the bias voltage to each sensor
individually and a low-voltage bus is used for powering the DC–DC
converters. Two sets of three different bus tapes are used for the
top and bottom sides of the super-module prototype [3].
A Super-Module Board (SMB) interfaces the off-detector highand low-voltage power lines and external control signals to thebus tapes. One SMB is used for one side of the super-module. Two
Analog-to-Digital Converters (ADCs) are mounted on the SMB tomeasure the temperature of each hybrid via its corresponding
surface-mounted thermistor.
The High-Voltage (HV) is supplied by iseg EHS8210n-F eightchannel HV-supply card loaded in ECH224 crate. The high- andlow-voltage power-supplies are operated through a custom-madeNational Instruments-LabVIEW [8] based control system.
2.2. The SEABAS system
A new Data Acquisition (DAQ) system has been developed inorder to evaluate the performance of the super-module prototype
by using a Soi EvAluation BoArd with Sitcp (SEABAS). SEABAS has
been developed as a multi-purpose DAQ board (Fig. 3). SEABAS has
two FPGAs (Virtex-4 XC4LVX25-10FF668) for user-FPGA and SiTCP[9]. The users can implement any logic into the user-FPGA to
operate devices under test and process their output data. SiTCP isused for communication between the user-FPGA and a computer.
SiTCP is a technology to realize TCP/IP and UDP communication
only with hardware logic in a FPGA without using any processor.
This allows Ethernet communication with low power consumption.
The maximum data transfer rate of TCP/IP with SiTCP in our system
is 100 Mbps by using 25 MHz operation clock and 1 Gbps with theFig. 3. Picture of the SEABAS board.

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Fig. 6. Results of strobe delay scan for hybrid 0.

Fig. 4. Patch card for the super-module prototype.

latest version of the SiTCP. UDP communication is used for slow
control due to its slow operation clock of 500 kHz.
The patch card (Fig. 4) was developed as the interface between
the super-module prototype and SEABAS. Two data buses arejointed with two 64-pin connectors to send operation signals fromSEABAS and data from hybrids both for top and bottom sides.
Our DAQ system is designed to make logic implemented inuser-FPGA as simple as possible, keeping the data processing
speed high enough. For that purpose, the encoding and decodingof commands and output data from the hybrids is done via software. The user-FPGA just generates operation signals for the frontend chips, receives data from them and stores them into a FIFO
memory. The data in the FIFO memory are sent to SiTCP with thespeciﬁc protocol and transferred to the computer via Ethernet.
This simple design of the ﬁrmware in user-FPGA allows to use thesame ﬁrmware to test different chips, requiring us to change only
design of the software in a computer.

Fig. 7. Results of threshold scan before trim scan.

The parameters of the chip conﬁguration need to be optimized
to operate the chips correctly. For that reason, the functionalities

to scan the chip parameters are implemented into our readout
system.
The ﬁrst optimization is for the readout timing. It is optimized
by setting two parameters, i.e., latency and strobe delay. The
readout chip stores hits into a pipeline which has 255 clock length.
Once a trigger is injected into the chip, the hits in the pipeline
corresponding to a certain time period before injecting the trigger(latency) are output. In the latency scan, the number of hits in each
strip channel is checked as a function of the latency as shown in
Fig. 5. In Fig. 5, latency of 112 is the optimal timing for readout.
After the latency scan, the timing of the injection pulse withrespect to the clock phase is adjusted by using strobe delay. Fig. 6
shows the hit efﬁciency as a function of strobe delay for each strip
channels. The rising edge ðT up Þ and falling edge ðT fall Þ of the region
with 100% efﬁciency are used to ﬁnd the optimal value of thestrobe delay (Topt), i.e., Topt ¼(Tfall  Tup)/4 þ Tup.

Fig. 5. Results of latency scan.

Fig. 8. Results of threshold scan after trim scan.

3. The evaluation of the system
3.1. The scan and the optimization

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Fig. 12. Gain distribution for all the modules. The dotted lines indicate theboundary between the hybrids.
Fig. 9. S-curve for a typical strip channel.

Fig. 13. Input noise distribution for all the modules. The dotted lines indicate theboundary between the hybrids.
Fig. 10. Response curve for a typical strip channel.

Fig. 11. Response curve in low threshold. Linearity is lost in lower threshold region.
Quadratic function is used as ﬁtting function for such region.

The last optimization is the trim scan. Before the trim scan, as
shown in Fig. 7, the results of the threshold scan for each channel
has a different threshold voltages to obtain 50% hit efﬁciency,
which is called Vt50, because of different offset of threshold foreach channel. The trim scan is determining an offset for eachchannel so that to achieve a uniform Vt50 across all the chips. Afterthe optimization, as shown in Fig. 8, the uniform Vt50 are obtained.
3.2. The evaluation of the performance
In order to evaluate the electrical performance of the supermodule prototype, the noise performances were estimated by the
distribution of hit ratio as a function of the threshold for a given
input charge for a given channel (so called S-curve, see Fig. 9). By
ﬁtting the S-curve as shown in Fig. 9 to a complementary error

function, the standard deviation of the ﬁtting function represents
the input noise. The standard deviation is in unit of voltage, but
the scale of voltage is depend on individual differences of preampliﬁer for each channels. Therefore, the input noise is evaluatedin unit of equivalent noise charge (ENC). To evaluate the input
noise in unit of ENC, the gain is used. The gain is determined fromthe slope of the response curve of the threshold scan, as shown in
Fig. 10. The response curve has a good linearity around the nominal operation threshold of 1 fC, however, loses its linearity inlower threshold region as shown in Fig. 11. The gain is, therefore,
obtained from the ﬁtting result around that linear region. The
input noise is determined as standard deviation, which is obtained
from the S-curve ﬁtting with 1 fC test pulse, divided by the gain.
The response curve is measured for all the modules expect for
hybrid 9 which had a problem in the powering with the DC–DC
converters.
Fig. 12 shows distribution of the gain for all the modules. The
average of the gain is 109 mV/fC. Fig. 13 shows distribution of the
input noise for all the modules. In Fig. 13, hybrid 11 (from 28,160
channel to 30,719 channel) and hybrid 31 (from 79,360 channel to89,119 channel) have large input noise which is assumed due tolarge noise created by the pulse generator in chip as
discussed later.
Except for hybrid 11 and hybrid 31, the average noise was 644
electrons. Only 0.3% of channels had an input noise larger than thespeciﬁcation value of the chip (750 electrons) [10]. The strips withnoise higher than 750 electrons localize at certain area, therefore,damage on the sensor is assumed to be the reason of thehigh noise.
The results shown in Fig. 13 were obtained by the measurementwith all the modules at the same time (simultaneous measurements). To evaluate cross-talks between hybrids and chips, wePlease cite this article as: K. Todome, et al., Nuclear Instruments & Methods in Physics Research A (2016), http://dx.doi.org/10.1016/j.
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Fig. 14. The input noise obtained in individual and simultaneous measurements.
Each point shows a noise value averaged over ten chips at each column in the
hybrids at the bottom side. The dotted lines indicate the boundary between eachhybrid.

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same side are electrically coupled. For that reason, the DC–DC
converter can pick up electrical noise from the others in the sameside which are operated simultaneously. That is assumed in thesource of higher input noise in the simultaneous measurement
than individual measurement.
As the last test, we performed a noise occupancy scan which isa threshold scan without any injected test charge to evaluate
random hit ratio. Since the random hit ratio is assumed to be low,
at most 106 triggers were sent at each threshold, then for eachchannel, a noise occupancy plot was obtained as shown in Fig. 15.
Since the random hit is observed only in low threshold regions,each threshold value was converted to equivalent charge by using
the response curve shown in Fig. 11. Each noise occupancy plot is
Q 0 Þ2Þ, then random hit ratio at Q¼ 1 fC was
ﬁtted with expð  ðQ 
2σ 2calculated.
Fig. 16 shows the random hit ratio at the threshold of 1 fC for all
the modules. Hybrid 11 and hybrid 31 have the same level of therandom hit ratio compared to the other hybrids, and it is inconsistent with higher input noise in these hybrids in response curvemeasurements shown in Fig. 13. The big difference of the input
noise between each hybrid in response curve measurements is
assumed to be caused by the noise generated by the pulse generator in the chip. The random hit ratio is evaluated by extrapolating ﬁtting function to 1 fC in noise occupancy plot shown in
Fig. 15, and the ﬁtting error on the hit ratio is less than 30% for
more than 96% of the channels, and the evaluated random hit ratio
distributes much wider. For that reason, the ﬁtting error is negligible. The random hit ratio is less than 10  13 for more than 90% ofchannels and 10  9 at the maximum.

4. SummaryFig. 15. Noise occupancy plot for a typical strip channel.

Fig. 16. Accidental hit ratio at 1 fC. The dotted lines indicate the boundary between
the hybrids.

performed response curve measurements for each hybrid on thebottom side of the super-module one by one without enabling theother hybrids (individual measurements). In order to save measurement time, only three points were taken for the response
curve in individual measurements. Fig. 14 shows the input noiseobtained in individual and simultaneous measurements. Eachpoint shows a noise value averaged over ten chips at each column
in the hybrids at the bottom side. Larger input noise was obtainedin simultaneous measurements on average. The differences of theaverages between simultaneous and individual measurements
were found to range between from 0.5% to 6.0%. The same channel
in the power-supply is used to provide power for operating all DC–
DC converters in one side, therefore, DC–DC converters in the

The super-module concept is one of the integration concepts of
the ATLAS SCT upgrade for the HL-LHC. A new simple DAQ system
has been developed by using SEABAS to investigate electricalperformance of the super-module prototype. The entire system
was successfully controlled and readout by the SEABAS system.
Furthermore, simultaneous and individual threshold scans andnoise occupancy scans were performed.
Two hybrids have larger input noise than the other as observedin the response curve of the threshold scan presumably due toproblem in DC–DC converters. Except for these two hybrids, theaverage of the input noise is found to be 644 electrons, with only
0.3% of the channels having larger noise than the speciﬁcation
value.
In reading out the modules individually, the noise decreased by
up to 6.0%, compared with the results of the simultaneous readout.
It is assumed that the differences came from DC–DC converters.
More than 90% of channels had lower random hit ratio than 10  13.

Acknowledgements
The research was supported and ﬁnanced in part by the Japan
Society for Promoting Science KAKENHI-A Grant number
20244038 and KAKENHI-C Grant numbers 20540291 and
25400298, KAKENHI for Young Scientists-B Grant number
26800156, the Ministry of Education, Culture, Sports, Science andTechnology-Japan KAKENHI for Research on Priority Area Grant
number 20025007, for Scientiﬁc Research on Innovative Areas
Grant number 23104002, Grants from the Swiss State Secretariat
for Education, Research and Innovation, the Swiss National Science
Foundation and the Canton of Geneva. We also thank the ITk pixel

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testbeam members who contributed to make these measurements
possible.

References[1] ATLAS Collaboration, Letter of Intent for the Phase-II Upgrade of the ATLAS
Experiment, CERN-LHCC-2012-022.
[2] ATLAS Collaboration, Final Report: ATLAS Phase-2 Tracker Upgrade Layout
Task Force, UPGRADE-PUG-2012-004, 2012.
[3] S. Gonzalez-Sevilla, et al., JINST 9 (2004) P02003.
[4] 〈http://rd.kek.jp/project/soi/SEABAS/〉.

[5] Y. Unno, et al., Development of n-on-p silicon sensors for very high radiation
environment, in: Proceedings of the 7th International Hiroshima Symposiumon the Development and Application of Semiconductor Tracking Detectors(HSTD7), Hiroshima, Japan, Nucl. Instr. Methods Phys. Res. Sect. A 636 (2011),
p. S24.
[6] F. Anghinolﬁ, et al., in: Proceedings of Topical Workshop on Electronics for
Particle Physics (TWEPP-09), Paris, France, CERN-2009-006, p. 62.
[7] C. Fuentes, et al., IEEE Trans. Nucl. Sci. NS-58 (2011) 2024.
[8] National Instruments Corporation, LabVIEW System Design Software.
[9] 〈http://research.kek.jp/people/uchida/technologies/SiTCP/〉.
[10] ABC-N ASIC Speciﬁcation Version v1.3.1, 12, 2008.

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