EtherNet/IP™ to the Edge – A Concept for"Low-complexity Ethernet”
Tom Weingartner
Analog Devices, Inc.
February 22, 2017

Dave Alsup
Analog Device, Inc.

Discussion Topics•

Why isn’t Ethernet at the Edge Today?

•Architecture of an Ethernet Node•Scaling an Ethernet Node•

Example of a Low-complexity Ethernet Node•

Future Directions•Conclusion

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Ethernet in Automation• Twisted Pair
• Distance (1km)• Power• Intrinsically SafeX

Drive down the size, cost, and powerof Ethernet, so simple devices talkdirectly with a controller

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2017 Industry Conference & 18th Annual Meeting
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Automation Architecture vs. Ethernet Complexity

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2017 Industry Conference & 18th Annual Meeting
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4Architecture of an Ethernet Node

• MAC filter logic of limited use• Process most Ethernet frames• Protocols increase Flash / RAM• Numerous high-speed pins
• Special layout considerations• Hard to provide isolation

Technical Track© 2017 ODVA, Inc.

2017 Industry Conference & 18th Annual Meeting
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5Mapping Ethernet to Node Architecture• Device application• TCP/IP Stack• Industrial Ethernet Stack• PTP stack (maybe)
Sockets Interface
SSL, TLS, etc.
LLDP,
RSTP,HTTP, SNMP, etc.
etc.

ARP, BOOTP, DHCP,ICMP, etc.

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2017 Industry Conference & 18th Annual Meeting
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6Scaling An Ethernet Node for Low-complexity

Target small-scale single-chipprocessing solution by reducing
oooProcessor speed / performanceFlash memory size
RAM sizeReduce interconnect complexity
from processor to network interfaceReduce pin-count and complexityof network interface
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2017 Industry Conference & 18th Annual Meeting
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Advanced MAC / Switch•

Instead of general filtering…
 perform intelligent / dynamic frame filtering and buffering before any frames arecommunicated to the processor•

Manage priorities among protocols– i.e. this ARP request isn’t for me, don’t send on– i.e. this ARP request in lower priority than incoming EtherNet/IP implicit message,
send EtherNet/IP message first••

Manage surges in frame receipt due to alignment of various protocols
Benefits– Reduces overall buffer space– Retain frames based on priority, application state, and processor load conditions– Substantially reduces the amount of data transferred to and processed by theprocessor

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2017 Industry Conference & 18th Annual Meeting
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Example Device with Low-complexity Ethernet

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2017 Industry Conference & 18th Annual Meeting
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Example Device Architecture
1.
2.

3.

Architecture using
current 4..20mA

Low-complexity Ethernet
concept provides similar:

4.

1.
2.

3.

1.

Processing power

2.

Memory footprint

3.

Total power budget

4.

Simple isolation scheme

Architecture using
Low-complexity Ethernet
concept
4.
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2017 Industry Conference & 18th Annual Meeting
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Future Directions••

Reducing the footprint of Ethernet opens the door to other possibilities
PHY-related– Ethernet over twisted-pair– Adding power– Adding Intrinsic safety Will the IEEE 10SPE effort get us these?

•Processor-related– Nano-stacks– IP-to-the-Edge versus Ethernet-to-the-Edge• i.e. stack versus no stack•

TSN down to the edge

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2017 Industry Conference & 18th Annual Meeting
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11Summary•The goal of low-complexity Ethernet is to reduce the power, area, and cost ofEthernet– It is a concept to bring Ethernet to resource constrained devices that may not evenhave a MAC•Device software has the biggest impact on complexity– Software footprint directly affects memory size – both Flash and RAM– The number and type of protocols directly affects processor selection•

Device hardware can be architected to help software manage complexity– Advanced MACs can offload software by providing more layer 2 processing– MAC / Processor Interface can be simplified from traditional MII•

Reallocating the MAC layer from the processor into the PHY creates theopportunity for the simplest processors to connect to Ethernet networks•

By using techniques previously identified (by Xu and Brooks), EtherNet/IP canbe scaled and placed on top of the concept of low-complexity Ethernet

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2017 Industry Conference & 18th Annual Meeting
All rights reserved.

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12

THANK YOU