Infrastructure for Big Data and AI
System Software and Application Research
Exploring Next-Gen
Memory Hierarchy

Inter-Cloud Infrastructurefor Big Data Analysis

To achieve higher performance and larger capacity on recent and futurearchitectures, we need to explore next-gen memory hierarchy, including
heterogeneous devices. Also placement of many-cores and memory devices can be reconsidered; 3D stacking of cores and memory chips may gomainstream in HPC/Big-data area.
Under such assumptions, understanding memory performance will be
more challenging for data and address traffic routed among many-cores,
which may often conform 2D mesh.
To analyze its effects, we have conducted preliminary measurements ofmemory latency from every core of Xeon Phi. We see 9% difference in thecurrent architecture; the effect will be expanded in future architecture wherechip cores are also stacked.

Building a Testbed Infrastructure on Overlay Cloud
Using SINET5 network infrastructure (100Gbps Network)
Cooperation with Cloud and Supercomputer
Providing the Science Data Repository
Testbed: Petabytes class object storage
Real System: Exabytes class object storage
Cloud and Supercomputer Federation
Development of collaboration technology between cloud andsupercomputer using TSUBAME 3.0 as a test caseAcademic Cloud@ Hokkaido Univ.

Apply cloud container technology
to Supercomputer for resourcecooperation with the Inter-Cloudetc.

33 32 25 24

NVM / FlashNVM / Flash

410161.2 161.2 163.1 163.2

35 34 27 26 19 18 13 12763Public Cloud Resource@ SINET Inter-Cloud

2171.3 171.4 168.2 168.3 166.5 166.5 162.9 162.9 161.5 161.5 163.8 163.7

Medium Bandwidth 2.5D DRAM
>64GBytes Capacity~3TB/s Bandwidth
NVM / Flash

170.9 171.0 168.1 168.1

3 nm UV fabrication

High Capacity Flash NVM>1 TBytes Capacity

5Low Latency 3D SRAM
>8GBytes Capacity>10TB/s Bandwidth

29 28 21 20 15

Photonic Network
VCSEL-based Multi-Port High Injection
1Tbps x 12 = 12Tbps

9168.9 168.9 166.8 166.8 163.6

8162.0 162.0

Exabyte DB on
Global Object Storage

31 30 23 22 17 16 11 10High Bandwidth& Secure Networkby SINET5

169.9 169.9 167.8 167.8 164.7 164.7 162.9 162.9

63 62 59 58 53 52 47 46 41 40

2.5D DRAM

3D SRAM

174.1 174.1 171.8 171.8 168.8 168.9 165.9 165.8 165.1 165.1

2.5D DRAM

3D SRAM

65 64 61 60 55 54 49 48 43 42 37 36

2.5D DRAM

3D SRAM

2.5D DRAM

Dataflow + Scalar Processor

VCSEL Optical
Launch Pad

VCSEL Optical
Launch Pad

175.7 175.6 172.8 172.8 170.5 170.6 167.3 167.3 166.2 166.2 167.7 167.8

SRAM
Neuromorphic Accelerator
TSV Interposer

TSV Interposer

Tight connection of Supercomputerand Inter-Cloud resources via SINET L2VPN

67 66

57 56 51 50 45 44 39 38

176.7 176.6

171.6 171.6 168.4 168.7 167.5 167.5 168.8 168.8

max: 176.7 (ns)delta: 15.5 (ns)min: 161.2 (ns)Organic Substrate

An Example of Future Architecture with 3D Stacking Technology
and Heterogeneous Memory

Memory access latency from every coreof Xeon Phi 7285. As the target ofaccess, one of MCDRAM modules,
placed close to core 4, 5 is used.

Acknowledgments. This research is supported by the New Energy and Industrial
Technology Development Organization (NEDO), Japan.

Cloud Resource@ NII

Cloud Platform@ Kyushu Univ.
@National Institute of Genetics

TSUBAME3 Bigdata Storage

Acknowledgments. These researches are supported by CREST, JST CREST
Grant Numbers JPMJCR1303 and JPMJCR1501.
(Research Area: Advanced Core Technologies for Big Data Integration).

Efficient Deep Learning for Video Processing

High-resolution Image Reconstruction on Supercomputers
CT is a widely used technology that requires compute-intense algorithms
for image reconstruction. We exploit the heterogeneity of GPU-accelerated systems by overlapping the filtering and back-projection stages on
CPUs and GPUs, respectively. We also propose a distributed frameworkfor high-resolution image reconstruction on state-of-the-art GPU-accelerated supercomputers. We demonstrate the scalability and instantaneous
CT capability of the distributed framework by using up to 2,048 V100
GPUs to solve 4K and 8K problems within 30 seconds and 2 minutes, respectively.
On CPUs

On CPUs

Input

On CPUs

Second Order Optimization for Deep
Distributed deep learning on thousands of GPUs forces the batch stochastic descent methods to operate in a regime where the increasing
batch size starts to have a detrimental effect on the convergence and generalization. We investigate the possibility of using second-order optimization methods with proper regularization as an alternative toconventional stochastic gradientdescent methods.

Scene Graph Prediction
Understanding higher-level concepts such as recognizing a scene in avideo stream requires algorithms that can leverage information beyond thepixel level. Graphs have been used to represent relationships between objects in a given image. A scene graph is a compact representation of animage that can represent both objects present and relationships between
them. We investigate the application of graph neural networks based
methods for designing efficient scene graph prediction models.

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Fine-to-Coarse Convolutional Neural Network for 3D HumanAction Recognition
Current convolutional action recognition models struggle to fully capture
the temporal dimension due to the required network depth. To avoid thisissue, we investigate a coarse-to-fine network architecture to learn
long-distance temporal dependencies.
The information of each body part is aggregated while respecting the structure ofthe body. We achieve state-of-the-art performance and improve it for two person interactions.

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ReducePresentation in SC19 Technical Program
iFDK: A Scalable Framework for Instant High-Resolution Image Reconstruction
Thursday 3:30pm-4pm @ Room 301-302-303

Acknowledgments.
This research is supported by CREST, JST CREST Grant Number JPMJCR19F5.

https://www.gsic.titech.ac.jp/sc19