The Design of PRESTO:
A Framework For Architecture Level Power Estimation
Chitaka Iwama, Luong Dinh Hung, Niko Demus Barli,Shuichi Sakai and Hidehiko Tanaka
This paper presents PRESTO, a framework for architecture level power estimation. To
enable ﬂexible adaptation to various hardware designs, PRESTO separates power model ofa hardware structure into three diﬀerent layers: technology layer, circuit layer and dynamic
behavior layer. Furthermore, to increase software reusability, circuit models are built usinga hierarchical approach. This paper explains the design of PRESTO and presents validation
results of analytical power models for logic gates and SRAM structure. A case study in which
PRESTO is used to evaluate an architecture level power reduction technique for caches is also
described.

1. Introduction
With recent trend toward higher clock frequency and larger transistor count, power and energy issues are increasingly important for modern
microprocessor design. In order to estimate andoptimize power at early design phases, many architecture level power estimation tools have been
proposed recently [5–7, 9, 11, 14]. Among them,those that use analytical power models are especially popular [6, 11], because the models by nature can be applied to a wide range of architecture
design. Unfortunately, from a software design
perspective, those tools are lacking the ﬂexibility
to make changes or extensions without requiring
major modiﬁcations to the existing implementations.
We have developed PRESTO, a framework forarchitecture level power estimation based on analytical power models. PRESTO emphasizes not
only on the accuracy of power models but also on
its ﬂexibility as a software tool. PRESTO employs the following software design policies:(1) Layering of power model : model for a hardware structure is divided into three modelinglayers i.e technology layer, circuit layer anddynamic behavior layer.
(2) Hierarchical circuit composition : model for alarge circuit is composed of models of smaller
subcircuits.
The ﬁrst policy makes it easier to modify or extend a model in one layer without aﬀecting otherlayers. For example, in order to model diﬀerent
process technologies, only the technology layer1needs to be modiﬁed. The second policy increases
the reusability of power model and the eﬃciency
of software development. Some components suchas decoder and memory cell can be repeatedlyused in multiple function blocks.
Taking advantage of the PRESTO’s layeredstructure, we added in the technology layer accurate device models based on analytical MOS
models of SPICE. Device parameters such as gate
capacitance per unit area are calculated directlyfrom SPICE model parameters. Thus, PRESTO
can model diﬀerent process technology provided
appropriate SPICE model parameter set. We
have conﬁrmed that the estimated energy constants of simple logic gates and SRAM cell arrays
are within 10% of accuracy against SPICE.
As a case study, we used PRESTO for evaluating a cache power reduction technique called
dynamic zero compression [12]. The hierarchicalcircuit composition helped to incorporate circuitlevel modiﬁcations of the proposed cache withsmall programming eﬀort.
The remainder of the paper is organized as follows. Section 2 describes prior work and explains
our contributions. Section 3 describes the structure of PRESTO and discusses the advantagesof the design from a software design perspective.
The power models implemented in PRESTO are
explained and validated in Section 4. Section 5
presents a case study on dynamic zero compression for caches. Section 6 concludes the paper.
2. Prior Work
Generally, there are two approaches for powerestimation : empirical approach and analyticalapproach. Empirical approach uses power datameasured with lower level tools. Several industrial companies have developed architecturelevel power estimation tools in this approach[7, 8]. SimplePower [14] and AccuPower [9] also
use power constants obtained from layout implementation and circuit level simulation. Analytical approach estimates power from transistorlevel schematic. CACTI [13] [10] [11] estimatescache access time, area, and energy consumption
per access based on an analytical SRAM model.
Wattch [6] models superscalar data path components using similar SRAM models, as well as several macro level assumptions on clocking power.
Combined with SimpleScalar tool set, it estimatesruntime power consumption of the simulated processor.
CACTI and Wattch are popular because of theinherent ﬂexibility of their analytical power models. However, we see many extensions and reﬁnements that should be made to those tools. For
example, CACTI uses 0.8um process parameters
and assume that both delay and energy consumption of a circuit scale linearly with technology feature size. This assumption is likely to produce
large errors as technology advances, so the parameters need to be corrected according to thelatest technology. Unfortunately, we found that
implementing the necessary extensions on thosetools is not straightforward due to the lack ofconsideration in their software design. Our motivation for developing PRESTO is to enhance theextendibility of these tools by carefully redesigning the software framework, and incorporate new
power models to improve their accuracy or widen
their use.
3. Software Design
3.1 System Overview
Figure 1 illustrates our system for architecturelevel power estimation, where PRESTO is combined with an instruction level performance simulator for general purpose superscalar processors.
First, PRESTO builds a power model for eachfunction block in the target processor. It deﬁnes
states of the block and power consumed when theblock is in each of the states. Then the performance simulator simulates execution of a given
binary and sends messages to PRESTO that contain access information on each function block.

2BinaryArchitecture
Configuration

DesignParameters

Instruction Level
Performance
Simulator

PRESTOTechnologyParameters

Energy Per Access
Access Statistics

Power Per Cycle
EnergyFig. 1 Architecture level power estimation usingPRESTO.

On receiving the messages, PRESTO collects access statistics and calculates power on a per-cycle
basis.
PRESTO takes design parameters and technology parameters as input. Design parameters include transistor sizes and wire lengths used inmodeled function blocks. To give an example,
there are about 50 parameters for a cache. Technology parameters include SPICE model parameters, interconnect parameters such as capacitance
per unit length, and several design rules such as
minimum wire spacing. Apart from those circuit level and device level parameters, architecture level conﬁguration parameters must be speciﬁed, such as cache size and number of ports. All
the parameters are listed in an input text ﬁle sothat they can be changed without recompilation.
3.2 Model Layering
PRESTO comprises three modeling layers:technology layer, circuit layer, and dynamic behavior layer. Figure 2 illustrates the relationshipbetween the three modeling layers using UML notation. The technology layer is implemented as acomposition of MOS FET, interconnect, and design rules classes. It calculates parasitics of thedevices using technology parameters given by theuser. The circuit layer manages design parameters speciﬁed by the user and describes circuit
structure. It then deﬁnes states of the circuit andpower consumption for each of the states. All circuits are implemented as subclasses of an abstractclass named Circuit. The circuit classes are technology independent : only when calculating absolute amount of power consumption, they makea request for device parameters to the technology
class. Dynamic behavior layer records runtimestates of the circuit such as activity factors of circuit nodes (i.e. the probability that an input signal to the gate causes a transition that consumes
energy). Each dynamic behavior class is linked toa circuit class. During binary simulations, it determine the current state of the circuit accordingDynamicBehavior

SRAM

Decoder

TechnologyCircuit

SRAM

Decoder

MOS
FETInterconnect

DesignRules

SPICE
ModelParameters

Metal
ProcessParametersDesignRules

NAND

DesignParameters

Fig. 2 Relationship between modeling layers.

to the messages from the performance simulator,and derives power consumption from the circuitclass.
The layering of the models enables modiﬁcation or extension of models in one layer withoutaﬀecting models in the other layers. For example,
all technology-dependent models are enclosed in
the technology layer, so that the circuit models
can be used over technology generations without
any modiﬁcation. It is also easy to replace or
add device models in the technology layer to exploit emerging technology characteristics. Similarly, the dynamic behavior layer decouples runtime characteristics of a circuit from its static
hardware structure. Changes in the dynamic behavior layer, including interface between the performance simulator, have little eﬀect on the othertwo layers.
3.3 Hierarchical Circuit Composition
Circuit layer follows a hierarchical design strategy. A circuit class can be built using one or moreother circuit classes that represent smaller subcircuits. Figure 3 shows the design of cache classin the circuit layer. The cache is composed ofdata arrays and tag arrays which are instances ofSRAM subbank class. The SRAM subbank class
Cache
Data : SRAMSubBank
Tag : SRAMSubBank
SRAMSubBank

DecoderNORNANDSRAMArray

INVWireSRAMCellFig. 3 Hierarchical implementation of cache class inthe circuit layer.

3comprises instance of SRAM macro class and decoder class, which are in turn built from instancesof logic gate class, wire class, etc.
Such implementation has two advantages.
First, some circuit classes can be repeatedly usedin one or more classes. In this example, SRAM
subbank class is used for both data array and tagarray. Decoder class can also be shared by otherclasses that comprises array structures, such as
register ﬁle. Second, any change in a subcircuitclass is automatically reﬂected to the classes thatuse it. If the decoder is replaced with another ofdiﬀerent design, the change is instantly reﬂected
to cache data array, tag array and register ﬁle,Those composite classes do not have to be awareof the modiﬁcation themselves. Thus, the hierarchical design improves software reusability, andreduces task of developing models for new circuitdesigns.
4. Power Models
4.1 Features
The fundamental power models currently implemented in PRESTO are similar to those usedby CACTI and Wattch. PRESTO estimates
dynamic power consumption based on the well2
known equation P = αfCVdd. Here α is activity
factor managed by the dynamic behavior layer,
and C is the equivalent capacitive load estimatedby the circuit layer and technology layer.
Unlike previous tools, however, PRESTO derives C using SPICE model parameters. Most
existing tools rely on empirical device parameters
tailored for them, so in order to simulate diﬀerent
process technology, user must extract the parameters using lower level tools or predict them fromthe parameters of the past generations. To enable more ﬂexible adaptation to diﬀerent process
technologies, we have implemented in the technology layer a class that calculates MOS capacitances directly from SPICE model cards [3]. The
class uses MOS model equations of SPICE in reduced forms : all terms that depend on potential
level of the MOS terminals are replaced by ﬁxed
constants. For example, drain capacitance is proportional to the reverse bias Vr at diﬀusion edge,
so we take an average assuming 0 ≤ Vr ≤ Vdd .
Using SPICE parameters, PRESTO can exploit process characteristics in a straightforward
way : diﬀerent process can be modeled bymerely preparing appropriate SPICE parameter2.50E-1420λ/40λ]F[ecnaticapactu
ptuo

20λ/40λ

PRESTO
SPICE
linear

130

100
7065
technology node [nm]40λ/40λ2.00E-14
1.50E-14
SPICE(max)PRESTO(max)SPICE(min)PRESTO(min)1.00E-14
5.00E-15
0.00E+00

45

23
number of inputs

4Fig. 5 Output capacitance of a NAND gate at 100nmprocess.

Fig. 4 Energy consumption of a FO4 inverter.

set which is widely recognized as a standard in
LSI design. If needed, however, user can also
selectively use empirical parameters instead of
the SPICE model parameters. Since the technology layer is decoupled from other layers, the device models can be exchanged without disturbing
other layers. It should also be noted that the calculation of the device parameters is usually done
only once at simulator initialization phase, so its
impact on the simulation speed is negligible.

1.20E-12
1.00E-12
read energy [J]

1E-13
9E-14
8E-14]
J[n 7E-14ioit 6E-14
snart 5E-14rep 4E-14
yg 3E-14rene 2E-14
1E-14
08.00E-13
PRESTO

6.00E-13

SPICE

4.00E-13
2.00E-13
0.00E+00
32x32 32x64 32x128 64x64 64x128
columns x rows

Fig. 6 SRAM read energy at 100nm process.

4.2 Validation
We validated our power models based on
SPICE parameters against HSPICE simulator itself. In all experiments, we used SPICE modelcards and metal parameters from Berkeley Predictive Technology Model (BPTM) [1].
We ﬁrst measured energy consumed by a FO4
inverter at a signal transition. Figure 4 shows
the results. For 130nm to 45nm technology, ourmodel was within 7% of error against SPICE. As
a reference, the ﬁgure also shows a simple estimation similar to CACTI, which assumes that,after 130nm technology generation, the energy
consumption scales linearly with the feature size.
It can be seen that the linear scaling does notmatch well to the predicted technology roadmap.
For gates that include series-stacked transistors,
the problem is more diﬃcult because their equivalent input and output capacitances depend on thepotential levels of the nodes in the stack. Figure 5
shows output capacitances of NAND gates with
diﬀerent input patterns. The output capacitanceof a NAND is maximum when all the inputs are
logical ’1’, because drain capacitances of all thestacked NMOS contribute to it. Conversely, thecapacitance is minimum when the top NMOS in
the stack is oﬀ. SPICE indicates that the maximum capacitance is larger than the minimum by
as much as 60% for the 4-input NAND gate. To4

account for the diﬀerence, PRESTO calculates
both maximum and minimum capacitance. An
user can use either of them according to his/herneeds. The estimations for maximum and minimum capacitances were both within 6% of accuracy.
Finally, we simulated a SRAM read operation
on a circuit that consists of memory cells, wordlines, bitlines and precharge transistors. Figure 6
shows the results for 100nm process. Our model
which ignores transistor’s non-linear characteristics overestimated capacitances of the pass transistors in the memory cells, but the error waswithin 10%.
5. Case Study : Dynamic Zero Compression for Caches
We used PRESTO to evaluate a recently proposed power reduction technique called dynamiczero compression (DZC) for caches [12]. The ideaof DZC is to compress zero byte data to reduce
SRAM access energy. For every zero-valued byte,
only a single bit ﬂag is read or written insteadof full eight bits. Thus, energy consumed by bitline swings can be reduced to approximately one
eighth of the baseline cache. In the original paper,Villa et al. evaluated the technique on a cache
implemented physically on 0.25um process. However, such experiment requires considerably large
eﬀort. PRESTO is useful to estimate potential
energy savings and explore a wider design space
before proceeding to lower level design phases.

5E-11
4.5E-11]
J[4E-11
3.5E-11da3E-11
err 2.5E-11
ep
2E-11
ygr
e 1.5E-11ne
1E-11

reported
PREST O

5E-12

5.1 Validation

0We implemented circuit layer models for a baseline cache and a DZC cache following the description of [12]. Because some details on the cachedesign are not given in the paper, we referredto [4] for memory cell size and sense ampliﬁer
energy constant, to SCMOS design rule [2] forwire spacings, and to [13] for the design of decoder and IO circuit. DZC requires circuit levelmodiﬁcations, such as adding zero-byte detection
logic and wordline gating circuit. In order to take
into account the overhead incurred by those additional circuits, we created their model by composing logic gate classes, and incorporated themto the baseline SRAM macro class. At dynamic
behavior layer, we modiﬁed cache class so that itrecognizes zero-valued bytes in the accessed data
and determines cache states accordingly.
In order to validate the model, we provided
PRESTO with device parameters of TSMC
0.25um process in which the cache was originallyimplemented and compared the estimated energy
constants with those reported in [12]. Figure 7
shows energy breakdown of the baseline cache forreading a 32-bit word. It can be seen that ourmodel shows similar characteristics as the original paper. Although we do not show the data
in detail, we have also conﬁrmed that estimation
for the maximum energy saving and overhead incurred by the DZC technique are close to the data
presented in the paper, 40% saving and 19% overhead per read and 67% saving and 17% overheadin maximum per write relative to the baseline
cache.
5.2 Experimental Results
Using our cache model, we estimated the effect of the DZC technique under diﬀerent conditions. The technology assumption is changed
from 0.25um to BPTM 0.10um process. Data
width is extended from 32 bits to 64 bits, andcache size is also increased accordingly.
We simulated eight applications from SPECint95
using our cycle-level simulator. The input param-5redocedeinldrow

einltibgatatadeinltiblatotsresesubOI

htoFig. 7 Breakdown of energy consumption for 32-bit
read accesses in base line cache.
Table 1 Processor conﬁguration assumed in the cyclelevel performance simulator.
Parameter
Pipeline stages
Arith/Logic units
Address units
Reorder buﬀer size
Load/Store queue size
Fetch/Decode/Rename/Retire width
L1 Instruction cache
L1 Data cache
L2 Uniﬁed cache]J 4m[ 3.5onti 3pm
sun 2.5
oc 2ygre 1.5en 1ehcac 0.5taa
d 0Conﬁguration
10426420
432 KB
32 KB
ideal

70
60
50
40
30
20energyS
av
ing[%baseline
DZCsaving]

10gom
sik88
m

ccg

sserpmcoli

egp
jilrepexrt
ov0Fig. 8 Data cache energy consumption.

eters for the applications are adjusted so that theexecutions ﬁnish between 100-300 million instructions. Processor conﬁguration used in the simulation is given in Table 1.
Figure 8 shows the eﬀect of DZC applied on aL1 data cache. The cache is 64B line, 2-way set
associative, 3-ported (2 read ports and 1 writeport), and is divided into macros of 128 rows of 64
columns. The energy savings range from 49% to59%, 55% on average. The savings are larger than
the results presented in [12] because of increased
percentage of zero bytes in 64-bit applications.

References

6. Conclusions and Future Work
This paper presented PRESTO, a framework
for architecture level power estimation based on
analytical power models. PRESTO emphasizes
not only on the accuracy of power models but
also on its ﬂexibility as a software tool. It separates power model of a hardware structure into
three diﬀerent layers: technology layer, circuit
layer and dynamic behavior layer. This is useful for modifying or extending a previously implemented model in one layer without aﬀecting
models in the other layers. Furthermore, circuit
models are built using a hierarchical approach toincrease software reusability.
In order to enable ﬂexible adaptation to diﬀerent process technologies, we implemented in thetechnology layer a model that calculates device
parameters directly from SPICE model parameters. Our power models on simple logic gatesand SRAM structure were approximately 10% of
accuracy against SPICE simulation. As a casestudy, we used PRESTO for evaluating dynamic
zero compression for caches. Taking advantage of
hierarchical circuit composition policy, we eﬀectively incorporated circuit-level design modiﬁcation required for the technique into the baseline
cache model. We then evaluated the techniqueunder diﬀerent conditions than the original paper, and showed its eﬀectiveness on wider datawidth and latest process technology.
Currently, PRESTO estimates only dynamic
power consumption. We are now working on themodel of static power as well which is an increasing portion of overall processor power consumption. We also intend to carry out further validation of power models at layout level and atlarger macro level. Finally, we plan to develop
models for various hardware structures and explore architecture level low power design spacewith PRESTO.
Acknowledgement
This research is partially supported by Grantin-Aid for Fundamental Scientiﬁc Research B(2)#13480077 from Ministry of Education, Culture,Sports, Science and Technology Japan, Semiconductor Technology Academic Research Center(STARC) Japan, CREST project of Japan Science and Technology Corporation, and by 21stcentury COE project of Japan Society for thePromotion of Science.

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