OVSNTWYZU\R[PQM]LX^_
cb eh `f ij mH nI gd Ja
oqiklkrspKty§£°áý-Òð¤z7MãQ§ ]Gâ¥áàð;3vÉÃðRÕâ×ê¨|£ã Register Promotion ÞÄÅ*½7ó!ÚÜ¤tó¦táiÍÐQ Register Allocation Þ$òÔÜ¤ztó/ÐÜÄðRÐÈÐQ¹mâ Register Promotion ãtýâéáºÏñÜ!òñÜÇïQ¤zóÃá/ÐÜÄðÞãÄÉñ
àÄR0Ýã1t¦S¬¦óBÄÜQ Register Promotion ótÝ!Å½ó»%ÒðRè×¤z/â^¢9ÞÐÜQ¦6é¥áÇÌðv3ó´ÐQtý Register Promotion ÞzçÜv3ÉiÒðÎÞó1Ð×R
Compiler Support for Load / Store PressureNaoya HattoriDaisuke Iizuka

Shuichi Sakai

Hidehiko TanakaGraduate School of Engineering, University of Tokyo

Abstract

Memory access instructions are potentially bottlenecks on processor performance. To reduce them,both Register Allocation and Register Promotion are performed in compiling phase. Register
Promotion is an important function to reduce explicit memory access instructions before Register
Allocation. Many algorithms have been presented for Register Promotion, but all of them are onlyintraprocedural. In this paper, we propose Interprocedural algorithm to overcome intraprocedural
limitation and demonstrate its capcacity in removing memory access.

øñúöï¦táÒðRÐÈÐQ/â Scalortã Register Allocation âáÒîÿÚÜ
52§ â±ÛO]G3LÉiÐÜ ÄàÄ×êQ8á¦É6áFBÝÊ×ÞÄðÉQ ALU ì FPU öÞ-àï§US ÐÜë¤zÉdàÈîÓ©ðR52Qz¢â]GOÁã¤z7M ¤zóîÒ,áPG¦ó 64 Ãâ1à(àâ×êáiÏÔþÄRè×Q% ðÄã 128 }Æ×íÅà§ ëñÜÄ§ âOÁÉiÉðáÛñQÎâ8ã ðÉQÎñÝã³Ð×¦É?áBÝ²áàðÞ ÆîñðR/ÝQ§£° ÊàÄRáã¤z7MÉdàÈîÓèñÜÇïQ§ ]Gâ¥áàðÞ Æ Register Allocation âÈîñÜÄðâîñðRÎâ;êáæ]Òð×êQU}~z ãQ (1) ¤z¦óªBÏñðtØÌÝàË¨|£â<áÇÄÜë ¡ (2) Global t â 2 ¾ÝÃïQJ¹ÞëzâBQ¦|¨â2 àßATà*½7â Ïñð'­É8ÝàÄ×êáQÐà¦1ÉàÏñÜÊ×ÉQÎâ°Ý¤z táãÝÊàÄRÐÈÐÎñîâtëztó/Òð Register Promotion (RP) ÞÄÅ '­É8à )Ýã¦táiÍ(Promotion) ÒðÎÞÉÝÊðRÎâ*½7É RP*½7ë±:ÏñÜÄðR
¹m¨|£ã Register Allocation ó!Ú ÝÃðRÜQ§£°â Scalor(|5O) tó;3à ÄEâ RP ãtýâéÝ!òñð×êQt
1

r=*g
r=*g
r++
*g=r

r++

*(p+0) = x*(p+4) = yF(p)*(p+0) = x*(p+4) = y
F(x, y)a = *(p+0)
b = *(p+4):
returna=xb=y:return*g=r

s 1: ©[à¥UáæÒð RPs 3: |¨1tóÐ×¤z (&)Þt RP Ý*½7Ïñ×U (3)t =*pÞÉòÈñäQÂ£¼á Load ó5­ÒðÎÞá
íïQz7Mâ¸!tó/ÒðÎÞÉÝÊð (s 23)Rs=*ps=t
ÄEâ RP ÝãQtâ|¨Èó!Å
ÎÞãÃÚÜëQU µåãtýâéÝ!ÚÜÄ×RÕâ×ê
(1) Global tóÐ×s 2: Speculative RPtâkµz (2) |¨1tóÐ×(Pro le UÉ~C)tâkµzó Promotion ÒðÎÞÉÝÊàÄRNÆä¹ãQØåæâ|¨ótÝ¿ÌÀÒ,áã8ÒðÉQ RP ótáÚÜzÏñð¤tó¦ Ý!ÆäÎñîâzë¦iÝ!òÔ
tá Promotion ÝÊàÈÚ×R0Ýã RPótá³ÐQÎñîâ¤tó 1t¦ ðÎÞÉÝÊð (s 3)RS¬¦á Promotion Òð½ó 3 Aòüvu RP»%S9ÒðR0½ã&6â½\Ý!ÅR
2Register Promotion
1. t|¨Èó!ÅR
RP[2, 5, 4] ã¤tó/²¼á¦
2. t2á 1tS¬â¸:áæ5Ð× RPtáiÍÒð*½7ÝÃðRÎâiÍáíÚ
ó½BÒð
Ü Register Allocation âÞàðtÉ×ÆQ 3. 7ÉàËàðèÝ ½ßÊ 2 ó6ïÒèòïá8´¼à¤zÉ/ÏñðR 4. ªBÐÜÄàÄ1tS¬ó/bÒðè× RP ãQ0E~CâàÄ¤zó/ÒðÞÄÅ*4Ý Partial Redundancy Elimi- RP ã|¨Èó~CÞÒðÉQ|¨nation(PRE) [1, 6, 3, 7] á°×ëãÄRÈã0â )ÈîñðâÝ"ÒðRNÆäs 1&ã¥Uâ°Ý§U¥t (3g) ÎÎÝãQ©át|¨ÈâUÉF
ó|¨¤¨ÒðíÅà§£ó´ÐÜ BÝÊðëâÞÒðRÄðRÎÎÝQ«Ý)èñ×ã Basic Block 0½ãÈ )â 2 jUUâ ¨ó!ÅóQ=0ã óÐÜÄðR*½7ÎâU ×êQ/Áá§£Ðåó*½7ÐíÅÞÒã&âíÅá¥Uýá¤zóôÝ ðÞ ¨KÉ78ÒðRÕÎÝ/â*½7 )ÐèÅ×êQ#Ýù.ãþÐÄRÐÈÐÎâNÝ ót©'áºÐQt2â RP óÀÛÒðèã§U¥t (3g) âz'­ã8Ý Ý6ïÒÎÞÝ!ÅÎÞÝÐåó*½7ÒðR
Ãð×êQ RP ó½BÒðÎÞÝs 13âíÅá ×ØÐt*½7á~CànãQ³áË8Ò
 ÏñðRè×Qs 2&âíÅà§£ ð8Òz7MáíïQtÝ¿ ÏñðRÝãQßâíÅá Load ó5­ÐÜëQ Load ¤z7MÞÐÜã¹mâ Load, Storeâ¸!tÉ×ÆÜÐèÅ;3vÉÃðRÐÈÐ ââáQ 2 Ûâ8Òz7M Pre-Loaded,Post-Stored ó Æð ( 1)R Pre-Loaded ã 3p
Pro le nöáíïäÄ=0â tÉãÄÎ
r=*pr=t7M

LoadStorePre-Loaded
Post-StoredH¥x 3p3pxx == 3p(3p) 1: (8Ò) z7MÞs°âH¥â¬ã¡áââtÝ Promotion ÏñÜÄÜÕâ¬É x ÝÃðÎÞó´ÒR Post-Stored ãQââtÉ Store Òð×êáÕÎÝ Store Òð~CÉàÄÎÞó*4ÒðRDxöCðó vw÷ RP0½áãQÎÊÝÇç×8Ò7Máæ5Ð×t2â RP É~CáàðRUÞàðtý
RP áã0*âz¥¤É½BÝÊðÉQÎ
ÎÝã%¸ÖÐ× Busy Code Motion óUáÐ×z¥¤óË8ÒðRÎâz¥¤ã&6â½\Ý!ÅR
1. 5*½7z7Mó 1 ÛÍë
2. ÍëÏñ×7MÞtýâ7Mâ(à´(3. Safety, Availability â ¨
4. z7M5­'­â º
5. U6. ÀÛÒðèÝ½ßÊ 1 V 5 ó6ïÒ
> #%
|¨ÈUó áQÍëÏñ×7MÞtýâ7Mâ(àó´çðR(à7ÞÐÜQ¸àúz¦æâz&áQ LoadÒðÈëÐñàÄ (May-Load) Þ Store ÒðÈëÐñàÄ (May-Store) óº§ÒðR8îÈáÍëÏñ×7MÞúz¦ózÐàÄ7Mã
6¯Òð (nop ÞÐÜ$Å)Rè×Q union öÝxÑð9É-àðzáÐÜãQ May-Load,
May-Store Þúöá$ÄQ RP áãBÄàÄëâÞÒðR
&'
U â,áãQ&6â 2 Ûâoó3×Ò~CÉÃðR
(a) 0E¦ÊàÄãÓâNó¦ÎÏàÄ(b) z7Mâ¸!tÉ×ÆàÄ3.1

3.1.1

3.1.2

Safety, Availability

FFT

F
T

Kill

Gen

TKillGenGen

Reuse

Reuse

TGenGenTs 4: DownSafety âÈNÞ PRE
DownSafety out[exit]= False
DownSafety
out[I ]\=DownSafety in[S]S 2succ[I ]

(1)
(2)

DownSafety in[I ]= Gen[I ] j(!Kill[I ] & DownSafety out[I ]) (3)s 5: DownSafety â0êÎñáãQ PRE â DownSafety (6á~ÓúÑ ¨ÉñðÞÄÅÞv) áÔõÒðÈÉ~CáàðRs 4ã PRE âù.ó´ÐÜÇïQ Gen
ÉÍëÏñ×kµà7MQ Kill É Gen æâÿLói`ÊÒð7MQ Reuse ã Gen â <ó)FBÒð7M óÐÜÄðR&âUã PRE á
íÚÜQ3âUáÏñðÉQ DownSafetyà'­á Gen ó5­ÐÜÄð×êQp×àNó¦ÎÐ×ïQ Gen â¸!tÉ×Æ×ïÒðÎÞãÃïÆàÄR×ØÐQ Gen ÉNó¦ÎÏàÄÎÞÉòÈÚÜÄðl$ìQ¾â¸!tÉòÈÚÜÄðl$áã DownSafety âÈã~C6ÄR
DownSafety ãs 4âíÅá7Mâi6âªÝ ¨ÏñQ )ýâÐÜâ7MáÛÄÜs 5â(2), (3) ¶óQ7É6ËàðèÝ6ïÐ ¨ÒðÎÝóûðR Gen[I]Q Kill ã 7M I É
GenQ Kill ÝÃðÈóÐQ DownSafety in[I] ãI â·ÎQ DownSafety out[I] ã I â· áÇÌð DownSafety óÒR¶ (1) ãQtÁªÝ
â DownSafety out Émá False ÝÃðÎÞó´ÒRè×Q succ[I] ã I â·á¸!Ïñð;3
vâÃð7MâÂ$ÝÃðRg+ã³ÊÝÇçðÉQ RP Ýã  2á´Ð×

DownSafety(PRE) Z
Gen kµ ¨Killâ <óÒð7M

L-Safety

L-Avail

S-Safety

S-Avail

LoadLoad,Pre-LoadedStoreStoreStore
Post-StoredZGenStore,May-StoreY

May-StoreY

May-LoadMay-StoreZ

May-Load,May-Store 2: Safty, Availability â0êB-0÷F0½ÝãQtáÚÜzÏñð¤tó1t¦S¬¦á Promotion ÏÔðR¹mâ Register Allocation ÝãQ1tÞ¬ãºtâ¦óBÄÜ¿ÌÀÏñðR¦ÉÜïðï¦ÉïõÜîñðâÝQ1tS¬ëÄ*4Ý Register Als 6: Avail âªBNlocation âáèñðRíÚÜQ¤t
ó1tS¬áfÒðÎÞÝtÝ RP ó!
ÅÎÞÉÝÊðR4 ÛâÞvó ¨Òð~CÉÃðRÎâÅÙ LoadeQ1tS¬æâ Promotion ã Callerâ DownSafety (L-Safety) Þ Store â UpSafety / CalleeâÑÝzÝÊð~CÉÃð×êQ
(S-Safety) ãQ Load / Store ó5­Òð'­ó(1) Global Scalor tR (2) z¦É 1t +üºÒð×êáBÄðRè×Q Load â Availa- ConstÝ´Ïñð¤tRâ 2 ¾áºÏñ
vility (L-Avail)Q Store â Availability (S-Avail)ðRã'­á0õá Load / Store É~CÈyÈó
?1$@9ºÒð×êáBÄðRÕñÖñã 2á´Ð×
AáQ DownSafety áÇÌð Gen Þ Kill ó' ¤tó1tá Promotion Òð,ëQÐçÆðÎÞÝ0êQè×°Ý DownSafety Þ týâ RP ÞúAáo (a), (b) ó3×Ò~CÉ-àðâÞvãi6óþá ¨ÒðÎÞÝ0 Ãð×êQ (1) Callee ÙÝÕâ¤tó~Ó
Load Òð (tâÌøÝ L-Safety) ÃðÄã (2)êðRÐÜâ CallSite Ý~Ó L-Avail ÝÃðâÄÓñ
Èó3×ÐÜÄðl$áîñðR()+*,"0½Ýãtýâ RP â,áQÎñîâoó3×Ò¤táæÐÜ&6â 3 Ûâ]Gó
Busy Code Motion ÝãQ7Mó DownSafety!ÄQ1tæPromotion Òð (s 7&X°)R
ÝÃð*i'¾á5­ÒðRs 4âl$ãQ Kill â·6Þ3iâ Gen â·ÎÉõÒðRÕÐÜ
ÃÚ× Gen ó Reuse áÒðR PRE âl 1. 1tó¸:Òð
2. CallSite â·Îá Load ó¸:Òð
$Q Reuse ÞÐÜãèÿ7MÉªBÏñðR
3.
Callee á Pre-Loaded ó¸:Òð
RP á4ÄÜëúAâ]Gó!ÅR Load /â,ã L-Safety ÝÃð*i'¾âÅÙQ L-Avail CallSite / Callee áÑá7Mó¸:ÒðÎÝàÄ'­á Load óÓÿÐQ â Load ãÐÜ ÞÝQ©ïâ]Gãtýâ RP á¤¯Òð (sèÿ7M (Load â Reuse áÔõ) á­ÊÆð 7°X3)R(s 6)R2!$@Store /â,ã S-Safety ÝÃð*6'¾âÅ
ÙQ S-Avail ÝàÄ'­á Store óÓÿÐQ â ¬â¸:]Gë1tâl$ÞúAáQ (1) Callee
Store ãÐÜ/b (Store â Reuse áÔõ) ÒðRâ return 7MÉ S-Safety ÝÃðl$ÃðÄã3.2*p ± zcall
y ==*px ±*p*p ± z
t±z

call
y ==*pt±yx±t

3.2.1

3.1.3

3.2.2

±*pz
F( )

y±±± *pz*pa*pF(a)F( )ya± *p± *p±±±±z
*paz
F(a)

F(a)

*pyay
F(a)

x± *pF

return tLRPx± *p:
returnFcallsiteF±a == *p*px:
returnF±a == *pax:
return± *pF( )z±x±F( )*pz± *pF( )y*pcallsite:
returnF±±x:(*p)
return x±±t F( )*pt*pz±±±t F( )*pty*pFLRP

nop:
(*p)
return x

LRP±±return t±±t F( )t == *py*pt F( )t == *pz
t±±t F( )t == *pyt± F( ) t± F( )nop*p ± t*p ± zy±tts 8: ¬â¸: (store â.ù?ï)°«­Â¨®­¯«²Â¨®­ëòêßâï ìã éìÞá ¥àìêíïâðð¶²¦*p±±t F( )t == *pz*p± *p:t±xx

Fs 9: ¬â¸: (store â.ù6Ð)s 7: 1tâ¸:
F± *pF( )y± *p:
t ± *px

callsite:returnFðíæééªæëéìÞá¯«­Â¨®­®«²Â¨®­®«­Â¨®­²«­Â¨­¶ÐÜâ CallSite Ý S-Avail ÝÃðl$áã&6â 3 Ûâ]Gó!ÄQ Store ótæÆÒ(s 8&X°)R
1. ¬ó¸:Òð
2. CallSite â·á Store ó¸:Òð
3. Callee â return 7Mâ·Îá Post-Storedó¸:ÒðÎâQtýâ RP áíïzÉ/Ïñð (s 8°X3)R×ØÐQi¥oó3×ÏàÄl$Ýë(3) Callee â return 7MÉ L-Avail ÝÃðl$ÃðÄã (4) ÐÜâ CallSite Ý~Ó L-Avail ÝÃðl$áã Load ó/Òð×êá¬ó¸:
Òð (s 9&X°)RÎâl$â]Gã&6âíÅ
áàðR
1. ¬ó¸:Òð
2. CallSite â·á Pre-Loaded ó¸:Òð
3. Callee â return 7Mâ·Îá Load ó¸:Òð(2)ýûïõî heuristicÎÊÝÇç×½óBÄðÞ Global Scalor tóÐÜ¦táiÍÒðÎÞÉÝÊð
ÉQèòïáéKâ spill É8xÒð4ñÉÃðR
s 10 ã compress95 á bigtest.in óÿLÐ×l$â load Þ spill-in â¸!tó´ÐÜÄðR3.3spill­«­Â¨­­¿¾ÐÂÉÏÍÄÏÍ

ÃÒÉÉs 10: SPARC allocation rule Ýâ spill tÎâ´(Ýã Register Allocation Rule ÞÐÜSPARC ¥ (1t¦ 6 0Q¬¦ 1 0) ó8ºÐ×R×ØÐ spill tówá4#Òð×êá Register Window 7MâªBã{Ì×R":ãÕñÖñ 5*½7U (BASE)Qtý RP âU (LRP)QÐÜâ GlobalScalor zó¼ïbÄ×U (FULL) ÞÇÒð¡U¤{óBÄ×t RP âU (GRP) ÝÃðR FULL Ýã spill tÉéKá×ÆÜÄðRspill É×Æ×âãtâ Life Time ÉµËàÚ
××êÝÃðÉQÎñã»á call 7MóÄÝxÊðtÉ×:Ð××êÞ ÆîñðRÕÎÝ FULL áæÐQ call óÄÝxÊðtó:ÆàÄ ÞÄÅu>ó:ÆðRÎâu>ã ÎÊâ z7MÞ call â7óÐÜ May-StoreÞÒðÎÞÝ3×ÒÎÞÉÝÊðRu>ó:Æ×l$â <És 10â GRP ÝÃðÉQ FULL ÞzÒðÞ«á spill tÉDÆîñÜÄðRè×Q SPARC Allocation Rule Ýã
GRP É LRP íïëÕ load tÉãËàÚÜÄð
ÉQÎñã Allocation RuleQüá¬¦tóÒðÎÞÝ@+áÏÏñðÞ ÆÜÄðR®«µÂ¨®­ÄéìßÞé ¾ïïÞöÒëèëìôë®«±Â¨®­¾ïä¥¨àìëðñ¦ëòêßâï ìã éìÞá ¥Ïâäº¦®«³Â¨®­ÄéìßÞé ÐàÞéìï®«¯Â¨®­®«­Â¨®­µ«­Â¨­¶³«­Â¨­¶±«­Â¨­¶¯«­Â¨­¶­«­Â¨­­¿¾ÐÂ ÉÏÍ ÄÏÍ ¿¾ÐÂ ÉÏÍ ÄÏÍ ¿¾ÐÂ ÉÏÍ ÄÏÍ ¿¾ÐÂ ÉÏÍ ÄÏÍ ¿¾ÐÂ ÉÏÍ ÄÏÍàìêíïâðð¶²

êµµèðæêéæ

æçíâääì

s 11: ¦W¥á­Ìð RP v3z.E»%½ó9Òð×êáQ¬¹1_â C¨|£ [8] â°UáæÐQ0½â§U/ó¸ÖÐ×R01ã*ÁUâ¤ztódÏÔðÎÞó:¼ÞÐÜÄðÉQ-Q Register Allocation èÝâ1á®ÚÜÄàÄ×êQ¦6é¥Ý
9ó!Ú×R SPECint95 â 5 Ûâ§£áÒð <ós 11á´ÒR§£æâÿLÞÐÜã ref óªBÐÜÄðRÅ·ãQ¦6é¥Ýâ§Uâtó´ÐÜÇïQ":ãÎÊâëâÞúÑÝÃðRè×Q£°â
Global Scalor ã FULL z¥¤ÝÐ/b;3àzQ Arg + Const ãQ|¨1tóÐ×zÝÃïQÎâ 2 ÛÉ GRP âæháàðR Global Array ã RP âæhÝÃð×ê LRPQ GRP Þëztã/ÝÊàÄR
Îâ£Ýã ijpeg Þ go ã LRP Þ GRP
â'ÉñÜÄàÄRÎñã GRP âæhÞàðGlobal Scalor ì Arg + Const æâzÉdàÄ×êÝÃïQÎñîáæÐÜã GRP ó½B
Òð9¬ã6ÄÞÆðRÐÈÐQ compress95,m88ksim, li áÐÜã GRP âæhóãËôÝÄð×êQ GRP ã LRP íïãËâ Load ó/ÝÊÜÄðR4Æð heuristic ó:Æ×l$ÝëQ LRP íïãËâ§Uó/ÝÊÜÄðÎÞó1Ð×R%â=êÞÐÜãQ&6â¾É2ÍîñðR
%BÄ×¡U¤{ãQ¸,â¦tì callee âéÊÏó IÐÜÄàÄR¦
?¥á½BÏÔð×êáQíïÄ¡U¤{ó %Òð~CÉÃðRè×Q Busy
Code Motion ÝãàËQ Lazy Code Motion Uâ RP ë÷Òð~CÉÃðR%ã SPARC
¥Ýâ spill táíð9ÝÃÚ×ÉQ0*â¦tS Allocation Rule Ý9ó!Å~CÉÃðRáQ Pro le Uó<¼áªBÒñä týStâ RP âv3ÉiÒð×êQ Pro le óBÄ×l$âv3ó9ÐàÇÒ~CÉÃðÞ ÆÜÄðR8701órêðáÃ×ïQ¬¹1_âcì2­Q9áÚ­á¨|£âªB3íÿåº¢¼àaó¶ÊèÐ×RqËº®ÐèÒR
64/9[1] Bodik, R. and Gupta, R. and So a, M.L. Complete
Removal of Redundant Expressions. Proceedingsof the ACM SIGPLAN'98 Conference on Program-, pp. 1{ming Language Design and Implementation

14, 1998.

[2] Keith D. Cooper and John Lu. Register Promotion
in C Programs. PLDI, pp. 308{319, 1997.
[3] Gupta, R. and Bodik, R. Register Pressure Sensitive Redundancy Elimination. Lecture Notes in
Computer Science, No. 1575, pp. 107{121, 1999.
[4] Raymond Lo, Fred Chow, Robert Kennedy, ShinMing Liu, and Peng Tu. Register Promotion bySparse Partial Redundancy Elimination of Loadsand Stores. SIGPLAN, pp. 26{37, 1998.
[5] A.V.S. Sastry and Roy D.C. Ju. A New Algorithm
for Scalar Register Promotion Based on SSA Form.
SIGPLAN, pp. 15{25, 1998.
[6] Ste en, B. Property Oriented Expansion. Lecture
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