ＳＯＩピクセル検出器とその応用

Mar. 3, 2016, @筑波大CiRfSE
Yasuo AraiHigh Energy Accelerator Research
Organization, KEK
yasuo.arai@kek.jp
http://rd.kek.jp/project/soi/
1

I. Introduction
Silicon-On-Insulator Pixel Detector (SOIPIX)

Monolithic Detector having fine resolution ofsilicon process and high functionality of CMOS
LSI by using a SOI Pixel Technology.

2

OutlineI.
II.

Introduction
Recent Progress*Layout Shrinking with NMOS‐PMOS merge*Double SOI Wafer & Process*Higher Dose LDD*Compensation with TunnelingIII. Summary

3

SOI Pixel検出器の特徴• 機械的接合がなく、半導体微細加工のみで製造。
高信頼性、高分解能、低価格が望める。
• 超薄型センサ(~50m)による、多重散乱を防ぐ荷電粒子検出。
厚い空乏層(~500m)による、X線・赤外線への高い感度。
• 高度信号処理回路やメモリーを持つインテリジェント・ピクセルが可能に。
• 過酷な環境（極低温、放射線）への強い耐性。
• 基本は産業界の標準技術。
（技術発展の取り込みが容易）
日本発の最先端技術。
4

Lapis (*) Semiconductor 0.2 m FD-SOI Pixel Process
Process

0.2m Low-Leakage Fully-Depleted SOI CMOS
1 Poly, 5 Metal layers.
MIM Capacitor (1.5 fF/um2), DMOS
Core (I/O) Voltage = 1.8 (3.3) VSOI
wafer

Diameter: 200 mm, 720 m thick
Top Si : Cz, ~18 -cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz (n) ~700 -cm,FZ(n) ~7k -cm, FZ(p) ~25 k -cm etc.

Backside Mechanical Grind, Chemical Etching, Back sideprocess Implant, Laser Annealing and Al plating(*) Former OKI Semiconductor Co. Ltd.

5

SOI Pixel Collaboration6

2014.10 Submit

15.3 mm

Multi-Project Wafer (MPW) run.
(1~2 runs/year)

2015.6 Submit
XRPIX524.6 mm~25 Designes/Mask
7

新学術領域研究(FY2013~2017)計画研究
研究班
A01
A02
B01
B02
C01
C02
D01
D02

研究代表
新井康夫
(KEK素核研)
川人祥二
(静岡大）
鶴剛
（京大）和田武彦（宇宙科学研）坪山透（KEK)
初井宇記（理研）
岸本俊二（KEK物構研）
粟津邦男
（阪大）

研究課題名
SOI ３次元ピクセルプロセスの研究
SOI技術を用いた極低ノイズ・高速イメージングデバイスの研究
宇宙最初期ブラックホールの探査研究を実現する衛星搭載
Ｘ線精密イメージングの開拓
ダストに隠された宇宙の物質進化を暴く 極低温SOI赤外線イメージングの開拓
高輝度加速器実験のための素粒子イメージング
X線自由電子レーザーによる超高速ナノ構造解析用検出器
放射光を用いた空間階層構造とダイナミクス研究のためのイメージング
投影型イメージング質量分析による迅速で高解像度な生体内分子イメージング

8公募研究(FY2014~2015)
タイトル

研究代表

所属

ＰＳＳ－ＳＯＩ高分解能検出器の開発および応用

島添 健次

東京大学

ワイドレンジプラズモンフィルタを実装したＳＯＩ量子イメージセンサの開発

小野 篤史

静岡大学

軟Ｘ線用の背面反射回折環二次元イメージング機構
佐々木 敏彦の開発
究極のエネルギー分解能を持つ大面積Ｘ線検出器の石野 宏和
開発ＸＲＰＩＸの位置分解能向上とＧ２格子不要のＸ線タルボ干渉計の開発
中性子星の磁場構造を解き明かすX線偏光イメージャーの開発研究
ＳＯＩ技術を用いたイメージセンサの重粒子線への応用

金沢大
岡山大学

林田 清

大阪大学

平賀 純子

東京大学

松村 彰彦

群馬大学
93D Tomographi with Syncrotron X‐rayINTPIX4Pixel Size : 17 um x 17 um
No. of Pixel : 512 x 832 (= 425,984)
Chip Size : 10.3 mm x 15.5 mm

•••
•

Dried
SardineSensor：INTPIX4 FZn, Backside Illumination
HV：200V、Integration Time：1ms、ScanTime：320ns/pix, 1000frame/event
KEK PF, X‐ray Energy：9.5keV
Took images for 0~180°at every 1 degree.

(by R. Nishimura, K. Hirano (KEK)10

INTPIX4: Computed Tomography with Syncrotron X‐ray3mm(by R. Nishimura, K. Hirano (KEK)11X線回折による金属の歪み測定(協力：金沢大佐々木敏彦 教授
12

STJ (Superconducting Tunnel Junction) on SOI
筑波大、KEK,、産総研(CRAVITY)、TIA

Signal from Nb/Al STJ on SOISOI transistors work attemperature below 1K.
By building STJ sensors
on SOI, multiple
channel readout
becomes possible!

NMOS
at 960mK

PMOS
at 750mK13II. Recent Progress*Layout Shrinking with NMOS‐PMOS merge*Double SOI Wafer & Process*Higher Dose LDD*Compensation with TunnelingLayout Shrink （Active Merge)
SOI

Bulk CMOS
PMOS

NMOS

N-Well

P-WellIn the SOI process, it ispossible to merge NMOS
& PMOS Active regionand share contacts.

PMOS

NMOS

ShareContacts

Salicide Connection 15

Single Port SRAM Bit Cell
BLBLB

WL
VSS

VDD
Nch

Pch

Nch

Cell Size : 3.94m X 3.06m = 12.06m216

Dual Port SRAM Bit Cell
BLB(WRITE)

BL(WRITE)WL(WRITE)WL(READ)BLB (READ) BL (READ)
Nch

VSS

VDD
Pch

Cell Size : 6.90m X 2.50m = 17.25m217SRAM Cell Size Comparison
DP‐SRAM
17.25m2

SP‐SRAM
12.06m2

K. Nii, et al., Symp. VLSI Circuit Digst., PP. 130‐131, 2006

Cell size of the SP- and the DP-SRAM is almost comparable to thatof advanced commercial products.
18

New D Flip‐Flop
25% of Previous Cell

19

15bit Counter + Overflow bit with Serial I/O

13.2um x 36.3 = 479 um220

II. Recent Progress*Layout Shrinking with NMOS‐PMOS merge*Double SOI Wafer & Process*Higher Dose LDD*Compensation with Tunneling

Single to Double SOI

Double SOISingle SOI• Shield Sensor–CircuitInterference• Compensate radiationinduced oxide trap
chargeMetal 5

Cross section of the Double SOI PixelMiddle SiTransistor

Metal 1Sensor
Contact

Middle SiContact

Structure of 2 kinds of Double SOI wafer
Layer

D‐1

D‐2

SOI1

p‐type 88 nm,<10 •cm
145 nmp‐type 88 nm,<10  •cm
145 nmp‐type 88 nm,<10  •cm
145 nmn‐type 150 nm,<10  •cm
145 nmn‐typeCZ, 725um,>700  •cm

p‐typeLow Oxygen CZ, 725um,>1.0 k  •cm

BOX1
SOI2
BOX2
Substrate24

Sheet Resistance of the Middle Si (SOI2)
VSOI2+0.2VSOI20V
VSOI20V

Sheet resistance of themiddle Si changes dependon its potential.
D-2 wafer has lower
resistance in operationregion.

Operation Region

25

Single SOI

By using Double SOIwafer, Cross Talk
between Circuit andSensor is reduced to
1/20.

Double SOI(by Lu Yunpeng (IHEP))
26

Gamma-ray Irradiation Test
(Id-Vg Characteristics v.s. SOI2 Potential)

I/O normal Vth
Source‐Tie Tr.
L/W =0.35um/5um

NMOS

100 kGy

0 kGy

Vg[V]

VSOI2=-5V
Id[A]

VSOI2=-2V
Id[A]

Id[A]

VSOI2=0V

100 kGy

0 kGy

0 kGy

Vg[V]

Vg[V]

By setting Vsoi2 ~ -5V, Id-Vg curve returned
nearly to pre-irradiation value at 100 kGy(Si)(by U. of Tsukuba)

27II. Recent Progress*Layout Shrinking with NMOS‐PMOS merge*Double SOI Wafer & Process*Higher Dose LDD*Compensation with TunnelingVariation of Id-Vg Characteristics
and Effect of SOI2 Potential

0 kGy

0 kGy

0 kGy

100kGy100kGyVg[V]Vds=‐0.1V

Linear Id

VSOI2=-5V
Id[A]

VSOI2=-2V
Id[A]

Id[A]

VSOI2=0VPMOSI/O Normal Vt
Source‐Tie
L/W =0.35um/5um‐80%

Threshold voltage shift is not solarge in PMOS, but Drain Current
decreases much .

112kGy29

Dose Increase in Lightle Doped Drain (LDD) Region• Major cause of the drain current degradation by radiation is Vt
increase at gate edge due to positive charge generation in spacer.
• Charge in spacer control the Vt of the parasitic transistor.
• To reduce this effect, lightly doped drain (LDD) dose should beincreased.
• Present process has rather low dose in LDD region to aiming lowerpower.

Parasitic transistor
P+Parasitic transistor

Gate
P‐P‐P+BOX
LDD（Lightly Doped Drain)(by I. Kurachi)30

Id‐Vg Characteristics in Triode Region
Present Process

LDD Dose x 6

Linear Id

Vds=‐0.1V

Vds=‐0.1V

0kGy

0kGy

112kGy112kGyWith increasing Implantation dose of PLDD region 6 times higher thanpresent value, the degradation is reduced from 80% to 20% at 112 krad(Si).
Ref.) I. Kurachi, et al. "Analysis of Effective Gate Length Modulation by X‐Ray Irradiation for Fully Depleted SOI p‐MOSFETs, IEEE Trans. on
Elec. Dev. Vol. 62, Aug. 2015, pp. 2371‐2376.
31Ultra-Low Temperature Operation
One of the feature in SOI transistor is operation capability in ultra-lowtemperature.

Drain Current Increase due toincrease of carrier mobility

3K
Room Temp.

Slow rise in low Vds region!

32

Improvement in Ultra-Low Temperature

3K
Room Temp.

Vds [V]LDD x 10
Ids/W [A/m]

Ids/W [A/m]

Present Process

Pch Transistor
Source-Tie type 2
L=1um, W=10um

Vds [V]

By increasing the LDD dose 6~10 times, characteristic ofthe transistors becomes smooth in Ultra-Low Temperature.
33

II. Recent Progress*Layout Shrinking with NMOS‐PMOS merge*Double SOI Wafer & Process*Higher Dose LDD*Compensation with TunnelingVd=1.8V

HV Impulse Application+140V (~3 s)

Vpulse
GS

BOX

n-+

D+BPW+++PS

Threshold shift with radiation isrecovered by applying a HV pulse
to under‐layer (SOI2 or BPW) oftransistor.
However, Leakage current wasincreased.
35

We assumed the origin of the leakage
current is Trap Assisted Tunneling.
If so, the leakage current should
disappear when an inversion layer isgenerated at the bottom of the transistor.

GSBOX

BPW

xxx

DPSn-36

Confirmation of the Trap Assisted TunnelingAfter VBPW= +140V
AfterVBPW= -140V

After generating an inversion layer at the bottom of thetransistor by applying negative pulse to the BPW layer, draincurrent become insensitive to the back gate (BPW) voltage.
37

Removing Radiation
Induced Oxide Charge withFN Tunneling

Preliminary+140V (~3 s)-140V (~3 s)

VpulseGSBOX+D+

BPW+++PSRadiation damage is recovered byapplying Plus‐Minus HV pulses tounder‐layer of transistor.

n38

Summary of Solutions in SOI pixel detector
BackGateEffect

UnVtSensor
IdId slow
Circuit Shift isotropic degrad
risedamage@Low
Interfer
ation
bybyTemp.
byence radiation radiation
radiation

Buried Well

○X

△

△--

Nested Well

○

△△

△

--

Double SOI

○

○

○

△

--

Higher LDD
Dose----○○FN Tunneling--○○--39

III. Summary•SOI Pixel 検出器は放射線センサーと読み出し回路とを一体化したモノリシック・センサー。
•SOI Pixelの相乗りプロセス(MPW run)を年1~2回行い、様々な検出器を開発している。
•新学術領域研究では、高エネルギー物理以外の、X線天文、放射光、宇宙遠赤外線、イメージング質量分析、等様々な分野の研究者が参加している。
•Double SOIウエハーや、新センサー構造、STJ等のさまざまな提案があり、放射線耐性の向上、複雑な機能の内臓、感度の向上等に向け新たな研究が進んでいる。
•次回MPWランは5月中旬締切。次回研究会を6月28-29日北大で行う。
40