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Speculative Multi-Path Execution Mechanism forSuperscalar Architecture

Yuichiro Ajima, Tomohiro Nakamura, Kenji Kise, Hidenori Tsuji, Hidehiko Tanaka
University of Tokyo, Graduate School of Engineering
We propose a speculative multi-path execution mechanism for superscalar architecture.
Branch miss-predictions cause serious penalties for a superscalar processor with deep
pipeline and multiple instruction issue system. Speculative multi-path execution reduces the branch miss penalty and improve processor performance. Our evaluation
results show that our mechanism improves processor performance by 3% to 10%.

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