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Architecture
Yuichiro Ajima, Hidenori Tsuji, Shuichi Sakai, Hidehiko Tanaka
University of Tokyo, Graduate School of Engineering
We propose the Very Large Data Path (VLDP) Processor Architecture which achieves
actual IPC 8 by using Multi-Path Execution and Massive Speculative Execution. This
paper presents execution mechanism for VLDP; the Multiple Execution Unit and Distributed Register can issue many instructions in a cycle and continue processing withpartial instruction invalidation when a branch is mispredicted. We also discuss processof register data transfer, execution unit assignment and instruction invalidation.

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