Selected Papers

Software Defined Radio Prototype (II) – Implementationand Evaluation of IEEE 802.11 Wireless LAN
Takashi Shono† and Munehiro Matsui
Abstract
We discuss the design of an IEEE 802.11 wireless local area network (WLAN) based on our prototype
software defined radio (SDR) transceiver that supports both Personal Handy-phone System (PHS) and
WLAN. The most difficult problem in implementing the WLAN in this way is meeting the short interframe space (SIFS) requirement of the IEEE 802.11 standard. We describe the software architecture of
the prototype and explain how it can process the IEEE 802.11 WLAN protocol. The hybrid programmable architecture of our SDR is a sophisticated combination of a general-purpose microprocessor, digital signal processors (DSPs), and programmable hardware. The media access control (MAC) layer functions are executed on the central processing unit (CPU), while the physical (PHY) layer functions suchas modulation/demodulation (MODEM) are processed by the DSP; higher-speed digital signal processes run on a field programmable gate array (FPGA). We also describe an experimental evaluation of the
prototype for IEEE 802.11 WLAN use.

1. Introduction
As mentioned in previous papers in this issue [1],[2] and other papers [3]-[5], software defined radio(SDR), whose radio functions can be changed byreplacing software instead of replacing hardware,
seems to be the essential technology for the next generation of mobile communications.
More and more international researchers are tackling SDR. In particular, to prove the feasibility of
SDR, several organizations have developed prototype
SDR units as the first step in SDR application studies[5]. We have reported an SDR unit that supports only
narrow bandwidth systems (up to a few hundred kilohertz) such as PDC (Personal Digital Cellular) andPHS (Personal Handy-phone System) [6]. We fabricated an advanced SDR transceiver that uses a newly
developed flexible-rate pre-/post-processor (FR-PPP)
that offers improved bandwidth (> 20 MHz), andimproved flexibility, to handle wireless local area network (WLAN) systems. This prototype SDR transceiver supports both PHS [7] and IEEE 802.11 [8]† NTT Network Innovation Laboratories
Yokosuka-shi, 239-0847 Japan
E-mail: shono.takashi@lab.ntt.co.jp

24

WLAN (the WLAN mode can be easily expanded toIEEE 802.11b). To confirm its feasibility, we
designed an IEEE 802.11 WLAN around this SDR.
This paper describes the software architecture of the
prototype with its distributed and heterogeneous
hybrid programmable architecture consisting of acentral processing unit (CPU), digital signal processors (DSPs), and PPPs and explains how it can beused to implement the IEEE 802.11 WLAN protocol.
The entire system configuration and details of the
hardware architecture were described in the previous
paper in this issue [2].
2. Software architecture of the prototype
In the WLAN mode, direct-sequence spread-spectrum (DSSS) is selected for the physical (PHY) layer.
Multi-rate transmission is enabled by two modulation
schemes: binary phase shift keying (BPSK) and
quadrature PSK (QPSK). The prototype offers a distributed coordination function (DCF) that supports
asynchronous frame transfer services based on carrier sense multiple access with collision avoidance(CSMA/CA). DCF is also offered by many current
commercial products. The access point (AP) is a portal with a bridge function to DIX Ethernet/IEEE
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Selected Papers

802.3. Moreover, passive scanning with a beacon
frame is used to allow a station (STA) to join the basic
service set. The functions not implemented at thistime include wired equivalent privacy, power management, and virtual carrier sense achieved byrequest to send/clear to send (RTS/CTS). Note thatthe inter-frame space (IFS) has a variable length, as
described later.
2.1 Functional allocation of communication tasks
System performance depends to a large extent on
how the critical functions such as modulation/demodulation (MODEM) processing and protocol sequence
processing are assigned to the different processors.
Since most DSPs have a special instruction set, parallel operation unit, and a memory bus optimized forthe digital signal processing, they can achieve higher
digital signal processing speeds than CPUs with thesame clock speed and the same power consumption.
Accordingly, the prototype has a multiprocessor

architecture like other SDRs [9]; protocol sequence
processing and equipment control are done by theCPU, and digital signal processing is done in the
DSPs. This approach was used in our previous SDR
unit [6]. The distributed processing for PHS mode inboth prototypes is shown in Fig. 1. Figure 2 shows thecorresponding software configuration of the prototype in WLAN mode. We used VxWorks because the
WLAN protocol has far stricter requirements in termsof interrupt response time than PHS. This real-time
operating system (OS) also allowed optimization of
the function allocation. Our previous SDR unit used
Solaris, so it was unable to achieve adequate interprocess communication. VxWorks offers significantly shorter interrupt times, so it allows finer allocationof tasks. Future work includes optimizing the SDR
design by examining other factors that influence thehardware and software configurations such as interrupt response time, context switching interval, bus
bandwidth, and the control of shared memories (sem-

PPP
Slot Interrupt

Coder/decoder(codec)External I/F

DSP
Modulation/
demodulation(MODEM)

Data I/O

Task management program

CPU
Call control program

Fig. 1. Distributed processing of PHS mode.
CPU
Application
task

SDR
controller
DSP

MAC protocol
handler

Ethernet/802.2
bridgeKernel

PLCP
task

MODEM
task
DSP monitor

VxWorks kernel
EthernetdriverDSP
driverFig. 2. Software configuration of WLAN mode.

Vol. 1 No. 4 July 2003

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aphore processing).
In implementing the various IEEE 802.11 functions
on the prototype, we assumed that the media access
control (MAC) layer functions would be executed on
the CPU while the PHY layer functions such as
MODEM would be processed by the DSPs. The PPP
is used to perform high-speed processes that cannot
be run on the CPU or DSP. For instance, the spreading process for DSSS incurs small loads, and so canbe implemented on a DSP. However, detecting thecorrelation peak in real time at the despreading stage
is beyond the ability of current DSPs, so it is done asa pre-process in the PPP.
2.2 Resolving the SIFS issue
When thinking about the PHY/MAC processes ofIEEE 802.11, its short IFS (SIFS) imposes the most
severe requirements in terms of response time. SIFS
in the DCF mode represents the time available forcompleting high priority operations such as theacknowledgement (ACK) response to MAC protocol
data unit (MPDU) reception and the CTS response to
RTS reception. The SIFS period is defined for each
PHY specification (10 µs in DSSS), and meeting thevalue specified imposes very severe demands on any
hybrid programmable architecture. In particular, thecontext switching interval of a real-time kernel is usuPPP

ally of the order of milliseconds and the CPU may fail
to complete a task if the interval is too short.
If the functional allocation for the CPU and DSP is
ideal, the delay elements of the SIFS process are asshown in Fig. 3, which gives an example of thesequence from the PHY layer convergence protocol(PLCP) protocol data unit (PPDU) reception to ACK
response. SIFS is the time from the reception of thelast PPDU symbol to the transmission of the firstsymbol of the response PPDU. The period fromPPDU reception in the radio frequency (RF) part to
ACK-PPDU transmission is defined as SIFS in thispaper.
The delay of the processes described in the timeline in Fig. 3 can be decreased to some extent byusing parallel processing. The prototype supports
parallel processing because it offers a high-speed
interrupt handler, direct memory access, and sharedmemory and input/output (I/O).
To complete the testing of the prototype in the
shortest period of time, we restricted ourselves tousing only commercial hardware. This imposed several restrictions on system performance. The key
problem was satisfying the SIFS specified in IEEE
802.11. We found that the VERSA Module European
Bus (VME) bus did not offer adequate performance:
40 µs was needed simply to transmit a 1500-byte Eth-

DSP

CPU

PPDU last symbol
Delay for interrupt response

process

Interrupt for fram
Response

e reception

SIFS processing time

Data frame transfer

End of transfer

Delay for data transfer
Delay for MAC processsfer

ion proc

ess

ACK frame transfer
End of transfer

Time

Delay inodulatDSP mDelay for ACK
generation

tran
Prepare for ACK

Response

PPDU first symbol

Delay for MPDU reception

Delay in
DSP demodulation

Fig. 3. Delay elements of the SIFS process.

26

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ernet frame between the DSP and CPU. Moreover,
the CPU interrupt response time was not shortenough. VxWorks running on the CPU yielded aninterrupt response time of 3 µs, an appreciable fraction of the SIFS period of IEEE 802.11 (10 µs).
Due to the above problems, ACK frames cannot betransmitted within the original SIFS period whichmeans that frame acknowledgement fails (ACK timeout). Accordingly, to allow the performance of the
prototype to be tested, we slightly modified the software to use a longer IFS. To be more precise, each
IFS value was multiplied by the same integer value.
The relationship between the IFS multiplier M andeach IFS value is as follows.
SIFS’ = M × SIFS
DIFS’= M × DIFS = M × (SIFS + 2 × aSlotTime)
EIFS’ = SIFS’ + DIFS’ + (8 × ACKSize)+ aPreambleLength + aPLCPHeaderLength
SIFS, DIFS: standard IFS value of IEEE 802.11
SIFS’, DIFS’, EIFS’: IFS value of this prototype
aSlotTime, ACKSize, aPreambleLength, aPLCPHeaderLength:
please see IEEE 802.11 [8]SDR with the hybrid programmable architecture canprovide WLAN support by selecting a suitable valueof M. Note that the slot time and ACK time-out alsochange as the IFS values change.
The relationship between the IFS multiplier and
WLAN mode throughput is shown in Fig. 4 (theMAC frame is unicast without fragmentation). The
throughput means the maximum data transmission
rate of MPDU assuming that the wireless channel has
no bit errors or congestion. When M is 10, throughput
is about 70% of the original performance.
2
BPSK
QPSK

M=1

Throughput [Mbit/s]

1.5

M=5
M = 101

M = 15
M = 20

M=1
M=5
M = 10 M = 15 M = 20

0.5

0

0

200

400

600 800 1000 1200 1400 1600
Frame length [byte]

Fig. 4. Relationship between IFS multiplier and throughput
for BPSK/QPSK for M = 1, 5, 10, 15, 20.

Vol. 1 No. 4 July 2003

3. Experimental evaluation of the SDR prototype
To evaluate the WLAN performance of this prototype, we examined both the PHY and MAC layers.
The PHY layer performance was described in the previous paper in this issue [2]. The MAC layer examination analyzed the throughput and DSP load.
After implementing the WLAN mode on the prototype, we found that M should be at least 10. The mainbarrier to supporting IEEE 802.11 on this prototype isthe context switching interval of the real-time OS.
The context switching interval of VxWorks can bereliably reduced to 200 µs (10 ms is the default
value), which supports the IFS-extended version of
the IEEE 802.11 standard. We also found that
VxWorks was sensitive to the system clock because
its internal timer is triggered from the system clock.
The 5-kHz system clock on the CPU board used creates significant jitter (399 µs). We determined that byextending SIFS to 100 µs, the default value of thisprototype, we can fully support CSMA/CA operation.
We measured throughput across a one-to-one cableconnection (one AP and one STA), and across a oneto-two cable connection (one AP and two STAs).
3.1 One-to-one throughput characteristics
First of all, we examined the one-to-one throughput
characteristics. The measurement environment isshown in Fig. 5(a). Packets were generated andreceived by connecting LAN analyzers via Ethernet
to SDR sets; DIX Ethernet frames were used. At the
SDR transmission set, the Ethernet frames received
from the Ethernet interface (I/F) were converted into
IEEE 802.11 frames without a frame check sequence(FCS), and then transmitted to the DSPs via the VME
bus. The PLCP frames were first generated by adding
FCS, the PLCP header, and PLCP preamble in the
DSP and then writing them into the first-in first-out(FIFO) buffer in the DSP board. The FIFO output was
passed to the PPP for subsequent hardware processing. The reverse process was done in the reception
set, and the Ethernet frames were analyzed on the
LAN analyzer.
The client PCs connected to the Ethernet I/F of the
SDR sets lie in the same subnet. The STA converts
the multicast frames into unicast frames and sends
them to the AP for multicast release. On the downlink, packets with local (AP) MAC addresses are terminated at the AP; packets with client (STA-side)
MAC addresses are sent to the air I/F. Packets withother MAC addresses are dropped at the AP. Packets
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SDR
AP

2.45 GHz

2.45 GHz
Attenuator

SDR
STA

Hub

Client PC
Hub

Client PC

LAN analyzer

LAN analyzer
(a)

SDR
AP

2.45 GHz

Splitter

Client PC
2.45 GHz

SDR
STA 1

Hub

Hub

Client PC

2.45 GHz
LAN analyzer

LAN analyzer

SDR
STA 2

Hub

Client PC

LAN analyzer(b)Fig. 5. System for measuring MAC layer performance. (a) one-to-one communication. (b) one-to-two communication.

received at the STA that have local (STA) MAC
addresses are terminated in the STA; packets withclient (STA-side) MAC addresses are sent to the Ethernet I/F, packets with other MAC addresses are
dropped at the STA. On the uplink, the STA terminates those packets that have local (STA) MAC
addresses; packets with other MAC addresses aresent to the air I/F. The AP terminates those packets
that have local (AP) MAC addresses; packets forother client (STA-side) MAC addresses are sent to the
air I/F. Packets for other MAC address are sent to the
Ethernet I/F.
Figure 6(a) shows the measured throughput whentransmitting multicast frames over uplinks and downlinks. Computer simulation results are also shown forreference. The contention window (CW) size used in
the computer simulation was set to 17. This value represents the average of the initial CW size because the
one-to-one connection prevented frame congestionand collision. For multicast transmission over the28

uplink, because channel contention occurs between
the frame re-transmitted by the AP and the next frameof STA, the average initial CW size is about 10.
Therefore, in the computer simulation of the uplink,
the CW size was set to 10 assuming that frame collision did not occur. Figure 6(b) shows the measured
throughput when transmitting unicast frames over
uplinks and downlinks, with BPSK and QPSK. Moreover, Fig. 6(c) shows the throughput for various IFS
multipliers. From Fig. 6(c) we can see that WLAN
operation was achieved regardless of the IFS multiplier value. Figure 6 indicates that the SDR prototype
offers throughput characteristics that closely matchthe results of computer simulation.
3.2 One-to-two throughput characteristics
Next, we assessed the one-to-two throughput characteristics. The measurement environment is shownin Fig. 5(b). To confirm CSMA/CA operation in
WLAN mode, we measured the throughput while
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0.8

1

0.7

Downlink

0.5
Uplink

0.4
0.3
0.2

Simulation
Experiment

0.1
0Throughput [Mbit/s]

1

Simulation (Case 2)

0

Experiment

82 byte

QPSK

BPSK
0.6
0.4
Simulation
Experiment (uplink)
Experiment (downlink)0200 400 600 800 1000 1200 1400 1600
Frame length [byte](b)

0.8
Simulation
Experiment

0.7

M = 100.6

M = 200.5
0.4

M = 500.3
0.2

M = 100

0.1
0

0

0.5

1
1.5
2
Offered load [Mbit/s]

2.5

3Fig. 7. Throughput characteristics vs. traffic load forunicast frames transfer with BPSK and M =10.

0.8

0.2

Throughput [Mbit/s]

Simulation (Case 1)
0.4

200 400 600 800 1000 1200 1400 1600
Frame length [byte]
(a)

0

0.6

0.2
0

1.2

0

Throughput [Mbit/s]

Throughput [Mbit/s]

1536 byte
0.8

0.6

200 400 600 800 1000 1200 1400 1600
Frame length [byte]

varying the offered load. Throughput was measured
for two frame lengths: 82 bytes and 1536 bytes. Figure 7 shows the measured throughput across the APwith equal traffic from each STA. The horizontal axis
shows the total traffic from STA 1 and STA 2, and thevertical axis shows the MAC frame throughput asreceived by AP. The computer simulations considered two cases. In Case 1, the local STA timer had nojitter and perfect slot synchronization was achieved
between STAs. In Case 2, frame collision occurred
when STA 1 and STA 2 selected adjacent slot numbers when performing backoff. Such a situation canoccur in a real system because STA slots are asynchronous due to the timer jitter of the OS (see Section2). One of the factors causing the discrepancy
between the measured and Case 1 plots is this jitter.
Moreover, when the traffic exceeds the maximum
rate of the wireless channel, packets are dropped due
to buffer overflow, which causes the throughput tosaturate. Short frames (82 bytes) yield low throughput due to the large overhead in the PLCP sublayer, as
can be understood from Fig. 6(b). Therefore, thethroughput vs. offered traffic characteristics of thisprototype agreed well with the computer simulation
results, and we could confirm normal CSMA/CA
operation.

(c)Fig. 6. Throughput characteristics. (a) multicast frametransfer over uplink and downlink for BPSK and
M =10. (b) unicast frame transfer over uplink anddownlink for BPSK/QPSK and M =10. (c) unicast
frame transfer for various IFS multipliers and
BPSK.

Vol. 1 No. 4 July 2003

3.3 DSP load characteristics
Finally, we investigated the characteristics of DSP
loads, which we measured by computing the numberof fetch cycles of each task. Transmission/reception
processes were executed in different DSPs. The DSP
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1

DSP load

0.8

0.6

Scramble
Modulation/spreading
CRC generation
Other

FIFO readAFC
Demodulation
Descramble
CRC check/memory
write
Other

theoretical results and computer simulation results.
We found that to fully support the IEEE 802.11 protocol, which has severe time-critical requirements, a
dedicated programmable hardware chip is required.
We are now developing a terminal-size SDR transceiver to meet all the requirements of certain existing
wireless standard specifications based on this prototype’s development results.

0.4

References
[1]

0.2

[2]
0
Rx

[3]

Fig. 8. DSP load characteristics.

[4]load on the transmitting side was measured when fourof the symbols constituting the MPDU underwent
DQPSK modulation. The DSP load on the receivingside was measured when demodulating one symbol.
Figure 8 shows the loads. Transmission loads wereheavier than receiving loads because the Tx DSP
could transmit MPDU while reading PLCP preamble
and PLCP header, whereas the Rx DSP read datafrom PPP symbol by symbol. The maximum DSP
load was 60%, which means that the DSPs can handle IEEE 802.11 signal processing.

[5]

Tx

4. Conclusion
We have fabricated a prototype SDR transceiverthat supports both PHS and IEEE 802.11 WLAN.
This paper reviewed our SDR software design
methodology with distributed and heterogeneous
hybrid programmable architecture that can achieve
IEEE 802.11 WLAN operation. The keys to achieving this were elucidated: allocation of signal processing functions to processors and reconfigurable hardware (CPU, DSPs, and PPP), and IFS extension for
full support of CSMA/CA operation, which is a fundamental MAC layer protocol of IEEE 802.11. The
latter resolves the problem caused by the slow bus
between the processors, interrupt response time ofeach processor, and context switching interval of thereal-time OS. No previous report has described an
SDR that supports several wireless communication
systems with quite different bandwidths and communication protocols. Our experiments performed toverify the operation of WLAN mode agreed well with
30

[6]

[7]
[8]
[9]

K. Uehara, K. Araki, and M. Umehira, “Trends in Research andDevelopment of Software Defined Radio,” NTT Technical Review,Vol. 1, No. 4, pp. 10-14, 2003.
H. Shiba, Y. Shirato, H. Yoshioka, and I. Toyoda, “Software DefinedRadio Prototype (I) – System Design and Performance Evaluation,”
NTT Technical Review, Vol. 1, No. 4, pp. 15-23, 2003.
J. Mitola, “The software radio architecture,” IEEE Commun. Mag.,
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T. Shono, K. Uehara, and S. Kubota, “Proposal for system diversity
on software defined radio,” IEICE Trans. Fund., Vol. E84-A, No. 9,
pp. 2346-2358, 2001.
W. Tuttlebee, “Software Defined Radio — Origins, Drivers andInternational Perspectives,” John Wiley & Sons, 2002.
Y. Suzuki, K. Uehara, M. Nakatsugawa, Y. Shirato, and S. Kubota,“Software radio base and personal station prototypes,” IEICE Trans.
Commun., Vol. E83-B, No. 6, pp. 1261-1268, 2000.
Personal Handy-phone System, RCR STD-28, 1995.
Wireless LAN Medium Access Control (MAC) and Physical Layer(PHY) specifications, ANSI/IEEE Std 802.11, 1999.
D. Efstathiou, L. Fridman, and Z. Zvonar, “Recent developments inenabling technologies for software defined radio,” IEEE Commun.
Mag., Vol. 37, No. 8, pp. 112-117, 1999.

Takashi Shono
NTT Network Innovation Laboratories.
He received the B.E. and M.E. degrees in electrical engineering from Keio University, Yokohama, in 1996 and 1998, respectively. In 1998,
he joined the NTT Wireless Systems Laboratories, Yokosuka, Japan. Since then, he has been
engaged in the research and development of software defined radio (SDR) systems, and synchronization and interference cancellation techniques
for orthogonal frequency division multiplexing(OFDM) and multi-carrier code division multiple
access (MC-CDMA). He is a member of theInstitute of Electronics, Information and Communication Engineers (IEICE) and IEEE. He
received the Young Investigators Award fromIEICE, and the 18th Telecom System Technology
Award from the Telecommunications Advancement Foundation in 2002 and 2003, respectively.

Munehiro Matsui
NTT Network Innovation Laboratories.
He received the B.E. and M.E. degrees in information engineering from Nagoya University,
Nagoya, in 1998 and 2000, respectively. In 2000,
he joined NTT Network Innovation Laboratories, Yokosuka, Japan. Since then, he has been
engaged in the research and development of SDR
systems and OFDM systems. He is a member of
the IEICE.

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