2013/09/11

Processor Memory Function Analysis Sample
Report
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Analysis flow chart
Analysis example result of XXXXX processor
Create block layout of each areas (Analog, IO, Logic, Memory)
Detailed analysis of Memory Section
Estimation of Memory
Layout of core area
Estimation of function
Calculate each block area
Estimate the No. of logic gates

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1. Function analysis flow chart
Identify each block based on layout
Distinctive layout of memory (memory cell array)

YESNO
Auto layout block？
YES

3

Memory area4 Detailed analysis of memory cell

5 Draw block layout of each memory
SRAM, Flaxh, EEPRO, ROM

Calculate memory size

8,9NO

Logic area

Analog area(C, R, Tr. layout)

Possible to estimate based on ARM core
analysis experience
YES
6
ARM core(Core, Memory)

Possible to estimate function bylayout vs. data sheet, Pin information

NO

YES

Distinctive layout？
ADC, BGR,YES VCO, Driver etc.)
Impossible to estimate
internal block function(*)

7

Block function

Calculate area, area size ratio and the No. of gates of each blocks

LTEC cooperationNONOImpossible to estimate

Detailed circuit analysis

Estimate function (almost 100%)(*)The block function might be fully understood only after
detailed circuit analysis is performed

Page： 2 of 92. Function Analysis Example of XXXXX Processor (not ARM core)

Bulldozer
Module2MB L2Cache

2MB L3 Cache
X-Bar

2MB L3 Cache
Bulldozer
Module2MB L2Cache

2MB L2
Cache

Bulldozer
Module2MB L3 Cache
Analog Area
2MB L3 Cache

2MB L2
Cache

Bulldozer
ModuleFirst Metal Layer

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Page： 3 of 9

3. Create block layout of each area (Analog, IO, Logic, Memory)
Draw the layout of Analog, IO, Logic, Memory by analyzing gate layer XXXXXX
Memory type is shown by detailed analysis
ARM CORE
Application processor

AnalogIO

Logic

6Tr.SP-SRAM(=Auto layout area)

10Tr.SP-SRAM
8Tr.DP-SRAM
ROM

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Page： 4 of 9

XXXXXXARM CORE Application processor

4. Detailed analysis of memory type

1bit size=0.60μｍ2

1bit size=0.30μｍ2

1.75μm

0.94μm

0.34μm
0.32μmAccess Tr.

1bit memory cell
Driver Tr.

1bit memory cell＋αLoad Tr.

Driver Tr.

Load Tr.

Access Tr.

6Tr.SP-SRAM

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10Tr.SP-SRAM

Page： 5 of 9

5. Estimation of memory size

XXXXXXARM CORE Application processor

Estimate memory size by using 1bit memory cell size and memory array size

6Tr.SP-SRAM(area1)

Estimation results

10Tr.SP-SRAM(area2)

area

8Tr.DP-SRAM(area3)

ROM(area4)

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area1
area2
area3
area4

size(μm2)42259121560716
59419
33578

1bit(μm2)
0.30
0.60
0.60
0.11
totalMemorysize(bit)17086373
188452749032
48707319507005
Page： 6 of 96. Layout of core area

XXXXXXARM CORE Application processor

Estimate core area by using data sheet or other information and layout configuration
It is difficult to distinguish form CPU, GPU and DSP without data sheet or other information.

Logic area
Core region※Note: The above example is just an illustration, not the result of an actual analysis

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Page： 7 of 9

XXXXXXARM CORE Application processor

7. Estimate circuit function

Analog area: To estimate internal block function based on data sheet (block diagram) and layout
Almost impossible to estimate internal block function in the logic area

12

• It is possible to estimate analog block functions having
distinctive layout such as BGR, ADC, Driver etc.
• It is possible to estimate analog block function that connect toexternal pin. (option)

21※Note: The above example is just an illustration, not the result of an actual analysis

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Page： 8 of 9

XXXXXXARM CORE Application processor

8. Calculate each block area

※Note: This example is just an illustration, not the result of an actual analysis

6Tr.SP-SRAM(area1)
10Tr.SP-SRAM(area2)
8Tr.DP-SRAM(area3)
ROM(area4)
Logic(area5)
Analog(area6)

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IO(area7)

area1
area2
area3
area4
area5
area6
area7
Die size

Area size(μm2)
5625912113471648732
5984
89285297
76846386458
64587

ratio(％)

6.2
1.3
0.05
0.06
70.5
9.2
10.4

Page： 9 of 9

9. Estimate the number of logic gates

XXXXXXARM CORE Application processor

Estimate No. of logic gate of total block by measuring standard cell area
STD cell area size=0.80μm2

0.63μm
1.27μmMeasure standard cell area size
Calculate the No. of logic gate
Density

LTEC cooperationarea(μm2)

No. of gates

100%48284297

72556621

80%46654237

58795296

60%

38971758

21713972

40%

19314118

36948309

20%

11689059

16571323

Page： 10 of 9