Montgomery’s Multiplication Technique:
How to Make it Smaller and Faster
Colin D. Walter
Computation Department, UMISTPO Box 88, Sackville Street, Manchester M60 1QD, UK
www.co.umist.ac.uk

Abstract. Montgomery’s modular multiplication algorithm has enabledconsiderable progress to be made in the speeding up of RSA cryptosystems. Perhaps the systolic array implementation stands out most in thehistory of its success. This article gives a brief history of its implementation in hardware, taking a broad view of the many aspects which need
to be considered in chip design. Among these are trade-offs between area
and time, higher radix methods, communications both within the circuitry and with the rest of the world, and, as the technology shrinks,
testing, fault tolerance, checker functions and error correction. We conclude that a linear, pipelined implementation of the algorithm may bepart of best policy in thwarting differential power attacks against RSA.

Key Words: Computer arithmetic, cryptography, RSA, Montgomery modular
multiplication, higher radix methods, systolic arrays, testing, error correction,
fault tolerance, checker function, differential power analysis, DPA.

1Introduction

An interesting fact is that the faster the hardware the more secure the RSA
cryptosystem becomes. The effort of cracking the RSA code via factorization of
the modulus M doubles for every 15 or so bits at key lengths of around 210 bits[10]. However, adding the 15 bits only increases the work involved in decryptionby ((1024+15)/1024)2 per multiplication and so by ((1024+15)/1024)3 per exponentiation, i.e. 5% extra! Thus speeding up the hardware by just 5% enables
the cryptosystem to become about twice as strong without needing any otherextra resources. Speed, therefore, seems to be everything. Indeed it is essential
not just for cryptographic strength but also to enable real time decryption of thelarge quantities of data typically required in, for example, the use of compressedvideo.
On the other side of the Atlantic, the first electronic computer is generally
recognised to be the Colossus, designed by Tommy Flowers, and built in 1943-4
at Bletchley Park, England. It was a dedicated processor to crack the Enigma
code rather than a general purpose machine like the ENIAC, constructed slightly
later by John Eckert and John Mauchly in Philadelphia. With the former view of

2Proc. CHES 99, LNCS vol. 1717, pp. 80-93, Springer, 1999

history, cryptography has a fair claim to have started the (electronic) computerage. Breaking Enigma depended on a number of factors, particularly humanweakness in adhering to strict protocols, but also on inherent implementation
weaknesses.
Timing analysis and differential power analysis techniques [12] show that
RSA cryptosystems mainly suffer not from lack of algorithmic strength but also
from implementation weaknesses. No doubt governments worked on such techniques for many years before they appeared in the public domain and have developed sufficiently powerful techniques to crack any system through side channel
leakage. Is it a coincidence that the US became less paranoid about the use oflarge keys when such techniques were first published? Now that there seems to be
no significant gain to be made from further improvement of algorithms, the top
priority must be to prevent such attacks by reducing or eliminating variations
in timing, power and radiation from the hardware.
This survey provides a description of the main ideas in the hardware implementation of the RSA encryption process with an emphasis on the importanceof Montgomery’s modular multiplication algorithm [17]. It indicates the main
publications where the significant contributions are to be found, but does not
attempt to be exhaustive. The paper discusses the major problems associatedwith space- and time- efficient implementation and reviews their solution. Amongthe issues of concern are carry propagation, digit distribution, buffering, communication and use of available area. Finally, there are a few remarks on thereliability and cryptographic strength of such implementations.

2

Notation

An RSA cryptosystem [20] consists of a modulus M , usually of around 1024 bits,
and two keys d and e with the property that Ade ≡ A mod M . Message blocks A
satisfying 0 ≤ A < M are encrypted to C = Ae mod M and decrypted uniquely
by A = C d mod M using the same algorithm for both processes. M = P Q isa product of two large primes and e is often chosen small with few non-zero
bits (e.g. a Fermat prime, such as 3 or 17) so that encryption is relatively fast.
d is picked to satisfy de ≡ 1 mod φ(M ) where φ is Euler’s totient function,
which counts the number of residue classes prime to its argument. Here φ(M ) =(P − 1)(Q − 1) so that d usually has length comparable to M . The owner of thecryptosystem publishes M and e but keeps secret the factorization of M andthe key d. Breaking the system is equivalent to discovering P and Q, which iscomputationally infeasible for the size of primes used.
The computation of Ae mod M is characterised by two main processes: modular multiplication and exponentiation. Here we really only consider computing(A×B) mod M . Exponentiation is covered in detail elsewhere, e.g. [9],[28]. To
avoid potentially expensive full length comparisons with M , it is convenient tobe able to work with numbers A and B which may be larger than the modulus.
Assume numbers are represented with base (or radix) r which is a power of 2,
say r = 2k , and let n be the maximum number of digits needed for any number

C. D. Walter, Montgomery’s Multiplication Technique3

encountered. Here r is determined by the multiplier used in the implementation:
an r×r multiplier will be used to multiply two digits together. The hardware
also determines n if we are considering dedicated co-processors with a maximum
register size of n digits. Generally, M must have fewer bits than the largest
representable number; how much smaller will be determined by the algorithm
used.
Except P
for the exponent e, each number X will have a representation of then−1form X = i=0 xi ri . Here the ith digit xi often satisfies 0 ≤ xi < r, yielding a
non-redundant representation, i.e. one for which each representation is unique.
The modulus M will always have such a representation. However, in order tolimit the scope of interactions between neighbouring digits, a wider range ofdigits is very useful. Typically this is given by an extra (carry) bit so that
digits lie in the range 0 .. 2r−1. For example, the output from a carry-save adder(with r = 2) provides two bits for each digit and so, in effect, is a redundant
representation where digits lie in the range 0 .. 3 rather than the usual 0 .. 1. Herethe k-bit architecture means that our adder will probably propagate carries up
the length of a single digit, providing a “save” part in the range 0 .. r−1 and a“carry” part representing a small multiple of r. A digit x split in this way is
written x = xs + rxc . In fact, the addition cycle in our algorithms involves digit
products, so that a double length result is obtained. Hence, with some notable
exceptions, the carry component regularly consists of another digit and a further
one or two more bits. In a calculation X ← X+Y , the digit slices can operatein parallel, with the jth digit slice computing
xj,s + rxj,c ← xj,s + xj−1,c + yj
The extra range of xj given through the carry component keeps xj from having
to generate a separate carry which would need propagating. Since only old values
appear on the right, not new ones, carry propagation does not force sequential
digit processing. The digit calculations can therefore be performed in parallel
when there is sufficient redundancy.

3

Digit Multipliers and their Complexity

Early modular multiplication designs treated radix 2, 4 or even 8 separately at agate level. With rapidly advancing technology, these have had to be replaced by
the generic radix r viewpoint which is now essential for a better understandingof the general principles as well as for a modular approach to design and forselecting from parametrised designs to make best use of available chip area. Today’s embedded cryptosystems are already using off-the-shelf 32-bit multipliers[21] where reduction of the critical path length by one gate makes virtually no
difference to the speed − and would probably cost too much in terms of additional silicon area. These r×r multipliers form the core of an RSA processor,
forming the digit-by-digit products.
In the absence of radical new algorithms we need to be aware of complexity results for multiplication but prepared to use pre-built state-of-the-art multipliers

4Proc. CHES 99, LNCS vol. 1717, pp. 80-93, Springer, 1999

which contain years of experience in optimisation and which come with a guarantee of correctness. Practical planar designs are known for multipliers which are
optimal with respect to some measure of time and area [3], [4], [15], [16], [19],[23]. A reasonable assumption which held until recently is that wires take area
but do not contribute noticeably to time. Under such a model, Area×T ime2
2
complexity for a k-bit multiplication is bounded below√ by k [3] and this boundcan be achieved for any time in the range logk to k [16]. Such designs tend touse the Discrete Fourier Transform and consequently involve large constants intheir measures of time and area. There are more useful designs which are asymptotically poorer but perform better if k is not too large. The cross-over point isgreater than the size of the digits here [15]. So classical multiplication methods
are preferable. Indeed, for a chip area of around 107 transistors devoted entirely
to RSA and containing hardware for a full length digit multiplication ai ×B, k= 32 or 64 is the maximum practical since there must be space for registers
and for other operations such as the modular reduction. In the latest technology
wires have significant capacitance and resistance and there is a requirement fromapplications as diverse as cell phones and deep space exploration for low power
circuitry. This requires a different model which is more sensitive to wire lengthand for which results are only just emerging [18].
Speed is most easily obtained by using at least n multipliers to perform afull length multiplication ai ×B (or equivalent) in one clock cycle. If we were notworried about modular reduction, the carry propagation problem could be takencare of by pipelining this row of multipliers (Fig. 1): ai bj is then computed by
the jth multiplier during the i+jth clock cycle, generating a carry which is fed
into the next multiplier, which computes ai bj+1 in the next cycle.
bj+1

 ai

bj

?

ai

?



j


?
rj+1

ai

?



j+1

carry

bj−1

j−1


carry

?
rj

 ai

carry

carry

?
rj−1

Figure 1. A Pipeline of Multipliers for R ← ai ×B.
Is this set-up fast enough for real-time processing? A realistic measure of
the speed required for real-time decryption is provided by an assumption thatthe internal bus speed is in the order of one k-bit digit per clock cycle. If thek-bit multiplier operates in one cycle with no internal pipelining then computing
A×B takes n cycles using n multipliers in parallel in order to compute ai ×B in
one cycle. The throughput is therefore one digit per cycle for a multiplication.

C. D. Walter, Montgomery’s Multiplication Technique5

Unfortunately, since RSA decryption requires O(nk) multiplications, we may
actually need a two dimensional array of multipliers rather than just a row ofthem to perform real-time decryption.
Of course, there is an immediate trade-off between time and area. Doubling
the number of digit multipliers in an RSA co-processor allows the parallel processing of twice as many digits and so halves the time taken. This does not contradict the Area×T ime2 measure being constant for non-pipelined multipliers,
although it appears to require less area than expected for the speed-up achieved.
Having two rows of digit multipliers with one row feeding into the other createsa pipeline (now with respect to digits of A) which doubles the throughput thatthe complexity rule expects. This indicates that choosing the largest r possible
for the given silicon area may not be the best policy; a pipelined multiplier orseveral rows of smaller multipliers may yield better throughput for a given area.
Finally, despite a wish to use well-established multipliers, differential power
analysis (DPA) attacks on cryptographic products [13] suggest that special purpose multipliers need to be designed for some RSA applications which containthe secret keys, such as smart cards. Briefly, switching a gate consumes more
power than not doing so. Inputs for which Hamming weights are markedly moreor less than average could therefore have a power consumption with measurable
deviation from average and reveal useful information to an attacker. This is trueof today’s optimised multipliers.

4

Modular Reduction & the Classical Algorithm

The reduction of A×B to (A×B) mod M can be carried out in several ways[11]. Normally it is done through interleaving the addition of ai B with modular
reductions instead of computing the complete product first. This makes somesavings in hardware. In particular, it enables the partial product to be kept
inside an n-digit register without overflow into a second such register. Each
modular reduction involves choosing a suitable digit q and subtracting qM fromthe current result. The successive choices of digit q can be pieced together toform the integer quotient Q = b(A×B)/M c or a closely related quantity:
Classical Modular Multiplication Algorithm:{ Pre-condition: 0 ≤ A < rn }R := 0 ;For i := n-1 downto 0 do
Begin
R := r×R + ai ×B ;qi := R div M ;R := R - qi ×M ;End
{ Post-condition: R = A×B − Q×M
and, consequently, R ≡ (A×B) mod M }6Proc. CHES 99, LNCS vol. 1717, pp. 80-93, Springer, 1999

Pn−1
If we define Ai = j=i aj rj−i so that Ai = rAi+1 +ai and use similar notationfor Qi then it is easy to prove by induction that at the end of the ith iteration
R = Ai ×B − Qi ×M . Hence the post-condition holds.
Brickell [5] observes that R div M need only be approximated using the top
bits of R and M in order to keep R bounded above. In particular [24], supposethat M is the approximation to M given by setting all but the k+3 most significant bits of M to zero, and that M 0 is obtained from M by incrementing its
k+3rd bit by 1. Then M ≤ M < M 0 ≤ (1+2−2 r−1 )M . Assume R is given similarly by setting the same less significant bits to zero and that the redundancy
in the representation of R is small enough for R < R+M to hold. The approximation to qi which is used is defined by the integer quotient qi = bR/M 0 c.
Thenqi = bR/M 0 c ≤ bR/M c = qi
≤ 1 + R/M ≤ 1 + (1+2−2 r−1 )R/M 0 ≤ 1 + (1+2−2 r−1 )(qi + 1)
so that qi −qi ≤ 1 + (1+2−2 r−1 )−1 + qi (1+4r)−1 from which, at the end of theloop, R < (1+qi −qi )M < 2M +(1+4r)−1 qi M . Assume the (possibly redundant)
digits ai are bounded above by a. We will establish inductively thatR < 3M + a(1+3r)−1 B
at each end of every iteration of the loop. Using the bound on the initial value of
R in the loop yields qi M ≤ rR+aB < 3rM +a(1+r(1+3r)−1 )B so that, from theabove, the value for R at the end of the loop satisfies R < 2M +(1+4r)−1 (3rM +a(1+r(1+3r)−1 )B) < 3M + a(1+3r)−1 B, as desired. Naturally, more bits for abetter approximation to qi will yield a lower bound on R, whilst fewer will yielda worse bound or even divergence.
The output from such a multiplication can be fed back in as an argument toa further such multiplication without any further adjustment by a multiple of
M providing the bound on R does not grow too much. Assuming, reasonably,that redundancy in A is bounded by a ≤ 2r we obtain R < 3M + 32 B from whichi) if B ≥ 9M then B is an upper bound for successive modular multiplications
and indeed the bound decreases towards a limit of 9M , and ii) if 9M is an upperbound for the input it is also an upper bound for the output. Hence only a small
number of extra subtractions at the end of the exponentiation yields M as a
final upper bound.
There are no communication or timing problems when there is just one multiplier. So, for the rest of this article, we will assume that the hardware for thealgorithm consists of an array of cells, each one for computing a digit of R, andso each containing two multipliers. The main difficulty is that qi needs to becomputed before any progress can be made on the partial product R. Scaling
M to make its leading two digits 10r makes the computation easier [25],[27], as
does shifting B downwards to remove the dependency on B. However, qi still has
to be broadcast simultaneously to every digit position (Fig. 2) and redundancy
has to be employed in R so that digit operations can be performed in parallel [5], [27]. These severe drawbacks make Montgomery’s algorithm for modular
multiplication appear more attractive.

C. D. Walter, Montgomery’s Multiplication Technique

7

ai
qi

mj+1bj+1

rj+1,s
rj+1,c


rj,c


mj bj

?? ? ?
 rj,sj+1

mj−1bj−1?? ? ?
?? ? ?
rj−3,srj−1,s


rj,c


@
@

j

 rj−1,cj−1@@

rj−2,c

rj−2,cFigure 2. Classical Algorithm with Shift Up, Carries and Digit Broadcasting5

Montgomery’s AlgorithmPeter Montgomery [17] has shown how to reverse the above algorithm so thatcarry propagation is away from the crucial bits, redundancy is avoided and simultaneous broadcasting of digits is no longer required. This noticeably reduces
silicon area and shortens the critical path. Although the complexities of thetwo algorithms seem to be identical in time and space, the constants for Montgomery’s version are better in practice. Montgomery uses the least significant
digit of an accumulating product R to determine a multiple of M to add rather
than subtract. He chooses multiplier digits in the opposite order, from least to
most significant and shifts down instead of up on each iteration:
Montgomery’s Modular Multiplication Algorithm:{ Pre-condition: 0 ≤ A < rn }R := 0 ;For i := 0 to n-1 do
Begin
R := R + ai ×B ;qi := (-r0 m0 -1 ) mod r ;R := (R + qi ×M) div r ;{ Invariant: 0 ≤ R < M +B }End
{ Post-condition: Rrn = A×B + Q×M
and, consequently, R ≡ (A×B×r−n ) mod M }Here m0 −1 is a residue mod r satisfying m0 ×m0 −1 ≡ 1 mod r. Since r is a powerof 2 and M is odd (because it is a product of two large primes) r and M are coprime, which is enough to guarantee the existence of m0 −1 . The digit qi is chosen
so that the expressionP
R+qi ×M is exactly divisible by r. Its lowest digit is clearlyi
0. If we define Ai = j=0 aj rj and Qi analogously then Ai = Ai−1 +ai ri and8Proc. CHES 99, LNCS vol. 1717, pp. 80-93, Springer, 1999

An = A. The value of R at the end of the iteration whose control variable hasvalue i is easily shown by induction to satisfy Rri+1 = Ai ×B + Qi ×M because
the division is exact. Hence the post-condition holds. The digits of A are requiredin ascending order. Thus, they can be converted on-line into a non-redundant
form and so we may assume ai ≤ r−1. This enables the loop invariant bounds
to be established by induction.
The extra power of r factor in the output R is easily cleared up by minor
pre- and post-processing [6]. The easiest way to explain this is to associate withevery number its Montgomery class mod M , namely
A ≡ Arn mod M
and to use × to denote the Montgomery modular multiplication. The Montgomery product of A and B is A × B ≡ A B r−n ≡ ABrn ≡ AB mod M . So
applying Montgomery multiplication to A in an exponentiation algorithm is going to produce Ae rather than (A)e . Introduction of the initial power of r to
obtain A is performed using the precomputed value
R2 = rn ≡ r2n mod M
and a Montgomery multiplication thus [7]: A×R2 ≡ Arn ≡ A mod M . Removalof the final extra power of r is also performed by a Montgomery multiplication:
Ae × 1 ≡ Ae mod M .
Throughout the exponentiation, an output from one multiplication is used
as an input to a subsequent multiplication. Without care the outputs will slowly
increase in size. However, suppose an−1 = 0. Then the bound R < M +B at
the end of the second last loop iteration is reduced to M +r−1 B on the final
round, which prevents unbounded growth when outputs are used as inputs. In
particular, if the second argument satisfies B < 2M then the output also satisfies
R < 2M . Thus, suppose 2rM < rn . It is reasonable to assume that A and R2
are less than 2M , even less than M , so that their topmost digits are both zero.
Then the scaling of A to A by Montgomery multiplication yields A < 2M andthis bound is maintained as far as the final output Ae . So only a single extra
subtraction of M may be necessary at the very end to obtain a least non-negative
residues.
However, when all the I/O is bounded by 2M , an interesting and usefulobservation about the output R of the final multiplication Ae × 1 ≡ Ae mod M
can be derived from the post-condition of the modular multiplication, namely
Rrn = Ae + QM . Q has a maximum value of rn −1. Hence, Ae < 2M would
lead to the output satisfying Rrn < (rn +1)M and so to R ≤ M , whilst a
sub-maximal value for Q immediately yields R < M in the same way. Hencea final subtraction is only necessary when R = M , i.e. when Ae ≡ 0 mod M ,that is, for A ≡ 0 mod M . It is entirely reasonable to assume that this neveroccurs in the use of the RSA cryptosystem as it would require starting with
A = M , whereas invariably the initial value should be less than M . Moreover,each modular multiplication in the exponentiation would also have to return M
rather than 0 to prevent all subsequent operands becoming 0. Hence the final
subtraction need never occur after the final re-scaling of an exponentiation.

C. D. Walter, Montgomery’s Multiplication Technique

9

Computation of qi is a potential bottleneck here. Simplification may beachieved in the same two ways that applied to the classical algorithm above:
this time scale M to make m0 = −1 and shift B up so that b0 = 0. These
would make qi = r0 , avoiding any computation at all. We consider the shift first,
supposing initially that B < 2M . If the shift B ← rB is added to the start ofthe multiplication code, then the loop invariant becomes R < M +rB. Hence
we require the top two digits of A to be zero in order for the bound on R to
be reduced first to M +B and then to M +r−1 B, so that R < 2M is output. If
we always have A < 2M then this is achieved if 2r2 M fits into the hardware
registers of n digits. The cost of this shift is hidden by the definition of n. The
shift can be hardwired and counted as free, as can a balancing adjustment of theoutput through a higher power of r in R2 . However, there is an extra iterationof the loop: before we had one more iteration than digits in M , now we have twomore. Fortunately, the cost of one more iteration per multiplication is low compared with the delay on every iteration which computing qi may cause. Apartfrom the extra storage cost of the scaled number, scaling M has a similar cost,
namely one more iteration per multiplication: M is replaced by (r−m0 −1 )M ,which increases its number of digits by 1 [26]. However, at the end of the exponentiation, the original M also needs to be loaded into the hardware and someextra subtractions of M may be necessary to reduce the output from a boundof 2rM .

6

Digit-Parallel and Digit-Serial Implementations

To overcome the problems of carry propagation in the classical algorithm, redundancy and extra hardware for digit broadcasting were required. Here, too,the same methods enable parallel digit processing. Indeed, if the shift direction
were reversed, the diagram of Fig. 2 would cover Montgomery’s algorithm also.
Pn−1 (i)For both algorithms, define the ith value of R, written R(i) = j=0 rj rj ,to be the value immediately before the shift is performed. This is calculated attime 2i in the parallel digit implementations, with qi computed and broadcast
at time 2i+1, say. The jth cell operates on the jth digits, transforming the i−1stvalue of R into the ith value. A common view of this process is:
(i)

(i−1)

(i−1)

rj ← rj±1,s + rj±1−1,c + ai bj ± qi mj
where the choice of signs is − for the classical algorithm and + for Montgomery’s.
(The input values of R on the right are partitioned into save and carry/borrowparts.)A restriction to only nearest neighbour communication is desirable becauseof the delays and wiring associated with global movement of data. For Montgomery’s algorithm, a systolic array makes this possible [26]. In this, the cells(i)
are transformed into a pipeline in which the jth cell computes rj at time 2i+j
(i−1)(Fig. 3). The input rj+1

is calculated on the preceding cycle by cell j+1 and(i)(i)
a carry cj−1 from rj−1 is computed in cell j−1, also in that cycle. This means

10Proc. CHES 99, LNCS vol. 1717, pp. 80-93, Springer, 1999

that carries can be propagated and so the cell function can become:
(i)

(i)

(i−1)

(i)

rj + rcj ← rj+1 + cj−1 + ai bj + qi mj(i)where the digits rj are now in the standard, non-redundant range 0 .. r−1. (Thedifferent notation for the carries recognises that they do not form part of thevalue of R(i) , unlike in the carry-save view.) If the digit qi is produced at time 2iin cell 0, it can be pipelined and received from cell j−1 at time 2i+j−1 ready forthe calculation. This pipeline can be extended to part or all of a 2-dimensional
array with n rows which computes iterations of the loop in successive rows.

?

?

ai









mj

bj

?

?

qi

j+1




?


qi


i−1
rj+1
-

-

?

ai


cij

j


rji

j−1
-

i
 cj−1Figure 3. Pipelined Montgomery Multiplication: I/O for cell j at time 2i+j.
The lowest cell, cell 0, computes only the quotient digit qi . Digits of index 0
are always discarded by the shift down and so do not need computing; the lowest(i−1)
digit of the final output is shifted down from index 1. We have qi = −(r1+−1
ai ×b0 )m0
mod r. This can indeed be calculated at time 2i because its only
(i−1)
timed input r1
is computed at time 2i−1. Observe that pre-computation−1of b0 ×m0
reduces the computation of qi to a single digit multiplication andan addition, giving lower complexity for cell 0 than for the other cells. Hence,computing qi no longer holds up the multiplication. Instead, the critical pathlies in the repeated, standard cell.
The communication infrastructure is less here than for the parallel digit operations illustrated in Fig. 2. Although the number of bits transmitted is almost
the same in both cases and is independent of n, the parallel digit set-up requires
an additional O(logn) depth network of multiplexers to distribute the digit qi .
Here the inputs and output are consumed, resp. generated, at a rate of one digit
every other cycle for A and R, and one digit every cycle in the case of B. Unlike
the parallel digit model, this is very convenient for external communication overthe bus, reducing the need for buffering or increased bandwidth.
When one multiplication has completed, another one can start without any
pause. However, the opposing directions of carry propagation and shift meanthat each cell is idle on alternate cycles. Thus, full use of the hardware requires
two modular multiplications to be processed in parallel. The normal square andC. D. Walter, Montgomery’s Multiplication Technique11

multiply algorithm for exponentiation can be programmed to compute squares
nose-to-tail starting loop iterations on the even cycles and interleave any necessary multiplications to start on the odd cycles. This enables an average 75%
take-up of the processing power, but has some overhead in storage and switching
between the two concurrent multiplications. Overall, with this added complexity, the classical, parallel digit, linear array might be faster for small n, but forlarger n and/or smaller r the broadcasting problem for qi means that a pipelined
implementation of Montgomery’s algorithm should be faster.
In [14] Peter Kornerup modified this arrangement, pairing or grouping digits
in order to reduce the waiting gap. In effect he alters the angle of the timing
front in the data dependency graph and, in the case he illustrates, he uses half
the number of cells with twice the computing power. This can be advantageous
in some circumstances.
An idea of the current speed of such array implementations is given in Blumand Paar [1] and amongst those actually constructed is one by Vuillemin et al.
[22]

7

Data Integrity

Correct functioning is important not only for critical applications but as a protection against, for example, attacks on RSA signature schemes through single fault
analysis [2]. Moreover, it is difficult and expensive to check all gate combinations
for faults at fabrication time because of the time need to load sufficiently manydifferent moduli [29] and, when smart cards are involved, a low unit price may
only be possible by using tests which occasionally allow sub-standard products
through to the market.
However, run-time checker functions are possible. These can operate in a similar way to those for multiplication in current chips. For example, results there
are checked mod 3 and mod 5 in one case [8]. Here the cost of a similar checkis minimal compared to that of the total hardware. The key observation is thatthe output from the modular multiplication algorithm satisfies an arithmetic
equation:
R = A×B − Q×M

or

Rrn = A×B + Q×M

These are easily checked mod m for some suitable m by accumulating partial
results for both sides on a digit-by-digit basis as the digits become available. A
particularly good choice for m is a prime just above the maximum cell output
value, but smaller m prime to r are also reasonable. The hardware complexity
for this is then equivalent to about one cell in the linear array and so the cost is
close to that of increasing n by 1.
If a discrepancy is found by the checker function, the computation can beaborted or re-computed by a different route. For example, to avoid the problem,
M might be replaced by dM for a digit d prime to r and combined as necessary
with some extra subtractions of the original M at the end.

12

8Proc. CHES 99, LNCS vol. 1717, pp. 80-93, Springer, 1999

Timing and Power Attacks

The literature contains descriptions of a number of attacks on the RSA cryptosystem which use timing or power information from hardware implementations
which contain secret keys [12], [13]. Experience of implementing both the classicaland Montgomery algorithms for modular multiplication suggests that most optimisation techniques which work with one also apply to the other. This suggeststhat attacks which succeed on well-designed implementations of the classical algorithm will have equivalents which apply to implementations of Montgomery’salgorithm.
However, an important difference arises when the pipelined linear array isused since, judging from the data dependency graph, there seems to be no equivalent for the classical algorithm. With parallel digit processing of the multiplication A×B mod M , the same digits of A and Q are used in every digit slice,
opening up the possibility of extracting information about both by averaging
the power consumption over all cells. However, during the related Montgomery
multiplication in a pipelined array, many digits of A and Q are being used simultaneously for forming digit products. This should make identification of theindividual digits much more difficult, and certainly increases the difficulty of any
analysis.

9

Conclusion

We have reviewed and compared the main bottlenecks which may arise in hardware for implementing the RSA cryptosystem using both the classical algorithm
for modular multiplication and Montgomery’s version, and shown how these aresolved. The hardware still suffers from broadcasting problems with the classicalalgorithm and scheduling complications with Montgomery’s. However, as far as
implementation attacks using power analysis are concerned, the pipelined arrayfor the latter seems to offer considerable advantages over any other implementations.

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