PLC from YOKOGAWA in Japan and Control system from Beckhoff in German are used in front control layer.
The two systems are also test in function test system, and have been integrated into EPICS system.

Jian Zhuang #1,2,3, Kejun Zhu1, 3, Yuanping Chu1, 3, Jiajie Li1, Lei Hu1 , Dapeng Jin1, 3Institute of High Energy Physics1
Graduate University of Chinese Academy of Sciences2
State Key Laboratory of Particle Detection and Electronics3

Introduction•The CSNS experimental control system isdivided into 3 layers, including front controllayer, local control layer and global controllayer. Global control layer and local control
layer are based on EPICS software.
•In CSNS Experimental Control System,YOKOGAWA PLC will be adopted ascontroller in device control layer.
•We want to integrate PLC and IOC into one
controller to improve system reliability andavailability and reduce cost.

Net performance test
All results are obtained with Netperf.

Figure 1: Simplify the path from front control
to global control. After Simplifying, reliability
increase while cost much fewer.

F3RP61 AND Test Environment

Figure 5: The net speed of F3RP61.

Figure 6: CPU Utilization of sending andreceiving

Figure 6 illustrate the CPU occupation with packet size. In this figure, the speed of net increases
with the packet size increasing, while the CPU occupation decreases. This effect is caused by thedifferent packing and unpacking cost in TCP/IP stack in different packet size. In control system,
the small size packet is dominated, so the net task will acquire more CPU time. And also fromfigure 6, as more interruption happens, receive task costs more CPU time than send task.

CA Access Time
Figure 2 F3RP61
Test Environment•DELL Optiplex 380MT/SLC 5.4•Yokogawa F3RP61-21•Cisco 3750 SwitchCPU Benchmark

Figure 7: Asynchronous read performancecomparison, MVME5100 vs. F3RP61

Nbench benchmark is used in performance test to known RP61 CPU well. MEM index is forprocessor bus, cache efficiency and memory performance. INT is integer computing capability ofprocessor. FP is double float performance of CPU. All these expose the theoretical upper limit ofthe CPU.

Figure 9: Synchronous read performancecomparison, MVME5100 vs. F3RP61

Figure 3: Ten reference program
performance Index of Nbench Program Set.

Figure 4: Performance Index
Comparison .F3RP61 vs MVME5100

Figure 8: Asynchronous Write
performance comparison, MVME5100 vs.
F3RP61EPICS IOC performance on F3RP61 canbe estimated through PV access speed test.
Figure 7, 8, 9 shows F3RP61 PV accessspeed comparing to MVME5100. In thistest, F3RP61 and Dell PC are connected inthe same CISCO 3750 switch. F3RP61 canprovide about one half PV access ofMVME5100 in case of full CPU
occupation.

Stability of Scan Period
Figure 10 depicts the output of IOC
period scan on F3RP61. The scan period
in this chart is 5ms, and the On-Offperiod is 10ms. After more than 190,000
samples, the Std. Dev. of scan period isabout 26us. The Max-min jitter is about
600us. For the general control task, thetypical period is about tens of ms. Thisdeviation can be neglected.

•The results of Nbench on RP61 are showed in figure 2. These results show that, comparing toAMD K6/233, computing intensive kind of program gain more accelerating.
•Figure 3 shows the performance comparison between RP61 and MVME5100, a widely usedsingle board computer in physics experiment and accelerator. Nbench test shows, for CPU
capability, CPU performance of F3RP61 is closed to the MVME5100. This means that comparing
to traditional ladder CPU, F3RP61 have advantages in compute-intensive applications . RP61 cando some more complex computing task, such as advanced PID algorithm.

Figure 10: Jitter of 10ms period scan

Reference[1] A. Uchiyama et al. “Development of Embedded EPICS on F3RP61-2L”, Proc ofPCaPAC2008, Ljubljana, Slovenia, Oct. 2008, pp.145-147[2] J. Odagiri et al., “Application of EPICS on F3RP61 to Accelerator Control”, Proc of
ICALEPCS2009, Kobe, Japan, Oct. 2009, pp.916-918,[3] http://www.tux.org/~mayer/linux/bmark.html[4] http://www.netperf.org/netperf/[5] RTOS-CPU module(F3RP61) Linux BSP Reference Manual, Yokogawa, Japan[6] RTOS-CPU Module (F3RP61) Hardware Instruction Manual, Yokogawa, Japan

13TH INTERNATIONAL CONFERENCE ON ACCELERATOR AND LARGE EXPERIMENTAL PHYSICS CONTROLSYSTEMS，10-14TH OCTOBER 2011, WTC GRENOBLE, FRANCE.

Summary
F3RP61 can be used as information exchange andcontrol node in the target and instruments control
system of CSNS.
Now, F3RP61 is used and long-term tested in Function
test system with the heavy water control simulation
involved in.

Figure 11: Function test system involving
F3RP61 as a controller