240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1

Advantech
AQD-D3L4GN16-SG1
Datasheet

Rev. 0.0
2017-07-07

1240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1
Description

Pin Identification

AQD-D3L4GN16-SG1 is a DDR3L 1600Mbps U-DIMM

SymbolFunctionhigh-speed, memory module that use 8pcs of 512Mx 64

A0~A14, BA0~BA2

Address/Bank input

bits DDR3L SDRAM in FBGA package and a 2K bits

DQ0~DQ63

Bi-direction data bus.

DQS0~DQS7

Data strobes/DQS0~/DQS7

Differential Data strobes

CK0, /CK0,CK1, /CK1

Clock Input. (Differential pair)Synchronous design allows precise cycle control with theCKE0, CKE1

Clock Enable Input.

use of system clock. Data I/O transactions are possible

ODT0, ODT1

On-die termination control line

on both edges of DQS. Range of operation frequencies,/S0, /S1

DIMM rank select lines.

programmable latencies allow the same device to be/RAS

Row address strobe/CASColumn address strobe/WEWrite Enable

DM0~DM7

Data masks/high data strobesCompliantVDD

Core power supply

 JEDEC standard 1.35V(1.28V~1.45V) Power supply

VDDQ

I/O driver power supply Backward compatible for 1.5V(1.425V~1.575V)

VREFDQ

DQ reference supply

serial EEPROM on a 240-pin printed circuit board.
AQD-D3L4GN16-SG1 is a Dual In-Line Memory Moduleand is intended for mounting into 240-pin edge connector
sockets.

useful for a variety of high bandwidth, high performance
memory system applications.

Features Lead-free and Halogen free products are RoHS VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)

Command/address reference

 MRS Cycle with address key programs

VREFCA- CAS Latency( 5,6,7,8,9,10,11)
VDDSPD- Burst Length (BL):8 and 4 with Burst Chop(BC) Bi-directional, differential data strobe (DQS and /DQS)

supplySPD EEPROM power supply
I2C serial bus address select for

SA0~SA2

 Differential clock input (CK, /CK) operation

EEPROM 8 bit pre-fetch

SCL

I2C serial bus clock for EEPROM

SDA

I2C serial bus data for EEPROM

 Internal calibration through ZQ pin

VSSGround On Die Termination with ODT pin/RESET

Set DRAMs Known StateVTTDRAM I/O termination supply

NCNo Connection

 Double-data-rate architecture; two data transfers perclock cycle

 Auto refresh and self refresh
Average Refresh Period 7.8us at lower than TCASE
85°C, 3.9us at 85°C < TCASE ≤ 95°C
 PCB Gold Plating: 30u” min2

240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1Dimensions (Unit: millimeter)

Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.

3

240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1
Pin Assignments
Pin
No

Pin
Name

Pin
NoPin
Name

Pin
NoPin
Name

Pin
NoPin
Name

Pin
NoPin
Name

Pin
NoPin
Name

1

VREFDQ

41

VSS

81

DQ32121

VSS

161

NC,DM8201

DQ37

2

VSS42

NC

82

DQ33122

DQ4162

NC

202

VSS

3

DQ043

NC

83

VSS

123

DQ5163

VSS

203

DM44

DQ144

VSS

84/DQS4124

VSS

164

NC,CB6204

NC

5VSS

45

NC,CB285

DQS4125

DM0165

NC,CB7205

VSS

6/DQS046

NC,CB386

VSS126

NC166

VSS206

DQ387DQS047

VSS87

DQ34127

VSS167

NC

207

DQ398

VSS48

NC

88

DQ35128

DQ6168/RESET

208

VSS9

DQ249NC

89

VSS

129

DQ7169

CKE1,NC

209

DQ4410

DQ350

CKE090

DQ40130

VSS

170

VDD

210

DQ45

11VSS

51

VDD

91

DQ41131

DQ12171

A15211

VSS

12

DQ852

BA292

VSS

132

DQ13172

A14212

DM513

DQ953

NC

93/DQS5133

VSS

173

VDD

213

NC

14VSS

54

VDD

94

DQS5134

DM1174

A12214

VSS15/DQS155

A1195

VSS135

NC175

A9215

DQ4616

DQS156

A796

DQ42136

VSS176

VDD

216

DQ47

17VSS57

VDD

97

DQ43137

DQ14177

A8217

VSS

18

DQ1058

A598

VSS

138

DQ15178

A6218

DQ5219

DQ1159A499

DQ48139

VSS179

VDD

219

DQ5320VSS

60

VDD

100

DQ49140

DQ20180

A3220

VSS

21

DQ1661

A2101

VSS

141

DQ21181

A1221

DM622

DQ1762VDD

102/DQS6142

VSS

182

VDD

222

NC

23

VSS

63

CK1,NC

103

DQS6143

DM2183

VDD

223

VSS

24/DQS264/CK1,NC

104

VSS144

NC

184

CK0224

DQ5425

DQS265

VDD

105

DQ50145

VSS185/CK0225

DQ5526

VSS66

VDD

106

DQ51146

DQ22186

VDD

226

VSS

27

DQ1867

VREFCA107

VSS147

DQ23187

NC,/EVENT

227

DQ60

28

DQ1968

NC108

DQ56148

VSS

188

A0228

DQ6129

VSS

69

VDD

109

DQ57

149

DQ28189

VDD

229

VSS

30

DQ2470

A10/AP

110

VSS

150

DQ29190

BA1230

DM731

DQ2571

BA0111/DQS7151

VSS

191

VDD

231

NC

32

VSS

72

VDD

112

DQS7152

DM3192/RAS

232

VSS

33/DQS373/WE

113

VSS153

NC

193/S0233

DQ6234

DQS374/CAS

114

DQ58154

VSS

194

VDD234DQ6335

VSS75

VDD

115

DQ59155

DQ30195

ODT0235

VSS36

DQ2676/S1,NC

116

VSS156

DQ31196

A13236VDDSPD37

DQ2777

ODT1,NC

117

SA0157

VSS

197

VDD

237

SA138

VSS78

VDD

118

SCL

158

NC,CB4198

NC

238

SDA

39

NC,CB079

NC

119

SA2

159

NC,CB5199

VSS

239

VSS

40

NC,CB180

VSS120
VTT160
VSS200
DQ36240/S1,ODT1,CKE1：Used for dual-rank UDIMMs; NC on single-rank UDIMMs.
CK1 and /CK1：Used for dual-rank UDIMMs; not used on single-rank UDIMMs but terminated.

VTT4

240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG14GB, 512Mx8 Module (1 Rank x8)

5

240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1
Operating Temperature Condition
Parameter

SymbolRating

Unit

Operating Temperature
TOPER
0 to 85
C
Note:Operating Temperature is the case surface temperature on the center/top side of the DRAM. For themeasurement conditions, please refer to JESD51-2 standard.

Note1Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD-0.4 ~ 1.975
V1
Voltage on VDDQ pin relative to Vss
VDDQ-0.4 ~ 1.975
V
1Voltage on any pin relative to Vss
VIN, VOUT-0.4 ~ 1.975
V
1Storage temperature
TSTG-55~+100
C
1,2
1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to theNote:device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For themeasurement conditions, please refer to JESD51-2 standard.

AC & DC Operating Conditions
Recommended DC operating conditions
RatingParameter

SymbolVoltage

Unit Notes
MinTyp.

Max

1.35V
1.283
1.35
1.45
V
1.5V
1.425
1.5
1.575
V
1.35V
1.283
1.35
1.45
V
Supply voltage for Output
VDDQ
1.5V
1.425
1.5
1.575
V
I/O Reference Voltage (DQ)
VREFDQ(DC)
1.35V0.49*VDDQ 0.50*VDDQ
0.51*VDDQV
I/O Reference Voltage (CMD/ADD) VREFCA(DC)
1.5V
0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
1.35V
VREF+0.160
V
AC Input Logic HighVIH(AC)
1.5V
VREF+0.175
V
1.35V
VREF-0.160
V
AC Input Logic Low
VIL(AC)
1.5V
VREF-0.175
V
1.35V
VREF+0.09
VDD
V
DC Input Logic HighVIH(DC)
1.5V
VREF+0.1
VDD
V
1.35V
VSS
VREF-0.09
V
DC Input Logic Low
VIL(DC)
1.5V
VSS
VREF-0.1
V
Note: 1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.
Supply voltage

VDD

61, 21, 233

240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1
IDD Specification parameters Definition - 4GB (1 Rank x8)
Parameter
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between validcommands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHINGSymbol

DDR3L 1600 CL11Unit

IDD0224mA

IDD1304

mA

IDD2P

64mA

IDD2Q

80

mA

IDD2N

88mA

IDD3P

80

mA

IDD3N

168

mA

IDD4R

544

mA

IDD4W

536

mA

IDD51520

mA

IDD696mA

IDD71008

mA

Operating One bank Active-read-Precharge current; IOUT = 0mA; BL =8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD),tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE isLOW; Other control and address bus inputs are STABLE; Data bus inputs areFLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data businputs are FLOATING

Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING

Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS =tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between validcommands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHINGOperating burst read current; All banks open, Continuous burst reads, IOUT= 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD),tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL =8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs areSWITCHING; Data bus inputs are SWITCHING IDD4R

Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control andaddress bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control andaddress bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT =0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc =tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH
between valid commands;Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;

Note:

1.Module IDD was calculated on the specific brand DRAM(4xnm) component IDD and can be differently
measured according to DQ loading capacitor.

7

240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1
Timing Parameters & Specifications
SpeedParameter

DDR3L 1600

UnitSymbol

MinMaxAverage Clock Period

tCK8-ns

CK high-level width

tCH

0.47

0.53

tCKCK low-level width

tCL

0.47

0.53

tCK

DQS, /DQS to DQ skew, per group,per access

tDQSQ-125psDQ output hold time from DQS, /DQS

tQH0.38-

tCK

DQ low-impedance time from CK, /CKtLZ(DQ)

-450

225

ps

tHZ(DQ)-225tDS

10-tDH

45tDIPW360-ps

DQS, /DQS Read preamble
DQS, /DQS differential Readpostamble

tRPRE

0.9-

tCKtRPST

0.3-

tCK

DQS, /DQS Write preamble

tWPRE

0.9-

tCK

DQS, /DQS Write postamble

tWPST

0.3-

tCK

DQS, /DQS low-impedance timetLZ(DQS)

-450

225

ps

DQS, /DQS high-impedance timetHZ(DQS)

-225

ps

tDQSL

0.45

0.55

tCK

tDQSH

0.45

0.55

tCKtDQSS

-0.27

0.27

tCKtDSS

0.18-

tCKtDSH

0.18-

tCKtWTRMax(4tck, 7.5ns)-Write recovery time

tWR15-ns

Mode register set command cycletimetMRD

4-tCK/CAS to /CAS command delay

tCCD

4-nCK

Auto precharge write recovery +precharge timetDAL

DQ high-impedance time from CK,/CK
Data setup time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
Data hold time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
DQ and DM input pulse width for eachinput

DQS, /DQS differential input low pulse
width
DQS, /DQS differential input highpulse width
DQS, /DQS rising edge to CK, /CKrising edge
DQS, /DQS falling edge setup time toCK, /CK rising edge
DQS, /DQS falling edge hold time toCK, /CK rising edge
Delay from start of Internal write
transaction to Internal read command

psps

tWR+tRP/tck

8psnCK

240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1
Active to active command period for
1KB page size
Speed
Parameter
Active to active command period for2KB page size
Four Activate Window for 1KB pagesizetRRDMax(4tck, 7.5ns)

DDR3L 1600UnitMinMax(4tck, 6ns)

MaxtFAW30-nsPower-up and RESET calibration time

tZQinitl

512

-tCK

Normal operation Full calibration timetZQoper

256-tCKtZQcs

64-

tCKtXSMax(5tCK, tRFC+10ns)-tXSDLLtDLL(min)-Normal operation short calibrationtime
Exit self refresh to commands not
requiring a locked DLL
Exit self refresh to commands
requiring a locked DLL
Internal read to precharge command
delay
Minimum CKE low width for Self
refresh entry to exit timing
Exit power down with DLL to any valid
command: Exit Precharge PowerDown with DLL
CKE minimum pulse width (high andlow pulse width)

Symbol

ns

tRRD

Max

tRTP

(4tck, 7.5ns)
tCKESRtCK(min)+1tCK
Max

tXP

(3tCK, 6ns)

-tCK

-

tCKE

Max
(3tCK, 5ns)

tAONPD

28.5

ns

tAOFPD28.5

ns

ODT turn-on

tAON

-225

225

ps

ODT turn-off

tAOF

0.3

0.7

tCK

Asynchronous RTT turn-on delay(Power-Down mode)
Asynchronous RTT turn-off delay(Power-Down mode)

9240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1
SERIAL PRESENCE DETECT SPECIFICATION (AQD-D3L4GN16-SG1 Serial Presence Detect)10

240Pin DDR3L 1.35V 1600 U-DIMM
4GB Based on 512Mx8
AQD-D3L4GN16-SG1
Note：
1. Byte 119 -- Manufacturing location by manufacturing location (00:Taiwan /01:China)
2. Byte 120 -- Module manufacturing date by year (YY).
3. Byte 121 -- Module manufacturing date by week (WW).
4. Bytes 122~125 -- Module Serial Number.
5. Bytes 128~145 -- Manufacturer Part Number by module part number , (Unused digits are coded as ASCII blanks (20h)).
6. Bytes 152~163 -- Manufacturer's Specific Data by working order number.
(Unused digits are coded as 00h.)
7. Bytes 164~175 -- Manufacturer's Specific Data by SPD naming number.
(Unused digits are coded as 00h.)
8. Bytes 176~255 --These bytes are undefined and can be used for ADATA's own purpose. (Unused digits are coded as 00h.)11