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Revision: 1.1.4
Release date: 6/6/2016eDatasheet

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S905

Amlogic, Inc.

S905 Datasheet

Revision 1.1.4

COPYRIGHT© 2015 Amlogic, Inc.
All rights reserved. No part of this document may be reproduced. Transmitted, transcribed, or translated into any language inany form or by any means with the written permission of Amlogic, Inc.
TRADEMARKSAMLOGIC is a trademark of Amlogic, Inc. All other trademarks and registered trademarks are property of their respective
companies.

This product is not intended for use in medical, life saving, or life sustaining applications.

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DISCLAIMER
Amlogic Inc. may make improvements and/or changes in this document or in the product described in this document at any
time.

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Circuit diagrams and other information relating to products of Amlogic Inc. are included as a means or illustrating typicalapplications. Consequently, complete information sufficient for production design is not necessarily given. Amlogic makes norepresentations or warranties with respect to the accuracy or completeness of the contents presented in this document.

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REVISION HISTORY
Revision Date

Changes

2015/7/18
2016/3/11

1.1.4

2016/6/1

Initial version release
Add Information about crypto, video path, audio path, mermory interface, DDR,
Nand, PLLs, JTAG, temperature sensor, Int 32K osc and PerfMon information
Add SHA-2 hash functions (SHA-224/SHA-256) supported in 3.3

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CONTACT INFORMATION
Amlogic, Inc.
2518 Mission College Blvd, Suite 120
Santa Clara, CA 95054
U.S.A.
www.amlogic.com

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Number
0.5
1.0

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Contents
Section I

About This Documentation ........................................................................................................................ 8

1. Documentation Overview.................................................................................................................................. 8
2. Acronyms and Abbreviations ............................................................................................................................. 8
Section II

General Information ............................................................................................................................. 10

3. Features ........................................................................................................................................................... 11
CPU Architecture ...................................................................................................................................... 11

3.2

GPU Architecture ...................................................................................................................................... 11

3.3

Crypto Engine ........................................................................................................................................... 11

3.4

Video Path ................................................................................................................................................ 11

3.5

Audio Path ................................................................................................................................................ 12

3.6

Memory .................................................................................................................................................... 12

3.7

I/O Interfaces............................................................................................................................................ 12

3.8

System Interface ....................................................................................................................................... 123.9Power Management ................................................................................................................................. 12

3.10

Security ................................................................................................................................................. 13

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3.1

4. System Block Diagram ..................................................................................................................................... 13

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5. Pin-Out Diagram (Top view) ......................................................................................................................... 14
6. Pin Description ................................................................................................................................................. 14e

7. Pin Multiplexing ............................................................................................................................................... 28ut

8. Signal Description ............................................................................................................................................ 30

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9. Absolute Maximum Ratings ............................................................................................................................. 36
Recommended Operating Conditions.......................................................................................................... 36

11.

Ripple Voltage Specifications ....................................................................................................................... 36

12.

Thermal Operating Specifications ................................................................................................................ 37

13.

DC Electrical Characteristics ......................................................................................................................... 38

13.1
13.2

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Normal GPIO Specifications (For DIO_xmA) ......................................................................................... 38
Open Drain GPIO Specifications (For DIO_OD) ..................................................................................... 38

13.3

DDR3/LPDDR2/LPDDR3 SDRAM Specifications .................................................................................... 38

13.4

Recommended Oscillator Electrical Characteristics ............................................................................. 40

14.

Recommended Power on sequence ............................................................................................................ 40

15.

Power Consumption..................................................................................................................................... 41

16.

Mechanical Dimension ................................................................................................................................. 41

Section III

System................................................................................................................................................... 44

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17.

Memory Map ............................................................................................................................................... 4418.

Power Domain.............................................................................................................................................. 46

18.1

Top Level Power Domains..................................................................................................................... 47

18.2

A53 Power Modes................................................................................................................................. 47

18.3

EE Top Level Power Modes ................................................................................................................... 48

18.4

Mali Power Modes ................................................................................................................................ 48

18.5

Power/Isolation/Memory Power Down Register Summary ................................................................. 49

19.

System Booting ............................................................................................................................................ 51
Overview ............................................................................................................................................... 51

19.2

Power-on Flow Chart ............................................................................................................................ 51

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CPU ............................................................................................................................................................... 52

20.1

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19.1

Overview ............................................................................................................................................... 52

21.

GPU .............................................................................................................................................................. 52

22.

Clock and Reset ............................................................................................................................................ 53
Overview ............................................................................................................................................... 53

22.2

Clock Trees ............................................................................................................................................ 53

22.3

Clock Gating .......................................................................................................................................... 56

22.4

Register Description .............................................................................................................................. 60

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22.1

GPIO ............................................................................................................................................................. 80
Overview ............................................................................................................................................... 80

23.2

GPIO Multiplex Function ....................................................................................................................... 80

23.3

GPIO Interrupt ...................................................................................................................................... 86

23.4

Register Description .............................................................................................................................. 87

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Interrupt Control .......................................................................................................................................... 88
Overview ............................................................................................................................................... 88

24.2

Interrupt Source.................................................................................................................................... 88

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Register Description .............................................................................................................................. 92

DIRECT MEMORY ACCESS CONTROLLER (DMAC) ........................................................................................ 93

25.1

Overview ............................................................................................................................................... 93

25.2

Descriptor Table.................................................................................................................................... 93

25.3

Register Description .............................................................................................................................. 94

26.

TIMER ........................................................................................................................................................... 99

26.1

Overview ............................................................................................................................................... 99

26.2

General-Purpose Timer ......................................................................................................................... 99

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26.3

Watchdog Timer ................................................................................................................................... 99

26.4

Register Definitions............................................................................................................................. 100

27.

Crypto ......................................................................................................................................................... 104

27.1

Overview ............................................................................................................................................. 104

27.2

Key Ladder .......................................................................................................................................... 104

27.3

RNG ..................................................................................................................................................... 104

27.4

EFUSE .................................................................................................................................................. 104

Section IV

Video Path........................................................................................................................................... 106lVideo Input ................................................................................................................................................. 106

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Overview ............................................................................................................................................. 107

28.2

Demux ................................................................................................................................................. 107

28.3

DVP...................................................................................................................................................... 107

28.4

Register Definition .............................................................................................................................. 107

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28.1

Video Output .............................................................................................................................................. 124
CVBS .................................................................................................................................................... 124

Section V

Audio Path .......................................................................................................................................... 182

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29.1

Audio_Input ............................................................................................................................................... 182
Overview ............................................................................................................................................. 182

30.2

SPIDF ................................................................................................................................................... 182

30.3

I2S(decode) ......................................................................................................................................... 183

30.4

PCM(decode) ...................................................................................................................................... 183

30.5

PDM .................................................................................................................................................... 183

30.6

To_ddr ................................................................................................................................................. 183

30.7

Register Description ............................................................................................................................ 185

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Audio Output.............................................................................................................................................. 198

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30.1

31.2
31.3

Overview ............................................................................................................................................. 198

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31.1

SPDIF(encode) ..................................................................................................................................... 198
I2S(encode) ......................................................................................................................................... 199

31.4

Register Description ............................................................................................................................ 201

Section VI

Memory INTERFACE ............................................................................................................................ 220

32.

DDR ............................................................................................................................................................ 220

32.1

Overview ............................................................................................................................................. 220

32.2

Register Description ............................................................................................................................ 221

33.

NAND .......................................................................................................................................................... 274

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33.1

Overview ............................................................................................................................................. 274

33.2

Register Definitions............................................................................................................................. 274

34.

eMMC/SD/SDIO ......................................................................................................................................... 278
Overview ............................................................................................................................................. 278

34.2

Pin Description .................................................................................................................................... 278

34.3

eMMC/SD Mode ................................................................................................................................. 278

34.4

Clock.................................................................................................................................................... 279

34.5

Descriptor ........................................................................................................................................... 279

34.6

Timing Specification ............................................................................................................................ 281

34.7

Register Definitions............................................................................................................................. 283

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SERIAL PERIPHERAL INTERFACE COMMUNICATION CONTROLLER............................................................ 287

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34.1

Overview ............................................................................................................................................. 287

35.2

Features .............................................................................................................................................. 287

35.3

Functional Description ........................................................................................................................ 288

35.4

Timing Specification ............................................................................................................................ 289

35.5

Register Description ............................................................................................................................ 290

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35.1

SERIAL PERIPHERAL INTERFACE FLASH CONTROLLER ................................................................................ 292
Overview ............................................................................................................................................. 292

36.2

Features .............................................................................................................................................. 292

36.3

Timing Specification ............................................................................................................................ 292

36.4

Register Description ............................................................................................................................ 293

Section VII

I/O Interface........................................................................................................................................ 301

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UNIVERSAL SERIAL BUS .............................................................................................................................. 301
Overview ............................................................................................................................................. 301

37.2

Features .............................................................................................................................................. 301

ETHERNET MAC .......................................................................................................................................... 301

38.1
38.2

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37.1

Overview ............................................................................................................................................. 301
Features .............................................................................................................................................. 302

38.3

Timing Specification ............................................................................................................................ 302

38.4

Register Description ............................................................................................................................ 304

39.

SDIO............................................................................................................................................................ 305

40.

INTER-INTEGRATED CIRCUIT (I2C) .............................................................................................................. 305

40.1

Overview ............................................................................................................................................. 305

40.2

Features .............................................................................................................................................. 305

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40.3

Timing Specification ............................................................................................................................ 305

40.4

Register Description ............................................................................................................................ 306

41.

UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER .................................................................... 309

41.1

Overview ............................................................................................................................................. 309

41.2

Features .............................................................................................................................................. 309

41.3

Functional Description ........................................................................................................................ 309

41.4

Register Description ............................................................................................................................ 310

42.

INFRARED REMOTE .................................................................................................................................... 312
Overview ............................................................................................................................................. 312

42.2

Decoder Functional Description ......................................................................................................... 312

42.3

NEC Infrared Transmission Protocol Example .................................................................................... 313

42.4

Register Description ............................................................................................................................ 314

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42.1

PULSE-WIDTH MODULATION ..................................................................................................................... 321
Overview ............................................................................................................................................. 321

43.2

Register Description ............................................................................................................................ 322

ISO7816 ...................................................................................................................................................... 324

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43.1

Overview ............................................................................................................................................. 324

44.2

Register Definition .............................................................................................................................. 324

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44.1

SAR ADC ..................................................................................................................................................... 328
Overview ............................................................................................................................................. 328

45.2

Register Description ............................................................................................................................ 328

Section VIII

System Interface ............................................................................................................................. 334

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Overview ............................................................................................................................................. 334

Temp Sensor............................................................................................................................................... 334

47.1
47.2
47.3

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JTAG............................................................................................................................................................ 334

Overview ............................................................................................................................................. 334

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45.1

Trimming ............................................................................................................................................. 335
Register Definition .............................................................................................................................. 336

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Section I About This Documentation
1.

Documentation Overview

This documentation is an overall Description of Amlogic advanced quad-core OTT/IP Set Top Box(STB) application processor
S905, providing programmers instructions from the following aspects: system, video path, audio path, memory interfaces, I/Ointerfaces and system interfaces.

Acronyms and Abbreviations
Table I.2.1 Acronyms and Abbreviations

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2.

AMBA High-speed Bus

A bus protocal designed for the connection andmanagement of functional blocks in system-on-achip (SoC) designs

APB

Advanced Peripheral Bus

A bus protocal designed for low bandwidth control
accesses

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AHB

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DMC
E

DDR memory controller

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HDMI

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Embedded multimedia card

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eMM
C

An engine connected to the DDR controller for the
purposes of moving data to/from DDR memory.

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Direct Memory Access Controller

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DMAC

An architecture consisting of an embedded
stortage solution with MMC interface, flash
memory and controler

A compact audio/video interface used fortransmitting uncompressed digital data

High-Definition Multimedian Interface

I2C

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An engine controls DDR

Inter-Integrated Circuit

An multi-master, multi-slave, single-ended, serial
computer bus used for attaching lower-speed
peripheral ICs to processors and microcontrollers.

I2S

Inter IC soundAn electrical serial bus interface stand used forconnnecting digital audio device together

PCM

Pulse Code Modulation

A method used to digitally represent sampled
analog signals

PDM

Pulse Density Modulation

A mothed used to represent an analog signal withdigital signal

P

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A synchronous serial data link standard operatingin sull duplex mode, devices communicate inmaster/slave mode where the master device
initiates the date frame

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Synchronous Peripheral Interface

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Section II General Information
S905 is an advanced application processor designed for OTT/IP Set Top Box(STB), smart projector and high-end media box
applications. It integrates a powerful CPU/GPU subsystem, and a secured UHD video CODEC engine with all major peripherals
to form the ultimate low power multimedia AP.
The main system CPU is a quad-core ARM Cortex-A53 CPU with 32KB L1 instruction and 32KB data cache for each core and alarge 512KB L2 unified cache to improve system performance. In addition, the Cortex-A53 CPU includes the NEON SIMD coprocessor to improve software media processing capability. The quad-core ARM Cortex-A53 CPU can be overdriven to 2.0GHz
and has a wide bus connecting to the memory sub-system.

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The graphic subsystem consists of two graphic engines and a flexible video/graphic output pipeline. The five core ARM Mali450 GPU including dual geometry processors (GP) and triple pixel processors (PP) handles all OpenGL ES 1.1/2.0 and OpenVG
graphics programs, while the 2.5D graphics processor handles additional scaling, alpha, rotation and color space conversion
operations. The video output pipeline can perform advanced video post-processing and enhancements. Together, the CPU andGPU handle all operating system, networking, user-interface and gaming related tasks.

HarAmlogic Video Engine (AVE) offloads the CPU by handling all video CODEC processing. It includes dedicated hardware video
decoder and encoder. AVE is capable of decoding 4K2K resolution video at 60fps with complete Trusted Video Path (TVP) for
secure applications and supports full formats including MVC, MPEG-1/2/4, VC-1/WMV, AVS, AVS+, RealVideo, MJPEG streams,
H.264, H265-10 and also JPEG pictures with no size limitation. The independent encoder is able to encode in JPEG and H.264
up to 1080p at 60fps.

toS905 integrates all standard audio/video input/output interfaces including a HDMI2.0 transmitter with 3D, CEC and HDCP 2.2
support, a CVBS output, I2S and SPDIF digital audio input/output interfaces, a PCM audio interface, two-channel PDM digital
MIC inputs and dual DVP camera interfaces.

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S905 also integrates a set of functional blocks for digital TV broadcasting streams. The built-in two demux can process the TV
streams from the serial and parallel transport stream input interface, which can connect to external tuner/demodulator. An
ISO7816 smart card interface and a crypto-processor are built in to help handling encrypted traffic and media streams.
The processor has rich advanced network and peripheral interfaces, including a Gigabit Ethernet MAC with RMII/RGMII
interface, dual USB 2.0 high-speed ports (one OTG and one HOST) and multiple SDIO/SD card controllers, UART, I2C, high-speed
SPI and PWMs.

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isStandard development environment utilizing GNU/GCC Android tool chain is supported. Please contact your AMLOGIC sales
representative for more information.

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3.

Features

3.1

CPU Architecture

3.4
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Crypto Engine

AES block cipher with 128/192/256 bits keys, standard 16 bytes block size and streaming ECB, CBC and CTR modes
DES/TDES block cipher with ECB and CBC modes supporting 64 bits key for DES and 192 bits key for 3DES
Hardware key-ladder operation and DVB-CSA for transport stream encryption
Built-in hardware True Random Number Generator (TRNG), CRC and SHA-1/SHA-2 (SHA-224/SHA-256) engine

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3.3

Penta-core ARM Mali-450 GPU up to 750MHz+ (DVFS)
Dual Geometry Processors with 32KB L2 cache
Triple Pixel Processors with 128KB L2 caches
Concurrent multi-core processing
2250Mpix/sec and 165Mtri/sec
Full scene over-sampled 4X anti-aliasing engine with no additional bandwidth usage
OpenGL ES 1.1/2.0 and OpenVG 1.1 support
Fast bitblt engine with dual inputs and single output
Programmable raster operations (ROP)
Programmable polyphase scaling filter
Supports multiple video formats 4:2:0, 4:2:2 and 4:4:4 and multiple pixel formats (8/16/24/32 bits graphics layer)
Fast color space conversion
Advanced anti-flickering filter

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GPU Architecture

Video Path

Amlogic Video Engine (AVE) with dedicated hardware decoders and encoders
Supports multiple “secured” video decoding sessions and simultaneous decoding and encodingVideo/Picture Decoding- H.265 HEVC MP-10@L5.1 up to 4Kx2K@60fps- H.264 AVC HP@L5.1 up to 4Kx2K@30fps- H.264 MVC up to 1080p @60fps- MPEG-4 ASP@L5 up to 1080P@60fps (ISO-14496)- WMV/VC-1 SP/MP/AP up to 1080P@60fps- AVS-P16(AVS+) /AVS-P2 JiZhun Profile up to 1080P@60fps- MPEG-2 MP/HL up to 1080P@60fps (ISO-13818)- MPEG-1 MP/HL up to 1080P@60fps (ISO-11172)- RealVideo 8/9/10 up to 1080P- WebM up to VGA- Multiple language and multiple format sub-title video support- MJPEG and JPEG unlimited pixel resolution decoding (ISO/IEC-10918)- Supports JPEG thumbnail, scaling, rotation and transition effects- Supports *.mkv,*.wmv,*.mpg, *.mpeg, *.dat, *.avi, *.mov, *.iso, *.mp4, *.rm and *.jpg file formats

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3.2

Quad core ARM Cortex-A53 CPU up to 2.0GHz (DVFS)
ARMv8-A architecture with Neon
8-stage in-order full dual issue pipeline
32KB instruction cache and 32KB data cache
512KB Unified L2 cache
Advanced TrustZone security system
Application based traffic optimization using internal QoS-based switching fabrics

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Video/Picture Encoding
Independent JPEG and H.264 encoder with configurable performance/bits-rate
JPEG image encoding
H.264 video encoding up to 1080P@60fps with low latency
Built-in HDMI 2.0 transmitter including both controller and PHY with CEC and HDCP 2,2, 4Kx2K@60 max resolution
outputCVBS 480i/576i standard definition output
Supports all standard SD/HD/FHD video output formats: 480i/p, 576i/p, 720p, 1080i/p and 4Kx2K

Audio Path

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Supports MP3, AAC, WMA, RM, FLAC, Ogg and programmable with 7.1/5.1 down-mixing
I2S audio interface supporting 8-channel (7.1) input and output
Built-in serial digital audio SPDIF/IEC958 output and PCM input/output
Dual-channel digital microphone PDM input
Supports concurrent dual audio stereo channel output with combination of I2S+PCM

16/32-bit SDRAM memory interface running up to DDR2133
Supports up to 2GB DDR3, DDR3L, LPDDR2, LPDDR3 with dual ranks
Supports SLC/MLC/TLC NAND Flash with 60-bit ECC, compatible to Toshiba toggle mode in addition to ONFI 2.2
SDSC/SDHC/SDXC card and SDIO interface with 1-bit and 4-bit data bus width supporting spec version 2.x/3.x/4.x
DS/HS modes up to UHS-I SDR104
eMMC and MMC card interface with 1/4/8-bit data bus width fully supporting spec version 5.0 HS400
Supports serial 1, 2 or 4-bit NOR Flash via SPI interface
Built-in 4k bits One-Time-Programming memory for key storage

I/O Interfaces

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Network
Integrated IEEE 802.3 10/100/1000 Gigabit Ethernet controller with RMII/RGMII interface
Supports Energy Efficiency Ethernet (EEE) mode
Optional 50MHz and 125MHz clock output to Ethernet PHY
WiFi/IEEE802.11 & Bluetooth supporting via SDIO/USB/UART/PCM
Network interface optimized for mixed WIFI and BT traffico Digital Television Interface- Transport stream (TS) input interface with built-in demux processor for connecting to external digital TV
tuner/demodulator- Built-in PWM, I2C and SPI interfaces to control tuner and demodulator- Integrated ISO 7816 smart card controller
o Integrated I/O Controllers and Interfaces- Dual USB 2.0 high-speed USB I/O, one USB Host and one USB OTG- Multiple UART, I2C and SPI interface with slave select- Multiple PWMs
- Programmable IR remote input/output controllers- Built-in 10bit SAR ADC with 2 input channels- A set of General Purpose IOs with built-in pull up and pull down

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System Interface
Integrated general purpose timers, counters, DMA controllers
24 MHz crystal input and internal 32KHz oscillator
Embedded debug interface using ICE/JTAGPower Management

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3.10

Multiple external power domains controlled by PMIC
Multiple internal power domains controlled by software
Multiple sleep modes for CPU, system, DRAM, etc.
Multiple internal PLLs for DVFS operation
Multi-voltage I/O design for 1.8V and 3.3V
Power management auxiliary processor in a dedicated always-on (AO) power domain that can communicate with an
external PMIC

Security
Trustzone based Trusted Execution Environment (TEE)
Secured boot, obfuscated OTP, internal control buses and storage
Protected memory regions and electric fence data partition
Hardware based Trusted Video Path (TVP) and secured contents (needs SecureOS software)

System Block Diagramdker

Fig II.4.1 shows the structure of S905.
Fig II.4.1 Block Diagram of S905

Memory Interface

S905

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ADVANCED CONNECTED MULTIMEDIA PROCESSORSPI NOR
Flash Controller

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DDR3/3L & LPDDR2/3 NAND/eMMC/iNAND/
Memory Controller
tSD Flash Controller

System Interface
PLLs

PMU

JTAG

32KHz
Osc

Temp
Sensor

PerfMonut

Cortex-A53
32KB I/D-Cache
NEON/VFPtr
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512K L2 Cache

Mali-450
GP

Mali-450
PP

Mali-450
PP

Mali-450
PP

MMU

160K L2
Cache

Video Output Unit

TrustZone Security
Audio Output Unit
Power
2.5D Graphic
Management
Processing
Processor

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Audio I/F

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PDM Stereo

I2S (7.1)

HDMI
CVBS

MMU

Audio Input Unit

SPDIF

ScalarCortex-A53
32KB I/D-Cache
NEON/VFP

DVP x2Mali-450
GP

Enhancement

Demux

Cortex-A53
32KB I/D-Cache
NEON/VFPe

TS Input x2

Cortex-A53
32KB I/D-Cache
NEON/VFP

De-interlacer

Video Input Unit

toCore and FabricVideo Engine(AVE)
CryptoEngineOTP

HDMI 2.0
Audio I/F

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SPDIF
I2S (7.1)
PCM

PCM

Input/Output Interfaces

USB OTG

USB Host

Giga
Ethernet
MAC

SDXC/
SDHC/
SD

SDIO

ISO7816

IR
Rx & Tx

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SAR ADC

I2C

UART

SPI

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Revision 1.1.4

Pin-Out Diagram (Top view)

Below is the pin-out diagram of S905.

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FigII.5.1 S905 Pin-out Diagram

6.

Pin Description

Table II.6.1 gives the pin Description of S905.

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Table II.6.1 Pin DescriptionBall#

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

GPIOX_0

DIO_4mA

UP

General purpose input/output bank X signal 0

VDDIO_X-F3

GPIOX_1

DIO_4mA

UP

General purpose input/output bank X signal 1

VDDIO_X-

D1

GPIOX_2

DIO_4mA

UP

General purpose input/output bank X signal 2

VDDIO_X-E2

GPIOX_3

DIO_4mA

UP

General purpose input/output bank X signal 3

E1

GPIOX_4

DIO_4mA

UP

General purpose input/output bank X signal 4

F2

GPIOX_5

DIO_4mAUP

F1GPIOX_6

DIO_3mA

G3

GPIOX_7

G2

l

F4

ne

GPIOX - Refer to Table II.7.1 for functional multiplex information.

-

VDDIO_X-

General purpose input/output bank X signal 5

VDDIO_X-

DOWN

General purpose input/output bank X signal 6

VDDIO_X-

DIO_3mA

UP

General purpose input/output bank X signal 7

VDDIO_X-

GPIOX_8

DIO_3mA

UP

General purpose input/output bank X signal 8

VDDIO_X-

G1

GPIOX_9

DIO_3mA

UP

General purpose input/output bank X signal 9

VDDIO_X-

H4

GPIOX_10

DIO_3mA

UP

General purpose input/output bank X signal 10

VDDIO_X-

H2

GPIOX_11

DIO_3mA

H1

GPIOX_12

DIO_3mA

J4GPIOX_13

J3

GPIOX_14

J2

General purpose input/output bank X signal 11

VDDIO_X-UP

General purpose input/output bank X signal 12

VDDIO_X-UP

General purpose input/output bank X signal 13

VDDIO_X-

DIO_3mA

UP

General purpose input/output bank X signal 14

VDDIO_X-

GPIOX_15

DIO_3mA

UP

General purpose input/output bank X signal 15

VDDIO_X-

J1

GPIOX_19

DIO_3mA

UP

General purpose input/output bank X signal 19

VDDIO_X-K3

GPIOX_20

DIO_3mA

DOWN

General purpose input/output bank X signal 20

VDDIO_X-

K1

GPIOX_21

DIO_3mAUp

General purpose input/output bank X signal 21

VDDIO_X-E4

VDDIO_XP-

Power supply for GPIO bank X

-

-

tr
ib

UP

D

ut

e

to

H

ar

dk
er

VDDIO_X

isDIO_3mA

15/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Ball#

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

GPIOY - Refer to Table II.7.2 for functional multiplex information.

GPIOY_0

DIO_3mA

UP

General purpose input/output bank Y signal 0

VDDIO_Y-A5

GPIOY_1

DIO_3mA

UP

General purpose input/output bank Y signal 1

VDDIO_Y-D4

GPIOY_2

DIO_3mA

UP

General purpose input/output bank Y signal 2

VDDIO_Y-C4GPIOY_3

DIO_3mA

UP

General purpose input/output bank Y signal 3

VDDIO_YB4

GPIOY_4

DIO_3mA

UP

General purpose input/output bank Y signal 4

A4

GPIOY_5

DIO_3mA

UP

General purpose input/output bank Y signal 5

VDDIO_Y-A3

GPIOY_6

DIO_3mA

UP

General purpose input/output bank Y signal 6

VDDIO_Y-B3

GPIOY_7

DIO_3mA

UP

General purpose input/output bank Y signal 7

VDDIO_Y-C3

GPIOY_8

DIO_3mA

UP

General purpose input/output bank Y signal 8

VDDIO_Y-A2

GPIOY_9

DIO_3mA

UP

General purpose input/output bank Y signal 9

VDDIO_Y-B2

GPIOY_10

DIO_3mAUP

VDDIO_Y-C2

GPIOY_11

DIO_3mA

UP

General purpose input/output bank Y signal 11

VDDIO_Y-A1

GPIOY_12

DIO_3mA

General purpose input/output bank Y signal 12

VDDIO_Y-

B1

GPIOY_13

C1

GPIOY_14

D2

GPIOY_15

D3

D5

ne

l

B5

to

H

ar

dk
er

VDDIO_YuteGeneral purpose input/output bank Y signal 10-

UP

General purpose input/output bank Y signal 13

VDDIO_Y-

DIO_3mA

DOWN

General purpose input/output bank Y signal 14

VDDIO_Y-

DIO_3mA

DOWN

General purpose input/output bank Y signal 15

VDDIO_Y-GPIOY_16

DIO_3mA

DOWN

General purpose input/output bank Y signal 16

VDDIO_Y-VDDIO_YP-

Power supply for GPIO bank Y

-

-

is

DIO_3mA

D

tr
ib

UP

-

GPIODV - Refer to Table II.7.3 for functional multiplex information.

P16

GPIODV_24

DIO_3mAZ

General purpose input/output bank DV signal 24

GPIO_DV-P17

GPIODV_25

DIO_3mAZ

General purpose input/output bank DV signal 25

GPIO_DV-

16/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

P19

GPIODV_26

DIO_4mAZ

General purpose input/output bank DV signal 26

GPIO_DV-P18

GPIODV_27

DIO_3mAZ

General purpose input/output bank DV signal 27

GPIO_DV-N18

GPIODV_28

DIO_3mAZ

General purpose input/output bank DV signal 28

GPIO_DV-N17

GPIODV_29

DIO_3mAZ

General purpose input/output bank DV signal 29

GPIO_DV-P15

VDDIO_DVP-Power supply for GPIO bank DV

-

-

ne

l

Ball#

dk
er

CARD - Refer to Table II.7.4 for functional multiplex information.

CARD_0

DIO_4mA

UP

General purpose input/output bank CARD signal 0

VDDIO_CARD-

K18

CARD_1

DIO_4mA

UP

General purpose input/output bank CARD signal 1

VDDIO_CARD-

L19

CARD_2

DIO_4mA

UP

General purpose input/output bank CARD signal 2

VDDIO_CARD-

L18

CARD_3

DIO_4mA

UP

General purpose input/output bank CARD signal 3

VDDIO_CARD-

M19

CARD_4

DIO_4mA

UP

General purpose input/output bank CARD signal 4

VDDIO_CARD-

M18

CARD_5

DIO_4mAUP

VDDIO_CARD-

N19

CARD_6

DIO_2mA

UP

General purpose input/output bank CARD signal 6

VDDIO_CARD-

M15

VDDIO_CARD

PPower supply for GPIO bank CARD

-

-

UP

General purpose input/output bank BOOT signal 0

VDDIO_BOOT

-

to

H

ar

K19

ut

e

General purpose input/output bank CARD signal 5

tr
ib

-

BOOT_0

DIO_4mA

B10

BOOT_1

DIO_4mA

UP

General purpose input/output bank BOOT signal 1

VDDIO_BOOT-

A10

BOOT_2

DIO_4mA

UP

General purpose input/output bank BOOT signal 2

VDDIO_BOOT-

C9

BOOT_3

DIO_4mA

UP

General purpose input/output bank BOOT signal 3

VDDIO_BOOT-

B9

BOOT_4

DIO_4mA

UP

General purpose input/output bank BOOT signal 4

VDDIO_BOOT-

A9

BOOT_5

DIO_4mA

UP

General purpose input/output bank BOOT signal 5

VDDIO_BOOT-

B8

BOOT_6

DIO_4mA

UP

General purpose input/output bank BOOT signal 6

VDDIO_BOOT

-

is

C10

D

BOOT - Refer to Table II.7.5 for functional multiplex information.

17/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

A8

BOOT_7

DIO_4mA

UP

General purpose input/output bank BOOT signal 7

VDDIO_BOOT-

D8

BOOT_8

DIO_4mA

UP

General purpose input/output bank BOOT signal 8

VDDIO_BOOT-

C7

BOOT_9

DIO_4mA

UP

General purpose input/output bank BOOT signal 9

VDDIO_BOOT-

B7

BOOT_10

DIO_4mA

UP

General purpose input/output bank BOOT signal
10

VDDIO_BOOT-

A7

BOOT_11

DIO_4mA

UP

General purpose input/output bank BOOT signal
11

VDDIO_BOOT

D6

BOOT_12

DIO_4mA

UP

General purpose input/output bank BOOT signal
12

C6

BOOT_13

DIO_4mA

UP

General purpose input/output bank BOOT signal
13

VDDIO_BOOT-

B6

BOOT_14

DIO_4mA

UP

General purpose input/output bank BOOT signal
14

VDDIO_BOOT-

A6

BOOT_15

DIO_4mA

UP

General purpose input/output bank BOOT signal
15

VDDIO_BOOT-

D7

VDDIO_BOOT

P-

Power supply for GPIO bank BOOT--

USB33_VDDIOH-

General purpose input/output bank H signal 1

USB33_VDDIOH-

General purpose input/output bank H signal 2

USB33_VDDIOH

-

Z

D16

GPIOH_1

DIO_ODZ

C17

GPIOH_2

DIO_OD

B17

GPIOH_3

E14

USB33_VDDIOH

ne
VDDIO_BOOT

dk
er

ar

H

General purpose input/output bank H signal 0e

DIO_ODut

GPIOH_0

to

GPIOH - Refer to Table II.7.6 for functional multiplex information.

D15

l

Ball#

tr
ib

Z

-

-

DOWN

General purpose input/output bank H signal 3

USB33_VDDIOH

-

P

-

Power supply for GPIO bank H and USB

-

-

is

DIO_2mA

N16

D

GPIOZ - Refer to Table II.7.7 for functional multiplex information.

GPIOZ_0

DIO_4mA

UP

General purpose input/output bank H signal 0

VDDIO_Z-

L16

GPIOZ_1

DIO_4mA

UP

General purpose input/output bank H signal 1

VDDIO_Z-

L17

GPIOZ_2

DIO_4mA

UP

General purpose input/output bank H signal 2

VDDIO_Z-

M16

GPIOZ_3

DIO_4mA

UP

General purpose input/output bank H signal 3

VDDIO_Z-

K16

GPIOZ_4

DIO_4mA

UP

General purpose input/output bank H signal 4

VDDIO_Z-

18/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

K17

GPIOZ_5

DIO_4mA

UP

General purpose input/output bank H signal 5

VDDIO_Z-

J16

GPIOZ_6

DIO_4mA

UP

General purpose input/output bank H signal 6

VDDIO_Z-

J17

GPIOZ_7

DIO_4mA

UP

General purpose input/output bank H signal 7

VDDIO_Z-

J19

GPIOZ_8

DIO_4mA

UP

General purpose input/output bank H signal 8

VDDIO_Z-

J18

GPIOZ_9

DIO_4mA

UP

General purpose input/output bank H signal 9

VDDIO_Z

H19

GPIOZ_10

DIO_4mA

UP

General purpose input/output bank H signal 10

H18

GPIOZ_11

DIO_4mA

UP

General purpose input/output bank H signal 11

VDDIO_Z-

H16

GPIOZ_12

DIO_4mA

UP

General purpose input/output bank H signal 12

VDDIO_Z-

G19

GPIOZ_13

DIO_4mA

UP

General purpose input/output bank H signal 13

VDDIO_Z-

G18

GPIOZ_14

DIO_4mA

DOWN

General purpose input/output bank H signal 14

VDDIO_Z-

F18

GPIOZ_15

DIO_4mA

UP

General purpose input/output bank H signal 15

VDDIO_Z-

L15

VDDIO_Z

P

-

-

-

General purpose input/output bank AO signal 0

VDDIO_AO

-

ne

l

Ball#

to

H

ar

dk
er

VDDIO_Z-ePower supply for GPIO bank Z-

R19

GPIOAO_1

R16

GPIOAO_2

T18

GPIOAO_3

T17

DIO_2mAUP

trib

GPIOAO_0

UP

General purpose input/output bank AO signal 1

VDDIO_AO-

DIO_2mA

UP

General purpose input/output bank AO signal 2

VDDIO_AO-

DIO_2mA

UP

General purpose input/output bank AO signal 3

VDDIO_AO-

GPIOAO_4

DIO_2mA

UP

General purpose input/output bank AO signal 4

VDDIO_AO-

U17

GPIOAO_5

DIO_2mA

UP

General purpose input/output bank AO signal 5

VDDIO_AO-

U18

GPIOAO_6

DIO_2mA

UP

General purpose input/output bank AO signal 6

VDDIO_AO-

T19

GPIOAO_7

DIO_2mA

UP

General purpose input/output bank AO signal 7

VDDIO_AO-

U19

GPIOAO_8

DIO_2mA

UP

General purpose input/output bank AO signal 8

VDDIO_AO-

is

DIO_2mA

D

R18

ut

GPIOAO - Refer to Table II.7.8 for functional multiplex information.

19/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

V19

GPIOAO_9

DIO_2mA

UP

General purpose input/output bank AO signal 9

VDDIO_AO-

V18

GPIOAO_10

DIO_2mA

UP

General purpose input/output bank AO signal 10

VDDIO_AO-

W19

GPIOAO_11

DIO_2mA

UP

General purpose input/output bank AO signal 11

VDDIO_AO-

T16

GPIOAO_12

DIO_ODZ

General purpose input/output bank AO signal 12

VDDIO_AO-

U16

GPIOAO_13

DIO_3mA

UP

General purpose input/output bank AO signal 13

VDDIO_AO

T15

TEST_N

DIO_2mAUp

General purpose input/output bank AO signal 14.
Should be pulled up during normal operation.

R15

RESET_NDI

DOWN

System reset input

P13

VDDIO_AO

P-Power supply for GPIO bank AO

ne

dk
er

VDDIO_AO--

VDDIO_AO---

GPIOCLK_0

DIO_3mA

UP

General purpose input/output bank CLK signal 0

VDD18_XTAL_CLK-D10GPIOCLK_1

DIO_3mA

UP

General purpose input/output bank CLK signal 1

VDD18_XTAL_CLK-

E11

VDD18_XTAL
_CLK

P

-

-

-

D11

SARADC_CH0

AI

ADC channel 0 input

AVDD18_USB_AD
C

-

D12

SARADC_CH1

A12

OSC_BUF_OU
T

D13

AVDD18_USB
_ADC

CVBS

A16

to

H

C11

D

ar

GPIOCLK - Refer to Table II.7.9 for functional multiplex information.

l

Ball#

e

Power supply for GPIO bank CLK and crystal

ut

SARADC

tr
ib

-

-

ADC channel 1 input

AVDD18_USB_AD
C

-

AO

-

Buffered 24MHz XTAL output

AVDD18_USB_AD
C

-

AP

-

Analog power supply for SARADC and USB--

CVBS_COMPA-

CVBS external compensation capacitor connection

AVDD18_CVBS_EF
USE

NC

C16

CVBS_RSETA-

CVBS output strength setting resistor

AVDD18_CVBS_EF
USE

NC

B16

CVBS_VREF

A-

CVBS reference voltage filter cap

AVDD18_CVBS_EF
USE

NC

B15

CVBS_IOUT

AO-

CVBS output

AVDD18_CVBS_EF
USE

NC

is

AI

20/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Ball#

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

D14

AVDD18_CVB
S_EFUSE

P-

Analog power supply for CVBS and eFuse-

To 1.8V

F12

CVBS_AVSSP-

Analog power ground for CVBS-

To VSS

C18

HDMITX_0P

AO-

HDMI TMDS data0 positive output

HDMITX_AVDD33

NC

D18

HDMITX_0N

AO-

HDMI TMDS data0 negative output

HDMITX_AVDD33

A19

HDMITX_1P

AO-

HDMI TMDS data1 positive output

B19

HDMITX_1N

AO-

HDMI TMDS data1 negative output

HDMITX_AVDD33

NC

A17

HDMITX_2P

AO-

HDMI TMDS data1 positive output

HDMITX_AVDD33

NC

A18

HDMITX_2N

AO-

HDMI TMDS data1 negative output

HDMITX_AVDD33

NC

D19

HDMITX_CKPAO-HDMI TMDS clock positive output

HDMITX_AVDD33

NC

E19

HDMITX_CKNAO-HDMI TMDS clock negative output

HDMITX_AVDD33

NC

D17

HDMI_REXTA-HDMI_AVDD18

NC

F19

HDMI_CEXTA-

HDMI TX external filter cap

HDMI_AVDD18

NC

G16,E15

HDMITX_AVD
D33

PAnalog power supply 3.3V for HDMI-

To 3.3V

E16,F1
6

HDMITX_AVD
D18

F14

HDMITX_VDD
0P9

B18,E1
8,F15,
G15

HDMITX_AVS
S

P4

to

H

ar

ne

dk
er

HDMITX_AVDD33

ute

HDMI output strength setting resistor

NC

NC

-

Analog power supply 1.8V for HDMI-

To 1.8V

P-Power supply 0.9V for HDMI-

To 0.9V

P-

Analog power ground for HDMI-

To VSS

A0DO-

DRAM address bus bit 0

VDDQ

-

P1

A1

DO

-

DRAM address bus bit 1

VDDQ

-

R1

A2

DO

-

DRAM address bus bit 2

VDDQ

-

V1

A3

DO

-

DRAM address bus bit 3

VDDQ

-

DRAM

D

P

is

tr
ib

-

l

HDMI

21/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

L4

A4

DO

-

DRAM address bus bit 4

VDDQ

-

U2

A5

DO

-

DRAM address bus bit 5

VDDQ

-

N2

A6

DO

-

DRAM address bus bit 6

VDDQ

-

T2

A7

DO

-

DRAM address bus bit 7

VDDQ

-

M2

A8

DO

-

DRAM address bus bit 8

VDDQ

R2

A9

DO

-

DRAM address bus bit 9

L2

A10

DO

-

DRAM address bus bit 10

N3

A11

DO

-

DRAM address bus bit 11

P2

A12

DO

-

DRAM address bus bit 12

T1

A13

DO

-

N4

A14

DO

-

M1

A15

DO

-

R4

BA_0

DO

-

L3

BA_1

DO

P3

BA_2

W1

CAS_N

W4

CLKP

V4

ne
dk
er

VDDQ

-

-

VDDQ

-

VDDQ

-

DRAM address bus bit 13

VDDQ

-

DRAM address bus bit 14

VDDQ

-

VDDQ

-

DRAM bank address bus bit 0

VDDQ

-

DRAM bank address bus bit 1

VDDQ

-

to

H

ar

VDDQ

e

DRAM address bus bit 15

ut

-

-

DRAM bank address bus bit 2

VDDQ

-

DO

-

DRAM column address strobe

VDDQ

-

DO

-

DRAM clock positive output

VDDQ

-

CLKN

DO

-

DRAM clock negative output

VDDQ

-

K2

CKE0

DO

-

DRAM clock enable output 0

VDDQ

-

L1

CKE1

DO

-

DRAM clock enable output 1

VDDQ

-

U3

CS0_N

DO

-

DRAM chip select output 0

VDDQ

-

T3

CS1_N

DO

-

DRAM chip select output 1

VDDQ

-

is

DO

D

tr
ib

-

l

Ball#

22/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

V2

ODT0

DO

-

DRAM on-die termination 0

VDDQ

-

W2

ODT1

DO

-

DRAM on-die termination 1

VDDQ

-

T4

RAS_N

DO

-

DRAM row address strobe

VDDQ

-

R5

WE_N

DO

-

DRAM write enable

VDDQ

-

U4

DDR_RST

DO-

DRAM reset

VDDQ

V5

DQ0

DIO

-

DRAM data bus bit 0

R9

DQ1

DIO

-

DRAM data bus bit 1

T6

DQ2

DIO

-

DRAM data bus bit 2

R8

DQ3

DIO

-

DRAM data bus bit 3

U5

DQ4

DIO

-

T9

DQ5

DIO

-

T5

DQ6

DIO

-

U8

DQ7

DIO

-

V11

DQ8

DIO

W7

DQ9

W11

DQ10

W5

DQ11

W10

ne
dk
er

VDDQ

-

-

VDDQ

-

VDDQ

-

DRAM data bus bit 4

VDDQ

-

DRAM data bus bit 5

VDDQ

-

VDDQ

-

DRAM data bus bit 7

VDDQ

-

DRAM data bus bit 8

VDDQ

-

to

H

ar

VDDQ

e

DRAM data bus bit 6

ut

-

-

DRAM data bus bit 9

VDDQ

-

DIO

-

DRAM data bus bit 10

VDDQ

-

DIO

-

DRAM data bus bit 11

VDDQ

-

DQ12

DIO

-

DRAM data bus bit 12

VDDQ

-

W6

DQ13

DIO

-

DRAM data bus bit 13

VDDQ

-

V10

DQ14

DIO

-

DRAM data bus bit 14

VDDQ

-

V7

DQ15

DIO

-

DRAM data bus bit 15

VDDQ

-

T11

DQ16

DIO

-

DRAM data bus bit 16

VDDQ

-

is

DIO

D

tr
ib

-

l

Ball#

23/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

T13

DQ17

DIO

-

DRAM data bus bit 17

VDDQ

-

R11

DQ18

DIO

-

DRAM data bus bit 18

VDDQ

-

R13

DQ19

DIO

-

DRAM data bus bit 19

VDDQ

-

U10

DQ20

DIO

-

DRAM data bus bit 20

VDDQ

-

T14

DQ21

DIO

-

DRAM data bus bit 21

VDDQ

T10

DQ22

DIO

-

DRAM data bus bit 22

U14

DQ23

DIO

-

DRAM data bus bit 23

W18

DQ24

DIO

-

DRAM data bus bit 24

W14

DQ25

DIO

-

DRAM data bus bit 25

W17

DQ26

DIO

-

V12

DQ27

DIO

-

V16

DQ28

DIO

-

W12

DQ29

DIO

-

V17

DQ30

DIO

V13

DQ31

T8

DQM0

V8

DQM1

U12

ne
dk
er

VDDQ

-

-

VDDQ

-

VDDQ

-

DRAM data bus bit 26

VDDQ

-

DRAM data bus bit 27

VDDQ

-

VDDQ

-

DRAM data bus bit 29

VDDQ

-

DRAM data bus bit 30

VDDQ

-

to

H

ar

VDDQ

e

DRAM data bus bit 28

ut

-

-

DRAM data bus bit 31

VDDQ

-

DO

-

DRAM data mask 0

VDDQ

-

DO

-

DRAM data mask 1

VDDQ

-

DQM2

DO

-

DRAM data mask 2

VDDQ

-

V14

DQM3

DO

-

DRAM data mask 3

VDDQ

-

U7

DQS0_PDIO-

DRAM data strobe 0

VDDQ

-

T7

DQS0_N

DIO-

DRAM data strobe 0 complementary

VDDQ

-

W8

DQS1_PDIO-

DRAM data strobe 1

VDDQ

-

is

DIO

D

tr
ib

-

l

Ball#

24/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

V9

DQS1_N

DIO-

DRAM data strobe 1 complementary

VDDQ

-

R12

DQS2_PDIO-

DRAM data strobe 2

VDDQ

-

T12

DQS2_N

DIO-

DRAM data strobe 2 complementary

VDDQ

-

W15

DQS3_PDIO-

DRAM data strobe 3

VDDQ

-

V15

DQS3_N

DIO-

DRAM data strobe 3 complementary

VDDQ

W3

PVREF

A

-

DRAM reference voltage

V3

PZQ

A

-

DRAM reference pin for ZQ calibration

VDDQ

-

C13

USBA_DPAIO-USB OTG positive data signal

USB33_VDDIOH

NC

C14

USBA_DMAIO-

USB OTG negative data signal

USB33_VDDIOH

NC

B13

USBA_VBUS

AI-

USB OTG cable power detection (5V tolerance)

AVDD18_USB_AD
C

NC

A13

USBA_ID

DI-

AVDD18_USB_AD
C

NC

A14

USBB_DPAIO-

USB host positive data signal

USB33_VDDIOH

NC

B14

USBB_DMAIO

USB host negative data signal

USB33_VDDIOH

NC

A15

USB_TXRTUN
E-

USB output strength setting resistor

AVDD18_USB_AD
C

NC1

tr
ib

ne
dk
er

H

to

ut

e

USB OTG mini-receptacle identifier (Internal 10KΩpull-up resistor to AVDD18)

-

-

A11

sys_osc_in

AI-

24MHz crystal oscillator input

VDD18_XTAL_CLK

-

B11

D

is

System Clock & PLL

AIO

VDDQ

ar

USB

-

l

Ball#

sys_osc_out

AO-

24MHz crystal oscillator output

VDD18_XTAL_CLK-

B12

EXTC_DPLLA-

DPLL external filter cap

AVDD18_DPLL-

E12

AVDD18_DPL
L

P-

Analog power supply 1.8V for DPLL

-

-

F11

AVSS_DPLLP-

Analog power ground for DPLL

-

-

G17

HPLL_AVDD1
8

P-

Analog 1.8V power supply for HPLL--

25/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Ball#

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

H15

HPLL_AVSSP-

Analog power ground for HPLL

-

-

F17

HPLL_CEXTA-

HPLL external filter cap

HPLL_AVDD18-

P8

PLL_VDDP-

Power supply for PLL--

VDDCPUP-Power supply for CPU (Cortex A5)

VDDQ

P

-

Power supply for DDR

VDDEE_0V9

P-Power Supply for GPU and core logic

P12

VDDAO_0V9

P

-

D9

IOVREF_1V8

P

-

ne

dk
er

-

-

-

-

-

Power supply 0.9V for AO domain--

1.8V Power supply for IOVREF

-

-

-

-

to

H

ar

-

ut

e

J5,J7,E
5,E6,E
7,E8,E
9,F5,G
4,G8,H5
M4,N5,P9,P1
0,R6,R
7,R10,R14
H13,J1
5,K4,K
15,E10,E13,L6,L12,M
8,N15,
P7,P11,P14lDigital Power

is
D

H9,H1
0,H11,
H12,H
14,J6,J
8,J9,J1
0,J11,J
13,J14,
K5,K6,
K7,K9,
K10,K1
1,K12,
K13,K1
4,U1,U
9,L5,L7,L8,L9,
L10,L1
1,L13,L
14,M5,
M6,M9
,M11,
M12,M
14,N1,
N6,N7,
N8,N9,
N10,N
11,N12tr
ib

Digital Ground

DVSS

P

-

Digital power ground26/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Ball#

Revision 1.1.4

Net Name

Type

Default Pull
UP/DN

Description

Power Domain

If Unused

Note 1: USB_TXRTUNE can only be NC when both USBA/USBB are not used.

D

is

tr
ib

ut

e

to

H

ar

dk
er

Abbreviations: DI = Digital input pin
 DO = Digital output pin
 DIO = Digital input/output pin
 DIO_OD = 5V input tolerant open drain (OD) output pin, need external pull up
 A = Analog setting or filtering pin
 AI = Analog input pin
 AO = Analog output pin
 AIO = Analog input/output pin P = Power pin AP = Analog power pin NC = No connection
 UP = Pull-Up
 DOWN = Pull-down
 Z = Tri-Statenel,N13,U
15,V6,
F6,F7,F
8,F9,F1
0,F13,
G6,G9,
G11,G
12,G14,H6,H7,H8,N1
4,P6,W
13,W1
6

27/336AMLOGIC, Inc. Proprietary

S905 Datasheet

7.

Revision 1.1.4

Pin Multiplexing

Multiple usage pins are used to conserve pin consumption for different features. The S905 devices can be used in manydifferent applications but each application will not utilize all the on chip features. As a result, some of the features share thesame pin. Most of the multiple usage pins can be used as a GPIO pin as well.
Table II.7.1 GPIOX_x Multi-Function Pin
Pin Name Func1

Func2

Func3

Func4

SDIO_IRQ
ISO7816_CLKISO7816_DATA

ne

PWM_A
PWM_F

PCM_OUT_A
PCM_IN_A
PCM_FS_A
PCM_CLK_Adker

TSIN_D_VALID_B
TSIN_SOP_B
TSIN_CLK_B
TSIN_D0_Bl

SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_CLKSDIO_CMDSLIP_UART_TX
SLIP_UART_RX
SLIP_UART_CTS
SLIP_UART_RTS
PWM_E

ar

UART_TX_A
UART_RX_A
UART_CTS_A
UART_RTS_A
UART_RTS_B

H

GPIOX_0
GPIOX_1
GPIOX_2
GPIOX_3
GPIOX_4
GPIOX_5
GPIOX_6
GPIOX_7
GPIOX_8
GPIOX_9
GPIOX_10
GPIOX_11
GPIOX_12
GPIOX_13
GPIOX_14
GPIOX_15
GPIOX_19
GPIOX_20
GPIOX_21

Func2

GPIOY_0
GPIOY_1
GPIOY_2
GPIOY_3
GPIOY_4
GPIOY_5
GPIOY_6
GPIOY_7
GPIOY_8
GPIOY_9
GPIOY_10
GPIOY_11
GPIOY_12
GPIOY_13
GPIOY_14
GPIOY_15
GPIOY_16

DVP_HS_A
DVP_VS_A
DVP_CLK_A
DVP_D2_A
DVP_D3_A
DVP_D4_A
DVP_D5_A
DVP_D6_A
DVP_D7_A
DVP_D8_A
DVP_D9_A

Func3

Func4

I2SIN_CH67

ut

is

D

Func5
I2S_AO_CLK_IN
I2S_LR_CLK_IN

ISO7816_CLKISO7816_DATA
I2SIN_CH45
I2SIN_CH23
I2SOUT_CH23
I2SOUT_CH45
I2SOUT_CH67

tribTSin_D_VALID_A
TSin_SOP_A
TSin_CLK_A
TSin_D0_A
TSin_D1_A
TSin_D2_A
TSin_D3_A
TSin_D4_A
TSin_D5_A
Tsin_D6_A
TSin_D7_A
TSin_FAIL_Ae

Pin Name Func1

to

Table II.7.2 GPIOY_x Multi-Function Pin

SPDIF_IN
SPDIF_OUT
DMIC_IN
DMIC_CLK_OUT
DVP_D0_A
DVP_D1_A

28/336

UART_CTS_C
UART_RTS_C
UART_TX_C
UART_RX_C
CLKOUT

PWM_F
PWM_A

AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Table II.7.3 GPIODV_x Multi-Function Pin
Pin Name

Func1

Func2

Func3

GPIODV_24
GPIODV_25
GPIODV_26
GPIODV_27
GPIODV_28
GPIODV_29

UART_TX_B
UART_RX_B
UART_CTS_B
UART_RTS_B

I2C_SDA_A
I2C_SCK_A
I2C_SDA_B
I2C_SCK_B
I2C_SDA_C
I2C_SCK_C

PWM_D
PWM_B

JTAG_TDIJTAG_TDO
JTAG_CLK
JTAG_TMSUART_TX_AO_A
UART_RX_AO_A

ne

Func2

SDCARD_D1
SDCARD_D0
SDCARD_CLK
SDCARD_CMD
SDCARD_D3
SDCARD_D2

dk
er

Func1

CARD_0
CARD_1
CARD_2
CARD_3
CARD_4
CARD_5
CARD_6l

Table II.7.4 CARD_x Multi-Function Pin
Pin Name

Table II.7.5 BOOT_x Multi-Function Pin

ut

tr
ib
is
D

Func2

Func3

ar

EMMC_NAND_D0
EMMC_NAND_D1
EMMC_NAND_D2
EMMC_NAND_D3
EMMC_NAND_D4
EMMC_NAND_D5
EMMC_NAND_D6
EMMC_NAND_D7
NAND_CE0
NAND_CE1
NAND_RB0
NAND_ALE
NAND_CLE
NAND_WEN_CLK
NAND_REN_WR
NAND_DQS

H

BOOT_0
BOOT_1
BOOT_2
BOOT_3
BOOT_4
BOOT_5
BOOT_6
BOOT_7
BOOT_8
BOOT_9
BOOT_10
BOOT_11
BOOT_12
BOOT_13
BOOT_14
BOOT_15

to

Func1

e

Pin Name

EMMC_CLKEMMC_CMD

NOR_D
NOR_Q
NOR_C
NOR_CS

EMMC_DS

Table II.7.6 GPIOH_x Multi-Function Pin
Pin Name

Func1

GPIOH_0
GPIOH_1
GPIOH_2
GPIOH_3

HDMI_HPD (5V)
HDMI_SDA (5V)
HDMI_SCL (5V)

Table II.7.7 GPIOZ_x Multi-Function Pin

29/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Pin Name

Func1

Func2

GPIOZ_0
GPIOZ_1
GPIOZ_2

ETH_MDIO
ETH_MDCETH_CLK_RMII_50M_IN/
ETH_RGMII_RX_CLK
ETH_RX_DV
ETH_RXD0ETH_RXD1
ETH_RXD2
ETH_RXD3
ETH_RGMII_TX_CLK
ETH_TX_EN
ETH_TXD0ETH_TXD1
ETH_TXD2
ETH_TXD3

DVP_VS_B
DVP_HS_B

DVP_CLK_B
DVP_D2_B
DVP_D3_B
DVP_D4_B
DVP_D5_B
DVP_D6_B
DVP_D7_B
DVP_D8_B
DVP_D9_B

Func4

SPI_SCLKSPI_SS0

ISO7816_CLKISO7816_Data

nel

SPI_MISO
SPI_MOSI
CLKOUTdk
er

GPIOZ_3
GPIOZ_4
GPIOZ_5
GPIOZ_6
GPIOZ_7
GPIOZ_8
GPIOZ_9
GPIOZ_10
GPIOZ_11
GPIOZ_12
GPIOZ_13
GPIOZ_14
GPIOZ_15

Func3

Table II.7.8 GPIOAO_x Multi-Function Pin
Func1

Func2

GPIOAO_0
GPIOAO_1
GPIOAO_2
GPIOAO_3

UART_TX_AO_A
UART_RX_AO_A
UART_CTS_AO_A
UART_RTS_AO_A
I2C_SCK_AO/
I2C_SLAVE_SCK_AO
I2C_SDA_AO/
I2C_SLAVE_SDA_AO
I2S_IN_01 (default)

UART_TX_AO_B
UART_RX_AO_B
UART_CTS_AO_B
UART_RTS_AO_B

GPIOAO_6

UART_RX_AO_B
SPDIF_OUTREMOTE_INPUT/REMOTE_OUTPUT

PWM_AO_A

CLK_32K_IN

PWM_AO_A

I2S_AO_CLK_IN
I2S_LR_CLK_IN

JTAG_TCKJTAG_TMS
JTAG_TDIJTAG_TDO

EE_CECSPDIF_OUT
WD_RESET_OUT

PWM_AO_B
PWM_Fis

RESET_ND
8.

AO_CECREMOTE_OUTPUT

tr
ib

I2SOUT_CH45

ut

I2S_AM_CLK
I2S_AO_CLK_OUT
I2S_LR_CLK_OUT
I2SOUT_CH01e

GPIOAO_7
GPIOAO_8
GPIOAO_9
GPIOAO_10
GPIOAO_11
GPIOAO_12
GPIOAO_13
TEST_NRESET_N

Func4

H

GPIOAO_5

UART_TX_AO_B

to

GPIOAO_4

Func3

ar

Pin Name

Table II.7.9 GPIOCLK_x Multi-Function Pin

Pin Name

Func1

Func2

GPIOCLK_0
GPIOCLK_1

CLK24
CLK25

CLK12(wifi)
pwm_F

Signal Description

Table II.8.1~Table II.8. 21 give the Description of signals.
Table II. 8.1 SDIO Interface Signal Description
Signal NameType

Description

SDIO_D0

DIO

SDIO data bus bit 0 signal

SDIO_D1DIO

SDIO data bus bit 1 signal

SDIO_D2

DIO

SDIO data bus bit 2 signal

SDIO_D3

DIO

SDIO data bus bit 3 signal

SDIO_CLKDO

SDIO clock signal30/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Signal NameType

Description

SDIO_CMDDIOSDIO command signal

SDIO_IRQ

DIO

SDIO interrupt request signal

Table II.8.2 SDCARD Interface Signal Description
Signal NameType

Description

SDCARD_D0

DIO

SD Card data bus bit 0 signal

SDCARD_D1

DIO

SD Card data bus bit 1 signal

SDCARD_D2

DIO

SD Card data bus bit 2 signal

SDCARD_D3

DIO

SD Card data bus bit 3 signal

DO

SD Card clock signal

DIO

SD Card command signal

Table II.8.3 Clock Interface Signal Description

nel

SDCARD_CLK
SDCARD_CMD

Type

Description

CLK12

DO

12MHz XTAL oscillator output

CLK24

DO

CLK25

DO

CLKOUTDO

dker

Signal Name

24MHz XTAL oscillator output
25MHz clock output

Configurable clock output

Table II.8.4 UART Interface Signal Description

UART_RX_A

DI

UART_CTS_A

DI

UART_RTS_A

DO

UART_TX_B
UART_RX_B

UART Port A data input

UART Port A Clear To Send Signal
UART Port A Ready To Send Signale

UART Port B data output

DI

UART Port B data input

DI

UART Port B Clear To Send Signal

DO

UART Port B Ready To Send Signal

DO

UART Port C data output

DI

UART Port C data input

DI

UART Port C Clear To Send Signal

UART_RTS_C

DO

UART Port C Ready To Send Signal

SLIP_UART_TX

DO

UART Port SLIP data output

SLIP_UART_RX

DI

UART Port SLIP data input

SLIP_UART_CTS

DI

UART Port SLIP Clear To Send Signal

SLIP_UART_RTS

DO

UART Port SLIP Ready To Send Signal

UART_TX_AO_A

DO

UART Port AO_A data output

DI

UART Port AO_A data input

D

is

tr
ib

UART_CTS_C

ut

UART_RTS_B
UART_TX_C

UART Port A data output

DO

UART_CTS_B

UART_RX_C

Description

ar

DO

H

Type

UART_TX_A

to

Signal Name

UART_RX_AO_A

UART_CTS_AO_A

DI

UART Port AO_A Clear To Send Signal

UART_RTS_AO_A

DO

UART Port AO_A Ready To Send Signal

UART_TX_AO_B

DO

UART Port AO_B data output

UART_RX_AO_B

DI

UART Port AO_B data input

UART_CTS_AO_B

DI

UART Port AO_B Clear To Send Signal

UART_RTS_AO_B

DO

UART Port AO_B Ready To Send Signal

Table II.8.5 PCM Interface Signal Description
Signal NameType

Description

PCM_OUT_A

DO

PCM port A output data stream

PCM_IN_ADI

PCM port A input data stream

31/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Signal NameType

Description

PCM_FS_ADO

PCM port A frame synchronization

PCM_CLK_A

DO

PCM port A master clock input

Table II.8.6 TS In Interface Signal Description
Type

Description

TSin_D0_A

DI

TS input port A data bus bit 0 (LSB)

TSin_D1_A

DI

TS input port A data bus bit 1

TSin_D2_A

DI

TS input port A data bus bit 2

TSin_D3_A

DI

TS input port A data bus bit 3

TSin_D4_A

DI

TS input port A data bus bit 4

TSin_D5_A

DI

TS input port A data bus bit 5

TSin_D6_A

DI

TS input port A data bus bit 6nel

Signal NameDI

TS input port A data bus bit 7 (MSB)DI

TS input port A clock

TS input port A start of stream signal

DI
DI

TSin_FAIL_A

DI

TSin_D0_B

DI

TSin_CLK_B

DI

TSin_SOP_B

DI

TSin_D_VALID_B

DI

TS input port A date valid signal

TS input port A data failure signal

TS input port B data bus bit 0 (LSB)
TS input port B clock

TS input port B start of stream signal
TS input port B date valid signalarTSin_SOP_A
TSin_D_VALID_Adker

TSin_D7_A
TSin_CLK_A

Type

DVP_D0_A

DI

DVP_D1_A

toH

Table II.8.7 DVP Interface Signal Description
Signal NameDI

DVP Port A input data bus bit 1

DI

DVP Port A input data bus bit 2

DI

DVP Port A input data bus bit 3

DI

DVP Port A input data bus bit 4

DI

DVP Port A input data bus bit 5

DI

DVP Port A input data bus bit 6

DI

DVP Port A input data bus bit 7

DVP_D8_A

DI

DVP Port A input data bus bit 8

DVP_D9_A

DI

DVP Port A input data bus bit 9

DVP_CLK_A

DI

DVP Port A input master Clock

DVP_HS_A

DVP_D2_Ae

DVP_D3_A
DVP_D5_A
DVP_D6_A

trib

DVP_D7_A

ut

DVP_D4_A

DVP Port A input data bus bit 0 (LSB)DI

DVP Port A input HSYNC Signal

DVP_VS_ADI

DVP Port A input VSYNC Signal

DVP_D2_B

DI

DVP Port B input data bus bit 2 (LSB)

DVP_D3_B

DI

DVP Port B input data bus bit 3

DVP_D4_B

DI

DVP Port B input data bus bit 4

DVP_D5_B

DI

DVP Port B input data bus bit 5

DVP_D6_B

DI

DVP Port B input data bus bit 6

DVP_D7_B

DI

DVP Port B input data bus bit 7

DVP_D8_B

DI

DVP Port B input data bus bit 8

DVP_D9_B

DI

DVP Port B input data bus bit 9

DVP_CLK_B

DI

DVP Port B input master Clock

DVP_HS_B

DI

DVP Port B input HSYNC Signal

DVP_VS_B

DI

DVP Port B input VSYNC Signal

isD

Description

Table II.8.8 PWM Interface Signal Description

32/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Signal NameType

Description

PWM_A

DO

PWM channel A output signal

PWM_B

DO

PWM channel B output signal

PWM_C

DO

PWM channel C output signal

PWM_D

DO

PWM channel D output signal

PWM_E

DO

PWM channel E output signal

PWM_F

DO

PWM channel F output signal

PWM_AO_ADO

PWM channel AO_A output signal

PWM_AO_BDO

PWM channel AO_B output signal

PWM_VSDOPWM VSYNC output signal

Table II.8.9 I2C Interface Signal Description
Type

Description

I2C_SDA_A

DIO

I2C bus port A data input/output, Master or Slave

I2C_SCK_ADIO

I2C bus port A clock input/output, Master or Slave

I2C_SDA_B

DIO

I2C bus port B data input/output, Master or Slave

I2C_SCK_B

DIO

I2C bus port B clock input/output, Master or Slave

I2C_SDA_C

DIO

I2C bus port C data input/output, Master or Slave

dk
er

ne

l

Signal NameDIO

I2C bus port C clock input/output, Master or Slave

DIO

Always-on I2C bus data input/output, Master or Slave

I2C_SCK_AO

DIO

Always-on I2C bus port A clock input/output, Master or Slavear

I2C_SCK_C
I2C_SDA_AO

Table II.8.10 I2S Interface Signal Description
Type

I2S_OUT_01

DO

I2S_OUT_23

DO

I2S_OUT_45

DODO

I2S Audio Data Output channel 6 and 7

Description

I2S Audio Data Output channel 0 and 1
I2S Audio Data Output channel 2 and 3
I2S Audio Data Output channel 4 and 5

I2S_LR_CLK_OUT

to

H

Signal NameDO

I2S Left/Right Clock output

I2S_AO_CLK_OUT

DO

I2S data clock output

DI

I2S Audio Data Input channel 0 and 1DI

I2S Audio Data Input channel 2 and 3DI

I2S Audio Data Input channel 4 and 5
I2S Audio Data Input channel 6 and 7

I2S_IN_CH23

tr
ib

I2S_IN_CH45ut

I2S_IN_CH01e

I2S_OUT_67

I2S_AO_CLK_IN

DI

I2S data clock input

I2S_LR_CLK_IN

DI

I2S Left/Right clock input

I2S_AM_CLK

DO

I2S master clock output

Dis

I2S_IN_CH67

DI

Table II.8.11 TCON Interface Signal Description

Signal NameType

TCON_OEVDO

Description
TCON output enable input for scan driver

TCON_OEH

DO

TCON output enable input for data driver /DE

TCON_VCOM

DO

TCON common electrode driving signal
TCON shift clock input for scan driver

TCON_CPVDO

TCON_STV1

DO

TCON vertical start pulse / VSYNC

TCON_STH1

DO

TCON horizontal start pulse / HYSNC

TCON_CPH

DO

TCON sampling and shifting clock pulse for data driver / PCLK

33/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Table II.8.12 EMMC/NAND Interface Signal Description
Type

Description

EMMC_NAND_D0

DIO

eMMC/NAND data bus bit 0

EMMC_NAND_D1

DIO

eMMC/NAND data bus bit 1

EMMC_NAND_D2

DIO

eMMC/NAND data bus bit 2

EMMC_NAND_D3

DIO

eMMC/NAND data bus bit 3

EMMC_NAND_D4

DIO

eMMC/NAND data bus bit 4

EMMC_NAND_D5

DIO

eMMC/NAND data bus bit 5

EMMC_NAND_D6

DIO

eMMC/NAND data bus bit 6

EMMC_NAND_D7

DIO

eMMC/NAND data bus bit 7

NAND_CE0DO

NAND chip enable 0

NAND_CE1DO

NAND chip enable 1

NAND_CE2DO

NAND chip enable 2
NAND chip enable 3lSignal Name

DO
DI

NAND ready/busy

NAND_ALEDO

NAND address latch enable:

NAND_REN_WR

DO

NAND_DQSDIO

EMMC_CLKDO

EMMC_CMDDIO

EMMC_DS

DI

dk
er

DO

NAND command latch enable:
NAND write enable and clock:

NAND read enable and write/read:
NAND data strobe

eMMC clock output

eMMC command signalarDO

eMMC data strobe

H

NAND_CLE
NAND_WEN_CLK

ne

NAND_CE3
NAND_RB0

Table II.8.13 NOR Interface Signal Description
Type

NOR_D

DO

DescriptionDI

SPI NOR Master Input

SPI NOR Master Output

NOR_C

to

Signal NameDOSPI NOR Serial Clock

NOR_CSDOSPI NOR chip select

ut

e

NOR_Q

Signal Name

Description

DIO

SPI master output, slave input

SPI_MISODIO

SPI master input, slave output

SPI_SCLKDO

SPI serial clock

SPI_SS0DO

SPI slave select 0

SPI_SS1DO

SPI slave select 1

SPI_SS2DO

SPI slave select 2

D

tr
ib

Type

SPI_MOSI

is

Table II.8.14 SPI Interface Signal Description

Table II.8.15 Remote Interface Signal Description

Signal NameType

Description

IR_REMOTE_INPUTDI

IR remote control input

IR_REMOTE_OUTPUTDO

IR remote control output

Table II.8.16 JTAG Interface Signal Description
Signal NameType

Description

JTAG_TDODO

JTAG data output

JTAG_TDIDI

JTAG data input

JTAG_TMSDI

JTAG Test mode select input

JTAG_TCKDI

JTAG Test clock input

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S905 Datasheet

Revision 1.1.4

Table II.8.17 HDMI Interface Signal Description
Signal NameType

Description

HDMI_HPDDI

HDMI hot plug in detection signal input

HDMI_SDADIO

HDMI I2C control interface data signal

HDMI_SCLDO

HDMI I2C control interface clock signal

EE_CECDIO

HDMI EE CEC (Consumer electronics control)

AO_CECDIO

HDMI AO CEC (Consumer electronics control)

Table II.8.18 RMII/RGMII Interface Signal Description
Description
Ethernet RMII interface reference clock input

ETH_RGMII_RX_CLKDI

Ethernet RGMII interface receive clock input

ETH_RGMII_TX_CLKDO

Ethernet RGMII transmit clock

ETH_TX_ENDO

Ethernet RMII/RGMII Interface transmit enable

ETH_TXD3

DO

Ethernet RGMII interface transmit data 3

ETH_TXD2

DO

Ethernet RGMII interface transmit data 2

ETH_TXD1

DO

ETH_TXD0DO

ETH_RX_CLKDI

ETH_RX_DVDI

Ethernet RMII/RGMII interface receive data valid signal

ETH_RXD3

DI

Ethernet RGMII interface receive data 3

ETH_RXD2

DI

ETH_RXD1

DI

ETH_RXD0DI

ETH_MDIO

DIO

ETH_MDC

DO

dk
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ne

l

Type
DI

Ethernet RMII/RGMII interface transmit data 1
Ethernet RMII/RGMII interface transmit data 0

arEthernet RMII/RGMII receive clock

Ethernet RGMII interface receive data 2

Ethernet RMII/RGMII interface receive data 1

H

Signal Name

Ethernet RMII/RGMII interface receive data 0

Ethernet RMII/RGMII interface management data input/output

to

ETH_CLK_RMII_50M_IN

Ethernet RMII/RGMII interface management data clock

Table II.8.19 SPDIF Interface Signal Description

tr
ib

SPDIF_OUT

ut

SPDIF_INe

Signal NameType

Description

DI

SPDIF input signal

DO

SPDIF output signal

Table II.8.20 Digital MIC Interface Signal Description
Type

Description

DMIC_IN

DI

Digital MIC input signal

DMIC_CLK_OUT

DO

Digital MIC clock output signal

Dis

Signal Name

Table II.8.21 ISO7816 Interface Signal Description

Signal NameType

Description

ISO7816_CLK

DO

ISO7816 clock signal

ISO7816_DATA

DIO

ISO7816 serial data signal

35/336AMLOGIC, Inc. Proprietary

S905 Datasheet

9.

Revision 1.1.4

Absolute Maximum Ratingsdker

10. Recommended Operating Conditions

nel

The table below gives the absolute maximum ratings. Exposure to stresses beyond those listed in this table may result inpermanent device damage, unreliability or both.
Table II.9.1 Absolute Maximum Rating
Characteristic
Value
Unit
VDD_CPU Supply Voltage
1.3
V
VDD_EE Supply Voltage
1.3
V
VDDQ Supply Voltage
1.75
V
1.8V Supply Voltage
1.98
V
3.3V Supply Voltage
3.63
V
Input voltage, VI-0.3 ~ VDDIO+0.3
V
Junction Temperature
125
°C

D

is

tr
ib

ut

e

to

H

ar

The table below gives the recommended operating conditions of S905. Exposure to stresses beyond those listed in this table
may result in permanent device damage, unreliability or both.
Table II.10.1 Recommended Operating Conditions
SymbolParameterMin.
Typ.
Max. Unit
1
VDDCPU
Voltage for Cortex A53 CPU
0.77
1.0
1.192
V
1
VDDEE_0V9
Voltage for GPU & core logic
0.77
1.0
1.192
V
1
2
VDDAO_0V9
Voltage for AO core logic
0.77
1.0
1.19
V
VDDQ
DDR3/LPDDR2/LPDDR3 IO Supply Voltage
1.15
1.6
V
1.8V AVDD for VDD18_XTAL_CLK, AVDD18_DPLL, 1.71
1.80
1.89
V
AVDD18
AVDD18_USB_ADC, AVDD18_CVBS_EFUSE, PLL_VDD,
HDMI_AVDD18, HPLL_AVDD18
USB33_VDDIOH
3.3V AVDD for USB and 3.3V VDDIO for GPIO_H
3.15
3.3
3.45
V
LV mode
1.71
1.80
1.89
V
VDDIO
HV mode2.8/3.03 3.3
3.45
V
IOVREF_1V8
Voltage for IOVREF
1.71
1.80
1.89
V
TJ
Junction Temperature
0
1254
°C
TA
Operating Temperature
0
70
°C
Note:
1) Minimal VDD_CPU/VDD_EE voltage is for sleep mode while system runs at 32.768KHz. Higher clock will need higher
voltage. Considering the power supply may have 3% deviation, the minimal voltage in actual application should not be set
to lower than 0.8V.
2) Likewise, this maximum VDD_CPU/VDD_EE voltage in actual application should not be higher than 1.1V. Voltage of
VDD_CPU will affect CPU speed. Use lower voltage when CPU runs on lower speed to save power.
3) GPIO output driving strength will be weaker when VDDIO < 3.0V in HV mode. Signal ramp-up speed and max operation
speed are lower than VDDIO at 3.3V.
4) For operating temperature, good heat sink may be needed to guarantee Tj < 125°C.

11. Ripple Voltage Specifications
Table II.11.1 below gives the ripple voltage of S905.

36/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Max Ripple

Unit

VDD_EE

1.0V

50

mV

VDDIO_AO18

1.8V

55

mV

VCCK

1.05V

50

mV

VDDIO_AO

3.3V

100

mV

VCC1.8V

1.8V

55

mV

DDR3_1.5V

1.5V

50

mV

MDDR3_VREF0

0.75V

50

mV

VDDIO_BOOT

1.8V/3.3V

55/100mV

HDMI_AVDD18

1.8V

55

mV

HDMI_VDD09

1.05V

50

mV

VCC3.3V

3.3V

100

mV

dk
er

12. Thermal Operating Specifications

neRecommended VoltagearParameterlTable II.11.1 Ripple Voltage Specifications

Value.

Unit

9.42°C/Watt

D

is

tr
ib

ut

e

to

H

The table below gives the thermal operation specification.
Table II.12.1 Thermal Operation Specification
SymbolParameterΘjc
Package junction-to-case thermal resistance in nature convection

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S905 Datasheet

Revision 1.1.4

13. DC Electrical Characteristics
13.1 Normal GPIO Specifications (For DIO_xmA)
Table II.13.1 gives the normal GPIO specifications.
Table II.13.1 Normal GPIO Specifications
SymbolParameterMin.
Typ.
High-level input voltage
IOVREF/2+0.3
ViH
Low-level input voltage-0.3
ViL
Built-in pull up/down resistor
60K
RPU/PD
21

3mA IO driving capability

31

IOVREF/2-0.3

V

l

ne

DIO_3mA

2mA IO driving capability

Unit
V

ohm
32

dk
er

DIO_2mAMax.
VDDIO+0.3

mA
mA

62

ar

4mA IO driving capability
41
DIO_4mA
Note:1) Minimal driving capability applies when VDDIO LV 1.71V, or VDDIO HV 3.0V, VOL<0.4V.
2) Maximal driving capability only applies to applications such as driving LED when VOL<0.6V.

4.52

mA

H

13.2 Open Drain GPIO Specifications (For DIO_OD)

OD IO driving low capability

6

5.5

Max.

Unit
V

0.8

V
ohm
mA

is

Iol

tr
ib

ut

e

to

Table II.13.2 shows the open drain GPIO Specifications.
Table II.13.2 Open Drain GPIO Specification
SymbolParameterMin.
Typ.
High-level input voltage
2.2
ViH
Low-level input voltage-0.3
ViL
No built-in pull up/down resistor on OD IO
N/A
RPU/PD13.3 DDR3/LPDDR2/LPDDR3 SDRAM Specifications

D

Table II.13.3~Table II.13.6 show the recommended operating conditions of DDR/SDRAM, DDR3/DDR3L/DDR3U LPDDR2 andLPDDR3 module respectively.
Table II.13.3 Recommended Operating Conditions of DDR/SDRAM Module
SymbolParameter
Min.
Typ.
Max.
Unit
IO supply voltage(DDR3)
1.46
1.50
1.57
V
VDDQ
IO supply voltage(DDR3L)
1.31
1.35
1.45
V
VDDQ
IO supply voltage(DDR3U)
1.21
1.25
1.31
V
VDDQ
IO supply voltage(LPDDR2/LPDDR3)
1.16
1.20
1.30
V
VDDQ

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S905 Datasheet

Revision 1.1.4

SymbolTable II.13.5 DC Specifications – LPDDR2 mode
ParameterMin.
Typ.
DC input voltage highVref + 0.13

VIH
DC input voltage low

VSSQ

DC output logic high

0.9*VDDQ

ar

VIL
VOH
VOL

to

Table II.13.6 DC Specifications – LPDDR3 mode
ParameterMin.
Typ.
DC input voltage highVref + 0.100

VIH

ut

DC input voltage loweSymbolVIL

DC output logic high

tr
ib

VOH

VSSQ

Max.
VDDQ
Vref-0.100

Unit
V
V
V
V
ohm

0.2*VDDQ
140
66
44

Max.
VDDQ

Unit
V

Vref-0.13

VV

0.1*VDDQ

V

Max.
VDDQ

Unit
V

Vref-0.100

V

0.9*VDDQV

DC output logic low
VOL

100
200

120
240

0.1*VDDQ

V

140
280

ohm

D

is

Input termination resistance to VDDQ
RTT

V

H

DC output logic low

0.51*VDDQlTable II.13.4 DC specifications - DDR3/DDR3L/DDR3U mode
ParameterMin.
Typ.
DC input voltage highVref + 0.100
DC input voltage low
VSSQ
DC output logic high
0.8*VDDQ
DC output logic low
Input termination resistance to VDDQ/2
100
120
54
60
36
40

dk
er

Symbol
VIH
VIL
VOH
VOL
RTT

0.5*VDDQne

Input reference supply voltage
0.49*VDDQ
Vref
Note: The minimal VDDQ voltage in sleep mode is defined by memory.

39/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

13.4 Recommended Oscillator Electrical Characteristics
S905 requires the 24MHz oscillator for generating the main clock source.

Description
Nominal Frequency

Δf/fo

Frequency Tolerance

Unit
MHz
ppm

Notes

-50

+50

ppm

At -20~85 ℃

20
80

pF
oHm

CL

ne

Load Capacitance
8
12
ESR
Equivalent Series Resistance
Note: 10ppm Tolerance is preferred if 24MHz XTAL is also driving WIFI module.

At 25 ℃l

SymbolFo

Table II.13.7 24MHz Oscillator Specification
Min.
Typ.
Max.
24
-30
+30

dk
er

14. Recommended Power on sequence
Example power on sequence is shown in Fig II.14.1：

VDDIO_AO18&IOVREF->VDDEE_0V9->VDDIO_AO3.3V&VDDIO_3.3V&AVDD18& VDDIO1.8V ->VDDCPU&VDDQ

D

is

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e

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H

ar

Fig II.14.1 Recommended Power on Sequence

Note:
1)
2)

No sequence requirement between power domains which are grouped as showing in the example sequence above.
Step delay should be 0-4ms. VDDIO_AO3.3V&VDDIO_3.3V is recommended to ramp up at least 1ms later than VDDEE.

40/336AMLOGIC, Inc. Proprietary

S905 Datasheet

3)
4)
5)
6)
7)

Revision 1.1.4

VCC_CORE is the power Name if VDDEE and VDDCPU are merged.
VDDQ can be off and enabled by software.
VDDIO3.3V should never exceed IOVREF_1V8 + 2V.
Reset should be low before power up & kept low > 40ms after all power is on (except VDDQ).
VDDIO_AO18 is for some GPIOs such as WiFi IO.

Please refer to reference schematics.

15. Power Consumption

VDDCPUVDDEE_0V9
VDDQ

2A
2A
1A

Note

ne

Maximum Current

dk
er

Symboll

Note：Value listed here is typical max value tested. Enough margin in circuit needs to be reserved.
Table II. 15.1 System Power Consumption

Total power of controller and DDR3 memory
Table II.15.2 Module Power Consumption

SymbolTypical current

Maximum current

HDMITX_AVDD33

80mA
32mA

-

80mA
9mA
7mA
35mA
0.4mA
-

-

AVDD18_CVBS_EF
USE

ar

H

to

40mA

0mA

-

20mA

Typical value when DDR3 controller is enabled
Typical value 0.4mA when XTAL is oscillating
USB: 19mA per channel at high speed ode , total 2 channel
ADC: 1.2mA During sampling
EFUSE: Max 100mA when programing EFUSE. Normally 0mA
CVBS: 38mA typically when CVBS output enabled.
Max 20mA when all GPIO powered with 3.3V & switch at 75MHz.
Normally 0mA

is

IOVREF_1V8

Mechanical Dimension

D

16.

38mA

e

AVDD18_USB_ADC

At 6Gbps mode
USB: 16mA Per channel, full/low speed mode, total 2 channel
VDDIOH: normally 0mA, will be higher if there’s pull low loading.
At 6Gbps modeut

HDMI_AVDD18
HPLL_AVDD18
AVDD18_DPLL
PLL_VDD
VDD18_XTAL_CLKtrib

USB33_VDDIOH

Note

The S905 processor comes in a 19x19 ball matrix LFBGA RoHS package. The mechanical dimensions are given in millimeters as
below.
Note the following positions have null balls: C5, C8, C12, C15, C19, E3, E17, G5, G7, G10, G13, H3, H17, J12, K8, M3, M7, M10,
M13, M17, P5, R3, R17, U6, U11, U13, W9.

41/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

D

is

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Fig II.16.1 Mechanical Dimension of S905

42/336AMLOGIC, Inc. Proprietary

Revision 1.1.4

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S905 Datasheet

43/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

dker

17. Memory Map

neThis part describes the S905 system architecture from the following aspects:
 MEMORY MAP
 POWER DOMAIN CPU and GPU SUBSYSTEM
 CLOCK AND RESET UNIT
 SYSTEM BOOT
 GENERAL PURPOSE INPUT/OUTPUT (GPIO) INTERRUPT CONTROLLER DIRECT MEMORY ACCESS CONTROLLER (DMAC)
 TIMER CryptolSection III System

S905’s memory map is listed as following in Table III.17.1.
Table III.17.1 S905 Memory Map
Start

End

Region (Normal)

NIC Arbitor
DDR

0xBFFFFFFF

DDR

0xC01FFFFF

USB

0xC0200000

0xC03FFFFF

0xC0400000

0xC07FFFFF

0xC0800000

0xC08043FF

0xC0804400

0xC08044FF

0XC0804500

0xC08047FF

0xC0804800

0xC08048FF

0xC0804900

0xC08053FF

0xC0805400

0xC08054FF

0xC0805500

0xC08057FF

ar0x00000000
0xC0000000

DAP

e

to

H

CSSYS

RESET
VDIN
AIU

0xC08058FF

STB

0xC0805900

ut

0xC0805800

ASSIST

0xC0808400

0xC08084FF

PERIPHS

0xC0808500

0xC0808BFF

0xC0807C00

0xC0807CFF

0xC0808C00

0xC0808CFF

0xC0808D00

0xC08097FF

0xC0809800

0xC08098FF

0xC0809900

0xC080BFFF

0xC080A000

0xC080A0FF

0xC080A100

0xC080A3FF

0xC080A400

0xC080A4FF

0xC080A500

0xC12FFFFF

D

CAPB3

0xC08083FF

is

tr
ib

0xC0807D00

0xC0807BFF

0xC1300000

0xC42FFFFF

0xC4300000

0xC4307FFF

0xC4308FFF

0xC7FFFFFF

0xC8000000

0xC8013FFF

0xC8014000

0xC80FFFFF

0xC8100000

0xC81FFFFF

0xC8200000

0xC881FFFF

0xC8820000

0xC882FFFF

0xC8830000

0xC8831FFF

0xC8832000

0xC8833FFFPERIPHSISA
AUDINPARSER

GIC

GIC

RTI
SYS AHBDOS
BLKMV

44/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Region (Normal)
PERIPHS

0xC8836000

0xC8837FFF

DDR TOP

0xC8838000

0xC8839FFF

DMC

0xC883A000

0xC883BFFF

HDMITX

0xC883C000

0xC883DFFF

HIU

0xC883E000

0xC8FFFFFFF

0xC9000000

0xC90FFFFF

USB0

0xC9100000

0xC91FFFFF

USB1

0xC9200000

0xC940FFFF

0xC9410000

0xC941FFFFETHERNET

0xCC000000

0xCFFFFFFF

SPI

0xD0000000

0xD0041FFF
0xD0043FFF

PDM

0xD0044000

0xD00440FF

HDCP220xD0044100

0xD0047FFF

0xD0048000

0xD004FFFF

BT656

0xD0050000

0xD005FFFF

BT656_2

0xD0060000

0xD006FFFF

0xD0070000

0xD0071FFF

SD_EMMC_A

0xD0072000

0xD0073FFF

SD_EMMC_B

0xD0074000

0xD0075FFF

SD_EMMC_C

0xD0076000

0xD00BFFFF

0xD0150000

0xD015FFFF

0xD0160000

0xD016FFFF

0xD0170000

0xD01FFFFF

0xE0000000

0xFFFFFFFF

MALI APB

ar

0xD013FFFF

VPU

H

0xD00FFFFF

0xD0100000

GE2D

VAPB3

D

is

tr
ib

ut

e

to

0xD00C0000

CAPB3

dk
er

0xD0042000

NIC ArbitorlEnd
0xC8835FFF

ne

Start
0xC8834000

45/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

18. Power Domain
Fig III.18.1 shows the power domain of S905.

Fig III.18.1 Power DomainPower Management IC
DC/DC

LDO

VDD_A53 (e.g.
0.81v ~ 1.2v
(overdrive))

ne

l

DC/DC

0.9v EE Domain logicdker

Always On 0.9v

VDD_A5

VDD_EE

VDD

ISO

AO Domain

VDDA5_SAXI(VDDCE,VDDPE)

Everything Else Domain(VDDCE,VDDPE)

ut

CPU0 power switch control
CPU1 power switch control
CPU2 power switch control
CPU3 power switch control

DDR0_VDDQ
1.2v ~ 1.5v

VDD_EEDOS

PLLS (1.8v)
SAR ADC (1.8v)

misc
VDD_EE

ISO

ISO

SYS
PLL

tr
ib

A53 Power Domain

DDR0_PLL (1.8v)

Level shift(VDDCE,VDDPE)e

CPU3(+neon)RAMs

toa53_clk_rst_tst()

CPU2(+neon)RAMs

MMC

DDRPHY(VDDCE,VDDPE)

H

CPU1(+neon)
RAMs

ar

SCU
L2 CacheCPU0(+neon)RAMs

Signal Register Bit(s)scssys_mem_pd AO_RTI_PWR_SYS_CPU_MEM_PD1 0xc81000f8[4]cpu0_mem_pd[3:0] AO_RTI_PWR_SYS_CPU_MEM_PD1 0xc81000f8[3:0]
cpu1_mem_pd[3:0] AO_RTI_PWR_SYS_CPU_MEM_PD0 0xc81000f4[31:28]
cpu2_mem_pd[3:0] AO_RTI_PWR_SYS_CPU_MEM_PD0 0xc81000f4[37:24]
cpu3_mem_pd[3:0] AO_RTI_PWR_SYS_CPU_MEM_PD0 0xc81000f4[23:20]
l2_mem_pd[17:0] AO_RTI_PWR_SYS_CPU_MEM_PD0 0xc81000f4[17:0]
cpu_isolate_n[3:0] AO_RTI_PWR_SYS_CPU_CNTL0 0xc81000E0[3:0]a53mp_isolate_n AO_RTI_PWR_SYS_CPU_CNTL0 0xc81000E0[4]cpu0_sleep[1:0] AO_RTI_PWR_SYS_CPU_CNTL1 0xc81000E4[3:2]
cpu1_sleep[1:0] AO_RTI_PWR_SYS_CPU_CNTL1 0xc81000E4[5:4]
cpu2_sleep[1:0] AO_RTI_PWR_SYS_CPU_CNTL1 0xc81000E4[7:6]
cpu3_sleep[1:0] AO_RTI_PWR_SYS_CPU_CNTL1 0xc81000E4[9:8]l2_scu_top_sleep AO_RTI_PWR_SYS_CPU_CNTL1 0xc81000E4[0]cpu_sleep_status[3:0] AO_RTI_PWR_SYS_CPU_CNTL1 0xc81000E4[19:16]
l2_scu_top_sleep_status AO_RTI_PWR_SYS_CPU_CNTL1 0xc81000E4[20]u_vdec_top
VDD_EEu_hevc_top

is

ISO

VDD_EEu_hcodec_top

DGPU

HDMI-TX
2.97Ghz
2.8v ± 400mV

VDD_EE

GP0+L2C_0
PP0+L2C_1
PP1

vpu_hdmi

VDD_EE

Video DAC
54Mhz,
1.8v supply

VPU
HDMI

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S905 Datasheet

Revision 1.1.4

18.1 Top Level Power Domains
The power supplies for the different domains must follow a specific power supply order: The A53 can’t be powered without
the EE domain. The EE domain can’t be powered up without the AO domain. If you read the Table III.18.1 left to right thenright to left, that’s essentially the power up/down sequence for the entire chip.
Table III.18.1 Power on Sequence of Different Power Domains
Always On

EE Domain

A53 domain
A53(SCU/L2)

EE Logic

Mali and DOS and VPU

L2 Cache

CPU0

CPU1

CPU2/3

STATE 0All off

Off

The EE domain must be OFF if the AO
domain is off

The A53 domain must be off if the EE domain is OFF

STATE 1
Hibernate: Only the Always
on Domain is powered

On

Off

The Mali must be OFF is if
the EE domain is off

The A53 domain must be off if the EE domain is OFF

STATE 2
Always On/EE only (forexample audio applications
or simple video applications
that don’t need the A53)

On

On

On or off as needed

STATE 3Single CPU

On

On

On or off as needed

STATE 42 CPU’sOn

On

On or off as needed

STATE 5
4 CPUsOn

On

On or off as needed

dk
er

Off

Off

Off

Off

All three must be enabled

Off

Off

All three must be enabled

On

Off

All three must be enabled

On

On

H

ar

Off

ne

l

Logic

18.2 A53 Power Modes

tr
ib

ut

e

to

The A53 domain is the last to power up and the first to power down. The A53 domain itself consists of a quad (4) CPU, an L2
cache controller and an SCU. The A53 CPU boots with the SCU/L2 powered and CPU0 powered. After CPU0 boots, subsequent
CPU’s can be enabled and disabled independently of one another using the control bits described below. The most likely
scenario would be for the CPU0 to be used for low load conditions, CPU0 and CPU1 to be used for medium load conditions andCPU0,1,2 and CPU3 to all be used for heavy load conditions. It’s unlikely we will run a 3 CPU configuration (although it’s notprecluded by the hardware). The flow-diagram below illustrates the transition to each legal state.
Table III.18.2 Power On Sequence of A53

Domain Power Sleep bitis(1 = power off)D

Domain Power Acknowledge bit
Input Signal isolation bit(1 = isolated)
Output signal isolation bit(1 = isolated)

CPU0

CPU1

CPU2

CPU3

Bit[2]
of
0xC81000E4

Bit[4]
of
0xC81000E4

Bit[6]
of
0xC81000E4

Bit[8]
of
0xC81000E4

Bit[16]of
0xC81000E4
Bit[0]
of
0xC81000E0

Bit[17]of
0xC81000E4
Bit[1]
of
0xC81000E0

Bit[18]of
0xC81000E4
Bit[2]
of
0xC81000E0

Bit[19]of
0xC81000E4
Bit[3]
of
0xC81000E0

Bit[0]
of
0xC81000E0

Bit[1]
of
0xC81000E0

Bit[2]
of
0xC81000E0

Bit[3]
of
0xC81000E0

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S905 Datasheet

Revision 1.1.4

Fig III.18.2 Power Seuquence of A53
COLD BOOT

Shutdown

cpu0_sleep = 1;
cpu1_sleep = 1;
cpu2_sleep = 1;
cpu3_sleep = 1;

MediumLoad
2 CPU’s

cpu0_sleep = 0;
cpu1_sleep = 0;
cpu2_sleep = 1;
cpu3_sleep = 1;

Light Load 1
CPU’s

cpu0_sleep = 0;
cpu1_sleep = 1;
cpu2_sleep = 1;
cpu3_sleep = 1;

Intermediate
power to fullload

cpu0_sleep = 0;
cpu1_sleep = 0;
cpu2_sleep = 0;
cpu3_sleep = 1;

MediumLoad 2 CPU’s

cpu0_sleep = 0;
cpu1_sleep = 0;
cpu2_sleep = 1;
cpu3_sleep = 1;

Full Load
4 CPU’s

cpu0_sleep = 0;
cpu1_sleep = 0;
cpu2_sleep = 0;
cpu3_sleep = 0;

Intermediate
power
tomedium load

cpu0_sleep = 0;
cpu1_sleep = 0;
cpu2_sleep = 0;
cpu3_sleep = 1;

18.3 EE Top Level Power Modes

to

H

ar

dk
er

cpu0_sleep = 0;
cpu1_sleep = 1;
cpu2_sleep = 1;
cpu3_sleep = 1;

ne

Boot

l

Warm boottribEthernet Memory PDute

EE domain is powered off by DC-DC. VDD_EE also share the same VDD with VDDCE of A53 memory arrays. So if EE domains isshut off, A53 memory is also shut off. That does not matter. Before EE power domain is shut off, A53 should be shut off at first.
Table III.18.3 Power Sequence of EE Domain

HDMI Memory PD

Bits[3:2] of 0xC883C100 (HI_MEM_PD_REG0)
0x3 = power off, 0x0 = normal operation
Bits[15:8] of 0xC883C100 (HI_MEM_PD_REG0)0xFF = power off, 0x0 = normal operation
Bit[31:0] of 0xC883C104/ 0xC883C108
0xFFFFFFFF = power off, 0x0 = normal operation

Dis

VPU memory PD

Register/Bit(s)18.4 Mali Power Modes
The Mali block sits within the EE domain and the Mali module itself has 3 distinct power domains: GP + L2C_0
 PP0 + L2C_1
 PP12
We will power these up in sequence so as to reduce the surge currents. The following combinations are possible.

48/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Table II.18.4 Power Sequence of Mali Module
Mali AXI Cores

GP + L2C_0
PP0 + L2C_1
PP12

1PP
Power
up/down
1st / last
2nd / 1st

3PP
Power
up/down
1st / last
2nd / 2nd
3rd / 1st

18.5 Power/Isolation/Memory Power Down Register Summary
Below lists the registers related to A53.

tr
ib

is

D

A53 RAM Power Down Control
Bit(s)
31-28
27-24
23-20
19-18
17~0

R/W
R/W
R/W
R/W
R/W

0xc81000f4

Default
0xF
0xF
0xF
0
0x00000

A53 RAM Power Down Control (cont.)
Bit(s)
31-4
3~0

R/W
R/W

Description
Reserved
CPU3 Sleep status: 1 = powered down
CPU2 Sleep status: 1 = powered down
CPU1 Sleep status: 1 = powered down
CPU0 Sleep status: 1 = powered downReserved
CPU3 sleep: 1 = powered down
CPU2 sleep: 1 = powered down
CPU1 sleep: 1 = powered down
CPU0 sleep: 1 = powered downReservedeDefault
0
00
11
11
11
00
10

ut

R/W
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W

to

A53 Power 0xc81000e4Bit(s)
31~20
19
18
17
16
15~10
9~8
7~6
5~4
3~2
1-0

ne

Description
CPU3 CTRL_MODE set by the CPU
CPU3 CTRL_MODE set by the CPU
CPU3 CTRL_MODE set by the CPU
CPU3 CTRL_MODE set by the CPU
CPU3 CTRL_MODE
CPU2 CTRL_MODE
CPU1 CTRL_MODE
CPU0 CTRL_MODE (set to tell the CPU which mode to enter)Reserved
A53 Pwr top level clamp
SCURAM Clamp
NEON[3:0] Clamp
CPURAM[3:0] clamp
CPU[3:0] clampdkerDefault
11
11
11
00
0
0
0
0xE
0xE
0xE

ar

R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

H

Bit(s)
31~30
29~28
27~26
25~24
23~22
21~20
19~18
17~16
15~14
13
12
11~8
7~4
3~0

l

A53 Isolation 0xc81000e0

Default0
0x0

Description
CPU1 RAM power down (Each Bit controls different RAMs): 1 = powered down
CPU2 RAM power down (Each Bit controls different RAMs): 1 = powered down
CPU3 RAM power down (Each Bit controls different RAMs): 1 = powered downReserved
L2 RAM power down (Each Bit controls different RAMs): 1 = powered down

0xc81000f8
Description
Reserved
CPU0 RAM power down (Each Bit controls different RAMs): 1 = powered down

49/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

A53 SYS PLL 0xc1104300
PLL Enable = Bit[30]: 1 = pll enabled, 0 = pll disabled

Default
00000Always On domain PWR_CNTL00xc8100010

General Power gen_pwr_sleep_cntl0
Default
0
0
0
0
1
1
1
1
1
1

General Isolation gen_pwr_iso_cntl0

D

ne

dk
er

0xc81000e8

Description
Reserved
VPU/HDMI Isolation
VPU/HDMI power: 1 = powered off
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

tr
ib

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

is

Bit(s)
31~10
9
8
7~6
5
4
3
2
1
0

Description
Reserved
reservedAHB SRAM Memory power down: 00 = normal operation, 10 = power down. Other conditions reserved
Reserved
Reserved
32khz DS:
Alternate 32khz input clock select from GPIO pad
Reset to the EE domain. 0 = reset, 1 = normal operation
RTC oscillator input select: 1 = use RTC clock as clock. 0= used clk81 as the clock
reserved
EE domain isolation In
EE domain Isolation out
Reserved
Always on RESET isolation: 1 = isolated
ReservedlDefault
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0

ar

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

H

Bit(s)
31~28
27~22
21~20
19~16
15~14
13~12
11~10
9
8
7~5
4
3
2
1
0

Description
Reserved
DDR1PHYIO_RET_EN
DDR1PHYIO_REG_EN_N
DDR0PHYIO_RET_EN
DDR0PHYIO_REG_EN_N

e

R/W
R/W
R/W
R/W
R/W
R/W

ut

Bit(s)
31~4
3
2
1
0

0xc810000c

toAlways On domain PWR_CNTL1

Bit(s)
31~10
9
8
7
6
5
4
3
2
1~0

0xc81000ec
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPU ISO OUTGPU ISO IN
reserved

General Acknowledge gen_pwr_sleep_ack0

0xc81000f0

50/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Description
Reserved
MALI PP456 power up: Write a 1 to power up
MALI PP12 power up
MALI PP0 power up
MALI GP power up

Mali Power Down (domains_npwr_up) 0xd00c2004

arDescription
Reserved
MALI PP456 power down: Write a 1 to power down
MALI PP12 power down
MALI PP0 power down
MALI GP power downH

Bit(s)
31~3
3
2
1
0

l

Bit(s)
31~3
3
2
1
0

0xd00c2000

neMali Power UP (domains_npwr_up)

Description
Reserved
Reserved
MALI_PWRUP_ACK: PP456 acknowledge: 1 = powered off
MALI_PWRUP_ACK: PP12 acknowledge: 1 = powered off
MALI_PWRUP_ACK: PP0 acknowledge: 1 = powered off
MALI_PWRUP_ACK: GP acknowledge: 1 = powered off
Reserved
Reserved
Reserved
ReserveddkerBit(s)
31~9
8
7
6
5
4
3
2
1
0

to

19. System Bootinge19.1 Overview

ut

The part describes the power–on mode configuration of S905, which include two portions: Cortex-M3 for security control and
A53 for others.

trib

19.2 Power-on Flow Chart

D

isFig22.1 illustrates S905’s power on sequence.

51/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

to

H

ar

dk
er

ne

l

Fig III.19.1 Power-on Flow Chart

20. CPUe

20.1 Overview

tr
ib

ut

The Cortex™-A53 MP subsystem of the chip is a high-performance, low-power, ARM macrocell with an L1 cache subsystem andan L2 cache subsystem that provide full virtual memory capabilities. The Cortex-A53 processor implements the ARMv8
architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions and 64 bit ARMv8 instructions. The
developers can follow the ARM official reference documents for programming details.

D

is

The Cortex-A53 processor features are:
in-order pipeline with dynamic branch prediction
ARM, Thumb, and ThumbEE instruction set supportTrustZone security extensions
Harvard level 1 memory system with a Memory Management Unit (MMU)
128-bit AXI master interface
ARM CoreSight debug architecture
trace support through an Embedded Trace Macrocell (ETMv4) interfaceIntelligent Energy Manager (IEM) support with­
asynchronous AXI wrappers­
two voltage domains
Media Processing Engine (MPE) with NEON technologySurpports FPUSurpports Hardware Virtualization

21. GPU

52/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

The Mali-450 MP GPU is a hardware accelerator for 2D and 3D graphics system which compatible with the following graphics
standards: OpenGL ES 2.0, OpenGL ES 1.1, OpenVG 1.1, EGL 1.5. The developers can follow the ARM and Khronos official
reference documents for programming details.

22. Clock and Reset
22.1 Overview
The clock and reset unit is an APB slave module that is designed for generating all of the internal and system clocks, resets of
chip.

22.2

Clock Treesnel

FigIII. 22.1 shows the PLLs of S905.
FigureIII.22.1 PLLs

N

÷1,2,4

2000Mhz

OD
M

÷2

÷2
÷3
÷4

FCLK_DIV2

666.7Mhz

FCLK_DIV3

500MhzFCLK_DIV4

400MhzFCLK_DIV5H÷51000Mhzar

FIXED_DPLL

Crystal
24Mhz

dk
er

2000Mhz because that’s the only way to get 50Mhz
for Ethernet using a 24Mhz Crystal

÷7

285.7Mhz

250Mhz ~ 637Mhz MPLL_CLK_OUT0/1/2/3

ut

e

to

MP0/1/2/3

FCLK_DIV7DDR PLL

N

OD

tr
ib

M

GP PLLNisM

÷1,2,4,8

Pll_ref: 5~25Mhz, VCO:
750~1.5Ghz

DDR_DPLL_CLK_OUT

Pll_ref: 5~25Mhz, VCO:
1.2G~3.0Ghz

GP0_DPLL_CLK_OUT

Pll_ref: 5~25Mhz, VCO:
1.2G~3.0Ghz

HDMI_DPLL_CLK_OUTOD

÷2

HDMI PLL

ND

÷1,2,4

÷1,2,4,8

OD
M

÷2
OD_FB

53/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Table III.22.1 Integer PLL Parameters
Integer PLL
DDR_DPLL
VID_DPLL
HDMI_DPLL (VIID_DPLL)FIXED_DPLL

F-Ref Min(XTAL/N)
5 Mhz
5 Mhz
5 Mhz

F-Ref Max(XTAL/N)
30 Mhz
30 Mhz
30 Mhz

5 Mhz

30 Mhz

VCO MIN

9
9
9

OD
Bits
2
2
2

750Mhz1.2Ghz1.2GhzVCO
MAX
1.5Ghz3.0Ghz3.0Ghz

9

1

1Ghz

2Ghz

N-bitsM-bits5555OD divider
2-bits: ÷1, ÷2, ÷4
2-bits: ÷1, ÷2, ÷4, ÷8
OD: ÷1, ÷2, ÷4, ÷8
FB: ÷1, ÷2
LVDS: ÷1, ÷2, ÷4, ÷8

Fig III.22.2 Mutil Phase PLLS

÷1,2,4

2.00G

OD
M

OD_FB

Multi-Phase
PLL

÷XD

ne

FIXED_DPLL
N

final_clk

dk
er

24Mhz

l

f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)

Table III.22.2 Multi-Phase PLL Parameters
SDM_IN SDM_IN
[Min]
[Max]
1
16383
1
16383
1
16383

ar

MP0_DPLL
MP1_DPLL
MP2_DPLL

N2_integer
[Max]
127
127
127

H

N2_integer
[Min]
4
4
4

Multi-Phase

Fout
[Min]
5 Mhz
5 Mhz
5 Mhz

Fout
[Max]
500Mhz
500Mhz
500MhzTable III.22.3 Direct Divide Frequencies (assuming 2.000 GHz fixed source clock)to

PLL_DIV7
364Mhz

÷1

D

is

tr
ib

ut

666.6667
500
400
333.3333
285.7143250
222.2222200
166.6667
142.8571
133.3333125
111.1111100
95.238183.3333380
74.07407
71.42857
66.66667
62.5
60.60606
57.14286
55.55556
51.2820550
47.61905
45.45455

Effective
PLL_DIV3 PLL_DIV4 PLL_DIV5
Divider from 2.550Ghz 850Mhz
637.5
510
3
÷1
4
÷1
5
÷1
6
÷2
7
8
÷2
9
÷3
10
÷2
12
÷4
÷3
14
15
÷5
÷3
16
÷4
18
÷6
20
÷5
÷4
21
÷7
24
÷8
÷6
25
÷5
27
÷9
28
÷7
30
÷10
÷6
32
÷8
33
÷11
35
÷7
36
÷12
÷9
39
÷13
40
÷10
÷8
42
÷14
44
÷11

e

Target Frequency

54/336

÷2

÷3

÷4

÷5

÷6

AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

44.44444
41.66667
40.81633
40
39.21569

45
48
49
50
51

÷15
÷16

÷9
÷12
÷7
÷10

÷17

Table III.22.4 Audio Frequencies (using Multi-phase PLL)
Error
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%

l

final_clk
[Mhz]
2.016
3.024
2.048
3.072
2.822
4.234
3.072
4.608
4.096
6.144
5.645
8.467
6.144
9.216
8.192
12.28811.29016.93412.28818.43224.57636.86449.15273.728ne

Divider in
clk_rst_tst
127
77
125
86
87
61
86
67
100
43
87
58
43
53
50
23
42
29
23
26
13
13
9
6

dk
er

SDM_IN
13296
9655
13312
9343
2376
12197
9343
7832
14464
9343
1188
1188
9343
1550
14464
1254
3571
1188
1254
2840
4260
2840
8538
8538

ar

N2_integer
7
8
7
7
8
7
7
6
4
7
4
4
7
4
4
7
4
4
7
4
6
4
4
4

H

Target freq
[Mhz]
2.016
3.024
2.048
3.072
2.82244.2336
3.072
4.608
4.096
6.144
5.64488.4672
6.144
9.216
8.192
12.28811.2896
16.9344
12.28818.43224.57636.86449.15273.728toOver
Sampling
256
384
256
384
256
384
256
384
256
384
256
384
256
384
256
384
256
384
256
384
256
384
256
384

e

Sampling
Frequency
7875 Hz7875 Hz
8000 Hz
8000 Hz11025 Hz11025 Hz
12000 Hz
12000 Hz
16000 Hz
16000 Hz
22050 Hz
22050 Hz
24000 Hz
24000 Hz
32000 Hz
32000 Hz44100 Hz44100 Hz
48000 Hz
48000 Hz
96000 Hz
96000 Hz
192000 Hz
192000 Hz

tr
ib

ut

Ethernet Frequencies: 10/100 Ethernet: 50Mhz
 10/100/1000 Ethernet: 125Mhz and 25Mhz

is

USB Frequencies:
 19.2, 20, 24, 50Mhz

D

HDMI Frequencies:
 Min: 250Mhz (at the PHY) 25Mhz to the logic
 Max: 5.94Ghz at the PHY (4k2k)

55/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Fig III.22.3 N Frenquency Divider Diagram
clk_rst_tst()
ALWAYS ON DOMAIN
Always On
CPU

0x105d
[14:12]32khz

00x105d[7]7

scan_clk

G

÷N

0

1

clk81 (166.7Mhz)

00x105d[8]0x105d
[14:0]

ISO

24Mhz

0x105d[9]fclk_div5
fclk_div3
fclk_div4
mpll_clk_out2
mpll_clk_out1
fclk_div7
1’b0
XTAL/32khz

32khz

0

clk_system_in

1

0

1

dk
er

All over EE domainnel

XTAL/32khz

22.3 Clock Gating

address

Bit(s)

CBUS

0x55

31-5
4
3
2
1
0

UnusedPERIPHSASSIST

is

tr
ib

ut

Ao_i2cAlways on Registers, timers,…
AHB bus in the always on domain
AHB SRAMAO CPU

Table III.22.6 EE Domain Clock Gating
Final address = 0xc8834400 + offset * 4

address

Bit(s)

Module Description

0x50

31

Reserved

30

SPI Interface

29

Reserved

28

Reserved

27

Reserved

26

Reserved

25

Reserved

24

Reserved

23

ASSIST_MISC

22

ReservedD

ModuleModule DescriptioneModuletoHarModules and sub-modules within the chip can be disabled by shutting off the clock. The control for these clocks comes fromsix CBUS registers that collectively make up a 64-bit register that controls the MPEG_DOMAIN and a32-bit register that controls
the OTHER_ DOMAIN. The table below indicates the Bits associated with either the MPEG_DOMAIN and OTHER_DOMAIN
gated clock enables. The table is organized by function rather than by bit order because it makes it easier to determine how
to turn on/off a particular function within the chip. If a bit is set high, the clock is enabled. If a bit is set low, the clock is turned
off and the module is disabled.
Table III. 22.5 AO Domain Clock Gating
Final address = 0xc8834400 + offset * 4

56/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Module Description

21

Reserved

20

Reserved

HIU

19

HIU Registers

ABUF

18

Audio Buffer u_abuf_top.HCLKPERIPHS17

SDIO

PERIPHS

16

ASYNC_FIFOPERIPHS

15

STREAM Interface

PERIPHS14SDHC

PERIPHS13

UART0

PERIPHS

12

Random Number generator

PERIPHS

11

Smart CardPERIPHS10SAR ADCPERIPHS

9I2C Master / I2C SLAVEPERIPHS8SPICCPERIPHS7

PERIPHS module top level (there are separate register Bits for internal blocks)

DDR

6PL301 (AXI Matrix) to CBUS

ISA

5

ISA module

4

Reserved

3

Reserved

2

Reserved1

u_dos_top()0

DDR Interfaces and bridges

DOS(MDEC)
DDR

ne
dk
er

ar

ROM BOOT ROM clock

30

EFUSE logic

MISC

29

AHB ARB0

VIU

28

VDIN1

ut

e

31

MISC

tr
ib

MISC

0x51

l

Bit(s)

H

addresstoModuleRevision 1.1.4

27
26

USB General

25

U_parser_top()

PERIPHS

24

NAND Interface

23

RESET

22

USB 1

21

USB 0

20

General 2D Graphics Engine

19

Reserved

18

Reserved

17

Reserved

PERIPHS

16

UART1

AIU

15

AIU Top level (there is internal gating shown below)

BLKMV

14

Block move core logic

AIU

13

ADC

USB
USB
GE2D

D

MISC

is

USB
DOS

57/336AMLOGIC, Inc. Proprietary

S905 Datasheet

address

Bit(s)

Module Description

AIU

12

Mixer Registers: u_ai_top.u_mixer_reg.clk

AIU

11

Mixer: u_ai_top.u_aud_mixer.clk

AIU

10

AIFIFO2: u_ai_top.u_aififo2.clk

AIU

9

AMCLK measurement circuit

AIU

8

I2S Out: This bit controls the clock to the logic between the DRAM control unit and the FIFO’s that transfer data to theaudio clock domain. (u_ai_top.I2S_fast.clk)

AIU

7

IEC958: iec958_fast()l

ModuleRevision 1.1.4

AIU

6

ne

AIU – ai_top_glue
u_ai_top.ai_top_glue.clk
u_ai_top.fifo_async_fast_I2S.clk

dk
er

u_ai_top.fifo_async_fast_958.clk
5
4

Set top box demux moduleu_stb_top.clk

ETHERNET

3

Ethernet core logic

AUDIN

2

I2S / SPDIF Input

1

Reserved

0

Reserved

31

Reserved

30

Reserved

29

CLK81 to the A53 domain

28

Reserved

27

Reserved

AHB

26

Secure AHB to APB3 Bridge

VPU

25

VPU Interrupt

24

Reserved

H
to

e

tr
ib

MISC

ut

0x52

ar

DEMUX

23

Reserved

22

SANA

21

Reserved

20

Reserved

19

Reserved

18

Reserved

17

Reserved

16

Reserved

15

UART 2

13

Reserved

MISC

12

DVIN

DDR

11

MMC PCLK

10

ReservedUSB

9

USB0 to DDR bridgeUSB

8

USB1 to DDR bridge

7

Reserved

D

is

PERIPHSPERIPHS

58/336AMLOGIC, Inc. Proprietary

S905 Datasheet

ModuleRevision 1.1.4

address

Bit(s)

Module Description
Reserved

5

Reserved

HDMI

4

HDMI PCLKHDMI

3HDMI interrupt synchronization

MISC

2

AHB control bus

MISC

1

AHB data bus

0

Reserved

31

Video clock enable

30

Reserved

29

Reserved

28

Reserved

27

Reserved

VENC

26

VCLK2_OTHER

VENC

25

VCLK2_VENCL

VENC

24

VCLK2_VENCLMMC Clock All

23

Reserved

VENC

22

gclk_vencl_int

PERIPH

21

Random Number Generator

VENC

20

ENC480P

19

Reserved

18

Reserved

17

Reserved

16

IEC958_GATE

15

Reserved

14

AOCLK_GATE

13

Reserved

12

Reserved

11

Reserved

VENC

10

DAC_CLKVENC

9gclk_vencp_int

8gclk_venci_int

7

Reserved

6

Reserved

5

Reserved

4

VCLK2_VENCP

VENC

3

VCLK2_VENCP

VENC

2

VCLK2_VENCI for venc_i_top other normal function

VENC

1

VCLK2_VENCI for venc_i_top BIST function

0

Reserved

ne
dk
er
ar
H
to

tr
ib

AIU

e

AIU

ut

EDP

0x54

l

6

VENC

D

is

VENC

59/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

22.4 Register Description
Each register’s final address = 0xC883C000 + offset * 4
SCR System Clock ReferenceBit(s)
31-0

R/W
R/W

0x0B

Default
0

TIMEOUT_VALUE: Program timer
Bit(s)
15-12
11-0

R/W
R
R/W

Default
00

Description
System clock reference high: Bits 31:16

0x0F
Description
UnusedProgram timerlIncreased by 1 every 900 cycles. Triggers timer interrupt to CPU when it expires.

HHI_GP0_PLL_CNTL3

HHI_GP0_PLL_CNTL4
Bit(s)
31~26
25~24
23~16
15~4
3
2
1
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

dk
er
H
to

Description
DPLL_LM_W
DPLL_LM_S
DPLL_DPFD_LMODE
DC_VC_IN
DCO_SDMCK_SEL
DCO_M_EN
Reserved
Reserved
AFC_DSEL_BYPASSAFC_DSEL_IN
Reserved

0x12

Default
0
0
0
0
0

is

R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0
0
0
0

D

Bit(s)
31~30
29~26
25~22
21~11
10~0

0x11

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

e

Bit(s)
31~28
27~22
21
20~19
18~17
16
15
14
13
12
11~0

Description
LOCK
ENABLERESETReserved
OD
ReservedN
M

ut

HHI_GP0_PLL_CNTL2

Default
0
0
0
0
0
0
0
0

ar

R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W

tr
ib

Bit(s)
31
30
29
28~18
17~16
15~14
13~9
8~0

ne

HHI_GP0_PLL_CNTL 0x10

Description
Reserved
FILTER_PVT2
FILTER_PVT1
FILTER_ACQ2
FILTER_ACQ1

0x13
Default
0
0
0
0
0
0
0
0

Description
Reserved
DCO_IUP
TDC_BUFREVE
PVT_FIX_EN
DCO_SDM_EN
IIR_BYPASS_N
TDC_EN

60/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Default
00x384

Description
Unused90khz divider

0x40

15~8
7~4
3~2
1~0

R/W
R/W
R/W
R/W

Default
0xFFFFF
FFF
0xFF
0xF
0x3
0x3

HHI_VPU_MEM_PD_REG0:

D

Description
Reserved
Deinterlacer – di_post: 11 = power down. 00 = normal operation
Deinterlacer – di_prePicture rotation3
Picture rotation2
Picture rotation1
Vdin1 memory
Vdin0 memory
Osd_scaler
Scaler memory
Vpp output fifo
Color management module
Vd2 memory
Vd1 memory
Osd2 memory
Osd1 memorytrib

HHI_VPU_MEM_PD_REG1:
R/W
R/W
R/W
R/W
R/W
R/W

HDMI memory PD
Reserved
Ethernet memory PD
Reserved

0x41

Default
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3

is

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Description
Reserved

ar

R/W
R/W

H

Bit(s)
31~16

Bit(s)
31~30
29~28
27~26
25~24
23~22

dk
er

0x3B
R/W
R/W
R/W

HHI_MEM_PD_REG0

Bit(s)
31~30
29~28
27~26
25~24
23~22
21~20
19~18
17~16
15~14
13~12
11~10
9~8
7~6
5~4
3~2
1~0

l

Description
reserved
gpioCLK_3_xtal
gpioCLK_3_xtal_2
reserved
reserved
gpioCLK_2_xtal_2
gpioCLK_2_xtal
reserved
gpioCLK_1_fclk_div2
gpioCLK_1_xtal_2
gpioCLK_1_xtal
reserved
Fclk_div2_gclk_en
Fclk_div2_tcnt

toBit(s)
31-16
15-0

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0

e

HHI_TIMER90K

0x2f

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

ut

Bit(s)
31~20
19
18
17
16
15
14
13
12
11
10
9
8
7~0

ne

HHI_XTAL_DIVN_CNTL

0x42

Default
0x3
0x3
0x3
0x3
0x3

Description
Reserved
Reserved
ISP memory: 11 = power down. 00 = normal operation
CVBS inci interface
Panel encl top

61/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
21~20
19~18
17~16
15~14
13~12
11~10
9~8
7~6
5~4
3~2
1~0

Revision 1.1.4

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3

Description
Hdmi encp interface
Reserved
Reserved
Reserved
VIU2 OSD scaler
VIU2 scaler
VIU2 VPP
VIU2 color management
VIU2 VD1
VIU2 OSD2
VIU2 OSD1

Default
0
0
0
0
0
0
0
0
0
0

Description
DAC0_CLK_SEL
DAC1_CLK_SEL
DAC2_CLK_SEL
Select adc_pll_clk_b2 to be cts_clk_vdac
UnusedV2_cntl_clk_div_reset
V2_cntl_clk_div_en
Encl_clk_sel
UnusedV2_cntl_xd0

HHI_GCLK_MPEG0 0x50
R/W
R/W

ne
dk
er

H

Description
UnusedV2_cntl_clk_en0
V2_cntl_clk_in_sel
V2_cntl_soft_reset
UnusedV2_cntl_div12_en
V2_cntl_div6_en
V2_cntl_div4_en
V2_cntl_div2_en
V2_cntl_div1_en

Default
0

Description
Bits [31:0] of the composite MPEG clock gating register

Default
0

Description
Bits [63:32] of the composite MPEG clock gating register

Default
0

Description
Bits [63:32] of the composite MPEG clock gating register

Default
0

Description
Bits [31:0] of the composite Other clock gating registerisBit(s)
31-0

Default
0
0
0
0
0
0
0
0
0
0

to

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

e

Bit(s)
31-20
19
18-16
15
14-5
4
3
2
1
0

0x4b

ut

HHI_VIID_CLK_CNTL

ar

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

tr
ib

Bit(s)
31-28
27-24
23-20
19
18
17
16
15-12
14-8
7-0

l

HHI_VIID_CLK_DIV 0x4a

D

HHI_GCLK_MPEG1 0x51
Bit(s)
31-0

R/W
R/W

HHI_GCLK_MPEG2 0x52
Bit(s)
31-0

R/W
R/W

HHI_GCLK_OTHER 0x54
Bit(s)
31-0

R/W
R/W

HHI_GCLK_AO 0x55

62/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
31-8
7-5
4
3
2
1
0

Revision 1.1.4

R/W
R
R/W
R/W
R/W
R/W
R/W
R/W

HHI_SYS_OSCIN_CNTL

Description
Unusedunusedi2c
Always On Register logic
Always on general clock in the always on domain
AHB SRAMAO CPU

0x56

R/W
R
R/W
R/W

Default
01
0x7FFF

Description
UnusedPadu_sys_osc_en
Xtal_source_en[14:0]

0x57

R/W
R/W
R/W

Default
0
0

22:20

R/W

0

19
18

R/W
R/W

0
0

17
16

R/W
R/W

0
0

15
14~12
11~9

R/W
R/W
R/W

0
0
0

8~6
5~3

R/W
R/W

0
0

Description
Reserved
A53_trace_clk _DIS: Set to 1 to manually disable the A53_trace_clk when changing the mux selection. TypicallyThis bit is set to 0 since the clock muxes can switch without glithces. This is a “just in case” bit
A53_trace_clk:
1. A53 clock divided by 2
2. A53 clock divided by 3
3. A53 clock divided by 4
4. A53 clock divided by 5
5. A53 clock divided by 6
6. A53 clock divided by 7
7. A53 clock divided by 8Har

Bit(s)
31-24
23

dk
er

HHI_SYS_CPU_CLK_CNTL1nel

Bit(s)
31-16
15
14-0

Default
0
0x7
1
1
1
1
1

to

AXI_CLK_DIS: Set to 1 to manually disable the AXI clock when changing the mux selection. Typically This bit is set
to 0 since the clock muxes can switch without glithces. This is a “just in case” bit

e

ut

tr
ib

is

D
2
1
0

R/W
R/W
R/W

0
0
0

HHI_SYS_CPU_RESET_CNTL
Bit(s)
31-11
10
9

R/W
R/W
R/W
R/W

APB_CLK_DIS: Set to 1 to manually disable the APB clock when changing the mux selection. Typically This bit is
set to 0 since the clock muxes can switch without glithces. This is a “just in case” bitReserved
Reserved
AXI_CLK _MUX:
8. A53 clock divided by 2
9. A53 clock divided by 3
10. A53 clock divided by 4
11. A53 clock divided by 5
12. A53 clock divided by 6
13. A53 clock divided by 7
14. A53 clock divided by 8
Reserved
APB_CLK _MUX:
1. A53 clock divided by 2
2. A53 clock divided by 3
3. A53 clock divided by 4
4. A53 clock divided by 5
5. A53 clock divided by 6
6. A53 clock divided by 7
7. A53 clock divided by 8
Soft_reset
Div16_en
Pclk_en_dbg

0x58

Default000Description
Reserved
Cpu_axi_reset
nPRESETDBG

63/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
8
7-4
3-0

Revision 1.1.4

R/W
R/W
R/W
R/W

Default000Description
nL2RESETnCORERESET[3:0]
Cpu_soft_reset[3:0]Default
0
0
0
0
0
0
0
0

Description
ENCI_CLK_SEL
ENCP_CLK_SEL
ENCT_CLK_SEL
UNUSED
CLK_DIV_RESET
CLK_DIV_EN
XD1
XD0

0x5d

R/W
R/W

Default
0

30~16
15

R/W
R/W

0
0

14-12
11-10
9

R.W
R/W
R.W

6
0
0

8

R/W

0

7

R/W

1

6-0

R/W

0

7-0

ar

H

to

0x5e
Default
0
0
0
0
0
0
0

1

Description
UnusedAudio DAC clock select (See clock document)
Audio DAC Clock enable
Audio DAC Clock divider
UnusedAMCLK_SRC_SEL: (see clock tree document)
PLL Clock Enable. Set This bit to 1 to enable the PLL to the rest of the logic. To avoid glitching state machinesinside the chip please change the PLL using the following sequence:
Set Bit[8] = 0 to block the logic from the PLL
set the PLL using register 0x15b and wait for the PLL to settle (1mS)
Set Bit[8] = 1 to enable the PLL driving all of the logic
PLL Output divider. The Audio System clock equals the video PLL clock frequency divided by (N+1).

Default
0
0
0
0
0
0
0

Description
TCON_CLK0_CTRL
CLK_EN1
CLK_EN0
CLK_IN_SEL
SOFT_RESET
PH23_ENABLE
DIV12_PH23

is

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

D

Bit(s)
31-26
25-24
23
22-16
15-11
10-9
8

MPEG_CLK_SEL (See clock document)
unusedRTC Oscillator Enable: Set This bit to 1 to connect the RTC 32khz oscillator output as the XTAL input for the divider
above
Divider Mux: 0 = the ao cpu clock and the MPEG system clock are connected to the 27Mhz crystal. 1 = the ao
cpu clock and the MPEG system clock are connected to the MPEG PLL divider
PLL Mux: 0 = all circuits associated with the MPEG PLL are connected to 27Mhz. 1 = all circuits associated with
the MPEG PLL are connected to the MPEG PLLPLL Output divider. The MPEG System clock equals the video PLL clock frequency divided by (N+1). Note: N must
be odd (1,3,5,….) so that the MPEG clock is divided by an even number to generate a 50% duty cycle.

trib

HHI_AUD_CLK_CNTL

R/W

Description
NEW_DIV_EN: If This bit is set to 1, then Bits[30:16] make up the clk81 divider. If This bit is 0, then Bits[6:0]dictate the divider value. This is a new feature that allows clk81 to be divided down to a very slow frequency.
NEW_DIV: New divider value if Bit[31] = 1
Production clock enabledkerBit(s)
31e

HHI_MPEG_CLK_CNTL

ne

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

ut

Bit(s)
31-28
27-24
23-20
19-18
17
16
15-8
7-0

l

HHI_VID_CLK_DIV 0x59

HHI_VID_CLK_CNTL 0x5f
Bit(s)
31-21
20
19
18-16
15
14
13

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

64/336AMLOGIC, Inc. Proprietary

S905 Datasheet

R/W
R/W
R/W
R/W
R/W
R/W
R/W

Bit(s)
31~24
23~20
19
18
17~16

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

R/W
R
R/W
R/W
R/W
R/W

Description
Final_mux_sel
Final_dyn_mux_sel
Busy_cnt
busy
Dyn_enable
Mux1_divn_tcnt
Postmux1
Premux1
Manual_mux_mode
Manual_mode_post
Manual_mode_preForce_update_t
Final_mux_sel
Final_dyn_mux_sel
mux0_divn_tcnt
Rev
Postmux0
Premux0

tr
ib

D

HHI_VID_PLL_CLK_DIV

Reserved
Atv demod vdac gated clock control
LCD_AN_CLK_PHY2 gated clock control. 1 = enable
LCD_AN_CLK_PH3 gated clock control
HDMI_TX_PIXEL_CLK gated clock control
VDAC_clk gated clock control
ENCL gated clock control
ENCP gated clock control
ENCT gated clock control
ENCI gated clock control

0x67

is

R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Description

ar

Default
0
0
0
1
1
1
1
1
1
1
1

H

R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

dk
er

0x65

HHI_SYS_CPU_CLK_CNTL0
Bit(s)
31
30
29
28
26
25-20
18
17-16
15
14
13
12
11
10
9-4
3
2
1-0

Description
UnusedIEC958_USE_CNTL: If This bit is set to 1, then Bits[26;16] are used as the IEC958 clock divider
IEC958_CLK_SRC_SEL. See the clock tree document
IEC958_CLK_DIV.
ReservedlDefault
0
0
0
0
0

to

HHI_VID_CLK_CNTL2
Bit(s)
31-16
15-9
8
7
6
5
4
3
2
1
0

0x64

R/W
R/W
R/W
R/W
R/W
R/W

e

Bit(s)
31-28
27
26-25
23-16
15-0

Description
UNUSEDDIV12_EN
DIV6_EN
DIV4_EN
DIV2_EN
DIV1_ENne

HHI_AUD_CLK_CNTL2

Default
0
0
0
0
0
0

ut

Bit(s)
12-5
4
3
2
1
0

Revision 1.1.4

0x68
Default000
00Description
RESERVED
Reserved
CLK_FINAL_EN
CLK_DIV1
CLK_SEL

65/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
15
14-0

Revision 1.1.4

R/W
R/W
R/W

HHI_AUD_CLK_CNTL3

Default
00

Description
SET_PRESETSHIFT_PRESET

0x69

R/W
R/W
R/W

Default
0
0

16
15-0

R/W
R/W

0
0

Description
UnusedPdm_clk_src_sel:
0:cts_amclk
1:mp0_clk_out
2:mp1_clk_out
3:mp2_clk_out
Pdm_clk_en
Pdm_clk_div

HHI_MALI_CLK_CNTL

Description
Reserved
CLK_SEL: See the Clock Tree document for information related to cts_mali _clk
CLK_EN: See the Clock Tree document for information related to cts_ mali _clk
Reserved
CLK_DIV: See the Clock Tree document for information related to cts_ mali _clk

R/W
R/W
R/W
R/W

0
0
0
0

CLK_SEL: See the Clock Tree document for information related to cts_mali _clk
CLK_EN: See the Clock Tree document for information related to cts_ mali _clk
Reserved
CLK_DIV: See the Clock Tree document for information related to cts_ mali _clk

H

ar

dk
er

Default
0
0
0
0
0

0x6f

R/W
R/W
R/W
R/W

0
0
0
0

Description
Final mux sel
Reserved
TVFE MCLK EN
CLK_SEL: See the Clock Tree document for information related to cts_vpu_clk
CLK_EN: See the Clock Tree document for information related to cts_vpu_clk
Reserved
CLK_DIV: See the Clock Tree document for information related to cts_vpu_clk

toDefault
0
0
0
0
0
0
0

e

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

ut

HHI_VPU_CLK_CNTL

CLK_SEL: See the Clock Tree document for information related to cts_vpu_clk
CLK_EN: See the Clock Tree document for information related to cts_vpu_clk
Reserved
CLK_DIV: See the Clock Tree document for information related to cts_vpu_clk

isBit(s)
31
30-29
28
27~25
24
23
22~16
15~12
11~9
8
7
6-0

0x6c

R/W
R/W
R/W
R/W
R/W
R/W

tr
ib

Bit(s)
31-28
27~25
24
23
22~16
15~12
11~9
8
7
6-0

ne

l

Bit(s)
31-29
18:17

0x73

D

HHI_HDMI_CLK_CNTL
Bit(s)
31-20
19~16
15~11
10~9
8
7
6-0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

HHI_VDEC_CLK_CNTL
Bit(s)
31-28
27~25

R/W
R/W
R/W

Default
0
0
0
0
0
0
0

Description
Reserved
crt_hdmi_pixel_clk_sel
Reserved
CLK_SEL: See the Clock Tree document for information related to cts_hdmi_sys_clk
CLK_EN: See the Clock Tree document for information related to cts_hdmi_sys_clk
Reserved
CLK_DIV: See the Clock Tree document for information related to cts_hdmi_sys_clk

0x78
Default
00

Description
Reserved
CLK_SEL: See the Clock Tree document for information related to cts_hcodec_clk

66/336AMLOGIC, Inc. Proprietary

S905 Datasheet

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default000
00Description
Reserved
HEVC_CLK_SEL: See the Clock Tree document for information related to cts_vdec2_clk
HEVC_CLK_EN: See the Clock Tree document for information related to cts_vdec2_clk
Reserved
HEVC_CLK_DIV: See the Clock Tree document for information related to cts_vdec2_clk

R/W
R/W
R/W
R/W

0
0
0
0

VDEC2_CLK_SEL: See the Clock Tree document for information related to cts_vdec2_clk
VDEC2_CLK_EN: See the Clock Tree document for information related to cts_vdec2_clk
Reserved
VDEC2_CLK_DIV: See the Clock Tree document for information related to cts_vdec2_clk

dk
er

ar

Default
0

Description
See the clock tree document. This register controls the Alternate clock for cts_vdec_clk and cts_hcodec_clk

H

Bit(s)
31-0

0x7a

R/W
R/W

HHI_VDEC4_CLK_CNTL

ne

R/W
R/W
R/W
R/W
R/W
R/W

HHI_VDEC3_CLK_CNTL
Bit(s)
31~0

0x79

0x7b

R/W
R/W

Default
0

Description
See the clock tree document. This register controls the Alternate clock for cts_vdec2_clk and cts_hevc_clk

toBit(s)
31-28
27~25
24
23
22~16
15~12
11~9
8
7
6-0

Description
CLK_EN: See the Clock Tree document for information related to cts_hcodec_clk
Reserved
CLK_DIV: See the Clock Tree document for information related to ctshcodec_clk
Reserved
CLK_SEL: See the Clock Tree document for information related to cts_vdec_clk
CLK_EN: See the Clock Tree document for information related to cts_vdec_clk
Reserved
CLK_DIV: See the Clock Tree document for information related to cts_vdec_clk

HHI_HDCP22_CLK_CNTL 0x7c
Default
0
0

24
23-0

R/W
R/W

0
0

is

HHI_VAPBCLK_CNTL

Description
Reserved
Clk_sel:0:cts_oscin_clk
1:fclk_div4
2:fclk_div3
3:fclk_div5
Clk_enClk_div

ut

R/W
R/W
R/W

tr
ib

Bit(s)
31-0
26-25

l

HHI_VDEC2_CLK_CNTL

Default
0
0
0
0
0
0
0
0

e

Bit(s)
24
23
22~16
15~12
11~9
8
7
6-0

Revision 1.1.4

0x7d

R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0

24
23

R/W
R/W

0
0

D

Bit(s)
31
30
29-28
27-25

Description
Final_mux_sel
EnableReserved
Mux1_sel:
0:fclk_div4
1:fclk_div3
2:fclk_div5
3:fclk_div7
4:mp1_clk_out
5:vid_pll_clk
6:mp2_clk_out
7:gp0_pll_clk
Mux1_enReserved

67/336AMLOGIC, Inc. Proprietary

S905 Datasheet

R/W
R/W
R/W
R/W
R/W
R/W
R/W

HHI_VPU_CLKB_CNTL
Bit(s)
31-9
8
7-0

Default
0
0
0
0
0
0

Description
Mux1_div
Reserved
Mux0_sel,as mux1_sel
Mux0_enReserved
Mux0_div

0x83

R/W
R/W
R/W
R/W

Default000Description
Reserved
Vpu_clkb_en
Vpu_clkb_div

Description
Reserved
Usb_clk_sel:
0:cts_oscin_clk
1:rtc_oscin_i
Usb_clk_en
Usb_clk_divlBit(s)
22-16
15-12
11-9
8
7
6-0

Revision 1.1.4

R/W
R/W
R/W

Default
0
0

9
8-0

R/W
R/W

0
0

dk
er

Bit(s)
31-0
11-10

ne

HHI_USB_CLK_CNTL 0x88

15
14
13-0

R/W
R/W
R/W

0
0
0

Default
0
0
0

D
11
10~0

R/W
R/W

ut

R/W
R/W
R/W
R/W

is

Bit(s)
31-17
16
15~12

0x8a

Description
Reserved
OSCIN GATE CLK ENABLE
CLK_SEL:
0:cts_oscin_clk
1:rtc_oscin_i
2:sys_cpu_clk_div16
3:ddr_dpll_pt_clk
4:vid_pll_clk
5:vid2_pll_clk
6:mp0_clk_out
7:mp1_clk_out
8:mp2_clk_out
9:fclk_div4
10:fclk_div3
11:fclk_div5
12:cts_msr_clk
13:fclk_div7
14:gp0_pll_clk
CLK_EN: See the Clock Tree document for information related to gen_clk_out
CLK_DIV: See the Clock Tree document for information related to gen_clk_out

trib

HHI_GEN_CLK_CNTL

Description
Reserved
Hi_32k_clk_sel:
0:cts_oscin_clk
1:cts_slow_oscin_clk
2:fclk_div3
3:fclk_div5
Hi_32k_clk_en
Reserved
Hi_32k_clk_div

H

Default
0
0

to

R/W
R/W
R/W

e

Bit(s)
31-0
17-16

ar

HHI_32K_CLK_CNTL 0x89

0068/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

HHI_PCM_CLK_CNTL

0x96

Clock control for cts_pcm_mclk and cts_pcm_sclk
Bit(s)
31-23
22
21-16
15-12
11-10
9
8-0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

HHI_NAND_CLK_CNTL

Default
0
0
0
0
0
0
48

Description
unused
CLK_EN: See the Clock Tree document for information related to cts_pcm_sclk
CLK_DIV: See the Clock Tree document for information related to cts_pcm_sclk
Unused
CLK_SEL: See the Clock Tree document for information related to cts_pcm_mclk
CLK_EN: See the Clock Tree document for information related to cts_pcm_mclk
CLK_DIV: See the Clock Tree document for information related to cts_pcm_mclk

0x97

0
48

0x99

R/W
R/W
R/W

Default
0
0

24
23
22-16
15-12
11-9

R/W
R/W
R/W
R/W

0
48
0
0

8
7
6-0

R/W
R/W

0
48

Description
unusedSd_emmc_B_CLK_SEL:
0:cts_oscin_clk
1:fclk_div2
2:fclk_div3
3:fclk_div5
4:fclk_div7
5:mp2_clk_out
6:mp3_clk_out
7:gp0_pll_clk
Reserved
Sd_emmc_B_CLK_EN:
Sd_emmc_B_CLK_DIV
Reserved
Sd_emmc_A_CLK_SEL:
0:cts_oscin_clk
1:fclk_div2
2:fclk_div3
3:fclk_div5
4:fclk_div7
5:mp2_clk_out
6:mp3_clk_out
7:gp0_pll_clk
Reserved
Sd_emmc_A_CLK_EN:
Sd_emmc_A_CLK_DIV

D

is

tr
ib

ut

Bit(s)
31-28
27-25

e

HHI_SD_EMMC_CLK_CNTL

ne

R/W
R/W

dk
er

8
7
6-0

Description
unused
CLK_SEL:
0:cts_oscin_clk
1:fclk_div2
2:fclk_div3
3:fclk_div5
4:fclk_div7
5:mp2_clk_out
6:mp3_clk_out
7:gp0_pll_clk
Reserved
CLK_EN:
CLK_DIVar

Default
0
0

H

R/W
R/W
R/W

to

Bit(s)
31-12
11-9

l

Clock control for cts_pcm_mclk and cts_pcm_sclk

69/336AMLOGIC, Inc. Proprietary

S905 Datasheet

HHI_MPLL_CNTL

0xa0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0
0
0
0

Description
MPLL_LOCKMPLL_ENABLE. 1 = enable
MPLL_RESET
Reserved
DDS0_P_SET
DDS0_SSEN
DDS0_F_SET
Reserved
MPLL_OD
UnusedMPLL_N
MPLL_M

Default
0
0
0
0
0
0
0
0
0
0
0

Description
LM_W
LM_S
DPFD_LMODE
VC_IN
SDMCK_SEL
DCO_M_EN
SDM_PR_EN
DIV_MODE
AFC_DSEL_BYPASSAFC_DSEL_IN
DPLL_DIV_FRAC

Default000
00Description
RESERVEDFILTER_PVT2
FILTER_PVT1
FILTER_ACQ2
FILTER_ACQ1

nel

Bit(s)
31
30
29
28~18
28-26
25
24-20
19~18
17-16
15-14
13-9
8-0

Revision 1.1.4

R/W
R/W
R/W
R/W
R/W
R/W

HHI_MPLL_CNTL4 0xa3

Default
0
0
0
0
0
0
0
0
0
0
0

Description
REVE
TDC_BUF
TDC_CAL_EN
PVT_FIX_EN
DCO_IUP
SS_AMP
SS_CLKSSEN
DCO_SDM_EN
IIR_BYPASS_EN
TDC_EN

Default00
00Description
DPLL_BGP_C
VR_FB2
VR_FB1
DDS_VC_VDD

is

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

D

Bit(s)
31~24
23~16
15
14
13~12
11~8
7~4
3
2
1
0

ar
H

tr
ib

Bit(s)
31~30
29~26
25~22
21~11
10~0

ut

HHI_MPLL_CNTL3 0xa2

to

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

e

Bit(s)
31-28
27~22
21
20~19
18~17
16
15
14
13
12
11-0

dk
er

HHI_MPLL_CNTL2 0xa1

HHI_MPLL_CNTL5 0xa4
Bit(s)
31~28
27~26
25~24
23~22

R/W
R/W
R/W
R/W
R/W

70/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
21
20
19~17
16~14
13
12
11~10
9~8
7
6~5
4~2
1-0

Revision 1.1.4

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0
0
0
0
0

Description
DDS_LDO_RUPSELDDS_ENLDOTEST_CRESERVED
IRSEL
MP_OD
TDC_OFF_C
TDO_NC_SEL
TDO_CLK_SEL
TDC_CAL_PG
TDC_CAL_OFF
TDC_CAL_IG

Default
0
0
0
0
0
0
0
0
0
0

Description
CKEN[3:0]
CKEN[4]
SYS_DPLL_BGP_EN
SYS_DPLL_EXLDO
VREF_CS2
VREF_CF2
VREF_CS1
VREF_CF1
VREF_CS0
VREF_CF0

ne
dk
er
ar

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

H

Bit(s)
31~28
27
26
25~24
23~20
19~16
15~12
11~8
7~4
3~0

l

HHI_MPLL_CNTL6 0xa5

Description
IR_BYPASS0
MODLSEL0
IR_BYIN0
LP_EN0
N_IN0
SDM_EN0
EN_DDS0
SDM_IN0e

Default
0
0
0
0
0
0
0
0

ut

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

tr
ib

Bit(s)
31
30
29~26
25
24~16
15
14
13~0

to

HHI_MPLL_CNTL7 (MP0) 0xa6

HHI_MPLL_CNTL8 (MP1) 0xa7

Default
0
0
0
0
0
0
0
0

is

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

D

Bit(s)
31
30
29~26
25
24~16
15
14
13~0

Description
IR_BYPASS1
MODLSEL1
IR_BYIN1
LP_EN1
N_IN1
SDM_EN1
EN_DDS1
SDM_IN1

HHI_MPLL_CNTL9 (MP2) 0xa8
Bit(s)
31
30
29~26
25
24~16
15
14

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0

Description
IR_BYPASS2
MODLSEL2
IR_BYIN2
LP_EN2
N_IN2
SDM_EN2
EN_DDS2

71/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
13~0

Revision 1.1.4

R/W
R/W

HHI_MPLL_CNTL10 (MP2)
Bit(s)
31-13
12
11-8
7~0

R/W
R/W
R/W
R/W
R/W

Default
0

Description
SDM_IN2

0xa9
Default00
00Description
Reserved
Mpll_clk25M_en
Mpll_clk_out_div3_en
Mpll_clk_out_div2_en

Default
0
0
0
0
0
0

Description
MPLL_IR_BYIN3
MPLL_SDM_IN3
MPLL_SDM_EN3
MPLL_N_IN3
MPLL_MODELSEL3
MPLL_EN_DDS3

Default000
00Description
Reserved
MPLL_LP_EN3
MPLL_IR_BYPASS3
MPLL_VREF_CS3
MPLL_VREF_CF3

Default
0
0
0
0
0
0
0
0

Description
CDAC_BIAS_C
CDAC_EXT_VREF_EN
CDAC_DRIVER_ADJ
CDAC_CLK_PHASE_SEL
CDAC_RL_ADJ
CDAC_VREF_ADJ
CDAC_CTRL_RESV2
CDAC_CTRL_RESV1

Default00
00Description
CDAC_DIG_OUT_RESVReserved
Cdac_pwd
CDAC_GSW

Default
0-

Description
RESERVED
GP1_AFC_DONE
Reserved
GP0_AFC_DONE
MPLL_IR_DONE2
MPLL_IR_DONE1
MPLL_IR_DONE0
MPLL_IR_OUT2
MPLL_IR_OUT1
MPLL_IR_OUT0

ne

R/W
R/W
R/W
R/W
R/W
R/W
R/W

dk
er

Bit(s)
31-28
25-12
11
10~2
1
0

l

HHI_MPLL3_CNTL0 0xb8

R/W
R/W
R/W
R/W
R/W
R/W

H

Bit(s)
31~10
9
8
7-4
3-0

ar

HHI_MPLL3_CNTL1 0xb9

HHI_VDAC_CNTL1 0xbe
R/W
R
R
R/W
R/W

HHI_DPLL_TOP_I

0xc6

Bit(s)
31-22
21
20
19
18
17
16
15~12
11~8
7~4

R/W
R
R
R
R
R
R
R
R
R
R

D

is

Bit(s)
23~16
15~4
3
2~0

e

ut

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

tr
ib

Bit(s)
27
26
25
24
23~21
20~16
15~8
7~0

to

HHI_VDAC_CNTL0 0xbd

72/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
3
2
1
0

Revision 1.1.4

R/W
R
R
R
R

Default
0-

Description
RESERVEDMPLL_TDC_CAL_DONE
SYS_TDC_CAL_DONE
SYS_AFC_DONE

Default
0

Description
MPLL_DPLL_OUT_RSVSYS_DPLL_OUT_RSV
Reserved
MPLL_IR_DONE3
MPLL_IR_OUT3
GP0_DPLL_OUT_RSV

HHI_DPLL_TOP2_I 0xc7
R/W
R
R
R
R
R
R

-

HHI_HDMI_PLL_CNTL

nelBit(s)
31-24
23-16
15-13
12
11-8
7~0

0xc8

HHI_HDMI_PLL_CNTL2

Description
Lock
EnableReserved
RESET
ReservedN
M = VLOCK_CNTL_EN ? vpu_hdmi_top.m_int_pll : (this register)ar

Default
0
0
0
0
0
0
0

H

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0xc9

to

Bit(s)
31
30
29
28
27~14
13~9
8~0

dk
er

There is some internal muxing controlled by “VLOCK_CNTL_EN” Bit[20] of HHI_HDMI_PLL_CNTL6.

There is some internal muxing controlled by “VLOCK_CNTL_EN” Bit[20] of HHI_HDMI_PLL_CNTL6.

e

Description
DSEL_IN
DSEL_BYPASSReserved
OD[3:2]
Reserved
OD2
OD[1:0]Reserved
DIV_MODE
Reserved
DIV_FRAC = VLOCK_CNTL_EN ? vpu_hdmi_top.m_frac_pll : (this register)ut

Default
0
0
0
0
0
0
0
0
0
0
0

is

tr
ib

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

D

Bit(s)
31
30
29~24
23~22
21~20
19~18
17~16
15
14
13~12
11~0

HHI_HDMI_PLL_CNTL3
Bit(s)
31-29
28~18
17~7
6
5~4
3~2
1
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

HHI_HDMI_PLL_CNTL4

0xca
Default
0
0
0
0
0
0
0
0

Description
Reserved
FILTER_ACQ2
FILTER_ACQ1
DPFD_LMODE
DC_VC_IN
DCO_SDMCK_SEL
DCO_M_EN
SDM_PR_EN

0xcb

73/336AMLOGIC, Inc. Proprietary

S905 Datasheet

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

HHI_HDMI_PLL_CNTL6
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W

ne
dk
er

0xcd
Default
0
0
0
0
0
0
0

Description
Reserved
Reserved
VLOCK_CNTL_EN: See HHI_HDMI_PLL_CNTL above,1: have VPU_VLOCK module to control the M/N setting of PLL
CNEW
OUT_GATE_CTRL
Reserved
HDMI_DPLL_BGP_C

trib

Bit(s)
31-28
27~21
20
19~12
11~10
9-4
3~0

Description
Reserved
VID2_DPLL_BGP_EN
REVE
TDC_OFF_C
TDC_NC_SEL
TDC_CLK_SEL
TDC_CAL_PG
TDC_CAL_OFF
TDC_CAL_IG
TDC_CAL_EN
PVT_FIX_EN
TDC_BUFar

Default
0
0
0
0
0
0
0
0
0
0
0
0

H

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

l

0xcc

to

Bit(s)
31
30
29~22
21~20
19~18
17
16~15
14~12
11~10
9
8
7~0

Description
DCO_IUP
SS_AMP
SS_CLKSSEN
DCO_SDM_EN
IIR_BYPASSTDC_EN
LM_W
LM_S
FILTER_PVT2
FILTER_PVT1

e

HHI_HDMI_PLL_CNTL5

Default
0
0
0
0
0
0
0
0
0
0
0

ut

Bit(s)
31~30
29~26
25~22
21
20
19
18
17~14
13~8
7~4
3~0

Revision 1.1.4

HHI_HDMI_PLL_CNTL_I 0xce

Default
0

is

R/W
R
R
R
R

0
0

D

Bit(s)
31-12
11~4
3~1
0

HHI_HDMI_PLL_CNTL7
Bit(s)
31-18
17-16
15-0

R/W
R
R
R

Description
Reserved
DPLL_OUT_RSV
Reserved
AFC_DONE

0xcf
Default000Description
Reserved
HDMI_DPLL_EXLDOHDMI_DPLL_RSV

HHI_HDMI_PHY_CNTL0 0xe8
Bit(s)
31~16
15~0

R/W
R/W
R/W

Default
00

Description
HDMI_CTL1
HDMI_CTL0

HHI_HDMI_PHY_CNTL1 0xe9

74/336AMLOGIC, Inc. Proprietary

S905 Datasheet

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0
0
0
0
0
0

Description
Reserved
BIT_INVERTMSB_LSB_SWAP
Reserved
CAPTURE_CLK_GATE_EN
HDMI_TX_PRBS_EN: Set to 1 to enable the PRBS engine
HDMI_TX_PRBS_ERR_EN: Set to 1 to enable the error flag detector. Set to 0 to reset the error detection logic
HDMI_TX_SET_HIGH: Set Each Bit to 1 to set the HDMI pin high
HDMI_TX_SET_LOW: Set Each Bit to 0 to set the HDMI Pins low
HDMI_FIFO_WR_ENALBE
HDMI_FIFO_ENABLE
HDMI_TX_PHY_CLK_EN: Set to 1 to enable the HDMI TX PHYHDMI_TX_PHY_SOFT_RESET: Set to 1 to reset the HDMI TX PHY

nel

Bit(s)
31~18
17
16
15
14
13
12
11~8
7~4
3
2
1
0

Revision 1.1.4

HHI_HDMI_PHY_CNTL2 0xea
R/W
R
R
R

Default000Description
Reserved
Test error
HDMI_REGRD

dker

Bit(s)
31~9
8
7~0

HHI_HDMI_PHY_CNTL3 0xeb

R/W
R/W
R/W

Default
0
0

7
6-0

R/W
R/W

0
0

0xf5

tr
ib

HHI_BT656_CLK_CNTL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0

8
7
6-0

R/W
R/W
R/W

0
0
0

is

Bit(s)
31~27
26-25
24
23
22-16
15-11
10-9

D

Description
reserved
Clk_sel:0:cts_oscin_clk
1:cts_encl_clk
2:cts_enci_clk
3:cts_encp_clk
Clk_enClk_div

H

0xf2

Bit(s)
31~10
9-8

to

HHI_VID_LOCK_CLK_CNTL

Description
RSV

arDefault
0

e

R/W
R/W

ut

Bit(s)
31~0

Description
Reserved
Bt656_2_clk_sel, the same as bt656_1_clk_sel
Reserved
Bt656_2_clk_en
Bt656_2_clk_div
Reserved
Bt656_1_clk_sel
0:fclk_div2
1:fclk_div3
2:fclk_div5
3:fclk_div7
Reserved
Bt656_1_clk_en
Bt656_1_clk_div

HHI_SAR_CLK_CNTL 0xf6
Bit(s)
31~11
10-9

R/W
R/W
R/W

Default
00

Description
Reserved
Clk_sel:0:cts_oscin_clk

75/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Bit(s)

R/W

Default

8
7-0

R/W
R/W

0
0

l
ne
dk
er
ar
H
to

Description
MIPI
mmc
Vcbus_clk81
Ahb_data
Ahb_cntl
Cbus_capb3
Sys_cpu_capb3
Dos_capb3
Mali_capb3
Hdmitx_capb3
Nand_capb3
Capb3_decode
Gic
Reserved
Reservedvcbus
AFIFO2ASSIST
VENC
PMUX
Reserved
Vid_pll_div
AIU
VIU
DCU_RESETDDR_TOP
DOS_RESET
Reserved
HIU

eDefault
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0xc11004408

D

is

RESET1_REGISTER

0xc11004404
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

tr
ib

Bit(s)
31-28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

ut

RESET_REGISTER

Description
1:clk81
Clk_enClk_div

76/336AMLOGIC, Inc. Proprietary

S905 Datasheet

is

RESET3_REGISTER
Bit(s)
15
14
13
12
11
10
9
8
7
6

Description
Hdmi system reset
MALI
AO CPU RESET
Reserved
Reservedparser_top
parser_ctl
Paser_fetch
Parser_reg
GE2D
Reserved
Reserved
Reserved
HDMI_TX
AUDIN
VD_RMEM

l
ne
dk
er
ar

e

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

to

0xc1100440c
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

D

Bit(s)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Description
Reserved
Sys_cpu_mbist
Sys_cpu_p
Sys_cpu_l2
Sys_cpu_axi
Sys_pll_div
Sys_cpu_core[3:0]
Sys_cpu[3:0]
Rom_boot
Sd_emmc_c
Sd_emmc_b
Sd_emmc_a
Ethernet
ISA
BLKMV (NDMA)PARSER
Reserved
AHB_SRAM
BT656
AO Reset
DDR
USB_OTG
DEMUX
Cppm

ut

RESET2_REGISTER

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

H

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

tr
ib

Bit(s)
31-29
28
27
26
25
24
23-20
19-16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Revision 1.1.4

0xc11004410

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0
0
0

Description
Demux reset 2
Demux reset 1
Demux reset 0
Demux S2P 1
Demux S2p 0
Demux DES
Demux top
Audio DAC
ReservedAHB BRIDGE CNTL

77/336AMLOGIC, Inc. Proprietary

S905 Datasheet

R/W
R/W
R/W
R/W
R/W
R/W
R/W

0xc11004414

RESET6_REGISTER
Bit(s)
15
14
13
12
11
10
9
8

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

is

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

l
ne
dk
er
to

0xc1100441c

D

Bit(s)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Description
I2C_Master 1
I2C_Master 2
VENCL
VDI6
Reserved
RTC
VDAC
Reserved
VENCP
VENCI
RDMA
DVIN_RESET
Reserved
Reserved
Reserved
Reserved
MISC PLL
DDR PLL

Description
Uart_slip
PERIPHS: SDHCPERIPHS: SPI 0
PERIPHS: Async 1
PERIPHS: Async 0
PERIPHS: UART 1, 2
PERIPHS: UART 0
PERIPHS: SDIOPERIPHS: Stream Interfacee

RESET6_REGISTER

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

ar

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

ut

Bit(s)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0

Description
tvfe
AIFIFO
Sys_cpu_bvci
EFUSE
SYS CPU
Ring oscillator

H

RESET4_REGISTER

Default
0
0
0
0
0
0

tr
ib

Bit(s)
54
3
2
1
0

Revision 1.1.4

SANA
PERIPHS: I2C Master 0
PERIPHS: SAR ADC
PERIPHS: Smart CardPERIPHS: SPICCPERIPHS: General

0xc11004420
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0

Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A9_dmc_pipel

78/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
7
6
5
4
3~0

Revision 1.1.4

R/W
R/W
R/W
R/W
R/W
R/W

Default000
00Description
vid_lockReserved
Device_mmc_arb
Reserved
Usb_ddr[3:0]

RESET0_MASK 0xc11004440
The Bits of this register correspond to the RESET[n] REGISTERs above. If a bit is set in this register, then when the watchdog
timer fires, that particular module will NOT be reset.
RESET1_MASK 0xc11004444

nel

The Bits of this register correspond to the RESET[n] REGISTERs above. If a bit is set in this register, then when the watchdog
timer fires, that particular module will NOT be reset.
RESET2_MASK 0xc11004448

dker

The Bits of this register correspond to the RESET[n] REGISTERs above. If a bit is set in this register, then when the watchdog
timer fires, that particular module will NOT be reset.
RESET3_MASK 0xc1100444c

ar

The Bits of this register correspond to the RESET[n] REGISTERs above. If a bit is set in this register, then when the watchdog
timer fires, that particular module will NOT be reset.
RESET4_MASK 0xc11004450

to

H

The Bits of this register correspond to the RESET[n] REGISTERs above. If a bit is set in this register, then when the watchdog
timer fires, that particular module will NOT be reset.
RESET5_MASK 0xc11004454

RESET6_MASK 0xc11004458

ute

The Bits of this register correspond to the RESET[n] REGISTERs above. If a bit is set in this register, then when the watchdog
timer fires, that particular module will NOT be reset.

trib

The Bits of this register correspond to the RESET[n] REGISTERs above. If a bit is set in this register, then when the watchdog
timer fires, that particular module will NOT be reset.
RESET7_MASK 0xc1100445c

Dis

The Bits of this register correspond to the RESET[n] REGISTERs above. If a bit is set in this register, then when the watchdog
timer fires, that particular module will NOT be reset.

AO_RTI_GEN_CTNL_REG0 0xC8100040

79/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Description
Reserved
IR_BLASTER_RESETUART2_RESET
Reserved
I2C_SLAVE_RESET: Set to 1 to reset
I2C_MASTER_RESET: Set to 1 to reset
UART_MODULE_RESET: Set to 1 to reset
IR_MODULE_RESET: Set to 1 to reset
Reserved
Reserved
IR_BLASTER clock gate: 1 = clock enabled
UART2 module clock gate
Reserved
UART module clock gate
I2C slave module clock gate
I2C master module clock gate
IR remote decoder clock gatelDefault
0
0
0
0
0
0
0
0
0xFF
1
1
1
1
1
1
1
1

ne

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

dk
er

Bit(s)
31-24
23
22
21:20
19
18
17
16
15-8
7
6
5
4
3
2
1
0

Revision 1.1.4

23. GPIO
23.1 Overview

Har

The SOC has a number of multi-function digital I/O pads that can be multiplexed to a number of internal resources (e.g. PWM
generators, SDIO controllers …). When a digital I/O is not being used for any specific purpose, it is converted to a general
purpose GPIO pin. A GPIO pin can be statically set to high/low logical levels. The structure of a GPIO is given below.

Built-in pull-up
resistore

Input Level:
To Software read back& interrupt controller

toFigure III.23.1. GPIO Structure

Digital I/O pad

ut

Output level:
From Software control

Built-in pulldown resistor

trib

Output Enable:
From Software control

DisEach GPIO pin has an individual control bitthat can be used to set the output level, output enable of the I/O pad (0 = output, 1= input). Additionally all digital I/O pads have built-in pull-up and pull-down resistors. The input from the digital I/O pad canbe read back in software and is also connected to an interrupt controller. The interrupt controller allows up to 8 GPIO pins to
be used as active high, active low, rising edge or falling edge interrupts.
Finally, the GPIO’s are grouped into voltage domains. Some GPIOs (depending on the PCB design) can be configured to operate
between 0 and 1.8v while others may operate between 0.0v and 3.3v.

23.2 GPIO Multiplex Function
The GPIO multiplex functions are shown in the sections below, where the RegNN[MM] corresponds to CBUS registers definedin Table III. 23.1
Table III.23.1 Pin Mux Registers
Pin Mux Registers

Abbreviation

Offset80/336

Default Valueafter power-on/Reset

AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

REG0
REG1
REG2
REG3
REG4
REG5
REG6
REG7
REG8
REG9
AO_REG
AO_REG2

0xc88344b0
0xc88344b4
0xc88344b8
0xc88344bc
0xc88344c00xc88344c4
0xc88344c8
0xc88344cc
0xc88344d0
0xc88344d4
0xc8100014
0xc8100018

0x00000x00000x00000x00000x00000x00000x00000x00000x00000x00000x00000x0000

D

is

tr
ib

ut

e

to

H

ar

dk
er

ne

l

PERIPHS_PIN_MUX_0
PERIPHS_PIN_MUX_1
PERIPHS_PIN_MUX_2
PERIPHS_PIN_MUX_3
PERIPHS_PIN_MUX_4
PERIPHS_PIN_MUX_5
PERIPHS_PIN_MUX_6
PERIPHS_PIN_MUX_7
PERIPHS_PIN_MUX_8
PERIPHS_PIN_MUX_9
AO_RTI_PIN_MUX_REG
AO_RTI_PIN_MUX_REG2

81/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Table III.23.2 GPIOX Pin Multiplexing Table
Package Name

Func1

Func2

Func3

Func4

Func5

TSin_D_VALID_B
reg3[9]TSin_SOP_B
reg3[8]
TSin_CLK_B
reg3[10]
TSin_D0_B
reg3[7]

PWM_A
reg3[17]
PWM_F
reg3[18]

GPIOX_1
GPIOX_2
GPIOX_3
GPIOX_4
GPIOX_5
GPIOX_6

SDIO_IRQ
Reg8[11]
ISO7816_CLK
reg4[7]
ISO7816_DATA
reg4[6]GPIOX_8
GPIOX_9

PCM_OUT_A
Reg3[30]
PCM_IN_A
Reg3[29]
PCM_FS_A
Reg3[28]
PCM_CLK_A
Reg3[27]
SLIP_UART_TX
reg4[17]
SLIP_UART_RX
reg4[16]
SLIP_UART_CTS
reg4[15]
SLIP_UART_RTS
reg4[14]dk
er

GPIOX_7

GPIOX_10

GPIOX_13
GPIOX_14
GPIOX_15

PWM_E
reg2[30eto

GPIOX_19
GPIOX_20
GPIOX_21

H

UART_TX_A
Reg4[13]
UART_RX_A
Reg4[12]
UART_CTS_A
Reg4[11]
UART_RTS_A
Reg4[10]
UART_RTS_B
Reg2[22]ar

GPIOX_11
GPIOX_12

ne

GPIOX_0l

SDIO_D0
Reg8[5]
SDIO_D1
Reg8[4]
SDIO_D2
Reg8[3]
SDIO_D3
Reg8[2]
SDIO_CLK
Reg8[1]
SDIO_CMD
Reg8[0]GPIOY_0
GPIOY_1
GPIOY_2

is

GPIOY_3

D

GPIOY_4
GPIOY_5
GPIOY_6
GPIOY_7
GPIOY_8
GPIOY_9

GPIOY_10
GPIOY_11
GPIOY_12
GPIOY_13

Func1

Func2

DVP_HS_A
reg2[19]
DVP_VS_A
reg2[18]
DVP_CLK_A
reg2[17]
DVP_D2_A
reg2[16]
DVP_D3_A
reg2[16]
DVP_D4_A
reg2[16]
DVP_D5_A
reg2[16]
DVP_D6_A
reg2[16]
DVP_D7_A
reg2[16]
DVP_D8_A
reg2[16]
DVP_D9_A
reg2[16]

TSin_D_VALID_A
reg3[2]
TSin_SOP_A
reg3[1]
TSin_CLK_A
reg3[0]
TSin_D0_A
reg3[4]
TSin_D1_A
reg3[5]
TSin_D2_A
reg3[5]
TSin_D3_A
reg3[5]
TSin_D4_A
reg3[5]
TSin_D5_A
reg3[5]
Tsin_D6_A
reg3[5]
TSin_D7_A
reg3[5]
TSin_FAIL_A
reg3[3]trib

Package Nameut

Table III.23.3 GPIOY Pin Multiplexing Table
Func3

Func4

Func5
I2S_AO_CLK_IN
reg1[0]I2S_LR_CLK_IN
reg1[1]I2SIN_CH67
reg1[2]
ISO7816_CLK
reg1[12]
ISO7816_DATA
reg1[13]

UART_CTS_C
reg1[19]
UART_RTS_C
reg1[18]
UART_TX_C
reg1[17]82/336I2SIN_CH45
reg1[3]
I2SIN_CH23
reg1[4]I2SOUT_CH23
reg1[5]I2SOUT_CH45
reg1[6]I2SOUT_CH67
reg1[7]
SPDIF_IN
reg1[8]
SPDIF_OUT
reg1[9]
DMIC_IN
reg1[10]AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Package Name

Func1

Func2

Func3

Func4

Func5

UART_RX_C
reg1[16]GPIOY_14
DVP_D0_A
reg2[20]
DVP_D1_A
reg2[21]GPIOY_15
GPIOY_16

DMIC_CLK_OUT
reg1[11]
CLKOUT
reg1[22]

PWM_F
reg1[20]
PWM_A
reg1[21]

Table III.23.4. GPIOZ Pin Multiplexing Table

GPIOZ_4
GPIOZ_5
GPIOZ_6
GPIOZ_7
GPIOZ_8
GPIOZ_9
GPIOZ_10
GPIOZ_11
GPIOZ_12
GPIOZ_13l

DVP_CLK_B
reg5[7]
DVP_D2_B
reg5[4]
DVP_D3_B
reg5[4]
DVP_D4_B
reg5[4]
DVP_D5_B
reg5[4]
DVP_D6_B
reg5[4]
DVP_D7_B
reg5[4]
DVP_D8_B
reg5[4]
DVP_D9_B
reg5[4]ne

GPIOZ_3

GPIOZ_14

SPI_SCLK
reg5[27]
SPI_SS0
reg5[26]

ISO7816_CLK
reg4[9]
ISO7816_Data
reg4[8]

SPI_MISO reg5[28]SPI_MOSI reg5[29]GEN_CLK_OUT
reg6[15]ut

e

GPIOZ_15

Func4

dk
er

GPIOZ_2

Func3

ar

GPIOZ_1

Func2
DVP_VS_B
reg5[5]
DVP_HS_B
reg5[6]H

GPIOZ_0

Func1
ETH_MDIO
reg6[1]
ETH_MDC
reg6[0]
ETH_CLK_RX_CLK
reg6[13]
ETH_RX_DV
reg6[12]
ETH_RXD0
reg6[11]
ETH_RXD1
reg6[10]
ETH_RXD2
reg6[9]ETH_RXD3
reg6[8]
ETH_RGMII_TX_CLK
reg6[7]
ETH_TX_EN
reg6[6]
ETH_TXD0
reg6[5]
ETH_TXD1
reg6[4]
ETH_TXD2
reg6[3]
ETH_TXD3
reg6[2]

to

Package Name

Func2

Func3

DVIN_VS
reg0[12]
DVIN_HS
reg0[11]
DVIN_CLK
reg0[10]
DVIN_DEreg0[9]

TCON_STV1
reg5[12]
TCON_STH1
reg5[11]
TCON_CPH
reg5[10]
TCON_OEH
reg5[9]

Table III.23.5 GPIO Bank DV Pin Multiplexing Table

Func1

tr
ib

Package NameLCD_VS
reg0[7]
LCD_HS
reg0[6]GPIODV_24
GPIODV_25

GPIODV_27

TCON_VCOM
reg5[8]D

GPIODV_28

is

GPIODV_26

Func4

PWM_VS
reg3[22]

GPIODV_29

Func5

Func6

UART_TX_B
reg2[29]
UART_RX_B
reg2[28]
UART_CTS_B
reg2[27]
UART_RTS_B
reg2[26]
PWM_D
reg3[20]
PWM_B
reg3[21]I2C_SDA_A
reg7[26]
I2C_SCK_A
reg7[27]
I2C_SDA_B
reg7[24]I2C_SCK_B
reg7[25]
I2C_SDA_C
reg7[22]I2C_SCK_C
reg7[23]

Table III.23.6 GPIO Bank H Pin Multiplexing Table
Package Name
GPIOH_0
GPIOH_1
GPIOH_2

Func1
HDMI_HPD
reg1[26]
HDMI_SDA
reg1[25]
HDMI_SCL
reg1[24]

GPIOH_3

83/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Table III.23.7 GPIO Bank CLK Pin Multiplexing Table
Package Name

Func1

Func2

GPIOCLK_0

CLK24

CLK12(wifi)

GPIOCLK_1

CLK25

pwm_F

Table III.23.8. GPIO Bank AO Pin Multiplexing Table

GPIOAO_2
GPIOAO_3
GPIOAO_4
GPIOAO_5
GPIOAO_6
GPIOAO_7

REMOTE_INPUT
ao_reg[0]I2S_AO_CLK_IN
default
I2S_LR_CLK_IN
default

H

GPIOAO_10
GPIOAO_11

RESET_N

EE_CEC
ao_reg[14]SPDIF_OUT
ao_reg[4]toTEST_NRESET_N

PWM_AO_A
ao_reg[22]I2C_SCK_AO
ao_reg[6]I2C_SDA_AO
ao_reg[5]PWM_AO_A
ao_reg[18]I2C_SLAVE_SCK_AO
ao_reg[2]I2C_SLAVE_SDA_AO
ao_reg[1]SPDIF_OUT
ao_reg[16]JTAG_TCK
See *1-jtag_sel
JTAG_TMS
See *1-jtag_sel
JTAG_TDI
See *1-jtag_sel
JTAG_TDO
See *1-jtag_sel
PWM_AO_A
ao_reg[17]PWM_AO_B
ao_reg[3]PWM_F
ao_reg[19]I2S_AM_CLK
ao_reg[30]I2S_AO_CLK_OUT
ao_reg[29]I2S_LR_CLK_OUT
ao_reg[28]
I2SOUT_CH01
ao_reg[27]
I2SOUT_CH23
ao_reg2[0]I2SOUT_CH45
ao_reg2[1]
I2SOUT_CH67
ao_reg2[2]uteGPIOAO_13

AO_CEC
ao_reg[15]
REMOTE_OUTPUT
ao_reg[31]

GPOAO_12

Func4

ar

GPIOAO_8
GPIOAO_9

Func3l

GPIOAO_1

Func2
UART_TX_AO_B
ao_reg[26]UART_RX_AO_B
ao_reg[25]UART_CTS_AO_B
ao_reg[8]UART_RTS_AO_B
ao_reg[7]UART_TX_AO_B
ao_reg[24]UART_RX_AO_B
ao_reg[25]I2S_IN_01
default
REMOTE_OUTPUT
ao_reg[21]ne

GPIOAO_0

Func1
UART_TX_AO_A
ao_reg[12]UART_RX_AO_A
ao_reg[11]UART_CTS_AO_A
ao_reg[10]UART_RTS_AO_A
ao_reg[9]dkerPackage Nametr
ib

Table III.23.9 GPIO Bank BOOT Pin Multiplexing Table

Package Name

Func1

BOOT_0D

is

BOOT_1
BOOT_2
BOOT_3
BOOT_4
BOOT_5
BOOT_6
BOOT_7
BOOT_8
BOOT_9

BOOT_10
BOOT_11
BOOT_12

NAND_CE0
reg4[26]
NAND_CE1
reg4[27]
NAND_RB0
reg4[25]
NAND_ALE
reg4[24]
NAND_CLE
reg4[23]

Func2

Func3

EMMC_NAND_D0
reg4[30]
EMMC_NAND_D1
reg4[30]
EMMC_NAND_D2
reg4[30]
EMMC_NAND_D3
reg4[30]
EMMC_NAND_D4
reg4[30]
EMMC_NAND_D5
reg4[30]
EMMC_NAND_D6
reg4[30]
EMMC_NAND_D7
reg4[30]
EMMC_CLK
reg4[18]

EMMC_CMD
reg4[19]
NOR_D
reg5[1]
NOR_Q
reg5[3]84/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Package Name

Func1

Func2

NAND_WEN_CLK
reg4[22]
NAND_REN_WR
reg4[21]
NAND_DQS
reg4[20]

BOOT_13
BOOT_14
BOOT_15

Func3
NOR_C
reg5[2]

EMMC_DS
reg4[31]

NOR_CS
reg5[0]

Table III.23.10 GPIO Bank CARD Pin Multiplexing Table

CARD_2
CARD_3
CARD_4
CARD_5

Func3

Func4
JTAG_TDI
See *1-jtag_sel
JTAG_TDO
See *1-jtag_sel
JTAG_CLKSee *1-jtag_sel
JTAG_TMS
See *1-jtag_sel

UART_TX_AO_A
reg8[10]
UART_RX_AO_A
reg8[17]

D

is

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ib

ut

e

to

H

ar

CARD_6

UART_RX_AO_A
reg8[18]
UART_TX_AO_A
reg8[9]l

CARD_1

Func2

ne

CARD_0

Func1
SDCARD_D1
reg2[14]SDCARD_D0
reg2[15]SDCARD_CLK
reg2[11]
SDCARD_CMD
reg2[10]SDCARD_D3
reg2[12]SDCARD_D2
reg2[13]dk
er

Package Name

85/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

23.3 GPIO Interrupt
There are 8 independent filtered GPIO interrupt modules that can be programmed to use any of the GPIOs in the chip as aninterrupt source (listed in the table below). For example, to select boot_3 as the source for GPIO IRQ #0, then CBUS 0x2621
Bits[7:0] = 27 (according to the table below).
Table III.23.11 GPIO Interrupt Sources
Input Mux Location
CBUS registers 0x2621 and 0x2622
255~133
132~129128~106
105~89
88~59
58~52
51~34
33~30
29~14
13 ~ 0Description

dk
er

ne

l

Undefined (no interrupt)
gpioCLK[3:0]
gpioX[22:0]
gpioY[16:0]
gpioDV[29:0]
Card[6:0]
Boot[17:0]
gpioH[3:0]
gpioZ[15:0]
gpioAO[13:0]

ar

The diagram below illustrates the path a GPIO takes to become an interrupt. The eight GPIO interrupts respond to the MASK,STATUS and STATUS/CLEAR registers just like any other interrupt in the chip. The difference for the GPIO interrupts is that they
can be filtered and conditioned. Filtering can either be bypassed or enabled so that a GPIO must be high or low for [3n] * 125nS,
where n = 1, 2, …, 7.

Polarity

0

tr
ib

255

GPIO
IRQ #3

See
table
above

0

is

CBUS 0x2621 bits[31:24]

D

GPIO
IRQ #0CBUS
0x2620bit[23]

Edge SelectCBUS
0x2623bits[30:28]

CBUS 0x2620
bit[7]

bit[7]

bit[3]
bit[0]

Polarity

FilterEdge SelectCBUS
0x2620bit[19]CBUS
0x2623bits[14:12]

CBUS 0x2620
bit[3]

Polarity

FilterEdge SelectCBUS
0x2620bit[16]CBUS
0x2623bits[2:0]

CBUS 0x2620
bit[0]

255

See
table
above

CBUS 0x2621 bits[7:0]Filtere

CBUS 0x2622 bits[31:24]

to

See
table
above

ut

GPIO
IRQ #7

CBUS 0x2618, 0x2619

bit[8]

255

IRQ IN2 Status / clear

bit[31]

CBUS 0x261a

Other IRQ_IN2
Interrupts

IRQ IN2 Mask

H

Fig III.23.2 GPIO Interrupt Path0

NOTE: The input for the GPIO interrupt module (the input into the 256:1 mux) comes directly from the I/O pad of the chip.
Therefore if a pad (say card_6) is configured as a UART TX pin, then in theory, the UART TX pin can be a GPIO interrupt since
the TX pin will drive card_6 which in turn can drive the GPIO interrupt module.

86/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

23.4 Register Description
Table III.23.11 and Table III.23.12 shows the information of GPIO related registers.
Table III.23.11 GPIO Register Infromation I
Final address = 0xc8834400 + offset * 4IN(Read Only)

GPIOX_22~00x18
Bit[22:0]

0x19
Bit[22:0]

0x1aBit[22:0]

GPIOY_16~0

0x0F
Bit[16:0]

0x10
Bit[16:0]

0x11
Bit[16:0]

GPIODV_29~0

0x0C
Bit[29:0]

0x0D
Bit[29:0]

0x0E
Bit[29:0]

GPIOH_3~0

0x0F
Bit[23:20]

0x10
Bit[23:20]

0x11
Bit[23:20]

BOOT_17~00x12
Bit[17:0]

0x13
Bit[17:0]

0x14
Bit[17:0]

CARD_6~00x12
Bit[26:20]

0x13
Bit[26:20]

0x14
Bit[26:20]

CLK_3~00x15
Bit[31:28]

0x16
Bit[31:28]

0x17
Bit[31:28]

PU/PD-EN(Read Write)
0x4c
Bit[22:0]
0x49
Bit[16:0]
0x48
Bit[29:0]
0x49
Bit[23:20]]
0x4aBit[17:0]
0x4aBit[26:20]
0x4bBit[31:28]

PU/PD(Read Write)
0x3e
Bit[22:0]0x3bBit[16:0]
0x3aBit[29:0]0x3bBit[23:20]
0x3c
Bit[17:0]0x3c
Bit[26:20]
0x3d
Bit[31:28]

IO Type
Tri-State
Tri-State
Tri-Statel

OUT(Write Only)

Tri-Statene

OEN(Read Write)dk
erPackage
Name

Tri-State
Tri-State
Tri-Statear

Table III.23.12 GPIO Register Information II
Final address = 0xc8100000 + offset * 4
OEN(Read Write)

OUT(Write Only)

IN(Read Only)

GPIOAO_13~00x09
Bit[13:0]

0x09
Bit[29:16]

0x0a
Bit[13:0]

PU/PD-EN(Read Write)
0x0b
Bit[13:0]

PU/PD(Read Write)
0x0b
Bit[29:16]

IO Type
Tri-State

D

is

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to

H

PackageName

87/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

24. Interrupt Control
24.1 Overview
Generic Interrupt Controller (GIC) is a centralized resource that supports and manages interrupts in a system. For more details
about GIC, please refer to the ARM GIC Architecture Specification V2.0.

24.2 Interrupt Source
There are 224 interrupt sources in the chip. All of the interrupts are connected to the integrated GIC in Cortex-A53 while the
AO-CPU see a sub-set of the interrupts. The control Bits of AO-CPU interrupt are listed in the following table.

Description
unused254

1'b0unused253

1'b0

unused252

1'b0

unused251

1'b0

unused250

sd_emmc_C_irq

249

sd_emmc_B_irq

248

sd_emmc_A_irq

247

m_i2c_2_irq

246

m_i2c_1_irq

245

mbox_irq_send5

244

mbox_irq_send4

243

mbox_irq_send3

242

mbox_irq_receiv2

241

mbox_irq_receiv1

240

mbox_irq_receiv0

239

1'b0

238

ao_timerA_irq

237

1'b0

236

ao_watchdog_irq

ar
H
e

to
unusedis

ao_gpio_irq0
ao_cec_irq

D229

unusedao_gpio_irq1

233

230

ut

1'b0

234

231

unusedao_jtag_pwd_fast_irq

235

232

ne

Interrupt sources
1'b0

dk
er

255

tr
ib

A53 GIC BitlTable III.24.1 EE Interrupt Source

ao_ir_blaster_irq
ao_uart2_irq

228

ao_ir_dec_irq

227

ao_i2c_m_irq

226

ao_i2c_s_irq

225

ao_uart_irq

224

1'b0

unused223

1'b0

unused222

1'b0

unused221

1'b0unused220

1'b0unused219

1'b0

unused88/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Interrupt sources
vp9dec_irq

Description
unused217

1'b0

unused216

1'b0

unused215

1'b0

unused214

1'b0unused213

1'b0

unused212

1'b0

unused211

mali_irq_ppmmu7

210mali_irq_pp7

209

mali_irq_ppmmu6

208

mali_irq_pp6

207

mali_irq_ppmmu5

206

mali_irq_pp5

205

mali_irq_ppmmu4

204mali_irq_pp4

203

mali_irq_ppmmu3

202

mali_irq_pp3

201

mali_irq_ppmmu2

200mali_irq_pp2

199

mali_irq_ppmmu1

198

mali_irq_pp1

197

mali_irq_ppmmu0196mali_irq_pp0

195

mali_irq_pmu

194

mali_irq_pp

193

mali_irq_gpmmu

192

mali_irq_gp

COMMIRQ3

188

COMMIRQ2

187

COMMIRQ1

isviu1_line_n_irq
1'b0

D

180

ne

PMUIRQ2

184

181

dk
er

PMUIRQ3

185

182

ar
H

COMMIRQ0

186

183

ut

189

tr
ib

EXTERRIRQ

e

191
190

l

218

to

A53 GIC Bit

ge2d_irq
cusad_irq

179

asssit_mbox_irq3

178

asssit_mbox_irq2

177

asssit_mbox_irq1

176

asssit_mbox_irq0

175

det3d_int

174

1'b0

173

VCPUMNTIRQ3172

VCPUMNTIRQ2171

VCPUMNTIRQ1

89/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Interrupt sources
VCPUMNTIRQ0169

PMUIRQ1

168

PMUIRQ0

167

1'b0

166

1'b0

165

1'b0

164

1'b0

163

1'b0

162

ctiirq3

161

ctiirq2

160

ctiirq1

127

ctiirq0

Description

l

170

ne

A53 GIC Bit

126
1'b0

unused124

uart3_slip_irq

UART slip

123

uart2_irq

UART 2122

1'b0

unused121

1'b0

unused120

1'b0

unused119

rdma_done_int

RDMA

118

I2S_cbus_ddr_irq

Audio I2S CBUS IRQ

117

1'b0

unused116

vid1_wr_irq

115

vdin1_vsync_int

114

vdin1_hsync_int

113

vdin0_vsync_int

112

vdin0_hsync_int

111

spi2_int

110

spi_int109

vid0_wr_irq

108

1'b0

107

1'b0

106

ar

H
to
e

ut

tr
ib
1'b0

dk
er

125

unusedunusedunuseduart1_irq

105

1'b0

is

104

unusedSAR ADC

1'b0

unusedgpio_irq[7]GPIO Interrupt

gpio_irq[6]GPIO Interrupt

99

gpio_irq[5]GPIO Interrupt

98

gpio_irq[4]GPIO Interrupt

97

gpio_irq[3]GPIO Interrupt

96

gpio_irq[2]GPIO Interrupt

95

gpio_irq[1]GPIO Interrupt

94

gpio_irq[0]GPIO Interrupt

92

TimerI

TimerI

91

TimerH

TimerH

102
101
100

D

sar_adc_irq

103

93

90/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

90Interrupt sources
TimerG

Description
TimerG

89

TimerF

TimerF88

1'b0

unused87

hdcp22_irq

86

hdmi_tx_interrupt

85

1'b0

84

hdmi_cec_interrupt

83

1'b0

82

demux_int_2

81

dmc_irq80

dmc_sec_irq

79

ai_iec958_int

IEC958 interrupt

78

iec958_ddr_irq

IEC958 DDR interrupt

77

I2S_irq

I2S DDR Interrupt

76

crc_doneFrom AIU CRC done75

deint_irq

Reserved for Deinterlacer74

dos_mbox_slow_irq[2]DOS Mailbox 273

dos_mbox_slow_irq[1]DOS Mailbox 1

72

dos_mbox_slow_irq[0]DOS Mailbox 0

71

1'b0

unused70

1'b0unused69

1'b0

unused68

m_i2c_3_irq

67

1'b0

66

smartcard_irq

65

ndma_irq

64

spdif_irq

63

nand_irq

62

viff_empty_int_cpu

61parser_int_cpu

60
59
58
57

53
52

l
ne

dk
er

ar

H

Block MoveetounusedUSB

U3h_interrupt

USB

Timer D

Timer Disbus_mon0_fast_irq
uart0_irq

D54

I2C Master #3

bus_mon1_fast_irq

56
55

unusedtrib

U2d_interrupt

unusedut

A53 GIC Bit

async_fifo2_flush_irq
async_fifo2_fill_irq

51demux_int

50

encif_irq49

m_i2c_0_irq

48bt656_irq

47

async_fifo_flush_irq

46

async_fifo_fill_irq

45bt656_2_rq

bt656_B44

1'b0

unused43

1'b0unused91/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Interrupt sources
eth_lip_intro_o

Description

42
41

1'b0

unused40

1'b0unused39

Timer B

Timer B

38

Timer A

Timer A37

1'b0

unused36

eth_gmac_int

35

audin_irq

34

Timer C33

demux_int_1

32

eth_pmt_intr_oTimer Cnel

A53 GIC Bit

dker

24.3 Register Description
Each register’s final address = 0xC1100000 + offset * 4

GPIO Interrupt EDGE and Polarity: 0x2620

Default
0

R/W
R
R/W

0
0

6
5
4
3
2
1
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W

Description
unusedGPIO_POLARITY_PATH_7: If a bitin this field is 1, then the GPIO signal for GPIO interrupt path 7 is inverted.
GPIO_POLARITY_PATH_6:
GPIO_POLARITY_PATH_5:
GPIO_POLARITY_PATH_4:
GPIO_POLARITY_PATH_3:
GPIO_POLARITY_PATH_2:
GPIO_POLARITY_PATH_1:
GPIO_POLARITY_PATH_0:
UnusedGPIO_EDGE_SEL_PATH_7: If a bit is set to 1, then the GPIO interrupt for GPIO path 7 is configured to be anedge generated interrupt. If the polarity (above) is 0, then the interrupt is generated on the rising edge. If
the polarity is 1, then the interrupt is generated on the falling edge of the GPIO. If a bit is this field is 0, thenthe GPIO is a level interrupt.
GPIO_EDGE_SEL_PATH_6
GPIO_EDGE_SEL_PATH_5
GPIO_EDGE_SEL_PATH_4
GPIO_EDGE_SEL_PATH_3
GPIO_EDGE_SEL_PATH_2
GPIO_EDGE_SEL_PATH_1
GPIO_EDGE_SEL_PATH_0

H

R/W
R

tr
ib

is

D

GPIO 0 ~ 3 Pin Select:

ut

e

to

Bit(s)
31-24
23
22
21
20
19
18
17
16
15-8
7

ar

This register controls the polarity of the GPIO interrupts and whether or not the interrupts are level or edge triggered. There
are 8 GPIO interrupts. These 8 GPIO interrupts can be assigned to any one of up to 256 pins on the chip.

0

0x2621Each GPIO interrupt can select from any number of up to 256 GPIO pins on the chip. The Bits below control the pin selection
for GPIO interrupts 0 ~3.
Bit(s)
31-24
23-16
15-8

R/W
R/W
R/W
R/W

Default000Description
GPIO_PIN_SEL3: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 3
GPIO_PIN_SEL2: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 2
GPIO_PIN_SEL1: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 1

92/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
7-0

Revision 1.1.4

R/W
R/W

GPIO 4 ~ 7 Pin Select:
Bit(s)
31-24
23-16
15-8
7-0

Default
0

Description
GPIO_PIN_SEL0: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 00x2622

R/W
R/W
R/W
R/W
R/W

Default00
00Description
GPIO_PIN_SEL7: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 7
GPIO_PIN_SEL6: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 6
GPIO_PIN_SEL5: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 5
GPIO_PIN_SEL4: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 4

GPIO Filter Select (interrupts 0~7): 0x2623

dk
er

ne

l

Description
unusedFILTER_SEL7: (see FILTER_SEL0)
UnusedFILTER_SEL6: (see FILTER_SEL0)
UnusedFILTER_SEL5: (see FILTER_SEL0)
UnusedFILTER_SEL4: (see FILTER_SEL0)
UnusedFILTER_SEL3: (see FILTER_SEL0)
UnusedFILTER_SEL2: (see FILTER_SEL0)
UnusedFILTER_SEL1: (see FILTER_SEL0)
unusedFILTER_SEL0: This value sets the filter selection for GPIO interrupt 0. A value of 0 = no filtering. A value of 7
corresponds to 7 x 3 x (111nS) of filtering.

ar

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

H

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

to

Bit(s)
31
30-28
27
26-24
23
22-20
19
18-16
15
14-12
11
10-8
7
6-4
3
2-0

e

25. DIRECT MEMORY ACCESS CONTROLLER (DMAC)

ut

25.1 Overview

is

tr
ib

The DMA controller is an engine connected to the DDR controller for the purposes of moving data to/from DDR memory. The
DMA controller supports 4 independent threads. Each thread is driven by DMA table descriptors placed in DDR memory. Each
DMA descriptor consists of 8 entries that describe the source/destination location as well as the stride and burst. Inline
processing is also supported to allow data from DDR to be processed using an AES, Triple-DES, CRC, or SHA module before
being placed back into DDR memory.

D

25.2 Descriptor Table
Below is the descriptor Table.

1
2
3
4
5

8

7

NO Break

INLINE TypeIRQ

Dest Hold

DmatabPre Endian

Source Hold

Owner ID

0

Table III.25.1 Descriptor Table

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
( 01=system, 10=DMA engine,
00=no woner)

Entry

6

5

4

3

2

1

0

Thread Slice Count(0 = use default slice)
Number of 256-byte blocks toallocate to this thread

SP: Source Pointer (AHB address)
DP: Destination Pointer (AHB address) (0xFFFFFFFF = send data to the parser)
Byte transfer countSource Skip
Source Burst Count
Destination Skip
Destination Burst Count

93/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Mode

Encrypt

CTR
Limit

CTR Endian

Reset IV

6-AES
Type

IN
EndianOUT Endian

restart

6-TDES

dk
er

Mode

Last blk

6-SHA

ne

l

CRC Countrestartnowrite

6-CRC

Post EndianH

ar

6-OTHERSIN
Endian25.3 Register Description

toThe following registers’ final address = 0xda832000 + offset*4
SEC_BLKMV_GEN_REG0 0x24

Description
ddr_secure_id
ddr_non_sec_val
ddr_sec_val1
ddr_sec_val0
sec_read_sel
non_sec_mask: 1 = a thread is non-secure
sec_ddr_sec_id_en: Even though a thread is secure, we may not want it to use the DDR secure ID (JIC)
ddr_thread_id[5:2]: 2-bit below used for securityeDefault
‘h0
‘h0
‘h0
‘h0
‘h0
‘hF
‘h0
‘h0

ut

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

tr
ib

Bit(s)
31-20
19-18
17-16
15-14
13-12
11-8
7-4
3-0

27-24
23-20
19-18
17-16
15-12
11-8
7
6
5-4
3
2
1
0

R/W
R
R/W
R/W

Default‘h0‘h0DBit(s)
31
30
29-28

is

SEC_BLKMV_AES_REG0 0x00

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

‘h0
‘hF
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0

Description
aes_key_valid: read-back signal of aes_key_valid
Reserved
aes_pio_ctr_limit: pio mode CTR limit: Counter set up of counter mode (CTR): 00 = 128-bit Counter in CTR mode, 01 =32 bit counter, 10 = 64-bit counter. 11 = 128-bit counter
aes_pio_ctr_endian: pio mode CTR endian: Endian set up of counter mode (CTR)
Reserved
aes_pio_type: pio mode aes type: 00 = 128, 01 = 192, 10 = 256, 11 = reserved
aes_pio_mode: pio mode aes mode: 00 = ECB mode, 01 = CBC mode, 10 = CTR mode, 11 = reserved
aes_pio_out_endian: pio mode aes out endian: Endian control of the outgoing message
aes_pio_in_endian: pio mode aes in endian: Endian control of the incoming message
aes_pio_encrypt: pio mode aes encrypt sel: 0 = decrypt, 1 = encrypt
aes_get_key_sim: Paused for simulation checking only
aes_key_iv_thread:
aes_use_sec_thread: used for woftware simulation/debug and PIO mode
Reserved
aes_pio_init_IV: (manual mode). Write with a 1 then a 0 to manually initialize the IV when running in PIO mode.
aes_clk_en_jic: backup enable and also used when the CPU needs to load keys/IV values into the save/restore engine

94/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

SEC_BLKMV_TDES_KEY_LO 0x08
The Triple DES engine maintains up to 4 IV keys used for CBC processing. The following three registers are used to setup andwrite the IV keys to an internal memory. Because each IV key is 64 Bits, the key must be written to an internal register before
a 3rd register write is used to push the stored IV key into the internal RAM.
Writing this register sets the IV key Bits [31:0] of the register to be written to the RAM. Reading this register returns the current
IV value for processing. This is useful if Cipher Block Chaining must be interrupted. Software can read the current IV key andrestore it later to continue processing.
Bit(s)31-0

R/W
W

Default‘h0

Description
sec_sr_tdes_key_IV_in[31:0]: secure lower 32 bits of tdes_sr_key_IV_in (key_IV_in)

SEC_BLKMV_TDES_KEY_HI 0x09

R/W
W

Default‘h0

Description
sec_sr_tdes_key_IV_in[63:32]: secure upper 32 bits of tdes_sr_key_IV_in (key_IV_in)dkerBit(s)
31-0

nel

The register represents the 2nd32-bit component of the 64-bit IV key. Writing this register sets the IV key Bits [63:32] of theregister to be written to the RAM. Reading this register returns the current IV value for processing. This is useful if Cipher
Block Chaining must be interrupted. Software can read the current IV key and restore it later to continue processing.

SEC_BLKMV_TDES_CONTROL 0x0a

H

‘h0
‘h0
‘h0
‘h0

to

R/W
R/W
R/W
R/W

e

3
2
1
0

Description
sec_sr_tdes_key_IV_wr: TDES key_IV_wr control signal
sec_sr_tdes_mode_wr: the write control signal of mode of TDES
Reserved
sec_sr_des_modes: set to ‘101’ for TDES decryption, ‘010 for DES Encryption
sec_sr_tdes_cbc: 0 = ECB mode, 1= CBC mode.
sec_sr_tdes_decrypt: set to 1 to decrypt, set to 0 to encrypt
sec_sr_tdes_wr_thread: CPU thread
sec_sr_tdes_key_IV_in_addr: 0 = key0, 1 = key1, 2 = key2, 3 = IVtdes_pio_key_busy: TDES key busy read back signal
tdes_pio_busy: TDES busy read back signal
Reserved
des_pio_modes: Mode for the 3 DES engines: [0] = first DES engine, …, [2] = last DES core.
// 0=encrypt, 1=decrypt
Reserved
tdes_pio_key_compute: set true for one clock to start key computation
tdes_pio_decrypttdes_pio_start: set true for one clock to process this message (msg_in)utDefault
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0

tr
ib

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W

is

Bit(s)
31
30
29-25
24-22
21
20
19-18
17-16
15
14
13-7
6-4

ar

In addition to the 4 IV keys, the Triple DES engine also maintains 4 structures that dictate the individual DES modes, CBC enable,
and whether or not we’re encrypting or decrypting.
Once the 64-bit IV Key has been established and the MODE, CBC_EN and DECRYPT_EN Bits have been set below, write thisregister again setting Bits 30 and 31. This pushes the 64-bit IV key and MODE, CBC_EN and DECRYPT_EN Bits into internal RAM.
The processing engine will look up these values later using the 2-bit index (TDES_INDEX) supplied in the DMA table entry.

SEC_BLKMV_SHA_CONTROL 0x32
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0
‘h0

D

Bit(s)
31
30-23
22
21
20
19-18
17-16
15-10
9-8
7
6
5-4
3
2
1
0

Description
sha_busy: sha engine busy read-back signal
Reserved
sha_pio_fb: sha pio mode feedback sel. 1: sha_msg_in = sha_msg_out, 0: sha_msg_in = sha_pio_msg_in
sha_pio_last_wdata: last wdata signal for sha_pio_data_wrtire interface: CPU (PIO mode) to SHA engine
sha_pio_last_block: last block signal for sha_pio_data_wrtire interface: CPU (PIO mode) to SHA engine
sha_pio_wdata_byte_cnt: byte cnt signal for sha_pio_data_wrtire interface: CPU (PIO mode) to SHA engine
sec_sha_pio_mode: pio mode cntl of sha mode: 1:sha1, 2:sha2-256, 3:sha2-224
Reserved
sec_sha_rd_thread: sha message read out thread sel
Reserved
sec_sha_ cpu_save_init: pulsed. Reset the internal address counters for CPU writes
sec_sha_wr_thread: sha message write thread sel
sec_sha_dma_enable: sha enable signal
sec_sha_clk_en_jic: just in case sha gclk enable signal.
Reserved
sec_sha_pio_enable: pio mode sha enable signal

95/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

SEC_BLKMV_PIO_CNTL0
Bit(s)
31
30-6
5
4
3
2-0

R/W
R
R/W
R/W
R/W
R/W
R/W

0x25

Default
‘h0
‘h0
‘h0
‘h0
‘h0

Description
pio_granted: pio grant signal (of pio_request) read-backReserved
pio_hold_all: set to 1 to block all in-line processing regardless of the PIO being used
pio_request: pio mode request signal
Reserved
pio_inline_type: 0: Normal 1D or 2D move, 1: Triple-DES (TDES) processing, 2: Rijndael (DIVX) processing, 3: CRC
processing, 4: AES processing, 5: SHA processing

The following registers’ final address = 0xc8832000 + offset*4
NDMA_CNTL_REG0 0x70
Default
1

30

R/W

1

29

R/W

1

28

R/W

1

27

R/W

1

26
25-16

R
R/W

0x63

15

R/W

0

14

R/W

0

13

R/W

0

12
11
10-0

R
R/W
R/W

0
0x00

Description
IN-LINE processing clock gating mode: If This bit is set to 0, then the clocks to the DMA engine are always on. If This bit
is set to 1, then the DMA engine operates in auto-power down mode. That is, the internal clocks are shut down
dynamically to save power.
CRC_GATED_CLK_MODE: If This bit is set to 0, then the clocks to the CRC engine are always enabled. If This bit is set to1, then the CRC block operates in auto-power down mode which will save power when the CRC module is not being
used.
RIJNDAEL_GATED_CLK_MODE: If This bit is set to 0, then the clocks to the RIJNDAEL engine are always enabled. If Thisbit is set to 1, then the RIJNDAEL block operates in auto-power down mode which will save power when the RIJNDAEL
module is not being used.
TDES_GATED_CLK_MODE: If This bit is set to 0, then the clocks to the TDES engine are always enabled. If This bit is set
to 1, then the TDES block operates in auto-power down mode which will save power when the TDES module is not being
used.
DMA_GATED_CLK_MODE: If This bit is set to 0, then the clocks to the general DMA engine are always enabled. If Thisbit is set to 1, then the general DMA block operates in auto-power down mode which will save power when the general
DMA module is not being used.
Status: ‘1’ indicates the DMA engine is processing a descriptor. ‘0’ indicates that all descriptors have been processed
Periodic Interrupt Delay: This value dictates the rate at which periodic interrupts are generated if Bit 15 is set below.
Note: If you change this value, then disable the periodic interrupt (Bit 15 below) and then re-enable the period interrupt
to reset the internal periodic counter.
Periodic Interrupt Enable: If This bit is set to ‘1’, then the DMA engine will generate an interrupt every N+1 uS where N
is described above as the Periodic Interrupt Delay.
DMA Engine Enable: Set This bit to ‘1’ to enable the DMA Engine. Note, the DMA engine will not do anything until a
descriptor has been placed into memory and the NEW_DMA_ADD_DESCRIPTOR register has been written. Set This bit
to ‘0’ to abort the current DMA and return the DMA engine to an idle state. Note: If you abort a transfer you should
also clear the internal descriptor count by writing 0x2271 with 0x00000001.
AES_GATED_CLK_MODE: If This bit is set to 0, then the clocks to the AES engine are always enabled. If This bit is set to1, then the AES block operates in auto-power down mode which will save power when the AES module is not being
used.
AES STATUS: 1 = AES decryption/encryption engine is busy.
Use std crc: 1: use standard crc32. 0: use mpeg2 crc32
Reserved

l

R/W
R/W

tr
ib

ut

e

to

H

ar

dk
er

ne

Bit(s)
31

NDMA_TABLE_ADD_REG 0x72
Default-

Description
Blkmv (DME engine) descriptor_cnt[3] read_out
Blkmv (DME engine) descriptor_cnt[2] read_out
Blkmv (DME engine) descriptor_cnt[1] read_out
Blkmv (DME engine) descriptor_cnt[0] read_out

is

R/W
R
R
R
R

D

Bit(s)
31:24
23-16
15-8
7-0

NDMA_TDES_IV_KEY_LO 0x73
The Triple DES engine maintains up to 4 IV keys used for CBC processing. The following three registers are used to setup andwrite the IV keys to an internal memory. Because each IV key is 64 Bits, the key must be written to an internal register before
a 3rd register write is used to push the stored IV key into the internal RAM.
Writing this register sets the IV key Bits [31:0] of the register to be written to the RAM. Reading this register returns the current
IV value for processing. This is useful if Cipher Block Chaining must be interrupted. Software can read the current IV key andrestore it later to continue processing.
Bit(s)31-0

R/W
W

Default
0

Description
Non-secure IV Key Bits[31:0]: Write Only

96/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

NDMA_TDES_IV_KEY_HI 0x74
The register represents the 2nd32-bit component of the 64-bit IV key. Writing this register sets the IV key Bits [63:32] of theregister to be written to the RAM. Reading this register returns the current IV value for processing. This is useful if Cipher
Block Chaining must be interrupted. Software can read the current IV key and restore it later to continue processing.
Bit(s)31-0

R/W
W

Default
0

Description
Non-secure IV Key Bits[63:32] Write Only

NDMA_TDES_CONTROL 0x75

Default
0

30

W

0

29-9
8-6

R
R/W

0
0

5

R/W

0

4

R/W

0

3-2

R/W

0

1-0

R/W

0

Description
This bit is a write only bit. Writing This bit pushes the IV key stored in registers (0x2273 & 0x2274) into the IV key
internal RAM. The RAM index is supplied by Bits [3:0] below.
This bit is a write only bit. Writing This bit pushes the DES_MODES, CBC_EN and DECRYPT_EN Bits into an internal RAM.
The RAM index is supplied by Bits [3:0] below.
Reserved
MODE: Set to 0x5 for Triple DES decryption and 0x2 for Triple DES Encryption. Note this value is simply shadowed inthis register. This bit should be written first before setting Bits 30/31 above to push this value into the internal MODERAM.
CBC_EN: 0 = ECB mode, 1 = CBC mode. Note This bit is simply shadowed in this register. This bit should be written first
before setting Bits 30/31 above to push this value into the internal MODE RAM.
DECRYPT_EN: Set This bit to 1 to decrypt, 0 to encrypt using triple DES. Note This bit is simply shadowed in this register.
This bit should be written first before setting Bits 30/31 above to push this value into the internal MODE RAM.
IV KEY and Modes Address. These 2 Bits are used to index the 4 locations in the IV KEY RAM and the MODE RAM. These
2 Bits should be set before writing Bits 30 and 31 above.
TDES KEY IV IN ADDR: 0 = key0, 1 = key1, 2 = key2, 3 = IV

ne

R/W
W

NDMA_RIJNDAEL_CONTROL 0x76
This register directs DIVX processing.

NDMA_RIJNDAEL_RK_FIFO
Bit(s)
31-0

R/W
R/W

R/W
R
R/W
R/W
R/W

Description
Reserved
THREAD_INIT: Each Bit is used to initialize a particular thread.
Reserved
CORE_BUSY: This bit indicates that the thread state-machine is busy
Reserved
CURR_THREAD_NUM: This value represents the current thread ID being processed by the DMA state-machine
THREAD_ENABLE: There are 4 threads that can be enabled/disabled corresponding to Bits[11:8]
DEFAULT_SLICE_CNT: The DMA engine will move from one thread to another after [n] * 256 byte transfers. If a slice
count is not provided in the descriptor table, the default value is applied to that thread’s descriptor

is

NDMA_SHA_CONTROL
Bit(s)
31-8
7-6
5-4
3

Description
Writing this register writes the RK FIFO for DIVX Decryption

0x79

Default
0
0
0
0
0
0
1

D

R/W
R/W
R/W
R/W
R
R/W
R
R/W
R/W

0x77

Default
0

NDMA_THREAD_REG
Bit(s)
31-28
27-24
23-16
15
14
13-12
11-8
7-0

Description
This bit is a write only bit. If This bit is set when writing, the RK fifo write pointer is reset.
Reserved
NR Value: 10,12 or 14eDefault
0
0
0

ut

R/W
W
R
R/W

tr
ib

Bit(s)
31
30-4
3-0

to

H

ar

dk
er

Bit(s)
31l

In addition to the 4 IV keys, the Triple DES engine also maintains 4 structures that dictate the individual DES modes, CBC enable,
and whether or not we’re encrypting or decrypting.
Once the 64-bit IV Key has been established and the MODE, CBC_EN and DECRYPT_EN Bits have been set below, write thisregister again setting Bits 30 and 31. This pushes the 64-bit IV key and MODE, CBC_EN and DECRYPT_EN Bits into internal RAM.
The processing engine will look up these values later using the 2-bit index (TDES_INDEX) supplied in the DMA table entry.

0x9f

Default00
00Description
Reserved
Reserved
non_sec_sha_rd_thread: the non_secure SHA msg_out/datalen_out read out thread selection
Reserved

97/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Bit(s)
2

R/W
R/W

Default
0

1-0

R/W

0

-

13-10
9-8
7-0

R
R/W
R/W

0
0
0

NDMA_CNTL_REG1

ar

R

dk
er

-

17-14

Description
Reserved
mem_st_dbg[4:0]: debug (monitor) of mem_st signal:
0 = MEM_ST_IDLE;
1 = MEM_ST_CHECK_PIO
2 = MEM_ST_INIT;
3 = MEM_ST_READY
4 = MEM_ST_TDES_WAIT;
5 = MEM_ST_TDES_WR_MODULE
6 = MEM_ST_TDES_WR_FIFO; 7 = MEM_ST_RIJNDAEL_WRITE
8 = MEM_ST_RIJNDAEL_WAIT; 9 = MEM_ST_RIJNDAEL_READ
10 = MEM_ST_CRC_PROCESS; 11 = MEM_ST_CRC_NEXT
12 = MEM_ST_AES_WRITE;
13 = MEM_ST_AES_WAIT
14 = MEM_ST_AES_READ;
15 = MEM_ST_SHA_WRITE
16 = MEM_ST_SHA_WAIT;
17 = MEM_ST_SHA_SAVE
cache_st_dbg[1:0]: debug (monitor) of cache_st signal (of new_blkmv_top):
0 = CACHE_ST_IDLE;
1 = CACHE_ST_STORE_TABLE
2 = CACHE_ST_STORE_THREAD; 3 = CACHE_ST_READ_THREAD
dma_st_dbg[3:0]: debug (monitor) of dma_st signal (of new_blkmv_top):
0 = DMA_ST_IDLE;
1 = DMA_ST_RD_TABLE_PRE;
2 = DMA_ST_RD_TABLE_REQ;
3 = DMA_ST_RD_TABLE_WAIT;
4 = DMA_ST_RD_TABLE_TAG_OWN;
5 = DMA_ST_RD_TABLE_TAG_DONE;
6 = DMA_ST_CHECK_THREAD_STATUS; 7 = DMA_ST_CACHE_TABLE;
8 = DMA_ST_PROCESS;
9 = DMA_ST_CACHE_THREAD;
10 = DMA_ST_ABORT;
11 = DMA_ST_GET_THREAD_DATA;
12 = DMA_ST_PROCESS_UNPAUSE;
Reserved
non_sec_aes_key_iv_thread: non secure aes key / IV write thread selectReservedlDefault
0
-

ne

R/W
R
R

0x8c

R/W
R

Default
-

15-10
9-4
3
2
1
0

R/W
R/W
R/W
R/W
R/W
R/W

0
6’h3f
0
0
0
‘h1

Description
debug (monitor) of xfer_st signal (of new_blkmv_core):
XFER_ST_IDLE = 16'h0001;
XFER_ST_RD_START = 16'h0002
XFER_ST_RD_DDR_REQUEST = 16'h0004; XFER_ST_RD_DDR_WAIT = 16'h0008
XFER_ST_INLINE = 16'h0010;
XFER_ST_WR_AHB_PROCESS = 16'h0040
XFER_ST_PARSER_PRE = 16'h0080;
XFER_ST_PARSER_XFER = 16'h0100
XFER_ST_CHECK = 16'h0200;
XFER_ST_RD_START_FNL = 16'h0400
XFER_ST_WR_DDR_PREP0 = 16'h0800;
XFER_ST_WR_DDR_PREP1 = 16'h1000
ddr_burst_num: burst_num_blkmv output to DDRReserved
Reserved
thread_speed_up: thread speed up control of BLKMV DMA_ST_PROCESS
A_urgent: DDR Urgent bit
cntl_wr_avail_en: write available enable (jic) signal: Write available forces the DMA state-machines to wait until all data
is sent to the DDR memory before moving to the next task. NOTE: This only applies to the very last byte of data for a
block to minimize transfer delays. This feature ensures data is actually in the DDR memory before issuing an interrupt
to the CPU subsequently forcing a “sync” operation.

D

is

tr
ib

ut

e

Bit(s)31-16

toBit(s)
31-25
24-20

0x9c

H

NDMA_AES_REG0

Description
non_sec_sha_cpu_save_init: control of sha_save_restore CPU init signal: reset the internal address counters for cpu
writes
non_sec_sha_wr_thread: the non_secure SHA msg_wr/datalen_wr write thread selection

98/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

26. TIMER
26.1 Overview
The SOC contains 11 general purpose timers and 2 watchdog timers.

26.2 General-Purpose Timer
The SOC contains a number of general-purpose timers that can be used as general counters or interrupt generators. Eachcounter (except TIMER E) can be configured as a periodic counter (for generating periodic interrupts) or a simple count-down
and stop counter. Additionally, the timers have a programmable count rate ranging from 1uS to 1mS. The table below outlines
the general-purpose timers available in the chip.

Counter size
16-bits

Timer B
Timer C
Timer D
Timer E

1uS, 10uS, 100uS, 1mS
1uS, 10uS, 100uS, 1mS
1uS, 10uS, 100uS, 1mS
System clock, 1uS, 10uS,
100uS, 1mS
1uS, 10uS, 100uS, 1mS
1uS, 10uS, 100uS, 1mS
1uS, 10uS, 100uS, 1mS
1uS, 10uS, 100uS, 1mS
System clock, 1uS, 10uS,
100uS
System clock

16-bits
16-bits
16-bits
64-bits

Doesn’t generate an interrupt. This is a count up counter that counts from 0 to
0xFFFFFFFF. The counter can be written at any time to reset the value to 0.

ar

16-bits
16-bits
16-bits
16-bits
16-bits

Used in the Always On domain to generate interrupts for the AO-CPUH

Timer E-AO

Comment
The 16-bit counter allows the timer to generate interrupts as infrequent as every
65.535 Seconds

32-bits

This Always On counter doesn’t generate an interrupt. Instead it simply counts
up from 0 to 0xFFFFFFFF. The counter can be written at any time to reset thevalue to 0.

toTimer F
Timer G
Timer H
Timer I
Timer A-AO

neTimebase Options
1uS, 10uS, 100uS, 1mS

dk
er

Timer
Timer Al

Table III. 26.1. General-Purpose Timere26.3 Watchdog Timerut

There are two watchdog timers, one in AO and the other in EE domain, illustrated as following:
Figure 26.1 Watchdog Timertrib

ee_reset_n

D

is

ee_wd

irq

ee_clk_rst

irq[0]
irq[203]

A53

gpio_osel

test_nee_reset_n

irq

ao_irq[49]

m3

ao_wd
gpio_oao_reset_n

ao_reg99/336AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

AO domain watchdog timer and EE domain watchdog timer have the same design, as illustrated in the folloing figure:
Figure 26.2 EE domain Watchdog Timer degisn

0x2634[19]

0x2634[24]

0x2634[17:0]

0x2636[15:0]

0x2636[23]/[22]/[21]

ee_wd
0/
!0x2634[27]/!0x2634[26]
0

0/1/1
0

osc_clk
0
clk81

G

cCNT

tick

tCNT

reset/!reset/!reset

irq/
ao_reset_n/sys_reset_n1

10x2634[25]

0x2636[31:16]nel

10x2634[31]

dker

0x2634[18]

Har

The AO Domain watchdog timer is driven from the system clock (typically 157Mhz). It is a 16-bit counter that is periodically
reset by either the AO CPU or the System CPU (A53). This AO-watchdog timer can be used to generate an interrupt of the AO
domain. Additionally, the AO-watchdog timer can be used to “enable” a delay generator that can toggle a GPIO pin (currently
the TEST_n I/O pad). The “delay generator” allows an interrupt to first be acknowledged by the AO-CPU before the TEST_N
pad is toggled. The “delay generator” is programmable from 1 to 65535 system clocks (typically 417uS).

to

It should be noted that the AO watchdog timer can also be used to reset the AO domain but this feature is only used when
operating in a suspend mode (only the AO-domain is powered). As long as the system periodically resets the AO-watchdog
timer the WD_GPIO_CNT (delay generator) will not be enabled and the I/O pad will not toggle.

ute

NOTE: The maximum delay between two AO-watchdog periodic resets is about 100mS (assuming a 157Mhz system clock).

is

tr
ib

The EE Domain watchdog timer is driven by the 24Mhz crystal clock and can be used to generate an interrupt to the system
CPU (the A53) or optionally, the watchdog timer can completely reset the chip (causing a cold boot). There are a few registers
that are not affected by watchdog timer. These registers are only reset by the external RESET_n I/O pad and can be used tostore information related to a possible watchdog event. As long as the system CPU periodically resets the EE-watchdog timer,
it will never timeout and cause an interrupt or system reset.

D

NOTE: The maximum delay between two EE-watchdog periodic resets is about 8.3 Seconds. This time is independent of thesystem clocks and is driven by the external 24Mhz crystal.

26.4 Register Definitions
Each register final address = 0xC1100000 + offset * 4
ISA_TIMER_MUX
Bit(s)
31-20
19

0x2650R/W
R
R/W

Default
01

Description
unusedTIMERD_ EN: Set to 1 to enable Timer D

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7-6
5-4
2-3
1-0

R/W
R/W
R/W
R/W

0x0
0x0
0x0
0x0

ISA_TIMERA

0x2651

Description
TIMERC_ EN: Set to 1 to enable Timer C
TIMERB_ EN: Set to 1 to enable Timer B
TIMERA_EN: Set to 1 to enable Timer A
TIMERD_MODE: If This bit is set to 1, then timerD is a periodic . 0 = one-shot timer
TIMERC_MODE: If This bit is set to 1, then timerC is a periodic . 0 = one-shot timer
TIMERB_MODE: If This bit is set to 1, then timerB is a periodic . 0 = one-shot timer
TIMERA_MODE: If This bit is set to 1, then timerA is a periodic . 0 = one-shot timer
unusedTIMER E input clock selection:
000:
System clock001:
1uS Timebase resolution
010:
10uS Timebase resolution
011:
100uS Timebase resolution
100:
1mS timebase
NOTE: The mux selection for Timer E is different from timer A, B, C and D
TIMER D input clock selection: See TIMER A below
TIMER C input clock selection: See TIMER A below
TIMER B input clock selection: See TIMER A below
TIMER A Input clock selection: These Bits select the input timebase for the counters for TimerA00:
1uS Timebase resolution
01:
10uS Timebase resolution
10:
100uS Timebase resolution
11:
1mS Timebase resolutionlDefault
1
1
1
0
0
1
1
0
0x1

ne

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W

dk
er

Bit(s)
18
17
16
15
14
13
12
11
10-8

ISA_TIMERB

Default
0x0

Description
Current Count value
Starting count value. Write this value to start TIMER A.

H

R/W
R
R/W

to

Bit(s)
31-16
15-0

ar

Timer A is a 16 bit count DOWN counter driven by the clock selected in register 0x01000530. TIMER A will count down fromsome value to zero, generate an interrupt and then re-load the original start count value. This timer can be used to generate
a periodic interrupt (e.g. interrupt every 22 uS).

0x2652Timer B is just like Timer A.

ISA_TIMERC

Default
0x0

0x2653Bit(s)
31-16
15-0

0x2654

Default0
0x0

Description
unusedStarting count value. Write this value to start TIMER C

is

ISA_TIMERD

R/W
R
R/W

tr
ib

Timer C is just like Timer A.

Description
Current Count value
Starting count value. Write this value to start TIMER B

e

R/W
R
R/W

ut

Bit(s)
31-16
15-0

D

Timer D is identical to Timer A.
Bit(s)
31-16
15-0

R/W
R
R/W

Default0
0x0

Description
unusedStarting count value. Write this value to start TIMER D

ISA_TIMERE 0x2662
Timer E is simply a 64-bit counter that increments at a rate set by register 0x2650. To reset the counter to zero, simply write
this register with any value. The value below is a read-only value that reflects the current count of the internal counter. This
register can be used by software to simply provide a polling delay loop based on a programmable timebase.
Bit(s)
31-0

R/W
R

Default-

Description
Current value of Timer E. Write this register with any value to clear the counter.

ISA_TIMERE _HI 0x2663

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Bit(s)
31-0

Revision 1.1.4

R/W
R

Default-

Description

Current value of Timer E[63:32]. Need read ISA_TIMERE first.

ISA_TIMER_MUX1 0x2664
Default
0
1
1
1
1
0
0
1
1
0
0x1

7-6
5-4
2-3
1-0

R/W
R/W
R/W
R/W

0x0
0x0
0x0
0x0

Description
unusedTIMERD_ EN: Set to 1 to enable Timer D
TIMERC_ EN: Set to 1 to enable Timer C
TIMERB_ EN: Set to 1 to enable Timer B
TIMERA_EN: Set to 1 to enable Timer A
TIMERD_MODE: If This bit is set to 1, then timerD is a periodic . 0 = one-shot timer
TIMERC_MODE: If This bit is set to 1, then timerC is a periodic . 0 = one-shot timer
TIMERB_MODE: If This bit is set to 1, then timerB is a periodic. 0 = one-shot timer
TIMERA_MODE: If This bit is set to 1, then timerA is a periodic. 0 = one-shot timer
unusedTIMER E input clock selection:
000:
System clock001:
1uS Timebase resolution
010:
10uS Timebase resolution
011:
100uS Timebase resolution
100:
1mS timebase
NOTE: The mux selection for Timer E is different from timer A, B, C and D
TIMER D input clock selection: See TIMER A below
TIMER C input clock selection: See TIMER A below
TIMER B input clock selection: See TIMER A below
TIMER A Input clock selection: These Bits select the input timebase for the counters for TimerA00:
1uS Timebase resolution
01:
10uS Timebase resolution
10:
100uS Timebase resolution
11:
1mS Timebase resolution

l

R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W

H

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ne

Bit(s)
31-20
19
18
17
16
15
14
13
12
11
10-8

ISA_TIMERF 0x2665

ISA_TIMERG

Default
0x0

0x2666Bit(s)
31-16
15-0

R/W
R
R/W

tr
ib

Timer G is just like Timer F.

Description
Current Count value
Starting count value. Write this value to start TIMER A.

e

R/W
R
R/W

ut

Bit(s)
31-16
15-0

to

Timer F is a 16 bit count DOWN counter driven by the clock selected in register 0x01000530. TIMER A will count down fromsome value to zero, generate an interrupt and then re-load the original start count value. This timer can be used to generate
a periodic interrupt (e.g. interrupt every 22 uS).

Default
0x0

is

ISA_TIMER_H 0x2667

Description
Current Count value
Starting count value. Write this value to start TIMER B

Timer H is just like Timer F.
R/W
R
R/W

D

Bit(s)
31-16
15-0

Default0
0x0

Description
unusedStarting count value. Write this value to start TIMER C

WATCHDOG_CNTL 0x2634
Bit(s)
31

R/W
R

Default
0

30-28

R/W

0

27

R/W

0

26

R/W

0

25

R/W

0

Description

Watchdog_reset
Reserved
Ao_reset_n_now, if watchdog_en =0, output ao_reset_n = ! ao_reset_n_now
Sys_reset_n_now, if watch_dog_en = 1, output sys_reset_n = !sys_reset_n_now.
Clk_div_en:
0: no tick;
1: generate tick;

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0

22

R/W

0

21

R/W

0

20

R/W

0

19

R/W

0

18

R/W

0

17-0

R/W

0

Clk_sel：0:osc_clk;
1:clk_81
Watchdog_en
0: no watchdog reset
1: gen watchdog reset
Clk_div_tcnt, when clk_div_en is 1, generate a tick each tcnt clock

0x2635

17

R/W

0

16

R/W

0

15-0

R/W

Description

Reserved
Gpio_pulse
0:level reset
1:pulse reset
Gpio_polarity
0: 1 is reset;
1: 0 is reset.
Gpio_pulse_tcnt
If gpio_pulse is 1, level reset will hold tcnt clock.

to

Default
0

e

R/W
R

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Bit(s)
31-18

ut

WATCHDOG_CNTL1l

R/W

Clk_en:0: no clk;
1: clk work;
Interrupt_en:
0: no irq out;
1: irq = watchdog_reset;
Ao_reset_n_en:
0: output ao_reset_n = 1;
1: output ao_reset_n = ! watchdog_reset;
Sys_reset_n_en
0: output sys_reset_n = 1;
1: output sys_reset_n = ! watchdog_reset;
Reserved

ne23

Description

dkerDefault
0

ar

R/W
R/W

H

Bit(s)
24

is

0

R/W
R

Default
0

Description

R/W

5000

The cnt of tick.
If watchdog_en is 1, when tick cnt reached “5000”, generate watchdog_reset.

WATCHDOG_TCNT 0x2636

15-0

D

Bit(s)
31-16

WATCHDOG_RESET 0x2637
Bit(s)31-0

AO_TIMER_REG

R/WW

Default
0

Description

When write any value(include 0), watchdog module will be reset.

0xc810004c

Timer controls.
Bit(s)
31-5

R/W
R/W

Default
0

Description
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3
2
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Revision 1.1.4

R/W
R/W
R/W
R/W

AO_TIMERA_REG

0
0
0
0

TIMER_E_EN
TIMER_A_EN
TIMER_A_MODE: 1 = periodic, 0 = one-shot
TIMER_CLK_MUX:
00 = TimerA clock = AO CPU clock
01 = Timer A clock = 1uS ticks
10 = Timer A clock = 10uS ticks
11 = Timer A clock = 100uS ticks

0xc8100050

Timer A starts at a non-zero value and decrements to 0. When timer A reaches a count of 0 it will re-load with the
TIMER_A_TCNT value.
R/W
R
R/W

Default
00

Description
TIMER A current count.
TIMER_A_TCNT: Timer A Terminal count00xc8100054

AO_TIMERE_REG

nelBit(s)
31-16
15-0

Bit(s)
31-0

Default
0

Description
TIMER E current Count

Crypto

ar

27.

R/W
R/W

dk
er

If this register is written (with any value), then Timer E is reset to 0. Immediately after being cleared, timer E will start
incrementing at a clock rate equal to the clock used for the AO CPU.

27.1 Overview

toH

The crypto engine is one encrypt/decrypt function accelerator. It supports both encryption/decryption andsignature/verification. Crypto engine supports 4 different modes, i.e. A53 secure, A53 non secure, M3 secure and M3 nonsecure. The crypto engine has special internal DMA controller to transfer data.

tr
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e

It has the following features:
 AES block cipher with 128/192/256 Bits keys, standard 16 bytes block size and streaming ECB, CBC and CTR modes DES/TDES block cipher with ECB and CBC modes supporting 64 Bits key for DES and 192 Bits key for 3DES Hardware key-ladder operation and DVB-CSA for transport stream encryption
 Built-in hardware True Random Number Generator (TRNG), CRC and SHA-1/SHA-2 (SHA-224/SHA-256) engine

27.2 Key Ladder

Dis

The Key Ladder is a series of TDES / AES crypto processes that iterates on different user supplied and OTP keys. The key laddermodule uses a single AES / TDES crypto module and iterates using internal storage to hold temporary states.

27.3 RNG

Functionality the Random Number Generator (RNG) contains two main modules: True Random Number Generator (TRNG) and
Deterministic Random Number Generator (DRNG).
True Random Number Generator (TRNG): this TRNG is realized by using metastability and jitter for random bit generation basedon four free running ring oscillator
Deterministic Random Number Generator (DRNG): this DRNG, which has32-bit random number generator, is mainly designed
to increase the throughput and do post-processing of the Digital TRNG, which will need hundreds cycles to collect entropy.

27.4 EFUSE

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l

The EFUSE consists of a 4kbit One Time Programmable (OTP) memory that is broken up into 32, 128-bit blocks. Data is always
read/written in 128-bit blocks using the APB bus (software) or by the Key-ladder which is integrated with EFUSE block.

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Section IV Video Path
The data path of the video path module is shown in the Fig IV.1 below:
The working flow of S905 video path module is as following:
For TS input, it will go to DEMUX, which will separate the data in to video data, audio data and control data, and will write
video data in to DDR, the VDEC module will read this data from DDR and decode it, and then write it back to DDR, which will
be sent to VPU module and display in either HDMI format or CVBS format.
For DVP input, DVP module will write it directly to DDR, and VPU module read it and display it in either HDMI or CVBS format.

ar

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l

This section describe S905 video path from the following aspects:•
Video Input-TS input-DEMUX-DVP•Video Output-RDMA-VPP(VIU/VPP)
-HDMI
-DVBS

to

DDR

H

Fig IV.1 Data Path of Video Path

DECODE BUFFER

DVP BUFFER

ut
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is

D

DEMUX

Control

Audio

Video

e

VIDEO BUFFER

VDEC

VPU
RDMA

CVBS
(TVENCODER)

Display

DVP

VIU
VPP

HDMITX

Display

TS Input

28. Video Input

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28.1 Overview
This part describes the video input module of S905, including TS input, Demux and DVP submodules.

28.2 Demuxnel

Demux submodule of S905 is designed for connecting to external digital TV tuner/demodular and de-mux the input signal. It
decomposes the TS input signal into video signal, audio signal, and clock signal, the video signal will be first writen in to DDR,
then decoded by the video decoder(VDEC). S905 use external demudulator to demulate received signal in to TS (Transport
Stream) signal. TS signals contains one or more program of coded data. S905 TS abide by H.222.0, for more detail, please check
H.222.0 files. TS uses GPIO ports for input, check 23. GPIO for more information about registers.

28.3 DVPdker

DVP is an interface designed for camera input. S905’s DVP supports ITU656 and ITU601 format. S905 has 2-channle DVP
interface, the data recoded by digital camera will be written directly in to DDR, and VPU will read this data and display it ineither HDMI format or CVBS format.

ar28.4 Register Definition
Demux Register

R/W

Default

Description

30:28

RW

0

ciplus_o_sel

27:26

RW

0

ciplus_i_sel

25

RW

0

24

RW

0

23

RW

0

22

RW

21

RW

20

RW

use FAIL from TS1

trib

use FAIL from TS0
invert fec_error for S2P1

0

invert fec_data for S2P1

0

invert fec_sync for S2P1

RW

0

invert fec_valid for S2P1

RW

0

invert fec_clk for S2P1

RW

fec_s_sel for S2P1 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved

D18

use FAIL from TS2

0

is

19

e

Bit(s)ut

STB_TOP_CONFIG 0xf0

toH

Demux Common Register
Final address = 0xc1105800 + offset * 4

0

RW

0

enable_des_pl_clk

14:13

RW

0

reserved

12:10

RW

0

ts_out_select, 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File

9:8

RW

0

des_i_sel 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved

7

RW

0

enable_des_pl

6

RW

0

invert fec_error for S2P0

5

RW

0

invert fec_data for S2P0

4

RW

0

invert fec_sync for S2P0

3

RW

0

invert fec_valid for S2P0

2

RW

0

invert fec_clk for S2P0

1:0

RW

0

fec_s_sel for S2P0 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved

17:16
15

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TS_TOP_CONFIG 0xf1
R/W

Default

Description

31:28

RW

7

s2p1_clk_div

27:24

RW

7

s2p0_clk_div

23

RW

0

s2p1_disable

22

RW

0

s2p0_disable

21

RW

0

Reserved

20

RW

0

TS_OUT_error_INVERT

19

RW

0

TS_OUT_data_INVERT

18

RW

0

TS_OUT_sync_INVERT

17

RW

0

TS_OUT_valid_INVERT

16

RW

0

TS_OUT_clk_INVERT

15:8

RW

187

TS_package_length_sub_1 (default : 187)

7:0

RW

0x47

fec_sync_byte (default : 0x47)

Bit(s)

R/W

Default

25:24

RW

3

transport_scrambling_control_odd_2 // should be 3

23:16

RW

0

file_m2ts_skip_bytes

15:8

RW

0

des_out_dly

7:6

RW

3

transport_scrambling_control_odd // should be 3

5

RW

0

ts_hiu_enable

4:0

RW

4

fec_clk_div

Bit(s)

R/W

Default

Description

19:14

R

0

des_2 ts pl state -- Read Only

13:8

R

0

des ts pl state -- Read Only

3:0

RW

0

PID index to 8 PID to get key-set
auto increse after TS_PL_PID_DATA read/write

29

RW

28:16

RW

13

RW

Default

RW

ne

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ut
Description

0

PID #INDEX +1 match disble

0

PID #INDEX+1

0

PID #INDEX match disble

0

PID #INDEX

Description

Bit(s)

D

12:0

tr
ib

R/W

is

Bit(s)ar

Description

TS_PL_PID_INDEX 0xf3

TS_PL_PID_DATA 0xf4

dker

TS_FILE_CONFIG 0xf2

lBit(s)

R/W

Default

31:0

RW

0

COMM_DESC_KEY0 0xf5

Common descrambler key (key Bits[63:32])

COMM_DESC_KEY1 0xf6
Bit(s)

R/W

Default

31:0

RW

0

Description

Common descrambler key (key Bits[31:0])

COMM_DESC_KEY_RW 0xf7
Bit(s)

R/W

Default

Description

7

RW

0

Key endian;

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Bit(s)

R/W

Default

6

RW

0

Write key ladder cw [127:64] to key;

5

RW

0

Write key ladder cw [63:0] to key;

4

RW

0

0: write to descramble 1; 1: write to descramble 2;

3:0

RW

0

The address of key

Bit(s)

R/W

Default

31:0

RW

0

Bit(s)

R/W

Default

31:0

RW

0

Bit(s)

R/W

Default

31:0

RW

0

Bit(s)

R/W

Default

31:0

RW

0

CIPLUS_KEY0

Description

0xf8
CI+ Register defines Bits[31:0] of the key

0xf9

0xfa
Description

CI+ Register defines Bits[95:64] of the key

CIPLUS_KEY3 0xfb
Descriptionar

CI+ Register defines Bits[127:96] of the key

0xfc
R/W

Default

5

RW

0

write AES IV B value

4

RW

0

write AES IV A value

3

RW

0

write AES B key

2

RW

0

write AES A key

1

RW

0

write DES B key

0

RW

0

write DES A key

Bit(s)

R/W

15:8

RW

3

RW

2

RW

e

ut
Description0

TS out delay. This controls the rate at which the CIplus module drives TS out

0

General enable for the ciplus module0

AES CBC disable (default should be 0 to enable AES CBC)RW

0

AES Enable

RW

0

DES Eanble

D

0

Default

is

1

tr
ib

CIPLUS_CONFIG 0xfd

DescriptiontoBit(s)H

CIPLUS_KEY_WRl

CI+ Register defines Bits[63:32] of the key

dker

CIPLUS_KEY2

Descriptionne

CIPLUS_KEY1

Description

CIPLUS_ENDIAN 0xfe
Bit(s)

R/W

Default

Description

31:28

RW

0

AES IV endian

27:24

RW

0

AES message out endian

23:20

RW

0

AES message in endian

19:16

RW

0

AES key endian

15:11

RW

0

unused

10:8

RW

0

DES message out endian

6:4

RW

0

DES message in endian

2:0

RW

0

DES key endian

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COMM_DESC_2_CTL 0xff
Bit(s)

R/W

Default

Description

15:8

RW

0

des_out_dly_2

7

RW

0

reserved

6RW

0

enable_des_pl_clk_2

5

RW

0

enable_des_pl_2

4:2

RW

0

use_des_2 Bit[2] -- demux0, Bit[3] -- demux1, Bit[4] -- demux2

1:0

RW

0

des_i_sel_2 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reservedneldemux core registerdemux core 0 Final address = 0xc1105800 + offset * 4
demux core 1 Final address = 0xc1105940 + offset * 4
demux core 2 Final address = 0xc1105a80 + offset * 4
STB_VERSION_O 0x00
R/W

31:0

R

Default

Description

0x30003

The version of stbdker

Bit(s)

Bit(s)

R/W

Default

Description

31:0

RW

0xfe015aa5

Test register.

Default

Descriptionar

STB_TEST_REG_O 0x01

R/W

15

RW

0

fec_core_select 1 - select descramble output

14:12

RW

0

11

RW

0

FEC_CLK

10

RW

0

SOP

9

RW

0

D_VALID

8

RW

0

D_FAIL

7:0

RW

0

ut

Bit(s)H

FEC_INPUT_CONTROL_O 0x02

R/W

11

R

20

R

9

R

7:0

to

e

Description

0

FEC_CLK

0

SOP

0

VALID

R

0

FAIL

R

0

FEC DATAIN

Description

D

8

Defaultis

Bit(s)

D_DATA 7:0

trib

FEC_INPUT_DATA_O 0x03

fec_select 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File

DEMUX_CONTROL_O 0x04
Bit(s)

R/W

Default

31

RW

0

enable_free_clk_fec_data_valid

30

RW

0

enable_free_clk_stb_reg

29

RW

0

always_use_pes_package_length

28

RW

0

disable_pre_incomplete_section_fix

27

RW

0

pointer_field_multi_pre_en

26

RW

0

ignore_pre_incomplete_section

25

RW

0

video2_enable

24:22

RW

0

video2_type

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R/W

Default

Description

21

RW

0

do_not_trust_pes_package_length

20 (bit4)

RW

0

Bypass use recoder path19 (bit3)RW

0clear_PID_continuity_counter_valid

18 (bit2)

RW

0

Disable Splicing

17 (bit1)

RW

0

Insert PES_STRONG_SYNC in Audio PES

16 (bit0)RW

0Insert PES_STRONG_SYNC in Video PES

15

RW

0

do not trust section length

14

RW

0

om cmd push even zero

13

RW

0

set_buff_ready_even_not_busy

12

RW

0

SUB, OTHER PES interrupt at beginning of PES

11

RW

0

discard_av_package -- for ts_recorder use only

10

RW

0

ts_recorder_select 0:after PID filter 1:before PID filter

9

RW

0

ts_recorder_enable

8

RW

0

(table_id == 0xff) means section_end

7

RW

0

do not send uncomplete section

6

RW

0

do not discard duplicate package

5

RW

0

search SOP when trasport_error_indicator

4

RW

0

stb demux enable

3

RW

0

do not reset state machine on SOP

2

RW

0

search SOP when error happened ( when ignore_fail_n_sop, will have this case)

1

RW

0

do not use SOP input ( check FEC sync byte instead )

0

RW

0

ignore fec_error bit when non sop ( check error on SOP only)

R/W

Default

15:8

RW

187

demux package length - 1 ( default : 187 )

7:0

RW

0

default is 0x47e

R/W

Default

31:16

RW

0

15:0

RW

0

FM_WR_ADDR_O 0x07
Bit(s)

R/W

31:24

RW

Description

filter memory write data hi[31:16]
filter memory write data low [15:0]

tr
ib

Bit(s)

ut

FM_WR_DATA_O 0x06

Default

Description
advanced setting hi0advanced setting low

R0filter memory write data request

R0filter memory write addr

is

0

RW

D

7:0

ne

DescriptiontoBit(s)

15

dk
er

ar

H

FEC_SYNC_BYTE_O 0x05

23:16

l

Bit(s)

MAX_FM_COMP_ADDR_O 0x08
Bit(s)

R/W

Default

Description

13:8

R

0

demux state -- read only

7:4

RW

0

maxnum section filter compare address

3:0

RW

0

maxnum PID filter compare address

R/W

Default

TS_HEAD_0_O 0x09
Bit(s)

Description

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15

RW

0

transport_error_indicator

14

RW

0

payload_unit_start_indicator

13

RW

0

transport_priority

12:0

RW

0

PID

Bit(s)

R/W

Default

7:6

R
R

0

transport_scrambling_control

5:40

adaptation_field_control

3:0

R

0

continuity_counter

TS_HEAD_1_O 0x0a
Description

R/W

Default

15:12

R

Description0

om_cmd_count (read only)

11:9

R

0

overflow_count // bit 11:9 -- om_cmd_wr_ptr (read only)

8:6

R

0

om_overwrite_count // bit 8:6 -- om_cmd_rd_ptr (read only)

5:3

R

0

type_stb_om_w_rd (read only)

2

R

0

unit_start_stb_om_w_rd (read only)

1

R

0

om_cmd_overflow (read only)

0

R

0

om_cmd_pending (read)

0

R

0

om_cmd_read_finished (write)

R/W

Default

15:9

R

0

count_stb_om_w_rd (read only)

8:0

R

0

start_stb_om_wa_rd (read only)

0x0d
Default

11:0

R

0

Bit(s)

R/W

31:16

RW

15:0

RW

15:0

R/W

D

31:16

Default

Description

0base address for section buffer group 0 (*0x400 to get real address)

0base address for section buffer group 1 (*0x400 to get real address)

0x0f

is

SEC_BUFF_23_START_O

offset for section datatr
ib

SEC_BUFF_01_START_O 0x0e

Description

e

R/W

ut

Bit(s)

Bit(s)

DescriptiontoBit(s)

OM_CMD_DATA2_O

ar

H

OM_CMD_DATA_O 0x0cdker

Bit(s)nel

OM_CMD_STATUS_O 0x0b

Default

Description

RW

0base address for section buffer group 2 (*0x400 to get real address)

RW

0base address for section buffer group 3 (*0x400 to get real address)

SEC_BUFF_SIZE_O 0x10
Bit(s)

R/W

Default

Description

3:0

RW

0

section buffer size for group 0 (bitused, for example, 10 means 1K)

7:4

RW

0

section buffer size for group 1

11:8

RW

0

section buffer size for group 2

15:12

RW

0

section buffer size for group 3

SEC_BUFF_BUSY_O 0x11

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Bit(s)

R/W

Default

31:0

R

0

Description

Section buffer busy status for buff 31:0 (Read Only)

SEC_BUFF_READY_O 0x12
Bit(s)

R/W

31:0

Default

RW

0

Description

section buffer write status for buff 31:0 -- Readclear buffer status ( buff READY and BUSY ) – write

SEC_BUFF_NUMBER_O 0x13
R/W

Default

Description

4:0

RW

0

SEC_BUFFER_INDEX RW

12:8

RW

0

SEC_BUFFER_NUMBER for the INDEX buffer Read_Only

14

RW

0

output_section_buffer_valid

15

RW

0

section_reset_busy (Read Only)nelBit(s)

Bit(s)

R/W

Default

9:5

RW

0

BYPASS PID number

4:0

RW

0

PCR PID number

dker

ASSIGN_PID_NUMBER_O 0x14
Descriptionar

VIDEO_STREAM_ID_O 0x15
R/W

Default

Description

31:16

RW

0

for video2

15:0

RW

0

stream_id filter Bit(s) enable

0x16

R/W

Default

Description

15:0

RW

0

For audio

0x17
R/W

Default

15:0

RW

0

OTHER_STREAM_ID_O

Description
For subtr
ib

Bit(s)ut

SUB_STREAM_ID_OeBit(s)

0x18

R/W

Default

Description

15:0

RW

0

For other

R/W

Default

Description

RW

0

PCR_ENRW

0

PCR90K_DIV

Bit(s)

R/W

Default

Description

31:0

RW

0

12

0x19

D

Bit(s)isBit(s)

PCR90K_CTL_O

to

AUDIO_STREAM_ID_O

H

Bit(s)

11:0

PCR_DEMUX_O 0x1a

VIDEO_PTS_DEMUX_O

PCR

0x1b

Bit(s)

R/W

Default

31:0

RW

0

Description

VPTS

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VIDEO_DTS_DEMUX_O 0x1c
Bit(s)

R/W

Default

31:0

RW

0

Description

VDTS

AUDIO_PTS_DEMUX_O 0x1d
Bit(s)

R/W

Default

31:0

RW

0

SUB_PTS_DEMUX_O

Description

APTS

0x1e
R/W

Default

31:0

RW

0

Description

SPTS

l

Bit(s)

Description

15

R
R

0

SUB_PTS[32]140

AUDIO_PTS[32]

13

R

0

VIDEO_DTS[32]

12

R

0

VIDEO_PTS[32]

3

R

0

sub_pts_ready

2

R

0

audio_pts_ready

1

R

0

video_dts_ready

0

R

0

video_pts_ready

STB_DEBUG_INDEX_O

dker

Default

ar

R/W

H

Bit(s)ne

STB_PTS_DTS_STATUS_O 0x1f

0x20
R/W

Default3

RW0

pes_ctr_byte[7:0], pes_flag_byte[7:0]

2

RW

0

pes_package_bytes_left[15:0]

1

RW

0

stream_id[7:0], pes_header_bytes_left[7:0]

0

RW

0

adaptation_field_length[7:0], adaption_field_byte_1[7:0]

R/W

15:0

R

STB_MOM_CTL_Oe

Debug data out[15:0]

Default0

no_match_record_en

RW0

reserved

D

Description

RW
RW

0

MAX OM DMA COUNT (default: 0x40)

RW

0LAST ADDR OF OM ADDR (default: 127)

30:16
8:0

Description

0x22
R/W

31
15:9

0

is

Bit(s)

Defaulttrib

Bit(s)ut

STB_DEBUG_DATAOUT_O 0x21

DescriptiontoBit(s)

STB_INT_STATUS_O

0x23

Bit(s)

R/W

Default

Description

12

R
R

0

INPUT_TIME_OUT

110

PCR_ready

10

R

0

audio_splicing_point

9

R

0

video_splicing_point

8

R

0

other_PES_int

7

R

0

sub_PES_int

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Bit(s)

R/W

Default

Description

6

R

0

discontinuity

5

R

0

duplicated_pack_found

4

R

0

New PDTS ready

3

R

0

om_cmd_buffer ready for access

2

R

0

section buffer ready

1

R

0

transport_error_indicator

0

R

0

TS ERROR PIN

Description

R/W

Default

23:21

RW

0

demux om write endian control for OTHER_PES_PACKET

20:18

RW

0

demux om write endian control for SCR_ONLY_PACKET

17:15

RW

0

demux om write endian control for SUB_PACKET

14:12

RW

0

demux om write endian control for AUDIO_PACKET

11:9

RW

0

demux om write endian control for VIDEO_PACKET

8:6

RW

0

demux om write endian control for else

5:3

RW

0

demux om write endian control for bypass

2:0

RW

0

demux om write endian control for section

Bit(s)

R/W

Default

15:8

RW

0

last_burst_threshold

7

RW

0

use hi_bsf interface

6:2

RW

0

fec_clk_div

1

RW

0

ts_source_sel

0

RW

0

Hiu TS generate enable

15:0

RW

0

R/W

11

RW

10

RW

8
7
6:0

Default

Description0

mask bit for OTHER_PES_AHB_DMA_EN

0mask bit for SUB_AHB_DMA_EN

RW

0mask bit for BYPASS_AHB_DMA_EN

RW

0mask bit for SECTION_AHB_DMA_EN

RW

0mask bit for recoder stream

RW

0mask bit for each typeis9base address for section buffer start (*0x10000 to get real base)D

Bit(s)

Descriptiontrib

DEMUX_MEM_REQ_EN_O 0x27eDefault

ut

R/W

H

Description

SEC_BUFF_BASE_O 0x26
Bit(s)

ar

0x25

to

TS_HIU_CTL_Odker

Bit(s)

l

0x24

ne

DEMUX_ENDIAN_O

VIDEO_PDTS_WR_PTR_O 0x28
Bit(s)

R/W

Default

31:0

RW

0

Description

vb_wr_ptr for video PDTS

AUDIO_PDTS_WR_PTR_O 0x29
Bit(s)

R/W

Default

31:0

RW

0

Description

ab_wr_ptr for video PDTS

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SUB_WR_PTR_O 0x2a
Bit(s)

R/W

Default

20:0

RW

0

Bit(s)

R/W

Default

19:0

RW

0

SB_START_O

Description
SB_WRITE_PTR (sb_wr_ptr << 3 == byte write position)

0x2b
Description
SB_START (sb_start << 12 == byte address);

SB_LAST_ADDR_O 0x2c
R/W

Default

20:0

RW

0

Description
SB_SIZE (sb_size << 3 == byte size, 16M maximun)nelBit(s)

SB_PES_WR_PTR_O 0x2d
R/W

Default

31:0

RW

0

Description
sb_wr_ptr for sub PES

dker

Bit(s)OTHER_WR_PTR_O 0x2e
R/W

Default

31:21

RW

0

ob_wr_ptr for other PES

20:0

RW

0

OB_WRITE_PTR (ob_wr_ptr << 3 == byte write position)

Bit(s)

R/W

Default

19:0

RW

0

Description

OB_START (ob_start << 12 == byte address);

OB_LAST_ADDR_O 0x30
Default

20:0

RW

0

OB_PES_WR_PTR_O 0x31
R/W

31:0

RW

STB_INT_MASK_O 0x32

0Default

is

9

R/W

Description

ob_wr_ptr for sub PES

Description

RW

0

splicing_point

RW

0other_PES_int

RW

0

sub_PES_int

6D

Bit(s)

Default

OB_SIZE (ob_size << 3 == byte size, 16M maximun)tribBit(s)

Description

e

R/W

ut

Bit(s)

H

0x2f

to

OB_START_O

DescriptionarBit(s)

RW

0

discontinuity

5

RW

0

duplicated_pack_found

4

RW

0

New PDTS ready

3

RW

0

om_cmd_buffer ready for access

2

RW

0

section buffer ready

1

RW

0

transport_error_indicator

0

RW

0

TS ERROR PIN

Description

8
7

VIDEO_SPLICING_CTL_O 0x33
Bit(s)

R/W

Default

15

RW

0

splicing VIDEO PID change enable

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Bit(s)

R/W

Default

Description

14:10

RW

0

VIDEO PID FILTER ADDRESS

9

RW

0

PES splicing active (Read Only)

8

RW

0

splicing active (Read Only)

7:0

RW

0

splicing countdown (Read Only)

AUDIO_SPLICING_CTL_O 0x34
R/W

Default

Description

15

RW

0

splicing AUDIO PID change enable

14:10

RW

0

AUDIO PID FILTER ADDRESS

9

RW

0

PES splicing active (Read Only)

8

RW

0

splicing active (Read Only)

7:0

RW

0

splicing countdown (Read Only)nelBit(s)

TS_PACKAGE_BYTE_COUNT_O 0x35
R/W

Default

23:16

RW

0

M2TS_SKIP_BYTES

15:8

RW

0

LAST TS PACKAGE BYTE COUNT (Read Only)

7:0

RW

0

PACKAGE BYTE COUNT (Read Only)

PES_STRONG_SYNC_O 0x36
R/W

Default

15:0

RW

0

Description
2 bytes strong sync add to PESH

Bit(s)OM_DATA_RD_ADDR_O 0x37
R/W

Default

Description

15

RW

0

stb_om_ren

14:11

RW

0

reserved

10:0

RW

0

OM_DATA_RD_ADDR

15:0

RW

Defaulte

Description

tr
ib

R/W

ut

OM_DATA_RD_O 0x38

toBit(s)

Bit(s)ar

DescriptiondkerBit(s)

0

OM_DATA_RD

Default

Description

SECTION_AUTO_STOP_3_O 0x39
31

RW

0

Auto stop count 31 Wr_en

RW0

Auto stop count 31

RW

Auto stop count 30 Wr_en

D

30:28

R/W

is

Bit(s)

0RW

0Auto stop count 30

23

RW

0

Auto stop count 29 Wr_en

22:20

RW

0

Auto stop count 29

19

RW

0

Auto stop count 28 Wr_en

18:16

RW

0

Auto stop count 28

15

RW

0

Auto stop count 27 Wr_en

14:12

RW

0

Auto stop count 27

11

RW

0

Auto stop count 26 Wr_en

10:8

RW

0

Auto stop count 26

7

RW

0

Auto stop count 25 Wr_en

27
26:24

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Bit(s)

R/W

Default

Description

6:4

RW

0

Auto stop count 25

3

RW

0

Auto stop count 24 Wr_en

2:0

RW

0

Auto stop count 24

SECTION_AUTO_STOP_2_O 0x3a
R/W

Default

Description

31

RW

0

Auto stop count 23 Wr_en

30:28

RW

0

Auto stop count 23

27

RW

0

Auto stop count 22 Wr_en

26:24

RW

0

Auto stop count 22

23

RW

0

Auto stop count 21 Wr_en

22:20

RW

0

Auto stop count 21

19

RW

0

Auto stop count 20 Wr_en

18:16

RW

0

Auto stop count 20

15

RW

0

Auto stop count 19 Wr_en

14:12

RW

0

Auto stop count 19

11

RW

0

Auto stop count 18 Wr_en

10:8

RW

0

Auto stop count 18

7

RW

0

Auto stop count 17 Wr_en

6:4

RW

0

Auto stop count 17

3

RW

0

Auto stop count 16 Wr_en

2:0

RW

0

Auto stop count 16

R/W

Default

31

RW

0

Auto stop count 15 Wr_en

30:28

RW

0

Auto stop count 15

27

RW

0

Auto stop count 14 Wr_en

26:24

RW

0

Auto stop count 14

23

RW

0

22:20

RW

0

19

RW

18:16

RW

15

RW

14:12

RW

7
6:4

dk
er

e

ut

Auto stop count 13 Wr_entribAuto stop count 13

0

Auto stop count 12 Wr_en0

Auto stop count 12

0

Auto stop count 11 Wr_en
Auto stop count 11

0

Auto stop count 10 Wr_en

RW0

Auto stop count 10

RW

0

Auto stop count 9 Wr_en

is

0

RW

D

10:8

to

Bit(s)11

ar

H

SECTION_AUTO_STOP_1_O 0x3b
DescriptionnelBit(s)

RW

0

Auto stop count 9

3

RW

0

Auto stop count 8 Wr_en

2:0

RW

0

Auto stop count 8

SECTION_AUTO_STOP_0_O 0x3c
Bit(s)

R/W

Default

Description

31

RW

0

Auto stop count 7 Wr_en

30:28

RW

0

Auto stop count 7

27

RW

0

Auto stop count 6 Wr_en

26:24

RW

0

Auto stop count 6

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R/W

Default

Description

23

RW

0

Auto stop count 5 Wr_en

22:20

RW

0

Auto stop count 5

19

RW

0

Auto stop count 4 Wr_en

18:16

RW

0

Auto stop count 4

15

RW

0

Auto stop count 3 Wr_en

14:12

RW

0

Auto stop count 3

11

RW

0

Auto stop count 2 Wr_en

10:8

RW

0

Auto stop count 2

7

RW

0

Auto stop count 1 Wr_en

6:4

RW

0

Auto stop count 1

3

RW

0

Auto stop count 0 Wr_en

2:0

RW

0

Auto stop count 0nelBit(s)

Bit(s)

R/W

Default

31:0

R

0

Description

Bit 31:0 reset channel status - Each Bit reset each channel

DEMUX_SCRAMBLING_STATE_O 0x3e
R/W

Default

31:0

R

0

Description

Scrambling state of each channelarBit(s)

Default

31:0

R

0

DEMUX_STAMP_CTL_O

Description

Channel activity of each channel

0x40

Bit(s)

R/W

Default

4

RW

0

video_stamp_use_dts

3

RW

0

audio_stamp_sync_1_en

2

RW

0

1

RW

0

0

RW

ut

e

Description

to

R/W

H

DEMUX_CHANNEL_ACTIVITY_O 0x3f
Bit(s)dk
er

DEMUX_CHANNEL_RESET_O 0x3d

audio_stamp_insert_entrib

video_stamp_sync_1_en0video_stamp_insert_en

DEMUX_VIDEO_STAMP_SYNC_0_O 0x41
Default

RW

0

Bit(s)

D

31:0

R/W

is

Bit(s)

R/W

Default

31:0

RW

0

Description

Video stamp sync [63:32]

DEMUX_VIDEO_STAMP_SYNC_1_O 0x42

DEMUX_AUDIO_STAMP_SYNC_0_O
Bit(s)

R/W

Default

31:0

RW

0

DEMUX_AUDIO_STAMP_SYNC_1_O
Bit(s)

R/W

Default

31:0

RW

0

Description

Video stamp sync [31:0]
0x43
Description

Aideo stamp sync [63:32]
0x44
Description

Aideo stamp sync [31:0]

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Revision 1.1.4

DEMUX_SECTION_RESET_O
Bit(s)

0x45

R/W

31:0

Default

R

Description

Write : Bit[4:0] secter filter number for reset Read : select according to
output_section_buffer_valid: per bit per section buffer valid status or
section_buffer_ignore

0

DEMUX_INPUT_TIMEOUT_C_O

0x46

Bit(s)

R/W

Default

31:0

RW

0

Description

channel_reset_timeout_disable

DEMUX_INPUT_TIMEOUT_O 0x47
R/W

Default

Description

31

RW

0

no_match_reset_timeout_disable

30:0

RW

0

input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-countBit(s)

R/W

Default

31:0

RW

0

Description

channel_packet_count_disable

R/W

Default

31

RW0

no_match_packet_count_disable

30:0

RW

0

input_packet_count

31:0

RW

Default

31:0

RW

0x4b
Default
0xffffffff

ne

Description

channel_process_enable

tr
ib

R/W

channel_record_enable

0xffffffff

DEMUX_CHAN_PROCESS_EN_O
Bit(s)

Description

e

R/W

ut

Bit(s)

0x4a

to

DEMUX_CHAN_RECORD_EN_O

DescriptionH

Bit(s)ar

DEMUX_PACKET_COUNT_C_O 0x49

dker

DEMUX_PACKET_COUNT_O 0x48l

Bit(s)DEMUX_SMALL_SEC_CTL_O 0x4c
Bit(s)

R/W

31:24

RW

23:16

RW

1
0

Description
small_sec_size ((n+1) * 256 Bytes)

0

small_sec_rd_ptr

RW0

small_sec_wr_ptr

RW0

reserved

RW

0

small_sec_wr_ptr_wr_enable

RW0

small_section_enable

is

0

D

15:8
7:2

Default

DVP Register
Final Address = 0xd0048000 + offset *4
Write Register
CTRL 0x00

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Revision 1.1.4

Bit(s)

Name

Description

31

Soft_reset

The reset of all bt656 module30

syncfifo_soft_reset_n_sys

The reset of syncfifo output

29

syncfifo_soft_reset_n_bt

The reset of syncfifo input

28

Syncfifo_reset
raw_isp

1: use 1 port send raw data;

vs_to_viu_sel/

0:sof;1:eof;2:vbi_start;3:vbi_end;

vs_to_isp_sel
hs_to_viu_sel/[24:23]0:eav;1:sav;2:eol;3:sol

hs_to_isp_sel

22

camera_mode

Go to camera state.

[21:18]Eol_delay

Eol =vdo_en’s negedge[delay]

16

update_st_ctl

15color_repeat

14:13

video_mode

0:YCbCr;1:565RGB;

12

auto_fmt

Go to ntsc/pal state and auto check.

11

prog_mode

Go to DVP state.

Update all status register by:
0:eof/1:sof.
Format select of YCbCr422 to YCbCr444.

dker

Input format and output format.

l[26:25]ne27

The reset of syncfifo all
0: use 3 port send raw data;

2:1byte raw

Gate enable of sys_clk.

Sys_clk_en

need set 1 at first

H

9

ar

10

8
bt_clk_en

6

clk27_phase5

auto_cover_error

toGate enable of clkin

7

need set 1 at first
Reverse of clk27.
Reset after error occurs.

2

ref_mode1

Bt_mode0bt_data_en

VBIST 0x01

D

Bit(s)[12:0]

Auto check for: 0:pal,1:ntsc
Use data or port control
1: normal pasl/ntsc; 0: programe
Enable of input

Name

Description

vbi0_start

The line number when vblanking started.

isBit(s)[12:0]VBIEND 0x02

ut

Fmt_mode

tr
ib

3

e

4

Name

Description

vbi0_end

The line number when vblanking finished.

LINECTRL 0x04
Bit(s)

Name

Description
0: control by vs/hs/field;[31]

soft_video_active[30:16]hend

The end of active pixel[14:0]

hoffsetThe start of active pixel

1: control by cnt and sw;

AVST 0x05

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Revision 1.1.4

Bit(s)

Name

Description[28:16]

video1_start

The start of active line, field1[12:0]

video0_start

The start of active line, field0

AVEND 0x06
Bit(s)

Name

Description[28:16]

video1_end

The end of active line, field1[12:0]

video0_end

The end of active line, field0

Name

Description

PORT_CTRL 0x09
Bit(s)

Pd_memPower down the memory27

Vdo_rdy_bypass_eav

1: bypass eav for vdo_rdy

26

data_endian25

clk_inv_sel

Reverse clk in

24

dual_edge_clk_en

Use dual edge clock23

port_active_hmode22

vref_fro_vs_only21

fid_hsvs_falling

0: afifo_wdata = {data1,data2}

dker

1: afifo_wdata = {data2,data1}ne[29:28]l[31:30]

0: active data when hsync is low;

1: active data when hsync is high;0: use reference reverse vblank；ar1：use vsync reverse vblank;
For 601 format:

0: do not use falling edge of vsync

H

1:use falling edge of vsync
For 601 format:

fid_hsvs_rising

fid_hsvs_pcnt

bt_10bto8b

tr
ib

9

8

bt_d8bidq_phase6

idq_en

is

7

[3:2]

fid_hsvs

D

5
4

ut

e

19

0: do not use rising edge of vsync

to20

1:use rising edge of vsync
For 601 format:
0：use hs/vs generate field；

1：use pixel cnt generate field;
When use 8Bits data port:
0：[9:2]；
1：[9:2] + [1]；0：use 10Bits data port；
1：use 8Bits data port;
Reverse de port
Enable de port
For 601 format:
0: use hs/vs generate fid;
1: use field port directly;

fid_phase

Reverse field port

1

vsync_phase

Reverse vsync port0hsync_phase

Reverse hsync port

SWAP_CTRL 0x0a
Bit(s)

Name

Description[14:12]

y1 sel

Y1 poistion[10:8]

cr0 selCr0 poistion[6:4]

y0 sel

Y0 poistion[2:0]

cb0 selCb0 poistion

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Revision 1.1.4

RAW_CTRL 0x13
Bit(s)

Name

Description[11:9]

pixel_even,line_even[r,g,b] output select[8:6]

pixel_even,line_odd[r,g,b] output select[5:3]

pixel_odd,line_even[r,g,b] output select[2:0]

pixel_odd,line_odd[r,g,b] output selectBit(s)

Name

Description[30:16]

even_field_cnt_max[14:0]

even_field_cnt_min

C601_CTRL0 0x0e

Name
top_field_cnt_left_max

Description[14:0]

top_field_cnt_left_mindkerBit(s)[30:16]

C601_CTRL2 0x10
Name
field_det_close_max[14:0]

top_field_cnt_right

DescriptionarBit(s)[21:16]

Vsync4[22:20]Fid[18:16]

Vsync3[14:12]

Vsync2
Vsync1[6:4]

Hsync2[2:0]

Hsync1tr
ib[10:8]

4
3

D

Bit(s)isInterrupt Register
INTEN 0x15

to

[26:24]

Descriptione

Name
Vsync5ut

Bit(s)H

DELAY_CTRL 0x1d
[30:28]nel

C601_CTRL1 0x0f

Name

Description

sof_int_en

Interrupt after sof

eof_int_en

Interrupt after eof

1btin_ov_int_en

Interrupt after sync_fifo overflow

0

bt_error_int_en

Interrupt after error

Bit(s)

Name

Description[28:16]

max_line_cnt

When line number bigger than it, will generate an error[14:0]

max_pix_cnt

When pixel number bigger than it, will generate an error

ERRCNT 0x19

STATUS 0x14

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Revision 1.1.4

Bit(s)

Name

Description

14

fmt_stDetect result of Pal/Ntsc mode

13

field_st

The field of current one

12

pre_field_st

The field of last one

9

sof_int_st

to 1 after interrupt occurs, to 0 after write This bit

8

eof_int_st

to 1 after interrupt occurs, to 0 after write This bit

7

btin_ov_st

to 1 after interrupt occurs, to 0 after write This bit

6

lcnt_error_st

to 1 after interrupt occurs, to 0 after write This bit

5

dcnt_error_st

to 1 after interrupt occurs, to 0 after write This bit

4

error_stto 1 after interrupt occurs, to 0 after write This bit[3:0]

bt_state

The state of fsm

Bit(s)

Name

Description[12:0]

vline_num

Line number in one field[31:15]

11

VLINE

0x17

Description

Accumulated of Y

H

Name
field_luma

Bit(s)

Name[30:16]

dcnt_max[14:0]

dcnt_minto

0x1a

Description

The maximum input counter in one line
The minimum input counter in one line

e

LCNT

Bit(s)ar

LUMA 0x12[31:0]

nedk
er

Read Register

l

10

Name
pcnt_max[14:0]

pcnt_mintribBit(s)[30:16]ut

PCNT 0x1c

Description
The maximum pixel counter in one line
The minimum pixel counter in one lineis29. Video Output

D

this section ion describes S905’s VPU sub-module, including CVBS sub-module.

29.1 CVBS

S905 supports CVBS 480i/576i standard definition output.
Register Definition
LCD Registers
L_Gamma Control
L_GAMMA_CNTL_PORT

0x1400124/336

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S905 Datasheet

Bit(s)
7
6
5
4
3
2
1
0

Revision 1.1.4

Field NameGAMMA_VCOM_POL
GAMMA_RVS_OUT
ADR_RDY
WR_RDY
RD_RDYGAMMA_TR
GAMMA_SETGAMMA_EN

L_GAMMA_DATA_PORT

Default
0
0
0
0
0
0
0
0

Description
Reverse VCOM Polarity
GAMMA DATA REVERSE OUTPUT FOLLOWING VCOMGAMMA ADDR PORT Is Ready for access
GAMMA DATA PORT IS RDY to Write
GAMMA DATA PORT IS RDY to Read
RGB10-->RGB8 using Trancate or Round off
Gamma turn on syncing with Vsync
Gamma Enable

R/W-

Default
0

Description
GAMMA DATA PORT ADDR, all gamma data read/write
operation is via this port

Default
0
0
0
0
0
0

Description
GAMMA is READY for Host to read/write
BURST MODE *GAMMA R Selected
GAMMA G Selected
GAMMA B Selected
GAMMA ADDR.

0x1401

Field NameGAMMA_DATA_PORT

Bit(s)
12
11
10
9
8
7:0

VCBUS: 0x1402

Field Name
H-RD
H-AUTO_INC
H_SEL_R
H_SEL_G
H_SEL_B
HADR

R/W
R/W
R/W
R/W
R/W
R/W
W

dk
er

L_GAMMA_ADDR_PORTnelBit(s)
15:0

R/W
R/W
R/W
R
R
R
R/W
R/W
R/W

0x1403H

L_GAMMA_VCOM_HSWITCH_ADDRar*NOTE:: When Programming the Gamma with Burst Mode, please turn off the IRQ service (Or make sure the IRQ service task
have no Gamma programming operation)

Field Name

R/W

Default

Description

12:0

GAMMA_VCOM_HSWITCH_ADDR

R/W

0Horizontal Switch Point for VCOM with Gamma

R/W

Default

Description

R/W

0

RGB Converter OFFSET

R/W

Default

Description

R/W

0

RGB Converter SCALE

Bit(s)

Field Name

9:0

RGB_BASE_ADDR

L_RGB_COEFF_ADDR

0x1406

Field Name

10:0

RGB_COEFF_ADDR

0x1407

Field Name

R/W

Default

Description

15:14

DCLK_SEL

R/W

0

DCLK output

11

TCON_VSYNC_SEL_DVI

R/W

0

TCON_HSYNC_SEL_DVI

R/W

0

9

TCON_DE_SEL_DVI

R/W

0

8

CPH3_POL

R/W

0

VSYNC generated by TCON for RGB format DVI output(support Digital LCD interface)
HSYNC generated by TCON for RGB format DVI output(support Digital LCD interface)
DE generated by TCON for RGB format DVI output(support Digital LCD interface)
CPH3 Polarity Control

7

CPH2_POL

R/W

0

CPH2 Polarity Control

6

CPH1_POL

R/W

0

CPH1 Polarity Control

5

TCON_DE_SEL

R/W

0

DE Generate by TCON

4

TCON_VS_SEL

R/W

0

Vsync Generate by TCON

3

TCON_HS_SEL

R/W

0

Hsync Generate by TCON

10

D

Bit(s)

is

L_POL_CNTL_ADDRtrib

Bit(s)e

0x1405ut

L_RGB_BASE_ADDR

to

Bit(s)

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Revision 1.1.4

Bit(s)

Field Name

R/W

Default

Description

2

DE_POL

R/W

0

De polarity control

1

VS_POL

R/W

0

Vsync polarity control

0

HS_POL

R/W

0

Hsync polarity control

L_DITH_CNTL_ADDR

0x1408Field Name

R/W

Default

Description

13

DITH_R5

R/W

0

12

DITH_G5

R/W

0

11

DITH_B5

R/W

0

10

DITH10_EN

R/W

01=use the current dithering to dither input 10-bit R
down to 5-bit . Applicable only if both dith10_en &dith8_en = 1, otherwise no effect
1=use the current dithering to dither input 10-bit G
down to 5-bit . Applicable only if both dith10_en &dith8_en = 1, otherwise no effect
1=use the current dithering to dither input 10-bit B
down to 5-bit . Applicable only if both dith10_en &dith8_en = 1, otherwise no effect10-bits Dithering to 8 Bits Enable9

DITH8_EN

R/W

08-bits Dithering to 6 Bits Enable

8

DITH_MD

R/W

0

Dithering Mode select

7:4

DITH8_CNTL

R/W

08-bits Dithering control

3:0

DITH10_CNTL

R/W

010-bits Dithering control

ne

dk
er

ar

0x1409Field Name

R/W

1

HIGHLIGHT_EN

R/W

0

PROBE_EN

Default

Description

00x140aBit(s)

Field Name

15:0

GAMMA_PROBE_COLOR_L

R/W

0

R/W

Default

DescriptionR0

Probe_pix[15:0]

0x140btr
ib

L_GAMMA_PROBE_COLOR_H

ut

L_GAMMA_PROBE_COLOR_LetoBit(s)H

L_GAMMA_PROBE_CTRLlBit(s)

Field Name

R/W

Default

Description

15

PROBE_PIX_V

R

0probe_pix_v

14reserveR0reserve

13:0

GAMMA_PROBE_COLOR_H

R

0

Probe_pix[29:16]

Field Name

R/W

Default

Description

GAMMA_PROBE_HL_COLOR

R

0

5:6:5 colorDisBit(s)

L_GAMMA_PROBE_HL_COLOR

0x140c

L_GAMMA_PROBE_POS_X

0x140dBit(s)
15:0

Bit(s)

Field Name

R/W

Default

Description

12:0

GAMMA_PROBE_POS_X

R/W

0

Pos_x

L_GAMMA_PROBE_POS_Y

0x140eBit(s)

Field Name

R/W

Default

Description

12:0

GAMMA_PROBE_POS_Y

R/W

0

Pos_y

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Revision 1.1.4

L_TCON Control
L_STH1_HS_ADDR

0x1410Bit(s)

Field Name

R/W

Default

Description

12:0

STH1_HS_ADDR

R/W

0

STH1 Horizontal Start

L_STH1_HE_ADDR

0x1411Bit(s)

Field Name

R/W

Default

Description

12:0

STH1_HE_ADDR

R/W

0

STH1 Horizontal End

Field Name

R/W

Default

Description

12:0

STH1_VS_ADDR

R/W

0

STH1 Vertical Start

L_STH1_VE_ADDR

0x1413

Field Name

R/W

Default

Description

12:0

STH1_VE_ADDR

R/W

0

STH1 Vertical End

L_STH2_HS_ADDR

0x1414dkerBit(s)

Field Name

R/W

Default

Description

12:0

STH2_HS_ADDR

R/W

0

STH2 Horizontal Start

Default

Description

0

STH2 Horizontal End

R/W

12:0

STH2_HE_ADDR

R/W

0x141612:0

STH2_VS_ADDR

R/W

Default

Description

R/W

0

STH2 Vertical Start

R/W

Default

Description

R/W

0

STH2 Vertical End

R/W

Default

Description

R/W

0

OEH Horizontal Start

Field Name

R/W

Default

Description

OEH_HE_ADDR

R/W

0OEH Horizontal End

L_STH2_VE_ADDR

0x1417

Field Name

12:0

STH2_VE_ADDR

L_OEH_HS_ADDRtrib

Bit(s)

0x1418Field Name

12:0

OEH_HS_ADDR

0x1419

D

12:0

is

Bit(s)

Bit(s)

L_OEH_VS_ADDReField Nameut

Bit(s)

L_OEH_HE_ADDR

toField Name

H

0x1415Bit(s)

L_STH2_VS_ADDR

ar

Bit(s)

L_STH2_HE_ADDR

0x141aBit(s)

Field Name

R/W

Default

Description

12:0

OEH_VS_ADDR

R/W

0OEH Vertical Start

L_OEH_VE_ADDRl0x1412Bit(s)

ne

L_STH1_VS_ADDR

0x141bBit(s)

Field Name

R/W

Default

Description

12:0

OEH_VE_ADDR

R/W

0OEH Vertical End

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Revision 1.1.4

L_VCOM_HSWITCH_ADDR

0x141cBit(s)

Field Name

R/W

Default

Description

12:0

VCOM_HSWITCH_ADDR

R/W

0VCOM Horizontal Switch Point

L_VCOM_VS_ADDR

0x141dBit(s)

Field Name

R/W

Default

Description

12:0

VCOM_VS_ADDR

R/W

0VCOM Vertical Startl0x141eField Name

R/W

Default

Description

12:0

VCOM_VE_ADDR

R/W

0VCOM Vertical End

L_CPV1_HS_ADDR

0x141fdkerBit(s)

Field Name

R/W

Default

Description

12:0

CPV1_HS_ADDR

R/W

0

CPV1 Horizontal Start

0x1420ar

Bit(s)

L_CPV1_HE_ADDR

Field Name

R/W

Default

Description

12:0

CPV1_HE_ADDR

R/W

0

CPV1 Horizontal End

12:0

CPV1_VS_ADDR

R/W

Default

Description

R/W

0

CPV1 Vertical Start

R/W

Default

Description

R/W

0

CPV1 Vertical End

R/W

Default

Description

R/W

0

CPV2 Horizontal Start

Field Name

R/W

Default

Description

CPV2_HE_ADDR

R/W

0CPV2 Horizontal End

0x1422

Field Name

12:0

CPV1_VE_ADDR

L_CPV2_HS_ADDRtrib

Bit(s)

0x1423

Field Name

12:0

CPV2_HS_ADDR

12:00x1424D

Bit(s)isBit(s)

L_CPV2_HE_ADDR

L_CPV2_VS_ADDR

ut

L_CPV1_VE_ADDReField Nameto0x1421Bit(s)H

Bit(s)

L_CPV1_VS_ADDR

0x1425Bit(s)

Field Name

R/W

Default

Description

12:0

CPV2_VS_ADDR

R/W

0CPV2 Vertical Start

L_CPV2_VE_ADDR

0x1426Bit(s)

Field Name

R/W

Default

Description

12:0

CPV2_VE_ADDR

R/W

0CPV2 Vertical End

L_STV1_HS_ADDR

ne

L_VCOM_VE_ADDR

0x1427

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Revision 1.1.4

Bit(s)

Field Name

R/W

Default

Description

12:0

STV1_HS_ADDR

R/W

0

STV1 Horizontal Start

L_STV1_HE_ADDR

0x1428Bit(s)

Field Name

R/W

Default

Description

12:0

STV1_HE_ADDR

R/W

0

STV1 Horizontal End

L_STV1_VS_ADDR

0x1429Bit(s)

Field Name

R/W

Default

Description

12:0

STV1_VS_ADDR

R/W

0

STV1 Vertical Start

Bit(s)

Field Name

R/W

Default

Description

12:0

STV1_VE_ADDR

R/W

0

STV1 Vertical End

0x142bdk
er

L_STV2_HS_ADDR
Bit(s)

Field Name

R/W

Default

Description

12:0

STV2_HS_ADDR

R/W

0

STV2 Horizontal Start

L_STV2_HE_ADDR

0x142cField Name

R/W

Default

Description

12:0

STV2_HE_ADDR

R/W

0

STV2 Horizontal End

Field Name

R/W

12:0

STV2_VS_ADDR

R/W

L_STV2_VE_ADDR

0x142e
STV2_VE_ADDR

Default

Description0

STV2 Vertical End

R/W

Default

Description

R/W

0

OEV1 Horizontal Start

R/W

Default

Description

R/W

0

OEV1 Horizontal End

Field Name

R/W

Default

Description

OEV1_VS_ADDR

R/W

0

OEV1 Vertical Start

0x142fField Name

12:0

OEV1_HS_ADDR

L_OEV1_HE_ADDRtrib

Bit(s)

0x1430Field Name

12:0

OEV1_HE_ADDR

D

isBit(s)

L_OEV1_VS_ADDR
12:0

STV2 Vertical Start

R/W

L_OEV1_HS_ADDR

Bit(s)

Description

0

R/W

L_OEV1_VE_ADDReField Name

12:0

ut

Bit(s)

DefaulttoBit(s)

H

0x142darBit(s)

L_STV2_VS_ADDR

0x14310x1432Bit(s)

Field Name

R/W

Default

Description

12:0

OEV1_VE_ADDR

R/W

0

OEV1 Vertical End

L_OEV2_HS_ADDRl0x142ane

L_STV1_VE_ADDR

0x1433Bit(s)

Field Name

R/W

Default

Description

12:0

OEV2_HS_ADDR

R/W

0

OEV2 Horizontal Start

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Revision 1.1.4

L_OEV2_HE_ADDR

0x1434Bit(s)

Field Name

R/W

Default

Description

12:0

OEV2_HE_ADDR

R/W

0

OEV2 Horizontal End

L_OEV2_VS_ADDR

0x1435Bit(s)

Field Name

R/W

Default

Description

12:0

OEV2_VS_ADDR

R/W

0

OEV2 Vertical Start

L_OEV2_VE_ADDR

0x1436Bit(s)

Field Name

R/W

Default

Description

12:0

OEV2_VE_ADDR

R/W

0

OEV2 Vertical End

l0x1437

Field Name

R/W

Default

Description

12:0

OEV3_HS_ADDR

R/W

0

OEV3 Horizontal Start

L_OEV3_HE_ADDR

0x1438dkerBit(s)

Bit(s)

Field Name

R/W

Default

Description

12:0

OEV3_HE_ADDR

R/W

0

OEV3 Horizontal End

0x1439ar

L_OEV3_VS_ADDR

Field Name

R/W

Default

Description

12:0

OEV3_VS_ADDR

R/W

0

OEV3 Vertical StartH

Bit(s)

0x143aBit(s)

Field Name

12:0

OEV3_VE_ADDR

R/W

0

OEV3 Vertical End

R/W

Default

Description

R/W

0

LCD VDD control

R/W

0

LCD VBL control

R/W

0

LCD GPIO control

R/W

Default

Description

R/W

0

LOW Count

Field Name

R/W

Default

Description

LCD_PWM0_HI_ADDR

R/W

0High CountLCD_VDD

4

LCD_VBL

3:0

LCD_GPIO

L_LCD_PWM0_LO_ADDR

ut

5

tr
ib

Field Namee0x143b ( Unused)

Bit(s)

0x143c ( Unused)

Field Name

12:0

LCD_PWM0_LO_ADDR

D

isBit(s)

L_LCD_PWM0_HI_ADDR

0x143d ( Unused)

L_LCD_PWM1_LO_ADDR

0x143e ( Unused)

12:0

Description

R/W

L_LCD_PWR_ADDR

Bit(s)

Default

to

L_OEV3_VE_ADDR

Bit(s)

Field Name

R/W

Default

Description

12:0

LCD_PWM0_LO_ADDR

R/W

0

LOW Count

L_LCD_PWM1_HI_ADDR

ne

L_OEV3_HS_ADDR

0x143f( Unused)

Bit(s)

Field Name

R/W

Default

Description

12:0

LCD_PWM0_HI_ADDR

R/W

0High Count

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S905 Datasheet

Revision 1.1.4

L_INV_CNT_ADDR

0x1440Bit(s)

Field Name

R/W

Default

Description

4

INV_EN

R/W

0

Invert data output Enable

3:0

INV_CNT

R/W

0

Invert data count define

L_TCON_MISC_SEL_ADDR

0x1441

Field Name

R/W

Default

Description

12

STH2_SEL

R/W

0

STH2 is Line signal

11

STH1_SEL

R/W

0

STH1 is Line Signal

10

OEH_SELR/W

0

OEH is Line Signal

9

VCOM_SEL

R/W

0

VCOM is Line Signal

8

DB_LINE_SW

R/W

0

VCOM switched double lines

7

CPV2_SEL

R/W

0

CPV2 is Line Signal

6

CPV1_SEL

R/W

0

CPV1 is Line Signal

5

STV2_SEL

R/W

1

STV2 is frame Signal

4

STV1_SEL

R/W

1

STV1 is frame Signal

3

OEV_UNITE

R/W

1

OEV3/2/1 look like one signal

2

OEV3_SEL

R/W

0

OEV3 is Line Signal

1

OEV2_SEL

R/W

0

OEV2 is Line Signal

0

OEV1_SEL

R/W

0

OEV1 is Line Signal

ne

dk
er

ar

0x1442H

L_DUAL_PORT_CNTL_ADDRl

Bit(s)

Bit(s)

Field Name

R/W

15

OUTPUT_YUV

R/W

14:12

IDF

R.W

0

11:9

ISF

R/W

0

8

LCD_ANALOG_SEL_CPH3

R/W

0

CPH3/INVT pin select7

LCD_ANALOG_3PHI_CLK_SEL

R/W

0

CPH3/2/1 Output 3 phases

6

LCD_LVDS_SEL54

R/W

0

5

LCD_LVDS_SEL27

R/W

0

4

LCD_TTL_SEL

R/W

0

3

DUAL_LVDS_EN

R/W

0

2

PORT_SWP

R/W

0

1

RGB_SWP

R/W

0

R/B Swapped in data path

0

BIT_SWP

R/W

0

Bit Swap in data path(7:00:7)

Bit(s)
15-0

R/W
R/W

Default
0

MLVDS_CLK_CTL1_LO
Bit(s)
31-30
24
23:0

R/W
R/W
R/W
R/W

R/W
W

to
e

Description

00x1443 (Unused in Athena)
Description
Ask Chen Shi

0x1444 (Unused)
Default
00
0

L_TCON_DOUBLE_CTL
Bit(s)
16

ut

tr
ib

is

D

MLVDS_CLK_CTL1_HI

Default

Description
Enable mlvds clocks
Mlvds_clk_half_delay
Mlvds_clk_pattern

0x1449Default
0

Description
tcon_double_reset

131/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Default
00

L_TCON_PATTERN_HI
R/W
R/W

0x144aDefault
0

L_TCON_PATTERN_LO
Bit(s)
15:0

R/W
R/W

0x144bDefault
0

LDIM_BL_ADDR_PORT
Bit(s)

Description
tcon_pattern[15:0]

0x144eField Name

R/W

Default

Description

LDIM_BL_ADDR_PORT

R/W

0

N/A

Field Name

R/W

Default

Description

LDIM_BL_DATA_PORT

R/W

0

N/A

LDIM_BL_DATA_PORT
Bit(s)

Description
tcon_pattern[31:16]

L_DE_HS_ADDR

0x144f0x1451lBit(s)
15:0

Description
tcon_double_ini
tcon_double_inv

ne

R/W
R/W
R/w

dk
er

Bit(s)
15:8
7:0

Revision 1.1.4

Field Name

R/W

Default

Description

15:14

enable_tcon_double[7:6]R/W0enable_tcon_double[7:6]

12:0

de_hs

R/W

0

H

0x1452
Field Name

15:14

enable_tcon_double[5:4]

12:0

DE_HE_ADDR

0x1453
Field Name

15:14

enable_tcon_double[3:2]

12:0

DE_VS_ADDR

L_DE_VE_ADDRtrib

Bit(s)ut

L_DE_VS_ADDR

R/W

DefaulttoBit(s)

DE Horizontal Start

Description

R/W0enable_tcon_double[5:4]R/W

0

DE Horizontal End

R/W

Default

Description

R/W0enable_tcon_double[3:2]

R/W

0

DE Vertical Starte

L_DE_HE_ADDR

ar

Bit(s)

0x1454
Field Name

R/W

Default

Description

15:14

enable_tcon_double[1:0]R/W0enable_tcon_double[1:0]

12:0

DE_VE_ADDR

R/W

0DE Vertical End

D

is

Bit(s)

L_HSYNC_HS_ADDR

0x1455Bit(s)

Field Name

R/W

Default

Description

12:0

HSYNC_HS_ADDR

R/W

0

HSYNC Horizontal Start

L_HSYNC_HE_ADDR

0x1456Bit(s)

Field Name

R/W

Default

Description

12:0

HSYNC_HE_ADDR

R/W

0

HSYNC Horizontal End

L_HSYNC_VS_ADDR

0x1457Bit(s)

Field Name

R/W

Default

Description

12:0

HSYNC_VS_ADDR

R/W

0

HSYNC Vertical Start

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S905 Datasheet

Revision 1.1.4

L_HSYNC_VE_ADDR

0x1458Bit(s)

Field Name

R/W

Default

Description

12:0

HSYNC_VE_ADDR

R/W

0

HSYNC Vertical End

L_VSYNC_HS_ADDR

0x1459Bit(s)

Field Name

R/W

Default

Description

12:0

VSYNC_HS_ADDR

R/W

0VSYNC Horizontal Start

L_VSYNC_HE_ADDR

0x145aBit(s)

Field Name

R/W

Default

Description

12:0

VSYNC_HE_ADDR

R/W

0VSYNC Horizontal End

l0x145bField Name

R/W

Default

Description

12:0

VSYNC_VS_ADDR

R/W

0VSYNC Vertical Start

L_VSYNC_VE_ADDR

0x145cdkerBit(s)

Bit(s)

Field Name

R/W

Default

Description

12:0

VSYNC_VE_ADDR

R/W

0VSYNC Vertical End

0x145dar

L_LCD_MCU_CTL

ne

L_VSYNC_VS_ADDR

Field Name

R/W

Default

Description

11:10

MCU_SOURCE

R/W

0

mcu_source

9

DISABLE_GAMMA_10B

R/W

0

8

VFIFO_MCU_ENABLE

R/W

7

HALT_VS_DE

6

R/W

0

5

R6G6B6_FORMAT

R/W

0

If true RGB666

4

R5G6B5_FORMAT

R/W

0

If true RGB565

3

DAC_DITH_SEL

R/W

0

If true, dither result is selected to VDAC

2

LCD_MCU_ENABLE_DE

R

0

Read only

1

LCD_MCU_ENABLE_VSYNC

R

0

Read only

0

LCD_MCU_ENABLE

R/W

0

LCD MCU interface enable

ut

R/W

0

D

is

tr
ib

H

R8G8B8_FORMAT

0: after vsync, halt the encp venc 1: after vsync and DE,
halt encp venc
If true, RGB888e0

If true, disable GAMMA 10bit input resolution(8bit
input)
Read data from viu vfifo output

toBit(s)

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AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Gamma Control
GAMMA_CNTL_PORT
Field NameGAMMA_VCOM_POL
GAMMA_RVS_OUT
ADR_RDY
WR_RDY
RD_RDYGAMMA_TR
GAMMA_SETGAMMA_EN

R/W-

Default
0

Description
GAMMA DATA PORT ADDR, all gamma data read/write
operation is via this port

R/W
R/W
R/W
R/W
R/W
R/W
W

Default
0
0
0
0
0
0

Description
GAMMA is READY for Host to read/write
BURST MODE *GAMMA R Selected
GAMMA G Selected
GAMMA B Selected
GAMMA ADDR.

GAMMA_ADDR_PORT

0x1482H

Field Name
H-RD
H-AUTO_INC
H_SEL_R
H_SEL_G
H_SEL_B
HADR

l0x1481

Field NameGAMMA_DATA_PORT

Bit(s)
12
11
10
9
8
7:0

Description
Reverse VCOM Polarity
GAMMA DATA REVERSE OUTPUT FOLLOWING VCOMGAMMA ADDR PORT Is Ready for access
GAMMA DATA PORT IS RDY to Write
GAMMA DATA PORT IS RDY to Read
RGB10-->RGB8 using Trancate or Round off
Gamma turn on syncing with Vsync
Gamma EnableneBit(s)
15:0

Default
0
0
0
0
0
0
0
0

dk
er

GAMMA_DATA_PORT

R/W
R/W
R/W
R
R
R
R/W
R/W
R/W

ar

Bit(s)
7
6
5
4
3
2
1
0

0x14800x1483

Field Name

12:0

GAMMA_VCOM_HSWITCH_ADDR

RGB_BASE_ADDR

0x1485
Field Name

9:0

RGB_BASE_ADDR

RGB_COEFF_ADDRtrib

Bit(s)ut

Bit(s)e

GAMMA_VCOM_HSWITCH_ADDR

to*NOTE:: When Programming the Gamma with Burst Mode, please turn off the IRQ service (Or make sure the IRQ service task
have no Gamma programming operation)

R/W

Default

Description

R/W

0

Horizontal Switch Point for VCOM with Gamma

R/W

Default

Description

R/W

0

RGB Converter OFFSET

R/W

Default

Description

R/W

0

RGB Converter SCALE

0x1486

Field Name

10:0

RGB_COEFF_ADDR

D

isBit(s)

POL_CNTL_ADDR

0x1487Bit(s)

Field Name

R/W

Default

Description

15:14

DCLK_SEL

R/W

0

DCLK output

11

TCON_VSYNC_SEL_DVI

R/W

0

10

TCON_HSYNC_SEL_DVI

R/W

0

9

TCON_DE_SEL_DVI

R/W

0

8

CPH3_POL

R/W

0

VSYNC generated by TCON for RGB format DVI output(support Digital LCD interface)
HSYNC generated by TCON for RGB format DVI output(support Digital LCD interface)
DE generated by TCON for RGB format DVI output(support Digital LCD interface)
CPH3 Polarity Control

7

CPH2_POL

R/W

0

CPH2 Polarity Control

6

CPH1_POL

R/W

0

CPH1 Polarity Control

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S905 Datasheet

Revision 1.1.4

Bit(s)

Field Name

R/W

Default

Description

5

TCON_DE_SEL

R/W

0

DE Generate by TCON

4

TCON_VS_SEL

R/W

0

Vsync Generate by TCON

3

TCON_HS_SEL

R/W

0

Hsync Generate by TCON

2

DE_POL

R/W

0

De polarity control

1

VS_POL

R/W

0

Vsync polarity control

0

HS_POL

R/W

0

Hsync polarity control

DITH_CNTL_ADDR

0x1488Field Name

R/W

Default

Description

13

DITH_R5

R/W

0

12

DITH_G5

R/W

0

11

DITH_B5

R/W

0

10

DITH10_EN

R/W

01=use the current dithering to dither input 10-bit R
down to 5-bit . Applicable only if both dith10_en &dith8_en = 1, otherwise no effect
1=use the current dithering to dither input 10-bit G
down to 5-bit . Applicable only if both dith10_en &dith8_en = 1, otherwise no effect
1=use the current dithering to dither input 10-bit B
down to 5-bit . Applicable only if both dith10_en &dith8_en = 1, otherwise no effect10-bits Dithering to 8 Bits Enable9

DITH8_EN

R/W

08-bits Dithering to 6 Bits Enable

8

DITH_MD

R/W

0

Dithering Mode select

7:4

DITH8_CNTL

R/W

0

3:0

DITH10_CNTL

R/W

0

1

HIGHLIGHT_EN

0

PROBE_EN

0x148aField Name

15:0

GAMMA_PROBE_COLOR_Ltrib

Bit(s)ut

GAMMA_PROBE_COLOR_L

dk
er

ar

Default

Description

R/W

0

R/W

0

R/W

Default

DescriptionR0

Probe_pix[15:0]

0x148bField Name

R/W

Default

Description

15

PROBE_PIX_V

R

0probe_pix_v

14reserveR0reserve

13:0

R

0

Probe_pix[29:16]

isBit(s)D

GAMMA_PROBE_COLOR_H

R/W

to

Field Name

10-bits Dithering control

H0x1489Bit(s)

8-bits Dithering controle

GAMMA_PROBE_CTRL

nelBit(s)GAMMA_PROBE_COLOR_H

GAMMA_PROBE_HL_COLOR

0x148cBit(s)

Field Name

R/W

Default

Description

15:0

GAMMA_PROBE_HL_COLOR

R

0

5:6:5 color

GAMMA_PROBE_POS_X

0x148dBit(s)

Field Name

R/W

Default

Description

12:0

GAMMA_PROBE_POS_X

R/W

0

Pos_x

GAMMA_PROBE_POS_Y

0x148e135/336

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S905 Datasheet

Revision 1.1.4

Bit(s)

Field Name

R/W

Default

Description

12:0

GAMMA_PROBE_POS_Y

R/W

0

Pos_y

TCON Control
STH1_HS_ADDR

0x1490Bit(s)

Field Name

R/W

Default

Description

12:0

STH1_HS_ADDR

R/W

0

STH1 Horizontal Start

STH1_HE_ADDR

0x1491
Field Name

R/W

Default

Description

12:0

STH1_HE_ADDR

R/W

0

STH1 Horizontal End

STH1_VS_ADDR

0x1492
Field Name

R/W

Default

Description

12:0

STH1_VS_ADDR

R/W

0

STH1 Vertical Start

STH1_VE_ADDR

0x1493dkerBit(s)

Field Name

R/W

Default

Description

12:0

STH1_VE_ADDR

R/W

0

STH1 Vertical End

0x1494ar

Bit(s)

STH2_HS_ADDR

Field Name

R/W

Default

Description

12:0

STH2_HS_ADDR

R/W

0

STH2 Horizontal Start

Field Name

12:0

STH2_HE_ADDR

R/W

Default

Description

R/W

0

STH2 Horizontal End

R/W

Default

Description

R/W

0

STH2 Vertical Start

R/W

Default

Description

R/W

0

STH2 Vertical End

Field Name

R/W

Default

Description

OEH_HS_ADDR

R/W

0OEH Horizontal Start

0x1496
Field Name

12:0

STH2_VS_ADDR

STH2_VE_ADDRtrib

Bit(s)

0x1497
Field Name

12:0

STH2_VE_ADDR

12:0

0x1498D

Bit(s)isBit(s)

OEH_HS_ADDR

OEH_HE_ADDR

ut

STH2_VS_ADDRe

Bit(s)

to0x1495H

Bit(s)

STH2_HE_ADDR

0x1499Bit(s)

Field Name

R/W

Default

Description

12:0

OEH_HE_ADDR

R/W

0OEH Horizontal End

OEH_VS_ADDR

0x149aBit(s)

Field Name

R/W

Default

Description

12:0

OEH_VS_ADDR

R/W

0OEH Vertical Start

OEH_VE_ADDR

nelBit(s)

0x149b136/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Bit(s)

Field Name

R/W

Default

Description

12:0

OEH_VE_ADDR

R/W

0OEH Vertical End

VCOM_HSWITCH_ADDR

0x149cBit(s)

Field Name

R/W

Default

Description

12:0

VCOM_HSWITCH_ADDR

R/W

0VCOM Horizontal Switch Point

VCOM_VS_ADDR

0x149dBit(s)

Field Name

R/W

Default

Description

12:0

VCOM_VS_ADDR

R/W

0VCOM Vertical Start

Bit(s)

Field Name

R/W

Default

Description

12:0

VCOM_VE_ADDR

R/W

0VCOM Vertical End

0x149fdk
er

CPV1_HS_ADDR
Bit(s)

Field Name

R/W

Default

Description

12:0

CPV1_HS_ADDR

R/W

0

CPV1 Horizontal Start

CPV1_HE_ADDR

0x14a0Field Name

R/W

Default

Description

12:0

CPV1_HE_ADDR

R/W

0

CPV1 Horizontal End

Field Name

R/W

12:0

CPV1_VS_ADDR

R/W

CPV1_VE_ADDR

0x14a2
CPV1_VE_ADDR

Default

Description0

CPV1 Vertical End

R/W

Default

Description

R/W

0

CPV2 Horizontal Start

R/W

Default

Description

R/W

0

CPV2 Horizontal End

Field Name

R/W

Default

Description

CPV2_VS_ADDR

R/W

0CPV2 Vertical Start

0x14a3
Field Name

12:0

CPV2_HS_ADDR

CPV2_HE_ADDRtrib

Bit(s)

0x14a4
Field Name

12:0

CPV2_HE_ADDR

D

isBit(s)

Bit(s)
12:0

CPV2_VE_ADDR

CPV1 Vertical Start

R/W

CPV2_HS_ADDR

CPV2_VS_ADDR

Description

0

R/W

e

Field Name

12:0

ut

Bit(s)

DefaulttoBit(s)

H

0x14a1ar

Bit(s)

CPV1_VS_ADDR

0x14a50x14a6Bit(s)

Field Name

R/W

Default

Description

12:0

CPV2_VE_ADDR

R/W

0CPV2 Vertical End

STV1_HS_ADDRl0x149ene

VCOM_VE_ADDR

0x14a7Bit(s)

Field Name

R/W

Default

Description

12:0

STV1_HS_ADDR

R/W

0

STV1 Horizontal Start

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S905 Datasheet

Revision 1.1.4

STV1_HE_ADDR

0x14a8Bit(s)

Field Name

R/W

Default

Description

12:0

STV1_HE_ADDR

R/W

0

STV1 Horizontal End

STV1_VS_ADDR

0x14a9Bit(s)

Field Name

R/W

Default

Description

12:0

STV1_VS_ADDR

R/W

0

STV1 Vertical Start

STV1_VE_ADDR

0x14aaBit(s)

Field Name

R/W

Default

Description

12:0

STV1_VE_ADDR

R/W

0

STV1 Vertical End

l0x14abField Name

R/W

Default

Description

12:0

STV2_HS_ADDR

R/W

0

STV2 Horizontal Start

STV2_HE_ADDR

0x14acdkerBit(s)

Bit(s)

Field Name

R/W

Default

Description

12:0

STV2_HE_ADDR

R/W

0

STV2 Horizontal End

0x14adar

STV2_VS_ADDR

Field Name

R/W

Default

Description

12:0

STV2_VS_ADDR

R/W

0

STV2 Vertical Start

0x14aeField Name

12:0

STV2_VE_ADDR

Field Name

12:0

OEV1_HS_ADDR

0x14b0tr
ib

OEV1_HE_ADDRe0x14afBit(s)ut

OEV1_HS_ADDR

R/W

Bit(s)

Field Name

12:0

OEV1_HE_ADDR

DefaulttoBit(s)

Description

R/W

0

STV2 Vertical End

R/W

Default

Description

R/W

0

OEV1 Horizontal Start

R/W

Default

Description

R/W

0

OEV1 Horizontal End

0x14b1is

OEV1_VS_ADDR

H

Bit(s)

STV2_VE_ADDR

Field Name

R/W

Default

Description

12:0

OEV1_VS_ADDR

R/W

0

OEV1 Vertical StartD

Bit(s)

OEV1_VE_ADDR

0x14b2Bit(s)

Field Name

R/W

Default

Description

12:0

OEV1_VE_ADDR

R/W

0

OEV1 Vertical End

OEV2_HS_ADDR

0x14b3Bit(s)

Field Name

R/W

Default

Description

12:0

OEV2_HS_ADDR

R/W

0

OEV2 Horizontal Start

OEV2_HE_ADDR

ne

STV2_HS_ADDR

0x14b4

138/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Bit(s)

Field Name

R/W

Default

Description

12:0

OEV2_HE_ADDR

R/W

0

OEV2 Horizontal End

OEV2_VS_ADDR

0x14b5Bit(s)

Field Name

R/W

Default

Description

12:0

OEV2_VS_ADDR

R/W

0

OEV2 Vertical Start

OEV2_VE_ADDR

0x14b6Bit(s)

Field Name

R/W

Default

Description

12:0

OEV2_VE_ADDR

R/W

0

OEV2 Vertical End

Bit(s)

Field Name

R/W

Default

Description

12:0

OEV3_HS_ADDR

R/W

0

OEV3 Horizontal Start

0x14b8dker

OEV3_HE_ADDR
Bit(s)

Field Name

R/W

Default

Description

12:0

OEV3_HE_ADDR

R/W

0

OEV3 Horizontal End

OEV3_VS_ADDR

0x14b9Field Name

R/W

Default

Description

12:0

OEV3_VS_ADDR

R/W

0

OEV3 Vertical Start

Field Name

R/W

12:0

OEV3_VE_ADDR

R/W

LCD_PWR_ADDR

0x14bb ( Unused)

4

LCD_VBL

3:0

LCD_GPIO

Default

Description

0

LCD VDD control

R/W

0

LCD VBL control

R/W

0

LCD GPIO control

R/W

Default

Description

R/W

0

LOW Count

Field Name

R/W

Default

Description

LCD_PWM0_HI_ADDR

R/W

0High Count0x14bc (Unused)

Field Name

12:0

LCD_PWM0_LO_ADDR

is

Bit(s)D

LCD_PWM0_HI_ADDR
12:0

OEV3 Vertical End

R/W

LCD_PWM0_LO_ADDR

Bit(s)

Description

0

R/W

e

LCD_VDDut

Field Name

5

tr
ib

Bit(s)

DefaulttoBit(s)

H

0x14baarBit(s)

OEV3_VE_ADDR

LCD_PWM1_LO_ADDR

0x14bd (Unused)

0x14be (Unused)

Bit(s)

Field Name

R/W

Default

Description

12:0

LCD_PWM0_LO_ADDR

R/W

0

LOW Count

LCD_PWM1_HI_ADDRl0x14b7

ne

OEV3_HS_ADDR

0x14bf (Unused)

Bit(s)

Field Name

R/W

Default

Description

12:0

LCD_PWM0_HI_ADDR

R/W

0High Count139/336

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S905 Datasheet

Revision 1.1.4

INV_CNT_ADDR

0x14c0Bit(s)

Field Name

R/W

Default

Description

4

INV_EN

R/W

0

Invert data output Enable

3:0

INV_CNT

R/W

0

Invert data count define

TCON_MISC_SEL_ADDR

0x14c1

Field Name

R/W

Default

Description

12

STH2_SEL

R/W

0

STH2 is Line signal

11

STH1_SEL

R/W

0

STH1 is Line Signal

10

OEH_SELR/W

0

OEH is Line Signal

9

VCOM_SEL

R/W

0

VCOM is Line Signal

8

DB_LINE_SW

R/W

0

VCOM switched double lines

7

CPV2_SEL

R/W

0

CPV2 is Line Signal

6

CPV1_SEL

R/W

0

CPV1 is Line Signal

5

STV2_SEL

R/W

1

STV2 is frame Signal

4

STV1_SEL

R/W

1

STV1 is frame Signal

3

OEV_UNITE

R/W

1

OEV3/2/1 look like one signal

2

OEV3_SEL

R/W

0

OEV3 is Line Signal

1

OEV2_SEL

R/W

0

OEV2 is Line Signal

0

OEV1_SEL

R/W

0

OEV1 is Line Signal

ne

dk
er

ar

0x14c2

H

DUAL_PORT_CNTL_ADDRl

Bit(s)

Bit(s)

Field Name

R/W

15

OUTPUT_YUV

R/W

14:12

IDF

R.W

0

11:9

ISF

R/W

0

8

LCD_ANALOG_SEL_CPH3

R/W

0

CPH3/INVT pin select7

LCD_ANALOG_3PHI_CLK_SEL

R/W

0

CPH3/2/1 Output 3 phases

6

LCD_LVDS_SEL54

R/W

0

5

LCD_LVDS_SEL27

R/W

0

4

LCD_TTL_SEL

R/W

0

3

DUAL_LVDS_EN

R/W

0

2

PORT_SWP

R/W

0

1

RGB_SWP

R/W

0

R/B Swapped in data path

0

BIT_SWP

R/W

0

Bit Swap in data path(7:00:7)

Bit(s)

Description

0

to
e

ut

tr
ib

is

D

LVDS_PACK_CNTL_ADDR

Default

0x14d0Field Name

R/W

Default

Description

15:14

G_SELECT

R/W

00:R, 1:G, 2:B, 3:0

13:12

G_SELECT

R/W

00:R, 1:G, 2:B, 3:0

11:10

R_SELECT

R/W

00:R, 1:G, 2:B, 3:0

9:8

BIT_SIZE

R/W

0

0:10Bits, 1:8Bits, 2:6Bits, 3:4Bits

7

LVDS_USE_TCONR/W

0hs, vs, de controlled by tcon

6

LVDS_DUAL

R/W

0

dual port mapping

5

PN_SWPR/W

0

pn_swp4

LSB_FIRST

R/W

0

0:MSB first, 1:LSB first3

LVDS_RESV

R/W

0

invert hs and vs

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S905 Datasheet

Revision 1.1.4

Bit(s)

Field Name

R/W

Default

Description

2

ODD_EVEN_SWP

R/W

0

0:normal, 1:swap

1:0

LVDS_rEPACK

R/W

0

0:normal, 1,2:repack

DE_HS_ADDR

0x14d1Bit(s)

Field Name

R/W

Default

Description

12:0

DE_HS_ADDR

R/W

0

DE Horizontal Start

DE_HE_ADDR

0x14d2Bit(s)

Field Name

R/W

Default

Description

12:0

DE_HE_ADDR

R/W

0

DE Horizontal End

l0x14d3
Field Name

R/W

Default

Description

12:0

DE_VS_ADDR

R/W

0DE Vertical Start

DE_VE_ADDR

0x14d4dkerBit(s)

Bit(s)

Field Name

R/W

Default

Description

12:0

DE_VE_ADDR

R/W

0DE Vertical End

0x14d5ar

HSYNC_HS_ADDR

Field Name

R/W

Default

Description

12:0

HSYNC_HS_ADDR

R/W

0

HSYNC Horizontal Start

0x14d6
Field Name

12:0

HSYNC_HE_ADDR

Field Name

12:0

HSYNC_VS_ADDR

0x14d8tr
ib

HSYNC_VE_ADDRe0x14d7Bit(s)ut

HSYNC_VS_ADDR

R/W

Bit(s)

Field Name

12:0

HSYNC_VE_ADDR

DefaulttoBit(s)

Description

R/W

0

HSYNC Horizontal End

R/W

Default

Description

R/W

0

HSYNC Vertical Start

R/W

Default

Description

R/W

0

HSYNC Vertical End

0x14d9is

VSYNC_HS_ADDR

H

Bit(s)HSYNC_HE_ADDR

Field Name

R/W

Default

Description

12:0

VSYNC_HS_ADDR

R/W

0VSYNC Horizontal StartD

Bit(s)

VSYNC_HE_ADDR

0x14daBit(s)

Field Name

R/W

Default

Description

12:0

VSYNC_HE_ADDR

R/W

0VSYNC Horizontal End

VSYNC_VS_ADDR

0x14dbBit(s)

Field Name

R/W

Default

Description

12:0

VSYNC_VS_ADDR

R/W

0VSYNC Vertical Start

VSYNC_VE_ADDR

ne

DE_VS_ADDR

0x14dc141/336

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S905 Datasheet

Revision 1.1.4

Bit(s)

Field Name

R/W

Default

Description

12:0

VSYNC_VE_ADDR

R/W

0VSYNC Vertical End

LCD_MCU_CTL

0x14ddField Name

R/W

Default

Description

11:10

MCU_SOURCE

R/W

0

mcu_source

9

DISABLE_GAMMA_10B

R/W

0

8

VFIFO_MCU_ENABLE

R/W

0

If true, disable GAMMA 10bit input resolution(8bit
input)
Read data from viu vfifo output

7

HALT_VS_DE

R/W

0

6

R8G8B8_FORMAT

R/W

0

0: after vsync, halt the encp venc 1: after vsync and DE,
halt encp venc
If true, RGB888

5

R6G6B6_FORMAT

R/W

0

If true RGB666

4

R5G6B5_FORMAT

R/W

0

If true RGB565

3

DAC_DITH_SEL

R/W

0

If true, dither result is selected to VDAC

2

LCD_MCU_ENABLE_DE

R

0

Read only

1

LCD_MCU_ENABLE_VSYNC

R

0

Read only

0

LCD_MCU_ENABLE

R/W

0

LCD MCU interface enable

R/W

Default

DescriptionR

0

Field NameLCD_MCU_DATA_1

0x14deField NameeBit(s)

to

H

15-0

Default

DescriptionR0

If (RGB666 or RGB888)
15:8 G, 7:0 B
Else
14:10 G[9:5], 9:0 B

is0x14e0

R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0

3
2

R/W
R/W

0
0

1-0

R/W

0

D

Bit(s)
15
14-11
10:6
5-4

ne

tr
ib

LVDS Registers
LVDS_GEN_CNTL

If RGB565 mode
15:11 R, 10:5 G, 4:0 B
Else If (RGB666 or RGB888)
15:8 G, 7:0 R
Else
14:10 G[4:0], 9:0 R

R/W

ut

15-0

dk
er

Bit(s)

0x14dear

LCD_MCU_DATA_0l

Bit(s)

Description
Mini LVDS (Ask Chen Shi)
unusedLVDS_PHY_MODE,unused
LVDS_FIFO_CLK_SEL:
0 = PHY clock divided by 6
1 = PHY clock divided by 7
2 = PHY clock divided by 8
FIFO_WR_EN: Set to 1 to enable the LVDS FIFO
FIFO_WR_BIST_GATE: This bit is used during production test to enable the FIFO writes at a particular time toensure the data sent is consistent from run to run
FIFO_WR_MODE:
0 = FIFO disabled
1 = FIFO enabled
2 = FIFO write = DCLK / 2
3 = FIFO write = signal control (preferred)

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S905 Datasheet

Revision 1.1.4

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Description
unusedLVDS_PDN_CHCK
LVDS_PDN_CH5
LVDS_PDN_CH4
LVDS_PDN_CH3
LVDS_PDN_CH2
LVDS_PDN_CH1
LVDS_PDN_CH0
UnusedLVDS_DININV_CHCK
LVDS_DININV_CH5
LVDS_DININV_CH4
LVDS_DININV_CH3
LVDS_DININV_CH2
LVDS_DININV_CH1
LVDS_DININV_CH0

0x14e3( Unused)

R/W
R/W

Default
0

Description
unused

R/W
R/W
R/W

Default
00

Description
unusedLVDS_COMMON

0x14e5)( Unused)

Default
00

Description
unusedLVDS_MDR_PU

0x14e6( Unused)

Default00
00Description
LVDS_REFCTL
LVDS_VCM_CTL
LVDS_SWING_CTL
LVDS_PREM_CTL

LVDS_PHY_CNTL2
Bit(s)
15-0

Bit(s)
15-12
11-0

0x14e4 ( Unused)trib

LVDS_PHY_CNTL3

LVDS_PHY_CNTL4
R/W
R/W
R/W

D

Bit(s)
15-7
6-0

LVDS_PHY_CNTL5
Bit(s)
15-11
10-8
7-4
3-0

LVDS_SRG_TEST
Bit(s)
12-0

ne

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

dk
er

Bit(s)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

ar

( Unused)H

0x14e2

LVDS_PHY_CNTL1

toDescription
unusedLVDS_CLKSEL_CHCK
LVDS_CLKSEL_CH5
LVDS_CLKSEL_CH4
LVDS_CLKSEL_CH3
LVDS_CLKSEL_CH2
LVDS_CLKSEL_CH1
LVDS_CLKSEL_CH0
LVDS_CTL_REG

eDefault
0
0
0
0
0
0
0
0
0

l

0x14e1 ( Unused)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

ut

Bit(s)
15-11
10
9
8
7
6
5
4
3-0

is

LVDS_PHY_CNTL0

R/W
R/W
R/W
R/W
R/W

0x14e8 ( Unused)
R/W
R

Default
0

Description
unused143/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

11-10

R/W

0

9-8

R/W

0

7-6

R/W

0

5-4

R/W

0

3-2

R/W

0

1-0

R/W

0

Bit(s)
15-8
7-6

R/W
R/W
R/W

Default
0
0

5-4

R/W

0

3-2

R/W

0

1-0

R/W

0

ne

0

dk
er

R/W

ar

13-12

Description
B2 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED2 (see below)
B1 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED1 (see below)
B0 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED0 (see below)
A4 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED0 (see below)
A3 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED3 (see below)
A2 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED2 (see below)
A1 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED1 (see below)
A0 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED0 (see below)

H

Default
0

LVDS_BIST_FIXED0
Bit(s)
15-8
7-0

R/W
R/W
R/W

ut

0x14eaDescription
unused
CLKB BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED3 (see below)
CLKA BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED2 (see below)
B4 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED0 (see below)
B3 BIST MUX
0 = pre-select random LFSR selection
1 = LFSR[8:1]
2 = LVDS_BIST_FIXED3 (see below)

tr
ib

is

LVDS_BIST_MUX1

e

to

R/W
R/W

l

0x14e9Bit(s)
15-14

D

LVDS_BIST_MUX0

0x14ebDefault
00

Description
LVDS_BIST_FIXED1LVDS_BIST_FIXED0

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AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

LVDS_BIST_FIXED1

0x14ec

R/W
R/W
R/W

Default
00

LVDS_BIST_CNTL00x14ed

R/W
R
R/W
R/W
R/W

Default
0
0
0
0

R/W
R/W
R/W
R/W
R/W

Default
0
0x63
0
0x63

LVDS_PHY_CLK_CNTL
Bit(s)
15
14
13-0

R/W
R/W
R/W
R/W

0x14efDefault
000Default
0

LVDS_PHY_CNTL6

0x14f1
R/W
R/W

Default
0

R/W
R/W

Default
0

R/W
R/W

Default0

Bit(s)
15-0

0x14f20x14f30x14f4D

MLVDS_CLK_CTL_HI

R/W
R/W

Default
0

MLVDS_CLK_CTL_LO
Bit(s)
15-0

Description
unusedis

LVDS_PHY_CNTL8

Bit(s)
15-0

Description
Unusedtr
ib

LVDS_PHY_CNTL7

Description
unusedR/W
R/W

Description
Ask Chen Shi

0x14f5
Default
0

MLVDS_DUAL_GATE_WR_START
Bit(s)
15-0

ut

Bit(s)
15-0

Description
unusedn

to

R/W
R/W

H

0x14f0Bit(s)
15-0

Bit(s)
15-0

Description
LVDS_DIV_RESET_N
LVDS_DIV_SOFT_RESET
unusede

LVDS_SER_EN

Description0
CLKB LVDS value shifted out serially0
CLKA LVDS value shifted out seriallylBit(s)
15
14-8
7
6-0

0x14eene

LVDS_CLKB_CLKA

Description
unusedLVDS_BIST_DUAL_PIXELLVDS_BIST_TAP_SEL: This selects the LFSR polynomial
BIST_ENdker

Bit(s)
15-7
6
5-1
0

Description
LVDS_BIST_FIXED3
LVDS_BIST_FIXED2

ar

Bit(s)
15-8
7-0

R/W
R/W

Default
0

MLVDS_DUAL_GATE_WR_END

Description
Ask Chen Shi

0x14f6
Description
Ask Chen Shi

0x14f7145/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
15-0

Revision 1.1.4

R/W
R/W

Default
0

Description
Ask Chen Shi

MLVDS_DUAL_GATE_RD_START
Bit(s)
15-0

R/W
R/W

Default
00x14f8Description
Ask Chen Shi

MLVDS_DUAL_GATE_RD_END 0x14f9
Default
0

R/W
R/W

Default
0

MLVDS_GATE_CTL_HI
Bit(s)
15-0

R/W
R/W

0x14fbDefault
0

MLVDS_GATE_CTL_LO
Bit(s)
15-0

R/W
R/W

Description
Ask Chen ShilBit(s)
15-0

0x14faDescription
Ask Chen Shi, mlvds_dual_gate_ctl[31:16]

0x14fcDefault
0

Description
Ask Chen Shii, mlvds_dual_gate_ctl[15:0]

ENCI_VIDEO_MODE

0x1b00

R/W
R/W
R/W
R/W

Default
0
0
0

3
2
1
0

ENCI_VIDEO_MODE_PED
ENCI_VIDEO_MODE_PDRSTENCI_VIDEO_MODE_PHALTENCI_VIDEO_MODE_LNFMT

R/W
R/W
R/W
R/W

0
0
0
0

Field NameENCI_VIDEO_MODE_EN_CSYNC_MACV
CFG_LUMA_FOR_CVBS_HIGH
CFG_CHROMA_MOD_HIGH
CFG_LUMA_FOR_RGB_HIGH
ENCI_VIDEO_MODE_ADV_HY_SYLPF_SEL

R/W
R/W
R/W
R/W
R/W
R/W

Default
00000ENCI_VIDEO_MODE_ADV_CMPT_BURST_WIN_SEL
ENCI_VIDEO_MODE_ADV_CBWENCI_VIDEO_MODE_ADV_YBW
ENCI_VIDEO_MODE_ADV_VBICTL
ENCI_VIDEO_MODE_ADV_DMXMD

R/W
R/W
R/W
R/W
R/W

0
0
0
1
2'b10

to

Field NameENCI_VIDEO_MODE_PAL_LN309_AVONENCI_VIDEO_MODE_SQPXENCI_VIDEO_MODE_FSCSELDENCI_VIDEO_FSC_ADJ

Description
Fix the bug pal video is not on some fields of ln309
Square pixel mode
0: Fc=3.5795M, 1:Fsc=4.4336M, 2: Fsc=3.5756M,
3:Fsc=3.582M.
0: No pedestal, 1: Pedestal enable
0: Phase reset every field, 1: Phase not reset
0: Phase alternate disable, 1: Phase alternate enable
0: 525 lines, 1:625 lines

0x1b01

is

ENCI_VIDEO_MODE_ADV

tr
ib

ut

e

Bit(s)
7
6
5-4

9 -8
7 -6
5 -4
2
1 -0

H

Video Encoder Registers

Bit(s)
15
14
13
12
11-10

ne

MLVDS_SECOND_RESET_CTL

Description
Ask Chen Shi

dk
er

R/W
R/W

ar

Bit(s)
15-0

Description
Enable macrovision signal on CSYNC
Luma for CVBS high bandwidth
Chroma modulation high bandwidth
Using high bandwidth luma for RGB
Low pass filter selection on sync of high bandwidth
Luma signal.
0=Bypass LPF;
1=Use 3-tap LPF;
2=Use 5-tap LPF.
Chroma Filter bandwidth, 0:Low, 1:Medium, 2:Higher
Luma Filter bandwidth , 0:Medium, 1:Low, 2:High
0: Blank line end at line6 1: Blank line end at line17/22
Video input demux shifting mode, adjust this value
When input video stream is shifted.

0x1b02

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AMLOGIC, Inc. ProprietaryField NameENCI_VIDEO_FSC_ADJ

ENCI_VIDEO_BRIGHTENCI_VIDEO_SAT

ENCI_VIDEO_HUE

ENCI_VIDEO_SCH

Default
8'd0

Description
Contrast

R/W
R/W

Default
8'd0

Description
Saturation

R/W
R/W

Default
8'd0

R/W
R/W

Default
8'd0

R/W
R/W

Default
8'd7

0x1b07
Field NameENCI_VIDEO_SCH

ENCI_SYNC_MODE

0x1b08H

Field NameENCI_SYNC_MODE

Description
Hue

Description
Sch adjust, adjust the phase of the FSC

Description
Video
input
Synchronization
mode
Define Field sync/Vertical Sync/Horizontal Sync source,
0: FFF All from fsi (Not used in T25)
1:
FVH
From
FSI,
VSI,
HSI
respectively
2:
FVV
From
FSI,
VSI,
VSI
respectively
3: 0VV No FSI, Vsync/Hsync from VSI, HSI respectively
4: FVH_EAV From CCIR601 stream directly
5: FFF_EAV From CCIR601 stream, but use Field sync only
6: FMVH field rst when vs is near around line start.
7: MASTER Master mode, free run, send HSO/VSO out

tr
ib

ut

e

to

Bit(s)
7 -0

R/W
R/W

0x1b06
Field NameENCI_VIDEO_HUE

Bit(s)
7 -0

Description
Brightness

0x1b05
Field NameENCI_VIDEO_SAT

Bit(s)
7 -0

Default
8'd0

0x1b04
Field NameENCI_VIDEO_CONT

Bit(s)
7 -0

R/W
R/W

l

Bit(s)
7 -0

Description
FSC adjust , 16 bit value that can adjust FSC frequency(Add with setting value)

0x1b03

Field NameENCI_VIDEO_BRIGHTENCI_VIDEO_CONT

Default
16'd0ne

Bit(s)
7 -0

R/W
R/W

ar

Bit(s)
15 -0

Revision 1.1.4

dker

S905 Datasheet

Notes: Suggest use Master mode only

Field NameENCI_SYNC_HSO_BEGIN

D

Bit(s)
10 -0

ENCI_SYNC_HSO_END
Bit(s)
10 -0

Bit(s)
15 -8

Default
11'd3

Description
HSO begin position

R/W
R/W

Default
11'd5

Description
HSO end postion

R/W
R/W
R/W

Default
88Description
VSO output start line in even field
VSO output end line in even field

R/W
R/W

Default
9

Description
VSO output start line in odd field

0x1b0bField NameENCI_SYNC_VSO_EVN_STRTLN
ENCI_SYNC_VSO_EVN_ENDLN

ENCI_SYNC_VSO_ODDLN

R/W
R/W

0x1b0aField NameENCI_SYNC_HSO_END

ENCI_SYNC_VSO_EVNLN
Bit(s)
15 -8
7 -0

0x1b09is

ENCI_SYNC_HSO_BEGIN

0x1b0eField NameENCI_SYNC_VSO_ODD_STRTLN

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Bit(s)
7 -0

Revision 1.1.4

Field NameENCI_SYNC_VSO_ODD_ENDLN

ENCI_SYNC_CTRL

R/W
R/W

Default
9

Description
VSO output end line in odd field

Description

0x1b0fField NameENCI_SYNC_DE_V
ENCI_SYNC_VSO_INACTIVE_MODE
ENCI_SYNC_CTRL_VSOMD

R/W
R/W
R/W
R/W

Default
0
0
0

5
4
3
2
1
0

ENCI_SYNC_CTRL_FSOPENCI_SYNC_CTRL_VSOPENCI_SYNC_CTRL_HSOPENCI_SYNC_CTRL_FSIP
ENCI_SYNC_CTRL_VSIP
ENCI_SYNC_CTRL_HSIP

R/W
R/W
R/W
R/W
R/W
R/W

0
0
0
1
0
0

VSO position in odd field, 0:Half line after VSO in Even
field, 1:Same as Even Field
FSO polarity
VSO polarity
HSO polarity
FSI polarity
VSI polarity
HSI polarity

R/W
R/W

Default2

Description
Horizontal offset after HSI in slave mode

R/W
R/W

Default
0

ENCI_SYNC_VOFFST
Bit(s)
8 -0

ne0x1b10Field NameENCI_SYNC_HOFFST

0x1b11

Field NameENCI_SYNC_VOFFSTENCI_SYNC_ADJ

Description
Horizontal offset aftet VSI in slave modearBit(s)
10 -0

dk
er

ENCI_SYNC_HOFFSTl

Bit(s)
8
7
6

0x1b12
Field NameENCI_SYNC_ADJ_EN

R/W
R/W

Default
0

14 -10
9 -5
4 -0

ENCI_SYNC_ADJ_BU_V
ENCI_SYNC_ADJ_BU_U
ENCI_SYNC_ADJ_SYNC

R/W
R/W
R/W

0
0
0

R/W
R/W
R/W

Default
00

Description
Resevered
Analog RGB sync disable (1:Enable Sync, 0:Disable) , bit
2 for Blue, bit 1 for Green. Bit 0 for Red

R/W
R/W
R/W

Default
00

Description
CbCr matrix parameter Ma (signed value)
CbCr matrix parameter Mb (signed value)toe0x1b13

Field NameRESERVEDENCI_RGB_SYNC

trib

Bit(s)
12 -3
2 -0

ut

ENCI_RGB_SETTINGH

Bit(s)
15

Description
Analog Synchronization and color burst value adjust
enableAnalog V burst adjustment, Signed value
Analog U burst adjustment, Signed value
Analog sync adjustment, Signed value

ENCI_CMPN_MATRIX_CB 0x1b14

Field Name
ENCP_VIDEO_MATRIX_MA
ENCP_VIDEO_MATRIX_MB

is

Bit(s)
15:8
7:0

D

Note: These 2 register is for HUE adjustment. The formula is : Cb’ = Cb*Ma + Cr*Mb, Cr’ = Cb*Mc + Cr*Md(effective only when Enable HUE matrix by bit ENCI_VIDEO_MODE_ADV[11])ENCI_CMPN_MATRIX_CR 0x1b15
Bit(s)
15:8
7:0

Field Name
ENCP_VIDEO_MATRIX_MC
ENCP_VIDEO_MATRIX_MD

R/W
R/W
R/W

Default
00

Description
CbCr matrix parameter Mc (signed value)
CbCr matrix parameter Md (signed value)

R/W
R/W

Default
0

Description
Close caption phase adjustment (Value is from TTXDT0)

Note: See above.
ENCI_VBI_SETTING
Bit(s)
13

0x1b20Field NameENCI_VBI_SETTING_CCCSTM

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Bit(s)
12
11
10 -8
5
4
3
2
1
0

Revision 1.1.4

Field NameENCI_VBI_SETTING_TTX_ODD_EN
ENCI_VBI_SETTING_TTX_EVN_EN
ENCI_VBI_SETTING_TTX_FREQ
ENCI_VBI_SETTING_CGMS_ODD_EN
ENCI_VBI_SETTING_CGMS_EVN_EN
ENCI_VBI_SETTING_WSS_ODD_EN
ENCI_VBI_SETTING_WSS_EVN_EN
ENCI_VBI_SETTING_CC_ODD_EN
ENCI_VBI_SETTING_CC_EVN_EN

ENCI_VBI_CCDT_EVN

Default
0
0
0
0
0
0
0
0
0

Description
Teletext odd field enable
Teletext even field enable
Teletext frequency selection
CGMS odd field enable
CGMS even field enable
WSS odd field enable
WSS Even Field enable
Close Caption Odd Field enable
Close Caption Even Field enable

R/W
R/W

Default
0

Description
Close caption even field data

R/W
R/W

Default
0

Description
Close caption even odd data

R/W
R/W

Default
16'h1211

R/W
R/W

Default
16'h1615

0x1b21

Field NameENCI_VBI_CCDT_EVN

Field NameENCI_VBI_CCDT_ODD

ENCI_VBI_CC525_LN
Bit(s)
15 -0

0x1b23

Field NameENCI_VBI_CC525_LN

ENCI_VBI_CC625_LN

0x1b24

Field NameENCI_VBI_CC625_LN

ENCI_VBI_WSSDT

0x1b25

Field NameENCI_VBI_WSS_LN

ENCI_VBI_CGMSDT_L

Field NameENCI_VBI_CGMSDT_L

is

Bit(s)
15 -0

ENCI_VBI_CGMSDT_H

ENCI_VBI_CGMS_LN
Bit(s)
15 -0

Bit(s)
15 -10
9 -0

ENCI_VBI_TTX_LN

Description
WSS data

R/W
R/W

Default
16'd22

Description
WSS line

R/W
R/W

Default
16'h0

Description
CGMS data low 16 Bits

R/W
R/W

Default
8'h0

Description
CGMS data high 8 Bits

R/W
R/W

Default
16'h1110

Description
CGMS line

R/W
R/W
R/W

Default
6'h2d
11'h135

Description
Teletext total bytes
Teletext start postion

0x1b29Field NameENCI_VBI_CGMS_LN

ENCI_VBI_TTX_HTIME

Default
16'h0

0x1b28Field NameENCI_VBI_CGMSDT_H

D

Bit(s)
7 -0

0x1b27trib

Bit(s)
15 -0

0x1b26e

ENCI_VBI_WSS_LN

R/W
R/W

to

Field NameENCI_VBI_WSSDT

ut

Bit(s)
15 -0

Description
Close caption line in 625 formatH

Bit(s)
15 -0

Description
Close caption line in 525 formatarBit(s)
15 -0

0x1b22dk
er

ENCI_VBI_CCDT_ODD

nelBit(s)
15 -0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0x1b2aField NameENCI_VBI_TTX_HTIME_TOTAL_BYTESENCI_VBI_TTX_HTIME_STRT_POS

0x1b2b149/336

AMLOGIC, Inc. ProprietaryField NameENCI_VBI_TTX_STRT_LN
ENCI_VBI_TTX_END_LN

ENCI_VBI_TTXDT0

ENCI_VBI_TTXDT1

ENCI_VBI_TTXDT3

ENCI_MACV_N0

ENCI_MACV_N1

trib

Field NameENCI_MACV_N3

ENCI_MACV_N4

ENCI_MACV_N7
Bit(s)
1 -0

ENCI_MACV_N8

Default
16'h0

R/W
R/W

Default
8'h00

R/W
R/W

Default
6'h17

Description
Teletext data3

Description
Macrovision register N0

Description
Macrovision register N1

R/W
R/W

Default
6'h15

Description
Macrovision register N2

R/W
R/W

Default
6'h21

Description
Macrovision register N3

R/W
R/W

Default
6'h15

Description
Macrovision register N4

R/W
R/W

Default
3'h5

Description
Macrovision register N5

R/W
R/W

Default
3'h5

Description
Macrovision register N6

R/W
R/W

Default
2'h2

Description
Macrovision register N7

is0x1b35

Field NameENCI_MACV_N5

D

Bit(s)
2 -0

R/W
R/W

0x1b34
Field NameENCI_MACV_N4

ENCI_MACV_N6

Description
Teletext data2e0x1b33ut

ENCI_MACV_N3

Bit(s)
2 -0

Default
16'h0

H0x1b32
Field NameENCI_MACV_N2

ENCI_MACV_N5

R/W
R/W

to

ENCI_MACV_N2

Bit(s)
5 -0

Description
Teletext data1

0x1b31
Field NameENCI_MACV_N1

Bit(s)
5 -0

Default
16'h0

0x1b30Field NameENCI_MACV_N0

Bit(s)
5 -0

R/W
R/W

0x1b2fField NameENCI_VBI_TTXDT3

Bit(s)
5 -0

Description
Teletext data00x1b2eField NameENCI_VBI_TTXDT2Bit(s)
7 -0

Default
16'h0

l

ENCI_VBI_TTXDT2Bit(s)
15 -0

R/W
R/W

0x1b2dField NameENCI_VBI_TTXDT1

Bit(s)
15 -0

Description
Teletext Start line
Teletext End Line0x1b2cField NameENCI_VBI_TTXDT0

Bit(s)
15 -0

Default
16'h1415
16'h1415ne

Bit(s)
15 -0

R/W
R/W
R/W

ar

Bit(s)
15 -9
8 -0

Revision 1.1.4

dker

S905 Datasheet

0x1b36
Field NameENCI_MACV_N6

0x1b37
Field NameENCI_MACV_N7

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Field NameENCI_MACV_N8

ENCI_MACV_N9

ENCI_MACV_N10

ENCI_MACV_N12

ENCI_MACV_N13

ENCI_MACV_N14

Field NameENCI_MACV_N16

Field NameENCI_MACV_N17

Bit(s)
3 -0

ENCI_MACV_N20
Bit(s)
2 -0

ENCI_MACV_N21

Description
Macrovision register N11

R/W
R/W

Default
15'h0

Description
Macrovision register N12

R/W
R/W

Default
8'h0f

R/W
R/W

Default
8'h0f

lDescription
Macrovision register N13

Description
Macrovision register N14

R/W
R/W

Default
8'h60

Description
Macrovision register N15

R/W
R/W

Default
1'h1

Description
Macrovision register N16

R/W
R/W

Default
4'ha

Description
Macrovision register N17

R/W
R/W

Default
4'h0

Description
Macrovision register N18

R/W
R/W

Default
4'h5

Description
Macrovision register N19

R/W
R/W

Default
3'h4

Description
Macrovision register N20

R/W
R/W

Default
10'h3ff

Description
Macrovision register N21

is

0x1b42

Field NameENCI_MACV_N18

D

ENCI_MACV_N19

Bit(s)
9 -0

0x1b41

tr
ib

ENCI_MACV_N17e0x1b40ut

ENCI_MACV_N16

Bit(s)
3 -0

Default
15'h07f8

H

0x1b3fField NameENCI_MACV_N15

ENCI_MACV_N18

R/W
R/W

to

ENCI_MACV_N15

Bit(s)
3 -0

Description
Macrovision register N10

0x1b3eField NameENCI_MACV_N14

Bit(s)
0 -0

Default
6'h24

0x1b3dField NameENCI_MACV_N13

Bit(s)
7 -0

R/W
R/W

0x1b3cField NameENCI_MACV_N12

Bit(s)
7 -0

Description
Macrovision register N90x1b3bField NameENCI_MACV_N11

Bit(s)
7 -0

Default
6'h1b

ne

ENCI_MACV_N11

Bit(s)
14 -0

R/W
R/W

0x1b3aField NameENCI_MACV_N10

Bit(s)
14 -0

Description
Macrovision register N80x1b39Field NameENCI_MACV_N9

Bit(s)
5 -0

Default
6'h1b

dk
er

Bit(s)
5 -0

R/W
R/W

ar

Bit(s)
5 -0

Revision 1.1.4

0x1b43

Field NameENCI_MACV_N19

0x1b44
Field NameENCI_MACV_N20

0x1b45
Field NameENCI_MACV_N21

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ENCI_MACV_N22
Bit(s)
15 -0

0x1b46
Field NameENCI_MACV_N22

ENCI_DBG_PX_RST

R/W
R/W

Default
16'h0

Description
Macrovision register N22

0x1b48Bit(s)
15

Field NameENCI_DBG_PX_RST_EN

R/W
R/W

Default
1

10 -0

ENCI_DBG_PX_RST_VAL

R/W

0

Description
1:Reset enable (Interlaced TV encoder is disabled),
0:NormalPixel value after reset

R/W
R/W
R/W
R/W
R/W

Default00
00Description
Line reset enable
Field reset enable
Field reset value
Line reset value

R/W
R/W
R/W

Default
0
0

R/W
R/W
R/W
R/W
R/W

Default
00
00

ENCI_DBG_PX_INT
Bit(s)
15
10 -0

0x1b4aField NameENCI_DBG_PX_INT_EN
ENCI_DBG_PX_INT_VAL

ENCI_DBG_FLDLN_INT

ENCI_DBG_MAXLN

0x1b4dBit(s)
15
10 -0

is

D

l

R/W
R/W
R/W

Default
00

Description
Debug mode, change the max pixel.
The value of max pixel

R/W
R/W
R/W

Default
00

Description
Debug mode, change the max line counter
The value want to change

R/W
R/W
R/W

Default
00

Description
Macrovision max amplitude change enable
The value want to change

R/W
R/W
R/W

Default
00

Description
Macrovision low pulse change enable.
The value want to change

R/W
R/W
R/W

Default
00

Description
Macrovision high pulse change enable.
The value want to change

0x1b52

Field NameENCI_MACV_PULSE_HI_EN
ENCI_MACV_PULSE_HI_VAL

ENCI_MACV_BKP_MAX

Description
Field interrupt enable
Line interrupt enable
Field value that trig the interrupt
Line value that trig the interrupt

0x1b51

Field NameENCI_MACV_PULSE_LO_EN
ENCI_MACV_PULSE_LO_VAL

ENCI_MACV_PULSE_HI

Description
Pixel Interrupt enable
Pixel value that trig the interrupt

0x1b50Field NameENCI_MACV_MAX_AMP_EN
ENCI_MACV_MAX_AMP_VAL

ENCI_MACV_PULSE_LO
Bit(s)
15
10 -0

tr
ib

Field NameENCI_DBG_MAXLN_EN
ENCI_DBG_MAXLN_CHGVALENCI_MACV_MAX_AMP
Bit(s)
15
10 -0

H

Field NameENCI_DBG_MAXPX_EN
ENCI_DBG_MAXPX_CHGVAL

ut

Bit(s)
15
10 -0

0x1b4cto

ENCI_DBG_MAXPX

Bit(s)
15
8 -0

0x1b4bField NameENCI_DBG_FLD_INT_EN
ENCI_DBG_LN_INT_EN
ENCI_DBG_FLD_INT_VAL
ENCI_DBG_LN_INT_VALeBit(s)
1511
14 -128 -0

neField NameENCI_DBG_LN_RST_EN
ENCI_DBG_FLD_RST_EN
ENCI_DBG_FLD_RST_VAL
ENCI_DBG_LN_RST_VAL

ar

Bit(s)
15
14
11 -9
8 -0

0x1b49dk
er

ENCI_DBG_FLDLN_RST

0x1b53

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Bit(s)
15
9 -0

Revision 1.1.4

Field NameENCI_MACV_BKP_MAX_EN
ENCI_MACV_BKP_MAX_VAL

ENCI_CFILT_CTRL

R/W
R/W
R/W

Default
00

Description
Macrovision back porch max value change enable.
The value want to change

0x1b54
Field NameENCI_CFILT_CMPT_SMOOTH_FLT
ENCI_CFILT_CMPT_SEL

R/W
R/W
R/W

Default
10

10

ENCI_CFILT_CMPT_SEL
ENCI_CFILT_CVBS_SEL

R/W
R/W

1
0

Description
Component Cb/Cr smooth filter
Filter component bandwith Cb/Cr sel
0: High,
1: Medium2: Low
Filter component CbCr bandwith sel (1:high, 0:low)Filter CVBS CbCr bandwith sel (1:high, 0:low)

R/W
R/W

Default15‘h4d53

Description
Filter7 parameters

R/W
R/W
R/W
R/W

Default
0
4’h2
4’h0

R/W
R/W

Default
0

ENCI_YC_DELAY
Bit(s)
9-8
7-4
3-0

0x1b56
Field NameENCI_COMPY_DELAY
ENCI_Y_DELAY
ENCI_C_DELAY

ENCI_VIDEO_EN

0x1b57

0x1b5815-8

VFIFO2VD_VD_SEL

7

VFIFO2VD_DROP

6-1

VFIFO2VD_DELAY

0

VFIFO2VD_EN

Description

R/W

0

vfifo2vd_vd_sel

R/W0

vfifo2vd_drop

R/W0

vfifo2vd_delay

R/W

0

vfifo2vd_en

R/W
R/W

Default
0

Description
Pixel startField Name
VFIFO2VD_YC_USE_FIRST_VFIFO_REQ

R/W
R/W

Default
0

VFIFO2VD_PIXEL_END

R/W

0

Description
0=Keep as previous version;
1=On the very first pixel since VFIFO is enabled, YC
pipeline values take from default setting, rather thanfrom values stored in the pipeline.
Pixel end

12-0

R/W
R/W

Default
0

Description
Top field line end

R/W
R/W

Default
0

Description
Top field line end

0x1b59isField Name
VFIFO2VD_PIXEL_START

0x1b5aD

ENCP_VFIFO2VD_PIXEL_END
Bit(s)
15

ENCP_VFIFO2VD_LINE_TOP_START
Bit(s)
10-0

0x1b5bField Name
VFIFO2VD_LINE_TOP_START

ENCP_VFIFO2VD_LINE_TOP_END
Bit(s)
10-0

Description
Interlace video enable

Default

ENCP_VFIFO2VD_PIXEL_START
Bit(s)
12-0

Description
Component Y delay
Interlace Y delay
Interlace C delay

R/We

Field NametribBit(s)

to

ENCP_VFIFO2VD_CTL

HField NameENCI_VIDEO_EN

ut

Bit(s)
0ne

Field NameENCI_CFILT7dker

0x1b55Bit(s)
14-0

ar

ENCI_CFILT7l

Bit(s)
12
11-10

Field Name
VFIFO2VD_LINE_TOP_END

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Revision 1.1.4

ENCP_VFIFO2VD_LINE_BOT_START
Bit(s)
10-0

0x1b5dField Name
VFIFO2VD_LINE_BOT_START

ENCP_VFIFO2VD_LINE_BOT_END
Bit(s)
10-0

R/W
R/W

Default
0

Description
Bottom field line end

R/W
R/W

Default
0

Description
Bottom field line end

0x1b5eField Name
VFIFO2VD_LINE_BOT_END

VENC_SYNC_ROUTE

0x1b60Field NameVENC_SYNC_ROUTE

R/W
R/W

Default
0

1
0

VIU_SYNC_ROUTE
VPINS_SYNC_ROUTE

R/W
R/W

0
1

R/W
R/W

Default
1

Description
Internal Vencoder hsync/vsync source (0-VIU, 1-External
Venc)
VIU hsync/vsync input source (0-Venc, 1-External Venc)
External Vencoder hsync/vsync source ( 0-Internal Venc,
1-VIU)nel

Bit(s)
2

VENC_VIDEO_EXSRC

0x1b61

Field NameVENC_VIDEO_EXSRC

ar

Notes: This is not supported by T25, clear this when init.

Field NameVENC_DVI_SEL_DVI

R/W
R/W

Default
0

14
13

VENC_DVI_SEL_INTL_DE
VENC_DVI_GAMMA_EN

R/W
R/W

0
0

12
11
10
9
8
7

VENC_DVI_DDR_DESELVENC_DVI_DDR_CKSELVENC_DVI_DDR_CKPHI
VENC_DVI_DDR_SEL
VENC_DVI_INV_CLK
VENC_DVI_SEL_INTERNAL_HDMI

R/W
R/W
R/W
R/W
R/W
R/W

0
0
0
0
0
0

56:4

VENC_DVI_CLK_SEL

R/W

0

VENC_DVI_INV_VSYNC
VENC_DVI_INV_HSYNC
SYNC_SEL_OUT_SYNC
VENC_DVI_SRC_SEL

R/W
R/W
R/W
R/W

0
0
0
1

D

tr
ib

ut

e

to

H

Bit(s)
15

is

VENC_DVI_SETTING

3
2
1
0

VENC_C656_CTRL

Description
External Video Source enable, get video data fromexternal pins.

dkerBit(s)
0

0x1b62

Description
1=use programmable vs/hs/de whose only connection is
to DVI/HDMI.
For interlace mode only. 1=use intl_de for DE.
0=Send to DVI/HDMI interface with data NOT from
Gamma table.
1=Send to DVI/HDMI interface with data from Gammatable.
For external DVI device only.
For external DVI device only.
For external DVI device only.
For external DVI device only.
Invert DVI clock0=Select the external DVI device which is compatible tochips predate M1
1=Select the internal HDMI tx which is in chips startingfrom meson.
DVI Clock selection:
0: clk27
1: clk54
2: ½ of ENCP pixel_clk
3: clk108
4: ½ of ENCI pixel_clk
5: cts_vclk1
6-7: Reserved(Note : here the clk27/54/108 is signal Name, not the real
frequency)
1=Invert DVI/HDMI Vsync output polarity
1=Invert DVI/HDMI Hsync output polarity
DVI/601 sync use output sync ( not viu sync)
DVI source select ( 0: interlace, 1:progressive)

0x1b63

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Bit(s)
3
2
1
0

Revision 1.1.4

Field NameVENC_C656_CLKP
VENC_C656_FLDP
VENC_C656_VSOPVENC_C656_HSOP

R/W
R/W
R/W
R/W
R/W

Default00
00Description
Clock out Polarity
Field Polarity
Vsyn Polarity
Hsyn Polarity

Upsamping is only used for 480i/576i, 480p/576p, not for 720p/1080i/1080p mode,
For 480i/576i upsampling, video signal is upsampled from 27Mhz to 108Mhz,

Field NameUPSAMPLE_SEL

R/W
R/W

11-9
8
7
6
5
4

UNUSED
BYPASS
F1_DIV_INV
F1_UPSAMPLE_EN
F1_EN
F1_CLK_RATIO

3
2
1
0

F0_DIV_INV
F0_UPSAMPLE_EN
F0_EN
F0_CLK_RATIO

Description
Upsample0
dinselection
0: Interlace High bandwidth Luma
1:CVBS
2: S-Video luma
3:
S-Video
Chroma4: Interlace Pb
5:InterlacePr
6:
InterlaceR
7:
InterlaceG
8:
InterlaceB
9:ProgressiveY
a: Progressive Pb
b: Progressive Pr
c: Progressive R
d: Progressive G
e: Progressive B
f: VDAC test value (VENC_VDAC_TST_VAL)
UnusedIf true, bypass
If true, invert div
Filter1 upsample enable
Filter1 filtering enable
If true, Filter1 clk ratio is 2, input data sample every 2clocks, otherwise 1
If true, invert div
Filter0 upsample enable
Filter0 filtering enable
If true, Filter0 clk ratio is 2, input data sample every 2clocks, otherwise 1

R
R/W
R/W
R/W
R/W
R/W

0
0
0
0
0
0

R/W
R/W
R/W
R/W

0
0
0
0

R/W
R/W

Default
0

D

is

tr
ib

ut

e

to

H

ar

Default
0ne

0x1b64Bit(s)
15-12

dk
er

VENC_UPSAMPLE_CTRL0l

For 480p/576p upsampling, video signal is upsampled from 54Mz to 108Mhz
set VENC_UPSAMPLE_CTRL0 = 0x9061
set VENC_UPSAMPLE_CTRL1 = 0xa061
set VENC_UPSAMPLE_CTRL2 = 0x1b061

VENC_UPSAMPLE_CTRL1
Bit(s)
15-12

0x1b65

Field NameUPSAMPLE_SEL

155/336

Description
Upsample1
din0: Interlace High bandwidth Luma
1:
2: S-Video luma
3:
S-Video
4: Interlace Pb
5:Interlace
6:
Interlace
7:
Interlace
8:
Interlaceselection
CVBS
ChromaPr
R
G
B

AMLOGIC, Inc. Proprietary

S905 Datasheet

Field Name

R/W

Default

UNUSED
BYPASS
F1_DIV_INV
F1_UPSAMPLE_EN
F1_EN
F1_CLK_RATIO

R
R/W
R/W
R/W
R/W
R/W

0
0
0
0
0
0

3
2
1
0

F0_DIV_INV
F0_UPSAMPLE_EN
F0_EN
F0_CLK_RATIO

R/W
R/W
R/W
R/W

0
0
0
0

R/W
R/W

Default
0

VENC_UPSAMPLE_CTRL2

UnusedIf true, bypass
If true, invert div
Filter1 upsample enable
Filter1 filtering enable
If true, Filter1 clk ratio is 2, input data sample every 2clocks, otherwise 1
If true, invert div
Filter0 upsample enable
Filter0 filtering enable
If true, Filter0 clk ratio is 2, input data sample every 2clocks, otherwise 1

ne

0x1b66

Field NameUPSAMPLE_SEL

11-9
8
7
6
5
4

UNUSED
BYPASS
F1_DIV_INV
F1_UPSAMPLE_EN
F1_EN
F1_CLK_RATIO

R
R/W
R/W
R/W
R/W
R/W

0
0
0
0
0
0

F0_DIV_INV
F0_UPSAMPLE_EN
F0_EN
F0_CLK_RATIO

R/W
R/W
R/W
R/W

0
0
0
0

R/W
R/W
R/W
R/W

Default
1'b0
1'b0
1'b0

H
to
e
ut
tr
ib

is

D

TCON_INVERT_CTL
Bit(s)
15
14
13

Description
Upsample2
dinselection
0: Interlace High bandwidth Luma
1:CVBS
2: S-Video luma
3:
S-Video
Chroma4: Interlace Pb
5:InterlacePr
6:
InterlaceR
7:
InterlaceG
8:
InterlaceB
9:ProgressiveY
a: Progressive Pb
b: Progressive Pr
c: Progressive R
d: Progressive G
e: Progressive B
f: VDAC test value (VENC_VDAC_TST_VAL)
UnusedIf true, bypass
If true, invert div
Filter1 upsample enable
Filter1 filtering enable
If true, Filter1 clk ratio is 2, input data sample every 2clocks, otherwise 1
If true, invert div
Filter0 upsample enable
Filter0 filtering enable
If true, Filter0 clk ratio is 2, input data sample every 2clocks, otherwise 1arBit(s)
15-12

3
2
1
0

Y

l

11-9
8
7
6
5
4

Description
9:
Progressivea: Progressive Pb
b: Progressive Pr
c: Progressive R
d: Progressive G
e: Progressive B
f: VDAC test value (VENC_VDAC_TST_VAL)dker

Bit(s)

Revision 1.1.4

0x1b67
Field Name

156/336

Description
vsync invert
hsync invert
Oev3 invert

AMLOGIC, Inc. Proprietary

S905 Datasheet

Field Name

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0

Description
Oev2 invert
Cpv2 invert
Cph3 invert
Cph2 invert
Cph1 invert
oeh invert
vcom invert
Stv2 invert
Stv1 invert
Cpv1 invert
Oev1 invert
Sth1 invert
Sth2 invert

Description
Select clk108 as DAC clock
Venc bist and venc_field output selection.
0:Interlace, 1:Progressive.
VIU Vsync input select, 0:Progressive, 1:Interlace
VIU Hsync input select, 0:Progressive, 1:Interlace
Pin Vsync input select, 0:Progressive, 1:Interlace
Pin Hsync input select, 0:Progressive, 1:Interlace
DAC1 clock select, 0:clk54, 1:clk27
DAC0 clock select, 0:clk54, 1:clk27

0x1b68Field NameVENC_DAC_CLK_SEL_CLK108
VENC_BIST_FIELD_SEL

R/W
R/W
R/W

Default
1'b0
1'b0

7
6
5
4
3
2

VENC_VIU_VSIN_SEL
VENC_VIU_HSIN_SEL
VENC_VPIN_VSIN_SEL
VENC_VPIN_HSIN_SEL
VENC_DAC1_CLK_SEL
VENC_DAC0_CLK_SEL

R/W
R/W
R/W
R/W
R/W
R/W

1'b0
1'b0
1'b0
1'b0
1'b0
1'b0

0x1b69Field NameVENC_ENCI_LINE

VENC_ENCI_PIXEL

0x1b6a

VENC_ENCP_LINE

0x1b6bField NameVENC_ENCP_LINEtrib

Bit(s)
9 -0

VENC_ENCP_PIXEL

Bit(s)
2 -0

VENC_INTCTRL
Bit(s)
13
12
11
10
9
8
7

is

VENC_STATA

Default-

Description
Current interlace encoder line

R/W
R

Default-

Description
Current interlace encoder line

R/W
R

Default-

Description
Current interlace encoder line

R/W
R

Default-

Description
Current interlace encoder line

Default-

Description
Current Venc Field

0x1b6cField NameVENC_ENCP_LINE

0x1b6dD

Bit(s)
9 -0e

Field NameVENC_ENCI_LINEut

Bit(s)
9 -0

R/W
R

to

Bit(s)
9 -0

H

VENC_ENCI_LINEarBit(s)
98dker

VENC_VIDEO_PROG_MODEnelBit(s)
12
11
10
9
8
7
6
5
4
3
2
1
0

Revision 1.1.4

Field NameVENC_FILED

R/W
R

0x1b6eField Name
ENCP_TIMER_INT_EN
ENCP_FLDINT_EN
ENCP_PXRST_EN
ENCP_TIMER_INT_EN
ENCP_LNRST_INT_EN
ENCP_PXRST_INT_EN
ENCL_TIMER_INT_EN

R/W
R/W
R/W
R/W
R/W
R /W
R /W
R/W

Default
0
0
0
0
0
0
0

157/336

Description

Progressive encoder filed change interrupt enable
Progressive encoder line change interrupt enable

AMLOGIC, Inc. Proprietary

S905 Datasheet

Field Name
ENCL_FLDINT_EN
ENCL_PXRST_EN
ENCI_TIMER_INT_EN
ENCI_TTXLOAD_INT_EN
ENCI_FDRST_INT_EN
ENCI_LNRST_INT_EN
ENCI_PXRST_INT_EN

Default
0
0
0
0
0
0

Description
Progressive encoder filed change interrupt flag
Progressive encoder line change interrupt flag
Interlace encoder teletext data load interrupt flag
Interlace encoder field reset interrupt flag
Interlace encoder filed change interrupt flag
Interlace encoder line change interrupt flag

R/W
R/W

Default
0

R/W
R/W

Default
8’h01

0x1b70Field NameVENC_VIDEO_TST_EN

0x1b71toH

Field NameVENC_VIDEO_TST_MDSELlField Name
ENCP_LNRST_INT_F
ENCP_PXRST_INT_F
ENCI_TTXLOAD_INT_F
ENCI_FDRST_INT_F
ENCI_LNRST_INT_F
ENCI_PXRST_INT_F

VENC_VIDEO_TST_MDSEL
Bit(s)
7-0

R/W
R /W
R /W
R /W
R /W
R /W
R /W

Interlace encoder teletext data interrupt enable
Interlace encoder field reset interrupt enable
Interlace encoder filed change interrupt enable
Interlace encoder line change interrupt enable

0x1b6f

VENC_VIDEO_TST_EN
Bit(s)
0

DescriptionneBit(s)
98
3
2
1
0

Default
0
0
0
0
0
0
0

dk
er

VENC_INTFLAG

R/W
R/W
R/W
R/W
R /W
R /W
R /W
R /W

Description
BIST enable

Description
BIST
Mode
0: TST_MODE_FIXVAL---- Fix Value on Y/Cb/Cr
1: TST_MODE_COLORBAR ---- 100/75 color bar
2: TST_MODE_THINLINE ---- Thin horizonl/vertical linesonscreen3: TST_MODE_DOTGRID ---- Dot grid on screenarBit(s)
6
5
4
3
2
1
0

Revision 1.1.4

0x1b72

Field NameVENC_VIDEO_TST_Ytrib

Bit(s)
9 -0

ut

VENC_VIDEO_TST_Ye

Notes: In none color bar mode, value is from register
TST_Y/TST_CB/TST_CR.

R/W
R/W

Default
10'd512

Description
BIST fix value Y

Notes: Value is 10 bists,X4 if convert from 8 Bits CCIR601 value
VENC_VIDEO_TST_CB

0x1b73

Field NameVENC_VIDEO_TST_CB

isBit(s)
9 -0

R/W
R/W

Default
10'd512

Description
BIST fix value Cb

D

Notes: Value is 10 bists,X4 if convert from 8 Bits CCIR601 value
VENC_VIDEO_TST_CR
Bit(s)
9 -0

0x1b74

Field NameVENC_VIDEO_TST_CR

R/W
R/W

Default
10'd512

Description
BIST fix value Cr

Notes: Value is 10 bists,X4 if convert from 8 Bits CCIR601 value
VENC_VIDEO_TST_CLRBAR_STRT
Bit(s)
12-0

0x1b75

Field NameVENC_VIDEO_TST_CLRBAR_STRT

R/W
R/W

Default
11'd275

Description
Colorbar BIST start position

Notes: VENC_VIDEO_TST_CLRBAR_STRT Interlace mode : 235, Progressive mode : 274
VENC_VIDEO_TST_CLRBAR_WIDTH

0x1b76

158/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
12 -0

Revision 1.1.4

Field NameVENC_VIDEO_TST_CLRBAR_WIDTH

R/W
R/W

Default
11'd360

Description
Colorbar BIST Width

Notes: VENC_VIDEO_TST_CLRBAR_WIDTH Interlace mode : 360, Progressive mode: 180
VENC_VIDEO_TST_VDCNT_STSET

Field NameVENC_VIDEO_TST_VDCNT_STSETVENC_VDAC_DACSEL0

Default
0

Description
BIST video data shifting setting, adjust this value if thedata sequence generated by BIST is incorrect.

R/W
R/W
R/W
R/W

Default00
4'h2

Description
VDAC delay (0-15 clocks)
1: select VDAC0 source from ATV demod
Video
Dac0
0: Interlace Y
1:
2: S-Video luma
3:
S-Video
4: Interlace Pb
5:Interlace
6:
Interlace
7:
Interlace
8:
Interlace
9:
Progressivea: Progressive Pb
b: Progressive Pr
c: Progressive R
d: Progressive G
e: Progressive B
f: VDAC test value (VENC_VDAC_TST_VAL)
0x10: upsampled data00x11: upsampled data1
0x12 upsampled data2

0x1b78Field NameVENC_VDAC_DLY
VENC_VDAC_SEL_ATV_DMD
VENC_VDAC_DACSEL0

selection
CVBS
ChromaPr
R
GB
Y

VENC_VDAC_DACSEL2

Field NameVENC_VDAC_DACSEL3

Field NameVENC_VDAC_DACSEL4
Bit(s)

Bit(s)

R/W

Default
16’h5

Description
Same as above

R/W

Default
16’h1

Description
Same as above

R/W

Default
16’h2

Description
Same as above

R/W

Default
16’h3

Description
Same as above

0x1b7dField NameVENC_VDAC_SETTING

Description
Same as above

0x1b7cField NameVENC_VDAC_DACSEL5

Default
16’h4

0x1b7bD

Bit(s)

R/W

0x1b7aisBit(s)

0x1b79Field NametribBit(s)ut

VENC_VDAC_DACSEL1

e

to

H

ar

dk
er

ne

Bit(s)
15-12
5
4-0

R/W
R/W

l

Bit(s)
1-0

0x1b77

0x1b7e159/336

AMLOGIC, Inc. ProprietaryBit(s)
0
1
2
3
4
5
6
7
8
9
12
13
15

Revision 1.1.4

Field NameVENC_VDAC0_PWDN
VENC_VDAC1_PWDN
VENC_VDAC2_PWDN
VENC_VDAC3_PWDN
VENC_VDAC4_PWDN
VENC_VDAC5_PWDN

Default
0
0
0
0
0
0
0
0
0
0
0
0
0

Description
Powers down video DAC 0
Powers down video DAC 1
Powers down video DAC 2
Powers down video DAC 3
Powers down video DAC 4
Powers down video DAC 5
UnusedPowers down all video DACs
VDAC SOG signal (Sync on green, not used)
VDAC IREN signal (7.5 IRE setup, not used)
VDAC sync signal when SYBL_en is 0
VDAC blank signal when SYBL_EN is 0
Enable tv encoder to control VDAC sync and blank

R/W
R/W

Default
10'h200

Description
Video DAC test value

R/W
R/W

Default
0

R/W
R/W

Default
8'h7

VENC_VDAC_TST_VAL

Field NameVENC_VDAC_TST_VAL

ENCP_VIDEO_EN
Bit(s)
0

0x1b80Field Name
ENCP_VIDEO_EN

ENCP_VIDEO_SYNC_MODE

0x1b82

Field Name
ENCP_VIDEO_PB_SCL

ENCP_VIDEO_PR_SCL

Field Name
ENCP_VIDEO_PR_SCL

ENCP_VIDEO_SYNC_SCL
Bit(s)
7 -0

Bit(s)
7 -0

R/W
R/W

Default
8'd81

Description
Y scaleR/W
R/W

Default
8'd79

Description
Cb scale

R/W
R/W

Default
8'd79

Description
Cr scale

R/W
R/W

Default
8'd128Description
Analog Sync value scale

R/W
R/W

Default
8'd128Description
Macrovision value scale

0x1b87

Field Name
ENCP_VIDEO_MACV_SCL

ENCP_VIDEO_Y_OFFST

Description
Macrovision enable

0x1b86

Field Name
ENCP_VIDEO_SYNC_SCL

ENCP_VIDEO_MACV_SCL

Default
00x1b85D

Bit(s)
7 -0

R/W
R/W

0x1b84isBit(s)
7 -0

trib

ENCP_VIDEO_PB_SCL

ut

0x1b83

Field Name
ENCP_VIDEO_Y_SCL

Description
Video input Synchronization mode ( 4:Slave mode,
7:Master mode)e

Field Name
ENCP_MACV_EN

ENCP_VIDEO_Y_SCL
Bit(s)
7 -0

H

Field Name
ENCP_VIDEO_SYNC_MODE

ENCP_MACV_EN
Bit(s)
0

0x1b81toBit(s)
7 -0

Description
Progressive encoder enablearBit(s)
9 -0

0x1b7fnel

VENC_VDAC_ALL_PWDN
VENC_VDAC_SOG
VENC_VDAC_IREN
VENC_VDAC_SYNC
VENC_VDAC_BLNK
VENC_VDAC_SYBL_EN

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

dk
er

S905 Datasheet

0x1b88160/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Field Name
ENCP_VIDEO_Y_OFFST

ENCP_VIDEO_PB_OFFST

R/W
R/W

Default
10'h0

Description
Pr offset

R/W
R/W

Default
10'h0

Description
Sync pulse offset

R/W
R/W

Default
10'h0

Description
Macrovision offset

R/W
R/W
R/W

Dfault000x1b8cField Name
ENCP_VIDEO_MACV_OFFST

0x1b8dField Name
ENCP_PX_LN_CNT_SHADOW_EN
ENCP_VIDEO_MODE_DE_V

Description
pixel count and line count shadow enable
1=DE signal’s polarity is active high.
0=DE signal’s polarity is active low.
13
ENCP_VIDEO_MODE_EN_VSO_OFLD_FIX_EN
R/W 0
1=Extend ENCP_VIDEO_MAX_PXCNT by 1 pixel.
0=Treat ENCP_VIDEO_MAX_PXCNT as is.
12
ENCP_VIDEO_MODE_EN_FIELD_ODD
R/W 0
Enable odd field ( for 1080i)
11
ENCP_VIDEO_MODE_EN_VSO_OFLD
R/W 0
Enable VSO odd field
10
ENCP_VIDEO _MODE_EN_VAVON_OFLD
R/W 0
Enable Vertical Active On for odd field
9
ENCP_VIDEO _MODE_EN_EQU_OFLD
R/W 0
Enable Equalization pulse for odd field
8
ENCP_VIDEO _MODE_EN_EQU
R/W 0
Enable Equalization pulse
6
ENCP_VIDEO _MODE_EN_HSEQ_SWITCH
R/W 0
Enable Hsync and equalization pulse switch in center
5
ENCP_VIDEO _MODE_EN_VP_OFLD
R/W 0
Enable Vertical Pulse for odd field
4
ENCP_VIDEO _MODE_EN_VP2
R/W 0
Enable 2nd vertical pulse in a line (1080i)
3
ENCP_VIDEO _MODE_EN_VPE_HALF_OFLD
R/W 0
Vertical pulse on end line of odd field is half
2
ENCP_VIDEO _MODE_EN_VPB_HALF_OFLD
R/W 0
Vertical pulse on begin line of odd field is half
1
ENCP_VIDEO _MODE_EN_VPE_HALF
R/W 0
Vertical pulse on end line of even field is half
0
ENCP_VIDEO _MODE_EN_VPB_HALF
R/W 0
Vertical pulse on begin line of even field is half
Note: This register should be set as 0x140 for 720p , and 0x1ffc for 1080i, and 0x0 for 480p/576p

Field Name
ENCP_SP_TIMING_CTRL
ENCP_CR_BAPASS_LIM
ENCP_CB_BAPASS_LIM
ENCP_Y_BAPASS_LIM
ENCP_SEL_GAMMA_RGB_IN

D

Bit(s)
15-14
13
12
11
10
9-8
7
6
5
4
3
2 :0

0x1b8eis

ENCP_VIDEO_MODE_ADV

tr
ib

ut

e

to

H

ar

Bit(s)
15
14

Description
Pb offsetlField Name
ENCP_VIDEO_SYNC_OFFST

ENCP_VIDEO_MODE

Default
10'h0

0x1b8b

ENCP_VIDEO_MACV_OFFST
Bit(s)
9 -0

R/W
R/W

0x1b8aField Name
ENCP_VIDEO_PR_OFFST

ENCP_VIDEO_SYNC_OFFST
Bit(s)
9 -0

Description
Y offset

0x1b89Field Name
ENCP_VIDEO_PB_OFFST

ENCP_VIDEO_PR_OFFST
Bit(s)
9 -0

Default
10'h3c0neBit(s)
9 -0

R/W
R/W

dk
er

Bit(s)
9 -0

Revision 1.1.4

ENCP_VIDEO_MODE_ADV_EN_HUE_MATRIXENCP_VIDEO_MODE_ADV_SWAP_PBPR
ENCP_VIDEO_MODE_ADV_EN_HS_PBPR
ENCP_VIDEO_MODE_ADV_GAIN_HDTV
ENCP_VIDEO_MODE_ADV_VFIFO_EN
ENCP_VIDEO_MODE_ADV_VFIFO_UPMODE

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0
0
0
0
1

161/336

Description

UnusedEnable HUE matrix
Swap PB PR
Enable sync pulse on PB PRYPBPR gain as HDTV type
Data input from VFIFO
Sampling rate:
0: 1
1: ½
2: ¼

AMLOGIC, Inc. Proprietary

S905 Datasheet

Field Name

ENCP_DBG_PX_RST

ENCP_DBG_LN_RST

trib

Field Name
ENCP_VIDEO_Y_DLY
ENCP_VIDEO_CB_DLY
ENCP_VIDEO_CR_DLY

Default
00

Description
Pixel Interrupt enable
Pixel value that trig the interrupt

R/W
R/W
R/W

Default
0
0

R/W
R/W

Default
240

is

ne

ar

Description
Filter switch start point

R/W
R/W

Default
1657

Description
Filter switch end point

R/W
R/W
R/W
R/W

Default
16’h0
16’h0
16’h0

Description
Y delay
Cb delay
Cr delay

R/W
R/W

Default
13'd1715

Description
Max pixel counter

R/W
R/W

Default
13'd1715

Description
Analog Horizontal Sync Begin

R/W
R/W

Default
13'd125

Description
Analog Horizontal Sync End

R/W
R/W

Default
13'd88Description
Analog Horizontal switch point (for HDTV)

D

0x1b99Field Name
ENCP_VIDEO_HSPULS_END

0x1b9aField Name
ENCP_VIDEO_HSPULS_SWITCHENCP_VIDEO_VSPULS_BEGIN

Description
Line Interrupt enable
Line value that trig the interrupt

0x1b98Field Name
ENCP_VIDEO_HSPULS_BEGIN

ENCP_VIDEO_HSPULS_SWITCH
Bit(s)
12 -0

R/W
R/W
R/W

0x1b97

Field Name
ENCP_VIDEO_MAX_PXCNT

ENCP_VIDEO_HSPULS_END
Bit(s)
12 -0

Description
Debug mode line reset enable
Debug mode line reset valuel0x1b96

ENCP_VIDEO_HSPULS_BEGIN
Bit(s)
12 -0

Default00H0x1b95

Field Name
ENCP_VIDEO_YFP2_HTIMEENCP_VIDEO_MAX_PXCNT
Bit(s)
12 -0

R/W
R/W
R/W

0x1b94

Field Name
ENCP_VIDEO_YFP1_HTIMEENCP_VIDEO_YC_DLY
Bit(s)
5 –4
3 –2
1 –0

Description
Debug mode pixel reset enable
Debug mode pixel reset value

0x1b93

Field Name
ENCP_DBG_LN_INT_EN
ENCP_DBG_LN_INT_VAL

ENCP_VIDEO_YFP2_HTIME
Bit(s)
12 -0

Default
00dker

Field Name
ENCP_DBG_PX_INT_EN
ENCP_DBG_PX_INT_VAL

ENCP_VIDEO_YFP1_HTIME
Bit(s)
12 -0

R/W
R/W
R/W

0x1b92

ENCP_DBG_LN_INT
Bit(s)
15
10 -0

Description
3: 1/80x1b91

Field Name
ENCP_DBG_LN_RST_EN
ENCP_DBG_LN_RST_VAL

ENCP_DBG_PX_INT
Bit(s)
15
12 -0

DefaulttoBit(s)
15
10 -0

R/W

0x1b90Field Name
ENCP_DBG_PX_RST_EN
ENCP_DBG_PX_RST_VALeBit(s)
15
12 -0

ut

Bit(s)

Revision 1.1.4

0x1b9b162/336

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S905 Datasheet

Field Name
ENCP_VIDEO_VSPULS_BEGIN

ENCP_VIDEO_VSPULS_END

ENCP_VIDEO_VSPULS_BLINE

0x1ba3

Field Name
ENCP_VIDEO_HAVON_END

Bit(s)
12 -0

Bit(s)
12 -0

tr
ib

is

D

R/W
R/W

Default
13'd0

Description
Analog Equalization pulse begin point

R/W
R/W

Default
13'd1589

R/W
R/W

Default
11'd5

l

ar

Description
Analog Equalization pulse end point

Description
Equalization pulse begin line

R/W
R/W

Default
11'd10Description
Equalization pulse end line

R/W
R/W

Default
13'd1656

Description
Vertical active video end point

R/W
R/W

Default
13'd217

Description
Vertical active video start point

R/W
R/W

Default
11'd519

Description
Vertical active video on end line

R/W
R/W

Default
11'd42

Description
Vertical active video on start line

R/W
R/W

Default
16

Description
Digital Hsync out start point

R/W
R/W

Default
32

Description
Digital Hsync out end point

0x1ba6

Field Name
ENCP_VIDEO_VAVON_BLINE

0x1ba7

Field Name
ENCP_VIDEO_HSO_BEGIN

ENCP_VIDEO_HSO_END

Description
Vso end line

0x1bafField Name
ENCP_VIDEO_VAVON_ELINEENCP_VIDEO_HSO_BEGIN

Default
11'd100x1ba4

Field Name
ENCP_VIDEO_HAVON_BEGIN

ENCP_VIDEO_VAVON_BLINE
Bit(s)
10 -0

R/W
R/W

H

0x1ba2

Field Name
ENCP_VIDEO_EQPULS_ELINEENCP_VIDEO_VAVON_ELINE
Bit(s)
10 -0

Description
Vso begin line

0x1ba1

Field Name
ENCP_VIDEO_EQPULS_BLINEENCP_VIDEO_HAVON_BEGIN
Bit(s)
12 -0

Default
11'd5

0x1ba0Field Name
ENCP_VIDEO_EQPULS_END

ENCP_VIDEO_HAVON_END
Bit(s)
12 -0

R/W
R/W

dk
er

Field Name
ENCP_VIDEO_EQPULS_BEGIN

ENCP_VIDEO_EQPULS_ELINE
Bit(s)
10 -0

Description
Analog Veritcal Sync end point

0x1b9f

ENCP_VIDEO_EQPULS_BLINE
Bit(s)
10 -0

Default
13'd1589

neField Name
ENCP_VIDEO_VSPULS_ELINEENCP_VIDEO_EQPULS_END
Bit(s)
12 -0

R/W
R/W

0x1b9e

ENCP_VIDEO_EQPULS_BEGIN
Bit(s)
12 -0

Description
Analog Veritcal Sync begin point

0x1b9dField Name
ENCP_VIDEO_VSPULS_BLINEENCP_VIDEO_VSPULS_ELINE
Bit(s)
10 -0

Default
13'd0toBit(s)
10 -0

R/W
R/W

0x1b9cField Name
ENCP_VIDEO_VSPULS_ENDe

Bit(s)
12 -0

ut

Bit(s)
12 -0

Revision 1.1.4

0x1ba8Field Name
ENCP_VIDEO_HSO_END

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S905 Datasheet

Revision 1.1.4

ENCP_VIDEO_VSO_BEGIN

0x1ba9Field Name
ENCP_VIDEO_VSO_BEGIN

ENCP_VIDEO_VSO_END

Field Name
ENCP_VIDEO_VSO_BLINE

Bit(s)
13 -0

Bit(s)
10 -0

R/W
R/W

Default
1'b1

R/W
R/W

Default
10'd524

tr
ib

l

dk
er

Description
Enable curve wave on analog sync edgearDescription
Max line counter

Default
0

Description
Analog Sync Pulse value 1

R/W
R/W

Default
480

Description
Analog Sync Pulse value 2

R/W
R/W

Default
10'd240

Description
Blank Y value

R/W
R/W

Default
10'd512

Description
Blank Pb value

R/W
R/W

Default
10'd512

Description
Blank Pr value

R/W
R/W

Default2

Description
Horizontal offset after HSI

R/W
R/W

Default
0

Description
Vertical offset after VSI

is

0x1bb4D

Field Name
ENCP_VIDEO_BLANKPR_VAL

0x1bb5

Field Name
ENCP_VIDEO_HOFFST

0x1bb6

Field Name
ENCP_VIDEO_VOFFST

ENCP_VIDEO_RGB_CTRL

Description
Digital Vsync out end line

0x1bb3

Field Name
ENCP_VIDEO_BLANKPB_VAL

ENCP_VIDEO_VOFFST

Default
39

H

0x1bb2

Field Name
ENCP_VIDEO_BLANKY_VAL

ENCP_VIDEO_HOFFST

R/W
R/W

to

Field Name
ENCP_VIDEO_SY2_VAL

ENCP_VIDEO_BLANKPR_VAL
Bit(s)
9 -0

Description
Digital Vsync out start line

R/W
R/W

0x1bb1

ENCP_VIDEO_BLANKPB_VAL
Bit(s)
9 -0

Default
37

0x1bb0Field Name
ENCP_VIDEO_SY_VAL

ENCP_VIDEO_BLANKY_VAL
Bit(s)
9 -0

R/W
R/W

0x1baeField Name
ENCP_VIDEO_MAX_LNCNT

ENCP_VIDEO_SY2_VAL
Bit(s)
9 -0

Description
Digital Vsync out end point

0x1badField Name
ENCP_VIDEO_SYNC_WAVE_CURVEENCP_VIDEO_SY_VAL
Bit(s)
9 -0

Default
32

neField Name
ENCP_VIDEO_VSO_ELINEENCP_VIDEO_MAX_LNCNT
Bit(s)
10 -0

R/W
R/W

0x1bac

ENCP_VIDEO_SYNC_WAVE_CURVE
Bit(s)
0

Description
Digital Vsync out start point

0x1bab

ENCP_VIDEO_VSO_ELINE
Bit(s)
10 -0

Default
160x1baaField Name
ENCP_VIDEO_VSO_END

ENCP_VIDEO_VSO_BLINE
Bit(s)
10 -0

R/W
R/W

e

Bit(s)
12 -0

ut

Bit(s)
12 -0

0x1bb7164/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Field Name
CFG_BLANK_DLY
CFG_MACV_R_EN
CFG_MACV_G_EN
CFG_MACV_B_EN
CFG_RGB_SEPERATE_BLANK
CFG_SYNC_ON_R
CFG_SYNC_ON_G
CFG_SYNC_ON_B

Default
4
0
0
0
0
0
1
0

Description

Description
Disable auto reset Y filter each line
Disable auto reset C filter each line
If true, chroma input is 444 instead of 422
By pass all ENCP filter
Swap chroma Cb/Cr
Chroma filter by pass control
4 Bits Y filter parameter 1, will be effect after
ENCP_VIDEO_YFP1_HTIME
Bit 3 : Edge modeBit 2:0 : By pass ctrl
4 Bits Y filter parameter 1, will be effect after
ENCP_VIDEO_YFP1_HTIME
Bit 3 : Edge modeBit 2:0 : By pass ctrl

Field Name
ENCP_VIDEO_FILT_YF_NO_RSTENCP_VIDEO_FILT_CF_NO_RST
CFILT_CHROMA444_EN
ENCP_VIDEO_FILT_BYPASS_TOP
ENCP_VIDEO_FILT_CHROMA_SWAP
ENCP_VIDEO_FILT_CF_BYPASSENCP_VIDEO_FILT_YF_CFG1

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0

3:0

ENCP_VIDEO_FILT_YF_CFG2

R/W

0

tr
ib

Field Name
ENCP_VIDEO_OFLD_VSO_OFST_BEGIN
ENCP_VIDEO_OFLD_VSO_OFST_END
ENCP_VIDEO_OFLD_VAVON_OFST_BEGIN
ENCP_VIDEO_OFLD_VAVON_OFST_END

H
Default01
00

Description
Odd field Vsync pulse offset begin, 4 Bits signed.
Odd field Vsync pulse offset end, 4 Bits signed.
Odd field EQU pulse offset begin, 4 Bits signed.
Odd field EQU pulse offset end, 4 Bits signed.

R/W
R/W
R/W
R/W
R/W

Default
01
1
1

Description
Odd field VSO offset begin, 4 Bits signed.
Odd field VSO offset end, 4 Bits signed.
Odd field VAVON offset begin, 4 Bits signed.
Odd field VAVON offset end, 4 Bits signed.

R/W
R/W
R/W

Default
00

Description
CbCr matrix parameter Ma (signed value)
CbCr matrix parameter Mb (signed value)

0x1bbbis

ENCP_ VIDEO_MATRIX_CB

Field Name
ENCP_VIDEO_MATRIX_MA
ENCP_VIDEO_MATRIX_MB

D

Bit(s)
15:8
7:0

0x1bba

R/W
R/W
R/W
R/W
R/W

e

ENCP_ VIDEO_OFLD_VOAV_OFST
Bit(s)
15:12
11:8
7:4
3:0

0x1bb9Field Name
ENCP_VIDEO_OFLD_VPULS_OFST_BEGIN
ENCP_VIDEO_OFLD_VPULS_OFST_END
ENCP_VIDEO_OFLD_EQPULS_OFST_BEGIN
ENCP_VIDEO_OFLD_EQPULS_OFST_END

ut

Bit(s)
15:12
11:8
7:4
3:0

to

ENCP_ VIDEO_OFLD_VPEQ_OFSTar

Bit(s)
15
14
14
12
11
10:8
7:4

l

0x1bb8ne

ENCP_VIDEO_FILT_CTRL

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

dk
er

Bit(s)
12-8
6
5
4
3
2
1
0

Revision 1.1.4

Note: These 2 register is for HUE adjustment. The formula is : Cb’ = Cb*Ma + Cr*Mb, Cr’ = Cb*Mc + Cr*Md(effective only when Enable HUE matrix by Bit ENCP_VIDEO_MODE_ADV[7])Note : see the descritption of register ENCI_CMPN_MATRIX_CB.
ENCP_ VIDEO_MATRIX_CR
Bit(s)
15:8
7:0

0x1bbcField Name
ENCP_VIDEO_MATRIX_MC
ENCP_VIDEO_MATRIX_MD

ENCP_ VIDEO_RGBIN_CTRL

R/W
R/W
R/W

Default
00

Description
CbCr matrix parameter Mc (signed value)
CbCr matrix parameter Md (signed value)

0x1bbd165/336

AMLOGIC, Inc. ProprietaryField Name

ENCP_MACV_BLANKY_VAL

Bit(s)
15 -0

R/W
R/W

Default
1

R/W
R/W

Default
61

R/W
R/W

Default
141

lne

Description
Macrovision pseudo sync start

Description
Macrovision AGC pulse start

Description
Macrovision AGC pulse end

Default
175

Description
Macrovision wave end

R/W
R/W

Default
11

Description
Macrovision start line

R/W
R/W

Default
19

Description
Macrovision end line

R/W
R/W

Default
16'h7dcd

Description
Macrovistion Cyclic Variation Time step Counter, Low
16Bits

R/W
R/W

Default
4'h3

Description
Macrovistion Cyclic Variation Time step Counter, High
4Bits

R/W
R/W

Default
16'd3068

Description
Macrovistion Cyclic Variation Time start going down

e

R/W
R/W

D

0x1bcbField Name
ENCP_MACV_TIME_DOWN

ENCP_MACV_TIME_LO

Description
Macrovision first pseudo sync start

0x1bcaField Name
ENCP_MACV_TS_CNT_MAX_H

ENCP_MACV_TIME_DOWN

Default
238

0x1bb9Field Name
ENCP_MACV_TS_CNT_MAX_L

ENCP_MACV_TS_CNT_MAX_H
Bit(s)
3 -0

ut

tr
ib

Field Name
ENCP_MACV_ENDLINEENCP_MACV_TS_CNT_MAX_L
Bit(s)
15 -0

R/W
R/W

0x1bc8is

Bit(s)
9 -0

0x1bc7

Field Name
ENCP_MACV_STRTLINE

ENCP_MACV_ENDLINE

Description
Macrovision max Y valueH0x1bc6

Field Name
ENCP_MACV_WAVE_END

ENCP_MACV_STRTLINE
Bit(s)
9 -0

Default590

0x1bc5

Field Name
ENCP_MACV_AGC_END

ENCP_MACV_WAVE_END
Bit(s)
7 -0

R/W
R/W

0x1bc4

Field Name
ENCP_MACV_AGC_STRT

ENCP_MACV_AGC_END
Bit(s)
7 -0

Description
Macrovision Blank Y value

0x1bc3

Field Name
ENCP_MACV_PSSYNC_STRT

ENCP_MACV_AGC_STRT
Bit(s)
7 -0

Default
00x1bc2

Field Name
ENCP_MACV_1ST_PSSYNC_STRT

ENCP_MACV_PSSYNC_STRT
Bit(s)
7 -0

R/W
R/W

0x1bc1

Field Name
ENCP_MACV_MAXY_VAL

ENCP_MACV_1ST_PSSYNC_STRT
Bit(s)
10 -0

Description
USE RGB data from VIU
VIU RGB IN BLANK ZERO

0x1bc0Field Name
ENCP_MACV_BLANKY_VAL

ENCP_MACV_MAXY_VAL
Bit(s)
9 -0

Default
00ar

Bit(s)
9 -0

R/W
R/W
R/W

to

Bit(s)
1
0

Revision 1.1.4

dker

S905 Datasheet

0x1bbc166/336

AMLOGIC, Inc. ProprietaryField Name
ENCP_MACV_TIME_LO

ENCP_MACV_TIME_UP

ENCP_MACV_TIME_RST

ENCP_VBI_SETTING

ENCP_VBI_BEGIN

0x1bd30x1bd4

Description
Enable VBI
VBI data no curve at edge

R/W
R/W
R/W

Default
0x16
0x28

R/W
R/W

Default
0

Description
VBI line number
VBI data bitcountDescription
VBI pulse begin point

Default
0

Description
VBI data bitwidth

R/W
R/W

Default
0

Description
VBI pulse value when data bit is high

R/W
R/W

Default
0

Description
VBI data 0 (LSB first)

R/W
R/W

Default
0

Description
VBI data 1 (LSB first)

R/W
R/W
R/W
R/W

Default000Description
gain bypass, 1:bypass
Unusedgain setting 8-bit

R/W
R/W

Default
0

Description
offset setting, 11 Bits

R/W
R/W
R/W

Default
00

Description
gain bypass, 1:bypass
Unused0x1bd6isField Name
ENCP_VBI_DATA1D

VENC_VDAC_DAC0_GAINCTRL

0x1bf0Field Name
DAC_GAIN_BP
DAC_GAINVENC_VDAC_DAC0_OFFSET

0x1bf1

Field NameDAC_OFFSET_VAL

VENC_VDAC_DAC1_GAINCTRL
Bit(s)
15
14-8

e

tr
ib

Field Name
ENCP_VBI_DATA0ut

0x1bd5 )ENCP_VBI_DATA1

Bit(s)
10-0

Default
0
0

R/W
R/W

Field Name
ENCP_VBI_HVAL

ENCP_VBI_DATA0

Bit(s)
15
14-8
7-0

R/W
R/W
R/W

to

Field Name
ENCP_VBI_WIDTHENCP_VBI_HVAL

Bit(s)
15-0

Description
Macrovistion Cyclic Variation reset

H

ENCP_VBI_WIDTH

Bit(s)
15-0

Default
16'd4956

0x1bd2
Field Name
ENCP_VBI_BEGIN

Bit(s)
9-0

R/W
R/W

0x1bd1

Field Name
ENCP_VBI_LN
ENCP_VBI_CNT

Bit(s)
12-0

Description
Macrovistion Cyclic Variation Time start going up

0x1bd0Field Name
ENCP_VBI_EN
ENCP_VBI_NO_CURVE

Bit(s)
12-0

Default
16'd4366l

ENCP_VBI_CTRL

Bit(s)
1
0

R/W
R/W

0x1bceField Name
ENCP_MACV_TIME_RST

Bit(s)
1
0

Description
Macrovistion Cyclic Variation Time start maitain low

0x1bcdField Name
ENCP_MACV_TIME_UP

Bit(s)
15 -0

Default
16'd3658

ne

Bit(s)
15 -0

R/W
R/W

ar

Bit(s)
15 -0

Revision 1.1.4

dker

S905 Datasheet

Field Name
DAC_GAIN_BP

0x1bf2

167/336

AMLOGIC, Inc. ProprietaryField Name
DAC_GAINVENC_VDAC_DAC1_OFFSETVENC_VDAC_DAC2_GAINCTRL

DAC_GAINDAC_GAIN

0x1bf9trib

Field NameDAC_OFFSET_VAL

Default
0

Description
offset setting, 11 Bits

R/W
R/W
R/W
R/W

Default
0
0
0

R/W
R/W

Default
0

Description
gain bypass, 1:bypass
Unusedgain setting 8-bit

Description
offset setting, 11 Bits

R/W
R/W
R/W
R/W

Default000Description
gain bypass, 1:bypass
Unusedgain setting 8-bit

R/W
R/W

Default
0

Description
offset setting, 11 Bits

R/W
R/W
R/W
R/W

Default000Description
gain bypass, 1:bypass
Unusedgain setting 8-bit

R/W
R/W

Default
0

Description
offset setting, 11 Bits

R/W
R/W
R/W
R/W
R/W
R/W

Default000
00Description

0x1bfaisField Name
DAC_GAIN_BP
DAC_GAIND

Bit(s)
14
13
12
11-6
5-0

R/W
R/W

to

0x1bf8Field Name
DAC_GAIN_BP

0x1bfbField NameDAC_OFFSET_VAL

VENC_VDAC_FIFO_CTRL

Description
gain bypass, 1:bypass
Unusedgain setting 8-bit

0x1bf7

Field NameDAC_OFFSET_VAL

VENC_VDAC_DAC5_OFFSET
Bit(s)
10-0

Default
000lDAC_GAINVENC_VDAC_DAC5_GAINCTRL
Bit(s)
15
14-8
7-0

R/W
R/W
R/W
R/W

ar

Field Name
DAC_GAIN_BP

VENC_VDAC_DAC4_OFFSET
Bit(s)
10-0

Description
offset setting, 11 Bits

0x1bf6

VENC_VDAC_DAC4_GAINCTRL
Bit(s)
15
14-8
7-0

Default
0

ne

Field NameDAC_OFFSET_VAL

VENC_VDAC_DAC3_OFFSET
Bit(s)
10-0

R/W
R/W

0x1bf5

VENC_VDAC_DAC3_GAINCTRL
Bit(s)
15
14-8
7-0

Description
gain setting 8-bit

0x1bf4

Field Name
DAC_GAIN_BP

VENC_VDAC_DAC2_OFFSET
Bit(s)
10-0

Default
0H

Bit(s)
15
14-8
7-0

R/W
R/W

0x1bf3

Field NameDAC_OFFSET_VALeBit(s)
10-0

ut

Bit(s)
7-0

Revision 1.1.4

dker

S905 Datasheet

0x1bfcField NameFIFO_EN_ENCTFIFO_EN_ENCIFIFO_EN_CNCP
DAC_CLOCK_2X
DAC_CLOCK_4X

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S905 Datasheet

Revision 1.1.4

ENCI_DVI_HSO_BEGIN

0x1c02

trib

0x1c04

Field NameENCI_DVI_VSO_ELINE_EVN

is

D

l
ne

Description
DVI/HDMI Interlace HSO end position.

R/W
R/W

Default
261

Description
DVI/HDMI Interlace VSO start line for even field.

R/W
R/W

Default
261

Description
DVI/HDMI Interlace VSO start line for odd field.

R/W
R/W

Default
1

Description
DVI/HDMI Interlace VSO end line for even field.

R/W
R/W

Default2

Description
DVI/HDMI Interlace VSO end line for odd field.

R/W
R/W

Default
855

Description
DVI/HDMI Interlace VSO begin position for even field.

R/W
R/W

Default
1713

Description
DVI/HDMI Interlace VSO begin position for odd field.

R/W
R/W

Default
1713

Description
DVI/HDMI Interlace VSO end position for even field.

0x1c07

Field NameENCI_DVI_VSO_BEGIN_ODD

ENCI_DVI_VSO_END_EVN
Bit(s)
10-0

Default
121

0x1c06

Field NameENCI_DVI_VSO_BEGIN_EVN

ENCI_DVI_VSO_BEGIN_ODD
Bit(s)
10-0

R/W
R/W

Description
DVI/HDMI Interlace HSO begin position.

0x1c05

Field NameENCI_DVI_VSO_ELINE_ODD

ENCI_DVI_VSO_BEGIN_EVN
Bit(s)
10-0

0x1c03

Field NameENCI_DVI_VSO_BLINE_ODD

ENCI_DVI_VSO_ELINE_ODD
Bit(s)
8-0

Default1713

toField NameENCI_DVI_VSO_BLINE_EVN

ENCI_DVI_VSO_ELINE_EVN
Bit(s)
8-0

R/W
R/W

H

Field NameENCI_DVI_HSO_END

ENCI_DVI_VSO_BLINE_ODD
Bit(s)
8-0

Description
vsync invert
hsync invert
Oev3 invert
Oev2 invert
Cpv2 invert
Cph3 invert
Cph2 invert
Cph1 invert
oeh invert
vcom invert
Stv2 invert
Stv1 invert
Cpv1 invert
Oev1 invert
Sth1 invert
Sth2 invert

0x1c01

ENCI_DVI_VSO_BLINE_EVN
Bit(s)
8-0

Default
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0

ar

ENCI_DVI_HSO_END
Bit(s)
10-0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0x1c00Field NameENCI_DVI_HSO_BEGINe

Bit(s)
10-0

0x1bfdField Nameut

Bit(s)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

dk
er

ENCL_TCON_INVERT_CTL

0x1c08Field NameENCI_DVI_VSO_END_EVN

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Revision 1.1.4

ENCI_DVI_VSO_END_ODD
Bit(s)
10-0

0x1c09Field NameENCI_DVI_VSO_END_ODD

ENCI_CFILT_CTRL2

Default
855

Description
DVI/HDMI Interlace VSO end position for odd field.

R/W
R/W
R/W
R/W
R/W

Default00
00Description
Filter CVBS Cb delay. Delay same as below.
Filter CVBS Cr delay. Delay same as below.
Filter component Cb delay. Delay same as below.
Filter component Cr delay.
0=No delay;
1=Delay by 1 cycle;…
6=Delay by 6 cycles;
7-16=Reserved.

R/W
R/W
R/W
R/W
R/W

Default03
2
1

Description
dac3
dac2
dac1
dac0

R/W
R/W
R/W
R/W

Default05
40x1c0aField NameENCI_CFILT_CVBS_CB_DLY
ENCI_CFILT_CVBS_CR_DLY
ENCI_CFILT_CMPT_CB_DLY
ENCI_CFILT_CMPT_CR_DLY

Bit(s)
15-12
11-8
7-4
3-0

Field NameVENC_I_DACSEL_0
VENC_I_DACSEL_0
VENC_I_DACSEL_0
VENC_I_DACSEL_0

ENCP_DACSEL0

0x1c0d0x1c0eField Name
DVI_SYNC_SEL
VENC_P_DACSEL_1
VENC_P_DACSEL_1

is

Bit(s)
9-8
7-4
3-0

D

ENCP_MAX_LINE_SWITCH_POINT
Bit(s)
12-0

ut

ENCP_DACSEL1e

Field NameVENC_P_DACSEL_0
VENC_P_DACSEL_0
VENC_P_DACSEL_0
VENC_P_DACSEL_0

trib

Bit(s)
15-12
11-8
7-4
3-0

H

Field Name
DVI_SYNC_SEL
VENC_I_DACSEL_1
VENC_I_DACSEL_1

to

Bit(s)
9-8
7-4
3-0

ar

ENCI_DACSEL1 0x1c0cdker

ENCI_DACSEL0 0x1c0bnelBit(s)
15-12
11-8
7-4
3-0

R/W
R/W

Description
Dvi_sync_sel
dac5
dac4

R/W
R/W
R/W
R/W
R/W

Default03
2
1

Description
dac3
dac2
dac1
dac0

R/W
R/W
R/W
R/W

Default
0
5
4

Description
Dvi_sync_sel
dac5
dac4

R/W
R/W

Default
13’h1fff

Description
max_pxcnt = (line >= cfg_max_line_switch_point) ?
max_pxcnt_tmp - 1: max_pxcnt_tmp;

R/W
R/W

Default
0

Description
Enci_tst_en

R/W
R/W

Default
1

Description
Video test mode selectl:
0: enci_tst_mode_fixval
1: enci_tst_mode_colorbar

0x1c0fField Name
ENCP_DE_V_END_ODD

ENCI_TST_EN 0x1c10
Bit(s)
0

ENCI_TST_MDSEL
Bit(s)
1-0

Field NameENCI_TST_EN

0x1c11
Field NameENCI_TST_MDSEL

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AMLOGIC, Inc. ProprietaryBit(s)

Revision 1.1.4

Field Name

R/W

Default

Description
2: enci_tst_mode_thinline
3: enci_tst_mode_dotgrid

R/W
R/W

Default
512

Description
Default value of Y in test mode

R/W
R/W

Default
512

Description
Default value of Pb in test mode

R/W
R/W

Default
512

Description
Default value of Pr in test mode

R/W
R/W

Default
275

R/W
R/W

Default
360

dker

S905 Datasheet

R/W
R/W

Default
0

ENCI_TST_Y 0x1c12
Bit(s)
9-0

Field NameENCI_TST_Y

ENCI_TST_CB 0x1c13
Bit(s)
9-0

Field NameENCI_TST_CB

Field NameENCI_TST_CRne

Bit(s)
9-0

ENCI_TST_CLRBAR_STRT 0x1c15
Bit(s)
10-0

Field NameENCI_TST_CLRBAR_STRT

Bit(s)
10-0

Field NameENCI_TST_CLRBAR_WIDTHENCI_TST_VDCNT_STSEL 0x1c17

H

Field NameENCI_TST_VDCNT_STSELto

Bit(s)
1-0

7
6-1
0

VFIFO2VD_DROP
VFIFO2VD_DELAY
VFIFO2VD_EN

ut

Field Name
VFIFO2VD_VD_SEL

trib

Bit(s)15-8

e

ENCI_VFIFO2VD_CTL 0x1c18

Description
Color bar start position

Description
Color bar widthar

ENCI_TST_CLRBAR_WIDTH 0x1c16

l

ENCI_TST_CR 0x1c14

Description
For interlace, vdata count set when color bar start

R/W
R/W

Default
‘h1b

R/W
R/W
R/W

0
0
0

Description
Vfifo2vd_vd_sel:
00_01_10_11 -> Y_Cb_Y_Cr
Vfifo2vd_drop
Vfifo2vd_delay
Vfifo2vd_en

R/W
R/W

Default
0

Description
Vfifo2vd_pixel_start

R/W
R/W

Default
0

Description
Vdata_yc_use_vfifo_req

R/W0

Vfifo2vd_pixel_end

R/W
R/W

Default
0

Description
enci_vfifo2vd_line_top_start

R/W
R/W

Default
0

Description
enci_vfifo2vd_line_top_end

ENCI_VFIFO2VD_PIXEL_START 0x1c19

Field NameENCI_VFIFO2VD_PIXEL_STARTis

Bit(s)
12-0

ENCI_VFIFO2VD_PIXEL_END 0x1c1a
Field NameVDATA_YC_USE_FIRST_VFIFO_REG
RESERVEDENCI_VFIFO2VD_PIXEL_END

D

Bit(s)
15
14-13
12-0

ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b
Bit(s)
10-0

Field NameENCI_VFIFO2VD_LINE_TOP_STARTENCI_VFIFO2VD_LINE_TOP_END 0x1c1c
Bit(s)
10-0

Field NameENCI_VFIFO2VD_LINE_TOP_END

ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d

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AMLOGIC, Inc. ProprietaryBit(s)
10-0

Revision 1.1.4

Field NameENCI_VFIFO2VD_LINE_BOT_START

R/W
R/W

Default
0

Description
enci_vfifo2vd_line_bot_start

R/W
R/W

Default
0

Description
enci_vfifo2vd_line_bot_end

R/W
R/W
R/W

Default
10

Description
cfg_vfifo2vd_out_scaler_bypass
cfg_vfifo_din_full_range

R/W
R/W

Default
16

Description
DVI/HDMI Hsync out start point

R/W
R/W

Default
32

R/W
R/W

Default
40

dk
er

S905 Datasheet

ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e
Bit(s)
10-0

Field NameENCI_VFIFO2VD_LINE_BOT_END

ENCI_VFIFO2VD_CTL2 0x1c1f
Field Name
CFG_VFIFO2VD_OUT_SCALER_BYPASS
CFG_VFIFO_DIN_FULL_RANGE

ENCP_DVI_HSO_END

0x1c31

Field Name
ENCP_DVI_HSO_END

ENCP_DVI_VSO_BLINE_EVN

0x1c32

Field Name
ENCP_DVI_VSO_BLINE_EVN

ENCP_DVI_VSO_BLINE_ODD
Bit(s)
10-0

0x1c33

Field Name
ENCP_DVI_VSO_BLINE_ODD

ENCP_DVI_VSO_ELINE_EVN

Field Name
ENCP_DVI_VSO_ELINE_EVN

ENCP_DVI_VSO_ELINE_ODD

ENCP_DVI_VSO_BEGIN_EVN

Bit(s)
12-0

D

ENCP_DVI_VSO_BEGIN_ODD

Bit(s)
12-0

Bit(s)
12-0

Default
42

Description
DVI/HDMI Vsync out end line for even field.

R/W
R/W

Default
42

Description
DVI/HDMI Vsync out end line for odd field.

R/W
R/W

Default
16

Description
DVI/HDMI Vsync out start point for even field.

R/W
R/W

Default
16

Description
DVI/HDMI Vsync out start point for odd field.

R/W
R/W

Default
32

Description
DVI/HDMI Vsync out end point for even field.

R/W
R/W

Default
32

Description
DVI/HDMI Vsync out end point for odd field.

0x1c39Field Name
ENCP_DVI_VSO_END_ODD

ENCP_DE_H_BEGIN

R/W
R/W

0x1c38Field Name
ENCP_DVI_VSO_END_EVN

ENCP_DVI_VSO_END_ODD

Description
DVI/HDMI Vsync out start line for odd field.

0x1c37

Field Name
ENCP_DVI_VSO_BEGIN_ODD

ENCP_DVI_VSO_END_EVN

Default
40

0x1c36

Field Name
ENCP_DVI_VSO_BEGIN_EVN

isBit(s)
12-0

Description
DVI/HDMI Vsync out start line for even field.

0x1c35

Field Name
ENCP_DVI_VSO_ELINE_ODD

trib

Bit(s)
10-0

R/W
R/W

ut

Bit(s)
10-0

0x1c34

Description
DVI/HDMI Hsync out end pointarBit(s)
10-0

H

Bit(s)
12-0lField Name
ENCP_DVI_HSO_BEGIN

to

Bit(s)
12-0

0x1c30ne

ENCP_DVI_HSO_BEGINe

Bit(s)
1
0

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S905 Datasheet

Field Name
ENCP_DE_H_BEGIN

ENCP_DE_V_BEGIN_EVEN

R/W
R/W

Default
519

Description
DVI/HDMI vertical active video end line for even field.

R/W
R/W

Default
42

Description
DVI/HDMI vertical active video start line for odd field.

R/W
R/W

Default
519

R/W
R/W
R/W

Default
0
0

H

to

tr
ib

is

D

l

Description
Sync_pulse_length
Sync_pulse_start_line

R/W
R/W
R/W
R/W
R/W

Default00
00Description
Sync_pulse_enable

R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0

Description
Enci_sync_enable
Encp_sync_enable
Enct_sync_enable
Encl_sync_enable
Fussy_sync_enable
Sync_pulse_target_line

R/W
R/W

Default
0

Description
Sync_pulse_target_pixel

R/W
R/W
R/W

Default
00

Description
Sync_pulse_length
Sync_pulse_start_line

Short_fussy_sync
Sync_pulse_start_pixel

0x1c44

Field NameSYNC_PULSE_LENGTHSYNC_PULSE_START_LINE

ENCP_SYNC_PIXEL_EN

Description
DVI/HDMI vertical active video end line for odd field.

0x1c43

Field NameSYNC_PULSE_TARGET_PIXELENCP_SYNC_LINE_LENGTH
Bit(s)
15-11
10-0

0x1c42

Field NameENCI_SYNC_ENALBE
ENCP_SYNC_ENALBE
ENCT_SYNC_ENALBE
ENCL_SYNC_ENALBE
FUSSY_SYNC_ENABLE
SYNC_PULSE_TARGET_LINE

ENCI_SYNC_TO_PIXEL
Bit(s)
12-0

0x1c41

Field NameSYNC_PULSE_EN
RESERVEDSHORT_FUSSY_SYNC
SYNC_PULSE_START_PIXELENCI_SYNC_TO_LINE_EN
Bit(s)
15
14
13
12
11
10-0

Description
DVI/HDMI vertical active video start line for even field.

0x1c40Field NameSYNC_PULSE_LENGTHSYNC_PULSE_START_LINE

ENCI_SYNC_PIXEL_EN
Bit(s)
15
14
13
12-0

Default
42

0x1c3fField Name
ENCP_DE_V_END_ODD

ENCI_SYNC_LINE_LENGTH
Bit(s)
15-11
10-0

R/W
R/W

0x1c3eField Name
ENCP_DE_V_BEGIN_ODD

ENCP_DE_V_END_ODD
Bit(s)
10-0

Description
DVI/HDMI horizontal active video end point.

0x1c3dField Name
ENCP_DE_V_END_EVEN

ENCP_DE_V_BEGIN_ODD
Bit(s)
10-0

Default
1657

ne

ENCP_DE_V_END_EVEN
Bit(s)
10-0

R/W
R/W

0x1c3cField Name
ENCP_DE_V_BEGIN_EVENeBit(s)
10-0

Description
DVI/HDMI horizontal active video start point.

0x1c3bField Name
ENCP_DE_H_END

ut

Bit(s)
12-0

Default
217

dk
er

ENCP_DE_H_END

R/W
R/W

ar

Bit(s)
12-0

Revision 1.1.4

0x1c45173/336

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S905 Datasheet

Bit(s)
15
14
13
12-0

Revision 1.1.4

Field NameSYNC_PULSE_EN
RESERVEDSHORT_FUSSY_SYNC
SYNC_PULSE_START_PIXELENCP_SYNC_TO_LINE_EN

Default00
00Description
Sync_pulse_enable

R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0

Description
Enci_sync_enable
Encp_sync_enable
Enct_sync_enable
Encl_sync_enable
Fussy_sync_enable
Sync_pulse_target_line

R/W
R/W

Default
0

Description
Sync_pulse_target_pixel

R/W
R/W
R/W

Default
0
0

R/W
R/W
R/W
R/W
R/W

Default00
00Description
Sync_pulse_enable

R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0

Description
Enci_sync_enable
Encp_sync_enable
Enct_sync_enable
Encl_sync_enable
Fussy_sync_enable
Sync_pulse_target_line

R/W
R/W

Default
0

Description
Sync_pulse_target_pixel

Description
0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4]
1=Do not scale LCD input data
0=Scale enc480p_vadj input data to y [16*4,235*4], c[16*4,240*4]
1=Do not scale data to enc480p_vadj
0=Scale vfifo2vd's output vdata to y[16,235], c[16,240]
1=Do not scale vfifo2vd's output vdata
0=Data from viu fifo is y[16*4,235*4], c[16*4,240*4]
1=Data from viu fifo is full range [0,1023]

Short_fussy_sync
Sync_pulse_start_pixel

0x1c46

Field NameENCI_SYNC_ENALBE
ENCP_SYNC_ENALBE
ENCT_SYNC_ENALBE
ENCL_SYNC_ENALBE
FUSSY_SYNC_ENABLE
SYNC_PULSE_TARGET_LINE

ENCL_SYNC_LINE_LENGTH

ENCL_SYNC_PIXEL_EN

0x1c4dENCL_SYNC_TO_LINE_EN

0x1c4eField NameENCI_SYNC_ENALBE
ENCP_SYNC_ENALBE
ENCT_SYNC_ENALBE
ENCL_SYNC_ENALBE
FUSSY_SYNC_ENABLE
SYNC_PULSE_TARGET_LINEtrib

Bit(s)
15
14
13
12
11
10-0

D

Field NameSYNC_PULSE_TARGET_PIXELENCP_VFIFO2VD_CTL2

Description
Sync_pulse_length
Sync_pulse_start_line

Short_fussy_sync
Sync_pulse_start_pixel

0x1c4fis

ENCL_SYNC_TO_PIXEL
Bit(s)
12-0

H

Field NameSYNC_PULSE_EN
RESERVEDSHORT_FUSSY_SYNC
SYNC_PULSE_START_PIXEL

to

Bit(s)
15
14
13
12-0

0x1c4cField NameSYNC_PULSE_LENGTHSYNC_PULSE_START_LINEeBit(s)
15-11
10-0

dk
er

Field NameSYNC_PULSE_TARGET_PIXEL

ut

Bit(s)
12-0

0x1c47ar

ENCP_SYNC_TO_PIXELnel

Bit(s)
15
14
13
12
11
10-0

R/W
R/W
R/W
R/W
R/W

0x1c50Bit(s)
3

Field Name
VFIFO2VD_ENCP_LCD_SCALER_BYPASS

R/W
R/W

Default
1

2

VFIFO2VD_ENCP_VADJ_SCALER_BYPASS

R/W

1

1

VFIFO2VD_OUT_SCALER_BYPASS

R/W

1

0

VFIFO_DIN_FULL_RANGE

R/W

0VENC_DVI_SETTING_MORE

0x1c51

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S905 Datasheet

Bit(s)
0

Revision 1.1.4

Field NameVENC_DVI_SEL_RGB

VENC_VDAC_DAC0_FILT_CTRL0
Bit(s)
0

Default
0

Description
Applicable for using on-chip hdmi tx module only. This bit
controls correct Bit(s)-mapping from Venc to hdmi_tx
depending on whether YCbCr or RGB mode.
0=Map data bitfrom Venc to hdmi_tx for YCbCr mode;
1=Map data bitfrom Venc to hdmi_tx for RGB mode.

R/W
R/W

Default
0

Description
0=Bypass filter;
1=Enable filter.

0x1c58Field NameVENC_VDAC_DAC0_FILT_EN

VENC_VDAC_DAC0_FILT_CTRL1

R/W
R/W

0x1c59

VENC_VDAC_DAC1_FILT_CTRL0
Bit(s)0

R/W
R/W

Default
00x1c5b

Notes: dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6

VENC_VDAC_DAC2_FILT_CTRL00x1c5cField NameVENC_VDAC_DAC2_FILT_EN

Default
8’h00
8’h40

R/W
R/W

Default
0

VENC_VDAC_DAC2_FILT_CTRL1

Description
0=Bypass filter;
1=Enable filter.

Description
Filter coef1
Filter coef0

Description
0=Bypass filter;
1=Enable filter.

uteBit(s)
0

R/W
R/W
R/W

H

Field NameVENC_VDAC_DAC1_FILT_COEF1
VENC_VDAC_DAC1_FILT_COEF0

to

Bit(s)
15-8
7-0

Description
Filter coef1
Filter coef0

neDefault
8’h00
8’h40

0x1c5aField NameVENC_VDAC_DAC1_FILT_EN

VENC_VDAC_DAC1_FILT_CTRL1

R/W
R/W
R/W

dk
er

Field NameVENC_VDAC_DAC0_FILT_COEF1
VENC_VDAC_DAC0_FILT_COEF0

ar

Bit(s)
15-8
7-0lNotes: dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6

0x1c5dBit(s)
15-8
7-0

tr
ib

Notes: dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
Field NameVENC_VDAC_DAC2_FILT_COEF1
VENC_VDAC_DAC2_FILT_COEF0

VENC_VDAC_DAC3_FILT_CTRL1

Default
8’h00
8’h40

Description
Filter coef1
Filter coef0

R/W
R/W

Default
0

Description
0=Bypass filter;
1=Enable filter.

0x1c5eField NameVENC_VDAC_DAC3_FILT_EN

D

Bit(s)0is

VENC_VDAC_DAC3_FILT_CTRL0

R/W
R/W
R/W

0x1c5fNotes: dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
Bit(s)
15-8
7-0

Field NameVENC_VDAC_DAC3_FILT_COEF1
VENC_VDAC_DAC3_FILT_COEF0

R/W
R/W
R/W

Default
8’h00
8’h40

Description
Filter coef1
Filter coef0

R/W
R/W

Default‘h1b

Description
Vfifo2vd_vd_sel:
00_01_10_11 -> Y_Cb_Y_Cr

ENCL_VFIFO2VD_CTL 0x1c90
Bit(s)
15-8

Field Name
VFIFO2VD_VD_SEL

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AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
7
6-1
0

Revision 1.1.4

Field Name
VFIFO2VD_DROP
VFIFO2VD_DELAY
VFIFO2VD_EN

R/W
R/W
R/W
R/W

Default000Description
Vfifo2vd_drop
Vfifo2vd_delay
Vfifo2vd_en

R/W
R/W

Default
0

Description
Vfifo2vd_pixel_start

R/W
R/W

Default
0

Description
Vdata_yc_use_vfifo_req

R/W0

Vfifo2vd_pixel_end

R/W
R/W

Default
0

Description
ENCL_vfifo2vd_line_top_start

R/W
R/W

Default
0

R/W
R/W

Default
0

ENCL_VFIFO2VD_PIXEL_START 0x1c91
Bit(s)
12-0

Field Name
ENCL_VFIFO2VD_PIXEL_START

Field NameVDATA_YC_USE_FIRST_VFIFO_REG
RESERVEDENCL_VFIFO2VD_PIXEL_END

ne

Bit(s)
15
14-13
12-0

Field Name
ENCL_VFIFO2VD_LINE_TOP_START

Bit(s)
10-0

Field Name
ENCL_VFIFO2VD_LINE_TOP_END

ENCL_VFIFO2VD_LINE_BOT_START 0x1c95
Field Name
ENCL_VFIFO2VD_LINE_BOT_STARTH

Bit(s)
10-0

Bit(s)
10-0

Field Name
ENCL_VFIFO2VD_LINE_BOT_END

Field Name
CFG_ENCL_LCD_SCALER_BYPASSCFG_ENCL_VADJ_SCALER_BYPASS
CFG_VFIFO2VD_OUT_SCALER_BYPASS
CFG_VFIFO_DIN_FULL_RANGE

ENCL_TST_EN 0x1c98

Field Name
ENCL_TST_EN

ENCL_TST_Y
Bit(s)
9-0

Description
ENCL_vfifo2vd_line_bot_start

R/W
R/W

Default
0

Description
ENCL_vfifo2vd_line_bot_end

R/W
R/W
R/W
R/W
R/W

Default11
10

Description
cfg_encl_lcd_scaler_bypass
cfg_encl_vadj_scaler_bypass
cfg_vfifo2vd_out_scaler_bypass
cfg_vfifo_din_full_range

R/W
R/W

Default
0

Description
ENCL_tst_en

R/W
R/W

Default
1

Description
Video test mode selectl:
0: ENCL_tst_mode_fixval
1: ENCL_tst_mode_colorbar
2: ENCL_tst_mode_thinline
3: ENCL_tst_mode_dotgrid

R/W
R/W

Default
512

Description
Default value of Y in test mode

0x1c99D

ENCL_TST_MDSEL

is

Bit(s)
0

tr
ib

ut

Bit(s)
32
1
0e

ENCL_VFIFO2VD_CTL2 0x1c97

Bit(s)
1-0

to

ENCL_VFIFO2VD_LINE_BOT_END 0x1c96

Description
ENCL_vfifo2vd_line_top_end

ar

ENCL_VFIFO2VD_LINE_TOP_END 0x1c94

dker

ENCL_VFIFO2VD_LINE_TOP_START 0x1c93
Bit(s)10-0l

ENCL_VFIFO2VD_PIXEL_END 0x1c92

Field Name
ENCL_TST_MDSEL

0x1c9aField Name
ENCL_TST_Y

ENCL_TST_CB 0x1c9b

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Bit(s)
9-0

Revision 1.1.4

Field Name
ENCL_TST_CB

R/W
R/W

Default
512

Description
Default value of Pb in test mode

R/W
R/W

Default
512

Description
Default value of Pr in test mode

R/W
R/W

Default
275

Description
Color bar start position

R/W
R/W

Default
360

Description
Color bar width

R/W
R/W

Default
0

Description
For interlace, vdata count set when color bar start

R/W
R/W

Default
0

R/W
R/W

Default
8'd81

ENCL_TST_CR 0x1c9c
Bit(s)
9-0

Field Name
ENCL_TST_CR

ENCL_TST_CLRBAR_STRT 0x1c9d
Bit(s)
10-0

Field Name
ENCL_TST_CLRBAR_STRT

Field Name
ENCL_TST_CLRBAR_WIDTHne

Bit(s)
10-0

Field Name
ENCL_TST_VDCNT_STSEL

0x1ca0Field Name
ENCL_VIDEO_EN

ENCL_VIDEO_Y_SCL

0x1ca1

ENCL_VIDEO_PR_SCL
Bit(s)
7 -0

isD

Description
Y scaleR/W
R/W

Default
8'd79

Description
Cb scale

R/W
R/W

Default
8'd79

Description
Cr scale

R/W
R/W

Default
10'h3c0

Description
Y offset

R/W
R/W

Default
10'h0

Description
Pb offset

R/W
R/W

Default
10'h0

Description
Pr offset

0x1ca6

Field Name
ENCL_VIDEO_PR_OFFST

ENCL_VIDEO_MODE

Description
Progressive encoder enable

0x1ca5

Field Name
ENCL_VIDEO_PB_OFFST

ENCL_VIDEO_PR_OFFST
Bit(s)
9 -0

0x1ca4

Field Name
ENCL_VIDEO_Y_OFFST

ENCL_VIDEO_PB_OFFST
Bit(s)
9 -0

0x1ca3

Field Name
ENCL_VIDEO_PR_SCL

ENCL_VIDEO_Y_OFFST
Bit(s)
9 -0

0x1ca2

Field Name
ENCL_VIDEO_PB_SCLeBit(s)
7 -0

to

ENCL_VIDEO_PB_SCL

H

Field Name
ENCL_VIDEO_Y_SCL

ut

Bit(s)
7 -0

trib

Bit(s)
0ar

ENCL_VIDEO_EN

dk
er

ENCL_TST_VDCNT_STSEL 0x1c9f
Bit(s)
1-0l

ENCL_TST_CLRBAR_WIDTH 0x1c9e

0x1ca7Bit(s)

Field Name

R/W

15
14

ENCL_PX_LN_CNT_SHADOW_EN
ENCL_VIDEO_MODE_DE_V

R/W
R/W

13

ENCL_VIDEO_MODE_EN_VSO_OFLD_FIX_EN

R/W

Df Description
lt
0 pixel count and line count shadow enable
0 1=DE signal’s polarity is active high.
0=DE signal’s polarity is active low.
0 1=Extend ENCL_VIDEO_MAX_PXCNT by 1 pixel.
0=Treat ENCL_VIDEO_MAX_PXCNT as is.

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Field Name

R/W

Df Description
lt
12
ENCL_VIDEO_MODE_EN_FIELD_ODD
R/W 0 Enable odd field ( for 1080i)
11
ENCL_VIDEO_MODE_EN_VSO_OFLD
R/W 0 Enable VSO odd field
10
ENCL_VIDEO _MODE_EN_VAVON_OFLD
R/W 0 Enable Vertical Active On for odd field
9
ENCL_VIDEO _MODE_EN_EQU_OFLD
R/W 0 Enable Equalization pulse for odd field
8
ENCL_VIDEO _MODE_EN_EQU
R/W 0 Enable Equalization pulse
6
ENCL_VIDEO _MODE_EN_HSEQ_SWITCH
R/W 0 Enable Hsync and equalization pulse switch in center
5
ENCL_VIDEO _MODE_EN_VP_OFLD
R/W 0 Enable Vertical Pulse for odd field
4
ENCL_VIDEO _MODE_EN_VP2
R/W 0 Enable 2nd vertical pulse in a line (1080i)
3
ENCL_VIDEO _MODE_EN_VPE_HALF_OFLD
R/W 0 Vertical pulse on end line of odd field is half
2
ENCL_VIDEO _MODE_EN_VPB_HALF_OFLD
R/W 0 Vertical pulse on begin line of odd field is half
1
ENCL_VIDEO _MODE_EN_VPE_HALF
R/W 0 Vertical pulse on end line of even field is half0
ENCL_VIDEO _MODE_EN_VPB_HALF
R/W 0 Vertical pulse on begin line of even field is half
Note: This register should be set as 0x140 for 720p , and 0x1ffc for 1080i, and 0x0 for 480p/576p

0x1ca8Field Name
ENCL_SP_TIMING_CTRLRESERVEDENCL_SEL_GAMMA_RGB_IN

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

to

H

ENCL_VIDEO_MODE_ADV_EN_HUE_MATRIXENCL_VIDEO_MODE_ADV_SWAP_PBPR
ENCL_VIDEO_MODE_ADV_EN_HS_PBPR
ENCL_VIDEO_MODE_ADV_GAIN_HDTV
ENCL_VIDEO_MODE_ADV_VFIFO_EN
ENCL_VIDEO_MODE_ADV_VFIFO_UPMODE

Default
0
0
0
0
0
0
0
0
0
1

ENCL_DBG_LN_RST

Field Name
ENCL_DBG_PX_INT_EN
ENCL_DBG_PX_INT_VAL

ENCL_DBG_LN_INT
Bit(s)
15
10 -0

Description
Debug mode pixel reset enable
Debug mode pixel reset value

R/W
R/W
R/W

Default
00

Description
Debug mode line reset enable
Debug mode line reset value

R/W
R/W
R/W

Default
00

Description
Pixel Interrupt enable
Pixel value that trig the interrupt

R/W
R/W
R/W

Default
00

Description
Line Interrupt enable
Line value that trig the interrupt

R/W
R/W
R/W

Default
00

Description
Y delay[2]Cb delay[2]0x1cacField Name
ENCL_DBG_LN_INT_EN
ENCL_DBG_LN_INT_VAL

ENCL_VIDEO_YC_DLY
Bit(s)
10
8

Default
000x1cabD

Bit(s)
15
12 -0

R/W
R/W
R/W

0x1caaField Name
ENCL_DBG_LN_RST_EN
ENCL_DBG_LN_RST_VAL

ENCL_DBG_PX_INT

UnusedEnable HUE matrix
Swap PB PR
Enable sync pulse on PB PRYPBPR gain as HDTV type
Data input from VFIFO
Sampling rate:
0: 1
1: ½
2: ¼
3: 1/8is

Bit(s)
15
10 -0e

Field Name
ENCL_DBG_PX_RST_EN
ENCL_DBG_PX_RST_VAL

trib

Bit(s)
15
12 -00x1ca9ut

ENCL_DBG_PX_RSTDescriptiondkerBit(s)
15-14
13-11
10
9-8
7
6
5
4
3
2 :0

ar

ENCL_VIDEO_MODE_ADV

nelBit(s)

Revision 1.1.4

Field Name
ENCL_VIDEO_Y_DLY
ENCL_VIDEO_CB_DLY

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AMLOGIC, Inc. ProprietaryField Name
ENCL_VIDEO_CR_DLY
ENCL_VIDEO_Y_DLY
ENCL_VIDEO_CB_DLY
ENCL_VIDEO_CR_DLY

ENCL_VIDEO_MAX_PXCNT

ENCL_VIDEO_HAVON_END

Bit(s)
12 -0

0x1cb6

Field Name
ENCL_VIDEO_HSO_END

trib

Field Name
ENCL_VIDEO_VSO_BEGIN

is

0x1cb9ENCL_VIDEO_VSO_ELINE

0x1cbaBit(s)
10 -0

Bit(s)
10 -0

Field Name
ENCL_VIDEO_VSO_BLINE

Field Name
ENCL_VIDEO_VSO_ELINEENCL_VIDEO_MAX_LNCNT
Bit(s)
10 -0

Description
Vertical active video start point

R/W
R/W

Default
11'd519

R/W
R/W

Default
11'd42ar

Description
Vertical active video on end line

Description
Vertical active video on start line

R/W
R/W

Default
16

Description
Digital Hsync out start point

R/W
R/W

Default
32

Description
Digital Hsync out end point

R/W
R/W

Default
16

Description
Digital Vsync out start point

R/W
R/W

Default
32

Description
Digital Vsync out end point

R/W
R/W

Default
37

Description
Digital Vsync out start line

R/W
R/W

Default
39

Description
Digital Vsync out end line

R/W
R/W

Default
10'd524

Description
Max line counter

0x1cbbField Name
ENCL_VIDEO_MAX_LNCNT

ENCL_VIDEO_BLANKY_VAL

Default
13'd2170x1cb8Field Name
ENCL_VIDEO_VSO_END

ENCL_VIDEO_VSO_BLINE

R/W
R/W

0x1cb7D

Bit(s)
12 -0

Description
Vertical active video end point

H

0x1cb5

Field Name
ENCL_VIDEO_HSO_BEGIN

ENCL_VIDEO_VSO_END

Default
13'd1656

0x1cb4

Field Name
ENCL_VIDEO_VAVON_BLINEENCL_VIDEO_VSO_BEGIN
Bit(s)
12 -0

R/W
R/W

0x1cb3

Field Name
ENCL_VIDEO_VAVON_ELINEENCL_VIDEO_HSO_END

Description
Max pixel counterne

Field Name
ENCL_VIDEO_HAVON_BEGIN

ENCL_VIDEO_HSO_BEGIN
Bit(s)
12 -0

Default
13'd1715

0x1cb2

ENCL_VIDEO_VAVON_BLINE
Bit(s)
10 -0

R/W
R/W

l

Field Name
ENCL_VIDEO_HAVON_END

ENCL_VIDEO_VAVON_ELINE
Bit(s)
10 -0

Description
Cr delay[2]Y delay[1:0]
Cb delay[1:0]
Cr delay[1:0]0x1cb1

ENCL_VIDEO_HAVON_BEGIN
Bit(s)
12 -0

Default
0
0
0
0

to

Bit(s)
12 -0

R/W
R/W
R/W
R/W
R/W

0x1cb0Field Name
ENCL_VIDEO_MAX_PXCNTeBit(s)
12 -0

ut

Bit(s)
6
5 –4
3 –2
1 –0

Revision 1.1.4

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Field Name
ENCL_VIDEO_BLANKY_VAL

ENCL_VIDEO_BLANKPB_VAL

Bit(s)
12-8
6
5
4
3
2
1
0

R/W
R/W

Default2

Description
Horizontal offset after HSI

R/W
R/W

Default
0

Description
Vertical offset after VSI

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
4
0
0
0
0
0
1
0

R/W
R/W
R/W
R/W
R/W

Default
01
1
1

Description
Odd field VSO offset begin, 4 Bits signed.
Odd field VSO offset end, 4 Bits signed.
Odd field VAVON offset begin, 4 Bits signed.
Odd field VAVON offset end, 4 Bits signed.

R/W
R/W
R/W

Default
00

Description
CbCr matrix parameter Ma (signed value)
CbCr matrix parameter Mb (signed value)

e

ut

tr
ib

l

ne

Description

0x1cc5

Field Name
ENCL_VIDEO_MATRIX_MA
ENCL_VIDEO_MATRIX_MB

is

Bit(s)
15:8
7:0

0x1cc4

Field Name
ENCL_VIDEO_OFLD_VSO_OFST_BEGIN
ENCL_VIDEO_OFLD_VSO_OFST_END
ENCL_VIDEO_OFLD_VAVON_OFST_BEGIN
ENCL_VIDEO_OFLD_VAVON_OFST_END

ENCL_VIDEO_MATRIX_CB

Description
Blank Pr value

0x1cc1

Field Name
CFG_BLANK_DLY
CFG_MACV_R_EN
CFG_MACV_G_EN
CFG_MACV_B_EN
CFG_RGB_SEPERATE_BLANK
CFG_SYNC_ON_R
CFG_SYNC_ON_G
CFG_SYNC_ON_B

ENCL_VIDEO_OFLD_VOAV_OFST
Bit(s)
15:12
11:8
7:4
3:0

Default
10'd5120x1cc0Field Name
ENCL_VIDEO_VOFFST

ENCL_VIDEO_RGB_CTRL

R/W
R/W

dk
er

Bit(s)
10 -0

Description
Blank Pb value

0x1cbfField Name
ENCL_VIDEO_HOFFST

ENCL_VIDEO_VOFFST

Default
10'd512ar

Bit(s)
13 -0

R/W
R/W

0x1cbeField Name
ENCL_VIDEO_BLANKPR_VAL

ENCL_VIDEO_HOFFST

Description
Blank Y value

0x1cbdField Name
ENCL_VIDEO_BLANKPB_VAL

ENCL_VIDEO_BLANKPR_VAL
Bit(s)
9 -0

Default
10'd240H

Bit(s)
9 -0

R/W
R/W

to

Bit(s)
9 -0

Revision 1.1.4

D

Note: These 2 register is for HUE adjustment. The formula is : Cb’ = Cb*Ma + Cr*Mb, Cr’ = Cb*Mc + Cr*Md(effective only when Enable HUE matrix by bit ENCL_VIDEO_MODE_ADV[7])Note : see the descritption of register ENCI_CMPN_MATRIX_CB.
ENCL_VIDEO_MATRIX_CR
Bit(s)
15:8
7:0

Field Name
ENCL_VIDEO_MATRIX_MC
ENCL_VIDEO_MATRIX_MD

ENCL_VIDEO_RGBIN_CTRL
Bit(s)
1
00x1cc6
R/W
R/W
R/W

Default
00

Description
CbCr matrix parameter Mc (signed value)
CbCr matrix parameter Md (signed value)

R/W
R/W
R/W

Default
00

Description
USE RGB data from VIU
VIU RGB IN BLANK ZERO

0x1cc7

Field Name
CFG_VIDEO_RGBIN_ZBLK

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ENCL_MAX_LINE_SWITH_POINT

0x1cc8Field Name
CFG_VID_LOCK_ADJ_EN
CFG_MAX_LINE_SWITH_POINT

Bit(s)
15-12
11-8
7-4
3-0

Description

R/W
R/W
R/W
R/W
R/W

Default03
2
1

Description
dac3
dac2
dac1
dac0

R/W
R/W
R/W

Default
5
4

Description
dac5
dac4

0x1cc9Field NameVENC_L_DACSEL_0
VENC_L_DACSEL_0
VENC_L_DACSEL_0
VENC_L_DACSEL_0

ENCL_DACSEL1

Default0‘h1fff0x1ccaField NameVENC_L_DACSEL_1

3-0

VENC_L_DACSEL_1

D

is

tr
ib

ut

e

to

H

ar

dk
er

Bit(s)
7-4

l

ENCL_DACSEL0

R/W
R/W
R/W

ne

Bit(s)
13
12-0

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Revision 1.1.4

Section V Audio Path
Audio Path includes 2 parts: audio_in submodule and audio_out submodule, as illustrated in FigV.1. Audio_in part supports 4
formats of audio input, after decoding, these signal will be written to DDR via to_ddr module. Audio_out read signals from DDR
and encode the signal to 4 formats of audio output.
Fig V.1 Diagram of Audio Pathaudio_path
audio_out

spidf(decode)

spidf(encode)i2s(decode)i2s(encode)

dk
er

ddr

to_ddrnelaudio_in

pcm(decode)

pcm(encode)

hdmi(tx)

H

ar

pdm

to

30. Audio_Input
30.1 OvervieweAudio_input supports 4 decoding formats: spidf, I2S, PCM and PDM, each of which has different decoding algorithm.

ut

30.2 SPIDF

D

is

tr
ib

Spdif used biphase mark code(BMC) encode, it’s double frequency of original data, and between two original data, there musthave a invert operation.
At working status, the spdif module decodes the 1bit input it receives to 32 bit output.
The decoding procedure consists of the following 5 steps:
Resampling: lock input using a clock’s(from control) posedge or negedge.
Sreg: shift store 32 input.
Find preamble: find 3 preamble and tell control.
Control: configured by register and find preamble, auto select clock.
Format: transfer 32Bit(s) data to a new format.

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30.3 I2S(decode)
I2S(decode) supports 4 streams(8ch) input and 1 time division multiplexing output. Register I2S_ctrl[13:10] can be used tocontrol it.
I2S will sent 24 Bits data in default, we can use I2S_ctrl[9:8] to mask some Bits,

30.4 PCM(decode)

ar

dk
er

ne

l

The hardware will detect data_valid and frame_sync first.
Next hardware will counter data_valid, if counter reached slot_msb_Bits(pcmin_ctrl1[26:21]), that means finished receive slot0,
then counter clear and start receive slot1/2/…
Each slot has 1 enable bit (pcmin_ctrl1[15:0]):
if [0] is 0, slot0 will not be sent out.
if [0] is 1, slot1 will be sent out.
if [1:0] is 2’b11, slot0 and slot1 will be sent out.
if [3:0] is 4’b1001, slot0 and slot3 will be sent out, but slot1 and slot2 will not.
Hardware has another counter to accumulate slot num. When one frame is finished(fs invert), hardware will compare it withtheoretically (accumulate by pcmin_ctrl1[15:0]), if it’s not the same, there will send a pcm_err to register(AUDIN_FIFO_INT[8]).

H

The format modification include: left_justified/msb_first/data_msb_bit ( output data bit_width):30.5 PDM

toWith PDM module, we can receive the pdm data and transfer it to sample data.

e30.6 To_ddr

Fig V.30.5 Diagram of to_ddr

D

is

tr
ib

ut

To_ddr_unit selects source audio data and modifies it, then write the modified data to the ddr memory.
The modification consists of 2 parts: audio sample format modification and the ddr address obtaining.
S905 can send 3 channels of audio data to ddr at the same time.

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to

H

ar

dk
er

ne

l

S905 Datasheet

Fig V.30.6 Data Path of to_ddr

D

is

tr
ib

ut

e

The to_ddr_unit functions in the following step:
Step1: select source audio.
Step2: select byte number of audio sample.
Step3: select the mode of write adderss.
Step4: store audio sample to 64x64 fifo first, then read to ddr.
Step5: select endian mode before data to ddr.

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30.7 Register Description

to

H

ar

dk
er

ne

l

S905 Datasheet

Bit(s)

R/W

31

RW

30

RW

tr
ib

AUDIN_SPDIF_MODE 0x00

ute

Audio In registers:
The final address of the following registers should be calculated with the following eqution:
Final Address = 0xC110A000 + offset*4

Default

Description

0x0

SPDIF_EN

0x0

SPDIF_INT_EN

0x0

SPDIF_BURST_PRE_INT_EN

RW

28:25

RW

0x0

Reservered

RW

0x0

SPDIF_TIE_0

RW

0x0

SPDIF_SAMPLE_SEL

RW

0x0

SPDIF_REVERSE_EN

RW

0x1

SPDIFIN_SEL

20

RW

0x0

SPDIF_BIT_ORDER

19

RW

0x0

SPDIF_CHNL_ORDER

18

RW

0x0

SPDIF_DATA_TYPE_SEL

17

RW

0x0

Reservered

16:14

RW

0x0

SPDIF_XTDCLK_UPD_ITVL

13:0

RW

0x2501SPDIF_CLKNUM_54U

23
22
21

D

24

is

29

AUDIN_SPDIF_FS_CLK_RLTN 0x01

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R/W

Default

29：24

RW

0x7

SPDIF_CLKNUM_192K

23:18

RW

0xe

SPDIF_CLKNUM_96K

17:12

RW

0x1d

SPDIF_CLKNUM_48K

10：6

RW

0x1f

SPDIF_CLKNUM_44K

5：0

RW

0x2b

SPDIF_CLKNUM_32K

AUDIN_SPDIF_CHNL_STS_A

Description

0x02

Bit(s)

R/W

Default

31:0

R

0x0

The channel A status information

Bit(s)

R/W

Default

31:0

R

0x0

l

0x03
Description
The channel B status information

AUDIN_SPDIF_MISC 0x04
Bit(s)

R/W

Default

Description

31:9

R

0x0

reserved

8

R

0x0

Burst

7

R

0x0

Valid_in

R

0x0

3

R

0x0

reserved

2

R

0x0

1

R

0x0

0

R

0x0

R/W

31:16

R

15:0

R

Default

R/We

userdata

Description

0x0

The burst sub pc

0x0

The burst sub pd

is

AUDIN_I2SIN_CTRL 0x10
Bit(s)

ValiditytribBit(s)

0x05

Parity error

ut

AUDIN_SPDIF_NPCM_PCPD

to

H

ar

6:4

Xtdclk_sel:
0: 32K
1:44K
2:46K
3:48K
4:96K
5:192Kne

AUDIN_SPDIF_CHNL_STS_B

DescriptiondkerBit(s)

Revision 1.1.4

Default

Description

0x0

I2SIN_EN

RW

0x0

I2SIN_CHAN_EN

RW

0x0

I2SIN_SIZE

RW

0x0

I2SIN_LRCLK_INVT

6:4

RW

0x0

I2SIN_LRCLK_SKEW

3

RW

0x0

I2SIN_POS_SYNC

2

RW

0x0

I2SIN_LRCLK_SEL

1

RW

I2SIN_CLK_SEL I2S clk selection : 0 : from pad input. 1 : from AIU.

0

RW

0x0
0x0

13:10
9:8

RW

D

15

7

AUDIN_SOURCE_SEL

I2SIN_DIR

0x11

Bit(s)

R/W

Default

Description

31:15

RW

0x0

Reserved

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Revision 1.1.4

Bit(s)

R/W

Default

14:12

RW

0x0

Description
Hdmirx_chsts_sel

11:8

RW

0x0

Hdmirx_chsts_en

7:6

RW

0x0

Reserved

5:4

RW

0x0

Spdif_src_sel

3:2

RW

0x0

Reserved

1:0

RW

0x0

I2sin_src_sel

AUDIN_DECODE_FORMAT 0x12
R/W

Default

Description

31:25

RW

0x0

Reserved

24

RW

0x0

SPIDF enabled

23:22

RW

0x0

Reserved

21:20

RW

0x0

I2S_block_start_src:

19:17

RW

0x0

Reserved

16

RW

0x0

I2S enabled

RW

audio_channel_alloc

RW

6

RW

0x0

I2S_channel_config

5:4

RW

0x0

I2S_format_select

3:2

RW

0x0

I2S_bit_width

1

RW

0x0

ws polarity

0

RW

0x0

For SPDIF modearhdmi_tx_audio_decoder input sel

AUDIN_DECODE_CONTROL_STATUS
R/W

31:25

R

Default

Description

0x0

Reserved

0x0

23:16

RW

15：8

RW

7：4

RW

3

RW

channel_status stablility indicator

0x0
0x0

Valid Bits for audio sample packet. [7] for valid_sp3_right, [6] for valid_sp3_left, ..., [1]for valid_sp0_right, [0] for valid_sp0_left.
User Bits for audio sample packet. [7] for user_sp3_right, [6] for user_sp3_left, ..., [1] foruser_sp0_right, [0] for user_sp0_left
cntl_init_discard. Number of initial hdmi_tx_audio_decoder samples to discard fromreset.

tr
ib

0x0

e

R

ut

24

0x13

to

Bit(s)

H

15:8

dk
er

7

0x0
0x0

ne

l

Bit(s)

0x0

cntl_invert_I2S_lrclk Invert WS before input to hdmi_tx_audio_decoder

0x0

RW

1

RW

0x0

audio_user_overwrite. User bit selection in audio packet. 0=use input data; 1=use

RW

0x0

audio_sample_valid,sample non-flat indication. 0=flat, non-valid; 1=non-flat, validD0

audio_valid_overwrite. Valid bit selection in audio packet. 0=use input data; 1=use

is

2

AUDIN_DECODE_CHANNEL_STATUS_A_0
Bit(s)

R/W

Default

31:0

R

0x0

AUDIN_DECODE_CHANNEL_STATUS_A_1
Bit(s)

R/W

Default

31:0

R

0x0

AUDIN_DECODE_CHANNEL_STATUS_A_2
Bit(s)

R/W

Default

31:0

R

0x0

0x14
Description
Channel status information from HDMIRX, [31:0]

0x15
Description
Channel status information from HDMIRX, [63:32]

0x16
Description
Channel status information from HDMIRX, [95:64]

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S905 Datasheet

Revision 1.1.4

AUDIN_DECODE_CHANNEL_STATUS_A_3
Bit(s)

R/W

Default

31:0

R

0x0

0x17
Description
Channel status information from HDMIRX, [127:96]

AUDIN_DECODE_CHANNEL_STATUS_A_4
Bit(s)

R/W

Default

31:0

R

0x0

0x18
Description
Channel status information from HDMIRX, [159:128]

AUDIN_DECODE_CHANNEL_STATUS_A_5
R/W

Default

31:0

R

0x0

Channel status information from HDMIRX, [191:160]

0x20

R/W

31:3

RW

0x1fffffff

The start address of fifo0 writes ddr.

2:0

R

0x0

reserved

AUDIN_FIFO0_END

Default

Description

0x21
R/W

Description

31:3

RW

0x1fffffff

The end address of fifo0 writes ddr.

2:0

R

0x0

reserved

H

0x22

ar

Bit(s)

AUDIN_FIFO0_PTR

Defaultdker

Bit(s)ne

AUDIN_FIFO0_START

DescriptionlBit(s)

0x19

R/W

Default

31:3

R

0x0

The current address of fifo0 writes ddr.

2:0

R

0x0

reserved

R/W

Default

31:3

RW

0x0

2:0

R

0x0

AUDIN_FIFO0_RDPTR
R/W

31:3

RW

2:0

R

Bit(s)

When current address of fifo0 writes ddr matched, fifo0 will generate IRQ
reserved

0x24

Default

Description

0x0

The read address of fifo0.

0x0

reserved

0x25

D

AUDIN_FIFO0_CTRL

DescriptionisBit(s)trib

Bit(s)

e

0x23

ut

AUDIN_FIFO0_INTR

DescriptiontoBit(s)

Default

Description

RW

0x0

reserved

28

RW

0x0

AUDIN_FIFO0_HOLD_LVL

27:26

RW

0x0

AUDIN_FIFO0_HOLD2_SEL

25:24

RW

0x0

AUDIN_FIFO0_HOLD1_SEL

23:22

RW

0x0

AUDIN_FIFO0_HOLD0_SEL

21

RW

0x0

AUDIN_FIFO0_HOLD2_EN

20

RW

0x0

AUDIN_FIFO0_HOLD1_EN

19

RW

0x0

AUDIN_FIFO0_HOLD0_EN

15

RW

0x0

AUDIN_FIFO0_UG, urgent request enable

0x0

AUDIN_FIFO0_CHAN.
channel and 2 channel

31:29

14:11

R/W

RW

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S905 Datasheet

Revision 1.1.4

10:8

0x0

RW

AUDIN_FIFO0_ENDIAN

0x0

AUDIN_FIFO0_DIN_SEL// 1 I2Sin// 2 PCMIN// 3 HDMI in// 4 DEMODULATOR IN

data endian control// 0

spdifIN

3

RW

2

RW

0x0

AUDIN_FIFO0_LOAD write 1 to load address to AUDIN_FIFO0.

1

RW

0x0

AUDIN_FIFO0_RST

RW

0x0

AUDIN_FIFO0_EN

R/W

Default

Description
reserved

31:8

RW

0x0

7

RW

0x0

Din_pos[2]

6

RW

0x0

Reserved

5:4

RW

0x0

Dest_sel

3:2

RW

0x0

Din_byte_num

1:0

RW

0x0

Din_pos[1:0]

Description

AUDIN_FIFO0_LVL0

0x27

R/W

Default

31:3

R

0x0

Fifo0 empty lvl0

2:0

R

0x0

reserved

Description

H

0x28

Bit(s)

R/W

Default

31:3

R

0x0

2:0

R

0x0

reserved

Default

31:3

R

0x0

2:0

R

0x0

tr
ib

R/W

RW

17:12
11:6
5:0

Fifo0 empty lvl2
reserved

0x30

Default

Description

0x0

reserved

RW

0x3

Audin req burst number

RW

0x3f

Fifo0 req burst number

0x0

Fifo0 req ID

is

R/W

31:18

Description

D

AUDIN_FIFO0_REQID
Bit(s)e

0x29

Bit(s)

ut

AUDIN_FIFO0_LVL2

Fifo0 empty lvl1

to

AUDIN_FIFO0_LVL1

ar

Bit(s)lBit(s)

0x26

ne

AUDIN_FIFO0_CTRL1

dk
er

0

RW

AUDIN_FIFO0_WRAP

0x31

Bit(s)

R/W

Default

Description

31:16

R

0x0

reserved

15:0

R

0x0

Fifo0 wrap counter

AUDIN_FIFO1_START

0x33

Refer to FIFO0.
AUDIN_FIFO1_END

0x34

Refer to FIFO0.

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Revision 1.1.4

AUDIN_FIFO1_PTR

0x35

Refer to FIFO0.
AUDIN_FIFO1_INTR

0x36

Refer to FIFO0.
AUDIN_FIFO1_RDPTR

0x37

Refer to FIFO0.
AUDIN_FIFO1_CTRL

0x38

Refer to FIFO0.

l

0x39

ne

AUDIN_FIFO1_CTRL1
Refer to FIFO0.
0x40

dk
er

AUDIN_FIFO1_LVL0
Refer to FIFO0.
AUDIN_FIFO1_LVL1

0x41

AUDIN_FIFO1_LVL2

arRefer to FIFO0.
0x42

AUDIN_FIFO1_REQID

H

Refer to FIFO0.
0x43

AUDIN_FIFO1_WRAP

toRefer to FIFO0.
0x44

0x45

tr
ib

Refer to FIFO0.
AUDIN_FIFO2_END

0x46

Refer to FIFO0.

0x47

D

Refer to FIFO0.

is

AUDIN_FIFO2_PTR

ut

AUDIN_FIFO2_STARTeRefer to FIFO0.

AUDIN_FIFO2_INTR

0x48

Refer to FIFO0.

AUDIN_FIFO2_RDPTR

0x49

Refer to FIFO0.
AUDIN_FIFO2_CTRL

0x4a

Refer to FIFO0.
AUDIN_FIFO2_CTRL1

0x4b

Refer to FIFO0.

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Revision 1.1.4

AUDIN_FIFO2_LVL00x4c

Refer to FIFO0.
AUDIN_FIFO2_LVL1

0x4d

Refer to FIFO0.
AUDIN_FIFO2_LVL2

0x4e

Refer to FIFO0.
AUDIN_FIFO2_REQID

0x4f

Refer to FIFO0.

l

0x50

ne

AUDIN_FIFO2_WRAPAUDIN_INT_CTRL
Bit(s)

0x51
R/W

31:16

Default

Description

0x0

reserved

RW

15:14

RW

0x3

reserveddk
erRefer to FIFO0.

RW

0x1

Fifo2 flush mask

12

RW

0x1

Fifo2 int mask

11

RW

0x1

Fifo2 overflow int mask

10

RW

0x1

audout address trigger interrupt mask

RW

8

RW

0x1

H

9

0x1

ar

13

0x1
RW

6

RW

5

RW

0x1

4

RW

0x1

3

RW

0x1

AUDOUT_FIFO level low pulse interrupt mask. once the audout fifo counter lower thanthe 22:16Bits. it will generate one interrupt

RW
RW

ut

fifo1 PIO mode flush request interrupt mask
fifo0 PIO mode flush request interrupt mask
fifo1 address trigger interrupt mask
fifo1 overflow interrupt mask

0x1

fifo0 address trigger interrupt mask

0x1

fifo0 overflow interrupt mask

0x52

Bit(s)

R/W

Default

Description

31:14

D

AUDIN_FIFO_INTAUDOUT_FIFO level low level interrupt mask. if the audout fifo coutner is lower than
22:16 Bits, it will generate interrupt

0x1

is

0

tr
ib

RW

1

e

0x1

2

PCMIN error interrupt mask

to7

PCMOUT error interrupt mask

R

0x0

Reserved

13

R

0x0

Fifo2 flush int st

12

R

0x0

Fifo2 int st

11

R

0x0

Fifo2 overflow int st

10

R

0x0

audout address trigger interrupt. Write 1 to clean

9

R

0x0

PCMOUT error interrupt. Write 1 to clean

8

R

0x0

PCMIN error interrupt. Write 1 to clean

7

R

0x0

AUDOUT_FIFO level low pulse interrupt. Write 1 to clean

6

R

0x0

AUDOUT_FIFO level low level interrupt. Write 1 to clean

5

R

0x0

fifo1 PIO mode flush request interrupt. Write 1 to clean

4

R

0x0

fifo0 PIO mode flush request interrupt. Write 1 to clean

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S905 Datasheet

Bit(s)

Revision 1.1.4

R/W

Default

3R

0x0

Description
fifo1 address trigger interrupt. Write 1 to clean

2

R

0x0

fifo1 overflow interrupt. Write 1 to clean

1

R

0x0

fifo0 address trigger interrupt. Write 1 to clean

0

R

0x0

fifo0 overflow interrupt. Write 1 to clean

PCMIN_CTRL00x60

Bit(s)

R/W

Default

Description

31

RW

0x0

PCMIN enable

30

RW

0x0

PMCIN soft reset. write 1 to reset PCMIN module

RW

0x0

PCMIN sync on clock posedge

0x0

PCMIN fs skew
001. delay fs one cycle.
010. delay fs two cycle.
011. delay fs 3 cycle.
111. delay data one cycle.
110. delay data 2 cycle.
101. delay data 3 cycle.
100. delay data 4 cycle.

0x0

system clock data sample count

RW

15:4

RW

l
ne

18:16

000: FS and data no skew.

dk
er

29

0x0

system clock data sample selection
0 = use the clock data sample counter

1 = use edge detection.

RW

2

RW

0x0

fs invert. invert the FS signal

RW

0x0

1 = the coming data is msb first. 0 = lsb first.

0

RW

0x0

1 = the coming data is left justified. 0 = the coming data is right justified.

PCMIN_CTRL1

0x61

Bit(s)

R/W

H

to

1

ar

3

Default

Description

0x0

28

RW

0x0
0x0

RW
26:21
20:16

RW

15:0

RW

31
30
29

1: use negedge clock to sample the coming data. 0. use pcmin posedge clk to sample thedata
max slot number in one frame

0x0

max bit number in one slot

0x0

valid slot . Each Bit for one slot

isBit(s)

pcmin clock sel. 1= internal from cts_pcm_clk. 0 = external PCM interface

0x62

R/W

Default

Description

RW

0x0

PCMIN enable.

RW

0x0

PMCIN soft reset. write 1 to reset PCMIN module.

RW

0x0

PCMIN sync on clock posedge.

0x0

PCMIN fs skew.
//000: FS and data no skew.
//001. delay fs one cycle.
//010. delay fs two cycle.
//011. delay fs 3 cycle.
//111. delay data one cycle.
//110. delay data 2 cycle.
//101. delay data 3 cycle.
//100. delay data 4 cycle.

0x0

system clock data sample count.

D

PCMIN1_CTRL0

0x0

RW

tr
ib

27

pcmin SRC sel. 1= pcmin is from internal audio CODEC(I2S format). 0 = external PCM
interface (from pad).

e

RW

ut

29

18:16

RW

15:4

RW

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S905 Datasheet

Bit(s)

Revision 1.1.4

R/W

Default

Description

0x0

system clock data sample selection.
1 = use edge detection.
0 = use the clock data sample counter.

3

RW

2

RW

0x0

fs invert. invert the FS signal.

RW

0x0

1 = the coming data is msb first. 0 = lsb first.

RW

0x0

1 = the coming data is left justified. 0 = the coming data is right justified.

0

PCMIN1_CTRL1
Bit(s)

0x63
R/W

Default

Description

0x0
RW

28

RW

pcmin SRC sel. 1= pcmin is from internal audio CODEC(I2S format). 0 = external PCM
interface (from pad).

l

29

0x0

pcmin clock sel. 1= internal from cts_pcm_clk. 0 = external PCM interface.

0x0

1: use negedge clock to sample the coming data. 0. use pcmin posedge clk to sample the
data.

RW

26:21

RW

0x0

max slot number in one frame.

RW

0x0

max bit number in one slot.

RW

0x0

valid slot . Each Bit for one slot.

20:16
15:0

PCMOUT_CTRL0

Default

RW0x0

pcmout enable bit.

29

RW

0x0

pcmout 1= master mode. 0 = slave mode.

28

RW

0x0

system clock sync at pcmout posedge clock.

RW

0x0

system clock sync at clock edge of pcmout clock. 0 = sync on clock counter.

26：15

RW

0x0

14

RW

0x0

13

RW

0x0

12

RW

0x0
0x0

11：6

RW

5：0

RW

PCMOUT_CTRL1
R/W

D

28

Default

RW

31：30

H

to

left justified.
output data is at h24b of the input.
in PCM slave mode. when pcmo received a FS, it will sync the slot bit counter to thisnumber.
in PCM slave mode. when pcmo received a FS, it will sync the frame slot counter to thisnumber.

0x71

is

Bit(s)

pcmout is msb first.

tr
ib

0x0

system clock sync at counter number if sync on clock counter.

e27

Description

ar

R/W

31

ut

Bit(s)

0x70

dk
er

27

ne

1

0x0
0x0

RW

0x0

Description
pcmo output data byte number. 00 : 8Bits. 01: 16Bits. 10: 24Bits. 11: 32Bits.
pcmo clock slow invert. invert the pcm output logic clock. for example, use negedge to
output data.
pcmo slave parts clock invert. invert the clock which is used to sample the fs_in when
pcmo in slave mode.

27

RW

26

RW

0x0

invert fs phase.

25

RW

0x0

invert the fs_o for master mode.

23：18

RW

0x0

fs_o start postion frame slot counter number

RW

0x0

fs_o start postion slot bit counter number.

11：6

RW

0x0

fs_o end postion frame slot counter number.

5：0

RW

0x0

fs_o end postion slot bit counter number.

17：12

PCMOUT_CTRL2

0x72

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R/W

Default

Description

31

RW

0x0

pcmo mute.

30：29

RW

0x0

pcmo_underrun mode. 00: the output data will use mute constant. 01: repeat theprevious data.

27：22

RW

0x0

pcmo max slot number in one frame.

21：16

RW

0x0

pcmo max bit number in one slot.

15：0

RW

0x0

pcmo valid slot. Each Bit for one slot.

PCMOUT_CTRL3

0x73

Bit(s)

R/W

Default

31:0

RW

0x0

0x74
Description

0x0

pcmout enable bit

29

RW

0x0

pcmout 1= master mode. 0 = slave mode

28

RW

0x0

system clock sync at pcmout posedge clock.

RW

0x0

system clock sync at clock edge of pcmout clock. 0 = sync on clock counter.

26:15

RW

0x0

system clock sync at counter number if sync on clock counter.

14

RW

0x0

pcmout is msb first.

RW

0x0

left justified.

RW

0x0

output data is at h24b of the input.

0x0

in PCM slave mode. when pcmo received a FS, it will sync the slot bit counter to thisnumber.
in PCM slave mode. when pcmo received a FS, it will sync the frame slot counter to thisnumber.

11:6

RW

5:0

RW

PCMOUT1_CTRL1
Bit(s)

0x0

0x75
R/W

Default

RW

28

RW

27

RW

26

RW

25

RW

0x0
0x0
0x0

pcmo output data byte number. 00 : 8Bits. 01: 16Bits. 10: 24Bits. 11: 32Bits.
pcmo clock slow invert. invert the pcm output logic clock. for example, use negedge to
output data.
pcmo slave parts clock invert. invert the clock which is used to sample the fs_in when
pcmo in slave mode.
invert fs phase
invert the fs_o for master mode0x0

fs_o start postion frame slot counter number

0x0

fs_o start postion slot bit counter number

RW

0x0

fs_o end postion frame slot counter number

RW

0x0

fs_o end postion slot bit counter number

Default

Description

0x0

pcmo mute

0x0

pcmo_underrun mode. 00: the output data will use mute constant. 01: repeat theprevious data

RW

17:12

RW

11:6

is

0x0

23:18

D

5:0

Description

0x0

tr
ib

31:30

ar

12

to

13

e

27

dk
er

Default

RW

H

R/W

31

ut

Bit(s)

pcmo mute constant value.

l

PCMOUT1_CTRL0

DescriptionneBit(s)

Revision 1.1.4

PCMOUT1_CTRL2
Bit(s)
31

0x76

R/W
RW

30:29

RW

27:22

RW

0x0

pcmo max slot number in one frame

21:16

RW

0x0

pcmo max bit number in one slot

RW

0x0

pcmo valid slot. Each Bit for one slot.

15:0

PCMOUT1_CTRL3
Bit(s)

0x77
R/W

Default

Description

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31:0

Revision 1.1.4

0x0

RW

AUDOUT_CTRL

0x80
Description

RW

0x0

AUDOUT FIFO enable.

30

RW

0x0

AUDOUT FIFO reset. write 1 to reset

29

RW

0x0

AUDOUT fifo load DMA address. write 1 to load.

RW

0x0

Clr audout wrap counter. write 1 to clear.

27

RW

0x0

clr audout rdrsp counter. write 1 to clear.

24

RW

0x0

audout next bufer enable. if in pingpeng buffer mode.

23:22

RW

0x0

audout level control write pointer selection.

21:25

RW

0x0

audout DMA one time request size.

14:8

RW

0x0

audout buffer level. buffer level must > one time DMA request size.

7

RW

0x0

audout buffer level control enable.

RW

0x0

1 audout DMA mode. 0. audout PIO mode.(CPU use cbus to push data.)

0x0

audout use circur Buffer in DDR2/3 SDRAM. 1 = circur buffer mdoe. 0 = pingpang buffer
mode.

31

28

6

l

Default

ne

R/W

dk
er

Bit(s)

Pcmo1 mute constant value.

RW

4

RW

0x0

audout buffer selection if in ping pang buffer mode.

3

RW

0x0

audout DMA request urgent bit.

RW

0x0

audout DMA data endian control.

Default

Description

2:0

AUDOUT_CTRL1

ar

5

0x81
R/W

11:6

RW

0x0

AUDOUT DMA request burst number control for pre_mmc_arb.

RW

0x0

AUDOUT DMA request ID.

31:0

RW

AUDOUT_BUF0_EDA
R/W

31:0

RW

AUDOUT_BUF0_WPTRD

RWAUDOUT_BUF1_STA

R/W

31:0

RW

AUDOUT_BUF1_EDA

Description

0x0

Default
0x0

buf0 start address. or circur buffer start address

Description

buf0 end address. or circur buffer end address

0x84

Default

Description

0x0

buf0 write pointer.

is

R/W

31:0

Bit(s)

Default

0x83

Bit(s)

Bit(s)toR/We

Bit(s)

0x82

ut

AUDOUT_BUF0_STA

tr
ib

5:0

H

Bit(s)

0x85
Default

Description

0x0

Buf1 start address. or circur buffer start address

0x86

Bit(s)

R/W

31:0

RW

AUDOUT_BUF1_WPTR
Bit(s)

R/W

31:0

RW

Default

Description

0x0

Buf1 end address. or circur buffer end address

0x87
Default

Description

0x0

Buf1 write pointer.

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Revision 1.1.4

AUDOUT_FIFO_RPTR
R/W

31:0

RW

Default

Description

0x0

Buffer DMA read address

AUDOUT_INTR_PTR
Bit(s)

0x89

R/W

31:0

RW

AUDOUT_FIFO_STS

Default

Description

0x0

When DMA read to this address, it will generate an interrupt to CPU

Default

Description

0x8a
R/W

31:7

R

0x0

R

0x0

reserved
AUDOUT FIFO depth counter.

Description

6:0

0x35

Bit(s)

R/W

Default

31:0

RW

0x0

AUDIN_FIFO0_PIO_STS

Default

DescriptionR

0x0

Fifo0 pio request.

R

0x0

Reserved

Bit(s)
31:0

R/W

Default

Description

RW

0x0

Fifo0 pio write data [31:0]

AUDIN_FIFO0_PIO_RDH

8'hb2 0xb2

R/W

Default

RW

0x0

AUDIN_FIFO1_PIO_STS

0xb3

31:0

Bit(s)
31
30:0

R/W
R
R

31:0

R/W

D

Bit(s)RW

AUDIN_FIFO1_PIO_RDH
Bit(s)
31:0

31
30:0

Fifo0 pio write data [63:32]

Description
Fifo1 pio request.

0x0

Reserved

0xb4

Default

Description

0x0

Fifo1 pio write data [31:0]

0xb5

R/W

Default

Description

RW

0x0

Fifo1 pio write data [63:32]

AUDIN_FIF0O2_PIO_STS
Bit(s)

Description

0x0

is

AUDIN_FIFO1_PIO_RDL

Defaulttrib

Bit(s)

0xb1

H

AUDIN_FIFO0_PIO_RDL

ar

R/W

to

30:0

0xb0

e

31

cntl_mute_val: Use this value during mute, if cntl_mute_mode=2.

ut

Bit(s)dk
er

AUDIN_MUTE_VAL

neBit(s)

0xb6

R/W

Default

DescriptionR

0x0

Fifo2 pio request.

R

0x0

Reserved

AUDIN_FIFO2_PIO_RDLl

Bit(s)

0x88

0xb7

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Bit(s)
31:0

Revision 1.1.4

R/W

Default

Description

RW

0x0

Fifo2 pio write data [31:0]

AUDIN_FIFO2_PIO_RDH
Bit(s)
31:0

R/W

Default

Description

RW

0x0

Fifo2 pio write data [63:32]

AUDOUT_FIFO_PIO_STS

0xb9

R/W

Default

Description

31

R

0x0

audout pio request.

30:7

R

0x0

Reserved

6:0

R

0x0

Audout fifo low level

AUDOUT_FIFO_PIO_WRL

0xba

R/W

Default

Description

31:0

R

0x0

Audout fifo rdata [31:0]

AUDOUT_FIFO_PIO_WRH

0xbb

dk
er

Bit(s)

R/W

Default

Description

31:0

R

0x0

Audout fifo rdata [63:32]

Description

0x0

soft_reset: 1 = reset

30:29

RW

0x0

resample source select: 0: fifo0, 1:fifo1, 2:fifo2

28

RW

0x0

27:26

RW

0x0

25:16

RW

0x0

RW

0x0

AUD_RESAMPLE_CTRL1

0xc0

Bit(s)
31:0

R/W
RW

AUD_RESAMPLE_STATUS

tooutrdy generate count: equal mclk/lrclk*2

Default
0x0

RW

average count initial value

Description

phase step

0xc1

Default

Description

0x0

report the real frequency of input data

D

21:0

R/W

resample method select:2,3 reserved.

isBit(s)

resample enable: 0 = disable, 1 = enable

e

15:0

H

Default

RW

31

ut

R/W

0xbf

tr
ib

Bit(s)ar

Bit(s)

AUD_RESAMPLE_CTRL

nelBit(s)

0xb8

PDM Registers:
Final Address = 0xd0042000+offset*4
PDM_CTRL

0x40

Bit(s)

R/W

Default

Description
CIC_DEC8OR16_SEL, 0:8, 0:16

2

RW

0x0

1

RW

0x0

PDM_HPF_BYPASS

RW

0x0

PDM_ENABLE,1 enable

Default

Description

0

PDM_IN_CTRL
Bit(s)

0x42
R/W

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18

RW

0x0

PDMIN_REV

17

RW

0x0

PDMCLK_REV

16

RW

0x0

GET_STA_EN

8

RW

0x0

SAMPLE_CNT

PDM_VOL_CTRL

0x43

Bit(s)

R/W

1
0

25:0

PDMR_INV

0x44
R/W

Default

Description

RW

0x0

The left channel vol gain

R/W

Default

Description

RW

0x0

The right channel vol gain

PDM_VOL_GAIN_R
Bit(s)

RW

0x45

0x46

Bit(s)

R/W

Default

DescriptionR

0x0

Clk_cnt _overflow

30:24

R

0x0

Min_clk_cnt

23:16

R

0x0

Max_clk_cnt

R0x0

Det_din_mincnt

R0x0

Det_din_maxcnt

15:8

to

7:0

H

31

ar

PDM_STATUS

l

25:0

PDML_INV

0x0

dk
er

Bit(s)

Description

0x0

ne

PDM_VOL_GAIN_L

Default

RW

ute

31. Audio Output
31.1 Overview

tribThis part describe the audio output from the following aspect: SPIDF(encode) and I2S(encode), also all the registers related toaudio path are listed in the end of this part.

is31.2 SPDIF(encode)

D

The SPDIF(encode) module works in the following 4 steps:
Step1: get the data from ddr.
Step2: write to fifo and make endian modification.
Step3: get the data from fifo by mode select.
Step4: encode.
Fig V.31.1 Diagram of spdif(encode)

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SPDIF supports the following mode:

8ch

dk
er

Table V.31.1 SPIDF Modein ddr2ch
16Bits**1
8ch
16Bits**1
normal2ch
32Bits**3nelS905 Datasheet

32Bits**3

ar

16Bits**1
24Bits**2

split
nonpcmH

24Bits(32Bits) **3
16Bits**4

31.3 I2S(encode)

ut

e

to

**1: In this mode, data in ddr is 16Bits.
**2: In this mode, data in ddr is 2x24Bits.
**3: In this mode, data in ddr is 32Bits.
**4: In this mode, data in ddr is 16Bits.
In normal mode, it support 2/8channel & 16Bits/24Bits/32Bits

D

is

tr
ib

The I2S(encode) module works in the following 4 steps:
Step1: get the data from ddr or cbus.
Step2: write to fifo and make endian modification.
Step3: get the data from fifo by mode select.
Step4: encode 4 streams.

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Fig V.31.2 Diagram of I2S(encode)i2s(encode)
step2

step1

step3

aiu_i2s_cbus_ddr_cntl[6]step4

aiu_i2s_source_desc[11]ddr

split out
split mode
1

1

[63:0]

ddr_endiani2s_fifo(64x64)[63:0][63:0]

24bit x 4

ddr_endian

1bit x 4
encodenormal out

0normal mode0

Step3, I2S supports the following modes:

ar

split

output4streams
4streams
1stream
1stream
1stream4streamdk
ernormalTable V.31.2 I2S Modein ddr8ch
16Bits**1
8ch 24Bits(32Bits)**22ch
16Bits**3
8ch
16Bits**3
8ch 24Bits(32Bits) **4
8ch 24Bits(32Bits) **4

ne

l

cbus

to

H

**1: In this mode, data in ddr is 16Bits,**2: In this mode, data in ddr is 32Bits,**3: In this mode, data in ddr is 16Bits,**4: In this mode, data in ddr is 32Bits,
In normal mode, it support only 8channel & 4streams & 16Bits/24Bits.

is

tr
ib

ut

e

The register aiu_mem_I2S_mask[15:0] can skip some read (by [15:8]) and output operation(by [7:0]).
For example:
if [15:8] = 8’b1111_1111, read ch0/ch1/ch2/ch3/ch4/ch5/ch6/ch7
if [15:8] = 8’b1110_1101, read ch0/ch2/ch3/ch5/ch6/ch7,ch1/ch4 skipped
if [7:0] = 8’b1111_1111, output ch0/ch1/ch2/ch3/ch4/ch5/ch6/ch7
if [7:0] = 8’b1110_1101, output ch0/mute/ch2/ch3/mute/ch5/ch6/ch7
In split mode, it will read data from ddr by linear sequence, and support 24Bits(1/4 streams) and 16Bits(1 stream) mode.

D

In split mode, there is no mask control, so aiu_mem_I2S_mask[15:0] must set 8’hffff_ffff.
I2S_encode_core can encode four I2S sample[23:0] to four 1 bitsignal at the same time.
The control includes:
hold, stop working until set to 1’b0.
underrun,
2’d0: send 0,
2’d1: send 0x800000,
2’d2: send last sample.
med_ctrl, if median work, out = (s1>(s0+s2)/2+th)?(s0+s2)/2:s1, that’s mean if there are a burst noise sample, it will
be replaced.
ch_swap: change the channel, assume input = L + R,
2’d0: output = L + R,

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ne

is

tr
ib

ut

e

to

H

ar

dk
er

2’d1: output = L + L,
2’d2: output = R + R,
2’d3: output = R + L.
sel: use four mux4 to change the connect of in/out
sel0:
2’d0: out0 = in0,
2’d1: out0 = in1,
2’d2: out0 = in2,
2’d3: out0 = in3,
sel1:
2’d0: out1 = in0,
2’d1: out1 = in1,
2’d2: out1 = in2,
2’d3: out1 = in3,
sel2/sel3 are the same.
mute: [0] mute channel 0, [1] mute channel1, …[7] mute channel7
msb_first: 0:lsb first, 1: msb first.
dac_size:
2’d0: output 16Bits,
2’d1: output 20Bits,
2’d2/3: output 24Bits
Fig V.31.3 Diagram of I2S encode corel

S905 DatasheetD

31.4 Register Description
The final addresses of the following registers should be calculated with the following equation:
Final address = 0xc1105400+offset*4

AIU_958_bpf
Bit(s)
15:0

0x00
R/W

Default

Description

RW

0x0

Bytes per frame in spdif.

Default

Description

AIU_958_brst

0x01

Bit(s)

R/W

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15:0

Revision 1.1.4

0x0

Burst info in spdif

R/W

Default

Description

RW

0x0

The length of code in spdif

RW

AIU_958_lengthBit(s)
15:0

0x02

AIU_958_paddsize

0x03

Bit(s)

R/W

Default

Description

15:0

RW

0xc00

The padd size of spdif

0x04

Bit(s)

R/W

Default

Description

0x0

pcm_sample_ctl, 00-pcm_no_sample, 01-pcm_sample_up, 10-pcm_sample_down, 11pcm_sample_down_drop
if true, force each audio data to left or right according to the bit attached with the audio
data.This bit should be used with Register AIU_958_force_left(0x505) together
if true, the U(user data) is from the stream otherwise it is filled by zero while encoding
iec958 frame
if true big endian(highword,lowword) otherwise little endian(lowword,highword)for 32 bit
model

AIU_958_misc

RW

13

RW

12

RW

11

RW

10:8

RW

0x0

7

RW

0x0

32 bit mode turn on while This bit is true and bit 1 is true

0x0

Specifies output alignment for 16 bit pcm data.
//
00 : dout = {8'b0, din};//
01 : dout = {4'b0, din, 4'b0};//
10 : dout = { din, 8'b0};

ne

15:14

0x0

dk
er

0x0
0x0

ar

shift number for 32 bit mode

RW

4

RW

0x0

True if data should be sent out MSB first. LSB first is the default in the spec.

3

RW

0x0

True if msb should be extended (only used with 16 bit pcm data.)

RW

0x0

True if msb of PCM data should be inverted.

1

RW

0x0

0

RW

0x06
R/W

6:0

R

AIU_958_dcu_ff_ctrl

to

0x1

Description
how many data discarded in the last dma after one frame data finish transfering to AIU.
Should used together with register AIU_958_dcu_ff_ctrl, read only

0x07

Bit(s)R/W

RW

Default
0x0

Description
A read from this register indicates the IEC958 FIFO count value

is

15:8

Defaulttrib

Bit(s)

True if source data is non-PCM data. False if it is PCM data.

ut

AIU_958_discard_num

True if PCM data is 16 Bits wide. False if 24 bit or 32 bit mode.

0x1

e

2

H

6:5

RW

0x0

ai_958_req_size if ture, set to 8 Bits interface, used to handle odd frame continous read

RW

0x0

continue seeking and dont discard the rest data in one dma after frame end

RW

0x0

if true, byte by byte seeking, otherwise word by word seeking

4

RW

0x0

if true, the function for sync head seeking is enabled

3:2

RW

0x0

IEC958 interrupt mode

0x0

fifo auto disable, High means after one frame data put into the FIFO, the FIFO willautomatically disabled

0x0

fifo enable

Description

6
5

D

7

1

RW

0

RW

AIU_958_chstat_l0

0x08

Bit(s)

R/W

Default

31:0

R

0x0

channel status registers for Left channel

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AIU_958_chstat_l1

0x09

Bit(s)

R/W

Default

31:0

R

0x0

R/W

Default

Description

0x0

what to do if there is a fifo underrun
00 => insert 24'h000000
01 => insert mute constant as defined below
10 => repeat last l/r samples
mute constant000 => 24'h000000
001 => 24'h800000
010 => 24'h080000
011 => 24'h008000
100 => 24'h000001
101 => 24'h000010
110 => 24'h000100

AIU_958_ctrl

Description

channel status registers for right channel

0x0aBit(s)
9:8

RW
0x0

RW

4

RW

0x0

mute left speaker

RW

0x0

mute right speaker

RW

0x0

swap channels

0x0

Set This bit to hold iec958 interface after the current subframe has been completelytransmitted.

Description

0

RW

AIU_958_rpt

0x0bBit(s)

R/W

Default

31:0

RW

0x0

R/W

Default

to

15:8

RW

0x0

Mute 8 channel

7:6

RW

0x0

5:4

RW

3:2

RW

ut

Ch4/5 swap sel.

0x0

Ch2/3 swap sel.

0x0

Ch0/1 swap sel.

0x0d

R/W

Default

Description

RW

0x0

Use_i2s_split

RW

0x0

Endian_32bit

RW

0x0

Mode_32bit

RW

0x0

Sft_bits

5

RW

0x0

Steam_16or24b

4:3

RW

0x0

Msb_position

2

RW

0x0

Msb_extend

1

RW

0x0

Msb_invert

0

RW

0x0

Num_streams:0:2ch;1:8ch;

is

Bit(s)

Ch6/7 swap sel.

0x0

tr
ib
RW

AIU_I2S_source_desc

Description

e

0x0c

1:0

10
9
8:6

D

11

ne

H

A write operation to this register will cause one of the output samples
to be repeated. This can be used to switch the left and the rightchannels.

Bit(s)

AIU_I2S_mute_swap

dk
er

2:1

ar

3

l

7:5

AIU_I2S_med_ctrl

0x0e

Bit(s)

R/W

Default

Description

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1

RW

0x0

0=> data is offset binary
1=> data is signed

0

RW

0x0

enable median filter

AIU_I2S_med_thresh

0x0f

Bit(s)

R/W

Default

15:0

RW

0x0

AIU_I2S_dac_cfg

0x10

Bit(s)R/W

Description

Median filter threshold constantDefault

Description
sign extend sample before downshift

RW

6:4

RW

0x0

payload downshift constant

0x0

mute constant0 => 'h0000000
1 => 'h800000

0x0

send msb first

0x0

Size of payload, 00 => 16 bit, alrclk = aoclk/32
01 => 20 bit, alrclk = aoclk/40
10 => 24 bit, alrclk = aoclk/48
11 => 24 bit, but alrclk = aoclk/64

Default

Description

0x0

if true, force each audio data to left or right according to the bit attached with the audio
data.This bit should be used with Register AIU_I2S_sync(0x511) together

2

RW

1:0

RW

0x12

Bit(s)R/War

AIU_I2S_misc

ne

RW

dk
er

3

l

7

0x0

RW

3

RW

0x0

Same Audio source for IEC958 and I2S stream 0, both from I2S buffer

2

RW

0x0

Set This bit to put I2S interface in hold mode

0x0

How to handle underruns//
00 => send zeros//
01 => send 'h800000//
10 => repeat last samples

0x13

Bit(s)

R/W

3
2
1

is

Bit(s)

R/W

0

AIU_clk_ctrl
Bit(s)
15

Description

0x0

Audio output config.
2 Bits for each dac, 7:6 for dac3, 5:4 for dac2,3:2 for dac1, 1:0 for dac0
For each 2Bits: 00: connect channel0-1 to the dac
01: connect channel2-3 to the dac
10: connect channel4-5 to the dac
11: connect channel6-7 to the dac

0x15

D

AIU_rst_soft

RW

Default

tr
ib

7:0

to

AIU_I2S_out_cfg

e

RW

ut

1:0

H

4

Default

Description

RW

0x0

reset slow domain iec958

RW

0x0

soft reset iec958 fast domain

RW

0x0

reset slow domain I2S

RW

0x0

soft reset I2S fast domain

Default

Description

0x0

enable_ddr_arb, set low to reset

0x0

parser_A_addr_sel 00-A_addr_aififo2, 01-A_addr_iec958, 10-A_addr_aififo, 11A_addr_I2S

0x0

958 divisor more, if true, divided by 2, 4, 6, 8

0x16
R/W
RW

14:13

RW

12

RW

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Bit(s)

R/W

11

RW

10

RW

Default

Description

0x0

amclk output divisor
0 => dont divide
1 => divide by 2
clock source selection
0 => aiclk from pin
1 => ai_pll_clk from pll
alrclk skew
00 => alrclk transitions at the same time msb is sent
01 => alrclk transitions on the cycle before msb is sent
10 => alrclk transitions on the cycle after msb is sent

0x0

0x0
9:8

RW

7

RW

0x0

invert alrclk

6

RW

0x0

invert aoclk

0x0

958 divisor
00 => divide by 1
01 => divide by 2
10 => divide by 3
11 => divide by 4
I2S divisor. NOTE: this value is ignored if AIU_clk_ctrl_more[5:0] != 0
00 => divide by 1
01 => divide by 2
10 => divide by 4
11 => divide by 8

l

RW

ne

5:4

0x0
RW

1

RW

0x0

enable 958 divider

0

RW

0x0

enable I2S divider

Default

Description

0x0

selects adc input

0x0

adc size
00 => 16 Bits
01 => 18 Bits
10 => 20 Bits
11 => 24 Bits
adc l/r swap mode
00 => stereo
01 => send the right adc input to both l and r speakers
10 => send the left adc input to both l and r speakers
11 => sum the left and right inputs and forward to both speakers

Bit(s)

R/W

12

RW

RW

to

11:10

7:5

RW

2

11

0x0

1=>Latch the data on the positive edge of the _internal_aoclk.

RW

0x0

1=>adc data is in signed 2's complement mode

Default

Description

0x0

if true, toggle each mixed audio data to left or right channel

0x0

abuf din left selection, if true, select bit 24 of the data from abuf otherwise select bit 25 ofthe data from abuf
mix sync select, when music, mic and abuf are mixed togather, the main sync source canbe selected
00: not sync source
01: music data is the main sync source
10: abuf input data is the main sync source
11: music and abuf togather as the sync source
0=> data from abuf is offset binary
1=> data from abuf is signed
the source for data from aiu to abuf
00 => mic
01 => mic saled + abuf scaled
10 => mic scaled + abuf scaled + music scaled
11 => musicis12

1=>invert the adc's lrclk (This is the lrclk going _out_of the chip.

RW

0x18

R/W

D

Bit(s)

adata/lrclk skew mode

0x0

RW

3

AIU_mix_ctrl

0x0

tr
ib

4

ut

RW

e

0x0
9:8

RW
RW

0x0
10:9

RW

8

RW

0x0
0x0

7:6

ar

0x17

H

AIU_mix_adccfg

dk
er

3:2

RW

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Bit(s)

R/W

Default

Description
channel from aiu to abuf is on

5

RW

0x0

4

RW

0x0

channel from abuf to aiu is on

RW

0x0

mic is on

RW

0x0

music is on

0x0

if true the mixed data are outputed to I2S dac channel,otherwise the mixed data are
outputed to IEC958 output
if true music source for mixing is from I2S buffer, otherwise music source is from iec958
buffer

3
2
1

RW

0

RW

0x19

Bit(s)
15

R/W

Default

Description

RW

0x0

invert_audin_sclk
enable_adc_sclk.

l

AIU_clk_ctrl_more

0x0

RW

13:8

RW

0x0

divisor_adc_sclk.

RW

0x0

invert_acodec_adc_sclk

0x0

Bit 6 hdmitx_sel_aoclkx2: 0=Select cts_clk_i958 as AIU clk to hdmi_tx_audio_master_clk;
1=Select cts_aoclkx2_int as AIU clk to hdmi_tx_audio_master_clk;
More control on I2S divisor. For backward compatiblity, this value is ignored if is 0,
if non-zero, it takes effect over AIU_clk_ctrl[3:2].
0=I2S divisor will use the old value in AIU_clk_ctrl[3:2] (divide by 1/2/4/8)
1=divide by 2;
2=divide by 3;
3=divide by 4;... and so on ...
63=divide by 64.

6

RW

dk
er

7

0x0

RW

0x1a

Bit(s)

R/W

15:0

RW

R/W

14:10

RW
RW

4:0

AIU_958_synword1

mic gain

0x0

abuf gainmusic gain

R/W

Default

Description

RW

0x0

sync head seeking, word1

R/W

Default

Description

RW

0x0

sync head seeking, word2

is

0x1c

D

15:0

Description

0x0
0x0

RW

Bit(s)

Default

tr
ib

9:5

A read from this register pops 16 Bits of data off the 958 fifo. A write
has no effect.

e

0x1b

Bit(s)

AIU_958_synword2
Bit(s)

Description

0x0

ut

AIU_mix_gain

Default

to

AIU_958_pop

H

ar

5:0

ne

14

0x0

15:0

AIU_958_synword3

0x1d

0x1e

Bit(s)

R/W

Default

Description

15:0

RW

0x0

sync head seeking, word3

AIU_958_synword1_mask

0x1f

Bit(s)

R/W

Default

Description

15:0

RW

0x0

sync head seeking, mask word1

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AIU_958_synword2_mask

0x20

Bit(s)
15:0

R/W

Default

Description

RW

0x0

sync head seeking, mask word 2

AIU_958_synword3_mask

0x21

Bit(s)
15:0

R/W

Default

Description

RW

0x0

sync head seeking, mask word 3

Default

Description

0x0

fifo read-out threshold, one condition to generate interrupt is met after
fifo readout counter reach this value in a frame, please refer to register
AIU_958_dcu_ff_ctrl

AIU_958_ffrdout_thd

0x22
R/W

15:0

RW

R/W

15:0

RW

AIU_958_pause_num
Bit(s)

Default

Description

0x0

For pause burst sequence adding, one pause burst sequence is consistof a serious pause burst.

Default

Description

if true, one pause burst sequence will be added

0x24
R/W

ar

Bit(s)

0x23

dk
er

AIU_958_length_per_pausenelBit(s)

RW

14:0

RW

0x0

the number of pause burst in a pause burst sequence

Description

0x25

Bit(s)

R/W

Default

15:0

RW

0x0

0x26
R/W
RW

14

RW

7:0

RW

Bit(s)

pause pack option, just for debugging and adding one option

0x0

auto_pause threshold

R/W

Default
0x0

RW

AIU_CODEC_DAC_LRCLK_CTRL
Bit(s)

if true, auto pause function enable

0x0

0x27

D

15:0

Description

0x0

is

AIU_958_pause_pd_length

Default

tr
ib

15

e

Bit(s)

When paused, use this payload .

ut

AIU_958_auto_pause

toAIU_958_pause_payload

H

15

0x0

Description
Pause pd length

0x28
Default

Description

15:12

R/W

0x0

Reserved

11:0

0x0

dac_lrclk_div

RW

AIU_CODEC_ADC_LRCLK_CTRL
Bit(s)

0x29
Default

Description

15:14

0x0

Reserved

13

RW

0x0

inv_audin_lrclk: whether to invert lrclk before output to Audin

RW

0x0

inv_acodec_adc_lrclk: whether to invert lrclk before output to Audio Codec

12

R/W

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0x0

RW

AIU_HDMI_CLK_DATA_CTRL

0x2a
R/W

15:6
RW

3:2
1:0

RW

AIU_CODEC_CLK_DATA_CTRL
Bit(s)

R/W

RW

3:2
1:0

RW

AIU_958_chstat_r0

Reserved0x0

hdmi_data_sel: 00=output 0, disable hdmi data; 01=Select pcm data; 10=Select AIU I2S
data; 11=Not allowed

0x0

Reserved0x0

hdmi_clk_sel: 00=Disable output hdmi clock; 01=Select pcm clock; 10=Select AIU clk;
11=Not allowed.

Default

Description

0x0

Reserved

0x0

acodec_data_sel: 00=output 0, disable acodec_sdin; 01=Select pcm data; 10=Select AIU
I2S data; 11=Not allowed.

0x0

Reserved

0x0

acodec_clk_sel: 00=Disable output acodec_sclk; 01=Select pcm clock; 10=Select AIU aoclk;
11=Not allowed

Description

0x2b

15:6
5:4

Description

0x0

0x30

Bit(s)

R/W

Default

15:0

RW

0x0

ar

contains Bits 15:0 of the channel status word. Note that bit zero of the channel status
word is sent out first.chstat_r1[15:0] contains Bits 31:16 of the channel status word

0x31

Bit(s)

R/W

Default

15:0

RW

0x0

RW

0

RW

to

Default

Description

0x0

if true, turn on Digital output Valid control

0x0

tr
ib

1

ut

R/W

0x40

Bit(s)

R/W

Default

Description

RW

0x0

CRC pop aififo2 enable

RW

0x0

writing to This bit to 1 causes CRC module reset

RW

0x0

unusedRW

0x0

writing to This bit to 1 causes AIFIFO2 soft reset

Description

3
2

D

AIU_AIFIFO2_STATUS

0x41

Bit(s)

R/W

Default

4:0

R

0x0

AIU_AIFIFO2_GBIT

0: output 0, 1: output 1 to the valid bit in audio digital output when bit 1 is trueis

AIU_AIFIFO2_CTRL

1contains Bits 15:0 of the channel status word. Note that bit zero of the channel status
word is sent out first.chstat_r1[15:0] contains Bits 31:16 of the channel status word

0x32

Bit(s)

Descriptione

AIU_958_valid_ctrl

H

AIU_958_chstat_r1

1

l

5:4

Defaultne

Bit(s)

0 adc_lrclk_div

dk
er

11:0

how many Bits left in the first pop register

0x42

Bit(s)

R/W

Default

Description

15:0

R

0x0

The gb data

AIU_AIFIFO2_CLB

0x43

Bit(s)

R/W

Default

Description

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R

0x0

The gb data

Bit(s)

R/W

Default

Description

13:8

RW

3

RW

0x0

CRC pop data from FIFO enable

2

RW

0x0

CRC input register clear

1

RW

0x0

CRC core soft reset

RW

0x0

CRC caculation start

Default

Description

RW

0x0

CRC internal shift register bit select, just for debug purpose

3

RW

0x0

CRC internal shift register data valid, just for debug purpose

2

RW

0x0

CRC input register data valid

RW

0x0

CRC result, 1: CRC not correct, 0: CRC correct

RW

0x0

CRC state, 1: CRC busy, 0: CRC idle

Description

15:0

0x44

0x45

Bit(s)

R/W

7:4

1
0

AIU_CRC_SHIFT_REG

0x46

Bit(s)

R/W

Default

15:0

R

0x0

Bit(s)

R/W

Default

15:0

RW

0x0

ar

CRC internal shift register, read only, for debug purpose

AIU_CRC_CAL_REG1
R/W

Default

15:0

RW

0x0

CRC calculation register high-bit part [31:16]

ut

R/W

Defaulttrib

Bit(s)

DescriptioneBit(s)

0x49

Description

CRC data input register

0x48

AIU_CRC_CAL_REG0

H

0x47

to

AIU_CRC_IREGl

AIU_CRC_STATUS

CRC polynomial equation order, between 1 to 32

ne

0

0x10

dk
er

AIU_CRC_CTRL

Description

CRC calculation register high-bit part [15:0]
CRC polynomial coefficient high-bit part [31:16], read/write
15:0

RW

D

Bit(s)
15:0

0x4a

is

AIU_CRC_POLY_COEF1

0x0

R/W

Default

RW

0x0

AIU_CRC_POLY_COEF0

R/W

Default

15:0

RW

0x0

Bit(s)
3:0

AIU_CRC_BIT_SIZE0
Bit(s)

CRC calculation register high-bit part [15:0]

0x4b

Bit(s)AIU_CRC_BIT_SIZE1

Description

Description

CRC polynomial coefficient low-bit part [15:0]

0x4c
R/W

Default

RW

0x0

Description

CRC frame size, high-bit part [19:16]

0x4d
R/W

Default

Description

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15:0

RW

AIU_CRC_BIT_CNT1

CRC frame size, low-bit part [15:0]

0x0

0x4e

Bit(s)

R/W

Default

3:0

R

0x0

How many Bits have been processed right now in the current frame[19:16]0x4f

Bit(s)

R/W

Default

15:0

R

0x0

R/W

Default

3

RW

0x0

2:0

RW

0x0

AIU_AMCLK_GATE_LO

Start msr clk
The msr period [18:16]

Bit(s)

R/W

Default

15:0

RW

0x0

0x52

Bit(s)

R/W

Default

15:0

R

0x0

H

0x60
R/W

Default

31:0

RW

0x0

RW

R/W

Default

RW

0x0

is

D

0x0

Description

The new read access address from DDR

0x62

AIU_MEM_I2S_MASKS
Bit(s)

Default

tr
ib

R/W

31:0

The start address from DDR

e

0x61

Bit(s)

Descriptionut

AIU_MEM_I2S_RD_PTR

31:0

Description

The msr countBit(s)

Bit(s)

Description

The msr period [15:0]

AIU_AMCLK_MSR

AIU_MEM_I2S_END_PTR

Description

0x51

AIU_MEM_I2S_START_PTR

ne

l

0x50

ar

Bit(s)How many Bits have been processed right now in the current frame[15:0]dk
er

AIU_AMCLK_GATE_HI

Description

to

AIU_CRC_BIT_CNT0

Description

Description

The end address from DDR

0x63

R/W

Default

Description

RW

0x0

IRQ block

15:8

RW

0x0

chan_mem_mask. Each Bit indicates which channels exist in memory

7:0

RW

0x0

chan_rd_mask. Each Bit indicates which channels are READ from memory

31:16

AIU_MEM_I2S_CONTROL
Bit(s)

0x64
R/W

11:10

RW

9

RW

Default

Description

0x0

Select which hardware pointer to use to control the buffer level:00 = parser
01 = audin_fifo0_wrpt
1x = audin_fifo1_wrpt

0x0

Use level control: 1 = use buffer level control

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R/W

Default

R

0x0

Read Only. This bit is 1 when there is data available for reading

0x0

Read only. This bit will be high when we're fetching data from the DDR memory.To reset
this module, set cntl_enable = 0, and then wait for busy = 0.

0x0

cntl_mode_16bit:Set to 1 for 16 bit storage format in DDR

RW

0x0

endian2RW0x0

cntl_empty_en Set to 1 to enable reading data from the FIFO

1

RW

0x0

cntl_fill_en Set to 1 to enable reading data from DDR memory

0

RW

0x0

cntl_init: After setting the read pointers, sizes, channel masks and read masks, set Thisbit to 1 and then to 0

7

R

6
5:3

AIU_MEM_IEC958_START_PTR

0x65

Bit(s)

R/W

Default

31:0

RW

0x0

The start address from DDR

0x66

Bit(s)

R/W

Default

31:0

RW

0x0

The read access address from DDR

0x67

Bit(s)

R/W

Default

31:0

RW

0x0

Default

Description

RW

0x0

RW

0x0

AIU_MEM_IEC958_CONTROL

0x69
R/W
RW

30

RW

10
9
8
7

D

11

A_urgent

0x0

ch_always_8
rdata_rd_base_begin ( used for select from different channel )0x0

reserved

RW

0x0

cntl_sim_en

RW

0x0

cntl_use_level

R

0x0

Read only. This bit will be set to 1 when there is data in the FIFO to process

R

0x0

Read only. This bit will be high when we're fetching data from the DDR memory

0x0

cntl_endian_jic Just in case endian. last minute byte swap of the data out of the FIFO to
the rest of the IEC958 logic

0x0

Set This bit to 1 to tell the IEC958 FIFO to read and process data linearly for raw data.

0x0

cntl_mode_16bit:Set to 1 for 16 bit storage format in DDR. Only valid when mode_raw =0
cntl_rd_ddr Set This bit to read if you want AIU_MEM_IEC958_RD_PTR and
AIU_MEM_IEC958_RD_PTR_HIGH to refer to the pointer into DDR memory.Otherwise, thecurr_ptr,registers refer to the byte address of the dataat the output of the FIFO to the rest of the IEC958 logic

is

13
12

Description

0x0
0x0

RW

23:14

chan_rd_mask. Each Bit indicates which channels are READ from memory

Defaulttrib

31

chan_mem_mask. Each Bit indicates which channels exist in memory

e

7:0

R/W

ut

15:8

27:24

ar

0x68

Bit(s)

Bit(s)The end address from DDR

to

AIU_MEM_IEC958_MASKS

Description

H

AIU_MEM_IEC958_END_PTR

Description

dker

AIU_MEM_IEC958_RD_PTR

Descriptionl8

DescriptionneBit(s)

RW
RW
RW

0x0
6

RW

5:3

RW

2

RW

1

RW

0x0

endian0x0

cntl_empty_en Set to 1 to enable reading the DDR memory FIFO and filling the pipeline
to get-bit Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init

0x0

cntl_fill_en Set to 1 to enable reading data from DDR memory

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R/W

Default

RW

0x0

0

AIU_MEM_AIFIFO2_START_PTR

cntl_init

0x6a

Bit(s)

R/W

Default

31:0

RW

0x0

AIU_MEM_AIFIFO2_CURR_PTR

0x6b

R/W

Default

31:0

R

0x0

The current address from DDR

Default

RW

0x0

AIU_MEM_AIFIFO2_BYTES_AVAILThe end address from DDR

0x6d

Bit(s)

R/W

Default

31:0

R

0x0

Available bytes in afifo2.

0x6e

RW

9

RW

8

RW

7

RW

Description

0x0

unused0x0

use_level
Set This bit to 1 to enable filling of the FIFO controlled by the buffer level
control. If This bit is 0, then use Bit[1] to control the enabling of filling

0x0

Data Ready.

0x0

fill busy
This bit will be high when we're fetching data from the DDR memory.To reset
this module, set cntl_enable = 0, and then wait for busy = 0.
cntl_endian_jic Just in case endian. last minute byte swap of the data out of the FIFO to
get bit

0x0

6

0x0

5：3

0x0

RW

1

RW

unusedRW

cntl_fill_en Set to 1 to enable reading data from DDR memory

0x0

cntl_init: After setting the read pointers, sizes, channel masks and read masks, set Thisbit to 1 and then to 0

Default

RW

0x0

D

R/W

AIU_MEM_AIFIFO2_MAN_RP

Description

Manual write ptr.

0x70

Bit(s)

R/W

Default

31:0

RW

0x0

AIU_MEM_AIFIFO2_LEVEL

Description

Manual read ptr.

0x71

Bit(s)

R/W

Default

31:0

RW

0x0

AIU_MEM_AIFIFO2_BUF_CNTL
Bit(s)

cntl_empty_en Set to 1 to enable reading the DDR memory FIFO and filling the pipeline
to get-bit
Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init

0x6f

is

AIU_MEM_AIFIFO2_MAN_WP

endian

0x0

tr
ib

RW

This bit is set when data can be popped

ut

0x0

2

H

10

Default

to

R/W

15:11

31:0

Descriptione

AIU_MEM_AIFIFO2_CONTROL

Description

ne

R/W

31:0

l

0x6c

Bit(s)

Bit(s)

Description

dker

AIU_MEM_AIFIFO2_END_PTR

0

Description

The start address from DDR

Bit(s)

Bit(s)

DescriptionarBit(s)R/W

Description

Level = reg[31:0] – level_hold

0x72
Default

Description

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1
0

RW

0x0

Set to 1 for manual write pointer mode

RW

0x0

Set high then low after everything has been initialized

AIU_MEM_I2S_MAN_WP

0x73

Bit(s)

R/W

Default

31:0

RW

0x0

AIU_MEM_I2S_MAN_RP

Description

Manual write ptr.

0x74

Bit(s)

R/W

Default

31:0

RW

0x0

Manual read ptr.

Bit(s)

R/W

Default

31:0

RW

0x0

Description

Level = reg[31:0] – level_hold

0x76
R/W

Default

1

RW

0x0

mode 0 = parser (or audin_fifo0 or audin_fifo1), 1 for manual write pointer

0

RW

0x0

initialize Set high then low after everything has been initialized

AIU_MEM_I2S_BUF_WRAP_COUNT

Description

0x77

Bit(s)

R/W

Default

31:0

RW

0x0

DescriptionarBit(s)dker

AIU_MEM_I2S_BUF_CNTL

l

0x75

ne

AIU_MEM_I2S_LEVEL

Description

H

The wrap count

0x78
R/W

Default

29:24

RW

0x0

to

AIU_MEM_I2S_MEM_CTL

21:16

RW

0x0

A_id

RW

0x0

Bit(s)

R/W

29:24
21:16

Default

Description

RW

0x0

A_brst_num

RW

0x0

A_id

RW

0x0

level_hold

is

15:0

31:0

D

AIU_MEM_IEC958_WRAP_COUNT
Bit(s)

level_hold

0x79

tr
ib

AIU_MEM_IEC958_MEM_CTL

A_brst_num

e

15:0

DescriptionutBit(s)

0x7a

R/W

Default

RW

0x0

AIU_MEM_IEC958_IRQ_LEVEL

Description

The wrap count

0x7b

Bit(s)

R/W

Default

Description

31:0

RW

0x0

The irq level

AIU_MEM_IEC958_MAN_WP

0x7c

Bit(s)

R/W

Default

31:0

RW

0x0

AIU_MEM_IEC958_MAN_RP

Description

Manual write ptr.

0x7d

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Bit(s)

R/W

Default

31:0

RW

0x0

AIU_MEM_IEC958_LEVEL

Description

Manual read ptr.

0x7e

Bit(s)

R/W

Default

31:0

RW

0x0

AIU_MEM_IEC958_BUF_CNTL

Description

Level = reg[31:0] – level_hold

0x7f
R/W

Default

Description

29:24

RW

0x0

A_brst_num

21:16

RW

0x0

A_id

15:0

RW

0x0

level_hold

AIU_AIFIFO_CTRL

0x80

Bit(s)

R/W

Default

Description
CRC pop aififo enable

dk
er

ne

l

Bit(s)

RW

2

RW

0x0

writing to This bit to 1 causes CRC module reset

1

RW

0x0

enable aififo

0

RW

0x0

writing to This bit to 1 causes aififo soft reset

AIFIFO_STATUS

0x81

H

ar

3

0x0

Same fucntion as the AIGBIT of AIFIFO in CDROM module write to this register how many Bits wanna pop, and reading this register gets thecorresponding Bits data
Default
0x0

12

RW

0x0

11:5

RW

0x0

RW

0x0

4:0

0x82

tr
ib

AIFIFO_GBIT

Description

aififo request to dcu status
dcu select status
aififo word counter number
how many Bits left in the first pop register

ut

RW

to

R/W

13

e

Bit(s)

Same function as the AICLB of AIFIFO in CDROM module return the leading zeros by reading this registers
Bit(s)

Bit(s)
15:0

D

AIFIFO_CLB

R/W

Default

DescriptionR

0x0

The gb data

R/W

Default

DescriptionR

0x0

The gb data

Description

is

15:0

0x83

MEM_AIFIFO_START_PTR 0x84
Bit(s)

R/W

Default

31:0

RW

0x0

The start address from DDR

MEM_AIFIFO_CURR_PTR 0x85
Bit(s)

R/W

Default

31:0

RW

0x0

Description

The current address from DDR

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MEM_AIFIFO_END_PTR

0X86

Bit(s)

R/W

Default

31:0

RW

0x0

Description

The start address from DDR

MEM_AIFIFO_BYTES_AVAIL 0x87
Bit(s)

R/W

Default

31:0

RW

0x0

The available bytes.

0x88

R/W

15:11

Default

Description

0x0

unused0x0

use_level
Set This bit to 1 to enable filling of the FIFO controlled by the buffer level
control. If This bit is 0, then use Bit[1] to control the enabling of fillingdkerBit(s)nel

AIU_MEM_AIFIFO_CONTROL

Description

10

RW

9

RW

0x0

Data Ready.

8

RW

0x0

fill busy

7

RW

0x0

cntl_endian_jic Just in case endian. last minute byte swap of the data out of the FIFO to
get bit

6

RW

0x0

unusedRW

0x0

endian0x0

cntl_empty_en Set to 1 to enable reading the DDR memory FIFO and filling the pipeline
to get-bit
cntl_fill_en Set to 1 to enable reading data from DDR memory

1

RW

0x0

RW

0x0

0

AIU_MEM_AIFIFO_MAN_WP

0x89
R/W

31:0

RW

Default

31:0

D

Bit(s)

R/W

Default

RW

0x0

1
0

Description

Manual read ptr.

0x8b

R/W

Default

RW

0x0

AIU_MEM_AIFIFO_BUF_CNTL
Bit(s)

ar

0x8a

is

AIU_MEM_AIFIFO_LEVELManual write ptr.

tr
ib

31:0

Description

0x0

AIU_MEM_AIFIFO_MAN_RP
Bit(s)

cntl_initut

Bit(s)

H

RW

to

2

e

5：3

This bit is set when data can be popped

This bit will be high when we're fetching data from the DDR memory

Description

Level = reg[31:0] – level_hold

0x8c
R/W

Default

Description

RW

0x0

manual mode

RW

0x0

Init

AIU_MEM_AIFIFO_BUF_WRAP_COUNT

Set high then low after everything has been initialized

0x8d

Bit(s)

R/W

Default

31:0

R

0x0

AIU_MEM_AIFIFO2_BUF_WRAP_COUNT

Set to 1 for manual write pointer mode

Description

Fifo wrap count
0x8e

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Bit(s)

R/W

Default

31:0

R

0x0

AIU_MEM_AIFIFO_MEM_CTL

Description

Fifo2 wrap countox8f

Bit(s)

R/W

Default

Description

29:24

RW

0x0

A_brst_num

21:16

RW

0x0

A_id

15:0

RW

0x0

level_hold

AIFIFO_TIME_STAMP_CNTL

0x90

Bit(s)

R/W

Default

Description
drop_bytes

RW

15:14

RW

0x0

drop_status (Read-Only)

RW

0x0

sync_match_position (Read-Only)

0x0

reserved

RW

0x0

TIME_STAMP_NUMBER, 0-32Bits, 1-64Bits, 2-96Bits, 3-128Bits

RW

0x0

stamp_soft_reset

2

RW

0x0

TIME_STAMP_length_enable

1

RW

0x0

TIME_STAMP_sync64_enable

0

RW

3

0x0

0x91
R/W

Default

31:0

RW

0x0

AIFIFO_TIME_STAMP_SYNC_1

TIME_STAMP_SYNC_CODE_0

0x92

Bit(s)

R/W

Default

31:0

RW

0x0

R/W

31:0

RW

AIFIFO_TIME_STAMP_1
31:0

R/W

Default

RW

0x0

31:0

D

AIFIFO_TIME_STAMP_2
Bit(s)

0x0

Description
TIME_STAMP_0

0x94

is

Bit(s)

Defaulttrib

Bit(s)

TIME_STAMP_SYNC_CODE_1

e

0x93

Description

ut

AIFIFO_TIME_STAMP_0

DescriptionH

Bit(s)

to

AIFIFO_TIME_STAMP_SYNC_0

TIME_STAMP_enable

ne

5:4

dk
er

11:6

ar

13:12

l

31:16

0x0

TIME_STAMP_1

0x95

R/W

Default

RW

0x0

AIFIFO_TIME_STAMP_3

Description

Description
TIME_STAMP_2

0x96

Bit(s)

R/W

Default

31:0

RW

0x0

AIFIFO_TIME_STAMP_LENGTH

Description
TIME_STAMP_3

0x97

Bit(s)

R/W

Default

31:0

RW

0x0

Description
TIME_STAMP_LENGTH

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AIFIFO2_TIME_STAMP_CNTL

Description

0x0

drop_bytes

15：14

RW

0x0

drop_status (Read-Only)

13：12

RW

0x0

sync_match_position (Read-Only)

0x0

reserved

RW

0x0

TIME_STAMP_NUMBER, 0-32Bits, 1-64Bits, 2-96Bits, 3-128Bits

3

RW

0x0

stamp_soft_reset

2

RW

0x0

TIME_STAMP_length_enable

1

RW

0x0

TIME_STAMP_sync64_enable

0

RW

0x0

TIME_STAMP_enable

11：6

AIFIFO2_TIME_STAMP_SYNC_0

0x99

Bit(s)

R/W

Default

31:0

RW

0x0

AIFIFO2_TIME_STAMP_SYNC_1

TIME_STAMP_SYNC_CODE_0

0x9a

Bit(s)

R/W

Default

31:0

RW

0x0

AIFIFO2_TIME_STAMP_0

0x9b
R/W

Default

31：0

RW

0x0

H

TIME_STAMP_0

0x9c

Bit(s)

R/W

Default

31：0

RW

0x0

31：0

RW

Default
0x0

tr
ib

R/W

Default

RW

0x0

is

R/W

R/W

Default

RW

0x0

D

31：0

IEC958_TIME_STAMP_CNTL
Bit(s)

Description
TIME_STAMP_2

0x9e

AIFIFO2_TIME_STAMP_LENGTH
Bit(s)

TIME_STAMP_1

e

0x9d

Bit(s)

Description

ut

AIFIFO2_TIME_STAMP_2

31:0

Description

to

AIFIFO2_TIME_STAMP_1

Bit(s)

Description

TIME_STAMP_SYNC_CODE_1

Bit(s)

AIFIFO2_TIME_STAMP_3

Description

dk
er

5：4

l

Default

RW

ne

R/W

31：16

ar

Bit(s)

0x98

Description
TIME_STAMP_3

0x9f
Description
TIME_STAMP_LENGTH

0xa0
R/W

Default

Description
drop_bytes

31：16

RW

0x0

15：14

RW

0x0

drop_status (Read-Only)

RW

0x0

sync_match_position (Read-Only)

11：6

0x0

reserved

5：4

RW

0x0

TIME_STAMP_NUMBER, 0-32Bits, 1-64Bits, 2-96Bits, 3-128Bits

3

RW

0x0

stamp_soft_reset

RW

0x0

TIME_STAMP_length_enable

13：12

2

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1

RW

0x0

TIME_STAMP_sync64_enable

0

RW

0x0

TIME_STAMP_enable

IEC958_TIME_STAMP_SYNC_0

0xa1

Bit(s)

R/W

Default

31:0

RW

0x0

IEC958_TIME_STAMP_SYNC_1

TIME_STAMP_SYNC_CODE_0

0xa2

Bit(s)

R/W

Default

31:0

RW

0x0

TIME_STAMP_SYNC_CODE_1

R/W

Default

31:0

RW

0x0

Description
TIME_STAMP_0

0xa4

Bit(s)

R/W

Default

31:0

RW

0x0

Description
TIME_STAMP_1

0xa5

Bit(s)

R/W

Default

31:0

RW

0x0

TIME_STAMP_2

R/W

Default

31:0

RW

0x0

IEC958_TIME_STAMP_LENGTH

H

0xa6

Bit(s)

Description

TIME_STAMP_3

0xa7

R/W

Default

31:0

RW

0x0

DescriptioneBit(s)

toIEC958_TIME_STAMP_3

Description

ut

TIME_STAMP_LENGTH

0xa8

Default

Description

RW

0x0

A_brst_num

RW

0x0

A_id

RW

0x0

level_hold

is

tr
ib

AIU_MEM_AIFIFO2_MEM_CTL
R/W

0xa9

29:24
21:16
15:0

AIU_I2S_CBUS_DDR_CNTL

Dar

IEC958_TIME_STAMP_2

dk
er

IEC958_TIME_STAMP_1

l

0xa3

Bit(s)

Bit(s)

DescriptionneIEC958_TIME_STAMP_0

Bit(s)

Description

Default

Description

0x0

unused

RW

0x0

A_req

24

RW

0x0

data_req If This bit is 1, then (a_req_cnt != 'h0)

23：16

RW

0x0

a_req_cnt This value corresponds to the number of32-bit words

0x0

unusedRW

0x0

Set This bit to mux in the cbus_ddr_interface

5

RW

0x0

Set This bit to allow back to back A_req's to be serviced

4

RW

0x0

Set This bit to generate an IRQ on the first A_req

3：1

RW

0x0

Endian0

RW0x0

Set This bit enable the cbus_ddr_interface

31:26
25

R/W

15:7
6

level

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AIU_I2S_CBUS_DDR_WDATA

0xaa

Bit(s)

R/W

Default

31:0

RW

0x0

AIU_I2S_CBUS_DDR_ADDR

Description

32-bit data to write to the cbus_ddr interface

0xab

Bit(s)

R/W

Default

31:0

RW

0x0

Description

D

is

tr
ib

ut

e

to

H

ar

dk
er

ne

l

First address associated with the first request by the I2S_fast() to read
DDR data

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S905 Datasheet

Revision 1.1.4

Section VI Memory INTERFACE
This part describes S905’s memory interfaces from the following aspects:

DDR

NAND

EMMC/SDIO/SD

SPICC

SPIFC

32. DDRnel32.1 Overview

to

H

ar

dk
er

DDR memory interface consists of the 2 parts: DDR memory controller (DMC) and DDR PHY controller. The main features ofthis module are listed below:
 Electronic fence protected Security system.
 Optimized DDR read reordering to improve DDR efficiency.
 Dual channel 16Bits shared AC mode and signal channel 32Bits mode to support more DDR size
combination.
 VPU ports changed to AXI like 128Bits interface. READ/write bus are separated.
 Dedicated GE2D port for maximum 2D graphic bandwidth.
 Device port directly to AXI arbitration.. No canvas address translation latency.
 PCTL moved inside DMC to optimize DDR command generation.
 Improved DDR Frequency update 933Mhz(DDR3/LPDDR3 1866MBPS).

e

Below is the diagram of DDR modul, in which SPI is the Serial Peripherial Interface for transport, AXI3 and AXI3-like are theinterface (ports) between DMC and SPI, signals will go through the Arbiter to the DDR Commend Generator to generate DDR
commend signal, and through DDR Phy Controler to execute read or write to DDR.

tr
ib

ut

Fig VI.31.1 Diagram of DDR Interface

DMC
To DDR

Arbiter
AXI3 LikeSPI

DDR Command
Generator

To DDR

AXI3

D

is

SPI

To DDR

DDR
PHY
Con.

To DDR
To DDR
To DDR…
To DDR

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S905 Datasheet

Revision 1.1.4

32.2 Register Description
DMC Register spec.
DMC unsecure register. Base address 0xc8838000. Each register takes 4 byte address.
Each register’s final address = 0xc8838000 + offset * 4.

Default

Description

31~16

R/W

0

Not used.

15

R/W

0

enable dmc request of port15. GE2D interface. Async interface.

14

R/W

0

enable dmc request of port 14. DOS HCODEC interface Sync interface.

13

R/W

0

enable dmc request of port 13. DOS VDEC interface Sync interface..

12

R/W

0

enable dmc request of port 12. VPU write interface 1 Sync interface.

11

R/W

0

enable dmc request of port 11. VPU write interface 0 Sync interface.

10

R/W

0

enable dmc request of port 10. VPU read interface 2. Sync interface.

9

R/W

0

enable dmc request of port 9. VPU read interface 1. Sync interface

8

R/W

0

enable dmc request of port 8. VPU read interface 0. Sync interface.

7

R/W

0

enable dmc request of port 7. DEVICE. Async interface.

6

R/W

0

enable dmc request of port 6. not used.

5

R/W

0

enable dmc request of port 5. not used.

4

R/W

0

enable dmc request of port 4. HEVC sync interface.

3

R/W

0

enable dmc request of port 3. HDCP/HDMI 32Bits. Async interface..

2

R/W

0

enable dmc request of port 2. Mali 1 Sync interface..

1

R/W

0

enable dmc request of port 1. Mali 0. Sync interface.

0

R/W

0

enable dmc request of port 0. CPU/A53 Sync interface.

0x01

R/W
R/W

Default
0

Description
Not used.

28

R/W

0

DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.

27

R/W

0

DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.

26

R/W

0

DMC register modle soft reset_n.

25

R/W

0

24

R/W

0

23~20

R/W

0

19

R/W

0

18

R/W

0

DDR channel 1 PCTL module n_clk domain soft reset_n. 0 : reset. 1 : normal working mode.

17

R/W

0

DDR channel 0 PCTL module PCLK domain soft reset_n. 0 : reset. 1 : normal working mode.

16

0 : reset. 1 : normal working mode.

tr
ib

ut

e

Bit(s)
31~29

D

DMC_SOFT_RST

to

H

ar

dk
er

R/W

l

0x0

Bit(s)

ne

DMC_REQ_CTRL

DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode..
DMC command buffers and command generation modules soft reset. 0 = reset. 1:
Not used.

is

DDR channel 1 PCTL module PCLK domain soft reset_n. 0 : reset. 1 : normal working mode.

R/W

0

DDR channel 0 PCTL module n_clk domain soft reset_n. 0 : reset. 1 : normal working mode.

15:0

R/W

0

16 input chan inteface n_clk domain reset control. if the channel is asynchronous FIFO interface, then both side of
the clocks must be turn off before reset this module. If the channel is synchronous interface, you can reset it any time.

15

R/W

0

n_clk domain port 15 soft reset_n control. 0 : reset. 1: normal working mode.

14

R/W

0

n_clk domain port 14 soft reset_n control. 0 : reset. 1: normal working mode.

13

R/W

0

n_clk domain port 13 soft reset_n control. 0 : reset. 1: normal working mode.

12

R/W

0

n_clk domain port 12 soft reset_n control. 0 : reset. 1: normal working mode.

11

R/W

0

n_clk domain port 11 soft reset_n control. 0 : reset. 1: normal working mode.

10

R/W

0

n_clk domain port 10 soft reset_n control. 0 : reset. 1: normal working mode.

9

R/W

0

n_clk domain port 9 soft reset_n control. 0 : reset. 1: normal working mode.

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R/W
R/W

Default
0

Description
n_clk domain port 8 soft reset_n control. 0 : reset. 1: normal working mode.

7

R/W

0

n_clk domain port 7 soft reset_n control. 0 : reset. 1: normal working mode.

6

R/W

0

n_clk domain port 6 soft reset_n control. 0 : reset. 1: normal working mode.

5

R/W

0

n_clk domain port 5 soft reset_n control. 0 : reset. 1: normal working mode.

4

R/W

0

n_clk domain port 4 soft reset_n control. 0 : reset. 1: normal working mode.

3

R/W

0

n_clk domain port 3 soft reset_n control. 0 : reset. 1: normal working mode.

2

R/W

0

n_clk domain port 2 soft reset_n control. 0 : reset. 1: normal working mode.

1

R/W

0

n_clk domain port 1 soft reset_n control. 0 : reset. 1: normal working mode.

0

R/W

0

n_clk domain port 0 soft reset_n control. 0 : reset. 1: normal working mode.

Bit(s)
31~16

R/W
R/W

Default
0

Description
Not used.

15~0

R/W

0

if the input port interface is asynchronous interface, then the related bit is for the main clock domain reset control. if
the interface is synchronouse interface, This bit is not used.

14~8

R/W

0

Not used

7

R/W

0

input port 7 main clock domain soft reset_n.

6~4

R/W

0

Not used

3

R/W

0

input chan 3 main clock domain soft reset_n.

2~-

R/W

0

Not used

ne

0x02

H

ar

dk
er

DMC_SOFT_RST1l

Bit(s)
8

DMC_SOFT_STS1

0x04

R/W
R/W

Default
0

Description
Not used.

15~0

R/W

0

Read only. the DMC_SOFT_RST1 signal in n_clk domain. the purpose of this register is if the n_clk is too fast or too slow
related to APB clock, we can read this register to make sure another clock domain reset is done.

R/W
R

Default
0x000a001

Bit(s)
31~6

R/W
R/W

Default
0

Description
Not used.

5:4

R/W

0

DDR channel1 read/write data path SRAM in power down mode. 2’b11: power down. 2’b00 working mode.

3:2

0x11

is

DMC_RAM_PD

1:0

Description
Read only.

tribBit(s)
31~0

0x05

D

DMC_VERSION

ut

e

to

Bit(s)
31~16

R/W

0

DDR channel0 read/write data path SRAM in power down mode. 2’b11: power down. 2’b00 working mode

R/W

0

CANVAS LUT SRAM in power down mode control. 2’b11: power down. 2’b00 working mode.

Default
0

Description
low 32 Bits of canvas data which need to be configured to canvas LUT memory

DMC_CAV_LUT_DATAL
Bit(s)
31~0

R/W
R/W

0x12

DMC_CAV_LUT_DATAH

0x13

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R/W
R/W

Default
0

Description//high 32Bits of cavnas data which need to be configured to canvas memory.
//64Bits CANVAS look up table//bit 61:58 Endian control.
//bit 61: 1 : switch 2 64Bits data inside 128Bits boundary. 0 : no change.
//bit 60: 1 : switch 2 32Bits data inside 64Bits data boundary. 0 : no change.
//bit 59: 1 : switch 2 16Bits data inside 32Bits data boundary. 0 : no change.
//bit 58: 1 : switch 2 8Bits data inside 16Bits data bournday. 0 : no change.
//bit 57:56. Canvas block mode. 2 : 64x32, 1: 32x32; 0 : linear mode.
//bit 55: canvas Y direction wrap control. 1: wrap back in y. 0: not wrap back.
//bit 54: canvas X direction wrap control. 1: wrap back in X. 0: not wrap back.
//bit 53:41. canvas Hight.
//bit 40:29. canvas Width, unit: 8bytes. must in 32bytes boundary. that means last 2 Bits must be 0.
//bit 28:0. cavnas start address. unit. 8 bytes. must be in 32bytes boundary. that means last 2Bits must
be 0.

H

ar

dk
er

ne

l

Bit(s)
31~0

Revision 1.1.4

DC_CAV_LUT_ADDR

0x14

R/W
R/W

Default
0

Description
Not used.

9~8

R/W

0

write 2'b10. it would trigger a canvas write operation. the data saved in DC_CAV_LUT_DATAL and
DC_CAV_LUT_DATAH will be written to LUT table, the LUT table index is the bit 7:0 of this regsiter.
write 2'b01, it would trigger a read operation. after the read finished, the LUT table value in index[7:0]
would read back to DC_CAV_LUT_RDATAL and DC_CAV_LUT_RDATAH register.

7~0

R/W

0

256 canvas look up table index addresstrib

DC_CAV_LUT_RDATAL
R/W
R/W

Default
0is

Bit(s)
31~0

ut

e

to

Bit(s)
31~10

0x15

Description
CBUS low 32 Bits canvas read back data from LUT.

DC_CAV_LUT_RDATAH
R/W
R/W

D

Bit(s)
31~0

Default
00x16
Description
CBUS high 32 Bits canvas read back data from LUT.

DMC_2ARB_CTRL

0x20

Bit(s)
31~12

R/W
R/W

Default
0

Description
Not used

11:6

R/W

0

the final arbitration. weight for all AXI bus(ports 0~7).

5:0

R/W

0

the final arbitration. weight for all AMbus(ports 8~15).

R/W
R/W

Default
0

Description
Not used

DMC_REFR_CTRL1
Bit(s)
31~28

0x23

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Revision 1.1.4

Bit(s)
26~24

R/W
R/W

Default
0

Description
theres 4 depath FIFO to same the REFR request. use this regsiter to set when FIFO level to set the refreshcommand to be highest priority.

23:8

R/W

0

Not used.

7

R/W

0

dmc to control auto_refresh enable

6~4

R/W

0

refresh number per refresh cycle.

3

R/W

0

pvt enable

2

R/W

0

zqc enable

1

R/W

0

ddr1 auto refresh enable.

0

R/W

0

ddr0 auto refresh enable.

Bit(s)
31~24

R/W
R/W

Default
0

Description
tZQCI

23~16

R/W

0

tPVTI

15:8

R/W

0

tREFI

7:0

R/W

0

t100nsBit(s)31

R/W
R/W

Default
0

Description
qos_mon_en. write 1 to trigger the enable. polling This bit 0, means finished. or use interrupt to checkfinish.

30

R/W

0

qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.

29~21

R/W

0

Not used.

20

R/W

0

qos_mon_trig_sel. 1 = vsync. 0 = timer.

19~16

R/W

0

qos monitor port select. select one at one time only.

15:0

R/W

0

16 SubID ID[9:6] selections for selected port.

0x24

dk
er

ne

l

DMC_REFR_CTRL2

0x26

DMC_MON_ALL_REQ_CNT
R/W
R

H

to

Default
00x28

Description
at the test period, the whole MMC request high time.

isBit(s)
31~0

Description
qos_mon_clk_timer. How long to measure the bandwidth.

utDefault
0

0x27

tr
ib

R/W
R/W

e

DMC_MON_CTRL2
Bit(s)
31~0

ar

DMC_MON_CTRL2

D

DMC_MON_ALL_GRANT _CNT
Bit(s)
31~0

R/W
R

Default
00x29
Description
at the test period, the whole MMC data grant cycles.

DMC_MON_ONE _GRANT _CNT
Bit(s)
31~0

R/W
read

Default
00x2a
Description
at the test period, the granted data cycles for the selected port and subIDs.

DMC_CLKG_CTRL0
Bit(s)
31~30

0x30
R/W
R/W

Default
0

Description
Not used.

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Default
0

Description
enable auto clock gating for write rsp generation.

28

R/W

0

enable auto clock gating for read rsp generation.

27

R/W

0

enable auto clock gating for ddr1 read back data buffer.

26

R/W

0

enable auto clock gating for ddr0 read back data buffer.

25

R/W

0

enable auto clock gating for ddr1 command filter.

24

R/W

0

enable auto clock gating for ddr0 command filter.

23

R/W

0

enable auto clock gating for ddr1 write reorder buffer.

22

R/W

0

enable auto clock gating for ddr0 write reorder buffer.

21

R/W

0

enable auto clock gating for ddr1 write data buffer.

20

R/W

0

enable auto clock gating for ddr0 write data buffer.

19

R/W

0

enable auto clock gating for ddr1 read reorder buffer.

18

R/W

0

enable auto clock gating for ddr0 read reorder buffer.

17

R/W

0

enable auto clock gating for read canvas.

16

R/W

0

enable auto clock gating for write canvas.

15

R/W

0

enable auto clock gating for port 15.

14

R/W

0

enable auto clock gating for port 14

13

R/W

0

enable auto clock gating for port 13.

12

R/W

0

enable auto clock gating for port 12.

11

R/W

0

enable auto clock gating for port 11.

10

R/W

0

enable auto clock gating for port 10.

9

R/W

0

enable auto clock gating for port 9.

8

R/W

0

enable auto clock gating for port 8.

7

R/W

0

enable auto clock gating for port 7.

6

R/W

0

enable auto clock gating for port 6.

5

R/W

0

enable auto clock gating for port 5.

4

R/W

0

enable auto clock gating for port 4.

3

R/W

0

enable auto clock gating for port 3.

2

R/W

0

enable auto clock gating for port 2.

1

R/W

0

enable auto clock gating for port 1.

0

R/W

0

enable auto clock gating for port 0.

ar
H

to

e

ut

tr
ib

is

DMC_CLKG_CTRL1

ne

R/W
R/W

dk
er

Bit(s)
29l

S905 Datasheet

0x31

R/W
R/W

Default
0

Description
Not used.

29

R/W

Force to disable the clock of for write rsp generation.

0

28

D

Bit(s)
31~30

R/W

0

Force to disable the clock of read rsp generation.

27

R/W

0

Force to disable the clock of ddr1 read back data buffer.

26

R/W

0

Force to disable the clock of ddr0 read back data buffer.

25

R/W

0

Force to disable the clock of ddr1 command filter.

24

R/W

0

Force to disable the clock of ddr0 command filter.

23

R/W

0

Force to disable the clock of ddr1 write reorder buffer.

22

R/W

0

Force to disable the clock of ddr0 write reorder buffer.

21

R/W

0

Force to disable the clock of ddr1 write data buffer.

20

R/W

0

Force to disable the clock of ddr0 write data buffer.

19

R/W

0

Force to disable the clock of ddr1 read reorder buffer.

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R/W
R/W

Default
0

Description
Force to disable the clock of ddr0 read reorder buffer.

17

R/W

0

Force to disable the clock of read canvas.

16

R/W

0

Force to disable the clock of write canvas.

15

R/W

0

Force to disable the clock of port 15.

14

R/W

0

Force to disable the clock of port 14

13

R/W

0

Force to disable the clock of port 13.

12

R/W

0

Force to disable the clock of port 12.

11

R/W

0

Force to disable the clock of port 11.

10

R/W

0

Force to disable the clock of port 10.

9

R/W

0

Force to disable the clock of port 9.

8

R/W

0

Force to disable the clock of port 8.

7

R/W

0

Force to disable the clock of port 7.

6

R/W

0

Force to disable the clock of port 6.

5

R/W

0

Force to disable the clock of port 5.

4

R/W

0

Force to disable the clock of port 4.

3

R/W

0

Force to disable the clock of port 3.

2

R/W

0

Force to disable the clock of port 2.

1

R/W

0

Force to disable the clock of port 1.

0

R/W

0

Force to disable the clock of port 0.

ar

dk
er

ne

l

Bit(s)
18

0x32

H

DMC_CHAN_STS
R/W
R/W

Default
0

Description
Not used.

19

R

0

ddr0 write data buffer idle. 1 : idle 0: busy.

18

R

0

ddr0 write data buffer idle. 1 : idle 0: busy.

17

R

0

ddr1 wbuf idle.

1 : idle 0: busy.

16

R

0

ddr0 wbuf idle.

1 : idle 0: busy.

15~8

R

0

AMBUS ports idle.

7~0

R

0

AXI ports idle.

Bit(s)
31~9

R/W
R/W

Default
0

Description
Not used.

8

R/W

0

Manual control for hcodec n_clk. 1: enable clock. 0 : disable clock.

7

R/W

0

Manual control for hevc n_clk. 1: enable clock. 0 : disable clock.

6

R/W

0

Manual control for hdcp n_clk. 1: enable clock. 0 : disable clock..

R/W

0

Manual control for DEVICE n_clk 1: enable clock. 0 : disable clock.

4

D

5

e

ut

1 : idle 0: busy.

1 : idle 0: busy.

tr
ib

is

DMC_N_CLK_CTRL

toBit(s)
31~20

0x33

R/W

0

Manual control for ge2d n_clk. 1: enable clock. 0 : disable clock.

3

R/W

0

Manual control for Mali n_clk. 1: enable clock. 0 : disable clock.

2

R/W

0

Manual control for VPU n_clk. 1: enable clock. 0 : disable clock.

1

R/W

0

Manual control for VDEC n_clk. 1: enable clock. 0 : disable clock.

0

R/W

0

Manual control for CPU n_clk. 1: enable clock. 0 : disable clock.

DMC_CMD_FILTER_CTRL1

0x40

Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29~20

R/W

0x1f

nugt read buf full access waiting limit

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Bit(s)
19~10

R/W
R/W

Default
0x1f

Description
ugt read access waiting limit.

9~0

R/W

0x2f

nugt read access waiting limit

DMC_CMD_FILTER_CTRL2

0x41

Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29~20

R/W

0x0f

ugt read buf full access waiting limit

19~10

R/W

0x3f

nugt write access pending waiting limit

9~0

R/W

0x7f

ugt write access pending waiting limit.

0x42
Description
force wbuf empty.

30~26

R/W

24

wbuf high level number

25~21

R/W

16

wbuf mid level number

20~16

R/W

8

wbuf low level number

15

RW

0

Not used.

14~10

R/W

20

rbuf high level number

9~5

R/W

12

rbuf middle level number

4~0

R/W

6

rbuf low level number

neDefault
0

dk
er

R/W
R/W

ar

Bit(s)31l

DMC_CMD_FILTER_CTRL3

H

DMC_CMD_FILTER_CTRL4

0x43

R/W
R/W

Default
8

Description
sugt rbuf pending limit.

23~16

R/W

30

auto precharge timer when bank is idle

15~8

R/W

0

not used.

7~0

R/W

30

rbuf idle timer if there's small number of write buffers pendingetoBit(s)
31~24

R/W
R/W

Default
0x1f

23~16

R/W

0x1f

15~8

R/W

0x0f

7~0

R/W

0x44

Description
Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's
write request pending for write buffer.
Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's
read request pending too long.
Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if
there's still pending read request.
Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if
there's still pending write.

is

tr
ib

Bit(s)
31~24

ut

DMC_CMD_FILTER_CTRL5

D

0x0f

DMC_CMD_BUFFER_CTRL

0x45

Bit(s)
31~26

R/W
R/W

Default
32

Description
total write buffer number.

25~20
19~10

R/W
R/W

24
0x7f

total read buffer number.
ugt age waiting limit. over this age limit, this read buffer would turn to super urgent.

9~0

R/W

0x3ff

nugt age waiting limit. over this age limit, this read buffer would turn to super urgent..

DMC_PCTL_LP_CTRL

0x46

Bit(s)
31~23

R/W
R/W

Default
0

Description
Not used.

22
21

R/W
R/W

0
0

enable DDR chan1 PCTL n_clk auto clock disable feature.
disable DDR chan1 PCTL n_clk.

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Bit(s)
20

R/W
R/W

Default
0

Description
DDR CHAN1 PCTL APB P_clk enable.

18

R/W

0

enable ddr0 PCTL n_clk auto clock disable feature.

17

R/W

0

disable ddr0 PCTL n_clk.

16

R/W

0

ddr0 PCTL APB P_clk enable..

15~8

R/W

0

latency to disable clock after c_active low.

7~0

R/W

0

latency to disable clock after dfi_lp_req && dfi_lp_ack.

DMC_RDDBUF_CTRL

0x47

R/W
R/W

Default
0

Description
Not used.

9~5

R/W

8

read data BUFFER empty number restriction with no data output. when read data buffer empty number
less than this threshold, restrict the dmc_cmd_filter only allow the command with id sequency number =0 to be generated.

4~0

R/W

4

read data BUFFER empty number restriction with data outputing.

0x60

dk
er

DMC_AM0_CHAN_CTRL

nelBit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

29:20
18

R/W
R/W

0xff
0

write request pending cycle number to inc urgent level if not granted.
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

Har

Bit(s)
31~30

DMC_AM0_QOS_INC

0x62

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

e

DMC_AM0_QOS_INCBK

to

Bit(s)
31~10

0x63

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

tr
ib

ut

Bit(s)
31~10

DMC_AM0_QOS_DEC

0x64

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

DisBit(s)
31~10

DMC_AM0_QOS_DECBK

0x65

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AM0_QOS_DIS

0x66

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

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DMC_AM0_QOS_DISBK

0x67

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AM0_QOS_CTRL0

0x68

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

R/W
R/W

Default
0

Description
Not used.

1
0

R/W
R/W

0
0

side bank urgent increase enable.
side bank urgent decrease enable.

ne

0x6a

H

DMC_AM1_CHAN_CTRL

dk
er

0x69

Bit(s)
31~2

ar

DMC_AM0_QOS_CTRL1l

Bit(s)
31~20

R/W
R/W

Default
0

Description
Not used.

29:20
18

R/W
R/W

0xff
0

write request pending cycle number to inc urgent level if not granted.
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

e

ut

tr
ib

DMC_AM1_QOS_INC

toBit(s)
31~30

0x6c

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

isBit(s)
31~10

DMC_AM1_QOS_INCBK

0x6d

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

D

Bit(s)
31~10

DMC_AM1_QOS_DEC

0x6e

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

DMC_AM1_QOS_DECBK
Bit(s)
31~10

R/W
R/W

0x6f
Default
0

Description
Not used.

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Bit(s)
9~0

Revision 1.1.4

R/W
R/W

Default
0

Description
if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AM1_QOS_DIS

0x70

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

DMC_AM1_QOS_DISBK

0x71

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AM1_QOS_CTRL0nelBit(s)
31~10

0x72

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

R/W
R/W

Default
0

Description
Not used.

1
0

R/W
R/W

0
0

side bank urgent increase enable.
side bank urgent decrease enable.

0x73

tr
ib

ut

e

Bit(s)
31~2

DMC_AM2_CHAN_CTRL

ar

H

to

DMC_AM1_QOS_CTRL1dker

Bit(s)
31~20

0x74

R/W
R/W

Default
0

Description
Not used.

29:20
18

R/W
R/W

0xff
0

write request pending cycle number to inc urgent level if not granted.
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

DisBit(s)
31~30

DMC_AM2_QOS_INC

0x76

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

DMC_AM2_QOS_INCBK

0x77

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

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DMC_AM2_QOS_DEC

0x78

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

DMC_AM2_QOS_DECBK

0x79

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AM2_QOS_DIS

0x7a

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

DMC_AM2_QOS_DISBK

0x7b

dk
er

ne

l

Bit(s)
31~10

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

0x7c

ar

DMC_AM2_QOS_CTRL0
R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

to

e

ut

tr
ib

DMC_AM2_QOS_CTRL1

H

Bit(s)
31~20

R/W
R/W

Default
0

Description
Not used.

1
0

R/W
R/W

0
0

side bank urgent increase enable.
side bank urgent decrease enable.

DisBit(s)
31~2

DMC_AM3_CHAN_CTRL

0x7d

0x7e

Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29:20
18

R/W
R/W

0xff
0

write request pending cycle number to inc urgent level if not granted.
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

DMC_AM3_QOS_INC

0x80

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S905 Datasheet

Revision 1.1.4

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

DMC_AM3_QOS_INCBK

0x81

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

0x82

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

DMC_AM3_QOS_DECBKne

Bit(s)31~10l

DMC_AM3_QOS_DEC

0x83

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AM3_QOS_DIS

0x84

dk
er

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0H

ar

Bit(s)
31~10

0x85

to

DMC_AM3_QOS_DISBK
R/WR/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AM3_QOS_CTRL0ute

Bit(s)
31~10

0x86

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

0

qos decrease urgent enable. enable the decrease urgent function.

1

D

is

tr
ib

Bit(s)
31~20

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

DMC_AM3_QOS_CTRL1

0x87

Bit(s)
31~2

R/W
R/W

Default
0

Description
Not used.

1
0

R/W
R/W

0
0

side bank urgent increase enable.
side bank urgent decrease enable.

Default
0

Description
Not used.

DMC_AM4_CHAN_CTRL
Bit(s)
31~30

R/W
R/W

0x88

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S905 Datasheet

Revision 1.1.4

Bit(s)
29:20
18

R/W
R/W
R/W

Default
0xff
0Description
write request pending cycle number to inc urgent level if not granted.
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

DMC_AM4_QOS_INC

0x8a

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

l

0x8b

ne

DMC_AM4_QOS_INCBK
R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

DMC_AM4_QOS_DEC

0x8c

dk
er

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

arBit(s)
31~10

DMC_AM4_QOS_DECBK

0x8d

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AM4_QOS_DIS

0x8e

e

to

H

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

tr
ib

DMC_AM4_QOS_DISBK

ut

Bit(s)
31~10

0x8f

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

isBit(s)
31~10

D

DMC_AM4_QOS_CTRL00x90

Bit(s)
31~20

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

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DMC_AM4_QOS_CTRL1

0x91

Bit(s)
31~2

R/W
R/W

Default
0

Description
Not used.

1
0

R/W
R/W

0
0

side bank urgent increase enable.
side bank urgent decrease enable.

0x92

R/W
R/W

Default
0

Description
Not used.

29:20
18

R/W
R/W

0xff
0

write request pending cycle number to inc urgent level if not granted.
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

0x94

dk
er

DMC_AM5_QOS_INC

neBit(s)
31~30

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

DMC_AM5_QOS_INCBK

0x95

l

DMC_AM5_CHAN_CTRL

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

Har

Bit(s)
31~10

0x96

to

DMC_AM5_QOS_DEC
R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

DMC_AM5_QOS_DECBKut

eBit(s)
31~10

0x97

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AM5_QOS_DIS

trib

Bit(s)
31~10

0x98

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

D

is

Bit(s)
31~10

DMC_AM5_QOS_DISBK

0x99

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AM5_QOS_CTRL00x9a

Bit(s)
31~20

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.

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Bit(s)
13~6

R/W
R/W

Default
0

Description
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

Default
0

Description
Not used.

29:20
18

R/W
R/W

0xff
0

write request pending cycle number to inc urgent level if not granted.
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

DMC_AM6_QOS_INC

0x9e

dk
er

R/W
R/W

l

0x9c

Bit(s)31~30

ne

DMC_AM6_CHAN_CTRL

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

arBit(s)
31~10

0x9f

H

DMC_AM6_QOS_INCBK
R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

DMC_AM6_QOS_DECetoBit(s)
31~10

0xa0

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

tr
ib

DMC_AM6_QOS_DECBKut

Bit(s)
31~10

0xa1

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

isBit(s)
31~10

D

DMC_AM6_QOS_DIS

0xa2

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

DMC_AM6_QOS_DISBK

0xa3

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AM6_QOS_CTRL0

0xa4

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Bit(s)
31~20

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

0xa6

R/W
R/W

Default
0

Description
Not used.

29:20
18

R/W
R/W

0xff
0

write request pending cycle number to inc urgent level if not granted.
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

0xa7

ar

DMC_AM7_HOLD _CTRLdker

Bit(s)
31~30

ne

l

DMC_AM7_CHAN_CTRL

R/W
R/W

Default
0x18

Description
Write hold number. If the outstanding write request meet this number disable the write request.

23~16
15~8

R/W
R/W

0x10
0x18

Write hold release number. Enable the request if outstanding request is lower than this number.
Read hold number. If the outstanding write request meet this number disable the write request.

7~0

R/W

0x10

READ hold release number. Enable the request if outstanding request is lower than this number.

DMC_AM7_QOS_INC

toH

Bit(s)
31~24

0xa8

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

uteBit(s)
31~10

0xa9

tr
ib

DMC_AM7_QOS_INCBK
R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

isBit(s)
31~10

DMC_AM7_QOS_DEC

0xaa

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

D

Bit(s)
31~10

DMC_AM7_QOS_DECBK

0xab

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

Default
0

Description
Not used.

DMC_AM7_QOS_DIS
Bit(s)
31~10

R/W
R/W

0xac

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Bit(s)
9~0

Revision 1.1.4

R/W
R/W

Default
0

Description
when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

DMC_AM7_QOS_DISBK

0xad

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AM7_QOS_CTRL0

0xae

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

ar

dk
er

ne

l

Bit(s)
31~20

DMC_AXI0 _CHAN_CTRL

0xb0

R/W
R/W

Default
0

Description
Not used.

29:20
19
18

R/W
R/W
R/W

0xff
0
0

write request pending cycle number to inc urgent level if not granted.
AXI0 default urgent bit
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

7~0

R/W

0

force this channel all request to be urgent request.

to

e

ut

tr
ib

DMC_AXI0_QOS_INC

H

Bit(s)
31~30

0xb2

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

isBit(s)
31~10

DMC_AXI0_QOS_INCBK

0xb3

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

D

Bit(s)
31~10

DMC_AXI0_QOS_DEC

0xb4

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

Default
0

Description
Not used.

DMC_AXI0_QOS_DECBK
Bit(s)
31~10

R/W
R/W

0xb5

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Bit(s)
9~0

Revision 1.1.4

R/W
R/W

Default
0

Description
if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AXI0_QOS_DIS

0xb6

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

DMC_AXI0_QOS_DISBK

0xb7

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AXI0_QOS_CTRL0nelBit(s)
31~10

0xb8

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

ar

H

to

0xb9

R/W
R/W

Default
0

Description
Not used.

19~16

R

0

FIQ pin status.

15~12

R

0

IRQ pin status.

11

R/W

1

ARM FIQ controlled super urgent enable.

10

R/W

0

ARM FIQ controlled urgent enable.

9

R/W

0

8

R/W

1

7

R/W

1

6~5

R/W

0

4

R/W

1

enable AXI0 auto urgent enable. When there's no other request, treat the AXI0 as super urgent request.
other wise, use the bit 3:0 to set the urgent.

3~2

R/W

0

AXI0 urgent level if the VIU read ports are not IDLE.

R/W

2’b01

AXI0 uregent level if the VIU read ports are IDLE.

1~0

is

tr
ib

ut

e

Bit(s)
31~20

D

DMC_AXI0_QOS_CTRL1dker

Bit(s)
31~20

ARM IRQ controlled super urgent enable.
ARM IRQ controlled urgent enable.
IRQ/FIQ enable.
Not used.

DMC_AXI1_CHAN_CTRL

0xba

Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29:20
19
18

R/W
R/W
R/W

0xff
0
0

write request pending cycle number to inc urgent level if not granted.
AXI0 default urgent bit
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

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Revision 1.1.4

Bit(s)
3~0

R/W
R/W

Default
0xf

Description
canvas arbiter arbiter weight.

7~0

R/W

0

force this channel all request to be urgent request.

DMC_AXI1_QOS_INC

0xbc

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

DMC_AXI1_QOS_INCBK

0xbd

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

DMC_AXI1_QOS_DECnelBit(s)
31~10

0xbe

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

DMC_AXI1_QOS_DECBK

0xbf

dk
er

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

Har

Bit(s)
31~10

DMC_AXI1_QOS_DIS

0xc0

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

DMC_AXI1_QOS_DISBK
R/WR/W

Default
0

9~0

R/W

0

DMC_AXI1_QOS_CTRL0

0xc1

Description
Not used.

tribBit(s)
31~10

ut

e

to

Bit(s)
31~10

after disable the request, when the leacky bucket counter less than this number, reenable this request..

0xc2

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

D

is

Bit(s)
31~20

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

DMC_AXI2_CHAN_CTRL

0xc4

Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29:20

R/W

0xff

write request pending cycle number to inc urgent level if not granted.

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Revision 1.1.4

Bit(s)
19
18

R/W
R/W
R/W

Default
00

Description
AXI0 default urgent bit
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

7~0

R/W

0

force this channel all request to be urgent request.

DMC_AXI2_QOS_INC

0xc6

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

DMC_AXI2_QOS_INCBKnel

Bit(s)
31~10

0xc7

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

DMC_AXI2_QOS_DEC

0xc8

dk
er

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

arBit(s)
31~10

0xc9

H

DMC_AXI2_QOS_DECBK
R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AXI2_QOS_DISetoBit(s)
31~10

0xca

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

tr
ib

ut

Bit(s)
31~10

DMC_AXI2_QOS_DISBK

0xcb

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DisBit(s)
31~10

DMC_AXI2_QOS_CTRL00xcc

Bit(s)
31~20

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

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Bit(s)
0

Revision 1.1.4

R/W
R/W

Default
0

Description
qos enable.

DMC_AXI3_CHAN_CTRL

0xce

R/W
R/W

Default
0

Description
Not used.

29:20
19
18

R/W
R/W
R/W

0xff
0
0

write request pending cycle number to inc urgent level if not granted.
AXI0 default urgent bit
force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

7~0

R/W

0

force this channel all request to be urgent request.

ne

DMC_AXI3_HOLD _CTRLlBit(s)
31~30

0xcf

R/W
R/W

Default
0x18

Description
Write hold number. If the outstanding write request meet this number disable the write request.

23~16

R/W

0x10

Write hold release number. Enable the request if outstanding request is lower than this number.

15~8

R/W

0x18

Read hold number. If the outstanding write request meet this number disable the write request.

7~0

R/W

0x10

READ hold release number. Enable the request if outstanding request is lower than this number.

0xd0

ar

DMC_AXI3_QOS_INCdker

Bit(s)
31~24

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

DMC_AXI3_QOS_INCBKtoH

Bit(s)
31~10

0xd1

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

DMC_AXI3_QOS_DECuteBit(s)
31~10

0xd2

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

is

DMC_AXI3_QOS_DECBKtr
ib

Bit(s)
31~10

0xd3

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

D

Bit(s)
31~10

DMC_AXI3_QOS_DIS

0xd4

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

DMC_AXI3_QOS_DISBK
Bit(s)
31~10

R/W
R/W

0xd5
Default
0

Description
Not used.

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Bit(s)
9~0

Revision 1.1.4

R/W
R/W

Default
0

Description
after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AXI3_QOS_CTRL0

0xd6

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

R/W
R/W

Default
0

Description
Not used.

29:20

R/W

0xff

write request pending cycle number to inc urgent level if not granted.

19

R/W

0

AXI0 default urgent bit

18

R/W

0

force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

7~0

R/W

0

force this channel all request to be urgent request.

to

H

ar

Bit(s)
31~30

DMC_AXI4_QOS_INC

0xda

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

tr
ib

ut

e

Bit(s)
31~10

DMC_AXI4_QOS_INCBK

ne

0xd8

dk
er

DMC_AXI4_CHAN_CTRLlBit(s)
31~20

0xdb

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

isBit(s)
31~10

DMC_AXI4_QOS_DEC

0xdc

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

D

Bit(s)
31~10

DMC_AXI4_QOS_DECBK

0xdd

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

Default
0

Description
Not used.

DMC_AXI4_QOS_DIS
Bit(s)
31~10

R/W
R/W

0xde

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Bit(s)
9~0

Revision 1.1.4

R/W
R/W

Default
0

Description
when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

DMC_AXI4_QOS_DISBK

0xdf

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AXI4_QOS_CTRL0

0xe0

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

4

R/W

0

qos idle mode enable. enable the idle counter.

3

R/W

0

qos disable enable. enable the feature to disable request.

2

R/W

0

qos decrease urgent enable. enable the decrease urgent function.

1

R/W

0

qos inccrease urgent enable. enabel the increase urgent function.

0

R/W

0

qos enable.

ar

dk
er

ne

l

Bit(s)
31~20

DMC_AXI7_CHAN_CTRL

0xf6

R/W
R/W

Default
0

Description
Not used.

29:20

R/W

0xff

write request pending cycle number to inc urgent level if not granted.

19

R/W

0

AXI0 default urgent bit

18

R/W

0

force this channel all request to be super urgent request.

17

R/W

0

force this channel all request to be urgent request.

16

R/W

0

force this channel all request to be non urgent request.

13~4

R/W

0x3c

read request pending cycle number to inc urgent level if not granted.

3~0

R/W

0xf

canvas arbiter arbiter weight.

7~0

R/W

0

force this channel all request to be urgent request.

to

e

ut

tr
ib

0xf7

R/W
R/W

Default
0x18

Description
Write hold number. If the outstanding write request meet this number disable the write request.

23~16

R/W

0x10

Write hold release number. Enable the request if outstanding request is lower than this number.

15~8

R/W

0x18

Read hold number. If the outstanding write request meet this number disable the write request.

7~0

R/W

0x10

READ hold release number. Enable the request if outstanding request is lower than this number.

D

Bit(s)31~24

is

DMC_AXI7_HOLD _CTRL

H

Bit(s)
31~30

DMC_AXI7_QOS_INC

0xf8

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the leacky bucket counter less this number increase the urgent.

DMC_AXI7_QOS_INCBK

0xf9

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

once the increase urgent triggered, after leacky bucket counter is larger than this number, deassert theincrease urgent function.

DMC_AXI7_QOS_DEC

0xfa

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Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

leacky bucket counter is larger this number, decrease the urgent of this request.

DMC_AXI7_QOS_DECBK

0xfb

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

if the decrease urgent triggered, after leacky buck counter less this number, deassert the decrease urgent
function.

DMC_AXI7_QOS_DIS

0xfc

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

when leacky bucket counter larger this number, disable each request some cycles. the disable cycle
number is defined in bit 19:12 of QOS_CTRL0

0xfd

dk
er

DMC_AXI7_QOS_DISBKnelBit(s)
31~10

Bit(s)
31~10

R/W
R/W

Default
0

Description
Not used.

9~0

R/W

0

after disable the request, when the leacky bucket counter less than this number, reenable this request..

DMC_AXI7_QOS_CTRL0

0xfe

R/W
R/W

Default
0

Description
qos idle number. if the channel no request for that long, set leaky bucket counter to 0.

19~14

R/W

0

13~6

R/W

0

qos disable cycles. if the leaky bucket counter larger than QOS_DIS register number, than disable the eachrequest how many cycles.
leackey bucket counter minus number..

5

R/W

0

qos mode. 1 : use bankdwidth as the QOS control. 0 : Use latency as QOS control.

to

H

ar

Bit(s)
31~20

DMC_SEC_CTRLute

DMC secure register.
Base address 0x0xda838400. Each register takes 4 byte address
0x0

R/W
R/W

Default
0

Description
wriTE bit 31 to 1 to update the setting in shadow register for range control registers.

30~0

R/W

0

Not used.

DMC_SEC_RANGE0_CTRLtrib

Bit(s)
31

0x1

R/W
R/W

Default
0

Description
16Bits Range 0 end address. unit : 64Kbyte.

15~0

R/W

0

16Bits Range 0 start address. unit: 64Kbyte.

DisBit(s)
31~16

DMC_SEC_RANGE1_CTRL

0x2

Bit(s)
31~16

R/W
R/W

Default
0

Description
16Bits Range 1 end address. unit : 64Kbyte.

15~0

R/W

0

16Bits Range 1 start address. unit: 64Kbyte.

DMC_SEC_RANGE2_CTRL

0x3

Bit(s)
31~16

R/W
R/W

Default
0

Description
16Bits Range 2 end address. unit : 64Kbyte.

15~0

R/W

0

16Bits Range 2 start address. unit: 64Kbyte.

DMC_SEC_RANGE3_CTRL

0x4

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Bit(s)
31~16

R/W
R/W

Default
0

Description
16Bits Range 3 end address. unit : 64Kbyte.

15~0

R/W

0

16Bits Range 3 start address. unit: 64Kbyte.

DMC_SEC_RANGE4_CTRL

0x5

Bit(s)
31~16

R/W
R/W

Default
0

Description
16Bits Range 4 end address. unit : 64Kbyte.

15~0

R/W

0

16Bits Range 4 start address. unit: 64Kbyte.

DMC_SEC_RANGE5_CTRL

0x6

R/W
R/W

Default
0

Description
16Bits Range 5 end address. unit : 64Kbyte.

15~0

R/W

0

16Bits Range 5 start address. unit: 64Kbyte.

0x7

R/W
R/W

Default
0

Description
Not used.

6

R/W

0

default range security level. 1: secure. 0: unsecure.

5

R/W

0

Range 5 security level. 1 : secure. 0 : unsecure.

4

R/W

0

Range 4 security level. 1 : secure. 0 : unsecure.

3

R/W

0

Range 3 security level. 1 : secure. 0 : unsecure.

2

R/W

0

Range 2 security level. 1 : secure. 0 : unsecure.

1

R/W

0

Range 1 security level. 1 : secure. 0 : unsecure.

0

R/W

0

Range 0 security level. 1 : secure. 0 : unsecure.

Har

Bit(s)
31~7

DMC_SEC_AXI_PORT_CTRL

dker

DMC_SEC_RANGE_CTRL

nelBit(s)
31~16

0xe

R/W
R/W

Default
0

Description
Not used.

23

R/W

0

AXI port3 (HDCP ) secure region write access enable bit 1: enable. 0 : disable.

22

R/W

0

AXI port3 (HDCP ) non secure region write access enable bit. 1: enable. 0 : disable.

21

R/W

0

AXI port2 (Mali 1) secure region write access enable bit. 1: enable. 0 : disable.

20

R/W

0

AXI port2 (Mali 1) non secure region write access enable bit. 1: enable. 0 : disable.

19

R/W

0

AXI port1 (Mali 0) secure region write access enable bit. 1: enable. 0 : disable.

18

R/W

0

AXI port1 (Mali 0) non secure region write access enable bit. 1: enable. 0 : disable.

17

R/W

0

16

R/W

0

15~8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

AXI port2 (Mali 1) secure region read access enable bit. 1: enable. 0 : disable.
//Bit(s)AXI port2
1) nonsecureaccessbit. 01:: enable.
AXI
port24.(Mali1) non(Malisecureregionreadregion
accessread
enablebit. enable
1: enable.
disable. 0 : disable.

R/W

0

AXI port1 (Mali 0) secure region read access enable bit. 1: enable. 0 : disable.

AXI port0 (CPU) secure region write access enable bit. 1: enable. 0 : disable.
AXI port0 (CPU) non secure region write access enable bit. 1: enable. 0 : disable.
AXI port3 (HDCP ) secure region read access enable bit. 1: enable. 0 : disable.
AXI port3 (HDCP ) non secure region read access enable bit. 1: enable. 0 : disable.

2

D

is

tr
ib

ut

e

to

Bit(s)
31~24

R/W

0

AXI port1 (Mali 0) non secure region read access enable bit. 1: enable. 0 : disable.

1

R/W

0

AXI port0 (CPU) secure region read access enable bit. 1: enable. 0 : disable.

0

R/W

0

AXI port0 (CPU) non secure region read access enable bit. 1: enable. 0 : disable.

3

DMC_VDEC_SEC_READ_CTRL

0x10

Bit(s)31

R/W
R/W

Default
0

Description
VDEC subID15 ( not used )

30

R/W

0

VDEC subID15 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

29

R/W

0

VDEC subID14 ( not used )

28

R/W

0

VDEC subID14 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

27

R/W

0

VDEC subID13 ( not used )secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

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Bit(s)26

R/W
R/W

Default
0

Description
VDEC subID13 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

25

R/W

0

VDEC subID12 ( not used )

24

R/W

0

VDEC subID12 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

23

R/W

0

VDEC subID11 ( not used )

22

R/W

0

VDEC subID11 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

21

R/W

0

VDEC subID10 ( mbbot )

20

R/W

0

VDEC subID10 ( mbbot ) non secure region read access enable bit. 1: enable. 0 : disable.

19

R/W

0

VDEC subID9 ( not used.)

18

R/W

0

VDEC subID9 ( not used) non secure region read access enable bit. 1: enable. 0 : disable.

17

R/W

0

VDEC subID8 ( not used.)

16

R/W

0

VDEC subID8 ( not used) non secure region read access enable bit. 1: enable. 0 : disable.

15

R/W

0

VDEC subID7 (dw)

14

R/W

0

VDEC subID7 (dw) non secure region read access enable bit. 1: enable. 0 : disable..

13

R/W

0

VDEC subID6 (comb)

12

R/W

0

VDEC subID6 (comb) non secure region read access enable bit. 1: enable. 0 : disable.

11

R/W

0

VDEC subID5 (lmem)

10

R/W

0

VDEC subID5 (lmem) non secure region read access enable bit. 1: enable. 0 : disable.

9

R/W

0

VDEC subID4 (imem)

8

R/W

0

VDEC subID4 (imem) non secure region read access enable bit. 1: enable. 0 : disable.

7

R/W

0

VDEC subID3 (picdc)

6

R/W

0

VDEC subID3 (picdc) non secure region read access enable bit. 1: enable. 0 : disable.

5

R/W

0

VDEC subID2 (psc)

4

R/W

0

VDEC subID2 (psc) non secure region read access enable bit. 1: enable. 0 : disable.

3

R/W

0

VDEC subID1 (dcac)

2

R/W

0

VDEC subID1 (dcac) non secure region read access enable bit. 1: enable. 0 : disable.

1

R/W

0

VDEC subID0 (vld)

0

R/W

0

VDEC subID0 (vld) non secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable
secure region read access enable bit. 1: enable. 0 : disable.

lsecure region read access enable bit. 1: enable. 0 : disable.

nesecure region read access enable bit. 1: enable. 0 : disable.

dk
ersecure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

arsecure region read access enable bit. 1: enable. 0 : disable.

Hsecure region read access enable bit. 1: enable. 0 : disable.

DMC_VDEC_SEC_WRITE _CTRL

tosecure region read access enable bit. 1: enable. 0 : disable.

0x11

Bit(s)31

R/W
R/W

Default
0

Description
VDEC subID15 ( not used )

30

R/W

0

VDEC subID15 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.

29

R/W

0

VDEC subID14 ( not used )

28

R/W

0

VDEC subID14 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.

27

R/W

0

VDEC subID13 ( not used )

26

R/W

0

25

R/W

0

24

R/W

0

23

R/W

0

22

R/W

0

VDEC subID11 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.

21

R/W

0

VDEC subID10 ( mbbot )

20

R/W

VDEC subID10 ( mbbot ) non secure region write access enable bit. 1: enable. 0 : disable.

R/W

0

VDEC subID9 ( not used.)

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

VDEC subID13 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.
VDEC subID12 ( not used )secure region write access enable bit. 1: enable. 0 : disable.

VDEC subID12 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.
VDEC subID11 ( not used )secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

D

is

tr
ib

ut

e

secure region write access enable bit. 1: enable. 0 : disable.

0

R/W

0

VDEC subID9 ( not used) non secure region write access enable bit. 1: enable. 0 : disable.

17

R/W

0

VDEC subID8 ( not used.)

16

R/W

0

VDEC subID8 ( not used) non secure region write access enable bit. 1: enable. 0 : disable.

15

R/W

0

VDEC subID7 (dw)

14

R/W

0

VDEC subID7 (dw) non secure region write access enable bit. 1: enable. 0 : disable..

13

R/W

0

VDEC subID6 (comb)

12

R/W

0

VDEC subID6 (comb) non secure region write access enable bit. 1: enable. 0 : disable.

11

R/W

0

VDEC subID5 (lmem)

10

R/W

0

VDEC subID5 (lmem) non secure region write access enable bit. 1: enable. 0 : disable.

9

R/W

0

VDEC subID4 (imem)

8

R/W

0

VDEC subID4 (imem) non secure region write access enable bit. 1: enable. 0 : disable.

19
18

secure region write access enable bit. 1: enable. 0 : disable
secure region write access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

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Bit(s)
7

R/W
R/W

Default
0

Description
VDEC subID3 (picdc)

6

R/W

0

VDEC subID3 (picdc) non secure region write access enable bit. 1: enable. 0 : disable.

5

R/W

0

VDEC subID2 (psc)

4

R/W

0

VDEC subID2 (psc) non secure region write access enable bit. 1: enable. 0 : disable.

3

R/W

0

VDEC subID1 (dcac)

2

R/W

0

VDEC subID1 (dcac) non secure region write access enable bit. 1: enable. 0 : disable.

1

R/W

0

VDEC subID0 (vld)

0

R/W

0

VDEC subID0 (vld) non secure region write access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

DMC_VDEC_SEC_CFG

0x12

R/W

0

VDEC subID14 () To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID13 () To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

29

R/W

0

28

R/W

0

27

R/W

0

26

R/W

0

25

R/W

0

24

R/W

0

23

R/W

0

22

R/W

0

21

R/W

0

20

R/W

0

19

R/W

0

18

R/W

0

17

R/W

0

16

R/W

0

15

R/W

0

VDEC subID15 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

14

R/W

0

13

R/W

0

12

R/W

0

11

R/W

0

10

R/W

0

VDEC subID14 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID13 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID12 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID11 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID10 (mbbot) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

dk
er

30

D

ne

l

DWC_VDEC_SEC_READ_CTRL and DMC_VDEC_SEC_WRITE_CTRL register APB bus configuation enable. 2 bit for each port. one for read, one for write.
Bit(s)
R/W Default Description
31
R/W
0
VDEC subID15 () To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

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e

to

H

ar

VDEC subID12 () To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID11 () To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID10 (mbbot) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID9 ()To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID8 ()To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID7 (dw) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID6 (comb) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID5 (lmem) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID4 (imem) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

is

tr
ib

VDEC subID3 (picdc) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID2 (psc) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID1 (dcac) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID0 (vld) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

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AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Bit(s)
9

R/W
R/W

Default
0

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

Description
VDEC subID9 ()To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID8 ()To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID7 (dw)
To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID6 (comb) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID5 (lmem) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

dk
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l

VDEC subID4 (imem) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID3 (picdc) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID2 (psc) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VDEC subID1 (dcac) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
VDEC subID0 (vld) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

DMC_VDEC_EF_TRIG_CTRL

0x13

R/W

0

trigger type selection for subID14 (). 1 = secure access. 0 : non secure access.

29

R/W

0

trigger type selection for subID13 (). 1 = secure access. 0 : non secure access

28

R/W

0

trigger type selection for subID12 (). 1 = secure access. 0 : non secure access

27

R/W

0

trigger type selection for subID11 (). 1 = secure access. 0 : non secure access

26

R/W

0

trigger type selection for subID10 (mbbot). 1 = secure access. 0 : non secure access

25

R/W

0

trigger type selection for subID9 (). 1 = secure access. 0 : non secure access

24

R/W

0

trigger type selection for subID8 (). 1 = secure access. 0 : non secure access

23

R/W

0

trigger type selection for subID7 (DW). 1 = secure access. 0 : non secure access

22

R/W

0

trigger type selection for subID6 (COMB). 1 = secure access. 0 : non secure access

21

R/W

0

trigger type selection for subID5 (LMEM). 1 = secure access. 0 : non secure access

20

R/W

0

trigger type selection for subID4 (IMEM). 1 = secure access. 0 : non secure access

19

R/W

0

18

R/W

0

17

R/W

0

16

R/W

0

15

R/W

0

trigger source selection for subID15 (). 1 = selected. 0 : not selected.

14

R/W

0

trigger source selection for subID14 (). 1 = selected. 0 : not selected.

13

R/W

0

trigger source selection for subID13 (). 1 = selected. 0 : not selected..

R/W0

trigger source selection for subID12 (). 1 = selected. 0 : not selected..

R/W0

trigger source selection for subID11 (). 1 = selected. 0 : not selected.

10

R/W

0

trigger source selection for subID10 (mbbot). 1 = selected. 0 : not selected..

9

R/W

0

trigger source selection for subID9 (). 1 = selected. 0 : not selected..

8

R/W

0

trigger source selection for subID8 (). 1 = selected. 0 : not selected.

7

R/W

0

trigger source selection for subID7 (dw). 1 = selected. 0 : not selected.

6

R/W

0

trigger source selection for subID6 (comb). 1 = selected. 0 : not selected.

5

R/W

0

trigger source selection for subID5 (lmem). 1 = selected. 0 : not selected..

4

R/W

0

trigger source selection for subID4 (imem). 1 = selected. 0 : not selected.

3

R/W

0

trigger source selection for subID3 (picdc). 1 = selected. 0 : not selected.

2

R/W

0

trigger source selection for subID2 (psc). 1 = selected. 0 : not selected..

1

R/W

0

trigger source selection for subID1 (dcac). 1 = selected. 0 : not selected..

12
11

is

tr
ib

ut

e

to

H

30

D

ar

VDEC Electronic fence trigger selection and trigger secure type. 1 bit for trigger select for one read port. 1 bit for trigger type for one read port. Electronic
fence would be triggered by the read from defined secure level from selected subIDs
Bit(s)
R/W Default Description
31
R/W
0
trigger type selection for subID15 (). 1 = secure access. 0 : non secure access.

trigger type selection for subID3 (PICDC). 1 = secure access. 0 : non secure accesstrigger type selection for subID2 (PSC). 1 = secure access. 0 : non secure access.
trigger type selection for subID1 (dcac). 1 = secure access. 0 : non secure access.
trigger type selection for subID0 (vld). 1 = secure access. 0 : non secure access248/336

AMLOGIC, Inc. Proprietary

S905 Datasheet

Bit(s)
0

Revision 1.1.4

R/W
R/W

Default
0

Description
trigger source selection for subID0 (vld). 1 = selected. 0 : not selected.

DMC_VDEC_EF_PROT

0x14

To define which subID would be affected after the EF got triggered.
Bit(s)
R/W Default Description
31
R/W
0
EF would affect subID15 () write access secure control. 1 = selected. 0 : not selected. .
R/W0

EF would affect subID14 () write access secure control. 1 = selected. 0 : not selected.

29

R/W

0

EF would affect subID13 () write access secure control. 1 = selected. 0 : not selected.

28

R/W

0

EF would affect subID12 () write access secure control. 1 = selected. 0 : not selected.

27

R/W

0

EF would affect subID11 () write access secure control. 1 = selected. 0 : not selected.

26

R/W

0

EF would affect subID10 (mbbot) write access secure control. 1 = selected. 0 : not selected.

25

R/W

0

EF would affect subID9 () write access secure control. 1 = selected. 0 : not selected.

24

R/W

0

EF would affect subID8 () write access secure control. 1 = selected. 0 : not selected.

23

R/W

0

EF would affect subID7 (dw) write access secure control. 1 = selected. 0 : not selected.

22

R/W

0

EF would affect subID6 (comb) write access secure control. 1 = selected. 0 : not selected.

21

R/W

0

EF would affect subID5 (lmem) write access secure control. 1 = selected. 0 : not selected.

20

R/W

0

EF would affect subID4 (imem) write access secure control. 1 = selected. 0 : not selected.

19

R/W

0

EF would affect subID3 (picdc) write access secure control. 1 = selected. 0 : not selected.

18

R/W

0

EF would affect subID2 (psc) write access secure control. 1 = selected. 0 : not selected.

17

R/W

0

EF would affect subID1 (dcac) write access secure control. 1 = selected. 0 : not selected.

16

R/W

0

EF would affect subID0 (vld) write access secure control. 1 = selected. 0 : not selected.

15

R/W

0

EF would affect subID15 () read access secure control. 1 = selected. 0 : not selected. .

14

R/W

0

EF would affect subID14 () read access secure control. 1 = selected. 0 : not selected.

13

R/W

0

EF would affect subID13 () read access secure control. 1 = selected. 0 : not selected.

12

R/W

0

EF would affect subID12 () read access secure control. 1 = selected. 0 : not selected.

11

R/W

0

EF would affect subID11 () read access secure control. 1 = selected. 0 : not selected.

10

R/W

0

EF would affect subID10 (mbbot) read access secure control. 1 = selected. 0 : not selected.

9

R/W

0

EF would affect subID9 () read access secure control. 1 = selected. 0 : not selected.

8

R/W

0

EF would affect subID8 () read access secure control. 1 = selected. 0 : not selected.

7

R/W

0

EF would affect subID7 (dw) read access secure control. 1 = selected. 0 : not selected.

6

R/W

0

EF would affect subID6 (comb) read access secure control. 1 = selected. 0 : not selected.

5

R/W

0

EF would affect subID5 (lmem) read access secure control. 1 = selected. 0 : not selected.

4

R/W

0

EF would affect subID4 (imem) read access secure control. 1 = selected. 0 : not selected.

3

R/W

0

EF would affect subID3 (picdc) read access secure control. 1 = selected. 0 : not selected.

2

R/W

0

EF would affect subID2 (psc) read access secure control. 1 = selected. 0 : not selected.

1

R/W

0

0

R/W

0

ne

dk
er

ar

H

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ib

EF would affect subID1 (dcac) read access secure control. 1 = selected. 0 : not selected.
EF would affect subID0 (vld) read access secure control. 1 = selected. 0 : not selected.

0x15

is

DMC_VDEC_EF_READ

l

30

D

This register contains the vdec read security control Bits after the EF got triggered. If the DMC_VDEC_EF_PROT register Bit 15:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_VDEC_SEC_READ_CTRL related Bits.

DMC_VDEC_EF_WRITE

0x16

This register contains the vdec write security control Bits after the EF got triggered. If the DMC_VDEC_EF_PROT register Bit 15:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_VDEC_SEC_WRITE _CTRL related Bits.

DMC_HCODEC_SEC_READ_CTRL

0x17

Bit(s)31

R/W
R/W

Default
0

Description
HCODEC subID15 ( not used )

30

R/W

0

HCODEC subID15 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

29

R/W

0

HCODEC subID14 ( not used )

28

R/W

0

HCODEC subID14 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

27

R/W

0

HCODEC subID13 ( not used )

26

R/W

0

HCODEC subID13 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

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AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Bit(s)25

R/W
R/W

Default
0

Description
HCODEC subID12 ( me )

24

R/W

0

HCODEC subID12 ( me ) non secure region read access enable bit. 1: enable. 0 : disable.

23

R/W

0

HCODEC subID11 ( mfdin )

22

R/W

0

HCODEC subID11 (mfdin) non secure region read access enable bit. 1: enable. 0 : disable.

21

R/W

0

HCODEC subID10 ( mcmbot )

20

R/W

0

HCODEC subID10 ( mcmbot ) non secure region read access enable bit. 1: enable. 0 : disable.

19

R/W

0

HCODEC subID9 (i_pred.)

18

R/W

0

HCODEC subID9 (i_pred) non secure region read access enable bit. 1: enable. 0 : disable.

17

R/W

0

HCODEC subID8 ( qdct.)

16

R/W

0

HCODEC subID8 ( qdct) non secure region read access enable bit. 1: enable. 0 : disable.

15

R/W

0

HCODEC subID7 (vlc)

14

R/W

0

HCODEC subID7 (vlc) non secure region read access enable bit. 1: enable. 0 : disable..

13

R/W

0

HCODEC subID6 (comb)

12

R/W

0

HCODEC subID6 (comb) non secure region read access enable bit. 1: enable. 0 : disable.

11

R/W

0

HCODEC subID5 (lmem)

10

R/W

0

HCODEC subID5 (lmem) non secure region read access enable bit. 1: enable. 0 : disable.

9

R/W

0

HCODEC subID4 (imem)

8

R/W

0

HCODEC subID4 (imem) non secure region read access enable bit. 1: enable. 0 : disable.

7

R/W

0

HCODEC subID3 (mcrcc)

6

R/W

0

HCODEC subID3 (mcrcc) non secure region read access enable bit. 1: enable. 0 : disable.

5

R/W

0

HCODEC subID2 (psc)

4

R/W

0

HCODEC subID2 (psc) non secure region read access enable bit. 1: enable. 0 : disable.

3

R/W

0

HCODEC subID1 (dcac)

2

R/W

0

HCODEC subID1 (dcac) non secure region read access enable bit. 1: enable. 0 : disable.

1

R/W

0

HCODEC subID0 (vld)

0

R/W

0

HCODEC subID0 (vld) non secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable
secure region read access enable bit. 1: enable. 0 : disable.

nesecure region read access enable bit. 1: enable. 0 : disable.

lsecure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.

dk
ersecure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.

arsecure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.

Hsecure region read access enable bit. 1: enable. 0 : disable.

R/W
R/W

Default
0

Description
HCODEC subID15 ( not used )

30

R/W

0

HCODEC subID15 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.

29

R/W

0

HCODEC subID14 ( not used )secure region write access enable bit. 1: enable. 0 : disable.

28

R/W

0

HCODEC subID14 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.

27

R/W

0

HCODEC subID13 ( not used )secure region write access enable bit. 1: enable. 0 : disable.

26

R/W

0

ut

0x18

Bit(s)
31

HCODEC subID13 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.

25

R/W

0

24

R/W

0

23

R/W

0

22

R/W

0

21

R/W

0

HCODEC subID10 (mcmbot )

20

R/W

0

HCODEC subID10 (mcmbot ) non secure region write access enable bit. 1: enable. 0 : disable.

19

D

to

DMC_HCODEC_SEC_WRITE _CTRL

R/W

0HCODEC subID9 (i_pred.)

R/W

0

HCODEC subID9 (i_pred) non secure region write access enable bit. 1: enable. 0 : disable.

R/W

0

HCODEC subID8 ( qdct.)

16

R/W

0

HCODEC subID8 (qdct) non secure region write access enable bit. 1: enable. 0 : disable.

15

R/W

0

HCODEC subID7 (vlc)

14

R/W

0

HCODEC subID7 (vlc) non secure region write access enable bit. 1: enable. 0 : disable..

13

R/W

0

HCODEC subID6 (comb)

12

R/W

0

HCODEC subID6 (comb) non secure region write access enable bit. 1: enable. 0 : disable.

11

R/W

0

HCODEC subID5 (lmem)

10

R/W

0

HCODEC subID5 (lmem) non secure region write access enable bit. 1: enable. 0 : disable.

9

R/W

0

HCODEC subID4 (imem)

8

R/W

0

HCODEC subID4 (imem) non secure region write access enable bit. 1: enable. 0 : disable.

7

R/W

0

HCODEC subID3 (mcrcc)

18
17

is

tr
ib

e

secure region write access enable bit. 1: enable. 0 : disable.

HCODEC subID12 ( me )secure region write access enable bit. 1: enable. 0 : disable.

HCODEC subID12 ( me ) non secure region write access enable bit. 1: enable. 0 : disable.
HCODEC subID11 (mfdin)

secure region write access enable bit. 1: enable. 0 : disable.

HCODEC subID11 (mfdin) non secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

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AMLOGIC, Inc. Proprietary

S905 Datasheet

Revision 1.1.4

Bit(s)
6

R/W
R/W

Default
0

Description
HCODEC subID3 (mcrcc) non secure region write access enable bit. 1: enable. 0 : disable.

5

R/W

0

HCODEC subID2 (psc)

4

R/W

0

HCODEC subID2 (psc) non secure region write access enable bit. 1: enable. 0 : disable.

3

R/W

0

HCODEC subID1 (dcac)

2

R/W

0

HCODEC subID1 (dcac) non secure region write access enable bit. 1: enable. 0 : disable.

1

R/W

0

HCODEC subID0 (vld)

0

R/W

0

HCODEC subID0 (vld) non secure region write access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

DMC_HCODEC_SEC_CFG

0x19

R/W

0

HCODEC subID14 () To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
HCODEC subID13 () To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

29

R/W

0

28

R/W

0

27

R/W

0

26

R/W

0

25

R/W

0

24

R/W

0

23

R/W

0

22

R/W

0

21

R/W

0

20

R/W

0

19

R/W

0

18

R/W

0

17

R/W

0

16

R/W

0

15

R/W

0

HCODEC subID15 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

14

R/W

0

13

R/W

0

12

R/W

0

11

R/W

0

10

R/W

0

9

R/W

0

HCODEC subID14 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
HCODEC subID13 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
HCODEC subID12 (me) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID11 (mfdin) To enable APB bus modifiy the read security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID10 (mcmbot) To enable APB bus modifiy the read security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID9 (i_pred)To enable APB bus modifiy the read security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.

dk
er

30

D

ne

l

DWC_HCODEC_SEC_READ_CTRL and DMC_HCODEC_SEC_WRITE_CTRL register APB bus configuation enable. 2 bit for each port. one for read, one forwrite.
Bit(s)
R/W Default Description
31
R/W
0
HCODEC subID15 () To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

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ar

HCODEC subID12 (me) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID11 (mfdin) To enable APB bus modifiy the write security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID10 (mcmbot) To enable APB bus modifiy the write security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID9 (i_pred)To enable APB bus modifiy the write security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID8 (qdct)
To enable APB bus modifiy the write security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID7 (vlc) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID6 (comb) To enable APB bus modifiy the write security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID5 (lmem) To enable APB bus modifiy the write security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID4 (imem) To enable APB bus modifiy the write security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.

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HCODEC subID3 (mcrcc) To enable APB bus modifiy the write security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID2 (psc) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID1 (dcac) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID0 (vld) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

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Bit(s)
8

R/W
R/W

Default
0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

Description
HCODEC subID8 (qdct)
To enable APB bus modifiy the read security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID7 (vlc) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID6 (comb) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID5 (lmem) To enable APB bus modifiy the read security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.

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HCODEC subID4 (imem) To enable APB bus modifiy the read security control Bits. 1 : eable the APB
modify. 0 : disable APB bus modify.
HCODEC subID3 (mcrcc) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID2 (psc) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID1 (dcac) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HCODEC subID0 (vld) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

DMC_HCODEC_EF_TRIG_CTRL

0x1a

R/W

0

trigger type selection for subID14 (). 1 = secure access. 0 : non secure access.

29

R/W

0

trigger type selection for subID13 (). 1 = secure access. 0 : non secure access

28

R/W

0

trigger type selection for subID12 (me). 1 = secure access. 0 : non secure access

27

R/W

0

trigger type selection for subID11 (mfdin). 1 = secure access. 0 : non secure access

26

R/W

0

trigger type selection for subID10 (mcmbot). 1 = secure access. 0 : non secure access

25

R/W

0

trigger type selection for subID9 (i_pred). 1 = secure access. 0 : non secure access

24

R/W

0

trigger type selection for subID8 (qdct). 1 = secure access. 0 : non secure access

23

R/W

0

trigger type selection for subID7 (vlc). 1 = secure access. 0 : non secure access

22

R/W

0

trigger type selection for subID6 (COMB). 1 = secure access. 0 : non secure access

21

R/W

0

trigger type selection for subID5 (LMEM). 1 = secure access. 0 : non secure access

20

R/W

0

trigger type selection for subID4 (IMEM). 1 = secure access. 0 : non secure access

19

R/W

0

trigger type selection for subID3 (mcrcc). 1 = secure access. 0 : non secure access

18

R/W

0

trigger type selection for subID2 (PSC). 1 = secure access. 0 : non secure access.

17

R/W

0

16

R/W

0

15

R/W

0

14

R/W

0

13

R/W

0

trigger source selection for subID13 (). 1 = selected. 0 : not selected..

12

R/W

0

trigger source selection for subID12 (me). 1 = selected. 0 : not selected..

11

R/W

0

trigger source selection for subID11 (mfdin). 1 = selected. 0 : not selected.

10

R/W

0

trigger source selection for subID10 (mcmbot). 1 = selected. 0 : not selected..

9

R/W

0

trigger source selection for subID9 (i_pred). 1 = selected. 0 : not selected..

8

R/W

0

trigger source selection for subID8 (qdct). 1 = selected. 0 : not selected.

7

R/W

0

trigger source selection for subID7 (vlc). 1 = selected. 0 : not selected.

6

R/W

0

trigger source selection for subID6 (comb). 1 = selected. 0 : not selected.

5

R/W

0

trigger source selection for subID5 (lmem). 1 = selected. 0 : not selected..

4

R/W

0

trigger source selection for subID4 (imem). 1 = selected. 0 : not selected.

3

R/W

0

trigger source selection for subID3 (mcrcc). 1 = selected. 0 : not selected.

2

R/W

0

trigger source selection for subID2 (psc). 1 = selected. 0 : not selected..

1

R/W

0

trigger source selection for subID1 (dcac). 1 = selected. 0 : not selected..

0

R/W

0

trigger source selection for subID0 (vld). 1 = selected. 0 : not selected.

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30

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HCODEC Electronic fence trigger selection and trigger secure type. 1 bit for trigger select for one read port. 1 bit for trigger type for one read port.
Electronic fence would be triggered by the read from defined secure level from selected subIDs
Bit(s)
R/W Default Description
31
R/W
0
trigger type selection for subID15 (). 1 = secure access. 0 : non secure access.

trigger type selection for subID1 (dcac). 1 = secure access. 0 : non secure access.
trigger type selection for subID0 (vld). 1 = secure access. 0 : non secure accesstrigger source selection for subID15 (). 1 = selected. 0 : not selected.
trigger source selection for subID14 (). 1 = selected. 0 : not selected.

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DMC_HCODEC_EF_PROT

0x1b

To define which subID would be affected after the EF got triggered.
Bit(s)
R/W Default Description
31
R/W
0
EF would affect subID15 () write access secure control. 1 = selected. 0 : not selected. .
R/W0

EF would affect subID14 () write access secure control. 1 = selected. 0 : not selected.

29

R/W

0

EF would affect subID13 () write access secure control. 1 = selected. 0 : not selected.

28

R/W

0

EF would affect subID12 (me) write access secure control. 1 = selected. 0 : not selected.

27

R/W

0

EF would affect subID11 (mfdin) write access secure control. 1 = selected. 0 : not selected.

26

R/W

0

EF would affect subID10 (mcmbot) write access secure control. 1 = selected. 0 : not selected.

25

R/W

0

EF would affect subID9 (i_pred) write access secure control. 1 = selected. 0 : not selected.

24

R/W

0

EF would affect subID8 (qdct) write access secure control. 1 = selected. 0 : not selected.

23

R/W

0

EF would affect subID7 (vlc) write access secure control. 1 = selected. 0 : not selected.

22

R/W

0

EF would affect subID6 (comb) write access secure control. 1 = selected. 0 : not selected.

21

R/W

0

EF would affect subID5 (lmem) write access secure control. 1 = selected. 0 : not selected.

20

R/W

0

EF would affect subID4 (imem) write access secure control. 1 = selected. 0 : not selected.

19

R/W

0

EF would affect subID3 (mcrcc) write access secure control. 1 = selected. 0 : not selected.

18

R/W

0

EF would affect subID2 (psc) write access secure control. 1 = selected. 0 : not selected.

17

R/W

0

EF would affect subID1 (dcac) write access secure control. 1 = selected. 0 : not selected.

16

R/W

0

EF would affect subID0 (vld) write access secure control. 1 = selected. 0 : not selected.

15

R/W

0

EF would affect subID15 () read access secure control. 1 = selected. 0 : not selected. .

14

R/W

0

EF would affect subID14 () read access secure control. 1 = selected. 0 : not selected.

13

R/W

0

EF would affect subID13 () read access secure control. 1 = selected. 0 : not selected.

12

R/W

0

EF would affect subID12 (me) read access secure control. 1 = selected. 0 : not selected.

11

R/W

0

EF would affect subID11 (mfdin) read access secure control. 1 = selected. 0 : not selected.

10

R/W

0

EF would affect subID10 (mcmbot) read access secure control. 1 = selected. 0 : not selected.

9

R/W

0

EF would affect subID9 (i_pred) read access secure control. 1 = selected. 0 : not selected.

8

R/W

0

EF would affect subID8 (qdct) read access secure control. 1 = selected. 0 : not selected.

7

R/W

0

EF would affect subID7 (vlc) read access secure control. 1 = selected. 0 : not selected.

6

R/W

0

EF would affect subID6 (comb) read access secure control. 1 = selected. 0 : not selected.

5

R/W

0

EF would affect subID5 (lmem) read access secure control. 1 = selected. 0 : not selected.

4

R/W

0

EF would affect subID4 (imem) read access secure control. 1 = selected. 0 : not selected.

3

R/W

0

EF would affect subID3 (mcrcc) read access secure control. 1 = selected. 0 : not selected.

2

R/W

0

EF would affect subID2 (psc) read access secure control. 1 = selected. 0 : not selected.

1

R/W

0

EF would affect subID1 (dcac) read access secure control. 1 = selected. 0 : not selected.

0

R/W

0

EF would affect subID0 (vld) read access secure control. 1 = selected. 0 : not selected.

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DMC_HCODEC_EF_READ

l

30

0x1c

is

This register contains the HCODEC read security control Bits after the EF got triggered. If the DMC_HCODEC_EF_PROT register Bit 15:0 related bit was
enabled, then the related secure control Bits would be copied to DMC_HCODEC_SEC_READ_CTRL related Bits.

DMC_HCODEC_EF_WRITE

0x1d

D

This register contains the HCODEC write security control Bits after the EF got triggered. If the DMC_HCODEC_EF_PROT register Bit 15:0 related bit was
enabled, then the related secure control Bits would be copied to DMC_HCODEC_SEC_WRITE _CTRL related Bits.

DMC_HEVC_SEC_READ_CTRL

0x1e

Bit(s)
31~18

R/W
R/W

Default
0

Description
Not used.

17

R/W

0

HEVC LMEM secure region read access enable bit. 1: enable. 0 : disable.

16

R/W

0

HEVC LMEM non secure region read access enable bit. 1: enable. 0 : disable.

15

R/W

0

HEVC subid 7( MPRED) secure region read access enable bit. 1: enable. 0 : disable.

14

R/W

0

HEVC subid 7( MPRED) non secure region read access enable bit. 1: enable. 0 : disable..

13

R/W

0

HEVC subid 6(DBLK_D) secure region read access enable bit. 1: enable. 0 : disable.

12

R/W

0

HEVC subid 6(DBLK_D) non secure region read access enable bit. 1: enable. 0 : disable.

11

R/W

0

HEVC subid 5(DBLK_P) secure region read access enable bit. 1: enable. 0 : disable.

10

R/W

0

HEVC subid 5(DBLK_P) non secure region read access enable bit. 1: enable. 0 : disable.

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Bit(s)
9

R/W
R/W

Default
0

Description
HEVC subid 4(IPP)

secure region read access enable bit. 1: enable. 0 : disable.

8

R/W

0

HEVC subid 4(IPP)

non secure region read access enable bit. 1: enable. 0 : disable.

7

R/W

0

HEVC subid 3(MPP)

secure region read access enable bit. 1: enable. 0 : disable.

6

R/W

0

HEVC subid 3(MPP)

non secure region read access enable bit. 1: enable. 0 : disable.

5

R/W

0

HEVC subID2 (SAO)

secure region read access enable bit. 1: enable. 0 : disable.

4

R/W

0

HEVC subID2 (SAO) non secure region read access enable bit. 1: enable. 0 : disable.

3

R/W

0

HEVC subID1 (stream)

2

R/W

0

HEVC subID1 (stream) non secure region read access enable bit. 1: enable. 0 : disable.

1

R/W

0

HEVC subID0 (IMEM)

0

R/W

0

HEVC subID0 (IMEM) non secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

DMC_HEVC_SEC_WRITE_CTRL

0x1f

R/W
R/W

Default
0

Description
Not used.

17

R/W

0

HEVC LMEM secure region read access enable bit. 1: enable. 0 : disable.

17

R/W

0

HEVC LMEM non secure region read access enable bit. 1: enable. 0 : disable.

15

R/W

0

HEVC subid 7( MPRED) secure region read access enable bit. 1: enable. 0 : disable.

14

R/W

0

HEVC subid 7( MPRED) non secure region read access enable bit. 1: enable. 0 : disable..

13

R/W

0

HEVC subid 6(DBLK_D) secure region read access enable bit. 1: enable. 0 : disable.

12

R/W

0

HEVC subid 6(DBLK_D) non secure region read access enable bit. 1: enable. 0 : disable.

11

R/W

0

HEVC subid 5(DBLK_P) secure region read access enable bit. 1: enable. 0 : disable.

10

R/W

0

HEVC subid 5(DBLK_P) non secure region read access enable bit. 1: enable. 0 : disable.

9

R/W

0

HEVC subid 4(IPP)

secure region read access enable bit. 1: enable. 0 : disable.

8

R/W

0

HEVC subid 4(IPP)

non secure region read access enable bit. 1: enable. 0 : disable.

7

R/W

0

HEVC subid 3(MPP)

secure region read access enable bit. 1: enable. 0 : disable.

6

R/W

0

HEVC subid 3(MPP)

non secure region read access enable bit. 1: enable. 0 : disable.

5

R/W

0

HEVC subID2 (SAO)

secure region read access enable bit. 1: enable. 0 : disable.

4

R/W

0

HEVC subID2 (SAO) non secure region read access enable bit. 1: enable. 0 : disable.

3

R/W

0

HEVC subID1 (stream)

2

R/W

0

HEVC subID1 (stream) non secure region read access enable bit. 1: enable. 0 : disable.

1

R/W

0

HEVC subID0 (IMEM)

0

R/W

0

HEVC subID0 (IMEM) non secure region read access enable bit. 1: enable. 0 : disable.

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Bit(s)
31~18

secure region read access enable bit. 1: enable. 0 : disable.

utesecure region read access enable bit. 1: enable. 0 : disable.

DMC_HEVC_SEC_CFG

0x20

0

23

R/W

0

22

R/W

0

21

R/W

0

20

R/W

0

19

R/W

0

18

R/W

0

17

R/W

0

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R/W

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24

D

DWC_HEVC _SEC_READ_CTRL and DMC_HEVC _SEC_WRITE_CTRL register APB bus configuation enable. 2 bit for each port. one for read, one for write.
Bit(s)
R/W Default Description
31~25 R/W
0
Not used
HEVC subID (LMEM) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subid 7( MPRED) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subid 6(DBLK_D) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subid 5(DBLK_P) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subid 4(IPP)
To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subid 3(MPP) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subID2 (SAO) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subID1 (stream) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

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Bit(s)
16

R/W
R/W

Default
0

Description
HEVC subID0 (IMEM) To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

15~9

R/W

0

Not used

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

HEVC subID (LMEM) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
HEVC subid 7( MPRED) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subid 6(DBLK_D) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subid 5(DBLK_P) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

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HEVC subid 4(IPP)
To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subid 3(MPP)
To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subID2 (SAO) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subID1 (stream) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.
HEVC subID0 (IMEM) To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify.
0 : disable APB bus modify.

DMC_HEVC _EF_TRIG_CTRL

0x21

H

ar

HEVC Electronic fence trigger selection and trigger secure type. 1 bit for trigger select for one read port. 1 bit for trigger type for one read port. Electronic
fence would be triggered by the read from defined secure level from selected subIDs
Bit(s)
R/W Default Description
31~25 R/W
0
Not used.
R/W0

trigger type selection for subID LMEM 1 = secure access. 0 : non secure access.

23

R/W

0

trigger type selection for subID7 (MPRED) 1 = secure access. 0 : non secure access

22

R/W

0

trigger type selection for subID6(DBLK_D). 1 = selected. 0 : not selected.

21

R/W

0

trigger type e selection for subID5 (DBLK_P). 1 = selected. 0 : not selected.

20

R/W

0

trigger type selection for subID4 (IPP). 1 = selected. 0 : not selected..

19

R/W

0

trigger type selection for subID3 (MPP). 1 = selected. 0 : not selected..

18

R/W

0

trigger type selection for subID2 (SAO). 1 = selected. 0 : not selected.

17

R/W

0

trigger type selection for subID1 (stream). 1 = selected. 0 : not selected..

16

R/W

0

trigger type selection for subID0 (IMEM). 1 = selected. 0 : not selected..

15~9

R/W

0

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

trigger source selection for subID4 (IPP). 1 = selected. 0 : not selected.

3

R/W

0

trigger source selection for subID3 (MPP). 1 = selected. 0 : not selected.

R/W0

trigger source selection for subID2 (SAO). 1 = selected. 0 : not selected..

Not used.

trigger source selection for subID8 (LMEM). 1 = selected. 0 : not selected.
trigger source selection for subID7 (MPRED). 1 = selected. 0 : not selected.
trigger source selection for subID6 (DBLK_D). 1 = selected. 0 : not selected.
trigger source selection for subID5 (DBLK_P). 1 = selected. 0 : not selected..

1

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24

R/W

0

trigger source selection for subID1 (stream). 1 = selected. 0 : not selected..

0

R/W

0

trigger source selection for subID0 (IMEM). 1 = selected. 0 : not selected.

2

DMC_HEVC _EF_PROT

0x22

To define which subID would be affected after the EF got triggered.
Bit(s)
R/W Default Description
31~25 R/W
0
Not used..
24

R/W

0

EF would affect subID LMEM write access secure control. 1 = selected. 0 : not selected.

23

R/W

0

EF would affect subID7 (mpred) write access secure control. 1 = selected. 0 : not selected.

22

R/W

0

EF would affect subID6 (DBLK_D) write access secure control. 1 = selected. 0 : not selected.

21

R/W

0

EF would affect subID5 (DBLK_P) write access secure control. 1 = selected. 0 : not selected.

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R/W
R/W

Default
0

Description
EF would affect subID4 (IPP) write access secure control. 1 = selected. 0 : not selected.

19

R/W

0

EF would affect subID3 (MPP) write access secure control. 1 = selected. 0 : not selected.

18

R/W

0

EF would affect subID2 (SAO) write access secure control. 1 = selected. 0 : not selected.

17

R/W

0

EF would affect subID1 (STREAM) write access secure control. 1 = selected. 0 : not selected.

16

R/W

0

EF would affect subID0 (IMEM) write access secure control. 1 = selected. 0 : not selected.

15~9

R/W

0

Not used.

8

R/W

0

EF would affect subID8= (LMEM) read access secure control. 1 = selected. 0 : not selected.

7

R/W

0

EF would affect subID7 (MPRED) read access secure control. 1 = selected. 0 : not selected.

6

R/W

0

EF would affect subID6 (DBLK_D) read access secure control. 1 = selected. 0 : not selected.

5

R/W

0

EF would affect subID5 (DBLK_P) read access secure control. 1 = selected. 0 : not selected.

4

R/W

0

EF would affect subID4 (IPP) read access secure control. 1 = selected. 0 : not selected.

3

R/W

0

EF would affect subID3 (MPP) read access secure control. 1 = selected. 0 : not selected.

2

R/W

0

EF would affect subID2 (SAO) read access secure control. 1 = selected. 0 : not selected.

1

R/W

0

EF would affect subID1 (STREAM) read access secure control. 1 = selected. 0 : not selected.

0

R/W

0

EF would affect subID0 (IMEM) read access secure control. 1 = selected. 0 : not selected.

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DMC_HEVC _EF_READlBit(s)
20

This register contains the HEVC read security control Bits after the EF got triggered. If the DMC_HEVC _EF_PROT register bit 8:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_HEVC_SEC_READ_CTRL related Bits.

DMC_HEVC _EF_WRITE

0x24

ar

This register contains the HEVC write security control Bits after the EF got triggered. If the DMC_HEVC _EF_PROT register bit 8:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_HEVC _SEC_WRITE _CTRL related Bits.

0x32

Bit(s)31

R/W
R/W

Default
0

Description
VPU subID15 (RDMA_RD)

30

R/W

0

VPU subID15 (RDMA_RD) non secure region read access enable bit. 1: enable. 0 : disable.

29

R/W

0

VPU subID14 ( not used )

28

R/W

0

VPU subID14 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

27

R/W

0

VPU subID13 ( not used )

26

R/W

0

VPU subID13 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable.

25

R/W

0

VPU subID12 (DI_MISC)

24

R/W

0

VPU subID12 ( DI_MISC ) non secure region read access enable bit. 1: enable. 0 : disable.

23

R/W

0

VPU subID11 (DI_CHAN2)

22

R/W

0

21

R/W

0

20

R/W

0

19

R/W

0

18

R/W

0

VPU subID9(DI_MEM ) non secure region read access enable bit. 1: enable. 0 : disable.

17

R/W

0

VPU subID8 (DI_IF1)

16

D

H

DMC_VPU _SEC_READ_CTRL

R/W

0

VPU subID8 (DI_IF1) non secure region read access enable bit. 1: enable. 0 : disable.

R/W

0

VPU subID7 ()secure region read access enable bit. 1: enable. 0 : disable.

R/W

0

VPU subID7 ()non secure region read access enable bit. 1: enable. 0 : disable..

13

R/W

0

VPU subID6 ()secure region read access enable bit. 1: enable. 0 : disable.

12

R/W

0

VPU subID6 () non secure region read access enable bit. 1: enable. 0 : disable.

11

R/W

0

VPU subID5 ()

10

R/W

0

VPU subID5 () non secure region read access enable bit. 1: enable. 0 : disable.

9

R/W

0

VPU subID4 (AFBC_DEC)

8

R/W

0

VPU subID4 (AFBC_DEC) non secure region read access enable bit. 1: enable. 0 : disable.

7

R/W

0

VPU subID3 (VD2)

6

R/W

0

VPU subID3 (VD2) non secure region read access enable bit. 1: enable. 0 : disable.

5

R/W

0

VPU subID2 (VD1)

4

R/W

0

VPU subID2 (VD1) non secure region read access enable bit. 1: enable. 0 : disable.

15
14

to

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

esecure region read access enable bit. 1: enable. 0 : disable.

is

tr
ib

ut

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

VPU subID11 (DI_CHAN2) non secure region read access enable bit. 1: enable. 0 : disable.
VPU subID10 (DI_INP)

secure region read access enable bit. 1: enable. 0 : disable.

VPU subID10 (DI_INP) non secure region read access enable bit. 1: enable. 0 : disable.
VPU subID9 (DI_MEM) secure region read access enable bit. 1: enable. 0 : disable
secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

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Bit(s)
3

R/W
R/W

Default
0

Description
VPU subID1 (OSD2)

2

R/W

0

VPU subID1 (OSD2) non secure region read access enable bit. 1: enable. 0 : disable.

1

R/W

0

VPU subID0 (OSD1)

0

R/W

0

VPU subID0 (OSD1) non secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

DMC_VPU_SEC_WRITE _CTRL

0x33

Bit(s)31

R/W
R/W

Default
0

Description
VPU subID15 (RDMA_WR)

30

R/W

0

VPU subID15 (RDMA_WR) non secure region write access enable bit. 1: enable. 0 : disable.

29

R/W

0

VPU subID14 ( not used )

28

R/W

0

VPU subID14 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.

27

R/W

0

VPU subID13 ( not used )

26

R/W

0

VPU subID13 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable.

25

R/W

0

VPU subID12 (DI_MISC )

24

R/W

0

VPU subID12 (DI_MISC) non secure region write access enable bit. 1: enable. 0 : disable.

23

R/W

0

VPU subID11 (DI_WR)

22

R/W

0

VPU subID11 (DI_WR) non secure region write access enable bit. 1: enable. 0 : disable.

21

R/W

0

VPU subID10 (NR_WR)

20

R/W

0

VPU subID10 (NR_WR) non secure region write access enable bit. 1: enable. 0 : disable.

19

R/W

0

VPU subID9 (VDIN1)

18

R/W

0

VPU subID9 (VDIN1) non secure region write access enable bit. 1: enable. 0 : disable.

17

R/W

0

VPU subID8 (VDIN0.)

16

R/W

0

VPU subID8 (VDIN0) non secure region write access enable bit. 1: enable. 0 : disable.

15

R/W

0

VPU subID7 ()

14

R/W

0

VPU subID7 () non secure region write access enable bit. 1: enable. 0 : disable..

13

R/W

0

VPU subID6 ()

12

R/W

0

VPU subID6 () non secure region write access enable bit. 1: enable. 0 : disable.

11

R/W

0

VPU subID5 ()

10

R/W

0

VPU subID5 () non secure region write access enable bit. 1: enable. 0 : disable.

9

R/W

0

VPU subID4 ()

8

R/W

0

VPU subID4 () non secure region write access enable bit. 1: enable. 0 : disable.

7

R/W

0

VPU subID3 ()

6

R/W

0

VPU subID3 () non secure region write access enable bit. 1: enable. 0 : disable.

5

R/W

0

VPU subID2 ()

4

R/W

0

VPU subID2 () non secure region write access enable bit. 1: enable. 0 : disable.

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

secure region write access enable bit. 1: enable. 0 : disable.

nesecure region write access enable bit. 1: enable. 0 : disable.

lsecure region write access enable bit. 1: enable. 0 : disable.

dk
ersecure region write access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disablearsecure region write access enable bit. 1: enable. 0 : disable.

Hsecure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

tosecure region write access enable bit. 1: enable. 0 : disable.

esecure region write access enable bit. 1: enable. 0 : disable.

tr
ib

ut

secure region write access enable bit. 1: enable. 0 : disable.

VPU subID1 ()secure region write access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.

VPU subID1 () non secure region write access enable bit. 1: enable. 0 : disable.
VPU subID0 ()secure region write access enable bit. 1: enable. 0 : disable.

is

VPU subID0 () non secure region write access enable bit. 1: enable. 0 : disable.

0x19

D

DMC_VPU_SEC_CFG

secure region write access enable bit. 1: enable. 0 : disable.

DWC_VPU_SEC_READ_CTRL and DMC_VPU_SEC_WRITE_CTRL register APB bus configuation enable. 2 bit for each port. one for read, one for write.
Bit(s)
R/W Default Description
31
R/W
0
VPU subID15 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
30

R/W

0

29

R/W

0

28

R/W

0

27

R/W

0

26

R/W

0

VPU subID14To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID13 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID12 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID11 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID10 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.

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Bit(s)25

R/W
R/W

Default
0

24

R/W

0

23

R/W

0

22

R/W

0

21

R/W

0

20

R/W

0

19

R/W

0

18

R/W

0

17

R/W

0

16

R/W

0

15

R/W

0

VPU subID15 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

14

R/W

0

13

R/W

0

12

R/W

0

11

R/W

0

10

R/W

0

9

R/W

0

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

VPU subID14 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID13 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID12 To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID11 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID10 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID9 ()To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID8 ()To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID7 ()To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID6 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID5 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

4

R/W

0

3

R/W

0

tr
ib

ut

e

to

H

ar

dk
er

ne

l

VPU subID3 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID2 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID1 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID0 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.

D

is

2

R/W

0

1

R/W

0

0

R/W

0

Description
VPU subID9 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID8 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID7 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID6 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID5 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.
VPU subID4 To enable APB bus modifiy the write security control Bits. 1 : eable the APB modify. 0 : disable
APB bus modify.

VPU subID4 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID3 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID2 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID1 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.
VPU subID0 () To enable APB bus modifiy the read security control Bits. 1 : eable the APB modify. 0 :disable APB bus modify.

DMC_VPU_EF0_TRIG_CTRL

0x26

VPU Electronic fence trigger selection and trigger secure type. 1 bit for trigger select for one read port. 1 bit for trigger type for one read port. Electronic
fence would be triggered by the read from defined secure level from selected subIDs
Bit(s)
R/W Default Description
31
R/W
0
trigger type selection for subID15 (). 1 = secure access. 0 : non secure access.

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Default
0

Description
trigger type selection for subID14 (). 1 = secure access. 0 : non secure access.

29

R/W

0

trigger type selection for subID13 (). 1 = secure access. 0 : non secure access

28

R/W

0

trigger type selection for subID12 (). 1 = secure access. 0 : non secure access

27

R/W

0

trigger type selection for subID11 (). 1 = secure access. 0 : non secure access

26

R/W

0

trigger type selection for subID10 (t). 1 = secure access. 0 : non secure access

25

R/W

0

trigger type selection for subID9 (). 1 = secure access. 0 : non secure access

24

R/W

0

trigger type selection for subID8 (). 1 = secure access. 0 : non secure access

23

R/W

0

trigger type selection for subID7 (). 1 = secure access. 0 : non secure access

22

R/W

0

trigger type selection for subID6 (). 1 = secure access. 0 : non secure access

21

R/W

0

trigger type selection for subID5 (). 1 = secure access. 0 : non secure access

20

R/W

0

trigger type selection for subID4 (). 1 = secure access. 0 : non secure access

19

R/W

0

trigger type selection for subID3 (). 1 = secure access. 0 : non secure access

18

R/W

0

trigger type selection for subID2 (). 1 = secure access. 0 : non secure access.

17

R/W

0

trigger type selection for subID1 (). 1 = secure access. 0 : non secure access.

16

R/W

0

trigger type selection for subID0 (). 1 = secure access. 0 : non secure access

15

R/W

0

trigger source selection for subID15 (). 1 = selected. 0 : not selected.

14

R/W

0

trigger source selection for subID14 (). 1 = selected. 0 : not selected.

13

R/W

0

trigger source selection for subID13 (). 1 = selected. 0 : not selected..

12

R/W

0

trigger source selection for subID12 (). 1 = selected. 0 : not selected..

11

R/W

0

trigger source selection for subID11 (). 1 = selected. 0 : not selected.

10

R/W

0

trigger source selection for subID10 (). 1 = selected. 0 : not selected..

9

R/W

0

trigger source selection for subID9 (). 1 = selected. 0 : not selected..

8

R/W

0

trigger source selection for subID8 (). 1 = selected. 0 : not selected.

7

R/W

0

trigger source selection for subID7 (). 1 = selected. 0 : not selected.

6

R/W

0

trigger source selection for subID6 (). 1 = selected. 0 : not selected.

5

R/W

0

trigger source selection for subID5 (). 1 = selected. 0 : not selected..

4

R/W

0

trigger source selection for subID4 (). 1 = selected. 0 : not selected.

3

R/W

0

trigger source selection for subID3 (). 1 = selected. 0 : not selected.

2

R/W

0

trigger source selection for subID2 (). 1 = selected. 0 : not selected..

1

R/W

0

trigger source selection for subID1 (). 1 = selected. 0 : not selected..

0

R/W

0

trigger source selection for subID0 (). 1 = selected. 0 : not selected.

ne

R/W
R/W

e

to

H

ar

dk
er

Bit(s)
30

l

S905 Datasheet

0x27

ut

DMC_VPU_EF0_PROTtrib

To define which subID would be affected after the EF got triggered.
Bit(s)
R/W Default Description
31
R/W
0
EF would affect subID15 () write access secure control. 1 = selected. 0 : not selected. .
R/W

0

29

R/W

0

28

R/W

0

27

R/W

0

26

R/W

0

EF would affect subID10 () write access secure control. 1 = selected. 0 : not selected.

25

R/W

0

EF would affect subID9 () write access secure control. 1 = selected. 0 : not selected.

R/W

0

EF would affect subID8 () write access secure control. 1 = selected. 0 : not selected.

EF would affect subID14 () write access secure control. 1 = selected. 0 : not selected.
EF would affect subID13 () write access secure control. 1 = selected. 0 : not selected.
EF would affect subID12 () write access secure control. 1 = selected. 0 : not selected.
EF would affect subID11 () write access secure control. 1 = selected. 0 : not selected.

23

D

is

30

R/W

0

EF would affect subID7 () write access secure control. 1 = selected. 0 : not selected.

22

R/W

0

EF would affect subID6 () write access secure control. 1 = selected. 0 : not selected.

21

R/W

0

EF would affect subID5 () write access secure control. 1 = selected. 0 : not selected.

20

R/W

0

EF would affect subID4 () write access secure control. 1 = selected. 0 : not selected.

19

R/W

0

EF would affect subID3 () write access secure control. 1 = selected. 0 : not selected.

18

R/W

0

EF would affect subID2 () write access secure control. 1 = selected. 0 : not selected.

17

R/W

0

EF would affect subID1 () write access secure control. 1 = selected. 0 : not selected.

16

R/W

0

EF would affect subID0 () write access secure control. 1 = selected. 0 : not selected.

15

R/W

0

EF would affect subID15 () read access secure control. 1 = selected. 0 : not selected. .

14

R/W

0

EF would affect subID14 () read access secure control. 1 = selected. 0 : not selected.

13

R/W

0

EF would affect subID13 () read access secure control. 1 = selected. 0 : not selected.

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R/W
R/W

Default
0

Description
EF would affect subID12 () read access secure control. 1 = selected. 0 : not selected.

11

R/W

0

EF would affect subID11 () read access secure control. 1 = selected. 0 : not selected.

10

R/W

0

EF would affect subID10 () read access secure control. 1 = selected. 0 : not selected.

9

R/W

0

EF would affect subID9 () read access secure control. 1 = selected. 0 : not selected.

8

R/W

0

EF would affect subID8 () read access secure control. 1 = selected. 0 : not selected.

7

R/W

0

EF would affect subID7 () read access secure control. 1 = selected. 0 : not selected.

6

R/W

0

EF would affect subID6 () read access secure control. 1 = selected. 0 : not selected.

5

R/W

0

EF would affect subID5 () read access secure control. 1 = selected. 0 : not selected.

4

R/W

0

EF would affect subID4 () read access secure control. 1 = selected. 0 : not selected.

3

R/W

0

EF would affect subID3 () read access secure control. 1 = selected. 0 : not selected.

2

R/W

0

EF would affect subID2 ()read access secure control. 1 = selected. 0 : not selected.

1

R/W

0

EF would affect subID1 () read access secure control. 1 = selected. 0 : not selected.

0

R/W

0

EF would affect subID0 () read access secure control. 1 = selected. 0 : not selected.

ne

DMC_VPU_EF0_READlBit(s)
12

0x28

DMC_VPU_EF0_WRITE

0x29

dk
er

This register contains the VPU read security control Bits after the EF got triggered. If the DMC_VPU_EF_PROT register Bit 15:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_VPU_SEC_READ_CTRL related Bits.

arThis register contains the VPU write security control Bits after the EF got triggered. If the DMC_VPU_EF_PROT register Bit 15:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_VPU_SEC_WRITE _CTRL related Bits.

DMC_VPU_EF1_TRIG_CTRL

0x2a

H

VPU Electronic fence trigger selection and trigger secure type. 1 bit for trigger select for one read port. 1 bit for trigger type for one read port. Electronic
fence would be triggered by the read from defined secure level from selected subIDs
Bit(s)
R/W Default Description
31
R/W
0
trigger type selection for subID15 (). 1 = secure access. 0 : non secure access.
R/W0

trigger type selection for subID14 (). 1 = secure access. 0 : non secure access.

29

R/W

0

trigger type selection for subID13 (). 1 = secure access. 0 : non secure access

28

R/W

0

trigger type selection for subID12 (). 1 = secure access. 0 : non secure access

27

R/W

0

trigger type selection for subID11 (). 1 = secure access. 0 : non secure access

26

R/W

0

trigger type selection for subID10 (t). 1 = secure access. 0 : non secure access

25

R/W

0

trigger type selection for subID9 (). 1 = secure access. 0 : non secure access

24

R/W

0

trigger type selection for subID8 (). 1 = secure access. 0 : non secure access

23

R/W

0

trigger type selection for subID7 (). 1 = secure access. 0 : non secure access

22

R/W

0

21

R/W

0

20

R/W

0

19

R/W

0

18

R/W

0

17

R/W

0

trigger type selection for subID1 (). 1 = secure access. 0 : non secure access.

16

R/W

0

trigger type selection for subID0 (). 1 = secure access. 0 : non secure access

R/W

trigger type selection for subID6 (). 1 = secure access. 0 : non secure accesstrigger type selection for subID5 (). 1 = secure access. 0 : non secure accesstrigger type selection for subID4 (). 1 = secure access. 0 : non secure accesstrigger type selection for subID3 (). 1 = secure access. 0 : non secure accesstrigger type selection for subID2 (). 1 = secure access. 0 : non secure access.

0

trigger source selection for subID15 (). 1 = selected. 0 : not selected.

14

D

is

tr
ib

ut

e

to

30

R/W

0

trigger source selection for subID14 (). 1 = selected. 0 : not selected.

13

R/W

0

trigger source selection for subID13 (). 1 = selected. 0 : not selected..

12

R/W

0

trigger source selection for subID12 (). 1 = selected. 0 : not selected..

11

R/W

0

trigger source selection for subID11 (). 1 = selected. 0 : not selected.

10

R/W

0

trigger source selection for subID10 (). 1 = selected. 0 : not selected..

9

R/W

0

trigger source selection for subID9 (). 1 = selected. 0 : not selected..

8

R/W

0

trigger source selection for subID8 (). 1 = selected. 0 : not selected.

7

R/W

0

trigger source selection for subID7 (). 1 = selected. 0 : not selected.

6

R/W

0

trigger source selection for subID6 (). 1 = selected. 0 : not selected.

5

R/W

0

trigger source selection for subID5 (). 1 = selected. 0 : not selected..

4

R/W

0

trigger source selection for subID4 (). 1 = selected. 0 : not selected.

15

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Revision 1.1.4

Bit(s)
3

R/W
R/W

Default
0

Description
trigger source selection for subID3 (). 1 = selected. 0 : not selected.

2

R/W

0

trigger source selection for subID2 (). 1 = selected. 0 : not selected..

1

R/W

0

trigger source selection for subID1 (). 1 = selected. 0 : not selected..

0

R/W

0

trigger source selection for subID0 (). 1 = selected. 0 : not selected.

DMC_VPU_EF1_PROT

0x2b

R/W

0

EF would affect subID14 () write access secure control. 1 = selected. 0 : not selected.

29

R/W

0

EF would affect subID13 () write access secure control. 1 = selected. 0 : not selected.

28

R/W

0

EF would affect subID12 () write access secure control. 1 = selected. 0 : not selected.

27

R/W

0

EF would affect subID11 () write access secure control. 1 = selected. 0 : not selected.

26

R/W

0

EF would affect subID10 () write access secure control. 1 = selected. 0 : not selected.

25

R/W

0

EF would affect subID9 () write access secure control. 1 = selected. 0 : not selected.

24

R/W

0

EF would affect subID8 () write access secure control. 1 = selected. 0 : not selected.

23

R/W

0

EF would affect subID7 () write access secure control. 1 = selected. 0 : not selected.

22

R/W

0

EF would affect subID6 () write access secure control. 1 = selected. 0 : not selected.

21

R/W

0

EF would affect subID5 () write access secure control. 1 = selected. 0 : not selected.

20

R/W

0

EF would affect subID4 () write access secure control. 1 = selected. 0 : not selected.

19

R/W

0

EF would affect subID3 () write access secure control. 1 = selected. 0 : not selected.

18

R/W

0

EF would affect subID2 () write access secure control. 1 = selected. 0 : not selected.

17

R/W

0

EF would affect subID1 () write access secure control. 1 = selected. 0 : not selected.

16

R/W

0

EF would affect subID0 () write access secure control. 1 = selected. 0 : not selected.

15

R/W

0

EF would affect subID15 () read access secure control. 1 = selected. 0 : not selected. .

14

R/W

0

EF would affect subID14 () read access secure control. 1 = selected. 0 : not selected.

13

R/W

0

EF would affect subID13 () read access secure control. 1 = selected. 0 : not selected.

12

R/W

0

EF would affect subID12 () read access secure control. 1 = selected. 0 : not selected.

11

R/W

0

EF would affect subID11 () read access secure control. 1 = selected. 0 : not selected.

10

R/W

0

EF would affect subID10 () read access secure control. 1 = selected. 0 : not selected.

9

R/W

0

EF would affect subID9 () read access secure control. 1 = selected. 0 : not selected.

8

R/W

0

EF would affect subID8 () read access secure control. 1 = selected. 0 : not selected.

7

R/W

0

EF would affect subID7 () read access secure control. 1 = selected. 0 : not selected.

6

R/W

0

EF would affect subID6 () read access secure control. 1 = selected. 0 : not selected.

5

R/W

0

EF would affect subID5 () read access secure control. 1 = selected. 0 : not selected.

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

is

tr
ib

ut

e

to

H

ar

dk
er

ne

30

0

l

To define which subID would be affected after the EF got triggered.
Bit(s)
R/W Default Description
31
R/W
0
EF would affect subID15 () write access secure control. 1 = selected. 0 : not selected. .

EF would affect subID4 () read access secure control. 1 = selected. 0 : not selected.
EF would affect subID3 () read access secure control. 1 = selected. 0 : not selected.
EF would affect subID2 ()read access secure control. 1 = selected. 0 : not selected.
EF would affect subID1 () read access secure control. 1 = selected. 0 : not selected.
EF would affect subID0 () read access secure control. 1 = selected. 0 : not selected.

0x2c

D

DMC_VPU_EF1_READ

This register contains the VPU read security control Bits after the EF got triggered. If the DMC_VPU_EF_PROT register Bit 15:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_VPU_SEC_READ_CTRL related Bits.

DMC_VPU_EF1_WRITE

0x2d

This register contains the VPU write security control Bits after the EF got triggered. If the DMC_VPU_EF_PROT register Bit 15:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_VPU_SEC_WRITE _CTRL related Bits.

DMC_VPU_EF2_TRIG_CTRL

0x2e

VPU Electronic fence trigger selection and trigger secure type. 1 bit for trigger select for one read port. 1 bit for trigger type for one read port. Electronic
fence would be triggered by the read from defined secure level from selected subIDs
Bit(s)
R/W Default Description
31
R/W
0
trigger type selection for subID15 (). 1 = secure access. 0 : non secure access.

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Default
0

Description
trigger type selection for subID14 (). 1 = secure access. 0 : non secure access.

29

R/W

0

trigger type selection for subID13 (). 1 = secure access. 0 : non secure access

28

R/W

0

trigger type selection for subID12 (). 1 = secure access. 0 : non secure access

27

R/W

0

trigger type selection for subID11 (). 1 = secure access. 0 : non secure access

26

R/W

0

trigger type selection for subID10 (t). 1 = secure access. 0 : non secure access

25

R/W

0

trigger type selection for subID9 (). 1 = secure access. 0 : non secure access

24

R/W

0

trigger type selection for subID8 (). 1 = secure access. 0 : non secure access

23

R/W

0

trigger type selection for subID7 (). 1 = secure access. 0 : non secure access

22

R/W

0

trigger type selection for subID6 (). 1 = secure access. 0 : non secure access

21

R/W

0

trigger type selection for subID5 (). 1 = secure access. 0 : non secure access

20

R/W

0

trigger type selection for subID4 (). 1 = secure access. 0 : non secure access

19

R/W

0

trigger type selection for subID3 (). 1 = secure access. 0 : non secure access

18

R/W

0

trigger type selection for subID2 (). 1 = secure access. 0 : non secure access.

17

R/W

0

trigger type selection for subID1 (). 1 = secure access. 0 : non secure access.

16

R/W

0

trigger type selection for subID0 (). 1 = secure access. 0 : non secure access

15

R/W

0

trigger source selection for subID15 (). 1 = selected. 0 : not selected.

14

R/W

0

trigger source selection for subID14 (). 1 = selected. 0 : not selected.

13

R/W

0

trigger source selection for subID13 (). 1 = selected. 0 : not selected..

12

R/W

0

trigger source selection for subID12 (). 1 = selected. 0 : not selected..

11

R/W

0

trigger source selection for subID11 (). 1 = selected. 0 : not selected.

10

R/W

0

trigger source selection for subID10 (). 1 = selected. 0 : not selected..

9

R/W

0

trigger source selection for subID9 (). 1 = selected. 0 : not selected..

8

R/W

0

trigger source selection for subID8 (). 1 = selected. 0 : not selected.

7

R/W

0

trigger source selection for subID7 (). 1 = selected. 0 : not selected.

6

R/W

0

trigger source selection for subID6 (). 1 = selected. 0 : not selected.

5

R/W

0

trigger source selection for subID5 (). 1 = selected. 0 : not selected..

4

R/W

0

trigger source selection for subID4 (). 1 = selected. 0 : not selected.

3

R/W

0

trigger source selection for subID3 (). 1 = selected. 0 : not selected.

2

R/W

0

trigger source selection for subID2 (). 1 = selected. 0 : not selected..

1

R/W

0

trigger source selection for subID1 (). 1 = selected. 0 : not selected..

0

R/W

0

trigger source selection for subID0 (). 1 = selected. 0 : not selected.

ne

R/W
R/W

e

to

H

ar

dk
er

Bit(s)
30

l

S905 Datasheet

0x2f

ut

DMC_VPU_EF2_PROTtrib

To define which subID would be affected after the EF got triggered.
Bit(s)
R/W Default Description
31
R/W
0
EF would affect subID15 () write access secure control. 1 = selected. 0 : not selected. .
R/W

0

29

R/W

0

28

R/W

0

27

R/W

0

26

R/W

0

EF would affect subID10 () write access secure control. 1 = selected. 0 : not selected.

25

R/W

0

EF would affect subID9 () write access secure control. 1 = selected. 0 : not selected.

R/W

0

EF would affect subID8 () write access secure control. 1 = selected. 0 : not selected.

EF would affect subID14 () write access secure control. 1 = selected. 0 : not selected.
EF would affect subID13 () write access secure control. 1 = selected. 0 : not selected.
EF would affect subID12 () write access secure control. 1 = selected. 0 : not selected.
EF would affect subID11 () write access secure control. 1 = selected. 0 : not selected.

23

D

is

30

R/W

0

EF would affect subID7 () write access secure control. 1 = selected. 0 : not selected.

22

R/W

0

EF would affect subID6 () write access secure control. 1 = selected. 0 : not selected.

21

R/W

0

EF would affect subID5 () write access secure control. 1 = selected. 0 : not selected.

20

R/W

0

EF would affect subID4 () write access secure control. 1 = selected. 0 : not selected.

19

R/W

0

EF would affect subID3 () write access secure control. 1 = selected. 0 : not selected.

18

R/W

0

EF would affect subID2 () write access secure control. 1 = selected. 0 : not selected.

17

R/W

0

EF would affect subID1 () write access secure control. 1 = selected. 0 : not selected.

16

R/W

0

EF would affect subID0 () write access secure control. 1 = selected. 0 : not selected.

15

R/W

0

EF would affect subID15 () read access secure control. 1 = selected. 0 : not selected. .

14

R/W

0

EF would affect subID14 () read access secure control. 1 = selected. 0 : not selected.

13

R/W

0

EF would affect subID13 () read access secure control. 1 = selected. 0 : not selected.

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R/W
R/W

Default
0

Description
EF would affect subID12 () read access secure control. 1 = selected. 0 : not selected.

11

R/W

0

EF would affect subID11 () read access secure control. 1 = selected. 0 : not selected.

10

R/W

0

EF would affect subID10 () read access secure control. 1 = selected. 0 : not selected.

9

R/W

0

EF would affect subID9 () read access secure control. 1 = selected. 0 : not selected.

8

R/W

0

EF would affect subID8 () read access secure control. 1 = selected. 0 : not selected.

7

R/W

0

EF would affect subID7 () read access secure control. 1 = selected. 0 : not selected.

6

R/W

0

EF would affect subID6 () read access secure control. 1 = selected. 0 : not selected.

5

R/W

0

EF would affect subID5 () read access secure control. 1 = selected. 0 : not selected.

4

R/W

0

EF would affect subID4 () read access secure control. 1 = selected. 0 : not selected.

3

R/W

0

EF would affect subID3 () read access secure control. 1 = selected. 0 : not selected.

2

R/W

0

EF would affect subID2 ()read access secure control. 1 = selected. 0 : not selected.

1

R/W

0

EF would affect subID1 () read access secure control. 1 = selected. 0 : not selected.

0

R/W

0

EF would affect subID0 () read access secure control. 1 = selected. 0 : not selected.

ne

DMC_VPU_EF2_READlBit(s)
120x30

DMC_VPU_EF2_WRITE

0x31

dk
er

This register contains the VPU read security control Bits after the EF got triggered. If the DMC_VPU_EF_PROT register Bit 15:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_VPU_SEC_READ_CTRL related Bits.

arThis register contains the VPU write security control Bits after the EF got triggered. If the DMC_VPU_EF_PROT register Bit 15:0 related bit was enabled,
then the related secure control Bits would be copied to DMC_VPU_SEC_WRITE _CTRL related Bits.

DMC_GE2D_SEC_CTRL

0x34

H

GE2D is ambus port 7. There’s only 2 read subID and 1 write subID for GE2D ports. Used one
Bit(s)
R/W Default Description
31~22 R/W
0
Not used.
R/W

0

GE2D secure control after EF triggered.

14

R/W

0

GE2D EF protection selection after EF triggered for write.

13

R/W

0

GE2d EF protection selection after EF triggered for source 1

12

R/W

0

GE2d EF protection selection after EF triggered for source 0

11:10

R/W

0

trigger type selection for 2 source. 1 : secure. 0 : unsecure.

9:8

R/W

0

Trigger source selection for 2 source.

7:6

R/W

0

Not used.

5

R/W

0

Secure enable for GE2D write. 1 = enable. 0 = disable.

4

R/W

0

Non-Secure enable for GE2D write. 1 = enable. 0 = disable.

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

tr
ib

ut

e

to

21~16

Secure enable for GE2D read source 1. 1 = enable. 0 = disable.
Non-Secure enable for GE2D read source 1. 1 = enable. 0 = disable.
Secure enable for GE2D read source 0. 1 = enable. 0 = disable.

isNon-Secure enable for GE2D read source 0. 1 = enable. 0 = disable.

DMC_PARSER_SEC_CTRL

0x35

D

Parser is in device port with the subID == 9Bit(s)
R/W Default Description
31~12 R/W
0
Not used.
11:8

R/W

0

Parser write and read security control Bits after EF triggerd.

7

R/W

0

Parser EF protection selection Parser write.

6

R/W

0

Parser EF protection selection for Parser read.

5

R/W

0

Parser EF trigger read type 1 : secure. 0: unsecure.

4

R/W

0

Parser eF trigger read enable. 1 : enable 0 : disable.

3:2

R/W

0

Parser write security control Bits.

1:0

R/W

0

Parser read security control Bits.

DMC_DEVICE_SEC_READ_CTRL
Bit(s)31

R/W
R/W

Default
00x36
Description
DEVICE subID15 ()secure region read access enable bit. 1: enable. 0 : disable.

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Bit(s)30

R/W
R/W

Default
0

Description
DEVICE subID15 (non secure region read access enable bit. 1: enable. 0 : disable.

29

R/W

0

DEVICE subID14 (SANA)

28

R/W

0

DEVICE subID14 (SANA) non secure region read access enable bit. 1: enable. 0 : disable.

27

R/W

0

DEVICE subID13 (ETH)

26

R/W

0

DEVICE subID13 (ETH) non secure region read access enable bit. 1: enable. 0 : disable.

25

R/W

0

DEVICE subID12 (SPICC)

24

R/W

0

DEVICE subID12 (SPICC) non secure region read access enable bit. 1: enable. 0 : disable.

23

R/W

0

DEVICE subID11 (SD_EMMC_C)

22

R/W

0

DEVICE subID11 (SD_EMMC_C) non secure region read access enable bit. 1: enable. 0 : disable.

21

R/W

0

DEVICE subID10 (M3 CPU)

20

R/W

0

DEVICE subID10 (M3 CPU) non secure region read access enable bit. 1: enable. 0 : disable.

19

R/W

0

Not used.

18

R/W

0

Not used.

17

R/W

0

DEVICE subID8 (AIU.)

16

R/W

0

DEVICE subID8 (AIU) non secure region read access enable bit. 1: enable. 0 : disable.

15

R/W

0

DEVICE subID7 (AUDIN)

14

R/W

0

DEVICE subID7 (AUDIN) non secure region read access enable bit. 1: enable. 0 : disable..

13

R/W

0

DEVICE subID6 (AUDOUT)

12

R/W

0

DEVICE subID6 (AUDOUT) non secure region read access enable bit. 1: enable. 0 : disable.

11

R/W

0

DEVICE subID5 (USB1)

10

R/W

0

DEVICE subID5 (USB1) non secure region read access enable bit. 1: enable. 0 : disable.

9

R/W

0

DEVICE subID4 (SD_EMMC_B)

8

R/W

0

DEVICE subID4 (SD_EMMC_B) non secure region read access enable bit. 1: enable. 0 : disable.

7

R/W

0

DEVICE subID3 (ARB0)

6

R/W

0

DEVICE subID3 (ARB0) non secure region read access enable bit. 1: enable. 0 : disable.

5

R/W

0

DEVICE subID2 (BLKMV)

4

R/W

0

DEVICE subID2 (BLKMV) non secure region read access enable bit. 1: enable. 0 : disable.

3

R/W

0

DEVICE subID1 (USB0)

2

R/W

0

DEVICE subID1 (USB0) non secure region read access enable bit. 1: enable. 0 : disable.

1

R/W

0

DEVICE subID0 (SD_EMMC_A)

0

R/W

0

DEVICE subID0 (SD_EMMC_A) non secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

lsecure region read access enable bit. 1: enable. 0 : disable.

nesecure region read access enable bit. 1: enable. 0 : disable.

dk
ersecure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.

secure region read access enable bit. 1: enable. 0 : disable.

arsecure region read access enable bit. 1: enable. 0 : disable.

Hsecure region read access enable bit. 1: enable. 0 : disable.
secure region read access enable bit. 1: enable. 0 : disable.

tosecure region read access enable bit. 1: enable. 0 : disable.

esecure region read access enable bit. 1: enable. 0 : disable.

ut

0x37

R/W
R/W

Default
0

Description
DEVICE subID15 ()

30

R/W

0

DEVICE subID15 (non secure region write access enable bit. 1: enable. 0 : disable.

29

R/W

0

28

R/W

0

27

R/W

0

26

R/W

0

DEVICE subID13 (ETH) non secure region write access enable bit. 1: enable. 0 : disable.

25

R/W

0

DEVICE subID12 (SPICC)

24

R/W

0

DEVICE subID12 (SPICC) non secure region write access enable bit. 1: enable. 0 : disable.

R/W

0

DEVICE subID11 (SD_EMMC_C)

R/W

0

DEVICE subID11 (SD_EMMC_C) non secure region write access enable bit. 1: enable. 0 : disable.

21

R/W

0

DEVICE subID10 (M3 CPU)

20

R/W

0

DEVICE subID10 (M3 CPU) non secure region write access enable bit. 1: enable. 0 : disable.

19

R/W

0

Not used.

18

R/W

0

Not used.

17

R/W

0

DEVICE subID8 (AIU.)

16

R/W

0

DEVICE subID8 (AIU) non secure region write access enable bit. 1: enable. 0 : disable.

15

R/W

0

DEVICE subID7 (AUDIN)

14

R/W

0

DEVICE subID7 (AUDIN) non secure region write access enable bit. 1: enable. 0 : disable..

13

R/W

0

DEVICE subID6 (AUDOUT)

12

R/W

0

DEVICE subID6 (AUDOUT) non secure region write access enable bit. 1: enable. 0 : disable.

23
22

is

tr
ib

Bit(s)
31

D

DMC_DEVICE_SEC_WRITE _CTRL

secure region read access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.

DEVICE subID14 (SANA)

secure region write access enable bit. 1: enable. 0 : disable.

DEVICE subID14 (SANA) non secure region write access enable bit. 1: enable. 0 : disable.
DEVICE subID13 (ETH)

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

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Bit(s)
11

R/W
R/W

Default
0

Description
DEVICE subID5 (USB1)

10

R/W

0

DEVICE subID5 (USB1) non secure region write access enable bit. 1: enable. 0 : disable.

9

R/W

0

DEVICE subID4 (SD_EMMC_B)

8

R/W

0

DEVICE subID4 (SD_EMMC_B) non secure region write access enable bit. 1: enable. 0 : disable.

7

R/W

0

DEVICE subID3 (ARB0)

6

R/W

0

DEVICE subID3 (ARB0) non secure region write access enable bit. 1: enable. 0 : disable.

5

R/W

0

DEVICE subID2 (BLKMV)

4

R/W

0

DEVICE subID2 (BLKMV) non secure region write access enable bit. 1: enable. 0 : disable.

3

R/W

0

DEVICE subID1 (USB0)

2

R/W

0

DEVICE subID1 (USB0) non secure region write access enable bit. 1: enable. 0 : disable.

1

R/W

0

DEVICE subID0 (SD_EMMC_A)

0

R/W

0

DEVICE subID0 (SD_EMMC_A) non secure region write access enable bit. 1: enable. 0 : disable.

Default
0

Description
DES KEY high 32Bits for unsecure region.

Default
0

Description
DES KEY low 32Bits for unsecure region.

Default
0

Description
DES KEY high 32Bits for secure region.

Default
0

Description
DES KEY low 32Bits for secure region.

Default
0

Description
32Bits address padding used for DES data generation.

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.
secure region write access enable bit. 1: enable. 0 : disable.

0x90

R/W
R/W

DMC_DES_KEY0_LO
Bit(s)
31~0

0x91

R/W
R/W

0x92

H

R/W
R/W

0x93

R/W
R/W

to

DMC_DES_KEY1_LO
Bit(s)
31~0

tr
ib

DMC_CA_RMAP_L

ut

R/W
R/W

DMC_CA_RMAP_H

0x9a

e

DMC_DES_PADDING
Bit(s)
31~0

ar

DMC_DES_KEY1_HI
Bit(s)
31~0

ne

Bit(s)
31~0dk
er

DMC_DES_KEY0_HIlsecure region write access enable bit. 1: enable. 0 : disable.

0x9b
0x9c

is

There’s a 4 Bits column address remap for the column address generation. Column address bit 9:6 would be remapped through this table.
Bit(s)
R/W Default Description
63:60
R/W
0
New address for input value 15.
R/W0

New address for input value 14.

55:52

R/W

0

New address for input value 13.

51:48

R/W

0

New address for input value 12.

47:44

R/W

0

New address for input value 11.

43:40

R/W

0

New address for input value 10.

39:36

R/W

0

New address for input value 9.

35:32

R/W

0

New address for input value 8.

31:28

R/W

0

New address for input value 7.

27:24

R/W

0

New address for input value 6.

23:20

R/W

0

New address for input value 5.

19:16

R/W

0

New address for input value 4.

15:12

R/W

0

New address for input value 3.

11:7

R/W

0

New address for input value 2.

7:4

R/W

0

New address for input value 1.

3:0

R/W

0

New address for input value 0.

D

59:56

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S905 Datasheet

Revision 1.1.4

DMC_PROT0_RANGE

0xa0

protection 0 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address.
Bit(s)
R/W Default Description
31:16
R/W
0
Range end address
R/W

0

Range start address

Bit(s)
31:20

R/W
R/W

Default
0

Description
Not used.

19

R/W

0

protection 0 for write access enable bit.

18

R/W

0

protection 0 for read access enable bit.

17

R/W

0

protection 0 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if notenabled only generate a interrupt, but the access still wrote to DDR.

16

R/W

0

Not used.

15:0

R/W

0

Each Bit to enable one of the 16 ports for the protection function.

0xa1

DMC_PROT1_RANGE

0xa2

l

DMC_PROT0_CTRL

ne

15:0

R/W

0

Range start address

DMC_PROT1_CTRL

0xa3

ar

15:0

dk
er

protection 1 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address.
Bit(s)
R/W Default Description
31:16
R/W
0
Range end address

R/W
R/W

Default
0

Description
Not used.

19

R/W

0

protection 1 for write access enable bit.

18

R/W

0

protection 1 for read access enable bit.

17

R/W

0

protection 1 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if notenabled only generate a interrupt, but the access still wrote to DDR.

16

R/W

0

Not used.

15:0

R/W

0

Each Bit to enable one of the 16 ports for the protection function.

e

to

H

Bit(s)
31:20

0xa4

ut

DMC_WTCH0_D0

0xa5

tr
ib

DMC_WTCH0_D1
DMC_WTCH0_D2
DMC_WTCH0_D3

0xa6
0xa7

is

WTCH0 will watch upto 128Bits data access {d3, d2,d1,d0}

DMC_WTCH0_RANGE

0xa8

R/W
R/W

Default
0

Description
Range end address

15:0

R/W

0

Range start addressD

Bit(s)
31:16

DMC_WATCH0_CTRL

0xa9

Bit(s)
31:16

R/W
R/W

Default
0

Description
16Bits write data strb

15:0

R/W

0

16Bits input ports selectDMC_WATCH0_CTRL1

0xaa

Bit(s)
31:3

R/W
R/W

Default
0

Description
Not used

2

R/W

0

watch point 0 enable.

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Bit(s)
1:0

Revision 1.1.4

R/W
R/W

Default
0

Description
watch point0 type. 2'b00 : double bytes. only watchpoint data 15:0 and data strb 1:0 is valid. 2'b01: 4
bytes. 2'b10: 8 bytes. 2'b11, all 16bytes.

DMC_WTCH1_D0

0xab

DMC_WTCH1_D1

0xac

DMC_WTCH1_D2

0xad

DMC_WTCH1_D3

0xae

WTCH0 will watch upto 128Bits data access {d3, d2,d1,d0}

Default
0

Description
Range end address

15:0

R/W

0

Range start address

DMC_WATCH1_CTRL

0xb0

R/W
R/W

Default
0

Description
16Bits write data strb

15:0

R/W

0

16Bits input ports selectarBit(s)
31:16

dk
er

R/W
R/W

l

0xaf

Bit(s)
31:16

ne

DMC_WTCH1_RANGE

DMC_WATCH0=1_CTRL1

0xb1

R/W
R/W

Default
0

Description
Not used

2

R/W

0

watch point 1 enable.

1:0

R/W

0

watch point1 type. 2'b00 : double bytes. only watchpoint data 15:0 and data strb 1:0 is valid. 2'b01: 4
bytes. 2'b10: 8 bytes. 2'b11, all 16bytes.

toH

Bit(s)
31:3

e

DMC_TRAP0 _RANGE

0xb2

ut

trap function: all read access with predefined PORT or SubIDs must be in the predefine range. Other wire the read accesswould be blocked. And an error will be generated.
R/W
R/W

Default
0

Description
Range end address

15:0

R/W

0

Range start address

0xb3

R/W
R/W

Default
0

Description
Not used.

30

R/W

0

Trap0 port ID 2 selection enable.

29

R/W

0

Trap0 port ID 1 selection enable.

R/W0

Trap0 port ID 0 selection enable.

R/W0

Trap0 port ID 2 subID selection enable.

26

R/W

0

Trap0 port ID 1 subID selection enable.

25

R/W

0

Trap0 port ID 0 subID selection enable.

23~20

R/W

0

Trap0 port port ID2 ID number.

19~16

R/W

0

Trap0 port port ID1 ID number.

15~12

R/W

0

Trap0 port port ID0 ID number.

11~8

R/W

0

Trap0 port port ID2 subID number.

7~4

R/W

0

Trap0 port port ID1 subID number.

3~0

R/W

0

Trap0 port port ID0 subID number.

28
27

is

Bit(s)
31

D

DMC_TRAP0 _CTRLtrib

Bit(s)
31:16

DMC_TRAP1 _RANGE

0xb4

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trap function: all read access with predefined PORT or SubIDs must be in the predefine range. Other wire the read accesswould be blocked. And an error will be generated.
Bit(s)
31:16

R/W
R/W

Default
0

Description
Range end address

15:0

R/W

0

Range start address

DMC_TRAP1 _CTRL

0xb5

R/W
R/W

Default
0

Description
Not used.

30

R/W

0

Trap1 port ID 2 selection enable.

29

R/W

0

Trap1 port ID 1 selection enable.

28

R/W

0

Trap1 port ID 0 selection enable.

27

R/W

0

Trap1 port ID 2 subID selection enable.

26

R/W

0

Trap1 port ID 1 subID selection enable.

25

R/W

0

Trap1 port ID 0 subID selection enable.

23~20

R/W

0

Trap1 port port ID2 ID number.

19~16

R/W

0

Trap1 port port ID1 ID number.

15~12

R/W

0

Trap1 port port ID0 ID number.

11~8

R/W

0

Trap1 port port ID2 subID number.

7~4

R/W

0

Trap1 port port ID1 subID number.

3~0

R/W

0

Trap1 port port ID0 subID number.

Bit(s)
31~4

R/W
R/W

Default
0

Description
Not used.

3

R/W

0

DDR channel 1 write secure violation.(secure, address over DDR size, trap violation, protection violation)

29

R/W

0

DDR channel 1 read secure violation.

28

R/W

0

DDR channel 0 write secure violation.

27

R/W

0

DDR channel 0 read secure violation.

R/W
R/W

Default
0

Description
DDR channel 0 write secure violation address.

Bit(s)
31~23

R/W
R/W

Default
0

Description
Not used.

22

R/W

0

DDR channel 0 write secure check violation.

21

R/W

0

20

R/W

0

19

R/W

0

DDR channel 0 write watch 1 catch.

18

R/W

0

DDR channel 0 write watch 0 catch.

17

R/W

0

DDR channel 0 write address overflow. Write out of DDR size.

R/W

0

DDR channel 0 write violation AWPROT Bits.

R/W

0

DDR channel 0 write violation access ID.

R/W
R/W

Default
0

Description
DDR channel 1 write secure violation address.

Bit(s)
31~23

R/W
R/W

Default
0

Description
Not used.

22

R/W

0

DDR channel 1 write secure check violation.

21

R/W

0

DDR channel 1 write protection 1 violation.

0xb6

is

D

ut

0xb8

tr
ib

DMC_VIO_ADDR1

16~14
/13~0

H

to

0xb7

e

DMC_VIO_ADDR0
Bit(s)
31~0

ar

DMC_SEC_STATUS

DDR channel 0 write protection 1 violation.
DDR Channel 0 write protection 0 vilation.

DMC_VIO_ADDR2
Bit(s)
31~0

dk
er

ne

l

Bit(s)
31

0xb9

DMC_VIO_ADDR3

0xba

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Bit(s)
20

R/W
R/W

Default
0

Description
DDR Channel 1 write protection 0 vilation.

19

R/W

0

DDR channel 1 write watch 1 catch.

18

R/W

0

DDR channel 1 write watch 0 catch.

17

R/W

0

DDR channel 1 write address overflow. Write out of DDR size.

16~14
/13~0

R/W

0

DDR channel 1 write violation AWPROT Bits.

R/W

0

DDR channel 1 write violation access ID.

DMC_VIO_ADDR4
Bit(s)
31~0

0xbb
R/W
R/W

Default
0

Description
DDR channel 0 read secure violation address.

DMC_VIO_ADDR5

0xbc
R/W
R/W

Default
0

Description
Not used.

22

R/W

0

DDR channel 0 read secure check violation.

21

R/W

0

DDR channel 0 read protection 1 violation.

20

R/W

0

DDR Channel 0 read protection 0 vilation.

19

R/W

0

DDR channel 0 read trap1 violation

18

R/W

0

DDR channel 0 read trap 0 violation..

17

R/W

0

DDR channel 0 read address overflow. Write out of DDR size.

16~14
/13~0

R/W

0

DDR channel 0 read violation ARPROT Bits.

R/W

0

DDR channel 0 read violation access ID.

dk
er

ar

DMC_VIO_ADDR6

0xbd

R/W
R/W

Default
0

Description
DDR channel 1 read secure violation address.

H

Bit(s)31~0nelBit(s)
31~23

0xbe

to

DMC_VIO_ADDR7
R/W
R/W

Default
0

Description
Not used.

22

R/W

0

DDR channel 1 readsecure check violation.

21

R/W

0

DDR channel 1 read protection 1 violation.

20

R/W

0

DDR Channel 1 read protection 0 violation.

19

R/W

0

DDR channel 1 read trap1 violation..

18

R/W

0

DDR channel 1 read trap 0 violation. .

17

R/W

0

16~14
/13~0

R/W

0

R/W

0

ut

tr
ib

DDR channel 1 read address overflow. Write out of DDR size.
DDR channel 1 read violation AWPROT Bits.
DDR channel 1 read violation access ID.

is

DDR0_ADDRMAP_4e

Bit(s)
31~23

0xd4

D

For DDR channel 0, row, bank and rank address can be selected from any one of 32Bits linear address.
Since the DDR is at least 16Bits. So bit 0 of the 32Bits linear address is never used. So in this address map, if the value = 0, we’lltreat This bit is not used.
Because we used the burst 8 for DDR3/LPDDR3/LPDDR2, so the column address[2:0] would be always 0.
Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29~25

R/W

30

rank select..

24~20

R/W

0

Bank address 3 (not used in DDR3/LPDDR3).

19~15

R/W

29

Bank address 2

14~10

R/W

13

Bank address 1

9~5

R/W

12

Bank address 0

4~0

R/W

0

Row address Bit 15.

DDR0_ADDRMAP_3

0xd3

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Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29~25

R/W

28

Row address bit 14.

24~20

R/W

27

Row address bit 13.

19~15

R/W

26

Row address bit 12.

14~10

R/W

25

Row address bit 11.

9~5

R/W

24

Row address bit 10.

4~0

R/W

23

Row address bit 9..

0xd2
Default
0

Description
Not used.

29~25

R/W

22

Row address bit 8.

24~20

R/W

21

Row address bit 7.

19~15

R/W

20

Row address bit 16.

14~10

R/W

19

Row address bit 5.

9~5

R/W

18

Row address bit 4.

4~0

R/W

17

Row address bit 3.

ne

R/W
R/W

0xd1
Default
0

Description
Not used.

29~25

R/W

16

Row address bit 2.

24~20

R/W

15

Row address bit 1.

19~15

R/W

14

Row address bit 0.

14~10

R/W

0

Column address bit 11.

9~5

R/W

0

Column address bit 10.

4~0

R/W

11

Column address bit 9.

H

R/W
R/W

to

Bit(s)
31~30

ar

DDR0_ADDRMAP_1dker

Bit(s)
31~30

l

DDR0_ADDRMAP_2

DDR0_ADDRMAP_0

0xd0

R/W
R/W

Default
0

Description
Not used.

29~25

R/W

10

Column address bit 8.

24~20

R/W

9

Column address bit 7.

19~15

R/W

8

Column address bit 6.

14~10

R/W

7

Column address bit 5.

9~5

R/W

6

4~0

R/W

5

ut

tr
ib

DDR1_ADDRMAP_4e

Bit(s)
31~30

Column address bit 4..
Column address bit 3..

0xd9

R/W
R/W

Default
0

Description
Not used.

29~25

R/W

30

rank select..

24~20

R/W

0

Bank address 3 (not used in DDR3/LPDDR3).

19~15

R/W

29

Bank address 2

14~10

R/W

13

Bank address 1

9~5

R/W

12

Bank address 0

4~0

R/W

0

Row address Bit 15.

DisBit(s)
31~30

DDR1_ADDRMAP_3

0xd8

Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29~25

R/W

28

Row address bit 14.

24~20

R/W

27

Row address bit 13.

19~15

R/W

26

Row address bit 12.

14~10

R/W

25

Row address bit 11.

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Bit(s)
9~5

R/W
R/W

Default
24

Description
Row address bit 10.

4~0

R/W

23

Row address bit 9..

0xd7

Bit(s)
31~30

R/W
R/W

Default
0

Description
Not used.

29~25

R/W

22

Row address bit 8.

24~20

R/W

21

Row address bit 7.

19~15

R/W

20

Row address bit 16.

14~10

R/W

19

Row address bit 5.

9~5

R/W

18

Row address bit 4.

4~0

R/W

17

Row address bit 3.

R/W
R/W

Default
0

Description
Not used.

29~25

R/W

16

Row address bit 2.

24~20

R/W

15

Row address bit 1.

19~15

R/W

14

Row address bit 0.

14~10

R/W

0

Column address bit 11.

9~5

R/W

0

Column address bit 10.

4~0

R/W

11

Column address bit 9.

0xd5

R/W
R/W

Default
0

Description
Not used.

29~25

R/W

10

Column address bit 8.

24~20

R/W

9

Column address bit 7.

19~15

R/W

8

Column address bit 6.

14~10

R/W

7

Column address bit 5.

9~5

R/W

6

Column address bit 4..

4~0

R/W

4

Column address bit 3..

Bit(s)
31~23

R/W
R/W

Default
0

Description
Not used.

22

R/W

0

21

R/W

0

rank1 is same as rank0. only in not shared-AC mdoe. and chan0 second rank not selected. that's means
still in rank0 32Bits mode.
channel0 second rank selection enable. only in not shared-AC mode.

20

R/W

0

19

R/W

0

bit 19: DDR channel 1 16Bits data interface. 1 : 16Bits data inteface. 0 : 32Bits data interface . always 0.

18

R/W

0

bit 18: DDR channel 0 16Bits data interface.1 : 16Bits data inteface. 0 : 32Bits data interface. always 0

17

R/W

0

for DDR channel 1. 1: only use 16Bits data in a 32Bits phy data interface. 0: normal 32Bits data interface.

16

R/W

0

for DDR channel 0. 1 only use 16Bits data in a 32Bits phy data interface. 0 : normal data interface.

15~11

R/W

0

Not used.

0xda

is

tr
ib

DMC_DDR_CTRL

ut

e

to

H

Bit(s)
31~30

D

DDR1_ADDRMAP_0

ar

Bit(s)
31~30

ne

0xd6

dk
er

DDR1_ADDRMAP_1l

DDR1_ADDRMAP_2

Shared AC mode.

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R/W
R/W

Default
0

Description
Channel select bit for shared_ac_mode. We can select one of linear address Bits 15 to 8 for the DDR
channel select Bits.
3’b000: use bit8 for the channel select. bit 8 = 0 this access goes to channel 0. bit 8 = 1, this access goesto channel 1.
3’b001: use bit9 for the channel select. bit 9 = 0 this access goes to channel 0. bit 9 = 1, this access goes tochannel 1.
3’b010: use bit10 for the channel select. bit 10 = 0 this access goes to channel 0. bit 10 = 1, this accessgoes to channel 1.
3’b011: use bit11 for the channel select. bit 11 = 0 this access goes to channel 0. bit 11 = 1, this accessgoes to channel 1.
3’b100: use bit12 for the channel select. bit 12 = 0 this access goes to channel 0. bit 12 = 1, this accessgoes to channel 1.
3’b101: use bit13 for the channel select. bit 13 = 0 this access goes to channel 0. bit 13 = 1, this accessgoes to channel 1.
3’b110: use bit14 for the channel select. bit 14 = 0 this access goes to channel 0. bit 14 = 1, this accessgoes to channel 1.
3’b111: use Bit 15 for the channel select. bit 15 = 0 this access goes to channel 0. bit 15 = 1, this accessgoes to channel 1.
If (ddr0_size != ddr1_size && linear address <= 2*(minimum(ddr1_size, ddr0_size) ) || ddr0_size ==ddr1_size ) use this channel select bit to select this address goes to DDR0 or DDR1.
Else if ( ddr0_size != ddr1_size && linear address > 2*(minimum(ddr1_size, ddr0_size)))
This access goes to the ddr channel with bigger size.

7

R/W

0

DDR1_ONLY. 1: DDR channel 1 only. when both channel 0 and 1 in the design. 0 : normal.

6

R/W

0

DDR0_ONLY. 1: DDR channel 0 only. when both channel 0 and 1 in the design. 0 : normal.

5~3

R/W

0

DDR channel 1 size.
3’b000: DDR channel 1 : 128Mbyte.
3’b001: DDR channel 1 : 256Mbyte.
3’b010: DDR channel 1 : 512Mbyte.
3’b011: DDR channel 1 : 1GMbyte.
3’b100: DDR channel 1 : 2GMbyte.

2~0

R/W

0

DDR channel 0 size.
3’b000: DDR channel 0 : 128Mbyte.
3’b001: DDR channel 0 : 256Mbyte.
3’b010: DDR channel 0 : 512Mbyte.
3’b011: DDR channel 0 : 1GMbyte.
3’b100: DDR channel 0 : 2GMbyte.

trib

DMC DDR Channel 0 DRAM register.

ut

e

to

H

ar

dk
er

ne

l

Bit(s)
10~8

Base address 0xc8839000.

DMC DDR Channel 1 DRAM register.

isBase address 0xc8839400.

D

MMC DDR PHY control register.
Base address 0xc8836800.
AM_DDR_PLL_CNTL

0x0

Bit(s)
31

R/W
R

Default
0

Description
PLL lock status

30

R/W

0

PLL power down. 1 = PLL power down. 0 = PLL enable.

29

R/W

0

PLL reset.

28

R/W

0

SSEN

27~24

R/W

0

SS_AMP

23~20

R/W

0

SS_CLK

17~16

R/W

0

OD.

15~14

R/W

0

OD1

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Bit(s)
13~9

R/W
R/W

Default
0

Description
N

8~0

R/W

0

M.

AM_DDR_PLL_CNTL1

0x1

R/W
R/W

Default
0

Description
DPLL_LM_W

27~22

R/W

0

DPLL_LM_S

21

R/W

0

DPFD_LMODE

20~19

R/W

0

DC_VC_IN

18~17

R/W

0

DCO_SDMCK_SEL

16

R/W

0

DCO_M_EN

15

R/W

0

SDM_PR_EN.

14

R/W

0

DIV_MODE

13~2

R/W

0

DIV_FRAC

1

R/W

0

AFC_DSEL_BYPASS.

0

R/W

0

AFC_DSEL_IN

dk
er

ne

l

Bit(s)
31~28

0x2

R/W
R/W

Default
0

Description
Not used.

29~26

R/W

0

FILTER_PVT2.

25~22

R/W

0

FILTER PVT1

21~11

R/W

0

FILTER ACQ2

10~0

R/W

0

FILTER ACQ1

H

Bit(s)
31~30

ar

AM_DDR_PLL_CNTL2

Default
0

Description
DPLL_REVE

13~6

R/W

0

TDC_BUF.

5

R/W

0

PVT_FIX_EN.

4~3

R/W

0

DCO_IUP

2

R/W

0

IIR_BYPASS_N.

1

R/W

0

TDC_EN0

R/W

0

Not used.

tr
ib

R/W
R/W

Description
Not used.

21~20

R/W

19~14

R/W

0

DPLL_CLK_EN

0

13

Not used.

R/W

0

DCO_SDM_EN

D

Bit(s)
31~22

12

Default0is

AM_DDR_PLL_CNTL4

0x3

e

R/W
R/W

ut

Bit(s)
31~20

toAM_DDR_PLL_CNTL3

R/W

0

BGP_EN.

11~8

R/W

0

GPB_C

7~0

R/W

0

Not used.

Bit(s)31

R/W
R/W

Default
0

Description
DDR_PLL_LOCK

30~9

R/W

0

Not used.

8~1

R/W

0

DPLL_OUT_RSV

0

R/W

0

AFC_DONE

0xc8836810

AM_DDR_PLL_STS

0xc8836814

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DDR_CLK_CNTL

0xc8836818

Bit(s)31

R/W
R/W

Default
0

Description
ddr_pll_clk enable. enable the clock from DDR_PLL to clock generation. whenever change the DDR_PLL
frequency, disable the clock, after the DDR_PLL locked, then enable it again..

30

R/W

0

29

R/W

0

ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement andproduction test pin.
ddr_phy_ctl_clk
enable28

R/W

0clock generation logic soft reset. 0 = reset.

27

R/W

0

phy_4xclk phase inverter..

26
25~0

R/W
R/W

0
0

pll_freq divide/2. 1: use pll div/2 clock as the n_clk. 0: use pll clock as n_clk.
Not used.

DDR0_CLK_CNTL

0xc8836c00
R/W
R/W

Default
0

Description
Not used

3

R/W

0

force to disable PUB PCLK.production test pin.

2

R/W

0

PUB auto ctrl n_clk clock gating enable. when the DFI_LP_REQ and DFI_LP_ACK detected , auto gated PUB
n_clk.

1

R/W

0

force to disable PUB PCLK.

0

R/W

0

PUB pclk auto clock gating enable. when the IP detected PCTL enter power down mode, use This bit togating pub pclk.

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Bit(s)
31~4

ar

DDR0_SOFT_RESET
R/W
R/W

Default
0

Description
Not used

3

R/W

0

PUB n_CLK domain soft reset. 1 : reset. 0 normal.

2

R/W

0

PUB p_CLk domain soft reset. 1: reset. 0 normal.

1

R/W

0

Not used.

0

R/W

0

Not used.

0xc8836c08e

DDR0_APD_CTRL

toH

Bit(s)
31~4

0xc8836c04

R/W
R/W

Default
0

Description
Not used

15~8

R/W

0

power down enter latency. when IP checked the dfi_lp_req && dfi_lp_ack, give PCTL and pub additional
latency let them settle down, then gating the clock.

7~0

R/W

0

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Bit(s)
31~16

isno active latency. after c_active_in become to low, wait additional latency to check the pctl low powerstate.

D

DDR PHY PUB register.

Base address 0xc8836000. Please refer dwc_ddr_multiphy_g2_pubm2_databook.pdf.

33. NAND
33.1 Overview
S905 supports SLC/MLC/TLC NAND Flash with 60-bit ECC.

33.2 Register Definitions
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The base address of NAND registers is 0xd0074000, and the final address of each register is listed below:

Table VI.33.1 NAND Register List
Description

Address

R/W

P_NAND_CMD

Write Command and Read Status

Base + 0x00

R/W

P_NAND_CFG

Configuration

Base + 0x04

R/W

P_NAND_DADR

Data Address

Base + 0x08

R/W

P_NAND_IADR

Information Address

Base + 0x0c

R/W

P_NAND_BUF

Read Data Buffer

Base + 0x10

R

P_NAND_INFOInformation

Base + 0x14

R

P_NAND_DC

DDR interface

Base + 0x18

R

P_NAND_ADR

DDR Address

Base + 0x1c

R

P_NAND_DL

DDR Low 32 Bits Data

Base + 0x20

R/W

P_NAND_DH

DDR High 32 Bits Data

Base + 0x24

R/W

P_NAND_CADR

Command Queus Address

Base + 0x28

R/W

P_NAND_SADR

Status Address

Base + 0x2c

R/W

P_NAND_PINS

CS2: SDRAM/NAND pin sharing

Base + 0x30

R/W

P_NAND_VER

Version number

Base + 0x38

R

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Register Name

P_NAND_CMD
Name
Cmd
Cmd_go31

Cmd_reset

Description
NAND command sent to NAND queue buffer
When 1, and NAND bus is in waiting Rb mode, due to time out or longer than expected Rb
waiting, the command queue will move on by disable RB waiting in current command.
When 1 the NAND command queue buffer is reset to zero.

toBit(s)
21:0
30

H

Write : Send NAND command to controller, the command format is specified in previous section.

P_NAND_CFG
Bit(s)
4:0

Name
Bus_cyc

9:5

Bus_tim

11:10

Sync

12

Cmd_start

ut

Description
NAND command current on NAND bus, still going, not finished.
Number of NAND commands still in NAND command queue buffer, the buffer size is 32.
When 1 wait Rb command timed out.
Current Rb0 status, 1: ready, 0: busy.
Current Rb1 status, 1: ready, 0: busy.
Current Rb2 status, 1: ready, 0: busy.
Current Rb3 status, 1: ready, 0: busy.
When 1, DDR interface is idle and ready to accept memory movement request.
When 1, ECC BCH encoder/decoder is idle and read to accept encode or decode activity.

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Name
Cmd_curr
Cmd_cnt
Timer out
Rb0
Rb1
Rb2
Rb3
Mem_rdyEcc_rdyD

Bit(s)
19:0
24:20
25
26
27
28
29
30
31

e

Read : Read NAND controller status

Description
The number of system clock cycles in one NAND cycle – 1, for example, if the bus_cyc is 3, thenthe NAND cycle is 4 system clock cycles, the minimum setting is 3, the maximum setting is 31.
program this register according NAND timing mode.
The timing to lock the NAND data when read NAND data or status, please refer to “Timing
Calculator” for details.
00: Async mode
01: Micron Sync mode
10: Toshiba-Samsung toggle mode
When set to “1”, if the NAND controller internal 32 command buffer has less than 16
commands, the command DMA starts reading commands from DDR and saves them to internalbuffer, the DMA keeps watching the internal buffer, reads whenever there are less than 16
commands left, if an all “zero” command is met, This bit is cleared and current command DMA
is done.

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Cmd_auto

14

Apb_mode

15

Spare_only

16

Sync_adj

20
21
26

Sts_irq_en
Cmd_irq_en
Oob_on27

Oob_mode28
29

Dc_ugtNand_wpn

30

Core_power31

Top_power

When set to ‘1’, the command DMA will check the previous command queue end location,
whether it is changed from all “zero” back to valid command, the auto check period is 1 ms.
Special NAND mode for ROM boot or debug, when 1, DDR interface is redirected to APB register,
all the read/write activities are through APB registers. When used in ROM boot and DDR is notready.
When 1, the NAND controller read NAND with/without ECC, but only save the information bytes
into DDR memory, the main data is discarded, designed for software to survey the NAND flash
spare bytes and prepare NAND programming.
Used to adjust data timing in sync or toggle mode, 0: default timing, 1: delay 1 system clock
cycle.
Enable STS IRQ.
Enable RB pin or RB IO IRQ.
Set to 1 oob_mode 16/0,
Set to 0 no oob bytes.
New in M8 v2,
Set to 1 enable new oob mode.
First page 16 bytes, all other pages 0 byte.
Set NAND controller DDR interface to Urgent mode.
When 1, the NAND wpn pin is set to low, the NAND is in write protection mode, default to 0, the
NAND is not protected.
When 1, internal NAND controller core clock gating is override to always on. The clock gating is
disabled.
When 1, internal NAND top clock gating is override to always on, the clock gating for top is
disabled.

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13

P_NAND_DADRH

arSet DDR data address by registers, the address is 32 Bits, since the DDR data address can also be set by NAND commands, whenboth happens at the same time, register setting is ignored, the NAND command setting takes effect. Software should avoid
conflict address setting.

to

P_NAND_IADRe

Set DDR information (spare bytes) address by registers, the address is 32 Bits, since the DDR information address can also be
set by NAND commands, when both happens at the same time, register setting is ignored, the NAND command setting takes
effect. Software should avoid conflict address setting.

ut

P_NAND_BUF

P_NAND_INFO

trib

When read NAND status, features or data, the results are buffer in this register, the register is 32 Bits, it can only hold 4 bytes,
if the host not doesn’t read out the results, it will be over written by the following “read”.

One 32 Bits information per each 512 bytes in ECC mode.

28:24
29
30
31

is

Name
Info 0
Info 1
Pages

D

Bit(s)
7:0
15:8
21:16

Errcnt
Unc
Ecc
Done

Description
Information (spare) byte 0, errors already corrected by BCH.
Information (spare) byte 1, errors already corrected by BCH
Count down page number in current DMA read, starts from the total page size, count down to1.
Number of errors corrected by BCH in current page, 0 means no error in current page, 0x1f
means this page is uncorrectable.
When 1, this page is uncorrectable by BCH, this page is bad.
When 1, current NAND read is with ECC on.
When 1, the information content and data read from NAND are valid, otherwise the “read” isnot done.

P_NAND_DC
Used for apb_mode, internal NAND controller still uses DDR interface, only the DDR request and DDR grant are redirected from
DDR to apb registers, this enables the host to read NAND without DDR, for ROM boot and debug.
Bit(s)

Name

Description

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7:0
8
9
10

Dc_wr_dm
Dc_wr
Dc_lbrst
Dc_ugt11

Dc_req

DDR write data mask, Each Bit masks one byte.
When 1, write data from NAND to DDR. When 0, read data from DDR to NAND.
When 1, the 64 Bits data is the last in current DDR burst, used with Dc_req.
When 1, current DDR request of read/write is urgent, in NAND controller, the Dc_ugt is set to 0,
none-urgent.
When 1, the NAND controller send request to DDR to read or write data, in case of apb_mode,
when dc_req is “1”, the host is responsible for send to or receive from NAND controller.
Note: this is the only signal the host needs to check when in apb_mode.

P_NAND_ADR
32 Bits DDR address when NAND controller read or write to DDR memory, any address space within the DDR memory installedin the system is valid.

dker

P_NAND_DHne

The DDR interface uses 64 Bits width bus, this register is for low 32 Bits, [31:0].

l

P_NAND_DL

The DDR interface uses 64 Bits width bus, this register is for high 32 Bits, [63:32].
Read and write to this register will generate “grant” and “dc_wr_avail” or “dc_rd_avail”.

H

to

NAND controller programs NAND flash in apb_mode: Check P_NAND_DC till “dc_req” is high.
 Write low 32 Bits to P_NAND_DL.
 Write high 32 Bits to P_NAND_DH.
 Go back to beginning till all the data is written.

ar

Always read or write low 32 Bits first, then read or write to high 32 Bits and NAND controller hardware will generate “grant”
and “dc_wr_avail” or “dc_rd_avail”, combined with the data, the DDR address advances to next address.

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e

NAND controller reads data from NAND flash in apb_mode: Check P_NAND_DC till “dc_req” is high.
 Read low 32 Bits from P_NAND_DL.
 Read high 32 Bits from P_NAND_DH.
 Go back to beginning till all the data is read.

P_NAND_CADR

isSince the DDR interface in NAND controller process the data in group of 16 double words (64 Bits), the software can only check“dc_req” at the beginning of each 16 double words.

D

Set command queue memory address, 32 Bits, any memory location.
This address can only be programmed by APB bus.
P_NAND_SADR

Set status memory location, 32 Bits, any memory location.
This address can also be programmed through command queue.
P_NAND_PINS
Bit(s)
13:0

Name
Pins_len27:14

Pins_off31

Not shared

Description
When pins are acquired by NAND, it will use Pins_len number of NAND bus cycles before
releasing pins. Defult is 8.
When pins are released by NAND, it will wait Pins_off number of NAND bus cycles before sending
next request. Default is 2.
When 1 the pins is not shared, default is 0, pins are shared.

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P_NAND_VER
Start from M8, NAND controller hardware version ID, 16 Bits year in hexadecimal, 8 Bits month in hexadecimal, maximum
ECC in decimal.
Project
Version ID
Description
M6, M6TV older
0
N/A
M6TVlite
0x2012081e
Designed on Aug 2012, ECC 30
M80x2012083c
Designed on Aug 2012, ECC 60

34. eMMC/SD/SDIO
34.1 Overview

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S905 has the following features of eMMC/SD/SDIOSupports SDSC/SDHC/SDXC card and SDIO specification version 2.x/3.x/4.x DS/HS modes up to UHS-I SDR104

Supports eMMC and MMC card specification version 5.0 up to HS400 with data content DES crypto
1 bit, 4 Bits, 8 Bits date lines supported (8 Bits only for MMC)
Descriptor chain architecture, timing tuning and adjustment
Supports descriptor-based internal DMA controllerarThis module uses eMMC/SD/SDIO CONTROLLERs to connect varied SD/MMC Card, SDIO device (e.g. Wi-Fi module), or eMMC
protocol compatible memory with high throughput.

34.2 Pin Description

e

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Description
SD eMMC clock, 0~200MHz
Data Strobe, HS400 mode
only

Speed (MHz)200
200

Data, 1,4,8 mode

200

Command Response

100

Hardware reset
Device interrupt
can be replaced by DAT[1]

Low
Low

D

Rst_n
IRQ

ut

DAT[7:0]

CMD

Type
OutputeMMC optional
SD Card or SDIO not used
Input (used as device IRQ in SDIO)RDS pull-down used in HS400 mode.
SD Card/SDIO 4 Bits, eMMC 8 Bits
Input/Output/Push-Pull
Internal pull-up for pins not used
Input/Output/Push-Pull/Open-Drain
Open-drain for initialization
Push-pull for fast command transfer
ROD is connected when in open-drain mode.
eMMC required
SDIO required
SD Card or eMMC not used.

to

Name
CLK
DS

H

Table VI.34.1 Pin Description of eMMC/SD/SDIO Module34.3 eMMC/SD ModeeMMC Mode:

Table VI.34.2. eMMC Mode
Mode Name

Data Rate

IO Voltage

Bus Width

Frequency

Max Data Transfer

Legacy MMC card

Single3/1.8/1.2V

1, 4, 80-26MHz26MB/sHigh Speed SDR

Single3/1.8/1.2V

1,4, 80-52MHz52MB/sHigh Speed DDR

Dual

3/1.8/1.2V4, 8

0-52MHz

104MB/s

HS200

Single1.8/1.2V4, 8

0-200MHz

200MB/s

HS400 (highest)Dual

1.8/1.2V

80-200MHz

400MB/s

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The HS200 mode offers the following features:
SDR Data sampling method
CLK frequency up to 200MHz Data rate – up to 200MB/s

4 or 8-bits bus width supportedSingle ended signaling with 4 Drive Strengths

Signaling levels of 1.8V and 1.2VTuning concept for Read Operations

SD Mode:TableVI.34.3. SD ModeBus Width
1, 4
1, 4
1,4
1,4
1,4
1,4
4

Frequency
0-25MHz
0-50MHz
0-25MHz
0-50MHz0-100MHz
0-208MHz
0-50MHz34.4 ClockMax Data Transfer
12.5MB/s
25MB/s
12.5MB/s
25MB/s
50MB/s104MB/s
50MB/sar

IO Voltage
3.3V
3.3V
1.8V
1.8V
1.8V
1.8V
1.8V

H

Data Rate
SingleSingleSingleSingleSingleSingleDual

toMode Name
Default Speed
High Speed
SDR12
SDR25
SDR50
SDR104 (highest)
DDR50

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The HS400 mode has the following features
DDR Data sampling method
CLK frequency up to 200MHz, Data rate is up to 400MB/s

Only 8-bit bus width supported

Signaling levels of 1.8V and 1.2VSupport up to 5 Drive Strengths

Data strobe signal is toggled only for Data out and CRC responseute

In S905, clock source has the options to select from the table below.
Table VI.34.4. Clock Sources

Name
Cts_oscin_clk
Fclk_div2
Fclk_div3
Fclk_div5
Fclk_div7
Mp2_clk_out
Mp3_clk_out
Gp0_pll_clk

Frequency MHz
24
1000
667
400
286
Programmable
Programmable

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is

Clock source
0
1
2
3
4
5
6
7

Note
Default

34.5 Descriptor
Descriptor Structure
The descriptor has a size of 4x32 Bits.
TableVI.34.5 Descriptor Structure
byte
0

7

6

5

4

3

2

1

0

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1Timeout 4 Bits2

data num

resp num

3

owner

error

resp 128

End of chain

R1b

block
mode

length[8]Data wr

Data io

No cmdNo respresp nocrc

cmd index 6 Bits

45

cmd argument 32 Bits

6
7
8
9

data address 32 Bits or data 0-4 bytes[1]Big Endian, [0]SRAM

10

12
13

dk
er

response address 32 Bits or response irq en[0]SRAM

14

ne

l

11

15

ar

Descriptor Definition

TableVI.34.5 Descriptor Definition

Cmd_cfg[9]R1b

Cmd_cfg[10]End_of_chain

Cmd_cfg[11]Timeout

Cmd_cfg[15:12]

H

Block_mode

Description
same as spec, copy the content from command argument into this field, different byte size and 512
bytes, different number of blocks and infinite blocks.
If the command is operating on bytes, block mode = 0, this field contains the number of bytes toread or write, A value of 0 shall cause 512 bytes to be read to written, if the command is operatingon blocks, block mode = 1, this field contains the number of blocks, a value of 0 is infinite number ofblocks.
1: the read or write shall be performed on block basis. The block size is from SD/eMMC device, andsaved in APB3 register in module.
0: the read or write is byte based.
1: check the DAT0 busy after received response R1
0: do not check the DAT0 busy state.
1: it is the end of descriptor chain, the host stops and issues IRQ after this descriptor is done.
0: the host reads next descriptor and continues.
The command chain execution is started by write an APB3 register and stopped by the “end of chain”
or clear a APB3 start register, or found one descriptor with owner is set to 0.
2timeout ms when timeout != 0, max timeout 32.768s, when over the timeout limit, error bit is set, IRQ
is issued.
When timeout is 0, no time limit.
1: this command doesn’t have response, used with command doesn’t have response.
0: there is a response. The module waits for response, the response timeout setting is in APB3
register.
1: this descriptor doesn’t have command in it, it does data DMA only, used with command to reador write SD/eMMC with data from multiple locations.
1: there is data action in this descriptor, used with command have data process.
0: there is no data read/write action.
1: host writes data to SD/eMMC
0: host read data from SD/eMMC
1: R3 response doesn’t have CRC.
0: host does CRC check.
1: R3 response with 128 Bits information.
0: 32 Bits responses.
1: the resp_addr is the IRQ enable Bits, used to check the response error status, when there is anerror, IRQ[14] is issued, the first 4 bytes of response is saved into resp_addr.

to

Bits
Cmd_cfg[8:0]

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Cmd_cfg[16]D

No_resp

ut

e

Name
LengthNo_cmdCmd_cfg[17]Data_io

Cmd_cfg[18]Data_wr

Cmd_cfg[19]Resp_nocrc

Cmd_cfg[20]Resp_128

Cmd_cfg[21]Resp_num

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Cmd_cfg[23]Cmd_cfg[29:24]

Error

Cmd_cfg[30]Owner

Cmd_cfg[31]Cmd_argDesc
4~7 bytes

Data_addr

Desc
8~11 bytes

Resp_addr

Desc
12~15 bytes

0: save response into SRAM or DDR location.
1: save 4 bytes of data back into descriptor itself at bytes 8~11.
The SD/eMMC command index.
Desc REG wr: 4 reg44, 12 reg4c.
Write back by host.
The combined error from command, response, data, includes CRC error and timeout.
When it is set the descriptor execution is stopped and an IRQ is issued.
The CPU can read SD_EMMC_STATUS register to get detail information.
Programmed by CPU to 1, cleared by host to 0.
1: the descriptor is valid and owned by host, after it is done, even it has error, the owner bit is cleared,
the descriptor is owned by CPU.
In case of descriptor chain execution when host found a descriptor with “0” owner bit, it will stop.
32 Bits.
The actual command argument some of the previous fields are copied from this command argument,
the software need to make sure they are consistent.
Desc REG wr: new value
Data_addr: write mask, 1: change, 0: no change.
32 Bits.
If the data_num is 0, the content is data address.
If the data_num is 1, ths content is 4 data bytes.
When it is an address:
Data_addr[0]:1: SRAM address, 0: DDR address.
If the data_addr[31:12] matches with SD_EMMC_BASE, it is SRAM address.
Data_addr[1]:1: 4 bytes big endian, 0: little endian(default).
32 Bits
If the resp_num is 0, the content is resp address.
If the resp_num is 1, before execution, it is the response IRQ enable Bits, after execution, it is thefirst 4 response bytes.

H

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Data_num
Cmd_index

ut

34.6 Timing SpecificationetoWhen it is an address:
Resp_addr[0]:1: SRAM address, 0: DDR address.
If the resp_addr[31:12] matches with SD_EMMC_BASE, it is SRAM address.

fPP/fOD
fWL

fODLY
fWH

is

SD CLK

trib

FigureVI.34.1 MMC/SD/SDIO Timing Diagram

D

SD CMD/DAT(O)SD CMD/DAT(I)
fISU

fIH

Table VI.34.6 SDHC Timing Specification
SymbolfPP

Description
Clock Frequency Low Speed
Clock Frequency Full/High Speed
Clock Frequency UHS-I Speed

Min.
0
0
0

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Max.
400
25/80
100

Unit
KHz
MHz
MHz

Notes

AMLOGIC, Inc. Proprietary

S905 Datasheet

fOD
tWL
tWH
tODLY
tISU
tIH

Revision 1.1.4

Clock Frequency Identification Mode
Clock Low Time
Clock High Time
Output Delay
Input Setup Time
Input Hold Time

100
5
5
-2.5
4
4

400

2.5

KHz
ns
ns
ns
ns
ns

Table VI.34.7 SDIO Timing Specification
Notes

l

3.5

Unit
KHz
MHz
KHz
ns
ns
ns
ns
ns

ne

Max.
400
25/50
400

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H

ar

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Min.
0
0
100
8
8
-3.5
6
6

is

fOD
tWL
tWH
tODLY
tISU
tIH

Description
Clock Frequency Low Speed
Clock Frequency Full/High Speed
Clock Frequency Identification Mode
Clock Low Time
Clock High Time
Output Delay
Input Setup Time
Input Hold TimeD

SymbolfPP

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34.7 Register Definitions
Each register final address = module base address+ offset * 4
Where module address addresses are 0xd0070000 for port A (Wifi/SDIO) and portC(eMMC) and 0xd0072000 for port B (SDcard).
SD_EMMC_CLOCK

0x0
R/W
R
R/W

Default
0
0

24

R/W

0

23:20

R/W

0

19:16

R/W

0

15:14
13:12

R/W

0

11:10

R/W

0

9:8

R/W

0

7:6

R/W

0

5:0

R/W

0

Description
unused
Cfg_irq_sdio_sleep:
1: enable IRQ sdio when in sleep mode.
When DAT1 IRQ, the controller uses PCLK to detect DAT1 level and starts core clock, the core initials
Cfg_always_on:
1: Keep clock always on
0: Clock on/off controlled by activities.
Any APB3 access or descriptor execution will turn clock on.
Recommended value: 0
Cfg_rx_delay: RX clock delay line
0: no delay, n: delay n*200ps
Maximum delay 3ns.
Cfg_tx_delay: TX clock delay line
0: no delay, n: delay n*200ps
Maximum delay 3ns.
Cfg_sram_pd: Sram power down
Cfg_rx_phase: RX clock phase
0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
Recommended value: 0
Cfg_tx_phase: TX clock phase
0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
Recommended value: 2
Cfg_co_phase: Core clock phase
0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
Recommended value: 2
Cfg_src: Clock source
0: Crystal 24MHz or other frequencies selected by clock reset test control register.
1: Fix PLL, 1000MHz
Recommended value: 1
Cfg_div: Clock divider
Frequency = clock source/cfg_div
Clock off: cfg_div==0, the clock is disabled
Divider bypass: cfg_div==1, clock source is used as core clock without divider
Maximum divider 63.

0x4

SD_EMMC_ADJUST
Bit(s)
31:22
21:16

Default
0
0
0
0
0
0
0
0

is

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

D

Bit(s)
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0

tr
ib

SD_EMMC_DELAY

ut

e

to

H

ar

dk
er

ne

l

Bit(s)
31:26
25

Description
Dly[7]: Data 7 delay line
Dly[6]: Data 6 delay line
Dly[5]: Data 5 delay line
Dly[4]: Data 4 delay line
Dly[3]: Data 3 delay line
Dly[2]: Data 2 delay line
Dly[1]: Data 1 delay line
Dly[0]: Data 0 delay line
Total delay = 200ps * Dly
When Dly == 0, no delay.
When Dly ==15, 3ns delay.
NOTE: the 200ps is typical delay, actually delay may vary from chip to chip, from different temperature.

0x8

R/W

Default

R/W

0

Description
Unused
Adj_delay: Resample the input signals when clock index==adj_delay

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R/W
R/W

Default
0

13

R/W

0

12

R/W

0

11:8

R/W

0

7:4
3:0

R/W
R/W

0
0

Description
Cali_rise:
1: test the rising edge, recording rising edge location only.
0: test the falling edge
Adj_enable:
Adjust interface timing by resampling the input signals
Cali_enable:
1: Enable calibration
0: shut off to save power.
Cali_sel: Select one signal to be tested
Signals are labeled from 0 to 9 the same as delay lines.
Only one signal is tested at anytime.
For example:
Cali_sel == 8, test CMD line.
Dly[9]: DS delay line
Dly[8]: Command delay line

SD_EMMC_CALOUTnel

Bit(s)
14

0x10

R/W

7

R

5:0

R

Default

Description
UnusedCali_setup: Calibration reading
The event happens at this index,
The index starts from rising edge of core clock from 0, 1, 2, …
Cali_vld: The reading is valid
When there is no rising edge or falling edge event, the valid is low, this reading is not valid.
Cali_idx: Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise.

R

0x40
Default
0

1

R/W

0

0

R/W

0

Description
Desc_addr[31:2]: Descriptor address, the last 2 Bits are 0,
SRAM: 4 bytes aligned, the valid address range is from 0x200~0x3ff
DDR: 8 bytes aligned the valid address is anywhere in DDR, the length of chain is unlimited.
Desc_addr = ADDR>>2.
Desc_busy: Start/Stop
1: Start command chain execution process.
0: Stop
Write 1 to this register starts execution.
Write 0 to this register stops execution.
Desc_int: SRAM/DDR
1: Read descriptor from internal SRAM, limited to 32 descriptors.
0: Read descriptor from external DDR

H

R/W
R/W

0x44
R/W
R/W

27

R/W

Default
0Dis

Bit(s)
31:28

26

tr
ib

SD_EMMC_CFG

ute

Bit(s)
31:2

to

SD_EMMC_START

ar

dk
er

Bit(s)
31:16
15:8

0

R/W

0

25

R/W

0

24

R/W

0

23

R/W

0

Description
Cfg_ip_txd_adj: Data 1 interrupt,
when in TXD mode, the data 1 irq is a input signal, the round trip delay is uncertain factor, change this cfg tocompensate the delay.
Cfg_err_abort:
1: abort current read/write and issue IRQ
0: continue on current read/write blocks.
Cfg_irq_ds:
1: Use DS pin as SDIO IRQ input,
0: Use DAT1 pin as SDIO IRQ input.
Cfg_txd_retry:
When TXD CRC error, host sends the block again.
The total number of retries of one descriptor is limited to 15, after 15 retries, the TXD_err is set to high.
Cfg_txd_add_err: TXD add error test.
Test feature, should not be used in normal condition.
It will inverted the first CRC Bits of the 3rd block.
Block index starts from 0, 1, 2, …
Cfg_auto_clk: SD/eMMC Clock Control
1: when BUS is idle and no descriptor is available, automatically turn off clock, to save power.
0:.whenever core clock is on the SD/eMMC clock is ON, it is still on/off during read data from SD/eMMC.

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0

20
19
18

R/W
R/W
R/W

0
0
0

17

R/W

0

16

R/W

0

15:12
11:8

R/W
R/W

0
0

7:4
3

R/W
R/W

0
0

2

R/W

0

1:0

R/W

0

l

R/W

ne

21

Description
Cfg_stop_clk: SD/eMMC Clock Control
1: no clock for external SD/eMMC, used in voltage switch.
0: normal clock, the clock is automatically on/off during reading mode to back off reading in case of DDR slow
response.
Cfg_cmd_low: Hold CMD as output Low
eMMC boot mode.
Cfg_chk_ds: Check data strobe in HS400
Cfg_ignore_owner: Use this descriptor even if its owner bit is “0”.
Cfg_sdclk_always_on:
1: SD/eMMC clock is always ON
0: SD/eMMC clock is controlled by host.
WARNING: Set SD/eMMC clock to always ON, host may lose data when DDR is slow.
Cfg_blk_gap_ip:
1: Enable SDIO data block gap interrupt period
0: Disabled.
Cfg_out_fall: DDR mode only
The command and TXD start from rising edge.
Set 1 to start from falling edge.
Cfg_rc_cc: Wait response-command, command-command gap before next command, 2cfg_rc_cc core clock cycles.
Cfg_resp_timeout: Wait response till 2cfg_resp_timeout core clock cycles.
Maximum 32768 core cycles.
Cfg_bl_len: Block length 2cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9.
Cfg_dc_ugt:
1: DDR access urgent
0: DDR access normal
Cfg_ddr:
1: DDR mode
0: SDR mode
Cfg_bus_width:
0: 1 bit
1: 4 Bits
2: 8 Bits
3: 2 Bits (not supported)dk
erDefault
0

ar

R/W
R/W

0x48

R/W
R

30

R

29:26
25
24
23:16
15
14
13

R
R
R
R
R/W
R/W
R/W

Default

Description
Core_busy:
1: core is busy, desc_busy or sd_emmc_irq or bus_fsm is not idle.
0: core is idle.
Desc_busy:
1: Desc input process is busy, more descriptors in chain.
0: no more descriptor in chain or desc_err.
Bus_fsm: BUS fsm
DS: Input data strobe
CMD_i: Input response signal
DAT_i: Input data signals
IRQ_sdio: SDIO device uses DAT[1] to request IRQ
Resp_status: When resp_num is set to 1, the resp_addr is the response status IRQ enable Bits, if there is an error.
End_of_Chain: End of Chain IRQ,
Normal IRQ
Desc_timeout: Descriptor execution time over time limit.
The timeout limit is set by descriptor itself.
Consider the multiple block read/write, set the proper timeout limits.
Resp_timeout: No response received before time limit.
The timeout limit is set by cfg_resp_timeout.
Resp_err: Response CRC error
Desc_err: SD/eMMC controller doesn’t own descriptor.
The owner bit is “0”, set cfg_ignore_owner to ignore this error.
Txd_err: TX data CRC error,
For multiple block write, any one of blocks CRC error.
Rxd_err: RX data CRC error per wire,
for multiple block read, the CRC errors are Ored together.

12

D

is

tr
ib

ut

Bit(s)31e

SD_EMMC_STATUS

toH

Bit(s)
22

11

R/W

10
9

R/W
R/W

8

R/W

7:0

R/W

R/W

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SD_EMMC_IRQ_EN

0x4c

R/W

Default

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0
0
0
0
0
0
0
0
0
0

0x50
R/W
R/W

Descriptor_REG1

Description
SD_EMMC_CMD_CFG
APB read wait
Same as descriptor first word,
resp_num = 1, response saved back into descriptor only.
Read from this APB will hold APB bus

0x54
R/W
R/W

Default

Description

SD_EMMC_CMD_ARG
APB write startSame as descriptor second word.
Write to this APB address starts execution.
If the current desc is busy, it will be executed after current descriptor is done.

HarBit(s)
31:0

DefaultlBit(s)
31:0

ne

Descriptor_REG0

Description
Unused
Cfg_secure: Data read/write with crypto DES
en_IRQ_sdio: Enable sdio interrupt.
En_resp_status: Response status error.
en_End_of_Chain: End of Chain IRQ
en_Desc_timeout: Descriptor execution time over time limit.
en_Resp_timeout: No response received before time limit.
en_Resp_err: Response CRC error
en_Desc_err: SD/eMMC controller doesn’t own descriptor.
En_txd_err: TX data CRC error
en_Rxd_err: RX data CRC error per wire.

dkerBit(s)
31:17
16
15
14
13
12
11
10
9
8
7:0

Descriptor_REG3

0x5c
R/W
R/W

Descriptor_REG4

D

R/W
R

Description
SD_EMMC_CMD_RSP1: Response bit 63:32

Default

Description
SD_EMMC_CMD_RSP2: Response bit 95:64

0x68
R/W
R

Descriptor_REG7
Bit(s)
31:0

Default

0x64

Descriptor_REG6
Bit(s)
31:0

Description
SD_EMMC_CMD_RSP:
Write: response status IRQ enable Bits.
Read: Response Bit 31:0

0x60
R/W
R

Descriptor_REG5
Bit(s)
31:0

Defaultis

Bit(s)
31:0

Description
SD_EMMC_CMD_DAT : Same as descriptor third word, 32 Bits data.

trib

Bit(s)
31:0

Default

to

0x58
R/W
R/W

ut

Bit(s)
31:0

e

Descriptor_REG2

Default

Description
SD_EMMC_CMD_RSP3: Response bit 127:96

0x6c
Default

Description
Reserved

Current_Next_Descriptor_REG0

0x70

Bit(s)
31:0

R/W

R/W
R

Default

Description
SD_EMMC_CURR_CFG: Current descriptor under execution.

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R/W
R

Default

Current_Next_Descriptor_REG3
Bit(s)
31:0

R/W
R

Default

Current_Next_Descriptor_REG4
Bit(s)
31:0

R/W
R

Default

Current_Next_Descriptor_REG5
Bit(s)
31:0

R/W
R

Default

Current_Next_Descriptor_REG6
Bit(s)
31:0

R/W
R

Default

Current_Next_Descriptor_REG7
Bit(s)
31:0

R/W
R

SD_EMMC_RXD

Default

0x78
Description
SD_EMMC_CURR_DAT

0x7c
Description
SD_EMMC_CURR_RSP

0x80
Description
SD_EMMC_NEXT_CFG: Next descriptor waiting for execution,
already read out from SRAM or DDR, can’t be changed.

0x84
Description
SD_EMMC_NEXT_ARG

0x88
Description
SD_EMMC_NEXT_DAT

0x8c
Description
SD_EMMC_NEXT_RSP

0x90
R/W
R
R

15:10
9:0

R

Default

Description
UnusedData_blk:
Rxd Blocks received from BUS
Txd blocks received from DDR.
unusedData_cnt:
Rxd words received from BUS.
Txd words received from DDR.

SD_EMMC_RXD

0x94

R
R

Default

is

R/W

D

Bit(s)
31:25
24:16
15
14:0

tr
ib

ut

e

Bit(s)
31:25
24:16

l

Bit(s)
31:0

neCurrent_Next_Descriptor_REG2

0x74
Description
SD_EMMC_CURR_ARG

dker

Default

ar

R/W
R

to

Bit(s)
31:0

H

Current_Next_Descriptor_REG1

Description
UnusedTxd_blk: Txd BUS block counter
unusedTxd_cnt: Txd BUS cycle counter

35. SERIAL PERIPHERAL INTERFACE COMMUNICATION CONTROLLER
35.1 Overview
SPI Communication Controller is designed for connecting general SPI protocol compatible module. This controller allows rapid
data communication with less software interrupts than conventional serial communications.

35.2 Features

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Revision 1.1.4

Full-duplex synchronous serial interface
Master/Slave configurable
Four chip selects to support multiple peripherals
Transfer continuation function allows unlimited length data transfers
64-bit wide by 16-entry FIFO for both transmit and receive data
Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
Both PIO(Programming In/Out interface) and DMA(Direct Memory Access interface) supported

35.3 Functional Description
The following are two SPICC modes of operation:l

Master Mode—When the SPICC module is configured as a master, it uses a serial link to transfer data between the
SPICC and an external device. A chip-enable signal and a clock signal are used to transfer data between these two
devices. If the external device is a transmit-only device, the SPICC master’s output port can be ignored and used forother purposes. To use the internal TXFIFO and RXFIFO, two auxiliary output signals, SS and SPI_RDY, are used for datatransfer rate control. The user can also program the sample period control register to a fixed data transfer rate.
Slave Mode–When the SPICC module is configured as a slave, the user can configure the SPICC Control register tomatch the external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to control datatransfers through the Shift register, as well as to load/store the data FIFO.

ar

•

dk
er

ne

•

H

There are 5 sub-modules in sd host controller, i.e. sd_ctrl, sd_async, sd_dphy_tx, sd_dphy_rx, and sd_clkgen. Transmitting andreceiving are using different channel, that means they have different buffer.
Fig VI.35.1 SPICC Block Diagram
APB_SIGNALS

EXTERNALSPISPICC_MAIN

SPICC_RXFIFO

spicc_reg is driven by host cpu, and spicc_reg is responsible for configuring other modules.
spicc_dmaif is responsible for dealing with DMA operatoins.
spicc_txfifo contains a transmission FIFO.
spicc_rxfifo contains a receiving FIFO.
spicc_main is responsible for main control of basic spi operation.

D

•
•
•
•
•

SPICC_DMAIFSPICC_TXFIFOis

DMA_SIGNALS

tr
ib

ut

e

to

SPICC_REG

Here are SPI External Signals:
Table VI.35.1 SPI External Signals
Signal Name
spicc_sclk
spicc_miso
spicc_mosi
spicc_ss[3:0]spicc_rdy_i

I/O

Description

IO
IO
IO
IO
I

SCLK, SPI Clock
MISO, Master Input Slave Output
MOSI, Master Output Slave In
SS, SPI chip Select, Supports up to 4 slaves.
RDY input, Data Ready Input

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And here is SPI Generic Timing:
Fig VI.35.2 SPI Generic Timing(CLK_POL=1,CLK_PHA=1)SCLK(CLK_POL=1,CLK_PHA=0)SCLKnel(CLK_POL=0,CLK_PHA=1)SCLK

Bn

Bn-1

Bn-2

Bn-3

MOSI

Bn

Bn-1

Bn-2

Bn-3

...

...

B1

B0

...

...

B1

B0

35.4 Timing Specification

to

H

ar

MISO

dk
er

(CLK_POL=0,CLK_PHA=0)SCLKeFig VI.35.3. SPICC Timing Diagram

fSPI

tr
ib

SPI CLK(O)tOSKEW

tISU

tIH

D

is

SPI MOSI (MO)SPI MISO(MI)

tSS1

ut

tSS0

SPI SS(O)

Master Mode, CPOL=0, CPHA=1
Table VI.35.2. SPICC Master Timing Specification
SymbolfSPItOSKEW
tISU
tIH
tSS0
tSS1

Description
Clock Frequency
Output SKEW
Input Setup Time
Input Hold TimeSS active time before transition
SS inactive time after transition

Min.
0
-3.5
8
8
8
8

Max.
30
3.5

Unit
MHz
ns
ns
ns
ns
ns

Notes

Slave Mode, CPOL=0, CPHA=1

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Table VI.35.3. SPICC Slave Timing Specification
SymbolfSPItOSKEW
tISU
tIH
tSS0
tSS1

Description
Clock Frequency
Output SKEW
Input Setup Time
Input Hold TimeSS active time before transition
SS inactive time after transition

Min.
0
-3.5
8
8
5
5

Max.
30
3.5

Unit
MHz
ns
ns
ns
ns
ns

Notes

35.5 Register Description
R/W
R

Default0l0xc1108d80
Bit(s)
31:0

Description
Rx Datane

RXDATATXDATA

0xc1108d84
Bit(s)
31:0

R/W
W

Default
0

Description
Tx Data

Note1: when PIO mode, programmer need send data to this register.

Default
0

18:16

RW

0

15:14
13:12

RW

0

11:10
9:8

RW

0

7

RW

6

RW

0

5

RW

0

4

RW

0

3

RW

0

2
1

RW
RW

0
0

0

RW

0

Description[13]burst_length([5:0]bit number of one word/package,[12:6]burst length-1)[ 3]data_rate(sclk will be divided by system clock with equation: 2^(data_rate+2), Example: if system clock = 128MHz anddata_rate=2, sclk's frequency equals 8MHz)
Reserved[ 2]chip_select(00:select ss_0,
01:select ss_1,
10:select ss_2,
11:select ss_3,)
Reserved[ 2]drctl(0:ignore RDY input,
1:Data ready using pin rdy_i's failing edge,
2:Data ready using pin rdy_i's low level,
3:reserved)[ 1]sspol(0:SS polarity Low active,1:High active)[ 1]ssctl(see details in Note1)[ 1]pha(clock/data phase control, see section 2.2)
[ 1]pol(clock polarity control, see section 2.2)
[ 1]smc(start mode control, see Note2)[ 1]xch(exchange bit, ATTN:will automatically cleared when burst finished, see Note3)[ 1]mode(0:slave,1:master)[ 1]en(0:spicc disable,1:enable)

H

R/W
RW

is

tr
ib

ut

e

to

Bit(s)
31:19

ar

0xc1108d88

D

CONREGdk
er

Note1: when PIO mode, programmer can get data from this register.

0

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Note1: In one burst of master mode, if ssctl ==0, ss will output 0 between each spi transition. And if ssctl ==1, ss will output 1.
Note2: smc is for start mode control. If smc ==0, burst will start when xch is set to 1'b1; if smc==1, burst will start when txfifo
is not empty.
Note3: setting xch will issue a burst when smc==0, and This bit will be self-cleared after burst is finished.

R/W

Default

RW
RW
RW
RW
RW
RW
RW
RW

0
0
0
0
0
0
0
0

Description
Reserved[ 1]tcen(transfer completed interrrupt enable)[ 1]roen(rxfifo overflow interrrupt enable)[ 1]rfen(rxfifo full interrrupt enable)[ 1]rhen(rxfifo half full interrrupt enable)[ 1]rren(rxfifo ready interrrupt enable)[ 1]tfen(txfifo full interrrupt enable)[ 1]then(txfifo half full interrrupt enable)[ 1]teen(txfifo empty interrrupt enable)

Note1: Interrupt Status presents in STATREG.
0xc1108d90

ar

Description[ 6]DMA Burst Number[ 6]DMA Thread ID[ 1]DMA Urgent[ 4]Number in one Write request burst(0:1,1:2...)[ 4]Number in one Read request burst(0:1,1:2...)[ 5]RxFIFO threshold(RxFIFO's count>=thres, will request write)[ 5]TxFIFO threshold(TxFIFO's count<=thres, will request read)[ 1]DMA Enable

H

Default
0
0
0
0x7
0x7
0x8
0
0

R/W

Default

RW
R
R
R
R
R

0
0
0
0
0
0

e

0xc1108d94
Bit(s)
31:8
7
6
5
4
3
2

Description
Reserved[ 1]tc(transfer completed, w1c, see Note1)[ 1]ro(rxfifo overflow)[ 1]rf(rxfifo full)[ 1]rh(rxfifo half full)[ 1]rr(rxfifo ready)[ 1]tf(txfifo full)ut

STATREG

R/W
RW
RW
RW
RW
RW
RW
RW
RW

to

Bit(s)
31:26
25:20
19
18:15
14:11
10:6
5:1
0

tr
ib

DMAREGne

Bit(s)
31:8
7
6
5
4
3
2
1
0

l

0xc1108d8c

dker

INTREG

D

is

Note1: tc is the status bit which indicates a burst transfer is completed. And a burst transfer should be started by writing xch
1'b1. This bit supports w1c(Write 1 clear).
PERIODREG 0xc1108d98
Bit(s)
31:15
14:0

R/W

Default

RW

0

Description
Reserved[15]period(wait cycles, see Note1)

Note1: Programmer can add wait cycles through this register if transmission rate need to be controlled.
TESTREG0xc1108d9c
Bit(s)
R/W Default
Description
31:23
RW
0
Reserved
Read Only (Need pay attention)
22:21
R
0
[ 2]fiforst(fifo soft reset)
20:15
R
0x15
[ 6]dlyctl(delay control)
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Bit(s)
R/W Default
Description
13
R0[ 1]lbc(loop back control)
Write Only (Need pay attention)
23:22
W
0
[ 2]fiforst(fifo soft reset)
21:16
W
0x15
[ 6]dlyctl(delay control)
15W0[ 1]swap(data swap for reading rxfifo)
14
W0[ 1]lbc(loop back control)
12:10
9:5

R
R

0
0

[ 3]smstatus(internal state machine status)[ 5]rxcnt(internal RxFIFO counter)Note1: Programmer can only use the TESTREG[9:0], rxcnt(internal RxFIFO counter) and txcnt(internal TxFIFO counter) , andother Bits just for test.

DWADDR

R/W
RW

Default
0

Description
Read Address of DMA

Default
0

Description
Write Address of DMA

ne

Bit(s)
31:0

l

0xc1108da0

0xc1108da4
Bit(s)
31:0

R/W
RW

dk
er

DRADDRar

36. SERIAL PERIPHERAL INTERFACE FLASH CONTROLLER

H

36.1 Overview

to

SPI Flash Controller is designed for connecting varied SPI Flash memory.

36.2 Features

is

tr
ib

ut

e

Support three operation modes, NOR Flash mode, Master mode, and Slave mode.
Support read/write buffer up to 64bytes.
Support no clock toggling during DUMMY state.
Support hold by an external pin during a transition.
AHB read support byte and halfword.
Support bit-number rather than byte-number for each stage.
Support 2/4 wire writing like fast reading
Support both rising-edge and falling-edge for SPI slave sampling and SPI master sampling.
Support 1 wire for SPI_D and SPI_Q.
Support SPI_CK setup and hold time by cycles
Support 8 bit clock divider, so SPI_CK can be low as 1/256 HCLK
Support byte-order in a word
Support no command state, so the command is sent/received in address state by 2/4 wires.
Support both data input and data output in a transition. SPI_DOUT->(SPI_DUMMY)->SPI_DIN

D

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
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

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36.3 Timing Specification

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Fig VI.36.1 SPIFC Timing Diagram
tSS0

tSS1

SPI SS(O)fSPISPI CLK(O)tOSKEW

SPI MOSI (MO)SPI MISO(MI)tIH

Master Mode, CPOL=0, CPHA=1
Table VI.36.1 SPIFC Master Timing Specification

36.4 Register Description
R/W
R/W

Default
0

30
29
28
27
26
25
24
23
22
21
20
19
18
17:0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0
0
0
0
0
0
0
0
0
0
0
0
0
0

is

D

SPIFC address register
Bit(s)
31:0

R/W
R/W

dk
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Notes

5

ns

Description
READ command. 1 = read. When it becames 0, the read command is finished.
The READ command could be (0xEB, 0x6B, 0xBB, 0x3B, 0x0B, 0x03). By default is 0x0B.
One read command will read continous 32x8Bits data. And saved in data cache.
WREN command. (0x06)
WRDI command. ( 0x04).
RDID command. (0x9f).
RDSR command. (0x05).
WRSR command. (0x01).
Page program command. (0xAD or 0x02).
SE command (0x20).
BE command ( 0xD8).
CE command.(0xC7).
Deep Power Down command(0xB9).
RES command. (0xAB).
HPM command.(0xA3). (Just For winbond SPI flash).
USER defined command.
Reserved for future.

tribBit(s)
31

0xc1108c80

Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns

ut

SPIFC FLASH Command register

Max.
20

ar

WP inactive time after transition

H

tWP1

Min.
0
20
20
-5
10
10
0
0
SoftwareControlled
SoftwareControlled

toDescription
Clock Frequency
Clock Low Time
Clock High Time
Output SKEW
Input Setup Time
Input Hold TimeSS active time before transition
SS inactive time after transition
WP active time before transitioneSymbolfSPI
tWL
tWH
tOSKEW
tISU
tIH
tSS0
tSS1
tWP0

ne

l

tISU

0xc1108c84
Default
0

Description
The address[31:0] of the user command

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SPIFC control register

0xc1108c88

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
1
0
1
0

17

R/W

1

16
15
14
13
12:0

R/W
R/W
R/W
R/W
R/W

0
1
0
1
0

Description
Reserved.
WriTE bit order. 1 = 0, 1, 2, 3, 4, 5, 6, 7. 0 = 7, 6, 5, 4, 3, 2, 1, 0.
Read bit order. . 1 = 0, 1, 2, 3, 4, 5, 6, 7. 0 = 7, 6, 5, 4, 3, 2, 1, 0.
Fast read QIO mode.
Fast read DIO mode.
Write 2 bytes status mode. For some of winbond SPI flash, the status register is 16Bits.
SPI flash WP pin value if use SPI flash WP pin as write protection.
Fast read QOUT mode.
1 = SPI share pins with SDRAM. 0 = doesn't share.
SPI hold mode. 1=SPI controller would use SPI hold function. 0 = SPI controller won’t use hold function. The
SPI flash hold pin can be tie high on the board. Or SPI controller can use hold pin as QIO/QOUT mode.
1 = enable AHB request. 0 = disable AHB request when you reconfigure SPI controller or running APB bus
commands.
1 =enable SST SPI Flash aai command. The APB bus PP command will send AAI command.
1 = release from Deep Power-Down command is with read electronic signature.
Fast read DOUT mode.
Fast read mode. AHB bus read requirement and APB bus read command use the command 0x0Bh.
Reserved for future.

dk
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R/W
R/W
R/W
R/W

Default
50xfff
0x0120Description
SPI Clock cycles for SPI flash timing requirement tCSH.
SPI Clock cycles for SPI flash timing requirement tRES.
System clock cycles for SPI bus timer. In SPI share bus and SPI hold function mode. SPI bus timer used , if SPI
use the bus for a limit time, SPI controller will diassert SPI hold pin to halt the SPI Flash, and give the bus
control to SDRAM.

0xc1108c90

R/W
R/W
R/W
R/W

Default000Description
Reserved.
For winbond SPI flash, this 8 Bits used for DIOmode M7~M0,
SPI status register value. WRSR command will write this value to SPI flash status.
RDSR or RES command will save the read result to this register.

ut

Bit(s)
31:24
23:16
15:0

e

SPIFC status registertoH

Bit(s)
31:28
27:16
15:0

0xc1108c8c

ar

SPIFC control registernelBit(s)
31:27
26
25
24
23
22
21
20
19
18

Bit(s)
31:0

R/W
R/W

tr
ib

When SPI controller in the slave mode, this register are the status for the SPI master to read out.
Default
0

SPIFC control register 2

0xc1108c904

Default
0

is

R/W
R/W

D

Bit(s)
31:28

Description
In SPI Slave mode, the read status of the user command

27:26

R/W

0

25:23

R/W

0

22:21

R/W

0

20:18

R/W

0

Description
Delay cycle number of SPI_CS input in SPI slave mode or SPI_CS output in SPI master mode
0= not delay, 1 = delayed by 1 cycle of system clock, 2 = delayed by 2 cycles of system clock , …
delay mode of SPI_CS input in SPI slave mode or SPI_CS output in SPI master mode
0= not latched by the edges of SPI_CK
1= latched by the falling edges of SPI_CK
2 = latched by the rising edges of SPI_CKDelay cycle number of SPI Data from SPI Master to SPI Slave
In SPI master mode, it is for data outputs; in SPI slave mode, it is for data inputs.
0= not delay, 1 = delayed by 1 cycle of system clock, 2 = delayed by 2 cycles of system clock , …
Delay mode of SPI Data from SPI Master to SPI Slave
In SPI master mode, it is for data outputs; in SPI slave mode, it is for data inputs.
0= not latched by the edges of SPI_CK
1= latched by the falling edges of SPI_CK
2 = latched by the rising edges of SPI_CKDelay cycle number of SPI Data from SPI Slave to SPI Master.
In SPI master mode, it is for data inputs; in SPI slave mode, it is for data outputs.

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R/W

Default

17:16

R/W

0

15:12

R/W

0

11:8

R/W

0

7:4
3:0

R/W
R/W

1
1

31:28

R/W

0

27:26

R/W

0

25:23

R/W

0

22:21

R/W

0

20:18

R/W

Description
0= not delay, 1 = delayed by 1 cycle of system clock, 2 = delayed by 2 cycles of system clock , …
Delay mode of SPI Data from SPI Slave to SPI Master.
In SPI master mode, it is for data inputs; in SPI slave mode, it is for data outputs.
0= not latched by the edges of SPI_CK
1= latched by the falling edges of SPI_CK
2 = latched by the rising edges of SPI_CKIn SPI master mode, SPI_CK rising edge mode
4’b1000 = later by 1/4 cycle of SPI_CK
4’b1001 = later by 1/8 cycle of SPI_CK
4’b1010 = later by 1/16 cycle of SPI_CK
4’b1011 = later by 1/32 cycle of SPI_CK
4’b1100 = earlier by 1/4 cycle of SPI_CK
4’b1101 = earlier by 1/8 cycle of SPI_CK
4’b1110 = earlier by 1/16 cycle of SPI_CK
4’b1111 = earlier by 1/32 cycle of SPI_CKOthers = Normal
In SPI master mode, SPI_CK falling edge mode
4’b1000 = later by 1/4 cycle of SPI_CK
4’b1001 = later by 1/8 cycle of SPI_CK
4’b1010 = later by 1/16 cycle of SPI_CK
4’b1011 = later by 1/32 cycle of SPI_CK
4’b1100 = earlier by 1/4 cycle of SPI_CK
4’b1101 = earlier by 1/8 cycle of SPI_CK
4’b1110 = earlier by 1/16 cycle of SPI_CK
4’b1111 = earlier by 1/32 cycle of SPI_CKOthers = Normal
In master mode, SPI clock cycles for SPI hold timing.
In master mode, SPI clock sycles for SPI setup timing.
SPI setup time and SPI hold time is used to configure how soon the controller can enable spi_cs_n after thecontroller get the bus and how long the controller still keep the bus after the spi_cs_n become to be high.
Delay cycle number of SPI_CS input in SPI slave mode or SPI_CS output in SPI master mode
0= not delay, 1 = delayed by 1 cycle of system clock, 2 = delayed by 2 cycles of system clock , …
delay mode of SPI_CS input in SPI slave mode or SPI_CS output in SPI master mode
0= not latched by the edges of SPI_CK
1= latched by the falling edges of SPI_CK
2 = latched by the rising edges of SPI_CKDelay cycle number of SPI Data from SPI Master to SPI Slave
In SPI master mode, it is for data outputs; in SPI slave mode, it is for data inputs.
0= not delay, 1 = delayed by 1 cycle of system clock, 2 = delayed by 2 cycles of system clock , …
Delay mode of SPI Data from SPI Master to SPI Slave
In SPI master mode, it is for data outputs; in SPI slave mode, it is for data inputs.
0= not latched by the edges of SPI_CK
1= latched by the falling edges of SPI_CK
2 = latched by the rising edges of SPI_CKDelay cycle number of SPI Data from SPI Slave to SPI Master.
In SPI master mode, it is for data inputs; in SPI slave mode, it is for data outputs.
0= not delay, 1 = delayed by 1 cycle of system clock, 2 = delayed by 2 cycles of system clock , …
Delay mode of SPI Data from SPI Slave to SPI Master.
In SPI master mode, it is for data inputs; in SPI slave mode, it is for data outputs.
0= not latched by the edges of SPI_CK
1= latched by the falling edges of SPI_CK
2 = latched by the rising edges of SPI_CKIn SPI master mode, SPI_CK rising edge mode
4’b1000 = later by 1/4 cycle of SPI_CK
4’b1001 = later by 1/8 cycle of SPI_CK
4’b1010 = later by 1/16 cycle of SPI_CK
4’b1011 = later by 1/32 cycle of SPI_CK
4’b1100 = earlier by 1/4 cycle of SPI_CK
4’b1101 = earlier by 1/8 cycle of SPI_CK
4’b1110 = earlier by 1/16 cycle of SPI_CK

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Bit(s)

D

0

17:16

R/W

0

15:12

R/W

0

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R/W

Default

11:8

R/W

0

7:4
3:0

R/W
R/W

1
1

Description
4’b1111 = earlier by 1/32 cycle of SPI_CKOthers = Normal
In SPI master mode, SPI_CK falling edge mode
4’b1000 = later by 1/4 cycle of SPI_CK
4’b1001 = later by 1/8 cycle of SPI_CK
4’b1010 = later by 1/16 cycle of SPI_CK
4’b1011 = later by 1/32 cycle of SPI_CK
4’b1100 = earlier by 1/4 cycle of SPI_CK
4’b1101 = earlier by 1/8 cycle of SPI_CK
4’b1110 = earlier by 1/16 cycle of SPI_CK
4’b1111 = earlier by 1/32 cycle of SPI_CKOthers = Normal
In master mode, SPI clock cycles for SPI hold timing.
In master mode, SPI clock sycles for SPI setup timing.
SPI setup time and SPI hold time is used to configure how soon the controller can enable spi_cs_n after thecontroller get the bus and how long the controller still keep the bus after the spi_cs_n become to be high.

nelBit(s)

R/W
R/W
R/W

Default
1
0

17:12
11:6

R/W
R/W

0
0

5:0

R/W

0

31
30:18

R/W
R/W

1
0

17:12
11:6

R/W
R/W

0
0

5:0

R/W

0

Description
1=SPI clock frequency is same as system clock. 0 = SPI clock frequency will use clock divider.
Clock counter for Pre-scale divider:0= not pre-scale divider, 1= pre-scale divided by 2, 2= pre-scale divided by 3, ….,
Clock counter for clock divider.
Clock high counter in SPI master mode.
In SPI slave mode, it is for the delay counter for the rising edges of spi_ck_i
Clock low counter, in SPI master mode.
In SPI slave mode, it is for the delay counter for the falling edges of spi_ck_i
If the SPI clock frequcncy = sys_clock_frequency / n.
Then the clock divider counter = n – 1; the clock high counter = n /2 – 1; the clock low counter = n– 1;
For example, if you want to SPI clock freqency is divided by 2 of the system clock.
The clock divider counter = 1, clock high counter = 0, clock low counter = 1.
For SPI clock frequency = system clock / 4.
The clock divider counter = 3, clock high counter = 1, clock low counter = 3.
1=SPI clock frequency is same as system clock. 0 = SPI clock frequency will use clock divider.
Clock counter for Pre-scale divider:0= not pre-scale divider, 1= pre-scale divided by 2, 2= pre-scale divided by 3, ….,
Clock counter for clock divider.
Clock high counter in SPI master mode.
In SPI slave mode, it is for the delay counter for the rising edges of spi_ck_i
Clock low counter, in SPI master mode.
In SPI slave mode, it is for the delay counter for the falling edges of spi_ck_i
If the SPI clock frequcncy = sys_clock_frequency / n.
Then the clock divider counter = n – 1; the clock high counter = n /2 – 1; the clock low counter = n– 1;
For example, if you want to SPI clock freqency is divided by 2 of the system clock.
The clock divider counter = 1, clock high counter = 0, clock low counter = 1.
For SPI clock frequency = system clock / 4.
The clock divider counter = 3, clock high counter = 1, clock low counter = 3.

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Bit(s)
31
30:18

dk
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SPIFC Clock register 0xc1108c98

SPIFC User register

0xc1108c9c

Bit(s)31

R/W
R/W

Default
1

30
29
28
27

R/W
R/W
R/W
R/W

0
0
0
0

Description
USER command COMMAND bit. 1 = user command includes command. 0 = no command.
If some SPI slaves may support 2/4 IO at the first cycle, clear This bit.
USER command Address bit. 1 = user command includes address. 0 = no address.
USER command DUMMY bit. 1= user command includes Dummy bytes.
USER command DIn bit. 1 = user command includes data in. 0 = no data in.
USER command DO bit. 1 = user command includes data output. 0 = no data output.
If both DIN and DO are valid, SPI master is firstly in data output state and then in data input state.
If all of DUMMY, DO and DIN are valid, SPI master is firstly in data output state and then in dummy state, finallyin data input state.

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R/W
R/W
R/W

Default
0
0

24

R/W

0

23

R/W

0

22

R/W

0

21

R/W

0

20

R/W

0

19

R/W

0

18

R/W

0

17
16
15
14
13
12
11
10
9:8
7
6
5
4
3
2

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

1
0
0
0
0
0
0
0
0
0
1
0
0
0
1

1

R/W

0

0

R/W

0

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SPIFC User register 1

0xc1108ca0

Bit(s)
31:26

R/W
R/W

Default
0

25:17

R/W

0

16:8

R/W

0

7:0

R/W

0

SPIFC User register 2
Bit(s)
31:28

R/W
R/W

Description
USER command dummy idle bit. 1= no SPI clock toggling in dummy state. 0= normal
USER command highpart bit for SPI_DOUT stage. It is for data-output in spi master mode and for data-input inspi slave mode.
1 = only high half part of buffer are used. 0 = low half part or the whole 64bytes are used.
USER command highpart bit for SPI_DIN stage. It is for data-input in spi master mode and for data-output in spi
slave mode.
1 = only high half part of buffer are used. 0 = low half part or the whole 64bytes are used.
User command external hold bit for prep. 1 = in prep state, SPI master controller can be hold by the external
pin SPI_HOLD
User command external hold bit for command. 1 = in command state, SPI master controller can be hold by theexternal pin SPI_HOLD
User command external hold bit for address. 1 = in address state, SPI master controller can be hold by theexternal pin SPI_HOLD
User command external hold bit for dummy. 1 = in dummy state, SPI master controller can be hold by theexternal pin SPI_HOLD
User command external hold bit for data input. 1 = in data input state, SPI master controller can be hold by theexternal pin SPI_HOLD
User command external hold bit for data output. 1 = in data output state, SPI master controller can be hold by
the external pin SPI_HOLD
User command external hold polarity bit. 1 = high is valid for hold, 0 = low is valid for hold.
Single DIO mode: Data output and input apply only 1 wire.
Fast write QIO mode.
Fast write DIO mode.
Fast write QOUT mode.
Fast write DOUT mode.
Write byte order. 0 = d[7:0], d[15:8], d[23:16], d[31:24]. 1 = d[31:24], d[23:16], d[15:8], d[7:0]
Read byte order. . 0 = d[7:0], d[15:8], d[23:16], d[31:24]. 1 = d[31:24], d[23:16], d[15:8], d[7:0]
AHB endian mode: 0= little-endian; 1= big-endian; 2~3 reserved
In SPI master mode, the clock output edge bit: 0 = SPI_CK is inverted, 1 = SPI_CK is not inverted
In SPI slave mode, the clock input edge bit: 0 = SPI_CK_I is inverted, 1 = SPI_CK_I is not inverted
SPI CS setup bit: 1 = valid in prep state
SPI CS hold bit: 1 = valid in done state
AHB-read apply the configurations of user-command, such as command value, Bit(s)-length,…
Backward Compatible: 1 = compatible to Apollo SPIThis bit affect the three registers: “SPI Flash Commmand Register”, “SPI Address Register” and “SPI Control
Register”
AHB-read support 4byte address, when AHB-read apply the configurations of user-command.
1 = 4byte address, 0 = 3byte address
In SPI master mode, Enable bit for Data input during SPI_DOUT stage.
1 = enable; 0 = disable
This bit shall not be used in 2/4wire or SIO.
When This bit is 1, during SPI_DOUT stage, data input are stored into cacheline/buffer from address 0, i.e., bit
24 is not controlling the start address. The data output can be specified by bit 25lBit(s)
26
25

Description
USER command bit number for address state
0 = 1 bit, 1= 2 Bits, …
USER command bit number for data output state
0 = 1 bit, 1= 2 Bits, …
USER command bit number for data input state
0 = 1 bit, 1= 2 Bits, …
USER command cycle number for dummy state
0 = 1 cycle, 1= 2 cycles, …

0xc1108ca4
Default
0

Description
USER command bit number for command state297/336

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Bit(s)

R/W

Default

27:16
15:0

R/W
R/W

0
0

SPIFC User register 3
Bit(s)
31:0

Description
0 = 1 bit, 1= 2 Bits, …
Reserved
The command content of the user command

0xc1108ca8

R/W
R/W

SPIFC PIN register

Default
0

Description
In SPI Master mode, the address[63:32] of the user command
In SPI Slave mode, the write status of the user command

0xc1108cac
R/W
R/W

Default
0

30

R/W

0

29

R/W

0

28:24
23

R/W
R/W

0
0

22:21

R/W

0

20

R/W

0

19

R/W

0

18:17

R/W

0

16

R/W

0

15:11

R/W

0

Description
Pin swap when it is in DIN stage and SPI data input are 4wire. This feature is for Ubec Zigbee chips.
1 = swap between {spi_q, spi_d_i} and {spi_hold_i, spi_wp_i}
0 = normal
In SPI Master mode, CS keep active after a transition.
1 = enable; 0 = disable
Idle edge of SPI_CK
0 = low when it is idle
1 = high when it is idle
Reserved
In the SPI slave mode, spi_cs_i polarity:
1= high voltage is active
0= low voltage is active
In the SPI slave mode, spi_ck_i and spi_cs_i source pins
0=SPI_CK and SPI_CS pins, respectively
1=SPI_CS2 and SPI_CS1 pins, respectively
2=SPI_HOLD and SPI_WP pins, respectively
SPI_CS2 and SPI_CS1 pin function MUX
0= spi_ck and spi_cs in the SPI master mode
1= input pads for spi_ck_i and spi_cs_i, respectively, in the SPI slave mode
SPI_CK and SPI_CS pin function MUX
0= spi_ck and spi_cs in the SPI master mode
1= input pads for spi_ck_i and spi_cs_i, respectively, in the SPI slave mode
SPI_HOLD and SPI_WP pin function MUX
0= normal
1= spi_q and spi_d, respectively
2= spi_cs3 and spi_cs2, repectively
3= input pads for spi_ck_i and spi_cs_i, respectively, in the SPI slave mode
SPI_D and SPI_Q switch
1= SPI_D and SPI_Q pin-functions are swapped
0= normal
In Master mode, these are spi_ck MUX Bit[4:0] for spi_cs4 (SPI_HOLD pin), spi_cs3 (SPI_WP pin), spi_cs2,
spi_cs1 and spi_cs, respectively
1= this pin is spi_ck, if this pin is not idle
0= this pin is spi_cs, if this pin is not idle
In Master mode, these are polarity Bit[4:0] for spi_cs4 (SPI_HOLD pin), spi_cs3 (SPI_WP pin), spi_cs2, spi_cs1
and spi_cs, respectively
1= high voltage is active
0= low voltage is active
In Master mode, these are idle Bit[5:0] for SPI_CK, for spi_cs4 (SPI_HOLD pin), spi_cs3 (SPI_WP pin), spi_cs2,
spi_cs1 and spi_cs, respectively
1= idle, i.e., the spi_ck signal is 0 or the spi_cs is at the inactive level0= active if SPI controller is working

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Bit(s)
31

10:6

R/W

0

5:0

R/W

0x1E

SPIFC Slave register
Bit(s)
31
30

R/W
R/W
R/W

0xc1108cb0
Default
00

Description
SPI controller SW reset: 1 = reset, 0 = none
SPI slave mode: 1 = slave, 0 = master298/336

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R/W
R/W

Default
0

28

R/W

0

27

R/W

0

26:4
11:10

R/W
R/W

0
0

9:5

R/W

0

4
3
2
1
0

R/W
R/W
R/W
R/W
R/W

0
0
0
0
0

R/W
R/W

Default
0

26
25

R/W
R/W

0
0

24:16

R/W

0

15:10

R/W

0

9:4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

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SPIFC Slave register 2

0xc1108cb8

R/W
R/W

Default
0

23:16

R/W

0

15:8

R/W

0

7:0

R/W

0

D

Bit(s)
31:24

Bit(s)
31:24

R/W
R/W

Description
In SPI slave mode, status bit number
0 = 1 bit, 1= 2 Bits, …
In SPI slave mode, status fast read/write enable bit: 1 = enable, 0 = disable
In SPI slave mode, status read back enable bit: 1 = reading status is written status in SPI User register 3, 0 =reading status is in SPI Status register.
In SPI slave mode, buffer bit number
0 = 1 bit, 1= 2 Bits, …
In SPI slave mode, address bit number for reading buffer
0 = 1 bit, 1= 2 Bits, …
In SPI slave mode, address bit number for writing buffer
0 = 1 bit, 1= 2 Bits, …
In SPI slave mode, dummy enable bit for writing status
1=enable, 0=disable
In SPI slave mode, Dummy enable bit for reading status
1=enable, 0=disable
In SPI slave mode, Dummy enable bit for writing buffer
1=enable, 0=disable
In SPI slave mode, Dummy enable bit for reading buffer
1=enable, 0=disableH

Bit(s)
31:27

SPIFC Slave register 3dker

0xc1108cb4

ar

SPIFC Slave register 1

Description
In SPI slave mode, the enable bit for the command of write-buffer-and-read-buffer
0= disable, 1=enable
In SPI slave mode, the enable bit for the command of write-status-and-read-status
0= disable, 1=enable
SPI slave command define enable
0=Apply the last 3Bits of Flash commands and two extra command
1=Apply the user defined command in SPI Slave register 3
Reserved
spi_cs_i recovery mode:
0= and
1= or
2= normal
3= delayed
Interrupt enable for bit 4:0
1= enable, 0=disable
A SPI transition is done. (whatever it is in SPI master mode or SPI slave mode)
In SPI slave mode, a status write is done
In SPI slave mode, a status read is done
In SPI slave mode, a buffer write is done
In SPI slave mode, a buffer read is doneneBit(s)
29l

S905 Datasheet

Description
In SPI slave mode, Dummy cycle number for writing buffer
0 = 1 cycle, 1= 2 cycles, …
In SPI slave mode, Dummy cycle number for reading buffer
0 = 1 cycle, 1= 2 cycles, …
In SPI slave mode, Dummy cycle number for writing status
0 = 1 cycle, 1= 2 cycles, …
In SPI slave mode, Dummy cycle number for reading status
0 = 1 cycle, 1= 2 cycles, …

0xc1108cbC
Default
0

Description
In SPI slave mode, Command value for writing status, when bit 27 “SPI slave command define enable” in SPI
Slave register is 1

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Bit(s)
23:16

R/W
R/W

Default
0

15:8

R/W

0

7:0

R/W

0

R/W
R/W

Default
0

SPIFC controller buffer 8~15
R/W
R/W

Default
00xc1108ce0~0xc1108cfc
Description
Buffer Word 8. Buffer is used to read/write data only for APB read/write user commands.

D

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to

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Bit(s)
31:0

Description
Cache line Word 0~7. Cache is used to read data both for AHB or APB read command. Cache is also used for
APB page programming etc.

l

Bit(s)
31:0

0xc1108cc0~0xc1108cdc

ne

SPIFC controller cache 0~7

Description
In SPI slave mode, Command value for reading status, when bit 27 “SPI slave command define enable” in SPI
Slave register is 1
In SPI slave mode, Command value for writing buffer, when bit 27 “SPI slave command define enable” in SPI
Slave register is 1
In SPI slave mode, Command value for reading buffer, when bit 27 “SPI slave command define enable” in SPI
Slave register is 1

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Section VII I/O Interface
This part describes S905’s I/O interfaces from the following aspects:

ne

l

USB
Ethernet
SDIO
Transport Interface and Transport Stream Demux
ISO7816
IR Remote
SAR ADC
I2C
UART
PWM

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










37. UNIVERSAL SERIAL BUS

ar37.1 Overview

H

The chips integrates in one USB OTG (On-the-GO) controller and one USB Host controller.

to

The USB OTG controller is a Dual-Role-Device (DRD) controller that supports both device and host functions and complies fully
with the On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3a and Revision 2.0. It can also be configured as ahost-only or device-only controller, fully compliant with the USB 2.0 Specification. The USB host controller supports hostfunctions and is fully compliant with USB2.0 specification,e37.2 Features

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ut

The OTG controller features:Support for the following speeds: High-Speed (HS, 480-Mbps),Full-Speed (FS, 12-Mbps) and Low-Speed (LS, 1.5-Mbps)
modes

Multiple DMA/non DMA mode access support on the application sideSupports up to 16 bidirectional endpoints, including control endpoint 0.
Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)Supports up to 16 host channels.

D

The Host controller features:Support for the following speeds: High-Speed (HS, 480-Mbps),Full-Speed (FS, 12-Mbps) and Low-Speed (LS, 1.5-Mbps)
modes

Multiple DMA/non DMA mode access support on the application sideSupports up to 16 host channels.

38. ETHERNET MAC
38.1 Overview

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The Ethernet MAC controller provides a complete Ethernet interface from the chip to a Reduced Gigabit Media Independent
Interface (RGMII) or Reduced Media Independent Interface (RMII) compliant Ethernet PHY.

38.2 Features
10/100/1000 MAC 3.70a
RGMII/RMII
AHB 32 Bits internal bus
RX FIFO 4KB, TX FIFO 2KB
2 MAC addresses
EEEPower Management

ne

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







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38.3 Timing Specification
Management Data Timing

Fig VII.38.1. Management Data Timing Diagram

tMDC

H

ar

MD CLK

to

MD

tMDCHDetMDCSU

Min.
400
10
10

tr
ib

Description
MDC clock Period
Setup time to rising edge of MDC
Hold time to rising edge of MDC

Typ.
500

Max.

Unit
ns
ns
ns

Notes
From MAC

is

RMII Timing

D

SymboltMDC
tMDCSUtMDCHDut

Table VII.38.1. Management Data Timing Specification

Fig VII.38.2 RMII Timing Diagram

tREFCLKRMII CLKRMII RXD
RMII DVtISU

tIHD

RMII TXDRMII TX_EN
tOSU

tOHD

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Table VII.38.2.RMII Timing Specification
SymboltREFCLK
tOSU
tOHD
tISU
tIHD

Description
RMII clock period
TXD & TX_EN setup time to rising edge of RMII clock
TXD & TX_EN hold time to rising edge of RMII clock
RXD & DV setup time to rising edge of RMII clock
RXD & DV hold time to rising edge of RMII clock

Min.
1.8
1.4
1.0
1.0

Typ.
20
10
10
10
10

Max

Unit
ns
ns
ns
ns
ns

Notes
50MHz from PHY
To PHYTo PHY
From PHY
From PHY

RGMII Timingl

Fig VII.38.3 RGMII Receive Timing Diagram

netRX_CLK

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RGMII RX_CLK
tIHD0

tIHD0

RGMII RXD[3:0]
RGMII RX_DV

tISU0

tIHD1

tISU1

tIHD1

ar

tISU0

tISU1
~2ns

H

~2ns

e

Description
RGMII RX_CLK clock period
RXD[3:0] & RX_DV setup time (PHY internal delay enabled)
RXD[3:0] & RX_DV hold time (PHY internal delay enabled)
RXD[3:0] & RX_DV skew between these 5 signals (PHY internaldelay disabled)ut

SymboltRX_CLKtSETUP
tHOLD
tSKEW

to

Table VII.38.3 RGMII Receive Timing Specification
Min.

Typ.
8

1.2
1.2
-0.5

Max

0.5

Unit
ns
ns
ns
ns

Notes
125MHz from PHY
From PHY
From PHY
From PHY

Fig VII.38.4 RGMII Transmit Timing Diagram
tREFCLK

istrib

When PHY internal delay is enabled, check setup/hold timing.
When PHY internal delay is disabled, check signal skew.

D

RGMII TX_CLK

tOHD0

tOHD0

RGMII TXD[3:0]
RGMII TX_EN
tOSU0

tOSU0
tOHD1

tOSU1

tOHD1

tOSU1
~2ns

~2ns

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Table VII.38.4 RGMII Transmit Timing Specification
SymboltTX_CLKtOSU

Description
RGMII TX_CLK clock period
TXD & TX_EN setup time to rising edge of RGMII clock (no clock
delay added)
TXD & TX_EN setup time to rising edge of RGMII clock (clock
delay added)
RXD & DV hold time to rising edge of RGMII clock (no clock delay
added)
RXD & DV hold time to rising edge of RGMII clock (clock delay
added)

Typ.
8

Max

1

Unit
ns
ns

Notes
125MHz to PHY
From PHY-0.9

ns

From PHY

0.8

ns

From PHY

2.7

ns

From PHY

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l

tOHD

Min.

38.4 Register Description
R/W
R/W
R/W

Default
0
0

29-27

R/W

0

26

R/W

0

25

R/W

0

24-20

R/W

0

19-15

R/W

0

14

R/W

0

13

R/W

0

12

R/W

0

11

R/W

0

10
9-7

R/W
R/W

0
0

H

to

e

ut

tr
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is
D

6-5

R/W

0

4
3

R
R/W

0
0

2

R/W

0

1

R/W

0

Description
Set AHB to DDR interface as urgent.
RGMII mode
Use RX_CLK as TX_CLK.
RMII & RGMII mode
Select one signal from {RXDV, RXD[3:0]} to calibrate.
RMII & RGMII mode
0: test falling edge
1: test rising edge
RMII & RGMII mode
Start calibration logic
RMII & RGMII mode
5 Bits correspondent to {RXDV, RXD[3:0]}, set to 1 will delay the data capture by 1 cycle.
Set bit14 to 0.
RMII & RGMII mode
Capture input data at clock index equal to adj_delay.
Set RXDV and RXD setup time, data is aligned with index 0.
When set to 1, auto delay and skew
RMII & RGMII mode
Enable data delay adjustment and calibration logic.
RMII & RGMII mode
Enable TX_CLK and PHY_REF_CLK generator.
RMII mode
Use inverted internal clk_rmii_i to generate 25/2.5 tx_rx_clk.
Generate 25MHz clock for PHY
RMII & RGMII mode,
000: invalid value.
001: mp2_clk_out is 250MHz.
010: mp2_clk_out is 500MHz.
…
Mp2_clk_out is “ratio” *250MHz.
RGMII mode,
TX_CLK related to TXD
00: clock delay 0 cycle.
01: clock delay ¼ cycle.
10: clock delay ½ cycle.
11: clock delay ¾ cycle.
UnusedRMII mode CLK_RMIIRGMII mode RX_CLKUse inverted signal when set to 1.
Sideband Descriptor Endianness Control Function: When set high, this signal configures the DMA to transfer
descriptors in reverse endianness of the data format. When low (by default), the descriptors are transferred in
the same endian format as the data. This signal is sampled during active reset (including soft-reset) only andignored after reset is de-asserted.
Sideband Data Endianness ControlarBit(s)
31
30

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PRG_ETHERNET_ADDR0 0xc8834108

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Bit(s)

R/W

Default

0

R/W

0

Description
Function: When set high, this signal configures the DMA to transfer data in big-endian format. When low (bydefault), the data is transferred in little-endian format. This signal is sampled during active reset (including softreset) only and ignored after reset is de-asserted.
PHY Interface SelectFunction: These pins select one of the multiple PHY interfaces of MAC. This is sampled only during reset assertionand ignored after that.
1: internal value 001: RGMII
0: internal value 100: RMIIPRG_ETHERNET_ADDR1 0xc883410c
Description
UnusedThe result is valid
The results is rising edge test or falling edge test.
The signal under test.
The Calibration logic is waiting for event.
The RX_CLK length in 1ns.
Signal switch position in 1ns.

lDefault
0
0
0
0
0
0
0

ne

R/W
R
R/W
R/W
R/W
R/W
R/W
R/W

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Bit(s)
31-16
15
14
13-11
10
9-5
4-0

ar

39. SDIO

H

Please refer to eMMC/SD/SDIO part for SDIO information.

40. INTER-INTEGRATED CIRCUIT (I2C)

to40.1 Overview

uteInter-Integrated Circuit (IIC or I2C) is a multi-slave serial communication bus between ICs. S905 integrates the I2C interface andsignals allowing communications with other I2C peripheral devices.

40.2 Features

D

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The I2C Master Module has the following features:Support for 7-bit and 10-bit addressable devices
Programmable bus speed including standard speed (100kBits/s) and fast speed (400kBits/sec)
Error transfer detection“Transfer complete” indication by polling or interrupt (Interrupts handled by the ISA module. See the ISA module fordetails).
Internal buffer holding up to 8 bytes for transfer (in either direction)
Flexible architecture allowing the software to dictate the format of the I 2C bit streams

Manual setting of the I2C bus to accommodate a software only mode

40.3 Timing Specification
There are two modes to the I2C master interface: Standard (100khz) and fast (400khz).

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Fig VII.40.1 I2C Interface Timing DiagramfSCLtSCLHIGHtSCLLOWSCLtSOPHtSTARTS

tBUF

tSDAS

tSDAH

l

SDA

ne

Table VII.40.1 I2C Interface Timing Specification
Description
SCL clock frequency

Min.

tSDAS

Data setup before the rising edge of clocktSDAH

Data hold after the falling edge of clocktSTARTStBUF

Clock hold time after the falling edge of SDA when a START
command is issued
Clock setup time before the rising edge of SDA when a STOP
command is issued
Delay between start and stoptSCLLOWClock LOW timetSCLHIGH

Clock HIGH time

Std. 4.0
Fast 0.6
Std. 4.0
Fast 0.6
Std. 4.0
Fast 0.6
Std. 4.0
Fast 0.6
SoftwareControlled
Std. 8.0
Fast 1.3
Std. 8.0
Fast 1.3

40.4 Register Description

Unit
kHz

Notes

μs

-

μs

-

μs
μs
μs
μs
μs

e

to

H

ar

tSTOPHMax.
Std. 100
Fast 400dk
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Symbol
fSCL

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ut

Each register final address = 0xC1100000 + offset * 4

I2C_M_0_CONTROL_REG 0x2140
R/W
R/W

30
29-28

R
R/W

Default
0is

Bit(s)
31

D

0
0

27
26
25
24

R
R
R
R/W

0
0
0
0

23

R/W

0

22
21:12

R/W
R/W

0
0x142

Description
CNTL_JIC: There is internal logic to dynamically enable the gated clocks. If this gated clock logic doesn’t work,
you can set This bit to always enable the clock. Setting This bit wastes power.
UnusedQTR_CLK_EXT: These two Bits extend the clock divider to 12 Bits:
QTR_CLK = {[29:28],[21:12]}
unusedRead back level of the SDA line
Read back level of the SCL line
Sets the level of the SDA line if manual mode is enabled. If This bit is ‘0’, then the SDA line is pulled low. If Thisbit is ‘1’ then the SDA line is tri-stated.
Sets the level of the SCL line if manual mode is enabled. If This bit is ‘0’, then the SCL line is pulled low. If This bitis ‘1’ then the SCL line is tri-stated.
This bit is used to enable manual mode. Manual I2C mode is controlled by Bits 12,13,14 and 15 above.
QTR_CLK_DLY. This value corresponds to period of the SCL clock divided by 4
Quarter Clock Delay = * System Clock Frequency
For example, if the system clock is 133Mhz, and the I2C clock period is 10uS (100khz), then
Quarter Clock Delay = * 133 Mhz = 332

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R/W
R

Default
-

7:4

R

-

3

R

-

2

R

-

1

R/W

0

0

R/W

0

Description
READ_DATA_COUNT: This value corresponds to the number of bytes READ over the I2C bus. If this value is zero,then no data has been read. If this value is 1, then Bits [7:0] in TOKEN_RDATA_REG0 contains valid data. The
software can read this register after an I2C transaction to get the number of bytes to read from the I2C device.
CURRENT_TOKEN: This value reflects the current token being processed. In the event of an error, the software
can use this value to determine the error location.
ERROR: This read only Bit is set if the I2C device generates a NACK during writing. This bit is cleared at on theclock cycle after the START Bit is set to 1 indicating the start of list processing. Errors can be ignored by setting
the ACK_IGNORE Bit(s) below. Errors will be generated on Writes to devices that return NACK instead of ACK. A
NACK is returned by a device if it is unable to accept any more data (for example because it is processing someother real-time function). In the event of an ERROR, the I2C module will automatically generate a STOP conditionon the bus.
STATUS: This bit reflects the status of the List processor:
0: IDLE
1: Running. The list processor will enter this state on the clock cycle after the START Bit is set. The software
can poll the status register to determine when processing is complete.
ACK_IGNORE: Set to 1 to disable I2C ACK detection. The I2C bus uses an ACK signal after every byte transfer todetect problems during the transfer. Current Software implementations of the I 2C bus ignore this ACK. This bit
is for compatibility with the current Amlogic software. This bit should be set to 0 to allow NACK operations toabort I2C bus transactions. If a NACK occurs, the ERROR bit above will be set.
START: Set to 1 to start list processing. Setting This bit to 0 while the list processor is operating causes the list
processor to abort the current I2C operation and generate an I2C STOP command on the I2C bus. Normally Thisbit is set to 1 and left high until processing is complete. To re-start the list processor with a new list (after aprevious list has been exhausted), simply set This bit to zero then to one.

10:8

R/W

0

7:0

R/W

0x00

Description
Reserved
USE_CNTL_SCL_LOW: If This bit is set to 1, then Bits[27:16] control the SCL low time.
SCL Low delay.
UnusedSCL_FILTER: A filter was added in the SCL input path to allow for filtering of slow rise times. 0 = no filtering, 7 =max filtering
SDA FILTER: A filter was added in the SDA input path to allow for filtering of slow rise times. 0 = no filtering, 7 =max filtering
SLAVE_ADDRESS. This is a 7-bit value for a 7-bit I2C device, or (0xF0 | {A9,A8}) for a 10-bit I2C device. By
convention, the slave address is typically stored in by first left shifting it so that it’s MSB is D7 (The I2C bus assumes
the 7-bit address is left shifted one). Additionally, since the SLAVE address is always an 7-bit value, D0 is always
0.

H

Default
0
0
0
0
0

to

R/W
R
R/W
R/W
R
R/W

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ib

ut

Bit(s)
31:29
28
27:16
15:14
13-11

ar

0x2141e

I2C_M_0_SLAVE ADDRESS

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Bit(s)
11:8

isNOTE: The I2C always transfers 8-bits even for address. The I2C hardware will use D0 to dictate the direction of
the bus. Therefore, D0 should always be ‘0’ when this register is set.

I2C_M_0_TOKEN_LIST_REG0 0x2142

D

The register below describes the first 8 tokens in the token list.
Bit(s)
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

Description
8th token in the list to process
7th token in the list to process
6th token in the list to process
5th token in the list to process
4th token in the list to process
3rd token in the list to process
2nd token in the list to process
1st token in the list to process (See the table below for token definitions)

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Table VII.40.2 Token Definitions
Value

Data

Description

END

0x0

N/A

START
SLAVE_ADDR-WRITESLAVE_ADDR-READ
DATA

0x1
0x2
0x3
0x4

N/A
7-bits7-bits8-bitsDATA-LAST
STOP

0x5
0x6

8-bitsN/A

Used to tell the I2C module that this is the end of the Token list. This token is not
associated with the I2C bus, but rather with the state-machine that drives the token
list processor.
The START Token is used to tell an I2C device that this is the beginning of an I2C transfer
This bit-sequence is used to address a device and tell the device it is being WRITTENThis bit sequence is used to address a device and tell the device it is being READ.
This 8-bit byte sequence is a byte transfer (READ or WRITE). The DATA token
corresponds to a WRITE if it follows a SLAVE_ADDR-WRITE token. The DATA token
corresponds to a READ if it follows a SLAVE_ADDR-READ token.
Used to indicate the last 8-bit byte transfer is a byte transfer of a READ.
This tells the I2C device it is no longer being addressedlCommand Token

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Write data associated with the DATA token should be placed into the I2C_TOKEN_WDATA_REG0 or I2C_TOKEN_WDATA_REG1
registers. Read data associated with the DATA or DATA-LAST token can be read from the I2C_TOKEN_RDATA_REG0 or
I2C_TOKEN_RDATA_REG1 registers.

I2C_M_0_TOKEN_WDATA_REG0
R/W
R/W
R/W
R/W
R/W

Default
0x00
0x00
0x00
0x00

I2C_M_0_TOKEN_WDATA_REG1
Default
0x00
0x00
0x00
0x00

is

R/W
R/W
R/W
R/W
R/W

D

Bit(s)
31:24
23:16
15:8
7:0

I2C_M_0_TOKEN_RDATA_REG0
Bit(s)
31:24
23:16
15:8
7:0

R/W
R/W
R/W
R/W
R/W

Default
0x00
0x00
0x00
0x00

I2C_M_0_TOKEN_RDATA_REG1
Bit(s)
31:24
23:16
15:8
7:0

R/W
R/W
R/W
R/W
R/W

0x2144H

Description
4th data byte written for a DATA (write) token.
3rd data byte written for a DATA (write) token.
2nd data byte written for a DATA (write) token.
1st data byte written for a DATA (write) token.

tribBit(s)
31:24
23:16
15:8
7:0

Description
16th token in the list to process
15th token in the list to process
14th token in the list to process
13th token in the list to process
12th token in the list to process
11th token in the list to process
10th token in the list to process
9th token in the list to processtoDefault
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00

e

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

ut

Bit(s)
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0

ar

I2C_M_0_TOKEN_LIST_REG1 0x2143

Default
0x00
0x00
0x00
0x00

0x2145

Description
8th data byte written for a DATA (write) token.
7th data byte written for a DATA (write) token.
6th data byte written for a DATA (write) token.
5th data byte written for a DATA (write) token.

0x2146
Description
4th data byte read for a DATA or DATA-LAST (READ) token.
3rd data byte read for a DATA or DATA-LAST (READ) token.
2nd data byte read for a DATA or DATA-LAST (READ) token.
1st data byte read for a DATA or DATA-LAST (READ) token.

0x2146
Description
8th data byte read for a DATA or DATA-LAST (READ) token.
7th data byte read for a DATA or DATA-LAST (READ) token.
6th data byte read for a DATA or DATA-LAST (READ) token.
5th data byte read for a DATA or DATA-LAST (READ) token.

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41. UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
41.1 Overview
There are a number of UART’s in the chip that offer 2-wire (RX/TX) and 4-wire (RX/TX, CTS/RTS) connections at the digital I/O
pins. Each UART contains one transmit FIFO and a receive FIFO (see depths below). The FIFO’s are filled by the CPU and readby the CPU. In some cases, the receive FIFO can be configured to be pushed directly to DDR memory without CPU intervention.
Table VII.41.1 UART List

41.2 Features

Comment
Located in the EE domain
Located in the EE domain
Located in the EE domain
Located in the Always On domain
Located in the Always On domainlRX FIFO DMA to DDR
Yes
Yes
Yes
No
No

ne

RX/TX FIFO depths
128 bytes
64 bytes
64 bytes
64 bytes
64 bytes

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UART
UART0
UART1
UART2
UART0-AO
UART2-AO

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Input filters: The CTS (clear to send) and RX (receive) input paths have input filters to deal with slow rise times. The filters are
configurable to use a 125nS or 1uS sampling mechanism. There is an implied 3 system clock cycle delay (15nS for a typicalsystem clock of 200Mhz) that is used to synchronize and detect the rising/falling edge of the RXD signal. The RXD signal may
be passed through an optional filter to deglitch the external signal in noisy conditions. The deglitch filter has two settings which
add to the ¡§detection delay¡¨ of the RXD signal by the internal logic:Filter setting 1 (125nS strobe): 375nS ~ 2.6uSFilter setting 2 (1uS strobe): 3uS ~ 21uS
The filter is described in the register specification. If the filter is disabled, the shortest RXD low time and high time is 12 system
clock cycles (60nS for a system clock of 200Mhz).

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Clear to Send: CTS is a signal sent from the receiver UART back to the transmitting UART to tell the transmitting UART to stop
sending data. The CTS signal must be received before the next START symbol is sent. The transmitting UART is allowed to send
one more byte after the CTS signal is recognized. The CTS signal coming into the chip goes through some synchronization anddetection which adds an additional 5 system clocks (typically 25nS for a 200Mhz system clock). This setup time for CTS detection
is called CTSstop. The CTS input also has an optional filter can be used to deglitch the incoming CTS signal. If the filter is disabled,
the CTS signal must be de-asserted 5 system clock cycles before the start of the next BYTE transfer. If the CTS filter is enabled,
then additional time must be added to the 25nS requirement. There are two programmable filter settings that effectively delay
CTS being seen by the internal logic:Filter setting 1 (125nS strobe): 375nS ~ 2.6uSFilter setting 2 (1uS strobe): 3uS ~ 21uS
Interrupts: The UARTs can generate interrupts if the receive FIFO exceeds a pre-programmed threshold. An interrupt can also
be generated if there is a frame or parity error.
Clock independent operation: Because the system clock can be altered to accommodate dynamic frequency scaling, theUARTs have an option in which they use the 24Mhz crystal clock as the source for the UART.

41.3 Functional Description
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The UART requires that a Baud Rate be established. The UART supports rates as slow as 1Hz up to rates as high as 8 MBits/Sec.
Once the baud rate has been established, bytes are transmitted as they are written to the transmit-FIFO by the CPU. A largetransmit-FIFO exists to allow the CPU to pre-load a transmit package because the CPU can often write faster than the UART
can transmit the data.
Data this automatically received by the UART is placed into the receive FIFO one byte at a time. The receive-FIFO decouples
the UART from the CPU allowing the CPU to read the UART byte data at a rate not dictated by the UART.

l

Fig VII.41.1 UART Timing Diagram

ne

tLOW

TX
RX

dk
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tHIGH

Table VII.41.2 UART Timing Specification
SymboltHIGH

Description

Min.
60ns

TX/RX high time
TX/RX low time

ar

60ns

Unit

Notes

167ms

H

tLOW

Max.
167ms

41.4 Register Description

UARTx_WFIFO: Write dataeBase Address
0xc11084c0 ~ 0xc11084d4
0xc11084dc ~ 0xc11084f0
0xc1108700 ~ 0xc1108714
0xc81004c0 ~ 0xc81004d4
0xc81004e0 ~ 0xc81004f4

Default
0-

Description
unusedWrite FIFO data. The Write FIFO holds 64 bytes. The Write FIFO can be written as long as it is not full.

Default
0-

Description
unusedRead FIFO data. The Read FIFO holds 64 bytes. The empty flag can be used to determine if data is available

is

R/W
R
R/W

D

Bit(s)
31-8
7-0

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ib

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Instantiations
UART0
UART1
UART2
UART0-AO
UART2-AO

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The following register definition is uniformly applied to all UART instantiations in the chip.
Table VII.41.3 UART Register List

UARTx_RFIFO: Read Data
Bit(s)
31-8
7-0

R/W
R
R/W

UARTx_CONTROL: UART Mode
Bit(s)
31
30
29
28

R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0

27

R/W

0

Description
Invert the RTS signal
Mask Error: Set to 1 to mask errors
Invert the CTS signal
Transmit byte Interrupt: Set to 1 to enable the generation an interrupt whenever a byte is read from the transmit
FIFO
Receive byte Interrupt: Set to 1 to enable the generation an interrupt whenever a byte is written to the receive
FIFO

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Bit(s)
26
25
24
23
22
21-20
19
18
17-16
15
14
13
12
11-0

Revision 1.1.4

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
1
0
0
0
0
0
0
0x120

Description
Set to 1 to invert the TX pin
Set to 1 to invert the RX pin
Clear Error
Reset the receive state machine
Reset the transmit state machine
Character length: 00 = 8 Bits, 01 = 7 Bits, 10 = 6 Bits, 11 = 5 Bits
Parity Enable: Set to 1 to enable parity
Parity type: 0 = even, 1 = odd
Stop bit length: 00 = 1 bit, 01 = 2 Bits
Two Wire mode:
UnusedReceive Enable. Set to 1 to enable the UART receive function
Transmit Enable. Set to 1 to enable the UART transmit function
Baud rate: This value sets the baud rate by dividing the MPEG system clock.

ne

dk
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Description
Unused
UART_RECV_BUSY: This bit will be 1 if the uart receive state machine is busy
UART_XMIT_BUSY: This bit will be 1 if the uart transmit state machine is busy
RECV_FIFO_OVERFLOW:CTS Level
Transmit FIFO Empty
Transmit FIFO Full
Receive FIFO empty
Receive FIFO fullThis bit is set if the FIFO is written when it is full. To clear This bit, wriTE bit 24 of register 0x2132
Frame error. To clear This bit, wriTE bit 24 of register 0x2132
Parity error. To clear This bit, wriTE bit 24 of register 0x2132
UnusedTransmit FIFO count. Number of bytes in the transmit FIFO
UnusedReceive FIFO count. Number of bytes in the receive FIFOar

Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

H

R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

to

Bit(s)
31-27
26
25
24
23
22
21
20
19
18
17
16
15
14-8
7
8-0

l

UARTx_STATUS: UART Status

UARTx_MISC: UART IRQ CONTROL

30

R/W

0

29

R/W

0

28

R/W

0

27

R/W

0

26-24
23-20

R/W
R/W

0
0

19

R/W

0

18-16
15-8

R/W
R/W

0
32

7:0

R/W

15

R/W
R/W

Default
0isD

Description
Added a “just in case” bit that can be set to 1 to enable clocks always. The default is 0 meaning the auto-clock
gating logic is enabled.
USE old Rx Baud: There was a bug in the RX baud rate generator. The Rx baud rate generator was re-designed
to compute a baud rate correctly. If you want to use the old (stupid) logic, you can set This bit to 1.
ASYNC_FIFO_PURGE: This bit can be set to 1 after all UART bytes have been received in order to purge the data
into the Async FIFO. This bit is needed because the UART receives 8-bit data, but the ASYNC FIFO can only be
written with 16-bit data. In this case there might be a residual byte if the UART is not receiving an even numberof bytes.
ASYNC_FIFO_EN: If This bit is set to 1, then the UART received data is automatically sent to the Async FIFO module
which will in turn automatically send the data to DDR memory
CTS: Filter Timebase select: 1 = 1uS, 0 = 111nS timebase. A filter was added to the CTS input to allow for a little
digital filtering. The amount of filtering is controlled by this timebase (longer = more filtering) and the value inBits FILTER_SEL below.
CTS: FILTER_SEL: 0 = no filter, 7 = max filtering
BAUD_RATE_EXT: These 4 Bits extend the baud rate divider to 16-bits:
Baud Rate = {Reg4[23:20],Reg2[11:0]}
RX: Filter Timebase select: 1 = 1uS, 0 = 111nS timebase. A filter was added to the RX input to allow for a little
digital filtering. The amount of filtering is controlled by this timebase (longer = more filtering) and the value inBits FILTER_SEL below.
RX: FILTER_SEL: 0 = no filter, 7 = max filtering
XMIT_IRQ_CNT: The UART can be configured to generate an interrupt if the number of bytes in the transmit FIFO
drops below this value.
RECV_IRQ_CNT: The UART can be configured to generate an interrupt after a certain number of bytes have been
received by the UART.

eDefault
0

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R/W
R/W

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Bit(s)
31

UARTx_REG5
Bit(s)
31-24

Description
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Bit(s)
24

R/W
R/W

Default
0

23

R/W

0

22:0

R/W

15

Description
USE_XTAL_CLK: If This bit is set, then the clock for generating the UART Baud rate comes from the crystal pad.
This allows the UART to operate independent of clk81.
USE New Baud rate. Over the years, the baud rate has been extended by concatenating Bits from different
registers. To take advantage of the full 23-bit baud rate generate (extended to 23 Bits to accommodate very low
baud rates), you must set This bit. If This bit is set, then the baud rate is configured using Bits [22:0] below
NEW_BAUD_RATE: If Bit[23] = 1 above, then the baud rate for the UART is computed using these Bits.

42. INFRARED REMOTE

nel

42.1 Overview

dker

An IR signal based Remote Control (RC) signal decoder and blaster are built in S905 to provide software a low-cost, convenient
way to implement remote control function in applications. This module is located in the AO power domain.

42.2 Decoder Functional Description

The function diagram of IR decoder is illustrated in the figure below.

ar

The decoder mainly consisted of two blocks: Decoder with input filter A set of registers including control & clock, data and tuning

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Fig VII.42.1 IR Decoder Function BlockIR Decoder decodes the IR remote control input signal. 13 operation modes are supported:Hardware Decode IR transmission protocol compatible frame decoder mode ( NEC MITSUBISHI Thomson Toshiba Sony
SIRC RC5 RC6 RCMM Duokan Comcast Sanyo Modes)
General programmable time measurement frame decoder mode (General Mode)
In Hardware Decode Mode, the Decoder uses signal pattern search mechanism to decode data frame. It can detect logical‘0’ ,‘1’ ,“00”,”01”,”10” and ”11”, as well as data frame start and end. Whenever Decoder detects and decodes the data frame,
the data are kept in data register.

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In General Mode, the Decoder uses edge detection mechanism to decode data frame. It can detect each input signal edge andrecord the time between two edges. The time measurement result is kept in control register.
The user should set proper operation mode corresponding to the selection of remote controller.
There is a simple time-based signal Filter between the signal input and the Decoder. The Filter is programmable and helps toimprove signal integrity.

l42.3 NEC Infrared Transmission Protocol Example

neMessage Bit

Standard NEC IR transmission protocol uses pulse distance encoding of the message Bits. The basic clock circle time is 562.5us.

dker

The logical Bits are defined and transmitted as follow:•
Logical ‘0’ – a 562.5us pulse burst (1 clock) followed by a 562.5us space (1 clock). The total transmit time is 1.125ms.
•
Logical ‘1’ – a 562.5us pulse burst (1 clock) followed by a 1.6875ms space (3 clocks). The total transmit time is 2.25ms.
The signals are illustrated in the picture below.

Logical ‘0’

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Fig VII.42.2 Message Bit Signal

562.5us

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562.5us

Logical ‘1’

is1687.5usD

Data Frame

562.5us

A data transmit frame is exchanged via IR to represent a message when a key is pressed on the remote control. Typically, thedata frame consists of, in order:•
A Leading Active – 9ms pulse burst (16 clocks)•
A Leading Idle – 4.5ms space (8 clocks)•
An 8-bit receiver address (ADDR), LSB first.
•
The complementary 8-bit receiver address (), LSB first•An 8-bit command (CMD), LSB first•
The complementary 8-bit command (), LST first•A final 562.5us pulse burst to indicate the end of message transmission.
The byte ADDR/ and CMD/ are sent with least significant bit (LSB) first.

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The example of data frame is illustrated below with ADDR=0x00 and CMD=0xAD.
Fig VII.42.3. Data FrameEnd
ADDR(0x00)LSB

ADDR(0xFF)

CMD(0xAD)

LSB

LSB

LSB

9ms

Address

Address (Logical Inverse)

CommandCommand(Logical inverse)

dk
er

4.5ms

CMD
(0x52)

l

Leading
Idle

ne

Leading
Active27ms

27ms

Repeat Code(s)arA repeat code will be issued if the key on the remote controller is kept pressed. A repeat code will continue to be sent out at
108ms intervals until the key is released.

e

The example of repeat code is illustrated below

toH

Typically, the repeat code consists of, in order:•
A Leading Active – 9ms pulse burst (16 clocks)•
A Leading Idle – 2.25ms space (4 clocks)•
A final 562.5us pulse burst to indicate the end of message transmission.

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Fig VII.42.4. Repeat Code

Repeat Code67.5ms

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Initial Message

11.8125ms

108ms

42.4 Register Description
AO_MF_IR_DEC_LDR_ACTIVE: Leader Active control

0xc8100580

This register controls the min/max Leader Active time window. For example, for NEC format, the Leader Active time is about
9mS. To identify a Leader Active time between 8.60 mS and 9.40 mS (assuming base resolution = 20uS), user can set Max
duration = 0x1d6 (‘d470) to represent 9.40 mS, and set Min duration = 0x1ae (‘d430) to represent 8.60 mS.

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Bit(s)
31-29
28-16
15-13
12-0

Revision 1.1.4

R/W
R
R/W
R
R/W

Default00
00Description
UnusedMax duration of Leader’s active part
UnusedMin duration of Leader’s active part

AO_MF_IR_DEC_LDR_IDLE: Leader Idle control
Bit(s)
31-29
28-16
15-13
12-0

R/W
R
R/W
R
R/W

Default
00000xc8100584

Description
UnusedMax duration of Leader’s idle part
UnusedMin duration of Leader’s idle part

Default
0
0

15-10
9-0

R
R/W

0
0

Description
UnusedMax duration of Repeat Code’s Leader.
In NECformat, it defines for the repeat leader’s idle part.
In Toshiba format, it defines for the repeat leader’s second idle part
(In Toshiba format, the repeat leader’s first idle part has the same duration time as the normal leader idle part.)
UnusedMin duration of Repeat Code’s Leader

ne

R/W
R
R/W

dk
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Bit(s)
31-26
25-16

l

AO_MF_IR_DEC_LDR_REPEAT: Repeat Leader Idle Time 0xc8100588

R/W
R
R/W

Default
0
0

15-10
9-0

R
R/W

0
0

Description
UnusedMax duration of Duration Setting Regiser 0.
It defines max tining duration for:
Logic”0” for NEC/Toshiba/Sony/Thomas format
orHalf trailer bit for RC6 format(RC6’s half trailer bit typically 888.89us)
ortime of Duokan/RCMM/4ppm format’s Logic “00”UnusedMin duration of Duration Setting Regiser 0.

R/W
R/W
R/W

27-25
24-12
11-0

R
R/W
R/W

D

AO_MF_IR_DEC_STATUS:
Bit(s)
31

Default
00is

Bit(s)
31
30-28

tr
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AO_MF_IR_DEC_REG0: 0xc8100590

R/W
R/W

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H

Bit(s)
31-26
25-16

ar

AO_MF_IR_DEC_BIT_0: 0xc810058C000

Description
Clock gating control just in case. Set 1 can force clock gating disabled.
Filter ctrl.
Set the monitor timing for input filter, bigger value means longer monitor time.
Value 0 = no filtering.
UnusedMax frame time. Max duration of one whole frame.
Base time parameter.
Used to generate the timing resolution.
Resolution = (base_time_paramter + 1) * (1/ Freq_sys_clk).
For example,
if Frequency of sys_clk is 1Mhz, and base_time_parameter=19,
Then resolution = (19+1)*(1uS) = 20uS.

0xc8100598
Default
0

Description
Frame data valid 1.
(This bit is set to 1 when a captured frame is updated/stored into “FrameBody_1” register. A read of“FrameBody_1” register will clear This bit. “FrameBody_1” register is used to store the over 32bit MSBs of theformats whose length is more than 32 bit )315/336

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R/W
R/W

Default
0

29-20

R/W

0

19-10
9
8

R/W
R
R

0
0
0

7
6-4

R
R

0
0

3-0

R

0

Description
bit_1_match_en. Set to 1 to enable the check of whether logic”1” bit matches timing configure during the frame
input process.
Max Duration 1. Max duration of Duration Setting Regiser 1.
It defines max duration for:
Logic”1” for NEC/Toshiba/Sony format
orWhole trailer bit for RC6 format(RC6’s whole trailer bit typically 1777.78us)ortime of Duokan/RCMM/4ppm format’s Logic “01”Min Duration 1. Min duration of Duration Setting Regiser 1.
irq_status. Appear as 1 if there is an interrupt.
ir_i_sync. IR remote serial input after synchronization.
This is the level of the digital signal coming into the IR module for decoding. This is the same as reading the I/O
pad level.
Busy. When =1, means state machine is active.
Decoder_status ( for debug only ).
000: OK
001: last frame timed out
010: leader time error (invalid IR signal)
011: repeat error (repeat leader, but other IR transitions found).
100: Invalid bit
Frame status.
bit 3: Frame data valid

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Bit(s)
30

toH(This bit is set to 1 when a captured frame is updated/stored into “FrameBody” register. A read of“FrameBody” register will clear This bit.
If store and read occurs at the same time, This bit is set to 1 in common,
But if “Hold first” is set to true and this valid Bit is already 1, a read clear takes precedance and This bit is clear to0. )bit 2: data code error (data != ~data in IR bit stream)bit1:
customcode
error(custom_code!=~custom_code
in
IR
bit
stream)bit 0: 1 = received frame is repeat key, 0 = received frame is normal key

R/W
R/W
R/W
R/W
R

15

R/W

0

14

R/W

D

0

13-8

R/W

0

Description
Set to 1 to use faster timebase. .
cntl_1us_eq_clk. Just use sys_clk to relace 1uS tick.
cntl_xtal3_eq_clk. Just use sys_clk to relace 111ns tick.
Pulse Width Counter. It stores the internal counter of pulse width duration.
Commonly used as time measurement when decode_mode is set to measure width mode (software decode).
Time measurement starts at the last time the internal time counter was reset by the rising and/or falling edge of
the IR signal. The selection of reset on rising and/or falling edge is determined by the IRQ Selection field (Bits 32 below)
Enable.
1 = enable the state machine of IR decoder.
0 = disable the state machine of IR decoder.
cntl_use_sys_clk. Use sys_clk for the timebase. It’s useful when sys_clk at low frequency ( such as 32Khz ) andcannot create 1uS timebase tick.
1 = use the system clock as timebase.
0 = use the 1uS timebase tick as timebase.
bit_length minus 1. (N-1).

0

Used to set the value of frame body’s bit length (frame body commonly includes address and data code part). If
a format has 24 bit frame body, this value shall be set to 23.
Record_at_error.

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R/W

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Bit(s)
31
30
29
28-16

7

Default
0000e

AO_MF_IR_DEC_REG1: 0xc810059C

1= record the frame body and status forcibly, even if data/custom code error check enabled by frame_mask andrelative error occurs.
0 = if data/custom code error check enabled by frame_mask and relative error occurs, not record the frame
body and status forcibly

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Bit(s)
6

R/W
R/W

Default
0

5-4

R/W

0

0

1
0

R/W
R/W

0
0

l

R/W

00 = ignore error check from either data or custom/address code
01= check if data code matches its inverse values, ignore error check from custom/address code
10= check if custom/address code matches its inverse values, ignore error check from data code
11= check if data and custom codes match their inverse values
Irq_sel. IRQ Selection and width measurement reset:
00: IR Decoder done
01: IR input rising or falling edge detected
10: IR input falling edge detected
11: IR rising edge detected
IR input polarity selection. Used to adjust/invert the polarity of IR input waveform.
Decoder Reset. Set to 1 to reset the IR decoder. This is useful because the IR remote state machine thinks interms of milliseconds and may take tens of milliseconds to return to idle by itself.

0xc81005A0

R/W
R
R/W

Default
0
0

25

R/W

0

24

R/W

0

Description
UnusedWidth_low_enable. Enable counter record of low pulse width duration.
0 = do not force enable of width low counter record
1 = force enable of width low counter record
Some IR formats’ decoding need to use internal width low counter record. By default, the width low counterrecord is enabled automatically for related formats. This bit is used for enable forcibly just in case.
Besides, if “leader plus stop bit” method is enabled for repeat detection, This bit is also need to be enabled.
Width_high_enable. Enable counter record of high pulse width duration.
0 = do not force enable of width high counter record
1 = force enable of width high counter record
Some IR formats’ decoding need to use internal width high counter record. By default, the width high counterrecord is enabled automatically for related formats. This bit is used for enable forcibly just in case.
Enable “leader plus stop bit” method for repeat detection.
0 = “leader plus stop bit” method disabled
1 = “leader plus stop bit” method enabled
Some IR formats use one normal frame's leader followed by a stop bit to represet repeat. There is no frame datain this kind repeat frame.
To use this method,
width_low_enable ( Bit 26 of 0x20 offset register) shall be set to 1,
and max_duration_3 and min_duration_3 in 0x28 offset register shall be set to appropriate value for stop bit's
timing duration.
UnusedRepeat_Bit_index.
These Bits are used for compare bit method to set the index of the bit that is used as repeat flag. The index value
can be 0 to 63.
Compare bit method is one of the methods for repeat detection . Some IR formats use one bit in frame to represet
whether the frame is repeat.
Running_count_tick_mode.
This bit is only valid when use_clock_to_counter Bit is 0.
0 = use 100uS as increasing time unit of frame-to-frame counter
1 = use 10uS as increasing time unit of frame-to-frame counter
Use_clock_to_counter.
If This bit is set to 1, the running_count_tick_mode Bit is ignored.
0 = do not use system clock as increasing time unit of frame-to-frame counter
1 = use system clock as increasing time unit of frame-to-frame counter

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Bit(s)
31-27
26

ar

AO_MF_IR_DEC_REG2

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3-2

Description
Hold_first
Used to hold the first captured frame data. If This bit is set to 1, then the “FrameBody/FrameBody_1” register
will only be updated if hasn’t already been updated. Once updated, the “FrameBody/FrameBody_1” register will
not be updated again until it has been read. This bit can be used to guarantee the first TV remote code captured
will not be overwritten by subsequent transmissions from a TV remote.
NOTE: Read the”FrameBody” register can clear the internal “Frame data valid” flag, and read the“FrameBody_1” register can clear the “Frame data valid 1” flag.
Frame_mask.
Some formats’ body include bit-inversed data or custom/address code for error check.

23-22
21-16

R
R/W

0
0

15

R/W

0

14

R/W

0

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R/W
R/W

Default
0

12

R/W

0

11

R/W

0

10

R/W

0

9

R/W

0

8

R/W

0

Description
Enable frame-to-frame time counter (running-counter).
0 = frame-to-frame time counter disabled
1 = frame-to-frame time counter enabled
If enabled, the frame-to-frame counter increases every 100uS or 10uS until it reaches its max value(all Bits are 1)
or it is reset. When it reaches its max value, it keeps the value until it is reset. When it is reset, it becomes zeroand then begin increasing again. The counter can be reset even when it has not reached its max value. The
increasing time unit can be 100uS or 10uS or system clock frequency which is set by running_count_tick_mode
and use_clock_to_counter settings.
When a frame’s data are capured and stored into FrameBody/FrameBody_1 register, frame-to-frame counter isreset to zero. After reset to zero, the frame-to-frame counter will begin increasing again, until it reaches its max
value or it is reset.
For repeat frame detection, users can use hardware detection by enabling compare frame or compare bit
method, or users can read frame-to-frame counter to let software to make the decision.
Enable repeat time check for repeat detection. This bit is valid only when compare frame method or compare Bit
method is enabled.
0 = repeat time check disabled
1 = repeat time check enabled
When repeat frame detection is enabled by enabling compare frame or compare Bit method, the frame timeinterval may need to be checked in order to decide whether the frames are repeat (key pressed without release)or not.
You can configure the repeat_time_max value by setting 0x38 offset register.
If frame interval is smaller than the “repeat time max”, it may considered as repeat.
If frame interval is bigger than the “repeat time max”, it is considered as not repeat.
Enable compare frame method for repeat detection.
0 = compare frame method disabled
1 = compare frame method enabled
Some IR formats transer the same data frame as repeat frame when the key is kept pressed without release. For
repeat detection, compare frame method can be used.
If a new frame and the old received frame are the sameand the repeat time is under the limit( frame-to-frame time counter value is smaller than the repeat_time_max ),the status register's frame_status0 is set to 1 automatically as repeat detected flag.
You can configure the repeat_time_max value by setting 0x38 offset register.
Enable compare Bit method for repeat detection.
0 = compare Bit method disabled
1 = compare Bit method enabled
Some IR formats use only one bit to represet whether the frame is repeat. You can compare only one bit insteadof compare the whole frame for repeat detection. If compare frame method is enabled, then This bit is ignored.
Disable read-clear of FrameBody/FrameBody_1.
0 = read-clear enabled
1 = read-clear disabled
FrameBody/FrameBody_1 registers are read-cleared in default. When these register are read, they are cleared tozero. This bit is used to disable this read-clear feature.
( FrameBody/FrameBody_1 registers are used to store captured frame data ).
input stream bit order.
0 = LSB first mode (first bit in input stream is considered as LSB)
1= MSB first mode (first bit in input stream is considered as MSB)
Note:
Commonly the following formats shall set 1 to enable MSB first mode ( unless you insist on LSBfirst mode for yourspecified use):
RC5, RC5 extend, RC6, RCMM, Duokan, Comcast
UnusedDecode_mode.(format selection)
0x0 =NEC0x1= skip leader (just Bits, without leader)
0x2=General time measurement (measure width, software decode)
0x3=MITSUBISHI
0x4=Thomson
0x5=Toshiba
0x6=Sony SIRC
0x7=RC5

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Bit(s)
13

R
R/W

0
0

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Default

R/W
R
R/W

Default
0
0

15-10
9-0

R
R/W

0
0

AO_MF_IR_DEC_DURATN3

Description
UnusedMax duration of Duration Setting Regiser 2.
It defines max duration for:Half bit for RC5/6 format(RC5 typically 888.89us for half bit, RC6 typically 444.44us)
ortime of Duokan/RCMM/4ppm format’s Logic “10”ortime of Comcast/16ppm’s base duration
UnusedMin duration of Duration Setting Regiser 2.

0xc81005A8

R/W
R
R/W

Default
0
0

15-10
9-0

R
R/W

0
0

Description
UnusedMax duration of Duration Setting Regiser 3.
It defines max duration for:
Whole bit for RC5/6 format(RC5 typically 1777.78us for whole bit, RC6 typically 888.89us)
ortime of Duokan/RCMM/4ppm format’s Logic “11”ortime of Comcast/16ppm’s offset duration
UnusedMin duration of Duration Setting Regiser 3.

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0xc81005B8

R/W
R
R/W

Default
00Dis

Bit(s)
31-20
19-0

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AO_MF_IR_DEC_REG3etoBit(s)
31-26
25-16

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Bit(s)
31-26
25-16

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0xc81005A4

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AO_MF_IR_DEC_DURATN2

Description
0x8=Reserved
0x9=RC60xA=RCMM
0xB=Duokan
0xC=Reserved
0xD=Reserved
0xE=Comcast
0xF=Sanyo

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Bit(s)

Revision 1.1.4

Description
UnusedRepeat time max.
Used to set the maximum time between two repeat frames for repeat frame detection.
Time unit is 100uS or 10uS according to the running_count_tick_mode.
When repeat frame detection is enabled by enabling compare frame or compare Bit method, the frame timeinterval may need to be checked in order to decide whether the frames are repeat (key pressed without release)or not.
If frame interval is smaller than the “repeat time max”, it may considered as repeat.
If frame interval is bigger than the “repeat time max”, it is considered as not repeat.

AO_MF_IR_DEC_FRAME: Frame Body ( Frame Data, LSB 32Bit )0xc8100594

Note: New keys will be ignored until FrameBody register is read if the hold first key Bit is set in the decode control register.
Reading this register resets an internal frame data valid flag.
Bit(s)
31-0

R/W
R

Default
0

Description
32 bit Read-Only register stores frame body (LSB 32 bit) captured from IR remote data flow, commonly includes
custom/address code and data code.

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AO_MF_IR_DEC_FRAME: Frame Body 1 ( Frame Data, MSB 32Bit )0xc81005AC

Note: New keys will be ignored until FrameBody register is read if the hold first key Bit is set in the decode control register.
Reading this register resets an internal frame data valid flag.
Default
0

AO_MF_IR_DEC_STATUS_1
Bit(s)
31-20
19-0

R/W
R
R

0xc81005B0

Default
00

AO_MF_IR_DEC_STATUS_2
Bit(s)
31-20
19-0

R/W
R
R

Description
Stores frame body excess 32 bit range. (MSB 32 bit)

Description
UnusedStores the last frame-to-frame counter value before the last counter reset caused by the last frame data
record/update.

0xc81005B4

Default
00

Description
UnusedStores the value of the frame-to-frame counter which is running currently.

Default
0
0
0

11-4

R/W

0

3

R/W

0

2
1
0

R/W
R/W
R/W

0
0
0

Description
unused
BUSY: If This bit is 1, then the IR Blaster module is busy.
This output is 1 when the FIFO is FullThis output is 1 when the FIFO is Empty
FIFO Level
UnusedMODULATOR_TB: This input controls the clock used to create the modulator output. The modulator is typicallyrun between 32khz and 56khz. The modulator output will equal a divided value of the following:
00: system clock “clk”
01: mpeg_xtal3_tick
10: mpeg_1uS_tick
11: mpeg_10uS_tick
SLOW_CLOCK_DIV: This is a divider value used to divide down the input “clk”. The divider is N+1 so a value of 0
equals divide by 1.
SLOW_CLOCK_MODE: Set this signal high to use a special mode in which the “clk” input is driven by a slow clock
less than 1Mhz. This is used for low power cases where we want to run the IR Blaster between 32khz and 1Mhz
INIT_LOW: Setting This bit to 1 initializes the output to be high. Please set This bit back to 0 when done
INIT_LOW: Setting This bit to 1 initializes the output to be low. Please set This bit back to 0 when done
ENABLE: 1 = Enable. If This bit is set to 0, then the IR blaster module is reset and put into an IDLE state.

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R/W
R
R
R
R
R
R/W
R/W

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Bit(s)
31-27
26
25
24
23-16
15-14
13-12

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IR_BLASTER_CNTL0 0xc81000c0

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R/W
R

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Bit(s)
31-0

IR_BLASTER_CNTL1 0xc81000c4

15-12
11-0

Default
0
0

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R/W
R/W
R/W

D

Bit(s)
31-28
27-16

R/W
R/W

0
0

Description
unusedThis value is used with “modulator_tb[1:0]” above to create a low pulse. The time is computed as(mod_lo_count+1) x modulator_tb. The purpose for having a low/high count is the modulator output might not
be 50% duty cycle. Hi/Lo counters allow us to modulate using a non-50% duty cycle waveform.
UnusedThis value is used with “modulator_tb[1:0]” above to create a high pulse. The time is computed as(mod_hi_count+1) x modulator_tb

IR_BLASTER_CNTL2 0xc81000c8

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Bit(s)
31-17
16
15-12
11-0

Revision 1.1.4

R/W
R
W
R
R/W

Default00
00Description
unusedSet This bit to 1 to write the data below to the FIFO
UnusedFIFO data to be written:
Bit[12]
output level (or modulation enable/disable: 1 = enable)
Bit[11:10]
Timebase:00 = 1uS
01 = 10uS
10 = 100uS
11 = Modulator clock
Bit[9:0]Count of timebase units to delayl

43. PULSE-WIDTH MODULATION

ne43.1 Overview

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The chip has 4 PWM modules that can be connected to various digital I/O pins, among which 3 are in EE domain and 1 is in AO
domain. Each PWM is driven by a programmable divider driven by a 4:1 clock selector. The PWM signal is generated using
two 16-bit counters. One is the High and Low counter, which is individually programmable with values between 1 and 65535.
Using a combination of the divided clock (divide by N) and the HIGH and LOW counters, a wide number of PWM configurations
are possible. The other is delta-sigma couter, generate 18-birt sigma, the PWM-out is the highest sigma. The PWM outputs
vs counters are also illustrate below.

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Fig VII.43.1 PWM Block Diagram

Fig VII.43.2 High/Low counter

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Fig VII.43.3 Delta-sigma conter, delta = 9362 & delta = 56000

D43.2 Register Description
Each PWM module contains two PWM generators call A and B, and controlled by 4 registers.
For PWM modules in EE domain, the each register’s final address = 0xc1100000 + offset*4
PWM_PWM_A 0x2154
Bit(s)
31-15
15-0

R/W
R/W
R/W

Default
00

Description
PWM_A_HIGH: This sets the high time (in clock counts) for the PWM_A generator output
PWM_A_LOW: This sets the high time (in clock counts) for the PWM_A generator output

Default
0

Description
PWM_B_HIGH: This sets the high time (in clock counts) for the PWM_A generator output

PWM_PWM_B 0x2155
Bit(s)
31-15

R/W
R/W

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Bit(s)
15-0

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R/W
R/W

Default
0

Description
PWM_B_LOW: This sets the high time (in clock counts) for the PWM_A generator output

PWM_MISC_REG_AB 0x2156
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0

2

R/W

0

1

R/W

0

0

R/W

0

Description
UnusedPWM_B_CLK_EN: Set This bit to 1 to enable PWM A clock
PWM_B_CLK_DIV: Selects the divider (N+1) for the PWM A clock. See the clock tress document
PWM_A_CLK_EN: Set This bit to 1 to enable PWM A clock
PWM_A_CLK_DIV: Selects the divider (N+1) for the PWM A clock. See the clock tress document
PWM_B_CLK_SEL: Select the clock for the PWM B. See the clock tress document
PWM_A_CLK_SEL: Select the clock for the PWM A. See the clock tress document
DS_B_EN: This bit is only valid if PWM_B_EN is 0: if This bit is set to 1, then the PWM_B output is configured togenerate a delta sigma output based on the settings in the register below. If This bit is set to 0, then the PWM_B
output is set low.
DS_A_EN: This bit is only valid if PWM_A_EN is 0: if This bit is set to 1, then the PWM_A output is configured togenerate a delta sigma output based on the settings in the register below. If This bit is set to 0, then the PWM_A
output is set low.
PWM_B_EN: If This bit is set to 1, then the PWM_B output is configured to generate a PWM output based on theregister above. If This bit is 0, then the PWM_B output is controlled by DS_B_EN above.
PWM_A_EN: If This bit is set to 1, then the PWM_A output is configured to generate a PWM output based on
the register above. If This bit is 0, then the PWM_A output is controlled by DS_A_EN above.

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Bit(s)
31-24
23
22-16
15
14-8
7-6
5-4
3

PWM_DELTA_SIGMA_AB 0x2157
Default
00

Description
DS_B_VAL: This value represents the delta sigma setting for channel B (PWM_B)
DS_A_VAL: This value represents the delta sigma setting for channel A (PWM_A)

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Bit(s)
31-15
15-0

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PWM_PWM_C 0x2194
PWM_PWM_D 0x2195

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PWM_MISC_REG_CD 0x2196

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PWM_DELTA_SIGMA_CD 0x2197

PWM_PWM_F 0x21b1

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PWM_PWM_E 0x21b0

PWM_MISC_REG_EF 0x21b2

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PWM_DELTA_SIGMA_EF 0x21b3

For PWM modules in AO domain, the each register’s final address = 0xc8100400 + offset*4
AO_PWM_PWM_A 0x54
AO_PWM_PWM_B 0x55
AO_PWM_MISC_REG_AB 0x56
AO_PWM_DELTA_SIGMA_AB 0x57

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44. ISO7816
44.1 Overview
S905 adopts ISO7816 interface for smart card.

44.2 Register Definition
Each register’s final address = 0xc1100000 + offset*4.

Default
0

30
29
28
27

R
R
R
W

0
0
0
0

26

R/W

0

25

R/W

0

24

R/W

0

23-20

R/W

0

19

R/W

0

18-16

R/W

5

D

15-0

R/W

Description
START_ATR: If This bit is set to 1, then the “answer to reset” logic that consists of a counter with two thresholds.
The counter counts 1us, 10uS, 100uS, 1mS or CLK pulses. This bit is usually set at the same time CLK_EN or
RST_LEVEL are set since smart cards either use clocks or RESET to govern the answer to reset process. See thediagram below.

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Bit(s)
31l0x2110

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This is a write only bit.
DETECT_LEVEL: Level on the detect pin
IO_LEVEL: Level on the I/O pin
unusedSTART_ATR: If This bit is set to 1, then the “answer to reset” logic that consists of a counter with two thresholds.
The counter counts 1us, 10uS, 100uS, 1mS or CLK pulses. This bit is usually set at the same time CLK_EN or
RST_LEVEL are set since smart cards either use clocks or RESET to govern the answer to reset process. See thediagram below.
RST_LEVEL: This bit sets the level on the RESET pin. This bit can be set at the same time the START_ATR Bit is set
to begin the “answer to reset” for a smartcard that uses reset.
CLK_OEN: This bit controls the output enable of the CLK pad. If This bit is set to 1, then the CLK pad is set to an
input. This allows the answer to reset logic to monitor the external clock (count external clocks).
CLK_EN: If This bit is set to 1, then the CLK output from the module is enabled. If This bit is set to 0, then the CLK
output is disabled (and set low). This bit can be set at the same time the START_ATR Bit is set to begin the “answer
to reset” for a smartcard that uses a clock.
RECV_FIFO_THRESHOLD: This value controls the number of bytes in the receive FIFO before an interrupt (orstatus bit) is generated. The receive FIFO is 8 bytes deep. If this value is set to say 6, then an interrupt will be
generated (or a status bit set) when 6 bytes have been received.
ENABLE: If This bit is 0, then all state machines are set to idle. If This bit is set to 1, then smartcard module isenabled. By default, when ENABLE is 1, the receive logic is enabled and ready to receive data.
FIRST_ETU_OFFSET: The ETU generator is reset upon seeing the falling edge of the start pulse. The time between
the start pulse falling edge to the first ½ ETU mark is shifted a little due to internal logic detecting the startingedge. This shift (delay) is approximately 185nS. For ETU values that are say 104uS, this 185nS is negligible. For
ETU values that are down near 1uS, the 185nS is a problem. This value can be used to steal back time and recenter the first ½ ETU mark in the correct position for ETU values around 1uS. This value probably never needs
to be changed.
ETU Divider. Smart Card characters are defined by a width called an ETU (Elementary Time Unit). An internal
ETU generator is used to define the width of Each Bit in a character frame. The value in this register is used todivide down the oscillator input (27Mhz) to generate an ETU. For example, the oscillator input is 47Mhz, and the
ETU is (1/9600 ) seconds (104.2uS), then this value should be programmed to 13436.

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SC_REG0

2813

104.2uS * 27Mhz = 2813
Since the counter is an N-1 counter, set the value to 2812.

SC_ANSWER_TO_RESET 0x2111
Bit(s)
31-30

R/W
R

Default
0

Description
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R/W
R/W

Default
0

27

R/W

0

26-24

R/W

0

23-16

R/W

80

15-0

R/W

8000

Description
ETU_CLK_SEL: This is a new feature in the smartcard starting with the M6TVlite chip. In the past, the ETU
generator was driven from the XTAL pin of the SOC. Although this clock is typically higher than the smartcard
clock, the ETU generator will walk a little relative to the smartcard clock. In M6TVlite and future chips, the ETU
generator can take a clock from the smartcard clock (input from the pad or output to the pad).
00: SOC Crystal
01: smartcard clock input from the Pad
10: smartcard clock generated internally and sent to the smartcard pad
11: no clock.
The advantage of using the smartcard clock (for example selection 10) is the ETU will track the smartcard clock
and the ETU divider value should match the F value of the smartcard (e.g. F = 372).
ATR_HOLDOFF_EN: If This bit is set to 1, then the Answer to Reset logic will disable the receive logic until theanswer to reset counter reaches ATR_HOLDOFF_TCNT. If This bit is set to 0, then the answer to reset logic doesn’t
effect the receive logic.
ATR_CLK_MUX: The answer to reset counter can count time or system clocks.
000: count 1uS ticks
001: count 10uS ticks
010: count 10uS ticks
011: count 10uS ticks
100: count smart card clocks (generated from inside the chip).
101:: count smart card clocks (from outside the chip).
ATR_HOLDOFF_TCNT: Answer to reset hold count. Typically 400 smartcard clocks but could also be a count oftime (see the input mux to the answer to reset counter). This value is used to disable the receive logic until theanswer to reset counter reaches the ATR_HOLDOFF_TCNT. During “Answer to Reset” the receive logic should
ignore the first 400 clocks of the smartcard output.
ATR_FINAL_TCNT: Answer to reset final count. Typically 40000 smartcard clocks but could also be a count oftime (see the input mux to the answer to reset counter). If the answer to reset counter reaches this value andwe haven’t seen a start pulse, then an ATR_EXPIRED interrupt will be generated. If a start pulse has been seenby the receiver logic, then the answer to reset logic shuts itself off.

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Bit(s)
29-28

e

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When the answer to reset logic is started by writing START_ATR, it will continue to count until:
it reaches the ATR_FINAL_TCNT
The receive logic receives one or more bytes.
Theut

If the counter reaches ATR_FINAL_TCNT (no byte received), then an ATR_EXPIRED interrupt will be generated.
ATR_EXPIRED status bit will be set in case the software wants to use polling instead of interrupts.

trib

If the receiver receives a byte before the counter reaches ATR_FINAL_TCNT, then the counter will be set to 0, and the
ATR_ENABLED status bit will be set to 0. That is, a received byte prevents the generation of the ATR_EXPIRED interrupt (andstatus bit).

SC_REG2

D

isTherefore, the software can simply start the answer to reset logic and wait for ATR_ENABLED to drop low. If ATR_ENABLED is
low and ATR_EXPIRED is high, then no byte was received. If ATR_ENABLED is low and ATR_EXPIRED is low, then a byte musthave been received.
0x2112Bit(s)
31-29
28-26

R/W
R/W
R

Default
0
0

25-23

R/W

0

22-20

R/W

0

Description
CLK_SEL: These Bits control the clock selection: See clock trees document
RECV_RETRY_CNT: If the card is sending data and we detect an error we can request a retry. This counts thenumber of retries we detected (max 7)
IO_FILTER_SEL: The I/O input signal has a small filter that allows the hardware to filter out noise on slow risetime signals. 0 = no filter. Otherwise, a filter is applied to the input using the filter window = 200nS * (n-1). Thisfilter can be used to filter out problems due to slow rise/fall times.
DET_FILTER_SEL: The DETECT input signal has a small filter that allows the hardware to filter out noise on slow
rise time signals. 0 = no filter. Otherwise, a filter is applied to the input using the filter window = 200nS * (n-1).
This filter can be used to filter out problems due to slow rise/fall times.

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R/W
R/W

Default
0

11

R/W

0

10

R/W

0

9
8
7
6
5-3

R/W
R/W
R/W
R/W
R/W

0
0
0
0
0

2
1
0

R/W
R/W
R/W

0
0
0

Description
CLK_TCNT: The frequency on the CLK pin is controlled by these Bits. These Bits are used to divide down thesystem clock to generate a clock. The divider divides the system clock by (N + 1).
PULSE_IRQ: Set This bit to 1 if you want the smartcard module to generate a pulse interrupt to the CPUs. In
previous smartcard designs, the smartcard module would generate a level interrupt. The interrupt routine would
need to clear the interrupt in the smartcard instead of just in the ISA module.
RECV_NO_PARITY: Ignore parity. This bit can be used to tell the receiver module to ignore the parity of thereceived character. This is useful during debug.
RECV_PARITY: 1 = Invert Parity during receiving
RECV_LSBMSB: 1 = Swap MSBits / LsBits during receiving
RECV_INVERT: 1 = invert the data Bits (excluding the parity) during receiving
XMIT_REPEAT_DIS: Set This bit to 1 to disable character repeats when an error is detected.
XMIT_RETRIES: Number of attempts to make sending a character. In the event the CARD responds with an Error,
the smart card module will attempt to re-send the character "N" times. If the value in this register is 1, then thetransmitter will only send the character once. If there is an error returned by the CARD, then we will not try again.
The value in these Bits should be greater than or equal to 1.
XMIT_PARITY: 1 = Invert Parity
XMIT_LSBMSB: 1 = Swap MSBits / LSBitsXMIT_INVERT: 1 = invert the data Bits (excluding the parity)dker

0x2113

R

0

6
5

R
R

0
0

4
3
2
1
0

R
R
R
R
R

0
0
0
0
0

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SC_INTERRUPT_REG

ar7

Description
True if the Answer to Reset logic is counting and waiting for a byte to be received from the smart card.
True if the transmitter module is enabled. This will be true if there are bytes in the transmit FIFO
True if the receiver module is enabled (not transmitting)
True if the receiver module is in the process of receiving a byte from the smart card
True if the transmit FIFO is FULL (contains 8 bytes)
True if the transmit FIFO is empty
Number of bytes in the Transmit FIFO
True if the receive FIFO is FULL (contains 8 bytes)
True if the receive FIFO is empty
Number of bytes in the Receive FIFO
unusedTrue if Card Detect Interrupt
True if Answer to Reset expired. This will occur if START_ATR is issued and no bytes are received from the smart
card in the programmed time frame.
True if there was a transmission error. That is, the card responded with an Error when we transferred a byte to
the smart card.
True if there was a receive error (parity error)
True if the CPU tried to write a byte to the transmit FIFO while the receiver was still receiving data. Transmitting
and receiving data are mutually exclusive (guaranteed by hardware / software)
True if the receiver tried to write to a full receiver FIFO
True if the Block Wait Time (BWT) expired
True if the Character Wait Time (CWT) expired
True if the last byte in the transmit FIFO was transferred to the smart card
True if the number of bytes in the receive FIFO is greater than or equal to RECV_FIFO_THRESHOLD.

H

Default
0
0
0
0
0
0
0
0
0
0
0
0
0

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R/W
R
R
R
R
R
R
R
R
R
R
R
R
R

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Bit(s)
31
30
29
28
27
26
25-22
21
20
19-16
15-10
9
8

e

SC_STATUS_REG

nel

Bit(s)
19-12

0x2114The interrupt register has two parts. The bottom 11 Bits contain the interrupt status of those interrupts that have acorresponding mask bit set to 1. If you write the bottom 11 Bits with a 1, then the corresponding interrupt will be cleared. The
upper 11 Bits are the mask enables for the interrupts. The status of disabled interrupts can still be seen in the status register.
For example: To generate an interrupt if the Answer to Reset expires, simply Set bit 24 below. If answer to reset expires, thenbit 8 will be set below and an interrupt will be generated. To clear the interrupt simply wriTE bit 8 with a 1. Note: You canalso see the status of the interrupts in the STATUS register.

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Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3
2

R/W
R/W

0
0

1

R/W

0

0

R/W

0

Bit(s)
31-20
19

R/W
R
R/W

Default
0
0

18

R/W

0

17

R/W

0

16

R/W

0

R/W

999

R/W
R

Default
0

dk
er

ar

H

to

e

0x211515-0

SC_REG6

Description
unusedMASK for Bit[9] below. Set to 1 to enable this interrupt.
MASK for Bit[8] below. Set to 1 to enable this interrupt.
MASK for Bit[7] below. Set to 1 to enable this interrupt.
MASK for Bit[6] below. Set to 1 to enable this interrupt.
MASK for Bit[5] below. Set to 1 to enable this interrupt.
MASK for Bit[4] below. Set to 1 to enable this interrupt.
MASK for Bit[3] below. Set to 1 to enable this interrupt.
MASK for Bit[2] below. Set to 1 to enable this interrupt.
MASK for Bit[1] below. Set to 1 to enable this interrupt.
MASK for Bit[0] below. Set to 1 to enable this interrupt.
unusedTrue if Card Detect Interrupt.
True if Answer to Reset expired and the Mask bit above is set. This will occur if START_ATR is issued and no bytes
are received from the smart card in the programmed time frame. Writing This bit will clear this interrupt.
True if there was a transmission error and the Mask bit above is set. That is, the card responded with an Error
when we transferred a byte to the smart card. Writing This bit will clear this interrupt.
True if there was a receive error (parity error) and the Mask bit above is set. Writing This bit will clear thisinterrupt.
True if the CPU tried to write a byte to the transmit FIFO while the receiver was still receiving data. Transmitting
and receiving data are mutually exclusive (guaranteed by hardware / software) and the Mask bit above is set.
Writing This bit will clear this interrupt.
True if the receiver tried to write to a full receiver FIFO and the Mask bit above is set. Writing This bit will clear
this interrupt.
True if the Block Wait Time (BWT) expired and the Mask bit above is set. Writing This bit will clear this interrupt.
True if the Character Wait Time (CWT) expired and the Mask bit above is set. Writing This bit will clear thisinterrupt.
True if the last byte in the transmit FIFO was transferred to the smart card and the Mask bit above is set. Writing
This bit will clear this interrupt.
True if the number of bytes in the receive FIFO is greater than or equal to RECV_FIFO_THRESHOLD and the Mask
bit above is set. Writing This bit will clear this interrupt.

l

R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W

ne

Bit(s)
31-26
25
24
23
22
21
20
19
18
17
16
15-10
9
8

ut

Description
ETU_MSR_CNT: This value represents the ETU measured value. The value has a resolution of 1uS
RECV_ETU_ERROR_CNT: According to the specification, if there is a parity error on receive the smartcard module
will generate an error ether 1 or two ETU’s wide. In previous designs the ERROR pulse was 1 ETU wide. If This bit
is set to 1, then an ERROR pulse that is 2 ETU’s wide will be generated.
ETU_MSR_EN: If This bit is set, then the hardware will measure the time between the first falling edge of the IO
pin to the next rising edge of the I/O pin. This can be used to measure the ETU of a card in the event that the ETU
is not known.
CWT_DETECT_EN: Set This bit to detect character wait time violations. The CWT is defined as the maximum time
between the leading edge of two consecutive characters in the same block. The CWT may be used by the receiving
node to detect the end of a block. That is, if the CWT is expired, then the card is not sending any more data.
BTW_DETECT_EN: Set This bit to detect block wait time violations. The Block wait time is the time between theleading edges of two characters in opposite directions. The BWT is used to detect an unresponsive card.
Block Wait Time Base time generator. This counter counts 1mS ticks. These ticks are counted by the Block Wait
Time logic to identify block wait time violations. The counter corresponds to (N+1) * 0.001 Seconds.

tr
ib

is

D

SC_REG5

Revision 1.1.4

0x2116Bit(s)
31-24

Description
Unused327/336

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S905 Datasheet

Bit(s)
23-20

Revision 1.1.4

R/W
R/W

Default
4

Description
BWI: The BWI is used to define the Block Wait Time (BWT). The BWT is defined as+ 11 work ETU
Since the time frame for the Block Wait Time is long (seconds) relative to the speed of the system clock, the Block
Wait Time is re-defined without the 11 work ETU’s to reduce logic:

The BWT_TIME_BASE is established in Control Register 5.

l

For example, if the BWT_TIME_BASE is set to pulse every 146nS, and BWI is set to 10 (decimal), then the Block
Wait Time will expire at 146nS * 1024 = 149.5uS.

20

11-8

R/W

13

7-0

R/W

0

ne

R/W

dk
er

19-12

Note: The block Wait time can be used to determine an unresponsive card. Status bit 18 of Control Register 4
indicates that the Block Wait Time has expired. An interrupt can also be generated in the event that the Block
Wait Time expires. Typically the Block Wait Time logic is reset at the beginning of a transmitted character.
BGT: Block Guard Time. The block guard time is defined as the minimum time between the leading edges of twoconsecutive characters sent in opposite directions. This value defines the BGT in an (N+2) relationship. For
example, a value of 20 corresponds to a BGT of 22 work ETU.
CWI value. The CWT is defined as the wait time between characters. The CWI value defines the CTW time as (2CWI + 11) work ETU
N parameter: the N parameter is used to provide extra guard time between characters.

R/W
R
R/W

Default
00

Description
UnusedWriting this register writes the Transmit FIFO
Reading this register reads the Receive FIFO

to

Bit(s)
31-8
7-0

H0x2117e

SC FIFOarxmit_char_time = (N_param == 8'd255) ? 'd10 : ('d11 + N_param);ut

45. SAR ADC

trib

45.1 Overview

DisThis SAR ADC is a general purpose ADC for measuring analog signals. The module can make RAW ADC measurements or
average a number of measurements to introduce filtering. The SAR ADC is a single block so an analog mux is placed in frontof the mux to allow multiple different measurements to be made sequentially. Timing of the samples, and delays between
muxing are all programmable as is the averaging to be applied to the SAR ADC.

45.2 Register Description
Each register final address = 0xC1100000 + offset * 4
SAR_ADC_REG0: Control Register #0
Bit(s)
31
30
29
28
27
26

R/W
R
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0

0x21a0Description
PANEL DETECT level.
DELTA_BUSY: If This bit is 1, then it indicates the delta processing engine is busy
AVG_BUSY: If This bit is 1, then it indicates the averaging engine is busy
SAMPLE_BUSY: If This bit is 1, then it indicates the sampling engine is busy
FIFO_FULL:FIFO_EMPTY:

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Revision 1.1.4

R/W
R/W
R/W
R/W
R/W
R/W

Default
4
0
0
0
0

13-12

R/W

0

11
10

R/W
R/W

0
0

9

R/W

0

8-4
3
2
1
0

R/W
R/W
W
R/W
R/W

0
0
0
0
0

Description
FIFO_COUNT: Current count of samples in the acquisition FIFO
ADC_BIAS_CTRL
CURR_CHAN_ID: These Bits represent the current channel (0..7) that is being sampled.
ADC_TEMP_SEN_SEL
SAMPLING_STOP: This bit can be used to cleanly stop the sampling process in the event that continuous samplingis enabled. To stop sampling, simply set This bit and wait for all processing modules to no longer indicate thatthey are busy.
CHAN_DELTA_EN: There are two Bits corresponding to Channels 0 and 1. Channel 0 and channel 1 can be
individually enabled to take advantage of the delta processing module.
UnusedDETECT_IRQ_POL: This bit sets the polarity of the detect signal. The detect signal is used during X/Y panel
applications to detect if the panel is touched
DETECT_IRQ_EN: If This bit is set to 1, then an interrupt will be generated if the DETECT signal is low/high. The
polarity is set in the bit above.
FIFO_CNT_IRQ: When the FIFO contains N samples, then generate an interrupt (if bit 3 is set below).
FIFO_IRQ_EN: Set This bit to 1 to enable an IRQ when the acquisition FIFO reaches a certain level.
SAMPLE_START: This bit should be written to 1 to start sampling.
CONTINUOUS_EN: If This bit is set to 1, then the channel list will be continually processed
SAMPLING_ENABLE: Setting This bit to ‘1’ enables the touch panel controller sampling engine, averaging module,
XY processing engine and the FIFO.

dk
er

ne

l

Bit(s)
25-21
20-19
18-16
15
14

SAR_ADC_CHAN_LIST:Channel List 0x21a1

ar

Description
unusedLength of the list of channels to process. If this value is 2, then only channels in Bits [8:0] below are processed.
8th channel
7th channel
6th channel
5th channel
4th channel
3rd channel
2nd channelFirst channel in the list of channels to process

H

Default
0
2
7
6
5
4
3
2
1
0

to

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

e

Bit(s)
31-27
26-24
23-21
20-18
17-15
14-12
11-9
8-6
5-3
2-0

ut

SAR_ADC_AVG_CNTL:Sampling/Averaging Modes 0x21a2

trib

Each channel listed in the CHANNEL_LIST is given independent control of the number of samples to acquire and averaging
mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Default
0
0
0
0
0
0
0
0

15-13
13-12
11-10
9-8
7-6
5-4
3-2
1-0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0
0
0
0
0
0
0
0

D

is

Bit(s)
31-30
29-28
27-26
25-24
23-22
21-20
19-18
17-16

Description
Channel 7: Averaging mode: 0 = no averaging, 1 = simple averaging, 2 = median averaging.
Channel 6: Averaging mode: 0 = no averaging, 1 = simple averaging, 2 = median averaging.
Channel 5: Averaging mode: 0 = no averaging, 1 = simple averaging, 2 = median averaging.
Channel 4: Averaging mode: 0 = no averaging, 1 = simple averaging, 2 = median averaging.
Channel 3: Averaging mode: 0 = no averaging, 1 = simple averaging, 2 = median averaging.
Channel 2: Averaging mode: 0 = no averaging, 1 = simple averaging, 2 = median averaging.
Channel 1: Averaging mode: 0 = no averaging, 1 = simple averaging, 2 = median averaging.
Channel 0: Averaging mode: 0 = no averaging. 1 = simple averaging of the number of samples acquired (1,2,4
or 8). 2 = median averaging. NOTE: If these Bits are set to 2, then you must set the number of samples to acquire
below to 8.
Channel 7: Number of samples to acquire 2N:
Channel 6: Number of samples to acquire 2N:
Channel 5: Number of samples to acquire 2N:
Channel 4: Number of samples to acquire 2N:
Channel 3: Number of samples to acquire 2N:
Channel 2: Number of samples to acquire 2N:
Channel 1: Number of samples to acquire 2N:
Channel 0: Number of samples to acquire 2N: 0 = 1, 1 = 2, 2 = 4, 4 = 8.

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Revision 1.1.4

0x21a3

TEMP_MODE
temp sensor
SAR_ADC_CH6

SAR_ADC_CTRL[2:0]Control logic
1
0

7
6
5
4
3
2
1
0

SAR_ADC_CH5

SAR_ADC_CH0

Default
0

30
29
28
27
26
25~23

R/W
R/W
R/W
R/W
R/W
R/W

0
0
0
0
0
0

22

R/W

0

21
20-18

R/W
R/W

0
2

17-16
15-10

R/W
R/W

Description
CNTL_USE_SC_DLY: hold time delay was added to the start conversion clock. Unfortunately, it appears that theanalog ADC design requires that we use the inverted clock so This bit is meaningless.
SAR ADC_CLK_EN: 1 = enable the SAR ADC clock
reserved
reserved
SARADC_CTRL[4]: is used to control the internal ring counter. 1 = enable the continuous ring counter. 0 = disable
SARADC_CTRL[3]: used to select the internal sampling clock phase
SARADC_CTRL[2:0]:000 ssa
001 vdda/4010 vdda/2
011 vdda*3/4
100 vdda
101, 110, 111 unused
DETECT_EN: This bit controls the analog switch that connects a 50k resistor to the X+ signal. Setting This bit to
1 closes the analog switch
ADC_EN: Set This bit to 1 to enable the ADC
PANEL_DETECT_COUNT: Increasing this value increases the filtering on the panel detect signal using the timebase
settings in Bits [17:16] below.
PANEL_DETECT_FILTER_TB: 0 = count 1uS ticks, 1 = count 10uS ticks, 2 = count 100uS ticks. 3 = count 1mS ticks
ADC_CLK_DIV: The ADC clock is derived by dividing the 27Mhz crystal by N+1. This value divides the 27Mhz
clock to generate an ADC clock. A value of 20 for example divides the 27Mhz clock by 21 to generate an equivalent
1.28Mhz clock.
BLOCK_DLY_SEL: 0 = count 1uS ticks, 1 = count 10uS ticks, 2 = count 100uS ticks. 3 = count 1mS ticks
BLOCK_DLY: After all channels in the CHANNEL_LIST have been processed, the sampling engine will delay for an
amount of time before re-processing the CHANNEL_LIST again. Combined with Bits [9:8] above, this value is used
to generate a delay between processing blocks of channels.

ar

R/W
R/W

SAR ADC

is

D

9-8
7-0

tr
ib

ut

e

to

H

Bit(s)31l

VDD
VDD*3/4
VDD/2
VDD/4
VSS

7
6
5
4
3
2
1
0

ne

SAR_ADC_CH7

dk
er

SAR_ADC_REG3: Control Register #3

R/W
R/W

0
20

1
10

SAR_ADC_DELAY:INPUT / SAMPLING DELAY 0x21a4
As the CHANNEL_LIST is process, the input switches are set according to the requirements of the channel. After setting theswitches there is a programmable delay before sampling begins. Additionally, each channel specifies the number of samples
for that particular channel. The sampling rate is programmed below.
Bit(s)
15-10

R/W
R

Default
0

Description
unused330/336

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S905 Datasheet

Revision 1.1.4

Bit(s)
25-24
16-23

R/W
R/W
R/W

Default
0
3

15-10
9-8
7-0

R
R/W
R/W

0
0
9

SAR_ADC_LAST_RD: Last Sample

Description
INPUT_DLY_SEL: 0 = 111nS ticks, 1 = count 1uS ticks, 2 = count 10uS ticks, 3 = count 100uS ticks
INPUT_DLY_CNY: For channels that acquire 2,4 or 8 samples, the delay between two samples is controlled bythis count (N+1) combined with the delay selection in the two Bits above.
unusedSAMPLE_DLY_SEL: 0 = count 1uS ticks, 1 = count 10uS ticks, 2 = count 100uS ticks. 3 = count 1mS ticks
SAMPLE_DLY_CNY: For channels that acquire 2,4 or 8 samples, the delay between two samples is controlled bythis count (N+1) combined with the delay selection in the two Bits above.

0x21a5

R/W
R
R
R
R

Default00
00Description
unusedLAST_CHANNEL1
unusedLAST_CHANNEL0dker

Bit(s)
31-24
23-16
15-10
9-0

ne

l

For channel 0 and channel 1, (the special X/Y channels) the last sample pushed into the FIFO for each channel is saved in aregister. This allows the software to see the last sample for channel 0 and channel 1 even when the FIFO overflows. For
example, if we are sampling quickly and there is a gesture on the screen, we can use the contents of the FIFO to see thedirection of the gesture and use the last sample values to see where the pen finally came to rest.

SAR_ADC_FIFO_RD: Control Register #6 (FIFO RD) 0x21a6
Default000
00Description
UnusedUnusedChannel ID. This value identifies the channel associated with the data in Bits [9:0] below
UnusedSample value: 9-bit raw or averaged ADC sample written to the FIFO.

ar

R/W
R
R
R
R
R

H

Bit(s)
31-16
15
14-12
11-10
9-0

to

SAR_ADC_AUX_SW:Channel 2~7 ADC MUX, Switch Controls 0x21a7

Description
unusedChannel 7 ADC_MUX setting when channel 7 is being measured.
Channel 6 ADC_MUX setting when channel 6 is being measured.
Channel 5 ADC_MUX setting when channel 5 is being measured.
Channel 4 ADC_MUX setting when channel 4 is being measured.
Channel 3 ADC_MUX setting when channel 3 is being measured.
Channel 2 ADC_MUX setting when channel 2 is being measured.
unused
VREF_P_MUX setting when channel 2,3..7 is being measured
VREF_N_MUX setting when channel 2,3..7 is being measured
MODE_SEL setting when channel 2,3..7 is being measured
YP_DRIVE_SW setting when channel 2,3..7 is being measured
XP_DRIVE_SW setting when channel 2,3..7 is being measured
YM_DRIVE_SW setting when channel 2,3..7 is being measured
YM_DRIVE_SW setting when channel 2,3..7 is being measured

tribDefault
0
7
7
7
6
0
1
0
0
0
0
1
1
0
0

is

R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W

D

Bit(s)
31-26
25-23
22-20
19-17
16-14
13-11
10-8
7
6
5
4
3
2
1
0

ut

e

Channels 2 ~ 7 can program the ADC input mux to any selection between 0 and 7. This register allows the software to associate
a mux selection with a particular channel. In addition to the ADC mux, there are a number of switches that can be set in any
particular state. Channels 2 ~ 7 share a common switch setting. Channels 0 and 1 on the other hand have programmableswitch settings (see other registers below).

SAR_ADC_CHAN_10_SW:Channel 0, 1 ADC MUX, Switch Controls 0x21a8
Channels 0 and 1 have independent programmable switch settings when either/both of these channels are being measured.
Bit(s)
31-26
25-23
22

R/W
R
R/W
R/W

Default02
0Description
unusedChannel 1 ADC MUX setting
Channel 1 VREF_P_MUX

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Revision 1.1.4

1

17

R/W

0

16

R/W

0

15-10
9-7
6
5
4
3

R
R/W
R/W
R/W
R/W
R/W

3
0
0
0
1

2

R/W

1

1

R/W

0

0

R/W

0

ne

R/W

dk
er

18

Description
Channel 1 VREF_N_MUXChannel 1 MODE_SEL
Channel 1 YP_DRIVE_SW setting:
0: TADC_CH6N = 3.3v
1: TADC_CH6N = floating
Channel 1 XP_DRIVE_SW setting:
0: TADC_CH6N = 3.3v
1: TADC_CH6N = floating
Channel 1 YM_DRIVE_SW setting:
0: TADC_CH4N = floating
1: TADC_CH4N = GND
Channel 1 YM_DRIVE_SW setting:
0: TADC_CH4N = floating
1: TADC_CH4N = GND
unusedChannel 0 ADC MUX setting
Channel 0 VREF_P_MUXChannel 0 VREF_N_MUXChannel 0 MODE_SEL
Channel 0 YP_DRIVE_SW setting:
0: TADC_CH6N = 3.3v
1: TADC_CH6N = floating
Channel 0 XP_DRIVE_SW setting:
0: TADC_CH6N = 3.3v
1: TADC_CH6N = floating
Channel 0 YM_DRIVE_SW setting:
0: TADC_CH4N = floating
1: TADC_CH4N = GND
Channel 0 YM_DRIVE_SW setting:
0: TADC_CH4N = floating
1: TADC_CH4N = GND

ar

Default
0
0
1

H

R/W
R/W
R/W
R/W

to

Bit(s)
21
20
19

lS905 Datasheet

SAR_ADC_DETECT_IDLE_SW:DETECT / IDLE Mode switches

0x21a9ute

IDLE MODE:
When nothing is being measured, the switches should be put into a safe state. This safe state is accomplished using Bits [9:0]
below.

D

is

tr
ib

DETECT MODE:
When bit [26] is set, the input muxes / switches are configured according to the Bits below. Typically the software configures
the switches below to correspond to the detect touch mode. That is, Y- internal MOSFET is closed so that the Y plane of thetouch screen is connected to Ground. Additionally, the DETECT_EN bit(different register) set to 1 so that the 50k resistor to
VDD is connected to X+. In this configuration, the detect comparator connected to the 50k resistor will be weakly pulled up to
VDD through the 50k resistor. If the user touches the screen, the X and Y planes of the touch screen will contact causing theX+ signal to be pulled to ground.
Bit(s)
31-27
26

R/W
R
R/W

Default
0
0

25-23
22
21
20
19

R/W
R/W
R/W
R/W
R/W

5
0
0
0
1

18

R/W

1

Description
unusedDETECT_SW_EN: If This bit is set, then Bits [25:16] below are applied to the analog muxes/switches of the touch
panel controller.
DETECT MODE ADC MUX setting
DETECT MODE VREF_P_MUX setting
DETECT MODE VREF_N_MUX setting
DETECT MODE MODE_SEL setting
DETECT MODE YP_DRIVE_SW setting:
0: TADC_CH6N = 3.3v
1: TADC_CH6N = floating
DETECT MODE XP_DRIVE_SW setting:
0: TADC_CH6N = 3.3v
1: TADC_CH6N = floating

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Revision 1.1.4

16

R/W

0

15-10
9-7
6
5
4
3

R
R/W
R/W
R/W
R/W
R/W

5
0
0
0
1

2

R/W

1

1

R/W

0

0

R/W

0

Description
DETECT MODE YM_DRIVE_SW setting:
0: TADC_CH4N = floating
1: TADC_CH4N = GND
DETECT MODE YM_DRIVE_SW setting:
0: TADC_CH4N = floating
1: TADC_CH4N = GND
UnusedIDLE MODE ADC MUX setting
IDLE MODE VREF_P_MUX setting
IDLE MODE VREF_N_MUX setting
IDLE MODE MODE_SEL setting
IDLE MODE YP_DRIVE_SW setting:
0: TADC_CH6N = 3.3v
1: TADC_CH6N = floating
IDLE MODE XP_DRIVE_SW setting:
0: TADC_CH6N = 3.3v
1: TADC_CH6N = floating
IDLE MODE YM_DRIVE_SW setting:
0: TADC_CH4N = floating
1: TADC_CH4N = GND
IDLE MODE YM_DRIVE_SW setting:
0: TADC_CH4N = floating
1: TADC_CH4N = GNDlDefault
0

ne

R/W
R/W

dk
er

Bit(s)
17

Description
unusedTEMP_SEL
TS_REVE[1]Channel 1 delta value when delta processing for channel 1 is enabled.
TS_REVE[0]
TS_C[3:0]
TS_VBG_EN
Channel 0 delta value when delta processing for channel 0 is enabled.

H

Default
0

0

to

R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0
0

D

is

tr
ib

ut

e

Bit(s)
31-28
27
26
25-16
15
14-11
10
9-0

ar

SAR_ADC_DELTA_10:Delta Mode Deltas 0x21aa

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S905 Datasheet

Revision 1.1.4

Section VIII System Interface
46. JTAG
46.1 Overview

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47.1 Overview

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47. Temp Sensor

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dk
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JTAG is an interface for internal test. The structure of S905 JTAG module is shown in the following diagram:
Fig VIII.47.1 Diagram of JTAGDis

The temperature sensor uses TSMC 28nm CMOS mix signal process and can provide a PTAT voltage which contains thetemperature information of the chip. This block together with the followed SAR ADC can give the chip temperature. Figure
shows block diagram of the temperature sensor.
FigVIII.48.1 Temperature Sensor Diagram

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S905 Datasheet

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TS_VBG_EN

EN_BG
IBG2
VBG/IBG
Generator

ADC_10U

IBG

EN_TEMP

TS_EN_TEMP+
VBG

TS_C<4:0>

PTAT_OUT-VPTATTS_TRIM<4:0>

TS_RSV<7:0>

Unusedne

TS_TEST_SEL

TS_TESTdk
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TS_TEST_SEL

IPTAT

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IPTAT
Generator

Fig VIII.48.2 Temperature sensor output

V(/mV)

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865
750

27 42.5125

T(/°C)

tr
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-40

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193

47.2 Trimming

7.4mV/°C

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1417

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Trimming is suggested before using this block. Fig.2 denotes the ideal output voltage of this block which also gives the directionof trimming. We use 16 Bits e-fuse resistor to trim this block, 10 Bits for the recording of the result of SARADC in FT process ,5 Bits for coarse trimming(Anti-saturation of this block) and 1 bitfor trimming fag. Two fixed points (27°,750mV) and (42.5,865mV) are provided in Fig.2, you can select either one of them as the coarse trimming target.
Fig.3 shows the real calibration curve for temperature sensor, please note the Y coordinate is different from Fig.2, but they are
the input and output of the SARADC respectively. In chip application, the temperature can be calculated when we get the realtime Dout if the line is determined. While in theory we can determine a line if the slope and a real arbitrary point are given,that is to say the slope(given by designer) and the Dout at a specified temperature in Fig.3.

Fig VIII.48.3 Temperature sensor calibration curve335/336

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S905 Datasheet

Revision 1.1.4

Dout(ADC output)

TS_C=31
TS_C=30

TS_C=8
TS_C=7
TS_C=6
Target Curve
TS_C=5l

TS_C=4

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Real Dout

offset

TS_C=0dk
erTarget Dout

Tunning Step

T(°C)

ar

27
(Depend on the FT
environment)

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Below is the calibration flow:
1. Get the real Dout when set the TS_C to 16;
2. According to the offset and Tunning step the ∆TS_C can be calculated(The tunning step and target Dout are given by
designer);
3. Calculate the final TS_C, TS_Cfinal=16+∆TS_C;
4. Read the Dout when set the TS_C to the final value;
5. Store the final the TS_C and the Dout which are get in step 4 to effuse;

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47.3 Register Definition
0xc810062c

Default
reserved
00000000
1
0
1
10000
1
reserved

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R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W

D

Bits
31-30
29-22
21
20
19
18-14
13
12-0

Description
TS_RSV<7:0>:Unused bit, can set to 0
Enable SARADC channel 6 sampling
TS_TEST_SEL: Enable the test mode
TS_EN_TEMP:Write 1 to enable temperature sensor circuit.
TS_C<4:0>.Trimming temperature sensor’s output voltage.0000: 550mV 1111:850mV
TS_VBG_EN. Write 1 to enable bandgap.
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