LT8625S
18V/8A Step-Down Silent Switcher 3 with
Ultralow Noise Reference
FEATURESDESCRIPTION

Silent Switcher®3 Architecturen Ultralow RMS Noise (10Hz to 100kHz): 4μV
RMSn Ultralow Spot Noise: 4nV/√Hz at 10kHz
n Ultralow EMI Emissions on Any PCB
n Internal Bypass Capacitors Reduce Radiated EMI
n High Efficiency at High Frequency
n Ultrafast Transient Response: 1μs
n Fast Minimum Switch On-Time: 15ns
n Input Voltage Range: 2.7V to 18Vn Output Voltage Range: 0V to (PV - 0.5V)IN
n 8A Maximum Continuous Output Current
n Precision Reference: ± 0.8% Over Temperature
with Remote Sensen Supports Dynamic Output Voltage Control
n PolyPhase® Operation: Up to 12 Phases
n Forced Continuous Mode Capabilityn Adjustable and Synchronizable: 300kHz to 4MHzn Programmable Power Goodn Small 20-Lead 4mm × 3mm LQFN Package

The LT®8625S synchronous step-down regulator features
third-generation Silent Switcher technology which is
uniquely designed to combine an ultralow noise referencewith Silent Switcher architecture in order to achieve both
high efficiency and excellent wideband noise performance.

APPLICATIONSn

The innovative ultralow noise architecture provides exceptional low frequency (0.1Hz to 100kHz) output noise performance in a switching regulator. The output voltage canbe programmed with a single resistor, resulting in virtuallyconstant output noise independent of output voltage.
Silent Switcher architecture minimizes EMI emissions while
delivering high efficiency at high switching frequencies.
The LT8625S is ideal for high current, noise sensitive
applications which benefit from the high efficiency of asynchronous switching regulator.

RF Power Suppliers: PLLs, VCOs, Mixers, LNAs, PAsn High Speed/High Precision ADCs/DACs
n Low Noise Instrumentationn

PACKAGE SIZE

MAX
TEMP

EXPOSEDBACK

INTVCCCAPACITOR

LT8625S

4mm × 3mm

125°C

No

Internal

LT8625SP

4mm × 3mm

150°C

Yes

External

LT8625SP-1

4mm × 4mm

150°C

Yes

External

Note: The LT8625SP-1 (8A) is Pin-to-Pin Compatible with the LT8627SP (16A).

All registered trademarks and trademarks are the property of their respective owners. Protectedby U.S. patents, including 8823345.

TYPICAL APPLICATION

12VIN to 1 VOUT Efficiency
0.33µH

VIN
2.7V TO 18V

10µF

PVIN

SW

SVIN

OUTS

VOUT
1V
8A

10k

PGFB

100µF

RT

4.7µF
47k

49.9k
GND
8625s TA1a

EFFICIENCY (%)

49.9k

85

4.0

80

2.4

75
70

1.6

POWER LOSS

0.8

65
60

fsw = 2MHz

3.2

EFFICIENCY

POWER LOSS (W)

SET

1k

2nF

LT8625S

SVIN = 3.3V

95

EN/UVLO
VC

90

6.4
1MHz
2MHz 5.6
3MHz
4MHz 4.8

100

1

2

3
4
5
6
LOAD CURRENT (A)

7

8

0

8625s TA01b

Rev. BFor more information www.analog.com

1

LT8625SPIN CONFIGURATION

PVIN, SVIN, EN/UVLO, PG..........................................18V
SYNC, OUTS, SET, PGFB..............................................6V
PHMODE......................................................................4V
Operating Junction Temperature (Note 2)
LT8625SI............................................ –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Peak Package Body Temperature........................... 260°C

CLKOUT

SYNC/MODE

22

BSTTOP VIEW

SW
20

19

18

17

25

SW

1

16

PG

NC

2

15

RT

GND

3

14

PGFB

GND

4

13

OUTS

PVIN

5

12

VC

PVIN

6

11

SET

7

8

9

10

INTVCCPHMODE

23

21
GND

EN/UVLO(Note 1)SVIN

ABSOLUTE MAXIMUM RATINGS

24

LQFN PACKAGE
20-LEAD (4mm × 3mm × 0.94mm)
JEDEC BOARD θJA = 46°C/W, θJC(top) = 40.3°C/W, θJC(pad) = 12.8°C/W (NOTE 3),
DEMO BOARD: θJA = 30°C/W, ΨJT = 2.0°C/W
EXPOSED PAD (PIN 21) IS GND, SHOULD BE SOLDERED TO PCB.

ORDER INFORMATIONTAPE AND REEL (MINI)TAPE AND REELPAD ORBALL
FINISH

LT8625SIV#TRMPBF

LT8625SIV#TRPBF

Au (RoHS)

PART MARKING*
DEVICEFINISH CODE

8625S

e4

PACKAGETYPE**MSL
RATINGTEMPERATURE
RANGE (SEE
NOTE 2)

LQFN (Laminate Packagewith QFN Footprint)

3–40°C to 125°C• Contact the factory for parts specified with wider operating temperature ranges. *Pad orball finish code is per IPC/JEDEC J-STD-609.

• Recommended LGA and BGA PCB Assembly and
Manufacturing Procedures• *The temperature grade is identified by a label on the shipping container.

• LGA and BGA Package and Tray Drawings

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Parts ending with PBF are RoHS and WEEE compliant. **The LT8625S package has the same dimensions as a standard 4mm × 3mm QFN package.

Rev. B2

For more information www.analog.com

LT8625S
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETERCONDITIONS

TYP

MAX

UNITS

VSET = 1Vl

MIN

Minimum PVIN
Minimum SVIN (Note 8)

2.5

2.7

V

VSET = 1V

l

2.5

2.7

SET Pin Current (ISET)VSET = VOUTS = 1V

V

99.7
99.2

100
100

100.3
100.8

µA
µA

Fast Start-Up Set Pin Current

SVIN = 12V, VSET = 1V

2.2

2.7

3.2

mA

Start-Up Time (Notes 5, 11)

VOUT = 1V, CSET = 1μF, SVIN = 12V, VPGFB = 0.5
VOUT = 1V, CSET = 4.7μF, SVIN = 12V, VPGFB = 0.5
VOUT = 1V, CSET = 1μF, SVIN = 12V, RPGFB(TOP) = 49.9k, RPGFB(BOT) = 49.9k
VOUT = 1V, CSET = 4.7μF, SVIN = 12V, RPGFB(TOP) = 49.9k, RPGFB(BOT) = 49.9k

l

25
120
1
2.5

ms
ms
ms
ms

Output Noise Spectral Density (10kHz) SVIN = 12V, VOUT = 1V, COUT = 22µF ×3, L = 180nH, RSET = 10kΩ, CSET = 4.7µF(Notes 5, 6, 7)
fSW = 4MHz, RC = 4.99kΩ, CC = 1nF

4nV/√HzOutput RMS Noise (10Hz – 100kHz)(Notes 5, 6, 7)

SVIN = 12V, VOUT = 1V, BW = 10Hz to 100kHz, COUT = 22µF ×3, L = 180nH
RSET = 10kΩ, CSET = 4.7µF fSW = 4MHz, RC = 4.99kΩ, CC = 1nF

3.5

μVRMS

SVIN Quiescent Current

VEN/UVLO = 2V, Not Switching
VEN/UVLO = 0.2V, Shutdown

2.8
50

3.3
105

mA
µA

Oscillator Frequency

RT = 392k
RT = 47k
RT = 18k

l
l
l

270
1.93
3.75

300
2
4

330
2.07
4.25

kHz
MHz
MHz

PGFB Upper Threshold

VPGFB Rising

l

529

537.5

546

mV

PGFB Upper Threshold Hysteresis
PGFB Lower Threshold

5
VPGFB Fallingl455

PGFB Lower Threshold Hysteresis
PGFB Pin Current

SVIN = 6V, VEN/UVLO = 3V, VPGFB = 0.5V

PG Leakage

VPG = 3.3V

PG Pull-Down Resistance

VPG = 0.5V

SYNC Threshold

SYNC DC and Clock Low Level Voltage
SYNC DC and Clock High Level Voltage

0.7

OUTS Pin Output Current

VOUTS = 1V

80

462.5

mV
mV

25

nA

380

Output Voltage Line Regulation (Note 10) VSVIN = 4V to 18V

470

5
–40
l

mV

40

nA

1200

Ω

1.5

V
V

160

240

nA

0.001

0.01

%/V

2
2

mV
mV

13.5
12.2

mS
mS

Error Amp Offset(Notes 9, 10)

VC = 1.2V, VSET = 3V, SVIN = 6V, PNP-Based Input Pair
VC = 1.2V, VSET = 5V, SVIN = 5.5V, NPN-Based Input Pair

Error Amp Transconductance(Note 9)

VC = 1.2V, VSET = 1V, SVIN = 6V, PNP-Based Input Pair
VC = 1.2V, VSET = 5V, SVIN = 5.5V, NPN-Based Input Pair

Error Amp Gain

VC = 1.2V, VSET = 1V, SVIN = 6V

2800

V/V

VC Source Current(Note 9)

VC = 1.2V, VSET = 1V, VOUTS = 0V, SVIN = 6V, PNP-Based Input Pair
VC = 1.2V, VSET = 5V, VOUTS = 4.7V, SVIN = 5.5V, NPN-Based Input Pair

330
330

µA
µA

VC Sink Current(Note 9)

VC = 1.2V, VSET = 1V, VOUTS = 2V, SVIN = 6V, PNP-Based Input Pair
VC = 1.2V, VSET = 5V, VOUTS = 5.3V, SVIN = 5.5V, NPN-Based Input Pair

330
330

µA
µA

VC Pin to Switch Current Gain

11.5

A/V

VC Clamp Voltage

2.2

V

11

mA

SVIN Current Consumption

RT = 47k, fSW =2MHz, SVIN = 6V

Minimum On-Time

ILOAD = 2A

Minimum Off-Time

ILOAD = 2A

–2
–2
9.5
7.8

l

Bottom Power N-Channel MOSFET
Current Limit
PVIN = 18V, VSW = 0V, 18V

11.5
10

15

20

ns

70

90

ns

13.5

16

17.5

A

9.25

11.5

13.75

A

15

µA

l

Top Power N-Channel MOSFET
Current Limit

SW Leakage Current

l
l

–15

Rev. BFor more information www.analog.com

3LT8625S
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETERCONDITIONS

MIN

TYP

Power MOSFET On-Resistance
Main Switch (Top)
Synchronous Switch (Bottom)

MAX

UNITS

35
15

EN/UVLO Threshold

EN/UVLO Rising

1.27

l

1.32

EN/UVLO Hysteresis

mΩ
mΩ
1.37

V

50

mV

EN/UVLO Input Current
EN Delay Time (Note 5, 12)

VEN/UVLO = 2V
–40
40
nA
SVIN = 12V, CVCC = 1µF (internal) +1µF (external), RC = 500R, CC = 10nF,
150µs
CSET = 2.2µF
PHMODE Thresholds
Between 180 and 120
0.7
1.5
V
Between 120 and 90
2.0
2.7
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
Note 5: Not subject to production test.
may cause permanent damage to the device. Exposure to any Absolute
Note 6: OUTS ties directly to VOUT.
Maximum Rating condition for extended periods may affect device
Note 7: Adding a capacitor across the SET pin resistor decreases output
reliability and lifetime.
voltage noise. Adding this capacitor bypasses the SET pin resistor’sNote 2: The LT8625SI is guaranteed over the full –40°C to 125°C
thermal noise as well as the reference current’s noise. Use of a SET pin
operating junction temperature range. High junction temperatures degrade
bypass capacitor also increases start-up time.
operating lifetimes. Operating lifetime is derated at junction temperatures
Note 8: Minimum SVIN can increase with OUTS once OUTS is above agreater than 125°C. The junction temperature (TJ, in °C) is calculated fromcertain value. Refer to the Typical Characteristics curves for how thisthe ambient temperature (TA in °C) and power dissipation (PD, in Watts)
parameter changes with OUTS.
according to the formula:
Note 9: The PNP-based input pair is active for the error amplifier as long as
TJ = TA + (PD • θJA)
SVIN is at least 1V above VSET. As SVIN drops to less than 1V above VSET, thewhere θJA (in °C/W) is the package thermal impedance.
part gradually transitions to operating with the NPN-based input pair active.
Note 3: θ values determined per JEDEC 51-7, 51-12. See the Applications
Note 10: The LT8625S is tested in a feedback loop that servos VC to a
Information for information on improving the thermal resistance andspecified voltage and measures the resultant VOUTS.
for actual temperature measurements of a demo board in typical
Note 11: The start-up time is defined as the time it takes from the EN/UVLO
operating conditions.
pin rising above the EN/UVLO threshold to when VOUT has reached 90% ofNote 4: This IC includes overtemperature protection that is intended to
final value.
protect the device during overload conditions. Junction temperature will
Note 12: EN Delay Time is the time from EN/UVLO high to first switchingexceed 150°C temperature when overtemperature protection is active.
cycle.
Continuous operation above the specified maximum operating junction
temperature will reduce lifetime.

TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Integrated RMS Output Noisevs Load (10Hz to 100kHz)

12
10
8
6
4
2
0

1

2

3
4
5
6
LOAD CURRENT (A)788625s G01

REFER TO TYPICAL APPLICATIONCIRCUITS TA03 (2MHz) AND TA02 (4MHz)

4

10
9
8
7
6
5
4
3
2

VOUT = 1V
VOUT = 3.3V

14

fSW = 2MHz, ILOAD = 2A
VIN = SVIN = PVIN

12
10
8
6

WHEN VIN – VOUT < 1V
SWAPS TO NPN ERROR AMPLIFIER

4
2

1

SVIN = PVIN = 12V

16

fSW = 2MHzfSW = 4MHz

11
RMS OUTPUT NOISE (µVRMS)14
RMS OUTPUT NOISE (µVRMS)

12fSW = 2MHzfSW = 4MHz

Integrated RMS Output Noise vs
VIN (10Hz to 100kHz)RMS OUTPUT NOISE (µVRMS)

16

Integrated RMS Output Noisevs CSET (10Hz to 100kHz)

00.1

SVIN = PVIN = 12V
1
SET PIN CAPACITANCE (µF)

108625s G02

REFER TO TYPICAL APPLICATIONCIRCUITS TA03 (2MHz) AND TA02 (4MHz)

For more information www.analog.com

0

2

3

4

5

6

7 8
VIN (V)910 11 128625s G03

REFER TO TYPICAL APPLICATIONCIRCUITS TA03 (1V) AND TA07 (3.3V)
Rev. BLT8625S
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

100(INTEGRATED NOISE
FROM 10Hz TO 100kHz)
SVIN = PVIN = 12V
101

fSW = 2MHz, VOUT = 1V
10

100

1k
10k
FREQUENCY (Hz)100k

SVIN = PVIN = 12V

108625s G04

Noise Spectral Density as a Function ofError Amplifier Input Pair

10

100

1k
10k
FREQUENCY (Hz)

100k

100k

fSW = 4MHz, VOUT = 1V, ILOAD = 2A
10

100

1k
10k
FREQUENCY (Hz)

100k

1M
8625s G06

Noise Spectral Density vs fSW

Noise Spectral Density(0.1Hz to 10Hz)
1000

1M

(INTEGRATED NOISE FROM
10Hz TO 100kHz)
SVIN = PVIN = 12V

1100

VOUT = 1V, ILOAD = 2A
10

100

1k
10k
FREQUENCY (Hz)

100k

10
0.1

1M

PVIN = SVIN = 12V, VOUT = 1V
RSET = 10kΩ, CSET = 4.7µF
1
FREQUENCY (Hz)8625s G08

108625s G09

REFER TO TYPICAL APPLICATIONCIRCUITS TA03 (2MHz) AND TA02 (4MHz)

Power Supply Ripple Rejection
100

DEMOBOARD APPLICATION CIRCUIT

90

PVIN = 12V, VOUT = 1V

80

100

DEMOBOARD APPLICATION CIRCUIT
PVIN = 5V, VOUT = 1V

70

80
60

60
50
40
30

40

20

100

1

(INTEGRATED NOISE FROM
10Hz TO 100kHz)
TYPICAL APPLICATION CIRCUIT TA02 (4MHz)

Power Supply Ripple Rejection

20

10

1M

10

(INTEGRATED NOISE FROM
10Hz TO 100kHz)
TYPICAL APPLICATION CIRCUIT TA07 (3.3V)

120

SVIN = PVIN = 12V(INTEGRATED NOISE FROM
10Hz TO 100kHz)
TYPICAL APPLICATION CIRCUIT TA03 (2MHz)

1008625s G07

140

CSET = 100nF (4µVRMS)CSET = 470nF (3.75µVRMS)CSET = 1µF (3.5µVRMS)CSET = 4.7µF (3.46µVRMS)CSET = 10µF (3.44µVRMS)LNA NOISE FLOOR

fSW = 2MHz (8.5µVRMS)fSW = 4MHz (3.46µVRMS)LNA NOISE FLOOR

fSW = 2MHz, VOUT = 3.32V, ILOAD = 2A
10

1k
10k
FREQUENCY (Hz)PSRR (dB)1100Noise Spectral Density vs CSET

100

fSW = 2MHz, VOUT = 1V, ILOAD = 2A
10

1000

OUTPUT NOISE (nV/√Hz)

100

PSRR (dB)OUTPUT NOISE (nV/√Hz)

VIN = 12V, PNP (8.4µVRMS)
VIN = 5V, PNP (8µVRMS)
VIN = 4.3V, NPN (10.5µVRMS)LNA NOISE FLOORSVIN = PVIN = 12V

1000

8625s G05

TYPICAL APPLICATION CIRCUIT TA03 (2MHz)

1000

CSET = 100nF (8.9µVRMS)CSET = 470nF (8.55µVRMS)CSET = 1µF (8.5µVRMS)CSET = 4.7µF (8.5µVRMS)CSET = 10µF (8.46µVRMS)LNA NOISE FLOOR

100

1

1M

Noise Spectral Density vs CSETOUTPUT NOISE (nV/√Hz)

ILOAD = 50mA (8µVRMS)
ILOAD = 1A (8.25µVRMS)
ILOAD = 2A (8.6µVRMS)
ILOAD = 4A (8.8µVRMS)
ILOAD = 8A (9.6µVRMS)OUTPUT NOISE (nV/√Hz)

OUTPUT NOISE (nV/√Hz)

1000

OUTPUT NOISE (nV/√Hz)

Noise Spectral Density vs Load
1000

ILOAD = 0A
ILOAD = 8A
1k

10k
100k
FREQUENCY (Hz)101M8625s G10

100

fSW = 2MHz, ILOAD = 0A
fSW = 2MHz, ILOAD = 8A
fSW = 1MHz, ILOAD = 0A
fSW = 1MHz, ILOAD = 8A
1k

10k
FREQUENCY (Hz)

100k

400k

8625s G11

Rev. BFor more information www.analog.com

5LT8625S
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
12VIN to 1VOUT Efficiency

4.0

80

3.2

EFFICIENCY

2.4

75
70

POWER LOSS

65
60

SVIN = 3.3V
1

2

3
4
5
6
LOAD CURRENT (A)78

12VIN to 1.2VOUT Efficiency

95
90

2.5
2.0
1.5

75

1.6

70

0.8

65

0

60

POWER LOSS

1

2

1.0

L = XGL6030 0.5
SVIN = 3.3V
0
3
4
5
6
7
8
LOAD CURRENT (A)8625s G13

5.6

95

4.8

90

1MHz, 0.68µH (2.9mΩ)
2MHz, 0.38µH (2mΩ)
3MHz, 0.22µH (1.2mΩ)
4MHz, 0.18µH (1mΩ)
L = XGL6030

80
75
70
65

3.2
2.4

POWER LOSS
1

2

3
4
5
6
LOAD CURRENT (A)7

8SVIN = 5V

75

0.8

65

0

60

5.6

4.0

1MHz, 1µH (4.2mΩ)
2MHz, 0.68µH (2.9mΩ)
3MHz, 0.38µH (2.0mΩ)
4MHz, 0.22µH (1.2mΩ)
L = XGL6030

80

70

EFFICIENCY

4.8

85

1.6

6.4

3.2
2.4

POWER LOSS (W)

4.0

85

60

100

EFFICIENCY (%)

EFFICIENCY

6.4

POWER LOSS (W)EFFICIENCY (%)

12VIN to 3.3VOUT Efficiency

SVIN = 3.3V

90

3.0

EFFICIENCY80

12VIN to 1.8VOUT Efficiency
95

3.5

85

8625s G12

100

4.0

1MHz, 0.47µH (2.2mΩ)
2MHz, 0.38µH (2mΩ)
3MHz, 0.22µH (1.2mΩ)
4MHz, 0.18µH (1mΩ)

POWER LOSS (W)

85

100

POWER LOSS (W)

90

1MHz, 0.56µH, XEL6060 (2.6mΩ)
2MHz, 0.33µH, XEL6060 (2mΩ)
5.6
3MHz, 0.28µH, XEL6030 (2.1mΩ)
4MHz, 0.15µH, XEL6030 (1.35mΩ) 4.8

95

EFFICIENCY (%)

6.4

EFFICIENCY (%)

100

1.6
POWER LOSS
1

2

3
4
5
6
LOAD CURRENT (A)

7

0.8
8

0

8625s G158625s G14

12VIN to 5VOUT Efficiency
100

6.4

SVIN = 12V

EFFICIENCY

95

5.6
4.8

85

4.0

1MHz, 1.5µH (6.2mΩ)
2MHz, 0.68µH (2.9mΩ)
3MHz, 0.47µH (2.2mΩ)
4MHz, 0.38µH (2mΩ)
L = XGL6030

80
75

3.2
2.4
1.6

70
POWER LOSS

65
60

1

2

3
4
5
6
LOAD CURRENT (A)

7

0.8
8

8625s G16

6POWER LOSS (W)EFFICIENCY (%)

90

For more information www.analog.com

0Rev. BLT8625S
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Efficiency vs VIN

100.8

95
SET PIN CURRENT (µA)

EFFICIENCY (%)

90
85
80
75
PVIN = SVIN
VOUT = 1V
fSW = 1MHzILOAD = 4A
L = XGL6030, 1µH (DCR = 4.2mΩ)

70
65
60

3

6

Load Regulation

SET Pin Current
101.0

9
12
INPUT VOLTAGE (V)

15

0.50

SVIN = 12V
VOUT = 1V

100.6

0.30

100.4

0.20

100.2
100.0
99.8
99.6

–0.40
–25

0
25
50
75
TEMPERATURE (°C)

100

–0.50

125

1.34
1.33

–0.26
–0.32
VOUT = 1.2
ILOAD = 1A
fSW = 2MHzFC MODE

–0.38
–0.44

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
INPUT VOLTAGE (V)

2

3
4
5
6
LOAD CURRENT (A)78Top MOSFET Current Limit
19

EN/UVLO RISING

18

1.32
1.31
1.30
1.29
1.28

17
16

10% DC

15
14

EN/UVLO FALLING

1.27

13

1.26
1.25
–50

–25

0
25
50
75
TEMPERATURE (°C)

1008625s G20

12
–50

125

–25

0
25
50
75
TEMPERATURE (°C)

8625s G21

Top MOSFET Current Limitvs Duty Cycle

100

125

8625s G22

Switch RDS(ON) vs Temperature

18

60

17

50

16

TOP SWITCH

15

RDS(ON) (mΩ)

CURRENT LIMIT (A)1

20

CURRENT LIMIT (A)–0.20

EN/UVLO THRESHOLD (V)

0.04
–0.02

–0.14

0

8625s G19

EN/UVLO Pin Thresholds
1.35

–0.08

PULSE-SKIPPING MODEFC MODE8625s G18

Line Regulation

CHANGE IN VOUT (%)

–0.20
–0.30

0.10

14
13

40
30
20

12

BOTTOM SWITCH

10

11
10

0.00
–0.10

99.2

8625s G17

–0.50

0.10

99.4

99.0
–50

18

VOUT = 1.2V

0.40

CHANGE IN VOUT (%)

100

10

20

30

40 50 60 70
DUTY CYCLE (%)

80908625s G23

For more information www.analog.com

0
–50

–25

0
25
50
75
TEMPERATURE (°C)

100

125

8625s G24

Rev. B7

LT8625S
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Minimum SVIN as a
Function of VSETPVIN Dropout Voltage
1000

8

18

PNP ERROR AMPLIFIER IS ACTIVE
16 FOR VSET AND SVIN OUTSIDE THE RED BOX
VSET
14MINIMUM SVIN

7
6

600
500
400
300

12

5
SVIN (V)MINIMUM SVIN (V)

4
3

200

0

1

2

3
4
5
6
LOAD CURRENT (A)

7

0

8

0

1

2

8625s G25

4

5

0

6

2.9
2.8

350

2.7

MINIMUM SVIN (V)

400

300
250
200
150

VOUT ≤ 2.1V

2.6
2.5
2.4
2.3

2.0
1.5

0.5
–25

0
25
50
75
TEMPERATURE (°C)

8625s G28

2.075

MINIMUM ON-TIME (ns)

2.000
1.975
1.950
1.925
0
25
50
75
TEMPERATURE (°C)

100

125

VOUT = 1V
L = 0.33µH
PULSE-SKIPPING MODE
IN REGULATION
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
INPUT VOLTAGE (V)8625s G29

RT = 47k

–25

0

125

8625s G30

Minimum On-Time vs Load

20

2.025

1.900
–50

100

Minimum On-Timevs Temperature

2.050

8625s G27

2.5

2.0
–50

Switching Frequency

6

3.0

2.1

2.100

5

3.5

0

125

4

4.0

50
100

3
VSET (V)

4.5

1.0

0
25
50
75
TEMPERATURE (°C)

2

No-Load Supply Current

2.2

–25

1

5.0

100

0

0

8625s G26

INPUT CURRENT (mA)

3.0

PVIN = 12V
450 VOUT > 2.4V
DROPOUT VOLTAGE (mV)

3

Minimum SVIN

500

SWITCHING FREQUENCY (MHz)2

MINIMUM SVINVSETVSET (V)SVIN Dropout Voltage

8

4

1

100

NPN ERROR AMPLIFIER ACTIVE
ONLY INSIDE RED BOX(WHEN SVIN – VSET ≤ 1V)

10

6

2

20

ILOAD = 2A
19 VOUT = 0.5V
fSW = 4MHz
18 FC
MODE
17

18

16
15
14
13

17
16
15
14
13

12

12

11

11

10
–50

–25

0
25
50
75
TEMPERATURE (°C)

VOUT = 0.5V
fSW = 4MHz
FC MODE19
MINIMUM ON-TIME (ns)

DROPOUT VOLTAGE (mV)

PVIN = 3.3V, SVIN = 5V
900 VSET = 3.3V, VOUT TO REGULATE TO 3.3V
L = HPL758040F, 0.33µH (DCR = 0.61mΩ)
800
PULSE-SKIPPING MODE
700

0Minimum SVIN as a
Function of VSET

100

8625s G31

125

8625s G32

10

0

1

2

3
4
5
6
LOAD CURRENT (A)788625s G33

Rev. B8

For more information www.analog.com

LT8625S
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
ISET During Start-Up with Fast
Start-Up Enabled

VPGFB = 400mV

3.5

3.0

3.0

2.5

2.5

ISET (mA)

2.0
1.5
1.0

WITH FAST START-UP
VOUT
250mV/DIVVEN
2V/DIV

1.5
1.0

SVIN = 3V
SVIN = 12V
SVIN = 18V

0.5
0
–50

–25

0
25
50
75
TEMPERATURE (°C)

100

0

125

0

2

VEN
2V/DIV8625s G37

SVIN = 5V
RSET = 10kΩ, WITH FAST START-UP
FSW = 2MHz, L = 330nH, C OUT = 5× 22µF
RL = 1ΩPG HIGH THRESHOLD VOLTAGE (mV)

CSET = 4.7μF
CSET = 10μF

500µs/DIVPG Low Thresholds

545.0

475.0

542.5

472.5

540.0
VPGFB RISING

537.5
535.0
532.5

VPGFB FALLING

530.0
527.5
525.0
–50

–25

0
25
50
75
TEMPERATURE (°C)

100

470.0
VPGFB RISING

467.5
465.0
462.5

VPGFB FALLING

460.0
457.5
455.0
–50

125

–25

0
25
50
75
TEMPERATURE (°C)

1008625s G38

SVIN Pin Current vs Frequency

Error Amp Output Current

12.0

SVIN PIN CURRENT (mA)

SVIN = 12V
18 PVIN = 12V
V= 1V
16 OUTFC MODE
14
12
10
8
6
4
2
1 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2
SWITCHING FREQUENCY (MHz)8625s G40

500

SVIN = 12V
11.8 VOUT = 1V
f = 2MHz
11.6 SW
IL = 2A
11.4

400
300

11.2
11.0
10.8
10.6

200
100
0
–100
–200

10.4

–300

10.2

–400

10.0

2

4

6

125

8625s G39

SVIN Pin Current vs PVIN

200
0.2 0.6

SVIN = 5V
RSET = 10kΩ, CSET = 4.7µF
FSW = 2MHz, L = 330nH, C OUT = 5× 22µF
RL = 1Ω

18

PG High Thresholds

CSET = 1μF
VOUT500mV/DIV

46
8 10 12 14 16
SVIN – VSET DIFFERENTIAL (V)8625s G35

Soft-Start Waveforms

8625s G36

50ms/DIV

0.5

8625s G34

SVIN PIN CURRENT (mA)WITHOUT FAST START-UP

2.0

PG LOW THRESHOLD VOLTAGE (mV)ISET (mA)

3.5

4.0

VSET = 1V

VC PIN CURRENT (µA)

4.0Start-Up Time with andwithout Fast Start-Up Circuitry
for Large CSETISET During Start-Up with Fast
Start-Up Enabled

8

10 12
PVIN (V)

14

16

18

8625s G41

–500
–150

VC = 1.2V
VSET = 1V–100 –50
0
50
100
VOUTS – VSET ERROR (mV)

150

8625s G42

Rev. BFor more information www.analog.com

9LT8625S
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Switching Waveforms, Full
Frequency Continuous Operation

Switch Rising EdgeIL
1A/DIV

Switching Waveforms, PulseSkipping Operation

IL
500mA/DIV

VSW
2V/DIV
VSW
5V/DIV

5ns/DIV

VSW
5V/DIV8625s G43

VIN = 12V
ILOAD = 6A

CLKOUT Waveforms

VCLKOUT
2V/DIV8625s G44

500ns/DIV

8625s G45

1µs/DIV

12VIN TO 1VOUT AT 5A
fSW = 2MHz

12VIN TO 1VOUT AT 100mA
VSYNC = 0V

Transient Response: Load Current
Stepped from 2A to 5A

Transient Response: Load Current
Stepped from 100mA to 3.1A

ILOAD
2A/DIVILOAD
2A/DIV

VSYNC
2V/DIVPULSE-SKIPPING MODE
VOUT
50mV/DIV

VOUT
50mV/DIVVSW
5V/DIV
200ns/DIVFC MODE8625s G46

8625s G47

10µs/DIV

20µs/DIV

8625s G48

fSW = 1MHz, PVIN = 5V, VOUT = 1V, ILOAD = 3A
SYNCRHONIZATION MODE
VPHMODE = 0V

PVIN = 12V, VOUT = 1V, fSW = 2MHz
CC = 2.2nF, RC = 1k
COUT = 2× 100µF + 2× 22µF

PVIN = 12V, VOUT = 1V, fSW = 2MHz
CC = 2.2nF, RC = 1k
COUT = 2× 100µF + 2× 22µF

Start-Up Dropout Performance

Start-Up Dropout Performance

LT8625S Case Temperature Rise
80

VIN
(FAST START-UP
ENDS HERE)

VIN
1V/DIV
VOUT

VOUT
1V/DIV

100ms/DIV
1Ω LOAD(4A IN REGULATION)

VOUT
1V/DIV8625s G49

(FAST START-UP
ENDS HERE)

VIN
1V/DIV
VOUT

100ms/DIV
20Ω LOAD(200mA IN REGULATION)

8625s G50

CASE TEMPERATURE RISE (°C)

VIN

DEMO BOARD DC3002A
70 ON STILL AIR
PVIN = 12V
SVIN = 3.3V
60
VOUT = 1V
50
40
30
20
1MHz
2MHz

10
0

0

1

2

3
4
5
6
LOAD CURRENT (A)788625s G51

Rev. B10

For more information www.analog.com

LT8625S
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Radiated EMI Performance (CISPR32 Radiated Emission Test with Class B Limits)
70

WITH EMI FILTER

CLASS B LIMITAMPLITUDE (dBµV/m)

60
50
40
30
20
10
0
–10

HORIZONTAL OPERATINGVERTICAL OPERATING
0

100

200

300

400
500
600
FREQUENCY (MHz)700

DC3002A DEMO BOARD
12V INPUT TO 1V OUTPUT AT 1A, fSW = 2MHz

800

900

1000

8625s G52

PIN FUNCTIONSSW (Pins 1, 20): The SW Pins are the outputs of the internal power switches. Tie these pins together and connect
them to the inductor. This node should be kept small on
the PCB for good performance and low EMI.
NC (Pin 2): No Connect. This pin is not connected tointernal circuitry and can be tied anywhere on the PCB,
typically ground.
GND (Pins 3, 4, 21): Ground. Place the negative terminal of the input capacitor as close to the GND pins as possible. The exposed pads should be soldered to the PCB for
good thermal performance. If necessary due to manufacturing limitations, the exposed pads may be left disconnected, however, thermal performance will be degraded.
PVIN (Pins 5–6): Power VIN. The PVIN pins supply current
to the LT8625S internal circuitry and to the internal topside power switch. These pins must be tied together andbe locally bypassed with a capacitor of 4.7µF or more. Be
sure to place the positive terminal of the input capacitor
as close as possible to the PVIN pins, and the negative
capacitor terminal as close as possible to the GND pins.
SVIN (Pin 7): Signal VIN. This pin supplies current to theLT8625S internal circuitry and regulator. In order to provide sufficient headroom for the current reference, SVIN

must be at least 400mV higher than the desired setpointthat is programmed via the SET pin. For example, fora desired setpoint of 3.3V, SVIN must be at least 3.3V
+ 400mV = 3.7V, or higher. See Typical Performance
Characteristics curves. If tied to a different supply thanPVIN, place a 1μF local bypass capacitor on this pin.
EN/UVLO (Pin 8): A voltage at this pin greater than 1.32V
will enable switching, and a voltage less than 400mV isguaranteed to shut down the internal current bias andsub-regulators. The hysteretic threshold voltage is 1.32V
going up and 1.28V going down. Tie to PVIN if the shutdown feature is not used. An external resistor divider
from PVIN can be used to program a PVIN threshold below
which the LT8625S will shut down.
INTVCC (Pin 9): Internal 3.4V Regulator Bypass Pin. Theinternal power drivers and control circuits are poweredfrom this voltage. Do not load the INTVCC pin with external
circuitry. INTVCC current will be supplied by SVIN. This pinshould be floated.
PHMODE (Pin 10): The PHMODE pin sets the phase shiftof the clock signal of the CLKOUT pin. Tie PHMODE toground for 180° phase shift, float for 120° phase shift andRev. BFor more information www.analog.com

11LT8625SPIN FUNCTIONS
tie high to INTVCC (~3.4V) or an external supply >3V fora 90° phase shift. See Block Diagram for internal pull-up
and pull-down resistance.
SET (Pin 11): This pin is the noninverting input of
the error amplifier and the regulation setpoint for theLT8625S. SET sources a precision 100µA current thatflows through an external resistor connected between SET
and GND. The LT8625S’s output voltage is determinedby VSET = ISET • RSET when used in the default unity gain
configuration. SET pin voltage range is from zero to 6V.
Increasing the capacitor from SET to GND improves noiseat the expense of increased start-up time. For optimum
load regulation, Kelvin connect the ground side of theSET pin resistor directly to the load. This pin is pulled to
ground with a 500Ω MOSFET during shutdown and fault
conditions.
VC (Pin 12): The VC pin is the output of the internal error
amplifier. The voltage on this pin controls the peak switch
current. Tie an RC network from this pin to ground tocompensate the control loop.
OUTS (Pin 13): Output Sense. This pin is the inverting
input to the error amplifier. For optimal transient performance and load regulation, Kelvin connect OUTS directly
to the output capacitor and the load. Also, tie the GND
connections of the output capacitor and the SET pin
capacitor directly together.
PGFB (Pin 14): Power Good Feedback. The PG pin pulls
low if PGFB increases above 537.5mV or decreases
below 462.5mV. Connecting an external resistor divider
between VOUT, PGFB and GND sets the programmablepower good threshold with the following transfer function:
0.5V (±7.5%) • (1 + RPGFB(TOP)/RPGFB(BOT)). As discussed
in the Applications Information section, PGFB also activates the fast start-up circuitry. PGFB must be tied to
0.5V if power good and fast start-up functionalities are
not needed.

RT (Pin 15): A resistor is tied between RT and ground to
set the switching frequency.
PG (Pin 16): The PG pin is the open-drain output of aninternal comparator. PG remains low until the PGFB pin iswithin ±7.5% of 0.5V, and there are no fault conditions.
PG is also pulled low when EN/UVLO is below 1.32V,
INTVCC has fallen too low, SVIN is too low, or during thermal shutdown. PG is valid when SVIN is above 2.7V.
SYNC/MODE (Pin 17): For the LT8625S, this pin programs three different operating modes: 1) Pulse-skipping
mode. Tie this pin to GND for pulse-skipping mode for
improved efficiency at light loads. 2) Forced Continuousmode (FCM). This mode offers fast transient response
and full frequency operation over a wide load range. Tie
this pin high to INTVCC (~3.4V) or an external supply>1.5V for FCM. The part will also operate in this modeby default if this pin is left floating. 3) Synchronization
mode. Drive this pin with a clock source to synchronize
to an external frequency. During synchronization the partwill operate in forced continuous mode.
CLKOUT (Pin 18): Output Clock Signal for PolyPhase
Operation. The CLKOUT pin provides a 50% duty-cycle
square wave of the switching frequency. The phase of
CLKOUT with respect to the LT8625S’s internal clock is
determined by the state of the PHMODE pin. CLKOUT’s
peak-to-peak amplitude is INTVCC to GND. Float this pin
if the CLKOUT function is not used.
BST (Pin 19): This pin is used to provide a drive voltage,
higher than the input voltage, to the topside power switch.
This pin should be floated.
Corner Pins (Pins 22-25): These pins are for mechanicalsupport only and can be tied anywhere on the PCB. It isconvenient to tie pin 22 to SW and to tie pin 23 to PVIN.

Rev. B12

For more information www.analog.com

LT8625S
BLOCK DIAGRAM
SVIN
PVIN

VIN

PVIN
CIN1
0.1µF

CIN3
REN1

1.32V
EN/UVLO

CIN2
0.1µF
SHDN

BIAS

PG

REN2

3.4V
REG

FAST START-UP
2.7mA

INTVCCSHDN
THERMAL SHDNVCC UVLO
VIN UVLOSLOPE COMPFASTSTART-UP
DISABLELOGIC

CURRENTREFERENCE
100μA

CVCC1
1µF

OSCILLATOR
300kHz TO 4MHz

BST

RPGFB(TOP)500mV ±37.5mV
PGFB
RPGFB(BOT)PROGRAMMABLE
POWER GOOD
OUTS

VC

SET
RSET

CBST
0.1µF

SWITCHLOGIC
AND
ANTI-SHOOT
THROUGHERRORAMPLIFIER

SW

L

VOUT
COUT

VC

CSET
SHDN
THERMAL SHDNVCC UVLO
VIN UVLO

RC

CC

GND
INTVCCRT
PLL

RT

INTVCCINTVCC

30k

30k

300k

300k

PHMODE

CLKOUT

SYNC/MODE

8625s BD

Rev. BFor more information www.analog.com

13

LT8625S
OPERATION
The LT8625S is a constant frequency, current mode,monolithic step-down regulator, operating using a current
reference-based architecture to allow the employment ofunity gain in order to minimize output noise across all
output voltages. An oscillator, with frequency set usinga resistor on the RT pin, turns on the internal top powerswitch at the beginning of each clock cycle. Current in
the inductor then increases until the top switch current
comparator trips and turns off the top power switch.
The peak inductor current at which the top switch turns
off is controlled by the voltage on the VC pin. The error
amplifier servos the VC node by comparing the voltage
on the OUTS pin to the reference voltage on the SET pin,which is set by the user with a resistor from the SET pin
to ground. When the load current increases it causes a
reduction in the OUTS voltage relative to the reference
leading the error amplifier to raise the VC voltage until theaverage inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on until the next clock cycle begins
or inductor current falls to zero (only in pulse-skippingmode). If overload conditions result in more than 11A
flowing through the bottom switch, the next clock cycle
will be delayed until switch current returns to a safe level.

technology. The output voltage can be programmed witha single resistor, providing unity-gain operation over the
output range, resulting in virtually constant ultralow output noise independent of output voltage.

The “S” in LT8625S refers to the second-generation Silent
Switcher technology. This technology allows fast switching edges for high efficiency at high switching frequencies, while simultaneously achieving good EMI performance. This includes the integration of ceramic capacitors
into the package for VIN, INTVCC, and boost (see Block
Diagram). These capacitors keep all the fast AC current
loops small, which improves EMI performance.

To improve efficiency across all loads, the SVIN pin can be
powered from an independent supply at a voltage lower
than PVIN.

The LT8625S features third-generation Silent Switcher
technology, which combines an ultralow noise current reference with second generation Silent Switcher

If the EN/UVLO pin is below 0.4V, the LT8625S is shut
down and draws 50μA from the input. When the EN/UVLO
pin rises above 1.32V, the switching regulator will become
active.
To improve efficiency at light loads, the LT8625S can
operate in pulse-skipping mode in light load situations.
The SYNC pin is tied low to use pulse-skipping operation and tied to INTVCC or to a voltage higher than 3V or
floated, to use forced continuous mode (FCM). If a clock
is applied to the SYNC pin, the part will synchronize to an
external clock frequency and operate in FCM.
The LT8625S can operate in forced continuous mode
(FCM) for fast transient response and full frequency operation over a wide load range. When in FCM the oscillator
operates continuously, and positive SW transitions arealigned to the clock. Negative inductor current is allowed.
The LT8625S can sink current from the output and return
this charge to the input in this mode, improving load steptransient response.

The VC pin allows the loop compensation of the switching regulator to be optimized based on the programmed
switching frequency, allowing for a fast-transient response.
The VC and CLKOUT pins enable multiple LT8625S regulators to run out-of-phase, reducing the amount of required
input and output capacitors. The PHMODE pin selects thephasing of CLKOUT for different multiphase applications.

Rev. B14

For more information www.analog.com

LT8625SAPPLICATIONS INFORMATION
Low Frequency Output Noise

1000

Unlike most step-down regulators, the LT8625S does
not use a voltage reference; instead, it uses a 100µA
current reference. One problem that conventional stepdown regulators face is that the resistor divider setting
the output voltage gains up the reference noise. In contrast, the current reference architecture employed by theLT8625S allows unity-gain operation to avoid gaining up
noise from the reference to the output. Therefore, if acapacitor bypasses the SET pin resistor, then the output
noise is independent of the programmed output voltage.
The resultant output noise is typically 4nV/√Hz at 10kHz.
With the previously mentioned noise sources operating
at such low noise levels, other noise sources become
non-negligible contributors to the output noise. Choosing
a compensation network that achieves good transient performance with a good phase margin will ensure optimalnoise performance. The Applications Information section
on Frequency Compensation provides guidelines on how
to choose appropriate compensation.

OUTPUT NOISE (nV/√Hz)

fSW = 2MHz (8.5µVRMS)fSW = 4MHz (3.46µVRMS)LNA NOISE FLOOR(INTEGRATED NOISE FROM
10Hz TO 100kHz)

100

10

1

VOUT = 1V, ILOAD = 2A
10

100

1k
10k
FREQUENCY (Hz)

100k

1M
8625s F01a

REFER TO TYPICAL APPLICATIONCIRCUITS TA03 (2MHz) AND TA02 (4MHz)

(a)
1000

OUTPUT NOISE (nV/√Hz)

The LT8625S offers many advantages with respect tonoise performance in the low frequency range (<100kHz).
Conventional step-down regulators have several sourcesof low frequency noise. The most critical noise sources fora conventional regulator are its reference, error amplifier,noise from the resistor divider network used for setting
output voltage and the noise gain created by this resistor
divider.

100

10
0.1

PVIN = SVIN = 12V, VOUT = 1V
RSET = 10kΩ, CSET = 4.7µF
1
FREQUENCY (Hz)108625s F01b

(b)
Figure 1. Noise Spectral Density

See Figure 1 for noise spectral density from 10Hz to 100kHz
and 0.1Hz to 10Hz. Refer to the Typical Performance
Characteristics section for RMS integrated noise overvarious load currents and SET pin capacitances, as well
as how the noise spectral density can vary over switching frequency, where each application is compensated forgood transient response and phase margin.

Rev. BFor more information www.analog.com

15

LT8625SAPPLICATIONS INFORMATION
Filtering Switching Ripple and High Frequency Noise
The LT8625S is a switching regulator and will also havethe typical artifacts of a switching regulator at the output,
namely a ripple at the fundamental switching frequency
as well as high frequency spikes associated with the fastswitching edges. While the output capacitor will absorb
some of these spikes, the capacitor ESL will limit its ability to do so at high frequencies. Additional filtering at
the output in the form of feedthrough capacitors, ferrite
beads, or an additional LC filter stage are recommended
to eliminate these high frequency spikes and significantly
reduce switching ripple.
Feedthrough capacitors are recommended if additionalswitching ripple reduction is required while retaining
fast transient response. Ensure sufficient feedthroughcapacitors are paralleled to carry the required load current. Figure 2 shows an example where two 3A rated
feedthrough capacitors are used for additional switchingripple suppression to deliver up to 6A at the output.
FEEDTHROUGHCAPACITOR
3A RATED
OUTS

1µH
SW
47µF

LT8625S

4.7µF
×2

47µF
×6

VOUT
6A

GND
8625s F02

Figure 2. Additional Output Ripple Filtering
Using Feedthrough Capacitors

If transient performance is not critical, other passive filter
solutions can be realized using a ferrite bead, PCB trace,or physical inductor as a second L, and additional output
capacitance for the second C, as shown in Figure 3.
OUTS

0.1µH

1µH
SW
47µF

LT8625SVOUT
6A

DISCRETE L
FERRITE BEAD
PCB TRACE

When designing an additional filter for further attenuation of the switching ripple, it is highly recommended todesign with LTpowerCAD® to ensure the design is stablewith good phase margin and provides sufficient attenuation at the switching frequency of interest.
The Silent Switcher 3 architecture makes it possible toachieve excellent noise performance from low to highfrequencies at the output of the LT8625S while utilizing
only passive filtering.
PCB Layout Recommendations
The LT8625S is specifically designed to minimize low frequency (10Hz-100kHz) noise, EMI emissions and maximize efficiency when switching at high frequencies. For
optimal performance the LT8625S can use multiple PVIN
bypass capacitors.
Two small capacitors can be placed as close as possible
to the LT8625S PVIN pins, and a third capacitor with alarger value, 4.7µF or higher, should be placed near oneof these two capacitors. See Figure 4 for a recommended
PCB layout.
For more detail and PCB design files refer to the Demo
Board guide for the LT8625S. Note that large, switchedcurrents flow in the LT8625S PVIN and GND pins and the
input capacitors. The loops formed by the input capacitors
should be as small as possible by placing the capacitors
adjacent to the PVIN and GND pins. Capacitors with small
case size such as 0402 or 0603 are optimal due to lowest
parasitic inductance. Special care must be taken with the
input capacitors to ensure they have a low impedance
return path to the IC ground. This can be achieved byplacing several ground vias on the GND side of the input
capacitors such that the ground plane is utilized to fulladvantage. This should be an unbroken ground plane witha solid connection to the exposed pad of the IC, as shownin Figure 4b.

47µF
×6

GND
8625s F03

Figure 3. Additional Output Ripple Filtering
Using a Second LC Filter
Rev. B16

For more information www.analog.com

LT8625SAPPLICATIONS INFORMATIONENSURE SOLID UNBROKEN COPPER FOR RETURN PATH
OF INPUT CAPS TO IC EXPOSED PAD GND.

CIN3
COPT2

COPT1

RSVIN
L
CSVIN
COUT

CINTVCC
RSET
CSET

CF

RC

RPGFB(TOP)
CC

COUTS
(OPT)
RPGFB(BOT)GROUND VIA

RTGROUND (REMOTE SENSE) VIA

CPGFB(OPT)VOUT VIAOTHER SIGNAL VIAS

8625s F04a

8625s F04b(a) Top Layer(b) Ground Plane Layer

Figure 4. LT8625S Suggested Layout

The main inductor and output capacitors should beplaced on the same side of the circuit board with the IC,
and their connections should be made on that layer. The
impedance of the output bulk capacitor’s return path to
IC ground should also be minimized through generous
use of ground vias.

SW and BOOST nodes should be as small as possible.
Finally, keep the OUTS, PGFB and RT nodes small sothat the ground traces will shield them from the SW and
BOOST nodes. The OUTS, PGFB and RT traces should
not pass underneath the main inductor and should also
be kept away from inductor vias.

Care with ground layout prevents switching currents fromthe input capacitors coupling to the output through theground which can introduce unintentional perturbations
onto the OUTS pin. A small capacitor may also be placed
locally to decouple the OUTS pin if needed.

The exposed pad on the bottom of the package should besoldered to the PCB to reduce thermal resistance to ambient. To keep thermal resistance low, extend the groundplane from GND as much as possible, and add thermal
vias to additional ground planes within the circuit board
and on the bottom side.

An additional LC filter, if used, can be placed on the otherside of the circuit board for optimal EMI performance,
though this is not required.
Place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. The

The current reference architecture of the LT8625S allows
remote sense of the negative terminals of the load in addition to the positive terminal; note the via on the groundRev. BFor more information www.analog.com

17

LT8625SAPPLICATIONS INFORMATION
side of the RSET and CSET going to the ground side of COUT
which can be configured for remote sense of the negative
terminal of a load placed further away. Refer to the Output
Sensing and Stability section for more information on
implementing remote sense for LT8625S.
Forced Continuous Mode
The LT8625S can operate in forced continuous mode
(FCM) for fast transient response and full frequency
operation over a wide load range. When in FCM, theoscillator operates continuously, and positive SW transitions are aligned to the clock. Negative inductor current isallowed at light loads or under large transient conditions.
The LT8625S can sink current from the output and return
this charge to the input in this mode, improving load steptransient response (see Figure 5). At light loads, FCM
operation is less efficient than pulse-skipping operation,
but may be desirable in applications where it is necessary
to keep switching harmonics out of the signal band. FCM
must be used if the output is required to sink current. To
enable FCM, tie the SYNC/MODE pin to INTVCC or > 1.5V,
or float the pin.

ILOAD
2A/DIVPULSE-SKIPPING

VOUT
50mV/DIVFC MODE
20µs/DIV

8625s F05

PVIN = 12V, VOUT = 1V, fSW = 2MHz
CC = 2.2nF, RC = 1k
COUT = 2× 100µF + 2× 22µF

Figure 5. Load Step Transient Response withand without Forced Continuous Mode

FCM is disabled under PVIN overvoltage conditions (PVIN
pin is held above 18V), if VOUT is too high (the PGFB pin
is held greater than 537.5mV) and is also disabled during start-up until the voltage on VOUT has charged up to
92.5% of its final value (as indicated when the PGFB pin
rises to above 462.5mV). For the latter two conditions, it isassumed the PGFB pin is tied to the output voltage throughan appropriate resistor divider. When FCM is disabled inthese ways, negative inductor current is not allowed andthe LT8625S operates in pulse-skipping mode.
Pulse-Skipping Mode
When not operating in forced continuous mode, theLT8625S will operate in pulse-skipping mode. In thismode the oscillator operates continuously, and all switching cycles are aligned to the clock. Negative inductor current is not allowed in this mode; therefore, at light loads
the LT8625S may be operating in discontinuous mode.
Additionally, in pulse-skipping mode the LT8625S may
also skip switching cycles at very light loads for improved
efficiency, or at very high duty cycles in order to achieve
better dropout. To enable pulse-skipping mode, tie the
SYNC/MODE pin to GND.
Synchronization
To synchronize the LT8625S oscillator to an externalfrequency, connect a square wave for the SYNC/MODE
pin. The square wave amplitude should have valleys thatare below 0.4V and peaks above 1.5V (up to 6V), with aminimum on-time and off-time of 50ns.
While synchronized to an external clock, the part will
run forced continuous mode to maintain regulation.
The LT8625S may be synchronized over a 300kHz to
4MHz range. The RT resistor should be chosen to set theLT8625S switching frequency to below the lowest synchronization input by approximately 20%. For example,
if the synchronization signal will be 500kHz and higher,
the RT should be selected for 400kHz. The slope compensation is set by the RT value, while the minimum slope
compensation required to avoid subharmonic oscillations
is established by the inductor size, input voltage and output voltage. Since the synchronization frequency will notchange the slopes of the inductor current waveform, if theinductor is large enough to avoid subharmonic oscillations at the frequency set by RT, then the slope compensation will be sufficient for all synchronization frequencies.
Setting the Switching Frequency
The LT8625S uses a constant frequency PWM architecture that can be programmed to switch from 300kHz to
4MHz by using a resistor tied from the RT pin to GND.
Rev. B18

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LT8625SAPPLICATIONS INFORMATIONThe RT resistor required for a desired switching frequency
can be calculated with Equation 1.
RT =

114.8
– 10.4fSW(1)

where RT is in kΩ and fSW is the desired switching frequency in MHz.
Table 1 shows the necessary RT value for a desired
switching frequency.
Table 1. SW Frequency vs RT ValuefSW (MHz)RT (kΩ)

0.3

392

0.4

287

0.5

226

0.6

187

0.7

154

0.8

137

0.9

118

1.0

105

1.2

86.6

1.4

71.5

1.6

61.9

1.8

53.6

2

47.0

2.5

35.7

3

28.7

3.5

23.2

4

18.0

(

For transient operation, VIN may go as high as the absolute maximum rating of 18V regardless of the RT value;
however, the LT8625S will reduce switching frequency
as necessary to maintain control of inductor current toassure safe operation.
In pulse-skipping mode, the LT8625S is capable of a
maximum duty cycle of approximately 99%, and the VINto-VOUT dropout is limited by the RDS(ON) of the top switch(provided there is sufficient headroom (~0.4V) between
SVIN and SET for the current reference circuit to function
correctly. In this mode the LT8625S skips switch cycles,
resulting in a lower switching frequency than programmed
by RT. The LT8625S will switch as frequently as necessary
to keep the boost capacitor refreshed, with a minimum
switching frequency of approximately 80kHz. Note thathigher switching frequency will increase the minimum
input voltage below which cycles will be dropped toachieve higher duty cycle.

Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, and input voltage range. The
advantage of high frequency operation is that smaller
inductor and capacitor values may be used. The disadvantages are lower efficiency and a smaller input voltage
range. The highest switching frequency (fSW(MAX)) fora given application can be calculated using Equation 2.
fSW(MAX) =where VIN is the typical input voltage, VOUT is the output
voltage, VSW(TOP) and VSW(BOT) are the internal switch
drops (~0.29V and ~0.13V, respectively at maximumload) and tON(MIN) is the minimum top switch on-time(see the Electrical Characteristics table). This equationshows that a slower switching frequency is necessary toaccommodate a high VIN/VOUT ratio.

VOUT + VSW(BOT)tON(MIN) VIN − VSW(TOP) + VSW(BOT))(2)

In FCM, the LT8625S does not skip cycles, and so the
maximum duty cycle is limited by the minimum off timeand chosen switching frequency. For applications thatcannot allow deviation from the programmed switchingfrequency at low VIN/VOUT ratios and thus must operate
in FCM, use Equation 3 to set switching frequency.
VIN(MIN) =VOUT + VSW(BOT)
1− fSW • tOFF(MIN)− VSW(BOT) + VSW(TOP) (3)where VIN(MIN) is the minimum input voltage withoutskipped cycles, VOUT is the output voltage, VSW(TOP)and VSW(BOT) are the internal switch drops (~0.29V and~0.13V, respectively at maximum load), fSW is the switching frequency (set by RT), and tOFF(MIN) is the minimum
switch off-time.

Rev. BFor more information www.analog.com

19

LT8625SAPPLICATIONS INFORMATION
Inductor Selection and Maximum Output Current
The LT8625S is designed to minimize solution size by
allowing the inductor to be chosen based on the output loadrequirements of the application. During overload or shortcircuit conditions, the LT8625S safely tolerates operation
with a saturated inductor through the use of a high-speed
peak-current mode architecture.
A good first choice for the inductor value is given by
Equation 4.
⎛ VOUT + VSW(BOT) ⎞L=⎜⎟⎠ • 0.5
fSW
⎝

(4)

where fSW is the switching frequency in MHz, VOUT is
the output voltage, VSW(BOT) is the bottom switch drop(~0.13V) and L is the inductor value in µH.
To avoid overheating and poor efficiency, an inductor
must be chosen with an RMS current rating that is greaterthan the maximum expected output load of the application. In addition, the saturation current (typically labeled
ISAT) rating of the inductor must be higher than the load
current plus ½ of inductor current. See Equation 5.
1
IL(PEAK) =ILOAD(MAX) + ∆IL
2(5)

where ∆IL Is the inductor ripple current as calculated in
Equation 7 and ILOAD(MAX) is the maximum output load
for a given application.
As a quick example, an application requiring 3A output
should use an inductor with an RMS rating of greater than
3A and an ISAT of greater than 4A. During long duration
overload or short-circuit conditions, the inductor RMS
rating requirement is greater to avoid overheating of theinductor. To keep the efficiency high, the series resistance(DCR) should be less than 0.015Ω, and the core material
should be intended for high frequency applications.
The LT8625S limits the peak switch current in order toprotect the switches and the system from overload faults.
The top switch current limit (ILIM) is 16A at low duty
cycles and decreases linearly to 13A at duty cycle = 80%.
The inductor value must then be sufficient to supply thedesired maximum output current (IOUT(MAX)), which isa function of the switch current limit (ILIM) and the ripple current (see Equation 6).
IOUT(MAX) =ILIM −

∆IL
2

(6)

The peak-to-peak ripple current in the inductor can becalculated using Equation 7.
∆IL =⎞VOUT ⎛V• ⎜ 1 − OUT ⎟L • fSW ⎝VIN(MAX) ⎠(7)

where fSW is the switching frequency of the LT8625S, and
L is the value of the inductor. Therefore, the maximum
output current that the LT8625S will deliver depends on
the switch current limit, the inductor value, and the input
and output voltages. The inductor value may have to be
increased if the inductor ripple current does not allow
sufficient maximum output current (IOUT(MAX)) given theswitching frequency and maximum input voltage used in
the desired application.
The optimum inductor for a given application may differ
from the one indicated by this design guide. A larger value
inductor provides a higher maximum load current andreduces the output voltage ripple. For applications requiring smaller load currents, the value of the inductor may
be lower and the LT8625S may operate with higher ripple
current. This allows use of a physically smaller inductor,
or one with a lower DCR resulting in higher efficiency. Be
aware that low inductance may result in discontinuous
operation, which further reduces maximum load current.
For more information about maximum output current anddiscontinuous operation, see Analog Device’s Application
Note 44.
For duty cycles greater than 50% (VOUT/VIN > 0.5), a
minimum inductance is required to avoid sub-harmonic
oscillation. See Application Note 19. Equation 8 calculates
that minimum inductance.
LMIN =

PVIN ( 2 •DC−1)
4.4 • fSW

(8)

where DC is the duty cycle ratio (VOUT/VIN) and fSW is theswitching frequency.
Rev. B20

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LT8625SAPPLICATIONS INFORMATION
Input Capacitors
The PVIN of the LT8625S should be bypassed with at least
three ceramic capacitors for best performance. Two small
ceramic capacitors can be placed close to the part (COPT1,
COPT2). These capacitors should be 0402 or 0603 in size.
Note that larger input capacitance is required when a lower
switching frequency is used. If the input power source hashigh impedance, or there is significant inductance due tolong wires or cables, additional bulk capacitance may benecessary. This can be provided with a low performanceelectrolytic capacitor.
A ceramic input capacitor combined with trace or cableinductance forms a high quality (under damped) tankcircuit. If the LT8625S is plugged into a live supply, theinput voltage can ring to twice its nominal value, possibly
exceeding the LT8625S’s voltage rating. This situation iseasily avoided (see Analog Device’s Application Note 88).
When SVIN and PVIN are powered from the same supply, asmall RC filter (e.g., 10Ω and 1µF) from the supply to SVIN
can be added for particularly noise sensitive applications.
If SVIN and PVIN are powered from independent supplies,
SVIN should also be bypassed with a single small ceramic
capacitor of at least 1µF placed as close to the pin as
possible.
Output Capacitor and Output Ripple

can be used to save space and cost, but transient performance will suffer and may cause loop instability. See
the Typical Applications in this data sheet for suggested
capacitor values.
When choosing a capacitor, special attention should begiven to the data sheet to calculate the effective capacitance under the relevant operating conditions of voltage
bias and temperature. A physically larger capacitor or one
with a higher voltage rating may be required.
The LT8625S will typically be operated at a switching frequency of 2MHz. Table 2 shows some examples of output
capacitors with ideal frequency characteristics for when
operating at switching frequencies around 2MHz. Figure 6
shows the frequency characteristics of these capacitors;
it can be seen that a combination of these capacitors will
minimize the impedance at the switching frequency on
the output and keep the impedance low enough to suppress any higher frequency harmonics near the switchingfrequency, thus achieving the lowest output ripple.
Table 2. Examples of Output Capacitors with Desirable
Frequency Characteristics for 2MHz Operation
PART DESCRIPTIONMANUFACTURER/PART NUMBER

22µF, X7R, 10V, 20% 1206

MURATA, GRM31CR71A226ME15K

10µF, X7R, 25V, 10% 1206

MURATA, GRM31CR71E106KA12

4.7µF, X7S, 16V, 10% 0603

MURATA, GRM188C71C475KE21

of Recommended Capacitors

Use X5R or X7R types. This choice will provide low output ripple and good transient response. Transient performance can be improved with a higher value output capacitor. Increasing the output capacitance will also decrease
the output voltage ripple. A lower value of output capacitor

10k
GRM31CR71A226ME15K (22µF)
GRM31CR71E106KA12 (10µF)
GRM188C71C475KE21 (4.7µF)

1k
100
IMPEDANCE (Ω)

The output capacitor has two essential functions. Alongwith the inductor, it filters the square wave generated by
the LT8625S to produce the DC output. In this role it
determines the output ripple, thus low impedance at theswitching frequency is important. The second function
is to store energy in order to satisfy transient loads andstabilize the LT8625S’s control loop. Ceramic capacitors
have very low equivalent series resistance (ESR) andprovide the best ripple performance. For good starting
values, see the Typical Applications section.

10
1
100m
10m
1m
100

1k

10k 100k
1M
FREQUENCY (Hz)

10M

100M

8625s F06

Figure 6. Frequency Characteristics of Example
Output Capacitors for 2MHz operationRev. BFor more information www.analog.com

21

LT8625SAPPLICATIONS INFORMATION
Output Voltage
The LT8625S incorporates a precision 100µA current
source flowing out of the SET pin, which also ties to theerror amplifier’s non-inverting input. Figure 7 illustrates
that connecting a resistor from SET to GND generates areference voltage for the error amplifier. This reference
voltage is simply the product of the SET pin current andthe SET pin resistor. The error amplifier’s unity-gain configuration produces a low impedance version of this voltage on its inverting input, the OUTS pin, which is externally tied to output voltage of the circuit.

4.7µF

SVIN
DRIVERS
100µA

SET

SW

L
VOUT
COUT

OUTS

–
+

VC
RC

CSET

Table 3. 1% Resistor for Common Output Voltages
VOUT (V)RSET (kΩ)

0.8

8.06

1

10

LT8625S

PVIN

VIN

for a 0.8V output voltage a resistor value of exactly 8k is
desired. The closest value with a single 1% resistor is
8.06k; with two resistors, 8.25k can be paralleled with
267k to achieve (almost) exactly 8k. 0.1% resistors may
be used in order to achieve higher accuracy.

RSET

CC
GND
8625s F07

Figure 7. Adjustable Reference for Error Amplifier

The LT8625S’s error amplifier and current reference
allows for a wide output voltage range from 0V (using a0Ω resistor) to 6V. A PNP-based input pair is active from
VOUT equals 0V up to VIN minus 0.9V and an NPN-based
input pair is active for output voltages where VIN – VOUT
< 0.5V or less, with a smooth transition between the two
input pairs in between these ranges. The PNP-based input
pair is designed to offer the best overall performance as
it is active in the vast majority of applications; refer tothe Electrical Characteristics table for details on offset
voltage, SET pin current and output noise. Output noise
variation with error amp input pair can be found in Typical
Performance Characteristics section. Table 3 lists many
common output voltages and their corresponding 1%
RSET resistors. Where the exact resistor value required
for the output voltage is not available, two resistors canbe paralleled to achieve the desired value. For example,

1.8

18

2.5

24.9

3.3

33.2

5

49.9

The benefit of using a current reference compared witha voltage reference as used in conventional regulators isthat the regulator always operates in unity gain configuration, independent of the programmed output voltage.
This allows the LT8625S to have loop gain, frequency
response, and bandwidth independent of the output voltage. Moreover, since none of the error amp gain is needed
to amplify the SET pin voltage to a higher output voltage,
output load regulation is more tightly specified.
Since the zero TC current source is highly accurate, theSET pin resistor can become the limiting factor in achieving high accuracy. Hence, it should be a precision resistor.
Additionally, any leakage paths to or from the SET pin
create errors in the output voltage. If necessary, use highquality insulation (e.g., Teflon, Kel-F); moreover, cleaning of all insulating surfaces to remove fluxes and otherresidues may be required. High humidity environments
may require a surface coating at the SET pin to providea moisture barrier.
Since the SET pin is a high impedance node, unwanted signals may couple into the SET pin and cause erratic behavior. This is most noticeable when operating with a minimum output capacitor at heavy load currents. Bypassing
the SET pin with a small capacitance to GND resolves
this issue—100nF is sufficient. This is the minimum recommended capacitance. In general a larger capacitanceis typically preferred (see Set Pin (Bypass) Capacitance:
Noise, Transient Response and Soft-Start section).
Rev. B22

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LT8625SAPPLICATIONS INFORMATION

Output Sensing and Stability
The LT8625S’s OUTS pin provides a Kelvin sense connection to the output. The SET pin resistor’s GND side provides a Kelvin sense connection to the load’s GND side.
The LT8625S internal error amplifier has a relatively highvoltage gain of ~2800. Therefore, it is very important toavoid adding extra impedance (ESR and ESL) to the feedback loop and to minimize the noise coupling onto the
OUTS pin, as a combination of excessive parasitics andnoise injection can cause instability in the system. To that
end, minimize the effects of PCB trace and solder inductance by tying the OUTS pin directly to COUT and the GND
side of CSET directly to the GND side of COUT. If this is notpossible, for example, due to a design requiring remotesense, a small local OUTS capacitor of 150pF or less may
be added for noise decoupling at the OUTS pin. Refer tothe LT8625S demo board manual for more information on
the recommended layout that meets these requirements.
The LT8625S is an externally compensated part, so even
if the recommended layout is not followed (sometimes it
is not possible due to application specific limitations), it
is possible to choose a more conservative compensation
with lower gain or bandwidth in order to retain stability
during operation. However, this would be at the expense oftransient response. A superior layout allows a better tradeoff between transient response, phase margin, and output
noise performance when selecting compensation values.

network can be complicated and the best values dependon the application. A practical approach is to start with
one of the circuits in this data sheet that is similar to yourapplication and tune the compensation network to optimize the performance. LTpowerCAD simulation can help
in this process. Stability should then be checked across all
operating conditions, including load current, input voltage
and temperature. The LT1375 data sheet contains a morethorough discussion of loop compensation and describes
how to test the stability using a transient load.
Figure 8 shows an equivalent circuit for the LT8625S
control loop. The error amplifier is a transconductance
amplifier with finite output impedance. The power section,
consisting of the modulator, power switches, and inductor,
is modeled as a transconductance amplifier generating an
output current proportional to the voltage at the VC pin.
Note that the output capacitor integrates this current, andthat the capacitor on the VC pin (CC) integrates the error
amplifier output current, resulting in two poles in the loop.
A zero is required and comes from a resistor RC in series
with CC. This simple model works as long as the valueof the inductor is not too high and the loop crossover
frequency is much lower than the switching frequency.
For more information about the compensation of switching mode power supplies, refer to Application Note 149:
Modeling and Loop Compensation Design of Switching
Mode Power Supplies.

LT8625SOUTPUT

gm = 11S

Frequency Compensation
Loop compensation determines the stability and transient
performance and is provided by the components tied to
the VC pin. Generally, a capacitor (CC) and a resistor (RC)in series to ground are used. Designing the compensation

VC

280k

RC
CC

gm = 12mS
OUTS

+
–

For applications requiring higher accuracy or an adjustable output voltage, the SET pin may be actively driven
by an external voltages source capable of sinking 100µA.
Connecting a precision voltage reference to the SET pin
eliminates any errors present in the output voltage dueto the reference current and SET pin resistor tolerances.

COUT
CSET

CF

RSET
8625s F08

Figure 8. Model for Loop Response
Rev. BFor more information www.analog.com

23

LT8625SAPPLICATIONS INFORMATION
Enable Pin
The LT8625S is in shutdown when the EN/UVLO pin is low
and active when the pin is high. The rising threshold of
the EN/UVLO comparator is 1.32V, with 50mV of hysteresis. The EN/UVLO pin can be tied to VIN if the shutdown
feature is not used or tied to a logic level if shutdown
control is required.
When the enable pin drops below 1.32V, the part enters ashutdown state where the part stops switching, but internal circuitry will continue drawing current as the INTVCC
regulator is still awake. Full shutdown is guaranteed whenthe enable pin drops below 400mV. In full shutdown the
INTVCC regulator is disabled and the part will draw lessthan 100µA.
Adding a resistor divider from PVIN to EN/UVLO programs
the LT8625S to regulate the output only when PVIN is above
a desired voltage (see the Block Diagram). Typically, thisthreshold, PVIN(EN), is used in situations where the input
supply is current limited, or has a relatively high source
resistance. A switching regulator draws constant powerfrom the source, so source current increases as source
voltage drops. This looks like a negative resistance loadto the source and can cause the source to current limit orlatch low under low source voltage conditions. The PVIN(EN)threshold prevents the regulator from operating at source
voltages where the problems might occur. This threshold
can be adjusted by setting the values REN1 and REN2 suchthat they satisfy Equation 9.
⎛R⎞
PVIN(EN) = ⎜ EN1 +1⎟ •1.32V⎝ REN2 ⎠(9)where the LT8625S will remain off until PVIN is above
PVIN(EN). Due to the comparator’s hysteresis, switching
will not stop until the input falls slightly below PVIN(EN).
INTVCC Regulator
An internal low dropout (LDO) regulator produces the
3.4V supply from SVIN that powers the drivers and theinternal bias circuitry. The INTVCC can supply enoughcurrent for the LT8625S’s circuitry. Voltage on INTVCC willvary between 2.6V and 3.4V when SVIN is between 2.7V
and 3.5V. If SVIN is connected to a different supply thanPVIN, be sure to bypass SVIN with a local ceramic capacitor. Do not connect an external load to the INTVCC pin.
Set Pin (Bypass) Capacitance: Noise, Transient
Response and Soft-Start
In addition to reducing output noise, using a SET pin
bypass capacitor will reduce sensitivity to any parasitic
coupling of voltage spikes onto the SET pin. Note that any
bypass capacitor leakage deteriorates the LT8625S’s DC
regulation. Capacitor leakage of even 100nA is a 0.1% DC
error. Therefore, it is recommended to use a good quality,
low leakage ceramic capacitor.
Using a SET pin bypass capacitor also soft-starts theoutput and limits inrush current. Soft-starting the output
prevents a current surge on the input supply. The SET pin
capacitor and resistor values set the ramp-up time of thereference voltage, and the output voltage will track thisvoltage. The SET pin resistor size is determined by theapplication’s desired output voltage, however the capacitor size may be selected to achieve the desired ramp up
time. It is important to keep in mind the size of the SET pin
capacitor also plays a role in noise performance, which
is typically the more important factor in determining thesize of this capacitor.
Ceramics are manufactured with a variety of dielectrics,
each with a different behavior across temperature andapplied voltage. Care should be taken when selecting aceramic capacitor for bypassing the SET pin, as this is a
critical component. A X7R (or better) ceramic capacitor
is strongly recommended for its superior stability acrosstemperature and DC voltage bias. Additionally, it is recommended to use larger case sizes for better DC bias
characteristics as well as AC voltage characteristics.
As shown in Figure 9 capacitor DC bias characteristics
tend to improve as component case size increases.

Rev. B24

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LT8625SAPPLICATIONS INFORMATION20CAPACITANCE CHANGE RATE (%)

20

CHANGE IN VALUE (%)

0
–20
–40
–60
–80
–100

MURATA: 25V,10%,
X7R, 10µF CERAMIC
1

5

10
15
DC BIAS (V)

0
–10
–20
–30
0402 6.3V (GRM155R70J105KA12)0402 10V (GRM155C71A105KE11)0805 35V (GRM219R7YA105KA12)0805 100V (GRM21BC72A105KE01)

–40
–50
–60
0.0

25

20

10

0.5

1.0
1.5
AC VOLTAGE (VRMS)

28625s F10a8625s F09(a) Rated Capacitance = 1μF

GRM SERIES, 0805, 1.45mm THICKGRM SERIES, 1206, 1.8mm THICKGRM SERIES, 1210, 2.2mm THICK

Larger case sizes are also beneficial for improved AC voltage characteristics. Capacitor values are often rated at
1VRMS of AC voltage, and can drop significantly when
operating near 0VRMS, which is the operating conditionof a bypass capacitor.
As shown in Figure 10a, Figure 10b and Figure 10c, larger
case sizes tend to experience a smaller capacitance dropwhen operating near 0VRMS. Therefore, an 0805 or larger
ceramic capacitor should be used for the SET pin bypass
capacitor for best performance. A larger desired capacitance value may require larger case sizes; for example, a
4.7µF value should use 1206 or larger.
Table 4 shows some recommended SET pin capacitors.
Table 4. Suggested SET Capacitor Part Numbers
PART DESCRIPTIONMANUFACTURER/PART NUMBER

1µF, X7R, 35V, 0805

MURATA, GRM219R7YA105KA12

4.7µF, X7R, 50V, 1206

MURATA, GRM31CR71H475MA1210µF, X7R, 100V, 1210

MURATA, GRM32EC72A106KE05

For high vibration environments, non-piezoelectrically
responsive capacitors should be used at the SET pin for
optimal performance. A piezoelectric ceramic capacitor
generates voltage across its terminals due to mechanicalstress upon it, induced by mechanical vibrations or thermaltransients. Film capacitors are the preferred option. If aceramic must be used, soft-termination ceramics are available which reduce the sensitivity to the piezo-electric effect.

10
0
–10
–20
–30
–40
–50
–60
0.0

0603 16V (GRM188C71C475KE)
0805 16V (GRM21BR71C475KE)
0805 50V (GRM21BC71H475KE)
1206 50V (GRM31CR71H475KA)
0.5

1.0
1.5
AC VOLTAGE (VRMS)

28625s F10b(b) Rated Capacitance = 4.7μF
20
CAPACITANCE CHANGE RATE (%)

Figure 9. Capacitor Voltage Coefficient for Different Case Sizes

CAPACITANCE CHANGE RATE (%)

20

10
0
–10
–20
–30
–40
–50
–60
0.0

0805 25V (GRM21BC71E106KE1)
1206 25V (GRM31CR71E106KA1)
1206 50V (GRM31CD71H106KE1)
1210 100V (GRM32EC72A106KE)
0.5

1.0
1.5
AC VOLTAGE (VRMS)

28625s F10c(c) Rated Capacitance = 10μF
Figure 10. AC Voltage Characteristics forDifferent Capacitor Case Sizes

Rev. BFor more information www.analog.com

25

LT8625SAPPLICATIONS INFORMATION
Without fast start-up enabled, the RC time constant,formed by the SET pin resistor and capacitor, controls
soft-start time. Tie the PGFB pin to 0.5V to disable fast
start-up. Ramp-up rate from 0% to 90% of nominal VOUT
is given by Equation 10.
tSTART _NO_FAST _START–UP = 2.3 •RSET •CSET(10)

With fast-start-up enabled, the start-up time can be significantly reduced with the ramp-up time from 0% to 90%
of nominal VOUT is given by Equation 11.
tSTART _FAST _START–UP =100µA •RSET •CSET
2.7mA

(11)

In most applications, fast start-up will be enabled, inwhich case a minimum SET capacitor size of 1μF is recommended for preventing reference voltage overcharge
as well as ensuring good noise performance.
The SET pin is pulled to ground with a 500Ω MOSFET(RSET-PULLDOWN) during shutdown, thermal shutdown,
VCC UVLO or VIN UVLO. To ensure soft-start when the partexits any of the above conditions, there must have been
sufficient time to allow the SET pin to be pulled to close
to ground prior to start-up. This time will be a functionof the chosen SET pin capacitance and RSET-PULLDOWN.
Soft-Start and Power Sequencing
As discussed in the previous Set Pin (Bypass) Capacitance:
Noise, Transient Response and Soft-Start section, softstart is achieved through the controlled ramp up time of
the SET pin voltage. Soft-start is guaranteed when PVIN
and SVIN are tied together.
When PVIN and SVIN are powered by independent supplies, power sequencing must be considered to guarantee
soft-start. The SET pin voltage should start at 0V when
PVIN is applied. To guarantee soft-start, do not power
PVIN last when sequencing PVIN, SVIN and EN/UVLO . An
example of a specific case to avoid is having SVIN and
EN/UVLO powered up before PVIN; in this instance, theSET pin voltage will have risen to some voltage greaterthan 0V when PVIN is applied, and the LT8625S will not
soft-start correctly.

If connecting EN/UVLO to PVIN instead of driving it witha digital signal, it is recommended to connect EN/UVLO
to PVIN through a resistor divider to set an appropriate
UVLO threshold. This ensures correct startup and shutdown behavior in the event of rapid power cycling.
Fast Start-Up
For ultralow noise applications that require low 1/f noise(i.e., at frequencies below 100Hz), a larger value SET pin
capacitor is required, up to 22µF. A larger value capacitor
can be used but care should be taken regarding leakage. While normally larger capacitors would significantly
increase the regulator’s start-up time, the LT8625S incorporates fast start-up circuitry that increases the SET pin
current to about 2.7mA during start-up.
Upon start-up, the 2.7mA current source remains
engaged while PGFB is below the Power Good thresholdof 462.5mV, unless the regulator is in thermal shutdown,
SVIN is too low, or INTVCC has fallen too low.
The fast start-up circuit is disabled permanently once
PGFB rises above the Power Good threshold, until either
the part is powered down, or the part is placed into shutdown by pulling the EN/UVLO pin below 1.32V.
There is one more condition under which the 2.7mA
current source is disabled during start-up. The purposeof this is to prevent overcharging VSET. Since the partassumes that the PGFB pin is an accurate indication of
the voltage on the SET pin, it assumes that VOUTS follows
VSET closely. However, this may not always be the case– for example if the output capacitance is very large, orif for some reason the output is temporarily shorted to
GND. Therefore, fast charge is also disabled whenever the
VC pin has railed to its maximum value (when VSET has
risen significantly about VOUTS). This prevents incorrect
behavior where the 2.7mA current sources stays on evenwhen VSET has risen above its intended value.
This means there is also a minimum SET capacitor
requirement for using fast start-up without overcharging
the reference voltage. This will depend on the compensation network, as the part is depending on the VC pin
voltage rising to its maximum value to inform the part topause fast charge.
Rev. B26

For more information www.analog.com

LT8625SAPPLICATIONS INFORMATIONThe recommended minimum required SET capacitancevalue to prevent overcharging the reference voltage is
given in Equation 12.
Minimum CSET = 27 •

CCOMP
VSET

(12)

If programmable power good and fast start-up capabilities are not required, the PGFB pin must be tied to 0.5V.

Table 5. Suggested PGFB Resistor Divider Values
VOUT (V)RPGFB(TOP) (kΩ)

RPGFB(BOT) (kΩ)

5

453

49.9

Power Good at Start-Up
In some cases, certain ceramic capacitors on the SET pin
may cause a small dip in the SET voltage during the transition from fast start-up current to 100μA. SET capacitors
VIN

Programmable Power GoodAs illustrated in the Block Diagram, power good threshold is user programmable using the ratio of two external
resistors, RPGFB(BOT) and RPGFB(TOP) (see Equation 13).

VIN
EN

OUTS
LT8625S

SET
RSET

CSET

PG

⎛ RPGFB(TOP) ⎞⎜ 1+⎟ + IPGFB • RPGFB(TOP)⎝ RPGFB(BOT) ⎠(13)

If the PGFB pin increases above 537.5mV or decreases
below 462.5mV, the open-drain PG pin de-asserts andbecomes high impedance. The power good comparator
has 5mV hysteresis. The PGFB pin current (IPGFB) fromthe Electrical Characteristics table must be consideredwhen determining the resistor divider network. Please
note that the programmable power good and fast startup capabilities are disabled when PGFB is tied to 0.5V orwhen the device is in shutdown.
The PGFB pin current (IPGFB) can be ignored if RPGFB(BOT)
is less than 50k. Table 5 suggests some 1% PGFB resistor
divider values for common VOUT configurations.
Table 5. Suggested PGFB Resistor Divider Values

RPGFB(TOP)PGFB
8625s F11

VOUT(PG_ THRESHOLD) = 0.5V •

VOUT

SW

RPGFB(BOT)CPGFB

Figure 11. Figure 1. Schematic with CPGFB

with better AC voltage characteristics (see Figure 10) may
be less susceptible to this phenomenon. This SET voltage
dip may cause a glitch on PG during start-up. If a PG glitch
during start-up may cause an issue in the system, this canbe handled simply by adding a small capacitor between
the PGFB pin and GND (CPGFB) as shown in Figure 11.
The addition of CPGFB delays the time past the PG threshold at which fast start-up current turns off; this capacitor can be sized to compensate for the SET voltage dip.
Table 6 shows suggested CPGFB values for a given CSET
value, assuming RPGFB(BOT) ≈ 50kΩ (as in Table 5). For
VOUT = 0.5V, the OUTS pin should be tied to the PGFB pin
with a 12.1k resistor, and a CPGFB value chosen according
to Table 6.
Table 6. Suggested CPGFB Value for Given CSETVOUT (V)RPGFB(TOP) (kΩ)

RPGFB(BOT) (kΩ)

0.8

29.4

48.7

CSET (µF)

CPGFB (pF)

0.9

39.2

48.7

0.47

220

1

49.9

49.9

1

470
1000

1.2

69.8

49.9

2.2

1.8

130

49.9

4.7

2200

3.3

280

49.9

10

4700

Rev. BFor more information www.analog.com

27

LT8625SAPPLICATIONS INFORMATION
Multiphase Operation

Output Voltages Above 6V

For output loads that demand more current, multiple
LT8625S can be connected in parallel to the same output. To do this, the VC, OUTS pins are connected together,and each LT8625S’s SW node is connected to the common output through its own inductor. The CLKOUT signal
can be connected to the SYNC/MODE pin of the following
LT8625S to line up both the frequency and the phase of
the entire system. Tying the PHMODE pin to GND, INTVCC,
or floating the pin generates a phase difference between
the LT8625S’s internal clock and CLKOUT of 180 degrees,
90 degrees, or 120 degrees respectively, which corresponds to 2-phase, 4-phase, or 3-phase operation. A totalof 12 phases can be paralleled to run simultaneously outof-phase with respect to each other by programming the
PHMODE pin of each LT8625S to different voltage levels.
During FCM and Synchronization modes all devices will
operate at the same frequency. Figure 12 shows a 2-phaseapplication where two LT8625S are paralleled to get one
output capable of up to 16A.

The LT8625S can be configured for output voltages above
6V, even though the SET pin voltage is limited to a maximum of 6V, by using a traditional resistor divider from
VOUT to OUTS as shown in Figure 13. It is recommended
to configure the SET pin voltage to be 5V, in which case theresistor values can be chosen according to Equation 14.

Due to the current reference architecture of the LT8625S,
the SET pins can also be tied together as shown in
Figure 12 for better noise performance in the low frequency range, reduced component count, and superior
current sharing between the phases due to the use of acommon reference.
If two SET pins are tied together as in Figure 12, the total
current running through RSET will be 200µA. The RSET
value should be sized accordingly; in this case, for 1VOUT,
a RSET value of 5k will be required.
L1
CSET

RSET

VC
RC

VOUT
16A
COUT

SW

SET
LT8625SOUTS
PGFB

CLKOUT

PHMODERPGFB(TOP)

CC

SET

RPGFB(BOT)

OUTS

VC
LT8625S(14)

The OUTS pin current must be taken into considerationin this configuration as an output divider is used. The
OUTS pin current (IOUTS) when VSET > 2V is 10µA ± 2.5µA
including variation over process and temperature. When
VSET ≤ 2V, the OUTS pin current is 160nA ± 80nA per theElectrical Characteristics table. The divider values R1 andR2 can be chosen such that this OUTS pin current variation introduces <0.1% error in output voltage regulation.
An example for VOUT = 9V can be found in the TypicalApplication section.
L
SW
SET
CSET

RSET

VOUT
R1

LT8625S
OUTS
GND

CPL
COUT

R2
8625s F13

Figure 13. Configuring the LT8625S for Output Voltages Above 6V

At output voltages above 6V, the low frequency noise will
have some dependency on the output voltage; the divider
gains up the noise. By configuring the SET voltage to be
5V, this dependency is minimized; for example, the noise
gain from a 5V reference to 9VOUT will be ten times lower
than the gain from a conventional 0.5V voltage reference
to 9VOUT.
Shorted and Reversed Input Protection

PGFB
L2

SYNC/MODE⎛ VOUT − 5V ⎞R1= R2 ⎜⎝ 5V +R2 •IOUTS ⎟⎠SW
8625s F12

Figure 12. Paralleling Two LT8625S Devices

The LT8625S will tolerate a shorted output. The bottom
switch current is monitored such that if inductor current
is beyond safe levels, switching on of the top switch will
be delayed until such time as the inductor current falls tosafe levels.
Rev. B28

For more information www.analog.com

LT8625SAPPLICATIONS INFORMATION
There is another situation to consider in systems where
the output will be held high when the input to the LT8625S
is absent. This may occur in battery charging applications
or in battery-backup systems where a battery or someother supply is diode ORed with the LT8625S’s output.
If the PVIN pin is allowed to float and the EN/UVLO pin
is held high (either by a logic signal or because it is tied
to VIN), then the LT8625S’s internal circuitry will pull its
quiescent current through its SW pin. This is acceptable
if the system can tolerate current draw in this state. If the
EN/UVLO pin is grounded the SW pin current will drop
to ~50µA.

junction rating. Power dissipation within the LT8625S
can be estimated by calculating the total power loss froman efficiency measurement and subtracting the inductor loss. The die temperature is calculated by multiplying
the LT8625S power dissipation by the thermal resistancefrom junction to ambient.

However, if the PVIN pin is grounded while the output isheld high, regardless of EN/UVLO, parasitic body diodes
inside the LT8625S can pull current from the output
through the SW pin and the PVIN pin. Figure 14 shows aconnection of the PVIN and EN/UVLO pins that will allow
the LT8625S to run only when the input voltage is present and that protects against a shorted or reversed input.

Temperature rise of the LT8625S is worst when operating
at high load, high VIN and high switching frequency. If thecase temperature is too high for a given application, theneither VIN, switching frequency, or load current can be
decreased to reduce the temperature to an appropriate
level. Figure 15 shows examples of how case temperaturerise can be managed by reducing switching frequency
or load.

D1
VIN

The internal overtemperature protection monitors thejunction temperature of the LT8625S. If the junction
temperature reaches approximately 165˚C, the LT8625S
will stop switching and indicate a fault condition until thetemperature drops about 5˚C cooler.

The LT8625S’s top switch current limit decreases withhigher duty cycle operation for slope compensation. This
also limits the output current the LT8625S can deliver
for a given application. See curve in Typical Performance
Characteristics.

VIN
LT8625S
EN/UVLO
GND
8625s F14

Figure 14. Reverse VIN Protection

Thermal Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of theLT8625S. The exposed pad on the bottom of the package
should be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread heat dissipated by the LT8625S.
Placing additional vias can reduce thermal resistancefurther. The maximum load current should be derated
as the ambient temperature approaches the maximum

CASE TEMPERATURE RISE (°C)

80

DEMO BOARD DC3002A
70 ON STILL AIR
PVIN = 12V
SVIN = 3.3V
60
VOUT = 1V
50
40
30
20
1MHz
2MHz

10
0

0

1

2

3
4
5
6
LOAD CURRENT (A)788625s F15

Figure 15. LT8625S Case Temperature Rise

Rev. BFor more information www.analog.com

29

LT8625S
TYPICAL APPLICATIONS
1V 8A 4MHz Step-Down Converter with Soft-Start, Fast Start-up and Power Good
0.18µH
VIN
2.7V TO 18V

PVIN
22µF

SW

EN/UVLO

22µF

SVIN

1µF

VOUT
1V
8A

OUTS
PG

LT8625S

49.9k

VC
SET
4.99k

4.7µF
1206
X7R
50V

10k

1nF

PGFB

RT
18k

49.9k

2.2nF

GND

22µF
×3
1206
X7R

8625s TA02

fSW = 4MHz
PINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCCCSET: GRM31CR71H475MA12

TYPICAL PERFORMANCE CHARACTERISTIC
4MHz, 1VOUT NOISE DATA USES THIS CIRCUIT

1V 8A 2MHz Step-Down Converter with Soft-Start, Fast Start-up and Power Good
0.33µH

VIN
2.7V TO 18V

PVIN
22µF

SW

EN/UVLO

22µF
1µF

VOUT
1V
8A

OUTS

SVIN
LT8625S

PG
49.9k

VC
SET
1k

4.7µF
1206
X7R
50V

10k

2nF

PGFB

RT
47k

2.2nF

GND

49.9k

22µF
×5
1206
X7R

8625s TA03

fSW = 2MHzPINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCCTYPICAL CHARACTERISTIC
2MHz, 1VOUT NOISE DATA USES THIS CIRCUITCSET: GRM31CR71H475MA12

1.2V 8A 1MHz Step-Down Converter with Soft-Start, Fast Start-up and Power Good
PVIN
2.7V TO 18V

PVIN
EXTERNAL ENABLE SIGNAL
22µF

SW

EN/UVLO

1µF

SVIN

VOUT
1.21V
8A

OUTS

22µF
SVIN
2.7V TO 18V

0.68µHPG

LT8625S

69.8k
VC

PGFB

SET

1k
12.1k
4.7nF

4.7µF
1206
X7R
50V

RT
105k

2.2nF

GND

49.9k

22µF
×5
1206
X7R

8625s TA04

fSW = 1MHzPINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCCTO GUARANTEE SOFT-START
DO NOT POWER PVIN LAST WHEN SEQUENCING
PVIN, SVIN AND EN/UVLO

CSET: GRM31CR71H475MA12Rev. B30

For more information www.analog.com

LT8625S
TYPICAL APPLICATIONS
0.5V 8A 1MHz Step-Down Converter with Soft-Start, Fast Start-Up and Power Good
0.33µH
PVIN
2.7V TO 18V

PVIN
EN/UVLO
22µF

SW

VOUT

OUTS

0.5V
8A

22µF
SVIN
2.7V TO 18V

1µF

SVIN

VC
1k
4.99k
4.7nF

4.7µF
1206
X7R
50V

PG

LT8625S

12.1k

PGFB

22µF
x5
1206
X7R

SET
RT
105k

2.2nF

GND
8625s TA05

fSW = 1MHzPINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCCTO GUARANTEE SOFT-START
DO NOT POWER PVIN LAST WHEN SEQUENCING
PVIN, SVIN AND EN/UVLO

CSET: GRM31CR71H475MA12

0.2V 8A 300kHz Step-Down Converter with Soft-Start
1.8µH
VIN
2.7V TO 18V

PVIN
22µF

EN/UVLO

22µF

OUTS

SVIN
1µF

LT8625S
220µF
×1

VC
220Ω
2k
33nF

1µF
0805
X7R
35V

VOUT
0.2V
8A

SW

PGFB

SET
RT
392k

GND

0.5V

22µF
×5
1206
X7R

8625s TA06

fSW = 300kHzPINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCC**NOTE THAT APPLICATIONS WITH VOUT BELOW 0.5V WILL NOT BE ABLETO USE THE POWER GOOD AND FAST-STARTUP FUNCTIONALITIES.
CSET: GRM219R7YA105KA12

Rev. BFor more information www.analog.com

31

LT8625S
TYPICAL APPLICATIONS
3.3V 8A 2MHz Step-Down Converter with Soft-Start, Fast Start-Up and Power Good
0.68µH
VIN
3.8V TO 18V

PVIN
22µF

OUTS

EN/UVLO

22µF

SVIN
1µF

VOUT
3.32V
8A

SW
100k

PG
LT8625S

280k

VC
SET
1k

4.7µF
1206
X7R
50V

33.2k

4.7nF

PGFB

RT

49.9k

2.2nF

GND

47k

22µF
×5
1206
X7R

8625s TA07

fsw = 2MHzPINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCCTYPICAL CHARACTERISTIC
2MHz, 3.3VOUT NOISE DATA USES THIS CIRCUITCSET: GRM31CR71H475MA12

5V 8A 2MHz Step-Down Converter with Soft-Start, Fast Start-Up, Power Good and UVLO
0.68µH

VIN
5.5V TO 18V
332k

22µF

22µF

10Ω

PVIN

SW

SVIN

OUTS

1µF
7.75V TURN ON
7.5V TURN OFF

64.9k

LT8625S

3.6nF

49.9k

100k
453k

EN/UVLO
PGFB

VC
2k

PG

4.7µF
1206
X7R
50V

VOUT
5V
8A

SET
RT
47k

2.2nF

GND

49.9k

22µF
×5
1206
X7R

8625s TA08

fSW = 2MHzPINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCCCSET: GRM31CR71H475MA12Rev. B32

For more information www.analog.com

LT8625S
TYPICAL APPLICATIONS
1V 16A 2MHz 2-Phase Step-Down Converter with Soft-Start, Fast Start-Up, and Power GoodCH1
0.33µH
VIN
2.7V TO 18V

22µF

22µF

10Ω

PVIN

SW

SVIN

OUTS

10Ω

100µF

LT8625S

1µF

PG

EXTERNAL
ENABLE
SIGNAL

EN/UVLO
PGFB

VC
SET
100nF

PHMODE

49.9k

RT

47k

GND

CLKOUT
220pF

4.99k

1µF
0805
X7R
35V

fSW = 2MHz

49.9k

VOUT
1V
16A
22µF
×6

CH2
0.33µH

10Ω
1µF

PVIN

SW

SVIN

OUTS

10Ω
100µF

EN/UVLO
LT8625S

1.33k

VC

4.7nF

PGFB

SET
100nF

RT
75k

SYNC
GND
8625s TA09

NOTE: CH2 IS SYNCHRONIZED TO 2MHz VIA SYNC PIN.
RT RESISTOR VALUE MUST SET INTERNAL OSCILLATOR
TO <1.6MHz (80% OF 2MHz)VC PINS TIED TOGETHERPHMODE TIED TO GND
FOR 180 DEG. PHASE SHIFTAT CLKOUT

SET PINS CAN BE TIED TOGETHER
FOR 200μA CURRENT REFERENCE.
THIS PROVIDES LOWER 1/F NOISE
AND BETTER CURRENT SHARING.
CSET: GRM219R7YA105KA12

Rev. BFor more information www.analog.com

33

LT8625S
TYPICAL APPLICATIONS
3.3V Step-Down Converter with Feedthrough Capacitors and Remote Sense
FEEDTHROUGHCAPACITOR
1µH
VIN
3.8V TO 18V

PVIN

10Ω
22µF

22µF

SW

4.7µF ×2

SVIN
1µF

EXTERNAL
ENABLE
SIGNAL

EN/UVLO

OUTS
LT8625S

PG

100k

VC

280k

SET
1k

2.2nF

33.2k

1µF
0805
X7R
35V

PGFB

RT
47k

49.9k
470pF

GND
8625s TA10

47µF
×1
1206
X6S
2.2µF
×1
0603
X6S

4.7µF
×1
0603
X6S

10µF
×1
0805
X6S

22µF
×1
0805
X6S

VOUT
47µF 3.3V
8A
×6
1206
X6S

fSW = 2MHzPINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCCCSET: GRM219R7YA105KA12

Rev. B34

For more information www.analog.com

LT8625S
TYPICAL APPLICATIONSPowering a Transceiver Using 3× LT8625S
0.33µH
PVIN

PVIN
2.7V TO 18V

4.7µF

SW

EN/UVLO

10Ω

SVIN

1µF

VOUT
0.8V

OUTS
LT8625S

PG
29.4k

VC
SET
150Ω

8.06k

47pF

1µF
0805
X7R
35V

RT

PHMODE
SYNC

47k

49.9k

100µF
×2

470pF

CLKOUT

GND

3.3nF

10µF
×2

PGFB

fSW = 2MHz
PHMODE FLOATED
FOR 120 DEG. PHASE SHIFTALLCSET: GRM219R7YA105KA12

0.33µH
PVIN
4.7µF

EN/UVLO

10Ω

OUTS

SVIN

1µF

VOUT (DYNAMIC)
1V

SW

LT8625S

2.8µH

PG

VOUT (STATIC)
1V

49.9k
VC
SET
150Ω
47pF

1µF
0805
X7R
35V

10k

RT

PHMODE
SYNC

105k

3.3nF

10µF
×2

PGFB
49.9k

1Ω

100µF
×2

100nF

470pF
100µF

CLKOUT

GND

0.33µH
PVIN
4.7µF

EN/UVLO

10Ω

OUTS

SVIN

1µF

VOUT (DYNAMIC)
1.8V

SW

LT8625S

3.3µH

PG

VOUT (STATIC)
1.8V

130k
VC

150Ω
47pF
3.3nF

18k

1µF
0805
X7R
35V

10µF
×2

PGFB

SET
RT

49.9k

PHMODE
SYNC

105k
GND

470pF

1Ω

100µF
×2

100nF
100µF

CLKOUT8625s TA11

Rev. BFor more information www.analog.com

35

LT8625S
TYPICAL APPLICATIONS
9V 8A 2MHz Step-Down Converter with Soft-Start, Fast Start-Up and Power Good
0.68µH
VIN
10V TO 18V

PVIN
22µF

1k

EN/UVLO

22µF

SVIN

OUTS

1µF

1k

1µF
0805
X7R
35V

49.9k

4.7nF

VOUT
9V
8A

SW

LT8625S
VC

PG

SET

PGFB

845k

RT

470pF

GND

47k

1.24k

49.9k

22µF
×3
1210
X7R

100µF
×1
1210
X7R

8625s TA12

fsw = 2MHz
CSET: GRM219R7YA105KA12PINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCC

Dynamic Voltage Control 1V-4V 1.6MHz Step-Down Converter with External DAC
VIN
16V
10

10µF

100K

1µF
AD5696

SW

SVIN

OUTS

1µF

INTVCC

82pF

61.9K

PGFB

15µF

GND

10nF
PINS NOT USED IN
THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT

4x 22µF
280K

RT

374

VOUT
1V-4V
8A

LT8625S

VC
49.9K

2.2µH

EN/UVLOSET10K

DAC Output
1.2V-4.8V

PVIN

49.9K
fsw = 1.6MHz

CSET: 1µF 16V X7R 0603 (GRM188R71C105MA12D)

Rev. B36

For more information www.analog.com

For more information www.analog.com

0.375

0.25 ±0.05

4.50 ±0.05

0.70 ±0.05

53.50 ±0.05

1.65

2.65

SUGGESTED PCB LAYOUTTOP VIEW

0.375

PACKAGE TOP VIEW

0.7500

aaa Z

2×

D

0.25000.00000.2500PIN 1
CORNER

0.7500aaa Z

1.25000.75000.25000.00000.25000.75001.2500PACKAGEOUTLINE

X

Y

E

2×

// bbb Z

SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff

DETAIL B

H2

MOLD
CAP

ddd Z
Z

MIN
0.85
0.01
0.30
0.22
NOM
0.94
0.02
0.40
0.25
3.00
4.00
1.65
2.65
0.50
0.24 REF
0.70 REF

DIMENSIONSH1DETAIL C

0.10
0.10
0.10
0.10
0.15
0.08

MAX
1.03
0.03
0.50
0.28

20b
eee M Z X Y
fff M ZZ
SUBSTRATEDETAIL C

A1

20×

e/2
e
L

SUBSTRATE THKMOLD CAP HTNOTESDETAIL A

DETAIL B

A(Reference LTC DWG # 05-08-1602 Rev A)

e

11

b

16

b

D1

e

6

DETAIL A

0.275

7

20

PACKAGE BOTTOM VIEW

0.375

10

17

7

6

1

4

SEE NOTESPIN 1 NOTCH
0.25 × 45°

CORNER SUPPORT PAD CHAMFER IS OPTIONAL

7

TRAY PIN 1
BEVEL

LQFN 20 0619 REV A

PACKAGE IN TRAY LOADING ORIENTATIONLTXXXXXXTHE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII

6COMPONENTPIN 1DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE

METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWNSO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
54

3. PRIMARY DATUM -Z- IS SEATING PLANE

2. ALL DIMENSIONS ARE IN MILLIMETERSNOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

0.375

E1

ccc M Z X Y

ccc M Z X Y

LQFN Package
20-Lead (4mm × 3mm × 0.94mm)

LT8625S

PACKAGE DESCRIPTION

Rev. B37

LT8625SREVISION HISTORY
REV

DATE

DESCRIPTIONPAGE NUMBER

A

01/23

Updated Features: Output Voltage Range

1

B

04/24

Updated Features and Description sections

1

Updated Pin Configuration2

Updated Electrical Characteristics

3

Updated Typical Performance Curves

5, 9Updated Pin Functions

12

Updated Block Diagram
Updated text for Applications Information
Added Typical Application Circuit

13
15, 23, 26
36

Rev. B

38

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license
is granted
by implicationor otherwise under any patent or patent rights of Analog Devices.
For more
informationwww.analog.com

LT8625S
TYPICAL APPLICATION
1V 8A 2MHz Step-Down Converter with Soft-Start, Fast Start-up and Power Good
0.33µH

VIN
2.7V TO 18V

PVIN
22µF

SW

EN/UVLO

22µF
1µF

VOUT
1V
8A

OUTS

SVIN
LT8625S

PG
49.9k

VC
SET
1k

2nF

10k

4.7µF
1206
X7R
50V

PGFB

RT
47k

2.2nF

GND

49.9k

22µF
×5
1206
X7R

8625s TA13

fSW = 2MHzPINS NOT USED IN THIS CIRCUIT:
BST, SYNC, PHMODE, CLKOUT, INTVCCTYPICAL CHARACTERISTIC
2MHz, 1VOUT NOISE DATA USES THIS CIRCUITCSET: GRM31CR71H475MA12RELATED PARTSPART

DESCRIPTIONCOMMENTS

LT8625SP/
LT8625SP-1

18V, 8A Synchronous Step-Down Silent Switcher 3 with Ultralow Noise
Reference

4µVRMS Noise, VIN = 2.7V to 18V, VOUT(MIN) = 0V, IQ = 2.8mA,
4mm × 3mm LQFN-20 or 4mm × 4mm LQFN-24

LT8627SP

18V, 16A Synchronous Step-Down Silent Switcher 3 with Ultralow
Noise Reference

4µVRMS Noise, VIN = 2.8V to 18V, VOUT(MIN) = 0V, IQ = 3.2mA,
4mm × 4mm LQFN-24

LT8642S

18V, 10A Synchronous Step-Down Silent Switcher 2 Regulator

96% Efficiency, VIN: 2.8V to 18V, VOUT(MIN) = 0.6V, IQ = 240µA,
ISD < 1µA, 4mm × 4mm LQFN-24

LTC7151S

20V, 15A Synchronous Step-Down Silent Switcher 2 Regulator

92.5% Efficiency, VIN: 3.1V to 20V, VOUT(MIN) = 0.5V, IQ = 2mA,
ISD < 20µA, 4mm × 5mm LQFN-28

LTC7150S

20V, 20A Synchronous Step-Down Silent Switcher 2 Regulator

92% Efficiency, VIN: 3.1V to 20V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD≤ 40µA, Differential Remote Sense, 6mm × 5mm BGA

LT3042

20V, 200mA, Ultralow Noise Ultrahigh PSRR Linear Regulator

0.8µVRMS Noise and 79dB PSRR at 1MHz, VIN = 1.8V to 20V,
350mV Dropout Voltage, Programmable Current Limit and Power
Good, 3mm × 3mm DFN and MSOP Packages

LT3045

20V, 500mA, Ultralow Noise Ultrahigh PSRR Linear Regulator

0.8µVRMS Noise and 75dB PSRR at 1MHz, VIN = 1.8V to 20V,
260mV Dropout Voltage, 3mm × 3mm DFN and MSOP Packages

LT8650S

42V, Dual 4A, 95% Efficiency, 2.2MHz Synchronous Silent Switcher 2
Step‑Down DC/DC Converter with IQ = 6.2µA

VIN = 3V to 42V, VOUT(MIN) = 0.8V, IQ = 6.2µA, ISD < 1µA,
4mm × 6mm QFN‑32 Package

LT8652S

18V, Dual 8.5A, 94% Efficiency, 2.2MHz Synchronous Silent Switcher 2
Step-Down DC/DC Converter with IQ = 16µA

VIN = 3V to 18V, VOUT(MIN) = 0.6V, IQ = 16µA, ISD = 6µA,
4mm s× 7mm LQFN-36 Package

LTC3636

20V, Dual 6A Synchronous Step-Down Regulator

95% Efficiency, VIN: 3.1V to 17V, VOUT(MIN) = 0.6V, IQ < 8µA(Both Channels Enabled), ISD < 1µA, 3mm × 5mm QFN-24
PackageLT8640S/
LT8643S

42V, 6A Synchronous Step-Down Silent Switcher 2 with IQ = 2.5µA

VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V,
IQ = 2.5μA, ISD < 1μA, 4mm × 4mm LQFN-24

LT8645S/
LT8646S

65V, 8A, Synchronous Step-Down Silent Switcher 2 with IQ = 2.5μA

VIN(MIN) = 3.4V, VIN(MAX) = 65V, VOUT(MIN) = 0.97V, IQ = 2.5µA,
ISD < 1µA, 6mm × 4mm LQFN-32

LT8609/LT8609A

42V, 2A, 94% Efficiency, 2.2MHz Synchronous MicroPower Step-Down
DC/DC Converter with IQ = 2.5µA

VIN(MIN) = 3V, VIN(MAX) = 42V, VOUT(MIN) = 0.8V, IQ = 2.5µA,
ISD < 1µA, MSOP-10E

Rev. B
04/24

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39