S-O2-2
Numerical Simulation of Plasma-induced Charging during SiO2 Etching
SiO2プラズマエッチング中のチャージングシミュレーション
Takashi Yagisawa, Tetsuya Tatsumi and Toshiaki Makabe
八木澤 卓, 辰巳 哲也，真壁 利明
Faculty of Science and Technology, Dept. Electrical Engineering, Keio University
3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223-8522, Japan慶應義塾大学大学院理工学研究科 〒223-8522 神奈川県横浜市港北区日吉3-14-1
A series of our works on a charging problem during SiO2 etching of high-aspect contact hole (HARC) isintroduced. A surface conduction, one of possible mechanisms for reducing the excessive chargeaccumulation at the bottom of the hole exposed to fluorocarbon-based plasma for SiO2 etching, isinvestigated by using both an experimental technique and a numerical model. In addition, a gate tunnelingcurrent is also combined to the model under the presence of a lower gate electrode. The charging voltage isreasonably coincides with a practical value in industry under the typical condition for HARC plasma
etching.

1. General
Top-down plasma processing is increasingly
important for a continuous development of ultra
large scale integrated (ULSI) circuits. In particular,etching of contact holes through SiO2 film to Si or
silicon nitride layers is a crucial process for thefabrication of multilayer interconnects. In past twodecades, dry etching technology of high aspect-ratio
contact hole (HARC) has been suffering from anumber of difficulties, such as RIE-lag, Si recess,etch stop, and breakdown of gate oxide, with afurther shrinkage of design rule to sub-nm.
According to ITRS roadmap in 2010, contact holewith the aspect-ratio of more than 20 and the size ofa few ten of nanometers is required for DRAM
device. A local charge accumulation caused by acharge separation inside the hole, i.e. an electron
shading effect, during SiO2 etching is classified as
one of the origin of plasma-induced damages (PID).
Reactive ion etching (RIE) of SiO2 using
fluorocarbon gas chemistry proceeds under thecompetition of surface protection by the depositionof neutral radicals (CxFy) and chemical sputtering
by energetic ions. Under a practical condition,etched surface is steadily covered with polymer
layer made of CF radicals. At the same time,sidewall is protected against the energetic ions bypolymer deposition. Therefore, the polymer film on
the sidewall with finite conductivity has big
influence on charge accumulation, resulting in thecharacteristics of SiO2 etching.
In this study, charging voltage accumulated in
the hole is investigated in terms of surface
conduction at the sidewall by using experimental
and numerical methods in order to estimate thesurface conductivity. Then, the charging voltage isalso calculated with a gate electrode taking atunneling current into account.
2. Methodologies
Charging voltage measurement system embeddedin a two-frequency capacitively coupled plasma(2f-CCP) chamber is shown in Fig. 1. Two types ofchips, a hole-patterned SiO2 chip and a blanket Sichip, are set on the electrode biased by the lowfrequency (LF: 500 kHz) source in order to measure
the bottom potential of both chips by using a pair ofhigh-voltage probes. A powered electrode driven byvery high frequency (VHF: 100 MHz) source islocated at the opposite of the LF source. The
difference of the bottom potential between twochips was defined as the charging voltage.

LF

Patterned
SiO2 chip

500 kHz

VHF

V

100 MHz
V-probe

Si chipFig. 1: Schematic of the arrangement of patterned SiO2 and flat
Si chips for measurement of the bottom charging voltage.

Temporal evolution of the local surface potential
inside the geometrically fixed structure was traced
by a particle simulation with Poisson’s equation as
a function of aspect-ratio,,
where V is the potential, np and ne are the number
density of positive ions and electrons, respectively.
Two-dimensional (x, z) trench structure withperiodic boundary was considered in a SiO2 layer
on a grounded Si substrate. The details of thecharging simulation can be referred elsewhere [3].

through a thin gate oxide (~ nm). Gate oxide
voltage Vox gives the complex behavior as shown inFig. 3. When the etching proceeds and the
aspect-ratio of the hole increases, Vch linearly
increases and Vox keeps almost constant. On theother hand, under the condition of aspect-ratio > 7,
Vch drastically decreases and Vox gradually
increases due to the contribution of the tunnelingcurrent.

3. Results and Discussion
The comparison of the charging voltages
obtained from the experiment and the simulation isshown in Fig. ○ as a function of voltage
amplitude of the biased LF electrode, V0. In theexperimental result (Aspect Ratio = 5), the charging
voltage increases almost linearly with V0, and thensaturates to the value of ~ 30 V. On the other hand,the simulated result simply shows a linear increase
with increasing V0, and finally approaches toseveral hundred of volts. The difference of bothcharging voltages V can be explained by thesurface conduction current on the sidewall as apossible mechanism for relaxing the charge buildup
at the bottom of the patterned SiO2 chip. When thesurface conductivity  was taken to be 1.0 x 10-8
-1cm-1, the charging voltage at V0 = 300 V and AR= 5 reduced to 48 V, as also shown in Fig. 2 (◆).
This indicates that the optimal value of the surface
conduction current Je can be determined bycomparing the experimental and numerical resultsby controlling  as V ~ 0.
500
150Charging voltage (V)Charging voltage (V)AR = 10400300100
Sim. (AR = 5)

V50Exp. (AR = 5)0100

AR = 5200

AR = 3

=010000

Bias amplitude (V)200 = 10-80500

Sim.
Exp. (AR = 5)
1000

1500

Bias amplitude (V)Fig. 2: Charging voltage as functions of voltage amplitude of
the biased electrode and aspect ratio of the patterned SiO2 chip.
Dotted line: experimental, solid lines: simulation.

Furthermore, we investigate the influence of theunderlying gate structure on the charging voltage
Vch by considering the tunneling current flowing

Fig. 3: Charging voltage at the bottom of the hole Vch and gateoxide voltage Vox as a function of aspect-ratio (right side).

Acknowledgments
This work was supported in part by aGrant-in-Aid for the Global COE Program (C12) inHigh-Level Global Cooperation for Leading-Edge
Platform on Access Space from the Ministry ofMEXT in Japan.
References[1] T. Ohmori and T. Makabe: Appl. Surf. Sci. 254(2008) 3696.
[2] J. Matsui, T. Makabe, et al: J. Phy. D 34 (2001)
2950.
[3] T. Yagisawa et al., Proc. 63rd GEC, (2010).