C‑V Characterization of MOS Capacitors Using
the 4200A-SCS Parameter Analyzer––
APPLICATION NOTEC‑V Characterization of MOS Capacitors Using
the 4200A-SCS Parameter Analyzer

Introduction

APPLICATION NOTE

Maintaining the quality and reliability of gate oxides ofOverview of C-V Measurement
Technique

MOS structures is a critical task in a semiconductor fab.

By definition, capacitance is the change in charge (Q) in a

Capacitance-voltage (C‑V) measurements are commonly

device that occurs when it also has a change in voltage (V):used in studying gate-oxide quality in detail. TheseC≡

measurements are made on a two-terminal device calleda MOS capacitor (MOS cap), which is basically a MOSFET∆Q∆V

without a source and drain. C‑V test results offer a wealth of

One general practical way to implement this is to apply adevice and process information, including bulk and interface

small AC voltage signal (millivolt range) to the device undercharges. Many MOS device parameters, such as oxide

test, and then measure the resulting current. Integrate

thickness, flatband voltage, threshold voltage, etc., can also

the current over time to derive Q and then calculate C

be extracted from the C‑V data.

from Q and V.

Using a tool such as the Keithley 4200A-SCS equipped

C-V measurements in a semiconductor device are madewith the 4210-CVU Integrated C-V Option for making C-V

using two simultaneous voltage sources: an applied AC

measurements on MOS capacitors can simplify testing andvoltage signal (dVac) and a DC voltage (Vdc) that is swept inanalysis. The 4200A-SCS is an integrated measurement

time, as illustrated in Figure 1.

system that can include instruments for both I-V andVdc

C-V measurements, as well as software, graphics, andmathematical analysis capabilities. The software incorporates
extracting common C-V parameters.
This application note discusses how to use a Keithley

VoltageC-V tests, which include a variety of complex formulas fordVac

4200A-SCS Parameter Analyzer equipped with the 4210CVU Integrated C-V Option to make C‑V measurementson MOS capacitors. It also addresses the basic principlesof MOS caps, performing C‑V measurements on MOS
capacitors, extracting common C‑V parameters, andmeasurement techniques. The Keithley Clarius softwarethat controls the 4200A-SCS incorporates many tests andTime

Figure 1. AC and DC voltage of C-V Sweep Measurement

projects specific to C-V testing. Each project is paired with

The magnitude and frequency of the AC voltage are fixed; thethe formulas necessary to extract common C-V parameters,

magnitude of the DC voltage is swept in time. The purpose

such as oxide capacitance, oxide thickness, doping density,of the DC voltage bias is to allow sampling of the material atdepletion depth, Debye length, flatband capacitance,

different depths in the device. The AC voltage bias provides

flatband voltage, bulk potential, threshold voltage, metal-

the small-signal bias so the capacitance measurement cansemiconductor work function difference, and effective oxide

be performed at a given depth in the device.

charge. This completeness is in sharp contrast to othercommercially available C-V solutions, which typically require
the user to research and enter the correct formula for eachparameter ­manually.

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C‑V Characterization of MOS Capacitors Using the4200A-SCS Parameter Analyzer

Basic Principles of MOS Capacitors
Figure 2 illustrates the construction of a MOS capacitor.
Essentially, the MOS capacitor is just an oxide placed
between a semiconductor and a metal gate. The
semiconductor and the metal gate are the two plates of thecapacitor. The oxide functions as the dielectric. The area ofthe metal gate defines the area of the capacitor.

Metal Gate
Metal
Oxide
Semiconductor

APPLICATION NOTE

The three modes of operation, accumulation, depletion
and inversion, will now be discussed for the case of ap‑type semiconductor, then briefly discussed for an n‑typesemiconductor at the end of this section.

Accumulation Region
With no voltage applied, a p‑type semiconductor has
holes, or majority carriers, in the valence band. When anegative voltage is applied between the metal gate andthe semiconductor, more holes will appear in the valenceband at the oxide-semiconductor interface. This is because
the negative charge of the metal causes an equal net
positive charge to accumulate at the interface between
the semiconductor and the oxide. This state of the p‑typesemiconductor is called accumulation.

Back Contact

For a p‑type MOS capacitor, the oxide capacitance ismeasured in the strong accumulation region. This is where

Figure 2. MOS capacitor

The most important property of the MOS capacitor is that its
capacitance changes with an applied DC voltage. As a result,the modes of operation of the MOS capacitor change as afunction of the applied voltage. Figure 3 illustrates a highfrequency C‑V curve for a p‑type semiconductor substrate.
As a DC sweep voltage is applied to the gate, it causes
the device to pass through accumulation, depletion, andinversion regions.

the voltage is negative enough that the capacitance isessentially constant and the C‑V curve is almost flat. This iswhere the oxide thickness can also be extracted from theoxide capacitance. However, for a very thin oxide, the slopeof the C‑V curve doesn’t flatten in accumulation and themeasured oxide capacitance differs from the actual oxide
capacitance.

Depletion Region
When a positive voltage is applied between the gate andthe semiconductor, the majority carriers are replaced
from the semiconductor-oxide interface. This state of thesemiconductor is called depletion because the surface ofthe semiconductor is depleted of majority carriers. This areaof the semiconductor acts as a dielectric because it canno longer contain or conduct charge. In effect, it becomesan insulator.
The total measured capacitance now becomes the oxide
capacitance and the depletion layer capacitance in series,
and as a result, the measured capacitance decreases.
This decrease in capacitance is illustrated in Figure 3
in the depletion region. As a gate voltage increases, thedepletion region moves away from the gate, increasing theeffective thickness of the dielectric between the gate and thesubstrate, thereby reducing the c­ apacitance.

Figure 3. C‑V curve of a p‑type MOS capacitor measured withthe 4210-CVU

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C‑V Characterization of MOS Capacitors Using
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APPLICATION NOTE

Inversion Regionn-type Substrate

As the gate voltage of a p‑type MOS-C increases beyond

The C‑V curve for an n‑type MOS capacitor is analogous

the threshold voltage, dynamic carrier generation andto a p‑type curve, except that (1) the majority carriers

recombination move toward net carrier generation. The

are electrons instead of holes; (2) the n‑type C‑V curve

positive gate voltage generates electron‑hole pairs andis essentially a mirror image of the p‑type curve; (3)attracts electrons (the minority carriers) toward the gate.

accumulation occurs by applying a positive voltage to the

Again, because the oxide is a good insulator, these minority

gate; and (4) the inversion region occurs at negative voltage.

carriers accumulate at the substrate-to-oxide/well-to-oxideinterface. The accumulated minority-carrier layer is called
the inversion layer because the carrier polarity is inverted.
Above a certain positive gate voltage, most available minority
carriers are in the inversion layer, and further gatevoltage increases do not further deplete the semiconductor.

Performing C‑V Measurements with the4210-CVU
To simplify testing, a project has been created for the4200A-SCS that makes C‑V measurements on a MOS

That is, the depletion region reaches a maximum depth.

capacitor and extracts common measurement parameters

Once the depletion region reaches a maximum depth,

etc. The MOS Capacitor C-V Project (cvu-moscap) is included

the capacitance that is measured by the high frequency

with all 4200A-SCS systems in the Clarius application.

capacitance meter is the oxide capacitance in series with the

Figure 4 is a screen shot of the project, which has threemaximum depletion capacitance. This capacitance is often

tests that generate a C‑V sweep (moscap-cvsweep), a 1/C2

referred to as minimum capacitance. The C‑V curve slope is

vs. Gate Voltage curve (moscap-c-2vsv), and a doping profile

almost flat.

(moscap-dopingprofile). Figure 4 also illustrates a C-V sweep

NOTE: The measured inversion-region capacitance at the
maximum depletion depth depends on the measurement
frequency. Therefore, C‑V curves measured at different
frequencies may have different appearances. Generally, suchdifferences are more significant at lower frequencies and lesssignificant at higher frequencies.

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such as oxide thickness, flatband voltage, threshold voltage,

generated with the moscap-cvsweep test. All of the extracted
C‑V parameters in these test modules are defined in the next
section of this application note.

C‑V Characterization of MOS Capacitors Using the4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 4. C-V sweep created with moscap-cvsweep test for the 4200A.

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C‑V Characterization of MOS Capacitors Using
the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

MOS Capacitor C-V Sweep (moscap-cvsweep) Test
This test performs a capacitance measurement at each step of a user-configured linear voltage sweep. A C‑V graph is
generated from the acquired data, and several device parameters are calculated using the Formulator, which is a tool in the4200A-SCS’s software that provides a variety of computational functions, common mathematical operators, and common
constants. Figure 5 shows the window of the Formulator. These derived parameters are listed in the Analyze view of the test.

Figure 5. Formulator window with parameters derived

MOS Capacitor I/C2 vs. Gate Voltage Sweep(moscap-c-2vsv) Test
This test performs a C‑V sweep and displays the capacitance(1/C2) as a function of the gate voltage (VG). This sweep canyield important information about doping profile because thesubstrate doping concentration (NSUB) is inversely related to
the reciprocal of the slope of the 1/C2 vs. VG curve. A positive
slope indicates acceptors and a negative slope indicatesdonors. The substrate doping concentration is extracted fromthe slope of the 1/C2 curve and is displayed on the graph.
Figure 6 shows the results of executing this test module.

Figure 6. 1/C2 vs. gate voltage plot generated with 4210-CVU

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C‑V Characterization of MOS Capacitors Using the4200A-SCS Parameter Analyzer

APPLICATION NOTE

Measurement Optimization

MOS Capacitor Doping Profile(moscap-dopingprofile) Test
This test performs a doping profile, which is a plot of thedoping concentration vs. depletion depth. The difference incapacitance at each step of the gate voltage is proportional
to the doping concentration. The depletion depth iscomputed from the high frequency capacitance and oxide
capacitance at each measured value of the gate voltage. The
results are plotted on the graph as shown in Figure 7.

Successful measurements require compensating for stray
capacitance, measuring at equilibrium conditions, andcompensating for series resistance.

Offset Correction for Stray Capacitance
C‑V measurements on a MOS capacitor are typically
performed on a wafer using a prober. The 4210-CVU isdesigned to be connected to the prober via interconnect
cables and adaptors and may possibly be routed through aswitch matrix. This cabling and switch matrix will add stray
capacitance to the measurements.
To correct for stray capacitance, the Clarius software has abuilt-in tool for offset correction, which is a two-part process:the corrections for open and/or short are performed first, andthen they can be enabled within a test.
To perform the corrections, select Tools and select CVU
Connection Compensation. For an Open correction, selectMeasure Open. Probes must be up during the correction.
Open is typically used for high impedance measurements(<10pF or >1MΩ).

Figure 7. Doping profile extracted from C‑V data taken with 4210-CVU

For a Short correction, select Measure Short. Short the probe
to the chuck. A short correction is generally performed forConnections to the 4210-CVU

low impedance measurements (>10nF or <10Ω).

To make a C‑V measurement, a MOS cap is connected to theAfter the corrections are performed, they must be enabled in

4210-CVU as shown in Figure 8. In the test, both the 4210-

the test. To enable corrections, select the CVU Open and/or

CVU ammeter and the DC voltage appear at the HCUR/HPOT

Short checkboxes in the Terminal Settings pane (Figure 9).

terminals. See the next section, “Measurement Optimization,”for further information on connecting the CVU to the device
on a wafer.
HICUR
HIPOT
4210-CVU

Gate

Wafer

Bulk
LPOT
LCUR
Figure 8. Basic configuration to test MOS capacitor with 4210-CVU

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C‑V Characterization of MOS Capacitors Using
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APPLICATION NOTE

Figure 9. CVU compensation window

Measuring at Equilibrium Conditions

Hold and Delay Times When Sweeping from Inversion →A MOS capacitor takes time to become fully charged after a

Accumulation. When the C‑V sweep starts in the inversion

voltage step is applied. C‑V measurement data should only

region and the starting voltage is initially applied, a MOS

be recorded after the device is fully charged. This condition

capacitor is driven into deep depletion. Thereafter, if theis called the equilibrium condition. Therefore, to allow thestarting voltage is maintained, the initial high frequency C‑V

MOS capacitor to reach equilibrium: (1) allow a sufficient

curve climbs toward and ultimately stabilizes to the minimum

Hold Time in the Test Settings panel to enable the MOS

capacitance at equilibrium. However, if the initial Hold Timecapacitor to charge up while applying a “PreSoak” voltage,is too short, the MOS capacitor cannot adequately recoverand (2) allow a sufficient Sweep Delay Time before recordingfrom deep depletion, and the measured capacitance will be

the capacitance after each voltage step of a voltage sweep.

smaller than the minimum capacitance at equilibrium. Set the

The appropriate Hold and Delay Times are determined“PreSoak” voltage to the first voltage in the voltage sweep

experimentally by generating capacitance vs. time plots andand allow a sufficient Hold Time for the MOS capacitor toobserving the time for the capacitance to settle.

reach equilibrium.

Although C‑V curves swept from different directions may look

However, once the MOS capacitor has reached equilibrium

different, allowing adequate Hold and Delay Times minimizes

after applying the “PreSoak” voltage, an inversion →such differences. One way to determine sufficient Hold andaccumulation C‑V sweep may be performed with small delay

Delay Times is to generate a series of C‑V curves in bothtimes. This is possible because minority carriers recombine

directions. Change the Hold and Delay Times for each pairrelatively quickly as the gate voltage is reduced. Nonetheless,of inversion → accumulation and accumulation → inversion

if the Delay Time is too short, non-equilibrium occurs, and thecurves until the curves look essentially the same for both

capacitance in the inversion region is slightly higher than thesweep directions.

equilibrium value. This is illustrated by the upper dotted line in
Figure 10.

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C‑V Characterization of MOS Capacitors Using the4200A-SCS Parameter Analyzer

APPLICATION NOTE

a sudden voltage change when the sweep starts. During
biasing, if necessary, a short light pulse can be applied tothe sample to help generate minority carriers. However,before the sweep starts, all lights should be turned off.

C

All measurements should be performed in total darkness

Swept too fast

because the semiconductor material may be light sensitive.

Equilibrium
sweep

VGS

During the sweep, the Delay Time should be chosen to
create the optimal balance between measurement speed
and measurement integrity, which requires adequate
equilibration time.

Figure 10. Effects of performing a C‑V sweep too quickly

Compensating for series resistance

Hold and Delay Times When Sweeping from
Accumulation → Inversion. When the C‑V sweep starts inthe accumulation region, the effects of Hold and Delay Timesin the accumulation and depletion regions are fairly subtle.
However, in the inversion region, if the Delay Time is too small(i.e., the sweep time is too fast), there’s not enough time for
the MOS capacitor to generate minority carriers to form an
inversion layer. On the high frequency C‑V curve, the MOS
capacitor never achieves equilibrium and eventually becomes
deeply depleted. The measured capacitance values fall well
below the equilibrium minimum value. The lower dotted line in
Figure 10 illustrates this phenomenon.

After generating a C‑V curve, it may be necessary tocompensate for series resistance in measurements. The
series resistance (RSERIES) can be attributed to either thesubstrate (well) or the backside of the wafer. For wafers
typically produced in fabs, the substrate bulk resistanceis fairly small (<10Ω) and has negligible impact on C‑V
measurements. However, if the backside of the wafer is used
as an electrical contact, the series resistance due to oxides
can significantly distort a measured C‑V curve. Without series
compensation, the measured capacitance can be lower thanthe expected capacitance, and C‑V curves can be distorted.
Tests for this project compensate for series resistance

Using the preferred sequence. Generating a C‑V curve byusing the simplified three-element shown in Figure 12.

sweeping from inversion to accumulation is faster and moreIn this model, COX is the oxide capacitance and CA is thecontrollable than sweeping from accumulation to inversion.

capacitance of the accumulation layer. The series resistance

Figure 11 illustrates a preferred measurement sequence.

is represented by RSERIES.

BiasVoltage

Bias
Hold Time

Start Voltage
Delay
Time

0V

Light
Pulse

Figure 11. Preferred C‑V measurement Sequence

The device is first biased at the “PreSoak” voltage forthe specified Hold Time. The bias or “PreSoak” voltage
should be the same as the sweep start voltage to avoid

CA
COX

COX

Simplifies to

RSERIES
Equivalent 3-element
model of MOS capacitor
in strong accumulation

RSERIES

Simplified model used
to determine RSERIES

Figure 12. Simplified model to determine series resistance

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C‑V Characterization of MOS Capacitors Using
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APPLICATION NOTE

The corrected capacitance (CADJ) and corrected conductance

while biasing the DUT (device under test) in the accumulation(GADJ) are calculated from the following formulas [1]:region as follows:(G + (2pfC) )CCADJ = __________________
		aR2 + (2pfC)22
G
		 _____
2pfC
		RS = __________________
2
			G
1+ ______
G		 2pfC

2

2(G2 + (2pfC)2)aR
GADJ = ___________________
		aR2 + (2pfC)2
where:
aR = G – (G2 + (2pfC)2)RSCADJ = series resistance compensated parallel capacitanceC = measured parallel capacitance
GADJ = series resistance compensated conductanceG = measured conductance( )[ ( )]

where:
RS = series resistanceG = measured conductanceC = measured parallel capacitance (in strong accumulation)f = test frequency
NOTE: The preceding equations for compensating for series
resistance require that the 4210-CVU be using the parallelf = test frequency

model (Cp-Gp).

RS = series resistanceFor this project, these formulas have been added into the
Formulator so the capacitance and conductance can be

The series resistance (RS) may be calculated from thecapacitance and conductance values that are measured

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automatically compensated for the series resistance.

C‑V Characterization of MOS Capacitors Using the4200A-SCS Parameter Analyzer

APPLICATION NOTE

Extracting MOS Device Parameters From C‑V Measurements
This section describes the device parameters that are extracted from the C‑V data taken in the three test modules in the MOS
Capacitor C-V Project. The parameters are derived in the Formulator and the calculated values appear in the Sheet tab in the
Analyze view of each test as shown in Figure 13.

Figure 13. Extracted C‑V parameters shown in the Sheet

Oxide thickness
For a relatively thick oxide (>50Å), extracting the oxide
thickness is fairly simple. The oxide capacitance (COX ) is thewhere:

high frequency capacitance when the device is biased for

TOX = oxide thickness (nm)strong accumulation. In the strong accumulation region, theA = gate area (cm2)

MOS-C acts like a parallel-plate capacitor, and the oxide
thickness (TOX ) may be calculated from COX and the gate area
using the following equation:
		 ___________(107)AεOXTOX(nm) =		 COXεOX = permittivity of the oxide material (F/cm)
COX = oxide capacitance (F)107 = units conversion from cm to nm

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C‑V Characterization of MOS Capacitors Using
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APPLICATION NOTE

Flatband capacitance and flatband voltage

l = extrinsic Debye length, which is calculated as follows:

Application of a certain gate voltage, the flatband voltage

		εSkT 1/2 –2
l = ______
		 (10 )q2 N		(VFB), results in the disappearance of band bending. At thispoint, known as the flatband condition, the semiconductor
band is said to become flat. Because the band is flat, thesurface potential is zero (with the reference potential being
taken as the bulk potential deep in the semiconductor).

()

where:
l = extrinsic Debye length
εS = permittivity of the substrate material (F/cm)

Flatband voltage and its shift are widely used to extract otherdevice parameters, such as oxide charges.

kT = thermal energy at room temperature (293K)(4.046 × 10 –21J)

VFB can be identified from the C‑V curve. One way is to use
the flatband capacitance method. For this method, the ideal
value of the flatband capacitance (CFB) is calculated fromthe oxide capacitance and the Debye length. The conceptof Debye length is introduced later in this section. Once thevalue of CFB is known, the value of VFB can be obtained fromthe C‑V curve data, by interpolating between the closest
gate-to-substrate (VGS) values [2].

q = electron charge (1.60219 × 10 –19C)
NX = N at 90% WMAX or N90W (refer to Nicollian andBrews; see References) or, when input by the user, NX = NAor NX = ND
10 –2 = units conversion from cm to m
The extrinsic Debye length is an idea borrowed from plasma

The Debye length parameter (l) must also be calculated tophysics. In semiconductors, majority carriers can movederive the flatband voltage and capacitance. Based on thefreely. The motion is similar to a plasma. Any electrical

doping profile, the l calculation requires one of the followinginteraction has a limited range. The Debye length is used todoping concentrations: N at 90% of WMAX (refer to Nicollian

represent this i­nteraction range. Essentially, the Debye lengthand Brews), a user-supplied NA (bulk doping concentration

indicates how far an electrical event can be sensed within a

for a p‑type, acceptor, material), or a user-supplied ND (bulksemiconductor.

doping concentration for an n‑type, donor, material).
NOTE: The flatband capacitance method is invalid when theinterface trap density (DIT ) becomes very large (1012–1013 or
greater). However, the method should give satisfactory results
for most users. When dealing with high DIT values, consult theappropriate literature for a more suitable method.

Threshold voltage
The turn-on region for a MOSFET corresponds to theinversion region on its C‑V plot. When a MOSFET is turned
on, the channel formed corresponds to strong generation of
inversion charges. It is these inversion charges that conduct
current. When a source and drain are added to a MOS-C

The flatband capacitance is calculated as follows:

to form a MOSFET, a p‑type MOS-C becomes an n‑type		
COX (εSA/l) (102)
CFB = ______________________
COX + (εSA/l) (102)MOSFET, also called an n‑channel MOSFET. Conversely, an

where:
CFB = flatband capacitance (F)COX = oxide capacitance (F)εS = permittivity of the substrate material (F/cm)

n‑type MOS-C becomes a p‑channel MOSFET.
The threshold voltage (V TH) is the point on the C‑V curve
where the surface potential (φS) equals twice the bulk
potential (φB). This curve point corresponds to the onset ofstrong inversion. For an enhancement-mode MOSFET, V TH
corresponds to the point where the device begins to conduct.
The physical meaning of the threshold voltage is the same for

A = gate area (cm2)both a MOS-C C‑V curve and a MOSFET I-V curve. However,102 = units conversion from m to cm

slightly different due to the particular method used to extract

in practice, the numeric V TH value for a MOSFET may be
the threshold voltage.

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C‑V Characterization of MOS Capacitors Using the4200A-SCS Parameter Analyzer

APPLICATION NOTE

The threshold voltage of a MOS capacitor can be calculated

effective oxide charge [3][4]. The work function represents

as follows:

the difference in work necessary to remove an electron fromA
COX

VTH = VF B ±the gate and from the substrate. The work function is derived
4 εS q NBULK φ B + 2 φ B

as follows:[]

where:		EBG
WMS = WM – WS + _____ – φB		2

V TH = threshold voltage (V)where:VFB = flatband potential (V)WMS = work function

A = gate area (cm2)

WM = metal work function (V) *COX = oxide capacitance (F)WS = substrate material work function, electron affinity (V) *εS = permittivity of the substrate material (F/cm)

EBG = substrate material bandgap (V) *q = electron charge (1.60219 × 10 –19C)

φB = bulk potential (V) (Note: The Formulator name for

NBULK = bulk doping (cm –3) (Note: The Formulator name for

φB is PHIB)NBULK is N90W.)*The values for WM, WS, and EBG are listed in the Formulator

φB = bulk potential (V) (Note: The Formulator name forthe type of materials.

as constants. The user can change the values depending on

φB is PHIB.)The following example calculates the work function for silicon,

The bulk potential is calculated as follows:()

silicon dioxide, and aluminum:[		kT		 NBULKφB = – ___ ln _______ (DopeType)		q		 Ni		
1.12
WMS = 4.1 – 4.15 + _____ – φB		2

where:

Therefore,
WMS = –0.61 + φB

φB = bulk potential (V) (Note: The Formulator name for
φB is PHIB.)k = Boltzmann’s constant (1.3807 × 10 –23J/K)
T = test temperature (K)

]

and

(

)

		
kT		 NBULKWMS = –0.61 – ___ ln _______
		q		 Ni(DopeType)where:

q = electron charge (1.60219 × 10 –19C)

WMS = work function

NBULK = Bulk doping (cm –3) (Note: The Formulator name fork = Boltzmann’s constant (1.3807 × 10 –23J/K)

NBULK is called N90W.)
Ni = Intrinsic carrier concentration (1.45 × 1010cm –3)

T = test temperature (K)q = electron charge (1.60219 × 10 –19C)

DopeType = +1 for p‑type materials and –1 for
n‑type materials

NBULK = bulk doping (cm –3)

Metal-semiconductor work function difference

DopeType = +1 for p‑type materials and –1 for

The metal-semiconductor work function difference (WMS) is

n‑type materials

commonly referred to as the work function. It contributes

For example, for an MOS capacitor with an aluminum gate

to the shift in VFB from the ideal zero value, along with theand p‑type silicon (NBULK = 1016cm –3), WMS = –0.95V. Also,

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C‑V Characterization of MOS Capacitors Using
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for the same gate and n‑type silicon (NBULK = 1016cm –3),
WMS = –0.27V. Because the supply voltages of modern

APPLICATION NOTEWMS = metal–semiconductor work function (V)CMOS devices are lower than those of earlier devices and

VFB = flatband potential (V)because aluminum reacts with silicon dioxide, heavily doped

A = gate area (cm2)polysilicon is often used as the gate material. The goal is toachieve a minimal work-function difference between the gate

For example, assume a 0.01cm2, 50pF, p‑type MOS-C with aand the semiconductor, while maintaining the conductive

flatband voltage of –5.95V; its NBULK of 1016cm –3 corresponds

properties of the gate.

to a WMS of –0.95 V. For this example, QEFF can be calculated
to be 2.5 × 10 –8C/cm2, which in turn causes the threshold

Effective and total bulk oxide charge

voltage to shift ~5V in the negative direction. Note that in

The effective oxide charge (QEFF) represents the sum of oxide

most cases where the bulk charges are positive, there isfixed charge (QF), mobile ionic charge (QM), and oxide trappedcharge (QOT):QEFF = QF + QM + QOT
QEFF is distinguished from interface trapped charge (QIT), inthat QIT varies with gate bias and QEFF does not [5] [6]. Simple
measurements of oxide charge using C‑V measurements do
not distinguish the three components of QEFF. These threecomponents can be distinguished from one another bytemperature cycling [7]. Also, because the charge profile in
the oxide is not known, the quantity (QEFF) should be used asa relative, not an absolute, measure of charge. It assumes
that the charge is located in a sheet at the silicon–silicona shift toward negative gate voltages. The effective oxidecharge concentration (NEFF) is computed from effective oxidecharge (QEFF) and the electron charge as follows:		Q
EFF
NEFF = ______
		q
where:NEFF = effective oxide charge density (cm –2)
QEFF = effective oxide charge (C)q = electron charge (1.60219 × 10 –19C)

Substrate doping concentration

dioxide interface.

The substrate doping concentration (N) is related to the

From Nicollian and Brews, Eq. 10.10, we have:concentration is calculated and displayed below the graph in		
QEFF
VFB – WMS = – ______
		COX

the moscap-c-2vsv test as follows:

reciprocal of the slope of the 1/C2 vs. VG curve. The doping

NSUB =

where:VFB = flatband potential (V)2qεS A2∆1/ C 2∆VG

WMS = metal-semiconductor work function (V)where:QEFF = effective oxide charge (C)NSUB = substrate doping concentration

COX = oxide capacitance (F)q = electron charge (1.60219 × 10 –19C)

Note that COX here is per unit of area. So that:A = gate area (cm2)		C
OX(WMS –VFB)
QEFF = __________________		A

εS = permittivity of the substrate material (F/cm)

where:

VG = gate voltage (V)QEFF = effective oxide charge (C)C = measured capacitance (F)COX = oxide capacitance (F)14 | WWW.TEK.COM

C‑V Characterization of MOS Capacitors Using the4200A-SCS Parameter Analyzer

APPLICATION NOTE

Doping concentration vs. depth (doping profile)

Summary

The doping profile of the device is derived from the C‑V curve

When equipped with the 4210-CVU option, the 4200A-SCS isbased on the definition of the differential capacitance as thedifferential change in depletion region charges produced by adifferential change in gate voltage [8].
The standard doping concentration (N) vs. depth (w)analysis discussed here does not compensate for the onsetof accumulation, and it is accurate only in depletion. Thismethod becomes inaccurate when the depth is less than two
Debye lengths. The doping concentration used in the doping
profile is calculated as:a very useful tool for making both C-V and I-V measurementson MOS capacitors and deriving many of the common MOS
parameters. In addition to the MOS Capacitor C-V Project,
the 4200A-SCS includes other projects specifically for testing
MOS capacitors. The MOS Capacitor Lifetime Test Projectis used for determining generation velocity and lifetime
testing (Zerbst plot) of MOS capacitors. The MOS Capacitor
Mobile Ion Project determines the mobile charge of a MOS
cap using the bias-temperature stress method. In addition
to making C-V measurements, the SMUs can make I-V–2N=d (1/C 2 )qεS A2dV

measurements on MOS caps, including leakage current andbreakdown testing.

The moscap-dopingprofile test computes the depletion

References

depth (w) from the high frequency capacitance and oxide

1.

Technology (New York: Wiley, 1982), 224.

capacitance at each measured value of the gate voltage(VG) [9]. The Formulator computes each (w) element of thecalculated data array as shown:

(

)

		
1		 1
W = AεS __ – ___ (102)		 C		COX
where:

E. H. Nicollian and J. R. Brews, MOS Physics and2.

Ibid., 487–488

3.

Nicollian and Brews, 462–477.

4.

S.M. Sze, Physics of Semiconductor Devices, 2ndedition. (New York: Wiley, 1985), 395–402.

W = depth (m)5.

Nicollian and Brews, 424–429.

6.

Sze, 390–395.

7.

Nicollian and Brews, 429 (Figure 10.2).

8.

Nicollian and Brews, 380–389.

9.

Nicollian and Brews, 386.

A = the gate area (cm )2

C = the measured capacitance (F)εS = the permittivity of the substrate material (F/cm)
COX = the oxide capacitance (F)10 = units conversion from cm to m
2

Once the doping concentration and depletion depth

Additional Suggested Reading

are derived, a doping profile can be plotted. This isD.K. Schroder, Semiconductor Material and Device

done in the Graph of the MOS Capacitor Doping Profile

Characterization, 2nd edition. (New York, Wiley, 1998).

(moscap-dopingprofile) test.

WWW.TEK.COM | 15

Using 4225-RPM Remote Amplifier/Switch to Switch
Automatically Between DC I-V, C-V, and Pulsed I-V Measurements

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