Advanced Packaging Technologies for Heterogeneous Integration (HI)Ravi Mahajan, Fellow; Sandeep Sane, Principal Engineer
Intel Corporation
Acknowledgments: Kemal Aygun, Kaladhar Radhakrishnan, Debendra Mallik, Gaurang Choksi, Rahul Manepalli, Chris Baldwin, Sergey Shumarayev, Ram Viswanath,
Pat Stover, Wilfred Gomes, Gans Ganesan, Sriram Srinivasan, Ahmet Durgun, CM Jha, Weihua Tang, Bill Chen (ASE), Subu Iyer (UCLA), Bill Bottoms (3MTS), Samantika
Sury, Robert Wisniewski, Dipankar Das, Pradeep Dubey

Executive Summary
Part 1 : The Package as a Compact HI Platform : Some Key Elements• On-Package Interconnects• High Bandwidth Signaling• Power Delivery• Thermal Management• Assembly Processes• Materials & Design Tools

Part 2 : Product implementations using Advanced Packaging Technologies

2Outline
•
•
•
•
•
•

Introduction – The Package as a Compact HI Platform
On Package Interconnects & High Bandwidth Signaling
Power Delivery Architectures
Thermal Management
Assembly Process, Materials and Design Tools
Summary3

Increased Interest in HI is Driven by
Need to Mix and Match ofDiverse IP Optimized on
Different processes
Need for Proximate Memory
with a High BW Low PowerInterfaceEscape from Reticle Limits

Additionally, Yield Resiliency and Time to Market Advantages Make On-Package HI Attractive
4

The Package is a Compact HI Platform For Several Interesting Use
Cases

Sources: Intel Architecture Day (2021) & ERI Summit (2020). The CHIPS work is supported by the DARPA MTO office (DARPA CHIPS Program))
5

The Package as a HI Platform – Key Focus Areas
Power-efficient, High
Bandwidth OnPackage IO links

Enable a diversity
of off-package IO
protocols

Manage increasing
cooling demands

Support complex
power delivery
architectures

Meet a broad
spectrum of
reliability
requirements fordifferent market
segments andapplications

Provide costeffective, highprecision quick
turn assembly

Deliver noise
isolation for single
ended anddifferential signals

Meet diverse
application
functionality
ranging from highperformanceservers to flexible,
wearableelectronics

6

On-Package Interconnects & High Bandwidth Signaling
Power-efficient, High
Bandwidth OnPackage IO links

Enable a diversity
of off-package IO
protocols

Manage increasing
cooling demands

Support complex
power delivery
architectures

Meet a broad
spectrum of
reliability
requirements fordifferent market
segments andapplications

Provide costeffective, highprecision quick
turn assembly

Deliver noise
isolation for single
ended anddifferential signals

Meet diverse
application
functionality
ranging from highperformanceservers to flexible,
wearableelectronics

7

High Density Interconnects : Physical Metrics• Wiring Density increases Require Wire (aka IO)
Width, Space & Pad reduction (Zero Pad Ideal)• Bump Density Increases Require Bump Pitch Shrinks

R. Mahajan et al., "Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect," 2016 ECTC
8

Current State of Advanced Packaging (Intel Centric View)
EMIB

Foveros

EMIB-Foveros

9Planar Interconnects : MCP Landscape

Focus : Increased Interconnect Density + Improved Power Efficiency
for Increased BW
10Vertical Interconnects : MCP LandscapeTransition from Solder Based Interconnects to Cu-Cu interconnects needed with shrinking
Bump Pitch**Li et al. “Scaling Solder Micro-Bump Interconnect Down to 10 μm Pitch for Advanced 3D IC Packages” ECTC 2021
11

Blending 2D and 3D• Architecture for >> reticle sized
die + High-Density Bridge links• Increased Partitioning
Opportunities in X, Y and Z

12

I/O Bandwidth & Speed Scaling Trends

Reproduced with permission from Ethernet Alliance•

Growing Network & Memory (BW + Speed)
Demand•As peak FLOPS grow BW will need to keep up•

BW Demand poses significant challenge for thephysical and signaling characteristics of the
package interconnect13

On-Package Bandwidth Density Scaling

Enable high bandwidth density connection between dies on an ‘advanced package’with simple I/O circuits and low power consumption with limited reach
R. Mahajan et al., "Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect," 2016 ECTC
14

Interconnect Scaling to Enable Bandwidth Scaling• Peripheral Interconnects for Solder Based 2D Architectures
Generations

1

2

3

4

5

Raw Bandwidth Density (GBps/mm)
Minimum Bump Pitch (µm)
IO/mm
Package Technology
IO/mm2Signaling Speed
Gbps

125
55
500
331
2

250
50
667
400
3

500
40
1000
625
4

1000
35
1500
816
5.33

2000
30
2000
1111
8

• Peripheral Interconnects for 2D Architectures with Aggressive pitch Scaling
Generations

1

2

3

4

5

Raw Bandwidth Density (GBps/mm)
Minimum Bump Pitch (µm)
IO/mm
Package Technology
IO/mm2Signaling Speed
Gbps

125
55
500
331
2

250
40
667
625
3

500
30
1000
1111
4

1000
20
1500
2500
5.33

2000
10
2000
10000
8

Source : Chapter 22 in IEEE Heterogeneous Integration Roadmap (https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html)
15

Interconnect Scaling to Enable Bandwidth Scaling• Area Interconnects for 3D Architectures
Generations

1

2

3

4

5

Raw Bandwidth Density (Gbps/mm2)

125

250

500

1000

2000

PackageTechnology

Minimum Bump Pitch
(µm)

40

30

20

15

10

IO/mm2

625

1111

2500

4444

10000

Gbps

1.6

1.8

1.6

1.8

1.6

Signaling Speed

Source : Chapter 22 in IEEE Heterogeneous Integration Roadmap (https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html)
16Power Delivery
Power-efficient, High
Bandwidth OnPackage IO links

Enable a diversity
of off-package IO
protocols

Manage increasing
cooling demands

Support complex
power delivery
architectures

Meet a broad
spectrum of
reliability
requirements fordifferent market
segments andapplications

Provide costeffective, highprecision quick
turn assembly

Deliver noise
isolation for single
ended anddifferential signals

Meet diverse
application
functionality
ranging from highperformanceservers to flexible,
wearableelectronics

17

The Evolution of Power Management• Historical Approach (1980s to early
2000s)• Frequency scaling → Faster (&leaky) transistors enable higher
frequency• Scale Vth & device dimensions• Increased leakage and active
power

Number of power rails has steadily gone up to improve power management• Shift to Multi-Core (mid 2000s)• Slow down Vth scaling & Process
improvements to control leakage• Slow down frequency scaling• Add more cores for performance18

FIVR – Fully Integrated Voltage Regulator
FIVR was introduced by Intel® on the 4th generation Core ™ Microprocessors
 Steps down the 1.8 V Vin to a range of output voltages (0.5 – 1.3V)
 The number of FIVR phases on a microprocessor can range from 50 to 300

A single MBVR converts the incoming platform power supply voltage to 1.8V

FIVR Implementation on Die & Package
19Efficiency on First Generation FIVRFirst generation of FIVR achieved an efficiency of 90% at full Vout (1.08 V)
 First generation FIVR ACI had a high Q-factor due to a large XY footprint and a 700um core

• Process scaling reduces core area → Shrinks the ACI XY
footprint• The push to thin and light devices has reduced thesubstrate core thickness hurting ACI performance20

Magnetic Inductor Arrays
The 10th generation Intel® Core™ microprocessors used a number of MIA modules for thedifferent voltage domains
 The use of magnetic inductors helps recover the loss of efficiency due to ACI area scaling

21

The Package as a HI Platform – Key Focus Areas
Power-efficient, High
Bandwidth OnPackage IO links

Enable a diversity
of off-package IO
protocols

Manage increasing
cooling demands

Support complex
power delivery
architectures

Meet a broad
spectrum of
reliability
requirements fordifferent market
segments andapplications

Provide costeffective, highprecision quick
turn assembly

Deliver noise
isolation for single
ended anddifferential signals

Meet diverse
application
functionality
ranging from highperformanceservers to flexible,
wearableelectronics

22

Intel 3D Heterogeneous Package Thermals

Key challenges:• Die-die thermal resistance, thermal cross-talk between neighboring die, and higher power density due to stacked
active die → The combined effect results in lower cooling capability for 3D packages compared to 2D packages.
How Intel manages Thermals :• Low resistance die-to-die thermal interfaces (Foveros Omni and Foveros Direct packages).
• Best in class metallic thermal interface material (TIM1) between die and integrated heat spreader (IHS).
• Thermally optimized Si floorplan and package architectures. Co-design of Si and Package for improved thermals.
23

Assembly Process, Materials and Design Considerations

Power-efficient, High
Bandwidth OnPackage IO links

Enable a diversity
of off-package IO
protocols

Manage increasing
cooling demands

Support complex
power delivery
architectures

Meet a broad
spectrum of
reliability
requirements fordifferent market
segments andapplications

Provide costeffective, highprecision quick
turn assembly

Deliver noise
isolation for single
ended anddifferential signals

Meet diverse
application
functionality
ranging from highperformanceservers to flexible,
wearableelectronics

24Assembly and Test Technology Development Scope

KGD

Tooling
solutions

Assembly TD Focus : High functionality, High Yield, High Quality & Reliability
25

Heterogeneous packaging: Challenges and opportunities
Better materials•••

UF/mold: Flow, Reliability, Warpage
Fluxes: joint quality/cleanability
Thermal interface materials•••

Bump Current carrying capability
HSIO and Power Delivery
Design co-optimization

EMIB

Passivation/bump compatibility
Design rule/ Design co-optimization•••

Die-Die, Die-Wafer, Die- Substrate
Improved alignment/ bump Coplanarity
Stacked die coplanarity

EMIB

External IP/die/pkg integration••

Fine pitch interconnect joint yield

Improved Electrical

EMIB

Advanced substrates•••

Improved bump coplanarity
Fine pitch/ Multi diameter bumping
High density routing

Acceptable Reliability•••

Temperature cycling
Electromigration
Temperature/humidity/Bias

Equipment/ Material/Process/ Design Co-optimization key toHeterogeneous Assembly & Packaging

26

Advanced Substrates: Challenges & Opportunities

Equipment/ Material Advances in Substrate Panel Processes key toHeterogeneous Integration

27

Design, Process & Materials Optimized for Performance,
Manufacturability & Cost

28

Summary•

Today there is Broad and Growing consensus that Heterogeneous Integration (HI) is a key enablerof performance moving forward.
•

On-Package Integration, using Advanced Packaging Architectures for Compact, Power Efficient, High
Bandwidth Platforms is a key HI Element•

Number of Innovative package architectures are available today to facilitate power efficient, high bandwidth
die-die interconnects on package → There is a roadmap to scale these interconnects in all three dimensions•

Delivering a clean power supply is important to optimize microprocessor performance• The increase in power rails & overall power levels introduces new power delivery challenges• Development of high efficiency, high density, high voltage IVRs will be critical to meet the requirements offuture high-performance microprocessors•

Thermal Management requires Continued Materials and Co-Design Focus•

Continued Scaling of Advanced Packaging requires focus on multiple aspects including interconnect design,
high-speed signaling, power delivery, thermal management, materials, assembly and process design29Legal Notices
Legal Notices
All product and service plans, and roadmaps are subject to change without notice. Any forecasts of goods and services needed for Intel'soperations are provided for discussion purposes only. Intel will have no liability to make any purchase in connection with forecasts
published in this document. Code names are often used by Intel to identify products, technologies, or services that are in development
and usage may change over time. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is grantedby this document.
All product and service plans and roadmaps are subject to change without notice. The products described may contain design defects orerrors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available
on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability,
fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or
usage in trade. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis
concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafterdrafted which includes subject matter disclosed herein.
Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on
current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or
implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent
earnings release and SEC filings at www.intc.com.
© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names andbrands may be claimed as the property of others. This document contains information on products and/or processes in development.

30

Advanced Packaging Technologies : Product Implementations
Sandeep Sane, Principal Engineer
Ravi Mahajan, Fellow
Intel Corporation

Acknowledgments: Ram Viswanath, Mark Gardner, Jan Krajniak, Luke Garner, Pat Stover, Chris Baldwin, Babak Sabi

Current State of Advanced Packaging (Intel Centric View)
EMIB

Foveros

EMIB-Foveros

32

EMIB Embedded Multi-Die Interconnect Bridge• Localized high-density wiring• Multiple Bridges, Multiple Bridge Sizes andBridge Technologies• Bridge Mix and Match → Enhanced Design
Flexibility• Bridge silicon costs < Silicon interposer
 No TSVs, Significantly less silicon area

• Die from Different Foundries• Large Overall Die Area enabled33

Sapphire Rapids - EMIB Implementation

Attribute
Top Die CountMax Top Die Size
EMIB Pitch
Core Pitch (minimum)
Memory (HBM)
Package size
EMIB count

SPR XCC
4~400 mm2
55µm
100µm
N/A
78 x 57 mm
10

SPR HBM4, + 4 HBM2E~400 mm255µm
100µm
4x 8H HBM2E
100 x 57 mm
1434

EMIB Link Capability
Improvement
due to EMIB

Intel MDF

Intel OPIO

Packaging Tech

EMIBStandard
2 routing layers

Bump Pitch (µm)

55

110

Pin Speed (Gbps)

5.4

8 – 16

Shoreline BW density(GBps/mm)

196

34.5 – 69

5.68x – 2.84x

Areal BW density(GBps/mm2)

158

36.7 – 73.4

4.3x – 2.15x

PHY power efficiency

0.5

1.5-2.0

3x – 4x• Intel MDF was announced in Semicon West 2019.
• Intel OPIO 8Gbps was used in a Client in 2013. Higher speeds were developed in an internal study.

35

Intel Foveros : High Density 3D

50µm Die-Die Interconnect Pitch
10nm Core
22nm Base Die

Compact Active Die Stacking : Initial
Offering is Single Tile on Base die @ 50µm
pitch

We are systematically Scaling tile
count, Bump pitch
Meteor Lake @36µm Bump pitch

1.
2.

D. Ingerly, et al. “Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices,” 2019 IEDM
W. Gomes et al., "8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package," 2020 ISSCC

36

Blending Planar and 3D MCPs (EMIB + Foveros)
Compute Tile

Rambo Tile

Ponte Vecchio

Foveros

SOC

Base Tile>100 Billion Transistors

HBM Tile

47 Active Tiles

Xe Link Tile

5 Process Nodes

Multi Tile Package
EMIB Tile

37

Ponte Vecchio
Attribute

PVC 2T

D2D Pitch

36µm

Active Top Die Count Per Stack

16

Max Active Top Die Size

41mm2

Base Die Size

650mm2

EMIB Pitch

55µm

Core Pitch (min)100µm

Memory (HBM)

8x

Package size

(77.5 x 62.5) mm

EMIB count11
38

Continued leadership in advanced packaging

Packaging Innovations In The Near Future: Foveros Omni andFoveros Direct• Rich Interconnect Portfolio allows
greater mix-and-match andbetter/independent interconnect
optimization for Power and IO• Pitch Scaling from 25µm → ≤ 10µm
leads to an order of magnitude
increase in IO/mm2 (1600 → ≥ 10,000)

40

Key Messages• Several Innovative Packaging Architectures are available today for Scaling in all 3
directions – In Today’s talks we have focused mainly on the physicalimplementations• Intel is using them in Client, Server and Discrete Graphics products to provide
unprecedented levels of Heterogeneous Integration• The next generation of Innovations in HI will offer increased partitioning
opportunities with an enhanced interconnect portfolio and significant increases
in interconnect density

41

Thank you!

42

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Packaging and Manufacturing Technology, Volume: 9, Issue: 10, Oct. 2019, pp. 1952-1962.
D. Greenhill, et al, “A 14nm 1GHz FPGA with 2.5D transceiver integration” 2017 IEEE International Solid-State Circuits Conference (ISSCC) 2017 pp. 54-55 Feb 2017.
IEEE Electronics Packaging Society Heterogeneous Integration Roadmap, 2019 Edition, https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html.
S. K. Moore, “Intel’s View of the Chiplet Revolution”, IEEE Spectrum, April 12, 2019; https://spectrum.ieee.org/tech-talk/semiconductors /processors/intels-view-of-the-chipletrevolution.
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D. Ingerly, et al. “Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices,” 2019 International Electron Devices Meeting, San Francisco, CA, Dec. 2019.
K. Oi, et al., “Development of New 2.5D Package with Novel Integrated Organic Interposer Substrate with Ultra-Fine Wiring and High-Density Bumps,” Proceedings of the 2014 IEEE
64th Electronic Components and Technology Conference, Orlando, pp. 348-353.
W. Gomes, et al., “Lakefield: 3D stacked 10 nm and 22 FFL Mobile Processor System in 12x12, 1 mm POP Package,” 2020 International Solid-State Circuits Conference, San
Francisco, Feb. 2018.
R. Mahajan, et al., "Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect," Proc. IEEE Electronic Components and Technology
Conference (ECTC), Las Vegas, NV, May 26-29, 2016, pp. 557-565.
https://www.anandtech.com/show/9390/the-amd-radeon-r9-fury-x-review.
D. Yu, “Advanced Heterogeneous Integration Technology Trend for Cloud and Edge,” 2017 IEEE Electron Devices Technology and Manufacturing Conference, Japan, March 2017.
https://www.darpa.mil/program/common-heterogeneous-integration-and-ip-reuse-strategies.
AIB Github: https://github.com/intel/aib-phy-hardware.
K. Oi, et al., “Development of New 2.5D Package with Novel Integrated Organic Interposer Substrate with Ultra-Fine Wiring and High-Density Bumps,” Proceedings of the 2014 IEEE
64th Electronic Components and Technology Conference, Orlando, pp. 348-353.
M. Sunohara, T. Tokunaga, T. Kurihara and M. Higashi, “Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring,” in Proc. IEEE Electronic Components andTechnol. Conf. (ECTC), Lake Buena Vista, FL, May 27–30, 2008, pp. 847–852.
S. Miki, H. Taneda, n. Kobayashi, K. Oi, K. Nagai, T. Koyama, “Development of 2.3D High Density Organic Package using Low Temperature Bonding Process with Sn-Bi Solder,”Proceedings of the 2019 IEEE 69th Electronic Components and Technology Conference, Las Vegas, pp. 1599-1604.
A. A. Elsherbini, S. M. Liff and J. M. Swan. “Heterogeneous Integration Using Omni-Directional Interconnect Packaging,” 2019 International Electron Devices Meeting, San
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43

Legal Notices
Legal Notices
All product and service plans, and roadmaps are subject to change without notice. Any forecasts of goods and services needed for Intel'soperations are provided for discussion purposes only. Intel will have no liability to make any purchase in connection with forecasts
published in this document. Code names are often used by Intel to identify products, technologies, or services that are in development
and usage may change over time. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is grantedby this document.
All product and service plans and roadmaps are subject to change without notice. The products described may contain design defects orerrors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available
on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability,
fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or
usage in trade. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis
concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafterdrafted which includes subject matter disclosed herein.
Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on
current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or
implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent
earnings release and SEC filings at www.intc.com.
© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names andbrands may be claimed as the property of others. This document contains information on products and/or processes in development.

44