Data Sheet No. PD94140

IRU3004
5-BIT PROGRAMMABLE SYNCHRONOUS BUCKCONTROLLER IC WITH DUAL LDO CONTROLLER
DESCRIPTIONFEATURES

Meets latest VRM 8.4 specification for PentiumIII
Provides single chip solution for Vcore, GTL+ andclock supply
On-Board DAC programs the output voltage from
1.3V to 3.5V. The IRU3004 remains on for VID codeof (11111)
Dual linear regulator controller on-board for 1.5V
GTL+ and 2.5V clock supplies
Loss-less Short Circuit Protection
Synchronous operation allows maximum efficiency
Patented architecture allows fixed frequency operation as well as 100% duty cycle during dynamic
load
Minimum Part Count, No External Compensation
Soft-Start Function
High current totem pole driver for direct driving of theexternal power MOSFET
Power Good Function

The IRU3004 controller IC is specifically designed to meetIntel specifications for Pentium III microprocessor
applications as well as the next generation P6 family
processors. The IC provides a single chip controller IC
for the Vcore, GTL+ and clock supplies required for thePentium III applications. The IRU3004 features a patented topology, that in combination with a few external
components as shown in the typical application circuit,will provide in excess of 20A of output current for an onboard DC-DC converter while automatically providing theright output voltage via the 5-bit internal DAC meetingthe latest VRM specification. The IRU3004 also featuresloss-less current sensing by using the RDS(on) of the highside power MOSFET as the sensing resistor and a Power
Good window comparator that switches its open collector output low when the output is outside of a ±10%window. Other features of the device are: under-voltage
lockout for both 5V and 12V supplies, an external programmable soft-start function as well as programming
the oscillator frequency by using an external capacitor.

APPLICATIONSPentium III & next generation processor DC to DC
converter application
Low Cost Pentium with AGP

TYPICAL APPLICATION
5V

R16
C5

C13

Note: Pentium III is trademark of Intel Corp.

L2

Q1

L1
R1

C7

VOUT 3
R17
C16

Q2

C3

C10

R4
R2

R3
R12

R13

3.3V
C4

12V

C6

Q3

V OUT 1
C11

R18
V12

V5

CS+

HDrv

CS-

LDrv

Gnd

R7

VFB3
R11

Ct

Lin1
C15

IRU3004

C1
SS
C2

V FB1

D4

D3

D2

D1

D0

V FB2

PGd

R8

Q4

V OUT 2

Lin2
C12

C9

3.3V

R14

VID4
VID3

R5

VID2
C8

VID1

R9

C14

R15

Power Good

VID0

Figure 1 - Typical application of the IRU3004.

PACKAGE ORDER INFORMATION
TA (8C)
0 To 70
0 To 70
Rev. 1.7
07/16/02

DEVICE
IRU3004CWIRU3004CF

PACKAGE
20-Pin Plastic SOIC (W)20-Pin Plastic TSSOP (F)www.irf.com

1

IRU3004
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage .................................................... 10V
V12 Supply Voltage .................................................. 20V
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C

PACKAGE INFORMATION
20-PIN WIDE BODY PLASTIC SOIC (W)

20-PIN PLASTIC TSSOP (F)TOP VIEWTOP VIEW
Ct 1

20 Lin2

Ct 1

20 Lin2

Lin1 219 D 0

Lin1 219 D 0V FB1 318 D 1

V FB1 318 D 1V FB2 417 D 2

V FB2 417 D 2V5 5

16 D 3V5 5

16 D 3

PGd 6

15 D 4

PGd 6

15 D 4CS- 7

14 V FB3

CS- 7

14 V FB3

CS+ 8

13 SS

CS+ 8

13 SS

HDrv 912 V12

HDrv 912 V12

Gnd 1011 LDrv

Gnd 1011 LDrv

uJA =858C/W

uJA =908C/W

ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70°C. Typical values refer
to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
VID Section
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID Input Internal Pull-Up
Resistor to V5
Power Good Section
Under-Voltage lower trip point
Under-Voltage upper trip point
UV Hysteresis
Over-Voltage upper trip point
Over-Voltage lower trip point
OV Hysteresis
Power Good Output LO
Power Good Output HI
Soft-Start Section
Soft-Start Current

2

SYM

TEST CONDITION

MIN

TYP

MAX

UNITS

0.98VsVs

1.02Vs
0.1
0.5
0.4

V
%
%
V
V
KV

0.91Vs

V
V
V
V
V
V
V
V

2
27

VOUT Ramping Down
VOUT Ramping Up
VOUT Ramping Up
VOUT Ramping Down

0.89Vs
0.015Vs
1.09Vs
0.015Vs

RL=3mA
RL=5K Pull-Up to 5V
CS+=0V, CS-=5V

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0.90Vs
0.92Vs
0.02Vs
1.10Vs
1.08Vs
0.02Vs4.8
100.025Vs
1.11Vs
0.025Vs
0.4

mA

Rev. 1.7
07/16/02

IRU3004
PARAMETERUVLO Section
UVLO Threshold-12V
UVLO Hysteresis-12V
UVLO Threshold-5V
UVLO Hysteresis-5V
Error Comparator Section
Input Bias Current
Input Offset Voltage
Delay to Output
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
Supply Current
Operating Supply Current

SYM

TEST CONDITION
Supply Ramping Up
Supply Ramping Up

MIN

TYP

MAX

UNITS

9.2
0.3
4.1
0.2

10
0.4
4.3
0.3

10.8
0.5
4.5
0.4

V
V
V
V

2
+2
100

mA
mV
ns

240
+5
2

mA
mV
%

-2
VDIFF=10mV
160
-5

200

Css=0.1mF

Output Drivers Section
Rise Time
Fall Time
Dead Band Time
Oscillator Section
Osc Frequency
Osc Valley
Osc PeakLDO Controller Section
VFB1 & VFB2
Input Bias Current
Lin1 or Lin2 Drive Current

CL=3000pF:
V5
V12

20
14

CL=3000pF
CL=3000pF
CL=3000pF

100

70
70
200

100
130
300

ns
ns
ns

Ct=150pF

160

220

260
0.2

KHz
V
V

1.545
2

V
mA
mA

mA

V5
1.455

1.500
50

Note 1: Vs refers to the set point voltage given in Table 1.
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05

D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5

Table 1 - Set point voltage vs. VID codes.
Rev. 1.7
07/16/02

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IRU3004
PIN DESCRIPTIONSPIN#
1PIN SYMBOL
Ct

2

Lin1

3
4
5
6

VFB1
VFB2
V5
PGd

7

CS-

8

CS+

9
10

HDrv
Gnd

11
12

LDrv
V12

13

SS

14

VFB3

15

D4

16

D3

17

D2

18

D1

19

D0

20

Lin2

4

PIN DESCRIPTIONThis pin programs the oscillator frequency in the range of 50KHz to 500KHz with an
external capacitor connected from this pin to the ground.
This pin controls the gate of an external transistor for either the GTL+ linear regulator or
Clock supply.
This pin provides the feedback for the linear regulator that its output drive is Lin1 pin.
This pin provides the feedback for the linear regulator that its output drive is Lin2 pin.
5V supply voltage.
This pin is an open collector output that switches LO when the output of the converter is
not within ±10% (typical) of the nominal output voltage. When Power Good pin switches
LO the sat voltage is less than 0.4V at 3mA.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resistor programs the CS threshold depending on the RDS of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
Output driver for the high-side power MOSFET.
This pin serves as the ground pin and must be connected directly to the ground plane. A
high frequency capacitor (0.1 to 1mF) must be connected from V5 and V12 pins to thispin for noise free operation.
Output driver for the synchronous power MOSFET.
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (0.1 to 1mF) must be connected directly from this pin
to ground pin in order to supply the peak current to the power MOSFET duringthe transitions.
This pin provides the soft-start for the switching regulator. An internal current source
charges an external capacitor that is connected from this pin to the ground which ramps
up the outputs of the switching regulator, preventing the outputs from overshooting aswell as limiting the input current. The second function of the Soft-Start cap is to provide
long off time (HICCUP) for the synchronous MOSFET during current limiting.
This pin is connected directly to the output of the Core supply to provide feedback to theError comparator.
This pin selects a range of output voltages for the DAC. When in the LOW state therange is 1.3V to 2.05V. For VID codes of all "1" the IRU3004 keeps all the outputs on.
MSB input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage. This pin can be pulled up externallyby a 10K resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage. This pin can be pulled up externallyby a 10KV resistor to either 3.3V or 5V supply.
LSB input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply.
This pin controls the gate of an external transistor for either the GTL+ linear regulator or
Clock supply.

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Rev. 1.7
07/16/02

IRU3004
BLOCK DIAGRAM

EnableVset

V12 12
V5

Enable

UVLO
+
Vset

D1 18
D2 17
D3 16
D4 15

9

HDrv

11

LDrv

7

CS-

8

CS+

1

Ct

13

SS

6

PGd

10

Gnd

V12

Enable

5Bit
DAC,
Ctrl
Logic

VFB3

PWM
Control

5

D0 19

14
V12

Slope
Comp

Soft
Start &
Fault
Logic

Osc
Over
Current

200uA
EnableVFB2 4
Lin2 20

1.1Vset

1.5V

Lin1 2
0.9Vset

VFB1 3Figure 2 - Simplified block diagram of the IRU3004.

Rev. 1.7
07/16/02

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IRU3004
TYPICAL APPLICATION
Pentium III
L2

L1

Q1

5V

VO U T 3
R16

C5

R1
C7

C13

R17
C16

Q2

C3

C10
R4

R2

R3
R12

R13

3.3V
C4

C6

Q3

VO U T 1

12V

C11

R18
V12

V5

CS+

HDrv

CS-

LDrv

Gnd

R7

V FB3
R11

Ct

Lin1

IRU3004

C1

C15

SS
C2

D4

V FB1
D3

D2

D1

D0

V FB2

PGd

Q4

VO U T 2

Lin2
C9

3.3V

C12

VID4
VID3

R14
R5

R9

VID2
VID1

R8

C14
C8

R15

Power Good

VID0

Figure 3 - Typical application of IRU3004 in an on-board DC-DC converter providing the Core, GTL+,
and Clock supplies for the Pentium II microprocessor.

6

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Rev. 1.7
07/16/02

IRU3004
IRU3004 APPLICATION PARTS LIST
Ref Desig Description

Qty

Part #Manuf

Q1

MOSFET1

IRL3103S, TO-263 packageIR

Q2

MOSFET1

IRL3103D1S, TO-263 package

IR

Q3

Bipolar Trans, GP

1

MPS2222A, SOT-23 package

Motorola

Q4

MOSFET1

IRLR024, TO-252 package

L1

Inductor

1

L=1mH, 5052 core with 4 turns of 1.0mm wire

MicroMetal

L2

Inductor

1

L=2.7mH, 5052B core with 7 turns of 1.2mm wire

Micro Metal

C1

Capacitor, Ceramic

1

150pF, 0603

C2, 6

Capacitor, Ceramic

2

1mF, 0603

C3

Capacitor, Electrolytic

2

10MV1200GX, 1200mF,10V

C4Capacitor, Ceramic

1

1mF, 0805

C5

Capacitor, Ceramic

1

220pF, 0603

C7, 14, 15 Capacitor, Ceramic

3

1000pF, 0603

C8

Capacitor, Ceramic

1

0.1mF, 0603

C9

Capacitor, Electrolytic

1

6MV1000GX, 1000mF, 6.3V

Sanyo

C10

Capacitor, Electrolytic

6

6MV1500GX, 1500mF, 6.3V

Sanyo

C11

Capacitor, Electrolytic

1

6MV150GX, 150mF, 6.3V

Sanyo

C12

Capacitor, Electrolytic

1

6MV1000GX, 1000mF, 6.3V

Sanyo

C13

Capacitor, Electrolytic

1

10MV470GX, 470mF, 10V

Sanyo

C16

Capacitor, Ceramic

1

4.7mF, 1206

R1

Resistor

1

3.3KV, 5%, 0603

R2, 3, 4Resistor

3

4.7V, 5%, 1206

R5, 15

Resistor

2

10KV, 5%, 0603

R7, 12

Resistor

2

100V, 1%, 0603

R8

Resistor

1

150V, 1%, 0603

R9, 11, 14 Resistor

3

100V, 5%, 0603

R13

Resistor

1

22KV, 1%, 0603

R16

Resistor

1

220V, 1%, 0603

R17

Resistor

1

330V, 1%, 0603

R18

Resistor

1

10V, 5%, 0603

IR

Sanyo

Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU transient
voltage.
Note 2: R14 and R15 set the 1.5V approximately 1% higher to account for the trace resistance drop.

Rev. 1.7
07/16/02

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IRU3004
TYPICAL APPLICATION
Pentium with AGP
L2

L1

Q1

5V

VOUT3
R16

C5
C13

R1

C7

R17
C16

Q2

C3

C10
R4

R2

R3
R12

R13

3.3V
C4

Q3

C6

12V

C9

R18
V12

V5

CS+

HDrv

CS-

LDrv

Gnd

C11
R7

VFB3
R11

Ct

Lin1
C15

IRU3004

C1

R8

VFB1

SS
C2

D4

D3

D2

D1

D0

VFB2

PGd

Q4

Lin2

3.3V

3.3V

VID4
VID3

C12
R14
R5

VID2
VID1

R9
C14

C8

Power Good

R15

VID0

Figure 4 - Typical application of IRU3004 in a Pentium with AGP where the power dissipation of the 3.3V
linear regulator is equally distributed between Q3 and Q4 pass transistors. This equal distribution ispossible by accurately regulating the first regulator using the IRU3004 linear controller and its internal
1% reference voltage while the second controller regulates the output of the first regulator from 4.17V to
3.3V, thereby distributing the power dissipation equally.

8

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Rev. 1.7
07/16/02

IRU3004
IRU3004 APPLICATION PARTS LIST
Ref Desig Description
Q1
MOSFET

Qty
1

Part #
IRL3103s, TO-263 package

Manuf
IR

Q2

MOSFET1

IRL3103D1S, TO-263 package

IR

Q3, 4

MOSFET

2

IRL3303S, TO-263 package

IR

L1

Inductor

1

L=1mH, 5052 core with 4 turns ofMicro Metal

1.0mm wire
L2

Inductor

1

L=2.7mH, 5052B core with 7 turns ofMicro Metal

1.2mm wire
C1

Capacitor, Ceramic

1

150pF, 0603

C2, 6

Capacitor, Ceramic

2

1mF, 0603

C3

Capacitor, Electrolytic

2

10MV1200GX, 1200mF, 10V

C4Capacitor, Ceramic

1

1mF, 0805

C5

Sanyo

Capacitor, Ceramic

1

220pF, 0603

C7, 14, 15 Capacitor, Ceramic

3

1000pF, 0603

C8

Capacitor, Ceramic

1

0.1mF, 0603

C9

Capacitor, Electrolytic

1

6MV1000GX, 1000mF, 6.3V

Sanyo

C10

Capacitor, Electrolytic

6

6MV1500GX, 1500mF, 6.3V

Sanyo

C11

Capacitor, Electrolytic

1

6MV150GX, 150mF, 6.3V

Sanyo

C12

Capacitor, Electrolytic

1

6MV1000GX, 1000mF, 6.3V

Sanyo

C13

Capacitor, Electrolytic

1

10MV470GX, 470mF, 10V

Sanyo

C16

Capacitor, Ceramic

1

4.7mF, 1206

R1

Resistor

1

3.3KV, 5%, 0603

R2, 3, 4Resistor

3

4.7V, 5%, 1206

R5, 15

Resistor

2

10KV, 5%, 0603

R7

Resistor

1

267V, 1%, 0603

R8

Resistor

2

150V, 1%, 0603

R9, 11, 14 Resistor

3

100V, 5%, 0603

R12

Resistor

1

100V, 1%, 0603

R13

Resistor

1

22KV, 1%, 0603

R16

Resistor

1

220V, 1%, 0603

R17

Resistor

1

330V, 1%, 0603

R18

Resistor

1

10V, 5%, 0603

Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU transient
voltage.

Rev. 1.7
07/16/02

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IRU3004
APPLICATION INFORMATION
An example of how to calculate the components for theapplication circuit is given below.
Assuming, two sets of output conditions that this regulator must meet:a) Vo=2.8V, Io=14.2A, DVo=185mV, DIo=14.2Ab) Vo=2V, Io=14.2A, DVo=140mV, DIo=14.2A
The regulator design will be done such that it meets theworst case requirement of each condition.
Output Capacitor Selection
The first step is to select the output capacitor. This isdone primarily by selecting the maximum ESR valuethat meets the transient voltage budget of the total DVo
specification. Assuming that the regulators DC initialaccuracy plus the output ripple is 2% of the output voltage, then the maximum ESR of the output capacitor is
calculated as:
ESR [

100
= 7mV
14.2

The Sanyo MVGX series is a good choice to achieveboth the price and performance goals. The 6MV1500GX,
1500mF, 6.3V has an ESR of less than 36mV typical.
Selecting 6 of these capacitors in parallel has an ESRof ≈ 6mV which achieves our low ESR goal.

output capacitor ESR at the cost of load regulation. One
can show that the new ESR requirement eases up by
half the total trace resistance. For example, if the ESR
requirement of the output capacitors without voltage level
shifting must be 7mV, then after level shifting the new
ESR will only need to be 9.5mV if the trace resistance
is 5mV (7 + 5/2=9.5). However, one must be careful thatthe combined “voltage level shifting” and the transient
response is still within the maximum tolerance of theIntel specification. To insure this, the maximum trace
resistance must be less than:Rs [ 2 3(Vspec - 0.02 3 Vo - DVo)
DI

Where:
Rs = Total maximum trace resistance allowed
Vspec = Intel total voltage specification
Vo = Output voltage
DVo = Output ripple voltage
DI = load current stepFor example, assuming:
Vspec = ±140mV = ±0.1V for 2V output
Vo = 2V
DVo = assume 10mV = 0.01V
DI = 14.2A
Then the Rs is calculated to be:

Other type of Electrolytic capacitors from other manufacturers to consider are the Panasonic FA series or the
Nichicon PL series.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the outputof the switching regulator to the Slot 1 can be used tothe circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transition from light load to full load and vice versa.
To accomplish this, the output of the regulator is typically set about half the DC drop that results from lightload to full load. For example, if the total resistance fromthe output capacitors to the Slot 1 and back to the Gnd
pin of the device is 5mV and if the total DI, the change
from light load to full load is 14A, then the output voltage
measured at the top of the resistor divider which is also
connected to the output capacitors in this case, must
be set at half of the 70mV or 35mV higher than the DAC
voltage setting. This intentional voltage level shifting
during the load transient eases the requirement for the10

Rs [ 2 3(0.140 - 0.02 3 2 - 0.01)= 12.6mV
14.2

However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor isbeing used) must also be considered. For example if
Rs=12.6mV, the power dissipated is:
Io23Rs = 14.22312.6 = 2.54W
This is a lot of power to be dissipated in a system. So, if
the Rs=5mV, then the power dissipated is about 1W
which is much more acceptable. If level shifting is not
implemented, then the maximum output capacitor ESR
was shown previously to be 7mV which translated to ≈ 6of the 1500mF, 6MV1500GX type Sanyo capacitors. With
Rs=5mV, the maximum ESR becomes 9.5mV which isequivalent to ≈ 4 caps. Another important considerationis that if a trace is being used to implement the resistor,
the power dissipated by the trace increases the casetemperature of the output capacitors which could seriously effect the life time of the output capacitors.

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Rev. 1.7
07/16/02

IRU3004
Output Inductor Selection
The output inductance must be selected such that under low line and the maximum output voltage condition,
the inductor current slope times the output capacitor
ESR is ramping up faster than the capacitor voltage isdrooping during a load current step. However, if the inductor is too small, the output ripple current and ripple
voltage become too large. One solution to bring the ripple
current down is to increase the switching frequency,
however that will be at the cost of reduced efficiency andhigher system cost. The following set of formulas arederived to achieve the optimum performance without
many design iterations.
The maximum output inductance is calculated using thefollowing equation:(V 2 3- Vo∆I )L = ESR3C3

IN(MIN)(MAX)

Where:
VIN(MIN) = Minimum input voltage
Vo = 2.8V , DI = 14.2A
L = 0.006390003

In our example for Vo=2.8V and 14.2A load, assuming
IRL3103 MOSFET for both switches with maximum onresistance of 19mV, we have:1= 5ms
200000Vsw = Vsync = 14.2 3 0.019 = 0.27V
2.8 + 0.27
D≈
= 0.61
5 - 0.27 + 0.27
TON = 0.61 3 5 = 3.1ms
T=

TOFF = 5 - 3.1 = 1.9ms
1.9
DIr = (2.8 + 0.27) 3= 1.94A
3
DVo = 1.94 3 0.006 = 0.011V = 11mV
Power Component Selection
Assuming IRL3103 MOSFETs as power components,
we will calculate the maximum power dissipation as follows:
For high-side switch the maximum power dissipation
happens at maximum Vo and maximum duty cycle.

- 2.8= 3.7mH( 4.752314.2 )(2.8 + 0.27)
DMAX ≈ (4.75 - 0.27 + 0.27) = 0.65

Assuming that the programmed switching frequency is
set at 200KHz, an inductor is designed using theMicrometals’ powder iron core material. The summaryof the design is outlined below:
The selected core material is Powder Iron, the selected
core is T50-52D from Micro Metal wound with 8 turns of#16 AWG wire, resulting in 3mH inductance with ≈ 3mV
of DC resistance.

PDH = DMAX 3 Io2 3 RDS(MAX)PDH = 0.65 3 14.22 3 0.029 = 3.8W
RDS(MAX) = Maximum RDS(ON) of the MOSFET (1258C)
For synchronous MOSFET, maximum power dissipation happens at minimum Vo and minimum duty cycle.
DMIN ≈(2 + 0.27)= 0.43(5.25 - 0.27 + 0.27)

PDS = (1 - DMIN) 3 Io2 3 RDS(MAX)
Assuming L=3mH and Fsw=200KHz (switching frequency), the inductor ripple current and the output ripple
voltage is calculated using the following set of equations:T ≡ Switching Period
D ≡ Duty Cycle
Vsw ≡ High side Mosfet ON Voltage
RDS ≡ Mosfet On ResistanceVsync ≡ Synchronous MOSFET ON Voltage
DIr ≡ Inductor Ripple Current
DVo ≡ Output Ripple Voltage
1
Fsw
Vsw = Vsync = Io3RDS
T=

D≈

Vo + Vsync
VIN - Vsw + Vsync

Rev. 1.7
07/16/02

TON = D3T
TOFF = T - TON
DIr = (Vo + Vsync)3

TOFF
L

PDS = (1 - 0.43) 3 14.22 3 0.029 = 3.33W
Heat Sink Selection
Selection of the heat sink is based on the maximum
allowable junction temperature of the MOSFETS. Since
we previously selected the maximum RDS(on) at 1258C,
then we must keep the junction below this temperature.
Selecting TO-220 package gives uJC=1.88C/W (from thevenders’ data sheet) and assuming that the selectedheat sink is black anodized, the heat-sink-to-case thermal resistance is uCS=0.058C/W, the maximum heat sinktemperature is then calculated as:
Ts = TJ - PD 3 (uJC + uCS)
Ts = 125 - 3.82 3 (1.8 + 0.05) = 1188C

DVo = DIr3ESR

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11

IRU3004
With the maximum heat sink temperature calculated in
the previous step, the heat-sink-to-air thermal resistance(uSA) is calculated as follows:
Assuming TA = 358C:

Switcher Timing Capacitor Selection
The switching frequency can be programmed using an
external timing capacitor. The value of Ct can be approximated using the equation below:
Fsw y

DT = Ts - TA = 118 - 35 = 838C
Temperature Rise Above Ambient

3.5 3 10-5
Ct

Where:
Ct = Timing Capacitor
Fsw = Switching Frequency

DT 83
uSA =
=
= 228C/W
PD 3.82
Next, a heat sink with lower uSA than the one calculated
in the previous step must be selected. One way is tosimply look at the graphs of the “Heat Sink Temp Rise
Above the Ambient” vs. the “Power Dissipation” given in
the heat sink manufacturers’ catalog and select a heatsink that results in lower temperature rise than the one
calculated in previous step. The following heat sinks fromAAVID and Thermalloy meet this criteria.
Company
Part #
Thermalloy............................6078B
AAVID..................................577002

If Fsw = 200KHz:
Ct y

3.5 3 10-5
= 175pF
200 3 103

LDO Power MOSFET Selection
The first step in selecting the power MOSFET for the
linear regulators is to select its maximum RDS(ON) basedon the input to output Dropout voltage and the maximum
load current.
For Vo = 1.5V, VIN = 3.3V and IL = 2A:
RDS(max) =Following the same procedure for the Schottky dioderesults in a heat sink with uSA=258C/W. Although it ispossible to select a slightly smaller heat sink, for simplicity, the same heat sink as the one for the high side
MOSFET is also selected for the synchronous MOSFET.
Switcher Current Limit Protection
The PWM controller uses the MOSFET RDS(ON) as thesensing resistor to sense the MOSFET current and compares to a programmed voltage which is set externally
via a resistor (Rcs) placed between the drain of the
MOSFET and the “CS+” terminal of the IC as shown in
the application circuit. For example, if the desired current limit point is set to be 22A and from our previous
selection, the maximum MOSFET RDS(ON)=19mV, thenthe current sense resistor, Rcs is calculated as:
Where:IB = 200mA is the internal current setting of the device(V IN - Vo) (3.3 - 1.5)=
= 0.9VIL
2

Note that since the MOSFETs RDS(ON) increases withtemperature, this number must be divided by ≈ 1.5, inorder to find the RDS(on) max at room temperature. The
Motorola MTP3055VL has a maximum of 0.18V RDS(ON)at room temperature, which meets our requirement.
To select the heat sink for the LDO MOSFET the firststep is to calculate the maximum power dissipation of
the device and then follow the same procedure as for theswitcher.
PD = (V IN - Vo) 3 IL
Where:PD = Power Dissipation of the Linear Regulator
IL = Linear Regulator Load Current
For the 1.5V and 2A load:
PD = (3.3 - 1.5) 3 2 = 3.6W
Assuming TJ(max) = 1258C then:Vcs = ICL 3 RDS = 22 3 0.019 = 0.418V
Vcs
0.418VRcs === 2.1KV
IB
200mA

12

Ts = TJ - PD 3 (uJC + uCS)
Ts = 125 - 3.6 3 (1.8 + 0.05) = 118°C

www.irf.com

Rev. 1.7
07/16/02

IRU3004
With the maximum heat sink temperature calculated in
the previous step, the heat-sink-to-air thermal resistance(uSA) is calculated as follows:

Disabling the LDO Regulators
The LDO controllers can easily be disabled by connecting the feedback pins (V FB1 and VFB2) to a voltage higher
than 1.5V such as 5V for all devices.

Assuming TA = 358C:
DT = Ts - TA = 118 - 35 = 838C
Temperature Rise Above Ambient
θSA =

DT 83
=
= 238C/W
PD 3.6The same heat sink as the one selected for the switcher
MOSFETs is also suitable for the 1.5V regulator. It isalso possible to use TO-263 package or even the
MTD3055VL in D-Pak if the load current is less than
1.5A. For the 2.5V regulator, since the dropout voltage
is only 0.8V and the load current is less than 0.5A, formost applications, the same MOSFET without heat sinkor for low cost applications, one can use PN2222A in
TO-92 or SOT-23 package.
LDO Regulator Component Selection
Since the internal voltage reference for the linear regulators is set at 1.5V for all devices, there is no need todivide the output voltage for the 1.5V, GTL+ regulator.
For the 2.5V Clock supply, the resistor dividers are selected per following:( RtR )3V

Vo = 1+V(V)((Vo - 1.0043V))
2.8
R13 = 1003 (= 11.76KV(2.835 - 1.00432.800))

=

DAC

DAC

Select 11.8KV, 1%
Note: The value of the top resistor must not exceed 100V.
The bottom resistor can then be adjusted to raise theoutput voltage.

Assuming Rt = 100V, for Vo = 2.5V:
Rt
Vo
VREF

For example, if DAC voltage setting is for 2.8V and thedesired output under light load is 2.835V, then R13 is
calculated using the following formula:
R13 = 1003

REF

B

Where:
Rt = Top resistor divider
RB = Bottom resistor divider
Vref = 1.5V typicalRB =Switcher Output Voltage Adjust
As was discussed earlier, the trace resistance from theoutput of the switching regulator to the Slot 1 can beused to the circuit advantage and possibly reduce thenumber of output capacitors, by level shifting the DC
regulation point when transitioning from light load to fullload and vice versa. To account for the DC drop, theoutput of the regulator is typically set about half the DC
drop that results from light load to full load. For example,
if the total resistance from the output capacitors to the
Slot 1 and back to the Gnd pin of the part is 5mV and if
the total DI, the change from light load to full load is
14A, then the output voltage measured at the top of theresistor divider which is also connected to the output
capacitors in this case, must be set at half of the 70mV
or 35mV higher than the DAC voltage setting. To do this,the top resistor of the resistor divider (R12 in the application circuit) is set at 100V, and the R13 is calculated.

100= 150V
2.5 - 1
1.5( )-1 ( )For 1.5V output, Rt can be shorted and RB left open.
However, it is recommended to leave the resistor dividers as shown in the typical application circuit so thatthe output voltage can be adjusted higher to account for
the trace resistance in the final board layout.
It is also recommended that an external filter be addedon the linear regulators to reduce the amount of the highfrequency ripple at the output of the regulators. This can
simply be done by the resistor capacitor combination
as shown in the application circuit.

Soft-Start Capacitor Selection
The soft-start capacitor must be selected such that during the start up, when the output capacitors are charging up, the peak inductor current does not reach thecurrent limit threshold. A minimum of 1mF capacitor insures this for most applications. An internal 10mA current source charges the soft-start capacitor which slowly
ramps up the inverting input of the PWM comparator
VFB3. This insures the output voltage to ramp at the samerate as the soft-start cap thereby limiting the input current. For example, with 1mF and the 10mA internal current source the ramp up rate is (DV/Dt)=(I/C)=1V/100ms.
Assuming that the output capacitance is 9000mF, themaximum start up current will be:
I = 9000mF 3 (1V / 100ms) = 0.09A

Rev. 1.7
07/16/02

www.irf.com

13

IRU3004
Input Filter
It is recommended to place an inductor between thesystem 5V supply and the input capacitors of the switching regulator to isolate the 5V supply from the switching
noise that occurs during the turn on and off of the switching components. Typically an inductor in the range of 1
to 3mH will be sufficient in this type of application.
Switcher External Shutdown
The best way to shutdown the switcher is to pull downon the soft-start pin using an external small signal transistor such as 2N3904 or 2N7002 small signal MOSFET.
This allows slow ramp up of the output, the same as thepower up.
Layout Considerations
Switching regulators require careful attention to the layout of the components, specifically power components
since they switch large currents. These switching components can create large amount of voltage spikes andhigh frequency harmonics if some of the critical components are far away from each other and are connectedwith inductive traces. The following is a guideline of how
to place the critical components and the connections
between them in order to minimize the above issues.
Start the layout by first placing the power components:
1) Place the input capacitors C3 and the high side
MOSFET, Q1 as close to each other as possible.
2) Place the synchronous MOSFET, Q2 and the Q1 asclose to each other as possible with the intention
that the source of Q1 and drain of the Q2 has theshortest length.
3) Place the snubber R4 & C7 between Q1 & Q2.
4) Place the output inductor, L2 and the output capacitors, C10 between the MOSFET and the load with
output capacitors distributed along the slot 1 andclose to it.
5) Place the bypass capacitors, C4 and C6 right next to
12V and 5V pins. C4 next to the 12V, pin 12 and C6
next to the 5V, pin 5.
6) Place the controller IC such that the PWM output
drives, pins 9 and 11 are relatively short distance fromgates of Q1 and Q2.
7) Place resistor dividers, R7 & R8 close to pin 3, R12& R13 (see note) close to pin 14 and R14 and R15(see note) close to pin 20.

14

Note: Although, the PWM controller does not require
R12-15 resistors, and the feedback pins 3 and 14
can be directly connected to their respective outputs,
they can be used to set the outputs slightly higher toaccount for any output drop at the load due to thetrace resistance.
8) Place R11, C15, Q3 and C11 close to each other anddo the same with R9, C14, Q4 and C12.
Note: It is better to place the linear regulator components close to the IC and then run a trace from theoutput of each regulator to its respective load suchas 2.5V to the clock and 1.5V for GTL + termination.
However, if this is not possible then the trace fromthe linear drive output pins, pins 2 and 20 must be
routed away from any high frequency data signals.
It is critical, to place high frequency ceramic capacitors close to the clock chip and termination resistors
to provide local bypassing.
9) Place timing capacitor C1 close to pin 1 and soft
start capacitor C2 close to pin 13.
Component connections:
Note: It is extremely important that no data bus shouldbe passing through the switching regulator section specifically close to the fast transition nodes such as PWM
drives or the inductor voltage.
Using the 4 layer board, dedicate on layer to ground,another layer as the power layer for the 5V, 3.3V, Vcore,
1.5V and if it is possible for the 2.5V. Connect all grounds
to the ground plane using direct vias to the ground plane.
Use large low inductance/low impedance plane to connect the following connections either using component
side or the solder side:a) C3 to Q1 Drainb) Q1 Source to Q2 Drainc) Q2 drain to L2d) L2 to the output capacitors, C10e) C10 to the slot 1f) Input filter L1 to the C3g) C9 to Q4 drainh) C12 to the Q4 source
Connect the rest of the components using the shortest
connection possible.
IR WORLD HEADQUARTERS : 233 Kansas St.,El Segundo,California 90245,
USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01

www.irf.com

Rev. 1.7
07/16/02

IRU3004(F) TSSOP Package
20-PinA
L
Q

R1B

1.0 DIA

C
R

E

N
M

P
O

PIN NUMBER 1F

D

DETAIL A

DETAIL A

G

J

H

K

SYMBOL
DESIG
A
B
C
D
E
F
G
H
J
K
L
M
N
O
P
Q
R
R1

MIN
4.30
0.19

6.40
--0.85
0.05

08
0.50
0.09
0.09

20-PIN
NOM
MAX
0.65 BSC
4.40
6.40 BSC--1.001.00
6.50--0.90--128 REF
128 REF--1.00 REF
0.60
0.20
-----

4.50
0.30

6.60
1.10
0.95
0.15

88
0.75
-----

NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.

Rev. 1.7
07/16/02

www.irf.com

15

IRU3004(W) SOIC Package
20-Pin Surface Mount, Wide Body
H

A
B

C

R

E

DETAIL-A
PIN NO. 1

L

D
0.516 0.020 x 458

DETAIL-A
K
F

G

SYMBOL
A
B
C
D
E
F
G
I
J
K
L
R
T

I

T

J

20-PIN
MIN
MAX
12.598 12.979
1.018 1.524
0.66 REF
0.33
0.508
7.40
7.60
2.032
2.64
0.10
0.30
0.229
0.32
10.008 10.654
0888
0.406 1.270
0.63
0.89
2.337 2.642

NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.

16

www.irf.com

Rev. 1.7
07/16/02

IRU3004
PACKAGE SHIPMENT METHOD
PKG
DESIG

PACKAGEDESCRIPTION

PIN
COUNT

PARTS
PER TUBEPARTSPER REEL

T&R
OrientationF

TSSOP Plastic

20

74

2500

Fig A

W

SOIC, Wide Body

20

38

1000

Fig B

1

1

1

1

Feed Direction
Figure A

1

1

Feed Direction
Figure B

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.7
07/16/02

www.irf.com

17