ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com■General description

ELM7C3793 series is an integrated circuit to monitor power voltage; it incorporates a watchdog timer. A reset
signal is output when the power is cut or falls abruptly. When the power recovers normally after resetting, apower-on reset signal is output to microprocessor units (MPUs). An internal watchdog timer with two inputs
for system operation diagnosis can provide a fail-safe function for various application systems.The standard
detection voltages are 3.0V, 3.7V, 4.2V and 4.5V; ELM7C3793 series can also be made as semi-custom IC
within the range of 1.6V to 5.0V by 0.1V step.

■Features■Application• Detection voltage with hysteresis function.
• Reset for Microprocessor, etc.
• Integrated dual input watchdog timer.
• Watchdog-timer halt function (by inhibition pin).
• Independently-set watchdog and reset times• Precise detection of power voltage fall
: ±2.5%• Low current consumption: Typ.31μA• Package: SOP-8 150mil, SOP-8 208mil, SON8-3×3■Maximum absolute ratings
Power supply

Parameter
CK1
CK2
INH

Input Voltage
Reset output voltage
Reset output current(RESET)

Symbol
Vcc
Vck1
Vck2
Vinh
Voh, Vol
Ioh, Iol

Power dissipation

Pd

Operating temperature
Storage temperature

Top
Tstg

Limit
6.5

Unit
V

Vss-0.3 to Vcc+0.3

V

Vss-0.3 to Vcc+0.3-10 to 10
300 (SOP-8)500 (SON8-3×3)-40 to +85-55 to +125

V
mA
mW
°C
°C

■Selection guide
ELM7C3793xxxxA-x
Symbola, b

Detection voltagec

Output formdefe.g. : 30: Vsl=3.0V
42: Vsl=4.2V

37: Vsl=3.7V
45: Vsl=4.5V

A: CMOS output
D: N-ch open-drain output

D: SOP-8 150mil P: SOP-8 208mil
G: SON8-3×3
Product version A
S: SON8-3×3 (Refer to PKG file)
Taping direction
N: SOP-8 (Refer to PKG file)
Package

ELM7C3793 x x x x A - x↑↑↑ ↑ ↑ ↑a bc d e f* Taping direction is one way.

Rev.1.4
1 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com■Pin configuration
SOP-8(TOP VIEW)
�

�

�

�

�

�

�

�

(BOTTOM VIEW) (BOTTOM VIEW)(TOP VIEW) VIEW)(TOP VIEW) SON8-3x3(BOTTOM
SON8-3x3(TOP
VIEW)
8

7

6

58

7

6

55

6

7

1

2

3

41

2

3

44

85

6

7

8

3

2

1

*

*

3

2

14

* The potential of the tab on the back is the ground(GND) level.
Please connect to GND pin(recommended) or set it to be open.

Pin No.

Pin name

Descriptions

1

Outputs reset pin

2
3

RESET
CTW
CTP

4
5

GND
VCC

Ground pin
Power supply pin

6
7
8

INH
CK2
CK1

Inhibit pin
Inputs clock 2 pin
Inputs clock 1 pin

Watchdog timer monitor time setting pin
Power-on reset hold time setting pin■Standard circuit
Vcc

5
VCC
RESET

2
3
Ctw

CTW
CTP

1

RESET Vcc

ELM7C3793
CK1

Ctp

8

Micro
Controller 2

CK

CK
GND

INH

GND

6

4

CK2

RESET Vcc

Micro
Controller 1

GND

7

Rev.1.4
2 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com■Block diagram

RESET
1

INH

(Buff)(Comp.O)

CTW

GND
4

CK2

TIMEUP

3uA

Pulse
Gen1

Watch Dog
Timer Circuit

CTW
2

CTP
3

CK1

Pulse
Gen2

30uA

CK1

8
CK2
7
INH
6

Logic
Circuit(75k ~ 755k) R1(Comp.S)(Vs)(240k)
Vref
R2
1.215VVCC

5

ELM7C3793■Functional descriptions
1. Comp.S
Comp.S is a comparator with hysteresis to compare the reference voltage with a voltage (Vs) that is the resultof dividing the power voltage (Vcc) by resistors 1 and 2. When VS falls below 1.215V, a reset signal is output.
This function enables the ELM7C379330xxA to detect an abnormality when the power is cut or falls abruptly.
2. Output circuit
The output circuit contains a RESET output control comparator that compares the voltage at the CTP pin to thethreshold voltage to release the RESET output if the CTP pin voltage exceeds the threshold value.
Since the reset (RESET) output buffer has CMOS organization, no pull-up resistor is needed.
3. Pulse generator
The pulse generator generates pulses when the voltage at the CK1 and CK2 clock pins changes to High from
Low level (positive-edge trigger) and exceeds the threshold voltage; it sends the clock signal to the watchdog
timer.
4. Watchdog timer
The watchdog timer can monitor two clock pulses. Short-circuit the CK1 and CK2 clock pins to monitor asingle clock pulse.
5. Inhibition pin
The inhibition (INH) pin forces the watchdog timer on/off. When this pin is High level, the watchdog timer is
stopped.
6. Logic circuit
The logic circuit controls the charging and discharging of the power-on reset hold time setting capacitor(Ctp),
and turns on/off the circuit that accelerates charging of the power-on reset hold time setting capacitor (Ctp) at areset. The accelerate charging circuit operates only at a reset; it does not operate at a power-on reset when the
power is turned on.

Rev.1.4
3 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com■Electrical characteristics
Vsl=3.7V(ELM7C379337xxA)

Parameter
Supply voltage
Power supply current
Detection voltage
Detection voltage hysteresis
difference

SymbolCondition
Vcc
Icc After exit from reset
Vcc falling
Vsl
Top=-40°C to +85°C
Vcc rising
Vsh
Top=-40°C to +85°C

40

85

130

(1.0)*
0.8(0.1)*
3.5
0
-1.0
4.50
-

1.6
1.3
0.3
0
0
4.75
0.12

2.5
(2.0)*(0.5)*
Vcc
0.8
1.0
0.40

Vccl Ireset=+50μA

-

0.8

1.2

V

Power-on reset hold time

tpr

Ctp=0.1μF*

30

75

120

ms

Watchdog timer monitor timetwd

Ctw=0.01μF *, Ctp=0.1μF

8

16

24

ms

Watchdog timer reset timetwr

Ctp=0.1μF

2.0

5.5

9.0

ms

Clock input pulse width
Clock input pulse cycle
Reset rising time
Reset falling time

tckw
tckt
tr*
Cl=50pF
tf*

500
20
-

-

500
500

ns
μs

Clock-input threshold voltage
Clock-input hysteresis
Inhibition-input voltage
Input current(CK1, CK2, INH)
Reset output voltage
Reset-output minimum power
voltageVshys Vsh-Vsl

Min.
1.2
3.60
(3.55)*
3.69(3.64)*

Vcc=5.0V, Top=25°C
Typ.
Max. Unit
5.0
6.0
V
30
50
μA
3.70
3.80
V
3.70 (3.85)*
3.79
3.89
V
3.79 (3.94)*

Vcih CK rising
Vcil CK falling
Vchys
Viih
Viil
Iih Vih=5.0V
Iil Vil=0.0V
Voh* Ireset=-5mA
Vol Ireset=+5mA

-

-

mV
V
V
V
μA
V

ns

* The values enclosed in parentheses ( ) are setting assurance values.
* Voh applies only to CMOS output.
* Ctp range is 0.001μF to 10μF, Ctw range is 0.001μF to 1μF.
* The voltage range is 10% to 90% at testing the reset output transition time.

Rev.1.4
4 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com
Vsl=3.0V(ELM7C379330xxA)

Parameter
Supply voltage
Power supply current
Detection voltage
Detection voltage hysteresis
difference

SymbolCondition
Vcc
Icc After exit from reset
Vcc falling
Vsl
Top=-40°C to +85°C
Vcc rising
Vsh
Top=-40°C to +85°C

30

70

110

(0.7)*
0.5(0.1)*
2.2
0
-1.0
2.80
-

1.3
1.0
0.3
0
0
3.10
0.12

1.9
(1.5)*(0.6)*
Vcc
0.8
1.0
0.40

Vccl Ireset=+50μA

-

0.8

1.2

V

Power-on reset hold time

tpr

Ctp=0.1μF*

30

75

120

ms

Watchdog timer monitor timetwd

Ctw=0.01μF *, Ctp=0.1μF

8

16

24

ms

Watchdog timer reset timetwr

Ctp=0.1μF

2.0

5.5

9.0

ms

Clock input pulse width
Clock input pulse cycle
Reset rising time
Reset falling time

tckw
tckt
tr*
Cl=50pF
tf*

500
20
-

-

500
500

ns
μs

Clock-input threshold voltage
Clock-input hysteresis
Inhibition-input voltage
Input current(CK1, CK2, INH)
Reset output voltage
Reset-output minimum power
voltageVshys Vsh-Vsl

Min.
1.2
2.93
(2.89)*
3.00(2.96)*

Vcc=3.3V, Top=25°C
Typ.
Max. Unit
3.3
6.0
V
31
45
μA
3.00
3.07
V
3.00 (3.11)*
3.07
3.14
V
3.07 (3.18)*

Vcih CK rising
Vcil CK falling
Vchys
Viih
Viil
Iih Vih=3.3V
Iil Vil=0.0V
Voh* Ireset=-3mA
Vol Ireset=+3mA

-

-

mV
V
V
V
μA
V

ns

* The values enclosed in parentheses ( ) are setting assurance values.
* Voh applies only to CMOS output.
* Ctp range is 0.001μF to 10μF, Ctw range is 0.001μF to 1μF.
* The voltage range is 10% to 90% at testing the reset output transition time.

Rev.1.4
5 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com■Timing chart
Fig.1: Basic operation (Positive clock pulse)

Rev.1.4
6 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com

Fig.2: Basic operation (Negative clock pulse)

Fig.3: Single-clock input monitoring (Positive clock pulse)

Rev.1.4
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ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com

Fig.4: Inhibition operation (Positive clock pulse)

Fig.5: Clock pulse input supplementation (Positive clock pulse)

Note :The ELM7C3793 watchdog timer monitors Clock1 (CK1) and Clock2 (CK2) pulses alternately.
When a CK2 pulse is detected after detecting a CK1 pulse, the monitoring time setting capacity (Ctw) switches to charging
from discharging.
When two consecutive pulses occur on one side of this alternation before switching, the second pulse is ignored.
In the above figure, pulse *1 and *2 are ignored.

Rev.1.4
8 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com■Operation sequence
1.Positive clock pulse input
See “Fig.1 Basic operation (positive clock pulse)” under “■Timing chart”.
2. Negative clock pulse input
See “Fig.2 Basic operation (negative clock pulse)” under “■Timing chart”.
ELM7C3793 operates in the same way whether it inputs positive or negative pulses.

3. One clock monitoring
To use ELM7C3793 while monitoring only one clock, connect clock pins CK1 and CK2.
Although ELM7C3793 operates basically in the same way as when monitoring two clocks, it monitors theclock signal at every other input pulse.
See “Fig.3 Single-clock input monitoring (positive clock pulse)” under “■Timing chart”.
4. Description of operations
The numbers given to the following items correspond to numbers (1) to (13) used in “■Timing chart”.
(1) ELM7C3793 outputs a reset signal when the supply voltage (Vcc) reaches about 0.8 V (Vccl).
(2) If Vcc reaches or exceeds the rise-time detected voltage Vsh, ELM7C3793 starts charging the power-on reset
hold time setting capacitor Ctp. At this time, the output remains in a reset state. The Vsh value is about 3.07V(Typ.).
(3) When Ctp has been charged for a certain period of time Tpr (until the CTP pin voltage exceeds the thresholdvoltage (Vth) after the start of charging), ELM7C3793 cancels the reset (setting the RESET pin to “H” levelfrom “L” level). The Vth value is about 1.245V(Typ.) regardless of Vcc voltage.
The power-on reset hold time tpr is set with the following equation:tpr(ms) ≈ A × Ctp(μF)
The value of A is about 750 regardless of Vcc voltage. ELM7C3793 also starts charging the watchdog time
setting capacitor (Ctw).
(4) When the voltage at the watchdog timer monitor time setting pin CTW reaches the “H” level thresholdvoltage Vh, the Ctw switches from the charge state to the discharge state. The value of Vh is always about
1.245 V regardless of Vcc voltage.
(5) If the CK2 pin inputs a clock pulse (positive edge trigger) when the Ctw is being discharged in the CK1-CK2
order or simultaneously, the Ctw switches from the discharge state to the charge state. ELM7C3793 repeats
operations (4) and (5) as long as the CK1/CK2 pin inputs clock pulses with the system logic circuit operating
normally.
(6) If no clock pulse is fed to the CK1 or CK2 pin within the watchdog timer monitor time twd due to some problem
with the system logic circuit, the CTW pin is set to the “L” level threshold voltage Vl or less and ELM7C3793
outputs a reset signal (setting the RESET pin to “L” level from “H” level).
The watchdog timer monitor time twd is set with the following equation:
twd(ms) ≈ B × Ctw(μF)
The value of B is hardly affected by the power supply voltage; it is about 1600 regardless of Vcc voltage.
(7) When a certain period of time twr has passed (until the CTP pin voltage reaches or exceeds Vth again after
recharging the Ctp), ELM7C3793 cancels the reset signal and starts operating the watchdog timer. The watchdog
timer monitor reset time twr is set with the following equation:twr (ms) ≈ D x Ctp(μF)
The value of D is 55 regardless of Vcc voltage.
ELM7C3793 repeats operations. (4) and (5) as long as the CK1/CK2 pin inputs clock pulses. If no clock
pulse is input, ELM7C3793 repeats operations (6) and (7).
Rev.1.4
9 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com(8) If Vcc is lowered to the fall-time detected voltage (Vsl) or less, the CTP pin voltage decreases and ELM7C3793
outputs a reset signal (setting the RESET pin to “L” level from “H” level). The value of Vsl is 3.0 V(9) When Vcc reaches or exceeds Vsh again, ELM7C3793 starts charging the Ctp.
(10) When the CTP pin voltage reaches or exceeds Vth, ELM7C3793 cancels the reset and restarts operating thewatchdog timer. It repeats operations (4) and (5) as long as the CK1/CK2 pin inputs clock pulses.
(11) Making the inhibit pin active (setting the INH pin to “H” from “L”) forces the watchdog timer to stop
operation. This stops only the watchdog timer, leaving ELM7C3793 monitoring Vcc (operations (8) to (10)).
The watchdog timer remains inactive unless the inhibit input is canceled.
(12) Canceling the inhibit input (setting the INH pin to “L” from “H”) restarts the watchdog timer.
(13) The reset signal is output when the power supply is turned off to set Vcc to Vsl or less.
(14) Equation of time-setting capacitances (Ctp and Ctw) and setting time:
tpr [ms) ≈ A × Ctp [μF]
twd [ms] ≈ B × Ctw [μF]
twr [ms] ≈ D × Ctp [μF]
Values of A, B and D
Product name
ELM7C3793xxxxA

A
750

B
1600

D
55

Setting example (When Ctp=0.1μF, Ctw=0.01μF)
Product nametpr[ms]twd[ms]twr[ms]

ELM7C3793xxxxA

75

16

5.5

■Marking
SOP-8

Symbol
a, b
c
d
e
f

SON8-3×3

Mark
0 to 9A or D
0 to 9
A to M (excepted I.)
0 to 9Content
Detection voltage
Output form
Last numeral of A.D.
Assembly month
Lot No.

Rev.1.4
10 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com■Application circuit example
1) Supply voltage monitor and watchdog timer (2 clocks monitoring)

5
2 CTW

VCC RESET 1
RESET

3 CTP

CK1 8

RESET

Vcc

Microprocessor 2

CK

CK
GND

GND

INH
6

GND
4

Vcc

Microprocessor 1

CK2 72) Supply voltage monitor and watchdog timer (1 clock monitoring)

5

VCC
2 CTW

RESET 1
RESET

3 CTP

Vcc

Microprocessor

CK1 8

CK
GND

INH
6

GND
4

CK2 7

Rev.1.4
11 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com

3) Supply voltage monitor and watchdog timer stop

5

VCC
6 INH

RESET 1RESET Vcc

RESET Vcc

2 CTW

CK1 8

3 CTP

Microprocessor1

Microprocessor2

CK

CK

HALT

GND
4

HALT
GND

GND

CK2 7

■Reference land pattern
SOP-8 208mil

7.45mm

1.27mm

0.60mm

1.75mm

SOP-8 150mil

Rev.1.4
12 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com■Typical Characteristics

Detection voltage (Vsh, Vsl) vs.
Operating ambient temperature characteristic
3.12

90

3.10

Watchdog timer monitoring�� (Vinh=0V)

80

Supply current Icc (�A)

Detection voltage Vsh, Vsl (V)Power supply current vs. Power supply voltage
100

70

60

50

40
30

When the watchdog timer
is stopped
�� (Vinh=Vcc)

20

f=1kHzDuty=10%CK1=CK2

10
0

7
6
5
4
3
2
Power-supply voltage Vcc(V)

1

3.08

3.06

3.04

3.02

2.98
2.96

-40 -20

8

Reset output voltage Vreset(mV)Reset output voltage Vreset(V)

Top=-40°C

Top=+25°C

Top=+85°C

900

800

600

Power-on reset hold time tpr(ms)Reset output voltage Vreset(V)543Top=+85°C

Top=+25°C

Top=-40°C

2

3

4

5

6

Top=-40°C

400

300

200
100
1

2 3 4 5 6 7 8 9Reset output current Ireset(mA)

10(When Vcc rising)200

Pull-up resistance 100k�1Top=+25°C

Power-on reset hold time vs.
Operating ambient temperature

Reset output voltage vs. power supply voltage
70

Top=+85°C

500

Reset output current Ireset(mA)

1(N-MOS side)at Vcc=3.3V

700

0-1 -2 -3 -4 -5 -6 -7 -8 -9 -10

2+20 +40 +60 +80 +100 +120

Reset output voltage vs. reset output current

1000

at Vcc=3.3V

60

Operating ambient temperature Top(°C)(P-MOS side)

0

Vsl

3.00

Reset output voltage vs. reset output current
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
1.9
1.8

Vsh

180

160

140

120

100

80

60

40
20
0

7

at Vcc=3.3V-40 -200+20 +40 +60 +80 +100 +120

Operating ambient temperature Top(°C)

Power supply voltage Vcc(V)Rev.1.4
13 / 14

ELM7C3793xxxxA CMOS voltage detector with dual input watchdog timer
http://www.elm-tech.com

26
24
22
20
18
16
14
12
10
8
6
4
2
0

at Vcc=3.3V

0-40 -20

Power-on reset hold time t��(ms)105

Watchdog timer monitoring time twd(ms)(When monitoring)+20 +40 +60 +80 +100 +120

26
24
22
20
18
16
14
12
10
8
6
4
2
0

Watchdog timer monitoring time vs.
Operating ambient temperature
at Vcc=3.3V-40 -200+20 +40 +60 +80 +100 +120

Operating ambient temperature Top(°C)

Operating ambient temperature Top(°C)

Power-on reset hold time vs. Ctp capacitance

Watchdog timer reset time vs. Ctp capacitance
104
Watchdog timer reset time tw�(ms)Watchdog timer reset time twr(ms)Watchdog timer reset time vs.
Operating ambient temperature

104
Top=-40°C

103102Top=+25°C

10
1
10-1

Top=+85°C

103

102
10
1

Top=-40°C

Top=+25°C-1

10Top=+85°C

10-2

10-4 10-3 10-2 10-11
10102Power-on reset hold time setting capacitance Ctp(�F)110-4 10-3 10-2 10-1
10102Power-on reset hold time setting capacitance Ctp(�F)

Watchdog timer monitoring time twd(ms)Watchdog timer monitoring time vs. Ctw capacitance104

103
Top=-40°C

102
10Top=+25°C

1
10-1
10-2

10-5

Top=+85°C

10-4 10-3 10-2 10-1
1
Watchdog timer monitoring time
setting capacitance Ctw(�F)

10

Rev.1.4
14 / 14