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Application Note

Multiplexers and Signal Switches Glossary

ABSTRACT
Table of Contents
1. Introduction to Multiplexers and Signal Switches

2. Operation of Multiplexers and Signal Switches

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

Signal switch
Multiplexer (Mux)
Analog switches and multiplexers
Protocol-specific switches and multiplexers
Precision
Protection
Low voltage
Mid voltage
Configuration
ChannelAbsolute maximum ratings
Recommended operating conditions
Single power supply
Dual power supply
Switch control signal levels (VIH, VIL)
Rail-to-rail
Input/Output voltage beyond supply
Bidirectional signal path

3. Additional Features

4. DC Characteristics•

1.8-V control logic•

On-resistance (RON)

•
•
•
•
•
•
•
•
•

Fail-safe logic
Injection current control
Integrated pulldown resistor on logic pin
Latch-up immunity
Overvoltage protection
Undervoltage protection
Fault Flag Indicators
Drain Response Output
Powered-off protection

•
•
•
•
•
•
•

On-resistance flatness (RON FLAT)
On-Resistance Mismatch between channels (ΔRON)
OFF leakage current (ID(OFF), IS(OFF))Powered-off I/O pin leakage current (IPOFF)
ON leakage current (ID(ON), IS(ON))
Control input leakage (ISEL or IEN)
Supply Current (IDD or ISS)

5. Dynamic Characteristics

6. Timing Characteristics

•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•

Off capacitance source and drain (COFF)On capacitance source and drain (CON)
Charge injection (QC)
Off-isolation (OISO)Channel-to-channel crosstalk (XTALK)
Bandwidth (BW)
Insertion Loss
THD + N

Transition time (tTRAN)
Device turn on time from enable pin (tON(EN) and tOFF(EN))
Break-before-make time (tOPEN (BBM))
Make-before-break time (tCLOSED (MBB))
Propagation delay through the switch (tpd)
Output-to-output skew (tSK)
Fault Response Time
Fault Flag Response Time
Drain Response Enable Time
Fault Recovery Time
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1 About This Multiplexers and Signal Switches Glossary
This glossary provides a brief overview and introduction to the terminology, features, and parameters for
TI'smultiplexers and signal switches for analog signal chain applications. The entire signal switches andmultiplexers portfolio can be found at www.ti.com/switches.
For components used to manage power rails and for applications that require a switch current of greaterthan 500mA, TI offers a power switch and power multiplexer portfolio which can each be found at www.ti.com/
powerswitch.

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Introduction to Multiplexers and Signal Switches

2 Introduction to Multiplexers and Signal SwitchesS

Signal switch — An integrated circuit (IC) used for connecting and disconnecting
an electrical circuit. For more information, see the Switches and muxes: What are
switches & multiplexers? training video from TI Precision Labs.

D

Figure 2-1. Ideal 1:1 SPST Switch
A0 A1

S1
S2

D

Multiplexer (Mux) — An integrated circuit that connects a selected signal path to asingle line.

S3
S4

Figure 2-2. Ideal 4:1 Mux
Analog switches and multiplexers — These devices are used for switching and multiplexing analog and digital signals up to 500 mA inapplications such as:
•
•
•
•
•
•
•
•

Precision Data Acquisition
GPIO Expansion
Diagnostics
System communication
Bus Isolation
System Protection
Power Sequencing
General-Purpose Signal Switching

Protocol-specific switches and multiplexers — These devices are defined to support specific protocol applications such as USB, HDMI,
LAN, MIPI, audio, memory and so forth.
Precision — These devices minimize offset error and signal distortion in a high-accuracy measurement system.
Protection — These devices isolate I/O signal paths and protect the system using powered-off, overvoltage and undershoot protection.
Low voltage — These devices support I/O signals ≤ ±25 V
Mid voltage — These devices support I/O signals > ±25 V
Configuration — Defines the number of signals that can be selected. Table 2-1 shows the typical configurations.
Channel — Defines the number of configurations (circuits) in a single device. Table 2-1 shows the 1- and 2- channel configurations, but the
number of channels may exceed 2.

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Table 2-1. Configurations and Channels
1-Channel

S

1:1

2:1

2-Channel
S1

D1

S2

D2

D

S1

S1A
D1

D

S1B

S2

S2A
D2
S2B

S1A
S1B

D1

S1

S1C

Configuration

3:1

S2

D

S2A
S3

S2B

D2

S2C

S1A
S1B
D1
S1

S1C

S2

4:1

S1D
D
S2A

S3

S2B

S4

D2
S2C
S2D

S1A
S1B

S1C
S1D
D1
S1

S1E

S2

S1F

S3

S1G
S1H

S4

Configuration

8:1

D
S5

S2A

S6

S2B

S7

S2C

S8

S2D
D2
S2E
S2F

S2G
S2H

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Introduction to Multiplexers and Signal Switches

Table 2-1. Configurations and Channels (continued)
1-Channel

2-Channel

S1
S2

S3
S4

S5
S6

S7
S8

Configuration

D

16:1

N/A

S9
S10

S11
S12

S13
S14

S15
S16

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3 Operation of Multiplexers and Signal Switches
Absolute maximum ratings — These are stress ratings only, which do not imply functional operation of the device at these or any otherconditions beyond those indicated under the Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability. Stresses beyond those listed under the Absolute Maximum Rating may cause permanent
damage to the device.
Recommended operating conditions — The operating conditions for which the device has been characterized.

VDD (+V)

Single power supply — Device with only positive power supply pins withreference to ground. The voltage applied is labeled as VDD, VCC, V+ and soforth.
Dual power supply — Device with positive and negative supply pins withreference to ground. Voltage applied at the positive pin is labeled as VDD, VCC,
V+, and so forth, and at the negative pin is labeled as VSS, VEE, V-, and soforth.

SingleSupply:Dual
Supply:GND

VSS (-V)

Figure 3-1. Single and Dual Supply
V DD

Log ic³HIG H´

Switch control signal levels (VIH, VIL) — Voltage levels required on thecontrol pins (EN, SEL, IN, and so forth) required for the switch to change theinternal signal path.
•
•

VIH

VIH – The minimum voltage for the input control signal to achieve a logic"1"high value
VIL – The maximum voltage for the input control signal to remain a logic"0"low value

VIL
Log ic³LOW´
GND

Figure 3-2. Switch Control Signal Levels

VDD

VI/O

Rail-to-rail — A common term meaning that a device will support VI/O voltage
range between the most positive and most negative power supply rails.
0V
(GND)
t

Figure 3-3. Rail-to-Rail
VI/O(MAX)
VDD

Input/Output voltage beyond supply – The switch can support voltage range
beyond the supply rail to VI/O(MAX)as indicated by the recommended operating
conditions.

0V
(GND)
t

Figure 3-4. I/O Voltage Beyond Supply

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Operation of Multiplexers and Signal Switches
A0

A1

S1

S2

Bidirectional signal path – The switch conducts equally well from source(S) to drain (D) or from drain (D) to source (S). Each channel has very
similar characteristics in both directions and supports both analog and digital
signals. TI analog switches and multiplexers are typically bidirectional. See theSwitches and muxes: Are switches & multiplexers bidirectional? training videofrom TI Precision Labs.

D
S3

S4

Figure 3-5. Bidirectional Signal Path

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4 Additional Features
1.8-V Control Logic – Switches with this feature have a built-in voltage translator to prevent voltage mismatch between the supply rail andthe control logic. VIH and VIL levels are compatible with the 1.8-V logic levels at any voltage supply. See the Simplifying Design With 1.8 V
logic MUXes and Switches Tech Note for more information.
VDD = 0 V

VDD

VCC = 5 V
Protection

VSEL

Fail-Safe Logic – Ensures the switch stays off andthe voltage on the logic pin (VSEL) does not backpower VDD when VSEL is greater than VDD. See theSwitches and muxes: What is fail-safe logic? training
video from TI Precision Labs.

0V
Subsystem
A

SEL

S

D

High-Z

Subsystem
B

Figure 4-1. Fail-Safe Logic

Injection Current Control — Devices with Injection
Current Control shunt injected current on disabled(high-Z) signal pathways to ground. This mitigateserror on the active signal pathway as the injectedcurrent is going into the ground rail and not thepower rail. See the Switches and muxes: Preventcrosstalk with injection current control training videofrom TI Precision Labs.

S1

D
Control
Circuitry

S2
Control
Circuitry+±

Figure 4-2. Injection Current Control

VDD
D

S

Integrated Pulldown Resistor on Logic Pin –Internal weak pulldown resistors to GND to ensure
the logic pins are not floating.

EN

GND

Figure 4-3. Integrated Pulldown Resistor on Logic Pin

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Additional Features

Gate

Gate

GND

n+

n+

p-epi

p+

p+

n+

n-wellTrench Oxidep+

Trench Oxide

Trench Oxide

Latch-Up Immunity – Devices that are latch-up
immune can use various methods to achieve latch up
immunity such as being built in a Silicon On Insulator(SOI) process, employing the use of guard rings,
or a mix between different methods. When thesemeasures are taken Electrical Overstress, Electrically
Fast Transients, and Injected Currents will not cause
latch up in these devices. See the Switches andmuxes: What is latch-up immunity? training videofrom TI Precision Labs.

VDD

PMOS

NMOS

Buried Oxide Layer (Insulator)
Substrate (p) / Handle

Figure 4-4. Latch-Up Immunity With SOI Process

VI/O(MAX)

Overvoltage Protection – When the input voltage
VI/O exceeds the defined threshold voltage, VTH
or VT, the switch enters the high impedancestate, isolates signal path, and protects downstream
components. Depending on device the threshold candetermined in 1 of 3 ways.
•••

FIXED Threshold

VI/O(MAX)

Supply (VDD)
ThresholdVI/O(MAX)

Switch“OFF”

Switch“OFF”

Switch
“OFF”

VI/O

VI/O
VOFF
VDD

VTH

Fixed Threshold
Threshold = Supply
Threshold = Configurable

Supply (VFP)
Threshold

VI/O
VOFF
VFP

VT

Switch“ON”

Switch“ON”

Switch“ON”

VI/O(MIN)

VI/O(MIN)VT

VI/O(MIN)

Figure 4-5. Overvoltage Protection
Undervoltage Protection – When the input voltage
VI/O falls below the defined threshold voltage, VTH,
the switch enters the high impedance state, isolates
signal path, and protects downstream components.
Depending on device the threshold can determinedin 1 of 2 ways.
••

Threshold = Supply
Threshold = Configurable

VI/O(MAX)

Supply (VSS)
Threshold

Supply (VFN)
ThresholdSwitch“ON”

Switch
“ON”

VI/O

VSS
VOFF

VFN
VOFF

VT

VT

VI/O

VSS

Switch“OFF”

Switch“OFF”
VI/O(MIN)

This feature typically exists alongside Overvoltage
Protection

Figure 4-6. Undervoltage Protection
VDD

1k

Fault Flag Indicators – On some devices there isa fault flag pin that will change states (typically fromhigh to low) when a fault is present on the device
and will return to its default state when the fault iscleared.

SwitchFLAG

MCU / ASIC+-

Figure 4-7. Fault Flag Indicators

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VDD

VFP

VDD

FAULT

Drain Response Output – On some protection
switches/multiplexers the output response of adevice during a fault condition can be set to either
clamp to supply or open circuit the output.

VFP

40k

FAULT

DR = Low

Vs
DR

VSS

DR = Float or High

Vs

Z

DR

Open Circuit When Fault
OccursZ

Clamp to Fault Supply(VFP if OV, VFN if UV)

VFN

VSS

VFN

Figure 4-8. Drain Response Output
VDD = 0 V

VDD

Powered-Off Protection – Protects switch andisolates signal path when signals are present at theI/O pins and VDD = 0 V. See the Switches andmuxes: Simplify power sequencing with powered-off
protection training video from TI Precision Labsand
the Eliminate Power Sequencing With Powered-off
Protection Signal Switches Tech Note for more
information.

VCC = 5 V
Pro tection
SEL

VS
Sub system 0 V
A

ISS

High-ZD

Sub system
B

Figure 4-9. Powered-Off Protection

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DC Characteristics

5 DC Characteristics
For more parameter information, see the device data sheet.
VDD

RON

S1

On-Resistance (RON) — The resistance of the switch pathway when theswitch pathway is closed (low impedance). The resistance varies withtemperature, supply voltage, and input voltage with respect to ground.

D1

+

VS

RL

Switch ON±

RON FLAT ( )Figure 5-1. On-Resistance

On-Resistance Flatness (RON FLAT) — Difference between the maximum
and minimum value of Ron in a channel over the VD or VS voltage range(w.r.t. ground).

Flatness

VD or VS (V)Figure 5-2. On-Resistance Flatness
VDD

S

D
R_ON1

Vs

On-Resistance Match Between Two Channels (ΔRON ) – Difference
between On-Resistance of two different switch pathways at the same input
voltage

S

D
R_ON2

VS

Channel Mismatch : [R_ON1 – R_ON2]

Figure 5-3. ΔRON
VDD

S1OFF leakage current (ID(OFF), IS(OFF)) — Leakage current measured at the
input port, with the corresponding channel output in the OFF state underworst-case input and output conditions.

VS

+

S

Hi-Z

D

D1

ID(OFF)
RL±

Switch OFF

Figure 5-4. OFF Leakage Current

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0V

Protection
IPOFF

S1

Powered-off I/O pin leakage current (IPOFF) — The leakage current flowing
into or out of the source pin when the device is powered off (VDD = 0V).

VS

S Hi-Z D

D1

+

RL

±
Switch OFF

Figure 5-5. Powered-Off I/O Pin Leakage
Current
VDD

IS

ON leakage current (ID(ON), IS(ON)) — Leakage current measured at the input
port in the ON state, with the corresponding output port in the ON state andthe output being open.

VS

S1

S

ON D

D1

ID

ID(ON)or
IS(ON)+±

RL

Switch ON
IS • ,D

Figure 5-6. ON Leakage Current
VDD

S Hi-Z D

S1

D1

EN

Control input leakage (ISEL or IEN) — Leakage measured at the switch
control pins.

VSEL
or
VEN

ISEL
or
IEN
Switch OFF

Figure 5-7. Control Input Leakage
IDD

VDD

Switch/Multiplexer

Supply Current (IDD or ISS) – The supply current is the amount of current
that is sourced from/sunk into the supply pins. IDD refers to current into the
VDD pin and ISS refers to current into the VSS pin.

ISS

VSS

Figure 5-8. Supply Current

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Dynamic Characteristics

6 Dynamic Characteristics
For detailed information of dynamic characteristics, see the Multiplexers: Bandwidth, Channel-to-Channel
Crosstalk, Off-Isolation and THD+Noise training video from TI Precision Labs.
For more parameter information, see the device data sheet.
VDD

S1

Off capacitance source and drain (COFF) — The capacitive loadingwhen a switch path is in the high-impedance state.

D1

S Hi-Z D
COFF

RL

VS
Switch OFF

Figure 6-1. Source and Drain Off Capacitance
VDD

S1

Vs

On capacitance source and drain (CON) — The capacitive loading whena switch path is in the low-impedance state.

S

D1

D

SWITCH “ON”
CON/2

RL
CON/2

Figure 6-2. Source and Drain On Capacitance

Charge injection (QC) — Charge injection is a measurement of unwanted
signal coupling from the control (EN) input to the analog output. This ismeasured in coulomb (C) and measured by the total charge induced due
to switching of the control input.

Figure 6-3. Charge Injection

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VDD
VS1

VD1
S

S1

Off-isolation (OISO) — A measurement OFF-state switch impedance. Thisis the ratio of VD1 to VS1 measured in dB at a specific frequency, with thecorresponding channel in the OFF state.

Hi-Z

D

D1

RL

VS
Switch OFF

Figure 6-4. Off-Isolation
VDD
VS1
S1

VS1

S

ON D

D1

+

RL

±

Channel-to-channel crosstalk (XTALK) — A measurement of unwanted
signal coupling from an ON channel to an OFF channel. This is the ratio of
VS2 to VS1 measured in dB at a specific frequency.

VS2

VS2

S2

S Hi-Z D

D2

+

RL

±

XTALK =

Magnitude (dB)Figure 6-5. Channel-to-Channel Crosstalk

Bandwidth (BW) — The frequency range of signals that can pass throughthe switch with no more than 3 dB of attenuation from the DC gain ( 0 Hz).

í3 dB
Ban dwidth

Freque ncy (Hz)Figure 6-6. Bandwidth

VOut

VS

Insertion Loss - The loss through the switch with predefined load acrossfrequency. Since the switch is more than just a resistor when closed there
is frequency dependent loss associated with the switch - this is defined byInsertion Loss

Rs

Vin

Switch ON

RL

CL

Inseron Loss IL = 20log(VOut/Vs)

Figure 6-7. Insertion Loss

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Dynamic Characteristics
VDD

VSS

VDD

VSS

0.1 µF

Total Harmonic Distortion + Noise (THD+N) Also called Sine Wave Distortion – this parameter looks at the harmonic
content introduced by the switch and is defined by summing all nonfundamental harmonics RMS amplitudes + the noise floor and dividing
it by the RMS amplitude of the fundamental frequency. This parameter iscommonly expressed as a percentage.

0.1 µF

Audio Precision
S1

40 Ÿ
D

VOUT
VS

RL

Other
Sx pins50Ÿ

GND

Figure 6-8. THD + N

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7 Timing Characteristics
For detailed information, see the Switches and muxes: What are timing characteristics? training video from TI
Precision Labs.
For more parameter information, see the device data sheet.
VDD

S1

S

ON

D

D1

+

VS

RL

±

SEL
Switch ON

VSELTransition time (tTRAN) — The time taken by the switch output to rise or fallwithin a given percentage of the final value after the address signal has risen
or fallen past the logic threshold.

VDD
VIH

VSEL

VIL
0V

tTRAN
VS

90%

VD1
10%
0V

Figure 7-1. Transition Time
VDD

S1
VS

S

ON

D1

D

EN

+

RL

±

Switch ON
VEN

Device turn on time from enable pin(t ON(EN) and t OFF(EN) ) — The time taken by the switch output to rise or fallwithin a given percentage of the final value after the enable has risen or fallen
past the logic threshold.

VDD
VEN

VIH
VIL

0V

tON (EN)
VS

90%

tOFF (EN)
90%

VD1
0V

Figure 7-2. Device Turn on Time From Enable
Pin

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Timing Characteristics
VDD

S1A

S

D

D1

+

VS

RL

±

S

S1B

CL

D

SEL
VSEL

Break-before-make time (tOPEN (BBM)) — Ensures that in a multiplexer, twomultiplexer paths are never electrically connected when the signal path ischanged by the select input.

VDD
VSEL
0V
VS

90%

VD1

tBBM1

0V

tBBM2

tOPEN (BBM) = min ( tBBM1, tBBM2)

Figure 7-3. Break-Before-Make Time
VDD

S1

VS

S

D1A

D

+

RL

CL

RL

CL

±

S

D 1B

D

SEL

VSEL

Make-before-break time (tCLOSED (MBB)) — Ensures that in a multiplexer, twomultiplexer paths are never electrically disconnected when the signal path ischanged by the select input.

VDD
VSEL

0V

VIH

VS

90%

VD1A
0V
VS
VD1B

0V

90%

tCL OS ED (MBB)

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VDD

S1

S

D1

ON D

+

VS

±

RL

Switch ON

VS
VS1

Propagation delay through the switch (tpd) — The time required for a
signal to pass from the input signal pin to the respective output signal pin.

50%

50%

tPD 1

tPD 2

50%

50
%

0V

VS
VD1
0V
tpd = max ( tPD 1, tPD 2)

Figure 7-5. Propagation Delay Through the
SwitchFigure 7-6. Output-to-Output Skew
VDD

S

S1

D1

+

VS

RL

±

S

S2

Output-to-output skew (tSK) — The maximum difference between the
propagation delays of different outputs due to different internal paths.

ON D

ON D

D2

+

VS

RL

±

Switches ON

VS
VD1

50%

50%

0V
tSK1

tSK2

VS
VD2

50%

50%

0V
tSK = max ( tSK1, tSK2)
VSS

VFP

0.1 µF0V

0.1 µF
VDD

GND

VFN

GND

VFP + 0.5 V
VSVS

0.1 µF

VFN - 0.5 V

Fault Response Time (tRESPONSE) - Fault response time (tRESPONSE)
measures the delay between the source voltage exceeding the fault supply
voltage (VFP or VFN) by 0.5V and the drain voltage failing to 90% of the fault
supply voltage exceeded. This only applies to Fault Protected Devices.

0.1 µF

0V
tRESPONSE (FP)
VFP
Output

VFP × 0.5

Sx

Output

VFN × 0.5
VFN

0V

VDD VSS

GND

tRESPONSE (FN)0V

VFP VFNSW

GND
Dx

All othersource &drain pinsVS
GND

tRESPONSE = max ( tRESPONSE(FP), tRESPONSE(FN))

Output

RL

CL

GND

GND

GND
GND

Figure 7-7. Fault Response Time18

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Timing Characteristics
VSS

VFP

0.1 µF0.1 µF
VDD

GND
0V

Fault Flag Response Time (tRESPONSE(FLAG)) - Fault flag response time
(tRESPONSE(FLAG)) measures the delay between the source voltage exceeding
the fault supply voltage (VFP or VFN) by 0.5 V and the general fault flag (FF)pin to go below 10% of its original value. This only applies to devices with an
FF pin.

VS

0.1 µFVDD VSSGND

VFN - 0.5 V
0V

GND
Dx

tRESPONSE(FLAG)_FN

5V

5V

VFF

VS

VFF

All othersource &drain pins

GND

0.5 V

0V

VFP VFNSW

SxtRESPONSE(FLAG)_FP

GND

0.1 µF

VFP + 0.5 V
VS

VFN

0.5 V

0V

tRESPONSE(FLAG) = max ( tRESPONSE(FLAG)_FP, tRESPONSE(FLAG)_FN)

RL

CL

GND

GND

5V
RPU

FF

GND

CL_FF

GND

GND

Figure 7-8. Fault Flag Response Time
VSS

VFP

0.1 µF0.1 µF
VDD

GND
3V

VFN

GND

3V
0.1 µF

VDR

Fault Drain Enable Time (tRESPONSE(DR)) -tRESPONSE(DR) represents thedelay between the voltage at the DR pin falling from a high to low signal andthe output of the drain pin reaching 90% of the fault supplies (VFP or VFN).
tRESPONSE(DR) is a measure of how quickly the internal pull-up engages in
response to the DR pin. Only on devices with a DR pin.

VDR

1.5V

1.5V

VFP VFNSW

Sx

0V
tRESPONSE(DR)_FP

GND
Dx

tRESPONSE(DR)_FN
VS

0V

VFP

0.1 µFVDD VSS

GND

RL

CL

GND

GND

VFP x 0.9
Output (VD)

Output (VD)

GND

0V

VFN x 0.9

VFN

All othersource &drain pinsDR
VDR

tRESPONSE(DR) = max ( tRESPONSE(DR)_FP, tRESPONSE(DR)_FN)

GND

GND

GND
VS > VFP + VT (to measure tRECOVERY(DR)_FP) or
VS < VFN - VT (to measure tRECOVERY(DR)_FN)

Figure 7-9. Fault Drain Enable Time

Fault Recovery Time (tRECOVERY) Fault recovery time (tRECOVERY) measures the delay between the source
voltage falling from overvoltage condition to below fault supply voltage (VFPor VFN) plus 0.5 V and the drain voltage rising from 0V to 50% of the fault
supply voltage exceeded (only on fault protected devices).

Figure 7-10. Fault Recovery Time
VSS

VFP

0.1 µF0.1 µF
VDD

GND

VFN

GND

0V
0.1 µF
VFP + 0.5 V

Fault Flag Recovery Time (tRECOVERY(FLAG)) – Fault flag recovery time
(tRECOVERY(FLAG)) measures the delay between the source voltage falling fromthe overvoltage condition to below the fault supply voltage (VFP or VFN) plus
0.5 V and the general fault flag (FF) pin to rise above 3 V with 5 V external
pull-up (only on devices with fault flags).

VS
0V

5V

Sx

0V

3V

VFF

VFP VFN
SW

GND
Dx

VS

5V
3V

VDD VSS

GND

tRECOVERY(FLAG)_FN

tRECOVERY(FLAG)_FP

VFF

0.1 µF

VFN - 0.5 V

VSAll othersource &drain pins

GND

0V
tRECOVERY(FLAG) = max ( tRECOVERY(FLAG)_FP, tRECOVERY(FLAG)_FN)

RL

CL

GND

GND

5V
RPU

FF

GND

GND

CL_FF
GND

Figure 7-11. Fault Flag Recovery TimeSLLA471B – JUNE 2021 – REVISED DECEMBER 2021
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Multiplexers and Signal Switches Glossary
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19

Revision History

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8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2021) to Revision B (November 2021)
Page• Added Undervoltage protection topic..................................................................................................................8• Added Fault Flag Indicators topic....................................................................................................................... 8• Added Drain Response Output topic.................................................................................................................. 8• Added On-Resistance Mismatch between Channels topic............................................................................... 11• Added Supply Current topic.............................................................................................................................. 11• Added Insertion Loss topic............................................................................................................................... 13• Added THD + N topic........................................................................................................................................13• Added Fault Response Time topic....................................................................................................................16• Added Fault Flag Response Time topic............................................................................................................16• Added Drain Response Enable Time topic.......................................................................................................16• Added Fault Recovery Time topic.....................................................................................................................16• Added Fault Flag Recovery Time topic.............................................................................................................16
Changes from Revision * (March 2020) to Revision A (June 2021)
Page• Updated the numbering format for tables, figures and cross-references throughout the document...................3

20

Multiplexers and Signal Switches Glossary

SLLA471B – JUNE 2021 – REVISED DECEMBER 2021
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