An Intel 3 Advanced FinFET Platform Technology for High
Performance Computing and SOC Product Applications
Walid M. Hafez, D. Abanulo, M. Abdelkader, S. An, C. Auth, D. Bahr, V. Balakrishnan, R. Bambery, M. Beck, M. Bhargava, S. Bhowmick, J. Biggshouck, J. Birdsall, D. Caselli, H.-Y. Chang, Y. Chang, R. Chaudhuri, S. Chauhan, C. Chen, V. Chikarmane, K. Chikkadi, T. Chu, C. Connor, R. De
Alba, Y. Deng, C. Destefano, D. Diana, Y. Dong, P. Elfick, T. Elko-hansen, B. Fallahazad, Y. Fang, D. Gala, D. Garg, C. Geppert, S. Govindaraju, W.
Grimm, H. Grunes, L. Guler, Z. Guo, A. Gupta, M. Hattendorf, S. Havelia, J. Hazra, A. Islam, A. Jain, S. Jaloviar, M. Jamil, M. Jang, M. Kabir, J.
Kameswaran, E. Karl, S. Kelgeri, A. Kennedy, C. Kilroy, J. Kim, Y. Kim, D. Krishnan, G. Lee, H.-P. Lee, Q. Li, H. Lin, A. Luk, Y. Luo, P. Macfarlane,A. Mamun, K. Marla, D. Mayeri, E. Mckenna, A. Miah, K. Mistry, M. Mleczko, S. Moon, D. Nardi, S. Natarajan, J. Nathawat, C. Nolph, C. Nugroho,P. Nyhus, A. Oni, P. Packan, D. Pak, A. Paliwal, R. Pandey, I. Paredes, K. Park, L. Paulson, A. Pierre, P. Plekhanov, C. Prasad, R. Ramaswamy, J.
Riley, J. Rode, R. Russell, S. Ryu, H. Saavedra, T. Salisbury, J. Sandford, F. Shah, K. Shang, P. Shekhar, A. Shu, E. Skoug, J. Sohn, J. Song, M.
Sprinkle, J. Su, A. Tan, T. Troeger, R. Tsao, A. Vaidya, C. Wallace, X. Wang, H. Wang, C. Ward, S. Wickramaratne, M. Wills, T. Wu, Z. Xia-hua, S.
Xu, P. Yashar, J. Yaung, Y. Yu, M. Zilm, B. Sell

Foundry Technology Development, Intel Corporation, Hillsboro, Oregon, USA, Contact: walid.m.hafez@intel.com

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2024 IEEE VLSI Symposium on Technology and Circuits

Slide 0Outline• Intel 3 – Technology Family Overview• Technology Performance and Basic Design Rules• Transistor and Interconnects• Summary

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2024 IEEE VLSI Symposium on Technology and Circuits

Slide 1Outline• Intel 3 – Technology Family Overview• Technology Performance and Basic Design Rules• Transistor and Interconnects• Summary

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2024 IEEE VLSI Symposium on Technology and Circuits

Slide 2

Intel Technology Scaling
Performance Per Watt

Angstrom Era
EUV Litho

Super
MIM Capacitor
COAG

First
FinFET

Hi-K
Metal Gate

StrainedSilicon

Intel
90nm

Intel
65nm

Intel
32nm

Intel
45nm

Intel
22nm

Intel
14nm

Intel
10nm

Intel
10nm

Intel

7Intel4

Increasedtransistor
drive current

Transistor
optimization
forperformance
Metal stackenhancements

Enhanced
FinFET

3

Denser design
libraries

SuperFin
Enhanced
FinFETIntel

Dense Routing

Intel

20A
RibbonFET+ PowerVia

Intel18A
Ribboninnovation
increased
performance
Continued
metallinewidthreduction

Reduced via
resistance
Increased useof EUV

Enhanced
HKMG

Enhanced Strain

2011

20002021

2024*Graphics for illustrative purposes only and not to scale.

TimeKey performance booster post 2000  Strain Si, HKMG, FinFET, DTCO, PowerVia, RibbonFETT1-1

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Slide 3

5 Nodes in 4 Years

EUV LithoRibbonFET + PowerVia

Denser design libraries
Increased transistor drive current
Increased use of EUVT1-1

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Slide 4

Intel 3 Technology Roadmap

Performance

LibraryFeatures

Applications

Intel 4

Intel 3 Base

FeatureExpansion

Performance
Enhancement

1x (ref)

Up to 1.18x Perf/watt vs Intel 4

Up to 1.18x Perf/watt vs Intel 4

Enhanced Performance& Ease of Use

240nm HighPerformance

240nm High Performance
210nm High Density

240nm High Performance
210nm High Density

240nm High Performance
210nm High Density

Through Si Via Support

1.2V Native, Deep N-well,Long channel analog devices

Builds on Intel 3-E, adds 9um
pitch TSV & Hybrid bonding

Server, Client,Base-die

Chipsets, Storage

Optimized for AI/HPC
applications & generalcomputeIntel 3 expanding technology features to support wide range of design applications
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Slide 5

Products(formerly codenamed Sierra Forest)(formerly codenamed Granite Rapids)Intel 3 is in High Volume Manufacturing with multiple products
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Slide 6

Outline• Intel 3 – Technology Family Overview• Technology Performance and Basic Design Rules• Transistor and Interconnects• Summary

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Slide 7

Intel 3 Power Performance Area
Total Power (Normalized)

PPA for Intel Standard Core
5Intel 3 is optimized for HPC applications
to support both low voltage (<0.65V) and4Intel 4high voltage (>1.3V) operation240nm HP

3Intel 3
2210nm HD~18%



Performance harvested from transistor
and interconnect improvements andprocess/design co-optimizations

1
2.5

3

3.5

4

4.5

5

Frequency (GHz)Intel 3 provides up to 18% iso-power performance gain over Intel 4
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Slide 8

Intel 3 Supported Libraries
Intel 4Intel 3

Key Technology Dimensions

210 HD library

240 HP library

240 HP library

Wide M030nm
fin pitch
1 dg

Wide M0Intel 4Intel 3

Contacted Poly Pitch (nm)5050

Fin Pitch (nm)3030

M0 Pitch (nm)3030

HP Library Height (nm)240240/210

Library Height x CPP (nm2)

12K

12K/10.5K

Gen Diffusion breakFin
Poly
S/D contact

Intel 3 offers high performance (240H) and high density (210H) std cells
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Slide 9Intel 3 Interconnect Stacks
Layer
M0
M1
M2
M3
M4
M5-M6
M7-M8
M9
M10
M11
M12
M13
M14M15M16M17-M18
Top Metal 0
Top Metal 1Intel 4
18ML*305045504560849898
130130160160280--1080
4000

Pitch (nm)Intel 314ML*
18ML*303050504242505042426060848498
98
9898
160
130-130-160-160-280----1080
1080
4000
4000

21ML*30504250
4260
8484849898
130130160160280
1080
4000

Intel 3 metal stacks (count includes M0):
14ML  Optimized for cost
18ML  Intel 4, balanced
performance/cost
21ML  Optimized for performance
M1-M6 enhanced RC vs Intel 4* count includes M0

Interconnect stack options to optimize for performance and cost
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Slide 10

Outline• Intel 3 – Technology Family Overview• Technology Performance and Basic Design Rules• Transistor and Interconnects• Summary

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Slide 11

FEOL Oscillator Performance

15% ring oscillator frequency improvement over Intel 4
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Slide 12

Improved Transistor Electrostatics
PMOS
VT [V]VT [V]

FinFinNMOS

Improved Fin width/profile

Straighter fin profile and introduction of dipole
work-functions to optimize low-power performance
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Slide 13

Improved Transistor Contact Integration

ContactContactGate
ViaGateViaGateGate

Contact Line ResistanceIntel 3Intel 4Intel 4Intel 3~20%~25%

COV (Overlap Capacitance)

Contact optimization on Intel 3 versus Intel 4 provides lower resistance and capacitance
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Slide 14

Logic Transistor I-V Characteristics
0.70V

0.70V

PMOS

PMOS

NMOS

NMOS
0.05V

0.05V

VGS=0.7V
VGS=0.6V

SS~71mV/dec
DIBL ~55mV/V

SS~68mV/dec
DIBL ~50mV/V

VGS=0.5V

Ioff = 8nA/um

Well controlled transistor I-V characteristics:
 DIBL 55mV/V (NMOS), ~50mV/V (PMOS)
 Subthreshold slope improved by 5-7mV compared to Intel 4
 Intel 3 offers 5x lower leakage at same drive current as Intel 4
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Slide 15

Front End Logic Reliability
BTI

Gate Oxide TDDBIntel 4NP

Intel 4

Intel 4
Intel 3

NIntel 4Intel 3

Intel 3PIntel 4Intel 3Intel 3

Hot carrier

FrequencyNIntel 4Intel 3

Normalized HCIIntel 3Normalized HCIIntel 4PIntel 3 transistor reliability vs Intel 4:• Gate Oxide TDDB  Improved• BTI  Improved• Hot Carrier  Intrinsically Improved

Frequency

Intel 3 front reliability matched/better compared to Intel 4 with improved performance
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Slide 16

1.2V High Voltage Device

NMOS VT vs Drive Current

PMOS VT vs Drive Current

CPP: 100nm
Gate length: 65nm

Native 1.2V IO device to support higher voltage applications
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1.2V High Voltage ReliabilityNative 1.2V IO device reliability specs meeting industry standard 10-year goals
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Slide 18

Interconnect RC Improvement
Intel 4CapacitanceIntel 4
Intel 3/-T/-E

Intel 3/-T/-E

Intel 3-PT

Intel 3-PT

1/ResistanceInterconnect resistance and capacitance optimized with improved ILDs and liners
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Slide 19

Outline• Intel 3 – Technology Family Overview• Technology Performance and Basic Design Rules• Transistor and Interconnects• Summary

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Slide 20

Intel 3 Summary• Transistor/interconnect improvements and DTCO deliver a full node ofperformance over Intel 4– Up to +18% frequency @ iso-power• Expanded offerings to support node longevity for foundry applications:– TSV enablement for advanced 3DIC packaging options (Intel 3-T)
– 1.2V I/O transistors, deep N-well isolation, long channel analog devices (Intel 3-E)
– Further performance enhancements and Ease of Use in development (Intel 3-PT)• Intel 3 is in high volume manufacturing for multiple products

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Slide 21

Intel Legal Notices

All product and service plans, and roadmaps are subject to change without notice. Any forecasts of products, services or technologies needed for Intel's operations areprovided for discussion purposes only. Intel will have no liability to make any purchase in connection with forecasts published in this document. Code names are often
used by Intel to identify products, services or technologies that are in development and usage may change over time. Product, service and technology performancevaries by use, configuration and other factors. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
Learn more at www.Intel.com/PerformanceIndex and www.Intel.com/ProcessInnovation.
Reference to research results, including comparisons to products, services or technology performance are estimates and do not imply availability. The products andservices described may contain defects or errors which may cause deviation from published specifications. Current characterized errata are available on request. Intel
disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and noninfringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Statements in this document that refer to future plans orexpectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual
results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially,see our most recent earnings releases, annual report on form 10-K and other SEC filings at www.intc.com.
© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as theproperty of others. This document contains information on products and technologies in development.

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Slide 22