ISSUE 1, 2024

Fixed-frequency DCS-Control:
Fast transient response withclock synchronization
A novel charge-mode control
algorithm for PFC
Redundant supply topologies
for automotive applications
using ideal diode controllers
Low-EMI designs for isolated
ADC signal-chain solutions
Solving AC dropout recovery ina high-density, GaN-optimized
PFC converter

Table of contents

02
novel charge-mode control
08 Aalgorithm
for PFC
This article introduces a new control concept for
power factor correction (PFC): instead of controllingthe inductor current (input current) directly, theelectric charge delivered to PFC output in eachswitching cycle is controlled.

supply topologies for
12 Redundant
automotive applications using ideal
diode controllers

This article discusses the concept and benefitsof ORing and Power Muxing using ideal diodecontrollers, the different types and architecturesof circuits, and the challenges and solutions for
implementing these techniques using ideal diodecontrollers in automotive systems.

Fixed-frequency DCS-Control:
Fast transient response with clock
synchronization
Features such as differential remote sensing, external controlloop compensation and stackability support the demandingtransient requirements of higher-current processors found innoise-sensitive applications, including automotive infotainment
and advanced driver assistance systems (ADAS). This article
provides an overview of the fixed-frequency DCS-Control
topology, discussing its excellent transient response, constantand synchronize-able switching frequency, lower-ripple powersave mode, and stackability for higher currents.

designs for isolated ADC
20 Low-EMI
signal-chain solutions
This article explains the sources of EMI – specificallyradiated emissions – and presents techniques tominimize EMI for an analog signal chain, including
detailed layout examples and measurement results.

AC dropout recovery in a high27 Solving
density, GaN-optimized PFC converter
To address the need for cost effective solutions toimprove power factor correction (PFC) light load andpeak efficiency while shrinking passive components,
this article discusses a unique GaN-based, highdensity design using two-phase, integrated triangularcurrent mode PFC.

ISSUE 1, 2024

Analog Design Journal

Fixed-frequency DCS-Control: Fasttransient response with clock
synchronization
Chris Glaser
Senior Member, Technical Staff
control loop for proper regulation. The VOS pin provides

Introduction

the topology’s fast transient response by directly feeding

A common drawback with constant on-time (COT)

the output voltage into a ramp and then into thecontrol topologies is the switching frequency variationcomparator, where it immediately affects the operating

and inability to synchronize to an external clock. TI’s

point. The FB pin is a lower-bandwidth path that provides

fixed-frequency direct control with seamless transition

highly accurate DC setpoint regulation. When combined

into power save mode (fixed-frequency DCS-Control)in DCS-Control, the VOS pin’s AC path and FB pin’s

topology builds on the popular COT DCS-Control

DC path provide an accurate output voltage that also

topology with its fast transient response, and adds

responds quickly to load transients.

an oscillator to achieve fixed-frequency operation with
optional clock synchronization. This combination enables
applications that require both a fast transient response

Gate
DriverControland have specific noise or frequency requirements.
Other features such as differential remote sensing,external control-loop compensation and stackability

VOS

Direct Control
andCompensation

Ramp

support the demanding transient requirements of highercurrent processors found in noise-sensitive applications,

FB

including automotive infotainment and advanced driver–+assistance systems (ADAS), communications equipment

Comparator

Timer (t ON_mi n )Error
Amplifier

VREF
0.8V

DCS-Control Topology

optical modules, industrial test and measurement,
medical, and aerospace and defense. This article

Figure 1. Block diagram of the DCS-Control topology.

provides an overview of the fixed-frequency DCS-Control

A COT topology such as DCS-Control sets the on-time

topology, discussing its excellent transient response,with a timer. By adjusting this on-time with the input andconstant and synchronize-able switching frequency,

output voltage, the timer gives a reasonably constantlower-ripple power-save mode, and stackability for higher

frequency operation for most duty cycles in pulse-widthcurrents.

modulation (PWM) mode. Equation 1 shows an example,
where 416ns is the period for a 2.4MHz switching

DCS-Control topology overview

frequency:

Figure 1 shows the basic block diagram of the DCSControl topology [1]. Both the output-voltage senseV

tON = VOUT × 416ns
IN(VOS) and feedback (FB) pins provide the inputs to theFixed-frequency DCS-Control: Fast transient response with clock synchronization

2(1)

ISSUE 1, 2024

Analog Design Journal
However, the switching frequency is not precise enoughfor not only the DC voltage drops across the PCB

for applications that require operation inside or outside ofplanes and traces, but also the delays that come froma specific frequency band. These applications generally

inductance between the device and the load. Both of

require setting the switching frequency with an oscillator,

these characteristics are important for maintaining verysuch as in voltage- or current-mode control, and intight regulation across the load range and during loadsome cases, the ability to synchronize with a systemtransients.

clock signal. Reference [2] offers further examples of the

The differential remote-sensing signals are fed into thefrequency variation of DCS-Control.

transconductance amplifier (gm), which compares theirdifference against the output voltage setpoint. (For

Fixed-frequency DCS-Control topology
overview

simplicity, Figure 2 shows this setpoint as a voltage
source in series with the GOSNS signal.) The COMP pin

Figure 2 shows a basic block diagram of the fixed-

gives the output of this amplifier, which is compensatedfrequency DCS-Control topology, as implemented inwith a Type II (one pole, one zero) network to ground.

the 15A TPS62873 buck converter. The addition of an
oscillator enables the direct setting of the switchingThis external compensation allows you to optimize thefrequency (fSW) in the same way as voltage- or current-

control loop to any system need – from systems withmode control. Having an oscillator input into thestrong load transients with large output capacitance, allcontrol loop also provides the ability to synchronize thethe way down to systems with small or no load transientsswitching frequency to an applied clock signal.

with very little output capacitance and small size. Unlike
DCS-Control, the fast feedback path goes through thisVIN

amplifier – not immediately to the comparator – where–R

compensation component selection can increase (or

ON

Q

+

Gate
DriverS

response, you increase the gain and add more output

COUT

EN

fsw

decrease) the gain. If you need a stronger transientLcapacitance. If no strong transients are present in theControlLogic

application, you decrease the gain and use a minimal
amount of output capacitance in order to achieve the
Slope
Compensation
gm

RLOAD

The ability to adjust the transient response to the

–

GOSNS
+

+

smallest size.

VOSNS

–

COMP

τaux

RZ

application needs enables tighter regulation underCC2harsher transients than what is possible with the previous

CC

DCS-Control topology, and meets the requirements of
Figure 2. Block diagram of the TPS62873’s fixed-frequency

demanding processor cores such as TI’s Jacinto™ J7

DCS-Control topology with the oscillator, differential remotesensing, transconductance amplifier and hysteretic comparator.

and MobileEye’s EyeQ6 [3-4]. Figure 3 shows a stackof three TPS62876-Q1 buck converters delivering a

Fixed-frequency DCS-Control, usually used in higher-

46A load transient, while maintaining the output voltage

current devices, uses differential remote sensing. The

within ±2% of the 0.875V setpoint.

device regulates the voltage between the VOSNS andGOSNS pins, which are routed across the printed circuitboard (PCB) to sense the output voltage directly at theload. Sensing at the load overcomes and compensates

Fixed-frequency DCS-Control: Fast transient response with clock synchronization

3

ISSUE 1, 2024

Analog Design Journal

Switching frequency variation
In addition to maintaining the fast transient response,
which can be further improved and tuned throughthe external compensation on the COMP pin, fixedfrequency DCS-Control provides a fixed switchingfrequency with a tight tolerance specification. Because
the switching frequency is directly set with an oscillator
instead of indirectly controlled with an on-timer, thefrequency’s tolerance is specified in the device-specificdata sheet. Table 1 and Table 2 compare the switchingfrequency specifications of the TPS62876-Q1, using the

Figure 3. The transient response of fixed-frequency DCS-Control

is tunable to the most severe load transients, where it provides
excellent regulation.

fixed-frequency DCS-Control topology, versus the typicalfrequency specification of the DCS-Control TPS62869

A hysteretic comparator compares the COMP pin output

step-down converter.

and a replica of the inductor current, created by the τaux

Parameter

Test Conditions

MIN

TYP

MAX

Unit

components, with slope compensation added to prevent

fSW

fSW = 1.5MHz, PWM
operation

1.35

1.5

1.65

MHz

the Set-Reset (SR) latch circuitry, along with the clock,fSW = 2.25MHz, PWM
operation

2.025

2.25

2.475

which controls the gate drivers and device operation. The

fSW = 2.5MHz, PWM
operation

2.25

2.5

2.75

oscillator controls the switching to occur exactly at thefSW = 3MHz, PWM
operation

2.7

3

3.3

subharmonic oscillations. The comparator’s output drives

switching frequency.

SwitchingFrequency

Table 1. The TPS62876-Q1, using the fixed-frequency DCSControl topology, specifies a ±10% tolerance of its four
switching frequency options over the full temperature and input
voltage ranges.

The Set-Reset latch is a simplified representation of
the detailed operation of the control block and is
implemented to maintain the fast, hysteretic nature of
DCS-Control and thus enable an immediate response
to load transients. For example, during a load-dump
transient (where the output voltage rises), the output

Parameter

Test Conditions

fSW

IOUT = 1A, VOUT = 0.9V

PWM
switchingfrequency

MIN

TYP

MAX

2.4

Unit
MHz

Table 2. The TPS62869, using DCS-Control, only specifies atypical switching frequency.

of the hysteretic comparator has priority over the clock
signal. The converter extends the off-time of the highside MOSFET as needed to bring the output voltage

Figure 4 and Figure 5 compare the actual variationback down with minimum overshoot. This is inherentlyof the switching frequency versus load current in an

improved behavior compared to textbook peak current-

application. Both devices support power-save mode,

mode control, which switches at every clock cycle,

which reduces the frequency at lower load currents

continuing to add energy to the output, even while it is(toward the left of both graphs). Operation in PWM

too high. By reducing the output-voltage overshoot, themode (at higher currents) results in a precisely controlledconverter significantly reduces the output capacitance,

switching frequency for fixed-frequency DCS-Control,

which is a key influence on the cost and size of thewhile the switching frequency of DCS-Control increases

power supply.

slightly with an increasing load. In forced PWM mode

Fixed-frequency DCS-Control: Fast transient response with clock synchronization

4

ISSUE 1, 2024

Analog Design Journal(not shown), fixed-frequency DCS-Control maintains its

regulation. This is improved performance compared toconstant frequency down to no load.

some current-mode devices that maintain the frequency
but let the output voltage rise in order to meet the3

Switching Frequency (MHz)required minimum on-time. While both fixed-frequency
DCS-Control and DCS-Control reduce the switching2

frequency in the same way [2], fixed-frequency DCSControl has fewer operating conditions during which theminimum on-time is reached, and the frequency reduced,

VOUT = 0.6 V, FPWM
VOUT = 0.6 V, PSM
VOUT = 0.9 V, FPWM
VOUT = 0.9 V, PSM
VOUT = 1.2 V, FPWM
VOUT = 1.2 V, PSM

1

0.5

1

1.5

2

2.5 3 3.5
Load (A)

4

4.5

5

5.5

because of its lower minimum on-time. For example, the
TPS62876-Q1 specifies the 44ns maximum value of its
minimum on-time at a 5V input voltage and across the6operating temperature. Such a low value of minimum

D007

on-time enables lower output-voltage applications inFigure 4. Switching frequency variation of the TPS62869 with

DCS-Control.

automotive and aerospace and defense, for example,
to operate in the higher-frequency region sometimes

3

Switching Frequency (MHz)required by the overall system.
2

Lower-ripple power-save mode
While most applications operate a fixed-frequency DCS-

1
0.8
0.7
0.6

Control device in forced PWM mode in order to obtainlower output-voltage ripple at light loads and a better

0.5

TJ = -40 C
TJ = 25 C
TJ = 105 C
TJ = 125 C

0.4
0.3
10m

100m
1
Output Current (A)transient response, the topology does support a powersave mode to increase efficiency at light loads. To

10maintain the target switching frequency and provide
lower ripple down to lower load currents, fixed-frequency

Figure 5. Switching frequency variation of the TPSM8287A12

DCS-Control reduces the on-time in power-save mode,

power module with fixed-frequency DCS-Control.

whereas DCS-Control keeps the on-time constant. BothBesides power-save mode, there are two conditions

topologies enter power-save mode when the inductor

where the switching frequency can deviate from thecurrent becomes discontinuous, which creates slightly

frequency set by the oscillator: during a strong load

higher ripple compared to PWM mode.

transient and if the minimum on-time is reached. When
applying a heavy load, the high-side MOSFET may be

Instead of reducing the frequency with the same on-

on for longer than a full switching period, and whentime, fixed-frequency DCS-Control’s power-save mode

removing a heavy load, it may be off for longer than a full

reduces the on-time while maintaining the same

switching period. Both scenarios result in one or more

frequency. Reducing the on-time delivers less energy

pulses that are not present because of the extended on-

to the output, thereby reducing the ripple voltage

or off-times.

compared to DCS-Control. Once the on-time reduces
to its minimum, skipping pulses reduces the output

If the minimum on-time of the high-side MOSFET ispower further for the lightest loads. Skipping pulses alsoreached, both fixed-frequency DCS-Control and DCS-

reduces the frequency.

Control reduce the switching frequency in order tomeet the minimum on-time and maintain output-voltage

Fixed-frequency DCS-Control: Fast transient response with clock synchronization

5

ISSUE 1, 2024

Analog Design Journal
Figure 4 and Figure 5 show the difference in frequency

good phase balancing without needing to specify the

reduction in power-save mode. The fixed-frequency

number of devices in the stack.

DCS-Control device reduces its frequency below

When interfacing to the stack through I2C,

loads of around 60mA, while the DCS-Control device

communication only happens to the primary device – notbegins reducing the frequency around 500mA. Althougheach device in the stack – in order to adjust the output

these current values are different for different devices

voltage, change the operating mode, or read back fault

and operating conditions, fixed-frequency DCS-Control

registers. Interfacing to a single device greatly simplifies

maintains its switching frequency down to lower load

the communication overhead and PCB routing by bothcurrents, leading to lower ripple.

reducing the number of reads and writes and the numberof PCB signals that need routing.

Stacking (paralleling) for higher (or lower) load
currents

Conclusion

On one hand, processor cores frequently require higher

With its fast transient response and stackability,

currents with each successive processor generation.

fixed-frequency DCS-Control powers the latest

On the other hand, some applications may not use allprocessors’ demanding load transient and output-currentof the functionality of a given processor or may use

requirements, while its fixed-frequency operation anda less-capable processor within the same processor

synchronization make it a great fit for noise-sensitive

family, resulting in lower current requirements. Scaling

applications. Automotive ADAS and infotainment, optical

the power supply’s current capability both up and down

modules, industrial test and measurement, medical, andrequires a stackable (parallelable) solution where it isaerospace and defense applications all benefit. The

possible to add or remove additional power-supply

tunable external control-loop compensation supports aphases as the current requirements change.

fast transient response with the minimum amount of

Fixed-frequency DCS-Control devices support stacking.

output capacitance, reducing the size and cost of a

While the specific implementation details vary slightly

power-supply system.

between each device family, features include current
sharing, phase interleaving and interface simplicity.

References

Current sharing is accomplished through the COMP

1. Texas Instruments: High-efficiency, low-ripple DCS-Control
offers seamless PWM/power-save transitions

pin. Since the COMP pin is essentially the small-signal
operating point, sharing this pin’s signal between all

2. Texas Instruments: Understanding frequency variation instacked devices enables fixed-frequency DCS-Control

the DCS-Control topology

to typically achieve tighter than 10% current-sharing

3. Texas Instruments: Powering Jacinto J7 SoC Family for

accuracy.

Isolated Power Groups with TPS6594133A-Q1 PMIC and Dual

Phase interleaving is accomplished by a dedicated

HCPS Converters
4. Texas Instruments: MobileyeEyeQ6L – Semi Discrete

SYNC_OUT pin, which connects to the MODE/SYNC

Power Tree

input pin of the next device in the stack. SYNC_OUT
is automatically phase-shifted in order to provide ripple

5. Priess, Canan.“How to Deliver Current Beyond 100

cancellation. Through this simple daisy chaining, all

A to an ADAS Processor.” TI E2E™ design support

devices in the stack operate at the same frequency andforums technical article, June 6, 2023.

with lower ripple than a single-phase design. You canstack a large number of converters and achieve very

Fixed-frequency DCS-Control: Fast transient response with clock synchronization

6

ISSUE 1, 2024

Analog Design Journal

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2024 Texas Instruments Incorporated

SLYT846

Analog Design Journal

A novel charge-mode control algorithm
for PFC
Bosheng Sun
System Engineer
Marketing/PDS, Dallas
VREF

+

+

A

GV

×

-

Introduction

÷

B

×
VOUT

In a control system, if you want to control something, you

+

GI

D

PWM
generator

PWM

-

C
ISENSE

Vrms2

need to sense it; this applies to power factor correction

IREF
+

VIN

(PFC) applications as well. In offline power supplies with

Figure 2. Traditional average current-mode control for PFC.

power levels >75W, PFC controls the input current tocreate a sinusoidal waveform (in other words, following

Almost all continuous conduction mode (CCM) PFC

the sinusoidal input AC voltage). In order to control thecontrollers use traditional average current-mode control.

input current, it needs to be sensed.

Although traditional average current-mode control
achieves a good power factor and has low total harmonic

The most common current-sensing method places a

distortion, it also has some limitations, especially inshunt resistor at the PFC ground return path (designatedtotem-pole bridgeless PFC. This article presents a brand-

as R in Figure 1) to sense the input current. The sensed

new control algorithm: charge-mode control [2].

input current signal (ISENSE) is then sent to an average
current-mode controller [1] (shown in Figure 2). Because

Charge-mode control

the current reference (IREF) is modulated by the input

The charge-mode control algorithm is a new control

voltage (VIN), it is a sinusoidal waveform. The control loop

concept: to control an object, you don’t really needforces the input current to follow IREF, thus achieving a

to sense it – you can sense its consequence andsinusoidal waveform.

then indirectly control the object. For PFC, insteadLILof controlling the input current directly, this control

VOUTalgorithm controls how much electric charge is delivered
to the PFC output in each switching cycle, and employs

VIN

a special control law such that the input current becomesVAC

Q

a sinusoidal waveform by controlling the electric charge.

PWM

There are a few ways to obtain the electric charge
information. Figure 3 shows an example of using aRcurrent shunt and an operational amplifier (op amp)

ISENSE

circuit, with the op amp configured as an integrator.

Figure 1. A common current-sensing method for PFC.

When the PFC boost switch turns off, the inductor
current starts to charge the PFC bulk capacitor. The
shunt resistor senses this current, which is thenintegrated through the integrator. The peak value ofthe integrator output represents the total electric charge

A novel charge-mode control algorithm for PFC

8

ISSUE 1, 2024

Analog Design Journaldelivered to the PFC output in each switching cycle. This

Figure 5 shows the typical signal waveform for charge-

electric charge (VCHARGE) is sampled by the controller asmode control.

a control-loop feedback signal. The integrator discharges

I2

to zero through Q1 before the boost switch turns off.
IL

I1

ID

L

IL

I1
Ton

VOUT

Toff
t

0
VIN

ID
VAC

Q

t

PWM

SampleVCHARGE
R

t
RESET

+

0

VCHARGET
C1

2T

Figure 5. Typical signal waveforms for charge-mode control.

Control law
Q1
RESET

Now that you know how to obtain the electric charge

Figure 3. Using the current shunt and op amp to obtain an

information for each switching cycle, let’s take a look atelectric charge.

how to get the sinusoidal input current waveform using

Figure 4 shows another method, which employs athe new control law, see Figure 6.

current transformer (CT) on the PFC output side. The CT

Compared to the traditional control law shown in Figure

output connects to capacitor C1. When the PFC boost

2, there are two differences:switch turns off, the inductor current starts to charge the• The current-loop reference is modulated by VIN 2, not

PFC bulk capacitor. The CT senses this current and its

by VIN.

output charges C1. The voltage on C1 rises up; its peak

• The feedback signal is the electric charge VCHARGE,

voltage represents the total charge delivered to the PFC
output. The controller samples the peak voltage VCHARGE

not ISENSE.

as a control-loop feedback signal. C1 discharges to 0V

VREF

+

+

A

GV

×

-

through Q1 before the boost switch turns off.

÷

B

×
VOUT
Vrms2

GI

D

PWM
generator

PWM

VIN2

VCHARGE'

Q1

C1

RESET

VIN

ID

L

+
-

C

VCHARGE

IL

IREF
+

Figure 6. Charge-mode control law for PFC.

VOUT

From Figure 6, the current reference IREF is given by:

VIN

VAC

Q
PWM

IREF = ABC(1)

where, IREF is the current-loop reference, A is the voltageloop output GV, B is Vrms2 used for VIN feedforward

Figure 4. Using a CT to obtain an electric charge.

A novel charge-mode control algorithm for PFC

control, and C is VIN 2.

9

ISSUE 1, 2024

Analog Design Journal
Looking at Figure 5, Equation 2 expresses the average

RHPZ effect and solution

inductor current in each switching cycle as:
IAVG =

I1 + I2

Ton + Toff
2 T

The loop compensation for charge-mode control
is simple when the PFC operates in DCM. Loop(2)

compensation becomes a challenge, however, because

where, IAVG is the average inductor current, I1 is thea right-half-plane zero (RHPZ) appears in the control

inductor current at the beginning of each switching cycle,

loop when the boost converter operates in CCM [3]. The

I2 is the inductor current peak value in each switching

RHPZ induces a phase drop that negatively impacts thecycle, Ton is the boost switch Q turn on time, Toff is thepotential phase margin of the control loop. Equation 7

boost diode D conduction time, and T is the switchingexpresses the small-signal model for the control loop as:

period.
vCHARGE

Equation 3 calculates the peak voltage of C1 (VCHARGE)din each switching cycle as:
VCHARGE =I1 + I2 Toff
2 C

sL
2
1 − D RLOAD=

1 − ωsz(7)Sω0where RLOAD is the output load of PFC, D is the(3)

VOUTT 1 − DsLCpulse-width-modulation duty cycle, ω0 =where, C is the capacitance of C1.

and ωz =In steady state, the control loop forces VCHARGE to equal
IREF (see Equation 4):
VCHARGE = IREFV
1−D T
= OUTsLC
1−

RLOADT 1 − DL

2.

Equation 7 clearly shows the RHPZ ωZ. Its frequency
varies with load, boost inductance and D (D varies(4)with the input and output voltage), which makes loop

For a boost-type converter in steady-state operation,compensation very difficult.

the volt-seconds applied to the boost inductor must be

To eliminate the RHPZ, Equation 8 modifies the feedback

balanced in each switching period (see Equation 5):
Ton VIN = Toff VOUT − VIN

signal:(5)′
VCHARGE=

Equation 6 combines Equation 1 through Equation 5:
G V
C
IAVG = v 2 OUT VIN
Vrms T

VCHARGE
Toff(8)

Figure 7 modifies the control law, where you can see that
IREF is now modulated by VIN, not by VIN 2.

(6)

VREF

+

+

A

GV

×

-

In Equation 6, since both C and T are constant, and

÷

B

IREF
+

GV, VOUT and Vrms2 do not change in steady state, IAVG

VOUT

GI

D

PWM
generator

PWM

C
VCHARGE'

Vrms2

follows VIN. When VIN is a sinusoidal waveform, IAVG is

+
-

×

VIN

also a sinusoidal waveform, thus achieving PFC. Note

Figure 7. Charge-mode control law for PFC after eliminatingthat Equation 2 and Equation 3 are valid for both CCM

RHPZ.

and discontinuous conduction mode (DCM); therefore,

With this modification, Equation 9 expresses the small-

Equation 6 is valid for both CCM and DCM operation.

signal model of the control loop as:v´CHARGEd

A novel charge-mode control algorithm for PFC

10

=

VOUT
sL

(9)

ISSUE 1, 2024

Analog Design Journal
The RHPZ disappears and the system becomes a firstorder system, which is very easy to compensate.
Figure 8 illustrates the verification of the new control
algorithm through simulation, achieving a sinusoidal input
current waveform.

References
1. Texas Instruments: High Power Factor Preregulator for OffLine Power Supplies.
2. Charge Mode Control for Power Factor Correction
Circuit. U.S. Patent 11,705,808 B2, filed Sept. 30,
2021, and issued July 18, 2023.
3. Texas Instruments: The Right-Half-Plane Zero – A

Figure 8. Simulation result: a sinusoidal input current waveform.

Simplified Explanation.

Conclusion
Instead of controlling the input current directly, charge
mode controls how much electric charge to deliver tothe PFC output in each switching cycle. This algorithm
works for all PFC topologies, but it is especially usefulfor totem-pole bridgeless PFC, which has traditionallyrequired a sensor such as Hall-effect sensor to sense
the bidirectional inductor current. The problem is that
Hall-effect sensors are not only expensive, but also
have limitations such as limited bandwidth, sensitive tomagnetic field and DC offset shifting with temperature,etc. Because charge-mode control eliminates the need tosense inductor current, there is no need for an expensive
bidirectional current sensor. Instead, you can use acurrent-sense resistor along with a low-bandwidth op
amp or a CT, which are much less expensive.
Because of its high efficiency, totem-pole bridgeless PFC
is attractive for applications that require high efficiency.
Its high cost was always a barrier for its broader
adoption, but this new control algorithm is now an option
in applications that require both high efficiency and low
cost. It is possible to implement charge-mode control
with existing digital controllers such as Texas Instruments
C2000™ microcontrollers and the UCD3138 controller, or
you can employ it in the development of a new analog
PFC controller.
Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
C2000™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
© 2024 Texas Instruments Incorporated

SLYT850

Analog Design Journal

Redundant supply topologies forautomotive applications using ideal
diode controllers
Abhijeet Godbole
Lead Systems Engineer
Praveen GD
Lead Applications Engineer
effect transistors (MOSFETs) to emulate the behavior

Introductionof ideal diodes. They offer several advantages overRedundant power supplies use more than one power-

conventional diodes, such as lower power dissipation,

supply unit to provide the necessary power for ahigher current capability, reverse polarity protection,load. They help increase a system’s reliability andreverse current blocking and load dump protection. Ideal

availability, and ensure system safety in case one of thediode controllers can also provide inrush current limiting

power-supply units fails. Redundant power supplies are

and overvoltage and overcurrent protection.

especially important in automotive systems for safety-

In this article, we will discuss the concept and benefits

critical applications, such as automated driving, whereof ORing and power multiplexing using ideal diodea loss of power could result in serious consequences.

controllers, the different types and architectures of ORing

ORing and priority power multiplexing are two popularand power multiplexing circuits, and the challenges andtechniques for implementing redundant power supplies

solutions for implementing ORing and power multiplexing

in automotive systems. In ORing, the system selects

using ideal diode controllers in automotive systems.

the highest-voltage power source from multiple inputs,
while power multiplexing allows the system to switch

ORing and power multiplexing techniques

between different power sources based on priority

Both ORing and power multiplexing techniques use ideal

levels or other criteria. Designers have traditionally used

diodes to connect multiple input power sources to a

Schottky diodes, P-channel field-effect transistors or asingle output load, but they differ in how they select andcombination of both for redundant circuits in a powerswitch between different input sources. Figure 1 shows

supply.

a typical use case for power supply ORing and priority

Ideal diode controllers are integrated circuits (ICs) thatmultiplexing.

can control external metal-oxide semiconductor field-

Redundant supply topologies for automotive applications using ideal diodecontrollers

12

ISSUE 1, 2024

Analog Design Journal
Power Supply Priority Muxing

Power Supply OR-ing

VIN1

VIN1
12V
BAT (VAUX)
Ideal Diode
Controller

Loads
HV
BAT (VPRIM)

VIN2

B2B FET Ideal
Diode Controller

GND

Loads

VIN2
DC/DC

Ideal Diode
Controller

B2B FET Ideal
Diode Controller

Figure 1. Typical use case of ORing and priority power multiplexer solution.

An ORing circuit facilitates system selection of thereverse current blocking and load path on and off control

best available power source from multiple inputs, based

features to enable the prioritized power supply to serveon the highest input voltage. The ideal diodes act as

the load.

switches that turn on when the input voltage is higher

Typical application circuits for power-supply
ORing

than the output voltage, and turn off when the input
voltage is lower than the output voltage. This way, theORing circuit ensures that the input source with theORing circuits are popular in automotive subsystems

highest voltage is connected to the output, and prevents

such as infotainment, body control modules, advanced

reverse current flow and cross conduction between thedriver assistance systems and lighting modules; they

input sources. If the input power supplies are almost

provide redundancy and reliability in case of a power-

equal, it is possible that both power supplies share thesupply failure or disconnection. Figure 2 shows different

load without any circulating current between them. Thus,

ORing topologies using ideal diode controller ICs

reverse current blocking is the primary feature required

combined with external N-channel MOSFETs.

for realizing an ORing circuit.

An effective ORing solution needs to be extremely fast

A power multiplexing circuit allows the system to switch

in order to limit the duration and amount of reverse

between different power sources irrespective of thecurrent in case one of the supplies fails. The ideal

voltage magnitude, based on criteria such as source

diode controllers in an ORing configuration constantly

priority or input voltage availability and magnitude. In

sense the voltage difference between the anode andthis configuration, the control circuit needs to switch

cathode pins, which are the voltage levels at the power

power paths between each power supply and load on

sources (VIN1, VIN2) and the common-load (VOUT) point,

and off, controlled by its own priority logic or an external

respectively. A fast comparator shuts down the gate

signal, such as a microcontroller general-purpose input/

drive through a fast pulldown – within microseconds as

output pin. The power multiplexing circuit ensures thatsoon as VIN – VOUT falls below a designated reverse

only one input source is connected to the output atthreshold, typically a few millivolts. Along with a fast

any point in time, and prevents reverse current flow andreverse-current detection comparator, TI ideal diodecross conduction between the input sources. The circuit

controllers have a linear gate regulation scheme thatin this configuration is therefore required to have both

Redundant supply topologies for automotive applications using ideal diodecontrollers

13

ISSUE 1, 2024

Analog Design Journal
ensures zero DC reverse current in the event of an input
supply loss.
Topology 1

Topology 2

Topology 3
Q2

Q1
Q1

VIN1

VIN1

VS

Q1
VIN1

DGATE CAP VS C
A
VSNS
SW
LM74800-Q1

ANODE GATE CATHODE
GATE

EN

VCAP

CATHODE

LM74700-Q1

ANODE
LM74700D-Q1

BATT_MON

ON
OFF

VOUT

OUT
VOUT
ON

EN

R2
EN/UVLO

GND

OFF

GND

OV

VCAP

R3

GND
Q2

Q3

VOUT

VIN2

Q2

VIN2

R1

HGATE

VS

Q4

Q3
VIN2

EN
ANODE

GATE

CATHODEVS

LM74700D-Q1
VCAP
GND

BATT_MONR1

DGATE CAP VS C
A
VSNS
SW
LM74800-Q1

VS

HGATE
OUT

VS
ON

R2
OV

EN/UVLOOFF

BATT_MONR1

DGATE CAP VS C
A
VSNS
SW
LM74800-Q1

HGATE
OUT

ON

GND

R3

OFF

R2
OV

EN/UVLO
GND

R3

Figure 2. Typical ORing topologies using ideal diode controllers.

Few subsystems require disconnecting the load from theallows Q2 to block reverse current, while Q3 remains on,

power supplies to achieve low quiescent current or toconnecting VIN1 to VOUT.

protect the system from fault conditions. Topology No.

Topology No. 3 in Figure 2 shows a typical application

2 in Figure 2 shows a typical application circuit for acircuit for ORing with load disconnect functionality fordual-supply input ORing with a common load disconnect

individual rails, thus allowing system designers to assign

control using TI’s LM7480-Q1 and LM7470-Q1 devices.

different load disconnect criteria for each rail.

FET Q1 and Q2, driven by the LM7470-Q1 and LM7480Q1, respectively, provide ORing functionality, whereas

Figure 3 and Figure 4 shows power-supply ORing

the Q3 FET driven by the LM7480-Q1 can isolate theswitchover performance between two power-supply rails

load from power supplies. When VIN1 is greater thanwhere VIN1 = 12V and VIN2 = 15V.

VIN2, the independent control of FETs by the LM7480-Q1

Redundant supply topologies for automotive applications using ideal diodecontrollers

14

ISSUE 1, 2024

Analog Design Journal

Figure 3. Supply switchover from VIN1 to VIN2.

Figure 4. Supply switchover from VIN2 to VIN1.

Redundant supply topologies for automotive applications using ideal diodecontrollers

15

ISSUE 1, 2024

Analog Design Journal
primary and AUX power supplies are present and within

Priority power multiplexer configuration

the acceptable range, and the primary is powering the

A priority power multiplexer automatically transitions theload, the AUX path controller must block reverse current

primary power supply to an auxiliary (AUX) or secondary

when the primary power-supply voltage is higher thanpower supply when the primary supply voltage drops

the AUX supply. Likewise, the AUX path controller must

below a designated threshold. When available and withinblock forward current when the primary voltage is lower

acceptable limits, the primary power supply is always

than the AUX. This ensures that the primary supply,

the first source for powering the load. For example,

which has the highest priority, powers the load and theif an upstream smart fuse in a power distribution unit

AUX supply is isolated from both the primary supply andtrips on the primary power supply to a subsystem, thethe load.

priority power multiplexer circuit automatically connects

The LM74900-Q1 ideal diode controller drives andthe AUX supply to the output and disconnects thecontrols external back-to-back N-channel MOSFETs toprimary supply from that output to avoid any disruptions

emulate an ideal diode rectifier with power path on orin the subsystem operation. If the upstream smart fuse

off control and overcurrent and overvoltage protection.

is reset and the primary supply voltage rises to an

Figure 5 is a schematic for a priority power multiplexer

acceptable threshold, then the priority power multiplexer

using two LM74900-Q1 devices in a common drain

circuit automatically connects the primary supply back totopology. The overvoltage pin of the LM74900-Q1 in

the output and disconnects the AUX supply.

the VAUX path is configured such that the VAUX power

A power multiplexer circuit requires a controller such as

supply connects to the load immediately when VPRIM

the LM74800-Q1 or LM74900-Q1 to control two back-to-

is disconnected for any reason and ensures continuousback MOSFETs on each power-supply rail. When both

Redundant supply topologies for automotive applications using ideal diodecontrollers

supply to the load.

16

ISSUE 1, 2024

Analog Design Journal
Q2

Q1
RSENSE

VPRIM
CVS
0.1uF

DGATE

CAP

RISCP

RSET

ISCP

C VS

CS+

CS-

A

HGATE
OUT

SW

R1

U1
LM749x0-Q1

FLT

UVLO

EN

ON

OFF

VOUT

R2
SLEEP
OV
GND

R3

TMR

OFF ON

IMON

ILIM

R3
R5

R4

Q3

Q4
RSENSE

VAUX
CVS
0.1uF

CIN

VCAP
Q5

RSET

RISCP

RCP

DGATE

CAP

ISCP

C VS

CS+

CS-

D2

HGATE

A
OUT
SW

VPRIM

FLT

U2
LM749x0-Q1

UVLO

EN

ON

OFF

R2
SLEEP

OV
GND

TMR

OFF ON

IMON

ILIM

R5

R4

Figure 5. Typical priority power multiplexer application circuit using the LM74900-Q1.

A power multiplexer circuit aims to keep the output

a transistor (Q5) and a diode (D2) can increase thevoltage drop low while the load switches to power fromHGATE source current. It is also possible to increase

VAUX when VPRIM is cut off or out of the acceptable

the gate source current by connecting the emitter ofrange. To keep the output voltage drop low during

Q5 to the gate of Q4, as Q5 allows the charge-pump

the transition, the load switch FET (Q4), driven by thecapacitor to pull the HGATE high directly. Alternately, you

LM74900-Q1 in the VAUX path, must be turned on very

could adjust the Q4 gate source current by changing thequickly while the power path of the VPRIM is turned off

resistor value of RCP. D2 provides a path around Q5 to(by turning off Q2). But the HGATE pin is designed toturn off Q4.

source only 55μA of gate current to achieve slow startup
for inrush current limiting, which is too low to turn the
HGATE high quickly. A small circuit with a resistor (RCP),

Redundant supply topologies for automotive applications using ideal diodecontrollers

17

ISSUE 1, 2024

Analog Design Journal
Figure 6 shows the waveform captured during the instance that VPRIM disconnects and the load transitions to the VAUX
rail quickly. The HGATE of the AUX rail turns on within 20µs to reduce the drop-in output voltage.

Figure 6. VPRIM to VAUX switchover in a power multiplexer application

Figure 7 shows a waveform of the instant when VPRIM recovers back to an acceptable level and the priority power
multiplexer circuit smoothly transitions the load with minimal voltage drop to VPRIM, as it has higher priority over VAUX.

Figure 7. VAUX to VPRIM switchover in a power multiplexer application.

Redundant supply topologies for automotive applications using ideal diodecontrollers

18

ISSUE 1, 2024

Analog Design Journal
Table 1 shows various ideal diode controllers and theredundant supply topologies that they can support basedon individual feature sets.
Power multiplexing configuration(back-to-back FET control)
Ideal diodecontroller

ORing
configuration

Common drain
topology

Commonsourcetopology

LM5050-1-Q1

✓

×

×

LM70700-Q1

✓

×

×

LM7480-Q1✓✓✓

LM74720-Q1

✓

✓

×

LM74900-Q1

✓

✓

×

LM74930-Q1

✓

×

✓

Table 1. List of ideal diode controllers for redundant supply
topologies.

Conclusion
Ideal diode controllers with advanced features enable
the different architectures of ORing and power
multiplexing circuits. Ideal diode controllers offer features
and advantages such as reverse polarity protection,
reverse current blocking, load dump protection, active
rectification, overvoltage protection and inrush current
limiting, thus enabling complete input power-path
protection and helping ensure system reliability andsafety.

References
1. Texas Instruments: Six System Architectures with Robust
Reverse-Battery Protection Using an Ideal-Diode Controller.
2. Texas Instruments: Addressing Automotive Reverse
Battery Protection Topologies with LM749x0-Q1..
3. Texas Instruments: Priority Power MUX Using Ideal Diodes
in Automotive Zonal Modules.

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2024 Texas Instruments Incorporated

SLYT848

Analog Design Journal

Low-EMI designs for isolated ADC
signal-chain solutions
Dr. Ralph Oberhuber
Precision Analog-to-Digital Converters
own requirements. Regulations in countries outside ofIntroduction

the U.S. and Europe often resemble the FCC or EU

The sheer volume of electronic devices in use today,

requirements [6].

coupled with the constant reduction in the size of

Product sector

these devices, makes electromagnetic interference (EMI)a major problem for circuit designers. Circuits used
for communications, computations and automationneed to operate in close proximity [1]. Products
must also comply with government electromagnetic
compatibility (EMC) regulations. Virtually every country
regulates the EMC of electronic products marketedor sold within its borders. In the United States, theFederal Communications Commission (FCC) regulates

CISPR standard

EN standard

FCC standard

Automotive

CISPR 25

EN 55025–

Multimedia

CISPR 32

EN 55032

Part 15

Industrial,
scientific,
medicalCISPR 11

EN 55011

Part 18

Householdappliances,electric tools
and similar

CISPR 14-1

EN 55014-1–

Lighting
equipment

CISPR 15

EN 55015

Parts 15 and 18

Table 1. Summary of the main product standards for radiatedand conducted emissions [5].

all commercial (nonmilitary) sources of electromagnetic
radiation [2] and defines the radiated and conducted
EMI test procedures in standards such as Standard

The need for low EMI becomes even more obvious

C63.4 [3] from the American National Standards Institutewhen considering a specific type of equipment, for(ANSI). Countries in the European Union (EU) regulate

example in smart metering. Smart electricity meters areboth electromagnetic emissions and the immunity ofa significant part of the future of energy distribution.

electronic devices; the Electromagnetic Compatibility

They provide real time data on usage to both utilities

Directive [4] basically states that equipment must comply

and end users, helping people monitor energy usage

with harmonized standards on EMC and be tested andand eliminating meter reading visits. The majority oflabeled accordingly.

smart meters connect via wireless communications [7],There are a large number of EMC standards pertaining tosuch as Wireless M-Bus or ZigBee, or they connect tovarious types of equipment. For example, International

the cellular phone network (GSM, LTE cat NB1- NB2,

Electrotechnical Commission (IEC) 61000 standards

2G/3G/5G). As illustrated in Figure 1, a smart electricity

cover immunity requirements for most commercial

meter contains a radio-frequency (RF) transmitter circuit,products, while theComité International Spécial desusually in the same housing with the energy-metering

Perturbations Radioélectriques (CISPR) 32 standard(metrology) circuit board. It is important to minimize

specifies limits on conducted and radiated emissions [5].

radiated emissions from the metrology circuit in order

Table 1 lists CISPR, European Norm and FCC standards

to not disturb RF communication, which can operate

for the relevant product sector. Many other countries

at frequencies such as 800MHz, 900MHz, 1,800MHz,

outside the U.S. and EU either specify compliance2,100MHz or 2,700MHz. The metrology circuit alsowith FCC or EU EMC requirements or have theirneeds to be resistant in terms of electromagnetic

Low-EMI designs for isolated ADC signal-chain solutions

20

ISSUE 1, 2024

Analog Design Journal
susceptibility (the ability to withstand electromagnetic

integrated circuit (IC) mounted on that PCB, some of theenergy from wireless communication) in order to avoid

primary sources of radiated emissions include:

billing errors from the injection of RF noise into the• Switching signals such as clocking signals, withsensitive energy-measurement front end.

rapid changes in voltage levels during digitalThis article explains the sources of EMI – specificallysignal transitions. This occurs because of the high-radiated emissions – and present some techniques

frequency components in the signals. Switching andto minimize EMI for an analog signal chain, including

clocking signals are essential for synchronizing thedetailed layout examples and measurement results.

operation of various components within and between

Power Lines

ICs.
• Switching regulators and other components, whichcause rapid changes in current draw through powersupply lines.
• Input/output buffers, especially those associatedwith high-speed interfaces such as USB, HDMI or
Ethernet, because of the high-speed signal transitions
they handle.

Applications
Processor

ADC

Metrology
MCU

Sensors

Electricity Meter• Harmonics created by nonlinear behavior in the
Wireless
Connectivity

IC’s internal circuits at frequencies higher than thefundamental signals.
• Parasitic capacitance, inductance and resistance in
the IC’s interconnects and structures.
• Electrostatic discharge (ESD) events that trigger ESD
protection circuits.

Electromagnetic
Interference

Figure 2 illustrates TI’s AMC131M03 galvanicallyFigure 1. An RF-enabled smart electricity meter.

isolated analog-to-digital converter (ADC) [8] and the

Sources of EMI and radiated emissions

predominant sources of radiated emissions resulting

EMC is the ability of an electric system to function

from its internal architecture and connections on theproperly in its intended environment in the presence

PCB. The ADC is used in a three-phase energy meteringof EMI, and to not be a source of interference toapplication, and Figure 2 shows the circuitry for one

that electromagnetic environment beyond the limits asphase (phase A). The signal chain is designed to extract

specified in the relevant standard [1].

voltage and current measurements for energy monitoring

EMI can be either radiated or conducted. Radiated[8]. ADC channel 0 measures the phase current usinga shunt resistor, and channel 1 measures the phaseinterference travels in the form of radio waves, andvoltage through a resistive divider [8]. The most relevant

is also called RF interference. Conducted interference

contributor to emissions is the internal switching DC/DC

comes from the magnetic field generated by current flow

converter (a in Figure 1) that generates the isolated

in cables carrying signals and power.

power supply on the high-voltage side [8]. The second-

The focus of this article is on minimizing radiatedhighest source of radiated emissions is the digitalemissions. On a printed circuit board (PCB) or inside an

Low-EMI designs for isolated ADC signal-chain solutions

isolation (b in Figure 2), as it is implemented using high-21

ISSUE 1, 2024

Analog Design Journal
frequency on/off keying transmission through a stacked

digital communication interface between the ADC andcapacitor barrier [8], [9]. Furthermore, clock signals emit

the microcontroller (d in Figure 2).

radiation in a wide frequency range, such as the ADC
modulator clock CLKIN (c in Figure 2) as well as the(a) DC/DC converter
Low-side supply(3.3V or 5V)

AMC131M03
3-phase system
aseC

DCDC_OUTas

Ph

HLDO_OUTeB

Neutral

DCDC_CAP
IsolatedPower

ISO GND

IsolatedPower

Reinforced Isolation

HLDO_IN
Phase ADVDD

DCDC_HGND

Ph

SourceHGND
1.2V
Reference

DGND
GND(c) ADC modulator clock

Temperature
Measurement

CLKIN
AIN2P/GPO+ISO GNDNTC–SPI Interface&
Control

ISHUNT

AIN12N
Voltage
Measurement

SYNC/RESET -ADC

–
AIN1P

CS
DIN
MCU

-ADC

SCLK

+

DOUT
RSHUNT

AIN0N

A

ISO GND

N

B

Current
Measurement

–

AIN0P

-ADC

DRDY+(d) SPI communication

C(b) Digital isolation channels

Figure 2. Analog signal chain with an isolated ADC, and sources of radiated emissions.

• Straight, short trace routing. Routing high-speed

Techniques to minimize EMI

traces in a straight line and keeping them as short

Several common PCB design techniques minimize EMI,as possible can minimize the potential for EMI. Also,

also detailed in references [1], [10], [11]:take care to avoid creating right angles in your traceroutes, which can cause reflections and signal losses.

• Proper grounding. This is one of the most effective• Using decoupling capacitors. Decoupling capacitors

ways to reduce radiated emissions. Careful grounding
can avoid ground loops that can act as antennas.

can provide a short return path for high-frequency

Using a ground plane can also help reduce loop areas

noise to ground. Place decoupling capacitors as closeand provide a return path for signals, reducing theas possible to the power pins of ICs.

potential for EMI. In other cases, however, ground• Controlled impedance. Controlling the impedance ofplanes can create antennas on sensitive nodes andsignal traces will match the impedance of the source

increase radiated emissions (see specific example

and load and can help prevent signal reflections thatshown in Figure 5).

can lead to radiated emissions.
• Shielding. Sometimes, using metal shields or• Component placement. Place components in a waythat minimizes the length of signal traces, particularly

shielding material on certain areas of the PCB canfor high-speed signals. Keep digital and analog

prevent radiated emissions.

components separate to avoid interference.

Low-EMI designs for isolated ADC signal-chain solutions

22

ISSUE 1, 2024

Analog Design Journal• Using filters. Filters can block out certain frequencies• Avoid clock harmonics. Clock signals can generatethat are causing radiated emissions, and are

harmonics that can interfere with other parts of theparticularly useful in power-supply circuits.

circuit. Spread-spectrum techniques can help spreadthese harmonics out and reduce their impact.

• Layer stacking. In multilayer PCBs, take care toarrange the layers in a way that minimizes EMI. It’s

• EMI simulations. Radiated emissions simulation tools

generally good practice to alternate between power

can help predict and minimize EMI in the PCB design

and ground layers, as this can help reduce loop areas

phase itself [12], [13].

and provide a return path for signals. Top and bottom

Figure 3 is a detailed schematic of the analog signal

ground layers can help act as a shield field for internal

chain introduced in Figure 2.

signal layers such as clocks that generate radiatedemissions.
Ferrite
F1

C6
1µF

C1
1nF

DCDC_OUT

DVDD
Resonator andDriverRectifier

DCDC_HGND

FerriteF2

LDO

HLDO_IN
C11
1nF

C24
100nF

C17
100nF

1.2-V
Reference

ISO GNDAIN2P/GPO
ISHUNT+NTC

ISO GND

Ferrite
F3

R7
49.9

–

C8
4.7nF

ADC
+

Phase
Shift &
DigitalFilter

CLKIN
from uC

R18
100k
R15
100k

Gain &
OffsetCalibration

SYNC/RESET
from uC

Phase
Shift &
DigitalFilterGain &
OffsetCalibration

Control &SerialInterface

SCLK

from uC

DIN

from uC
from uC

DOUT

AIN0N
–

Neutral

R19
100k

CS
–

AIN1P

C9
4.7nF
R9
49.9

Clock
Generation

AIN12N

R8
49.9

RSHUNT
Phase

ADC

Low side
supply3.0V to 5.5V

R32
100k

Temp
Sensor

C10
1nF

R6
49.9

GND

DCDC_CAP

HGND

C16
1µF

DGND

LDO

HLDO_OUT

Isolation Barrier

C13
100nF

C15
1nF

AMC131M03

ADC
+
AIN0P

Phase
Shift &
DigitalFilterGain &
OffsetCalibration

DRDY

to uC
to uC

Figure 3. Detailed schematic of the analog signal chain from Figure 2.

Figure 4 and Figure 5 illustrate the application

ISO_GND. Minimizing trace lengths and not placingof radiated emissions reduction techniques to thea ground plane in the high-voltage domain minimizes

corresponding PCB layout for the AMC131M03. Figure

the antenna on this node, and thus minimize radiated

4 shows a “good” layout, keeping traces short for ADC

emissions [14]. Ferrite beads F1 and F2 are inserted

inputs and power routes in the high-voltage domain

into power connections DCDC_OUT and DCDC_HGND(PCB area to the left of the AMC131M03 placement) andto block out high-frequency noise. You can also place

placing bypass capacitors C1, C6, C8, C9, C11, C13,

an additional ferrite bead (F3) with high impedance at

C14 and C24 close to the IC.

the frequency of excessive radiated emissions (which will
depend on the PCB design) in series with the resistive

An important aspect when mitigating EMI is thedivider for the voltage measurement.

grounding scheme of the isolated ground node

Low-EMI designs for isolated ADC signal-chain solutions

23

ISSUE 1, 2024

Analog Design Journal
Place ferrites
Close to the device
to improve EMI
performance.

Via to corresponding
voltage plane or pour+3.3 V

F1

C6
F2

Via

Clearance area, to be
kept free of any conductive
material.

C1

Terminate long digital
input lines with resistors toprevent reflection.

Top Metal
C24

Inner or Bottom
Layer Metal

C10

C13
Place smaller decoupling
caps closest to thedevice.

C11

1: DCDC_OUT

20: DIN

2: DCDC_HGND

19: CS

3: HLDO_IN

18: SCLK

4: HLDO_OUT

17: CLKIN

5: HGND

16: DRDY

ISO_GND
Ferrite in series withresistive divider

AMC131M03

Channel 2

Channel 1

7: AIN12N

14: DCDC_CAP

8: AIN1P

13: DVDD+3.3 V

C17
C15

Differential RC-filter
per channel.

9: AIN0P

12: DOUT

10: AIN0N

11: SYNC/RST

C16Place smaller decoupling
caps closest to thedevice.

C9R8RSHUNT

15: DGND

R7

F3Channel 0

Place bypass
capacitor directly
across ADC inputs.

R9

Minimum connections at
ADC inputs and ISO_GND

ISO_GNDx

GND

6: AIN2P/GPO
C8

R6

Keep layout ofshunt connections
symmetrical.

Place DCDC_CAP and power
supply decoupling capacitors close
to pins.

Use separate trace for HGND
connection to shunt terminal.

GND

Figure 4. Good PCB layout (low EMI).

Figure 5 illustrates a “bad” layout, showing a ground plane connected to the ISO_GND node, which acts as an antenna
and can increase radiated emissions significantly [14].
Place ferrites
Close to the device
to improve EMI
performance.

Via to corresponding
voltage plane or pour+3.3 V

F1

C6
F2

Via

Clearance area, to be
kept free of any conductive
material.

C1

Terminate long digital
input lines with resistors toprevent reflection.

Top Metal
C24

Inner or Bottom
Layer Metal

C10

C13
Place smaller decoupling
caps closest to thedevice.

C11

1: DCDC_OUT

20: DIN

2: DCDC_HGND

19: CS

3: HLDO_IN

18: SCLK

4: HLDO_OUT

17: CLKIN

5: HGND

16: DRDY

ISO_GND
Ferrite in series withresistive divider

AMC131M03
6: AIN2P/GPO

Channel 2
R6

R8
RSHUNT

7: AIN12N

14: DCDC_CAP

8: AIN1P

13: DVDD

Channel 0
R9

9: AIN0P

12: DOUT

10: AIN0N

11: SYNC/RST

C16Place smaller decoupling
caps closest to thedevice.

C9

Place bypass
capacitor directly
across ADC inputs.

ISO_GND plane(bottom layer) acts as antenna!

ISO_GNDx+3.3 V

C17
C15

R7

Differential RC-filter
per channel.

Keep layout ofshunt connections
symmetrical.

GND
15: DGND

C8Channel 1
F3

Place DCDC_CAP and power
supply decoupling capacitors close
to pins.

Use separate trace for HGND
connection to shunt terminal.

GND

Figure 5. Bad PCB layout (high EMI).

Low-EMI designs for isolated ADC signal-chain solutions

24

ISSUE 1, 2024

Analog Design Journal
Figure 6 and Figure 7 show the radiated emissions

Conclusion

measurement for the AMC131M03 PCB using the layout

To ensure that the electronic circuits perform as

implementation depicted in Figure 4. The measurements

designed, they must be protected from EMI. At the same

follow CISPR 11 requirements in a semianechoic

time, the circuits themselves must not radiate emissions

chamber using a broadband antenna configured forthat can threaten or degrade the performance of otherhorizontal and vertical polarizations with a 3m distance.

equipment. Compliance with EMC standards requires

The ADC is receiving a continuous clock at the CLKIN

EMI protection at four levels: the component level, board

pin and is generating conversion results. However,level, system level and overall system level [15].

there is no Serial Peripheral Interface communication
while the emission profile is characterized. This design

The techniques presented here minimize EMI at themeets CISPR 11 Class A and Class B standards with

PCB (board) design level and are easily applicable to a

13dB of margin, offering the lowest radiated emissions

practical example, a best-in-class precision ADC signal

performance on the market for an ADC with reinforced

chain with reinforced isolation [16] used for electricity

isolation for both data and power.

metering. With careful design using the proposed EMI
reduction techniques, the design achieves sufficient60

Max E (dBV/m)50

RE Horizontal
CISPR11ACISPR11B

margin [17] for the relevant EMC standards.

40

References30

1. Ott, Henry W. 2009. “Electromagnetic Compatibility

20

Engineering.” Hoboken, New Jersey: John Wiley &
Sons.

10

2. Part 15 – Radio Frequency Devices. FCC Title 47,

0
-10
30

Chapter I, Subchapter A. FCC: Washington, D.C.,
Jan. 11, 2024.
40 50 6070

100
200 300 400500 700 1000
Frequency (MHz)

3. American National Standard for Methods of
Measurement of Radio-Noise Emissions from Low-

Figure 6. Horizontal radiated emissions CISPR 11 measurement.

Voltage Electrical and Electronic Equipment in the60

Max E (dBV/m)

50

Range of 9 kHz to 40 GHz. IEEE C63.4-2009.

RE Vertical
CISPR11ACISPR11B

Piscataway, New Jersey, Sept. 15, 2009.
4. Directive 2004/108/EC of the European Parliament40

and of the Council of 15 December 2004 on the

30

Approximation of the Laws of the Member States
20

Relating to Electromagnetic Compatibility and

10

Repealing Directive 89/336/EEC. Official Journal of0

the European Union. Brussels, Belgium, Dec. 31,
2004.

-10
30

40 50 6070

5. Texas Instruments: An Overview of Conducted EMI

100
200 300 400500 700 1000
Frequency (MHz)Specifications for Power Supplies.

Figure 7. Vertical radiated emissions CISPR 11 measurement.

6. LearnEMC.com. n.d. EMC Regulations. Accessed
Jan. 14, 2024.

Low-EMI designs for isolated ADC signal-chain solutions

25

ISSUE 1, 2024

Analog Design Journal
7. Envocore.com. n.d. How Do Smart Meters
Communicate? Accessed Jan. 14, 2024.
8. Texas Instruments. n.d. AMC131M03 three-channel,
simultaneous-sampling 24-bit isolated delta-sigma
ADC. Accessed Jan. 14, 2024.
9. Texas Instruments: Addressing High-Voltage Challenges
with Reliable and Affordable Isolation Technologies.
10. Altium.com. n.d. PCB Design Techniques to ReduceEMI. Accessed Jan. 14, 2024.
11. Analog Devices (Maxim Integrated). Practical
Aspects of EMI Protection. Tutorial 1167, Aug. 21,
2002.
12. Remcom. n.d. Electromagnetic Simulation
Software. Accessed Jan. 14, 2024.
13. Cadence. n.d. Clarity 3D Transient Solver. Accessed
Jan. 14, 2024.
14. Texas Instruments: Best Practices to Attenuate AMC3301
Family Radiated Emissions EMI.
15. Electronic Design. n.d. Meet EMI Standards forElectronic Systems. Accessed Jan. 14, 2024.
16. Texas Instruments: High-Voltage Reinforced Isolation:
Definitions and Test Methodologies.
17. Texas Instruments: Understanding Electromagnetic
Compliance Tests in Digital Isolators.

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2024 Texas Instruments Incorporated

SLYT849

Analog Design Journal

Solving AC dropout recovery in a highdensity GaN-optimized PFC converter
Brent McDonald
System and Application Engineer
Power Design Services

Introduction

S21

S22
S4

Lg1

A loss of power in data center server power-supply units

Lg2
Vac

can interrupt everything from entertainment to financial

LISN

Lb1

transactions to home security systems. Specifications

Vdc

Lb2

Cb

such as the V2 Power Shelf Specification from the

S11

S12

S3

Open Compute Project (OCP) [1] emphasize the need
Figure 1. iTCM topology with inductor and current envelopes.

to reduce server downtime with robust AC dropout
control algorithms. In addition, the need for cost-effective

Parameterssolutions in data centers to improve power factor

Value

AC input

90 V-264 V

correction (PFC) light load and peak efficiency while

Line frequency

50-60 Hzshrinking passive components is becoming difficult with

DC output

conventional continuous conduction mode control [2-8].

Maximum power

5 kW

Holdup time at full load

20 ms

To address this problem, TI developed a gallium

400 V

Lg, low-frequency inductor

140 µHnitride (GaN)-based high-density design using two-phase

Lb, high-frequency inductor

14 µH

integrated triangular current mode (iTCM) PFC (Figure 1)

Cb, high-frequency blocking
capacitor

1.5 µF

Total harmonic distortion (THD)

OCP v3[9]. Low-value inductors operating at a high frequency
have enabled the high efficiency (>99%) and power

Electromagnetic interference (EMI)density (120 W/in3) of this design. These small inductors

European standard (EN) 55022
Class A

present a unique problem to AC dropout recovery in that

Operating frequency

Variable, 75 kHz-1.2 MHz

only a few microseconds of switch on-time can result

Microcontroller

TMS320F280049C [11]High-frequency GaN field-effecttransistors (FETs) (S11, S12, S22,
S21)

LMG3526R030 [12]further exacerbating PFC recovery. Keeping the current

Low-frequency silicon FETs (S3,S4)

IPT60R022S7XTMA1

levels at a safe magnitude and preventing reverse current

Dimensions

38 mm ´ 65 mm ´ 263 mm

required the development of a new solution to the AC

Power density

120 W/in3

dropout and recovery problem. This article discusses thisTable 1. iTCM topology with inductor and current envelopes.

in over 70 A of switch current. In addition, any delays
in timing can also result in significant reverse current,

solution with lab verification data based on the VariableFrequency, ZVS, 5-kW, GaN-Based, Two-Phase Totem-

Topology overview

Pole PFC Reference Design [10], for which Table 1 lists

The topology uses two phases operating 180° out ofthe primary components and system specifications.

phase with a single DC blocking capacitor, Cb, taking
advantage of the ripple current cancellation provided by
the two-phase architecture and reducing the root-mean-

Solving AC dropout recovery in a high-density GaN-optimized PFC converter

27

ADJ 3Q 2023

Analog Design Journalsquare (RMS) current stress in Cb. Lb1 and Lb2 are
sized to process the high-frequency AC ripple current

S21
S4

Lg1

necessary for TCM operation, removing the DC bias

Lb1
Vac

burden required for the inductor used in TCM, as definedVdc
Cbin [5]. Using ferrite cores for Lb1 and Lb2 ensures low
loss in the presence of the high flux swings necessary

S11

S3

for zero voltage switching (ZVS). Lg1 and Lg2 are larger inFigure 2. Synchronous rectifier S21 delayed turnoff Vdc discharge

value than Lb1 and Lb2 (approximately 10 times larger),path.

preventing most of the high-frequency current fromflowing into the input source and subsequently improving

The second challenge is resuming operation of theEMI. In addition, the reduced ripple current in Lg1 and Lg2

PFC after restoring AC. The central issue of this event

enables the possible use of lower-cost core materials.

comes from the fact that the bypass diodes on the PFC

Figure 1 also illustrates the ripple current envelopes forcharges the output voltage to the peak of the input sine

the inductors and switch nodes.

wave, which occurs most readily at high line when the
output voltage has fallen well below this peak value.

AC dropout technical challenges

During these events, the converter has no mechanism

The first challenge that I want to highlight is

to stop the current, making the surge current very large.

reverse-current generation when the AC input voltage

Improper control of the switches during these events candisappears. Since all of the switches in the totem-

make things much worse by saturating the inductors,pole PFC topology are bidirectional, it is essential

creating OCP events and further discharging the output

that the FETs operating as synchronous rectifiers shutvoltage. The need for a precise control algorithm during

off as quickly as possible when removing AC. This

this time is again multiplied by the high-frequency

shutoff prevents the generation of a negative current

operation point of the iTCM topology with the small-valuethat will cause the output voltage to discharge andinductors used for Lb1 and Lb2.

reduce the available holdup time. Figure 2 illustrates
the path for generating this negative current for theAC dropout solution

synchronous conduction interval during the positive half

In order to precisely determine the presence andcycle. In addition, any substantial delays in turning off

absence of the AC input, the solution uses a virtual

the synchronous rectifiers can also result in a large

AC input signal that monitors the integrity of the actual

current spike capable of activating overcurrent protection

AC input. This virtual signal is generated by measuring(OCP). For example, if the synchronous rectifier stays

the input voltage amplitude, frequency and phase, suchon when no input voltage is present, you can solvethat during normal operation it tracks the 50- and 60-Hz

dI
Vdc = Lb1 ⋅ dt1 for the amount of time it takes to generatecomponent of the actual AC input nearly perfectly. The
system can easily recognize the presence and absence

70 A of current, namely 2.5 µs. This short time presentsof the AC input voltage by comparing the actual input toa significant problem for the AC dropout detection to

the virtual input. Any sudden changes in the difference

identify the problem and stop switching before thebetween these two signals indicates an input transient

system hits OCP or causes damage.

event. It is this transient event that is used to detect boththe loss and restoration of the AC input voltage. Figure 3
illustrates the virtual AC input, along with the actual input
during a dropout event.

Solving AC dropout recovery in a high-density GaN-optimized PFC converter

28

ADJ 3Q 2023

Analog Design Journal
No
Sync Init

Sync On

Stop
Switching

Yes
Start UpAC Drop?
No
ResumeResumeReady

Yes
AC Restore?

Figure 4. AC dropout and restore state machine.

Results
Figure 5 illustrates the performance of the two-phase
iTCM totem-pole PFC with the aforementioned algorithm
during an AC dropout and restore event. The AC input
voltage is 230 VRMS at 60 Hz and the output voltage

Figure 3. AC input dropout with the virtual AC signal.

is 400 V. The load is 5 kW (400 V, 12.5 A) of constantFigure 4 illustrates the state machine that governs thecurrent with a 20-ms AC dropout event. In order todropout and restore process. During startup, the systemproduce the worst-case stress for the system, AC wasgoes through an initialization cycle (Sync Init) where it

removed such that it would return at the peak of the AC

determines the RMS input voltage magnitude. It uses aline cycle. This is the worst case for inrush current, insoftware phase-locked loop (SPLL) to ensure that thethat the input bypass diodes will cause significant inrush

phase of Vac,virtual matches Vac,actual. Once the SPLL

current into the output capacitors when the AC line peakis locked (Sync On), the processor monitors the ratio

exceeds VOUT.

between Vac,actual/Vac,virtual (see Figure 3). If this ratio is

The waveform in Figure 5 also provides an image

less than the target threshold, then a dropout event iszoomed in on the recovery portion of the event.

declared and switching stops immediately (Stop State).

It is clearly visible that the PFC switch current is

From here, the system clears any faults that occurred

well controlled and below the GaN FET OCP limit

and goes into a standby state (Ready), where it monitors[12]. Minimized reverse current prevents unnecessary

the Vac,actual/Vac,virtual ratio to determine when it goes

discharge of VOUT. In addition, there is no abnormal

above the resume threshold. Once the state machine

behavior from the bypass diode conduction intervals,

has determined that AC is restored, it resumes switching

since the algorithm is able to easily determine whether

immediately and resynchronizes the SPLL (Resume

the input voltage is above or equal to the output voltage.

State). By using the Vac,actual/Vac,virtual ratio in concert
with the SPLL, the algorithm is able to determine theAC dropout and restore times for any input voltage
or frequency. In addition, since the algorithm always

Isw,a

Lg1
Iac

monitors the ratio Vac,actual/Vac,virtual, it is able to respond

Vac

S21

S22
S4

Lg2
Lb1

Lb2
Vout

Cb

more quickly than a traditional level-based-solution that

S11

S3

S12

detects when the AC input voltage goes to zero. Levelbased monitoring for dropout can create delays thatcan result in large current spikes and significant reverse

Figure 5. AC dropout and restore performance at 5 kW.

current.

Solving AC dropout recovery in a high-density GaN-optimized PFC converter

29

ADJ 3Q 2023

Analog Design Journal
In addition to AC dropout, the design also delivers low

and Drives Systems, pp. 1542-1546. doi: 10.1109/

THD, high efficiency, high power density and fast load

PEDS.2005.1619933.

transient response.

7. Xu, Xiaojun, and Alex Q. Huang. A Novel Closed

If you are interested in more details on this algorithm

Loop Interleaving Strategy of Multiphase Criticalor other aspects of this design, you can find the fullMode Boost PFC Converters. Published in 2008

schematics, layout, bill of materials, test results and code

Twenty-Third Annual IEEE Applied Power Electronics

for the two-phase totem-pole PFC reference design in

Conference and Exposition (APEC), pp. 1033-1038.

reference [10].

doi: 10.1109/APEC.2008.4522849.
8. Neumayr, D., D. Bortis, E. Hatipoglu, J.W. Kolar,

References

and G. Deboy. Novel Efficiency-Optimal Frequency

1. V2 Power Shelf Specification 6600W @ 12.6V

Modulation for High Power Density DC/AC

DC (2+1) Redundant. OPEN Compute Project.

Converter Systems. Published in 2017 IEEE 3rd

Facebook: Menlo Park, California, February 2015.

International Future Energy Electronics Conference
and ECCE Asia (IFEEC 2017-ECCE Asia), pp.

2. Fernandes, Ryan, and Olivier Trescases. A
Multimode 1-MHz PFC Front End With Digital Peak

834-839. doi: 10.1109/IFEEC.2017.7992148.

Current Modulation. Published in IEEE Transactions

9. Rothmund, Daniel, Dominik Bortis, Jonas Huber,on Power Electronics 31, no. 8 (August 2016): pp.

Davide Biadene, and Johann W. Kolar. 10 kV SiC-

5694-5708. doi: 10.1109/TPEL.2015.2499194.

Based Bidirectional Soft-Switching Single-Phase
AC/DC Converter Concept for Medium-Voltage

3. Lim, Shu Fan, and Ashwin M. Khambadkone.
A Multimode Digital Control Scheme for Boost

Solid-State Transformers. Published in 2017 IEEE

PFC with Higher Efficiency and Power Factor

8th International Symposium on Power Electronics

at Light Load. Published in 2012 Twenty-Seventh

for Distributed Generation Systems (PEDG), pp. 1-8.

Annual IEEE Applied Power Electronics Conference

doi: 10.1109/PEDG.2017.7972488.
10. Texas Instruments. n.d. Variable-Frequency, ZVS,

and Exposition (APEC), pp. 291-298. doi: 10.1109/

5-kW, GaN-Based, Two-Phase Totem-Pole PFC

APEC.2012.6165833.

Reference Design. Texas Instruments reference

4. Huang, Long, Wenxi Yao, and Zhengyu Lu.

design No. PMP40988. Accessed Dec. 27, 2022.

Interleaved Totem-Pole Bridgeless PFC Rectifier

11. Texas Instruments. n.d. C2000™ 32-Bit MCU

with ZVS and Low Input Current Ripple. Publishedin 2015 IEEE Energy Conversion Congress andwith 100-MHz, FPU, TMU, 256-kb Flash, CLA,

Exposition (ECCE), pp. 166-171. doi: 10.1109/

InstaSPIN-FOC™, CLB, PGAs, SDFM. Accessed

ECCE.2015.7309684.

Dec. 27, 2022.
12. Texas Instruments. n.d. Automotive 650-V 30-mΩ

5. Liu, Zhengyang. 2017. Characterization andApplication of Wide-Band-Gap Devices for HighGaN FET with Integrated Driver, Protection andFrequency Power Conversion. Ph.D. dissertation,

Temperature Reporting. Accessed Dec. 27, 2022.

Virginia Polytechnic Institute and State University.
6. Kim, J.W., S.M. Choi, and K.T. Kim. Variable OnTime Control of the Critical Conduction Mode
Boost Power Factor Correction Converter to
Improve Zero-Crossing Distortion. Published in2005 International Conference on Power Electronics

Solving AC dropout recovery in a high-density GaN-optimized PFC converter

30

ADJ 3Q 2023

Analog Design Journal

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2023 Texas Instruments Incorporated

SLYT844

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