Single-phase power decoupling technique utilizing
Hybrid method with passive and active power
decoupling
Hiroki Watanabe

Jun-ichi Itoh

Quentin Roudier

Dept. of Energy Environment Science
Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japanhwatanabe@vos.nagaokaut.ac.jp

Dept. of Electric Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Dept. of Electric Engineering
ESIEE in Amiensamiens, France
roudier_q@esiee-amiens.fr

Abstract— This paper proposes a power decoupling method
utilizing active and passive method to improve the power
density. The active power decoupling techniques compensate thedouble-line frequency power ripple with a small capacitor.
However, when whole power ripple is compensated by the active
power decoupling circuit, the total volume becomes large due tothe additional component in comparison with the passive
method with large electrolytic capacitor. The proposed method
limits the power ripple compensation value of the power
decoupling circuit in order to reduce the buffer capacitance or
peak capacitor voltage. Instead, the small electrolytic capacitor
is installed on DC-link for the power decoupling capability. In
this method, the DC-link capacitor is smaller than that in thepassive power decoupling circuit owing to the small buffer
power and the low ripple current. From the experimental result,the second order harmonics is reduced by 76.8% by the DC
active filter with the small capacitor of 60 μF. Finally, the power
density of the DC active filter with the hybrid method isimproved by 38% in comparison with the whole active power
decoupling operation.
Keywords— Grid connected inverter, double-line frequency
power ripple, power decouplingI.

INTRODUCTION

The single phase grid connected inverters are utilizing for
DC to single-phase AC power conversion system such as
photovoltaic (PV) systems or battery energy storage systems
and so on [1]. These converter needs the high efficiency
conversion, high reliability, and miniaturization in order toenhance the convenience. Recently, the conversion efficiency
has been drastically improved by the wide-band gap devices
as SiC-MOSFET [2]. In the DC to single-phase AC system,
the double-line frequency power ripple is issue for MPPT
performance or battery life-time enhancement. Therefore, thepassive power decoupling which use a bulky electrolytic
capacitor is necessary. On the other hand, PV system
reliability evaluation have been reported by researchers, and it
is presented that an electrolytic capacitor limits the life-timeof the converter [3].
According to this problem, the active power decouplingtechniques which have a firm or ceramic capacitor are
attracted as the one of this solutions [4]-[6]. The active power
decoupling circuit charges and discharges the decoupling
capacitor in order to absorb the double-line frequency power
ripple, which enables to small capacitor. As a result, large
electrolytic capacitor does not necessary. The typical active
power decoupling topology is the DC active filter (DCA)
which is composed to of the boost converter or buck converter.

978-1-5386-6054-6/18/$31.00 ©2018 IEEE

The DC active filter is connected in parallel with the main
circuit, and it compensates the power ripple by the small
capacitor.
The authors have reported the power density evaluation of
the passive power decoupling circuit and the active power
decoupling circuit with DC active filter [7]. In this report, thecomponent volume miniaturization for active method isrequired to reach the power density of the passive method. In
particular, if the whole power ripple is compensated by thepower decoupling circuit, then the ripple voltage of the buffer
capacitor becomes large. On the other hand, the buffer
capacitor voltage has to keep more than the DC-link voltage
for the DC active filter control. As the result, minimum
capacitance value is increased.
This paper presents a hybrid power decoupling techniqueusing the active power decoupling capability and the passive
power decoupling capability. In this method, the active power
decoupling circuit limits the compensation value of the power
ripple in order to reduce the buffer capacitance or buffer
capacitor peak voltage. In this case, the power ripple still
occurs on DC-link. Therefore, the remaining double-line
frequency component is compensated by the DC-link
capacitor like a passive active power decoupling. Note that theDC link capacitance is reduced in comparison with that of thetypical passive power decoupling circuit because the buffer
power on DC link capacitor becomes small by the active
method. Besides, the low-order ripple current can suppress
owing to the active power decoupling circuit.
The remainder of this paper is organized as follows. In
section II, the configuration of the proposed converter andfundamental principle of the power decoupling are explained.
In section III, the detail of the power decoupling control is
explained. In section IV, the circuit design principle of thepassive method and the power decoupling circuit isintroduced. Finally, the experimental result and the power
density comparison among the passive power decoupling,
active power decoupling circuit, and the proposed method aredemonstrated.
II. CIRCUIT CONFIGURATION
Fig. 1 shows the single-phase grid-connected inverter witha boost converter. In this converter topology, a bulky
electrolytic capacitor Cdc is necessary on the DC-link to absorb
the double-line frequency power ripple by the single-phasegrid.

Fig. 2 shows a boost type DCA circuit which consists ofboost converter and a small buffer capacitor Cbuf to absorb the
double-line frequency power ripple on DC- link. The
capacitor Cbuf has the small capacitance, thus the long life-time
capacitor such as a film or a ceramic capacitor is usually usedinstead of electrolytic capacitor.
Fig. 3 shows the principle of the power decoupling
compensation. When both the output voltage and current
waveforms are sinusoidal, the instantaneous output power poutis given bypout =

Vacp I acp
2(1 − cos 2ωt )(1)

Fig. 1. Typical configuration of DC to single-phase AC grid connected
inverter. Large electrolytic capacitor is installed on DC link in order toachieve power decoupling.

where Vacp is the peak grid voltage, Iacp is the peak inverter
output current, and ω is the angular frequency of the gridvoltage [8]. As shown in (1), pout includes the frequency
component of the double line frequency. This frequency
component should be compensate by the energy buffer inorder to obtain the constant DC input power.
In order to absorb this power fluctuation, theinstantaneous buffer power pbuf should be controlled by1
pbuf = Vacp I acp cos 2ωt2(2)

When the pbuf is obtained as (2), the PV input power Pinbecomes constant, and it is expressed as1
pin = Vacp I acp = Vin Iin
2

Fig. 2. Circuit configuration of boost type DC active filter. Buffer
capacitor voltage Vcbuf is regulated more than the DC link voltage Vdc.
proposed hybrid power decoupling is achieved by small buffer capacitor
Cbuf and DC link capacitor Cdc.

(3)

III. CONTROL BLOCK DIAGRAM
Fig.4 shows the control block diagram for each converter.
In the boost converter control, an input current control with PI
control is applied to regulate the PV input current. On the other
hand, the DC-link voltage and the inverter output current
control are implemented on the Voltage Source Inverter(VSI). The DC link voltage is regulated to be higher than thepeak grid voltage Vacp, and the inverter output current is
controlled to sinusoidal waveforms.
The DCA control consists of the buffer capacitor averagevoltage control and the current control. In order to implement
the active power decoupling capability, the feed forward
control is applied to current control. The feed forward current
is expressed as

iamp =

Pcomp*
Vdc

cos 2ωt(4)

where Pcomp* is the compensation value of the power ripple.
Vdc is the DC-link voltage. In order to reduce the capacitanceof the buffer capacitor Cbuf, the capacitor voltage is actively
fluctuated at double-line frequency of the single-phase grid.
However, the response speed of the voltage control islimited to slow in comparison with the response speed of the

V I
pout = acp acp (1 − cos2ωt )2Fig. 3. Principle of the power ripple compensation. Buffer power Pbuf ischarge and discharge by the buffer capacitor Cbuf. The Pbuf is given by
the mismatch between input power Pin and output power Pout.

current control for control stabilization. Thus, the active
power decoupling control is applied to the current control
directly. On the other hand, the voltage control regulates only
average voltage of Cbuf. In addition, the band eliminate filter
which has double-line frequency elimination is installed to thedetection part of Vcbuf.
Owing to the active power decoupling control, the power
ripple is compensated by the small capacitor Cbuf. Note that,the capacitance of Cbuf is expressed asPcomp *Cbuf =

ωVave _ cbuf ΔVcbuf(5)

where Vave is the average voltage. ΔVcbuf is the ripple voltage.
As shown in (5), the buffer power becomes maximum when
the Pcomp* is set to 1 p.u. In addition, the ΔVcbuf becomes large
for reduction of Cbuf. However, it means that the high voltage
rating is necessary for each components. Focusing on thecapacitor volume, it depends on the capacitance and thevoltage rating.
In order to solve this problem, the hybrid power decouplingwith Cbuf and Cdc is proposed. In this method, the Pcomp* islimited to reduce the ΔVcbuf or Cbuf. The differential value
between the buffer power and the actual ripple power iscompensated by the DC-link capacitor Cdc. In this case, thecapacitance of Cdc is expressed as
C dc =

Pdiff

Sinθ

θ

Fig. 4. Control method of the DC active filter. Feed forward control isapplied to current control for active power decoupling.

(6)

ωVave _ cdc ΔVdc

3

Pdiff = Pbuf _ 1 p .u . − Pcomp*(7)

where Pdiff is the differential power between actual ripple
power and compensation power of the DCA. ΔVdc is the ripple
voltage of Vdc. The case of passive power decoupling, the ΔVdc
is designed to small in order to obtain the constant value. As aresult, the Cdc is drastically increase. The proposed power
decoupling method obtains the buffer energy from both the
Cbuf and Cdc. Therefore, the Pdiff can be reduced in comparison
with the passive power decoupling. Finally, the ripple currentof the double-line frequency can be suppressed by the DCA.
Thus, the Cdc can choose the small electrolytic capacitor withlow capacitance. Besides, the life-time of Cdc can be improvedby the small ripple current.
IV.

 L I 2 4
Vol_ Ldc = K v  dc max  K u Bmax J 

CIRCUIT DESIGNThis section introduce the circuit design of the boost
converter and the DCA in order to discuss the power densityof the power converter. In this paper, the design method of the
VSI does not include because it is the same in theactive/passive power decoupling capability.
A. Boost converter design
The boost inductor Ldc is designed by the ripple current
condition. The inductance of Ldc is expresses as

where Kv is the volume coefficient, Imax is the maximum
current of the inductor, Ku is the fill factor of the window, Bmax
is the maximum flux density, and J is the current density of
the wire.
Fig. 5 shows the relationship between the compensation
value Pcomp* and the capacitance of Cdc. Note that the DC-link
capacitance is designed from (6). According to Fig.5, thecapacitance is reduced when the Pcomp* is increased. In
particular, the capacitance for the power decoupling becomeszero when the pcomp* is set to 1 p.u.. Actually, the small
capacitor is necessary for the VSI control and the switchingfilter. Therefore, the small ceramic capacitor should beinstalled on DC-link because the capacity requirement of Cdc
is very small.
On the other hand, the electrolytic capacitor should beselected when the Pcomp* is small because the large capacitanceis required for the power decoupling capability.
The electrolytic capacitor is selected based on thecapacitance from Fig. 5, and the allowable ripple current. With
the frequency multipliers, the allowable ripple current iscalculated by

I rms _ cap =Vin Vdc − Vin
Ldc =ΔI Ldc f sw Vdc(8)

where Vin is the PV input voltage, Vdc is the DC-link voltage,
ΔILdc is the ripple current, fsw is the switching frequency.
The inductor volume is decided from many parameters of
the components, and there are a lot of ways to choose the core
for the inductor. In this paper, the inductor volume is decided
from an area product concept using the window area and thecross-sectional area.
The volume of the Ldc is calculated by(9)

I100 Hz _ rms
K100 Hz2 1  ∞
I nsw 2
+
 
n
1
=
 K sw (10)

where I100Hz_rms is the effective current whose frequencies aredouble line frequency of the single-phase grid, Insw is theeffective current at the switching frequency, K100Hz and Ksw are
the frequency multipliers at 100 Hz and the switchingfrequency, respectively. An electrolytic capacitor, which has
the allowable ripple current higher than the result of (10),should be required. In the passive method, the large ripple
current rating is necessary because the I100Hz_rms is becomeslarge. However, the hybrid method can reduce the ripple
current with low-order harmonics by the DC active filter.
Therefore, an electrolytic capacitor with low current rating canselect in the proposed method.

Fig. 6 shows the relationship between the low-orderharmonics ripple current through the DC-link capacitor with
100 Hz and the compensation value of Pcomp*. The low-orderripple current is suppressed by the active power decoupling
circuit. Therefore, the small electrolytic capacitor with low
ripple current rating is applied for the hybrid method in orderto improve the power density.
B. DC active filter design
The inductor of DCA Lbuf is also designed from the ripple
current as the boost converter, and the inductance Lbuf isexpressed as

ΔVcbuf) − Vdc
2
ΔV(Vcbuf _ ave + cbuf )2(11)

the ripple current becomes the maximum value when the
difference between the dc-link voltage and the buffer
capacitor voltage reaches the maximum. Therefore, the Lbuf isdesigned at the buffer capacitor peak voltage condition. The
buffer capacitor peak voltage is calculated by (5). The
inductor volume is also calculated from (9). Note that theinductor current becomes small in the hybrid method.
Therefore, the inductor volume is reduced when the Pcomp* is
set to low value.
Fig. 7 shows the relationship between the compensation
value Pcomp* and the minimum buffer capacitance for voltage
control, and Fig.8 shows the relationship between the buffer
capacitor peak voltage and the buffer capacitance condition.
The buffer capacitor voltage has to keep more than the DClink voltage due to the boost-up operation. According to Fig.
7, the minimum value of the Cbuf becomes large when the
Pcomp* is increased. This is because the ripple voltage ΔVbuf
becomes large. Therefore, the small buffer capacitor is
obtained when Pcomp* is set to low value. In addition, thecapacitance of Cbuf is drastically reduced when the averagevoltage Vcbuf_ave is set to high. On the other hand, the buffer
capacitor peak voltage becomes large from Fig. 8. As theresult, the switching loss of the DCA increases. However, thepeak voltage condition is changed due to the buffer
capacitance design. For example, the peak voltage is reduced
when the Cbuf is the same at each compensation value.
Therefore, the relationship between the heat sink volume andthe buffer capacitor volume has the trade-off because thebuffer capacitor is designed to minimum value at eachcompensation condition, the peak buffer capacitor becomessame.
C. Heat sink design
Generally, the cooling system volume is decided from thethermal resistance. In this paper, the cooling system volume isdesigned by the Cooling System Performance Index (CSPI).
CSPI means the cooling performance per unit volume of thecooling system. The cooling system is miniaturized when
CSPI become higher. The volume of the cooling system
Volheatsink is given by
Vol heatsink =1
Rth ( f − a )CSPI

Fig. 5. Relationship between compensation value and capacitance of Cdc.
the DC link capacitor volume becomes small when compensation value
increases.

Fig. 6. Relationship between compensation value and capacitance of Cdc.
the DC link capacitor volume becomes small when compensation value
increases.
35
30
Buffer capacitance minimum
value for voltage control [ F]

ΔI Lbuf f sw

(Vcbuf _ ave +DC link voltage Vdc : 400 V
1 p.u. : 1 kW

Vcbuf_ave = 500 V

25
20
Vcbuf_ave = 600 V

15
10
5

Vcbuf_ave = 700 V

0
0.2

0.4

0.6
0.8
Compensation value Pcomp* [p.u.]

1

Fig. 7. Buffer capacitor minimum value when average voltage is changed.

Peak voltage of Cbuf [V]Lbuf =

Vdc(12)
Fig. 8. Peak voltage of buffer capacitor when capacitor condition ischanged.

where Rth(f-a) is the thermal resistance of the cooling system
which is given byRth( f − a ) =T j − TaPloss

Table. I. Experimental condition.

(13)

where Tj is the junction temperature of the switching device,
Ta is the ambient temperature, and Ploss is the converter losses.
The total loss Ploss, which is composed of the conduction loss
Ploss_cond and the switching loss Ploss_sw from the switching
devices, and there are given by following equation.

1 Tout 2
0 iLbuf ron _ buffer dt
Tout

(14)

1
( eon + eoff ) f sw T1 0Tout vcbuf iLbuf dt
Edcd I md
out

(15)

Ploss _ cond _ buffer =Ploss _ sw _ buffer =respectively, where, Tout is the period of the grid, ron is the onresistance of the switching devices, fsw is the switchingfrequency of the DCA, eon and eoff are the turn-on and turn-off
energy per switching referred from a datasheet, respectively,
Edcd and Imd are the voltage and the current under themeasurement condition of the switching loss described in thedatasheet.

(a) Without power decoupling

The boost converter losses are also obtained based on (14)and (15), and it is calculated by

1 Tout 2
0 iLdc ron _ buffer dt
Tout

(16)

1
1 Touteon + eoff ) f sw(
0 vdc iLdc dt
Edcd I md
Tout

(17)

Ploss _ cond _ boost =Ploss _ sw _ boost =V.

EXPERIMENTAL RESULT AND POWER DENSITYEVALUATIONIn this section, the fundamental consideration isdemonstrated by experiment. Table. I shows the experimental
condition.

(b) With power decoupling
Fig. 9. Experimental result with DC active filter. The constant input
current is obtained by the power decoupling control.

Fig. 9 shows the experimental result when Pcomp* is set to
1.0 p.u., and Fig. 10 shows the harmonic analysis result of the
PV input current. According to Fig. 9 (b), the PV input current
becomes constant in comparison with without power
decoupling. In addition, it is confirmed that the buffer
capacitor voltage is fluctuated at the double-line frequency by
the active power decoupling control. Therefore, the active
power decoupling operation is achieved. According to Fig. 10,
the second order harmonics is reduced by 76.8% incomparison with without active power decoupling control.
Table II shows the component parameters, and Fig. 11
shows the pareto front between the power density and theconversion efficiency when the buffer capacitance is changed
to minimum at each condition. In this figure, the boost
converter and the DCA are considered. The conversion losses
are calculated from (14) to (17). In addition, the electrolytic
capacitor is selected based on the minimum capacitance value
for the power decoupling and the low-order harmonics current
ripple. Finally, the power density of the active power

Fig. 10. Harmonic analysis result. The second order harmonics is reducedby 76.8% in comparison with without power decoupling.

decoupling circuit based on the flying capacitor DC/DC
converter (FCC) without the additional components is also
considered. Note that the detail of the converter operation andthe circuit configuration is introduced in [8].

According to Fig. 11, the power density of the DC active
filter with whole power decoupling is 4.32 kW/dm3. On theother hand, the power density of the DC active filter withhybrid method is improved by 38% when the Pcomp* is set to
0.2 p.u.. This is because the buffer inductor volume isdrastically reduced. On the other hand, the power density of
the FCC becomes high more than the DCA and passive
method because this circuit does not need the additional
inductor for the power decoupling capability. The power
density of the FCC with the hybrid method is also improved
by 7%. This is because the flying capacitor volume is reduced.

VI.

Symbol[3][4]

Ceramic capacitor
SP 900 (TDK)

5 F/900 V

EKHS501VSN820MP30S(United Chemi-Con)

82 F/500 V
0.7A@100 Hz

SCT3030KL(ROHM sem.)

1200V/72A 30m

SCT3017AL(ROHM sem.)

650V/118A 17m

7.11kW/dm3 7.68kW/dm@ 60kHz@ 60kHz

99.5

3

Pcomp*= 0.2 *Pcomp = 0.5
Pcomp*= 0.8
Pcomp*= 1.0

99
98.5

5.98kW/dm3@ 100kHz
4.32kW/dm3@ 100kHz98
97.5

Pcomp*= 0.5
Pcomp*= 0.2

Boost conv. and DC active filter

97

FCC
Boost conv. and passive method

0

1

2

3
4
5
Power density [kW/dm3]

Pcomp*= 0.8
Pcomp*= 1.0
6

7

8

Fig. 11. Parato front with constant buffer voltage condition.
100
99.5

Pcomp*= 0.2
Pcomp*= 0.5
Pcomp*= 0.8
Pcomp*= 1.0

99
98.5
98

Boost conv. and DC active filter

Boost conv. and passive method

Pcomp*= 0.2
Pcomp*= 0.5
Pcomp*= 0.8
Pcomp*= 1.0

1

6

97.5

FCC

97
96.5

REFERENCES

[2]

Cbuf

100

CONCLUSION

Mitsumasa Ushiroda, Takaaki Wakimoto, Hiroaki Yamada, Toshihiko
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6, pp. 2905-2910, (2015)

400 V
1 kW
600 V

DCA,
Switching Boost conv.
devices
FCC

This paper proposed the hybrid power decoupling method
utilizing the active power decoupling circuit and passive
power decoupling to reduce the circuit volume. The proposed
method uses the active power decoupling circuit and the small
electrolytic capacitor in order to compensate the power ripple.
As the experimental result, the second order harmonics of
input current is reduced by 76.8%. Finally, the power densityof the hybrid method is improved by 38% in comparison withthe full power decoupling control. In addition, the FCC withthe hybrid method is obtained the high power density incomparison with the passive method and the DCA.

[1]

DC link voltage
Rated power
Buffer capacitor average vol.

Electrolytic capacitor

96.5

Value

Quantity

Vdc
PratedVcbuf_ave

Cdc

Efficiency [%]Fig. 12 shows the pareto front when the buffer capacitanceis the same at each condition. In this case, the buffer
capacitance is designed by the whole power decoupling
condition. According to Fig. 12, the each power density of the
DCA with the hybrid method is improved because the buffer
inductor and the heat sink volume becomes small. However,the power density of the FCC with the hybrid method isdecreased. This is because the boost inductor current is thesame at each condition. In other words the power density of
the FCC depends on the DC-link capacitor, and the heat sink.
In this case, the increasing rate of the DC-link capacitor
volume is large in comparison with the reduction of the heatsink volume. As the result, the power density becomes low.
According to Fig. 11 and 12, it is confirmed that the buffer
capacitor minimization design with the hybrid method
achieves the high power density.

Table. II. Device parameters.

0

2

3
4
5
Power density [kW/dm3]

78

Fig. 12. Parato front with constant buffer capacitor condition.
[5]
[6]

[7]

[8]

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