Pattern Design Criteria of Main Circuit Using Printed
Circuit Boards for Parasitic Inductance Reduction
Ayato Sagehashi , Keisuke Kusaka , Koji Orikawa ,Jun-ichi Itoh
Nagaoka University of Technology
Dept. of Electrical, Electronics and Information Engineering
Nagaoka, Niigata, Japansagehashi@stn.nagaokaut.ac.jp,
kusaka@stn.nagaokaut.ac.jp, orikawa@vos.nagaokaut.ac.jp,
itoh@vos.nagaokaut.ac.jp
Abstract— This paper investigates differences of parasitic
inductances caused by DC bus bar patterns on printed circuitboards(PCB). The DC bus bar pattern on the PCB is limited
depending on the layout of main circuits and the control circuits.
Two patterns which are a laminated wiring pattern and a planewiring pattern are compared in experiments and simulations. In
this paper, it will be clarified that effects of the DC bus bars on
PCBs such as a surge voltage of a switch in terms of the parasitic
inductance depending on the circuits on PCBs. As a result, if thesame parasitic inductance which is 20 nH, is realized between
each wiring pattern at the same length, the plane wiring pattern
requires over ten times of the pattern width compared with thatof the laminated wiring pattern. Hence, the circuit size can be
downsized when the laminated pattern is used. From theexperimental results, the maximum surge voltage in the planewiring pattern is larger than that in the laminated wiring pattern.
In this case, the parasitic inductance value of the plane wiring
pattern is three times that of the laminated wiring pattern.
However, the surge voltage in the laminated pattern is reduced
by 7% compared with the plane wiring pattern. As aconsequence, the ratio of the surge voltage does not match that ofthe parasitic inductance. As a result, not only the parasitic
inductance of the DC bus bar but also it is necessary to consider
other parasitic inductances on PCBs such as parasitic
inductances into input capacitors and the path between an upper
MOSFET and a lower one and so on.
Keywords- printed circuit board; parasitic inductance; frontloading; laminatedI.

INTRODUCTION

In recent years, design methods of a power converter on the
PCB are increasingly studied since a high frequency operationis one of solutions to downsize a volume of the power
converter [1]. However, high frequency switching often causes
problems on the parasitic inductance and EMI[2]. Therefore,
investigation techniques regarding the reduction of the parasitic
inductance and EMI countermeasures become important more
and more [3]. So far, in developments of power converters, theprototype is tried to make many times after a specification of
the circuit had been decided and designed. In addition, theparasitic inductances and noises can be evaluated by only

Akio Momma
Unipulse Corporation
Product Planning Headquarters
Nihonbashi, Tokyo, Japanakio_momma@unipulse.co.jp

experiments. It causes the increase of the cost for aexperimental production because the evaluation and redesign
are held through a repeating experiments and redesigns. Thus,
conventional methods increase the development cost of a
prototype and spends a long time for the development of theconverter.
In contrast, a front loading design has recently attracted in
the design of power converters. This method is alreadyestablished in the field of the design of LSIs. It obtains an exact
analysis about EMI and the heating by a simulation. Thus, themaking of a prototype is not needed many times by applying
the front loading design. As a result, the development period
and the cost will be reduced. However, the front loading designof the power converter is not commonly used. Moreover,verifications of EMI and the heating in power converters by
simulation are difficult compared to that of LSIs because therated power of the power converter is so large.
On the other hand, the DC bus bar is often analyzed in the
power converter in terms of the surge voltage due to parasitic
inductances. In general, patterns of the plane and the laminatedare known well as the DC bus bar to reduce the parasitic
inductance [4]. When the condition between DC bus bars areinto vacuum or air, the parasitic parameters of two wiring
patterns has been verified [5]-[13]. Especially, the laminatedpattern is superior in terms of low surge voltage due to a low
parasitic inductance. On the other hand, recently, main circuits,
control circuits and gate drive circuits are implemented onsame PCBs in order to downsize the power converter. However,effects of the DC bus bars on PCBs such as the surge voltage
of a switch and so on have not been clarified [14]-[16]. In thecase of a laminated wiring pattern, the resistance of the wiring
pattern can be small if the wiring pattern length can be short.
However, the laminated wiring pattern may be not usedbecause of layouts of control circuits, gate drive circuits and soon. Additionally, using a plane wiring pattern, the wiring
pattern resistance is reduced than another one when the wiring
pattern length cannot be shorten. However, the wiring pattern
width of the plane wiring pattern should be much wider thanthat of the laminated pattern in order to obtain parasitic
inductance as small as the laminated wiring pattern. From theSpecification(Vin, Vout, P, fsw etc)

above, an investigation and design of the DC bus bar wiring
pattern on the PCB is required in order to use the plane wiring
pattern and the laminate wiring pattern depending on circuitspecifications.

Circuit toporogy
Select elements

In this paper, the laminated wiring pattern which is superior
in terms of the small parasitic inductance and the plane wiring
pattern which can flow more current compared with thelaminated wiring pattern, are compared. First, parasitic
inductances of these wiring pattern is analyzed by Agilent
advanced design system (ADS) using a S parameter. Finally,
the surge voltage between the drain and source of MOSFETs
on PCBs is measured. As a result, a relationship between eachparasitic inductance of the DC bus bar on PCBs and the surge
voltage between the drain and source of MOSFETs will beclarified.

Pattern layout
VsurgeNo
is under the rated voltage?

Analysis ofpattern inductanceYes
Simulation of
circuits operation

Make circuits
Evaluate circuits
No

Specification
is satisfied?
Yes
CompletedII.

CIRCUIT DESIGNIn this paper, the voltage-source single-phase inverter isused as an analysis object. When this circuit is designed, somecomponents are provided in this circuit design. Some
components of the circuit design consists of a specification of asystem, a circuit topology, switching elements, the circuit size,
control circuits, and so on. In addition, an operation of thiscircuit is considered by simulations in design process. Then, abuildup of the circuit is started. However, it is rare case thatfirst prototype shows the desired operation, which is obtainedby the simulation, because the actual circuit has some factor
which does not appear in the simulation result.
Fig. 1 shows the conventional flow chart of the circuitdesign. In general, in the circuit design, specifications is
decided before the circuit topology is decided. Then, someelements of circuit are selected. When the circuit design isdelicate, parasitic inductances of the wiring pattern has to beconsidered. In this case, a selection and an analysis of wiring
pattern layout are included. In addition, the operation of thecircuit is considered by simulation using previous process
results. After that, the circuit is made. Finally, the operation of
the accomplished circuit is verified. If this circuit is satisfied
the specification, all process is finished.
However, there is a case, in which the completed circuit
doesn’t satisfy the specification. In this case, the working
process is returned, it is necessary to select elements again. In
addition, much time and costs are required to redesign thecircuit and a consideration of circuit operation. This redesign
process can be prevented if the circuit parameter is set finely,
and this circuit operation is simulated minutely. Hence, thefront loading design method needs to be applied to the power
converter design. Although, when this method is applied to thepower converter design, the actual phenomenon of the power
converter is analyzed in the design process.
Therefore, this paper focuses on the setting of the wiring
pattern layout, the analysis and simulation of the wiring pattern
inductance, and the consideration of the surge voltage at theswitching devices in the circuit design.

Fig. 1. Flow chart of circuit design

P line
LP

Vin

S1

S3

Cin

R
S2

Vout

S4

LN
N lineWiring pattern

fsw=1 MHz

Fig. 2. Circuit schematic of the inverter.

III.

WIRING PATTERN LAYOUT

Fig. 2 shows the circuit diagram of voltage-source singlephase inverter. In Fig. 2, parasitic inductances LP and LN on the
DC bus bars are the wiring pattern of analysis objects. Here,the detail of two wiring patterns used to analysis is described.
A. Plane Wiring PatternFig. 3 shows the pattern diagram when the wiring pattern
are placed in parallel on the same plane. In this pattern, theparasitic inductance LP and LN of wiring patterns are placed on
the same plane. Besides, when the actual circuit board isdesigned, wiring width W is decided depending on theallowable current. In addition, the wiring distance d is decided
by applied voltage of the power inverter because it is necessary
to consider about a distance of insulating on the operation.
B. Laminated Wiring PatternFig. 4 shows the pattern diagram when the wiring pattern
are placed on the both sides of a PCB. In this structure,parasitic inductances LP and LN of wiring patterns are placed on
the glass epoxy substrate of PCB material between two wiring
patterns. Also, the parasitic inductance is simulated at same
condition in order to compare to that of the plane wiring pattern.
In this case, the board thickness D of the laminated wiring

pattern and the wiring distance d of the plane wiring pattern
have same values in order to ensure the same wiring distance
between the laminated wiring pattern and the plane wiring
pattern.

Current direction
L

Note that, when the actual circuit is designed, the board
thickness D is necessary to be decided by a rated operating
voltage range and a dielectric strength voltage similar to theplane wiring pattern.
IV.

Cu
D

H
W

SIMULATION RESULTd Board(FR4)

Fig. 3. Plane wiring pattern layout.

In this chapter, parasitic inductances are calculated andsimulated in order to consider characteristics of two wiring
patterns on the board when the wiring pattern width W, thewiring distance d, the board thickness D and the frequency f arechanged. Besides, in this simulation, S parameters of the wiring
pattern are calculated as the two ports circuit.

L

Cu
D

H

A. Analysis of Inductance using the S parameters
In this section, the detail of the method to calculate theparasitic inductance with an electromagnetic analysis is
explained.

W Board(FR4)
Current direction
Fig. 4. Laminated wiring pattern layout.

Fig. 5 shows the equivalent circuit for analysis ofsimulation. Fig. 6 shows the equivalent circuit of the wiring
pattern. In this simulation, these S parameters S11，S21，S12，
S22 are calculated. S11 is the ratio of reflection of the signal in
Port 1 of Fig. 5. In this case, Port 1 means a signal input part ofthe left side of Fig. 5. In fact, Port 2 means a signal input partof the opposite side. S22 is the ratio of reflection of the signal in
Port 2. Furthermore, S21 is transmission ratio when the signaltransmits from Port 1 to Port 2. S12 is transmission ratio when
the signal transmits from Port 2 to Port 1. These relationships
are shown by (1).

S21

Port1

Port2
a2

a1

Z1
V1

b1

S11

S22
S12

b2

Z2
V2

Wiring pattern a1   S11 S12  a2       b1   S 21 S 22  b2 

Fig. 5. Analysis equivalent circuit of wiring pattern.



In this analysis, the S parameter S11 is used in order tocalculate the inductance. At this time, S11 of S parameter is thesynonymous parameter of coefficient of reflection Thus, S11
is coefficient of reflection First, an input impedance Zin is given by (2) using
coefficient of reflection  by the simulation in order tocalculate the wiring pattern inductance. After that, theinductance L is given by (3) using Zin. In this case, theimpedance of the wiring pattern given by (2) is not only
inductance component; it includes a parasitic capacitance Cp of
between the wirings shown in Fig. 6.



1   Z in  
  Z0 
1  LIm[Z in ]

2f

LS

LS

Port1

Port2
M

CP

M

CP

Fig. 6. Equivalent circuit of wiring pattern.

In this case, Z0 is a characteristic impedance in simulation.
(3) is also expressed by (4) using a self-inductance Ls and amutual inductance M.
L  2( Ls  M ) 







B. Characteristics of Inductance in Difference Width
Fig. 7 shows characteristic of the inductance when thewiring pattern width W of each wiring pattern is changed. In
Fig. 7, the inductance decreases when the wiring pattern W ofeach wiring pattern is increased. This is because that theinductance with the wide wiring pattern width is equivalent toconnecting a number of inductances in parallel. Moreover, theinductance of the laminated wiring pattern can be smaller thanthe plane wiring pattern. It is because that the mutual
inductance M of each wiring pattern is different. In this case,the self-inductance Ls is same value because this value depends
on the size of wiring pattern. On the other hand, the mutual
inductance M is affected by the coupling coefficient between
the each wiring pattern. In this paper, the effect of magnetic
coupling is discussed by subdividing the wiring pattern.
Current on the laminated wiring pattern flows uniformity on
the wiring. Then, the magnetic flux evenly interlink to anotherwiring. In contrast, the interlinkage magnetic flux on the planewiring pattern is smaller than that of the laminated wiring
pattern because the current flows mainly on the both ends ofthe wirings. As a result, the inductance of the laminated wiring
pattern is smaller than that of the plane wiring pattern because
the mutual inductance M of the laminated wiring pattern islarger than that of the plane wiring pattern.

C. Characteristics of Inductance in Difference DistanceFig. 8 shows characteristic of the inductance when thewiring pattern distance d and the board thickness D of eachwiring pattern are changed. In this result, the wiring pattern
distance d and the board thickness D are changed when theplane wiring pattern and the laminated wiring pattern are used,
respectively In Fig. 8, the inductance of the wiring patternincreases when the wiring pattern distance d and board
thickness D increase at each wiring pattern. In addition, theinductance of the laminated wiring pattern is smaller than thatof the plane wiring pattern.
The wiring inductance increases when the wiring pattern
distance d and the board thickness D are increased because themutual inductance M is decreased. In this case, the effect ofmutual inductance M between wiring patterns is small. As aresult, the wiring inductance increases according to (4) because
the mutual inductance M is reduced when the d and D are
increased.
D. Frequency Characteristics of InductanceFig. 9 shows characteristics of inductance of each wiring
pattern when the frequency is changed. In Fig. 9, theL=50 mm
H=0.035 mm
d=4 mm
D=1.6 mm

Inductance [nH]

40
30

Plane

20
Laminated

10
0

2

4

6

8

10

12

14

16

Pattern width W [mm]Fig. 7. Characteristics of wiring pattern inductancein difference width.

L=50 mm
H=0.035 mm
W=15 mm25
20
Inductance [nH]Furthermore, in order to obtain the same inductance value
in each wiring pattern, the plane wiring pattern needs the wide
pattern width. For example, in order to obtain same parasitic
inductance of 20 nH at the same length, the plane wiring
pattern requires over ten times of the pattern width comparedwith that of the laminated wiring pattern. However, if thenarrow wiring pattern is chosen, each parasitic inductance isclosed. At the same time, pattern widths of two wiring patterns
are near value. Consequently, when the downsizing of thecircuit board is required, the laminated wiring pattern issuitable compared to the plane wiring pattern. Whereas thecase of the plane pattern is chosen, the back side of PCB has afree large area to mount the circuit than the other pattern
because there is no pattern on the back side of PCBs. The plane
pattern prevents the design of the control circuit because it
intersects boards. Hence the choice of the wiring pattern
structure strongly affects to the circuit board and so on.

50

Plane

15
10
5
0

Laminated

1

2

3

4

5

6

Board thickness D and wiring distance d [mm]Fig. 8. Characteristics of wiring pattern inductance in difference board
thickness and distance.

inductance of the plane structure is constant value of 20.2 nH,
and that of the laminated structure is constant value of 3.52 nH
even if the operation frequency is changed. In addition, theinductance of laminated wiring pattern is suppressed comparedto the plane wiring pattern.
Those wiring pattern consist of parasitic inductances andparasitic capacitances. However, the inductance is not changed
when the operation frequency is changed because the effect ofparasitic capacitance can be negligible in the operation
frequency from 0 to 3 MHz. Considering the parasitic
capacitance from the impedance, the each impedance isexpressed by (5) where L is the simulation value, f is thefrequency. At this time, the parameter of R is the constant valueof 50 .



1 
Z in  R  j 2fL 
2fC p (5)

C p   0 r



A

d

(6)

Where, 0 is the dielectric constant of vacuum, r is the relative
permittivity, A is the area of the wiring pattern, and d is the
distance between the wiring patterns.
V.

L=50 mm
H=0.035 mm
W=15 mm
d=4 mm
D=1.6 mm

30

Inductance [nH]Also, the parasitic capacitance Cp is calculated using theparameter of analysis structure from (6) because it is difficult
to separate the parasitic capacitance from analysis results.

20

Plane

10

Laminated

EXPERIMENTAL RESULTS

In this section, the analysis result is verified by theexperiments. The high frequency inverter circuit board is usedin the experiment. On a board, each wiring pattern is mounted
on the DC bus bar part. Table 1 shows the wiring patterncondition of a prototype circuit board. In this case, wiring
distance d of each wiring pattern is different because wiring
distance d must be designed depending on the insulation
distance. The voltage between the drain and source of MOSFET VDS in the high frequency inverter circuit is measured toconfirm the validity of the analysis results on both of thelaminated wiring pattern and the plane wiring pattern. After
that, the effect of the inductance on the DC bus bars of the eachwiring pattern is considered.

0

0.5

1

1.5

2

2.5

3

3.5

Frequency [MHz]Fig. 9. Frequency characteristic of each wiring pattern.
Table 1. Wiring pattern condition.
15 mm
30 mm

Pattern Width W
Pattern Length L
Pattern Distance D(Plane type)
Pattern Distance D(Laminate type)

4 mm
1.6 mm
35 mm

Pattern Tickness H

Fig. 10 (a) and (b) show the actual prototypes of the highfrequency inverter circuit board. These circuits are configured
by only the PCBs. The wiring pattern from the input capacitor
to the MOS-FET is DC bus bar. Note that, each wiring patternis the same to the simulation conditions
Fig. 11 (a) and (b) show experimental voltage and current
waveforms of each circuit. Table 2 shows experimental
conditions. As a result, it is confirmed that the maximum surge
voltage of the laminated wiring pattern is reduced by 7% thanthat of the plane wiring pattern. Besides, compering
convergence time of surge voltage toward the steady state
between the plane wiring pattern and the laminated wiring
pattern, it is confirmed that the convergence time of the surge
voltage in the laminated wiring pattern is faster than theanother one because time constant of vibration of the surge
voltage is short in according to a low inductance value of theDC bus line in the laminated structure. Therefore, experimental
results show that the surge voltage between the drain and thesource is according to inductance value of the DC bus bars.
However, the surge voltage in the laminated wiring pattern isreduced by 7% than that of the plane wiring pattern while theparasitic inductance value of the laminated pattern is reduced
about one thirds than that of the plane wiring pattern. This isbecause there are parasitic inductances of input DC link
capacitor and the path between an upper MOSFET and a lower
one. Therefore, not only the parasitic inductance of the DC bus
bars but also it is necessary to consider other parasitic
inductances on PCBs
VI.

CONCLUSION

In this paper, the inductance of the two DC bus wiring
pattern for the high frequency inverter is analyzed. One is theDCinput DCcapacitor
MOSFET+Heatsink

Control circuit(a) Plane structure circuit board.

DC
input

DC
capacitor

MOSFET + Heatsink
Control circuit(b) Laminated structure circuit board.
Fig. 10. Picture of each wiring type circuit board.

plane wiring pattern, the another is the laminated wiring pattern.
In this analysis, the parasitic inductance of each wiring pattern

is considered using S parameters. The prototype circuits, whichhave two wiring patterns, are demonstrated in the experiments.
It is known well that the parasitic inductance of the planewiring pattern is larger than that of the laminated wiring pattern.
However, the surge voltage in the laminated wiring pattern isreduced by 7% than that of the plane wiring pattern while theparasitic inductance value of the laminated pattern is reduced
about one thirds than that of the plane wiring pattern on PCBs.
This is because there are parasitic inductances of input DC link
capacitor and the path between an upper MOSFET and a lower
one. Therefore, not only the parasitic inductance of the DC bus
bars but also it is necessary to consider other parasitic
inductances on PCBs in order to adequately use the planewiring pattern and the laminated wiring pattern depending on
circuit specifications of high-frequency power converters.
In the future work, the wiring inductance will be verified
using the prototype circuit board with the other condition, theseparation of a wiring inductance and a parasitic capacitancewill be considered.

Table 2. Experimental condition.

Dead time td
Switching device
Load

Voltage between drain and source of S3:Vds (20 V/div)0
Output Voltage(20 V/div)0

Output Current(5 A/div)

Time(200 ns/div)0(a) Plane wiring patter.

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