Suppression of Short-circuit Current
in Halt Sequence to StopTwo-level Inverter
connected to PMSM during Regeneration Mode

Tsuyoshi Nagano and Jun-ichi Itoh

Toba Akio

Dept. of Electrical Engineering
Nagaoka University of Technology
Niigata, Japanngn244@stn.nagaokaut.ac.jp /itoh@vos.nagaokaut.ac.jp

Fuji Electric Co., Ltd.
Tokyo, Japan
toba-akio@fujielectric.com

Abstract— This paper discusses an approach to suppress therise of the short-circuit current in a halt sequence which is named“Flux-weakening Short-circuit halt sequence (FSHS)”. When aback-to-back system with a small capacitor is stopped by gridfaults during regeneration, the DC-link capacitor voltage
increases rapidly due to regeneration current. FSHS stops theregeneration operation and suppresses the rise of the DC-link
capacitor voltage without a dynamic brake circuit. However,
FSHS cannot suppress the rise of short-circuit current caused by
the q-axis current which rises during the short-circuit mode
when the regeneration current is low or PMSM with small
synchronous inductance is driven. The improved FSHS
suppresses the rise of the short-circuit current in low-load region
by maintaining the q-axis current around zero until before themode is changed to Sequence II at zero-crossing point of thecurrent. In the experiment, it is confirmed that the improved
FSHS suppresses to 85% of the short-circuit current when theregeneration current is low.

In one of conventional methods to suppress voltage
increasing, a brake chopper circuit is connected in parallel to
the DC-link capacitor, i.e. a dynamic brake circuit [7]. When
the DC-link capacitor voltage exceeds the threshold voltage,
the regeneration power is consumed by the resistance in thebrake chopper circuit. However, the dynamic brake circuit
requires additional switching device and components. Several
methods to reduce the volume of the dynamic
brake
circuit have been reported in Ref. [8]. However, the cost andvolume of the dynamic brake circuit is not desirable in the
power conversion system, even it is operated only for the halt
sequence during the system failures.

Keywords—Permanent magent synchoronous motor, Haltsequence, Short-circuit

I. INTRODUCTION
Recently, power converters are required to reduce thevolume and to improve long life time in adjustable drive
systems with regeneration mode such as elevator, crane,
flywheel energy storage system and so on [1-5]. A back-toback (BTB) system which consists of a PWM rectifier and an
inverter is widely used for this kind of regeneration system. In
order to achieve the improvement of long life time, a film
capacitor is used as a DC-link capacitor [6]. However, thecapacitor with small capacitance causes overvoltage problemsof the DC-link part with grid faults. That is, when the BTB
system is stopped by the grid faults during regeneration, theDC-link voltage increases rapidly. Consequently, the switching
device will be broken when the DC-link capacitor voltage
becomes higher than the voltage rating of them. Therefore, it isnecessary to suppress the voltage rise of the DC-link capacitor
when system accidents occur.

The authors have proposed a halt sequence that shorts theterminal of the motor according to the motor current when thegrid is cutoff during the regeneration mode in order to avoid
the overvoltage of the DC-link capacitor, and also prevents theovercurrent [9-10]. This halt sequence, which is named “Fluxweakening short-circuit halt sequence (FSHS)”, can be also
applied to the regeneration system such as flywheel energy
storage systems. In addition, it is possible to downsize the BTB
system because the dynamic brake circuit is not required in thefux-weakening short-circuit halt sequence. However, the fluxweakening short-circuit halt sequence cannot suppress the riseof short-circuit current caused by the q-axis current which rises
during the short-circuit mode when the regeneration current is
low or PMSM with small synchronous inductance is driven.
Therefore, it is necessary to suppress the rise of the shortcircuit current caused by the q-axis current.
This paper proposes an improved FSHS to suppress the risecurrent of the short-circuit in low-load region. In the improved
FSHS, the q-axis current is maintained around zero by applying
the lagging and leading voltage vector to PMSM depending on
the q-axis current from the end of Sequence I to the beginningof Sequence II in order to suppress the rise of the q-axis current
which causes the rise of the short-circuit current. This paper isorganized as follows; Firstly, the principle of FSHS is
discussed. Second, its problem in the low-load region is
discussed. Next, the principle of the improved FSHS to solveits problem is discussed. Next, the operation of short-circuitcurrent suppression sequence is confirmed in simulation.
Finally, the effectiveness of the short-circuit current
suppression sequence is evaluated in experiments.
II. FLUX-WEAKENING SHORT-CIRCUIT HALT SEQUENCE
A. Principle of short-circuit halt sequenceFig. 1 shows the system configuration of the power
conversion system. This system uses a two-level PWM inverter
and rectifier in order to control an Interior Permanent Magnet
Synchronous Machine (IPMSM). A DC-link capacitor withsmall capacitance is used to absorb the switching ripples. The
regeneration power P from the motor depends on the rotating
speed and braking torque as (1).



CDC

In [9], the flux-weakening short-circuit halt sequence
prevents the over voltage at the DC-link capacitor by shorting
the terminal of motor when the relay is cutoff. The Fluxweakening short-circuit halt sequence consists of two
sequences; in Sequence I, the q-axis current is controlled to
become zero by the reactive power without a current regulator
while the DC-link voltage is maintained within a certain range
by selecting the switching patterns between the charge modeand discharge mode. After the q-axis current becomes zero,
Sequence II is implemented in order to conduct the shortcircuit mode until the d-axis current becomes zero. In a matterof fact, Sequence II alone can achieve this halt sequence andpreventing the DC-link capacitor from overvoltage, since themotor currents are circulating in the inverter during this halt
sequence. However, the motor current will be increased
drastically in high speed region because of the electromotive
force in the motor. As a result of the short circuit condition, thelarge motor current causes the irreversible flux loss in themagnet of PMSM. In addition, the inverter is required to
implement with high current rating switching devices.
Therefore, Sequence I is introduced to prevent the occurrenceof large current. The motor is typically designed in a matterthat the maximum current is allowed up to 2.5 to 3.7 p.u. of the
rated current [11-14]. By implementing Sequence I, themaximum current in the flux-weakening short-circuit halt
sequence is suppressed to less than three times of the rating
current.
Fig. 2 shows the relationship between the voltage command
vector and the motor current vector in Sequence I. The
instantaneous power pout becomes zero when the motor current
vector crosses the inverter voltage vector at the right angles asshown in Fig. 2. However, the instantaneous power pout cannot
always become zero because there are only eight space voltage

PWM rectifier(STOP)

OthersPM

PWM inverter(STOP)

Fig. 1. System configuration of the motor drive system connected to
the grid during the motor regeneration.

q
(110)

(010)
Charging
voltage vectorpinv>0(1)

where is the rotational speed, T is torque of the PMSM, Ld
and Lq are the d-axis and q-axis inductance, e is the linkage
magnetic flux of armature by permanent magnet, id and iq are
the d- and q-axis current, Pn is the number of the pairs of poles.
From (1), the negative torque will cause the increase of theDC-link voltage if the q-axis current is not controlled to zero.
Thus, in order to prevent the overvoltage at the DC-link
voltage, the q-axis current should be zero immediately.

VC

Generator

(100)

(011)
Discharging
voltage vector

pinv<0Motor current
(001)

d

(101)

Fig. 2. Relation between space voltage vector and current vector of
motor in Phase I. The two-level inverter has the switchingpatterns to charge and discharge the DC-link capacitor.
Table 1. Switching pattern of Phase I.

Direction ofcurrent
iu
iv
iw

Discharge

Parallel-off

ChargeP  T  Pniq 3e  Ld  Lq id

Regeneration current

+
+

-

+
+
+

-

+

-

+
+
+

-

+
+
+

-

+
+
+

-

+
+
+

-

State of switch of inverter
Spu

Spv Spw Snu

Snv Snw

ON OFF ON OFF ON OFF
OFF OFF ON ON ON OFF
OFF ON ON ON OFF OFF
OFF ON OFF ON OFF ON
ON ON OFF OFF OFF ON
ON OFF OFF OFF ON ON
OFF OFF ON ON ON OFF
OFF ON ON ON OFF OFF
OFF ON OFF ON OFF ON
ON ON OFF OFF OFF ON
ON OFF OFF OFF ON ON
ON OFF ON OFF ON OFF

vectors including zero voltage vectors in two-level inverter.
The two-level inverter has the switching patterns to charge anddischarge the DC-link capacitor. Therefore, in Sequence I, theswitching pattern to maintain the DC-link capacitor voltage isselected according the current polarity while the instantaneous
power pout is arranged to become zero by charging anddischarging the DC-link capacitor. Accordingly, the q-axis
current achieves zero at the very short time because the active
current is changed into a reactive current. Table 1 illustrated
the switching table that is implemented in the inverter that isdepending on the capacitor voltage in subjects to the charge
and discharge modes. The voltage command vector becomes alag of 30-90 degrees with respect to the motor current vector
during the discharge mode. Similarly, the voltage command
vector becomes the lead of 90-150 degrees with respects to themotor current vector during the charge mode. As a result, thevoltage command vector becomes the lagging phase of 60-120
degree with respects to the motor current vector. Sequence I
operation ends when the q-axis current becomes zero.

Sup

Svp

Cdc

Sun

Short mode
(All upper/lower arms is shut down)

IPMSM

Svn

Sequence 2

Start

Swp

Relay is open

No

Yes

Swn

Zero-crossing current
is detected ?

Open of relay(a) State 1 (short mode)
Sup

Svp

Detecting thedirection of current

Swp

Cdc

IPMSM

Yes

iq = 0

Sun

Svn

Swn

Sup

Svp

Sun

Generation ofswitching pattern

Vc>Vupper_limit

Swn

Yes

No

IPMSM

Svn

No

Yes
All gate off mode
End

Swp

Cdc

Zero-crossing current
is detected ?

No(b) State 2 (single-phase mode)No

Yes
Single phase mode
(correspond switch arm is open)

Yes

Vc<Vlower_limitNocharge mode

discharge mode(c) State 3 (all gate-off mode)
Fig. 3. Operational modes in Phase II. Phase II avoids the regeneration
current flowing into DC-link capacitor to prevent its voltage fromincrease. In addition, Phase II interrupts the three-phase current.

Fig. 3 shows the short circuit operation mode that intends toprevent the DC-link capacitor voltage from rising by
circulating the regenerating current inside the inverter. In
Sequence II, the switching states create a short condition toprevent the DC-link voltage from increasing. The followingshows the switching states of the inverter, first, all of upper orlower side arms of the inverter are short-circuited as shown in
Fig. 3(a). This switching state can avoid the motor current
flows into the DC-link capacitor because it is a short-circuit
condition. Then, when the zero-crossing current is detected, thecorresponded switch arm is opened sequentially as shown in
Fig. 3(b). Thus, the inverter becomes a condition of a single
phase operation. Finally, the remaining two switching arms are
opened when the zero-crossing current are detected,
respectively as shown in Fig. 3(c). Therefore, the suppressionof the circulating current and the rising of the DC-link voltage
can be achieved.
Fig. 4 shows the operation flow chart in Sequence I. Oncethe relay is opened, the current polarity is recorded then the qaxis current signal is comparing in the system to decide theoperation between Sequence I and Sequence II. Then, the qaxis current is changed into reactive current by changing thevoltage vectors in the inverter.
Fig. 5 shows the experimental waveform of the output
current and the DC link capacitor voltage which are obtainedby gate interruption. In the experiment, a relay is opened andall switches are turned off by interrupting the gate signal at thesame time. The DC link capacitor voltage is increased byapproximately 140 V after the relay is opened and all switches
are turned off.
Fig. 6 shows the experimental result of the output current
and the DC-link capacitor voltage which are obtained by the

Vupper_limit : upper limit voltage
Vlower_limit : lower limit voltage Sequence 1

Output of signal

Fig. 4. Operation flow chart of Short-circuit halt sequence.
Gate interruption Dynamic braking

DC-link voltage
EDC
50V/div
200

140V

2ms/div

iw

iv

Output current
iu, iv, iw 0
40A/div

iu
Output current
id, iq 0
2p.u./div

2ms/div

id
iq

2ms/div
t1 t2

Fig. 11. Experimental results when all gate signals are interrupted as thehalt sequence. the DC-link capacitor voltage rises by approximately 140
V after the relay is opened and all switches are turned off.

flux-weakening short-circuit halt sequence. In Fig. 6, once therelay is opened at 4 ms. At approximately 6 ms, the q-axis
current reaches zero, then Sequence II begins to be operated.
From the result, the output current can be suppressed to lessthan 2.5 p.u of the rated current by applying the fluxweakening short-circuit halt sequence. In addition, thefluctuation of the DC-link capacitor voltage is suppressed toless than 0.07 p.u. (= 22V) of the rated voltage, which is
sufficiently small.

Phase 1
DC-link voltage
EDC 200
50V/div

Phase 2

Sequence 1

Output current
iu, iv, iw [p.u.]

22V
8V

iw
iu

iv

2ms/div

State 1iu
Output current
iu, iv, iw 0
40A/div
Output current
id, iq0
2p.u./div

Output current
id, iq [p.u.]

State 2id
iq

2.5 p.u.
2ms/div

iv iw
id
iq

Detecting the q-axis current
2ms/div
t1 t2
t3
Fig. 6. Experimental result when the system is applied with the fluxweakening short-circuit halt sequence. iq reaches zero, then Phase II
begins to be operated. The output current can be suppressed to less than
2.5 p.u of the rated current.

Flag for detecting
the q-axis current
0

Sequence 2

DC-link
voltage
EDC [V]

Fig. 7. Simulation result in PMSM which has low inductance. If the highback electromotive force, the cross term of the d-axis current and the dand q- axis inductance, the q-axis current flows drastically in the negative
direction during short-circuit mode.
q

Table 3. Simulation conditions.
Rated motor power
Rated current
Rated speed
Number of poles
Winding resistanced-axis inductanceq-axis inductanceBack-electromotive force
Rated DC voltage
Threshold DC over-voltage

3 kW
16.9 Arms
7200 rpm
120.127 W
0.389 mH
5.56 mH
58 Vrms@7200rpm
200 V
330 V

B. Problem of flux-weakening short-circuit halt sequenceFig. 7 shows the simulation result when the flux-weakening
short-circuit halt sequence cuts low regeneration current (0.5p.u.) off. In Fig. 7, the q-axis current increase drastically during
short-circuit mode of Sequence II. The q-axis voltage equation,
when the sequence is changed to Sequence 2, is shown in (2).

Lq

diq
dt

  re Ld i d  e(2)Note that, the voltage drop caused by the resistance isneglected because it is very small. As shown in (2), the q-axis
current variation of negative direction is decided by backelectromotive force (back-EMF), the cross term of the d-axis
current and the d- and q- axis inductance. In Fig. 7, the q-axis
current flows in the negative direction during short-circuit
mode. When the regeneration current is low in high speed
region or PMSM with low inductance is driven, the q-axis
current flows drastically in the negative direction during theshort-circuit mode of Sequence II in Fig. 7. Accordingly, theshort-circuit current which is more than 2.4 times of theregeneration current flows because the d-axis current to cancel
the back-EMF is insufficient. In order to prevent the rise of the
q-axis current, it is necessary to shorten the period of the short-

(110)

(010)

pinv>0(011)(100)
pinv<0d
Charging voltage
vector(101)

Discharging
voltage vector(001)(a)Lagging voltage mode (iq<0)q(010)
Discharging
voltage vector(110)
Charging
voltage vectorpinv>0(011)
pinv<0

(001)

(100)
d

(101)

(b)Leading voltage mode (iq>0)
Fig. 8. Vector diagrams of lagging and leading voltage vector. When the qaxis current is negative, the inverter applies the lagging voltage vector to
PMSM. On the other hand, when the q-axis current is positive, the inverter
applies the leading voltage vector to PMSM during the short-circuit current
suppression sequence

circuit mode i.e. the period between the start of the short circuitand the first current zero-crossing point.
III. IMPROVED SHORT-CIRCUIT HALT SEQUENCE
In the improved the flux-weakening short-circuit halt
sequence, the the short-circuit suppression sequence maintains
the q-axis current of zero after the q-axis current reaches zeroin Sequence I. After that, the sequence is changed to Sequence
II at first current zero-crossing point.
Fig. 8 shows the vector diagrams of lagging and leading
voltage mode in the short-circuit current suppression sequence.

When the two-level inverter applies the lagging voltage vector
to PMSM, the q-axis current is rotated in the anticlockwise
direction. When the inverter applies the leading voltage vector
to PMSM, the q-axis current is rotated in the clockwise
direction. The short-circuit current suppression sequencemaintains the q-axis current around zero by applying thelagging and leading voltage vector to PMSM depending on the
q-axis current.
Fig. 9 shows the flowchart of the improved short-circuit
halt sequence with the short-circuit suppression sequence. The
green line in Fig. 8 is the short-circuit current suppression
sequence.
Fig. 10 shows the simulation result when the improved
FSHS applied with the short-circuit current suppression
sequence acts to stop the inverter. After the q-axis current
reaches zero in Sequence I, the short-circuit current
suppression sequence maintain the q-axis current around zero
until just before V-phase current crosses zero because theinverter applies the lagging and leading voltage vector to
PMSM depending on the q-axis current direction. From Fig. 10,
the q-axis current is maintained around zero by applying thelagging and leading voltage vector depending on the q-axis
current direction. After that, the inverter short-circuits PMSM.
IV. EXPERIMENTAL RESLUTS
Fig. 11 shows the experimental result when FSHS (without
the short-circuit current suppression sequence) stops theinverter. In Fig. 6, d-axis current flows in negative direction.
When the regeneration current is low in high speed region or
PMSM with low inductance is driven, the q-axis current flows
drastically in negative direction during short-circuit mode ofSequence II in Fig. 11. As a result, the short-circuit current
which is more than 5 times of the regeneration current flows
because the d-axis current to cancel the back-EMF isinsufficient.
Fig. 12 shows the experimental result when the improved
FSHS (with the short-circuit current suppression sequence)stops the inverter. After the q-axis current reaches zero in
Sequence I, the short-circuit current suppression sequencemaintains the q-axis current around zero until just before Wphase current crosses zero because the inverter applies thelagging and leading voltage vector to PMSM depending on the
q-axis current direction. After that, the inverter short-circuits
PMSM. The fluctuation of the DC-link capacitor voltage
during the charge and discharge by the lagging and leading
voltage vector is suppressed within 50V. In Fig. 12, the shortcircuit current which is more than four times the regeneration
current flows. On the other hand, the short-circuit current issuppressed to 85% of the shirt-circuit current in Fig. 11
because the q-axis current is maintain around zero until justbefore the W-phase current reaches zero. As a result, it isconfirm that the improved FSHS with the suppression sequencestops the regeneration operation and suppress the rise of theDC-link capacitor voltage and the short-circuit current without
the dynamic brake system when the regeneration current is low.

Start

Sequence 2
Short mode
(All upper/lower arms is shut down)

Relay is openNo

Yes
Zero-crossing current
detection

Open of relay

Detecting thedirection of current
Yes

iq=0
No

No

Yes
Single phase mode
(correspond switch arm is open)

Zero-crossing current
detection

Zero-crossing current
detectionNo

Yes
All gate off mode

Yes

No

End
Yes (Leading voltage)iq>0

No (Lagging volage)

Vc>Vupper_limit

Yes

No

Vc<Vlower_limit

Yes

No
Chargemode(Lead)

Discharge
mode(Lead)Yes

Vc>Vupper_limit
No

Vc<Vlower_limit

Yes

No
Chargemode(Lag)

Discharge
mode
(Lag)

Vupper_limit : upper limit voltage
Vlower_limit : lower limit voltage

Output of signal

Sequence 1

Fig. 9. Flowchart of the improved halt sequence with the short-circuit
suppression sequence.
Short-circuit current suppression sequence
Sequence 1
Sequence 2

Output current
iu, iv, iw [p.u.]

Output current
id, iq [p.u.]

iw
iu

iv
id
iq

DC-link
voltage
EDC [V]

Fig. 10. Simulation result when the short-circuit halt sequence with the
suppression sequence is applied in PMSM which has low inductance.

V. CONCLUSION
This paper proposed the improved FSHS to suppress therise current of the short-circuit in low-load region. The
improved FSHS stops the regeneration operation andsuppresses the rise of the DC-link capacitor voltage without
the dynamic brake circuit as well as FSHS. Moreover, theimproved FSHS suppresses the rise current of the short-circuitin low-load region by maintaining the q-axis current aroundzero with the leading and lagging voltage vector until before
the mode is changed to Sequence II at zero-crossing point of
the motor current. In the experiment, it is confirmed that the
improved FSHS with the suppression sequence suppresses to
85% of the short-circuit current when the regeneration current
is low. In addition, the voltage rise in the DC-link capacitor ismaintained within 50V.
In future work, the improved FSHS will be constructed on
the hardware in terms of the reliability.

Table 4. Experimental conditions.
Rated motor power
5.5 kW
Rated motor voltage
200 Vrms
Rated current
20 Arms
Rated speed
1500 rpm
Number of poles
6 polesWinding resistance
0.215 Wd-axis inductance
4.3 mHq-axis inductance10.2 mH
Back-electromotive force
164 Vrms@1500rpm
Rated DC voltage
200 V
Threshold DC over-voltage
330 V
Sequence 1
DC-link
voltage
200
EDC[50 V/div]

Sequence 2

15V

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Output current
iu, iv, iw
0[10 A/div]

iv
iw
iu

Output current
id, iq0[0.5 p.u./div]

id

36A(Rise : 410%)

iq
2 [ms/div]

t1 t2

t3

Fig. 11. Experimental result with the short-circuit halt sequence without
the flux-weakening short-circuit current suppression sequence.
Short-circuit current suppression sequence
Sequence 1
Sequence 2
DC-link
voltage
200
EDC[50 V/div]

Output current
iu, iv, iw[10 A/div]0

Output current
id, iq0[0.5 p.u./div]

50V

30A

iv
iw
iu

(Rise : 325%)

id
iq
2 [ms/div]

t1

t2

t3

t4

Fig. 12. Experimental result with the improved short-circuit halt sequencewith the short-circuit current suppression sequence.