The performance of the multilevel converter topologies for PV inverter
Yugo Kashihara, Jun-ichi Itoh
Nagaoka University of Technology
1603-1 Kamitomioka-cho
Nagaoka City Niigata,Japan
Tel/Fax.: +81 / (258) – 47.9533.
E-Mail: itoh@vos.nagaokaut.ac.jp

SummaryThis paper discusses the performance of a 5-level ANPC inverter for PV system which is evaluated by using the optimize design method. In addition, the performance of a 5-level ANPC inverter is then compared with the conventional 2level inverter, 3-level NPC inverter and 3-level T-type NPC inverter. From the comparison results, within the range ofswitching frequency from 1 kHz to 1 MHz, the 5-level ANPC inverter can achieve the highest efficiency, and the 3level T-type NPC inverter can achieve the highest power density converter.

1

Introduction

In general, the multilevel converters are applied to themedium voltage application such as the power converter
for large power motor drive and also for power transmission line. Because, the multilevel converter can reduce thevoltage stress of a switching device to 1/(n-1) of the DC
input voltage and also reduce the harmonic component of
the output voltage.Recently, low voltage applications also
has been studied to apply the multilevel converters forhigh efficiency such as in the uninterrupted power supply(UPS) and power converter for photo voltaic cell (PV) [3].
There are two conventional multilevel topologies; theneutral point clamped (NPC) type and the flying capacitor(FC) type [1]. NPC topology outputs the voltage levelfrom the neutral point voltage that is clamped by using thediodes. However the number of switching devices increases in proportional to the voltage level. FC topology
outputs the voltage level from the DC link voltage by adding the flying capacitor voltage. However, FC topology
requires more capacitors as the voltage level increased.
The active neutral point clamped (ANPC) type which isone of the multilevel topology has been proposed [2]. The
ANPC type is a new topology that combines the NPC andFC type into one converter. Compared to the conventional
NPC and FC type converters, the ANPC type can reduce
the number of devices. Therefore, ANPC type has lower
cost and higher efficiency than the conventional NPC andFC type.
Selection criteria of switching devices for multi-level
converter are necessary to obtain higher efficiency than
the two-level inverter in low voltage applications. Lossanalysis by using simulator is a simple method to study
the losses among the multilevel converter topologies under a same device specification. However the loss estimation by simulation is not useful to optimize the optimization of design because hundreds of simulations are required under different conditions.
This paper discusses the performance of a 5-level ANPC
inverter for PV system (Fig.1) which is calculated by us-

ing the optimize design method for a 5-level ANPC inverter [3],[4],[5]. In addition, the performance of a 5-level
ANPC inverter is compared with the conventional 2-level
inverter and 3-level NPC inverter and 3-level T-type NPC
inverter in a PV application. The performance comparison
among the four converters shows that the 5-level ANPC
inverter can achieve the highest efficiency and 3-level
NPC inverter can achieve the highest power density at aswitching frequency range from 50 kHz to 100 kHz.

2

Converter topologies and design
flowchart

2.1

Circuit topologies

Figure 2 shows the type of inverter topologies areevaluated in this paper. The performances of the 5-level
ANPC inverter is compared with the conventional 2-level
inverter, 3-level NPC inverter and 3-level T-type NPC
inverter [1], [2].

2.2

Circuit topologies

Figure 3 shows the inverter design procedure to obtain
Pareto-front curve. Input variables of the design
procedure are the converter specification and device
parameters, which are decided from the specification
directly. The parameters of the four elements which are
semiconductor, capacitor, inductor and heatsink arecalculated by using input parameters. The efficiency andpower density are obtained as the output parameters.
The parameter design such as loss analysis is calculated
by using mathematical expressions. In fact, loss analysis
by using circuit simulator is a simple method for themultilevel converter topologies under a same device
specification. However, the loss estimation fromsimulator is not a useful tool to consider the design
optimization because hundreds of simulations are required
to conduct under different of conditions to find out theoptimize point.
The capacitor design calculates the capacitance, the ripple current, the loss and the volume. The capacitance isdecided by the voltage ripple based on the specifications.
The ripple current of the capacitor is identified by the
analysis with the mathematical equations. In the capacitor
design, the power density and the volume of the capacitor
are important factors to achieve high power density forthe converter. The volume of the capacitor is calculatedby the converter specification and the volume coefficientwhich is obtained from by the survey of commercial production capacitors.
The inductor design calculates the inductance, the loss
and the volume. The inductance is decided by the ripple
current based on the specifications. In the inductor design, the core selection is an important factor. The core isselected by the product of the window area multiplied by
the area of cross section according to the area productconcept [5]. The core volume is proportional to the threeof the quarter (3/4) power of the area product value.
The heatsink design calculates the thermal resistanceand volume. The total loss of the semiconductor comesfrom the semiconductor design. The volume of theheatsink is calculated by using CSPI, which is defined as
the inverse of the product of thermal resistance and multiplied by the volume. The CSPI is very convenience toselect the heatsink because the same CSPI value indicatesthe same volume even the shape of the heatsink is different. Generally, the CSPI of an air cooling heatsink withfans are approximately between 3 to 10.

3Applications to Multilevel inverters

3.1

Power loss of semiconductor

imately 0 A, Im is the peak phase current, ron is the onresistance (Ω), a is the modulation index, φ is the power
factor. The on-voltage occurs in the switching device
from on-resistance and p-n junction, which is expressed in(1). On the other hand, if the switching device of theFig.1. A PV system.

(a)Five-level ANPC inverter. (b)Two-level inverter.

(c)Three-level NPC inverter. (d) Three-level T-type
NPC inverter.
Fig.2. Single leg multilevel converter topologies.

3.1.1 Five-level ANPC inverter topology (Figure3(a))
The power loss of the ANPC inverter is calculated under two ideal conditions, that is no current ripple and no
voltage ripple in capacitors.
The conduction loss is separated into two, namely theswitch side loss and FWD side loss. Assuming that thepositive current flows into the switch side and the negative current flows into the FWD side. In addition, if theswitching device of the ANPC converter is MOSFET,
both the positive current and negative currents flow into
the switch side due to low on-resistance.
The conventional loss P5A_con_Cell1_sw in the switch side
can be given by11
v
P5 A _ con _ Cell1 _ sw = I m  0 − v 0 cos φ +I m ron sin 2φ8π
 2π 2............... (1)
1
2
1

−
I m ronφ −I m aron cos φ − av0 cos φ 
4π
3π
4


where v0 is the on voltage (V) when I equals to approx-

Fig.3. Inverter design procedure.

ANPC converter is MOSFET, v0=0 in (1). It should be
noted that the detail of those equations for the ANPC aredescribed in [4]On the other hand, the conventional loss P5A_con_Cell1_FWD
in the switch side are given by
1
1
1
v
P5 A _ con _ Cell1_ FWD = I m  0 + v0 cos φ +I m ron sin 2φ +I m ron8π
4π
 2π 2.... (2)1
2
1

+I m ronφ −I m aron cos φ − av0 cos φ 
4π
3π
4


The conduction loss in Cell2 is obtained by the same formula that is used to calculate the conduction loss in Cell1.
However, the current flows into the Cell2 switches aredifferent from the Cell1 because of the following two
conditions: S5 and S7 are turn-on when the output voltage
command is positive and S6 and S8 are turn-on when the
output voltage command is negative.
Therefore, the conduction loss P5A_con_Cell2_swA for theswitch side of the S5 and S7 is given by1  12
1 2
aron  cos 2φ + cosφ +  I m
2π   632

P5 A _ con _ Cell 2 _ swA =

1
1
1

+ av0  π cosφ − sin φ + φ cosφ 
2
2
2


4

1  
φ 
 I m a 8I m ron sin  − 3v0 sin φ + 3φv0 cosφ 
12π  
2
 



.............................................................................. (4)Likewise, the conduction loss for the switch side of theS6 and S8 is given by (5) and the conduction loss for the
FWD side of the S6 and S8 is given by (6).
P5 A _ con _ Cell 2 _ swB =


1 
φ 1
2 π
 I m v0 (cosφ + 1)+ I m r  + − sin 2φ 
2π 
2 2 4

1
1
π− I m av0  cosφ − sin φ + φ cosφ 
2
2
2


−

....... (5)1  2 φ 1

 I m r  − sin 2φ  − I m v0 + I m v0 cosφ
2π 
2 4


1
2
1 
1
2
I m av0 (sin φ − φ cosφ ) + I m ar  cos 2φ − cosφ + 
2
3
2 
6

.. (6)

where Edc is the input voltage (V), eon is the turn-on
energy (J) per switching at datasheet, eoff is the turn-off
energy (J) per switching at datasheet, Edcd is the voltage(V) at the measurement condition of switching loss atdatasheet, Imd is the current (A) at the measurement
condition of switching loss at datasheet and fc is thecarrier frequency (Hz), n is output voltage level. The
recovery loss P5A_rec_Cell1 in Cell1 is given by1

E I

On the other hand, the conventional loss P2I_con_FWD in
the switch side is given by
1
1
 1

 1

P2 I _ con _ FWD = 
v0 + I m rs  I m − ars I m − av0  I m cos φ ... (10).
8
8
 2π

 3π


The switching loss P2I_sw is given by equation (7). The
recovery loss P2I_rec is given by (8) according to the sameprocedure to that of the ANPC.

This chapter explains the power loss expression of the 3level NPC inverter (Figure 3(c)). The current flows into
the switches are different because of the following three
conditions. Therefore, the conduction loss P3N_con_S1_sw for
the switch S1 and S4 side is given by (11) and the conduction loss P3N_con_S1_FWD for the FWD S1 and S4 side are
given by (12)P3 N _ con _ S1 _ sw =aI m   1
2
1
rI m cos(2φ ) + cos(φ ) + 
2π   6
3
2

φ
1
π

+ v0  cosφ − sin φ + cosφ  
2
2
2


dc m
e f
(n − 1)π Edcd I md rr c ..................................... (8),where err is the recovery energy (J) per switching fromthe datasheet.
The switching loss in the Cell2 is depending on the out-.................(11)aI m 
v0
1
2φ 
2 
rI m 4 sin   − sin φ  − [sin φ − φ cos φ ]
2π 
3

2
 2

........................................................................... (12)The conduction loss P3N_con_S2_sw for the switch side S2and S3 is given by (13) and the conduction loss
P3N_con_S2_FWD for the FWD S2 and S3 side is given by (14)+Im  π φ 1
+ − sin 2φ  + v0 [cosφ + 1]
rI m
2π   2 2 4  1φ  1
1
4
 φ  I m rI m  sin 2φ −  + a sin 2 φ − sin 2    .. (13)2π   42 33
 2  

φ
1
 
+ v0 (1 − cosφ ) + a sin φ − cosφ  
2
2
 


P3 N _ con _ S 2 _ FWD =aI m  1 
2 φ 
2 
rI m 4 sin   − sin φ 
2π  3 2v
− 0 [sin φ − φ cosφ ]
2


)

1
Edc I mP5 A _ sw _ Cell 1 =e +e f(n − 1)π Edcd I md on off c ............................ (7),P5 A _ rec _ Cell1 =

1
1
 1

 1

P2 I _ con _ sw = 
v0 + I m rs  I m + 
ars I m + av0  I m cos φ ....... (9).
8
8
 2π

 3π


P3 N _ con _ S 2 _ sw =Knowing that the switching loss of the switches in Cell1
is proportional to the applied voltage and current.
Therefore, the switching loss of the Cell1 depends on thecurrent flows through the switches and the number ofswitching. The Cell1 switching loss P5A_sw_Cell1 is given by(

The conventional loss P2I_con_sw in the switch side can begiven by

P3 N _ con _ S 1 _ FWD =

2
1 
1
+ I m ar  cos 2φ + cosφ + 
3
2 
6

P5 A _ con _ Cell 2 _ FWDB =3.1.2 Two-level inverter topology (Figure 3(b))

3.1.3 Two-level inverter topology (Figure 3(c))................ (3).

The conduction loss P5A_con_Cell2_FWDA for the FWD sideof S5 and S7 are given by
P5 A _ con _ Cell 2 _ FWDA =put frequency (50Hz). As a result, the switching loss in
the Cell2 is lower than the switching loss in the Cell1,
which is nearly equal to zero and therefore the switchingloss can be disregarded.

.................... (14)The conduction loss for the diode D1 and D2 is given by(15)
P3 N _ con _ D = π φ 1
1
2
1 
 1
I m rI m  + − sin 2φ  − a cos 2φ + cos φ +  
2π
3
2 
 6

 2 2 4
1φπ
  
+ v 0 (cos φ + 1) − a cos φ − sin φ + cos φ   22
2
  

+


 1
1
4
φ  1
 φ  I m rI m  sin 2φ −  + a  sin 2 φ − sin 2   
2π
2 3
3
 2  

 4


φ
1
  
+ v 0 (1 − cos φ ) + a sin φ − cos φ   22  
........................................................................... (15)The switching loss P3N_sw is given by(e + e )(n − 1)π Edcd I md on off 2 ............................. (16),The recovery loss P3N_rec is given by
P3 N _ sw =P3 N _ rec =1

E dc I m

1

Edc I mfc

fc

evice, Ta is the ambient temperature, and Pl is evolution
loss.

3.3

Design of capacitor(n − 1)π Edcd I md rr 2 ....................................... (17).

3.3.1 Design of the capacitance
3.1.4 Three-level T-type NPC inverter topology(Figure 3(d))
The switching operation of the 3-level T-type NPC inverter is the same as 3-level NPC inverter. The switching
operation of the S1 and S2 are same as the S1 and S4 in the
3-level NPC inverter. Thus, the conduction loss of the S1and S2 is given by (11) and (12), respectively. On the other hand, the switching operation of the S3 and S4 are sameas the D1 and D2 in the 3-level NPC inverter. Thus, theconduction loss of the S3 and S4 is given by (15). However, the rated voltage of the 3-level T-type NPC inverter is
not same as the 3-level NPC inverter.
The switching losses of the S1 and S2 are given by (18)and the recovery losses of the S1 and S2 are given by (19).
P3TN _ sw1 =E dc I m

2(n − 1)π Edcd I mdcon

E dc I m

2

P3TN _ rec1 =(e + e ) f2 ............................. (18)
off

fc

e
(n − 1)π Edcd I md rr 2 ..................................... (19)On the other hand, the switching losses of the S3 and S4
are given by (20) and the recovery losses of the S3 and S4
are given by (21).

()

E dc I m
2
P3TN _ sw3 =e +e f(n − 1)π Edcd I md on off c .............................. (20)
E dc I m
2
P3TN _ rec 3 =e f(n − 1)π Edcd I md rr c ...................................... (21)The capacitance of the flying capacitor C1 in the 5-level
ANPC inverter is calculated by the capacitor current, theripple voltage and the time integration of the charge
period or discharge period. The capacitance of C1 is givenby
C FC =I mT E dc............................................... (24),8∆VFC Vm

where ∆VC1 is the ripple voltage of the flying capacitor,
VDC is the DC link voltage, Vm is the maximum value of
output voltage, and T is the reciprocal of carrier frequency.
The capacitance CDCSC of DC smoothing capacitor C2
and C3 in the 5-level ANPC inverter is given by
C DCSC =Vmπ
I m  3 −  ............................. (25)2ω∆Vcn E DC 
3

where ∆Vcn is the maximum voltage ripple of C2. In addition, the capacity of the 3-level NPC inverter and the 3level T-type NPC inverter can be also calculated by thesame mathematical expression. On the other hand, the capacitance CDC of DC smoothing capacitor C1 in the 2-level
90

Specification : 3.3-kW rating
Switching frequency :20kHz
Input voltage : 350V
Output voltage :124V
Selected Capacitor : Electrolytic Capacitor
Flying Capacitor :5-parallel connection

80
70
60
50
40

3.1.5 Experimental verification
Figure 4 shows the comparison between the theoretical
calculated losses and experimental losses from the ANPC
inverter and the NPC inverter. Table 1 shows the experimental condition. The error ratio between the theoreticaland experimental values for the 5-level ANPC inverter is
6% at rated load. On the other hand, the error ratio between the theoretical and experimental values for the 3level NPC inverter is 6% at rated load. The loss estimation results well agreed with that of the experimental results.

3.2

30
20
10
0
0

500

1000

1500
2000
Power[W]

2500

3000

(a)Five-level ANPC inverter

Design of heatsink

The performance of the heatsink is discussed based on
the Cooling System Performance Index (CSPI) [5]. The
CSPI is an expressed value of the thermal resistance at
per unit volume. The larger the volume of the CSPI, thelarger is the cooling capacity per unit volume will become. The CSPI is given by
CSPI =

1..................................................... (22),RthV0

where Rth is the thermal resistance of the heatsink, andVo is the volume of the heatsink. In addition, Rth is givenbyRth ( f −a ) =T j − TaPl

− Rth( f − s ) .................................... (23),where Tj is the junction temperature of the switching de-(b)Three-level NPC inverter
Fig.4. Losses of multilevel converters.
Table 1 the experimental condition.

3500

inverter is given byVm
C DCSC =I m π ....................................... (26).
2ω ∆ v cn E dc

where KV is the constant value which is determined by
figure of the core, Ku is the window utilization factor, W
is the maximum energy of the reactor, Jw is the current
density, and Bm is the flux density.

3.3.2 Calculation method of the capacitor
The conduction loss PCap occurs in the capacitor is calculated from the equivalent series resistance (ESR). The
conduction loss PCap is given by2
PFC = I rms _ Cap RESC ................................................ (27),where Irms_Cap is the rms value of the capacitor current (A)and RESC is the ESR value of the capacitor (Ω).
The rms value of the capacitor value is given byequation (26) using the capacitor current coefficient KCap.
The capacitor current coefficient KCap is calculated fromthe normalized simulation.
I= K I ................................................... (28)rms _ CapCap m

3.3.3 Calculation method of the capacitor volume
The capacitors volume is calculated based on the film
capacitors and electrolytic capacitors that are available inthe market [5].
3.3.3.1 Film capacitor
The volume of the film capacitor is proportional to thestored energy in the capacitor. The volume VCF of the film
capacitor is given by
V CF = γ V−CF1

1
C F U O2 .............................................. (29),2where γ -1VCF is the proportionality factor between theenergy and the volume, CF is the capacity of the film
capacitor and UO is the applied volume of the film
capacitor.
3.3.3.2 Electrolytic capacitor
The volume of the electrolytic capacitor is proportional
to the rms value of the ripple current of the electrolytic
capacitor. The volume VCE of the electrolytic capacitor isgiven by
V CE = γ V−1 I C , RMS .................................................. (30),where γ--1VCE is the proportionality factor between the rms
value of the ripple current and the volume, and IC,RMS is
the rms value of the ripple current of the electrolytic capacitor.
CE

3.4

Design of inductor

This utility interaction inductor is to suppress the output
current ripple. The utility interaction inductor L is givenbyL=

E dc − 3Vm V1 3 m − T ............................ (31),(n − 1)∆I  Edc 2 

where ∆I is the ripple current.
The volume of the inductor is calculated by the area
product. The volume of the inductor is given by3

 2W  4
 ............................................ (32),
VL = KV  K u Bm J w 

4Comparison of the multilevel inverters using Pareto front curves

This chapter discusses the performances of the multilevel converters, the 5-level ANPC inverter, 2-level inverter, 3-level NPC inverter and 3-level T-type NPC inverter using Pareto front curves. In addition, the performance of the 5-level ANPC inverter is discussed with two
different capacitors, the flying capacitor and electrolytic
capacitor.
Figure 5 shows the loss analysis results of the five inverter topologies. Table 2 shows the converter specifications and device parameters. In figure 5, the major losses
are dominated by the copper loss of the inductor and conduction loss. It should be noted that the iron loss of theinductor is not considered. Conduction loss of the 2-level
inverter is the largest in these converter topologies. The
voltage rating of device for 2-level inverter is 600 V. On
the other hand, the voltage rating of device for the 5-level
ANPC inverter and the 3-level NPC inverter is 200 V and
300 V. The 3-level T-type NPC inverter uses 300 V rated
voltage and 600 V rated voltage devices. The 2-level inverter and Cell 1 of the 3-level T-type NPC inverter use
600 V rated voltage devices. However, the conduction
loss of the 3-level T-type NPC inverter is lesser than the2-level inverter. This is because, the current in Cell1
switch is only flow at half cycle of the output frequency.
Figure 6 shows the volume analysis of the five topologies. These results are calculated by table 2. In figure 6,
the major volumes are dominated by the inductor andheatsink. The volume of the 5-level ANPC inverter using
the electrolytic capacitor shows the largest amount comparing to other inverter topologies. However, flying capacitor can be replaced by the film capacitor to reduce thevolume of the 5-level ANPC inverter.
Figure 7 shows the Pareto front curves of the five inverter topologies at range of switching frequency from 1 kHz
to 1 MHz. Note that, the switching frequency of the 5level ANPC inverter using the film capacitor is from 20
kHz to 1 MHz. When the switching frequency is 30 kHz,the 5-level ANPC inverter using the electrolytic capacitor
achieves the maximum power density 6.3 kW/dm3 withthe efficiency 98.2%. On the other hand, when the switching frequency is 50 kHz, the 5-level ANPC inverter using
the film capacitor achieves the maximum power density
8.4 kW/dm3 with the efficiency 98.1%. When the switching frequency is 40 kHz, the 2-level inverter achieves the
maximum power density 6.3 kW/dm3 with the efficiency
96 %. When the switching frequency is 30 kHz, the 3level NPC inverter achieves the maximum power density
6.5 kW/dm3 with the efficiency 98.1%. When the switching frequency is 100 kHz, the 3-level T-type NPC inverter
achieves the maximum power density 9.7kW/dm3 and theefficiency 97.7 %.
Based on the results, the 5-level ANPC inverter canConclusion

This paper discussed the optimize design method for themultilevel converter based on the implementation of thesystem integration for the power electronics. Pareto front
curve is one of the effective tools to indicate the trade-off
problem among many factors. The results clarify that the5-level ANPC inverter can achieve the highest efficiency
and the 3-level T-type NPC inverter can achieve the highest power density.
In the future, the requirements for each component will
be discussed in order to obtain higher efficiency andpower density for each circuit topologies.

6

References

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2005 Page(s):2296 – 2301
[3] Yugo kashihara, Jun-ichi Itoh, “Parameter design of aFive-level Inverter for PV systems”, ICPE 2011[4] J. W. Kolar, J Biela and J. Miniböck：「Exploring thePareto Front of Multi –Objective Single-Phase PFC Rectifier Design Optimization -99.2% Efficiency vs. 7kW/dm3
Power Density」，IPEMC 2009-China，(2009)[5] Wm. T. Mclyman: “Transformer and inductor design
handbook”, Marcel Dekker Inc. (2004)[6] Kazuaki Mino, etc: “Technology Trends of High PowerDensity, Modeling, and Optimization for PowerElectronics”, IEEJ JIASC2011, No. 1-S13-2(2011)[7] Drofenik, U., Laimer, G., Kolar, J. W., “Theoretical
Converter Power Density Limits for Forced Convection
Cooling”., Proceedings of the International PCIM Europe
2005 Conference, Nuremberg, Germany, June 7 - 9, pp.
608 - 619 (2005).

Fig.5. Loss analysis of the inverter topologies.
5-level ANPC inverters and 3-level NPC inverter use
200 V rated voltage and 300 V rated voltage devices. 2level inverter use 600 V rated voltage devices. 3-level Ttype NPC inverter is uses 300V rated voltage and 600 V
voltage rating devices.

Volume[dm3]5

Fig.6. Volume analysis of the inverter topologies.

Efficiency[%]achieve the highest efficiency. On other hand, the 3-level
T-type NPC inverter can achieve the highest power density. Therefore, those converters should be used dependingon the aim of the applications.

20kHz 5level ANPC INV(Film)
100 5level ANPC INV(Electroytic) 40kHz
30kHz
50kHz
98 3level NPC INV
40kHz
96
1kHz
100kHz94
1MHz 3levelT-type NPC INV
92
2level INV
90
1kHz
88
Specification : 10-kW rating
86
Flying Capacitor
1MHz
Electrolytic capacitor : 5-parallel connection
84
Film capacitor: 6-parallel connection
82
DC smoothing Capacitor : 5-parallel connection
1MHz
80
0
2
4
6
8
10
12
Power density[kW/dm3]

Fig.7. Pareto front of the inverter topologies.
Table 2 the Converter specification of the PV system anddevices.