Thermal Stress Reduction for DC-link Capacitorsof Three-phase VSI with Multiple PWM
Switching Patterns
Koroku Nishizawa
Nagaoka University of Technology
Nagaoka, Niigata, Japan
koroku_nishizawa@stn.nagaokaut.ac.jp

Jun-ichi Itoh
Nagaoka University of Technology
Nagaoka, Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Satoru Fujita
Fuji Electric Co., Ltd.
Tokyo, Japanfujita-satoru@fujielectric.com

Akihiro Odaka
Fuji Electric Co., Ltd.
Tokyo, Japanodaka-akihiro@fujielectric.com

Akio Toba
Fuji Electric Co., Ltd.
Tokyo, Japan
toba-akio@fujielectric.com

Hidetoshi Umida
Fuji Electric Co., Ltd.
Tokyo, Japanumida-hidetoshi@fujielectric.com

Abstract—This paper demonstrates the thermal stress
reduction for the DC-link capacitors with multiple PWM
strategies. An optimized positioning of the gate pulse reduces theDC-link capacitor current. The capacitor current reduction
space vector PWM (SVPWM) strategies reduces the film
capacitor core temperature by a maximum of 9.0℃ comparedto those obtained with the conventional strategies, whereas the
maximum allowable temperature of the film capacitor is 105℃.
The carrier-based PWM approaches also reduce the thermal
stress; however, the reduction amount is not as large as the
SVPWM approach. In addition to the trade-off between theimplementation requirement and the reduction effect on thecapacitor current, the analytical and experimental results
confirm that there is a trade-off between the improved capacitor
current harmonics and the worsened load current harmonics.
Keywords— Two-level voltage source inverter, DC-link
capacitor, Thermal stress, PWM

I. INTRODUCTION
Three-phase AC motors are widely used in both industrial
and household applications [1]–[5]. The employment of film
capacitors in the DC-link part of the three-phase VSI havebeen actively researched to absorb the current ripple due to theinverter fast switching. The maximum allowable temperatureof polypropylene, which is a dielectric material of the film
capacitor, is 105℃ [6]; thus, the suppression of its
temperature rise is important. It is possible to suppress thetemperature rise of the capacitors by reducing the harmoniccomponents of DC-link current iDC.in, defined in Fig. 1.
So far, several modulation strategies of PWM inverter
have been proposed for the reduction of the current stress on
the DC-link capacitors [7]–[12]. In several approaches basedon space vector PWM (SVPWM), the capacitor current isminimized by selecting the optimized combination of thevoltage space vectors [7]–[10]. On the other hand, withapproaches based on triangular carrier-based PWM, threephase modulating signals which are shifted in every half
control period also achieve the switching patterns for thecapacitor current reduction [11]–[12]. Nevertheless, only the
reduction effect of these PWM strategies on the capacitor
current have been demonstrated in the past works, whereas thethermal stress for the DC-link capacitors with these strategies
have not been evaluated yet.
This paper provides experimental evaluations and thecomparison of the thermal stress for the DC-link capacitorswith regard to the several PWM strategies by using theiDC.in_ave iDC.in
iC

Edc

Sup

Motor
load

u

Cdc

v
w
Sun

Fig. 1.

Swp

Svp

Svn

Swn

Three-phase two-level VSI employed in motor drive system.

thermostatic bath, leading to fair comparisons. In addition,
multilateral evaluations demonstrate that there is trade-off
between the capacitor current and the output current
harmonics, which can be the choice index of the capacitor
current reduction PWM strategies.
This paper is organized as follows: first, the reduction
methods of the DC-link capacitor current with the multiple
PWM strategies are presented. Second, the effects on the DClink capacitor current, the output phase current, and theinverter efficiency are compared by analysis and experiment.
Finally, the capacitor temperature rise test is presented toconfirm the effectiveness of these capacitor current reduction
PWM strategies.
II. PWM STRATEGIES FOR DC-LINK CAPACITOR CURRENT
REDUCTION
A. SVPWM Approaches [7]–[10]Fig. 2 shows the conventional and the capacitor current
reduction SVPWM strategies at the modulation index (m) of
0.7, phase angle (θ) of 25 degrees, and the load power factor(cos φ) of 0.866. Instantaneous value of the inverter input
current is the superposition summation of the switched current
pulses from each phase leg [13] and calculated as

iDC .in    sx  ix . x u ,v ,w

The capacitor current is calculated as difference between iDC.in
and its average value iDC.in_ave as following equation, andcorresponds to the shaded areas in iDC.in waveform [14].

b

b

b
V2 (1 1 0)

V2 (1 1 0)

t2
V2
Ts
V*
t7
V7
Ts
a
V7 (1 1 1) t1 V
V1 (1 0 0)
1
Ts

t2
V2
Ts
t7
V7
Ts

b
V2 (1 1 0)

V2 (1 1 0)
t2
V2
Ts

V

*

a

V7 (1 1 1)

V1 (1 0 0)

t6
V6
Ts

t2
V2
V*
Ts
t7
V7
a
Ts
t1
V7 (1 1 1) t1 V V1 (1 0 0)
t6V1
V6 Ts 1
TsTs

V6 (1 0 1)(a) Conv. SVPWM.

su

sv

sv

sw

iu

iDC.in_ave

iDC.in

iu+iv
V1

V2

V7
Ts

V2

V1

V1

su

sv

sv

sw

sw

V7
Ts

V2

iDC.iniDC.in_ave
V6
Ts

V7

V1

iDC.in_ave

iu

iu+iw
V7

V2

(c) Zoomed-in waveform of iDC.in
with conv. SVPWM.

su

iu+iv
V2

iDC.in_ave

iu+iv(c) Zoomed-in waveform of iDC.in
with conv. SVPWM.

V222
iC .RMS Ts   iDC.in. RMS Ts   iDC .in _ ave
1 Ts 2iDC .in dt iDC .in.RMS Ts  

Ts 0
and 
3

iDC .in _ ave  4 m  I m cos 

iu+iw
V2

(d) Zoomed-in waveform of iDC.in
with iC reduction SVPWM.
Fig. 2.
Conventional and capacitor current reduction SVPWM strategies
at m = 0.7, θ = 25 deg., cos φ = 0.866. In low modulation index region, thetwo non-adjacent active vectors and one zero vector are used to reduce thecapacitor current.

(b) iC reduction SVPWM.

swiu

iDC.inaV1 (1 0 0)

V6 (1 0 1)(a) Conv. SVPWM.

(b) iC reduction SVPWM.

su

iDC.inV*where Ts is the control period, Im is the maximum value of theload current, and φ is the load power factor lagging angle.
Under these conditions, the combination of one active vector(V6), one non-adjacent active vector (V2), and one zero vector(V7) suppresses the capacitor current to the minimum [9]–[10].
This is because this vector combination results in the omissionof V1 which cause the largest error between the instantaneous
value (= iu) and average value of DC-link current.
Fig. 3 shows another example of the conventional and thecapacitor current reduction SVPWM strategies at m = 1.0, i.e.
higher modulation index. If the tip of the voltage reference
vector V* does not belong to the triangle formed by the tips of

V1

iu+iv
V6
Ts

V1

V2

(d) Zoomed-in waveform of iDC.in
with iC reduction SVPWM.
Fig. 3.
Conventional and capacitor current reduction SVPWM strategies
at m = 1.0, θ = 25 deg., cos φ = 0.866. In high modulation index region, thethree consecutive active vectors are used to reduce the capacitor current.

three voltage space vectors (V6, V2, and V7) shown in Fig. 2(b),the voltage reference vector cannot be generated bysynthesizing these voltage space vectors. Under these
conditions, the combination of three consecutive active
vectors (V6, V1, and V2) suppresses the capacitor current to theminimum [7]–[10]. In addition, the available areas with thethree consecutive voltage space vectors are the same as thosewith conventional SVPWM. Therefore, the capacitor current
reduction SVPWM strategy allows the same output voltage
limitations as conventional SVPWM to be obtained. However,those gate pulse layout for the capacitor current reduction
shown in Fig. 2(d) and Fig. 3(d) is not realized by using only
one triangular-carrier. Therefore, the capacitor current
reduction SVPWM leads to the requirement of high costhardware such as field-programmable gate array (FPGA).
B. Carrier-based Continuous PWM Approach [11]Fig. 4 shows the modulating signals of continuous PWM(CPWM) and output phase current at m = 0.7 and cos φ =0.866. The carrier-based PWM approaches generate the gate
pulses by comparing the calculated modulating signals and thehigh-frequency carrier only with the general-purpose micro-

Modulating signals[p.u.]

1
1.0

0.5
0.5

1
*
v.CPWM*
u.CPWM

v

v

v*
w.CPWM*
vu.CPWM

v

0
0.0

*
vw.CPWM

-0.5
–0.5

-1

-1
–1.0

su

0.0180.020.022
0.016
0.014
0.0080.010.012
0.006
0.004
-0.002 0 0.002
1.2
1.2
0.8
0.8
iw
iv
iu
0.4
0.4
0.0
0
–0.4
-0.4
–0.8
-0.8
-1.2
–1.2
90 120 150 180 210 240 270 300 330
30 60
–30 0
0.0180.020.022
0.016
0.014
0.012
0.008
0.006
0.004
-0.002 0 0.002[deg.]
2πft0.01

Output phasecurrents [p.u.]

sv
sw
V0
iu
iDC.inV1

V2

computer, whereas the SVPWM approach requires FPGA.
Generally, the modulating signals are set as the three-phasesinusoidal continuous waveforms as

*
xp

x

*
x .CPWM 1  1 **vxn   2  Ax   vx.CPWM  Ax  1

 if v*x .CPWM

 if v*x .CPWM

V0iu+iv(a) Conventional CPWM.
vup*

1

*
u.CPWM*
v.CPWM*
w.CPWM

v
v
v

*
un

v

vvp*

*
wp

v
*
vn

*
vwn

v

-1

sv
sw
V0
iu

The concept of the capacitor current reduction carrierbased PWM is realized under the premise that the modulating
signals can be updated twice during one carrier cycle, whichis the constraint of the micro-computer. By shifting themodulating signals in every half control period while
maintaining its average value during a control period, only thegate pulse timings is adjusted while maintaining these widths.
The positively-shifted modulating signal v*xp and thenegatively-shifted modulating signal v*xn are calculated asv  A   v

V1

Ts



where m is the modulation index and f is the fundamental
frequency.

v*xp   2  Ax   v*x.CPWM  Ax  1
 **vxn  Ax  vx.CPWM  1  1

V2su vu*.CPWM  m  cos  2 ft  *
 vv.CPWM  m  cos  2 ft  2 3 v *
 w.CPWM  m  cos  2 ft  2 3

V7

iDC.in_ave

Fig. 4.
Continuous modulating signals v*x.CPWM and output phasecurrents ix at m = 0.7 and cos φ = 0.866.

Triangular carrier*
v.CPWMm0 

0

where Ax is the shifting coefficient between the original andshifted modulating signal. The value of Ax is defined from 1.0
to 2.0. Ax of 1.0 means that the modulating signal shift is not
performed. Ax of 2.0 indicates that the modulating signal isshifted maximally in linear-modulation region.
Fig. 5 shows the zoomed-in waveforms of the modulating
signals, the three-phase switching functions, and the inverter
input current with the conventional and capacitor current
reduction continuous PWM (CPWM) strategies. For thecapacitor current reduction, firstly, u-phase modulating signal
should become larger than the other two phase modulating
signals, and the gate pulse su should cover sv and sw in the time
domain to avoid the iDC.in polarity flip compared to the iDC.in_ave
polarity. Secondly, the overlap of the other two gate pulses sv
and sw should be shortened to further reduce iDC.in fluctuation
around iDC.in_ave. With those modified gate pulse timings, theapplying durations of V1 and V7, which cause the large

iDC.in

V1

V6

V2
iu+iw

V0

iDC.in_ave

iu+iv
Ts

(b) Capacitor current reduction CPWM.
Fig. 5.
Zoomed-in waveforms of CPWM modulating signals, switching
functions, and inverter input current at m = 0.7, θ = 25 deg., cos φ = 0.866.
The divergence degree coefficients between the original voltage references
and shifted references are set as Au = 1.68, Av = 2.00, and Aw = 2.00.

difference between iDC.in (= iu with V1, or 0 with V7) andiDC.in_ave, are shortened and eliminated compared to theconventional CPWM. Furthermore, the applying durations ofV2 and V6, which result in the small iDC.in harmonics, areextended and generated with those gate pulses. In order toachieve both the criterion for avoiding the iDC.in polarity flipcompared to the iDC.in_ave polarity and the criterion for reducing
the iDC.in fluctuation,1)

v*u, whose output phase current is positive, is shiftedto the positive side simultaneously with the larger
phase voltage reference between the other two phases,
i.e. v*v.

2)

v*v and v*w are shifted alternately and maximally tothe positive side as long as they do not exceed v*up
and v*un.

C. Carrier-based Discontinuous PWM Approach [12]Fig. 6 shows the modulating signals of discontinuous
PWM (DPWM) and its injected zero sequence signal at m =0.7. The discontinuous modulating signals lead to theadvantages of the switching loss reduction due to the reduced
switching transitions compared to those with CPWM. In
addition, DPWM strategy extends the linear modulation range
compared to CPWM. The discontinuous modulating signals
are obtained by injecting the zero sequence signal v*offset into
v*x.CPWM [15] as 1 v
max*voffset


1

v
min


 if v
 if vmax  vmin  vmax 

min

, 



vmax  max v
,v
,v



.

*
*
*
 vmin  min vu .CPWM , vv.CPWM , vw.CPWM *
u .CPWM*
v.CPWM*
w.CPWM

Modulating signals [p.u.]

1.2
1.2

*
v*x.DPWM  v*x.CPWM  voffset
 x  u , v, w  ,v*v.DPWM

v*u.DPWM
v*u.CPWM

0.8
0.8

*
vw.DPWM

v*v.CPWM*
vw.CPWM

0.4
0.4
0.0
0

–0.4
-0.4

v*offset

–0.8
-0.8

Fig. 7 shows the zoomed-in waveforms of the modulating
signals, the three-phase switching functions, and the inverter
input current with the conventional and capacitor current
reduction DPWM strategies. In a similar way to the CPWM
approach, shifted discontinuous modulating signals,
calculated as following, are used to reduce the capacitor
current in the DPWM approach.

–1.2
-1.2

–30

0

30

60

90

120 150 180 210 240 270 300 330

0.0016667
0 0.0033333
0.005
0.0066667
0.0083333
0.0116667
0.0133333
0.015
0.0166667
0.0183333
0.02
2πft0.01[deg.]

Fig. 6.
Modulating signals of DPWM v*x.DPWM and its injected zero
sequence v*offset signal at m = 0.7.
1*
vu.DPWM

Triangular carrier*
vv.DPWM*
vw.DPWM

*vxp  1 **vxn  2  vx.DPWM  1
v*xp  2  v*x.DPWM  1 *vxn  1

-1

 if v*x . DPWM

0




su





if v*x.DPWM  0 .

These carrier-based CPWM and DPWM approaches
require only general-purpose micro-computer and FPGA is
not necessary. However, the reduction effects on the capacitor
current are inferior to the SVPWM approaches because thedegree of freedom for the gate pulse timing is limited in the
carrier-based PWM approaches. Therefore, the optimized gate
pulse layout for the capacitor current reduction cannot be
achieved in the carrier-based PWM approaches.
III. ANALYTICAL RESULTS
A. DC-link Capacitor RMS Current
As explained in above section, the DC-link capacitor RMS
current is dependent on m, φ, and the switching patterns. The
DC side of the three-phase VSI operates at six foldfundamental frequency; hence, the normalized DC-link
capacitor RMS current is calculated based on (2) byconsidering only a sixth of the fundamental period asI C .RMS (p.u.) 

1
Im

3



 3

0

  tk2
iDC .in.k  iDC .in _ ave   d    Ts





sw
V1

For the capacitor current reduction, overlap period between
two unclamped phases’ switching functions, sv and sw in Fig.
7, should be shortened. Therefore, there two phase modulating
signals v*v.DPWM and v*w.DPWM are shifted alternately to thepositive side. As a result, the applying durations of V1 and V7,
which cause the large difference between iDC.in and iDC.in_ave,
are shortened and eliminated Instead of the omission of theseworse switching periods for the capacitor current, the applying
durations of V2 and V6, which result in the small iDC.in
harmonics, are extended and generated just like CPWM
approach shown in Fig. 5.



sv



iDC.in

V2
iu

V7

V2

V1

iDC.in_ave

iu+iv
Ts
(a) Conventional DPWM.

1*vu.DPWM*
vv.DPWM*
vw.DPWM
-1

vvp*

v *u
*
v wp

*
vwn

vvn*

su
sv
sw
V2
iDC.iniDC.in_ave

V7
iu+iw

V6

iu

V1

iu+iv
Ts

(b) Capacitor current reduction DPWM.
Fig. 7.
Zoomed-in waveforms of DPWM modulating signals, switching
functions, and inverter input current at m = 0.7, θ = 25 deg., cos φ = 0.866.

where tk is the on-duty of VSI voltage space vector Vk (k =0~7) within Ts, and iDC.in.k is the instantaneous DC-link current
value with the voltage space vector Vk.
Fig. 8 shows the comparisons of the DC-link capacitor
RMS current under the high load power factor conditions.
Both figures confirm that there are no IC.RMS(p.u.) differences
between the conventional SVPWM, CPWM, and DPWM due
to those same applying durations of the active vectors and thezero vectors. Fig. 8(a) confirms that the capacitor current
reduction SVPWM leads to the best reduction effect in themodulation index region from 0.6 to 0.8 under the unity load
power factor condition, which is a typical operating conditionof the grid-tied VSI. Within the carrier-based PWM
approaches, the capacitor current reduction DPWM leads tothe better reduction effect compared to the CPWM approach.

0.50

7

Conv. SVPWM, CPWM, DPWM

V2

IC.RMS(p.u.) [p.u.]

0.40

V2h

0.30
iC reduction CPWM
[11]

0.20
0.10
0.00

-V0h = V*iC reduction
SVPWM [10]iC reduction DPWM
[12]
0.0

0.50
0.50

0.2
0.2

0.4

0.6

0.8

Conv. SVPWM, CPWM, DPWM

2

V1h

0.2

0.4

0.6
0.6

2

V1h

V0

V1

7

V6h

V6
(a) Conv. SVPWM.

0.20
0.20

0.0

o

λh

1.2

(b) iC reduc. SVPWM [10].

-V0h = V*iC reduction
SVPWM [10]

1
2 7 0
7
0o
1

1.0

λh 0

V2h

2

0o

1

-V0h = V*

V1h

V1h

2

6

V0, V7
0.8

V2

λh

V2h

iC reduction DPWM
[12]

V2h

2

-V0h = V*

V2

0.10
0.10

1

o

2
6

7

V1

0.30
0.30

0.00
0.00

1

V0, V7iC reduction
CPWM [11]

0.40
0.40

IC.RMS(p.u.) [p.u.]

1.0
1.0

Modulation index m [-](a) cos  = 1.0 ( = 0 deg.).

V2

λh

V1

V0

V1
V6h

1.2

Modulation index m [-](b) cos  = 0.891 ( = 27 deg.).
Fig. 8.
IC.RMS(p.u.) comparisons between conventional and capacitor
current reduction PWM strategies against different modulation index at highload power factor conditions.

V6(c) Conv. CPWM.

(d) iC reduc. CPWM [11].
7This is because the fact that certain one phase discontinuous
modulating signal is always clamped, making it possible to set
the switching pattern which leads to the smaller iDC.in ripple
longer than CPWM approach. Fig. 8(b) demonstrates theafter-mentioned experimental condition of cos φ = 0.891 withan induction motor load. This trend in the reduction effectbetween the three capacitor current reduction PWM
approaches is clearly shown also in this condition.
B. Load Current Quality
In order to evaluate the load current quality, the concept ofharmonic flux presented in [16] is used. Assuming that the
motor switching frequency model is an inductance L, aharmonic flux load current vector Ih has a proportional
relationship between the harmonic flux vector λh (timeintegral of the instantaneous error voltage vector) as

λ h  LI h   N 1TsNTs

 V - V  dt. 
*

k



Fig. 9 shows the harmonic flux vector trajectories at m =0.7, θ = 25 degrees. The distance between the trajectories andthe origin (o), which is the initial value of λh at the beginningof the carrier cycle, corresponds to the magnitude of theharmonic flux [16]. The calculation of (8) and Fig. 9 evaluate
the ripple current on a per-carrier cycle base. Since theharmonic flux vector characteristic has six-fold spacesymmetry, the per-fundamental cycle (per 60 degrees inspace) harmonic flux RMS value, which characterizes the load
current quality and the harmonic losses in the test motor, iscalculated as follows.

6

V2

λh
V2h

-V0h = V
V0, V7

*

1
2

2

V2
7
o

1

V2h

2

-V0h = V

V1h
V1

λh

*

1

o

V1h

V0

V1
V6h

V6
(e) Conv. DPWM.
(f) iC reduc. DPWM [12].
Fig. 9.
Harmonic flux vector λh trajectories at m = 0.7 and θ = 25 degrees.
The distance between the trajectories and the origin (o), which is the initialvalue of λh at the beginning of the carrier cycle, corresponds to the magnitudeof the harmonic flux.

RMS 

3

 3

 0



 N 1TsNTs

2

λ h dtd . Fig. 10 shows the comparison of the harmonic flux RMS
values Figs. 9–10 confirm that the capacitor current reduction
PWM strategies worsen the harmonic flux compared to thoseobtained with each conventional PWM strategies. The reason
is because the capacitor current reduction PWM strategies
result in the application of the voltage space vector which is
not the closes to V*, i.e. V6 in Fig. 9. Within the capacitor
current reduction PWM strategies, the SVPWM approachleads to the worst harmonic flux RMS value, and the carrierbased CPWM approach leads to the minimal deterioration.

This trend in the worsened harmonic flux RMS value with thecapacitor current reduction PWM strategies is in a trade-off
relationship with the trend in the improved DC-link capacitor
RMS current which is shown in Fig. 8.

Fig. 11 shows the experimental setup. The DC-link
capacitor and the inverter, operated at the switchingfrequency of 10 kHz, are placed inside thermostatic bath,whereas the temperature test starts from 25℃.
Fig. 12 shows the film capacitor under test as the DC-link
capacitor. The thermocouple is built in the central part of thefilm capacitor. An equivalent series resistance (ESR) is
measured using HIOKI 3532-50 LCR tester. At very low
frequencies, ESR is high due to prevalent leakage. At low
frequencies, ESR is dominated by the dielectric losses which
decrease in inverse proportion to the frequency. At medium
to high frequencies, the losses in the conductors are dominantand ESR becomes relatively constant. At high frequencies,
ESR increases again due to the skin effect [17].
Fig. 13 shows the inverter operating test results with each
modulation method. All capacitor current reduction PWM
strategies reduce the switching frequency harmonics of thecapacitor current compared to conventional strategies.
Furthermore, the capacitor loss, which is calculated as follows,is also reduced.

n1

. 

iC reduction
SVPWM [10]

0.20
0.20

0.10
0.10

Conv. SVPWM
Conv. CPWM

0.00
0.00
0.0

0.2

0.4
0.4

0.6

0.8
0.8

1.0

Fig. 10.

Comparison of harmonic flux RMS values λRMS.
Thermostatic bath: EPFH-125-2S (ISUZU)

iDC.in_ave iDC.in
DCL =
10 mH

Sup

Swp

Svp

iu

iCap
Vdc =
282.8 V

Cdc =
20 µF
Sun

vuv
Svn

Swn

The maximum PCap reduction of 54.2% is obtained by the
SVPWM approach as observed in Figs. 13(a)–(b). The
reduction effects on PCap with the capacitor current reduction
PWM strategies are correspond with the analytical results of
IC.RMS(p.u.) shown in Fig. 8(b).
Fig. 14 shows the measured capacitor core temperature.
The temperature tests are conducted until the bath internal
temperature reached 60℃, the rated temperature of the coatedvinyl of wire, under the same experimental conditions as inFig. 13. The largest reduction of PCap with the SVPWM
approach, which can be observed from Figs. 13(a)–(b),enables the greatest suppression of the capacitor coretemperature rise. The application of the capacitor current
reduction SVPWM reduces the equilibrium capacitor coretemperature, which is estimated by the least-square method,by 11℃ at most compared to the conventional strategy.
Table 1 lists the inverter efficiency with each PWM
strategies under same experimental conditions as in Fig. 13.
The CPWM strategies lead to the worst efficiency due to therequirement of more number of switching transitions. In
addition, the SVPWM and DPWM strategies result in almost
same efficiency because the number of switching transitions
is same.
Fig. 15 shows the harmonic spectrum of iu under the same
experimental conditions as in Fig. 13. All capacitor current
reduction PWM strategies worsen the phase current THD
compared to the conventional PWM strategies because of theinstantaneous error between the voltage reference vector andthe output voltage vector. This trend is similar to the analyticalresults of λRMS shown in Fig. 10. In particular, the capacitor

IM

MVK8115A-R(Fuji Electric)
Pn = 3.7 kW
Nn = 1500 rpm

Inverter: 7MBP50RA120 (Fuji Electric)

Fig. 11.

Experimental setup.
100
100



1.2

Modulation index m [-]

62 mm

42 mm

C = 20 µF
w = 200 g

Built-inthermocouple

Capacitor ESR RESR [mΩ]PCap   RESR.n  i

iC reduction DPWM
[12]iC reduction CPWM
[11]Conv. DPWM

45 mm



0.30
0.30

RMS [-]

IV. EXPERIMENTAL RESULTS

2
Cap.n

0.40
0.40

Capacitor coretemperature = 25℃

10
10

11

0.1
0.1

10

1002
10

(a) Photograph of film capacitor.
Fig. 12. Film capacitor under test.

3
1000
10000
10
10 4
Frequency [Hz]10000010 5(b) Measured ESR.

current reduction SVPWM leads the largest time integral of
the instantaneous voltage error and the worst current THD.
V. CONCLUSION
This paper demonstrated the thermal stress reduction for
the DC-link capacitors with multiple PWM strategies. The
SVPWM approaches realized the optimal gate pulses for thecapacitor current reduction with FPGA, and reduced thecapacitor core temperature by 9.0℃ at most compared to theconventional strategies. On the other hand, the optimal gate
pulses generation led to the large instantaneous inverter
voltage error; thus, the capacitor current and the output current
harmonics have the trade-off relationship. The carrier-based
PWM approaches, which do not require FPGA, realized theintermediate performances on the capacitor current and theoutput current harmonics between the conventional PWM
strategies and the capacitor current reduction SVPWM.

Capacitor current [Arms]0
iCap [20 A/div.]
0

11

10
10

vuv [500 V/div.]

8.26 Arms
PCap.conv= 0.780 W

Capacitor current [Arms]

1010

vuv [500 V/div.]0iCap [20 A/div.]

0.1
0.1

0

0.01
0.01

iu [50 A/div.]0iu [50 A/div.]

0.001
0.001
10

[5 ms/div.](i) Operating waveforms.

0

3
1000
10000
10000010
10 4
10 5
Frequency [Hz](ii) Harmonic spectrum of iC.

(i) Operating waveforms.

1002
10

3
1000
10000
10000010
10 4
10 5
Frequency [Hz](ii) Harmonic spectrum of iC.

(b) Capacitor current reduction SVPWM [10].
*vu.PCPWM[2.0 -/div.]

Capacitor current [Arms]

1010
vuv [500 V/div.]0iCap [20 A/div.]
0

11

0

8.65 Arms

1010
vuv [500 V/div.]

0

0.1
0.1

iCap [20 A/div.]

0.01
0.01

0.001
0.001

iu [50 A/div.]

PCap.conv= 0.777 W

Capacitor current [Arms]

0

10

0

1002
10

0

3
1000
10000
10
10 4
Frequency [Hz]11

3.69 Arms
PCap.prop= 0.531 W

0.1
0.1
0.01
0.01

0.001
0.001

iu [50 A/div.]

100000
10 5

10

1002
10

0

[5 ms/div.]

3
1000
10000
10
10 4
Frequency [Hz]10000010 5[5 ms/div.](i) Operating waveforms.

(ii) Harmonic spectrum of iC.

(i) Operating waveforms.

(c) Conventional CPWM.

(ii) Harmonic spectrum of iC.

(d) Capacitor current reduction CPWM [11].
*vu.PDPWM[2.0 -/div.]*
vu.DPWM[2.0 -/div.]

Capacitor current [Arms]

1010
vuv [500 V/div.]0iCap [20 A/div.]

11

0

6.22 Arms
PCap.conv= 0.807 W

vuv [500 V/div.]
0

0.1
0.1

iCap [20 A/div.]

0.01
0.01

0

0.001
0.001

iu [50 A/div.]

10
10

Capacitor current [Arms]

0

10

0

1002
10

0

3
1000
10000
10
10 4
Frequency [Hz]11

3.02 Arms
PCap.prop= 0.395 W

0.1
0.1
0.01
0.01

0.001
0.001

iu [50 A/div.]

100000
10 5

10

1002
10

0

[5 ms/div.]

3
1000
10000
10
10 4
Frequency [Hz]10000010 5[5 ms/div.](i) Operating waveforms.

(i) Operating waveforms.

(ii) Harmonic spectrum of iC.

(e) Conventional DPWM.

(ii) Harmonic spectrum of iC.

(f) Capacitor current reduction DPWM [12].

Conventional SVPWM
11℃
9.0℃

iC reduction SVPWM [10]

0

5000

10000 15000
Time [sec.]

20000(a) SVPWM approach.

25000

100
90
80
70
60
50
40
30
20
10
0

Conventional CPWM
6.0℃
4.4℃
iC reduction CPWM [11]

0

5000

10000 15000
Time [sec.]

20000(b) CPWM approach.

25000

Capacitor core temperature [℃]Experimental results at m = 0.643, cos φ = 0.891, and Pinv = 2.7 kW.

Capacitor core temperature [℃]Capacitor core temperature [℃]

0.01
0.01

10

[5 ms/div.]*
vu.CPWM[2.0 -/div.]

100
90
80
70
60
50
40
30
20
10
0

0.1
0.1

0.001
0.001

1002
10

(a) Conventional SVPWM.

Fig. 13.

11

3.42 Arms
PCap.prop= 0.357 W

100
90
80
70
60
50
40
30
20
10
0

Conventional DPWM

9.3℃

8.0℃

iC reduction DPWM [12]

0

5000

10000 15000
Time [sec.]

20000

25000

(c) DPWM approach.

Fig. 14. Measured capacitor core temperature and its approximated curves. The experimental conditions are at m = 0.643, cos φ = 0.891, and Pinv = 2.7 kW,
under same conditions in Fig. 13.

u-phase current [%]100

REFERENCES

Conventional SVPWM
THD = 3.67%

10

[1]

iC reduction SVPWM [10]THD = 5.07%

1
0.1

0.01 st
1

5th

10th

15th
20th
25th
Harmonic order [-]

30th

35th

40th

(a) SVPWM approach.

u-phase current [%]100

Conventional CPWM
THD = 2.87%

10iC reduction CPWM [11]THD = 4.03%

1
0.1

0.01

1st

5th

10th

15th
20th
25th
Harmonic order [-]

30th

35th

40th

(b) CPWM approach.

u-phase current [%]100

Conventional DPWM
THD = 2.89%

10iC reduction DPWM [12]THD = 4.61%

1
0.1

0.01

1st

5th

10th

15th
20th
25th
Harmonic order [-]

30th

35th

40th

(c) DPWM approach.

Fig. 15. iu harmonic spectrum and its THD at m = 0.643, cos φ = 0.891,
under same conditions in Fig. 13.

TABLE I.

MEASURED INVERTER EFFICIENCIES

Conv.
Conv.
iC reduction
SVPWM SVPWM [10] CPWM
Efficiency
[%]

96.11

96.39

95.27

Conv. iC reduction
iC reduction
CPWM [11] DPWM DPWM [12]

95.17

96.30

96.22

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