16 Mbit (x8/x16) Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet

GLS36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlashFEATURES:• Organized as 1M x16 or 2M x8• Dual Bank Architecture for Concurrent
Read/Write Operation– 16 Mbit Bottom Sector Protection- GLS36VF1601G: 4 Mbit + 12 Mbit
– 16 Mbit Top Sector Protection- GLS36VF1602G: 12 Mbit + 4 Mbit
• Single 2.7-3.6V for Read and Write Operations• Superior Reliability– Endurance: 100,000 cycles (typical)– Greater than 100 years Data Retention• Low Power Consumption:– Active Current: 6 mA typical– Standby Current: 4 µA typical– Auto Low Power Mode: 4 µA typical• Hardware Sector Protection/WP# Input Pin– Protects the 4 outermost sectors (8 KWord)in the smaller bank by driving WP# low andunprotects by driving WP# high• Hardware Reset Pin (RST#)– Resets the internal state machine to readingarray data
• Byte# Pin– Selects 8-bit or 16-bit mode
• Sector-Erase Capability– Uniform 2 KWord sectors• Chip-Erase Capability• Block-Erase Capability– Uniform 32 KWord blocks• Erase-Suspend / Erase-Resume Capabilities• Security ID Feature– Greenliant: 128 bits
– User: 256 Byte
• Fast Read Access Time– 70 ns• Latched Address and Data
• Fast Erase and Program (typical):– Sector-Erase Time: 18 ms– Block-Erase Time: 18 ms– Chip-Erase Time: 35 ms– Program Time: 7 µs
• Automatic Write Timing– Internal VPP Generation• End-of-Write Detection– Toggle Bit– Data# Polling– Ready/Busy# pin• CMOS I/O Compatibility• Conforms to Common Flash Memory Interface (CFI)• JEDEC Standards– Flash EEPROM Pinouts and command sets
• Packages Available– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)– 56-ball LFBGA (8mm x 10mm)• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTIONThe GLS36VF1601G and GLS36VF1602G are 1M x16 or
2M x8 CMOS Concurrent Read/Write Flash Memory manufactured with high performance SuperFlash memory technology. The split-gate cell design and thick oxide tunnelinginjector attain better reliability and manufacturability compared with alternate approaches. The devices write (Program or Erase) with a 2.7-3.6V power supply and conform
to JEDEC standard pinouts for x8/x16 memories.
Featuring high performance Program, the GLS36VF160xG
provide a typical Program time of 7 µsec and use Toggle
Bit, Data# Polling, or RY/BY# to detect the completion of
the Program or Erase operation. To protect against inadvertent write, the devices have on-chip hardware and Soft-©2010 Greenliant Systems, Ltd.

ware Data Protection schemes. Designed, manufactured,and tested for a wide spectrum of applications, thesedevices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the
GLS36VF160xG significantly improve performance andreliability, while lowering power consumption. These
devices inherently use less energy during Erase and Program than alternative flash technologies, because the totalenergy consumed is a function of the applied voltage, current, and time of application. For any given voltage range,

www.greenliant.com

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet
the SuperFlash technology uses less current to programand has a shorter erase time; therefore, the total energy
consumed during any Erase or Program operation is lessthan alternative flash technologies.

TABLE 1: Concurrent Read/Write State

SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system softwareor hardware does not have to be modified or de-rated as isnecessary with alternative flash technologies, whose
Erase and Program times increase with accumulatedErase/Program cycles.

Bank 2Read

No Operation

Write

Note: For the purposes of this table, write means to perform Blockor Sector-Erase or Program operations as applicable to theappropriate bank.

The Read operation of the GLS36VF160xG is controlled
by CE# and OE#, both of which have to be low for thesystem to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The
data bus is in a high impedance state when either CE# or
OE# is high. Refer to Figure 9, the Read cycle timing diagram, for further details.

To meet high-density, surface-mount requirements, the
GLS36VF1601G and GLS36VF1602G devices are offeredin 48-ball TFBGA, 48-lead TSOP, and 56-ball LFBGA
packages. See Figures 6, 7, and 8 for pin assignments.

Device Operation

Program Operation

Memory operation functions are initiated using standard
microprocessor write sequences. A command is written byasserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edgeof WE# or CE#, whichever occurs first.

These devices are programmed on a word-by-word orbyte-by-byte basis depending on the state of the BYTE#
pin. Before programming, ensure that the sector which is
being programmed is fully erased.
The Program operation is accomplished in three steps:
1. Initiate Software Data Protection using the threebyte load sequence.

Auto Low Power Mode
These devices also have the Auto Lower Power mode
which puts them in a near-standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the typical IDD active Read current to 4 µA.
While CE# is low, the devices exit Auto Low Power modewith any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.

2. Load address and data.
During the Program operation, the addresses arelatched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on therising edge of either CE# or WE#, whicheveroccurs first.
3. Initiate the internal Program operation after the rising edge of the fourth WE# or CE#, whicheveroccurs first. The Program operation, once initiated, will be completed typically within 7 µs.

Concurrent Read/Write Operation
The dual bank architecture of these devices allows theConcurrent Read/Write operation whereby the user canread from one bank while programming or erasing in theother bank. For example, reading system code in one bankwhile updating data in the other bank. See Table 1 below
for more information.

See Figures 10 and 11 for WE# and CE# controlled Program operation timing diagrams and Figure 25 for flowcharts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks.
Any commands issued during an internal Program operation are ignored.

TABLE 1: Concurrent Read/Write StateBank 1

Bank 2Read

No Operation

Read

Write

Write

Read

Write

No Operation©2010 Greenliant Systems, Ltd.

Bank 1No Operation

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

Sector-Erase/Block-Erase Operation

Erase-Suspend/Erase-Resume Operations

The Sector- or Block- Erase operation allows the system toerase the device on a sector-by-sector (or block-by-block)basis. The GLS36VF160xG offer both Sector-Erase andBlock-Erase operations.

The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to beread or programmed into any sector or block that is notengaged in an Erase operation. The operation is executedby issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically entersread mode no more than 10 µs after the Erase-Suspendcommand had been issued. (TES maximum latency equals
10 µs.) Valid data can be read from any sector or block thatis not suspended from an Erase operation. Reading ataddress location within erase-suspended sectors/blocks
will output DQ2 toggling and DQ6 at ‘1’. While in EraseSuspend mode, a Program operation is allowed except forthe sector or block selected for Erase-Suspend.

The sector architecture is based on a uniform sector size of
2 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a Sector-Erasecommand (50H) and sector address (SA) in the last bus
cycle.
The Block-Erase mode is based on a uniform block size of
32 KWord. Block-Erase is initiated by executing a six-bytecommand sequence with Block-Erase command (30H) andblock address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (50H or 30H) is latched on therising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse.

To resume a suspended Sector-Erase or Block-Erase
operation, the system must issue an Erase-Resume command. The operation is executed by issuing a one-bytecommand sequence with Erase Resume command (30H)
at any address in the one-byte sequence.

Any commands issued during the Sector- or Block-Erase
operation are ignored except Erase-Suspend and EraseResume. See Figures 15 and 16 for timing waveforms.

Write Operation Status Detection
To optimize the system Write cycle time, the
GLS36VF160xG provide two software means to detect thecompletion of a Write (Program or Erase) cycle The software detection includes two status bits: Data# Polling(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

Chip-Erase Operation
The GLS36VF1601G and GLS36VF1602G provide a
Chip-Erase operation, which erases the entire memory
array to the ‘1’ state. This operation is useful when theentire device must be quickly erased.
The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid Read is Toggle Bit or Data# Polling. Any commands issued during the Chip-Erase operation are ignored. See Table 6 for the command sequence,
Figure 14 for timing diagram, and Figure 29 for the flowchart. When WP# is low, any attempt to Chip-Erase will beignored.

©2010 Greenliant Systems, Ltd.

The actual completion of the nonvolatile write is asynchronous with the system. Therefore, Data# Polling or
Toggle Bit maybe be read concurrent with the completionof the write cycle. If this occurs, the system may possibly
get an incorrect result from the status detection process.
For example, valid data may appear to conflict with either
DQ7 or DQ6. To prevent false results, upon detection of
failures, the software routine should loop to read theaccessed location an additional two times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the failure is valid.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

Ready/Busy# (RY/BY#)

Toggle Bits (DQ6 and DQ2)

The GLS36VF160xG include a Ready/Busy# (RY/BY#)
output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to VDD via an external
pull-up resistor. After the rising edge of the final WE# pulsein the command sequence, the RY/BY# status is valid.

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘1’sand ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal
Program or Erase operation is completed, the DQ6 bit willstop toggling, and the device is then ready for the next
operation. For Sector-, Block-, or Chip-Erase, the toggle bit(DQ6) is valid after the rising edge of sixth WE# (or CE#)pulse. DQ6 will be set to ‘1’ if a Read operation is attemptedon an Erase-Suspended Sector or Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.

When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.

An additional Toggle Bit is available on DQ2, which can beused in conjunction with DQ6 to check whether a particularsector or block is being actively erased or erase-suspended. Table 2 shows detailed bit status information. The
Toggle Bit (DQ2) is valid after the rising edge of the lastWE# (or CE#) pulse of Write operation. See Figure 13 for
Toggle Bit timing diagram and Figure 26 for a flowchart.

Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether thedevice data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (VIH) the device is in x16 data configuration: alldata I/0 pins DQ0-DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic ‘0’, the device is in x8 data configuration -- only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The remaining data pins DQ8DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.

TABLE 2: Write Operation Status

Data# Polling (DQ7)

EraseSuspend
Mode

When the GLS36VF160xG are in an internal Program
operation, any attempt to read DQ7 will produce the complement of true data. Once the Program operation is completed, DQ7 will produce valid data.
During internal Erase operation, any attempt to read DQ7will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid
after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, theData# Polling is valid after the rising edge of sixth WE# (orCE#) pulse. See Figure 12 for Data# Polling (DQ7) timing
diagram and Figure 26 for a flowchart.

©2010 Greenliant Systems, Ltd.

Status

DQ7

DQ6

DQ2

RY/BY#

NormalStandard
Operation Program

DQ7#

ToggleNo Toggle

0Standard
Erase0

ToggleToggle0

Read From
Erase
Suspended
Sector/Block1

1

Toggle1

Read From
Non-Erase
Suspended
Sector/Block

Data

Data

Data

1

Program

DQ7#

ToggleN/A

0
T2.1 1342

Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation status. If the address is pointing to a different bank (not busy),
the device will output array data.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

Data Protection

These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes.

The GLS36VF160xG provide both hardware and softwarefeatures to protect nonvolatile data from inadvertent writes.

All Program operations require the inclusion of the threebyte sequence. The three-byte load sequence is used toinitiate the Program operation, providing optimal protection
from inadvertent Write operations. SDP for Erase operations is similar to Program, but a six-byte load sequence isrequired for Erase operations.

Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

During SDP command sequence, invalid commands willabort the device to read mode within TRC. The contents of
DQ15-DQ8 can be VIL or VIH, but no other value, during any
SDP command sequence.

Hardware Block Protection

Common Flash Memory Interface (CFI)The GLS36VF1601G and GLS36VF1602G provide hardware block protection which protects the outermost 8
KWord in the smaller bank. The block is protected when
WP# is held low. See Figures 2, 3, 4, and 5 for Block-Protection location.

These devices contain Common Flash Memory Interface(CFI) information that describes the characteristics of thedevice. In order to enter the CFI Query mode, the system
must write a three-byte sequence, using the CFI Query
command, to address BKx555H in the last byte sequence.
The system can also use the one-byte sequence withaddress BKx55H and Data Bus 98H to enter this mode.
See Figure 18 for CFI Entry and Read timing diagram.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 7through 9.

Block protection is disabled by driving WP# high. This
allows data to be erased or programmed into the protected
sectors. WP# must be held high prior to issuing the Writecommand and remain stable until after the entire Write
operation has completed. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations onthat block.

The system must write the CFI Exit command to return toRead mode from the CFI Query mode.

Hardware Reset (RST#)

Security ID

The RST# pin provides a hardware method of resetting thedevices to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate
and return to Read mode (see). When no internal Program/
Erase operation is in progress, a minimum period of TRHR
is required after RST# is driven high before a valid Readcan take place. See Figures 22 and 21 for more information.

The GLS36VF160xG offer a 136-word Security ID space.
The Secure ID space is divided into two segments — one
128-bit, factory-programmed, segment and one 256-Byte,
user programmed segment. The first segment is programmed and locked at Greenliant and contains a 128 bit
Unique ID which uniquely identifies the device. The user
segment is left un-programmed for the customer to programas desired.

The interrupted Erase or Program operation must be re-initiated after the device resumes normal operation mode toensure data integrity.

The user segment of the Security ID can be programmedusing the Security ID Program command. End-of-Write status is checked by reading the toggle bits. Data# Polling is
not used for Security ID End-of-Write detection.

Software Data Protection (SDP)The GLS36VF160xG devices implement the JEDEC
approved Software Data Protection (SDP) scheme for alldata alteration operations, such as Program and Erase.

©2010 Greenliant Systems, Ltd.

Once the programming is complete, lock the Sec ID byissuing the User Sec ID Program Lock-Out command.
Locking the Sec ID disables any corruption of this space.
Note that regardless of whether or not the Sec ID is locked,
the Sec ID segments can not be erased.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet
The Secure ID space can be queried by executing a threebyte command sequence with Query Sec ID command(88H) at address 555H in the last byte sequence. See Figure 20 for timing diagram. To exit this mode, the Exit Sec ID
command should be executed. Refer to Table 6 for moredetails.

TABLE 3: Product Identification
Manufacturer’s ID

Address

Data

BK0000H

00BFH

BK0001H

7343H

BK0001H

7344H

Device ID

GLS36VF1601G
GLS36VF1602G

Product Identification

T3.0 1342

Note: BK = Bank Address (A19-A18)

The Product Identification mode identifies the devices as
GLS36VF1601G or GLS36VF1602G and the manufacturer as Greenliant. For details, see Table 3 for software
operation, Figure 17 for the Software ID Entry and Readtiming diagram, and Figure 27 for the Software ID Entry
command sequence flowchart.

Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. The exit isaccomplished by issuing the Software ID Exit commandsequence, which returns the device to the Read mode.
This command may also be used to reset the device to theRead mode after any inadvertent transient condition thatcauses the device to behave abnormally. Please note that
the Software ID Exit/CFI Exit command is ignored during aninternal Program or Erase operation. See Table 6 for thesoftware command code, Figure 19 for timing waveformand Figure 28 for a flowchart.

The addresses A19 and A18 indicate a bank address.
When the addressed bank is switched to Product Identification mode, it is possible to read another address from thesame bank without issuing a new Software ID Entry command.

Address
Buffers

MemoryAddress

SuperFlash Memory
12 Mbit BankBYTE#SuperFlash Memory
4 Mbit Bank
(8 KWord Sector Protection)

RST#
CE#
WP#

Control
Logic
I/O Buffers

WE#

DQ15/A-1 - DQ0

OE#
RY/BY#
1342 B01.0

FIGURE 1: Functional Block Diagram©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet
Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21Block 20
Block 19

Bank 2Block 18
Block 17
Block 16
Block 15
Block 14Block 13Block 12Block 11Block 10Block 9Block 8Block 7Block 6Block 5Block 4Block 3Block 2

Bank 1

8 KWord Sector Protection(4-2 KWord Sectors)

FFFFFH
F8000HF7FFFH
F0000HEFFFFH
E8000H
E7FFFH
E0000HDFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
07FFFH
02000H
01FFFH
00000H

Block 1

Block 01342 F01.0

Note: The address input range in x16 mode (BYTE#=VIH) is A19-

FIGURE 2: GLS36VF1601G, 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21Block 20
Block 19
Block 18

Bank 2Block 17
Block 16
Block 15
Block 14Block 13Block 12Block 11Block 10Block 9Block 8Block 7Block 6Block 5Block 4Block 3Block 2

Bank 1

16 KByte Sector Protection(4-4 KByte Sectors)

1FFFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
004000H
003FFFH
000000H

Block 1

Block 01342 F02.0

Note: The address input range in x8 mode (BYTE#=VIL)FIGURE 3: GLS36VF1601G, 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

Top Block Protection; 32 KWord Blocks; 2 KWord Sectors
8 KWord Block Protection(4 - 2 KWord Sectors)

Block 31

Block 30
Block 29
Block 28
Block 27

Bank 2Block 26
Block 25
Block 24
Block 23
Block 22
Block 21Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14Block 13Block 12Block 11

Bank 1FFFFFH
FE000H
FDFFFH
F8000HF7FFFH
F0000HEFFFFH
E8000H
E7FFFH
E0000HDFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
07FFFH
00000H

Block 10Block 9Block 8Block 7Block 6Block 5Block 4Block 3Block 2Block 1
Block 01342 F03.0

Note: The address input range in x16 mode (BYTE#=VIH) is

FIGURE 4: GLS36VF1602G, 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet
Top Block Protection; 64 KByte Blocks; 4 KByte Sectors
16 KByte Block Protection(4 - 4 KByte Sectors)

Block 31

Block 30
Block 29
Block 28
Block 27

Bank 2Block 26
Block 25
Block 24
Block 23
Block 22
Block 21Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14Block 13Block 12

Bank 1

1FFFFFH
1FC000H
1FBFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
000000H

Block 11Block 10Block 9Block 8Block 7Block 6Block 5Block 4Block 3Block 2Block 1
Block 0Note: The address input range in x8 mode (BYTE#=VIL) is

1342 F04.0

FIGURE 5: GLS36VF1602G, 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

TOP VIEW (balls facing down)

6
5

A13 A12 A14 A15 A16 BYTE# NOTE* VSS
A9A8

A10 A11 DQ7 DQ14 DQ13 DQ6WE# RST# NC

A19 DQ5 DQ12 VDD DQ4

RY/BY# WP# A18

NC DQ2 DQ10 DQ11 DQ3

31342 48-tfbga P1.0

4

2
1

A7

A17

A6

A5

DQ0 DQ8 DQ9 DQ1

A3

A4

A2

A1

A0

CE# OE# VSS

A

B

C

D

E

F

G

H

Note* = DQ15/A-1

FIGURE 6: Pin Assignments for 48-ball TFBGA (6mm x 8mm)

A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Standard Pinout
Top View
Die Up

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0

1342 48-tsop P02.0

FIGURE 7: Pin Assignments for 48-lead TSOP (12mm x 20mm)©2010 Greenliant Systems, Ltd.

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GLS36VF1601G / GLS36VF1602G

Data Sheet

TOP VIEW (balls facing down)

8
7
6
5
4

A15

NC

NC

A16 BYTE# VSS

A11

A12

A13

A14

NC DQ15/A-1 DQ7 DQ14

A8

A19

A9

A10

DQ6 DQ13 DQ12 DQ5

WE#

NC

NC

DQ4

NC

WP# RST# RY/BY#

DQ3

VDD DQ11

NC

NC

NC

A18

A17

DQ1

DQ9

DQ10 DQ2

A7

A6

A5

A4

VSS

OE#

DQ0

A3

A2

A1

A0

CE#

NC

B

C

D

E

F

G

2
DQ8

1
A

1342 56-lfbga P1.0

3

H

FIGURE 8: Pin Assignments for 56-lead LFBGA (8mm x 10mm)
TABLE 4: Pin Description
SymbolName

A19-A0Address Inputs

Functions
To provide memory addresses. During Sector-Erase and Hardware Sector Protection,
A19-A11 address lines will select the sector. During Block-Erase A19-A15 addresslines will select the block.

DQ14-DQ0 Data Input/Output

To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state whenOE# or CE# is high.

DQ15/A-1

DQ15 is used as data I/O pin when in x16 mode (BYTE# = “1”)A-1 is used as the LSB address pin when in x8 mode (BYTE# = “0”)Data Input/Output
and LBS Address

CE#

Chip Enable

To activate the device when CE# is low.

OE#

Output EnableTo gate the data output buffers

WE#

Write Enable

To control the Write operations

RST#

Hardware ResetTo reset and return the device to Read mode

RY/BY#

Ready/Busy#

To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.

WP#

Write Protect

To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or
Program operation.

BYTE#

Word/Byte Configuration To select 8-bit or 16-bit mode.

VDD

Power Supply

VSS

GroundNC

No Connection

To provide 2.7-3.6V power supply voltage
Unconnected pins
T4.0 1342©2010 Greenliant Systems, Ltd.

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GLS36VF1601G / GLS36VF1602G

Data SheetTABLE 5: Operation Modes Selection
DQ15-DQ8
Mode1

CE#

OE#

WE#

DQ7-DQ0

BYTE# = VIH

BYTE# = VIL

Address

Read

VIL

VIL

VIH

DOUT

DOUT

DQ14-DQ8 = High Z

AIN

Program

VIL

VIH

VIL

DIN

DIN

DQ15 = A-1

AIN

Erase

VIL

VIH

VIL

X2

X

High Z

Sector or Blockaddress,
555H for Chip-Erase

Standby

VIHC

X

X

High ZHigh ZHigh ZX

Write Inhibit

X

VIL

X

High Z / DOUT

High Z / DOUT

High Z

X

X

X

VIH

High Z / DOUT

High Z / DOUT

High Z

X

VIL

VIL

VIH

Manufacturer’s ID(BFH)

Manufacturer’s ID(00H)High ZSee Table 6

Device ID3

Device ID3High Z

Product
Identification
SoftwareMode

T5.2 1342

1. RST# = VIH for all described operation modes
2. X can be VIL or VIH, but no other value.
3. Device ID =GLS36VF1601G = 7343H,
GLS36VF1602G = 7344H©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data SheetTABLE 6: Software Command Sequence
Command
Sequence

1st Bus
Write Cycle

2nd Bus
Write Cycle

3rd Bus
Write Cycle

4th Bus
Write Cycle

5th Bus
Write Cycle

6th Bus
Write Cycle

Addr1

Addr1

Addr1

Data2

Addr1

Data2

Addr1

Data2

Addr1

Data2

Data
AAH

2AAH

55H

SAX4

50H
30H
10H

Data2

Data2

Program

555H

AAH

2AAH

55H

555H

A0H

WA3

Sector-Erase

555H

AAH

2AAH

55H

555H

80H

555H

Block-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

BAX4

Chip-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

555H

Erase-Suspend

XXXXH

B0H

Erase-Resume

XXXXH

30H

Query Sec ID5

555H

AAH

2AAH

55H

555H

88H

User Security ID
Program

555H

AAH

2AAH

55H

555H

A5H

SIWA6

Data

User Security ID
Program Lock-out7

555H

AAH

2AAH

55H

555H

85H

XXH

0000H

Software ID Entry8

555H

AAH

2AAH

55H

BKX9
555H

90H

CFI Query Entry

555H

AAH

2AAH

55H

BKX9
555H

98H

CFI Query Entry

BKX9
55H

98H

Software ID Exit/
CFI Exit/
Sec ID Exit10,11

555H

AAH

2AAH

55H

555H

F0H

Software ID Exit/
CFI Exit/
Sec ID Exit10,11

XXH

F0H

T6.0 1342

1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode.
When in x8 mode, Addresses A19-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word/byte address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX for Block-Erase; uses A19-A15 address lines
5. For GLS36VF1601G,
Greenliant ID is read with A3 = 0 (Address range = 00000H to 00007H),
User ID is read with A3 = 1 (Address range = = 00008H to 00087H).
Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
For GLS36VF1602G,
Greenliant ID is read with A3 = 0 (Address range = C0000H to C0007H),
User ID is read with A3 = 1 (Address range = = C0008H to C0087H).
Lock Status is read with A7-A0 = C00FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. SIWA = User Security ID Program word/byte address
For GLS36VF1601G, valid Word-Addresses for User Sec ID are from 00008H to 00087H.
For GLS36VF1602G, valid Word-Addresses for User Sec ID are from C0008H to C0087H.
All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.
7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH).
8. The device does not remain in Software Product Identification mode if powered down.
9. A19 and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode
With A17-A1 = 0;Greenliant Manufacturer’s ID = 00BFH, is read with A0 = 0
GLS36VF1601G Device ID = 7343H, is read with A0 = 1
GLS36VF1602G Device ID = 7344H, is read with A0 = 1
10. Both Software ID Exit operations are equivalent©2010 Greenliant Systems, Ltd.

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GLS36VF1601G / GLS36VF1602G

Data Sheet
11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using theUser Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).
For GLS36VF1601G, valid Word-Addresses for User Sec ID are from 00008H to 00087H.
For GLS36VF1602G, valid Word-Addresses for User Sec ID are from C0008H to C0087H.

TABLE 7: CFI Query Identification String1
Addressx16 Mode
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH

Address
x8 Mode
20H
22H
24H
26H
28H
2AH
2CH
2EH
30H
32H
34H

Data2
0051H
0052H
0059H
0002H
0000H
0000H
0000H
0000H
0000H
0000H
0000H

Description
Query Unique ASCII string “QRY”

Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T7.0 1342

1. Refer to CFI publication 100 for more details.
2. In x8 mode, only the lower byte of data is output.

TABLE 8: System Interface Information
Addressx16 Mode

Address
x8 ModeData1

Description

1BH

36H

0027H

VDD Min (Program/Erase)

1CH

38H

0036H

VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH

3AH

0000H

VPP min (00H = no VPP pin)

1EH

3CH

0000H

VPP max (00H = no VPP pin)

1FH

3EH

0004H

Typical time out for Program 2N µs (24 = 16 µs)

20H

40H

0000H

Typical time out for min size buffer program 2N µs (00H = not supported)

21H

42H

0004H

Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H

44H

0006H

Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H

46H

0001H

Maximum time out for Program 2N times typical (21 x 24 = 32 µs)

24H

48H

0000H

Maximum time out for buffer program 2N times typical

25H

4AH

0001H

Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H

4CH

0001H

Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T8.0 1342

1. In x8 mode, only the lower byte of data is output.

©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data SheetTABLE 9: Device Geometry Information
Addressx16 Mode
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H

Address
x8 Mode
4EH
50H
52H
54H
56H
58H
5AH
5CH
5EH
60H
62H
64H
66H
68H

Data1
0015H
0002H
0000H
0000H
0000H
0002H
00FFH
0001H
0010H
0000H
001FH
0000H
0000H
0001H

Description
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0002H = x8/x16 asynchronous interface
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FFH = 512)z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.1 1342

1. In x8 mode, only the lower byte of data is output.

©2010 Greenliant Systems, Ltd.

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GLS36VF1601G / GLS36VF1602G

Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operationof the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Operating Range:
Range

Ambient Temp

VDD

Commercial

0°C to +70°C

2.7-3.6V

Industrial-40°C to +85°C

2.7-3.6V

AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 23 and 24©2010 Greenliant Systems, Ltd.

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GLS36VF1601G / GLS36VF1602G

Data SheetTABLE 10: DC Operating Characteristics VDD = 2.7-3.6V
LimitsSymbolParameter

IDD1

Active VDD Current
Read

Freq

Min

Max

Units

5 MHz

15

mA

1 MHz

4

mA

30

mA

5 MHz

45

mA

1 MHz

35

mA

Program and Erase
Concurrent Read/Write

Test Conditions

CE#=VIL, WE#=OE#=VIH
CE#=WE#=VIL, OE#=VIH
CE#=VIL, OE#=VIH

ISB

Standby VDD Current

20µA

CE#, RST#=VDD±0.3V

IALP

Auto Low Power VDD Current

20µA

CE#=0.1V, VDD=VDD Max
WE#=VDD-0.1V
Address inputs=0.1V or VDD-0.1V

IRT

Reset VDD Current

20µA

RST#=GND

ILI

Input Leakage Current

1µA

VIN =GND to VDD, VDD=VDD Max

ILIW

Input Leakage Current
on WP# pin and RST# pin

10µA

WP#=GND to VDD, VDD=VDD Max
RST#=GND to VDD, VDD=VDD Max

ILO

Output Leakage Current

1µA

VOUT =GND to VDD, VDD=VDD Max

VIL

Input Low Voltage

0.8

V

VDD=VDD Min

VILC

Input Low Voltage (CMOS)

0.3

V

VDD=VDD Max

VIH

Input High Voltage

0.7 VDD

VDD+0.3

V

VDD=VDD Max

VIHC

Input High Voltage (CMOS)

VDD-0.3

VDD+0.3

V

VDD=VDD Max

VOL

Output Low Voltage

0.2

V

IOL=100 µA, VDD=VDD Min

VOH

Output High Voltage

V

IOH=-100 µA, VDD=VDD Min

VDD-0.2

T10.1 1342

1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 23)

TABLE 11: Recommended System Power-up Timings
SymbolParameter

Minimum

Units

TPU-READ1Power-up to Read Operation

100

µs

TPU-WRITE1

Power-up to Write Operation

100

µs

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

T11.0 1342

TABLE 12: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
CI/O

1

CIN1

Description

Test Condition

Maximum

I/O Pin Capacitance

VI/O = 0V

10 pF

Input Capacitance

VIN = 0V

10 pF

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

T12.0 1342

TABLE 13: Reliability Characteristics
SymbolNEND

1Parameter

Minimum Specification

Units

Test Method

Endurance

10,000

CyclesJEDEC Standard A117

TDR1

Data Retention

100

Years

JEDEC Standard A103

ILTH1

Latch Up

100 + IDDmA

JEDEC Standard 78

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

AC CHARACTERISTICS
TABLE 14: Read Cycle Timing Parameters VDD = 2.7-3.6V
SymbolParameter

Min

TRC

Read Cycle Time

70

TCE

Chip Enable Access Time

70

ns

TAA

Address Access Time

70

ns

TOE

Output Enable Access Time

TCLZ1

CE# Low to Active Output

0

TOLZ1

OE# Low to Active Output

0

TCHZ1

CE# High to High-Z Output

TOHZ1

OE# High to High-Z Output

TOH1

Output Hold from Address Change

0

ns

TRP1

RST# Pulse Width

500

ns

TRHR1

RST# High before Read

50

ns

TRY

1,2

Max

Units
ns

35

ns
ns
ns

16

ns

16

RST# Pin Low to Read Mode

ns

20

µs
T14.1 1342

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.

TABLE 15: Program/Erase Cycle Timing Parameters
SymbolParameter

TBP

Program Time

Min

Max

Units

10

µs

TAS

Address Setup Time

0

ns

TAH

Address Hold Time

40

ns

TCS

WE# and CE# Setup Time

0

ns

TCH

WE# and CE# Hold Time

0

ns

TOES

OE# High Setup Time

0

ns

TOEH

OE# High Hold Time

10

ns

TCP

CE# Pulse Width

40

ns

TWP

WE# Pulse Width

40

ns

TWPH1

WE# Pulse Width High

30

ns

TCPH1

CE# Pulse Width High

30

ns

TDS

Data Setup Time30

ns

Data Hold Time

0

ns

TDH1
1

Software ID Access and Exit Time

150

ns

TSE

Sector-Erase

25

ms

TBE

Block-Erase

25

ms

TSCE

Chip-Erase

50

ms
µs

TIDA

TES

Erase-Suspend Latency

10

TBY1,2RY/BY# Delay Time

90

ns

TBR1

Bus Recovery Time0µs

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.

©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

TRC

TAA

ADDRESSES
TCE
CE#
TOE
OE#
TOLZ

VIH

TOHZ

WE#
TCLZ
DQ15-0TOH

HIGH-ZDATA VALIDTCHZDATA VALID

HIGH-Z
1342 F05.0

FIGURE 9: Read Cycle Timing Diagram

TBP
555

ADDRESSES

2AA

555

ADDR

TAH
TWP
WE#
TWPH

TAS
OE#

TCH
CE#
TCS

TBY

TBR

RY/BY#TDS
DQ15-0

XXAA

XX55

XXA0

TDH

DATA
WORD
(ADDR/DATA)

VALID

1342 F06.0

Note: X can be VIL or VIH, but no other value.

FIGURE 10: WE# Controlled Program Cycle Timing Diagram©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

TBP
555

ADDRESSES

2AA

555

ADDR

TAH
TCP
WE#
TAS

TCPH

OE#
TCH
CE#
TCS

TBY

TBR

RY/BY#TDS
DQ15-0

XXAA

XX55

XXA0

TDH

DATA

VALID

WORD
(ADDR/DATA)

1342 F07.1

Note: X can be VIL or VIH, but no other value.

FIGURE 11: CE# Controlled Program Cycle Timing Diagram

ADDRESS A19-0
TCE
CE#
TOEH

TOES

OE#
TOE
WE#
TBY
RY/BY#

DQ7

DATA

DATA#

DATA#

DATA
1342 F08.1

FIGURE 12: Data# Polling Timing Diagram©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

ADDRESS A19-0
TCE
CE#
TOEH

TOES

TOE

OE#

WE#
TBR
DQ7

VALID DATATWO READ CYCLESWITH SAME OUTPUTS

1342 F09.1

FIGURE 13: Toggle Bit Timing Diagram

TSCE

SIX-BYTE CODE FOR CHIP-ERASEADDRESSES

555

2AA

555

555

2AA

555

CE#

OE#
TOEH
WE#
TBY

TBR

RY/BY#

DQ15-0

XXAA

XX55

XX80

XX55

XXAA

XX10

VALID
1342 F10.1

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. See Table 15 on page 19.
X can be VL or VIH, but not other value.

FIGURE 14: WE# Controlled Chip-Erase Timing Diagram©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet
TBE

SIX-BYTE CODE FOR CHIP-ERASEADDRESSES

555

2AA

555

555

2AA

BAX

CE#

OE#
TWP
WE#
TBR

TBY
RY/BY#

DQ15-0

XXAA

XX55

XX80

XXAA

XX55

XX30

VALID
1342 F11.1

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals areinterchangeable as long as minimum timings are met. See Table 15 on page 19.
BAx = Block Address
X can be VL or VIH, but not other value.

FIGURE 15: WE# Controlled Block-Erase Timing Diagram

TSE

SIX-BYTE CODE FOR CHIP-ERASEADDRESSES

555

2AA

555

555

2AA

SAX

CE#

OE#
TWP
WE#
TBY

TBR

RY/BY#

DQ15-0

XXAA

XX55

XX80

XXAA

XX55

XX50

VALID
1342 F12.1

Note: This device also supports CD# controlled Sector-Erase operation. The WE# and CE# signals areinterchangeable as long as minimum timings are met. See Table 15 on page 19.
BAx = Block Address
X can be VL or VIH, but no other value.

FIGURE 16: WE# Controlled Sector-Erase Timing Diagram©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
555

ADDRESSES

555

2AA

0000

0001

CE#

OE#
TWP TWPH

TIDA

WE#
TAA
DQ15-0

XXAA

XX55

XX90

00BF

Device ID
1342 F13.1

Note: Device ID = 7343H for GLS36VF1601G, and 7344H for GLS36VF1602G
X can be VIL or VIH, but no other value.

FIGURE 17: Software ID Entry and Read

THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESSES

555

555

2AA

CE#

OE#
TWP TWPH

TIDA

WE#
TAA
DQ15-0

XXAA

XX55

XX98
1342 F14.1

Note: X can be VIL or VIH, but no other value.

FIGURE 18: CFI Entry and Read©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESETADDRESSES

DQ15-0

555

555

2AA

XXAA

XX55

XXF0
TIDA

CE#

OE#
TWP TWPH
WE#
1342 F15.1

Note: X can be VIL or VIH, but no other value.

FIGURE 19: Software ID Exit/CFI Exit

THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESSES

555

555

2AA

CE#

OE#
TWP TWPH

TIDA

WE#
TAA
DQ15-0

XXAA

XX55

XX88

SW0

SW1

SW2

1342 F16.1

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1 µs after the commandsequence.
X can be VIL or VIH, but no other value.

FIGURE 20: Sec ID Entry©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data SheetRY/BY#
0V
TRP
RST#

TRHR
CE#/OE#1342 F17.0

FIGURE 21: RST# Timing Diagram (When no internal operation is in progress)

TRY
RY/BY#
TRP
RST#

CE#

TBR

OE#
1342 F18.0

FIGURE 22: RST# Timing Diagram (During Sector- or Block-Erase operation)©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

VIHT
INPUT

VIT

REFERENCE POINTSVOTOUTPUT

VILT
1342 F19.0

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10%  90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

FIGURE 23: AC Input/Output Reference Waveforms

TO TESTER

TO DUTCL

1342 F20.0

FIGURE 24: A Test Load Example©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

Start

Load data: XXAAH
Address: 555H

Load data: XX55H
Address: 2AAH

Load data: XXA0H
Address: 555H

Load
Address/Data

Wait for end of
Program (TBP,
Data# Pollingbit, or Toggle bit
operation)
ProgramCompleted1342 F21.0

Note: X can be VIL or VIH, but no other value.

FIGURE 25: Program Algorithm©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data SheetInternal Timer

Toggle Bit

Data# Polling

Program/Erase
Initiated

Program/Erase
Initiated

Program/Erase
Initiated

Readbyte/word

Read DQ7

Wait TBP,
TSCE, TSE
or TBE

Read samebyte/word

Program/Erase
CompletedNo

Is DQ7 =true data?
Yes

No

Does DQ6
match?

Program/Erase
Completed

Yes
Program/Erase
Completed1342 F22.0

FIGURE 26: Wait Options©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

Software Product ID Entry
Command Sequence

CFI Query Entry
Command Sequence

Sec ID Query Entry
Command Sequence

Load data: XXAAH
Address: 555H

Load data: XXAAH
Address: 555H

Load data: XXAAH
Address: 555H

Load data: XX55H
Address: 2AAH

Load data: XX55H
Address: 2AAH

Load data: XX55H
Address: 2AAH

Load data: XX90H
Address: 555H

Load data: XX98H
Address: 555H

Load data: XX88H
Address: 555H

Wait TIDA

Wait TIDA

Wait TIDA

Read Software ID

Read CFI data

Read Sec ID

X can be VIL or VIH, but no other value1342 F23.0

FIGURE 27: Software Product ID/CFI/Sec ID Entry Command Flowcharts©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence

Load data: XXAAH
Address: 555H

Load data: XXF0H
Address: XXH

Load data: XX55H
Address: 2AAH

Wait TIDA

Load data: XXF0H
Address: 555H

Return to normal
operation

Wait TIDA

Return to normal
operation

X can be VIL or VIH, but no other value1342 F24.0

FIGURE 28: Software Product ID/CFI/Sec ID Exit Command Flowcharts©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

Chip-Erase
Command Sequence

Sector-Erase
Command Sequence

Block-Erase
Command Sequence

Load data: XXAAH
Address: 555H

Load data: XXAAH
Address: 555H

Load data: XXAAH
Address: 555H

Load data: XX55H
Address: 2AAH

Load data: XX55H
Address: 2AAH

Load data: XX55H
Address: 2AAH

Load data: XX80H
Address: 555H

Load data: XX80H
Address: 555H

Load data: XX80H
Address: 555H

Load data: XXAAH
Address: 555H

Load data: XXAAH
Address: 555H

Load data: XXAAH
Address: 555H

Load data: XX55H
Address: 2AAH

Load data: XX55H
Address: 2AAH

Load data: XX55H
Address: 2AAH

Load data: XX10H
Address: 555H

Load data: XX50H
Address: SAX

Load data: XX30H
Address: BAX

Wait TSCE

Wait TSE

Wait TBE

Chip erased
to FFFFH

Sector erased
to FFFFH

Block erased
to FFFFH
1342F25.0

Note: X can be VIL or VIH, but no other value.

FIGURE 29: Erase Command Sequence©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

PRODUCT ORDERING INFORMATION
GLS

36
XX

VF 1601G - 70
XX XXXXX - XXX

-

4C
XX

- B3K
- XXX

E
X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
B3 = TFBGA (6mm x 8mm)
E =TSOP (type 1, die up, 12mm x 20mm)
L1P = LFBGA (8mm x 10mm)
Temperature Range
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Bank Split
1 = 4 Mbit + 12 Mbit
2 = 12 Mbit + 4 Mbit
Device Density
160 = 1 Mbit x16 or
2 Mbit x8
VoltageV = 2.7-3.6V
Product Series
36 = Concurrent SuperFlash
1. Environmental suffix “E” denotes non-Pb solder.
Greenliant non-Pb solder devices are “RoHS Compliant”.

Valid combinations for GLS36VF1601G
GLS36VF1601G-70-4C-B3KE

GLS36VF1601G-70-4C-EKE

GLS36VF1601G-70-4C-L1PE

GLS36VF1601G-70-4I-B3KE

GLS36VF1601G-70-4I-EKE

GLS36VF1601G-70-4I-L1PE

Valid combinations for GLS36VF1602G
GLS36VF1602G-70-4C-B3KE

GLS36VF1602G-70-4C-EKE

GLS36VF1602G-70-4C-L1PE

GLS36VF1602G-70-4I-B3KE

GLS36VF1602G-70-4I-EKE

GLS36VF1602G-70-4I-L1PE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your Greenliant sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet

PACKAGING DIAGRAMSTOP VIEW

BOTTOM VIEW

8.00 ± 0.20

5.60
0.45 ± 0.05
(48X)

0.80

6

6

5

5
4.00

4

4

6.00 ± 0.20

3

3

2

2
1

1
0.80
A B C D E F G H
A1 CORNER

SIDE VIEW

H G F E D C B A
A1 CORNER

1.10 ± 0.10

0.12

SEATING PLANE

1mm

0.35 ± 0.05

Note:

1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
48-tfbga-B3K-6x8-450mic-4

FIGURE 30: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
Greenliant Package Code: B3K©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G

Data Sheet

1.05
0.95
Pin # 1 Identifier
0.50
BSC

0.27
0.17

12.20
11.80

0.15
0.05

18.50
18.30

DETAIL
1.20
max.
0.70
0.50

20.20
19.80
0°- 5°

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

0.70
0.50
1mm
48-tsop-EK-8

FIGURE 31: 48-lead Thin Small Outline Package (TSOP) 12mm x 20mm
Greenliant Package Code: EK©2010 Greenliant Systems, Ltd.

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16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Sheet
TOP VIEW

BOTTOM VIEW

10.00 ± 0.20

5.60
0.80

8

8

7

7

6

6

5.60

5

5

8.00 ± 0.20

4

4

3

3

2

2

1

1
0.80
0.45 ± 0.05
(56X)

H G F E D C B A

A B C D E F G H

A1 CORNER

A1 CORNER
1.30 ± 0.10

SIDE VIEW
1mm

0.12

SEATING PLANE
0.35 ± 0.05
Note:

1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
56-lfbga-L1P-8x10-450mic-4

FIGURE 32: 56-Ball, Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 8mm x 10mm
Greenliant Package Code: L1P

TABLE 16: Revision History
NumberDescription

Date

00

•

Initial release of data sheet

Dec 2006

01•

Edited Tby TY/BY# Delay Time in Table 15 on page 19 from 90ns Min to 90ns Max

Nov 2009

02•

Transferred from SST to Greenliant

May 2010

03•

Corrected XX50 and XX30 values in Figures 15 and 16 on page 23.

Nov 2010© 2010 Greenliant Systems, Ltd. All rights reserved.
Greenliant, the Greenliant logo and NANDrive are trademarks of Greenliant Systems, Ltd.
All trademarks and registered trademarks are the property of their respective owners.
These specifications are subject to change without notice.
CSF is a trademark and SuperFlash is a registered trademark of Silicon Storage Technology, Inc., a wholly owned subsidiary ofMicrochip Technology Inc.

©2010 Greenliant Systems, Ltd.

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