Omni

ision

Advanced Information
Preliminary Datasheet®

OV2640 Color CMOS UXGA (2.0 MegaPixel) CAMERACHIPTM
with OmniPixel2TM Technology
General Description

Applications

The OV2640 CAMERACHIPTM is a low voltage CMOS image
sensor that provides the full functionality of a single-chip
UXGA (1632x1232) camera and image processor in a small
footprint package. The OV2640 provides full-frame,
sub-sampled, scaled or windowed 8-bit/10-bit images in awide range of formats, controlled through the Serial Camera
Control Bus (SCCB) interface.
This product has an image array capable of operating at up
to 15 frames per second (fps) in UXGA resolution withcomplete user control over image quality, formatting andoutput data transfer. All required image processing functions,
including exposure control, gamma, white balance, color
saturation, hue control, white pixel canceling, noise
canceling, and more, are also programmable through the
SCCB interface. The OV2640 also includes a compression
engine for increased processing power. In addition,
OmniVision CAMERACHIPS use proprietary sensor technology
to improve image quality by reducing or eliminating common
lighting/electrical sources of image contamination, such as
fixed pattern noise, smearing, etc., to produce a clean, fully
stable color image.

Pb

Note: The OV2640 uses a lead-freepackage.

Features
•
•
•
•
•
•
•

•

•
•
•
•
•
•
•
•
•

High sensitivity for low-light operation
Low operating voltage for embedded portable apps
Standard SCCB interface
Output support for Raw RGB, RGB (RGB565/555),
GRB422, YUV (422/420) and YCbCr (4:2:2) formats
Supports image sizes: UXGA, SXGA, SVGA, and any
size scaling down from SXGA to 40x30
VarioPixel® method for sub-sampling
Automatic image control functions including Automatic
Exposure Control (AEC), Automatic Gain Control(AGC), Automatic White Balance (AWB), AutomaticBand Filter (ABF), and Automatic Black-Level
Calibration (ABLC)
Image quality controls including color saturation,
gamma, sharpness (edge enhancement), lenscorrection, white pixel canceling, noise canceling, and50/60 Hz luminance detection
Line optical black level output capability
Video or snapshot operation
Zooming, panning, and windowing functions
Internal/external frame synchronization
Variable frame rate control
Supports LED and flash strobe mode
Supports scaling
Supports compression
Embedded microcontroller

Ordering Information
Product
OV02640-VL9A (Color, lead-free)

Version 1.6, February 28, 2006

Package
38-pin CSP2

•
•
•
•

Cellular and Camera Phones
Toys
PC Multimedia
Digital Still Cameras

Key Specifications
Array SizeUXGA 1600 x 1200
Core 1.2VDC + 5%
Analog 2.5 ~ 3.0VDC
Power Supply
I/O 1.7V to 3.3V
125 mW (for 15 fps, UXGAYUV mode)Power
Active140 mW (for 15 fps, UXGA
Requirements
compressed mode)Standby 600 µA
Temperature
Operation -30°C to 70°C
Range Stable Image 0°C to 50°C
• YUV(422/420)/YCbCr422• RGB565/555
Output Formats (8-bit)• 8-bit compressed data
• 8-/10-bit Raw RGB data
Lens Size 1/4"
Chief Ray Angle 25° non-linear
Maximum UXGA/SXGA 15 fps
Image
SVGA 30 fps
Transfer Rate
CIF 60 fps
Sensitivity 0.6 V/Lux-sec
S/N Ratio 40 dB
Dynamic Range 50 dB
Scan Mode Progressive
Maximum Exposure Interval 1247 x tROW
Gamma Correction Programmable
Pixel Size 2.2 µm x 2.2 µm
Dark Current 15 mV/s at 60°C
Well Capacity 12 Ke
Fixed Pattern Noise <1% of VPEAK-TO-PEAK
Image Area 3590 µm x 2684 µm
Package Dimensions 5725 µm x 6285 µm

Figure 1 OV2640 Pin Diagram (Top View)

A1

A2

A3

A4

A5

A6

DOGND EXPST_B AGND SGND VREFN STROBE
B1

B2

DOVDD FREXC1

C2

SIO_D SIO_C
D2

B3

B4

B5

B6

AVDD

SVDD

SVDD

PWDN

C3

C4

C5

C6

HREF XVCLK VREFH RESETB
D6

OV2640

VSYNC

NC

E1

E2

E3

E4

E5

E6

Y1

Y0

PCLK

EGND

Y6

DGND

F1

F2

F3

F4

F5

F6

EVDD

DVDD

Y2

Y4

Y8

DVDD

G1

G2

G3

G4

G5

G6

EVDD

DGND

Y3

Y5

Y7

Y9

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Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

ision

Functional Description
Figure 2 shows the functional block diagram of the OV2640 image sensor. The OV2640 includes:•
Image Sensor Array (1632 x 1232 total image array)•
Analog Signal Processor•
10-Bit A/D Converters•
Digital Signal Processor (DSP)•
Output Formatter•
Compression Engine•
Microcontroller•
SCCB Interface•
Digital Video Port

Figure 2 Functional Block Diagram

10-Bit
A/D

AMP

Image Array(1632 x 1232)

Gain
Control

Row SelectColumn Sample/Hold

Black Level
Compensation

ChannelBalance

DSP

Formatter

Compression Video
EnginePortY[9:0]

Balance
Control
Control
Register
Bank

PLL

XVCLK

2

SCCB Slave
Interface

Timing Generator and Control Logic

HREF

PCLK

VSYNC

STROBE RESETBPWDNProprietary to OmniVision Technologies

SIO_C

Microcontroller

SIO_D

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Functional Description

Image Sensor Array

10-Bit A/D Converters

The OV2640 sensor has an image array of 1632 columns
by 1232 rows (2,010,624 pixels). Figure 3 shows across-section of the image sensor array.

3

4

5

1626

1627

1628

1629

1630

1631

1

0

ColumnRo 0 B Gw 1 G R

2

Figure 3 Sensor Array Region Color Filter Layout

B

G

B

G

B

G

B

G

B

G

Dummy

G

R

G

R

G

R

G

R

G

R

Dummy

2

B

G

B

G

B

G

B

G

B

G

B

G

Dummy

3

G

R

G

R

G

R

G

R

G

R

G

R

Dummy

4
5

Optical
Black

6
7
8

B

G

B

G

B

G

B

G

B

G

B

G

Dummy

9

G

R

G

R

G

R

G

R

G

R

G

R

Dummy

10

B

G

B

G

B

G

B

G

B

G

B

G

Dummy

11

G

R

G

R

G

R

G

R

G

R

G

R

Dummy

12

B

G

B

G

B

G

B

G

B

G

B

G

13

G

R

G

R

G

R

G

R

G

R

G

R

1206

B

G

B

G

B

G

B

G

B

G

B

G

1207

G

R

G

R

G

R

G

R

G

R

G

R

1208

B

G

B

G

B

G

B

G

B

G

B

G

After the analog amplifier, the bayer pattern Raw signal is
fed to two 10-bit analog-to-digital (A/D) converters, one for
G channel and one shared by the BR channels. These
A/D converters operate at speeds up to 20 MHz and are
fully synchronous to the pixel rate (actual conversion rate
is related to the frame rate).

Channel Balance
The amplified signals are then balanced with a channel
balance block. In this block, the Red/Blue channel gain is
increased or decreased to match Green channel
luminance level.

Balance Control
Channel Balance can be done manually by the user or by
the internal automatic white balance (AWB) controller.

1220
ActiveLines

Black Level Compensation
1231

G

R

G

R

G

R

G

R

G

R

G

R

The color filters are arranged in a Bayer pattern. The
primary color BG/GR array is arranged in line-alternatingfashion. Of the 2,010,624 pixels, 1,991,040 (1632x1220)
are active. The other pixels are used for black level
calibration and interpolation.
The sensor array design is based on a field integration
read-out system with line-by-line transfer and anelectronic shutter with a synchronous pixel read-out
scheme.

Analog Amplifier
When the column sample/hold circuit has sampled one
row of pixels, the pixel data will shift out one-by-one into
an analog amplifier.

Gain Control

After the pixel data has been digitized, black level
calibration can be applied before the data is output. The
black level calibration block subtracts the average signal
level of optical black pixels to compensate for the darkcurrent in the pixel output. The user can disable blacklevel calibration.

Windowing
The OV2640 allows the user to define window size or
region of interest (ROI), as required by the application.
Window size setting (in pixels) ranges from 2 x 4 to1632 x 1220 (UXGA) or 2 x 2 to 818 x 610 (SVGA), and408 x 304 (CIF), and can be anywhere inside the1632 x 1220 boundary. Note that modifying window size
or window position does not alter the frame or pixel rate.
The windowing control merely alters the assertion of the
HREF signal to be consistent with the programmed
horizontal and vertical ROI. The default window size is1600 x 1200. Refer to Figure 4 and registers HREFST,
HREFEND, REG32, VSTRT, VEND, and COM1 fordetails.

The amplifier gain can either be programmed by the user
or controlled by the internal automatic gain control circuit(AGC).

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Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

Figure 4 Windowing

ision

CIF Mode

ColumnStart

ColumnEnd

HREF
R Columnow

The OV2640 can also operate at a higher frame rate tooutput 400 x 296 sized images. Figure 6 shows the
sub-sampling diagram in both horizontal and verticaldirections for CIF mode.

Figure 6 CIF Sub-Sampling Mode
Row Start
HREF

Column

i
i+1
i+2
i+3
i+4
i+5
i+6
i+7
i+8
i+9
i+10
i+11
i+12
i+13
i+14
i+15
i+16
i+17
i+18
i+19
i+20
i+21
i+22
i+23

Display
Window

Row

Row EndSensor Array
Boundary

Zooming and Panning Mode
The OV2640 provides zooming and panning modes. The
user can select this mode under SVGA/CIF mode timing.
The related zoom ratios will be 2:1 of UXGA for SVGA and
4:1 of UXGA for CIF. Registers ZOOMS[7:0] (0x49) andCOM19[1:0] (0x48) define the vertical line start point.
Register ARCOM2[2] (0x34) defines the horizontal startpoint.

Sub-sampling Mode
The OV2640 supports two sub-sampling modes. Eachsub-sampling mode has different resolution and maximum
frame rate. These modes are described in the following
sections.

SVGA mode
The OV2640 can be programmed to output 800 x 600(SVGA) sized images for applications where higher
resolution image capture is not required. In this mode,both horizontal and vertical pixels will be sub-sampledwith an aspect ratio of 4:2 as shown in Figure 5.

n B
n+1
n+2
n+3
n+4
n+5 G
n+6
n+7

G

B

G

B

G

R

G

R

G

R

n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
n+20
n+21
n+22
n+23

B

G

B

G

B

G

G

R

G

R

G

R

B

G

B

G

B

G

G

R

G

R

G

R

Skipped Pixels

Timing Generator and Control Logic
In general, the timing generator controls the following:•
Frame Exposure Mode Timing•
Frame Rate Adjust•
Frame Rate Timing

Frame Exposure Mode Timing
Figure 5 SVGA Sub-Sampling Mode
i+9

i+8

i+7

i+6

G

B G

B G

G R

G R

G R

n+4

B

G

B G

B G

n+5

G R

G R

G R

n+1

i+4

i+5

B

Row n

i+3

i

i+1

i+2

Column

n+2
n+3

n+6
n+7
Skipped Pixels

4

Proprietary to OmniVision Technologies

The OV2640 supports frame exposure mode. Typically,
the frame exposure mode must work with the aid of an
external shutter.
The frame exposure pin, FREX (pin B2), is the frame
exposure mode enable pin and the EXPST_B pin (pin A2)
serves as the sensor's exposure start trigger. When theexternal master device asserts the FREX pin high, thesensor array is quickly pre-charged and stays in resetmode until the EXPST_B pin goes low (sensor exposure
time can be defined as the period between EXPST_B low
and shutter close). After the FREX pin is pulled low, thevideo data stream is then clocked to the output port in aline-by-line manner. After completing one frame of data
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ision

Functional Description

output, the OV2640 will output continuous live video data
unless in single frame transfer mode. Figure 18 and
Figure 19 show the detailed timing and Table 11 shows
the timing specifications for this mode.

Output Formatter
This block controls all output and data formatting required
prior to sending the image out.

Frame Rate Adjust

Scaling Image Output

The OV2640 offers three methods for frame rateadjustment:•
Clock prescaler: (see “CLKRC” on page 23)
By changing the system clock divide ratio and PLL,
the frame rate and pixel rate will change together.
This method can be used for dividing the frame/pixel
rate by: 1/2, 1/3, 1/4 … 1/64 of the input clock rate.
•Line adjustment: (see “REG2A” on page 26 and“FRARL” on page 26)
By adding a dummy pixel timing in each line
(between HSYNC and pixel data out), the frame rate
can be changed while leaving the pixel rate as is.
•
Vertical sync adjustment:
By adding dummy line periods to the vertical sync
period (see “ADDVSL” on page 26 and “ADDVSH”
on page 26 or see “FLL” on page 27 and “FLH” onpage 27), the frame rate can be altered while thepixel rate remains the same.

The OV2640 is capable of scaling down the image size
from CIF to 40x30. By using SCCB registers, the user can
output the desired image size. At certain image sizes,
HREF is not consistent in a frame.

Compression Engine
As shown in Figure 7, the Compression Engine consistsof three major blocks:
•
DCT
•
QZ
•
Entropy Encoder

Figure 7 Compression Engine Block Diagram
Compression Engine
Video Data

DCT

QZ

Entropy Encoder

Compressed
StreamFrame Rate Timing
Scale Factor

Q-TableH-TableMarkerDefault frame timing is illustrated in Figure 15, Figure 16,
and Figure 17. Refer to Table 1 for the actual pixel rate atdifferent frame rates.

Table 1

Frame/Pixel Rates in UXGA Mode

Frame Rate (fps)

15

7.5

2.5

1.25

PCLK (MHz)

36

18

6

3

Microcontroller
The OV2640 embeds an 8-bit microcontroller with
512-byte data memory and 4 KB program memory. It
provides the flexibility of decoding protocol commands
from the host for controlling the system, as well as theability to fine tune image quality.

Digital Signal Processor (DSP)
This block controls the interpolation from Raw data to
RGB and some image quality control.
•
Edge enhancement (a two-dimensional high passfilter)•Color space converter (can change Raw data to RGB
or YUV/YCbCr)•
RGB matrix to eliminate color cross talk•Hue and saturation control•
Programmable gamma control•
Transfer 10-bit data to 8-bit•
White pixel canceling•
De-noise

SCCB Interface
The Serial Camera Control Bus (SCCB) interface controls
the CAMERACHIP operation. Refer to OmniVision
Technologies Serial Camera Control Bus (SCCB)Specification for detailed usage of the serial control port.

Slave Operation Mode
The OV2640 can be programmed to operate in slave
mode (default is master mode).
When used as a slave device, COM7[3] (0x12), CLKRC[6](0x11), and COM2[2] (0x09) register bits should be set to

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Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

"1" and the OV2640 will use PWDN and RESETB pins asvertical and horizontal synchronization triggers supplied
by a master device. The master device must provide thefollowing signals:
1.

System clock MCLK to XVCLK pin

2.

Horizontal sync MHSYNC to RESETB pin

3.

Vertical frame sync MVSYNC to PWDN pin

See Figure 8 for slave mode connections and Figure 9 fordetailed timing considerations.

isionPower Down Mode
Two methods are available to place the OV2640 into
power-down mode: hardware power-down and SCCB
software power-down.
To initiate hardware power-down, the PWDN pin (pin B6)
must be tied to high. When this occurs, the OV2640
internal device clock is halted and all internal counters arereset. The current draw is less than 15 µA in this standby
mode.
Executing a software power-down through the SCCB
interface suspends internal circuit activity but does nothalt the device clock. The current requirements drop toless than 1 mA in this mode. All register content ismaintained in standby mode.

Figure 8 Slave Mode Connection

Y[9:0]RESETBMHSYNCPWDN

MVSYNC

XVCLK

MCLK

OV2640MasterDeviceDigital Video Port
MSB/LSB Swap
The OV2640 has a 10-bit digital video port. The MSB andLSB can be swapped with the control registers. Figure 10
shows some examples of connections with external
devices.

Figure 9 Slave Mode Timing
Figure 10 Connection Examples

T frameMVSYNCMSB Y9Y9LSB Y9

Y8

Y8

Y8

Y1

Y7

Y7

Y7

Y2

Y6

Y6

Y6

Y3

NOTE:

Y5

Y5

Y5

Y4

1) THS > 6 Tclk, Tvs > Tline
2) Tline = 1922 x Tclk (UXGA); Tline = 1190 x Tclk (SVGA);
Tline = 595 x Tclk (CIF)

Y4

Y4

Y4

Y5

Y3

Y3

Y3

Y6

Y2

Y2

Y2

Y7

Y1

Y1

Y1

Y8

LSB Y0Y0

MSB Y0Y9

OV2640External
Device

OV2640External
DeviceT VS

T lineMHSYNC

T HS

Tclk

MCLK

3) Tframe = 1248 x Tline (UXGA); Tframe = 672 x Tline (SVGA);
Tframe = 336 x Tline (CIF)

Default 10-bit Connection

Strobe Mode
The OV2640 has a Strobe mode that allows it to work withan external flash and LED.

Reset
The OV2640 includes a RESETB pin (pin C6) that forces
a complete hardware reset when it is pulled low (GND).
The OV2640 clears all registers and resets them to theirdefault values when a hardware reset occurs. A reset canalso be initiated through the SCCB interface.
6

Proprietary to OmniVision Technologies

Y0

Swap 10-bit Connection

MSB Y9Y7LSB Y9

Y8

Y6

Y8

Y7

Y5

Y7

Y0

Y6

Y4

Y6

Y1

Y5

Y3

Y5

Y2

Y4

Y2

Y4

Y3

Y3

Y1

Y3

Y4

Y2

Y0

Y2

Y5

Y1

Y1

Y6

LSB Y0MSB Y0

Y7

OV2640External
Device

OV2640External
DeviceDefault 8-bit Connection

Swap 8-bit Connection

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ision

Functional Description

Line/Pixel Timing

Pixel Output Pattern

The OV2640 digital video port can be programmed towork in either master or slave mode.

Table 2 shows the output data order from the OV2640.
The data output sequence following the first HREF andafter VSYNC is: B0,0 G0,1 B0,2 G0,3… B0,1598 G0,1599.
After the second HREF the output is G1,0 R1,1 G1,2 R1,3…
G1,1598 R1,1599…, etc. If the OV2640 is programmed to
output SVGA resolution data, horizontal and verticalsub-sampling will occur. The default output sequence forthe first line of output will be: B0,0 G0,1 B0,4 G0,5… B0,1596
G0,1597. The second line of output will be: G1,0 R1,1 G1,4
R1,5… G1,1596 R1,1597.

In both master and slave modes, pixel data output issynchronous with PCLK (or MCLK if port is a slave),
HREF, and VSYNC. The default PCLK edge for valid datais the negative edge but may be programmed using
register COM10[4] for the positive edge. Basic line/pixel
output timing and pixel timing specifications are shown in
Figure 14 and Table 10.
Also, using register COM10[5], PCLK output can be gatedby the active video period defined by the HREF signal.
See Figure 11 for details.

Figure 11 PCLK Output Only at Valid Pixels
PCLK
PCLK active edge negative

HREF
PCLK

Table 2
R/C

0

1

2

3

...

1598

1599

0

B0,0

G0,1

B0,2

G0,3

...

B0,1598

G0,1599

1

G1,0

R1,1

G1,2

R1,3

...

G1,1598

R1,1599

2

B2,0

G2,1

B2,2

G2,3

...

B2,1598

G2,1599

3

G3,0

R3,1

G3,2

R3,3

...

G3,1598

R3,1599

PCLK active edge positive

VSYNC

The specifications shown in Table 10 apply for
DVDD = +1.2 V, DOVDD = +2.8 V, TA = 25°C, sensor
working at 15 fps, external loading = 20 pF.

Version 1.6, February 28, 2006

Data Pattern

.
.

.
.

1198 B1198,0 G1198,1 B1198,2 G1198,3 . . . B1198,1598 G1198,1599
1199 G1199,0 R1199,1 G1199,2 R1199,3 . . . G1199,1598 R1199,1599

Proprietary to OmniVision Technologies

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OV2640

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Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

ision

Pin Description
Table 3

Pin Description

Pin Location
A1

8

Name

Pin Type

Function/Description

DOGND

GroundGround for digital video port

A2

EXPST_B

Input

Snapshot Exposure Start Trigger
0:
Sensor starts exposure (only effective in snapshot mode)
1:
Sensor stays in reset mode
Note: There is no internal pull-up/pull-down resistor.

A3

AGND

GroundGround for analog circuit

A4

SGND

GroundGround for sensor array

A5

VREFN

Reference

Internal analog reference - connect to ground using a 0.1 µF capacitor

A6

STROBE

I/O

B1

DOVDD

Power

Power for digital video port

B2

FREX

Input

Snapshot trigger - use to activate a snapshot sequence
Note: There is no internal pull-up/pull-down resistor.

B3

AVDD

Power

Power for analog circuit

B4

SVDD

Power

Power for sensor array

B5

SVDD

Power

Power for sensor array

B6

PWDN

Input

Power-down mode enable, active highNote: There is an internal pull-down resistor.

C1

SIO_D

I/O

SCCB serial interface data I/O

C2

SIO_C

Input

SCCB serial interface clock input
Note: There is no internal pull-up/pull-down resistor.

C3

HREF

I/O

Horizontal reference output
Default: Input
Note: There is no internal pull-up/pull-down resistor.

C4

XVCLK

Input

System clock input
Note: There is no internal pull-up/pull-down resistor.

C5

VREFH

Reference

C6

RESETB

Input

Reset mode, active low
Note: There is an internal pull-up resistor.

D2

VSYNC

I/O

Vertical synchronization output
Default: Input
Note: There is no internal pull-up/pull-down resistor.

D6

NC

–

No connection

E1

Y1

I/O

Video port output bit[1]Default: Input
Note: There is no internal pull-up/pull-down resistor.

Proprietary to OmniVision Technologies

Flash control output
Default: Input
Note: There is no internal pull-up/pull-down resistor.

Internal analog reference - connect to ground using a 0.1 µF capacitor

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ision

Table 3

Pin Description

Pin Description

Pin Location

Name

Pin Type

Function/Description

E2

Y0

I/O

Video port output bit[0]Default: Input
Note: There is no internal pull-up/pull-down resistor.

E3

PCLK

I/O

Pixel clock output
Default: Input
Note: There is no internal pull-up/pull-down resistor.

E4

EGND

Ground

E5

Y6

E6

DGND

GroundGround for digital core

F1

EVDD

Power

Power for internal regulator

F2

DVDD

Power

Sensor digital power (Core)

F3

Y2

I/O

Video port output bit[2]Default: Input
Note: There is no internal pull-up/pull-down resistor.

F4

Y4

I/O

Video port output bit[4]Default: Input
Note: There is no internal pull-up/pull-down resistor.

F5

Y8

I/O

Video port output bit[8]Default: Input
Note: There is no internal pull-up/pull-down resistor.

F6

DVDD

Power

Sensor digital power (Core)

G1

EVDD

Power

Power for internal regulator

G2

DGND

GroundGround for digital core

G3

Y3

I/O

Video port output bit[3]Default: Input
Note: There is no internal pull-up/pull-down resistor.

G4

Y5

I/O

Video port output bit[5]Default: Input
Note: There is no internal pull-up/pull-down resistor.

G5

Y7

I/O

Video port output bit[7]Default: Input
Note: There is no internal pull-up/pull-down resistor.

G6

Y9

I/O

Video port output bit[9]Default: Input
Note: There is no internal pull-up/pull-down resistor.

Version 1.6, February 28, 2006

I/O

Ground for internal regulator
Video port output bit[6]Default: Input
Note: There is no internal pull-up/pull-down resistor.

Proprietary to OmniVision Technologies

9OV2640

Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

ision

Figure 12 Pinout Diagram

A2

A1

A4

A3

A5

A6

DOGND EXPST_B AGND SGND VREFN STROBE
B2

B1

DOVDD FREXC2

C1

SIO_D SIO_C
D2

B3

B4

B5

B6

AVDD

SVDD

SVDD

PWDN

C3

C4

C5

C6

HREF XVCLK VREFH RESETB
D6

OV2640VSYNC

Table 4

E1

E2

E3

E4

E5

E6

Y1

Y0

PCLK

EGND

Y6

DGND

F1

F2

F3

F4

F5

F6

EVDD

DVDD

Y2

Y4

Y8

DVDD

G1

G2

G3

G4

G5

G6

EVDD

DGND

Y3

Y5

Y7

Y9

Ball Matrix
1

2

3

4

5

6

A

DOGND

EXPST_B

AGND

SGND

VREFN

STROBE

B

DOVDD

FREX

AVDD

SVDD

SVDD

PWDN

C

SIO_D

SIO_C

HREF

XVCLK

VREFN

RESETB

D

10

NC

VSYNC

NC

E

Y1

Y0

PCLK

EGND

Y6

DGND

F

EVDD

DVDD

Y2

Y4

Y8

DVDD

G

EVDD

DGND

Y3

75

Y7

Y9

Proprietary to OmniVision Technologies

Version 1.6, February 28, 2006

Omni

ision

Electrical Characteristics

Electrical Characteristics
Table 5Absolute Maximum Ratings

Ambient Storage Temperature

Supply Voltages (with respect to Ground)-40ºC to +95ºC
VDD-A

4.5V

VDD-C

3V

VDD-IO

4.5V

All Input/Output Voltages (with respect to Ground)-0.3V to VDD-IO+1V

Lead-free Temperature, Surface-mount process

245ºC

ESD Rating, Human Body model

2000V

NOTE:

Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.

Table 6

DC Characteristics (-30°C < TA < 70°C)

SymbolParameter

Min

Typ

Max

Unit

SupplyVDD-ASupply voltage

2.5

2.8

3.0

V

VDD-D

Supply voltage

1.14

1.2

1.26

V

VDD-IO

Supply voltagea

1.71

2.8

3.3

V

IDDA-A

Active (Operating) Currentb

30

40

mA

IDDA-D

Active (Operating) Currentb

25 (YUV)
35 (Compressed)

35 (YUV)
50 (Compressed)

mA

IDDA-IO

Active (Operating) Currentb

6

10

mA

1

2

mA

600

1200

µA

0.54

V

IDDS-SCCB

Standby Currentb

IDDS-PWDN
Digital Inputs
VIL

Input voltage LOW

VIH

Input voltage HIGH

CIN

Input capacitor

1.26

V
10

pF

Digital Outputs (standard loading 25 pF)
VOH

Output voltage HIGH

VOL

Output voltage LOW

1.62

V
0.18

V

Serial Interface Inputs
VIL

SIO_C and SIO_D

-0.5

0

0.54

V

VIH

SIO_C and SIO_D

1.26

1.8

2.3

V

a.

1.8V I/O is supported. Contact your local OmniVision FAE for further details.

b.

VDD-A = 2.8V, VDD-D = 1.2V, and VDD-IO = 1.8V for 15 fps in UXGA mode
IDDS-SCCB refers to SCCB-initiated Standby, while IDDS-PWDN refers to PWDN pad-initiated Standby

Version 1.6, February 28, 2006

Proprietary to OmniVision Technologies

11

OV2640
Table 7

Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

ision

AC Characteristics (TA = 25°C, VDD-A = 2.8V)

SymbolParameter

Min

Typ

Max

Unit

ADC Parameters
B

Analog bandwidth

20

MHz

DLE

DC differential linearity error

0.5

LSB

ILE

DC integral linearity error

1

LSB

Table 8Settling time for hardware reset<1

ms

Settling time for software reset<1

ms

Settling time for UXGA/SVGA mode change<1

ms

Settling time for register setting

<300

ms

Max

Unit

Timing Characteristics

SymbolParameter

Min

Typ

6

24

Oscillator and Clock Input
fOSC

Frequency (XVCLK)

tr, tfClock input rise/fall time
Clock input duty cycle

12

Proprietary to OmniVision Technologies

45

50

MHz
5

ns

55

%

Version 1.6, February 28, 2006

Omni

ision

Timing Specifications

Timing Specifications
Figure 13 SCCB Interface Timing DiagramtF

t HIGHtRt HD:DATt SU:DAT

t LOW
SIOC
t SU:STAt HD:STAtSU:STO

SIOD IN
t BUF
tAA

t DH

SIOD OUT

Table 9SCCB InterfaceTiming Specifications

SymbolParameter

Min

Typ

Max

Unit

400

KHz

fSIO_C

Clock Frequency

tLOW

Clock Low Period

1.3

µs

tHIGH

Clock High Period

600

ns

tAA

SIOC low to Data Out valid

100

tBUF

Bus free time before new START

1.3

µs

tHD:STASTART condition Hold time

600

ns

tSU:STASTART condition Setup time

600

ns

tHD:DAT

Data-in Hold time0µs

tSU:DAT

Data-in Setup time

100

ns

tSU:STOSTOP condition Setup time

600

ns

tR, tFSCCB Rise/Fall times

tDH

Data-out Hold time

Version 1.6, February 28, 2006

900

300
50

Proprietary to OmniVision Technologies

ns

ns
ns

13

OV2640

Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

ision

Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing
tp

t pr

t pf

PCLK orMCLKt dphft dphr
HREF

t hd

t su
D[9:0]

P1599/799/399

Invalid
Data

P0

P1

P2

P 1598/798/398 P1599/799/399

t dpd

Table 10

Pixel Timing Specifications

Symbol14

Parameter

Min

Typ

Max

Unit

tp

PCLK period

27.78

ns

tpr

PCLK rising time

3.5

ns

tpf

PCLK falling time

2.2

ns

tdphr

PCLK negative edge to HREF rising edge

0

5

ns

tdphf

PCLK negative edge to HREF negative edge

0

5

ns

tdpd

PCLK negative edge to data output delay

0

5

ns

tsu

Data bus setup time

15

ns

thd

Data bus hold time

8

ns

Proprietary to OmniVision Technologies

Version 1.6, February 28, 2006

Omni

ision

Timing Specifications

Figure 15 UXGA Frame Timing
1248 x tLINE
VSYNC
4 x tLINE

27193 tP

tLINE = 1922 tP

57697 tP

322 tP
HREF
1600 tP
189 tP

80 tP

HSYNC

D[9:0]

Invalid Data
P0 - P1599
Row 0

Row 1

Row 2

Row 1199

Figure 16 SVGA Frame Timing
672 x tLINE
VSYNC
4 x tLINE

7415 tP

tLINE = 1190 tP

73895 tP

390 tP
HREF
800 tP
179 tP

80 tP

HSYNC

D[9:0]

Invalid Data
P0 - P799
Row 0

Row 1

Row 2

Row 599

Figure 17 CIF Mode Frame Timing
336 x tLINE
VSYNC
3707.5 tP

4 x tLINE

tLINE = 595 tP

17907.5 tP

195 tP
HREF
400 tP
89.5 tP

40 tP

HSYNC

D[9:0]

Invalid Data
P0 - P399
Row 0

Version 1.6, February 28, 2006

Row 1

Row 2

Row 295

Proprietary to OmniVision Technologies

15

OV2640

Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

ision

Figure 18 Frame Exposure Mode Timing with EXPST_B Staying Low
Shutter Open
Shutter"Flash Turn ON"

FREXt lineExposure Time

SensorPrecharge

Sensor Timing

t dfvrt dfvft dvsc

VSYNC
t dvh

tdhv

HREF
D[9:0]
Row X

Row 0

Row 1

No following live video
frame if set to transfer
single frameRow 1199

Figure 19 Frame Exposure Mode Timing with EXPST_B Asserted
Shutter Open
Shutter
FREX
t des

tdef

"Flash Turn ON"

EXPST_Bt pre

Exposure Time

SensorPrecharge

Sensor Timing

t dfvrt dfvft dvsc

VSYNC
t dvh

tdhv

HREF
D[9:0]Row X

Table 11

Row 1

No following live video
frame if set to transfer
single frameRow 1199

Frame Exposure Timing Specifications
Symbol

Min

Typ

Max

Unit

tline

1922 (UXGA)

tp

tvs

4

tline

tdfvr

9

tp

tdfvf

4

tline

tdvsc

2

tline

8

tdhv

38964 (UXGA)

tp

tdvh

15928 (UXGA)

tp

tdhso

0

ns

tdef

20

tp

tdes

8

NOTE

16

Row 0

1900 (UXGA)

tp1) FREX must stay high long enough to ensure the entire sensor has been reset.
2) Shutter must be closed no later then 3896 tp after VSYNC falling edge.

Proprietary to OmniVision Technologies

Version 1.6, February 28, 2006

Omni

ision

Timing Specifications

OV2640 Light Response
Figure 20 OV2640 Light Response

OV-9620spectrum response
OV2640 Spectrum Response
200
180
160

Sensitivity

140
120
100
80
60
40
20
1180nm1100nm1060nm1020nm

980nm

940nm

900nm

860nm

820nm

780nm

740nm

700nm

660nm

620nm

580nm

540nm

500nm

460nm

420nm

380nm

300nm

0

WavelengthR

Version 1.6, February 28, 2006

G

B

Proprietary to OmniVision Technologies

17

OV2640

Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

ision

Register Set
Table 12 and Table 13 provides a list and description of the Device Control registers contained in the OV2640. For all register
Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 60 for write and 61 for read.
There are two different sets of register banks. Register 0xFF controls which set is accessible. When register 0xFF=00,
Table 12 is effective. When register 0xFF=01, Table 13 is effective.

Table 12

Device Control Register List (when 0xFF = 00) (Sheet 1 of 4)

Address(Hex)

Register
Name

Default
(Hex)

R/W

00-04

RSVD

XX

–

Description
Reserved
Bypass DSP

18

Bit[7:1]:
Bit[0]:

Reserved
Bypass DSP select0: DSP
1: Bypass DSP, sensor out directly

05

R_BYPASS

0x1

RW

06-43

RSVD

XX

–

Reserved

44

Qs

0C

RW

Quantization Scale Factor

45-4F

RSVD

XX

–

Reserved
Bit[7]:
Bit[6]:
Bit[5:3]:
Bit[2:0]:

LP_DP
Round
V_DIVIDER
H_DIVIDER

50

CTRLl[7:0]

00

RW

51

HSIZE[7:0]40

RW

H_SIZE[7:0] (real/4)

52

VSIZE[7:0]F0RW

V_SIZE[7:0] (real/4)

53

XOFFL[7:0]00

RW

OFFSET_X[7:0]54

YOFFL[7:0]00

RW

OFFSET_Y[7:0]
V_SIZE[8]OFFSET_Y[10:8]
H_SIZE[8]OFFSET_X[10:8]

55

VHYX[7:0]

08

RW

Bit[7]:
Bit[6:4]:
Bit[3]:
Bit[2:0]:56

DPRP[7:0]00

RW

Bit[7:4]:
Bit[3:0]:

DP_SELY
DP_SELX

57

TEST[3:0]00

RW

Bit[7]:
Bit[6:0]:

H_SIZE[9]Reserved

5A

ZMOW[7:0]

58

RW

OUTW[7:0] (real/4)

5B

ZMOH[7:0]

48

RW

OUTH[7:0] (real/4)

5C

ZMHH[1:0]00

RW

Bit[7:4]:
Bit[2]:
Bit[1:0]:

5D-7B

RSVD

XX

–

Reserved

7C

BPADDR[3:0]00

RW

SDE Indirect Register Access: Address

Proprietary to OmniVision Technologies

ZMSPD (zoom speed)
OUTH[8]OUTW[9:8]

Version 1.6, February 28, 2006

Omni

ision

Table 12

Register Set

Device Control Register List (when 0xFF = 00) (Sheet 2 of 4)

Address(Hex)

Register
Name

Default
(Hex)

R/W

7D

BPDATA[7:0]00

RW

SDE Indirect Register Access: Data

7E-85

RSVD

XX

–

Reserved

Description

Module Enable

86

CTRL2

0D

RW

Bit[7:6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

Reserved
DCW
SDE
UV_ADJ
UV_AVG
Reserved
CMX

Module EnableBit[7]:
Bit[6]:
Bit[5:0]:

BPC
WPC
Reserved

87

CTRL3

50

RW

88-8B

RSVD

XX

–

Reserved

8C

SIZEL[5:0]00

RW{HSIZE[11], HSIZE[2:0], VSIZE[2:0]}

8D-BF

RSVD

XX

–

Reserved

C0

HSIZE8[7:0]80

RW

Image Horizontal Size HSIZE[10:3]

C1

VSIZE8[7:0]60

RW

Image Vertical Size VSIZE[10:3]
Module Enable

C2

CTRL0

0C

RW

Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

AEC_EN
AEC_SEL
STAT_SEL
VFIRSTYUV422
YUV_ENRGB_EN
RAW_EN

Module Enable

C3

CTRL1

FF

RW

C4-D2

RSVD

XX

–

Version 1.6, February 28, 2006

Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:CIP
DMY
RAW_GMADGAWBAWB_GAIN
LENC
PRE

Reserved

Proprietary to OmniVision Technologies

19

OV2640
Table 12Address
(Hex)

Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

ision

Device Control Register List (when 0xFF = 00) (Sheet 3 of 4)
Register
Name

Default
(Hex)

R/W

D3

R_DVP_SP

82

RW

D4-D9

RSVD

XX

–

DA

IMAGE_MODE

00

DB-DF

RSVD

XX

Description
Bit[7]:
Bit[6:0]:

Auto mode
DVP output speed control
DVP PCLK = sysclk (48)/[6:0] (YUV0);= sysclk (48)/(2*[6:0]) (RAW)Reserved
Image Output Format SelectBit[7]:
Reserved
Bit[6]:
Y8 enable for DVP
Bit[5]:
Reserved
Bit[4]:
JPEG output enable
0: Non-compressed
1: JPEG output
Bit[3:2]: DVP output format
00: YUV422
01: RAW10 (DVP)
10: RGB565
11: Reserved
Bit[1]:
HREF timing select in DVP JPEG output mode
0: HREF is same as sensor
1: HREF = VSYNC
Bit[0]:
Byte swap enable for DVP
0: High byte first YUYV (C2[4]=0)
YVYU (C2[4] = 1)
1: Low byte first UYVY (C2[4] =0)
VYUY (C2[4] =1)–

Reserved
Reset

20

Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

Reserved
Microcontroller
SCCB
JPEG
Reserved
DVP
IPU
CIF

E0

RESET

04

RW

E1-EF

RSVD

XX

–

Reserved

F0

MS_SP

04

RW

SCCB Master Speed

F1-F6

RSVD

XX

–

Reserved

F7

SS_ID

RW

SCCB Slave ID

Proprietary to OmniVision Technologies

Version 1.6, February 28, 2006

Omni

ision

Table 12Address(Hex)

Register Set

Device Control Register List (when 0xFF = 00) (Sheet 4 of 4)
Register
Name

Default(Hex)

R/W

Description
SCCB Slave Control

F8F9

SS_CTRL

01

MC_BIST

RW

RW

Bit[7:6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

Reserved
Address auto-increase enable
Reserved
SCCB enable
Delay SCCB master clock
Enable SCCB master access
Enable sensor pass through accessBit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:

Microcontroller Reset
Boot ROM selectR/W 1 error for 12K-byte memory
R/W 0 error for 12K-byte memory
R/W 1 error for 512-byte memory
R/W 0 error for 512-byte memory
BIST busy bit for read; One-shot reset of
microcontroller for write
Launch BIST

Bit[0]:
FA

MC_AL

RW

Program Memory Pointer Address Low Byte

FB

MC_AH

RW

Program Memory Pointer Address High Byte

FC

MC_D

80

RW

Program Memory Pointer Access Address
Boundary of register address to separate DSP and sensor register

FD

P_CMD

00

RW

SCCB Protocol Command RegisterFE

P_STATUS

00

RW

SCCB Protocol Status Register
Register Bank SelectFF

RA_DLMT

7F

RW

Bit[7:1]:
Bit[0]:

Reserved
Register bank select0: DSP address
1: Sensor address

NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

Version 1.6, February 28, 2006

Proprietary to OmniVision Technologies

21

OV2640

Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

Table 13

Device Control Register List (when 0xFF = 01) (Sheet 1 of 7)

Address(Hex)

Register
Name

Default
(Hex)

R/W

ision

Description
AGC Gain Control LSBs
Bit[7:0]:

00

GAIN

00

RW

01-02

RSVD

XX

–

Gain setting•
Range: 1x to 32x
Gain = (Bit[7]+1) x (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16)
Note: Set COM8[2] = 0 to disable AGC.
Reserved
Common Control 1
Bit[7:6]:

03

COM1

0F (UXGA)
0A (SVGA),
06 (CIF)RW
Bit[5:4]:
Bit[3:2]:
Bit[1:0]:

Dummy frame control
00: Reserved
01: Allow 1 dummy frame
10: Allow 3 dummy frames
11: Allow 7 dummy frames
Reserved
Vertical window end line control 2 LSBs
(8 MSBs in VEND[7:0] (0x1A))
Vertical window start line control 2 LSBs
(8 MSBs in VSTRT[7:0] (0x19))

Register 04
Bit[7]:
Bit[6]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1:0]:

Horizontal mirror
Vertical flip
VREF bit[0]HREF bit[0]Reserved
AEC[1:0](AEC[15:10] is in register REG45[5:0] (0x45),
AEC[9:2] is in register AEC[7:0] (0x10))

04

REG04

20

RW

05-07

RSVD

XX

–

Reserved

08

REG08

40

RW

Frame Exposure One-pin Control Pre-charge Row Number
Common Control 2
Bit[7:5]:
Bit[4]:

22

Bit[3]:
Bit[2]:
Bit[1:0]:

Reserved
Standby mode enable
0: Normal mode
1: Standby mode
Reserved
Pin PWDN/RESETB used as SLVS/SLHS
Output drive select00: 1x capability
01: 3x capability
10: 2x capability
11: 4x capability

09

COM2

00

RW

0A

PIDH

26

R

Product ID Number MSB (Read only)

0B

PIDL

41

R

Product ID Number LSB (Read only)

Proprietary to OmniVision Technologies

Version 1.6, February 28, 2006

Omni

ision

Register Set

Table 13

Device Control Register List (when 0xFF = 01) (Sheet 2 of 7)

Address(Hex)

Register
Name

Default(Hex)

R/W

Description
Common Control 3
Bit[7:3]:
Bit[2]:

0C

COM3

38

RW
Bit[1]:
Bit[0]:

Reserved
Set banding manually
0: 60 Hz
1: 50 Hz
Auto set banding
Snapshot option
0: Enable live video output after snapshot sequence
1: Output single frame only

Common Control 4

0D

COM4

07

RW

Bit[7:3]:
Bit[2]:

Bit[1:0]:
0E-0F

RSVD

XX

–

Reserved
Clock output power-down pin status
0: Tri-state data output pin upon power-down
1: Data output pin hold at last state before power-downReserved

Reserved
Automatic Exposure Control 8 bits for AEC[9:2] (AEC[15:10] is inregister REG45[5:0] (0x45), AEC[1:0] is in register REG04[1:0] (0x04))
AEC[15:0]: Exposure time

10

AEC

33

RW

TEX = tLINE x AEC[15:0]
Note: The maximum exposure time is 1 frame period even if TEX islonger than 1 frame period.
Clock Rate Control
Bit[7]:

11

CLKRC

00

RW

Bit[6]:
Bit[5:0]:

Internal frequency doublers ON/OFF selection
0: OFF
1: ON
Reserved
Clock divider

CLK = XVCLK/(decimal value of CLKRC[5:0] + 1)

Version 1.6, February 28, 2006

Proprietary to OmniVision Technologies

23

OV2640

Omni

Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

Table 13

Device Control Register List (when 0xFF = 01) (Sheet 3 of 7)

Address(Hex)

Register
Name

Default
(Hex)

R/W

ision

Description
Common Control 7
Bit[7]:

Bit[6:4]:
12

COM7

00

RW
Bit[3]:
Bit[2]:
Bit[1]:

Bit[0]:SRST
1: Initiates system reset. All registers are set to factory
default values after which the chip resumes normal
operation
Resolution selection
000: UXGA (full size) mode
001: CIF mode
100: SVGA mode
Reserved
Zoom mode
Color bar test pattern
0: OFF
1: ON
Reserved

Common Control 8
Bit[7:6]:
Bit[5]:

13

COM8

C7

RW

Bit[4:3]:
Bit[2]:

Bit[1]:
Bit[0]:

Reserved
Banding filter selection
0: OFF
1: ON, set minimum exposure time to 1/120s
Reserved
AGC auto/manual control selection
0: Manual
1: AutoReserved
Exposure control
0: Manual
1: AutoCommon Control 9
Bit[7:5]:

14

COM9

50

RW

Bit[4:0]:24

Proprietary to OmniVision Technologies

AGC gain ceiling, GH[2:0]000: 2x001: 4x010: 8x011: 16x
100: 32x
101: 64x
11x: 128x
Reserved

Version 1.6, February 28, 2006

Omni

ision

Register Set

Table 13

Device Control Register List (when 0xFF = 01) (Sheet 4 of 7)

Address(Hex)

Register
Name

Default(Hex)

R/W

Description
Common Control 10 (if Bypass DSP is selected)
Bit[7]:

Bit[6]:

Bit[5]:

Bit[4]:
15

COM10

00

RW

Bit[3]:

Bit[2]:
Bit[1]:

Bit[0]:CHSYNC pin output swap
0: CHSYNC
1: HREF
HREF pin output swap
0: HREF
1: CHSYNC
PCLK output selection
0: PCLK always output
1: PCLK output qualified by HREF
PCLK edge selection
0: Data is updated at the falling edge of PCLK (user
can latch data at the next rising edge of PCLK)
1: Data is updated at the rising edge of PCLK (user canlatch data at the next falling edge of PCLK)HREF output polarity
0: Output positive HREF
1: Output negative HREF, HREF negative for data
valid
Reserved
VSYNC polarity
0: Positive
1: Negative
HSYNC polarity
0: Positive
1: Negative

16

RSVD

XX

–

Reserved

17

HREFST

11

RW

18

HREFEND

75 (UXGA),
43 (SVGA,
CIF)

RW

19

VSTRT

01 (UXGA),
00 (SVGA,
CIF)

RW

1A

VEND

97

RW

1B

RSVD

XX

–

Reserved

1C

MIDH

7F

R

Manufacturer ID Byte – High

(Read only = 0x7F)

1D

MIDL

A2

R

Manufacturer ID Byte – Low(Read only = 0xA2)

1E-23

RSVD

XX

–

Reserved

Horizontal Window Start MSB 8 bits (3 LSBs in REG32[2:0] (0x32))
Bit[10:0]: Selects the start of the horizontal window, each LSB
represents two pixels
Horizontal Window End MSB 8 bits (3 LSBs in REG32[5:3] (0x32))
Bit[10:0]: Selects the end of the horizontal window, each LSB
represents two pixels
Vertical Window Line Start MSB 8 bits (2 LSBs in COM1[1:0] (0x03))
Bit[9:0]:

Selects the start of the vertical window, each LSB
represents two scan lines.

Vertical Window Line End MSB 8 bits (2 LSBs in COM1[3:2] (0x03))

Version 1.6, February 28, 2006

Bit[9:0]:

Selects the end of the vertical window, each LSB
represents two scan lines.

Proprietary to OmniVision Technologies

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Table 13

Device Control Register List (when 0xFF = 01) (Sheet 5 of 7)

Address(Hex)

Register
Name

Default(Hex)

R/W

Description

24

AEW

78

RW

Luminance Signal High Range for AEC/AGC Operation
AEC/AGC values will decrease in auto mode when average luminanceis greater than AEW[7:0]

25

AEB

68

RW

Luminance Signal Low Range for AEC/AGC Operation
AEC/AGC values will increase in auto mode when average luminanceis less than AEB[7:0]
Fast Mode Large Step Range Threshold - effective only in AEC/AGC
fast mode (COM8[7] = 1)

26

VV

D4

RW

Bit[7:4]: High thresholdBit[3:0]:Low threshold
Note: AEC/AGC may change in larger steps when luminance averageis greater than VV[7:4] or less than VV[3:0].

27-29

RSVD

XX

–

Reserved
Register 2ABit[7:4]:

2A

REG2A

00

RW

Bit[3:2]:
Bit[1:0]:Line interval adjust value 4 MSBs (LSBs in FRARL[7:0](0x2B))HSYNC timing end point adjustment MSB 2 bits
(LSBs in register HEDY[7:0] (0x31))
HSYNC timing start point adjustment MSB 2 bits
(LSBs in register HSDY[7:0] (0x30))

Line Interval Adjustment Value LSB 8 bits (MSBs in REG2A[7:4](0x2A))
2B

FRARL

00

RW

2C

RSVD

XX

–

The frame rate will be adjusted by changing the line interval. Each LSB
will add 1/1922 Tframe in UXGA and 1/1190 Tframe in SVGA mode to teframe period.
Reserved
VSYNC Pulse Width LSB 8 bits

2D

ADDVSL00

RW

Bit[7:0]:Line periods added to VSYNC width. Default VSYNC
output width is 4 x tline. Each LSB count will add 1 x tline
to the VSYNC active period.

VSYNC Pulse Width MSB 8 bits
2E

2F

ADDVSH

YAVG

00

00

RW

RW

Bit[7:0]:Line periods added to VSYNC width. Default VSYNC
output width is 4 x tline. Each MSB count will add
256 x tline to the VSYNC active period.

Luminance Average (this register will auto update)
Average Luminance is calculated from the B/Gb/Gr/R channel average
as follows:
B/Gb/Gr/R channel average =(BAVG[7:0] + (2 x GbAVG[7:0]) + RAVG[7:0]) x 0.25

30

26

HSDY

08

RW

Proprietary to OmniVision Technologies

HSYNC Position and Width, Start Point LSB 8 bits
This register and REG2A[1:0] (0x2A) define HSYNC start position,
each LSB will shift HSYNC start by 2 pixel period

Version 1.6, February 28, 2006

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Register Set

Table 13

Device Control Register List (when 0xFF = 01) (Sheet 6 of 7)

Address(Hex)

Register
Name

Default
(Hex)

R/W

31

HEDY

30

RW

Description
HSYNC Position and Width, End Point LSB 8 bits
This register and REG2A[3:2] (0x2A) define HSYNC end position,
each LSB will shift HSYNC end by 2 pixel period
Common Control 32
Bit[7:6]:

32

REG32

36 (UXGA),
09 (SVGA,
CIF)

RW
Bit[5:3]:
Bit[2:0]:

Pixel clock divide option
00: No effect on PCLK
01: No effect on PCLK
10: PCLK frequency divide by 2
11: PCLK frequency divide by 4
Horizontal window end position 3 LSBs (8 MSBs inregister HREFEND[7:0] (0x18))
Horizontal window start position 3 LSBs (8 MSBs inregister HREFST[7:0] (0x17))

33

RSVD

XX

–

Reserved

34

ARCOM2

20

RW

35-44

RSVD

XX

–

45

REG45

00

RW

46

FLL

00

RW

Frame Length Adjustment LSBs
Each bit will add 1 horizontal line timing in frame

47

FLH

00

RW

Frame Length Adjustment MSBs
Each bit will add 256 horizontal lines timing in frameBit[7:3]:
Bit[2]:
Bit[1:0]:

Reserved
Zoom window horizontal start point
Reserved

Reserved
Register 45
Bit[7:6]:
Bit[5:0]:

AGC[9:8], AGC highest gain control
AEC[15:10], AEC MSBs

Common Control 19
48

COM19

00

RW

49

ZOOMS

00

RW

Zoom Mode Vertical Window Start Point 8 MSBs

4A

RSVD

XX

–

Reserved

4B

COM22

20

RW

4C-4D

RSVD

XX

–

Bit[7:2]:
Bit[1:0]:

Reserved
Zoom mode vertical window start point 2 LSBs

Common Control 22
Bit[7:0]:Flash light control

Reserved
Common Control 25 - reserved for banding
Bit[7:6]:
Bit[5:4]:
Bit[3:0]:50Hz Banding AEC 2 MSBs
60HZ Banding AEC 2 MSBs
Reserved

4E

COM25

00

RW

4F

BD50

CA

RW

50Hz Banding AEC 8 LSBs

50

BD60

A8

RW

60Hz Banding AEC 8 LSBs

51-5C

RSVD

XX

–

Reserved

Version 1.6, February 28, 2006

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Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™

Table 13

Device Control Register List (when 0xFF = 01) (Sheet 7 of 7)

Address(Hex)

Register
Name

Default
(Hex)

R/W

5D

REG5D

00

RW

5E

REG5E

00

RW

5F

REG5F

00

RW

60

REG60

00

RW

61

HISTO_LOW

80

RW

Histogram Algorithm Low Level

62

HISTO_HIGH

90

RW

Histogram Algorithm High Level

63-7E

RSVD

XX

–

Reserved

ision

Description
Register 5DBit[7:0]:

AVGsel[7:0], 16-zone average weight option

Register 5E
Bit[7:0]:

AVGsel[15:8], 16-zone average weight option

Register 5FBit[7:0]:

AVGsel[23:16], 16-zone average weight option

Register 60
Bit[7:0]:

AVGsel[31:24], 16-zone average weight option

NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

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Package Specifications

Package Specifications
The OV2640 uses a 38-ball Chip Scale Package 2 (CSP2). Refer to Figure 11 for package information, Table 9 for package
dimensions and Figure 12 for the array center on the chip.

Note: For OVT devices that are lead-free, all part marking letters arelower case. Underlining the last digit of the lot number indicates CSP2 isused.
Figure 21 OV2640 Package Specifications
A
1

2

3

J1

S1
4

5

6

6

5

4

3

2

1

S2

A

A

B

B
J2

C

C

wxyz
abcd

D

B

D

E

E

F

F

G

G

Top View (Bumps Down)

Bottom View (Bumps Up)
Center of BGA (die) =Center of the package

Glass

Die

C2

C3

C1

Table 14

Part Marking Code:w- OVT Product Versionx- Year the part is assembledy- Month the part is assembledz- Wafer number
abcd - Last four digits of lot number

C

C4

Side View

OV2640 Package Dimensions
Parameter

SymbolMinimum

NominalMaximum

Unit

Package Body Dimension X

A

5700

5725

5750

µm

Package Body Dimension Y

B

6260

6285

6310

µm

Package Height

C

845

905

965

µm

Ball Height

C1

150

180

210

µm

Package Body Thickness

C2

680

725

770

µm

Cover Glass Thickness

C3

375

400

425

µm

Airgap Between Cover Glass and Sensor

C4

30

45

60

µm

Ball Diameter

D

320

350

380

µm

Total Pin CountN

38 (1 NC)

Pin Count X-axis

N1

6

Pin Count Y-axis

N2

7

Pins Pitch X-axis

J1

800

µm

Pins Pitch Y-axis

J2

800

µm

Edge-to-Pin Center Distance Analog X

S1

833

863

893

µm

Edge-to-Pin Center Distance Analog Y

S2

713

743

773

µm

Version 1.6, February 28, 2006

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Sensor Array Center
Figure 22 OV2640 Sensor Array Center

A1

A2

A3

A4

A5

A6

A rray C enter(469.6 μm, 145 μm)3590.4 μm
2684 μm

S ens orA rrayOV 2640
P ac kage C enter(0, 0)T op V iew
NOT E S : 1. T his drawing is not to s cale and is for reference only.
2. As mos t optical as s emblies invert and mirror the image, the chip is typically mountedwith pins A1 to A6 oriented down on the P C B .

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Package Specifications

IR Reflow Ramp Rate Requirements
OV2640 Lead-Free Packaged Devices
Note: For OVT devices that are lead-free, all part marking letters arelower case
Figure 23 IR Reflow Ramp Rate Requirements
300.0

Z1

Z2

Z3

Z4

Z5

Z6

Z7

end

280.0
260.0
240.0
220.0

Temperature ( C )

200.0
180.0
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0

0.0
-22

-2

0.6
18

38

1.1
58

78

1.6
98

118

2.2
138

158

2.8
178

198

3.3
218

238

258

3.9
278

298

318

338

358 369

Time (sec)Table 15

Reflow Conditions
Condition

Exposure

Average Ramp-up Rate (30°C to 217°C)

Less than 3°C per second> 100°C

Between 330 - 600 seconds> 150°C

At least 210 seconds> 217°C

At least 30 seconds (30 ~ 120 seconds)

Peak Temperature

245°C

Cool-down Rate (Peak to 50°C)

Less than 6°C per second

Time from 30°C to 245°C

No greater than 390 seconds

Version 1.6, February 28, 2006

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ision

Note:
•

All information shown herein is current as of the revision and publication date. Please referto the OmniVision web site (http://www.ovt.com) to obtain the current versions of all
documentation.

•

OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current productdocumentation prior to placing orders).

•

Reproduction of information in OmniVision product documentation and specifications ispermissible only if reproduction is without alteration and is accompanied by all associatedwarranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.

•

This document is provided with no warranties whatsoever, including any warranty ofmerchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, byestoppels or otherwise, to any intellectual property rights is granted herein.

•‘OmniVision’, ‘VarioPixel’, and ’OmniPixel2’ are trademarks of OmniVision Technologies, Inc.
All other trade, product or service names referenced in this release may be trademarks orregistered trademarks of their respective holders. Third-party brands, names, and trademarks are
the property of their respective owners.

For further information, please feel free to contact OmniVision at info@ovt.com.

OmniVision Technologies, Inc.
1341 Orleans Drive
Sunnyvale, CA USA(408) 542-3000

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REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.0

DESCRIPTION OF CHANGES
Initial Release

Omni

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REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.01

DESCRIPTION OF CHANGESThe following changes were made to version 1.0:
• Under Key Specifications on page 1, changed specification for Core Power Supply from
“1.2VDC + 10%” to “1.2VDC + 5%”• Under Key Specifications on page 1, changed specification for Analog Power Supply
from “2.8VDC + 10%” to “2.5 ~ 3.0VDC”• Under Key Specifications on page 1, changed specification for I/O Power Supply from
“1.8V to 3.3V” to “1.7V to 3.3V”• On pages 17 to 20, changed title of Table 12 from “Device Control Register (for 0x00 ~0xFF at 0xF8 = 00 and 0xFF = 00)” to “Device Control Register (when 0xFF = 00)”
• On pages 21 to 27, changed title of Table 13 from “Device Control Register (for 0x00 ~0x7E at 0xF8 = 01 and 0xFF = 7F)” to “Device Control Register (when 0xFF = 01)”
• In Table 12 on pages 18, changed description of register CTRL3 (0x87) from:
Module EnableBit[7:6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

Reserved
DCW
SDE
UV_ADJ
UV_AVG
Reserved
CMX

toModule EnableBit[7]:
BPC
Bit[6]:
WPC
Bit[5:0]: Reserved•

In Table 15 on page 30, changed specification for Peak Temperature from “Greater than
245°C” to “245°C”

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REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.1

DESCRIPTION OF CHANGESThe following changes were made to version 1.01:• Under Features on page 1, changed bulleted item from “Supports image sizes: UXGA,
SVGA, and any size scaling down from SVGA to 40x30” to “Supports image sizes:
UXGA, SXGA, SVGA, and any size scaling down from SXGA to 40x30”• Under Key Specifications on page 1, deleted specifications for SVGA and CIF Array Size
• Under Key Specifications on page 1, changed Standby Power Requirements specification
to “TBD”• Under Key Specifications on page 1, changed specification for Chief Ray Angle from
“TBD” to “25° non-linear”• Under Key Specifications on page 1, changed specification for Well Capacity from
“TBD” to “12 Ke”• Under Electrical Characteristics on page 10, changed title of Table 6 from “DC
Characteristics (-20°C < TA < 70°C)” to “DC Characteristics (-30°C < TA < 70°C)”
•
•
•
•
•
•
•
•

•

In Table 6 on page 10, changed specification for Typ Standby Current from “10” to“TBD”
In Table 6 on page 10, changed specification for Max Input voltage LOW (VIL) from“0.8” to “0.54”
In Table 6 on page 10, changed specification for Min Input voltage HIGH (VIH) from “2”
to “1.26”
In Table 6 on page 10, changed subtitle “Digital Outputs (standard loading 25 pF, 1.2 KΩ
to 2.8V)” to “Digital Outputs (standard loading 25 pF)”
In Table 6 on page 10, changed specification for Min Output voltage HIGH (VOH) from“2.2” to “1.62”
In Table 6 on page 10, changed specification for Max Output voltage LOW (VOL) from“0.6” to “0.18”
In Table 6 on page 10, changed specification for Serial Interface Inputs Max SIO_C andSIO_D (VIL) from “1” to “0.54”
In Table 6 on page 10, changed specification for Serial Interface Inputs Min, Typ, andMax SIO_C and SIO_D (VIH) from “2.5, 2.8, and VDD-IO + 0.5” to “1.26, 1.8, and 2.3”,
respectively
In Table 6 on page 10, changed table footnote b from “...VDD-IO = 2.8V” to“...VDD-IO = 1.8V”

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DESCRIPTION OF CHANGES (CONTINUED)••••In Figure 21 on page 28, changed callout C3 to measure from thickness of glass and added
callout C4 to measure airgap from glass to die.
In Table 14 on page 28, changed C3 parameter name from “Thickness of Glass Surface toWafer” to “Cover Glass Thickness”
In Table 14 on page 28, changed C3 Minimum, Nominal, and Maximum specifications
from “425, 445, and 465” to “375, 400, and 425”
In Table 14 on page 28, added C4 parameter, Airgap Between Cover Glass and Sensor,
and Minimum, Nominal, and Maximum specifications “30, 45, and 60”, respectively

Omni

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TM

REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.2

DESCRIPTION OF CHANGESThe following changes were made to version 1.1:
• Under Key Specifications on page 1, changed Active Power Requirements specification to“TBD” to “125 mW (for 15 fps, UXGA YUV mode)” and “140 mW (for 15 fps, UXGA
compressed mode)”• Under Key Specifications on page 1, changed Standby Power Requirements specification
to “TBD” to “600 µA”• Under Key Specifications on page 1, deleted Preview (CIF) Power Requirements
specification• In Table 6 on page 10, changed specification for Typ Active (Operating) Current (IDDA-A)
from “TBD” to “30”
• In Table 6 on page 10, changed specification for Typ Active (Operating) Current (IDDA-D)
from “TBD” to “25 (YUV)” and “35 (Compressed)”• In Table 6 on page 10, changed specification for Typ Active (Operating) Current (IDDAIO) from “TBD” to “6”••IIn Table 6 on page 10, changed specification for Typ Standby Current from “10” to “600”In Table 6 on page 10, changed table footnote b from “...VDD-IO = 1.8V” to“...VDD-IO = 1.8V for 15 fps in UXGA mode”

Omni

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REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.21

DESCRIPTION OF CHANGESThe following changes were made to version 1.2:
• In Figure 1 on page 21, corrected the bottom view of the package by correcting the column
numbers corresponding to the ball locations from (left to right) “1”, “2”, “3”, “4”, “5”,and “6” to (left to right) “6”, “5”, “4”, “3”, “2”, and “1”, respectively

Omni

ision

TM

REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.3

DESCRIPTION OF CHANGESThe following changes were made to version 1.21:• In Table 1 on page 8, made the following changes/corrections:– Corrected pin type of pin A1 from Power to Ground– Corrected pin type of pin A2 from I/O to Input and added “Note: There is no internal
pull-up/pull-down resistor”– Corrected pin type of pin A3 from Power to Ground– Corrected pin type of pin A4 from Power to Ground– Corrected pin type of pin A5 from I/O to Reference– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pin A6– Corrected pin type of pin B2 from Power to Input and added “Note: There is nointernal pull-up/pull-down resistor”– Corrected pin type of pin B3 from Input to Power– Corrected pin type of pin B4 from I/O to Power– Corrected pin type of pin B5 from Input to Power– Corrected pin type of pin B6 from I/O to Input and “Note: There is an internal pulldown resistor”– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pin C3– Added “Note: There is no internal pull-up/pull-down resistor” to description of pin C4– Added “Note: There is an internal pull-up resistor” to description of pin C6– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pin D2– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pin E1– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pin E2– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pin E3– Corrected pin type of pin E4 from Power to Ground– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pin E5– Corrected pin type of pin E6 from Power to Ground

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DESCRIPTION OF CHANGES (CONTINUED)•In Table 1 on page 8, made the following changes/corrections:– Corrected pin type of pin F2 from Analog to Power and changed description to“Sensor digital power (Core)”– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pins F3, F4, and F5– Corrected pin type of pin F6 from Analog to Power and changed description to be thesame as pin F2– Corrected pin type of pin G2 from Power to Ground– Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” todescription of pins G3, G4, G5, and G6

Omni

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REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.4

DESCRIPTION OF CHANGESThe following changes were made to version 1.3:
• In Table 6 on page 11, made the following changes:– Added “40 mA” for Maximum specification of IDDA-A–

Added “35 mA (YUV)” and “50 mA (Compressed)” for Maximum specification of
IDDA-D–

Added “10 mA” for Maximum specification of IDDA-IO–

Added “2 mA” for Maximum specification of IDDS-SCCB–

Added “1200 µA” for Maximum specification of IDDS-PWDN

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REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.5

DESCRIPTION OF CHANGESThe following changes were made to version 1.4:
• Under Register Set section on page 18, changed the second paragraph from
“There are two different sets for register address from 0x00 to 0x7E. Both register 0xF8
and register 0xFF control which set is accessible. When 0xF8=00 and 0xFF=00, Table 12
is effective. When 0xF8=01, 0xFF=7F, Table 13 is effective.”to“There are two different sets of register banks. Register 0xFF controls which set isaccessible. When register 0xFF=00, Table 12 is effective. When register 0xFF=01, Table
13 is effective.”

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REVISION CHANGE LIST
Document Title: OV2640 Datasheet

Version: 1.6

DESCRIPTION OF CHANGESThe following changes were made to version 1.5:
• In Table 12 on page 18, changed name, default, R/W, and description of register 0x44
from “RSVD”, “XX”, “–”, and “Reserved” to “Qs”, “0C”, “RW”, and “Quantization Scale
Factor”• In Table 12 on page 21, changed description of register RA_DLMT (0xFF) from:
Sensor/Device Register Address Delimiter<(value of register 0xFF): Sensor address(value of register 0xFF): DSP address

to:Register Bank SelectBit[7:1]: Reserved
Bit[0]:
Register bank select0: DSP address
1: Sensor address••

In Table 13 on page 22, changed default value for register REG08 (0x08) from“00” to “40”In Table 13 on page 22, changed description of register bits COM2[1:0] (0x09) from:
00: Weakest
01: Double capability
10: Double capability
11: Triple drive capability

to:00: 1x capability
01: 3x capability
10: 2x capability
11: 4x capability•••

In Table 13 on page 22, changed default value for register PIDL (0x0B) from“40” to “41”
In Table 13 on page 23, changed description of register bit CLKRC[6] (0x11) to“Reserved”
In Table 13 on page 25, added “(if Bypass DSP is selected)” to description of register
COM10 (0x15)