Investigation and Optimal Design of
Output Capacitance in Chopper byHigh Speed Voltage Response Control
Jun-ichi Itoh*, Daisuke Sato*, and Takayuki Shibuya**Nagaoka University of Technology, Niigata, Japan
Abstract-- This paper describes an optimal design method
for a current regulator and an output voltage regulator witha output capacitor in a boost-up chopper. In order to reduce
the output capacitor and the boost-up reactor, high speed
response of the current regulator and the output voltage
regulator are required. In this paper, the current controller
is designed based on dead-beat control with P, PI or IP
regulator. Then, it is confirmed that the maximum control
response of the dead-beat controller is limited up to 0.32 of
the sampling frequency, which is the switching frequency.
The minimum output capacitor is calculated by thecontrol response of the output voltage regulator and theallowance of the voltage fluctuation. Moreover, the validitiesof the design method are confirmed by experimental resultsthat the design values agree well with the analysis results
within 8.53% error.
Index Terms-- Boost chopper, ACR(Auto Current
Regulator), AVR(Auto Voltage Regulator), Dead-beatcontrol.

I. INTRODUCTION
In recent years, high efficiency and high power density
for the high power DC/DC converters are increasingly
desired for electric vehicles (EV) and smart grid systems
and so on. In order to respect these demands, a passive
component such as a boost-up reactor and a smoothing
capacitor must become small [1-6].
A miniaturization of the boost-up reactor can achieve
by a high switching frequency, interleave or a multilevel[1-4].
Recently, digital controllers using DSP or FPGA are
applied widely to their DC/DC converters [7-9]. Since
especially development of FPGA is progressing, fasterhigh-speed control can be achieved. Previously, PI
control based on analog control is commonly used for thecurrent control in digital control system. On the other
hand, high performance control methods based on digital
control theory has been studied such as typified by adead-beat control and a multi-rate sampling control.
Certainly, the control performance can improve
spectacularly with high speed sampling using the FPGA.
However, the relation among the voltage fluctuation, thesmoothing capacitance and the response speed are notstill clarified. Furthermore, in the control system which
has current control loop and voltage control loop, thecontrol response of the output voltage regulator is also
limited because it is responded to the current regulator.
The maximum control response of the voltage controller
has also been not clarified yet.

This paper discusses a design method and responsebounds of the current control and the voltage control in aboost chopper. The PI regulator is used for the output
voltage control, and the dead-beat control is applied tothe input current control. The dead-beat controller isdesigned based on P regulator, PI regulator and IP
regulator [9]. The first section in this paper introduces adesign method about the input current control and theoutput voltage control. Secondly, how to select the
optimal sampling frequency from the gain characteristicof the input current is described. In addition, a design
method of a capacitance in terms of the suppression of
the output voltage fluctuation and the natural angler
frequency of the voltage control is clarified. Finally, thevalidity of the selection method of sampling frequency
and the design method of the capacitance is confirmed bysimulation and experimental results.
II. CIRCUIT CONFIGURATION
Fig. 1 shows a circuit configuration of two-quadrant
boost chopper. This circuit consists of two switching
devices, a boost-up reactor and a smoothing capacitor. In
order to obtain the high power density, it is very
important using the small passive components.
Fig. 2 shows the control block diagrams with thevoltage control loop and the current control loop. In the
boost chopper, the output voltage Vout is controlled by the
input current IL1 flowing into a reactor L. The PI regulator
is applied to the output voltage regulator and the deadbeat control is applied to the input current regulator. The
dead-beat control is designed for three kinds of regulators,
which is based on P, PI or IP regulator. Furthermore, theinput voltage Vin, the output voltage Vout and the input
current IL1 are detected for each control. It should be
noted that Vin is constant because of simplification for the
analysis.

Fig 1. Circuit configuration of two-quadrant boost chopper.

III. CONTROL METHOD
A. Output Voltage Control
It is assumed that the ACR (auto current regulator)
response is enough faster than that of the AVR (autovoltage regulator). Then the ACR system gain can beassumed to 1 when the output voltage control is discussed.
The output voltage is decided by the capacitor current
Ic. The capacitor current Ic is obtained by (1).

1K
1 + s PV
K IV

Fig. 3 shows the relationship between the input current
IL1 and the output current IL2. The input current IL1 isswitched by the switching device Sw1. Thus, the output
current IL2 is a discontinuous waveform of PWM.
Therefore, the relationship between IL1 and IL2 is obtainedby (2) by using the modulation factor of the chopper α.
I L 2 = αI L1 ....................................................................... (2)Thus, the input current command IL1* is obtained by(3).
I L1 * =

1

α

K IV
s

1

1
sC

α

α

(a) AVR (Auto Voltage Regulator).

I c = I L 2 − I out .................................................................. (1),where IL2 is the output current in the switching device
Sw1, and Iout is the load current. Therefore, Ic can becontrolled by a chopper output current IL2. In this case,the load current Iout is deemed to a disturbance. However,the current regulator controls the input current IL1, insteadof IL2. Therefore, it is need to convert from IL1 to IL2.

K PV +

1
Vout

K PP

1
2z −1

K PIP +

1
sL1

Vout

1
Vout

K PII
s

1
Vout

K IPI
s
K IPD

(b) ACR (Auto Current Regulator).
Fig. 2. Control block diagrams.

I L 2 * ................................................................ (3)The modulation factor α equals 1/β at static state when
the boost ratio of the chopper is defined by β. In additiona closed-loop transfer function of the AVR GV is obtainedby (4).
K IV
C

GV =
s2 −

K
K PV
s + IVC
C.................................................(4),where KPV is proportional gain of the PI regulator, KIV is
integral gain of the PI regulator in the AVR and C is
output capacitance value.
KPV and KIV is designed by natural angular frequency
and damping coefficient. These parameters are calculated
by comparing between the transfer function of the AVR
and the normal form of second-order lag. These are
obtained by (5).

Fig. 3. Relationship between the input current and the output
current of the chopper.

ACR. In terms that, the discrete transfer function GP, GPI
and GIP are calculated as (6), (7) and (8) from Fig. 2(b).

K PV = 2ξωnv C, K IV = ω nv C ............................................(5),

T
K PP
L
GP =
.........................................................(6),Tz + K PP − 1
Lwhere ξ is damping coefficient and ωnv is natural angularfrequency.

where KPP is proportional gain of the P regulator, L is theboost-up reactor value and T is sampling time.

B. Input current Control
The dead-beat control is applied to the ACR. The
dead-beat control can that controlled objects are followed
in n sampling time. Therefore, the effect of control delayof the ACR can be suppressed in the AVR.
P, PI and IP regulators are considered to apply to theT{( z − 1) K PIP + K PII }L..........(7),G PI =K PIP
K PIP
K PII 2 ⎞⎛2z +(T − 2) z + ⎜⎜1 −
T+
T ⎟⎟
L
L
L
⎠
⎝

2

where KPIP is proportional gain of the PI regulator and
KPII is integral gain of the PI regulator.

G IP =K IPI 2
T
L1
K
K
K
⎞
⎛
z + ( IPD T − 2) z + ⎜⎜1 − IPD T + IPI T 2 ⎟⎟
L
L
L
⎠
⎝

..........(8),2where KIPI is integral gain of the IP regulator and KIPD isdifferential gain of the PI regulator.
The destination filter in PI control at Fig. 2(b-2)
negates a zero point of control system. In order to achieve
the dead-beat control, the gain of each controller isdesigned so that all poles in each closed loop transfer
function become zero. As the result, GP=1/z,
GPI=GIP=1/z2, P control is a system to follow after one
sampling time. The current, which is regulated by the PI
control and the IP control follow in the current command
after two sampling time.
C. Selection of Sampling Frequency in Current Control
In this section, selection of the sampling frequency is
discussed in applying the dead-beat control to the current
control.
Fig. 4 shows an approximation model timing chart ofthe dead-beat control response. The current command is asinusoidal waveform of amplitude Im. The P regulator
follows a command after one sampling time and PI
regulator and IP regulator follow commands after two
sampling time. Thus, PI regulator and IP regulator have
one sample delay compared with P regulator and theirgain characteristics are same as P regulator.
Fig. 5 shows a gain characteristic of the input current
IL1 when the current command frequency fref is changed
for the sampling frequency fs. As show in Fig. 5, it isconfirmed that the gain degradation is suppressed when
the sampling frequency is higher than the command
frequency. If the gain degradation acceptable amount is 3
dB, fref / fs = 1/3.15 = 0.32. Therefore, if the current
command frequency fref is the intended current response
frequency fd, the switching frequency fs has to be
designed to three times of fd.
D. Relationship between Output Voltage Fluctuation andCapacitance value
The output voltage is fluctuated by load fluctuation. In
this section, the relationship among the voltage
fluctuation, the output capacitance and the voltage control
response is formulated when the load current Iout changes
step fluctuation. It assumes that the ACR response isenough faster than the AVR response. It means that thecommand of the output current IL2* equal to the output
current IL2, because the ACR gain is 1 in the AVR
response band. The disturbance closed-loop transfer
function when the load current is input Gload(s) is
obtained by (9).
1sC.......................................... (9)G load ( s ) = 2
2
s + 2ξω nv s + ω nv−

The damping factor ξ is 0.707 and the natural angularfrequency ωnv is design value. Therefore, the unit step
response Cload(t) of Gload(s) is obtained by (10).

Fig. 4. An approximation model timing chart of the input current of thedead-beat control response.

Fig. 5. The gain characteristic by the sampling frequency in the current
control applied to the dead-beat control.

1⎤⎡⎢G load ( s ) ⋅ s ⎥⎣⎦........... (10)1=−e −ξω n t sin ⎛⎜ ω nv 1 − ξ 2 t ⎞⎟⎝⎠Cω 1 − ξ 2

C load (t ) = L-1

nv

The maximum value of the output voltage fluctuation
is same as overshoot in the unit step response. Therefore,
the voltage fluctuation ΔVout is calculated when the slopeof differentiation of (10) equals zero. This time Tp isobtained by (11).
Tp =1

ω nv 1 − ξ 2tan −1 (−

1−ξ 2

ξ

) ................................. (11)The voltage fluctuation ΔVout by the load current
fluctuation ΔIout is calculated by substituting (11) into
(10), and it is obtained by (12).
ΔVout = −=−ΔI outCωnv 1 − ξ 2−eξ
1− ξ 2⎛ 1− ξ 2 ⎞⎜⎟tan − 1 ⎜
⎟
⎜ ξ
⎟
⎝
⎠

⎧
⎛ 1 − ξ 2 ⎞ ⎫⎪⎪⎟sin ⎨tan −1 ⎜
⎜ ξ
⎟⎬
⎪⎩
⎝
⎠ ⎪⎭

Ka
ΔI outCωnv....................................................................................(12),where Ka comprises ξ and it is constant. Therefore, thevoltage fluctuation ΔVout is inversely proportional to the
output capacitance C and the natural angular frequency
ωnv. The output capacitance C is calculated by acceptable
voltage fluctuation and ωnv, and it is obtained by (13).
The output capacitance can be designed by (13).
C= −ΔI out K a............................................................ (13)
ΔVoutωnv

IV. SIMULATION RESULTS
A. Characteristic of Gain in Current Control System
In this section, the validity of the sampling frequency
which developed in section 3 is confirmed. The
simulation conditions are the input voltage Vin = 1 p.u.,
the output voltage Vout = 2 p.u., the input current
amplitude Im = 1 p.u. and the boost-up reactor L = 0.16
msec. In addition, the sampling frequency of P, PI and IP
regulators are fs = 3.15 fref. It should be noted that any
parameters are normalized by the input voltage Vin = 25V
and the rating current In = 4A.
Fig. 6 shows the frequency response of the input
current IL1 by simulation. As a result, the gain
characteristics are decreased as the command frequency
fref approaches the intended response frequency fd. The
gain degradation acceptable amount which is designed on
fref = fd is nearly consistent with 3 dB at any regulators.
Thus, it is necessary that fs is designed to become 3.15
times of fd at the dead-beat control systems which do notcontain a zero point.
B. Characteristics of Output Voltage Response
In this section, it is confirmed that relationship among
the output voltage fluctuation ΔVout, the output
capacitance C and the natural angular frequency which
was considered in section 3. The simulation conditions
are the input voltage Vin = 1 p.u., the boost-up reactor L =0.32 msec, C = 11.3 msec, the voltage control naturalangular frequency ωnv = 100 rad/sec, the current control
natural angular frequency ωd = 2πfd = 20000 rad/sec andthe sampling frequency fs = 3.15fd = 10 kHz.
Fig. 7 shows the output voltage response and the input
current response when the output voltage command Vout*is fluctuated from 2 p.u. to 2.4 p.u.. Vout_ideal is obtained
from the output voltage by the control block diagram of
an ideal model. As a result, it is confirmed that thecontrol system achieves just as designed response.
Because, the output voltage Vout is almost equal Vout_ideal.
Fig. 8 shows the voltage response and the current
response when the load current Iout is step fluctuationfrom 0 p.u. to 0.5 p.u.. As a result, the voltage fluctuation
ΔVout is 0.199 p.u., the voltage fluctuation of the ideal
model ΔVout_ideal = 0.203 p.u. by the load current step andthe voltage fluctuation error is 1.97 %.
Fig. 9 shows the voltage fluctuation when the voltage
control natural angular frequency ωnv is changed in theload step response. As a result, ΔVout_cal which is
calculated by (11) is almost equal the voltage fluctuationof the ideal model. In addition, the output voltage
fluctuation of calculation result ΔVout_cal is inversely
proportional to ωnv as with the calculus equation. Thus,
the validity of the mathematical expression of output
voltage fluctuation is confirmed. It should be noted that,the simulation model has an error on the result of theideal model and calculation result. This reason is that the
input current command IL1* has to be compensated by themodulation factor α for IL2*, but the modulation factor at
static state in the proposed control is compensated by α =1/β.
Fig. 10 shows the voltage fluctuation by the load

Fig. 6. The gain characteristic by P, PI and IP regulator of the input
current applied to the dead-beat control.

Fig. 7. The output voltage response when the output voltage command isfluctuated.

Fig. 8. The output voltage and the input current response when the load
current is fluctuated.

Fig. 9. The output voltage fluctuation value by the load current step at
C=1800μF.

current step when the voltage fluctuation ΔVout isdesigned to 0.2 p.u.. The output capacitance was designedby (12). The voltage control natural angular frequency
ωnv are 50 rad/sec, 100 rad/sec and 200 rad/sec. The
simulation results have an error between the calculation
results because the above compensation method impinges.
Therefore, it is confirmed that the output capacitance canbe designed by the voltage fluctuation and the voltage
natural angular frequency using (12).

C. Maximum Natural Angular Frequency of Voltage
Control System
In the discussion of the preceding sections, the output
capacitance is designed by the voltage control naturalangular frequency ωnv. However, it has limitation toincrease the voltage control natural angular frequency ωnv.
Because there is control system delay or saturation ofmanipulated variable. At this point, the current control
assumes the dead-beat control 1/z and control systemdelay is simulated. The dead-beat control has to follow
the command within one sampling time, but rate ofchange of the current is limited by the boost-up reactor
and the source voltage. Namely, a step width of thecurrent has to be inside of VinTα/L in order to follow
within one sampling time. Therefore, the load current
step ΔIout is decided on 0.8 VinTα/L because a control
margin is considered.
Fig. 11 shows the output voltage fluctuation ΔVout by
simulation when the voltage control natural angularfrequency ωnv is changed. As the result, an error of ΔVout
increases for the calculation result from ωnv = 1000
rad/sec and the farther voltage fluctuation cannot
suppress at ωnv = 3000 rad/sec. The sampling frequency
is 10 kHz so the manipulated variable is saturated at
approximately 1/20 of the sampling frequency. This
reason is that the response of the voltage control systemslows by delay of the current control system because of
the increased ωnv. Therefore, a limit of the voltage control
system response frequency is approximately 1/20 of theswitching frequency. Further, when the design conditionare ωnv = 3000 rad/sec and ΔVout = 0.01 p.u., theminimum output capacitance value Cmin is 304 μF.
However, in case of ωnv = 600 rad/sec using theconventional PI regulator without the dead-beat control,
Cmin is 1520 μF, in other words it is 5 times as using thedead-beat control.
V. EXPERIMENTAL RESULTS
A. Response Confirmation of Current Control System
In this section, the response of the current control
system is confirmed by experimentation. The current
control system is applied to the P-type dead-bead control.
The conditions of experimentation are the input voltage
Vin = 1 p.u., the output voltage Vout = 2 p.u., the boost-up
reactor L = 0.32 msec and the sampling frequency fs = 1/T= 10 kHz. Further, parameters are normalized by the
input voltage Vin = 25V and the rating current In = 4A.
Fig. 12 shows the response of the current waveformwhen the current command is changed from 0.5 A to 1 A.
In addition, the command is raised at the point of risen
Trigger signal. As the result, IL1 follows from 0.5 A to 1A
in T = 100 μsec. Therefore, it is confirmed that the
response is one-order dead-beat control response.
B. Assessment of Voltage Control System
In this section, it is discussed that a basic operation byexperimentation and the voltage fluctuation by the designof the output capacitance. The load current step on thesimulation and the experimentation is simulated by a stepchange of the load resistance. The conditions ofFig. 10. The output voltage fluctuation value by the load
current step at designed ΔVout=0.2p.u..

Fig. 11. The output voltage fluctuation value for the voltage
control natural angular frequency ωnv.

Fig. 12 The response of the input current when the current command ischanged from 0.5 A to 1 A.

experimentation are the input voltage Vin = 1 p.u., theoutput voltage Vout = 2 p.u., the boost-up reactor L = 0.8
msec, the sampling frequency fs = 3.15 fd = 10kHz andthe load resistance R = 4 p.u.. It should be noted thatparameters are normalized by the input voltage Vin = 25 V
and the rating current In = 4 A.
Fig. 13 shows the output voltage step response when
the output voltage command Vout* is changed from 2 p.u.
to 2.4 p.u.. As the result, the time to peak of the output
voltage response Tpi is 42.4 msec. The time to peak of thenormal form of second-order lag Tpi_ideal is 44.4 msec, so
it is confirmed that the response of as designed is
obtained because the control system response of actual
equipment is an error of 4.4 %.
Fig. 14 shows the output voltage response when theload resistance is changed from 0 p.u. to 4 p.u.. As theresult, the voltage fluctuation ΔVout is 0.186 p.u. by theload current step. The error between the calculation result
is 8.53% by ΔVout_cal = 0.203 p.u.. The reasons of theseerrors are an effect of equivalent series resistance of theoutput capacitance (ESR), a damping effect by theconverter loss and an error of the output capacitancevalue.
Fig. 15 shows the voltage fluctuation when the load
resistance is changed from 0 p.u. to 4 p.u.. As the result,
it is confirmed that the voltage fluctuation ΔVout of thesimulation and the experimental result are smaller thanthe calculation at the low voltage control natural angularfrequency. This reason is that it is simulated by the load
resistance step rather than the load current step.
Fig. 16 shows the voltage fluctuation ΔVout by the load
resistance step when ΔVout is designed to 0.2 p.u. As theresult, it is confirmed that ΔVout is lower than the design
value. The cause of error is as above. From Fig. 16, it isconfirmed that even if the capacitance value is 1/4, thevoltage fluctuation value is not change by increasing thevoltage control natural angular frequency ωnv by 4 times.

Vout*=2p.u.

Vout*=2.4p.u.

Vout[0.4p.u/div]
ps = 42.4msec

00IL1 [0.625p.u./div]
20[msec/div]

Fig. 13.The output voltage response when the output voltage command ischanged from 2 p.u. to 2.4 p.u..

VI. CONCLUSION
This paper described about the current control of theboost chopper and the critical response design of theoutput voltage control system. When the dead-beatcontrol is applied to the input current control, thesampling frequency (carrier frequency) is designed toover 3.15 times of configured the response frequency.
Furthermore, relationship among the output voltage
fluctuation, the voltage natural angular frequency and theoutput capacitance is formulated on the voltage control
system when the load current step is input and these
relations were clarified. Therefore, the voltage systemnatural angular frequency has to design under 3000
rad/sec. In addition, from the experiment, it is confirmedthat the voltage fluctuation obtained a value as designed
and even if the capacitance value is 1/4, the voltage
fluctuation value is not change by increasing speed of thevoltage response.
In a future, the voltage control will be designed basedon dead-beat control. Besides it will be confirmed byexperimentation.
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Fig. 15. The output voltage fluctuation by load resistance step at
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Fig. 16. The output voltage fluctuation by load resistance step designed
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