Requirements for Circuit Components of Single-Phase Inverter
Applied with Power Decoupling Capability toward High Power Density
Jun-ichi Itoh, Tomokazu Sakuraba, Hoai Nam Le, Keisuke Kusaka
Nagaoka University of Technology
1603-1 Kamitomioka-machi, Nagaoka city Niigata, Japan
Tel., Fax: +81 / (258) – 47.9533.
E-Mail: itoh@vos.nagaokaut.ac.jp, t_sakuraba@stn.nagaokaut.ac.jp
URL: http://itohserver01.nagaokaut.ac.jp/itohlab/index.html

Keywords«High power density systems», «Single phase system», «Power conditioning»

Abstract
This paper discusses how to achieve high power density with high efficiency for a single-phase
inverter with an active power decoupling circuit. In conventional PV inverters, bulky electrolytic
capacitors are connected to DC-link in order to absorb power pulsation with twice the grid frequency.
On the other hand, in the active power decoupling circuit, the small capacitor can be used. However, theadditional inductors and switching devices are necessary. Thus, the power density of the active power
decoupling circuit is reduced. In this paper, the Pareto optimization of power density and efficiency isused to clarify the maximum power density points of the power decoupling circuits. As a result, themaximum power density of the conventional boost type active buffer, which connects a boost chopper
to DC-link, is 90% of that of electrolytic capacitor topology. In addition, this paper proposes a DC-DC
converter with the power decoupling capability in order to achieve higher power density than that of thepassive topology. The proposed circuit, which requires no additional inductor for the power decoupling
circuit, uses discontinuous current mode (DCM) for the power decoupling capability. As a result, themaximum power density is obtained to 1.1 times higher than that of passive topology. However, thetotal loss of switching devices is 1.5 times higher. Thus, in order to surpass the efficiency of the passive
topology by the active power decoupling, the switching device is required to reduce the total loss by
35% compared to the present products.

I. Introduction
In recent years, single-phase grid connected converters has been studied actively as the power
conversion systems (PCSs) for the photovoltaics system or battery energy storage system and so on [14]. Instantaneous power of the single-phase grid oscillates at twice the grid frequency whereas the output
power is constant. As a result, a power ripple with twice the grid frequency occurs at the connection
point between the chopper and the inverter. In order to absorb this power ripple, bulky electrolytic
capacitors are used in the conventional circuit. However, the electrolytic capacitor limits the lifetime of
the PCS [5].
As an alternative power decoupling method, an active power decoupling, which consists of small
capacitors, inductors and switching devices, has been proposed [6-8]. As a result, the PCS with long
lifetime is expected by using film capacitors or ceramic capacitors as the buffer capacitor. In particular,buck type active buffer circuits, whose the buffer capacitor voltage is lower than DC-link voltage, areactively proposed [9-11]. In these circuit topologies, since the maximum voltage of the buffer capacitor
is limited, the reduction of the buffer capacitance has limitations due to the satisfaction of the average
stored energy of buffer capacitor CV 2/2. Moreover, due to the large effective current of a smoothing
inductor, the conduction loss of the switching devices becomes high. As a result, the large coolingsystem leads to the lower power density system. In order to drastically increase the power density of asingle-phase inverter, fans are used to minimize the heatsinks [12]. However, the system lifetime islimited by these fans. Thus, the cooling system is desirable to be designed on the assumption that thenatural cooling is applied.
On the other hand, an additional inductor and switching devices for the buffer circuit are required tocontrol the buffer capacitor voltage. By increasing the switching frequency of the buffer circuit, theinductance can be reduced due to the reduction of required store energy of the inductor. However, thesize of the heatsink becomes larger due to the increase of the switching loss. As a result, the relationshipbetween the inductor volume and the heatsink volume results with the trade-off characteristics. Thus,
the buffer circuit should be designed and operated at an adequate switching frequency to maximize thepower density. However, past literatures which were investigated by authors do not mention clearly thecondition to achieve higher efficiency and power density than the electrolytic capacitor topology.
This paper clarifies the conditions to achieve high power density with high efficiency by comparison
between the electrolytic capacitor and the active power decoupling topologies. Moreover, a novel circuit
topology, which requires no additional inductor for the power decoupling circuit, is proposed. The
proposed circuit uses discontinuous current mode (DCM) for the power decoupling capability. This
paper is organized as follows; first, the design flow for the passive topology using the electrolytic
capacitor and the active buffer topology using the ceramic capacitor is introduced. Second, from thedesign flowchart and the specifications of the present products, the power density and the efficiency areevaluated by Pareto-front. Third, the requirements for components in the active power decoupling circuit
to surpass the passive topology in terms of the efficiency and the power density are clarified. Finally,
the power density and the efficiency of the proposed circuit are evaluated by Pareto-front optimization.

II. CIRCUIT CONFIGURATION AND DESIGN METHOD
A. Passive power decoupling circuit
Fig. 1 shows the circuit configuration of a DC to single-phase AC converter with the passive power
decoupling method. Table I shows the circuit specifications. This paper evaluates the volume of thebuffer circuit based on the ripple current in DC-link.
In the passive topology circuit, the bulky electrolytic capacitor is connected for compensation of thesingle-phase power ripple. The ripple current restricts the lifetime of the electrolytic capacitor.
Therefore, in this paper, the electrolytic capacitor, which has the allowable ripple current higher thanthe calculated ripple current, is selected. The current which flows into the electrolytic capacitor includes
not only the power ripple component but also the switching frequency component from the inverter. The
capacitor ripple current is the function of the output power factor angle φ and the modulation index m,which is a nonlinear value [13]. Then, the effective value of the capacitor ripple current is expressed by
I rms _ cap = K cap (φ , m ) I m(1),
where, Im is the maximum value of the output current and Kcap(φ, m) is the coefficient which is obtainedby simulation.
Fig. 2 shows the simulated result of Kcap(φ, m). Kcap(φ, m) is decided from Fig. 2 as follows. Generally,
the output power factor of the grid-connected inverter is approximately unity. The modulation index,
which expresses the ratio of the input voltage Vin andSpthe maximum output voltage Vm, is 0.74 in this case.
icap
iout
Therefore, from Fig. 2, Kcap(1.0, 0.74) is 0.56. With thevout
Cdc
Lchopperfrequency multipliers, the allowable ripple current is
2-levelLC
inverterfiltercalculated by
Vin
S
2

2

 I
  1  ∞ 2
  I nsw′ _ cap =  100 Hz  + 
(2),
I rms
 K 100 Hz   K sw  n =1
where, I100Hz is the effective current whose frequencies
are twice the grid frequency, Insw is the effective current
at the switching frequency, K100Hz and Ksw are thefrequency multipliers at 100 Hz and the switchingfrequency, respectively. An electrolytic capacitor,
which has the allowable ripple current higher than the
result of (2), should be required.

B. Boost type active buffer circuit
Fig. 3 shows the relationship among the input powerpin, the output power pout and the compensation powerpbuf in the active buffer. The output instantaneous
power is shown in (3) when the output current is thesinusoidal wave with unity power factor.

n

Vdc

Passive buffer

Fig. 1. DC to single-phase AC converter with
passive power decoupling circuit.
Table I. System specification.

Vm I m(1 − cos 2ω out t )2(3),

where, Vm is the peak voltage of the single-phasegrid and ωout is the angular frequency of a grid.
From (3), the power ripple, whose frequency is
twice the grid frequency, occurs at the DC link.
In order to absorb the power ripple, theinstantaneous power pbuf in the active buffer iscontrolled according to1
p buf = V m I m cos 2ω out t
2

(4).

0.7

Current ripple coefficient Kcap

p out =

0.6
0.5
0.4
0.3
0.2
0.1
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Fig. 2. Current coefficient for the calculation of theFig. 4 shows a circuit configuration of an ripple current flowing into the electrolytic capacitor.
active buffer circuit. In this circuit, because the
V I(1 − cos 2ω t )p =2
buffer capacitor voltage is higher than the DCVm I m
Pin =link voltage, this active power decoupling circuit
2
is classified as the boost type active buffer. The
active buffer consists of a boost chopper and asmall capacitor Cbuf which absorbs the power
ripple in the DC-link. The active buffer circuitachieves long lifetime because the film capacitors
or the ceramic capacitors is used as the buffer
Fig. 3. Single-phase power ripple compensation.
capacitor. A small filter capacitor Cf is connected
in order to absorb the ripple current at theswitching frequency. The principle for the power
decoupling between the DC and the AC sides is
explained as follows.
Fig. 5 shows the design flowchart in order todesign the boost type active buffer. First, thecapacitance of the buffer capacitor is calculated
based on an average voltage and a voltage
Fig. 4. DC to single-phase AC converter with boost
oscillation range of the buffer capacitor. Then, thetype active buffer circuit.
capacitor volume VolCbuf is determined from thepresent products. The switching device is decided based on the maximum voltage of the buffer capacitor.
In this paper, the switching device, which has a rating voltage of 1200 V, is used. Second, the boost
inductor is designed based on the switching frequency fsw and the inductor ripple current. The volumeof the boost inductor is estimated by Area Product concept [14]. Third, the heatsink volume is calculated
from the thermal resistance which depends on the conduction loss Ploss_cond and the switching loss Ploss_sw
of the switching devices. Finally, the pareto-front is obtained through varying the switching frequency
in order to clarify the maximum power density point.
The selection method of the buffer capacitor is discussed. The capacitance is decided from therelationship between the storage energy Pc and the capacitor voltage. Thus, from the instantaneous
power in (4), the capacitance to compensate the power ripple is calculated by
Pc
Cbuf =(5),
ωoutVave ΔVc
where Vave is the average voltage and ΔVc is the voltage oscillation range of the buffer capacitor.
In passive topology circuit with the bulky electrolytic capacitor, the storage power is achieved by thelarge capacitance. On the other hand, in the active buffer, the storage power is achieved through thelarge ΔVc. This is the principle to reduce the capacitance with active power decoupling method.
The buffer capacitor requires the large Vave and ΔVc for reducing the capacitance. However, when thebuffer capacitor voltage is increased, the switching device with the high rating voltage is required. In
this paper, the switching device which has the rating voltage of 1200 V is selected as the peak capacitor
voltage is designed at 800 V.
The boost inductor is designed based on the ripple current ΔiL. The inductance becomes the maximum
value when the difference between the input voltage and the buffer capacitor voltage reaches the
out

m m

out

maximum. Thus, the inductance of the boost
inductor is provided by
ΔV c 
 V ave + − V dc
V dc 
2 (6).
Lbuf =ΔV c
Δi L f sw
V ave +
2
The inductor volume depends on many
parameters of the components. There are several
ways to select the core for the inductor. In thispaper, the boost inductor is designed by Area
Product concept using the window area and thecross-sectional area [14]. Therefore, the volume of
the boost inductor VolLbuf is calculated by
3
4

Start
Input
Pout
Vdc
vout
fout
m
iL
Vin
iin
iin

Decision Vave, Vc
Calculation
Cbuf , VolCbuf from Fig. 7
Selection Switching device
Switching frequency fsw=1 kHz~100 kHz
Calculation
Lbuf , and VolLbuf by Eq. (7)Calculation
Conduction and Switching loss, Volheatsink by Eq. (8)Calculation total volumeVoltotal by Eq. (18)
Calculation
Power density

power, Efficiency

by Eq. (17), (19)fsw

2
 Lbuf I max



End
Vol Lbuf = K v(7),
 K u Bmax J 
Fig. 5. Designing flow for active buffer circuit.

where, Kv is the volume coefficient depending on the shape of cores, Imax is the maximum current flowing
to the inductor, Ku is the window utilization factor, Bmax is the maximum flux density of the core, and J
is the current density of the wire.
The switching devices require a cooling system such as heatsinks and fans. In general, the coolingsystem is designed based on the thermal resistance. CSPI (Cooling System Performance Index) is
introduced to estimate the volume of cooling system [15]. CSPI means the cooling performance per unit
volume of the cooling system. The cooling system is miniaturized when CSPI become higher. The
volume of the cooling system Volheatsink is provided by

Vol heatsink =1
Rth ( f − a )CSPI(8),

where, Rth(f-a) is the thermal resistance of the cooling system which is given by
T j − Ta(9),
Rth ( f −a ) =− (Rth ( j −c ) + Rth (c− f ) )Plosswhere, Tj is the junction temperature of the switching device, and Ta is the ambient temperature. The
total loss Ploss, which is composed of the conduction loss Ploss_cond and the switching loss Ploss_sw from theswitching devices, is calculated by
Ploss = Ploss _ cond + Ploss _ sw
(10),
where, Ploss_cond and Ploss_sw are given by
1 Tout 2
Ploss _ cond =iL ron dt(11),
Tout 0eon + eoff
1 Tout(12),
Ploss _ sw =f sw
vciL dt
Edcd I md
Tout 0respectively, where, Tout is the period time of the grid, ron is the on resistance of the switching device, fsw
is the switching frequency of the active buffer, eon and eoff is the turn-on and turn-off energy per switchingfrom datasheet respectively, Edcd and Imd are the voltage and the current under the measurement conditionof the switching loss from the datasheet. The buffer capacitor voltage vc and the boost inductor current
iL is expressed by(13),v c = V ave + ΔV c cos (2ω out t )Vdvi L = ave C buf c
(14),
Vin
dt
respectively. From (12), the increase in the switching frequency leads to the increase in the switchingloss. The cooling performance can be improved by fans to minimize the heatsinks. However, the system
lifetime is limited by these fans. Thus, in this paper, the cooling system is designed on the assumptionthat the natural cooling is applied.

C. Buck type active buffer circuit
Fig. 6 shows a circuit configuration of anactive buffer circuit. Because the buffer
capacitor voltage is lower than the DC-link
voltage, this circuit is classified as a buck typeactive buffer. The buck type active buffer canalso be designed through the flowchart in Fig. 5.
The buffer capacitor is designed by (5).
However, the DC-link voltage limits the peakvoltage of the buffer capacitor. As a result, thebuffer capacitance is larger than the one of theboost type active buffer.
The inductance of the smoothing inductor
reaches the maximum value when the capacitor
voltage is a half of the input voltage. Thus, theinductance is designed byVin
Lbuf =(15),
4 Δi L f sw
where, iL is the smoothing inductor current
which is provided by
dvPi L = Cbuf c = out sin (2ω out t )(16).
dt Vave
The volume of the smoothing inductor isestimated by Area Product of (7). The loss
generated by the switching devices is calculated
by substituting (16) to (10), (11) and (12).

Fig. 6. DC to single-phase AC converter with buck typeactive buffer circuit.
0.800

0.600

0.400

0.200

0.000
0.00

20.00

40.00

60.00

80.00

100.00120.00Fig. 7. Relationship between capacitor volume andcapacitance.

III. Efficiency and Power Density Evaluation
A. Comparison of Pareto-front for buffer circuit
In the passive topology circuit, the electrolytic capacitor connected to the DC-link is selected basedon (2). The allowable ripple current becomes 18.7 A on the assumption that K100Hz=1.0 and Ksw=1.4.
Thus, the electrolytic capacitor, which has the allowable ripple current larger than 18.7 A, is selected.
When the rating voltage of the electrolytic capacitor is fixed, the volume of the electrolytic capacitor
becomes smaller by connecting the capacitors with small allowable ripple current in parallel [16]. In thispaper, 28 electrolytic capacitors, which have the allowable ripple current of 1 A per one capacitor, areconnected in parallel with a ripple current margin of 50%. As a result, the total capacitance is 5040 μF.
Fig. 7 shows a relationship between the capacitance and the total volume when the ceramic capacitors
are connected in parallel. In the active buffer, the ceramic capacitor is used as the buffer capacitor interm of the high energy density. The DC bias characteristic, which is the decrease in the capacitance ofthe ceramic capacitor by DC bias, has been considered in Fig. 7. Comparing to the electrolytic capacitor,
the ceramic capacitor has the higher ratio between the allowable ripple current and the capacitance.
Therefore, when the requirement of the capacitance for the power decoupling is satisfied, the allowable
ripple current is sufficient for the ceramic capacitor. Specifically, when the average voltage Vave and thevoltage amplitude ΔVc are 600 V and 200 V respectively, the capacitance Cbuf is 79.6 μF. The volumesof capacitors of GRM series and KC series (Murata Manufacturing Co., Ltd.) are 0.23 dm3 and 0.44 dm3
respectively in the total capacitance of 79.6 μF. However, the required numbers of the ceramic capacitor
are 1136 and 13440 respectively, which are not realistic. On the other hand, when a ceramic capacitorof the EVS series (Murata Manufacturing Co., Ltd.) is applied, the total volume and the required number
are 0.11 dm3 and 45 in 79.6 μF. Therefore, the EVS series capacitor (Murata Manufacturing Co., Ltd.)is used in this paper.
Table II shows the selected components. Fig. 8 shows the pareto-front of the power density ρpower andthe efficiency η with the switching frequency fsw as a variable. The power density is calculated by (17)from the total volume of (18). The efficiency η is provided by (19).

Pout
(17),
Voltotal
Vol total = Vol Lbuf + Vol Cbuf + Vol sw + Vol heatsinkρ power =Table II. Selected components.
Circuit
Passive
buffer

(18),

η=

Pout

Pout + (Ploss + Ploss _ Cbuf + Ploss _ Cf )(19),

where, VolCbuf and Volsw are the volumes of thebuffer capacitor and the package of theswitching device. The power density reaches the
maximum value, when SiC-MOSFET is used in
the boost type active buffer at 30 kHz.
Specifically, the maximum power density of
17.0 kW/dm3 are achieved with the efficiency of
99.5%. On the other hand, the power density inthe passive topology, which is 18.8 kW/dm3andthe efficiency of 99.8%, is 1.4 times higher thanthat of the active buffer.

B. Volume comparison
Fig. 9 shows the volume ratio of components
at the maximum power density point. The
component volume is normalized with thevolume of the electrolytic capacitors as 100%.
The buffer capacitor size is reduced by 64%
compared to bulky electrolytic capacitors by theactive power decoupling. However, the volumesof the heatsink for the switching device and theboost inductor are 35% and 41% compared tothe electrolytic capacitors, respectively. By
increasing the switching frequency, the boost
inductor size can be reduced. However, thecooling system size increases due to the increaseof the switching loss. As a result, the maximum
power density of the active buffer is 90%
against the one of the passive topology.

IV. Requirements for Components

Cin
Cbuf

Boost
type
activebuffer

Cf

S1
S2

S1
Buck
S2
type
Boost
Sp
chopper Sn
Proposed S1
circuit -S4
100
100

1 kHz

Marking
Maximum rating
Nippon Chemi-Con
450 V, 1.0 Arms
EKMZ451VSN181MP30S
180 F
Murata Manufacturing
400 V
30 F
EVS20329S2G306MS09
Murata Manufacturing
450 V
1 F
KC355WD72E225MH01
ROHM
1200 V
SiC-MOSFET, SCH2080KE
40 A
Fuji Electric
1200 V
IGBT, FGW30N120HD
30 A
Fuji Electric
600 V(2 series
Si-MOSFET, FMH30N60S1 connection),30 A
ROHM
650 V
SiC-MOSFET, SCT2120AF
29 A
ROHM
650 V
SiC-MOSFET, SCT120AF
29 A
CREE
1200 V
60 A
SiC-MOSFET,C2M0025120D
fsw increases.

SiC-MOSFET
30 kHz

99.5
99.5

98.5
98.5

98
98

Passive

Si-MOSFET
20 kHzIGBT 15 kHz
SiC-MOSFET 20 kHz

99
99

Boost type active buffer
Buck type active buffer
00

5
5000

10
15
10000
15000
Power density [kW/dm3]

20
20000

Fig. 8. Pareto-front of passive and active buffer circuit.
120
120

Electrolytic capacitor
Filter capacitor

100
100

Switching device

80

80

Heatsink

60

60

Boost inductor

40

40

20

20

0

Buffer capacitor

0

C. Loss comparison
Fig. 10 shows the power loss ratio at the
maximum power density point. The loss causedby the boost inductor is ignored. The loss isnormalized with the loss of the passive
topology. In the passive topology, theconduction loss, which is caused by theequivalent series resistance (ESR) of theelectrolytic capacitors, is considered. The power
loss of the active buffer is 135% in comparison
with the one of the passive topology.

Part

従来
Passive
topology

SiC-MOSFET
Boost typeactive buffer
SiC-MOSFET

Fig. 9. Volume distribution (fsw=30 kHz).
140
120
100
80
60
40
20
0
従来

SiC-MOSFET

Fig. 10. Loss distribution (fsw=30 kHz).
The requirements for the power decoupling
components in the active buffer to surpass the passive topology in term of the efficiency and the power
density are discussed.
From Fig. 9, the total volume of the active buffer should be reduced to 90% of that of the present
products. Thus, the ceramic capacitor, whose the capacitance per unit volume is 1.4 times higher thanthe present products, is required. Otherwise, the ceramic capacitor, which has the high rated voltage assame as the film capacitor with the rated voltage of 630 V, can reduce the series numbers of 3 to 2. As
a result, the total volume reduces by 33%. On the other hand, the boost inductor size should be reduced
by improving the circuit topology. For example, by sharing the boost inductor with a boost chopper ora single-phase inverter, the additional inductor for the power decoupling can be omitted. Finally, a power
decoupling topology of the boost type, which can reduce the inductor volumes less than 90%, is required.
From Fig. 10, a switching device, which can reduce the total loss to 74% of the present products, isrequired. In particular, the on resistance and the switching loss are less than 92 mΩ and 166 μJ,
respectively, under the condition of 1200 V rating voltage and 40 A rating current at 140 ˚C. On theother hand, as an example of the improving method for circuit topologies, the switches for the buffer
capacitor voltage control are shared with a boost chopper.

V. Proposed Boost-Type Active-Buffer Circuit Operated in DCM
A. Circuit configuration and design
Fig. 11 shows a DC-DC converter which integrates a power decoupling capability. This circuit
requires no additional inductor for the power decoupling circuit. When the boost chopper operates in
the continuous current mode (CCM), the discharge mode for the buffer capacitor cannot be realized
because the direction of the current cannot be changed suddenly in CCM. Thus, this paper came up with
the idea that the charge and discharge modes are realized by the discontinuous current mode (DCM). In
particular, the zero-current period is utilized for the operation of power decoupling. By using the zerocurrent period, the DC-link voltage and the buffer voltage are controlled by only one boost inductor.
Fig. 12 shows inductor current waveform in the DCM active power decoupling circuit. The average
current of the boost inductor is the sum of the average current for the DC-link voltage control iL_ave_dc
and the buffer capacitor voltage control iL_ave_buf.
(20),
i L _ ave = i L _ ave _ dc + i L _ ave _ buf
where, iL_ave_dc is given by
i
P
(21),
iL _ ave _ dc = peak _ dc (d1 + d 2 ) = out {1 − cos (2ωout t )}2
Vinwhere, d1 and d2 are the on duties of S1 and S3. Thus, the input average current without the power
decoupling oscillates at twice the grid frequency. In order that the average current becomes constantvalue, iL_ave_buf is given byi peak _ buf(22),(d 3 + d 4 ) = Pout cos (2ω out t )iL _ ave _ buf =2
Vinwhere, d3 and d4 are the on duties of S1 and S2 for the buffer capacitor voltage control.
On the other hand, the conduction loss is calculated from (11) and duties d1~d4. From Fig. 8, theswitching loss of a turn-off caused by switching devices are calculated byeoff
1 Tout(23),
Psw _ off _ dc =f sw
Vdc i peak _ dc dt
E dcd I md
Tout 0eoff
1 Tout(24),
Psw _ off _ buf =f sw
vc i peak _ buf dt
E dcd I md
Tout 0where, ipeak_dc and ipeak_buf are current peaks of the boost inductor for the DC-link voltage control and thebuffer capacitor voltage control, respectively.
When the switch S1 and S2 are turned on, the recovery loss in the free-wheeling diode (FWD) does
not occur because the FWD is turned off naturally in DCM. However, the turn-on losses are caused by
the discharge of the parasitic capacitor, and are calculated by3
Psw _ on _ S 1 = CdsVin2 f sw
(25),
4
1
2
Psw _ on _ S 2 = Cds (vc − Vin ) f sw
(26),
4
where, Cds is the capacitance between the drain and the source of the switching device.
In order to avoid an interference between the voltage controls, in Fig. 12, the total of the duties is
d1 + d 2 + d 3 + d 4 ≤ 1(27).

When (27) is equal to 1, this circuit operates in
the critical current mode. In the criticalcondition, the current ripple of the boost
inductor becomes the minimum, which leads tothe minimum of the conduction loss. Thus, inthis paper, the inductance of the boost inductor
is designed based on the critical condition at the
rated power, and is calculated by
Vin2 (α di − 1)
Lboost =
2


−
α
α
1
bd
di

4 f sw Pout α di 1 +Fig. 11. DCM active-power-decoupling circuit.

2 α diα bd − 1 (28),
where, αbd is the boost ratio of the averagevoltage of the buffer capacitor to the DC-link
voltage, and αdi is the boost ratio of the DC-link
voltage to the input voltage.
Fig. 13 presents the operation waveforms
when a prototype of 600 W is operated. The
boost inductor current oscillates at twice thegrid frequency when the power decoupling is
not applied. On the other hand, the buffer
capacitor voltage with the power decoupling
control is oscillated at twice the grid frequency.
As a result, the single-phase power ripple can becompensated by the active power decoupling,which is confirmed by the significant ripple
reduction in the boost inductor current.
Fig. 14 shows the enlarged operation
waveforms with the power decoupling control.
The realization of the charge and the discharge
modes for the buffer capacitor by DCM isconfirmed.
Fig. 12. Boost inductor current waveform in DCM
active-power-decoupling circuit.
Fig. 15 shows the harmonics analysis resultof the boost inductor current. When the power
decoupling is applied, the second order harmonic component is reduced by 78.3% compared to thatwithout power decoupling. Thus, the compensation of the single-phase power fluctuation is confirmed.

B. Comparison of Pareto-front of DC-DC converter with power decoupling capability
Fig. 16 shows the pareto-front of ρpower and η with fsw as variable. In Fig. 16, the volume of thepassive topology, the boost type and the buck type active buffer circuit includes the volume of theboost chopper components. The maximum power density of the boost chopper with the passive buffer
is 4.1 kW/dm3 with the efficiency of 98.9% at the switching frequency of 30 kHz. On the other hand,the power density of the DCM active-power-decoupling circuit reaches the maximum value, when theswitching frequency is 25 kHz. Specifically, the maximum power density of 4.6 kW/dm3 is achieved
with the efficiency of 98.3%, and is 1.1 times higher than the power density of the passive topology.

C. Volume and loss analysis of DC-DC converter with power decoupling capability
Fig. 17 shows the volume distribution of components at the maximum power density point. The
component volume is normalized with the volume of the passive topology as 100%. The volume of theboost inductor of the DCM active-power-decoupling circuit is 63% of that of the boost chopper. As aresult, the total volume of the DCM active power decoupling circuit is 91% against that of the passive
topology.
Fig. 18 shows the power loss distribution at the maximum power density point. The total loss of the
DCM active-power-decoupling circuit is 154% in comparison with that of the passive topology. Notethat the loss caused by the boost inductor is ignored. In order that the efficiency of the DCM active-

power-decoupling circuit surpasses the one of passive topology, a switching device, which can reduce
the total loss to 65% of the present products, is required. In particular, the on resistance and the turnoff loss are less than 26 mΩ and 234 μJ, respectively, under the condition of 1200 V rating voltage
and 40 A rating current at 140 ˚C of the junction temperature.

Fig. 13. Operation waveforms.
Boost inductor current iL [20A/div]
0

0
0
0

Boost inductor current with low pass filter [2A/div]
DC-link voltage vdc [100V/div]
Output current [5 A/div][10 s/div](a) Buffer capacitor in charge mode.
Fig. 14. Enlarged operation waveforms with power decoupling control.

Fig. 15. Harmonics analysis on boost inductor current.

Fig. 17. Volume distribution of DC-DC converter.

Fig. 16. Pareto-front of DC-DC converter withpower decoupling capability.

Fig. 18. Loss distribution of DC-DC converter.

V. Conclusion
This paper discussed how to achieve high power density with high efficiency for single-phase inverterwith active power decoupling circuit. Based on the Pareto optimization of power density and efficiency,
the maximum power density points of the power decoupling circuits are clarified. The problems of theconventional boost type active buffer are following; The maximum power density is 90% of that of the passive topology which uses electrolytic
capacitors.
 The power loss caused by switching devices is 135% of that of the passive topology.
As a result, the circuit topology of the active power decoupling which can reduce the total component
volume less than 90%, especially the boost inductor volume, is required. Thus, this paper proposed a
new DC-DC converter which uses discontinuous current mode for the power decoupling capability. The
features of the proposed circuit are following; The proposed circuit requires no additional inductor for the power decoupling circuit.
 The maximum power density is 1.1 times higher than that of the passive topology.
 The power loss caused by switching devices is 1.5 times higher than that of the passive topology.
As a result, in order to surpass the efficiency of the passive topology by active power decoupling, theswitching device is required to reduce the total loss by 35% compared to the present products.
In future work, the power density and the efficiency of the proposed circuit are evaluated byexperiments in 6 kW.

References[1] Y. Hirase, O. Noro, E. Yoshimura, H. Nakagawa, K. Sakimoto : "Virtual Synchronous Generator Control with
Double Decoupled Synchronous Reference Frame for Single-Phase Inverter", IEEJ Journal of Industry
Applications, Vol. 4, No. 3, pp. 143-151 (2015)[2] R. Chattopadhyay, S. Bhattacharya, N. C. Foureaux, I. A. Pires, H. de Paula, S. M. Silva, B. C. Filho, J. A. de
S. Brito : "Low-Voltage PV Power Integration into Medium Voltage Grid Using High-Voltage SiC Devices", IEEJ
Journal of Industry Applications, Vol. 4, No. 6, pp. 767-775 (2015)[3] A. Tokumasu, K. Shirakawa, H. Taki, K. Wada : "AC/DC Converter Based on Instantaneous Power BalanceControl for Reducing DC-Link Capacitance",IEEJ Journal of Industry Applications,Vol.4,No.6,pp.745-751 (2015)[4] M. Matsui, T. Sai, B. G. Yu, X. D. Sun : "A New Distributed MPPT Technique using Buck-only MICs Linked
with Controlled String Current", IEEJ Journal of Industry Applications, Vol. 4, No. 6, pp. 674-680 (2015)[5] H. Hu, S. Harb, X. Fang, D. Zhang, Q. Zhang : "A Three-port Flyback for PV Microinverter Applications With
Power Pulsation Decoupling Capability", IEEE. Trans, Vol. 27, No. 9, pp. 3953-3964 (2012)[6] H. Hu, S. Harb, N. Kutkut, I. Batarseh, Z. J. Shen : “Power Decoupling Techniques for Micro-inverters in PV
Systems — a Review,” Energy Conversion Congress and Exposition 2010, pp.3235-3240, pp. 12-16 (2010)[7] S. Yamaguchi, T. Shimizu : "Single-phase Power Conditioner with a Buck-boost-type Power Decoupling
Circuit", IEEJ Journal of Industry Applications, Vol. 5, No. 3, pp. 191-198 (2016)[8] Chia-Tse Lee, Yen-Ming Chen, Li-Chung Chen, Po-Tai Cheng : “Efficiency Improvement of a DC/AC
Converter with the Power Decoupling Capability”, IEEE APEC 2012, pp. 1462-1468 (2012)[9] Yi Tang, Frede Blaabjerg, Poh Chiang Loh, Chi Jin, Peng Wang : "Decoupling of Fluctuating Power in SinglePhase Systems Through a Symmetrical Half-Bridge Circuit", IEEE Trans., Vol. 30, No. 4, pp. 1855-1865 (2015)[10] K. H. Chao, P. T. Cheng, T. Shimizu : "New Control Methods for Single Phase PWM Regenerative Rectifier
with Power Decoupling", IEEJ PEDS, Vol. , No. , pp. 1091-1096 (2009)[11] S. Qin, Y. Lei, C. Barth, W. Liu, R. C. N. Pilawa-Podgurski : “A High-Efficiency High Energy Density Buffer
Architecture for Power Pulsation Decoupling in Grid-Interfaced Converters”, IEEE ECCE 2015, pp.149-157(2015)[12] D. Neumayr, D. Bortis, J. W. Kolar : "Ultra-Compact Power Pulsation Buffer for Single-phase DC/AC
Converter Systems", ECCE Asia, No. Wa1-06 (2016)[13] Y. Kashihara, J. Itoh : “Parameter design of a Five-Level Inverter for PV systems”, ICPE 2011 - ECCE Asia,
No. ThB3-2, pp. 1886-1893 (2011)[14] Wm. T. Mclyman : “Transformer and inductor design handbook”, Marcel Dekker Inc., (2004)[15] U. Drofenik, G. Laimer and J. W. Kolar : ”Theoretical Converter Power Density Limits for Forced Convection
Cooling”, Proceedings of the International PCIM Europe Conference, pp. 608-619 (2005)[16] T. Nakanishi and J. Itoh, “Capacitor volume evaluation based on ripple current in Modular Multilevel
Converter”, International Conference on Power Electronics, No. 09, pp. 815-822(2015)