PRELIMINARY SPECIFICATION
1/5" color CMOS QSXGA (3 megapixel) image sensor
with OmniBSI™ technology

OV3660

datasheetOV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

00Copyright © 2011 OmniVision Technologies, Inc. All rights reserved.
This document is provided “as is” with no warranties whatsoever, including any warranty of merchantability,
non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification,or sample.
OmniVision Technologies, Inc. and all its affiliates disclaim all liability, including liability for infringement of any proprietary
rights, relating to the use of information in this document. No license, expressed or implied, by estoppel or otherwise, toany intellectual property rights is granted herein.
The information contained in this document is considered proprietary to OmniVision Technologies, Inc. and all its
affiliates. This information may be distributed to individuals or organizations authorized by OmniVision Technologies, Inc.
to receive said information. Individuals and/or organizations are not allowed to re-distribute said information.

Trademark Information
OmniVision and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. OmniBSI is atrademark of OmniVision Technologies, Inc.
All other trademarks used herein are the property of their respective owners.

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology
datasheet (CSP3)
PRELIMINARY SPECIFICATION
version 1.3
may 2011

To learn more about OmniVision Technologies, visit www.ovt.com.
OmniVision Technologies is publicly traded on NASDAQ under the symbol OVTI.

i00applications

ordering information

cellular phones

OV03660-A51A (color, lead-free)
51-pin CSP3

toys
PC multimedia
digital still cameras

00features
1.4 µm x 1.4 µm pixel with OmniBSI technology forhigh performance (high sensitivity, low crosstalk, low
noise, improved quantum efficiency)
optical size of 1/5"
automatic image control functions: automatic
exposure control (AEC), automatic white balance(AWB), automatic flicker detection, and automatic
black level calibration (ABLC)
programmable controls for frame rate, AEC/AGC
16-zone size/position/weight control, mirror and flip,
cropping, windowing, and panning
image quality controls: color saturation, hue, gamma,
sharpness (edge enhancement), lens correction,
defective pixel canceling, and noise cancelingsupport for output formats: RAW RGB,
RGB565/555/444, CCIR656, YCbCr422, andcompression

support for horizontal and vertical sub-sampling,binning
support 2x2 binning with binning filter to minimize
binning artifacts
support for data compression output
standard serial SCCB interface (see section 2.10 for
details)
digital video port (DVP) parallel output interface
embedded 1.5V regulator for core power
programmable I/O drive capability, I/O tri-state
configurability
support for black sun cancellation
support for images sizes: 3 megapixel and any
arbitrary size scaling down from 3 megapixel
suitable for module size of 6.5 x 6.5 x <6mm

support for LED and flash strobe mode

00key specifications (typical)
active array size: 2048 x 1536

max S/N ratio: 34 dB

power supply:
core: 1.5V ± 5% (with embedded 1.5V regulator)
analog: 2.6 ~ 3.0V (2.8V typical)
I/O: 1.8V / 2.8V (1.8V recommended)

dynamic range: 70 dB @ 8x gain

power requirements:
active: 98 mA
standby: 20 µA
temperature range:
operating: -20°C to 70°C junction temperature(see table 8-2)
stable image: 0°C to 50°C junction temperature(see table 8-2)
output formats: 8-/10-bit RAW, RGB and YCbCr
output, compression

maximum image transfer rate:
2048x1536: 15 fps
1080p: 20 fps
720p: 45 fps
XGA (1024x768): 45 fps
VGA (640x480): 60 fps
QVGA (320x240): 120 fps
sensitivity: 670 mV/Lux-sec
shutter: rolling shutter
maximum exposure interval: 1560 x tROW
pixel size: 1.4 µm x 1.4 µm
dark current: TBD

lens size: 1/5"

image area: 2912 µm x 2167.2 µm

lens chief ray angle: 27.6° (see figure 10-2)

package dimensions: 5010 µm x 4960 µm

input clock frequency: 6~27 MHz

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

note pixel
performance shown are
target values. These
values are subject tochange based on realmeasurements.

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

iii

00table of contents
1 signal descriptions

1-1

2 system level description

2-1

2.1 overview

2-1

2.2 architecture

2-1

2.3 pixel array structure

2-4

2.3.1 binning

2-5

2.4 power up sequence

2-5

2.4.1 power up with internal DVDD

2-6

2.4.2 power up with external DVDD source

2-7

2.5 reset

2-8

2.5.1 power ON reset generation

2-8

2.6 hardware and software standby

2-8

2.6.1 hardware standby

2-8

2.6.2 software standby

2-8

2.7 format and frame rate

2-9

2.7.1 output format control

2-9

2.8 I/O control

2-14

2.9 system control

2-16

2.9.1 system clock control

2-19

2.10 group write

2-22

3 image sensor core digital functions

3-1

3.1 mirror and flip

3-1

3.2 image windowing and scaling

3-2

3.2.1 image windowing

3-2

3.2.2 scaling

3-4

3.3 test pattern

3-7

3.4 exposure / gain control

3-8

3.4.1 overview

3-8

3.4.2 automatic exposure/gain control

3-8

3.4.3 50Hz/60Hz detection

3-12

3.4.4 anti-flicker

3-12

3.4.5 extending the exposure time under dark conditions

3-13

3.4.6 sub-row exposure time under extremely bright conditions

3-14

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

3.5 black level calibration (BLC)

3-15

3.6 strobe flash

3-16

3.6.1 strobe flash control

3-16

3.7 one time programmable (OTP) memory

3-19

3.7.1 OTP write sequence

3-19

3.7.2 OTP read sequence

3-19

3.8 temperature sensor

3-21

4 image sensor processor digital functions

5-1

4.1 ISP general controls

5-1

4.2 lens correction (LENC)

5-4

4.3 white balance

5-6

4.3.1 simple AWB

5-6

4.3.2 advanced AWB

5-6

4.3.3 AWB stable range and gain range

5-11

4.4 gamma

5-12

4.5 defect pixel cancellation (DPC)

5-14

4.6 sharpness control and de-noise

5-14

4.7 color matrix (CMX)

5-18

4.8 auto color saturation adjust

5-19

4.8.1 manual mode

5-19

4.8.2 auto mode

5-20

4.9 special digital effects (SDE)

5-21

5 image sensor output interface digital functions
5.1 compression engine

6-1
6-1

5.1.1 compression mode 1 timing

6-1

5.1.2 compression mode 2 timing

6-1

5.1.3 compression mode 3 timing

6-2

5.1.4 compression mode 4 timing

6-2

5.1.5 compression mode 5 timing

6-3

5.1.6 compression mode 6 timing

6-3

5.1.7 compression mode control

6-4

5.2 parallel digital video port (DVP)

6-6

5.2.1 overview

6-6

5.2.2 DVP timing

6-9

6 serial camera control bus (SCCB) interface

7-1

6.1 data transfer protocol

proprietary to OmniVision Technologies

7-1

PRELIMINARY SPECIFICATION

version 1.3

v

6.2 message format

7-1

6.3 read / write operation

7-1

6.4 SCCB timing

7-4

7 register tables

8-1

7.1 system and IO pad control [0x3000 ~ 0x3052]

8-1

7.2 SCCB control [0x3100 ~ 0x3108]

8-4

7.3 SRB control [0x3200 ~ 0x3213]

8-5

7.4 AWB gain control [0x3400 ~ 0x3406]

8-5

7.5 AEC/AGC control [0x3500 ~ 0x3513]

8-6

7.6 ANA control registers [0x3600 ~ 0x3634]

8-7

7.7 sensor control [0x3700 ~ 0x373C]

8-8

7.8 timing control [0x3800 ~ 0x3836]

8-8

7.9 AEC/AGC power down domain control [0x3A00 ~ 0x3A25]

8-10

7.10 strobe control [0x3B00]

8-13

7.11 sigmadelta/5060Hz detector [0x3C00 ~ 0x3C1E]

8-13

7.12 OTP control [0x3D00 ~ 0x3D21]

8-15

7.13 BLC control [0x4000 ~ 0x4033]

8-16

7.14 frame control [0x4201 ~ 0x4202]

8-18

7.15 format control [0x4300 ~ 0x430D]

8-19

7.16 compression control [0x4400 ~ 0x4458]

8-23

7.17 VFIFO control [0x4600 ~ 0x460D]

8-26

7.18 DVP control [0x4709 ~ 0x4745]

8-27

7.19 ISP frame control [0x4901 ~ 0x4902]

8-30

7.20 ISP top control [0x5000 ~ 0x5063]

8-30

7.21 AWB control [0x5180 ~ 0x51D0]

8-33

7.22 CIP control [0x5300 ~ 0x530F]

8-35

7.23 CMX control [0x5380 ~ 0x538B]

8-36

7.24 gamma control [0x5480 ~ 0x5490]

8-37

7.25 SDE control [0x5580 ~ 0x558C]

8-38

7.26 scale control [0x5600 ~ 0x5606]

8-40

7.27 average control [0x5680 ~ 0x56A2]

8-41

7.28 DPC control [0x5780 ~ 0x5794]

8-43

7.29 LENC control [0x5800 ~ 0x5849]

8-44

7.30 temperature sensor control [0x6700 ~ 0x6721]

8-49

8 operating specifications

05.13.2011

PRELIMINARY SPECIFICATION

9-1

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

8.1 absolute maximum ratings

9-1

8.2 functional temperature

9-1

8.3 DC characteristics

9-2

8.4 timing characteristics

9-4

9 mechanical specifications

10-1

9.1 physical specifications

10-1

9.2 IR reflow specifications

10-2

10 optical specifications

11-1

10.1 sensor array center

11-1

10.2 lens chief ray angle (CRA)

11-2

10.3 spectrum response

11-3

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PRELIMINARY SPECIFICATION

version 1.3

vii

00list of figures
figure 1-1

pin diagram

1-4

figure 2-1

OV3660 block diagram

2-2

figure 2-2

reference design schematic

2-3

figure 2-3

sensor array region color filter layout

2-4

figure 2-4

example of 2x2 binning

2-5

figure 2-5

power up timing with internal DVDD

2-6

figure 2-6

power up timing with external DVDD source

2-7

figure 2-7

PLL block diagram

2-20

figure 3-1

mirror and flip samples

3-1

figure 3-2

image windowing

3-2

figure 3-3

image windowing configuration

3-3

figure 3-4

scaling function

3-4

figure 3-5

test pattern

3-7

figure 3-6

average-based window definition

3-9

figure 3-7

xenon flash mode

3-16

figure 3-8

LED 1 & 2 mode - one pulse output

3-17

figure 3-9

LED 1 & 2 mode - multiple pulse output

3-17

figure 3-10

LED 3 mode

3-18

figure 4-1

control points of luminance and color channels

5-4

figure 4-2

luminance compensation level calculation

5-4

figure 4-3

gamma curve

5-12

figure 4-4

auto color saturation adjust graph

5-20

figure 5-1

compression mode 1 timing

6-1

figure 5-2

compression mode 2 timing

6-1

figure 5-3

compression mode 3 timing

6-2

figure 5-4

compression mode 4 timing

6-2

figure 5-5compression mode 5 timing

6-3

figure 5-6

compression mode 6 timing

6-3

figure 5-7

DVP frame timing diagram

6-9

figure 6-1

message type

7-1

figure 6-2

SCCB single read from random location

7-2

figure 6-3

SCCB single read from current location

7-2

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

figure 6-4

SCCB sequential read from random location

7-2

figure 6-5

SCCB sequential read from current location

7-3

figure 6-6

SCCB single write to random location

7-3

figure 6-7

SCCB sequential write to random location

7-3

figure 6-8

SCCB interface timing

7-4

figure 9-1

package specifications

10-1

figure 9-2

IR reflow ramp rate requirements

10-2

figure 10-1

sensor array center

11-1

figure 10-2

chief ray angle (CRA)

11-2

figure 10-3

spectrum response graph11-3

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

ix

00list of tables
table 1-1 signal descriptions

1-1

table 1-2 configuration under various conditions

1-3

table 1-3 pad symbol and equivalent circuit

1-5

table 2-1 binning-related registers

2-5

table 2-2 format and frame rate

2-9table 2-3 output format control registers

2-9table 2-4 format control registers

2-10

table 2-5 driving capability and direction control for I/O pads

2-14table 2-6 system control registers

2-16

table 2-7 PCLK divider ratio

2-19

table 2-8 PLL configurations

2-20

table 2-9 PLL control registers

2-21

table 2-10 group write registers

2-22

table 3-1 mirror and flip registers

3-1

table 3-2 image windowing registers

3-3

table 3-3 scaling control registers

3-5

table 3-4 test pattern selection control

3-7table 3-5 timing control functions

3-9

table 3-6 night mode control registers

3-14

table 3-7 BLC control functions

3-15

table 3-8 flashlight modes

3-16

table 3-9

strobe control functions

3-18

table 3-10 OTP control functions

3-20

table 3-11 temperature sensor function

3-21

table 4-1 ISP general control registers

5-1

table 4-2 LENC control registers

5-5table 4-3 white balance registers

5-6

table 4-4 AWB calibration registers

5-7

table 4-5 AWB control

5-9table 4-6 AWB stable range registers

5-11

table 4-7 gamma parameters and corresponding registers

5-12

table 4-8 gamma control registers

5-13

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 4-9 DPC control registers

5-14

table 4-10 sharpness and de-noise control registers

5-17

table 4-11 CMX control registers

5-19

table 4-12 SDE image effects

5-21

table 4-13 image contrast/brightness/saturation/hue control

5-23

table 4-14 SDE control registers

5-24

table 5-1 compression control registers

6-4

table 5-2 parallel DVP control registers

6-6

table 5-3 DVP timing specifications

6-9

table 6-1 SCCB interface timing specifications

7-4

table 7-1 system and IO pad control registers

8-1

table 7-2 SCCB control registers

8-4

table 7-3 SRB control registers

8-5

table 7-4 AWB gain control registers

8-5

table 7-5 AEC/AGC control functions

8-6

table 7-6 ANA control registers

8-7

table 7-7 sensor control registers

8-8table 7-8 timing control registers

8-8table 7-9

AEC/AGC power down domain control registers

8-10

table 7-10

strobe registers

8-13

table 7-11

sigmadelta/5060HZ detector registers

8-13

table 7-12 OTP control functions

8-15

table 7-13 BLC registers

8-16

table 7-14 frame control registers

8-18

table 7-15 format control registers

8-19

table 7-16 compression control registers

8-23

table 7-17 VFIFO registers

8-26

table 7-18 DVP control registers

8-27

table 7-19 ISP frame control registers

8-30

table 7-20 ISP top control registers

8-30

table 7-21 AWB registers

8-33

table 7-22 CIP control registers

8-35

table 7-23 CMX control registers

8-36

table 7-24 gamma control registers

8-37

table 7-25 SDE control registers

8-38

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

xi

table 7-26 scale control registers

8-40

table 7-27 AVG registers

8-41

table 7-28 DPC control registers

8-43

table 7-29 LENC control registers

8-44

table 7-30 TPM control registers

8-49

table 8-1 absolute maximum ratings

9-1

table 8-2 functional temperature

9-1

table 8-3 DC characteristics (-20°C < TJ < 70°C)

9-2

table 8-4 timing characteristics

9-4

table 9-1 package dimensions

10-1

table 9-2 reflow conditions

10-2

table 10-1 CRA versus image height plot

11-2

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

1-1

1 signal descriptions
table 1-1 lists the signal descriptions and their corresponding pin numbers for the OV3660 image sensor. The package
information is shown in section 9.

table 1-1

signal descriptions (sheet 1 of 2)

pinnumbersignal name

pin
type

description

A1

DVDD

power

power for digital circuit

A2

DOGND

groundground for digital circuit

A3

NC

–

no connect

A4

NC

–

no connect

A5

NC

–

no connect

A6

NC

–

no connect

A7

VNH

reference

internal analog reference

A8

VH

reference

internal analog reference

B1

HREF

I/O

video output horizontal sync signal

B2

XVCLK

input

system input clock/scan clock input

B3

DOVDD

power

power for I/O circuit

B6

VNL

reference

internal analog reference

B7

AGND

groundground for analog circuit

B8

AGND

groundground for analog circuit

C1

D8

I/O

image data output 8

C2

D9

I/O

image data output 9

C3

NC

–

no connect

C6

RESETB

input

reset (active low with internal pull up resistor)

C7

AVDD

power

power for analog circuit

C8

AVDD

power

power for analog circuit

D1

D6

I/O

image data output 6

D2

D7

I/O

image data output 7

D3

DOGND

groundground for digital circuit

D6

DOGND

groundground for digital circuit

D7

DOGND

groundground for digital circuit

D8

DOGND

groundground for digital circuit

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 1-1

signal descriptions (sheet 2 of 2)

pinnumbersignal name

pin
type

description

E1

DVDD

power

power for digital circuit

E2

D5

I/O

image data output 5

E3

FSIN

I/O

frame sync

E6

DOVDD

power

power for I/O circuit

E7

DOVDD

power

power for I/O circuit

E8

DOVDD

power

power for I/O circuit

F1

PCLK

I/O

image output clock

F2

D4

I/O

image data output 4

F3

DOVDD

power

power for I/O circuit

F6

PWDN

input

power down (active high with pull down resistor)

F7

DVDD

power

power for digital circuit

F8

DVDD

power

power for digital circuit

G1

D2

I/O

image data output 2

G2

D3

I/O

image data output 3

G3

DVDD

power

power for digital circuit

G6

STROBE

I/O

LED/flash control

G7

TM

input

test mode (active high with pull down resistor)

G8

VSYNC

I/O

video output vertical sync signal

H1

D0

I/O

image data output 0

H2

D1

I/O

image data output 1

H3

DOGND

groundground for digital circuit

H4

NC

–

no connect

H6

NC

–

no connect

H7

SIOC

input

SCCB input clock

H8

SIOD

I/O

SCCB data

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

1-3

table 1-2

configuration under various conditions
after RESET
releasesoftwarestandbyhardware standby(PWDNB = 0)

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

XVCLK

input

input

input

high-zC1

D8high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

C2

D9

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

C6

RESETB

input

input

input

input

D1

D6

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

D2

D7

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

E2

D5

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

E3

FSIN

input

input by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

F1

PCLK

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

F2

D4

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

F6

PWDN

input

input

input

input

G1

D2

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

G2

D3

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

G6

STROBE

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

G7

TM

input

input

input

input

G8

VSYNC

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

H1

D0

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

H2

D1

high-zhigh-z by default(configurable)

high-z by default(configurable)

high-z by default(configurable)

H7

SIOC

input

input

input

high-z

H8

SIOD

input

input

input

high-zpin

signal name

RESET

B1

HREF

B2

05.13.2011

PRELIMINARY SPECIFICATION

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

figure 1-1

pin diagram

A1

A2

A3

A4

A5

A6

A7

A8

DVDD

DOGND

NC

NC

NC

NC

VNH

VH

B1

B2

B3

B6

B7

B8

HREF

XVCLK

DOVDD

VNL

AGND

AGND

C1

C2

C3

C6

C7

C8

D8

D9

NC

RESETB

AVDD

AVDD

D1

D2

D3

D6

D7

D8

D6

D7

DOGND

DOGND

DOGND

DOGND

E1

E2

E3

E6

E7

E8

DVDD

D5

FSIN

DOVDD

DOVDD

DOVDD

F1

F2

F3

F6

F7

F8

PCLK

D4

DOVDD

PWDN

DVDD

DVDD

G1

G2

G3

G6

G7

G8

D2

D3

DVDD

STROBE

TM

VSYNC

H1

H2

H3

H4

H6

H7

H8

D0

D1

DOGND

NC

NC

SIOC

SIOD

OV36603660_CSP_DS_1_1

top view

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

1-5

table 1-3

pad symbol and equivalent circuit

symbolequivalent circuit
PAD

XVCLK
DOGND

EN

to corePADfrom core

SIOD

PD

DOGND
open-drain

PAD

SIOC

PD
DOGND

DOVDD
DOUT

D9, D8, D7, D6, D5, D4, D3, D2,
D1, D0, VSYNC, STROBE, FSIN

PAD
EN

DIN
DOGND

PD

PAD

AGND, DOGND, DGND
DOGND

PAD

AVDD, DVDD, DOVDD
DOGND

DOVDD

DOVDD

DOGND

RESETB
PAD

DOGND

PAD
DOVDD

TM, PWDN
DOGND

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

2-1

2 system level description
2.1 overview
The OV3660 (color) image sensor is a low voltage, high-performance, 1/5-inch 3 megapixel CMOS image sensor thatprovides the full functionality of a single chip 3 megapixel (2048x1536) camera using OmniBSI™ technology in a small
footprint package. It provides full-frame, sub-sampled, windowed or arbitrarily scaled 8-bit/10-bit images in various
formats via the control of the Serial Camera Control Bus (SCCB) interface.
The OV3660 has an image array capable of operating at up to 15 frames per second (fps) in 3 megapixel resolution withcomplete user control over image quality, formatting and output data transfer. All required image processing functions,
including exposure control, gamma, white balance, color saturation, hue control, defective pixel canceling, noise
canceling, etc., are programmable through the SCCB interface. The OV3660 also includes a compression engine forincreased processing power. In addition, OmniVision image sensors use proprietary sensor technology to improve image
quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise,smearing, etc., to produce a clean, fully stable, color image.
For identification and storage purposes, the OV3660 includes a one-time programmable (OTP) memory.
The OV3660 supports a digital video parallel port.

2.2 architecture
The OV3660 sensor core generates streaming pixel data at a constant frame rate, indicated by HREF and VSYNC.
figure 2-1 shows the functional block diagram of the OV3660 image sensor.
The timing generator outputs signals to access the rows of the image array, precharging and sampling the rows of thearray in series. In the time between pre-charging and sampling a row, the charge in the pixels decreases with the time
exposed to the incident light. This is known as exposure time.
The exposure time is controlled by adjusting the time interval between precharging and sampling. After the data of the
pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the datawith corresponding gain. Following analog processing is the ADC which outputs 10-bit data for each pixel in the array.

05.13.2011

PRELIMINARY SPECIFICATION

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

figure 2-1

OV3660 block diagram

OV366050/60 Hz
auto detection

DVP

10-bitADC

AMP

image output
interface

FIFO

row select

image
array

compression
engineimage sensor
processor

ISP

image sensor corecolumnsample/holdD[9:0]

gain
control

control register banktiming generator
and system control logic

PLL

SCCB interface

proprietary to OmniVision Technologies

SIOD

SIOC

VSYNC

HREF

PCLK

FSIN

STROBERESETB

PWDN

3660_DS_2_1

XVCLK

OV3660PRELIMINARY SPECIFICATION

version 1.3

2-3

figure 2-2

F6
PWDN

STROBE G6

D0

SIOC

F3

RESETB

D6

VSYNC

D7

PWDN

4
5
6
7
8

D8 DGND

HREF

E3

FSIN

FSIN

F1

PCLK

DOVDD

C2

D9

D9

C1

D8

XVCLK

D2

D7

D8

D1

D6

DGND

E2

D5

D7

F2

D4

PCLK

G2

D3

D6

G1

D2

D2

H2

D1

D5

H1

D0

D3

9
10
11
12
13
14
15
16
17
18
19
20
21

D4

22

D1

23

D0

24

note 7

note 1 PWDN should not be left floating. Please refer to power up sequence section
for more details on controlling the PWDN pin.
note 2 RESETB is mandatory during power up reset and should be connected out(please refer to section 2.9 for more details)

DVDD DOVDD

AVDD

VNL

D1

E8

3

C23 0.1μF-0201

D2

DOGND

PWDN

H3

D3

DOGND

AVDD

1
2

C25 0.1μF-0201 VNH

D3

D4

DOGND

E7

VH

DGND

D5

DVDD

SIOD

C24 0.1μF-0201

A2

D6

DVDD

XVCLK

F8

D7

DVDD

HREF

F7

D8

DVDD

B2

E1

D9

XVCLK

A1

DVDD

SIOD

G3

PCLK

OV3660CSP BSIRESETB

B1

C6

FSIN

U6

HREF

RESETB

VNL

SIOC

B6

H8

VNL

DOGND

VNH

SIOD

A7

TM

VNH

DOGND

VH

H7

A8

SIOC

VH

DOGND

AGND

VSYNC

B7

G7

DVDD

AGND

DOVDD

AGND

STROBE

B8

DOVDD

AVDD

G8

C7

DOVDD

AVDD

VSYNC

C8

E6

C28 0.1μF-0201

DOVDD

AGND

C27 0.1μF-0201

AVDD

STROBE

B3

JP2 flex cable to Molex 52437-2491

DOVDD
DOVDD

C26 0.1μF-0201

H4

C3

A6

A5

A4

H6
NC

NC

NC

NC

NC

NC

NC

A3

reference design schematicnote 3 AVDD is 2.8 V of sensor analog power (clean). During OTP programming,an AVDD voltage range of 2.5 V ±5% is required.
OTP read may use normal AVDD voltage range.
note 4 DOVDD is 1.7 ~ 3 V of sensor digital IO power (clean). 1.8 V is recommended.
note 5 DVDD is 1.5 V sensor core power (clean).
DVDD can be provided by internal regulator (recommended).
note 6 sensor AGND and DGND should be separated and connected to a single point outside module(do not connect inside module).
note 7 capacitors should be close to the related sensor pins.
note 8 if more space is available, use a capacitor of 1 μF-0402 between DVDD and DGND
note 9 D[9:0] (D9:MSB, D0:LSB) is sensor RGB raw 10-bit output
D[9:2] (D9:MSB, D2:LSB) is 8-bit output.

05.13.2011

PRELIMINARY SPECIFICATION

3660_CSP_DS_2_2

proprietary to OmniVision Technologies

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

2.3 pixel array structure
The OV3660 sensor has an image array of 2080 columns by 1548 rows (3,219,840 pixels). figure 2-3 shows across-section of the image sensor array.
The color filters are arranged in a Bayer pattern. The primary color BG/GR array is arranged in line-alternating fashion.
Of the 3,219,840 pixels, 3,145,728 (2048x1536) are active pixels and can be output. The other pixels are used for blacklevel calibration and interpolation.
The sensor array design is based on a field integration readout system with line-by-line transfer and an electronic shutter
with a synchronous pixel readout scheme.

figure 2-3

sensor array region color filter layout

2078
2079

...
B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R

2064
2065

2062
2063

0
1

...
0 B Gb B Gb B Gb
1 Gr R Gr R Gr R
2 B Gb B Gb B Gb
3 Gr R Gr R Gr R
4 B Gb B Gb B Gb
5 Gr R Gr R Gr R

16
17

14
15

columns...
B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R

dummy
line

6 B Gb B Gb B Gb
7 Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R
1540 B Gb B Gb B Gb
1541 Gr R Gr R Gr R

B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R

B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R

activeline

1542 B Gb B Gb B Gb
1543 Gr R Gr R Gr R
1544 B Gb B Gb B Gb
1545 Gr R Gr R Gr R
1546 B Gb B Gb B Gb
1547 Gr R Gr R Gr R

B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R

B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R
B Gb B Gb B Gb
Gr R Gr R Gr R

dummy
line

activecolumndummy
column...

rows

OV3660dummy
column3660_DS_2_3

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

2-5

2.3.1 binning
Binning mode is usually used for low resolution. When the binning function is ON, voltage levels of adjacent pixels areaveraged before sent to the ADC. If the binning function is OFF, the pixels, which are not output, are merely skipped.
The OV3660 supports 2x2 binning, where the voltage levels of two horizontal (2x1) adjacent same-color pixels areaveraged before entering the ADC.
figure 2-4 illustrates 2x2 binning, where the voltage levels of four (2x2) adjacent same-color pixels are averaged before
entering the ADC.

figure 2-4

example of 2x2 binning
2x2 green pixels are
2x2 blue pixels arebinned to 1 blue pixel binned to 1 green pixel
BGBG
GRGR
BGBG
GRGR

BG
GR

BGBG
GRGR
BGBG
GRGR

BG
GR

BGBG
GRGR
BGBG
GRGR

BG
GR

BGBG
GRGR
BGBG
GRGR

BG
GR

2x2 green pixels arebinned to 1 green pixel

2x2 red pixels arebinned to 1 red pixel
3660_DS_2_4

table 2-1

binning-related registers

address

register namedefault
value

R/W

description

0x3820

TIMING TC REG20

0x64

RW

Bit[0]:

Vertical binning enable

0x3821

TIMING TC REG21

0x0C

RW

Bit[0]:

Horizontal binning enable

2.4 power up sequence
Based on the system power configuration (1.8V or 2.8V for I/O power, using external DVDD or internal DVDD, the power
up sequence will differ. If 1.8V is used for I/O power, using the internal DVDD is preferred. If 2.8V is used for I/O power,
due to a high voltage drop at the internal DVDD regulator, there is a potential heat issue. Hence, for a 2.8V power system,
OmniVision recommends using an external DVDD source. Due to the higher power down current when using an external
DVDD source, OmniVision strongly recommends cutting off all powers, including the external DVDD, when the sensor
is not in use in the case of 2.8V I/O and external DVDD.

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

2.4.1 power up with internal DVDD
For powering up with the internal DVDD and I2C access during the power ON period, the following conditions must occur:1.

when DOVDD and AVDD are turned ON, make sure DOVDD becomes stable before AVDD becomes stable

2.

PWDN is active high with an asynchronized design (does not need clock)3.

PWDN must go high during the power on period

4.

for PWDN to go low, power must first become stable (AVDD to PWDNB ≥ 5 ms)

5.

RESETB is active low with an asynchronized design

6.

state of RESETB does not matter during power on period once DOVDD is up

7.

master clock XVCLK should provide at least 2 ms before host accesses the sensor’s registers

8.

host can access I2C bus (if shared) during entire period. 20 ms after PWDN goes low or 20 ms after RESETB
goes high if reset is inserted after PWDN goes low, host can access the sensor’s registers to initialize sensor

figure 2-5

power up timing with internal DVDD
power onpower off

t

0

DOVDD

AVDD

t

5
>=0ms

t

2

PWDN

RESETB

t6
t

t

1

3

t4

XVCLK
SCCB
note t ≥ 0ms, delay from DOVDD stable to AVDD stable, it is recommended to power up AVDD shortly
0
after DOVDD has been powered upt ≥ 0ms, delay from XVCLK off to AVDD off
1
t2 ≥ 5ms, delay from AVDD stable to sensor power up stable, PWDN can be pulled low after this point,XVCLK can be turned on after power on
t3 ≥ 1ms, delay from sensor power up stable to RESETB pull upt ≥ 20ms, delay from RESETB pull high to SCCB initialization
4t5 ≥ 0ms, delay from AVDD off to DOVDD off
t6 ≥ 0ms, delay from RESETB pull low to AVDD off
3660_DS_2_14

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

2-7

2.4.2 power up with external DVDD source
For powering up with an external DVDD source and I2C access during the power ON period, the following conditions
must occur:1.

when DOVDD and AVDD are turned ON, make sure DOVDD becomes stable before AVDD becomes stable2.

when AVDD and DVDD are turned ON, make sure AVDD becomes stable before DVDD becomes stable

3.

PWDN is active high with an asynchronized design (does not need clock)4.

for PWDN to go low, power must first become stable (DVDD to PWDNB ≥ 5 ms)

5.

all powers are cut off when the camera is not in use (power down mode is not recommended

6.

RESETB is active low with an asynchronized design

7.

state of RESETB does not matter during power on period once DOVDD is up

8.

master clock XVCLK should provide at least 2 ms before host accesses the sensor’s registers

9.

host can access I2C bus (if shared) during entire period. 20 ms after PWDN goes low or 20 ms after RESETB
goes high if reset is inserted after PWDN goes high, host can access the sensor’s registers to initialize sensor

figure 2-6

power up timing with external DVDD source

DOVDD first, then AVDD, followed by DVDD, and rising time is less than 5 ms
t0

cut off power

DOVDD

t6
t1

AVDD

t7

t2
DVDD
power on period

t3

t5

PWDN
RESETB

t4

XVCLK
SCCB

note t ≥ 0 ms: delay from DOVDD stable to AVDD stable, it is recommended to power up AVDD shortly after DOVDD
0
has been powered up
t1 ≥ 0 ms: delay from AVDD stable to DVDD stablet2 ≥ 5 ms: delay from DVDD stable to sensor power up stablet ≥ 1ms, delay from sensor power up stable to RESETB pull up3t ≥ 20ms, delay from RESETB pull high to SCCB initialization
4t5 ≥ 0ms, delay from AVDD off to DOVDD off
t6 ≥ 0ms, delay from RESETB pull low to DVDD off
3660_DS_2_15
t7 ≥ 0ms, delay from XVCLK off to DVDD off

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PRELIMINARY SPECIFICATION

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

2.5 reset
The OV3660 sensor includes a RESETB pin (pin C6) that forces a complete hardware reset when it is pulled low (GND).
The OV3660 clears all registers and resets them to their default values when a hardware reset occurs. A reset can also
be initiated through the SCCB interface by setting register 0x3008[7] to high. Reset requires ~2ms settling time.

2.5.1 power ON reset generation
The power on reset can be controlled from the RESETB pin. However, inside this chip, a power on reset is generated
after power is stable.

2.6 hardware and software standby
Two suspend modes are available for the OV3660:•

hardware standby•

software standby

2.6.1 hardware standby
To initiate a hardware standby, the PWDN pin (pin F6) must be tied to high. When this occurs, the OV3660 internal device
clock is halted and all internal counters are reset and registers are maintained. Majority of the digital circuitry will remainin the power-cut state.

2.6.2 software standby
Executing a software standby through the SCCB interface suspends internal circuit activity but does not halt the device
clock. All register content is maintained in standby mode.

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

2-9

2.7 format and frame ratetable 2-2

format and frame rate

formatresolution

frame ratescaling method

system clock

3 megapixel

2048x1536

15 fpsfull resolution

54 MHz1080p

1920x1080

20 fpscropping from full resolution

54 MHz720p

1280x720

45 fpscropping from full resolution

54 MHzXGA

1024x768

45 fpssubsampling in vertical and horizontal

54 MHzVGA

640x48060 fpssubsampling from 1280x960

27 MHz

QVGA

320x240

120 fpssubsampling from 1280x960

27 MHz2.7.1 output format control

table 2-3
address

0x501Fa.

output format control registers
register name

FORMAT CTRL

default
value

0x03

R/W

description

RW

Format ControlaBit[2:0]: Format select000: YUV422
001: RGB
010: Dither
011: RAW after DPC
101: RAW after CIP

for details, contact your local OmniVision FAE for the software application note

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

2.7.1.1 format description
Format control converts the internal data format into the desired output format including YUV, RGB, or RAW. Format
setting should also combine with 0x501F.

table 2-4
addressformat control registers (sheet 1 of 4)
register namedefault
value

R/W

description
Format Control 00
Bit[7:4]: Output format selection
0x0: RAWBit[3:0]: Output sequence
0x0: BGBG... / GRGR...
0x1: GBGB... / RGRG...
0x2: GRGR... / BGBG...
0x3: RGRG... / GBGB...
0x4~0xF: Not allowed
0x1: Y8
Bit[3:0]: Does not matter
0x2: Not used

0x4300

FORMAT CTRL 00

proprietary to OmniVision Technologies

0xF8

RW

0x3: YUV422
Bit[3:0]: Output sequence
0x0: YUYV...
0x1: YVYU...
0x2: UYVY...
0x3: VYUY...
0x4~0xE: Not allowed
0xF: UYVY...
0x4~0x5: Not used
0x6: RGB565
Bit[3:0]: Output sequence
0x0: {b[4:0],g[5:3]},{g[2:0],r[4:0]}
0x1: {r[4:0],g[5:3]},{g[2:0],b[4:0]}
0x2: {g[4:0],r[5:3]},{r[2:0],b[4:0]}
0x3: {b[4:0],r[5:3]},{r[2:0],g[4:0]}
0x4: {g[4:0],b[5:3]},{b[2:0],r[4:0]}
0x5: {r[4:0],b[5:3]},{b[2:0],g[4:0]}
0x6~0xE: Not allowed
0xF: {g[2:0],b[4:0]},{r[4:0],g[5:3]}
0x7: RGB555 format 1
Bit[3:0]: Output sequence
0x0: {b[4:0],g[4:2]},{g[1:0],1'b0,r[4:0]}
0x1: {r[4:0],g[4:2]},{g[1:0],1'b0,b[4:0]}

PRELIMINARY SPECIFICATION

version 1.3

2-11

table 2-4
addressformat control registers (sheet 2 of 4)
register namedefault
value

R/W

description
0x2: {g[4:0],r[4:2]},{r[1:0],1'b0,b[4:0]}
0x3: {b[4:0],r[4:2]},{r[1:0],1'b0,g[4:0]}
0x4: {r[4:0],b[4:2]},{b[1:0],1'b0,g[4:0]}
0x5: {g[4:0],b[4:2]},{b[1:0],1'b0,r[4:0]}
0x6~0xF: Not allowed
0x8: RGB555 format 2
Bit[3:0]: Output sequence
0x0: {1'b0,b[4:0],g[4:3]},{g[2:0],r[4:0]}
0x1: {1'b0,r[4:0],g[4:2]},{g[2:0],b[4:0]}
0x2: {1'b0,g[4:0],r[4:2]},{r[2:0],b[4:0]}
0x3: {1'b0,b[4:0],r[4:2]},{r[2:0],g[4:0]}
0x4: {1'b0,r[4:0],b[4:2]},{b[2:0],g[4:0]}
0x5: {1'b0,g[4:0],b[4:2]},{b[2:0],r[4:0]}
0x6: {b[4:0],1'b0,g[4:3]},{g[2:0],r[4:0]}
0x7: {r[4:0],1'b0,g[4:2]},{g[2:0],b[4:0]}
0x8: {g[4:0],1'b0,r[4:2]},{r[2:0],b[4:0]}
0x9: {b[4:0],1'b0,r[4:2]},{r[2:0],g[4:0]}
0xA: {r[4:0],1'b0,b[4:2]},{b[2:0],g[4:0]}
0xB: {g[4:0],1'b0,b[4:2]},{b[2:0],r[4:0]}
0xC~0xF: Not allowed
0x9: RGB444 format 1
Bit[3:0]: Output sequence
0x0: {1'b0,b[3:0],2'h0,g[3]},{g[2:0],1'b0,r[3:0]}
0x1: {1'b0,r[3:0],2'h0,g[3]},{g[2:0],1'b0,b[3:0]}
0x2: {1'b0,g[3:0],2'h0,r[3]},{r[2:0],1'b0,b[3:0]}
0x3: {1'b0,b[3:0],2'h0,r[3]},{r[2:0],1'b0,g[3:0]}
0x4: {1'b0,r[3:0],2'h0,b[3]},{b[2:0],1'b0,g[3:0]}
0x5: {1'b0,g[3:0],2'h0,b[3]},{b[2:0],1'h0,r[3:0]}

05.13.2011

PRELIMINARY SPECIFICATION

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 2-4
addressformat control registers (sheet 3 of 4)
register namedefault
value

R/W

description
0x6: {b[3:0],1'b0,g[3:1]},{g[0],2'h0,r[3:0],1'b0}
0x7: {r[3:0],1'b0,g[3:1]},{g[0],2'h0,b[3:0],1'b0}
0x8: {g[3:0],1'b0,r[3:1]},{r[0],2'h0,b[3:0],1'b0}
0x9: {b[3:0],1'b0,r[3:1]},{r[0],2'h0,g[3:0],1'b0}
0xA: {r[3:0],1'b0,b[3:1]},{b[0],2'h0,g[3:0],1'b0}
0xB: {g[3:0],1'b0,b[3:1]},{b[0],2'h0,r[3:0],1'b0}
0xC~0xF: Not allowed
0xA: RGB444 format 2
Bit[3:0]: Output sequence
0x0: {4'b0,b[3:0]},{g[3:0],r[3:0]}
0x1: {4'b0,r[3:0]},{g[3:0],b[3:0]}
0x2: {4'b0,b[3:0]},{r[3:0],g[3:0]}
0x3: {4'b0,r[3:0]},{b[3:0],g[3:0]}
0x4: {4'b0,g[3:0]},{b[3:0],r[3:0]}
0x5: {4'b0,g[3:0]},{r[3:0],b[3:0]}
0x6: {b[3:0],g[3:0],2'h0},{r[3:0],b[3:0],2'h0,g[3:0],r[3:0],2'h0}0x7: {r[3:0],g[3:0],2'h0},{b[3:0],r[3:0],2'h0,g[3:0],b[3:0],2'h0}0x8: {b[3:0],r[3:0],2'h0},{g[3:0],b[3:0],2'h0,r[3:0],g[3:0],2'h0}
0x9: {r[3:0],b[3:0],2'h0},{g[3:0],r[3:0],2'h0,b[3:0],g[3:0],2'h0}0xA: {g[3:0],b[3:0],2'h0},{r[3:0],g[3:0],2'h0,b[3:0],r[3:0],2'h0}0xB: {g[3:0],r[3:0],2'h0},{b[3:0],g[3:0],2'h0,r[3:0],b[3:0],2'h0}
0xC~0xF: Not allowed
0xB~0xE: Not allowed

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

2-13

table 2-4
addressformat control registers (sheet 4 of 4)
register namedefault
value

R/W

description
0xF: Bypass formatter module
Bit[3:0]: Output format
0x8: Raw
0x9: YUV422

0x4301

FORMAT CTRL 01

0x00

RW

Bit[1:0]: YUV422 UV control
00: U/V generated from average
01: U/V generated from first pixel
10: Not valid
11: U/V generated from second pixel

0x4302YMAX VALUE

0x03

RW

Bit[1:0]: Set y max clip value[9:8]0x4303YMAX VALUE

0xFF

RW

Bit[7:0]: Set y max clip value[7:0]0x4304YMIN VALUE

0x00

RW

Bit[1:0]: Set y min clip value[9:8]0x4305YMIN VALUE

0x00

RW

Bit[7:0]: Set y min clip value[7:0]0x4306

UMAX VALUE

0x03

RW

Bit[1:0]: Set u max clip value[9:8]0x4307

UMAX VALUE

0xFF

RW

Bit[7:0]: Set u max clip value[7:0]0x4308UMIN VALUE

0x00

RW

Bit[1:0]: Set u min clip value[9:8]0x4309UMIN VALUE

0x00

RW

Bit[7:0]: Set u min clip value[7:0]0x430A

VMAX VALUE

0x03

RW

Bit[1:0]: Set v max clip value[9:8]0x430B

VMAX VALUE

0xFF

RW

Bit[7:0]: Set v max clip value[7:0]0x430CVMIN VALUE

0x00

RW

Bit[1:0]: Set v min clip value[9:8]0x430D

VMIN VALUE

0x00

RW

Bit[7:0]: Set v min clip value[7:0]05.13.2011

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

2.8 I/O control
The I/O control allows the user to configure the I/O pad direction to either be an input or output. In addition, the I/O control
also allows the user to set the driving capability for the output. Please take note that the driving capability is notindependently controlled for each output. Setting the driving capability will apply to all configured outputs. table 2-5 lists
the driving capability and direction control registers of the I/O pads.

table 2-5

note

To achieve optimal
signal quality, for highspeed and highcapacitance loading
designs, OmniVision
recommends using ahigher drive capability.
Conversely, for low
speed and low
capacitance loading,use a lower driving
capability setting.

driving capability and direction control for I/O pads (sheet 1 of 2)

function

registerdefault value

R/W

description

output drive capability
control

0x302C

0x02

RW

Bit[7:6]: output drive capability for
all I/O type pads (seetable 1-2)
00: 1x01: 2x10: 3x11: 4xD[9:0] I/O control

0x3017[3:0],
0x3018[7:2]

0x00

RW

input/output control for the D[9:0] pins
0: input
1: output

D[9:0] output select0x301D[3:0],
0x301E[7:2]

0x00

RW

output selection for the D[9:0] pins
0: normal data path
1: register-controlled value

D[9:0] output value

0x301A[3:0],
0x301B[7:2]

0x00

RW

D[9:0] output value

D[9:0] input value

0x3051[3:0],0x3052[7:2]–R

D[9:0] input value

VSYNC I/O control

0x3017

0x00

Bit[6]:

input/output control for
the VSYNC pin
0:
input
1:
outputBit[6]:

output selection for the
VSYNC pin0:
normal data path1:
register-controlled
value

RW

VSYNC output select0x301D

0x00

RW

VSYNC output value

0x301A

0x00

RW

Bit[6]:

VSYNC output value

VSYNC input value

0x3051–R

Bit[6]:

VSYNC input value

Bit[5]:
HREF I/O control

0x30170x00

RW

input/output control for
the HREF pin
0:
input
1:
outputproprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

2-15

table 2-5

driving capability and direction control for I/O pads (sheet 2 of 2)

function

registerdefault value

R/W

description
Bit[5]:

output selection for the
HREF pin0:
normal data path1:
register-controlled
value

HREF output select0x301D

0x00

RW

HREF output value

0x301A

0x00

RW

Bit[5]:

HREF output value

HREF input value

0x3051–R

Bit[5]:

HREF input value

Bit[4]:

input/output control for
the PCLK pin
0:
input
1:
outputBit[4]:

output selection for the
PCLK pin0:
normal data path1:
register-controlled
value

PCLK I/O control

0x30170x00

RW

PCLK output select0x301D

0x00

RW

PCLK output value

0x301A

0x00

RW

Bit[4]:PCLK output value

PCLK input value

0x3051–R

Bit[4]:PCLK input value

05.13.2011

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

2.9 system control
System control registers include clock, reset control, and PLL configure. Individual modules can be reset or clock gatedby setting the appropriate registers.

table 2-6

system control registers (sheet 1 of 3)
default
value

R/W

description

SYSTEM RESET00~
SYSTEM RESET03–

RW

Reset for Individual Blocks

CLOCK ENABLE00~
CLOCK ENABLE03–

RW

Clock Enable Control for Individual
Blocksaddress

register name0x3000~0x30030x3004~0x30070x3008SYSTEM CTROL0

0x02

RW

System Control
Bit[7]:
Software reset
Bit[6]:
Software power downBit[5]:
Reserved
Bit[4]:SRB clock SYNC enable
Bit[3]:
Isolation suspend selectBit[2:0]: Not used

0x300ASENSOR CHIP ID HIGH BYTE

0x36

R

Chip ID High Byte

0x300BSENSOR CHIP ID LOW BYTE

0x60

R

Chip ID Low Byte

0x3016PAD OUTPUT ENABLE 00

0x22

RW

Input/Output Control (0: input; 1: output)
Bit[2]:FSIN output enableBit[1]:STROBE output enable
Bit[0]:
Not used

0x3017

PAD OUTPUT ENABLE 01

0x00

RW

Input/Output Control (0: input; 1: output)
Bit[7]:
Not usedBit[6]:
VSYNC output enableBit[5]:
HREF output enable
Bit[4]:PCLK output enable
Bit[3:0]: D[9:6] output enable

0x3018PAD OUTPUT ENABLE 02

0x00

RW

Input/Output Control (0: input; 1: output)
Bit[7:2]: D[5:0] output enableBit[1:0]: Not usedRW

PAD Output Value
Bit[7:3]: Not usedBit[2]:FSIN
Bit[1]:STROBEBit[0]:
Not used

0x3019PAD OUTPUT VALUE 00

proprietary to OmniVision Technologies

0xF0

PRELIMINARY SPECIFICATION

version 1.3

2-17

table 2-6
address

system control registers (sheet 2 of 3)
register namedefault
value

R/W

description

0x301APAD OUTPUT VALUE 01

0x00

RW

GPIO Output Value
Bit[7]:
Reserved
Bit[6]:
VSYNC
Bit[5]:
HREF
Bit[4]:
PCLK
Bit[3:0]: D[9:6]0x301BPAD OUTPUT VALUE 02

0x00

RW

GPIO Output Value
Bit[7:2]: D[5:0]
Bit[1:0]: Not usedRW

Pad select control
Bit[2]:IO FSIN selectBit[1]:IO STROBE selectBit[0]:
Not used

0x301CPAD SEL00x000x301D

PAD SEL1

0x00

RW

Pad select control
Bit[7]:
Not usedBit[6]:IO VSYNC selectBit[5]:IO HREF selectBit[4]:IO PCLK selectBit[3:0]: IO D[9:6] select0x301EPAD SEL20x00

RW

Pad select control
Bit[7:2]: IO D[5:0] selectBit[1:0]: Not used

0x302ACHIP REVISION–R

Bit[7:4]: Process
0xB: BSI
Bit[3:0]: Chip revision
Pad control
Bit[7:6]: Pad driving strength
00: 1x01: 2x10: 3x11: 4xBit[5]:
pd_dato_en
Bit[4:2]: Reserved
Bit[1]:FSIN input enable
Bit[0]:STROBE input enable

0x302CPAD CONTROL

0x03

RW

0x303ASC PLLS CTRL0

0x00

RW

Bit[7]:PLLS bypass
Bit[6:0]: Reserved

0x303BSC PLLS CTRL1

0x1B

RW

Bit[4:0]: PLLS multiplier

0x303CSC PLLS CTRL2

0x11

RW

Bit[6:4]: PLLS charge pump control
Bit[3:0]: PLLS system divider

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 2-6
address

0x303D

0x3050system control registers (sheet 3 of 3)
register nameSC PLLS CTRL3

IO PAD VALUE

default
value

0x30

–

R/W

RW

description
Bit[5:4]: PLLS predivider
00: /1
01: /1.5
10: /2
11: /3Bit[3]:
Not usedBit[2]:PLLS root divider
0:
/1
1:
/2
Bit[1:0]: PLLS seld500: /1
01: /1
10: /2
11: /2.5

R

Read pad value
Bit[7:4]: Not usedBit[3]:PWDN
Bit[2]:
Not usedBit[1]:
SIOC

0x3051IO PAD VALUE–

R

Read pad value
Bit[7]:OTP memory out
Bit[6]:
VSYNC
Bit[5]:
HREF
Bit[4]:
PCLK
Bit[3:0]: D[9:6]0x3052IO PAD VALUE–

R

Read pad value
Bit[7:2]: D[5:0]
Bit[1:0]: Not used

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

2-19

2.9.1 system clock control
The OV3660 PLL allows input clock frequency from 6~27 MHz and has VCO frequency of 150MHz~500MHz. SYS_CLK
is for the internal clock of the Image Signal Processing (ISP) block. The PLL can be bypassed by setting register0x303A[7] to 1.
By default, the PCLK frequency is decided by the horizontal scaling ratio. Refer to table 2-7 for the auto PCLK divider
ratio. When 0x460C[1] is set to 1, the PCLK divider ratio is manually set by 0x3824[4:0].

CF = horizontal input size / horizontal output size

table 2-7

PCLK divider ratio

horizontal scaling factor (CF)PCLK divider ratio

CF<2

1

2<=CF<42

4<=CF<84

8<=CF<16

8

CF>16

16

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

figure 2-7

PLL block diagram

PLL
XVCLK

predivider{0x303D[5:4], 2'h3}
1/1.5/2/3(6 ~ 27MHz)

REFIN(4 ~ 13.5MHz)

VCO (150~500MHz)
multiplier {0x303B[4:0], 5'h1B}(150MHz< multiplier*(root divider +1)*REFIN <500MHz){root divider, 0x303D[2], 1'h0}
fmax:
216MHzseld5(0x303D[1:0], 2'h0)
1/1/2/2.5

system divider({0x303C[3:0], 4'h1,4'h0} means
divide by

PLL bypass{0x303A[7], 1'h0}

MUX

PLL_CLK

digital core/2

table 2-8

note

Contact your local
OmniVision FAE for
additional assistanceon PLL configuration.

/2

pdiv
(auto control)

Sys_Clk

PCLK

3660_DS_2_5

PLL configurations

configuration

register
0x303Aregister
0x303Bregister
0x303C

register
0x303D

register
0x3824

register
0x460C

defaulta

0x00

0x1B

0x11

0x30

0x01

0x20

(sample 1)b

0x00

0x1B

0x12

0x30

0x01

0x20

a.

default settings are for 54MHz pixel clock, sensor output of 3 Mpixel at 15 fps, and DVP outputb.

sample settings are for 54MHz pixel clock, sensor output of 3 Mpixel at 7.5 fps and DVP output

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

2-21

table 2-9

PLL control registers

address

register namedefault
value

R/W

0x303ASC PLLS CTRL0

0x00

RW

Bit[7]:PLLS bypass
Bit[6:0]: Reserved

0x303BSC PLLS CTRL1

0x1B

RW

Bit[4:0]: PLLS multiplier

0x303CSC PLLS CTRL2

0x11

RW

Bit[6:4]: PLLS charge pump control
Bit[3:0]: PLLS system divider

description

0x303DSC PLLS CTRL3

0x30

RW

Bit[5:4]: PLLS predivider
00: /1
01: /1.5
10: /2
11: /3Bit[2]:PLLS root divider
0:
/1
1:
/2
Bit[1:0]: PLLS seld500: /1
01: /1
10: /2
11: /2.50x3824

TIMING TC REG24

0x01

RW

Bit[7:5]: Not usedBit[4:0]: PCLK ratio manualBit[1]:

0x460C

05.13.2011

VFIFO CTRL0C

0x20

PRELIMINARY SPECIFICATIONRWPCLK manual enable
0:
DVP PCLK divider
control by auto mode
1:
DVP PCLK divider
control by 0x3824[4:0]

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

2.10 group writeGroup write is supported in order to update a group of registers in the same frame. These registers are guaranteed tobe written prior to the internal latch at the frame boundary.
The OV3660 supports up to four groups. These groups share 512 MB RAM and the size of each group is programmableby adjusting the start address.

table 2-10
addressgroup write registers
register namedefault
value

R/W

description

0x3208

GROUP ACCESS–

W

Group AccessBit[7:4]: group_ctrl
0000: Group hold start
0001: Group hold end
1010: Group launchothers: Reserved
Bit[3:0]: group_id
0000: Group bank 0, default startfrom address 0x00
0001: Group bank 1, default startfrom address 0x40
0010: Group bank 2, default startfrom address 0x80
0011: Group bank 3, default startfrom address 0xB0
others: Reserved

0x3209

GRP0_PERIOD

0x00

RW

Frames For Staying in Group 00x320A

GRP1_PERIOD

0x00

RW

Frames For Staying in Group 10x320B

GRP_SWCTRL

0x01

RW

0x320DGRP_ACT–R

Indicates Which Group is Active

0x320EFRAME_CNT_GRP0–

R

frame_cnt_grp0

0x320F

FRAME_CNT_GRP1–

R

frame_cnt_grp1

proprietary to OmniVision Technologies

Bit[3]:
group_switch_repeat
Bit[2]:
context_en
Bit[1:0]: Second group selection

PRELIMINARY SPECIFICATION

version 1.3

3-1

3 image sensor core digital functions
3.1 mirror and flip
The OV3660 Mirror and Flip readout modes, which respectively reverse the sensor data readout order horizontally andvertically (see figure 3-1).

mirror and flip samples

F

F

F

original image

mirrored image

Ffigure 3-1

flipped image

mirrored and flipped
image
3660_DS_3_1

table 3-1
address

0x38200x3821a.

mirror and flip registers
register name

TIMING TC REG20

TIMING TC REG21

default
value

0x40

0x00

R/W

description

RW

Timing Control RegisterBit[2:1]: Vertical flip enablea
00: Normal
11: Vertical flip

RW

Timing Control RegisterBit[2:1]: Horizontal mirror enableb
00: Normal
11: Horizontal mirrorc

for full size flip, it is necessary to set register 0x4514 to 0x88b.

for full size mirror + flip, also set register 0x4514 to 0xBBc.

for bin + mirror, set register 0x4514 to 0xBB

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

3.2 image windowing and scaling
3.2.1 image windowing
The OV3660 uses registers 0x3800 ~ 0x3814 for image windowing. figure 3-2 illustrates how the registers define thewindowing size. Physical pixel size is the total pixel array size we have in the sensor. The ISP input size is the total pixel
data read from pixel array. Typically, the larger ISP input size is, the less maximum frame rate can be reached. The data
output size is the image output size of OV3660. This size is windowed from ISP input size and is defined by x_offset andy_offset as figure 3-2 shows.

figure 3-2

image windowing(0, 0)Y_ADDR_ST{0x3802, 0x3803}

Y_OUTPUT_SIZE{0x380A 0x380B}

Y_ADDR_END{0x3806, 0x3807}

Y_OFFSET{0x3812, 0x3813}
X_OFFSET{0x3810, 0x3811}

X_ADDR_ST{0x3800, 0x3801}

OV3660

data output size
X_OUTPUT_SIZE{0x3808, 0x3809}
X_ADDR_END{0x3804, 0x3805}

ISP input size

physical pixel size
(X_ADDR_MAX, Y_ADDR_MAX)
3660_DS_3_2

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

3-3

figure 3-3 shows the windowing configuration when scaling function is enabled. The pre-scaling image size is the ISP
input size subtracted by two times of offsets for both horizontal and vertical.

figure 3-3

image windowing configuration(0, 0)

data output size
(after scaling)pre-scaling size
Y_OFFSET{0x3812, 0x3813}

X_OUTPUT_SIZE{0x3808, 0x3809}

ISP input size

X_ADDR_END{0x3804, 0x3805}

physical pixel size

(X_ADDR_MAX, Y_ADDR_MAX)table 3-2

Y_OUTPUT_SIZE{0x380A, 0x380B}

Y_ADDR_END{0x3806, 0x3807}

X_OFFSET{0x3810, 0x3811}

Y_OFFSET{0x3812, 0x3813}
X_OFFSET{0x3810, 0x3811}

X_ADDR_ST{0x3800, 0x3801}

Y_ADDR_ST{0x3802, 0x3803}

3660 DS 3 3image windowing registers (sheet 1 of 2)

address

register namedefault
value

R/W

0x3800

TIMING HS

0x00

RW

Bit[3:0]: X address start[11:8]

0x3801

TIMING HS

0x00

RW

Bit[7:0]: X address start[7:0]0x3802TIMING VS

0x00

RW

Bit[2:0]: Y address start[10:8]

0x3803

TIMING VS

0x00

RW

Bit[7:0]: Y address start[7:0]0x3804

TIMING HW

0x08

RW

Bit[3:0]: X address end[11:8]

0x3805

TIMING HW

0x1F

RW

Bit[7:0]: X address end[7:0]0x3806

TIMING VH

0x06

RW

Bit[2:0]: Y address end[10:8]

0x3807

TIMING VH

0x0B

RW

Bit[7:0]: Y address end[7:0]0x3808TIMING DVPHO

0x08

RW

Bit[3:0]: DVP output horizontal width[11:8]

0x3809TIMING DVPHO

0x00

RW

Bit[7:0]: DVP output horizontal width[7:0]0x380A

TIMING DVPVO

0x06

RW

Bit[2:0]: DVP output vertical height[10:8]

05.13.2011

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description

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 3-2

image windowing registers (sheet 2 of 2)

address

register namedefault
value

R/W

0x380B

TIMING DVPVO

0x00

RW

Bit[7:0]: DVP output vertical height[7:0]0x380CTIMING HTS

0x08

RW

Bit[3:0]: Total horizontal size[11:8]

0x380D

TIMING HTS

0xFC

RW

Bit[7:0]: Total horizontal size[7:0]0x380E

TIMING VTS

0x06

RW

Bit[7:0]: Total vertical size[15:8]

0x380F

TIMING VTS

0x1C

RW

Bit[7:0]: Total vertical size[7:0]0x3810

TIMING HOFFSET

0x00

RW

Bit[3:0]: ISP horizontal offset[11:8]

0x3811

TIMING HOFFSET

0x10

RW

Bit[7:0]: ISP horizontal offset[7:0]0x3812TIMING VOFFSET

0x00

RW

Bit[2:0]: ISP vertical offset[10:8]

0x3813

TIMING VOFFSET

0x06

RW

Bit[7:0]: ISP vertical offset[7:0]

description

3.2.2 scaling
The OV3660 includes a scalar function that allows the user to arbitrarily set an output image size (width and height) up
to 1/32 of the designated array size. The scalar module outputs the specified image size and maintains the field-of-viewas the input image to the scalar. Note that the frame rate will not change in scaling mode.

figure 3-4

scaling function(0, 0)
vertical start point {0x3802, 0x3803}

vertical offset {0x3812, 0x3813}

physical pixel size

ISP input size

data output size
(after scaling)vertical output size
{0x380A, 0x380B}

vertical endpoint {0x3806, 0x3807}

pre-scaling size

horizontal offset {0x3810, 0x3811}

vertical offset {0x3812, 0x3813}
horizontal offset {0x3810, 0x3811}

horizontal start point {0x3800, 0x3801}

OV3660horizontal output size
{0x3808, 0x3809}

horizontal endpoint {0x3804, 0x3805}
3660_DS_3_4

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

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3-5

The following steps allow the user to set their required output size:
1.

The scaling function is enabled and disabled by register bit 0x5001[5]. The user then needs to set the image
input size, output size and offset. The output size < (input size - 2 × offset).
Horizontal output size: {0x3808, 0x3809}
Vertical output size: {0x380A, 0x380B}
Horizontal offset: {0x3810, 0x3811}
Vertical offset: {0x3812, 0x3813}
Horizontal input size:
Horizontal endpoint {0x3804, 0x3805} - Horizontal start point {0x3800, 0x3801} + 1 - 2 × {0x3810, 0x3811}
Vertical input size:
Vertical endpoint {0x3806, 0x3807} - Vertical start point {0x3802, 0x3803} + 1 - 2 × {0x3812, 0x3813}

2.

The scaling factor is calculated automatically.

table 3-3

scaling control registers (sheet 1 of 2)

address

register namedefault
value

R/W

0x5001ISP CONTROL 01

0x01

RW

Scale enable0:
Disable1:
EnableBit[6:4]: HDIV RW
DCW scale times
000: DCW 1 time001: DCW 2 times
010: DCW 4 times
100: DCW 8 times
101: DCW 16 times
Others: DCW 16 times
Bit[2:0]: VDIV RW
DCW scale times
000: DCW 1 time001: DCW 2 times
010: DCW 4 times
100: DCW 8 times
101: DCW 16 times
Others: DCW 16 times

description
Bit[7]:

0x5601SCALE CTRL 1

0x00

RW

0x5602SCALE CTRL 2

0x02

RW

XSC High Bits

0x5603SCALE CTRL 3

0x00

RW

XSC Low Bits

0x5604SCALE CTRL 4

0x02

RW

YSC High Bits

0x5605SCALE CTRL 5

0x00

RW

YSC Low Bits

0x5606SCALE CTRL 6

0x00

RW

Bit[3:0]: Voffset

0x3804

TIMING HW

0x00

RW

Bit[7:4]: Not usedBit[3:0]: HREF horizontal endpoint[11:8]

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PRELIMINARY SPECIFICATION

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 3-3

scaling control registers (sheet 2 of 2)

address

register namedefault
value

R/W

0x3805

TIMING HW

0xDF

RW

Bit[7:0]: HREF horizontal endpoint[7:0]0x3806

TIMING VH

0x00

RW

Bit[7:4]: Not usedBit[3:0]: HREF vertical endpoint[11:8]

0x3807

TIMING VH

0x9B

RW

Bit[7:0]: HREF vertical endpoint[7:0]0x3808TIMING ISPHO

0x00

RW

Bit[7:4]: Not usedBit[3:0]: ISP output horizontal width[11:8]

0x3809TIMING ISPHO

0xC0

RW

Bit[7:0]: ISP output horizontal width[7:0]0x380A

TIMING ISPVO

0x00

RW

Bit[7:4]: Not usedBit[3:0]: ISP output vertical width[11:8]

0x380B

TIMING ISPVO

0x90

RW

Bit[7:0]: ISP output vertical width[7:0]0x3810

TIMING HOFFS HIGH

0x00

RW

Bit[7:4]: Not usedBit[3:0]: Horizontal offset[11:8]

0x3811

TIMING HOFFS LOW

0x10

RW

Bit[7:0]: Horizontal offset[7:0]0x3812TIMING VOFFS HIGH

0x00

RW

Bit[7:4]: Not usedBit[3:0]: Vertical offset[11:8]

0x3813

TIMING VOFFS LOW

0x10

RW

Bit[7:0]: Vertical offset[7:0]

proprietary to OmniVision Technologies

description

PRELIMINARY SPECIFICATION

version 1.3

3-7

3.3 test pattern
For testing purposes, the OV3660 offers one type of test pattern, color bar.

figure 3-5

test patterncolor bartable 3-4
address

test pattern selection control
register namedefault
value

R/W

description
Bit[7]:

0x503D

05.13.2011

PRE ISP TESTSETTING 1

0x00

RW

PRELIMINARY SPECIFICATION

Color bar enable
0:Color bar disable
1:
Color bar enable
Bit[3:2]: Color bar style
00: Standard eight color bar
01: Gradual change at verticalmode 1
10: Gradual change at horizontal
11: Gradual change at verticalmode 2

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

3.4 exposure / gain control
3.4.1 overview
The exposure/gain control mode allows for a companion backend processor to control the exposure and gain of theOV3660 externally. The pixel array is reset and sampled in series on a row-by-row basis (also known as "rolling shutter").
The time between reset and sampling is called exposure time. As each pixel is exposed, the charge in the pixel
decreases proportionally with the time exposed to incident light and the light intensity.
In the OV3660, the exposure time is set by registers {0x3500[3:0], 0x3501[7:0], ox3502[7:0]} in units of 1/16 row period.

exposure = {0x3500[3:0], 0x3501[7:0], 0x3502[7:0]} / 16 × tROW
The pixel output can be further amplified by the analog amplifier and/or digital multiplier. The OV3660 supports up to 16x
analog gain and 4x digital gain. The gain can be calculated from the register value using the following formula:gain = {0x350A[1:0], 0x350B[7:0]} / 16
The first 15.9375x gain ({0x350A[1:0] = 2b’00, 0x350B[7:0] = 0x00~0xFF}) is analog gain and the remaining 4x gain isdigital gain. Please note that analog gain is always preferred to reduce image noise; thus, for gain adjustments, it isalways advisable to maximize analog gain before moving on to use digital gain.
Under AC lighting conditions (e.g., 50Hz or 60Hz fluorescent light), the light intensity is not constant. Though theexposure time of each row is equal to each other, the amount of photons each row receives may vary with the start pointof the exposure. In order for each row to receive the same amount of photons, the exposure time must be a multiple ofthe flicker period of the light intensity.

exposure =second, for 50Hz
{ n/100
n/120 second, for 60Hz

If the exposure time does not fall in these steps, the pixel array will not be evenly illuminated and horizontal bands willshow up in the image.

3.4.2 automatic exposure/gain control
The Automatic Exposure Control (AEC) function allows the OV3660 image sensor to adjust the exposure and gain values
without any external command or control to the sensor. The OV3660 has a built-in AEC/AGC (auto exposure control /auto gain control) algorithm to automatically control the exposure and gain to bring the image level to a pre-defined
range, namely stable range. The AEC and AGC can be enabled by setting register 0x3503[0] and 0x3503[1] to 1’b0,
respectively. Although the AEC and AGC can be enabled/disabled independently, it is highly recommended that bothproprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

3-9

AEC and AGC are enabled/disabled together; otherwise, the auto control may induce flicker artifacts in the image dueto the precision limitation of the exposure time.
The image level is a weighted average over a user-defined area as shown in figure 3-6. The area is specified by the
top-left point ({0x5680[3:0], 0x5681[7:0]}, {0x5682[2:0], 0x5683[7:0]}) and the bottom-right point ({0x5684[3:0],
0x5685[7:0]}, {0x5686[2:0], 0x5687[7:0]}). The area is equally divided into 4x4 zones and the weight of each zone canbe programmed by registers 0x5688~0x568F as shown in table 3-5. The average value is calculated in the linear domain
when register 0x5025[1:0] is 2’b00 or after gamma correction when register 0x5025[1:0] is set to 2b’10.

figure 3-6

average-based window definition
sensor array size X
X

HW

start

Y

VH
sensor arraysize Y

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

averagewindowsize

end

3660_DS_3_6

table 3-5

timing control functions (sheet 1 of 3)

address

register namedefault
value

R/W

0x3810

TIMING HOFFSET

0x00

RW

Bit[3:0]: ISP horizontal offset[11:8]

0x3811

TIMING HOFFSET

0x10

RW

Bit[7:0]: ISP Horizontal offset[7:0]0x3812TIMING VOFFSET

0x00

RW

Bit[3:0]: ISP vertical offset[11:8]

0x3813

TIMING VOFFSET

0x06

RW

Bit[7:0]: ISP vertical offset[7:0]0x3808TIMING DVPHO

0x08

RW

Bit[3:0]: DVP output horizontal width[11:8]

0x3809TIMING DVPHO

0x00

RW

Bit[7:0]: DVP output horizontal width[7:0]0x380A

TIMING DVPVO

0x06

RW

Bit[3:0]: DVP output vertical height[11:8]

05.13.2011

PRELIMINARY SPECIFICATION

description

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 3-5

timing control functions (sheet 2 of 3)

address

register namedefault
value

R/W

0x380B

TIMING DVPVO

0x00

RW

Bit[7:0]: DVP output vertical height[7:0]0x501D

ISP MISC

0x00

RW

Bit[4]:

0x5680X START

0x00

RW

Bit[3:0]: X start[11:8]
Horizontal start position for averagewindow high byte, valid when 0x501D[4]=10x5681X START

0x00

RW

Bit[7:0]: X start[7:0]
Horizontal start position for averagewindow low byte, valid when 0x501D[4]=10x5682Y START

0x00

RW

Bit[2:0]: Y start[10:8]
Vertical start position for average window
low byte, valid when 0x501D[4]=10x5683

Y START

0x00

RW

Bit[7:0]: Y start[7:0]
Vertical start position for average window
low byte, valid when 0x501D[4]=10x5684

X WINDOW

0x10

RW

Bit[3:0]: Window X[11:8]
Horizontal end position for average windowhigh byte, valid when 0x501D[4]=10x5685

X WINDOW

0xA0

RW

Bit[7:0]: Window X[7:0]
Horizontal end position for average window
low byte, valid when 0x501D[4]=1.

0x5686

Y WINDOW

0x0C

RW

Bit[2:0]: Window Y[10:8]
Vertical end position for average windowhigh byte, valid when 0x501D[4]=10x5687

Y WINDOW

0x78

RW

Bit[7:0]: Window Y[7:0]
Vertical end position for average window
low byte, valid when 0x501D[4]=10x5688

WEIGHT00

0x11

RW

Bit[7:4]: Window 01 weightBit[3:0]: Window 00 weight

0x5689WEIGHT01

0x11

RW

Bit[7:4]: Window 03 weightBit[3:0]: Window 02 weight

0x568A

WEIGHT02

0x11

RW

Bit[7:4]: Window 11 weightBit[3:0]: Window 10 weight

0x568B

WEIGHT03

0x11

RW

Bit[7:4]: Window 13 weightBit[3:0]: Window 12 weight

0x568CWEIGHT04

0x11

RW

Bit[7:4]: Window 21 weightBit[3:0]: Window 20 weight

0x568DWEIGHT05

0x11

RW

Bit[7:4]: Window 23 weightBit[3:0]: Window 22 weight

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description

Average size manual enable

PRELIMINARY SPECIFICATION

version 1.3

3-11

table 3-5

timing control functions (sheet 3 of 3)

address

register namedefault
value

R/W

0x568EWEIGHT06

0x11

RW

Bit[7:4]: Window 31 weightBit[3:0]: Window 30 weight

0x568F

WEIGHT07

0x11

RW

Bit[7:4]: Window 33 weightBit[3:0]: Window 32 weight

description

The upper limit of the stable range is specified by register 0x3A1B and the lower limit is set by register 0x3A1E.
When register 0x3A05[5] is set to 1, the sensor automatically calculates the exposure/gain step according to the distance
between the current image level and the center of the stable range. The ratio of the adjustment step to the distance canbe set using register 0x3A05[4:0]:

step =

0x3A05[4:0]________________ ×|current_image_level target_image_level|32

where target_image_level equals (0x3A1B+0x3A1E/2)
When register 0x3A05[5] is set to 0, the exposure/gain adjustment is manually set by registers 0x3A06 and 0x3A07,
depending on where the current image level is. Another wider range, specified by (0x3A10, 0x3A0F), is used to control
the step of the exposure/gain adjustment. When the image level is greater than the value of register 0x3A0F, the sensor
will decrease the exposure/gain by a big step1:

step1 =

0x3A07[3:0]________________ ×
current_exposure_gain
16

When the image level is less than the value of register 0x3A10, the sensor will increase the exposure/gain by a big step 2:

step2 =

0x3A06[4:0]________________ ×
current_exposure_gain
32

When the image level is within the wider range of (0x3A10, 0x3A0F) but outside of the stable range (0x3A1E, 0x3A1B),
the sensor will adjust the exposure/gain by a small step 3:

step3 =

05.13.2011

0x3A07[7:4]________________ ×
current_exposure_gain
16

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

3.4.3 50Hz/60Hz detection
The OV3660 has a built-in capability to identify 50Hz and 60Hz flickering frequency. When this function is enabled by
setting register 0x3004[2] to 1, the sensor will continuously detect the light frequency. The sensor will keep the previous
result whenever it is not able to determine the current AC flickering frequency.
The 50Hz/60Hz detection block needs an input clock at a frequency of approximately 3 MHz. Register 0x300C[3:0] is
the divider that generates this input clock frequency from the input clock pin (XVCLK).
Register 0x3C01[7] must be set to 0 for the AEC/AGC algorithm to apply the exposure constraint based on the result of
the 50Hz/60Hz detection.
Register 0x3C0C[0] shows the result of the 50Hz/60Hz detection. When the detection result is 60Hz, register
0x3C0C[0] = 0, the AEC/AGC algorithm will set the exposure time to an integer multiple of {0x3A0A[1:0], 0x3A0B[7:0]}.
Conversely, when the detection is 50Hz, register 0x3C0C[0] = 1, the AEC/AGC algorithm will set the exposure time to
an integer multiple of {0x3A08[1:0], 0x3A09[7:0]}.

3.4.4 anti-flicker
Under AC lighting conditions, the user can specify whether to restrict the exposure time to n/100 or n/120 second using
register 0x3A00[5]. When the exposure time is restricted to n/100 in 50Hz light or n/120 in 60Hz light, the pixel array will
be evenly exposed despite the flickering nature of the AC light source.
In order for the sensor to restrict the exposure time to n/100 or n/120 second, registers {0x3A08, 0x3A09} should be set
to 1/100 second in units of row period and registers {0x3A0A, 0x3A0B} should be set to 1/120 second in units of row
period. Furthermore, registers 0x3A0E and 0x3A0D should be set to the maximum number of flickering periods in one
frame period for 50Hz and 60Hz, respectively.
Given the frame rate (frame period) and the number of row period per frame period, registers {0x3A08, 0x3A09},{0x3A0A, 0x3A0B}, 0x3A0E, and 0x3A0D can be calculated by the following formula with the result rounded to theclosest integer:

frame_per_second × row_per_frame{0x3A08, 0x3A09} = __________________________________________________
100
frame_per_second × row_per_frame{0x3A0A, 0x3A0B} = __________________________________________________
100
0x3A0E =100__________________________
frame_per_second

0x3A0D =120__________________________
frame_per_second

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PRELIMINARY SPECIFICATION

version 1.3

3-13

For example, for a YUV output at 15 fps and full resolution of 2048x1536:

row_per_frame = register {0x380E, 0x380F} = 0x61C = 1564 (decimal){0x3A08, 0x3A09} = (1564 × 15)/100 = 234.6 (decimal) = 0xEA
{0x3A08, 0x3A09} = (1564 × 15)/120 = 195.5 (decimal) = 0xC3
0x3A0E = 100/15 = 6.67 (decimal) = 0x06
0x3A0D = 120/15 = 8 (decimal) = 0x08
The light flickering frequency is either automatically set by the 50Hz/60Hz detection circuit (explained in detail in
section 3.4.3) or manually selected through register 0x3C00[2].
Under very bright AC light conditions, the desired exposure time may be less than 1/100 or 1/120 second. In this case,the sensor can either adjust the exposure time to the desired value or limit the minimum exposure time to 1/100 or 1/120
second. By adjusting the exposure time under such bright AC lighting conditions, the user should expect that there will
be horizontal flickering artifacts in the image as the pixels are no longer integrating in a multiple of the flicker periods.
Conversely, by limiting the minimum exposure time to 1/100 or 1/120 second, the user can expect an over exposed
image.
The trade-off described above can be controlled through register 0x3A00[4]. When this register is set to 1, the exposure
time is allowed to go below 1/100 or 1/120 second to avoid over exposure. When this register is set to 0, the minimum
exposure is limited to 1/100 or 1/120 second to avoid the flicker.

3.4.5 extending the exposure time under dark conditions
From a noise point of view, it is always preferable to extend the exposure time rather than increasing gain. However, theexposure time is limited to the frame period at a given frame rate. Under extremely dark conditions, the image may still
be too dark when the exposure reaches its maximum and the gain then increases to a certain level. One common way
to achieve a better image is to slow down the frame rate which, in turn, extends the exposure time. The AEC/AGC
algorithm of the OV3660 supports this feature and terms this as night mode. Night mode can be enabled by setting
register 0x3A00[2] to 1.
The sensor enters night mode when the exposure time reaches the maximum and the gain reaches the threshold definedby register 0x3A17[1:0] (see table 3-6). The sensor starts to extend the frame period by the original frame period, or the
flickering period, depending on the value set in register 0x3A05[6]. When this register is set to 1, the sensor will extend
the exposure time up to the value set in register 0x3A21[6:4] until the image level falls into the stable range. If the image
is still too dark after the exposure has been extended to its maximum exposure time, the sensor will further increase thegain. When register 0x3A05[6] is set to 0, the sensor will extend the exposure time by flickering period {0x3A0A[1:0],
0x3A0B[7:0]} or {0x3A08[1:0], 0x3A09[7:0]}, depending on the light frequency. Note that even when the anti-flickeringfunction is disabled, the sensor will extend the exposure time by the flickering period when register 0x3A05[6] is set to 0.

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PRELIMINARY SPECIFICATION

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 3-6

night mode control registers

function

registersnight mode ceiling setting{0x3A02[7:0], 0x3A03[7:0], 0x3A14[7:0], 0x3A15[7:0]}

night mode disable

0x3A00[2]0: disable night modeincrease/decrease step in night mode
based on band or frames

0x3A05[6]0: in night mode, insert frame disable
1: in night mode, insert frame enable

3.4.6 sub-row exposure time under extremely bright conditions
Under extremely bright conditions, even the exposure time of one row period will result in an over exposed image. In thiscase, the AEC/AGC algorithm can set the exposure time to sub-row period. This function can be enabled by setting
register 0x3A00[6].
Due to the readout timing limitation, the minimum and maximum sub-row exposure times have certain constraints. The
maximum and minimum sub-row exposure times are:max_sub_row_exposure =min_sub_row_exposure =0x3A0C[7:4]_________________ ×
row_period
16

0x3A0C[3:0]_________________
× row_period
16

OmniVision recommends setting registers 0x3A0C to 0xC4.

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

3-15

3.5 black level calibration (BLC)
The pixel array contains several optically shielded (black) lines. These lines are used as reference for black level
calibration. Black level adjustments can be made with registers 0x4000 through 0x4013.

table 3-7

BLC control functions

address

register namedefault
value

R/W

description

0x4000BLC CTRL00

0x0D

RW

BLC Control 00
Bit[0]:
BLC enable

0x4002BLC CTRL02

0x45

RW

Bit[7]:

Format change enable
BLC update when format changes

Bit[7]:BLC redo enable
Write 1 into it will trigger a BLC redo
N frames begin, N is 0x4003[5:0]
Bit[6]:
BLC freeze
Bit[5:0]: Manual frame number

0x4003BLC CTRL03

0x01

RW

0x4005BLC CTRL05

0x10

RW

BLC always update0:
Normal freeze
1:
BLC always updated

0x4009BLACK LEVEL

0x10

RW

Bit[7:0]: BLC black level target at 10-bit range

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

Bit[1]:

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

3.6 strobe flash
3.6.1 strobe flash control
The strobe signal is programmable. It supports both LED and Xenon modes. The polarity of the pulse can be changed.
The strobe signal is enabled (turned high/low depending on the pulse’s polarity) by requesting the signal via the SCCB
interface. Flash modules are triggered by the rising edge by default or by the falling edge if the signal polarity is changed.
It supports the following flashlight modes (see table 3-8).

table 3-8

flashlight modes

mode

output

AEC / AGC

AWB

xenon

one-pulse

no

no

LED 1

pulse

no

no

LED 2

pulse

no

yes

LED 3

continuous

yes

yes

3.6.1.1 xenon flash control
After a strobe request is submitted, the strobe pulse will be activated at the beginning of the third frame (seefigure 3-7). The third frame will be correctly exposed. The pulse width can be changed in Xenon mode between 1H
and 4H, depending on register 0x3B00[3:2], where H is one row period.

figure 3-7

xenon flash mode
verticalblanking

exposure
time

data
out

stroberequeststrobepulse

request here

correctly
exposedframe

proprietary to OmniVision Technologies

zoomedstrobepulse
1H

PRELIMINARY SPECIFICATION

3660_DS_3_7

version 1.3

3-17

3.6.1.2 LED 1 & 2 modeTwo frames after the strobe request is submitted, the third frame is correctly exposed. The strobe pulse will be
activated only one time if the strobe end request is set correctly (see figure 3-8). If end request is not sent, the strobe
signal is activated intermittently until the strobe end request is set (see figure 3-9). The number of skipped frames
is programmable using registers {0x3A1C, 0x3A1D}.

figure 3-8

LED 1 & 2 mode - one pulse output
frame inis skippedverticalblanking

exposure
time

data
out

stroberequeststart

end

strobepulse
correctly
exposedframe

figure 3-9

request here

the number of skipped frames
is programmable
3660_DS_3_8

LED 1 & 2 mode - multiple pulse output
frame inis skippedverticalblanking

exposure
time

data
out

stroberequeststart
strobepulse
correctly
exposedframe

05.13.2011

request here

PRELIMINARY SPECIFICATION

the number of skipped frames
is programmable

3660_DS_3_9

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

3.6.1.3 LED 3 mode
In LED 3 mode, the strobe signal stays active until the strobe end request is sent (see figure 3-10).

figure 3-10

LED 3 mode

verticalblanking

exposure
time

data
out

stroberequeststart

end

strobesignalcorrectly
exposedframe

table 3-9
address

0x3B00

request hererequest here

3660_DS_3_10

strobe control functions
register name

STROBE CTRL

proprietary to OmniVision Technologies

default
value

0x00

R/W

description

RW

Strobe Control
Bit[7]:
Strobe request ON/OFF
0:
OFF
1:
ON
Bit[6]:
Strobe pulse reverse
Bit[3:2]: width_in_xenon
Bit[1:0]: Strobe mode
00: Xenon
01: LED 1
10: LED 2
11: LED 3

PRELIMINARY SPECIFICATION

version 1.3

3-19

3.7 one time programmable (OTP) memory
The OV3660 supports a maximum of 256 bits of one-time programmable (OTP) memory to store chip identification andmanufacturing information. OTP memory occupies registers 0x3D00 to 0x3D1F. Typically, registers 0x3D00 to 0x3D04
is reserved for OmniVision and registers 0x3D05 to 0x3D1F is for customer use. Detailed read/write sequences areshown below:

3.7.1 OTP write sequence
Write OTP Reg0x3d05-0x3d1f ¡§xx¡¨ //"xx" means the value that customer intends to program
Write Enable:
78 3000 20;Set Bit[4], Reset OTP=078 3004 df;Set Bit[4], Enable OTP clk=1

78 3d20 01;OTP Program Enable

Wait time 50mS
End Write Sequence:
78 3d20 00
78 3004 cf
78 3000 30

3.7.2 OTP read sequenceFirst, write OTP Reg0x3d05-0x3d1f to be "00"
Read Enable:
78 3000 20;Set Bit[4], Reset OTP=078 3004 df;Set Bit[4], Enable OTP clk=1

78 3d21 01;OTP Read Enable

Wait time 50mS
End Read Sequence:
78 3d21 00
78 3004 cf
78 3000 30
Read Reg0x3d00-0x3d1f back. Now, the values are what the customer programmed.

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 3-10
address

OTP control functions (sheet 1 of 2)
register namedefault
value

R/W

description
Bit[7]:
Bit[1]:

0x3D20OTP PROGRAM CTRL

0x00

RW
Bit[0]:
Bit[7]:
Bit[1]:

0x3D21OTP READ CTRL

0x00

RW
Bit[0]:OTP program busy
OTP program speed
0:
Fast
1:
Slow
OTP program enable
OTP read busy
OTP read speed
0:
Fast
1:
Slow
OTP read enable

0x3D00OTP DATA00

0x00

RW

OTP Dump/Load Data00

0x3D01OTP DATA01

0x00

RW

OTP Dump/Load Data01

0x3D02OTP DATA02

0x00

RW

OTP Dump/Load Data02

0x3D03OTP DATA03

0x00

RW

OTP Dump/Load Data03

0x3D04OTP DATA04

0x00

RW

OTP Dump/Load Data04

0x3D05OTP DATA05

0x00

RW

OTP Dump/Load Data05

0x3D06OTP DATA06

0x00

RW

OTP Dump/Load Data06

0x3D07OTP DATA07

0x00

RW

OTP Dump/Load Data07

0x3D08OTP DATA08

0x00

RW

OTP Dump/Load Data08

0x3D09OTP DATA09

0x00

RW

OTP Dump/Load Data09

0x3D0AOTP DATA0A

0x00

RW

OTP Dump/Load Data0a

0x3D0BOTP DATA0B

0x00

RW

OTP Dump/Load Data0b

0x3D0COTP DATA0C

0x00

RW

OTP Dump/Load Data0c

0x3D0DOTP DATA0D

0x00

RW

OTP Dump/Load Data0d

0x3D0EOTP DATA0E

0x00

RW

OTP Dump/Load Data0e

0x3D0FOTP DATA0F

0x00

RW

OTP Dump/Load Data0f

0x3D10OTP DATA10

0x00

RW

OTP Dump/Load Data10

0x3D11OTP DATA11

0x00

RW

OTP Dump/Load Data11

0x3D12OTP DATA12

0x00

RW

OTP Dump/Load Data12

0x3D13OTP DATA13

0x00

RW

OTP Dump/Load Data13

0x3D14OTP DATA14

0x00

RW

OTP Dump/Load Data14

0x3D15OTP DATA15

0x00

RW

OTP Dump/Load Data15

0x3D16OTP DATA16

0x00

RW

OTP Dump/Load Data16

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

3-21

table 3-10

OTP control functions (sheet 2 of 2)

address

register namedefault
value

R/W

description

0x3D17OTP DATA17

0x00

RW

OTP Dump/Load Data17

0x3D18OTP DATA18

0x00

RW

OTP Dump/Load Data18

0x3D19OTP DATA19

0x00

RW

OTP Dump/Load Data19

0x3D1AOTP DATA1A

0x00

RW

OTP Dump/Load Data1a

0x3D1BOTP DATA1B

0x00

RW

OTP Dump/Load Data1b

0x3D1COTP DATA1C

0x00

RW

OTP Dump/Load Data1c

0x3D1FOTP DATA1D

0x00

RW

OTP Dump/Load Data1d

0x3D1EOTP DATA1E

0x00

RW

OTP Dump/Load Data1e

0x3D1FOTP DATA1F

0x00

RW

OTP Dump/Load Data1f

3.8 temperature sensor
The OV3660 supports an on-chip temperature sensor that covers 0~80°C with an error range of 5°C. It can be controlled
through the SCCB interface (see table 3-11). When the temperature is lower than 0°C, the reading will stop at 0°C.

table 3-11

temperature sensor function

address

register namedefault
value

R/W

0x6719TPM CTRL19–

R

05.13.2011

PRELIMINARY SPECIFICATION

description
Bit[7:0]: Measured temperature

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

4-1

4 image sensor processor digital functions
4.1 ISP general controls
The ISP module provides the following functions:•lens correction•

gamma control•

de-noise

•

AWB

•

color matrix•

scaling•

CIP and sharpening

These functions are enabled by registers 0x501D, 0x501F~0x5020, 0x503D, 0x5061~0x5063.

table 4-1
address

0x500005.13.2011

ISP general control registers (sheet 1 of 3)
register name

ISP CONTROL 00

default
value

0x06

PRELIMINARY SPECIFICATION

R/W

description

RW

ISP Control 00
Bit[7]:LENC correction enable0:
Disable1:
EnableBit[5]:
Gamma enable0:
Disable1:
EnableBit[2]:
Black pixel cancellation enable0:
Disable1:
EnableBit[1]:White pixel cancellation enable0:
Disable1:
EnableBit[0]:
Color interpolation (CIP) enable0:
Disable1:
Enableproprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 4-1
address

0x5001

ISP general control registers (sheet 2 of 3)
register name

ISP CONTROL 01

default
value

0x01

R/W

description

RW

ISP Control 01
Bit[7]:
Special Digital Effects (SDE)enable0:Disable1:
EnableBit[5]:
Scale enable0:
Disable1:
EnableBit[2]:
UV average enable0:
Disable1:
EnableBit[1]:
Color matrix enable0:
Disable1:
EnableBit[0]:
Auto white balance (AWB)
enable0:Disable1:
EnableISP Control 03
Bit[2]:
Bin enable0:
Disable1:
EnableBit[0]:
Solarize enable0:
Disable1:
Enable0x5003

ISP CONTROL 03

0x08

RW

0x5004

ISP CONTROL 04

0x08

RW

Bit[3]:

0x5005

ISP CONTROL 05

proprietary to OmniVision Technologies

0x36

RW

Auto size control enable
0:
Manual1:
Auto

ISP Control 05
Bit[6]:AWB bias manual enable0:
Disable1:
EnableBit[5]:AWB bias on enable0:
Disable1:
EnableBit[4]:AWB bias plus enable0:
Disable1:
EnableBit[3]:
Reserved
Bit[2]:LENC bias on enable0:
Disable1:
EnableBit[1]:
GMA bias on enable0:
Disable1:
EnableBit[0]:LENC bias manual enable0:
Disable1:
EnablePRELIMINARY SPECIFICATION

version 1.3

4-3

table 4-1
address

0x501D

0x501F0x5020

ISP general control registers (sheet 3 of 3)
register name

ISP MISC

default
value

0x00

FORMAT MUX CONTROLDITHER CTRL 0

0x03

0x00

R/W

description

RW

Bit[6]:
Bit[5]:
Bit[4]:
Bit[3:0]:RW

RW

SDE AVG manual enable
AWB YUV2CBCR enable
AVG size manual enable
Reserved

Format Mux control
Bit[5]:
Enable option
Bit[4]:
Reserved
Bit[3]:
Format v firstBit[2:0]: Format select000: ISP YUV422
001: ISP RGB
010: ISP dither
011: ISP RAW(DPC)
100: SNR RAW
101: ISP RAW(CIP)
Bit[6]:
Bit[5:4]:
Bit[3:2]:
Bit[1:0]:

Dither mux
R dithering register
G dithering register
B dithering registerBit[7]:

Test enable0:
Test disable
1:
Color bar enableBit[6]:
RollingBit[5]:
Transparent
Bit[4]:
Square black and whiteBit[3:2]: Color bar style
00: Standard 8 color bar
01: Gradual change at verticalmode 1
10: Gradual change at
horizontal
11: Gradual change at verticalmode 2
Bit[1:0]: Test select
00: Color bar
01: Random data
10: Square data
11: Black image

0x503DPRE ISP TEST SETTING 1

0x00

RW

0x5061ISP SENSOR BIAS I–RISP Sensor Bias Input

0x5062

ISP SENSOR GAIN I–R

ISP Real Gain Input High Byte

0x5063

ISP SENSOR GAIN I–R

ISP Real Gain Input Low Byte

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

4.2 lens correction (LENC)
The main purpose of the LENC is to compensate for lens imperfection. According to the area where each pixel is located,the module calculates a gain for the pixel, correcting each pixel with its gain calculated to compensate for the luminanceand color distribution due to lens curvature. Also, the LENC supports the subsample function in both horizontal andvertical directions. LENC is performed in the RGB domain. Luminance channel consists of 36 control points while eachcolor channel consists of 25 control points.

figure 4-1

control points of luminance and color channels

*
G00

*
G10

*
G20

*
G30

*
G40

*
G50

*
G01

*
G11

*

*

*

*

*
G02

*

*

*

*

*

*
G03

*

*
G04

*

*
G05

*

figure 4-2

*

*

*

*

*

*

*

*

*

*

*

*
G55

*
*
*
*
*
B00/R00 B10/R10 B20/R20 B30/R30 B40/R40**
B01/R01 B11/R11

*

*

*

*
B02/R02

*

*

*

*

*
B03/R03

*

*

*

*

*
B04/R04****
B44/R443660_DS_4_1

luminance compensation level calculation

64

LENC gain

OV3660min
LENC gain

SensorGainThreshold1

SensorGainThreshold2
sensor gain

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

3660_DS_4_2

version 1.3

4-5

table 4-2

LENC control registers

address

register namedefault
value

R/W

0x5000ISP CONTROL 00

0x06

RW

description
Bit[7]:

0x58420x58430x58440x58450x58460x58470x58480x584905.13.2011

BR HSCALE

BR HSCAL

0xBD

BR VSCALE

BR VSCALE

G HSCALE

G HSCAL

G VSCALE

G VSCALE

0x00

0x00

0xFE

0x00

0xFC

0x00

0xA9

LENC correction enable0:
Disable1:
EnableRW

Bit[2:0]: br h scale[10:8]
Reciprocal of horizontal step for BR
channel. BR channel in whole image isdivided into 5x5 blocks. The step is used
to point to the border of the adjacent block

RW

Bit[7:0]: br h scale[7:0]
Reciprocal of horizontal step for BR
channel. BR channel in whole image isdivided into 5x5 blocks. The step is used
to point to the border of the adjacent block

RW

Bit[2:0]: br v scale[10:8]
Reciprocal of vertical step for BR channel.
BR channel in whole image is divided into
5x5 blocks. The step is used to point tothe border of the adjacent block

RW

Bit[7:0]: br v scale[7:0]
Reciprocal of vertical step for BR channel.
BR channel in whole image is divided into
5x5 blocks. The step is used to point tothe border of the adjacent block

RW

Bit[2:0]: g h scale[10:8]
Reciprocal of horizontal step for G
channel. G channel in whole image isdivided into 6x6 blocks. The step is used
to point to the border of the adjacent block

RW

Bit[7:0]: g h scale[7:0]
Reciprocal of horizontal step for G
channel. G channel in whole image isdivided into 6x6 blocks. The step is used
to point to the border of the adjacent block

RW

Bit[2:0]: g v scale[10:8]
Reciprocal of vertical step for G channel.
G channel in whole image is divided into
6x6 blocks. The step is used to point tothe border of the adjacent block

RW

Bit[7:0]: g v scale[7:0]
Reciprocal of vertical step for G channel.
G channel in whole image is divided into
6x6 blocks. The step is used to point tothe border of the adjacent block

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

4.3 white balance
The raw R, G, and B values of a white object detected by the OV3660 vary with the spectrum of the light source. The
spectrum of the light source is usually described by "color temperature," which is the surface temperature of a black bodyradiating the equivalent spectrum. The white balance process applies a different gain on each color channel to make thewhite object rendered white in the image.
The OV3660 has a built-in automatic white balance (AWB) algorithm that automatically adjusts the gain of each color
channel to achieve white balance. The AWB algorithm works in either simple or advanced mode. The on-chip AWB
algorithm can also be disabled so a backend processor can control the gain of each channel.

table 4-3
address

white balance registers
register namedefault
value

R/W

0x5001ISP CONTROL 01

1’b1

RW

0x5183AWB CONTROL 03

0x90

RW

RGAIN

0x400

RW

GGAIN

0x400

RW

BGAIN

0x400

RW

0x34000x34010x34020x34030x34040x3405description
Bit[0]:

Auto white balance (AWB) enable0:
Disable (manual AWB mode) where
AWB is controlled by an externalbackend processor
1:
Enable, where Rgain, Ggain, andBgain are updated automaticallyBit[7]:AWB algorithm select0:
Select advanced AWB mode
1:
Select simple AWB modeBit[3:0]: Red channel gain[11:8]
Bit[7:0]: Red channel gain[7:0]
Bit[3:0]: Green channel gain[11:8]
Bit[7:0]: Green channel gain[7:0]
Bit[3:0]: Blue channel gain[11:8]
Bit[7:0]: Blue channel gain[7:0]

4.3.1 simple AWB
The simple AWB algorithm is based on the gray world assumption, meaning the sensor will make the R, G and B averageof all pixels equal to each other by adjusting the gain of each color channel.

4.3.2 advanced AWB
The advanced AWB algorithm adjusts the R, G and B gain based on the color temperature of the ambient light. It will
make the R, G and B channel average of gray pixels equal to each other.
4.3.2.1 advanced AWB calibration
To identify the gray pixel over the color temperature range, the characteristics of the gray object must be calibrated
first using the target lens.

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

4-7

table 4-4
address

0x51860x5187

AWB calibration registers (sheet 1 of 3)
register name

AWB_M_RNG

AWB_L_XRNG

default
value

0x10

0x10

R/W

RW

RW

description
Bit[7:0]: AWB_M_RNG[7:0]
Tolerance of AWB_M_X and AWB_M_Y in
the middle color temperature range.
A tolerance that is too small may result inan unstable AWB, while a tolerance that is
too great may result in an inaccurate AWB.
Bit[7:0]: AWB_L_XRNG[7:0]
Tolerance of AWB_L_X in the low color
temperature range, where AWB_L_X is the
X characteristic of the gray object in the low
color temperature range.
A tolerance that is too small may result inan unstable AWB, while a tolerance that is
too great may result in an inaccurate AWB.
The typical value ranges from 0x08~0x18.

0x5188AWB_H_YRNG

0x10

RW

Bit[7:0]: AWB_H_YRNG[7:0]
Tolerance of AWB_H_Y in the high color
temperature range, where AWB_H_Y is the
Y characteristic of the gray object in thehigh color temperature range.
A tolerance that is too small may result inan unstable AWB, while a tolerance that is
too great may result in an inaccurate AWB.
The typical value ranges from 0x08~0x10.
Bit[7:0]: AWB_M_X[7:0]
X characteristics of the gray object in the
middle color temperature range.
When AWB_M_X increases, gray will shift
towards blue in low color temperature light,
or towards red in high color temperaturelight.

0x5189AWB_M_X

0x40

RW

When AWB_M_X decreases, gray will shift
towards yellow in low color temperaturelight or towards cyan in high color
temperature light.
If AWB_M_X is too big or too small, the
AWB algorithm may fail to identify the grayobject and the result may be unstable andunpredictable.

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 4-4
address

AWB calibration registers (sheet 2 of 3)
register namedefault
value

R/W

description
Bit[7:0]: AWB_M_Y[7:0]
Y characteristics of the gray object in the
middle color temperature range.
When AWB_M_Y increases, gray will shift
towards blue in low color temperature light,
or towards red in high color temperaturelight.

0x518AAWB_M_Y

0x40

RW

When AWB_M_Y decreases, gray will shift
towards yellow in low color temperaturelight or towards cyan in high color
temperature light.
If AWB_M_Y is too big or too small, the
AWB algorithm may fail to identify the grayobject and the result may be unstable andunpredictable.
Bit[7:0]: AWB_L_K
K characteristic of the gray object in the low
color temperature range

0x518BAWB_L_K

0x00

RW

When AWB_L_K increases/decreases, thegray color will shift slightly toward
yellow/blue, respectively, in the low color
temperature range.
Bit[7:0]: AWB_H_K
K characteristic of the gray object in thehigh color temperature range

0x518CAWB_H_K

0x00

RW

When AWB_H_K increases/decreases, thegray color will shift slightly toward cyan/red,
respectively, in the high color temperature
range.
Bit[7:0]: AWB_H_LMT[7:0]0x518D

0x518EAWB_H_LMTAWB_L_LMT

proprietary to OmniVision Technologies

0x00

0x00

RW

RW

Lower limit of AWB_H_X, where AWB_H_X
is the X characteristic of the gray object in
the high color temperature range.
A smaller AWB_H_LMT value covers agreater upper limit of the color temperature;
however, it also results in a less accurate
white balance.
Bit[7:0]: AWB_L_LMT[7:0]
Lower limit of AWB_L_Y, where AWB_L_Y
is the Y characteristic of the gray object in
the low color temperature range.
A smaller AWB_L_LMT value covers asmaller lower limit of the color temperature;
however, it also results in a less accurate
white balance.

PRELIMINARY SPECIFICATION

version 1.3

4-9

table 4-4

AWB calibration registers (sheet 3 of 3)

address

register namedefault
value

R/W

0x518FAWB_CTRL_D

0x20

RW

Bit[7:0]: AWB_CTRL_D
Day split

0x5190AWB_CTRL_A

0x20

RW

Bit[7:0]: AWB_CTRL_A
A splitRW

Bit[7:0]: AWB_DATA_ULMTPixels with an output value greater than
AWB_DATA_ULMT are excluded from the
AWB statistics

RW

Bit[7:0]: AWB_DATA_LLMT
Pixels with an output value smaller than
AWB_DATA_LLMT are excluded from the
AWB statistics

0x51910x5192

AWB_DATA_ULMTAWB_DATA_LLMT

0xFF

0x00

description

4.3.2.2 AWB control

table 4-5
address

AWB control (sheet 1 of 2)
register namedefault
value

R/W

description

0x5181AWB_STEP

0x58

RW

Bit[7:4]: AWB_STABLE_RNG_IN[3:0]
AWB will adjust the gain of each color
channel until the difference between eachchannel is no more thanAWB_STABLE_RNG_IN[3:0]
Bit[3:0]: AWB_STABLE_RNG_OUT[3:0]
AWB will start to adjust the gain once thedifference between each channel is greaterthan AWB_STABLE_RNG_OUT[3:0]0:Disable (manual AWB mode) where
AWB is controlled by an externalbackend processor
1:
Enable, where Rgain, Ggain, andBgain are updated automatically

0x5182AWB_UPDATE

0x11

RW

Bit[7:0]: Range of red channel gain
{AWB_RGAIN_RNG_[3:0], 4’h0} < RGain <{AWB_RGAIN_RNG[7:4], 4’hF}

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table 4-5
address

AWB control (sheet 2 of 2)
register namedefault
value

R/W

description
Bit[7]:

0x5183AWB_CTRL02

0x90

RW

AWB mode0:
Select advanced AWB
1:
Select simple AWB
Bit[5]:
Green channel gain enable
Green channel gain must be enabled to
avoid false color of bright objects in reddish
or bluish light.
0:
Only adjust red and blue channel gain
1:
Adjust red, green and blue channel
gain
Bit[4]:
Fast adjustment enable in simple AWB
mode0:
Disable, AWB speed is slow
1:
Enable, AWB adjustment is fast forfast scene changes
Bit[3:2]: AWB statistics window selection
00: Full image
01: Exclude 8 rows and columns at each
image boundary
10: Exclude 1/8 of the total rows andcolumns at each image boundary
11: Exclude 1/4 of the total rows andcolumns at each image boundaryBit[1:0]: AWB debug control
Changing these register bits is notrecommended.

0x5184AWB_CTRL03

0x25

RW

Bit[7:0]: AWB debug control
Changing this register value is notrecommended.

4.3.2.3 advanced AWB tuning guidelines
Before starting the calibration, the final lens shading correction (if needed) should be applied.
1.

Set the camera to full resolution raw format.

2.

Disable the AWB and set the R, G, and B gain to 1x.

3.

Apply the final lens shading correction setting.

4.

Capture an image of a uniform gray scene (e.g., gray 18 chart in raw data format under A (color temperaturearound 2950K), CWF (color temperature around 4150K), and D65 (color temperature around 6500K) light.

5.

Run the OVT AWB calibration tool.

6.

Select the image following the guide and generate the setting.

7.

Apply the normal YUV setting with the AWB setting and check the AWB performance under different light
conditions.

The procedure shown above are the basic steps required to adjust the OVT Advanced AWB. For a more detailed
procedure, refer to the OVTATool User Guide.

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4-11

4.3.3 AWB stable range and gain range
From an unstable state, the AWB algorithm will stop to adjust the AWB gain when the difference between each channel
is no more than the threshold, AWB_STABLE_RNG_IN[3:0]. From a stable state, the AWB algorithm will start to adjust
gain once the difference between each channel is greater than the threshold, AWB_STABLE_RNG_OUT[3:0].
The R, G and B gain can be further limited by register AWB_RGAIN_RNG, AWB_GGAIN_RNG and AWB_BGAIN_RNG,
respectively.

table 4-6
address

AWB stable range registers
register namedefault
value

R/W

description

0x5185AWB_STABLE_RNG

0x24

RW

Bit[7:4]: AWB_STABLE_RNG_IN[3:0]
AWB will adjust the gain of each color
channel until the difference between eachchannel is no more thanAWB_STABLE_RNG_IN[3:0]
Bit[3:0]: AWB_STABLE_RNG_OUT[3:0]
AWB will start to adjust the gain once thedifference between each channel is greaterthan AWB_STABLE_RNG_OUT[3:0]0:Disable (manual AWB mode) where
AWB is controlled by an externalbackend processor
1:
Enable, where Rgain, Ggain, andBgain are updated automatically

0x5193AWB_RGAIN_RNG

0x00

RW

Bit[7:0]: Range of red channel gain
{AWB_RGAIN_RNG_[3:0], 4’h0} < RGain <{AWB_RGAIN_RNG[7:4], 4’hF}

0x5194AWB_GGAIN_RNG

0x00

RW

Bit[7:0]: Range of green channel gain
{AWB_GGAIN_RNG_[3:0], 4’h0} < GGain <{AWB_GGAIN_RNG[7:4], 4’hF}

0x5195AWB_BGAIN_RNG

0x00

RW

Bit[7:0]: Range of blue channel gain
{AWB_BGAIN_RNG_[3:0], 4’h0} < BGain <{AWB_BGAIN_RNG[7:4], 4’hF}

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

4.4 gamma
The main purpose of the Gamma (GMA) function is to accommodate for the non-linear characteristics of the display
device. The gamma curve is constructed by 16 linear segments as shown in figure 4-3.

figure 4-3

gamma curve
SLOP

255
GAMST15GAMST14GAMSP16GAMSP15GAMST3GAMSP3GAMST2GAMSP2GAMST1

255

XREF15

XREF14

XREF3

XREF2

GAMSP1XREF1OV36603660_DS_4_3

There are sixteen gamma control registers, including fifteen curve starting points and one highest slope. All of thesecontrol registers are configurable.
The slope of the highest segment (register 0x5490) is calculated by the following equation:

SLOPE = register 0x5490[7:0] = (255 – GAM15[7:0] + 1) × 40/30
Note that the gamma starting point and the highest slope should be matched; otherwise, there will be a discontinuous
point in the gamma curve. refer to table 4-7 for the correspondence between the gamma curve and the control registers.

table 4-7

gamma parameters and corresponding registers
gamma vertical starting point

horizontal reference point

nameregister

namevalue (decimal)

GAM1

0x5481

XREF1

4

GAM2

0x5482

XREF2

8

GAM3

0x5483XREF316proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

4-13

table 4-7

gamma parameters and corresponding registers
gamma vertical starting point

horizontal reference point

nameregister

namevalue (decimal)

GAM4

0x5484

XREF4

32

GAM5

0x5485

XREF5

40

GAM6

0x5486

XREF6

48

GAM7

0x5487

XREF7

56

GAM8

0x5488

XREF8

64

GAM9

0x5489

XREF9

72

GAM10

0x548A

XREF1080

GAM110x548B

XREF1196

GAM120x548CXREF12112

GAM130x548DXREF13144

GAM140x548EXREF14176

GAM15

0x548F

XREF15208

highest segment slope

0x5490table 4-8

gamma control registers (sheet 1 of 2)

address

register namedefault
value

R/W

0x5000ISP CONTROL 00

0x06

RW

0x5481

GAM1

0x26

RW

Bit[7:0]: Gamma1

0x5482

GAM2

0x35

RW

Bit[7:0]: Gamma2

0x5483

GAM3

0x48

RW

Bit[7:0]: Gamma3

0x5484

GAM4

0x63

RW

Bit[7:0]: Gamma4

0x5485

GAM5

0x6E

RW

Bit[7:0]: Gamma5

0x5486

GAM6

0x77

RW

Bit[7:0]: Gamma6

0x5487

GAM7

0x80

RW

Bit[7:0]: Gamma7

0x5488

GAM8

0x88

RW

Bit[7:0]: Gamma8

0x5489

GAM9

0x8F

RW

Bit[7:0]: Gamma9

description
Bit[5]:

05.13.2011

PRELIMINARY SPECIFICATION

Gamma enable0:
Disable GMA
1:
Enable GMA

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 4-8

gamma control registers (sheet 2 of 2)

address

register namedefault
value

R/W

0x548A

GAM10

0x96

RW

Bit[7:0]: Gamma10

0x548B

GAM11

0xA3

RW

Bit[7:0]: Gamma11

0x548C

GAM12

0xAF

RW

Bit[7:0]: Gamma12

0x548D

GAM13

0xC5

RW

Bit[7:0]: Gamma13

0x548E

GAM14

0xD7

RW

Bit[7:0]: Gamma14

0x548F

GAM15

0xE8

RW

Bit[7:0]: Gamma15

0x5490

SLOPE

0x0F

RW

Bit[7:0]: Slope of the highest segment

description

4.5 defect pixel cancellation (DPC)
Due to processes and other reasons, pixel defects in the sensor array will occur.
The value of the defect pixel usually has an abrupt change compared to normal pixels. The DPC function is designed torecover these white or black pixels while maintaining image quality.

table 4-9
address

DPC control registers
register namedefault
value

R/W

description
Bit[2]:

0x5000ISP CONTROL 00

0x06

RW

Bit[1]:

Black pixel cancellation enable0:
Disable1:
EnableWhite pixel cancellation enable0:
Disable1:
Enable4.6 sharpness control and de-noise
The OV3660 supports built-in sharpness and de-noise control.
For sharpness, the OV3660 allows the user to select the level of edge enhancement. The sensor first detects the edgesof an image and through a complex selection process, the OV3660 amplifies the edges to enhance the sharpness of theimage.
The OV3660 supports both auto and manual mode control. If auto mode is selected, the sensor monitors the brightness
and noise levels of the image and, based on these two statistics, adjusts the magnitude of the sharpness automatically.
If manual mode is selected by setting register bit 0x5308[6] = 1, the sharpness level can be manually controlled byregister 0x5302.

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PRELIMINARY SPECIFICATION

version 1.3

4-15

The examples below show sample settings for auto sharpness, sharpness off, and five different manual sharpness
levels.
@@ Sharpness Auto
78 5308 00 40
78 5300 08 ;8x78 5301 30
78 5302 10
78 5303 00
78 5309 08
78 530a 30
78 530b 04
78 530c 06@@ Sharpness OFF
78 5308 40 40
78 5302 00@@ Sharpness 1
78 5308 40 40
78 5302 02@@ Sharpness 2
78 5308 40 40
78 5302 04@@ Sharpness 3
78 5308 40 40
78 5302 08@@ Sharpness 4
78 5308 40 40
78 5302 0c@@ Sharpness 5
78 5308 40 40
78 5302 10

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

To reduce noise, the OV3660 supports both auto and manual noise suppression modes. If auto mode is selected, theregister value of de-noise level is automatically updated by the sensor. If manual mode is selected by setting register bit
0x5308[4] = 1, the user can manually adjust the de-noise level using register 0x5306.
The examples below show sample settings for auto de-noise and manual de-noise control with five different de-noise
strengths.
@@ De-Noise Auto
78 5308 00 10
78 5304 08 ;8x78 5305 30
78 5306 08
78 5307 16@@ De-Noise 078 5306 00
78 5308 10 10@@ De-Noise 1
78 5306 02
78 5308 10 10@@ De-Noise 2
78 5306 04
78 5308 10 10@@ De-Noise 3
78 5306 08
78 5308 10 10@@ De-Noise 478 5306 0c
78 5308 10 10@@ De-Noise 578 5306 10
78 5308 10 10

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PRELIMINARY SPECIFICATION

version 1.3

4-17

table 4-10

sharpness and de-noise control registers

address

register namedefault
value

R/W

description

0x5300SHARPENMT THRESHOLD 1

0x08

RW

Sharpen MT Threshold 10x5301SHARPENMT THRESHOLD 2

0x48

RW

Sharpen MT Threshold 20x5302SHARPENMT OFFSET1

0x18

RW

Sharpen MT Offset1(Y edge mt manual setting when register
0x5308[6] = 1)0x5303

SHARPENMT OFFSET2

0x0E

RW

Sharpen MT Offset2

0x5304

DNS THRESHOLD 1

0x08

RW

DNS Threshold 10x5305

DNS THRESHOLD 2

0x48

RW

DNS Threshold 20x5306

DNS OFFSET1

0x09

RW

DNS Offset1(DNS threshold manual setting whenregister 0x5308[4] = 1)0x5307

DNS OFFSET2

0x16

RW

DNS Offset2

0x5308EDGE DNS CTRL

0x25

RW

0x5309SHARPENTH THRESHOLD 1

0x08

RW

Sharpen TH Threshold 10x530ASHARPENTH THRESHOLD 2

0x48

RW

Sharpen TH Threshold 20x530BSHARPENTH OFFSET1

0x04

RW

Sharpen TH Offset1(sharpen threshold manual setting whenregister 0x5308[6] = 1)0x530CSHARPENTH OFFSET2

0x06

RW

Sharpen TH Offset2

0x530DEDGE MT AUTO–

R

Edge MT Auto Read

0x530EDNS THRESHOLD AUTO–R

DNS Threshold Auto Read

0x530FSHARPEN THRESHOLD
AUTO

–

R

Sharpen Threshold Auto Read

05.13.2011

PRELIMINARY SPECIFICATION

Bit[6]:
Edge MT manual enable
Bit[4]:
DNS manual enableBit[2:0]: Threshold for BR sharpen

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

4.7 color matrix (CMX)The OV3660 supports a 3x3 color matrix. The general purpose of the color matrix is to convert color space from the RGB
domain to the YUV domain. However, for OmniVision, the CMX is not solely for color space conversion, but also forcrosstalk reduction. Therefore, during conversion, a color matrix should be applied first to eliminate crosstalk, which isnote

Color matrix tuning tool
is available as part of
the OVTATool. Pleasecontact your local FAE
for the latest version of
the tool.

generally induced by the microlens and the color filter. The calculation is shown below:[RGB] = [color correction] × [R0G0B0]
where [R0G0B0] is the primitive response from the sensor without any correction and [RGB] is the RGB response after
OmniVision’s color correction.
Then, the corrected RGB signal can be converted to YUV color space by the RGB-to-YUV conversion matrix:[YUV] = [RGB-to-YUV conversion matrix] × [RGB]
Combining the equation, we get:

[YUV] = [RGB-to-YUV conversion matrix] × [color correction] × [R0G0B0][YUV] = [combined matrix] × [R0G0B0]
The combined matrix can be described as:[

cmx1[combined matrix] = cmx4
cmx7

cmx2
cmx5
cmx8

cmx3
cmx6
cmx9

][
=

reg0x5381
reg0x5384
reg0x5387

reg0x5382
reg0x5385
reg0x5388

reg0x5383
reg0x5386
reg0x5389]

The sign bit is assigned by registers 0x538B and 0x538A.
Register 0x538B[0] → sign bit of CMX1
Register 0x538B[1] → sign bit of CMX2
Register 0x538B[2] → sign bit of CMX3
Register 0x538B[3] → sign bit of CMX4
Register 0x538B[4] → sign bit of CMX5
Register 0x538B[5] → sign bit of CMX6

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version 1.3

4-19

Register 0x538B[6] → sign bit of CMX7
Register 0x538B[7] → sign bit of CMX8
Register 0x538A[0] → sign bit of CMX9

table 4-11

CMX control registers

address

register namedefault
value

R/W

0x5001ISP CONTROL 01

0x01

RW

0x5381

CMX1

0x20

RW

Bit[7:0]: CMX1 for Y

0x5382

CMX2

0x64

RW

Bit[7:0]: CMX2 for Y

0x5383

CMX3

0x08

RW

Bit[7:0]: CMX3 for Y

0x5384

CMX4

0x30

RW

Bit[7:0]: CMX4 for U

0x5385

CMX5

0x90

RW

Bit[7:0]: CMX5 for U

0x5386

CMX6

0xC0

RW

Bit[7:0]: CMX6 for U

0x5387

CMX7

0xA0

RW

Bit[7:0]: CMX7 for V

0x5388

CMX8

0x98

RW

Bit[7:0]: CMX8 for V

0x5389

CMX9

0x08

RW

Bit[7:0]: CMX9 for V

0x538ACMXSIGN

0x01

RW

CMXsignBit[0]:CMX9 sign

RW

CMXsignBit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:CMX8 sign
CMX7 sign
CMX6 sign
CMX5 sign
CMX4 sign
CMX3 sign
CMX2 sign
CMX1 signdescription
Bit[1]:

0x538BCMXSIGN

0x98

Color matrix enable0:
Disable1:
Enable4.8 auto color saturation adjust
The main function of the auto color saturation adjust is to adjust the U/V channel value according to sensor gain. It
supports both manual and auto modes.

4.8.1 manual mode
By setting 0x5580[1] to 1 and 0x5588[6] to 1, auto color saturation adjust is controlled only by register 0x5583[7:0] and0x5584[7:0] for U and V gains.

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

4.8.2 auto mode
When the auto color saturation adjust is set for auto mode (0x5580[1]=1 and 0x5588[6]=0), the auto color saturation
adjust curve parameters (see figure 4-4) should be entered into the corresponding registers. The auto color saturation
adjust parameters, auto color saturation adjust threshold1, auto color saturation adjust threshold2, and offset low, offset
high should be entered into the registers to set the curve. To get these values, first set the values of auto color saturation
adjust threshold1, auto color saturation adjust threshold2, offset low and offset high. Then, calculate the values of a andk as follows:k = (offset high – offset low) / (UV adj th2 – UV adj th1)
a = offset high + (offset high – offset low) / (UV adj th2 – UV adj th1)
Registers to be changed:•

auto color saturation adjust threshold1[8:0] = registers 0x5589[7:0]•

auto color saturation adjust threshold2[8:0] = registers {0x558A[0], 0x558B[7:0]}•

offset high = register 0x5583[7:0] (when 0x5580[1]=1 and 0x5588[6]=0)•

offset low = register 0x5584[7:0] (when 0x5580[1]=1 and 0x5588[6]=0)

figure 4-4

auto color saturation adjust graphoffset_highauto color saturation adjust in

OV3660y = a - kx

offset_low

auto color saturation
adjust threshold1

auto color saturation
adjust threshold2
AGC gain

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3660_DS_4_4

version 1.3

4-21

4.9 special digital effects (SDE)
The special digital effects (SDE) include b&w, sepia, greenish, bluish, reddish and negative. The SDE of the OV3660
also allows the user to adjust contrast, brightness, saturation, and hue. For normal, b&w, bluish, sepia, reddish, greenish
and negative, set register bit 0x5001[7] = 1 to enable these special effects. Set register bit 0x5001[7] = 1 to fix UV values
or select negative effect. Then, manually change the values of the two chrominance registers, U and V. See table 4-12
for sample images and register settings.

table 4-12
effectSDE image effects (sheet 1 of 2)
sample image

register settings
Disable SDE by setting
register 0x5001[7]=0Turn off fixed UV by setting
register 0x5580[4]=0 andregister 0x5580[3]=0

normalSet U value by setting register
0x5583=0x40 (default)
Set V value by setting register
0x5583=0x40 (default)
Enable SDE by setting
register 0x5001[7]=1Turn on fixed UV by setting
register 0x5580[4]=1 andregister 0x5580[3]=1

b&w

Set U value by setting register
0x5583=0x80
Set V value by setting register
0x5583=0x80
Enable SDE by setting
register 0x5001[7]=1Turn on fixed UV by setting
register 0x5580[4]=1 andregister 0x5580[3]=1

bluishSet U value by setting register
0x5583=0xF0
Set V value by setting register
0x5583=0x68

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 4-12
effectSDE image effects (sheet 2 of 2)
sample image

register settings
Enable SDE by setting
register 0x5001[7]=1

sepia

Turn on fixed UV by setting
register 0x5580[4]=1 andregister 0x5580[3]=1Set U value by setting register
0x5583=0x40
Set V value by setting register
0x5583=0xA0
Enable SDE by setting
register 0x5001[7]=1

reddishTurn on fixed UV by setting
register 0x5580[4]=1 andregister 0x5580[3]=1Set U value by setting register
0x5583=0x80
Set V value by setting register
0x5583=0xC0
Enable SDE by setting
register 0x5001[7]=1

greenishTurn on fixed UV by setting
register 0x5580[4]=1 andregister 0x5580[3]=1Set U value by setting register
0x5583=0x60
Set V value by setting register
0x5583=0x60

negative

proprietary to OmniVision Technologies

Enable SDE by setting
register 0x5001[7]=1
Enable negative effect bysetting register 0x5580[6]=1

PRELIMINARY SPECIFICATION

version 1.3

4-23

For contrast, brightness, saturation, and hue, see table 4-13 for applicable register settings.

table 4-13
effectimage contrast/brightness/saturation/hue control
level/
degreesenable bit

register 0x5586=0x10; register 0x5587=0x10

level -2
Enable SDE by setting
register 0x5001[7]=1level -1
contrast

level 0

Enable contrast control by
setting register 0x5580[2]=1level +1

Set register 0x5588=0x01

register 0x5586=0x28; register 0x5587=0x18

level -2

register 0x5587=0x30; register 0x5588=0x08
Enable SDE by setting
register 0x5001[7]=1level 0

Enable contrast control by
setting register 0x5580[2]=1

register 0x5587=0x20; register 0x5588=0x08
register 0x5587=0x00; register 0x5588=0x00
register 0x5587=0x20; register 0x5588=0x00

level +2

register 0x5587=0x30; register 0x5588=0x00

level -2

register 0x5583=0x10; register 0x5588=0x10

level -1

Enable SDE by setting
register 0x5001[7]=1level 0

Enable saturation control by
setting register 0x5580[1]=1level +1

hue

register 0x5586=0x20; register 0x5587=0x00

register 0x5586=0x30; register 0x5587=0x20

level +1

saturation

register 0x5586=0x18; register 0x5587=0x18

level +2

level -1
brightness

register control

register 0x5583=0x20; register 0x5588=0x20
register 0x5583=0x40; register 0x5588=0x40
register 0x5583=0x60; register 0x5588=0x60

level +2

register 0x5583=0x70; register 0x5588=0x70-60 degrees

register 0x5581=0x40; register 0x5582=0x6F;
register 0x558A=0x02-30 degrees

register 0x5581=0x6F; register 0x5582=0x40;
register 0x558A=0x02

Enable SDE by setting
register 0x5001[7]=1

0 degree

Enable hue control by setting
register 0x5580[0]=1

register 0x5581=0x80; register 0x5582=0x00;
register 0x558A=0x01

30 degrees

register 0x5581=0x6F; register 0x5582=0x40;
register 0x558A=0x01

60 degrees

register 0x5581=0x40; register 0x5582=0x6F;
register 0x558A=0x01

The register control values shown above are presented as examples. The user can determine the appropriate level ofcontrol according to their requirements. See table 4-14 for detailed descriptions of SDE-related registers.

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PRELIMINARY SPECIFICATION

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 4-14

SDE control registers

address

register namedefault
value

R/W

0x5001ISP CONTROL 01

0x01

RW

0x5581

SDE CTRL1

0x80

RW

Bit[7:0]: Hue cos coefficient

0x5582

SDE CTRL2

0x00

RW

Bit[7:0]: Hue sin coefficient

RW

Bit[7:0]: Saturation U when 0x5580[1]=1 and
0x5588[6]=1, max value for auto color
saturation adjust when 0x5580[1]=1 and
0x5588[6]=0; or fixed U when 0x5580[3]=1

description
Bit[7]:

0x5583

SDE CTRL3

0x40

Special digital effect enable0:
Disable1:
Enable0x5584

SDE CTRL4

0x40

RW

Bit[7:0]: Saturation V when 0x5580[1]=1 and
0x5588[6]=1, min value for auto color
saturation adjust when 0x5580[1]=1 and
0x5588[6]=0; or Vreg when 0x5580[4]=10x5585

SDE CTRL5

0x00

RW

Bit[7:0]: Yoffset for contrast when 0x5044[3]=1; orfixed Y when 0x5580[7]=10x5586

SDE CTRL6

0x20

RW

Bit[7:0]: Y gain for contrast

0x5587

SDE CTRL7

0x00

RW

Bit[7:0]: Y bright for contrast
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:

0x5588SDE CTRL8

0x01

RW

Bit[2]:

Bit[1]:
Bit[0]:

Auto color saturation adjust manual enable
Sign5 for hue V, cos
Sign4 for hue U, cos
Sign3 Y bright sign for contrast
0:
Keep Y bright sign
1:
Negative Y bright sign
Sign2
Y offset sign for contrast when 0x5044[3]=10:
Keep Y offset sign
1:
Negative Y offset sign
Sign1 for hue V, sin
Sign0 for hue U, sin

Bit[7:0]: Auto color saturation adjust threshold 1
Valid when 0x5580[1]=10x5589SDE CTRL9

0x01

RW

0x558A

SDE CTRL10

0x01

RW

0x558BSDE CTRL11

0xFF

RW

Bit[7:0]: Auto color saturation adjust threshold 2[7:0]
Valid when 0x5580[1]=10x558CSDE CTRL12–

R

Bit[7:0]: Auto color saturation adjust value read out

proprietary to OmniVision Technologies

Bit[0]:

Auto color saturation adjust threshold 2[8]Valid when 0x5580[1]=1

PRELIMINARY SPECIFICATION

version 1.3

5-1

5 image sensor output interface digital functions
5.1 compression engine
5.1.1 compression mode 1 timing
The whole frame has only one line. PCLK will be gated when there is no valid image data transmitted.

figure 5-1

compression mode 1 timing

HREF

PCLK
3660 DS 5 1

5.1.2 compression mode 2 timing
Compression data is transmitted with programmable line width. PCLK is free running. The last line may contain dummy
data to match the width. By default, the line number varies from frame to frame. The user can set register 4600[5](0x4600) to ensure every frame has a fixed line number (programmable).

figure 5-2

compression mode 2 timing

HREF

VSYNC
3660_DS_5_2

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

5.1.3 compression mode 3 timing
Compression data is transmitted with programmable width. The last line width maybe different from the other line (there
is no dummy data). In each frame, the line number may be different.

figure 5-3

compression mode 3 timing

HREF

VSYNC
3660_DS_5_3

5.1.4 compression mode 4 timing
The width and height are fixed in each frame. The first two bytes are valid data length in every line, followed by valid
image data. Dummy data (0xFF) may be used as padding at each line end if the current valid image data is less than theline width.

figure 5-4

compression mode 4 timing
VSYNC to HREF delay

VSYNC

HREF

PCLK
valid data
lengthD[9:2]

Len_h

Len_l

valid data
data

data

data

dummy data
data

FF

FF

FF

FF

3660_DS_5_4

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PRELIMINARY SPECIFICATION

version 1.3

5-3

5.1.5 compression mode 5 timing
The width and height are fixed in each frame. Every line begins with valid image data. Dummy data may be used as
padding at each line end if the current valid image data is less than the line width. The last two bytes of every line is valid
data length.

figure 5-5compression mode 5 timing
VSYNC to HREF delay

VSYNC

HREF

PCLK

valid data
D[9:2]

data

data

data

valid data
lengthdummy data
data

FF

FF

FF

FF

Len_h

Len_l
3660_DS_5_5

5.1.6 compression mode 6 timing
The width and height are fixed in each frame. Every line begins with valid image data. Dummy data may be used as
padding at each line end if the current valid image data less than the line width.

figure 5-6

compression mode 6 timing
VSYNC to HREF delay

VSYNC

HREF

PCLK

valid data
D[9:2]

data

data

data

data

FF

FF

FF

FF

FF

FF

dummy data
3660_DS_5_6

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color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

5.1.7 compression mode control

table 5-1

compression control registers (sheet 1 of 2)

address

register namedefault
value

R/W

description

0x3821COMPRESSION ENABLE

0x00

RW

Bit[5]:

Compression enableBit[5]:

Compression output fixed heightenable0:
In compression mode2
Compression height isdifferent in each frame
1:
In compression mode2
Compression height isfixed in each frame

0x4600

VFIFO CTRL00

0x80

RW

0x4602

VFIFO HSIZE

0x04

RW

Compression Output Width High Byte

0x4603

VFIFO HSIZE

0x00

RW

Compression Output Width Low Byte

0x4604

VFIFO VSIZE

0x03

RW

Compression Output Height High Byte

0x4605VFIFO VSIZE

0x00

RW

Compression Output Height Low Byte

0x460CVFIFO CTRL0C

0x20

RW

0x460D

VFIFO CTRL0D

0x00

RW

Bit[7:4]: Compression dummy data pad
speed
Compression Pad Dummy Data

0x4713COMPRESSION MODE
SELECT

0x02

RW

Bit[2:0]: Compression mode select001: Compression mode 1
010: Compression mode 2011: Compression mode 3
100: Compression mode 4
101: Compression mode 5
110: Compression mode 6

0x471FDVP HREF CTRL

0x40

RW

HREF Minimum Blanking in Compression
Mode230x4723

DVP CTRL23

0x00

RW

DVP Compression Mode456 Skip Line
NumberBit[7]:

0x4400COMPRESSION CTRL00

proprietary to OmniVision Technologies

0x81

RW

input_format
0:
YUV4201:
YUV422
Bit[6:0]: JFIFO read speed control

PRELIMINARY SPECIFICATION

version 1.3

5-5

table 5-1
address

0x4401compression control registers (sheet 2 of 2)
register name

COMPRESSION CTRL01

default
value

0x01

R/W

RW

description
Bit[7:4]: SFIFO output buffer speed
control
Bit[3]:
Read SRAM enable whenblanking
0:
Disable1:
EnableBit[2]:
Read SRAM at first blanking0:
Disable1:
EnableBit[1:0]: SFIFO read speed control
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:

0x4404COMPRESSION CTRL04

0x24

RW

jfifo_pwrdn
SFIFO pwrdn
Header output enable
Enable gated clock0:
Disable gated clock
1:
Enable gated clock
Bit[3]:
Substitute 0xFF to 0xFE in QT
Bit[2:0]: Quantization rounding
Bias: set value = Bias/8

0x4417

JFIFO OVERFLOW–R

Bit[0]:

05.13.2011

PRELIMINARY SPECIFICATIONJFIFO overflow indicator

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OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

5.2 parallel digital video port (DVP)
5.2.1 overview
The parallel DVP provides 10-bit parallel data output in all formats supported and extended features including:•compression mode•

HSYNC mode•

CCIR656 mode•

test pattern output

table 5-2

parallel DVP control registers (sheet 1 of 3)

address

register namedefault
value

R/W

description

0x4709

DVP VSYNC WIDTH0

0x02

RW

VSYNC WIDTH Line Unit

0x470A

DVP VSYNC WIDTH1

0x00

RW

VSYNC WIDTH PCLK Unit High Byte

0x470B

DVP VSYNC WIDTH2

0x01

RW

VSYNC WIDTH PCLK Unit Low Byte

0x4711

PAD LEFT CTRL

0x00

RW

HSYNC Mode Left Padding Pixel CountAdd padding data at start of a line

0x4712

PAD RIGHT CTRL

0x00

RW

HSYNC Mode Right Padding Pixel CountAdd padding data at end of a line

RW

Bit[2:0]: Compression mode select001: Compression mode 1
010: Compression mode 2011: Compression mode 3
100: Compression mode 4
101: Compression mode 5
110: Compression mode 6

0x4713COMPRESSION MODE
SELECT

0x02

0x4715656 DUMMY LINE

0x00

RW

Bit[3:0]: CCIR656 dummy line
numberControl dummy line number
at beginning of the frame

0x4719CCIR656 CTRL

0x01

RW

Bit[1:0]: CCIR656 EAV/SAV option

0x471BHSYNC CTRL00

0x02

RW

Bit[0]:

proprietary to OmniVision Technologies

HSYNC mode enable

PRELIMINARY SPECIFICATION

version 1.3

5-7

table 5-2
address

parallel DVP control registers (sheet 2 of 3)
register namedefault
value

R/W

description

0x471D

DVP VSYNC CTRL

0x01

RW

Bit[2]:
vsync_sel1_clr
Bit[1:0]: vsync_mode
00: VSYNC positive edge
trigger by end of field,
negative edge trigger bystart of frame
01: VSYNC positive edge
trigger by end of frame,
the width define byregister
10: VSYNC positive edge
trigger by start of field,
the width define byregister

0x471FDVP HREF CTRL

0x40

RW

HREF Minimum Blanking in Compression
Mode230x4721VERTICAL STARTOFFSET

0x01

RW

Bit[3:0]: Vertical start delay between
video output and video input

0x4722VERTICAL END OFFSET

0x00

RW

Bit[3:0]: Vertical end delay between
video output and video input

0x4723

DVP CTRL23

0x00

RW

DVP Compression Mode456 Skip Line
NumberBit[7]:SYNC code selection
0:
Auto generate sync
code
1:
Sync code from registersetting 0x4732~4735
Bit[6]:
F value in CCIR656 SYNC
code when fixed f value
Bit[5]:
Fixed f value
Bit[4:3]: Blank toggle data options
00: Toggle data is
1'h040/1'h200
01: Use register setting
0x4736~0x4738
10: Blanking data always
keep 0Bit[2]:
Debug modeBit[1]:
Clip data disable
Bit[0]:CCIR656 mode enable

0x4730CCIR656 CTRL00

0x00

RW

0x4731

CCIR656 CTRL01

0x01

RW

0x4732

CCIR656 FS

0x01

RW

CCIR656 SYNC Code Frame Start

0x4733

CCIR656 FE

0x0F

RW

CCIR656 SYNC Code Frame End

05.13.2011

PRELIMINARY SPECIFICATION

Bit[0]:

Blanking toggle data order
optionproprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 5-2

parallel DVP control registers (sheet 3 of 3)

address

register namedefault
value

R/W

description

0x4734

CCIR656 LS

0x00

RW

CCIR6656 SYNC Code Line Start

0x4735CCIR656 LE

0x00

RW

CCIR656 SYNC Code Line End

0x4736CCIR656 CTRL6

0x00

RW

Bit[3:2]: Toggle data0[9:8]
Bit[1:0]: Toggle data1[9:8]0x4737CCIR656 CTRL7

0x00

RW

Bit[7:0]: Toggle data0[7:0]0x4738CCIR656 CTRL8

0x00

RW

Bit[7:0]: Toggle data1[7:0]
Bit[5]:

0x4740

POLARITY CTRL00

0x20

RW

Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:

Bit[0]:

Bit[2]:
Bit[1]:
0x4741TEST PATTERN

0x00

RW
Bit[0]:

0x4745DATA ORDER

proprietary to OmniVision Technologies

0x00

RW

PCLK polarity
0:
Active low
1:
Active highReserved
Gate PCLK under VSYNC
Gate PCLK under HREF
HREF polarity
0:
Active low
1:
Active high
VSYNC polarity
0:
Active low
1:
Active highTest pattern enable
Test pattern select0:Output test pattern 01:
Output test pattern 1
Test pattern 8-bit/10-bit
0:10-bit test pattern1:
8-bit test pattern

Bit[2:1]: DVP order option for debug
00: D[9:0]
10: {D[7:0],D[9:8]}
x1: {D[1:0],D[9:2]}
Bit[0]:
Output data order0:
Normal output
1:
Reverse output data bit
order

PRELIMINARY SPECIFICATION

version 1.3

5-9

5.2.2 DVP timing

figure 5-7

DVP frame timing diagram
(1)

VSYNC
(2)

(3)

(4)

(5)
(7)

HREF
(6)
(9)

(8)

HSYNC

D[9:0]

invalid data
3660_DS_5_7

table 5-3mode

3 megapixel
2048x1536

DVP timing specifications (sheet 1 of 2)notetiming

The timing values
shown in table 5-3 mayvary depending uponregister settings.

(1) 3,599,434 tp(2) 4,600 tp(3) 32,062 tp(4) 2,300 tp(5) 27,924 tp(6) 2,048 tp(7) 252 tp(8) 0 tp
(9) 252 tp
where tp = 1 sclk

1080p
1920x1080

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

2,702,760 tp
4,788 tp
127,396 tp
2,394 tp
19,476 tp
1,920 tp
474 tp0 tp
474 tpwhere tp = 1 sclk

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 5-3

DVP timing specifications (sheet 2 of 2)

mode

720p
1280x720

timing
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

1,201,330 tp
3,208 tp
30,410 tp
1,604 tp
13,156 tp
1,280 tp
324 tp0 tp
324 tpwhere tp = 1 sclk

XGA
1024x768

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

1,210,260 tp
3,068 tp
23,130 tp
1,534 tp
6,460 tp
1,024 tp
510 tp0 tp
510 tpwhere tp = 1 sclk

VGA
640x480

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

451,010 tp
1,808 tp
9,798 tp
904 tp5,748 tp
640 tp264 tp0 tp
264 tpwhere tp = 1 sclk

QVGA
320x240

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

225,844 tp
1,772 tp
8,130 tp
886 tp7,412 tp
320 tp566 tp0 tp
566 tpwhere tp = 1 sclk

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

6-1

6 serial camera control bus (SCCB) interface
The Serial Camera Control Bus (SCCB) interface controls the image sensor operation. Refer to the OmniVision
Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port.

6.1 data transfer protocol
The data transfer of the OV3660 follows the SCCB protocol.

6.2 message format
The OV3660 supports the message format shown in figure 6-1. The 7-bit address of the OV3660 is 0x3C by default but
can be programmed using register 0x3100[7:1] which has a default of 0x78. The repeated START (Sr) condition is notshown in figure 6-2, but is shown in figure 6-3 and figure 6-4.

figure 6-1

message typemessage type: 16-bit sub-address, 8-bit data, and 7-bit slave address

S

slave
address

R/WA

sub address[15:8]

A

index[15:8]

sub address
[7:0]

A

data

A/A

P

index[7:0]from slave to master

S

START conditionA

acknowledge

from master to slave

P

STOP conditionA

negative acknowledge

direction depends on operation

Sr

repeated START condition

3660_DS_6_1

6.3 read / write operation
The OV3660 supports four different read operations and two different write operations:•a single read from random locations•

a sequential read from random locations•

a single read from current location•a sequential read from current location•

single write to random locations•

sequential write starting from random location

The sub-address in the sensor automatically increases by one after each read/write operation.
In a single read from random locations, the master does a dummy write operation to desired sub-address, issues arepeated start condition and then addresses the camera again with a read operation. After acknowledging its slave

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

address, the camera starts to output data onto the SDA line as shown in figure 6-2. The master terminates the read
operation by setting a negative acknowledge and stop condition.

figure 6-2

SCCB single read from random location
previous index value, K

S

slave
address0A

sub address[15:8]

A

index M + 1

index M

sub address
[7:0]

A

slave
address

Sr

A

1

data

A

P

index value M

3660_DS_6_2

If the host addresses the camera with read operation directly without the dummy write operation, the camera respondsby setting the data from last used sub-address to the SDA line as shown in figure 6-3. The master terminates the read
operation by setting a negative acknowledge and stop condition.

figure 6-3

SCCB single read from current location

previous index value, K

S

slave
address1

Aindex K + 1

data

A

P

S

index K + 2

slave
address

1

A

A

data

P
3660_DS_6_3

The sequential read from a random location is illustrated in figure 6-4. The master does a dummy write to the desired
sub-address, issues a repeated start condition after acknowledge from slave and addresses the slave again with read
operation. If a master issues an acknowledge after receiving data, it acts as a signal to the slave that the read operation
shall continue from the next sub-address. When master has read the last data byte, it issues a negative acknowledge
and stop condition.

figure 6-4

SCCB sequential read from random location
previous index value, K

S

slave
address1A

sub address[15:8]

A

sub address[7:0]

index value M

proprietary to OmniVision Technologies

index
M+L-1

index M

A

Sr

slave
address

1

A

data

A

L bytes of data

PRELIMINARY SPECIFICATION

data

index
M+L

A

P

3660_DS_6_4

version 1.3

6-3

The sequential read from current location is similar to a sequential read from a random location. The only exception isthat there is no dummy write operation. as shown in figure 6-5. The master terminates the read operation by setting anegative acknowledge and stop condition.

figure 6-5

SCCB sequential read from current location

previous index value, K

S

slave
address

1

A

data

index
K+L-1

index K + 1

A

data

A

data

index
K+L

A

L bytes of data

P

3660_DS_6_5

The write operation to a random location is illustrated in figure 6-6. The master issues a write operation to the slave, sets
the sub-address and data correspondingly after the slave has acknowledged. The write operation is terminated with astop condition from the master.

figure 6-6

SCCB single write to random location
previous index value, K

S

slave
address0A

sub address[15:8]

A

index M

sub address
[7:0]

A

data

index M + 1

A/A

P

index value M

3660_DS_6_6

The sequential write is illustrated in figure 6-7. The slave automatically increments the sub-address after each data byte.
The sequential write operation is terminated with stop condition from the master.

figure 6-7

SCCB sequential write to random location
previous index value, K

S

slave
address0A

sub address[15:8]

A

sub address[7:0]

index value M

05.13.2011

index
M+L-1

index MPRELIMINARY SPECIFICATION

A

data

A

L bytes of data

data

index
M+L

A/A

P

3660_DS_6_7

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

6.4 SCCB timing
figure 6-8

SCCB interface timing
tHIGH

tF

tR

SIOC
tLOW

tSU:DATtHD:STASIOD (IN)tSU:STOtSU:STAtAA

tHD:DATtBUF

SIOD (OUT)
3660_DS_6_8

tDH

table 6-1a.
b.

SCCB interface timing specificationsab

symbolparameter

min

typ

max

unit

fSIOC

clock frequency

400

KHz

tLOW

clock low period

1.3

µs

tHIGH

clock high period

0.6

µs

tAA

SIOC low to data out valid

0.1

tBUF

bus free time before new start

1.3

µs

tHD:STAstart condition hold time

0.6

µs

tSU:STAstart condition setup time

0.6

µs

tHD:DATdata in hold time0µs

tSU:DATdata in setup time

0.1

µs

tSU:STOstop condition setup time

0.6

µs

tR, tFSCCB rise/fall times

tDH

data out hold time

0.9

µs

0.3

µs

0.05

µs

SCCB timing is based on 400KHz mode
timing measurement shown at the beginning of the rising edge or/and of the falling edge signifies 10%,timing measurement shown in the middle of the rising/falling edge signifies 50%, timing measurement shown at the
beginning of the rising edge or/and of the falling edge signifies 90%

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-1

7 register tables
The following tables provide descriptions of the device control registers contained in the OV3660. For all registers
enable/disable bits, ENABLE = 1 and DISABLE = 0.

7.1 system and IO pad control [0x3000 ~ 0x3052]
table 7-1

system and IO pad control registers (sheet 1 of 3)
default
value

R/W

description

SYSTEM RESET00~
SYSTEM RESET03–

RW

Reset for Individual Blocks

CLOCK ENABLE00–

RW

Clock Enable Control for Individual Blocks

address

register name0x3000~0x30030x3004~0x30070x3008SYSTEM CTROL0

0x02

RW

System Control
Bit[7]:
Software reset
Bit[6]:
Software power downBit[5]:
ReserveBit[4]:SRB clock SYNC enable
Bit[3]:
Isolation suspend selectBit[2:0]: Not used

0x300ACHIP ID HIGH BYTE

0x36

R

Chip ID High Byte

0x300BCHIP ID LOW BYTE

0x60

R

Chip ID Low Byte

RW

Input/Output Control (0: input; 1: output)
Bit[7:3]: Not usedBit[2]:FSIN output enableBit[1]:STROBE output enable
Bit[0]:
Not used

0x3016PAD OUTPUT ENABLE 00

0x220x3017

PAD OUTPUT ENABLE 01

0x00

RW

Input/Output Control (0: input; 1: output)
Bit[7]:
Not usedBit[6]:
VSYNC output enableBit[5]:
HREF output enable
Bit[4]:PCLK output enable
Bit[3:0]: D[9:6] output enable

0x3018PAD OUTPUT ENABLE 02

0x00

RW

Input/Output Control (0: input; 1: output)
Bit[7:2]: D[5:0] output enableBit[1:0]: GPIO1 output enable

RW

PAD Output Value
Bit[7:3]: Not usedBit[2]:FSIN
Bit[1]:STROBEBit[0]:
Not used

0x301905.13.2011

PAD OUTPUT VALUE 00

0xF0

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-1
address

system and IO pad control registers (sheet 2 of 3)
register namedefault
value

R/W

description

0x301APAD OUTPUT VALUE 01

0x00

RW

GPIO Output Value 01
Bit[7]:
Reserved
Bit[6]:
VSYNC
Bit[5]:
HREF
Bit[4]:
PCLK
Bit[3:0]: D[9:6]0x301BPAD OUTPUT VALUE 02

0x00

RW

GPIO Output Value 02
Bit[7:2]: D[5:0]
Bit[1:0]: Not usedRW

Pad Selection Control
Bit[7:3]: Not usedBit[2]:IO FSIN selectBit[1]:IO STROBE selectBit[0]:
Not used

0x301CPAD SELECT 00

0x00

0x301D

PAD SELECT 01

0x00

RW

Output Selection for GPIO
Bit[7]:
Not usedBit[6]:
VSYNC selectBit[5]:
HREF selectBit[4]:PCLK selectBit[3:0]: IO D[9:6] select0x301EPAD SELECT 02

0x00

RW

Pad select control
Bit[7:2]: IO D[5:0] selectBit[1:0]: Not used

0x302ACHIP REVISION

0xB0

R

Bit[7:4]: Process
0xB: BSI
Bit[3:0]: Chip revision
Pad Control
Bit[7:6]: Pad driving strength
00: 1x01: 2x10: 3x11: 4xBit[5]:
pd_dato_en
Bit[4:2]: Reserved
Bit[1]:FSIN input enable
Bit[0]:STROBE input enable

0x302CPAD CONTROL

0x03

RW

0x303ASC PLLS CTRL0

0x00

RW

Bit[7]:PLLS bypass
Bit[6:0]: Reserved

0x303BSC PLLS CTRL1

0x1B

RW

Bit[7:5]: Not usedBit[4:0]: PLLS multiplier

0x303CSC PLLS CTRL2

0x11

RW

Bit[7]:
Not usedBit[6:4]: PLL charge pump control
Bit[3:0]: PLL system divider

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-3

table 7-1
address

0x303D

0x3050system and IO pad control registers (sheet 3 of 3)
register nameSC PLLS CTRL3

IO PAD VALUE

default
value

0x30

–

R/W

RW

description
Bit[7:6]: Not usedBit[5:4]: PLLS predivider
00: /1
01: /1.5
10: /2
11: /3Bit[3]:
Not usedBit[2]:PLLS root divider
0:
/1
1:
/2
Bit[1:0]: PLLS seld500: /1
01: /1
10: /2
11: /2.5

R

Read Pad Value
Bit[7:4]: Not usedBit[3]:PWDN
Bit[2]:
Not usedBit[1]:
SIOC
Bit[0]:
Not used

0x3051IO PAD VALUE–

R

Read Pad Value
Bit[7]:OTP memory out
Bit[6]:
VSYNC
Bit[5]:
HREF
Bit[4]:
PCLK
Bit[3:0]: D[9:6]0x3052IO PAD VALUE–

R

Read Pad Value
Bit[7:2]: D[5:0]
Bit[1:0]: Not used

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

7.2 SCCB control [0x3100 ~ 0x3108]
table 7-2

SCCB control registers

address

register namedefault
value

R/W

description

0x3100SCCB_ID

0x78

RW

SCCB Slave ID

RW

Bit[7:6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

RW

Bit[7:2]: Not usedBit[1]:
Select PLL input clock0:
From pad clock
1:
From pre divider(clock modulator)
Bit[0]:
Power up reset disable

RW

Bit[7:6]: Not usedBit[5:4]: PCLK root divider
00: PCLK = pll_clki
01: PCLK = pll_clki/2
10: PCLK = pll_clki/4
11: PCLK = pll_clki/8
Bit[3:2]: SCLK2x root divider
00: SCLK2x = pll_clki
01: SCLK2x = pll_clki/2
10: SCLK2x= pll_clki/4
11: SCLK2x= pll_clki/8
Bit[1:0]: SCLK root divider
00: SCLK = pll_clki
01: SCLK = pll_clki/2
10: SCLK= pll_clki/4
11: SCLK= pll_clki/8

0x31020x31030x3108SCCB SYSTEM CTRL0SCCB SYSTEM CTRL1

SYSTEM ROOT DIVIDER

proprietary to OmniVision Technologies

0x80

0x11

0x16

Not used
SRB reset
SCCB slave reset
rst_pon_sccb
Reserved
Not used
PLL reset

PRELIMINARY SPECIFICATION

version 1.3

7-5

7.3 SRB control [0x3200 ~ 0x3213]
table 7-3

SRB control registers

address

register namedefault
value

R/W

description

0x3200

GROUP ADDR0

0x40

RW

SRAM Group Address0

0x3201GROUP ADDR1

0x4A

RW

SRAM Group Address1

0x3202

GROUP ADDR2

0x54

RW

SRAM Group Address2

0x3203

GROUP ADDR3

0x5E

RW

SRAM Group Address3

W

SRM Group AccessBit[7]:
Group launch enableBit[6]:
Test mode access groupBit[5]:
Group launchBit[4]:
Group hold end
Bit[3:0]: Group ID
00x: Group for register access
011: Group to hold register addressof embedded line SOF
100: Group to hold register addressof embedded line EOF
101: Test mode for store registervalue to memory
110: Test mode for restore registervalue from memory
111: Group for write mask addressR

SRM Group Status
Bit[7]:
Store
Bit[6]:
RestoreBit[5]:
Group holdBit[4]:
Group launchBit[3]:
Group writeBit[2:0]: Group select0x32120x3213

SRM GROUP ACCESSSRM GROUP STATUS––

7.4 AWB gain control [0x3400 ~ 0x3406]
table 7-4

AWB gain control registers (sheet 1 of 2)

address

register namedefault
value

R/W

0x3400AWB R GAIN

0x04

RW

Bit[7:4]: Not usedBit[3:0]: AWB R gain[11:8]

0x3401AWB R GAIN

0x00

RW

Bit[7:0]: AWB R gain[7:0]0x3402AWB G GAIN

0x04

RW

Bit[7:4]: Not usedBit[3:0]: AWB G gain[11:8]

05.13.2011

PRELIMINARY SPECIFICATION

description

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-4

AWB gain control registers (sheet 2 of 2)

address

register namedefault
value

R/W

0x3403AWB G GAIN

0x00

RW

Bit[7:0]: AWB G gain[7:0]0x3404AWB B GAIN

0x04

RW

Bit[7:4]: Not usedBit[3:0]: AWB B gain[11:8]

0x3405AWB B GAIN

0x00

RW

Bit[7:0]: AWB B gain[7:0]

RW

Bit[7:1]: Reserved
Bit[0]:AWB gain manual enable
0:
Auto
1:
Manual0x3406AWB MANUAL CONTROL

0x00

description

7.5 AEC/AGC control [0x3500 ~ 0x3513]
table 7-5

AEC/AGC control functions (sheet 1 of 2)

address

register namedefault
value

R/W

description

0x3500

AEC PK EXPOSURE

0x00

RW

Exposure Output
Bit[7:4]: Reserved
Bit[3:0]: Exposure[19:16]

0x3501

AEC PK EXPOSURE

0x02

RW

Exposure Output
Bit[7:0]: Exposure[15:8]

0x3502

AEC PK EXPOSURE

0x00

RW

Exposure Output
Bit[7:0]: Exposure[7:0]
AEC Manual Mode Control
Bit[7:6]: Reserved
Bit[5]:
Gain delay option
Valid when 0x3503[4]=1’b00:
Delay one frame latch
1:
One frame latch
Bit[4:2]: Reserved
Bit[1]:
AGC manual0:
Auto enable
1:
Manual enable
Bit[0]:
AEC manual0:
Auto enable
1:
Manual enable

0x3503

AEC PK MANUAL

0x00

RW

0x3504

AEC MANUAL SENSOR
GAIN

0x00

RW

Bit[7:2]: Reserved
Bit[1:0]: AGC manual sensor gain[9:8]
Valid when 0x3509[3]=1’b1

0x3505

AEC MANUAL SENSOR
GAIN

0x00

RW

Bit[7:0]: AEC manual sensor gain[7:0]
Valid when 0x3509[3]=1’b1

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-7

table 7-5
address

AEC/AGC control functions (sheet 2 of 2)
default
value

register name

R/W

description
Bit[7:6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1:0]:

Reserved
Digital gain manual enable
Reserved
Gain manual enable
Reserved
Manual digital gain
Valid when 0x3509[5]=1’b1

0x3509AEC GAIN CONTROL MISC

0x10

RW

0x350AAEC PK REAL GAIN

0x00

RW

Real GainBit[7:2]: Reserved
Bit[1:0]: Real gain[9:8]0x350BAEC PK REAL GAIN

0x10

RW

Real GainBit[7:0]: Real gain[7:0]0x350CAEC PK ADD VTS

0x00

RW

AEC Add VTS output
Bit[7:0]: Add VTS[15:8]

0x350D

AEC PK ADD VTS

0x00

RW

AEC Add VTS output
Bit[7:0]: Add VTS[7:0]0x3512

AEC PK SENSOR GAINOUTPUT–R

Bit[7:2]: Reserved
Bit[1:0]: AEC pk sensor gain[9:8]0x3513

AEC PK SENSOR GAINOUTPUT–R

Bit[7:0]: AEC pk sensor gain[7:0]

7.6 ANA control registers [0x3600 ~ 0x3634]
table 7-6

ANA control registers

address

register namedefault
value

R/W

description

0x3600~0x3634

RSVD––

Reserved

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

7.7 sensor control [0x3700 ~ 0x373C]
table 7-7

sensor control registers

address

register namedefault
value

R/W

description

0x3700~0x373CRSVD––

Reserved

7.8 timing control [0x3800 ~ 0x3836]
table 7-8

timing control registers (sheet 1 of 2)

address

register namedefault
value

R/W

0x3800

TIMING HS

0x00

RW

Bit[7:4]: Not usedBit[3:0]: X address start[11:8]

0x3801

TIMING HS

0x00

RW

Bit[7:0]: X address start[7:0]0x3802TIMING VS

0x00

RW

Bit[7:4]: Not usedBit[3:0]: Y address start[11:8]

0x3803

TIMING VS

0x00

RW

Bit[7:0]: Y address start[7:0]0x3804

TIMING HW

0x08

RW

Bit[7:4]: Not usedBit[3:0]: X address end[11:8]

0x3805

TIMING HW

0x1F

RW

Bit[7:0]: X address end[7:0]0x3806

TIMING VH

0x06

RW

Bit[7:4]: Not usedBit[3:0]: Y address end[11:8]

0x3807

TIMING VH

0x0B

RW

Bit[7:0]: Y address end[7:0]0x3808TIMING DVPHO

0x08

RW

Bit[7:4]: Debug modeBit[3:0]: DVP output horizontal width[11:8]

0x3809TIMING DVPHO

0x00

RW

Bit[7:0]: DVP output horizontal width[7:0]0x380A

TIMING DVPVO

0x06

RW

Bit[7:4]: Not usedBit[3:0]: DVP output vertical height[11:8]

0x380B

TIMING DVPVO

0x00

RW

Bit[7:0]: DVP output vertical height[7:0]0x380CTIMING HTS

0x08

RW

Bit[7:4]: Not usedBit[3:0]: Total horizontal size[11:8]

0x380D

TIMING HTS

0xFC

RW

Bit[7:0]: Total horizontal size[7:0]0x380E

TIMING VTS

0x06

RW

Bit[7:0]: Total vertical size[15:8]

proprietary to OmniVision Technologies

description

PRELIMINARY SPECIFICATION

version 1.3

7-9

table 7-8

timing control registers (sheet 2 of 2)

address

register namedefault
value

R/W

0x380F

TIMING VTS

0x1C

RW

Bit[7:0]: Total vertical size[7:0]0x3810

TIMING HOFFSET

0x00

RW

Bit[7:4]: Not usedBit[3:0]: ISP horizontal offset[11:8]

0x3811

TIMING HOFFSET

0x10

RW

Bit[7:0]: Horizontal offset[7:0]0x3812TIMING VOFFSET

0x00

RW

Bit[7:3]: Not usedBit[2:0]: Vertical offset[10:8]

0x3813

TIMING VOFFSET

0x06

RW

Bit[7:0]: Vertical offset[7:0]0x3814

TIMING X INC

0x11

RW

Bit[7:4]: Horizontal odd subsample increment
Bit[3:0]: Horizontal even subsample increment

0x3815

TIMING Y INC

0x11

RW

Bit[7:4]: Vertical odd subsample increment
Bit[3:0]: Vertical even subsample increment

0x3816HSYNC START

0x00

RW

Bit[7:4]: Not usedBit[3:0]: HSYNC start point[11:8]

0x3817HSYNC START

0x00

RW

Bit[7:0]: HSYNC start point[7:0]0x3818HSYNC WIDTH

0x00

RW

Bit[7:4]: Not usedBit[3:0]: HSYNC width[11:8]

0x3819HSYNC WIDTH

0x00

RW

Bit[7:0]: HSYNC width[7:0]

RW

Timing Control
Bit[7:5]: Reserved
Bit[4]:
Blackline vflip
Bit[3]:
Reserved
Bit[2]:
ISP vflipBit[1]:
Sensor vflip
Bit[0]:
Vertical binning enable
Timing Control
Bit[7:6]: Reserved
Bit[5]:
Compression enable
Bit[4:3]: Reserved
Bit[2]:ISP mirror
Bit[1]:
Sensor mirror
Bit[0]:
Horizontal binning enable

0x3820

TIMING TC REG20

0x40

description

0x3821

TIMING TC REG21

0x00

RW

0x3835

TIMING TC REG35

0x00

RW

Bit[7:2]: Not usedBit[1]:FSIN reverse
Bit[0]:FSIN enable

0x3836

TIMING TC REG36

0x00

RW

Bit[7:4]: Not usedBit[3:0] FSIN output width

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

7.9 AEC/AGC power down domain control [0x3A00 ~ 0x3A25]
table 7-9
address

AEC/AGC power down domain control registers (sheet 1 of 3)
register namedefault
value

R/W

description

0x3A00

AEC CTRL00

0x78

RW

AEC System Control (0: disable; 1: enable)
Bit[7:6]: Reserved
Bit[5]:
Band function enable
Bit[4]:
Less 1 band enable
Bit[3]:Start selection
Bit[2]:
Night modeBit[1]:
New balance function
Bit[0]:
Freeze0x3A01

AEC MIN EXPOSURE

0x04

RW

Minimum Exposure Output Limit
Bit[7:0]: Minimum exposure

0x3A02

AEC MAX EXPO
(60HZ)

0x30

RW

60Hz Maximum Exposure Output Limit
Bit[7:0]: Maximum exposure[15:8]

0x3A03

AEC MAX EXPO
(60HZ)

0xC0

RW

60Hz Maximum Exposure Output Limit
Bit[7:0]: Maximum exposure[7:0]

0x3A04

RSVD––

ReservedRW

AEC System Control 2
Bit[7]:
Reserved
Bit[6]:
frame insert
0:
In night mode, insert frame
disable1:
In night mode, insert frame
enableBit[5]:
Step auto enable
0:
Step manual mode
1:
Step auto modeBit[4:0]: Step auto ratio
In step auto mode, step ratio setting toadjust speed

RW

AEC System Control 3
Bit[7:5]: Reserved
Bit[4:0]: Step manual setting 1
Step manual
Increase mode fast stepRW

AEC Manual Step RegisterBit[7:4]: Step manual setting 2
Step manual, slow stepBit[3:0]: Step manual setting 3
Step manual, decrease mode fast step

0x3A05

0x3A06

0x3A07

AEC CTRL05

AEC CTRL06

AEC CTRL07

proprietary to OmniVision Technologies

0x30

0x10

0x18

PRELIMINARY SPECIFICATION

version 1.3

7-11

table 7-9

AEC/AGC power down domain control registers (sheet 2 of 3)

address

register namedefault
value

R/W

description

0x3A08AEC B50 STEP

0x00

RW

50Hz Band WidthBit[7:2]: Reserved
Bit[1:0]: B50 step[9:8]

0x3A09AEC B50 STEP

0xEA

RW

50Hz Band WidthBit[7:0]: B50 step[7:0]

0x3A0AAEC B60 STEP

0x00

RW

60Hz Band WidthBit[7:2]: Reserved
Bit[1:0]: B60 step[13:8]

0x3A0BAEC B60 STEP

0xC3

RW

60Hz Band WidthBit[7:0]: B60 step[7:0]
Bit[7:4]: E1 max
Decimal line high limit zone
Bit[3:0]: E1 min
Decimal line low limit zone

0x3A0CAEC CTRL0C

0xE4

RW

0x3A0D

AEC CTRL0D

0x08

RW

60Hz Max Bands in One Frame
Bit[7:6]: Reserved
Bit[5:0]: B60 max

0x3A0EAEC CTRL0E

0x06

RW

50Hz Max Bands in One Frame
Bit[7:6]: Debug modeBit[5:0]: B50 max

0x3A0FAEC CTRL0F

0x78

RW

Stable Range High Limit (Enter)Bit[7:0]: WPT

0x3A10

AEC CTRL10

0x68

RW

Stable Range Low Limit (Enter)Bit[7:0]: BPT

0x3A11

AEC CTRL11

0xD0

RW

Step Manual Mode, Fast Zone High Limit
Bit[7:0]: VPT high

0x3A12

RSVD––

Reserved

0x3A13

AEC CTRL13

0x90

RW

0x3A14

AEC MAX EXPO
(50HZ)

0x30

RW

50Hz Maximum Exposure Output Limit
Bit[7:4]: Reserved
Bit[3:0]: Max exposure[15:8]

0x3A15

AEC MAX EXPO
(50HZ)

0x72

RW

50Hz Maximum Exposure Output Limit
Bit[7:0]: Max exposure[7:0]

0x3A16

RSVD––

Reserved

05.13.2011

PRELIMINARY SPECIFICATION

Bit[7]:
Pre-gain enableBit[6:0]: Pre-gain enable
0x10: 1x

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-9
address

0x3A17

AEC/AGC power down domain control registers (sheet 3 of 3)
register name

AEC CTRL17

default
value

0x01

R/W

description

RW

Gain Base When in Night ModeBit[7:2]: Reserved
Bit[1:0]: Gain night threshold
00: 0x00
01: 0x10
10: 0x30
11: 0x70

0x3A18AEC GAIN CEILING

0x07

RW

Gain Output Top Limit
Bit[7:2]: Reserved
Bit[1:0]: AEC gain ceiling[9:8]
Real gain format

0x3A19AEC GAIN CEILING

0xC0

RW

Gain Output Top Limit
Bit[7:0]: AEC gain ceiling[7:0]Real gain format

0x3A1AAEC DIFF MIN

0x00

RW

Reserved Default Value for This RegisterBit[7:0]: Difference minimal

0x3A1BAEC CTRL1B

0x78

RW

Stable Range High Limit (Go Out)Bit[7:0]: WPT2

0x3A1CLED ADD ROW

0x06

RW

Exposure Values Added When Strobe is On
Bit[7:0]: AEC LED add row[15:8]

0x3A1D

LED ADD ROW

0x18

RW

Exposure Values Added When Strobe is On
Bit[7:0]: AEC LED add row[7:0]

0x3A1EAEC CTRL1E

0x68

RW

Stable Range Low Limit (Go Out)Bit[7:0]: BPT2

0x3A1FAEC CTRL1F

0x40

RW

Step Manual Mode, Fast Zone Low Limit
Bit[7:0]: VPT low

0x3A20

AEC CTRL20

0x20

RW

Bit[7:3]: Reserved
Bit[2]:
Strobe option
Bit[1:0]: Reserved

0x3A21

AEC CTRL21

0x78

RW

Bit[7]:
Reserved
Bit[6:4]: Insert frame numberBit[3:0]: Reserved

0x3A25

AEC CTRL25

0x00

RW

Bit[7:5]: Reserved
Bit[4:2]: Freeze countBit[1:0]: Reserved

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-13

7.10 strobe control [0x3B00]
table 7-10
address

strobe registers
register namedefault
value

R/W

description
Bit[7]:

0x3B00STROBE CTRL

0x00

RW

Strobe request on/off
0:
Off
1:
On
Bit[6]:
Strobe pulse reverse
Bit[3:2]: width_in_xenon
Bit[1:0]: Strobe mode
00: Xenon
01: LED1
10: LED2
11: LED3

7.11 sigmadelta/5060Hz detector [0x3C00 ~ 0x3C1E]
table 7-11
address

0x3C00sigmadelta/5060HZ detector registers (sheet 1 of 3)
register name

SIGMADELTA CTRL00

default
value

0x00

R/W

RW

description
Bit[7:6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1:0]:

Reserved
Time counter threshold divisor enable
Low limit enable
Reserve sigmaq
Band50 default value
Time counter threshold
00: 1s
01: 2s
10: 4s
11: 8sBit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3:0]:Band manual enable
Band begin reset enable
Sum auto mode enable
Band counter enable
Band counter
Counter threshold for band change

0x3C01SIGMADELTA CTRL01

0x00

RW

0x3C02SIGMADELTA CTRL02

0x00

RW

Bit[7:6]: Low light limit modeBit[5:0]: Low light thresholdNo detection under low light

0x3C03

SIGMADELTA CTRL03

0x00

RW

Bit[7:0]: Counter threshold for low light

0x3C04

SIGMADELTA CTRL04

0x20

RW

Bit[7:0]: Threshold for low sum

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-11

sigmadelta/5060HZ detector registers (sheet 2 of 3)

address

register namedefault
value

R/W

0x3C05SIGMADELTA CTRL05

0x70

RW

Bit[7:0]: Threshold for high sum

0x3C06

LIGHT METER1
THRESHOLD

0x00

RW

Bit[7:0]: Lightmeter1 threshold[15:8]

0x3C07

LIGHT METER1
THRESHOLD

0x00

RW

Bit[7:0]: Lightmeter1 threshold[7:0]

0x3C08LIGHT METER2
THRESHOLD

0x01

RW

Bit[7:0]: Lightmeter2 threshold[15:8]

0x3C09LIGHT METER2
THRESHOLD

0x2C

RW

Bit[7:0]: Lightmeter2 threshold[7:0]

0x3C0ASAMPLE NUMBER

0x4E

RW

Bit[7:0]: Sample number[15:8]

0x3C0BSAMPLE NUMBER

0x1F

RW

Bit[7:0]: Sample number[7:0]

0x3C0CSIGMADELTA CTRL0C–

R

Bit[7:1]: Reserved
Bit[0]:
Band50/60
0:60Hz light
1:
50Hz light

0x3C0DSUM 50–R

Bit[7:5]: Not usedBit[4:0]: Sum50[28:24]

0x3C0ESUM 50–R

Bit[7:0]: Sum50[23:16]

0x3C0FSUM 50–R

Bit[7:0]: Sum50[15:8]

0x3C10

SUM 50–R

Bit[7:0]: Sum50[7:0]0x3C11

SUM 60–R

Bit[7:5]: Not usedBit[4:0]: Sum60[28:24]

0x3C12

SUM 60–R

Bit[7:0]: Sum60[23:16]

0x3C13

SUM 60–R

Bit[7:0]: Sum60[15:8]

0x3C14

SUM 60–R

Bit[7:0]: Sum60[7:0]0x3C15

SUM 50 60–

R

Bit[7:0]: Sum50/60[15:8]

0x3C16

SUM 50 60–

R

Bit[7:0]: Sum50/60[7:0]0x3C17BLOCK COUNTER–R

Bit[7:0]: Block counter[15:8]

0x3C18BLOCK COUNTER–R

Bit[7:0]: Block counter[7:0]0x3C19

B6–

R

Bit[7:0]: B6[15:8]

0x3C1A

B6–

R

Bit[7:0]: B6[7:0]0x3C1B

LIGHTMETER OUTPUT–

R

Bit[7:4]: Not usedBit[3:0]: Light meter output[19:16]

0x3C1CLIGHTMETER OUTPUT–

R

Bit[7:0]: Light meter output[15:8]

proprietary to OmniVision Technologies

description

PRELIMINARY SPECIFICATION

version 1.3

7-15

table 7-11

sigmadelta/5060HZ detector registers (sheet 3 of 3)

address

register namedefault
value

R/W

0x3C1D

LIGHTMETER OUTPUT–

R

0x3C1E

SUM THRESHOLD–

R

description
Bit[7:0]: Light meter output[7:0]
Delta Sum Threshold

7.12 OTP control [0x3D00 ~ 0x3D21]
table 7-12

OTP control functions (sheet 1 of 2)

address

register namedefault
value

R/W

description

0x3D00OTP DATA00

0x00

RW

OTP Dump/Load Data00

0x3D01OTP DATA01

0x00

RW

OTP Dump/Load Data01

0x3D02OTP DATA02

0x00

RW

OTP Dump/Load Data02

0x3D03OTP DATA03

0x00

RW

OTP Dump/Load Data03

0x3D04OTP DATA04

0x00

RW

OTP Dump/Load Data04

0x3D05OTP DATA05

0x00

RW

OTP Dump/Load Data05

0x3D06OTP DATA06

0x00

RW

OTP Dump/Load Data06

0x3D07OTP DATA07

0x00

RW

OTP Dump/Load Data07

0x3D08OTP DATA08

0x00

RW

OTP Dump/Load Data08

0x3D09OTP DATA09

0x00

RW

OTP Dump/Load Data09

0x3D0AOTP DATA0A

0x00

RW

OTP Dump/Load Data0a

0x3D0BOTP DATA0B

0x00

RW

OTP Dump/Load Data0b

0x3D0COTP DATA0C

0x00

RW

OTP Dump/Load Data0c

0x3D0DOTP DATA0D

0x00

RW

OTP Dump/Load Data0d

0x3D0EOTP DATA0E

0x00

RW

OTP Dump/Load Data0e

0x3D0FOTP DATA0F

0x00

RW

OTP Dump/Load Data0f

0x3D10OTP DATA10

0x00

RW

OTP Dump/Load Data10

0x3D11OTP DATA11

0x00

RW

OTP Dump/Load Data11

0x3D12OTP DATA12

0x00

RW

OTP Dump/Load Data12

0x3D13OTP DATA13

0x00

RW

OTP Dump/Load Data13

0x3D14OTP DATA14

0x00

RW

OTP Dump/Load Data14

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-12

OTP control functions (sheet 2 of 2)

address

register namedefault
value

R/W

description

0x3D15OTP DATA15

0x00

RW

OTP Dump/Load Data15

0x3D16OTP DATA16

0x00

RW

OTP Dump/Load Data16

0x3D17OTP DATA17

0x00

RW

OTP Dump/Load Data17

0x3D18OTP DATA18

0x00

RW

OTP Dump/Load Data18

0x3D19OTP DATA19

0x00

RW

OTP Dump/Load Data19

0x3D1AOTP DATA1A

0x00

RW

OTP Dump/Load Data1A

0x3D1BOTP DATA1B

0x00

RW

OTP Dump/Load Data1B

0x3D1COTP DATA1C

0x00

RW

OTP Dump/Load Data1C

0x3D1DOTP DATA1D

0x00

RW

OTP Dump/Load Data1D

0x3D1EOTP DATA1E

0x00

RW

OTP Dump/Load Data1E

0x3D1FOTP DATA1F

0x00

RW

OTP Dump/Load Data1F

0x3D200x3D21OTP PROGRAM CTRLOTP READ CTRL

0x00

0x00

RW

Bit[7]:OTP program busy
Bit[6:2]: Not usedBit[1]:OTP program speed
0:
Fast
1:
Slow
Bit[0]:OTP program enable

RW

Bit[7]:OTP read busy
Bit[6:2]: Not usedBit[1]:OTP read speed
0:
Fast
1:
Slow
Bit[0]:OTP read enable

7.13 BLC control [0x4000 ~ 0x4033]
table 7-13
address

0x4000

BLC registers (sheet 1 of 3)
register name

BLC CTRL00

proprietary to OmniVision Technologies

default
value

0x0D

R/W

description

RW

BLC Control 00 (0: disable; 1: enable)
Bit[7:4]: Reserved
Bit[3]:
BGR comp enableBit[2]:
Apply selection
Bit[1]:
Mid filter enable
Bit[0]:
BLC enable

PRELIMINARY SPECIFICATION

version 1.3

7-17

table 7-13

BLC registers (sheet 2 of 3)

address

register namedefault
value

R/W

0x4001BLC CTRL01

0x04

RW

description
Bit[7:6]: Reserved
Bit[5:0]: BLC start line
Bit[7]:

0x4002BLC CTRL02

0x45

RW

Format change enable
BLC update when format changes
Bit[6]:
BLC auto enable
0:
Manual1:
AutoBit[5:0]: Reset frame number
Frame number BLC do after reset
Bit[7]:

0x4003BLC CTRL03

0x01

RW

BLC redo enable
Write 1 to this bit will trigger a BLC
redo N frames begin, where N is
0x4003[5:0]
Bit[6]:
BLC freeze
Bit[5:0]: Manual frame number

0x4004BLC CTRL04

0x08

RW

Bit[7:0]: BLC line number
Specify the line number BLC process

0x4005BLC CTRL05

0x10

RW

Bit[7:2]: Reserved
Bit[1]:
BLC always update0:
Normal freeze
1:
BLC always updateBit[0]:
Reserved

0x4006BLC CTRL06

0x08

RW

Bit[7]:
Reserved
Bit[6]:
Black line number manual enableBit[5:0]: Black number manual

0x4007BLC CTRL07

0x00

RW

Bit[7:5]: Reserved
Bit[4:3]: Window selection
00: Full image
01: A windows not contain the first
16 pixels and the end 16 pixels
10: A windows not contain the first
1/16 image and the end 1/16
image
11: A windows not contain the first
1/8 image and the end 1/8
image
Bit[2:0]: Reserved

0x4009BLACK LEVEL

0x10

RW

Bit[7:0]: BLC black level target at 10-bit range

0x400A~
0x402B

RSVD––

0x402CBLACK LEVEL00

0x00

RW

05.13.2011

PRELIMINARY SPECIFICATION

Reserved
Bit[7:0]: Blacklevel00[15:8]
With 3 decimal

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-13

BLC registers (sheet 3 of 3)

address

register namedefault
value

R/W

0x402D

BLACK LEVEL00

0x00

RW

Bit[7:0]: Blacklevel00[7:0]With 3 decimal

0x402EBLACK LEVEL01

0x00

RW

Bit[7:0]: Blacklevel01[15:8]
With 3 decimal

0x402F

BLACK LEVEL01

0x00

RW

Bit[7:0]: Blacklevel01[7:0]With 3 decimal

0x4030BLACK LEVEL10

0x00

RW

Bit[7:0]: Blacklevel10[15:8]
With 3 decimal

0x4031

BLACK LEVEL10

0x00

RW

Bit[7:0]: Blacklevel10[7:0]With 3 decimal

0x4032BLACK LEVEL11

0x00

RW

Bit[7:0]: Blacklevel11[15:8]
With 3 decimal

0x4033BLACK LEVEL11

0x00

RW

Bit[7:0]: Blacklevel11[7:0]With 3 decimal

description

7.14 frame control [0x4201 ~ 0x4202]
table 7-14
address

0x42010x4202frame control registers
register name

FRAME CTRL01

FRAME CTRL02

proprietary to OmniVision Technologies

default
value

0x00

0x00

R/W

description

R/W

Control Passed Frame Number
When both ON and OFF number set to 0x00,
frame control is in bypass modeBit[7:4]: Not usedBit[3:0]: Frame ON number

R/W

Control Masked Frame Number
When both ON and OFF number set to 0x00,
frame control is in bypass modeBit[7:4]: Not used
BIT[3:0]: Frame OFF number

PRELIMINARY SPECIFICATION

version 1.3

7-19

7.15 format control [0x4300 ~ 0x430D]
table 7-15
addressformat control registers (sheet 1 of 4)
register namedefault
value

R/W

description
Format Control 00
Bit[7:4]: Output format selection
0x0: RAWBit[3:0]: Output sequence
0x0: BGBG... / GRGR...
0x1: GBGB... / RGRG...
0x2: GRGR... / BGBG...
0x3: RGRG... / GBGB...
0x4~0xF: Not allowed
0x1: Y8
Bit[3:0]: Does not matter
0x2: Not used

0x430005.13.2011

FORMAT CTRL 00

0xF8

RW

PRELIMINARY SPECIFICATION

0x3: YUV422
Bit[3:0]: Output sequence
0x0: YUYV...
0x1: YVYU...
0x2: UYVY...
0x3: VYUY...
0x4~0xE: Not allowed
0xF: UYVY...
0x4~0x5: Not used
0x6: RGB565
Bit[3:0]: Output sequence
0x0: {b[4:0],g[5:3]},{g[2:0],r[4:0]}
0x1: {r[4:0],g[5:3]},{g[2:0],b[4:0]}
0x2: {g[4:0],r[5:3]},{r[2:0],b[4:0]}
0x3: {b[4:0],r[5:3]},{r[2:0],g[4:0]}
0x4: {g[4:0],b[5:3]},{b[2:0],r[4:0]}
0x5: {r[4:0],b[5:3]},{b[2:0],g[4:0]}
0x6~0xE: Not allowed
0xF: {g[2:0],b[4:0]},{r[4:0],g[5:3]}
0x7: RGB555 format 1
Bit[3:0]: Output sequence
0x0: {b[4:0],g[4:2]},{g[1:0],1'b0,r[4:0]}
0x1: {r[4:0],g[4:2]},{g[1:0],1'b0,b[4:0]}

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-15
addressformat control registers (sheet 2 of 4)
register namedefault
value

R/W

description
0x2: {g[4:0],r[4:2]},{r[1:0],1'b0,b[4:0]}
0x3: {b[4:0],r[4:2]},{r[1:0],1'b0,g[4:0]}
0x4: {r[4:0],b[4:2]},{b[1:0],1'b0,g[4:0]}
0x5: {g[4:0],b[4:2]},{b[1:0],1'b0,r[4:0]}
0x6~0xF: Not allowed
0x8: RGB555 format 2
Bit[3:0]: Output sequence
0x0: {1'b0,b[4:0],g[4:3]},{g[2:0],r[4:0]}
0x1: {1'b0,r[4:0],g[4:2]},{g[2:0],b[4:0]}
0x2: {1'b0,g[4:0],r[4:2]},{r[2:0],b[4:0]}
0x3: {1'b0,b[4:0],r[4:2]},{r[2:0],g[4:0]}
0x4: {1'b0,r[4:0],b[4:2]},{b[2:0],g[4:0]}
0x5: {1'b0,g[4:0],b[4:2]},{b[2:0],r[4:0]}
0x6: {b[4:0],1'b0,g[4:3]},{g[2:0],r[4:0]}
0x8: {g[4:0],1'b0,r[4:2]},{r[2:0],b[4:0]}
0x9: {b[4:0],1'b0,r[4:2]},{r[2:0],g[4:0]}
0xA: {r[4:0],1'b0,b[4:2]},{b[2:0],g[4:0]}
0xB: {g[4:0],1'b0,b[4:2]},{b[2:0],r[4:0]}
0xC~0xF: Not allowed
0x9: RGB444 format 1
Bit[3:0]: Output sequence
0x0: {1'b0,b[3:0],2'h0,g[3]},{g[2:0],1'b0,r[3:0]}
0x1: {1'b0,r[3:0],2'h0,g[3]},{g[2:0],1'b0,b[3:0]}
0x2: {1'b0,g[3:0],2'h0,r[3]},{r[2:0],1'b0,b[3:0]}
0x3: {1'b0,b[3:0],2'h0,r[3]},{r[2:0],1'b0,g[3:0]}
0x4: {1'b0,r[3:0],2'h0,b[3]},{b[2:0],1'b0,g[3:0]}
0x5: {1'b0,g[3:0],2'h0,b[3]},{b[2:0],1'h0,r[3:0]}
0x6: {b[3:0],1'b0,g[3:1]},{g[0],2'h0,r[3:0],1'b0}

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-21

table 7-15
addressformat control registers (sheet 3 of 4)
register namedefault
value

R/W

description
0x7: {r[3:0],1'b0,g[3:1]},{g[0],2'h0,b[3:0],1'b0}
0x8: {g[3:0],1'b0,r[3:1]},{r[0],2'h0,b[3:0],1'b0}
0x9: {b[3:0],1'b0,r[3:1]},{r[0],2'h0,g[3:0],1'b0}
0xA: {r[3:0],1'b0,b[3:1]},{b[0],2'h0,g[3:0],1'b0}
0xB: {g[3:0],1'b0,b[3:1]},{b[0],2'h0,r[3:0],1'b0}
0xC~0xF: Not allowed
0xA: RGB444 format 2
Bit[3:0]: Output sequence
0x0: {4'b0,b[3:0]},{g[3:0],r[3:0]}
0x1: {4'b0,r[3:0]},{g[3:0],b[3:0]}
0x2: {4'b0,b[3:0]},{r[3:0],g[3:0]}
0x3: {4'b0,r[3:0]},{b[3:0],g[3:0]}
0x4: {4'b0,g[3:0]},{b[3:0],r[3:0]}
0x5: {4'b0,g[3:0]},{r[3:0],b[3:0]}
0x6: {b[3:0],g[3:0],2'h0},{r[3:0],b[3:0],2'h0,g[3:0],r[3:0],2'h0}0x7: {r[3:0],g[3:0],2'h0},{b[3:0],r[3:0],2'h0,g[3:0],b[3:0],2'h0}0x8: {b[3:0],r[3:0],2'h0},{g[3:0],b[3:0],2'h0,r[3:0],g[3:0],2'h0}
0x9: {r[3:0],b[3:0],2'h0},{g[3:0],r[3:0],2'h0,b[3:0],g[3:0],2'h0}0xA: {g[3:0],b[3:0],2'h0},{r[3:0],g[3:0],2'h0,b[3:0],r[3:0],2'h0}0xB: {g[3:0],r[3:0],2'h0},{b[3:0],g[3:0],2'h0,r[3:0],b[3:0],2'h0}
0xC~0xF: Not allowed
0xB~0xE: Not allowed
0xF: Bypass formatter module
Bit[3:0]: Output format
0x8: Raw
0x9: YUV422

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-15
addressformat control registers (sheet 4 of 4)
register namedefault
value

R/W

description

0x4301

FORMAT CTRL 01

0x00

RW

Bit[1:0]: YUV422 UV control
00: U/V generated from average
01: U/V generated from first pixel
10: Not valid
11: U/V generated from second pixel

0x4302YMAX VALUE

0x03

RW

Bit[7:2]: Not usedBit[1:0]: Set y max clip value[9:8]0x4303YMAX VALUE

0xFF

RW

Bit[7:0]: Set y max clip value[7:0]0x4304YMIN VALUE

0x00

RW

Bit[7:2]: Not usedBit[1:0]: Set y min clip value[9:8]0x4305YMIN VALUE

0x00

RW

Bit[7:0]: Set y min clip value[7:0]0x4306

UMAX VALUE

0x03

RW

Bit[7:2]: Not usedBit[1:0]: Set u max clip value[9:8]0x4307

UMAX VALUE

0xFF

RW

Bit[7:0]: Set u max clip value[7:0]0x4308UMIN VALUE

0x00

RW

Bit[7:2]: Not usedBit[1:0]: Set u min clip value[9:8]0x4309UMIN VALUE

0x00

RW

Bit[7:0]: Set u min clip value[7:0]0x430A

VMAX VALUE

0x03

RW

Bit[7:2]: Not usedBit[1:0]: Set v max clip value[9:8]0x430B

VMAX VALUE

0xFF

RW

Bit[7:0]: Set v max clip value[7:0]0x430CVMIN VALUE

0x00

RW

Bit[7:2]: Not usedBit[1:0]: Set v min clip value[9:8]0x430D

VMIN VALUE

0x00

RW

Bit[7:0]: Set v min clip value[7:0]

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-23

7.16 compression control [0x4400 ~ 0x4458]
table 7-16

compression control registers (sheet 1 of 3)

address

register name0x4400COMPRESSIONCTRL00default
value

R/W

description
Bit[7]:

0x4401COMPRESSIONCTRL01

0x81

0x01

RW

input_format
0:
YUV4201:
YUV422
Bit[6:0]: JFIFO read speed control

RW

Bit[7:4]: SFIFO output buffer speed control
Bit[3]:
Read SRAM enable when blanking0:
Disable1:
EnableBit[2]:
Read SRAM at first blanking0:
Disable1:
EnableBit[1:0]: SFIFO read speed control
Bit[7]:

0x4402COMPRESSIONCTRL020x10

RW

SFIFO output control mode0:
Control by HREF and valid which
before scale down
1:
Control by input HREF and valid
Bit[6:4]: SOF control
001: Start at the first valid HREF
010: Start at the eighth valid HREF
Bit[3:0]: SFIFO output buffer speed control atlast stripe
Bit[7]:

0x4403COMPRESSIONCTRL030x33

RW

Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

Memory select0:
Select ROM QT
1:
Select SRAM QTMPEG enable
Enable zero stuff
Enable Huffman table output
Rounding enable for C
Rounding enable for Y
Input shift 128 select for C
Input shift 128 select for Y

0x4404COMPRESSIONCTRL040x24

RW

jfifo_pwrdn
SFIFO power down
Header output enable
Enable gated clock0:
Disable gated clock
1:
Enable gated clock
Bit[3]:
Substitute 0xFF to 0xFE in QT
Bit[2:0]: Quantization rounding
bias: Set value = Bias/8

0x4405COMPRESSIONCTRL050x40

RW

Bit[7:0]: QZ out truncate for Y

05.13.2011

Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-16

compression control registers (sheet 2 of 3)
default
value

R/W

COMPRESSIONCTRL06

0x40

RW

Bit[7:0]: QZ out truncate for C

COMPRESSIONCTRL07

0x0C

RW

Bit[7]:
Enable read QTA auto increment
Bit[5:0]: QS
Quantization scale

address

register name0x44060x4407

description

Bit[7]:

0x4408COMPRESSION ISI
CTRL

0x00

RW

Scalado mode enable0:
Normal1:
Insert 0xFF after EOB
Bit[6]:
Compression size manual enableBit[5:4]: Reserved
Bit[3]:
Replace 0xFF to 0xFE in comment
data
Bit[2]:
Cut 0xD9 at the end of frameBit[1]:
EOI generation enable
Bit[0]:ISI insert

0x4409COMPRESSIONCTRL090x00

RW

Bit[7:0]: D9 data

0x440ACOMPRESSIONCTRL0A

0x4E

RW

Bit[7:0]: JFIFO output delay

0x440BCOMPRESSIONCTRL0B

0x16

RW

Bit[7:6]: Not usedBit[5]:
Dummy read speed manual modeBit[4:0]: SFIFO SOF delay

0x440CCOMPRESSIONCTRL0C

0x00

RW

Bit[7:0]: Dummy read speed

0x440DCOMPRESSIONCTRL0D

0x0A

RW

Bit[7:5]: Not usedBit[4]:JFIFO test1
Bit[3:0]: JFIFO rm

0x440ECOMPRESSIONCTRL0E

0x09

RW

Bit[7:5]: Not usedBit[4]:SFIFO test1
Bit[3:0]: SFIFO rm

0x4410COMPRESSION QT
DATA

0x00

RW

Bit[7:0]: QT data

0x4411COMPRESSION QT
ADDR

0x00

RW

Bit[7:0]: QT address

0x4412COMPRESSION ISI
DATA

0x00

RW

Bit[7:0]: ISI dataR

Bit[7:4]: Not usedBit[3]:
D9 odd (read only)Bit[2]:
Reset counter write0:
Not valid
1:
Reset counterBit[1]:ISO EOF0x4413COMPRESSION ISI
CTRL

proprietary to OmniVision Technologies–

PRELIMINARY SPECIFICATION

version 1.3

7-25

table 7-16

compression control registers (sheet 3 of 3)
default
value

R/W

COMPRESSIONLENGTH–R

Bit[7:0]: Compression length[23:16]

0x4415COMPRESSIONLENGTH–R

Bit[7:0]: Compression length[15:8]

0x4416COMPRESSIONLENGTH–R

Bit[7:0]: Compression length[7:0]0x4417

JFIFO OVERFLOW–R

Bit[7:1]: Not usedBit[0]:JFIFO overflow indicator

0x4420~0x442FCOMPRESSIONCOMMENT

0x00

RW

Compression Comment Data Embedded inCompression Data

0x4430COMPRESSIONCOMMENT

0x00

RW

Comment Length
Two bytes align0x4431COMPRESSIONCOMMENT

0xFE

RW

Comment Data Marker

0x4440COMPRESSION
H SIZE MANUAL

0x02

RW

Compression Header Horizontal Size Manual

0x4441COMPRESSION
H SIZE MANUAL

0x80

RW

Compression Header Horizontal Size Manual

0x4442COMPRESSIONV SIZE MANUAL

0x01

RW

Compression Header Vertical Size Manual

0x4443COMPRESSIONV SIZE MANUAL

0xE0

RW

Compression Header Vertical Size Manual

0x4457

DRI HIGH

0x00

RW

Compression Dri High0x4458DRI LOW

0x02

RW

Compression Dri Low

address

register name

0x441405.13.2011

PRELIMINARY SPECIFICATION

description

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

7.17 VFIFO control [0x4600 ~ 0x460D]
table 7-17
address

VFIFO registers
register namedefault
value

R/W

description
Bit[7:6]: Not usedBit[5]:
Compression output fixedheight enable0:
In compression mode2,
Compression height isdifferent in each frame1:
in compression mode2,
Compression height isfixed in each frame
Bit[4]:
Test pattern enable,
incremental pattern
Bit[3:0]: Debug mode

0x4600

VFIFO CTRL00

0x80

RW

0x4602

VFIFO HSIZE

0x04

RW

Compression Output Width High Byte

0x4603

VFIFO HSIZE

0x00

RW

Compression Output Width Low Byte

0x4604

VFIFO VSIZE

0x03

RW

Compression Output Height High Byte

0x4605VFIFO HSIZE

0x00

RW

Compression Output Height Low Byte

0x460CVFIFO CTRL0C

0x20

RW

0x460D

VFIFO CTRL0D

0x00

RW

proprietary to OmniVision Technologies

Bit[7:4]: Compression dummy data
pad speedBit[2]:
Footer disable
Compression footer disable0:
In compression mode2
footer will be added in
the last six bytes ofeach frame
1:
Disable footer
Bit[1]:PCLK manual enable
0:
DVP PCLK divider
control by auto mode
1:
DVP PCLK divider
control by 0x3824[4:0]
Bit[0]:
Not used
Dummy Data

PRELIMINARY SPECIFICATION

version 1.3

7-27

7.18 DVP control [0x4709 ~ 0x4745]
table 7-18

DVP control registers (sheet 1 of 3)

address

register namedefault
value

R/W

description

0x4709

DVP VSYNC WIDTH0

0x02

RW

VSYNC Width Line Unit

0x470A

DVP VSYNC WIDTH1

0x00

RW

VSYNC Width PCLK Unit High Byte

0x470B

DVP VSYNC WIDTH2

0x01

RW

VSYNC Width PCLK Unit Low Byte

0x4711

PAD LEFT CTRL

0x00

RW

HSYNC Mode Left Padding Pixel CountAdd padding data at start of a line

0x4712

PAD RIGHT CTRL

0x00

RW

HSYNC Mode Right Padding Pixel CountAdd padding data at end of a line

RW

Bit[7:3]: Not usedBit[2:0]: Compression mode select001: Compression mode 1
010: Compression mode 2011: Compression mode 3
100: Compression mode 4
101: Compression mode 5
110: Compression mode 6

0x4713COMPRESSION MODE
SELECT

0x02

0x4715656 DUMMY LINE

0x00

RW

Bit[7:4]: Not usedBit[3:0]: CCIR656 dummy line number
Control dummy line number at
beginning of the frame

0x4719CCIR656 CTRL

0x01

RW

Bit[7:2]: Not usedBit[1:0]: CCIR656 EAV/SAV option

0x471BHSYNC CTRL00

0x02

RW

Bit[7:1]: Not usedBit[0]:HSYNC mode enable

RW

Bit[7:3]: Not usedBit[2]:
vsync_sel1_clr
Bit[1:0]: vsync_mode
00: VSYNC positive edge
trigger by end of field,
negative edge trigger bystart of frame
01: VSYNC positive edge
trigger by end of frame,
the width define byregister
10: VSYNC positive edge
trigger by start of field,
the width defined byregister

0x471D

05.13.2011

DVP VSYNC CTRL

0x01

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-18

DVP control registers (sheet 2 of 3)

address

register namedefault
value

R/W

description

0x471FDVP HREF CTRL

0x40

RW

HREF Minimum Blanking in Compression
Mode230x4721VERTICAL STARTOFFSET

0x01

RW

Bit[7:4]: Debug modeBit[3:0]: Vertical start delay between
video output and video input

0x4722VERTICAL END OFFSET

0x00

RW

Bit[7:4]: Not usedBit[3:0]: Vertical end delay between
video output and video input

0x4723

DVP CTRL23

0x00

RW

DVP Compression Mode456 Skip Line
NumberBit[7]:

0x4730CCIR656 CTRL00

0x00

RW

SYNC code selection
0:
Auto generate sync
code
1:
Sync code from registersetting 0x4732~4735
Bit[6]:
F value in CCIR656 SYNC
code when fixed f value
Bit[5]:
Fixed f value
Bit[4:3]: Blank toggle data options
00: Toggle data is
1'h040/1'h200
01: Use register setting
0x4736~0x4738
10: Blanking data always
keep 0Bit[2]:
Debug modeBit[1]:
Clip data disable
Bit[0]:CCIR656 mode enable

0x4731

CCIR656 CTRL01

0x01

RW

Bit[7:1]: Not usedBit[0]:
Blanking toggle data order
option0x4732

CCIR656 FS

0x01

RW

CCIR656 SYNC Code Frame Start

0x4733

CCIR656 FE

0x0F

RW

CCIR656 SYNC Code Frame End

0x4734

CCIR656 LS

0x00

RW

CCIR6656 SYNC Code Line Start

0x4735CCIR656 LE

0x00

RW

CCIR656 SYNC Code Line End

0x4736CCIR656 CTRL6

0x00

RW

Bit[7:4]: Not usedBit[3:2]: Toggle data0[9:8]
Bit[1:0]: Toggle data1[9:8]0x4737CCIR656 CTRL7

0x00

RW

Bit[7:0]: Toggle data0[7:0]0x4738CCIR656 CTRL8

0x00

RW

Bit[7:0]: Toggle data1[7:0]

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-29

table 7-18
address

0x47400x47410x474505.13.2011

DVP control registers (sheet 3 of 3)
register name

POLARITY CTRL00TEST PATTERNDATA ORDER

default
value

0x20

0x00

0x00

PRELIMINARY SPECIFICATION

R/W

description

RW

Bit[7:6]: Not usedBit[5]:PCLK polarity
0:
Active low
1:
Active highBit[4]:
Reserved
Bit[3]:
Gate PCLK under VSYNC
Bit[2]:
Gate PCLK under HREF
Bit[1]:
HREF polarity
0:
Active low
1:
Active highBit[0]:
VSYNC polarity
0:
Active low
1:
Active highRW

Bit[7:3]: Not usedBit[2]:
Test pattern enableBit[1]:
Test pattern select0:Output test pattern 01:
Output test pattern 1
Bit[0]:
Test pattern 8-bit/10-bit
0:10-bit test pattern1:
8-bit test pattern

RW

Bit[7:3]: Not usedBit[2:1]: DVP order option for debug
00: D[9:0]
10: {D[7:0],D[9:8]}
x1: {D[1:0],D[9:2]}
Bit[0]:
Output data order0:
Normal output
1:
Reverse output data bit
order

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

7.19 ISP frame control [0x4901 ~ 0x4902]
table 7-19
address

0x49010x4902

ISP frame control registers
register name

FRAME CTRL01

FRAME CTRL02

default
value

0x00

0x00

R/W

description

RW

Control Passed Frame Number
When both ON and OFF number set to 0x00, frame control
is in bypass modeBit[7:4]: Not usedBit[3:0]: Frame ON number

RW

Control Masked Frame Number
When both ON and OFF number set to 0x00, frame control
is in bypass modeBit[7:4]: Not usedBit[3:0]: Frame OFF number

7.20 ISP top control [0x5000 ~ 0x5063]
table 7-20
address

ISP top control registers (sheet 1 of 4)
register namedefault
value

R/W

description
Bit[7]:

0x5000ISP CONTROL 00

proprietary to OmniVision Technologies

0x06

RW

LENC correction enable0:
Disable1:
EnableBit[6]:
Reserved
Bit[5]:
Gamma enable0:
Disable1:
EnableBit[4:3]: Reserved
Bit[2]:
Black pixel cancellation enable0:
Disable1:
EnableBit[1]:White pixel cancellation enable0:
Disable1:
EnableBit[0]:
Color interpolation enable0:
Disable1:
EnablePRELIMINARY SPECIFICATION

version 1.3

7-31

table 7-20
address

ISP top control registers (sheet 2 of 4)
register namedefault
value

R/W

description
Bit[7]:

0x50010x50030x500405.13.2011

ISP CONTROL 01

ISP CONTROL 03

ISP CONTROL 04

0x01

0x08

0x08

RW

Special digital effect enable0:
Disable1:
EnableBit[6]:
Reserved
Bit[5]:
Scale enable0:
Disable1:
EnableBit[4:3]: Reserved
Bit[2]:
UV average enable0:
Disable1:
EnableBit[1]:
Color matrix enable0:
Disable1:
EnableBit[0]:
Auto white balance enable0:
Disable1:
EnableRW

Bit[7:3]: Reserved
Bit[2]:
Bin enable0:
Disable1:
EnableBit[1]:
Reserved
Bit[0]:
Solarize enable0:
Disable1:
EnableRW

Bit[7:4]: Reserved
Bit[3]:
Size auto control enable
0:
Manual1:
Automatic
Bit[2:0]: Reserved

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-20
address

ISP top control registers (sheet 3 of 4)
register namedefault
value

R/W

description
Bit[7]:
Bit[6]:

Bit[5]:

Bit[4]:
0x5005

ISP CONTROL 05

0x36

RW

Bit[3]:
Bit[2]:

Bit[1]:

Bit[0]:

0x5006~0x501CRSVD––

Reserved

Reserved
AWB bias manual enable0:
Disable1:
EnableAWB bias ON enable0:
Disable1:
EnableAWB bias plus enable0:
Disable1:
EnableReserved
LENC bias ON enable0:
Disable1:
Enable
GMA bias ON enable0:
Disable1:
EnableLENC bias manual enable0:
Disable1:
Enable0x501D

ISP MISC

0x00

RW

Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3:0]:

0x501ERSVD––

Reserved

RW

Format Control
Bit[7:6]: Not usedBit[5]:
Enable option
Bit[4]:
Reserved
Bit[3]:
Format vfirstBit[2:0]: Format select000: YUV422
001: RGB
010: Dither
011: RAW after DPC
101: RAW after CIP

0x501F0x5020

FORMAT CTRLDITHER CTRL 0

proprietary to OmniVision Technologies

0x03

0x00

RW

Bit[7]:
Bit[6]:
Bit[5:4]:
Bit[3:2]:
Bit[1:0]:

Reserved
SDE AVG manual enable
AWB YUV2CBCR enable
Average size manual enable
Reserved

Not used
Dither MUX
R dithering
G dithering
B dithering

PRELIMINARY SPECIFICATION

version 1.3

7-33

table 7-20
address

ISP top control registers (sheet 4 of 4)
register namedefault
value

R/W

description
Bit[7]:

Test enable0:
Test disable
1:
Color bar enableBit[6]:
RollingBit[5]:
Transparent
Bit[4]:
Square black and whiteBit[3:2]: Color bar style
00: Standard 8 color bar
01: Gradual change at vertical mode 1
10: Gradual change at horizontal
11: Gradual change at vertical mode 2
Bit[1:0]: Test select
00: Color bar
01: Random data
10: Square data
11: Black image

0x503DPRE ISP TESTSETTING 1

0x00

RW

0x503E~0x5060

RSVD––

Reserved

0x5061ISP SENSOR BIAS I–RISP Sensor Bias Input

0x5062

ISP SENSOR GAIN I–R

ISP Real Gain Input High Byte

0x5063

ISP SENSOR GAIN I–R

ISP Real Gain Input Low Byte

7.21 AWB control [0x5180 ~ 0x51D0]
table 7-21

AWB registers (sheet 1 of 3)

address

register namedefault
value

R/W

0x5180AWB CONTROL 00

0xFF

RW

Bit[7:0]: AWB B blockdescription

0x5181AWB CONTROL 01

0x58

RW

Bit[7:6]:
Bit[5:4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

0x5182AWB CONTROL 02

0x11

RW

Bit[7:4]: Max local counterBit[3:0]: Max fast counter

05.13.2011

PRELIMINARY SPECIFICATION

Step local
Step fast
Slop 8xSlop 4x
One zone
AVG all

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-21
address

AWB registers (sheet 2 of 3)
register namedefault
value

R/W

description
Bit[7]:

0x5183AWB CONTROL 03

0x90

RW

AWB simple enable0:
AWB advance1:
AWB simple
Bit[6]:
YUV enable0:
YUV enable1:
Simple YUV enableBit[5]:AWB preset
Bit[4]:AWB SIMF
Bit[3:2]: AWB win
Bit[1:0]: Reserved

0x5184AWB CONTROL 04

0x25

RW

Bit[7:6]:
Bit[5]:
Bit[4:2]:
Bit[1:0]:

Bit[7:4]: Stable range unstable
Threshold for unstable to stable change
Bit[3:0]: Stable range stable
Threshold for stable to unstable changeCount area selection
G enableCount limit control
Counter threshold

0x5185AWB CONTROL 05

0x24

RW

0x5186~0x5190AWB CONTROL–

RW

0x5191AWB CONTROL 17

0xFF

RW

Bit[7:0]: AWB top limit

0x5192AWB CONTROL 18

0x00

RW

Bit[7:0]: AWB bottom limit

0x5193AWB CONTROL 19

0xF0

RW

Bit[7:0]: Red limit

0x5194AWB CONTROL 20

0xF0

RW

Bit[7:0]: Green limit

0x5195AWB CONTROL 21

0xF0

RW

Bit[7:0]: Blue limit

Advanced AWB Control

Bit[7:6]:
Bit[5]:
Bit[4]:
Bit[3:2]:
0x5196AWB CONTROL 22

0x03

RW

Bit[1]:
Bit[0]:
0x5197AWB CONTROL 23

0x02

RW

0x5198~0x519D

RSVD––

Reserved

0x519EAWB CONTROL 30

0x30

RW

Bit[7:4]:
Bit[3]:
Bit[2]:
Bit[1:0]:

proprietary to OmniVision Technologies

Reserved
AWB freeze
Reserved
AWB simple selection
00: AWB simple from after AWB gain
01: AWB simple from after GMA
10: AWB simple from after GMA
11: AWB simple from after AWB gain
Fast enable
AWB bias statBit[7:0]: Local limit

Reserved
Local limit selectSimple stable selectReserved

PRELIMINARY SPECIFICATION

version 1.3

7-35

table 7-21

AWB registers (sheet 3 of 3)

address

register namedefault
value

R/W

description

0x519F~
0x51D0AWB G SUM–R

AWB Debug Information

7.22 CIP control [0x5300 ~ 0x530F]
table 7-22

CIP control registers (sheet 1 of 2)
default
value

R/W

description

CIP SHARPENMTTHRESHOLD 1

0x08

RW

Color Interpolation Sharpen MT
Threshold 10x5301CIP SHARPENMTTHRESHOLD 2

0x48

RW

Color Interpolation Sharpen MT
Threshold 20x5302

CIP SHARPENMT OFFSET1

0x18

RW

CIP Sharpen MT Offset1(Y edge mt manual setting when
0x5308[6]=1)0x5303

CIP SHARPENMT OFFSET2

0x0E

RW

CIP Sharpen MT Offset2

0x5304

CIP DNS THRESHOLD 1

0x08

RW

CIP DNS Threshold 10x5305

CIP DNS THRESHOLD 2

0x48

RW

CIP DNS Threshold 20x5306

CIP DNS OFFSET1

0x09

RW

CIP DNS Offset1(DNS threshold manual setting when
0x5308[4]=1)

0x5307

CIP DNS OFFSET2

0x16

RW

CIP DNS Offset2

address

register name0x5300Bit[7]:
Bit[6]:
Bit[4]:
Bit[3]:
Bit[2:0]:

Not used
CIP edge MT manual enable
CIP DNS manual enableNot used
CIP threshold for BR sharpen

0x5308CIP CTRL

0x25

RW

0x5309CIP SHARPENTH
THRESHOLD 1

0x08

RW

CIP Sharpen TH Threshold 10x530ACIP SHARPENTH
THRESHOLD 2

0x48

RW

CIP Sharpen TH Threshold 20x530BCIP SHARPENTH OFFSET1

0x04

RW

CIP Sharpen TH Offset1(Sharpen threshold manual setting when
0x5308[6]=1)0x530CCIP SHARPENTH OFFSET2

0x06

RW

CIP Sharpen TH Offset2

0x530DCIP EDGE MT AUTO–R

CIP Edge MT Auto Read

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-22

CIP control registers (sheet 2 of 2)
default
value

R/W

description

CIP DNS THRESHOLD
AUTO

–

R

CIP DNS Threshold Auto Read

CIP SHARPEN THRESHOLD
AUTO

–

R

CIP Sharpen Threshold Auto Readaddress

register name0x530E0x530F7.23 CMX control [0x5380 ~ 0x538B]
table 7-23

CMX control registers

address

register namedefault
value

R/W

0x5380

CMX0

0x00

RW

Bit[7:1]: Reserved
Bit[0]:
gb_cbcr

0x5381

CMX1

0x20

RW

Bit[7:0]: CMX1

0x5382

CMX2

0x64

RW

Bit[7:0]: CMX2

0x5383

CMX3

0x08

RW

Bit[7:0]: CMX3

0x5384

CMX4

0x30

RW

Bit[7:0]: CMX4

0x5385

CMX5

0x90

RW

Bit[7:0]: CMX5

0x5386

CMX6

0xC0

RW

Bit[7:0]: CMX6

0x5387

CMX7

0xA0

RW

Bit[7:0]: CMX7

0x5388

CMX8

0x98

RW

Bit[7:0]: CMX8

0x5389

CMX9

0x08

RW

Bit[7:0]: CMX9

0x538ACMXSIGN

0x01

RW

CmxsignBit[7:1]: Reserved
Bit[0]:CMX9 sign

RW

CmxsignBit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:

0x538BCMXSIGN

proprietary to OmniVision Technologies

0x98

description

CMX8 sign
CMX7 sign
CMX6 sign
CMX5 sign
CMX4 sign
CMX3 sign
CMX2 sign
CMX1 sign

PRELIMINARY SPECIFICATION

version 1.3

7-37

7.24 gamma control [0x5480 ~ 0x5490]
table 7-24

gamma control registers

address

register namedefault
value

R/W

0x5480GAMMA CONTROL00

0x01

RW

Bit[7:2]: Reserved
Bit[1]:YSLP15 manual enable
Bit[0]:
BIAS plus on

0x5481GAMMA YST00

0x26

RW

Bit[7:0]: Y yst1

0x5482GAMMA YST01

0x35

RW

Bit[7:0]: Y yst2

0x5483GAMMA YST02

0x48

RW

Bit[7:0]: Y yst3

0x5484GAMMA YST03

0x63

RW

Bit[7:0]: Y yst4

0x5485GAMMA YST04

0x6E

RW

Bit[7:0]: Y yst5

0x5486GAMMA YST05

0x77

RW

Bit[7:0]: Y yst6

0x5487GAMMA YST06

0x80

RW

Bit[7:0]: Y yst7

0x5488GAMMA YST07

0x88

RW

Bit[7:0]: Y yst8

0x5489GAMMA YST08

0x8F

RW

Bit[7:0]: Y yst9

0x548AGAMMA YST09

0x96

RW

Bit[7:0]: Y yst10

0x548BGAMMA YST0A

0xA3

RW

Bit[7:0]: Y yst11

0x548CGAMMA YST0B

0xAF

RW

Bit[7:0]: Y yst12

0x548DGAMMA YST0C

0xC5

RW

Bit[7:0]: Y yst13

0x548EGAMMA YST0D

0xD7

RW

Bit[7:0]: Y yst14

0x548FGAMMA YST0E

0xE8

RW

Bit[7:0]: Y yst15

0x5490GAMMA YSLP15

0x0F

RW

Bit[7:0]: Y yslp15
Slope of yst15

05.13.2011

PRELIMINARY SPECIFICATION

description

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

7.25 SDE control [0x5580 ~ 0x558C]
table 7-25
address

SDE control registers (sheet 1 of 2)
register namedefault
value

R/W

description
Bit[7]:

Bit[6]:

Bit[5]:

Bit[4]:
0x5580

SDE CTRL0

0x00

RW

Bit[3]:

Bit[2]:

Bit[1]:

Bit[0]:

Fixed Y enable0:
Disable1:
EnableNegative enable0:
Disable1:
EnableGray enable0:
Disable1:
EnableFixed V enable0:
Disable1:
EnableFixed U enable0:
Disable1:
EnableContrast enable0:
Disable1:
EnableSaturation enable0:
Disable1:
EnableHue enable0:
Disable1:
Enable0x5581

SDE CTRL1

0x80

RW

Bit[7:0]: Hue cos coefficient

0x5582

SDE CTRL2

0x00

RW

Bit[7:0]: Hue sin coefficient

RW

Bit[7:0]: Saturation U when 0x5580[1]=1 and
0x5588[6]=1, max value for auto color
saturation adjust when 0x5580[1]=1 and
0x5588[6]=0; or fixed U when 0x5580[3]=1

0x5583

SDE CTRL30x400x5584

SDE CTRL4

0x00

RW

Bit[7:0]: Saturation V when 0x5580[1]=1 and
0x5588[6]=1, min value for auto color
saturation adjust when 0x5580[1]=1 and
0x5588[6]=0; or Vreg when 0x5580[4]=10x5585

SDE CTRL5

0x00

RW

Bit[7:0]: Y offset for contrast when 0x5044[3]=1; orfixed Y when 0x5580[7]=10x5586

SDE CTRL6

0x20

RW

Bit[7:0]: Y gain for contrast

0x5587

SDE CTRL7

0x00

RW

Bit[7:0]: Y bright for contrast

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-39

table 7-25
address

SDE control registers (sheet 2 of 2)
register namedefault
value

R/W

description
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:

0x5588SDE CTRL8

0x00

RW
Bit[2]:

Bit[1]:
Bit[0]:

Reserved
Auto color saturation adjust manual enable
Sign5 for hue V, cos
Sign4 for hue U, cos
Sign3 Y bright sign for contrast
0:
Keep Y bright sign
1:
Negative Y bright sign
Sign2
Y offset sign for contrast when 0x5044[3]=10:
Keep Y offset sign
1:
Negative Y offset sign
Sign1 for hue V, sin
Sign0 for hue U, sin

0x5589SDE CTRL9

0x08

RW

Bit[7:0]: Auto color saturation adjust threshold 1
Valid when 0x5580[1]=10x558A

SDE CTRL10

0x80

RW

Bit[7:1]: Reserved
Bit[0]:
Auto color saturation adjust threshold 2[8]Valid when 0x5580[1]=10x558BSDE CTRL11

0x00

RW

Bit[7:0]: Auto color saturation adjust threshold 2[7:0]
Valid when 0x5580[1]=10x558CSDE CTRL12–

R

Bit[7:0]: Auto color saturation adjust value read out

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

7.26 scale control [0x5600 ~ 0x5606]
table 7-26
address

scale control registers (sheet 1 of 2)
register namedefault
value

R/W

description
Bit[7]:
Bit[6]:

Bit[5]:

Bit[4]:

0x5600SCALE CTRL 0

0x10

RW

Bit[3]:

Bit[2]:

Bit[1]:

Bit[0]:

0x5601SCALE CTRL 1

0x00

proprietary to OmniVision Technologies

RW

Reserved
V firstYUV444 to 422 output U or V first0:
U first1:
V firstUV drop
YUV444 to 422 drop mode versus AVG mode
selection
0:
AVG mode1:
Drop mode
Auto mode
Scale auto mode versus manual mode
selection
0:
Manual mode
1:
Auto mode
Horizontal round
DCW horizontal rounding0:
No horizontal rounding
1:
Horizontal rounding
Horizontal drop
DCW horizontal drop mode0:
Horizontal average mode
1:
Horizontal drop mode
Vertical round
DCW vertical rounding0:
No vertical rounding
1:
Vertical rounding
Vertical drop
DCW vertical drop mode
0:
Vertical average mode
1:
Vertical drop modeBit[7]:
Reserved
Bit[6:4]: Horizontal div
DCW scale times
000: DCW 1 time001: DCW 2 time
010: DCW 4 time
011: DCW 8 time
1xx: DCW 16 timeBit[2:0]: Vertical div
DCW scale times
000: DCW 1 time001: DCW 2 time
010: DCW 4 time
011: DCW 8 time
1xx: DCW 16 time

PRELIMINARY SPECIFICATION

version 1.3

7-41

table 7-26

scale control registers (sheet 2 of 2)

address

register namedefault
value

R/W

0x5602SCALE CTRL 2

0x02

RW

Bit[7:0]: XSC[15:8]

0x5603SCALE CTRL 3

0x00

RW

Bit[7:0]: XSC[7:0]0x5604SCALE CTRL 4

0x02

RW

Bit[7:0]: YSC[15:8]

0x5605SCALE CTRL 5

0x00

RW

Bit[7:0]: YSC[7:0]0x5606SCALE CTRL 6

0x00

RW

Bit[7:4]: Not usedBit[3:0]: Vertical offset

description

7.27 average control [0x5680 ~ 0x56A2]
table 7-27
address

AVG registers (sheet 1 of 3)
register namedefault
value

R/W

description

0x5680X START

0x00

RW

Bit[7:4]: Reserved
Bit[3:0]: X start[11:8]
Horizontal start position for average windowhigh byte, valid when 0x501D[4]=10x5681X START

0x00

RW

Bit[7:0]: X start[7:0]
Horizontal start position for average window
low byte, valid when 0x501D[4]=10x5682Y START

0x00

RW

Bit[7:3]: Reserved
Bit[2:0]: Y start[10:8]
Vertical start position for average window highbyte, valid when 0x501D[4]=10x5683

Y START

0x00

RW

Bit[7:0]: Y start[7:0]
Vertical start position for average window low
byte, valid when 0x501D[4]=10x5684

X WINDOW

0x10

RW

Bit[7:4]: Reserved
Bit[3:0]: Window X[11:8]
Horizontal end position for average windowhigh byte, valid when 0x501D[4]=10x5685

X WINDOW

0xA0

RW

Bit[7:0]: Window X[7:0]
Horizontal end position for average window
low byte, valid when 0x501D[4]=1

RW

Bit[7:3]: Reserved
Bit[2:0]: Window Y[10:8]
Vertical end position for average window highbyte, valid when 0x501D[4]=10x568605.13.2011

Y WINDOW

0x0C

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-27

AVG registers (sheet 2 of 3)

address

register namedefault
value

R/W

0x5687

Y WINDOW

0x78

RW

Bit[7:0]: Window Y[7:0]
Vertical end position for average window low
byte, valid when 0x501D[4]=10x5688

WEIGHT00

0x11

RW

Bit[7:4]: Window 01 weightBit[3:0]: Window 00 weight

0x5689WEIGHT01

0x11

RW

Bit[7:4]: Window 03 weightBit[3:0]: Window 02 weight

0x568A

WEIGHT02

0x11

RW

Bit[7:4]: Window 11 weightBit[3:0]: Window 10 weight

0x568B

WEIGHT03

0x11

RW

Bit[7:4]: Window 13 weightBit[3:0]: Window 12 weight

0x568CWEIGHT04

0x11

RW

Bit[7:4]: Window 21 weightBit[3:0]: Window 20 weight

0x568DWEIGHT05

0x11

RW

Bit[7:4]: Window 23 weightBit[3:0]: Window 22 weight

0x568EWEIGHT06

0x11

RW

Bit[7:4]: Window 31 weightBit[3:0]: Window 30 weight

0x568F

WEIGHT07

0x11

RW

Bit[7:4]: Window 33 weightBit[3:0]: Window 32 weight

description

0x5690AVG CTRL10

0x01

RW

Bit[7:1]: Reserved
Bit[0]:
AVG option0:
Sum=(4*B+9*G*2+10*R)/8
1:
Sum=(B+G*2+R)/4

0x5691

AVG WIN 00–

R

Bit[7:0]: Average of win 00

0x5692

AVG WIN 01–

R

Bit[7:0]: Average of win 01

0x5693

AVG WIN 02–

R

Bit[7:0]: Average of win 02

0x5694

AVG WIN 03–

R

Bit[7:0]: Average of win 03

0x5695

AVG WIN 10–

R

Bit[7:0]: Average of win 10

0x5696

AVG WIN 11–

R

Bit[7:0]: Average of win 11

0x5697

AVG WIN 12–

R

Bit[7:0]: Average of win 12

0x5698

AVG WIN 13–

R

Bit[7:0]: Average of win 13

0x5699AVG WIN 20–

R

Bit[7:0]: Average of win 20

0x569A

AVG WIN 21–

R

Bit[7:0]: Average of win 21

0x569B

AVG WIN 22–

R

Bit[7:0]: Average of win 22

0x569C

AVG WIN 23–

R

Bit[7:0]: Average of win 23

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

7-43

table 7-27

AVG registers (sheet 3 of 3)

address

register namedefault
value

R/W

0x569D

AVG WIN 30–

R

Bit[7:0]: Average of win 30

0x569E

AVG WIN 31–

R

Bit[7:0]: Average of win 31

0x569F

AVG WIN 32–

R

Bit[7:0]: Average of win 32

0x56A0

AVG WIN 33–

R

Bit[7:0]: Average of win 33

0x56A1

AVG READOUT–R

Bit[7:0]: Average value output

0x56A2

AVG WEIGHT
SUM

–

R

Bit[7:0]: Average weight sum

description

7.28 DPC control [0x5780 ~ 0x5794]
table 7-28

DPC control registers (sheet 1 of 2)

address

register namedefault
value

R/W

description

0x5780DPC CTRL00

0x14

RW

DPC Control Register

0x5781DPC CTRL01

0x0F

RW

DPC Control Register

0x5782DPC CTRL02

0x04

RW

DPC Control Register

0x5783

DPC CTRL03

0x02

RW

DPC Control Register

0x5784

DPC CTRL04

0x01

RW

DPC Control Register

0x5785DPC CTRL05

0x01

RW

DPC Control Register

0x5786DPC CTRL06

0x00

RW

DPC Control Register

0x5787

DPC CTRL07

0x04

RW

DPC Control Register

0x5788DPC CTRL08

0x0C

RW

DPC Control Register

0x5789DPC CTRL09

0x00

RW

DPC Control Register

0x578ADPC CTRL0A

0x01

RW

DPC Control Register

0x578BDPC CTRL0B

0x02

RW

DPC Control Register

0x578CDPC CTRL0C

0x03

RW

DPC Control Register

0x578D

DPC CTRL0D

0x03

RW

DPC Control Register

0x578EDPC CTRL0E

0x0F

RW

DPC Control Register

0x578FDPC CTRL0F

0x3F

RW

DPC Control Register

0x5790DPC CTRL10

0x08

RW

DPC Control Register05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-28

DPC control registers (sheet 2 of 2)

address

register namedefault
value

R/W

description

0x5791DPC CTRL11

0x04

RW

DPC Control Register

0x5792DPC CTRL12

0x04

RW

DPC Control Register

0x5793

DPC CTRL13

0x00

RW

DPC Control Register

0x5794

DPC CTRL14

0x03

RW

DPC Control Register7.29 LENC control [0x5800 ~ 0x5849]
table 7-29

LENC control registers (sheet 1 of 6)

address

register namedefault
value

R/W

0x5800

GMTRX00

0x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 00

0x5801

GMTRX01

0x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 01

0x5802

GMTRX02

0x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 02

0x5803

GMTRX03

0x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 03

0x5804

GMTRX04

0x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 04

0x5805

GMTRX05

0x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 05

0x5806

GMTRX100x10RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 06

0x5807

GMTRX110x08

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 07

0x5808GMTRX120x08

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 08

0x5809GMTRX130x08

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 09

0x580AGMTRX140x08

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 0A

0x580B

GMTRX150x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 0B

proprietary to OmniVision Technologies

description

PRELIMINARY SPECIFICATION

version 1.3

7-45

table 7-29

LENC control registers (sheet 2 of 6)

address

register namedefault
value

R/W

0x580CGMTRX20

0x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 0C

0x580D

GMTRX210x08

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 0D

0x580EGMTRX220x00

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 0E

0x580F

GMTRX23

0x00

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 0F

0x5810

GMTRX24

0x08

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 100x5811

GMTRX25

0x10

RW

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 11

0x5812

GMTRX30

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 120x5813

GMTRX310x08

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 13

0x5814

GMTRX32

0x00

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 14

0x5815

GMTRX33

0x00

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 15

0x5816

GMTRX34

0x08

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 16

0x5817

GMTRX35

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 17

0x5818GMTRX40

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 18

0x5819GMTRX410x08

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 19

0x581AGMTRX420x08

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 1A

0x581B

GMTRX43

0x08

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 1B

0x581CGMTRX44

0x08

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 1C

0x581D

GMTRX45

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 1D

0x581EGMTRX50

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 1E

05.13.2011

PRELIMINARY SPECIFICATION

description

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-29

LENC control registers (sheet 3 of 6)

address

register namedefault
value

R/W

0x581F

GMTRX51

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 1F

0x5820

GMTRX52

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 20

0x5821

GMTRX53

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 21

0x5822

GMTRX540x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 22

0x5823

GMTRX55

0x10

R/W

Bit[7:6]: Reserved
Bit[5:0]: Green matrix 23

0x5824

BRMATRX00

0xAA

R/W

Bit[7:4]: Blue matrix 00
Bit[3:0]: Red matrix 00

0x5825

BRMATRX01

0xAA

RW

Bit[7:4]: Blue matrix 01
Bit[3:0]: Red matrix 01

0x5826

BRMATRX02

0xAA

RW

Bit[7:4]: Blue matrix 02
Bit[3:0]: Red matrix 02

0x5827

BRMATRX03

0xAA

RW

Bit[7:4]: Blue matrix 03
Bit[3:0]: Red matrix 03

0x5828

BRMATRX04

0xAA

RW

Bit[7:4]: Blue matrix 04
Bit[3:0]: Red matrix 04

0x5829

BRMATRX05

0xAA

RW

Bit[7:4]: Blue matrix 05
Bit[3:0]: Red matrix 05

0x582A

BRMATRX06

0x99

RW

Bit[7:4]: Blue matrix 06
Bit[3:0]: Red matrix 06

0x582B

BRMATRX07

0x99

RW

Bit[7:4]: Blue matrix 07
Bit[3:0]: Red matrix 07

0x582CBRMATRX08

0x99

RW

Bit[7:4]: Blue matrix 08
Bit[3:0]: Red matrix 08

0x582D

BRMATRX09

0xAA

RW

Bit[7:4]: Blue matrix 09
Bit[3:0]: Red matrix 09

0x582EBRMATRX20

0xAA

RW

Bit[7:4]: Blue matrix 20
Bit[3:0]: Red matrix 20

0x582F

BRMATRX21

0x99

RW

Bit[7:4]: Blue matrix 21
Bit[3:0]: Red matrix 21

0x5830

BRMATRX22

0x88

RW

Bit[7:4]: Blue matrix 22
Bit[3:0]: Red matrix 22

0x5831

BRMATRX23

0x99

RW

Bit[7:4]: Blue matrix 23
Bit[3:0]: Red matrix 23

proprietary to OmniVision Technologies

description

PRELIMINARY SPECIFICATION

version 1.3

7-47

table 7-29

LENC control registers (sheet 4 of 6)

address

register namedefault
value

R/W

0x5832

BRMATRX24

0xAA

RW

Bit[7:4]: Blue matrix 24
Bit[3:0]: Red matrix 24

0x5833

BRMATRX30

0xAA

RW

Bit[7:4]: Blue matrix 30
Bit[3:0]: Red matrix 30

0x5834

BRMATRX31

0x99

RW

Bit[7:4]: Blue matrix 31
Bit[3:0]: Red matrix 31

0x5835

BRMATRX32

0x99

RW

Bit[7:4]: Blue matrix 32
Bit[3:0]: Red matrix 32

0x5836

BRMATRX33

0x99

RW

Bit[7:4]: Blue matrix 33
Bit[3:0]: Red matrix 33

0x5837

BRMATRX34

0xAA

RW

Bit[7:4]: Blue matrix 34
Bit[3:0]: Red matrix 34

0x5838

BRMATRX40

0xAA

R/W

Bit[7:4]: Blue matrix 40
Bit[3:0]: Red matrix 40

0x5839

BRMATRX41

0xAA

R/W

Bit[7:4]: Blue matrix 41
Bit[3:0]: Red matrix 41

0x583A

BRMATRX42

0xAA

R/W

Bit[7:4]: Blue matrix 42
Bit[3:0]: Red matrix 42

0x583B

BRMATRX43

0xAA

R/W

Bit[7:4]: Blue matrix 43
Bit[3:0]: Red matrix 43

0x583CBRMATRX44

0xAA

R/W

Bit[7:4]: Blue matrix 44
Bit[3:0]: Red matrix 44

0x583DLENC BR OFFSET

0x88

R/W

Bit[7:4]: LENC b offset
Bit[3:0]: LENC r offset

0x583EMAX GAIN

0x40

R/W

Bit[7:0]: Maximum gain

0x583FMIN GAIN

0x20

R/W

Bit[7:0]: Minimum gain

0x5840

MIN Q

0x18

R/W

Bit[7]:
Reserved
Bit[6:0]: Minimum Q

R/W

Bit[7:4]: Reserved
Bit[3]:
Add BLC enable0:
Disable BLC add back function
1:
Enable BLC add back function
Bit[2]:
BLC enable0:
Disable BLC function
1:
Enable BLC function
Bit[1]:
Reserved
Bit[0]:
Auto Q enable
0:
Used constant Q (0x40)
1:
Used calculated Q

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

0x584105.13.2011

LENC CTRL59

0x0D

description

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

table 7-29
address

0x58420x58430x58440x58450x58460x58470x5848LENC control registers (sheet 5 of 6)
register name

BR HSCALE

BR HSCAL

BR VSCALE

BR VSCALE

G HSCALE

G HSCAL

G VSCALE

proprietary to OmniVision Technologies

default
value

0x00

0xBD

0x00

0xFE

0x00

0xFC

0x00

R/W

description

RW

Bit[7:3]: Reserved
Bit[2:0]: BR H scale[10:8]
Reciprocal of horizontal step for BR
channel. BR channel in whole image
is divided into 5x5 blocks. The stepis used to point to the border of theadjacent block

RW

Bit[7:0]: BR H scale[7:0]
Reciprocal of horizontal step for BR
channel. BR channel in whole image
is divided into 5x5 blocks. The stepis used to point to the border of theadjacent block

RW

Bit[7:3]: Reserved
Bit[2:0]: BR V scale[10:8]
Reciprocal of vertical step for BR
channel. BR channel in whole image
is divided into 5x5 blocks. The stepis used to point to the border of theadjacent block

RW

Bit[7:0]: BR V scale[7:0]
Reciprocal of vertical step for BR
channel. BR channel in whole image
is divided into 5x5 blocks. The stepis used to point to the border of theadjacent block

RW

Bit[7:3]: Reserved
Bit[2:0]: G H scale[10:8]
Reciprocal of horizontal step for G
channel. G channel in whole image
is divided into 6x6 blocks. The stepis used to point to the border of theadjacent block

RW

Bit[7:0]: G H scale[7:0]
Reciprocal of horizontal step for G
channel. G channel in whole image
is divided into 6x6 blocks. The stepis used to point to the border of theadjacent block

RW

Bit[7:3]: Reserved
Bit[2:0]: G V scale[10:8]
Reciprocal of vertical step for G
channel. G channel in whole image
is divided into 6x6 blocks. The stepis used to point to the border of theadjacent block

PRELIMINARY SPECIFICATION

version 1.3

7-49

table 7-29
address

0x5849LENC control registers (sheet 6 of 6)
default
value

register name

G VSCALE

R/W

0xA9

RW

description
Bit[7:0]: G V scale[7:0]
Reciprocal of vertical step for G
channel. G channel in whole image
is divided into 6x6 blocks. The stepis used to point to the border of theadjacent block7.30 temperature sensor control [0x6700 ~ 0x6721]
table 7-30

TPM control registers

address

register namedefault
value

R/W

description

0x6700~0x6705

TPM CTRL00~05––

Temperature Sensor Control Registers
Bit[7:4]: Reserved
Bit[3:0]: Sample clock must be around 3MHz
If the user has 24 MHz XVCLK, sample
clock = XVCLK/clock divisor => 3MHz =24MHz / 8 (these 4 bits must be 4’b1000)
If the user has 12 MHz XVCLK, sample
clock = XVCLK/clock divisor => 3MHz =12MHz / 4 (these 4 bits must be 4’b0100)

0x6706

TPM CTRL06

0x78

RW

0x6707~0x6718

TPM CTRL09~18––

Temperature Sensor Control Registers

0x6719TPM CTRL19–

R

Bit[7:0]: Measured temperature

0x671A~
0x6721TPM CTRL1A~21––

Temperature Sensor Control Registers

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

8-1

8 operating specifications
8.1 absolute maximum ratings
table 8-1

absolute maximum ratingsparameterabsolute maximum ratinga

ambient storage temperature-40°C to +95°C

supply voltage (with respect to ground)belectro-static discharge (ESD)

a.

VDD-A

4.5V

VDD-D

3V

VDD-IO

4.5V

human body model

2000V

machine model

200V

all input/output voltages (with respect to ground)-0.3V to VDD-IO + 1V

I/O current on any input or output pin±200 mA

peak solder temperature (10 second dwell time)

245°C

exceeding the absolute maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods
may affect device reliability.

b.

for negative voltage with respect to ground, VDD-A (-4.5V), VDD-C (-3V), VDD-IO (-4.5V)

8.2 functional temperaturetable 8-2

functional temperatureparameter

range

operating temperaturea-20°C to +70°C junction temperaturestable image temperatureb

0°C to +50°C junction temperaturea.

sensor functions but image quality may be noticeably different at temperatures outside of stable image rangeb.

image quality remains stable throughout this temperature range

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

8.3 DC characteristics
table 8-3

DC characteristics (-20°C < TJ < 70°C) (sheet 1 of 2)

symbolparameter

min

typ

max

unit

VDD-A

supply voltage (analog)

2.6

2.8

3.0

V

VDD-Dasupply voltage (digital core)

1.425

1.5

1.575

V

VDD-IO

supply voltage (digital I/O)

1.71

1.8

3.0

V

power supply

internal DVDD, DOVDD=1.8V
IDD-A
IDD-IO

active (operating) currentb, cIDDS-SCCBd

IDDS-PWDNd
PO

standby current

28

mA

70

mA

20

µA

20

µA

active (operating) power consumption

PDDS-SCCBPDDS-PWDN

standby power consumption

TBD

mW

TBD

µW

TBD

µW

external DVDD, DOVDD=2.8V
IDD-A
IDD-D

b, c

active (operating) current

IDD-IOIDDS-SCCBIDDS-PWDN

standby current

28

mA

64

mA

6

mA

40

µA

40

µA

active (operating) power consumption

PO
PDDS-SCCBPDDS-PWDN

standby power consumption

TBD

mW

TBD

µW

TBD

µW

external DVDD, DOVDD=1.8V
IDD-A
IDD-D

b, c

active (operating) current

IDD-IOIDDS-SCCBIDDS-PWDN
PO
PDDS-SCCBPDDS-PWDN

standby current

28

mA

64

mA

4

mA

40

µA

40

µA

active (operating) power consumption
standby power consumptione

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

TBD

mW

TBD

µW

TBD

µW

version 1.3

8-3

table 8-3
symbolDC characteristics (-20°C < TJ < 70°C) (sheet 2 of 2)
parameter

min

typ

max

unit

0.54

V

digital inputs (typical conditions: AVDD = 2.8V, DVDD = 1.5V, DOVDD = 1.8V)
VIL

input voltage LOW

VIH

input voltage HIGH

CIN

input capacitor

1.26

V
10

pF

digital outputs (standard loading 25 pF)
VOH

output voltage HIGH

VOL

output voltage LOW

1.62

V
0.18

V

serial interface inputsf

a.
b.

VIL

SIOC and SIOD

-0.5

0

0.54

V

VIH

SIOC and SIOD

1.26

1.8

3.0

V

using the internal DVDD regulator is strongly recommended for minimum power down current
active current is based on sensor resolution at full size and at full speed in compression format. For smaller sizes
such as 720p or below preview, the total active current will be about half.

c.

DOVDD active current is based on loading of 10pF and typical compression format output PCLK (48MHz). For YUV
output with higher PCLK, or higher loading, DOVDD current can go up.

d.

at room temperature and typical supply voltagese.

standby current is measured at room temperaturef.

based on DOVDD = 1.8V.

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

8.4 timing characteristics
table 8-4
symboltiming characteristics
parameter

min

typ

max

unit

6

24

54

MHz

5 (10c)

ns

108

MHz

oscillator and clock input

a.

fOSC

frequency (XVCLK)atr, tfclock input rise/fall timeb

fPCLK

parallel port output pixel clock54

for input clock range 6~27MHz, the OV3660 can tolerate input clock jitter up to 1ns, for input clock range to 54MHz,
the OV3660 can tolerate input clock jitter up to 500psb.

if the PLL is bypassed, the delay from input clock to output clock is approximately 4~5ns

c.

if using the internal PLL

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

9-1

9 mechanical specifications
9.1 physical specifications
figure 9-1

package specifications
S2

1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H

B

WX Y Z
A BCD

C1table 9-1

DJ1

top view

center of BGA (die) =center of the package

S1bottom view

(bumps down)
glass

A
B
C
D
E
F
G
H

J2

A

C2

8 7 6 5 4 3 2 1

dieside view(bumps up)

C3

C4

C
3660_CSP_DS_9_1

package dimensions

parameter

symbol

min

typ

max

unit

package body dimension x

A

4985

5010

5035

µm

package body dimension y

B

4935

4960

4985

µm

package height

C

690

750

810

µm

ball height

C1

100

130

160

µm

package body thickness

C2

575

620

665

µm

cover glass thickness

C3

425

445

465

µm

ball diameter

D

220

250

280

µm

total pin countN

51 (7 NC)pin count x-axis

N18

pin count y-axis

N28

pins pitch x-axis

J1

580

µm

pins pitch y-axis

J2

600

µm

edge-to-pin center distance along x

S1

445

475

505

µm

edge-to-pin center distance along y

S2

350

380

410

µm

05.13.2011

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

9.2 IR reflow specifications
figure 9-2

note

Z1

280.0

The OV3660 uses a

260.0

lead-free package.

240.0

Z2

Z3

Z4

Z5

Z6

198

300.0

178

IR reflow ramp rate requirements
Z7

end

temperature (°C)

220.0
200.0
180.0
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0

time (sec)table 9-2

358
369

338

318

298

278

258

238

218

158

138

118

98

78

58

38

18

-2

-22

0.0

3660_DS_9_2

reflow conditions

condition

exposure

average ramp-up rate (30°C to 217°C)

less than 3°C per second> 100°C

between 330 - 600 seconds> 150°Cat least 210 seconds> 217°Cat least 30 seconds (30 ~ 120 seconds)

peak temperature

245°C

cool-down rate (peak to 50°C)

less than 6°C per second

time from 30°C to 245°C

no greater than 390 seconds

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

10-1

10 optical specifications
10.1 sensor array center
figure 10-1

sensor array center
2912 μm

A1

A2

A3

A4

A5

A6

A7

A8

first pixel readout(-1448 μm, 1222.6 μm)
array center(8 μm, 139 μm)

2167.2 μm

package center(0 μm, 0 μm)

sensorarray

OV3660

top view
note 1 this drawing is not to scale and is for reference only.
note 2 as most optical assemblies invert and mirror the image, the chip is
typically mounted with pin A1 to A8 oriented down on the PCB.

05.13.2011

PRELIMINARY SPECIFICATION

3660_CSP_DS_10_1

proprietary to OmniVision Technologies

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

10.2 lens chief ray angle (CRA)
figure 10-2

chief ray angle (CRA)

30.0
25.0

CRA (degrees)

20.0
15.0
10.0
5.0
CRA

image height (mm)table 10-1

1.790

1.700

1.610

1.520

1.430

1.340

1.250

1.160

1.080

0.990

0.900

0.810

0.720

0.630

0.540

0.450

0.360

0.270

0.180

0.090

0.0
0.000

OV36603660_DS_10_2

CRA versus image height plot (sheet 1 of 2)

field (%)

image height (mm)

CRA (degrees)

0

0

0

0.05

0.090

2.4

0.1

0.180

4.7

0.15

0.270

7.0

0.2

0.360

9.3

0.25

0.450

11.5

0.3

0.540

13.7

0.35

0.630

15.7

0.4

0.720

17.7

0.45

0.810

19.6

0.5

0.900

21.3

0.55

0.990

22.8

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

10-3

table 10-1

CRA versus image height plot (sheet 2 of 2)

field (%)

image height (mm)

CRA (degrees)

0.6

1.080

24.2

0.65

1.160

25.3

0.7

1.250

26.2

0.75

1.340

26.8

0.8

1.430

27.3

0.85

1.520

27.5

0.9

1.610

27.6

0.95

1.700

27.6

1

1.790

27.6

10.3 spectrum response
figure 10-3

spectrum response graph
R
Gr
Gb
B

300

400

500

600

700
wavelength (nm)05.13.2011

PRELIMINARY SPECIFICATION

800

900

1000

1100
3660_DS_10_3

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

rev-1

revision history
version 1.0

09.23.2010•

version 1.1

12.16.2010•

on page iii, under key specifications, added "junction temperature" to temperature range andremoved well capacity•

on page iii, under key specifications, changed image area from "2080 µm x 1548 µm" to "2912 µm
x 2167.2 µm"•

in section 3, updated figure 3-1•

in table 8-2, added "junction temperature" to range•

in section 10, updated figure 10-1

version 1.2

05.13.2011

initial release01.31.2011•

in features section on page i, removed "support for video or snapshot operations", "support forinternal and external frame synchronization for frame exposure mode", and "support for minimizing
artifacts on binned image"•in features section on page i, added "support 2x2 binning with binning filter to remove binning
artifacts"•

in key specifications section on page i, added "(1.8V recommended)" to I/O power supply
specification•in key specifications section on page i, removed "/ frame exposure" from shutter specification•

moved section 3, pixel array structure to section 2.3•

moved section 2.3, format and frame rate to section 2.7•

moved section 2.4, I/O control to section 2.8•

moved section 2.5, system clock control to section 2.9•

moved section 2.6, SCCB interface to chapter 6 and added subsections for data transfer protocol,
message format, read/write operation, and SCCB timing•

moved table 2-6, group write registers to new section 2.10, group write•changed chapter 4, image sensor core digital functions (with all subsections) to chapter 3•

in new chapter 3, added section 3.2.2, scaling•in new chapter 3, renamed AEC/AGC algorithms section to section 3.4, exposure/gain control andcompletely re-wrote the section•

removed AEC/AGC steps section (previously section 4.5)•

moved section 4.6, black level calibration to section 3.5•

removed light frequency selection (previously section 4.7) and merged content into new section 3.4•

removed digital gain (previously section 4.8) and merged content into new section 3.4•

moved section 4.9, strobe flash to section 3.6

PRELIMINARY SPECIFICATION

proprietary to OmniVision Technologies

OV3660

color CMOS QSXGA (3 megapixel) image sensor with OmniBSI™ technology•

moved section 4.10, one time programmable (OTP) memory to section 3.7 and completely re-wrote
the section•

moved section 4.11, temperature sensor to section 3.8 and completely re-wrote the section•changed chapter 5, image sensor processor digital functions (with all subsections) to chapter 4•

moved section 5.6 to section 4.6, renamed section to "color interpolation (CIP) and sharpening",
and re-wrote first paragraph•removed (previously numbered) section 5.8, UV average and (previously numbered) section 5.9,
scaling•

moved section 5.10, UV adjust to section 4.8 and renamed section to "auto color saturation adjust"•moved section 5.11, special digital effects (SDE) to section 4.9•

removed (previously numbered) section 5.12, ISP format and (previously numbered) section 5.13,
average•changed chapter 6, image sensor output interface digital functions (with all subsections) to chapter
5•

removed (previously numbered) section 6.2, system control and (previously numbered) section 6.3,
format description•

in chapter 7, added subsection number and title for each register table•

renamed section 8.4 from "AC characteristics" to "timing characteristics" and removed AC
characteristics table and SCCB timing figure and table•in chapter 10, added section 10.3, spectrum response•on page iii, under key specifications, added "junction temperature" to temperature range andremoved well capacity•

on page iii, under key specifications, changed image area from "2080 µm x 1548 µm" to "2912 µm
x 2167.2 µm"•

in section 3, updated figure 3-1•

in table 8-2, added "junction temperature" to range•

in section 10, updated figure 10-1

version 1.21

04.06.2011•

in chapter 8, updated table 8-3 title to DC characteristics (-20°C < TJ < 70°C)•

in chapter 8, table 8-3 added a table footnote to standby current

version 1.3

05.13.2011•

re-wrote section 4.3, white balance; section 4.4, gamma; section 4.6, sharpness and de-noise;
section 4.7, color matrix (CMX)

proprietary to OmniVision Technologies

PRELIMINARY SPECIFICATION

version 1.3

the clear advantage™

OmniVision Technologies, Inc.
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