REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Add paragraphs 1.5, 4.4.4.1, and 4.4.4.2 for radiation hardened requirements.
Make change to Input voltage Enable (EN) maximum limit as specified underparagraph 1.3 by deleting “6.5 V” and replacing with “3.6 V”. Delete Peak output
current and Power good (PGOOD) pin sink current parameters as specified
under paragraph 1.3. Delete footnote under paragraph 1.6.
Make change to the Shutdown parameter unit symbol as specified under
Table I by deleting “µA” and replacing with “mA”. Add note to AGND terminal
description as specified under Figure 1. Add static burn-in to Table IIA.
Add subgroup 1 to Group E endpoint parameters under Table IIA. - ro

16-06-21

C. SAFFLE

B

Drawing updated to reflect current MIL-PRF-38535 requirements. -rrp

21-06-25

J. ESCHMEYERC

Make change to the conditions column for “Shutdown current”, “VTTREF source
current limit”, and “VTTREF sink current limit” tests as specified under Table I.
Make change to symbol column to “Supply current VLDOIN”, “Shutdown current
VLDOIN” tests as specified under Table I.
Make change to “Output dc voltage, VO” test as specified under Table I.
Make correction to the “Output DC voltage (VO)” limit under Table IIB.
Make changes to dimension A and Q as specified under Figure 1. - ro
Add device type 02, device class P requirements. Add case outline Y.
Delete paragraph 1.6 and move the limits to paragraph 1.3.
Add Glass transition temperature information to paragraph 1.4 - ro.

23-01-05

J. ESCHMEYER

23-12-18

J. ESCHMEYER

D

Revision Status of Sheets
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PMIC N/A
PREPARED BY

STANDARD
MICROCIRCUITDRAWINGRICK OFFICERCHECKED BYRAJESH PITHADIAAPPROVED BY

THIS DRAWING IS AVAILABLEFOR USE BY ALL DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSEAMSC N/A

DSCC FORM 2233
APR 97

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/LandandMaritime

CHARLES F. SAFFLEDRAWING APPROVAL DATE
16-04-15
REVISION LEVELDMICROCIRCUIT, LINEAR, SINK/SOURCE DDRTERMINATION VOLTAGE REGULATOR,MONOLITHIC SILICON
SIZEACAGE CODESHEET

1 OF 2767268

DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

5962-14228
5962-E420-23

1. SCOPE
1.1 Scope. This drawing documents product assurance class levels consisting of high reliability (device class Q), space
application (device class V or Y), and plastic encapsulated microcircuits (PEM) (device class N) for military, terrestrial and avionics
application and device class P for space application. A choice of case outlines and lead finishes are available and are reflected in
the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the
PIN. For device classes N and P, the user is cautioned to assure that the device is appropriate for the application environment.
1.2 PIN. The PIN is as shown in the following example:
5962

R

14228

__________ _______
FederalRHA
supplydesignator
class(see 1.2.1)\\/
Drawing number

/

01

V

X

C

_______
Devicetype(see 1.2.2)_______
Deviceclass
designator(see 1.2.3)_________
Case
outline(see 1.2.4)________
Lead
finish(see 1.2.5)

1.2.1 RHA designator. RHA marked devices classes are N, P, Q, Y, and V and meet the MIL-PRF-38535 specified RHA levels andare marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type

Generic number

Circuit function

01

TPS7H3301-SP

02

TPS7H3302-SP (QMLP)

Sink/source double data rate (DDR)
termination voltage regulator
Sink/source double data rate (DDR)
termination voltage regulator

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows:
Device class

Device requirements documentation

N or P

Certification and qualification to MIL-PRF-38535 for PEM performanceenvironments.

Q or V

Certification and qualification to MIL-PRF-38535

Y

Certification and qualification to MIL-PRF-38535. Non hermetic flip chiptechnology on a ceramic or organic substrate.

1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
XY

Descriptive designator

Terminals

See figure 1
See figure 1

Package style16
32

Flat pack
Thermally enhanced thin shrink
small outline package

1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes N, P, Q, Y, and V.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 2

1.3 Absolute maximum ratings. 1/
Input voltage: 2/
Supply voltage (VDD) /input voltage (VIN), supply voltage for low dropout
regulator (VLDOIN), remote sensing (VTTSNS), sense input (VDDQSNS) ..................... -0.36 V to 3.6 V
Enable (EN) ......................................................................................................................... -0.3 V to 3.6 V
Signal ground (PGND) to ground (AGND) ........................................................................... -0.3 V to 0.3 V
Output voltage: 2/
Output voltage (VO/VTT), reference output (VTTREF) ........................................................ -0.3 V to 3.6 V
Power good (PGOOD) ......................................................................................................... -0.3 V to 3.6 V
Maximum operating junction temperature (TJ) ......................................................................... -55°C to +150°C
Storage temperature range ...................................................................................................... -55°C to +150°C
Lead temperature (soldering, 10 seconds) for device type 01 .................................................. +300°C
Thermal characteristics:
Case X:
Thermal resistance, junction to case (bottom) θJC(BOT) .................................................. 0.6°C/W 3/ 4/
Case Y:
Junction to ambient thermal resistance (θJA) ................................................................... 25.9°C/W
Junction to case (top) thermal resistance (θJC(TOP)) ....................................................... 15.9°C/W
Junction to board thermal resistance (θJB) ....................................................................... 7.9°C/W
Junction to top characterization parameter (ΨJT) ............................................................. 0.2°C/W
Junction to board characterization parameter (ΨJB) ........................................................ 7.9°C/W
Junction to case (bottom) thermal resistance (θJC(BOT)) ................................................. 1.1°C/W
Electrostatic discharge (ESD) ratings:
Human body model (HBM) ................................................................................................... -4,000 V to +4, 000 V 5/
Charged device model (CDM) .............................................................................................. -750 V to +750 V 6/______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum
levels may degrade performance and affect reliability.
2/ Unless otherwise specified, all voltage values are with respect to AGND.
3/ For device type 01, do not allow package body temperature to exceed 265°C at any time or permanent damage may result.
4/ Maximum power dissipation may be limited by overcurrent protection.
5/ JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
6/ JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 3

1.4 Recommended operating conditions.
Input voltages :VIN / VDD ............................................................................................................................. 2.375 V to 3.5 V
VDDQSNS ........................................................................................................................... 1.0 V to 3.5 V
VLDOIN ................................................................................................................................ 0.9 V to 3.5 V
EN, VTTSNS, PGOOD ......................................................................................................... -0.1 V to 3.5 V
PGND ................................................................................................................................... -0.1 V to 0.1 V
Ouput voltages :VO/VTT ................................................................................................................................ -0.1 V to 3.5 V
VTTREF ............................................................................................................................... -0.1 V to 1.8 V
Device type 02 only:
Input current:
PGOOD ............................................................................................................................ 0 mA to 4 mA
Ouput current :VTT ................................................................................................................................... -3 A to 3 A
VTTREF ........................................................................................................................... -0.01 A to 0.01 A
Operating junction temperature (TJ) ......................................................................................... -55°C to +125°C
Ambient operating temperature range (TA) .............................................................................. -55°C to +125°C
Glass transition temperature:
Mold compound (Tg) ............................................................................................................. +115°C 7/
1.5 Radiation features.
Maximum total ionizing dose available (dose rate = 50 – 300 rads(Si)/s) . ............................... 100 krads(Si) 8/
Maximum total ionizing dose available (dose rate = 10 mrads(Si)/s) ....................................... 100 krads(Si) 8/
Device type 02 only:
Single event phenomenon (SEP):No SEL occurs at effective linear energy transfer (LET) (see 4.3) .................................... ≤ 70 MeV/(mg/cm2) 9/
No SEB observe at effective LET (see 4.3) ...................................................................... ≤ 70 MeV/(mg/cm2) 9/
No SEGR observe at effective LET (see 4.3) ................................................................... ≤ 70 MeV/(mg/cm2) 9/
Neutron/displacement irradiation damaged test ( 1 MeV equivalent) ............................... = 1 x 1013 n/cm2 10/______
7/ Glass transition temperature (Tg) of mold compound measured specification value 115°C but, tested Tg is +135°C.
8/ The manufacturer supplying device types 01 has performed characterization testing in accordance with MIL-STD-883
method 1019 paragraph 3.13.1.1 and the parts exhibited no enhanced low dose rate sensitivity (ELDRS) at a dose level of
100 krads (Si). The radiation end point limits for the noted parameters are guaranteed only for the conditions as specified
in MIL-STD-883, method 1019, condition A and condition D to a maximum total dose of 100 krads(Si). However device type 02
supplied to this drawing has been tested with total ionizing dose (TID) test at high dose rate (HDR) condition A per MIL-STD-883,
method 1019 to TID level 100 krads(Si). For more information on TID test please contact device manufacturer.
9/ The heavy-ion test performed at TAMU cyclotron radiation effects facility. Holmium (165Ho) ion beam were used at anangle of incidence of 0° at flux of 105 ions/cm2·s, fluences level of 107 ions/cm2 and a temperature of 125°C and no single

event latch-up (SEL) was observed at effective LET of 75 MeV/(mg/cm2). Manufacturer also test Single event burnout (SEB)and Single event gate rupture (SEGR) test with (165Ho) ion beam were used at angles of incidence of 0°. No SEB/SEGR

observed up to effective LET of 75 MeV/(mg/cm2). For more information on SEE/SEP test please contact device manufacturer.

10/ Neutron Displacement damaged dosimetry test was performed in Fast Neutron Irradiation (FNI) facility of The University of
Massachusetts Lowell. The results show that all devices were fully functional and within production test limits after having been
irradiated up to 1 x 1013 n/cm2 (1-MeV equivalent). A sample size of nine units was exposed to radiation testing per
MIL-STD-883, Method 1017 for Neutron Irradiation, and an additional one device was used as a control unit and was not
irradiated.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 4

2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part ofthis drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in thesolicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATIONMIL-PRF-38535 -Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDSMIL-STD-883
MIL-STD-1835-

Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKSMIL-HDBK-103
MIL-HDBK-780-

List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.

(Copies of these documents are available online at https://quicksearch.dla.mil/.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
ASTM INTERNATIONAL (ASTM)
ASTM F1192– Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of Semiconductor Devices.

(Copies of this document is available online at https://www.astm.org/.)
JEDEC Solid State Technology Association
JEDEC JESD57 – Test Procedures for the Measurement of Single-Event Effects in Semiconductor Devices from
Heavy Ion Radiation.
JEDEC JEP 155 - Recommended ESD Target Levels for HBM/MM Qualification
JEDEC JEP 157 - Recommended ESD-CDM Target Levels(Copies of these documents are available online at https:/www.jedec.org.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specificexemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes N, P, Q, Y, and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The modificationin the QM plan shall not affect the form, fit, or function as described herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions for device classes N, P, Q,
Y, and V shall be as specified in MIL-PRF-38535 and herein.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 5

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electricalperformance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full ambient
operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electricaltests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked.
For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the optionof not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for
device classes N, P, Q, Y, and V shall be in accordance with MIL-PRF-38535.
Marking for case outline Y :If any additional information is needed, contact the manufacturer.
\T/ YMLLLLSG4\T/

TI LogoR1422802PY

YM

Year month date code

O Q MLA NNNN

LLLL

Assembly lot code

O – PIN 1

S

Assembly site code per QSS 005-120

TAI

Country

Q

QML

MLA

Country

NNNN

Serial number, 4 digit

MAXIMUM CHARACTERS:
8 CHARACTERS – 1ST LINE
10 CHARACTERS – 2ND LINE
#Symbol

device name:

R1422802PY#Symbol

ECAT: G4 must be symbolized with a solid line underscore

3.5.1 Certification/compliance mark. The certification mark for device classes N, P, Q, Y, and V shall be a "QML" or "Q" asrequired in MIL-PRF-38535.
3.6 Certificate of compliance. A certificate of compliance shall be required from a QML-38535 listed manufacturer in order tosupply to the requirements of this drawing (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA
prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets the requirements of
MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535 shall be provided with each lot of
microcircuits delivered to this drawing.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 6

TABLE IA. Electrical performance characteristics.
Test

SymbolConditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

Devicetype

L imits
Min

Unit

Max

Supply current.
Supply / quiescent current

IVDD/VIN

EN = 3.3 V, no load

1,2,301, 0230

mA

Shutdown current

IVDD(SDN)

EN = 0 V, VDDQSNS = 0 V,
no load

1,2,3

01

5

mA

8

EN = 0 V, VDDQSNS > 0.78 V,
no loadIVDD(SHDN)

EN = 0 V, VDDQSNS = 0 V,
no load02

3
6

EN = 0 V, VDDQSNS > 0.78 V,
no loadSupply / quiescent current
of VLDOINIVLDOIN

EN = 3.3 V, no load

1,2,3

01

1200

µA

Shutdown current of

IVLDOIN(SDN)

EN = 0 V, no load

1,2,3

01

100

µA

VLDOINIVLDOIN(SHDN) EN = 0 V, no load

02

1

VDDQSNS input current

IVDDQSNSEN = 3.3 V

1,2,301, 02

6µA

VVTTSNSVLDOIN = 2.5 V,
VVTTREF = 1.25 V (DDR1),
IVTT/VO = 0 A

1,2,3

01

1.244

1.256

V

VLDOIN = 1.8 V,
VVTTREF = 0.9 V (DDR2),
IVTT/VO = 0 A

0.894

0.906

VLDOIN = 1.5 V,
VVTTREF = 0.75 V (DDR3),
IVTT/VO = 0 A

0.744

0.756

VLDOIN = 1.35 V,
VVTTREF = 0.675 V (DDR3L),
IVTT/VO = 0 A

0.669

0.681

VLDOIN = 1.20 V,
VVTTREF = 0.60 V (DDR4),
IVTT/VO = 0 A

0.594

0.606

VO / VTT output.
Output dc voltage,
VTT/VOSee footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 7

TABLE IA. Electrical performance characteristics - Continued.
Test

SymbolConditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

Devicetype

L imits
Min

Max

1.24

1.26

VDDQSNS = VLDOIN = 1.8 V(DDR2), IVTT = 5 mA

0.89

0.91

VDDQSNS = VLDOIN = 1.5 V(DDR3), IVTT = 5 mA

0.745

0.759

VDDQSNS = VLDOIN = 1.35 V(DDR3L), IVTT = 5 mA

0.67

0.684

VDDQSNS = VLDOIN = 1.2 V(DDR4), IVTT = 5 mA

0.596

0.608

VDDQSNS = VLDOIN = 2.5 V(DDR1), IVTT = -5 mA

1.25

1.27

VDDQSNS = VLDOIN = 1.8 V(DDR2), IVTT = -5 mA

0.9

0.92

VDDQSNS = VLDOIN = 1.5 V(DDR3), IVTT = -5 mA

0.752

0.768

VDDQSNS = VLDOIN = 1.35 V(DDR3L), IVTT = -5 mA

0.675

0.692

VDDQSNS = VLDOIN = 1.2 V(DDR4), IVTT = -5 mA

0.602

0.618

VDDQSNS = VLDOIN = 2.5 V(DDR1), –1 A ≤ IVTT ≤ 1 A

1.24

1.28

VDDQSNS = VLDOIN = 1.8 V(DDR2), –1 A ≤ IVTT ≤ 1 A

0.885

0.93

VDDQSNS = VLDOIN = 1.5 V(DDR3), –1 A ≤ IVTT ≤ 1 A

0.735

0.78

VDDQSNS = VLDOIN = 1.35 V(DDR3L), –1 A ≤ IVTT ≤ 1 A

0.66

0.72

VDDQSNS = VLDOIN = 1.2 V(DDR4), –1 A ≤ IVTT ≤ 1 A

0.585

0.63

Unit

VO / VTT output – continued.
Output dc voltage,

VVTTSNS

VTT/VO

1,2,3

VDDQSNS = VLDOIN = 2.5 V(DDR1), IVTT = 5 mA

02

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 8mVTABLE IA. Electrical performance characteristics - Continued.
Test

SymbolConditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

Devicetype

L imits
Min

Unit

Max

VO / VTT output – continued .
VLODIN - VTT/VO 5/

VLODIN

VIN/VDD = 2.95 V, IO = 0.5 A,> VTT/VOVVDDQSNS = 2.50 V,

1,2,3

01

230

VTT = VVTTREF – 50 mV (DDR1)300

VIN/VDD = 2.95 V, IO = 1 A,
VVDDQSNS = 2.50 V,
VTT = VVTTREF – 50 mV (DDR1)
VIN/VDD = 2.95 V, IO = 2.0 A,

400

4/

VVDDQSNS = 2.50 V,
VTT = VVTTREF – 50 mV (DDR1)
230

VIN/VDD = 2.375 V, IO = 0.5 A, 4/
VVDDQSNS = 1.80 V,
VTT = VVTTREF – 50 mV (DDR2)300

VIN/VDD = 2.375 V, IO = 1 A, 4/
VVDDQSNS = 1.80 V,
VTT = VVTTREF – 50 mV (DDR2)

400

VIN/VDD = 2.375 V, IO = 2.0 A, 4/
VVDDQSNS = 1.80 V,
VTT = VVTTREF – 50 mV (DDR2)

230

VIN/VDD = 2.375 V, IO = 0.5 A,
VVDDQSNS = 1.50 V,
VTT = VVTTREF – 50 mV (DDR3)300

VIN/VDD = 2.375 V, IO = 1 A,
VVDDQSNS = 1.50 V,
VTT = VVTTREF – 50 mV (DDR3)400

VIN/VDD = 2.375 V, IO = 2.0 A, 4/
VVDDQSNS = 1.50 V,
VTT = VVTTREF – 50 mV (DDR3)
See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 9mV

TABLE IA. Electrical performance characteristics - Continued.
Test

SymbolConditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit

Max

VO / VTT output – cont inued.
VLODIN > VTT/VO 5/

VLODIN

VIN/VDD = 2.375 V, IO = 0.5 A,> VTT/VOVVDDQSNS = 1.35 V,

1,2,3

01

230

mV

VTT = VVTTREF – 50 mV (DDR3L)
300

VIN/VDD = 2.375 V, IO = 1 A,
VVDDQSNS = 1.35 V,
VTT = VVTTREF – 50 mV (DDR3L)

400

VIN/VDD = 2.375 V, IO = 2.0 A, 4/
VVDDQSNS = 1.35 V,
VTT = VVTTREF – 50 mV (DDR3L)

230

VIN/VDD = 2.375 V, IO = 0.5 A,
VVDDQSNS = 1.20 V,
VTT = VVTTREF – 50 mV (DDR4)300

VIN/VDD = 2.375 V, IO = 1 A,
VVDDQSNS = 1.20 V,
VTT = VVTTREF – 50 mV (DDR4)400

VIN/VDD = 2.375 V, IO = 2.0 A, 4/
VVDDQSNS = 1.20 V,
VTT = VVTTREF – 50 mV (DDR4)
Output voltage
tolerance to

VVOTOL/VTTTOLIVO = -3 A, 4/

1,2,3

01

34

-12

-34

mV

across VDD / VIN voltage range
IVO = 3 A, 4/

VTTREF12

across VDD / VIN voltage range
VO/VTT source
current
limit

IVOSRCL

VO/VTT sink current
limit

IVOSNCL

Discharge impedance

RDSCHRG

With reference to VVTTREF,

1,2,3

01

3.25

8

A

1,2,3

01

3.5

5.5

A

1

01

25

Ω

VVTTSNS = 90% x VVTTREF
With reference to VVTTREF,
VVTTSNS = 110% x VVTTREF
VDDQSNS = 0 V, VVO= 0.3 V,
VEN = 0 V, TA = +25C

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 10

TABLE IA. Electrical performance characteristics - Continued.
Test

SymbolConditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit

Max

VO / VTT output – cont inued.
Dropout voltage,
VDO = VLDOIN –VTTREF

VDO

VDO recorded when
VTT –VTTREF = 50 mVVDDQSNS = 2.5 V (DDR1),
IVTT = 0.5 A
VDDQSNS = 2.5 V (DDR1),

1,2,3

02

60
180

IVTT = 1 A
VDDQSNS = 2.5 V (DDR1),

465

IVTT = 2 A
VDDQSNS = 1.8 V (DDR2),

70

IVTT = 0.5 A
VDDQSNS = 1.8 V (DDR2),

200

IVTT = 1 A
VDDQSNS = 1.8 V (DDR2),

475

IVTT = 2 A
VDDQSNS = 1.5 V (DDR3),

65

IVTT = 0.5 A
VDDQSNS = 1.5 V (DDR3),

180

IVTT = 1 mA
VDDQSNS = 1.5 V (DDR3),

420

IVTT = 2 A
VDDQSNS = 1.35 V (DDR3L),

60

IVTT = 0.5 A
VDDQSNS = 1.35 V (DDR3L),

180

IVTT = 1 A
VDDQSNS = 1.35 V (DDR3L),

420

IVTT = 2 A
VDDQSNS = 1.2 V (DDR4),60

IVTT = 0.5 A
VDDQSNS = 1.2 V (DDR4),180

IVTT = 1 A
VDDQSNS = 1.2 V (DDR4),

420

IVTT = 2 A
See footnotes at end of table.

STANDARD
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REVISION LEVELDSHEET 11mV

TABLE IA. Electrical performance characteristics - Continued.
Test

SymbolVO / VTT output – continued.
VTT tolerance to
VTTTOLVTTREF(VTT – VTTREF)
VTT sourcing
current limit

ILIM_SRC_VTTVTT sinking current
limit

ILIM_SNK_VTT

VTT discharge
resistance

RDSCHRG

Conditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

1,2,3

IVTT = -3 A

Devicetype

02

IVTT = 3 A

Limits

Unit

Min

Max

1

30

-30

-1

mV

Ramp output 0 A to 10 A, record
current when VTT reaches lowest
value
Ramp output 0 A to -10 A, record
current when VTT reaches highest
value
VDDQSNS = 0 V, VTT = 0.3 V,
EN = 0 V

1,2,3

02

5

9

A

1,2,3

02

5

10

A

1,2,3

02

25

Ω

PGOOD window lower thresholdwith respect to VVTTREF

1,2,3

01

-23.5

-17.5

%

17.5

23.5

POWER-GOOD comparator.
VO/VTT PGOOD
threshold

VTH(PG)VTT PGOOD
threshold withrespect to VTTREF

VPG(LOW, Falling)

VTT PGOOD
threshold withrespect to VTTREF

VPG(HI, Falling)

PGOOD window upper thresholdwith respect to VVTTREFPGOOD window low falling
threshold

1,2,3

02

-21%

-18%

PGOOD window low risingthreshold

1,2,3

02

-17%

-13%

PGOOD window high falling
threshold

1,2,3

02

13%

17%

VPG
(HI, Rising)PGOOD window high risingthreshold

1,2,3

02

18%

21%

Output low voltage

VPGOODLOW

ISINK = 4 mA

1,2,3

01

0.4

V

Power good output
low

VPG(OL)IPGOOD(SINK) = 4 mA

1,2,3

02

0.4

V

Leakage current

IPGOODLKVTTSNS = VREFIN (PGOOD highimpedance),

1,2,3

01

1

µA

1,2,3

02

1

μA

Power goodleakage

VPG(LOW, Rising)

IPG(LKG)PGOOD = VIN + 0.2 V
VTTSNS = VTTREF (PGOOD highimpedance),
PGOOD = VDD + 0.2 V

See footnotes at end of table.

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REVISION LEVELDSHEET 12

TABLE IA. Electrical performance characteristics - Continued.
Test

SymbolConditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

Devicetype

Limits

Unit

Min

Max

1.0

2.8

V

VDDQSNS and VVTTREF output.
VDDQSNS voltage
range

VDDQSNS_UVLO

VDDQSNS UVLO
turn-on threshold

VDDQSNSUVLO

VDDQSNS UVLO
hysteresis

VDDQSNSUVLO(HYST)VTTREF voltage
tolerance to

VVTTREFVDDQSNSVTTREF voltage
tolerance to

VVTTREFVDDQSNS

1,2,3

01

1,2,3

02

900

mV

1,2,3

02

150

mV

1,2,3

01

-15

15

mV

-10 mA < IVTTREF < 10 mA,
VDDQSNS = 1.8 V

-15

15

-10 mA < IVTTREF < 10 mA,
VDDQSNS = 1.5 V

-15

15

-10 mA < IVTTREF < 10 mA,
VDDQSNS = 1.35 V

-15

15

-10 mA < IVTTREF < 10 mA,
VDDQSNS = 1.2 V

-15

15

49%

51%

-10 mA < IVTTREF < 10 mA,
VDDQSNS = 1.8 V

49%

51%

-10 mA < IVTTREF < 10 mA,
VDDQSNS = 1.5 V

49%

51.25%-10 mA < IVTTREF < 10 mA,
VDDQSNS = 1.35 V

49%

51.5%

-10 mA < IVTTREF < 10 mA,
VDDQSNS = 1.2 V

49%

51.5%

-3 mA < IVTTREF < 3 mA,
VDDQSNS = 1.5 V

49%

51%

-3 mA < IVTTREF < 3 mA,
VDDQSNS = 1.35 V

49%

51%

-3 mA < IVTTREF < 3 mA,
VDDQSNS = 1.2 V

49%

51%

VDDQSNS rising-10 mA < IVTTREF < 10 mA,
VDDQSNS = 2.5 V-10 mA < IVTTREF < 10 mA,
VDDQSNS = 2.5 V

1,2,3

02

mV

See footnotes at end of table.

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REVISION LEVELDSHEET 13

TABLE IA. Electrical performance characteristics - Continued.
Test

SymbolConditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit

Max

VDDQSNS and VVTTREF output – continued.
VTTREF source
current limit

IVTTREFSRCLVTTREF = 0 V

1,2,3

01

10

mA

VTTREF sinkcurrent
limit

IVTTREFSRCCLVTTREF = 0 V

1,2,3

01

6

mA

VTTREF sourcing
current limit

ILIM_SRC_VTTREF

Sourcing current ramped from0 to 55 mA.
Find when VTTREF drops tohalf its original value

1,2,3

02

35

mA

VTTREF sinking
current limit

ILIM_SINK_VTTREF

Sinking current ramped from 0
to 16.5 mA.
Find when VTTREF hits peak
value

1,2,3

02

12

mA

See footnotes at end of table.

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REVISION LEVELDSHEET 14

TABLE IA. Electrical performance characteristics - Continued.
Test

SymbolConditions 1/ 2/ 3/-55°C ≤ TA ≤ +125°C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit

Max

UVLO/EN logic threshold.
UVLO threshold

VVINUVVINVDD UVLO turn-on
threshold

VDDUVLO

High level input voltage

VENIH

Enable high-level input
voltage (turn-on)

VIH_ENLow level input voltage

VENIL

Enable low-level input
voltage (turn-off)

VIL_EN

Logic input leakage
current

IENLEAK

Enable input leakage
current

IEN(LKG)

1/

1

01

2.25

V

1,2,3

02

2.3

V

1,2,3

01

1,2,3

02

1.7

V

1,2,3

01

0.3

V

1,2,3

02

0.3

1

01

-1

1

µA

1,2,3

02

-1

1

µA

Wake up, TA = +25°C

EnableEnableEnable, TA = +25°C

1.7

V

V

Unless otherwise specified;
Device type 01. VDD/VIN = 3.3 V and 2.375 V, VLDOIN = 1.8 V, VDDQSNS = 1.8 V, VOSNS/VTTSNS = 0.9 V, EN = VDD/VIN.
Device type 02. 2.375 V ≤ VDD ≤ 3.5 V, VLDOIN = 1.8 V, VDDQSNS = 1.8 V, VTTSNS = 0.9 V, EN = VDD/VIN.

2/

The manufacturer supplying device types 01 has performed characterization testing in accordance with MIL-STD-883
method 1019 paragraph 3.13.1.1 and the parts exhibited no enhanced low dose rate sensitivity (ELDRS) at a dose level of
100 krads (Si). The radiation end point limits for the noted parameters are guaranteed only for the conditions as specified
in MIL-STD-883, method 1019, condition A and condition D to a maximum total dose of 100 krads(Si). However device type 02
supplied to this drawing has been tested with total ionizing dose (TID) test at high dose rate (HDR) condition A per MIL-STD-883,
method 1019 to TID level 100 krads(Si). For more information on TID test please contact device manufacturer.

3/

The manufacturer supplying RHA device types 01 and 02 has performed characterization testing in accordance with
MIL-STD-883 method 1019 paragraph 3.13.1.1 and the parts exhibited no enhanced low dose rate sensitivity (ELDRS) at adose level of 100 krads (Si).

4/The parameter is guaranteed to the limits specified by characterization but, not production tested.

5/

Dropout and headroom information provided to help designer in optimizing system efficiency.

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REVISION LEVELDSHEET 15

TABLE IB. SEP test limits. 1/ 2/ 3/ 4/
Devicetype

SEP/SEE

Temperature
(TA)

VIN

Effective Linear energy transfer
(LET)

02

No SEL

125°C

3.5 V

LET ≤ 70 MeV/(mg/cm2)

No SEB/SEGR

25°C

3.5 V

LET ≤ 70 MeV/(mg/cm2)

1/ For single event phenomena (SEP) test conditions, see 4.3 herein.
2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end of line
testing. Test plan must be approved by the technical review board and qualifying activity.
3/ The heavy-ion test performed at TAMU cyclotron radiation effects facility. Holmium (165Ho) ion beam were used at

an angle of incidence of 0° at flux of 105 ions/cm2·s, fluences level of 107 ions/cm2 and a temperature of 125°C andno single event latch-up (SEL) was observed at effective LET of 75 MeV/(mg/cm2). Manufacturer also test Single

event burnout (SEB) and Single event gate rupture (SEGR) test with (165Ho) ion beam were used at angles ofincidence of 0°. No SEB/SEGR observed up to effective LET of 75 MeV/(mg/cm2). For more information on
SEE/SEP test please contact device manufacturer.

4/ For SEL test temperature TA = +125°C ±10°C.

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REVISION LEVELDSHEET 16Case outline X

FIGURE 1. Case outline.

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REVISION LEVELDSHEET 17Case outline X – continued.

SymbolMillimeters

Inches

Min

Max

Min

Max

A

1.850

2.416

.073

.095

b

0.382

0.482

0.015

0.019

c

0.097

0.177

0.004

0.007

D

10.76011.260

0.424

0.443

D1

8.550

9.050

0.337

0.356

E

24.64225.142

0.970

0.990

E1

9.380

9.880

0.369

0.389

E2

6.340

6.840

0.250

0.269

e

1.190

1.350

0.047

0.053

Q

0.84

1.04

0.033

0.041

S1

0.844 REF

0.033 REFNOTES:
1. Controlling dimensions are millimeter, inch dimensions are given
for reference only.
2.

This package is hermetically sealed with a metal lid. Lid andheat sink are connected to pin 8 (GND).

3.

The leads are gold plated.

4.

Bottom side has a thermal pad.

FIGURE 1. Case outline - continued.

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REVISION LEVELDSHEET 18

Case YFIGURE 1. Case outline - continued.

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REVISION LEVELDSHEET 19

Case Y – continued.

SymbolDimensions
InchesMillimeters

Minimum

Maximum

Minimum

Maximum

A

---

.047

---

1.2

A1

.002

.006

0.05

0.15

b

.007

.012

0.19

0.30

c
D

.006 TYP
.429

D1
D2

0.15 TYP

.437

10.9

.384 BSC.124

11.1
9.75 BSC

.160

3.16

4.06

D3

.006 REF

0.15 REF

e.026 BSC

0.65 BSC

E

.311

.327

7.9

8.3

E1

.236

.244

6.0

6.2

E2

.129

.162

3.29

4.11

E3
L

.035 REF.020

0.9 REF

.029

0.50

0.75

NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2.

This drawing is subject to change without notice.

3.

This dimension does not include mold flash, protrusions, or gate burrs.
Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

4.

Reference JEDEC registration MO-153.

5.

Features may differ and may not be present.
FIGURE 1. Case outline - continued.

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REVISION LEVELDSHEET 20

Device type

01

Case outline

X

Terminal
numberTerminal
symbolInput / Output

1

VTTREF

O

Reference output. Connect to GND through0.1 µF ceramic capacitor.

2

VDDQSNSIVDDQ sense input. Reference input for VTTREF.

3

VLDOINI

4

VLDOINI

5

VLDOIN

I

6

PGND

---

Power ground. Connect output for the VTT / VO
low dropout voltage regulator to negative pin of theoutput capacitor.

7

PGND

---

Power ground. Connect output for the VTT / VO
low dropout voltage regulator to negative pin of theoutput capacitor.

8

PGND

---

9

EN

I

10

VDD / VIN

I

11

PGOOD

O

12

VTT / VOO

13

VTT / VOO

14

VTT / VO

O

15

AGND

---

16

VTTSNSI

Description

Supply voltage for the low dropout (LDO) voltage
regulator. Connect to VDDQ voltage or analternate voltage source.
Supply voltage for the low dropout (LDO) voltage
regulator. Connect to VDDQ voltage or analternate voltage source.
Supply voltage for the low dropout (LDO) voltage
regulator. Connect to VDDQ voltage or analternate voltage source.

Power ground. Connect output for the VTT / VO
low dropout voltage regulator to negative pin of theoutput capacitor.
Enable pin. Driving this pin to logic high enables
the device; driving this pin to logic low disables thedevice.
2.5 V or 3.3 V power supply. A ceramic
decoupling capacitor with a value between 1 µF
and 10 µF is required.
PGOOD output pin. PGOOD pin is an open drain
output to indicate the output voltage is within
specification.
Power output for VTT low drop out voltage
regulator.
Power output for VTT low drop out voltage
regulator.
Power output for VTT low drop out voltage
regulator.
Signal ground. Connect to negative pin of output
capacitors. See note.
VDDQ sense input, reference input for VTTREF.
Voltage sense for VTT/VO. Connect to positive
pin of the output capacitor or the load.

NOTE: Thermal pad and package lid are internally connected to ground.
FIGURE 2. Terminal connections.

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REVISION LEVELDSHEET 21

Device type02

Case outline

Y

Terminal
numberTerminal
symbolInput / Output 1/

1

NC 3/

---

No connection.

2

NC 3/

---

No connection.

3

NC 3/

---

No connection.

4

VTTREF

O

Reference output. Connect to GND through0.1 µF ceramic capacitor.

5

VDDQSNSIVDDQ sense input. Reference input for VTTREF. 2/

6

NC

---

No connection.

7

VLDOINI

8

VLDOIN

I

9

PGND

---

Power ground. Connect output for the VTT / VO low
dropout voltage regulator to negative pin of the output
capacitor.

10

PGND

---

Power ground. Connect output for the VTT / VO low
dropout voltage regulator to negative pin of the output
capacitor.

11

PGND

---

Power ground. Connect output for the VTT / VO low
dropout voltage regulator to negative pin of the output
capacitor.

12

NC 3/

---

No connection.

13

NC 3/

---

No connection.

14

NC 3/

---

No connection.

15

NC 3/

---

No connection.

16

NC 3/

---

No connection.

Description

Supply voltage for the low dropout (LDO) voltage
regulator. Connect to VDDQ voltage or an alternate
voltage source.
Supply voltage for the low dropout (LDO) voltage
regulator. Connect to VDDQ voltage or an alternate
voltage source.

FIGURE 2. Terminal connections - continued.

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REVISION LEVELDSHEET 22

Device type02

Case outline

Y

Terminal
numberTerminal
symbolInput / Output 1/

17

NC 3/

---

No connection.

18

NC 3/

---

No connection.

19

NC 3/

---

No connection.

20

EN

I

21

VDD

I

22

PGOOD

O

23

VTT

O

24

VTT

O

25

VTT

O

26

VTT

O

27

NC

---

28

AGND

---

29

VTTSNS

I

30

NC 3/

---

No connection.

31

NC 3/

---

No connection.

32

NC 3/

---

No connection.

Description

Enable pin. Driving this pin to logic high enables
the device; driving this pin to logic low disables thedevice.
2.5 V or 3.3 V power supply. A ceramic
decoupling capacitor with a value between 1 µF
and 10 µF is required.
PGOOD output pin. PGOOD pin is an open drain
output to indicate the output voltage is within
specification.
Power output for VTT low drop out voltage
regulator.
Power output for VTT low drop out voltage
regulator.
Power output for VTT low drop out voltage
regulator.
Power output for VTT low drop out voltage
regulator.
No connection.
Signal ground. Connect to negative pin of output
capacitors. See note.
VDDQ sense input, reference input for VTTREF.
Voltage sense for VTT/VO. Connect to positive
pin of the output capacitor or the load.

1/ I = Input, O = Output, ─ = Other
2/ VDDQSNS shall be connected to the regulated voltage supplying VDDQ. If the VDDQ supply is also used for
VLDOIN, an RC filter is recommended to isolate transients from VLDOIN to VDDQ.
3/ No connect. These pins are not internally connected. It is recommended to connect these pins to ground toprevent charge buildup; however, these pins can also be left open or tied to any voltage between ground and VDD.
FIGURE 2. Terminal connections - continued.

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REVISION LEVELDSHEET 23

4. VERIFICATION
4.1 Sampling and inspection. For device classes N, P, Q, Y, and V, sampling and inspection procedures shall be in accordancewith MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes N, P, Q, Y, and V, screening shall be in accordance with MIL-PRF-38535 and shall be
conducted on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes N, P, Q Y, and V.
a.

Test condition A, B, C and D. Burn-in test shall be performed in accordance with method 1015 of MIL-STD-883. Burn-in test
duration, test condition and test temperature, or approved alternatives shall be specified in the device manufacturer's QM
plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level controlof the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be madeavailable to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, andpower dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883.

b.

Unless otherwise specified in the QM plan, for devices class N, P, Q, Y, and V, dynamic burn-in shall be performed with test
condition D, method 1015 of MIL-STD-883.

c.

For devices class P, Y, and V, interim and post burn-in final electrical test delta parameters shall be specified in delta burn-intable IIB herein.

4.3 Qualification inspection. Qualification inspection for device classes N, P, Q, Y, and V shall be in accordance with
MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E
inspections (see 4.4.1 through 4.4.5).
4.4 Conformance inspection. Technology conformance inspection for classes N, P, Q, Y, and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified.
4.4.1 Group A inspection.
a.

Tests shall be as specified in table IIA herein.

b.

Subgroups 4, 5, 6, 7, 8, 9, 10, and 11 in table I, method 5005 of MIL-STD-883 shall be omitted.

4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be
as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained underdocument revision level control by the device manufacturer's TRB, in accordance with MIL-PRF-38535, and shall be made available
to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as
applicable, in accordance with the intent specified in method 1005 of MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
Preconditioning shall be performed on non hermetic device classes N, P, and Y surface mount devices as specified in the
manufacturer’s QM plan. Thermal shock is not applicable to class N, P, and organic class Y.

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REVISION LEVELDSHEET 24TABLE IIA. Electrical test requirements.
Test requirements

Subgroups(in accordance with
MIL-PRF-38535, tableIII)
Deviceclass N

Deviceclass P

Deviceclass Q

Deviceclass V

Deviceclass YInterim (pre burn-in) electricalparameters, (see 4.2)

1,2,3

1,2,3

1,2,3

1,2,3

1,2,3

Post burn-in electricalparameters (see 4.2.1)

1,2,3 1/

1,2,3 1/ 2/

1,2,3, 1/

1,2,3 1/ 2/

1,2,3 1/

Group A (Final electrical) test
requirements (see 4.4.1)

1,2,3

1,2,3

1,2,3

1,2,3

1,2,3

Group C end-point electricalparameters (see 4.4.2)

1,2,3

1,2,3

1,2,3

1,2,3

Group D end-point electricalparameters (see 4.4.3)

1

1

1

1

1

Group E end-point electricalparameters (see 4.4.4)

1

1

1

1

1

2/

2/

1,2,3

1/

PDA applies to subgroup 1.

2/

Delta limits as specified in table IIB shall be required where specified, and the delta limits shall be completed withreference to the previous endpoint electrical parameters.

TABLE IIB. Burn-in and operating life test delta parameters. TA = +25°C. 1/
Parameters

SymbolConditions

Supply / quiescentcurrent
Shutdown current

Device type

Limit

Unit

IVIN/IVDD

VEN = 3.3 V, no load

01, 02±1mA

IVDD(SDN)

VEN = 0 V, no load,

01, 02

±0.24

mA

±60

µA

±8.5

µA

±1

mV

02

±1

mV

02

±1

mV

VDDQSNS > 0.78 V
Supply / quiescentcurrent of VLDOIN
Shutdown current
of VLDOIN
Output DC
voltage, VO

IVLDOIN

VEN = 3.3 V, no load

ILDOIN(SDN)

VEN = 0 V, no load,
VDDQSNS > 0.78 V

VVOSNS/VTTSNS

Output DC voltage, VTT

VTTSNS

Output DC voltage, VTT

VTTSNS01, 02
01
01

VLDOIN = 1.8 V, IO = 0 A,
VVTTREF = 0.9 V (DDR2)
IVTT = 5 mA
IVTT = - 5 mA

1/ These parameters shall be recorded before and after the required burn-in and life test to determine delta limits.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 25

4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see
3.5 herein).
a.

RHA levels for device classes N, P, Q, Y, and V, shall be as specified in MIL-PRF-38535 and the end-point electricalparameters subgroups shall be as specified in table IIA herein.

b. For device classes N, P, Q, Y, and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point
electrical parameter limits as defined in table IA at TA = +25°C ±5°C, after exposure, to the subgroups specified intable IIA herein.
4.4.4.1 Total irradiation dose testing. Total irradiation dose testing shall be performed in accordance with MIL-STD-883,
method 1019, condition A and condition D for device type 01 and condition A for device type 02 as specified herein.
4.4.4.2 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level greaterthan 5 krads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table I herein and shall be thepre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after any
design or process changes which may affect the RHA response of the device.
4.3 Single event phenomena (SEP). SEP testing was performed on two units per the conditions in table IB.
The recommended test conditions for SEP are as follows:a.

The ion beam angle of incidence shall be between normal to the die surface and 60˚ to the normal, inclusive(i.e., 0°≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.

b.

The fluence shall be ≥ 100 errors or ≥ 107 ions/cm2.

c.

The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring
the cross-section at two flux rates which differ by at least an order of magnitude.

d.

The particle range shall be ≥ 20 micron in silicon.

e.

The test temperature shall be +125°C ± 10% for SEL.

f.

For SEP test limits, see table IB herein.

5. PACKAGING
5.1 Packaging requirements. The requirements for packaging for device classes N, P, Q, Y, and V shall be in accordance with
MIL-PRF-38535.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original
equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor preparedspecification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for theindividual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal, or emailcommunication.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 26

6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and thislist will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices(FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or
telephone (614) 692-0591.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply. Sources of supply for device classes N, P, Q, Y, and V are listed in MIL-HDBK-103 and QML-38535.
The vendors listed in MIL-HDBK-103 and QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land andMaritime-VA and have agreed to this drawing.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

DSCC FORM 2234
APR 97

SIZE

5962-14228

A

REVISION LEVELDSHEET 27

STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 23-12-18
Approved sources of supply for SMD 5962-14228 are listed below for immediate acquisition information only andshall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will berevised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and acertificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Standard
microcircuit drawing
PIN 1/

VendorCAGE
numberVendorsimilar
PIN 2/

5962-1422801VXC

01295

TPS7H3301-SP

5962R1422801VXC

01295

TPS7H3301-RHA

5962R1422802PYE

01295

TPS7H3302-QMLP

1/ The lead finish shown for each PIN is the most readily
available from the manufacturer listed for that part.
If the desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may notsatisfy the performance requirements of this drawing.

Vendor CAGE
number01295

Vendor nameand address
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

The information contained herein is disseminated for convenience only and theGovernment assumes no liability whatsoever for any inaccuracies in theinformation bulletin.