THAN0195_Rev.1.30_E

Application Note

THAN0195_Rev.1.30_E

THCV235(-Q)/THCV236(-Q) Application Note
System Diagram, Register Setting and PCB Design Guideline

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Contents
Contents.................................................................................................................................................................. 2
Selection table for typical application 1 ............................................................................................................... 4
Selection table for typical application 2 ............................................................................................................... 5
Application Diagram ............................................................................................................................................. 6
Main-Link .............................................................................................................................................................. 6
RGB24bit per pixel over 20MHz falling edge system ...................................................................................................... 6
35bit (RGB30bit and arbitrary 5bit) per pixel over 20MHz rising edge system ........................................................... 7
YCbCr16bit per pixel over 100MHz falling edge system ................................................................................................ 8
RGB30bit per pixel over 100MHz falling edge system .................................................................................................... 9

Main-Link & Sub-Link ....................................................................................................................................... 10
2-wire serial I/F (THCV235(-Q): Sub-Link Slave side, THCV236(-Q): Sub-Link Master side) ................................ 10
2-wire serial I/F (THCV235(-Q): Sub-Link Master side, THCV236(-Q): Sub-Link Slave side) ................................ 11
Low Speed Data Bridge (THCV235(-Q): Slave side, THCV236(-Q): Master side) .................................................... 12

Signaling Usage .................................................................................................................................................... 13
Example Connection 1: Sharing LOCKN ...................................................................................................................... 13
Example Connection 2: Sharing Power Supply ............................................................................................................. 13

Sub-Link Communication .................................................................................................................................. 14
Sub-Link Notification ...................................................................................................................................................... 14
Example Operation 1-1: Access to Sub-Link Master Device Register ......................................................................... 15
Example Operation 1-2: Access to Sub-Link Slave Device Register ............................................................................ 17
Example Operation 1-3: Access to 2-wire serial Slave Device with 8bit Register Address ......................................... 20
Example Operation 1-4: Access to 2-wire serial Slave Device with 16bit Register Address ....................................... 22
Example Operation 2-1: Programmable GPIO output control .................................................................................... 24
Example Operation 2-2: Programmable GPIO input control ...................................................................................... 25
Example Operation 2-3: Through GPIO Sub-Link Master to Sub-Link Slave .......................................................... 26
Example Operation 3-1: Interrupt feedback as internal factor.................................................................................... 27
Example Operation 3-2: Interrupt output as external factor by Slave side ................................................................ 28
Example Operation 4: UART Communication by Low Speed Data Bridge................................................................ 29
Example Operation 5: Sub-Link communication to THCV233 or THCV234 ............................................................ 30

Power Supply Usage ............................................................................................................................................ 31
Power Supply for THCV235(-Q) / THCV236(-Q) ......................................................................................................... 31
PCB layout guideline between VDD (41Pin) and AVDD (40Pin) for THCV236(-Q)................................................... 32

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Note ....................................................................................................................................................................... 33
1)Power On Sequence .............................................................................................................................................. 33

2)

Cable Connection and Disconnection ................................................................................................................. 33

3)

GND Connection................................................................................................................................................... 33

4)

Low Input Pulse into PDN1 and PDN0 Period Requirement ........................................................................... 33

5)Multiple device connection .................................................................................................................................. 34

PCB Layout Considerations ............................................................................................................................... 35
Notices and Requests ........................................................................................................................................... 36

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Selection table for typical application 1
Only Main-Link is Active

Main-Link Operation
THCV235(-Q)
V-by-OneⓇ HS Mode

V-by-OneⓇ HS Mode

24bit
@100MHzLVCMOS/RGB444

V-by-OneⓇ
HS ModeTx

3.0GbpsCML/RGB444

Sync Free Mode

3.0GbpsCML/RGB444

V-by-OneⓇ
HS ModeRx

24bit@100MHzLVCMOS/RGB444

Case 1→Page 6

Sync Free
Mode
Rx

35bit
@80MHz
LVCMOS/RGB444

Case 2→Page 7

Sync Free
Mode
Rx

16bit
@160MHzLVCMOS/YCbCr422

Case 3→Page 830bit
@160MHzLVCMOS/RGB444

Case 4→Page 9Sync Free Mode

35bit
@80MHz
LVCMOS/RGB444

Sync FreeMode
Tx

4.0GbpsCML/RGB444

Sync Free Mode

4.0GbpsCML/RGB444

Sync Free Mode

Sync FreeMode
Tx

3.2Gbps
3.2Gbps
CML
CML/YCbCr422 /YCbCr422

V-by-OneⓇ HS Mode

V-by-OneⓇ HS Mode

V-by-OneⓇ
HS ModeTx

4.0Gbps
4.0Gbps
CML
CML/YCbCr422 /YCbCr422

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V-by-OneⓇ
HS Mode
Rx

Mux

Demux

RGB444
to
YUV422

Mux

Demux

16bit
@160MHzLVCMOS/YCbCr422

30bit@160MHzLVCMOS/RGB444

Case No.
Page No.

THCV236(-Q)

YUV422
to
RGB444THine Electronics, Inc.
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Selection table for typical application 2
Main-Link & Sub-Link

Main-Link Operation
THCV235(-Q)
V-by-OneⓇ HS Mode

THCV236(-Q)
V-by-OneⓇ HS Mode

Case No.
Page No.

Sub-Link Operation
2-wire serial I/F Mode
SCL

Main-Link
THCV235
(-Q)
SCL
SDA

24bit
@100MHzLVCMOS/RGB444

3.0Gbps 3.0Gbps
CML
CML/RGB444 /RGB444

Sub-Link
Slave

SDA

THCV236(-Q)
Sub-Link

HOST
MPU

Case 5→Page 10INT

Sub-Link
Master

24bit
THCV235(-Q): Slave / THCV236(-Q): Master@100MHzLVCMOS 2-wire serial I/F Mode
/RGB444
SCL

HOST
MPU

THCV235(-Q)
INT

Case 6→Page 11Main-Link

SDA

Sub-Link
Master

THCV236(-Q)
Sub-Link

Sub-Link
Slave

SCL
SDA

THCV235(-Q): Master / THCV236(-Q): Slave

Low Speed Data Bridge Mode
THCV235
(-Q)
SD0
SD1
SD2
SD3

Sub-Link
Slave

Main-Link

Sub-Link

THCV236(-Q)
Sub-Link
Master

SD0
SD1
SD2
SD3

Case 7→Page 12

THCV235(-Q): Slave / THCV236(-Q): Master

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Application Diagram
Main-Link
RGB24bit per pixel over 20MHz falling edge system
Set MAINMODE pin Low (V-by-One®HS Mode), HFSEL pin Low (High Frequency Mode Disable), RF pin
Low (Falling edge LVCMOS input), LFSEL pin Low (over 20MHz), COL0 pin High (Data Width Setting) and
COL1 pin Low (for Color Space Converter Disable).
V-by-One®HS Mode is suitable to transmitting data of the system with DE.
BET, BETOUT and LATEN pins can be used as Bit Error Test in actual configuration in order for debug or test
purpose.
[THCV235(-Q)]
PDN0 can be controlled by external resistor or other driving source like MCU. Design PRE pin and CMLDRV
pin in order to adjust setting appropriate to actual PCB/cable transmission line. Unused LVCMOS inputs pins
should be connected to Low (GND).
[THCV236(-Q)]
Set RXDEFSEL pin High (Default setting for the THCV235(-Q)). PDN0 and OE can be controlled by external
resistor or other driving source like MCU. Design TTLDRV pin in order to adjust setting appropriate to actual
PCB transmission trace. Unused LVCMOS output pins should be left Open. Place 10Ω resistor close to outputs,
which can be eliminated when freq. is low, trace is short, and TTLDRV=Low.

*1
indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB*3 Field BET Operation. Please see the datasheet for details. (THCV235(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)*4 No HTPDN connection option. Please see the datasheet for details. (THCV235(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)

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35bit (RGB30bit and arbitrary 5bit) per pixel over 20MHz rising edge system
Set MAINMODE pin High (Sync Free Mode), HFSEL pin Low (High Frequency Mode Disable), RF pin
High (Rising edge LVCMOS input), LFSEL pin Low (over 20MHz), COL0 pin Low (Data Width Setting) and
COL1 pin Low (for Color Space Converter Disable). Incoming data can be transmitted by Sync Free Mode
without DE requirement, and sync signals (DE, H/VSYNC) can be use as any data.
BET, BETOUT and LATEN pins can be used as Bit Error Test in actual configuration in order for debug or test
purpose.
[THCV235(-Q)]
PDN0 can be controlled by external resistor or other driving source like MCU.
Design PRE pin and CMLDRV pin in order to adjust setting appropriate to actual PCB/cable transmission line.
[THCV236(-Q)]
Set RXDEFSEL pin High (Default setting for the THCV235(-Q)). PDN0 and OE can be controlled by external
resistor or other driving source like MCU. Design TTLDRV pin in order to adjust setting appropriate to actual
PCB transmission trace. Unused LVCMOS output pins should be left Open. Place 10Ω resistor close to outputs,
which can be eliminated when freq. is low, trace is short, and TTLDRV=Low.

*1
indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB*3 Field BET Operation. Please see the datasheet for details. (THCV235(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)*4 No HTPDN connection option. Please see the datasheet for details. (THCV235(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)

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YCbCr16bit per pixel over 100MHz falling edge system
Set MAINMODE pin High (Sync Free Mode), HFSEL pin High (High Frequency Mode Enable), RF pin Low(Falling edge LVCMOS input), LFSEL pin Low (over 20MHz), COL0 pin Low (Data Width Setting) and COL1
pin Low (for Color Space Converter Disable). Sync Free Mode is suitable to transmitting data of the system
without a separate sync signal (ITU656 etc.).
BET, BETOUT and LATEN pins can be used as Bit Error Test in actual configuration in order for debug or test
purpose.
[THCV235(-Q)]
PDN0 can be controlled by external resistor or other driving source like MCU.
Design PRE pin and CMLDRV pin in order to adjust setting appropriate to actual PCB/cable transmission line.
Unused LVCMOS inputs pins should be connected to Low (GND).
[THCV236(-Q)]
Set RXDEFSEL pin High (Default setting for the THCV235(-Q)). PDN0 and OE can be controlled by external
resistor or other driving source like MCU. Design TTLDRV pin in order to adjust setting appropriate to actual
PCB transmission trace. Unused LVCMOS output pins should be left Open. Place 10Ω resistor close to outputs,
which can be eliminated when freq. is low, trace is short, and TTLDRV=Low.

*1
indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB*3 Field BET Operation. Please see the datasheet for details. (THCV235(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)*4 No HTPDN connection option. Please see the datasheet for details. (THCV235(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)

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RGB30bit per pixel over 100MHz falling edge system
Set MAINMODE pin Low (V-by-One®HS Mode), HFSEL pin High (High Frequency Mode Enable), RF pin
Low (Falling edge LVCMOS input), LFSEL pin Low (over 20MHz), COL0 pin Low (Data Width Setting) and
COL1 pin High (for Color Space Converter Enable).V-by-One®HS Mode is suitable to transmitting data of thesystem with DE. In this case, D25-D24 pins are not able to use because internal data width rule.
BET, BETOUT and LATEN pins can be used as Bit Error Test in actual configuration in order for debug or test
purpose.
[THCV235(-Q)]
PDN0 can be controlled by external resistor or other driving source like MCU. Design PRE pin and CMLDRV
pin in order to adjust setting appropriate to actual PCB/cable transmission line. Unused LVCMOS inputs pins
should be connected to Low (GND).
[THCV236(-Q)]
Set RXDEFSEL pin High (Default setting for the THCV235(-Q)). PDN0 and OE can be controlled by external
resistor or other driving source like MCU. Design TTLDRV pin in order to adjust setting appropriate to actual
PCB transmission trace. Unused LVCMOS output pins should be left Open. Place 10Ω resistor close to outputs,
which can be eliminated when freq. is low, trace is short, and TTLDRV=Low.
1kΩ

TxPDWNLVCMOS
Driver

THCV235(-Q)

Damping resistor
ex. 10Ωclose toTHCV236 LVCMOS
Receiver(-Q)

THCV236(-Q)

NC

1kΩ

RxPDWNNC

D23-D0

D23-D0HTPDN/SUBMODE
D31-D26HTPDN/SUBMODE
D25-D24
NC

D25/GPIO4,D24/GPIO3

D31-D26

LATENset

DE, H/VSYNC
LOCKN/MSSEL

0Ω

1kΩ

TxPDWNLATENset
CMLDRVset
PREsetTxBETset
SSset

CMLDRVset
NC

NC

LOCKN/MSSEL
10kΩ

CLKIN

RXN
RXP

TXP

LATEN/SD3/AIN1/GPIO4

0.1uF

BET

BET/GPIO1
SSEN/GPIO0

MAINMODE/RCMN

1kΩ
1kΩ

PDN1

10uF

10uF

0.1uF

0.1uF

COL1/SD0CAPOUTCAPOUTPDN1
LFSEL

CAPINA

CAPINA

0Ω

1kΩ
NC
NC

0Ω

NC

1kΩ

RF/BETOUT

CAPINP0Ω

NC

RXDEFSEL

0.1uF
RF/BETOUTNC

OUTSELset

TTLDRVset

COL0/INT/GPIO2

LFSEL

TxBETset NC

OE

RxPDWN
BETlatch
OUTSELset
TTLDRVset
RxBETset
OEset

HFSEL/RCMP

COL0/INT/GPIO2
COL1/SD00Ω

LATEN/SD3/AIN1/GPIO0TTLDRV/SD2/AIN0/GPIO1

MAINMODE/TCMP

NC

PDN0
OUTSEL/SD1

PRE/SD1

PREset1kΩ

0.1uF

CMLDRV/SD2/AIN0/GPIO3

HFSEL/TCMN

0Ω0Ω

CLKOUT

TXN
PDN0

NC

BETlatch

DE, H/VSYNC

RxBETset
0Ω

0Ω

TEST1

TEST1

TEST2

TEST2

1kΩ

SSset

OEset

0Ω

NC

*1
indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB*3 Field BET Operation. Please see the datasheet for details. (THCV235(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)*4 No HTPDN connection option. Please see the datasheet for details. (THCV235(-Q)_THCV236(-Q)_Rev.1.00_E.pdf and up)

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Main-Link & Sub-Link
2-wire serial I/F (THCV235(-Q): Sub-Link Slave side, THCV236(-Q): Sub-Link Master side)
Set PDN1 pin High (Sub-Link Normal Operation) and SUBMODE pin Low (2-wire serial I/F Mode). The
THCV235(-Q) and THCV236(-Q) have to be same setting.
Unused GPIO output pins should be left Open, input pins should be connected to Low (GND).
[THCV235(-Q)]
Set MSSEL pin High (Sub-Link Slave side). Connect to 2-wire serial Slave Device by SD0 (SDA) and SD1(SCL).
GPIO4 and GPIO3 pins is invalid by this pins setting. Have to set internal registers.
[THCV236(-Q)]
Set MSSEL pin Low (Sub-Link Master side). Connect to MPU by SD0 (SDA) and SD1 (SCL).
Set RXDEFSEL pin High (Register default setting for the THCV235(-Q)).
Set AIN[1:0] pin Device ID (00: 7’b0001011).
Note 1: In order to change Main-Mode setting from default, it has to set internal registers (Refer to page 15,
17).
Note 2: In order to use GPIO by the THCV236(-Q) side at this pins setting, it has to set internal registers(Refer to page 25).
1kΩ

LVCMOSTxPDWN DriverNC

THCV235(-Q)
Sub-Link
Slave side

Damping resistor
ex. 10Ωclose toTHCV236 LVCMOS
Receiver(-Q)

THCV236(-Q)
Sub-Link
Master sideNC

D23-D0

D23-D0HTPDN/SUBMODEHTPDN/SUBMODE

D31-D26

D31-D24

NC

D25/GPIO4,D24/GPIO3

10kΩ

DE, H/VSYNC

TxGPIO4LOCKN/MSSELRxBETset

DE, H/VSYNC

1kΩ

0Ω

LOCKN/MSSEL

CLKIN

CLKOUT

10kΩ

TxPDWNPDN0
TXP
TxGPIO4
LATEN/SD3/AIN1/GPIO4
0.1uF
TxGPIO3CMLDRV/SD2/AIN0/GPIO3
TxGPIO2
COL0/INT/GPIO2TxGPIO1
BET/GPIO1TxGPIO010kΩ

TxGPIO2When GPIO
SSEN/GPIO0
set input, push
HFSEL/TCMN
10kΩ
pull output or
unused, there
MAINMODE/TCMPTxSCL
pull up
PRE/SD1
0.1uF
10kΩ TxSDA
resistors must
COL1/SD0
be dispensed
10uFTo
2-wireserialwith.
CAPOUT
Slave Device
1kΩ
10kΩ

TxGPIO1

NC

PDN1
LFSEL
RF/BETOUT

0.1uF

1kΩ

RXN

TXN

TxGPIO3

RXP
0.1uF

PDN0

TxGPIO0OEset

RxPDWNLATEN/SD3/AIN1/GPIO0TTLDRV/SD2/AIN0/GPIO1
BET
OE

NC

RxBETset
OEset
10kΩ

0.1uF

MAINMODE/RCMNRxSCL
OUTSEL/SD1
HFSEL/RCMP
RxSDA
COL1/SD0

10uF

CAPOUT

0.1uF

CAPINA

10kΩ
10kΩ

COL0/INT/GPIO2PDN1RXDEFSELCAPINA1kΩ

To 2-wire serial
MPU (Host Device)
1kΩ

LFSEL

0.1uF

NC

RF/BETOUT

CAPINP

0Ω
10kΩ

1kΩ

RxPDWN

0Ω

TEST1

TEST1

TEST2

TEST2

*1
indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB

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2-wire serial I/F (THCV235(-Q): Sub-Link Master side, THCV236(-Q): Sub-Link Slave side)
Set PDN1 pin High (Sub-Link Normal Operation) and SUBMODE pin Low (2-wire serial I/F Mode). The
THCV235(-Q) and THCV236(-Q) have to be same setting.
Unused GPIO output pins should be left Open, input pins should be connected to Low (GND).
[THCV235(-Q)]
Set MSSEL pin Low (Sub-Link Master side). Connect to MPU by SD0 (SDA) and SD1 (SCL).
Set AIN1, AIN0 pin Device ID (00: 7’b0001011).
[THCV236(-Q)]
Set MSSEL pin High (Sub-Link Slave side). Connect to 2-wire serial Slave Device by SD0 (SDA) and SD1(SCL).
Set RXDEFSEL pin High (Register default setting for the THCV235(-Q)).
Note 1: In order to change Main-Mode setting from default, it has to set internal registers (Refer to page 15,
17).
Note 2: In order to use GPIO by the THCV236(-Q) side at this pins setting, it has to set internal registers(Refer to page 25).
1kΩ

LVCMOS

THCV235(-Q)
Sub-Link
Master side

TxPDWN DriverNC

THCV236(-Q)
Sub-Link
Slave side

D23-D0HTPDN/SUBMODENC

HTPDN/SUBMODE
D31-D26

NC

D25/GPIO4,D24/GPIO3
DE, H/VSYNC

TxGPIO11kΩ

LOCKN/MSSELTxGPIO0TxPDWN

When GPIO
set input, push
pull output or
unused, there
pull upresistors must
be dispensed
with.

DE, H/VSYNC

RXN

TXN
PDN0

TXP

LATEN/SD3/AIN1/GPIO4

0.1uF

0.1uF

PDN0
RXP
LATEN/SD3/AIN1/GPIO0TTLDRV/SD2/AIN0/GPIO1

TxGPIO1
BET/GPIO1TxGPIO0

COL0/INT/GPIO2
BETOE

SSEN/GPIO0
COL0/INT/GPIO2

10kΩ

10kΩ

HFSEL/TCMN

MAINMODE/TCMPTxSCL PRE/SD1
TxSDA COL1/SD0

To 2-wire serial
MPU (Host Device)

1kΩ

PDN1

0.1uF

0.1uF

0.1uF

0.1uF

PDN1 1kΩ
RXDEFSELCAPINATo 2-wire serial
Slave Device
1kΩ

NC

CAPINP

10kΩ
10kΩ

RxGPIO2
10kΩ

RxGPIO1

LFSEL

0.1uF

NC

NC

COL1/SD0CAPOUT

CAPINA

OEset

10kΩ

HFSEL/RCMPOUTSEL/SD1

10uF

CAPOUT

1kΩ

RxPDWNRxGPIO0RxGPIO1RxGPIO2RxBETset
OEset

MAINMODE/RCMN

10uF

LFSEL

RF/BETOUT

0Ω

CLKOUTCMLDRV/SD2/AIN0/GPIO3

10kΩ

RxBETset

LOCKN/MSSEL

CLKIN

10kΩ

1kΩ

RxPDWN

D23-D0

D31-D2410kΩ

Damping resistor
ex. 10Ωclose toTHCV236 LVCMOS
Receiver(-Q)

RF/BETOUT

0Ω

0Ω

TEST1

TEST1

TEST2

TEST2

10kΩ

RxGPIO0
When GPIO
set input, push
pull output or
unused, there
pull upresistors must
be dispensed
with.

*1
indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB

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Low Speed Data Bridge (THCV235(-Q): Slave side, THCV236(-Q): Master side)
Set PDN1 pin High (Sub-Link Normal Operation) and SUBMODE pin High (Low Speed Data Bridge Mode).
The THCV235(-Q) and THCV236(-Q) have to be same setting.
BET and BETOUT pins can be used as Bit Error Test in actual configuration in order for debug or test purpose.
Unused SD3, SD2, SD1 and SD0 output pins should be left Open, input pins should be connected to Low(GND).
[THCV235(-Q)]
Set MSSEL pin High (Sub-Link Slave side).
[THCV236(-Q)]
Set MSSEL pin Low (Sub-Link Master side).
Set RXDEFSEL pin High (Register default setting for the THCV235(-Q)).
Note 1: Low Speed Data Bridge Mode cannot access to register (Sub-Link Master/Slave side and 2-wire serial
slave device), and does not support GPIO function.
1kΩ

TxPDWNLVCMOS
DriverNC

THCV235(-Q)
Sub-Link
Slave side
D23-D0HTPDN/SUBMODE

Damping resistor
ex. 10Ωclose toTHCV236 LVCMOS
Receiver(-Q)

THCV236(-Q)
Sub-Link
Master side1kΩ 1kΩ

1kΩ

NC

D31-D26

RxBETset

D25/GPIO4,D24/GPIO3
DE, H/VSYNC

TxSD3

0Ω

DE, H/VSYNC

LOCKN/MSSELLOCKN/MSSEL

CLKIN

CLKOUT

1kΩ

10kΩ

TxPDWN
PDN0
TXP
TxSD3
LATEN/SD3/AIN1/GPIO4
0.1uF
TxSD2

RXP
0.1uF

CMLDRV/SD2/AIN0/GPIO3

10kΩ

1kΩ

TxSD1

OEset

RXN

TXN

TxSD2

RxPDWNRxSD3
RxSD2
RxBETset
OEset

PDN0

LATEN/SD3/AIN1/GPIO0TTLDRV/SD2/AIN0/GPIO1

COL0/INT/GPIO2

BET

BET/GPIO1

OE

SSEN/GPIO0

TxSD1
TxSD0

TxSD0
Low Speed
Data Output(SD0, SD1,
SD2) and input(SD3)
A 10kΩ pull-up
resistor of input
pin is option.

1kΩ

MAINMODE/TCMP
PRE/SD1
COL1/SD0
PDN1

0.1uF
10uF

0.1uF

MAINMODE/RCMNOUTSEL/SD1
HFSEL/RCMP
COL1/SD0

10kΩ

0.1uF

CAPINA1kΩ

PDN1

CAPINARxSD210kΩ

RXDEFSEL
LFSEL

0.1uF

NC

10kΩ

1kΩ

CAPOUT

0.1uF

RxSD1
RxSD0

COL0/INT/GPIO2 1kΩ

10uF

CAPOUT

LFSEL

RF/BETOUT

NC

RxSD3

HFSEL/TCMN

10kΩ

NC

D23-D0HTPDN/SUBMODE

D31-D2410kΩ

1kΩ

RxPDWNRxSD1
NCCAPINP

RF/BETOUT

0Ω

10kΩ
0Ω

TEST1

TEST1

TEST2

TEST2

RxSD0
Low Speed Data
Input (SD3) and
Output (SD0, SD1,
SD2)
10kΩ pull-up
resistors of input
pins are option.

*1
indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω*2 Connect GNDs of both Tx and Rx PCB

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THAN0195_Rev.1.30_E

Signaling Usage
Example Connection 1: Sharing LOCKNLOCKN connection can be shared with CML trace. Put 1kΩ resistance on both side.
The THCV236(-Q) side AC coupling capacitors must be 100pF.

THCV235(-Q)

THCV236(-Q)

30kΩ

LOCKN/MSSELLOCKN/MSSEL

1kΩ

1kΩ
RXN

TXN

0.1uF

100pF

0.1uF

100pF

RXP

TXP

Example Connection 2: Sharing Power Supply
Power supply on common trace is also accomplished by another simple PCB circuit. Put 1uH inductor on bothside. Inductor SRF (Self-resonant frequency) should be more than 160MHz. Inductor supply current tolerance
must be more than requirement (ex. 500mA).
The THCV236(-Q) side AC coupling capacitors must be 100pF.
Secondary side VDD

Primary side VDD

1uH

1uH

160MHz < SRF

THCV235(-Q)

THCV236(-Q)
RXN

TXN

0.1uF

100pF

0.1uF

100pF

RXP

TXP

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Sub-Link Communication
Sub-Link Notification
All of Sub-Link specifications are on the premise that Sub-Link transmission is established because Sub-Link
continues the polling operation even if there are no data accesses.
Please keep below conditions.
1.
Sub-Link I/O is connected between the THCV235(-Q) and THCV236(-Q).
2.
The THCV235(-Q) and THCV236(-Q) are powered on and also PDN1=1.

If the above conditions cannot be held, please power down Sub-Link Master with PDN1=0.

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Example Operation 1-1: Access to Sub-Link Master Device Register
Writing MAINMODE to Sub-Link Master Device Register.

HOST

SCL
SDA
INT
SUBMODE
=0
MSSEL
=0

Ex. AIN0=1, AIN1=0→Device ID: 7'h34

Sub-Link Master Device

Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
MasterInternalBus

Sub-Link

Sub-Link
Slave

2-wire serial
MasterSUBMODE=0
Sub-Link Master side Register

Step

Address

Bits

W/R

Value

1

0x01

0

W

1

MSSEL
=1

SCL
SDA
2-wire serial
Slave Device

InternalBus
Sub-Link Slave side Register
Step

Address

Bits

W/R

Value

1

-

-

-

-

1. Write 1 to bit[0] of 0x01 in Sub-Link Master Device Register. Sub-Link Register is soft reset.
Write 1: Sub-Link rest
The register is automatically cleared into 0 after reset action.
Note: Sub-Link Master Register can set by 0x00-0x7F.

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Reading 2WIRE_DATA0 on Sub-Link Master Register.

1. Read 0x10 of Sub-Link Master Device Register.
Bit[7:0] 2-wire serial I/F Write/Read Data #0
Note: Sub-Link Master Register can set by 0x00-0x7F.

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Example Operation 1-2: Access to Sub-Link Slave Device Register
Writing MAINMODE to Sub-Link Slave Device.

1. Write any value to bit[7] of 0x02 for clear access status register. This bit is into 0 after any write action.
S

7'h34

W

A

8'h02

A

1

7'h00

A

P

8'h80

2. Set 09 to bit[6:0] of 0x10 for SCL high width changed.
((SCL_W_H + 1)*8+8)*tocs=((9+1)*8+8)*12.5ns(Typ)=1.1us

3. Set target Device ID (0x34) to bit[6:0] of 0x20.

4. Set 0x00 to bit[3:0] of 0x21 for the amount of data byte intended to be sent.
Note 1: The actual number of sent byte is register value +1.
Note 2: The maximum data size is 16byte.

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5. Set start address (0x8C) to bit[7:0] of 0x23.

6. Write 1 to bit[0] of 0x25 to start write access to Sub-Link Slave register.

7. When write access is complete, bit[7] of 0x02 value becomes “1” and INT pin H→L. HOST MPU thenreceives interruption read access status register, confirming that write access is complete. If normally ended,
the read result should be 0x80.

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Reading FMOD on Sub-Link Slave Register.

HOST

SCL
SDA
INT
Step 6
INT: H→L
SUBMODE
=0
MSSEL
=0

Ex. AIN0=1, AIN1=0→Device ID: 7'h34

Sub-Link Master Device

Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

2-wire serial
MasterInternal
Bus

SCL
SDA
2-wire serial
Slave Device

InternalBus
Sub-Link Master side Register

Step

Address

Bits

W/R

Value

1

0x02

7

W

*

2

0x20

6:0

W

0x34

3

0x22

3:0

W

4

0x24

7:0

5

0x26

6
7

SUBMODE=0

Sub-Link Slave side Register
Step

Address

Bits

W/R

Value

1

-

-

-

-

2

-

-

-

-

0x0

3

-

-

-

-

W

0xD2

4

-

-

-

-

0

W

1

5

-

-

-

-

0x02

7

R

1

6

0xD2

3:0

R

0x3

0x10

3:0

R

0x3

7

-

-

-

-

MSSEL
=1

1. Write any value to bit[7] of 0x02 for clear access status register. This bit is into 0 after any write action.

2. Set target Device ID (0x34) in 0x20.

3. Set “the number of reading register -1” (0x0) to bit[3:0] of 0x22.
Note: The maximum data size is 16byte.

4. Set start address (0xD2) in 0x24 for setting Slave Device Address.

5. Write 1 to bit[0] of 0x26, and start read access to Sub-Link Slave register.

6. When read access is complete, read data is stored bit[7:0] in 0x10 (FMOD value is bit[3:0]), bit[7] of 0x02
value becomes “1” and INT pin H→L. If normally ended, the read result should be 0x80.

7. Read FMOD setting in 0x10.

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Example Operation 1-3: Access to 2-wire serial Slave Device with 8bit Register Address
Writing 3byte data to 2-wire serial Slave Device with 8bit Register Address.

1. Set 2-wire serial Slave Device ID (ex. 0x27) to bit[6:0] in 0x04 and set 1 to bit[7]. This step is not supposed
to be repeated.
Bit[6:0] Device ID
Bit[7]
0=Disable / 1=Enable

Note: The maximum entry is 8devices, 0x04-0x0B.
2. Write any value to bit[7] of 0x02 for clear access status register. This bit is into 0 after any write action.

3. Set 3byte data (ex. 0x1A, 0x2B, 0x3C) into 0x10-0x12 for writing into 2-wire serial Slave Device.

Note: The maximum data size is 16byte.

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4. Set target 2-wire serial Slave Device ID (0x27) bit[6:0] of 0x20 and set 0 to bit[7].
Bit[7]
0 = 8bit Register Address (Default)
1 = 16bit Register Address
Bit[6:0]
Target Device ID

5. Set “the number of write byte -1” (0x02) in 0x21.

6. Set start address of 2-wire serial Slave Device (ex. 0xC2) in 0x23.

7. Write 1 to bit[0] of 0x25 to start write access to 2-wire serial Slave Device register.

8. When write access is complete, bit[7] of 0x02 value becomes “1” and INT pin H→L. HOST MPU thenreceives interruption read access status register, confirming that write access is complete. If normally ended,
the read result should be 0x80.

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Example Operation 1-4: Access to 2-wire serial Slave Device with 16bit Register Address
Reading 3byte data to 2-wire serial Slave Device with 16bit Register Address.

HOST

SCL
SDA
INT
Step 8
INT: H→L
SUBMODE
=0
MSSEL
=0

Ex. AIN0=1, AIN1=0→Device ID: 7'h34

Sub-Link Master Device

Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

SUBMODE=0InternalBus
Sub-Link Master side Register

MSSEL
=1

2-wire serial
Master2-wire serial Slave Device
Ex. device ID: 7'h3B
Register Address: 16bit

SCL
SDA

2-wire serial Slave Device Register

InternalBus
Sub-Link Slave side Register

Step

Address

Bits

W/R

Value

Step

Address

Bits

W/R

Value

1

0x04

7:0

W

0xBB

1

-

-

-

-

2

0x02

7

W

*

2

-

-

-

-

3

0x20

7:0

W

0xBB

3

-

-

-

-

4

0x22

3:0

W

0x2

4

-

-

-

-

5-1

0x29

7:0

W

0xA2

5-2

0x2A

7:0

W

0x5D

5

-

-

-

-

6

0x2C

0

W

1

6

-

-

-

7

0x02

7

R

1

7

0x5DA20x5DA4

7:0

R

0xA1,
0x92,
0x83

8

0x100x12

7:0

R

0xA1,
0x92,
0x83

8

-

-

-

-

1. Set 2-wire serial Slave Device ID (ex. 0x3B) to bit[6:0] of 0x04 and set 1 to bit[7]. This step is not supposed
to be repeated.
Bit[7]
0=Disable (Default) / 1=EnableBit[6:0] Device ID

Note: The maximum entry is 8devices, 0x04-0x0B.
2. Write any value to bit[7] of 0x02 for clear access status register. This bit is into 0 after any write action.

3. Set target 2-wire serial Slave Device ID (0x3B) bit[6:0] of 0x20 for reading register access and set 1 tobit[7] for 16bit Register Address.
Bit[7]
0 = 8bit Register Address (Default)
1 = 16bit Register Address
Bit[6:0] Target Device ID

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4. Set “the number of read byte -1” (0x02) in 0x22.
Note: The maximum data size is 16byte.

5. Set start address of 2-wire serial Slave Device ID (ex. 0x5DA2) in 0x29 and 0x2A.
0x29:
start address [7:0]
0x2A: start address [15:8]
S

7'h34

W

A

8'h29

A

8'hA2

A

8'h5D

A

P

6. Write 1 to bit[0] of 0x2C to start read access to 2-wire serial Slave Device register.

7. When read access is complete, reading data is stored into 0x10-0x12, bit[7] of 0x02 becomes “1”, and INT
pin H→L. If normally ended, the read result should be 0x80.

8. Read 3 byte data in 0x10-0x12.
S

7'h34

W

A

A

8'h10

8'hA1

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A

8'h92

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A

8'h83

A

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Example Operation 2-1: Programmable GPIO output control
Control output GPIO of the THCV235(-Q) (Sub-Link Master side) and GPIO of the THCV236(-Q)(Sub-Link Slave side).

HOST

SCL
SDA
INT
SUBMODE
=0
MSSEL
=0

AIN1, AIN0=00:7'h0B
01:7'h34
10:7'h77
11:7'h65

THCV235(-Q) Sub-Link Master Device

THCV236(-Q) Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
MasterInternalBus

Sub-Link

Sub-Link
Slave

2-wire serial
MasterSUBMODE=0
Sub-Link Master side Register

Step

Address

Bits

W/R

Value

1

0x40

1:0

W

0x0

2

0x46

1:0

W

Valid

3

0x42

1:0

W

Valid

4

0x43

1:0

W

0x0

MSSEL
=1

RXDEFSEL
=1

SCL
SDA
2-wire serial
Slave Device

InternalBus
Sub-Link Slave side Register
Step

Address

Bits

W/R

1

0xC0

2:0

W

0x0

2

0xC6

2:0

W

Valid

3

0xC2

2:0

W

Valid

4

0xC3

2:0

W

0x0

GPIO1, GPIO0 = H / L

Value

GPIO2, GPIO1, GPIO0 = H / L

1. GPIO transmission type setting with bit[1:0] of 0x40 (Master side Register) and bit[2:0] of 0xC0 (Slave side
Register, refer to page17).
Bit[4:3]
Bit[2:0] (Read only)

0 = Programmable GPIO enable
1 = Through GPIO enable (Default)
0 = Programmable GPIO enable

2. GPIO output buffer type setting with bit[1:0] of 0x46 (Master side Register) and bit[2:0] of 0xC6 (Slaveside Register).
1=Push-pull output
0=Open-Drain output (Default)
3. GPIO output value setting with bit[1:0] of 0x42 (Master side Register) and bit[2:0] of 0xC2 (Slave side
Register).
1=H (Push-pull output: H / Open-Drain output: Hi-Z)
0=L (Default)
4. GPIO polarity setting with bit[1:0] of 0x43 (Master side Register) and bit[2:0] of 0xC3 (Slave side
Register).
1=Input0=Output
Note: The number of valid GPIO depends on Slave or Master Side.

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Example Operation 2-2: Programmable GPIO input control
Control input GPIO of the THCV236(-Q) (Sub-Link Master side) and GPIO of the THCV235(-Q) (Sub-Link
Slave side). When the THCV236(-Q) is the Master side device, in order to enabling GPIO Pin, need to set as
register.

1. Set RXDEFSEL pin Low for using GPIO, and set 0x0 to bit[7:4] of 0x50 (Sub-Link Master Side Register)because Main-Link register is changed from default value.
2. GPIO transmission type setting with bit[4:3] of 0x40 (Master side Register) and bit[4:0] of 0xC0 (Slave side
Register, refer to page17).
Bit[4:3]
Bit[2:0] (Read only)

0 = Programmable GPIO enable
1 = Through GPIO enable (Default)
0 = Programmable GPIO enable

3. GPIO polarity setting with bit[4:3] of 0x43 (Master side Register) and bit[4:0] of 0xC3 (Slave side
Register).
1=Input0=Output
4. Read bit[4:3] of 0x41 (Master side Register) and bit[4:0] of 0xC1 (Slave side Register, refer to page 19).
Note 1: The number of valid GPIO depends on Slave or Master Side.
Note 2: Step 1 can be neglected if the system can change RXDEFSEL 1→0 after releasing Power Down Mode.

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Example Operation 2-3: Through GPIO Sub-Link Master to Sub-Link Slave
Control through GPIO of the THCV236(-Q) (Sub-Link Master) and through GPIO of the THCV235(-Q)(Sub-Link Slave Device).

1. Set RXDEFSEL pin Low for using GPIO, and set 0x0 to bit[7:4] of 0x50 (Sub-Link Master Side Register)because Main-Link register is changed from default value.
2. GPIO transmission type setting with bit[4:3] of 0x40 (Master side Register) and bit[4:3] of 0xC0 (Slave side
Register, refer to page 17).
Bit[4:3]
0 = Programmable GPIO enable
1 = Through GPIO enable (Default)
3. GPIO output buffer type setting with bit[4:3] of 0x46 (Master side Register) and bit[4:3] of 0xC6 (Slaveside Register).
1=Push-pull output
0=Open-Drain output (Default)
4. GPIO polarity setting with bit[4:3] of 0x43 (Master side Register) and bit[4:3] of 0xC3 (Slave side
Register).
1=Input0=Output
5. GPIO4 and GPIO3 input of Master side is updated automatically to GPIO4 and GPIO3 output of Slave side.
Note 1: Through GPIO is able to be implemented with this example composition only: GPIO Pin number, slave
side is the THCV235(-Q), master side is the THCV236(-Q), and data direction.
Note 2: Step 1 can be neglected if the system can change RXDEFSEL 1→0 after releasing Power Down Mode.

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Example Operation 3-1: Interrupt feedback as internal factor
Cause of interrupt is internal factor (ex. Sub-Link time out)

1. Set interrupt permission status about Sub-Link time out with bit[0] of 0x03 (Master side Register).
1=Interrupt allowed
0=Interrupt blocked (Default)
2. When disconnection occurs or Sub-Link access time out is occurred by Noise or other elements, aninterruption occurs. (INT=H → L)
3. Read the cause of interruption register with bit[7:0] in 0x02 (Master side Register).
4. Write any value to the cause of interruption register on bit[0] in 0x02 (Master side Register).
The cause of interruption register is cleared.
Interruption released. (INT=L → H)

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Example Operation 3-2: Interrupt output as external factor by Slave side
Cause of interrupt is external factor (ex. NACK signal from 2-wire serial Slave Device).

HOST

SCL
SDA
INT
Step 3
INT: H→L
Step6
INT: L→H

MSSEL=0
AIN1, AIN0=00:7'h0B
01:7'h34
10:7'h77
11:7'h65

Sub-Link Master Device

Sub-Link Slave Device

Sub-Link Block

Sub-Link Block2-wire serial
Slave

Sub-Link
Master

Sub-Link

Sub-Link
Slave

2-wire serial
MasterInternal
Bus

InternalBus
Sub-Link Master side Register

SCL
SDA
Step 3
NACK
signal2-wire serial
Slave Device

Sub-Link Slave side Register

Step

Address

Bits

W/R

Value

Step

Address

Bits

W/R

1

0x03

4

W

1

1

-

-

-

-

2

-

-

-

-

2

0x83

4

W

1
-

MSSEL
=1

Value

3

-

-

-

-

3

-

-

-

4

0x02

7:0

R

0x10

4

-

-

-

-

5

-

-

-

-

5

0x82

7:0

R

0x01

6

0x02

4

W

*

6

0x82

4

W

*

1. Set interrupt permission status about Slave side interrupt action with bit[4] of 0x03 (Master side Register).
1=Interrupt allowed
0=Interrupt blocked (Default)
2. Set interrupt permission status about 2-wire serial Slave Device NACK action with bit[4] of 0x83 (Slaveside Register, refer to page17).
1=Allowed to be reported to Master side
0=Blocked to be reported to Master side (Default)
3. Slave side device receive NACK signal from 2-wire serial Slave Device. An interruption occurs. (INT=H →L)
4. Read the cause of interruption register (SLAVESIDE_INT) with bit[4] of 0x02 (Master side Register).
5. Read the cause of interruption register (2WIRE_NACK_INT) with bit[4] of 0x82 (Slave side Register),refer to page 19.
6. Write any value to a cause of interruption register with bit4 of 0x02 (Master side Register) and bit[4] of
0x82 (Slave side register).
Cause of interruption register is cleared.
Interruption released. (INT=L → H)

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Example Operation 4: UART Communication by Low Speed Data Bridge

UART
Device 1

SD0
SD3
SUBMODE
=1
MSSEL
=0

AIN1, AIN0=00:7'h0B
01:7'h34
10:7'h77
11:7'h65

Sub-Link Master Device

Sub-Link Slave Device

Sub-Link Block

Sub-Link Block

Low Speed Data
Bride Master side

Sub-Link
Master

Sub-Link

Sub-Link
Slave

Low Speed Data
Bride Slave sideSUBMODE=1InternalBus
Sub-Link Master side Register

MSSEL
=1

SD0
SD3

UART
Device 2

InternalBus
Sub-Link Slave side Register

Set SUBMODE pin High to both Master and Slave. The UART transmission can be implemented by SD0, SD1
or SD2 and SD3.
Note 1: Low Speed Data Bridge Mode cannot access to register (Sub-Link Master/Slave side and 2-wire serial
slave device), and does not support GPIO function.
Note 2: Master side device has 3 input-pins and 1 output-pin. Slave side device has 1 input-pin and 3
output-pins.

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Example Operation 5: Sub-Link communication to THCV233 or THCV234
When the THCV235(-Q) is Sub-Link master side and the THCV234 is Sub-Link slave side.

Sub-Link signaling is able to same as above Example Operations. Refer to the THCV234 register map instead of
the THCV236(-Q) register map.
When the THCV236(-Q) is Sub-Link master side and the THCV233 is Sub-Link slave side.

Sub-Link signaling is able to same as above Example Operations. Refer to the THCV233 register map instead of
the THCV235(-Q) register map.
When the THCV233 is Sub-Link master side and the THCV236(-Q) is Sub-Link slave side.
andWhen the THCV234 is Sub-Link master side and the THCV235(-Q) is Sub-Link slave side.

Refer to the THCV233/THCV234 application note (THAN0097_Rev.1.40_E.pdf and up). The 2-wire serial
access is clock stretching mode only.
Note: Sub-Link containing the THCV233/THCV234 is not capable to support 16bit Register address device.

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Power Supply Usage

Separate all power domains in order to avoid unwanted noise coupling between noisy digital and sensitive
analog domains. In particular, PCB layout guide between AVDD (40 Pin) and VDD (41 Pin) are shown
page 32 for the THCV236(-Q).
Use 0.1uF high frequency ceramic capacitors as bypass capacitors between power and ground pins. Placethe capacitors as close to each power pin as possible.

0.1uF

Power Supply for THCV235(-Q) / THCV236(-Q)

0.1uF

VDD
3.6V-1.7V

10uF

AVDD

0.1uF

47

46

45

44

43

42

AVDD

48

VDD

VDD

10uF

41

40

39

38

37

36

35

34

33

49

32

50

31

51

30

52

29

53

28

54

VDD

0.1uF

27

THCV235(-Q)/THCV236(-Q)

55

26

56

25

Exposed PAD

57

24

58

VDD

0.1uF

23

65 EXPGND

59

22

60

21

61

20

62

19

63

18

64

17
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VDD
0.1uF

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PCB layout guideline between VDD (41Pin) and AVDD (40Pin) for THCV236(-Q)
When power is supplied from reverse side layer to AVDD, please place ferrite bead behind through-hole (GoodExample1, 2). If it is needed to set ferrite beads on reverse side, please set GND-through-hole between AVDD
and VDD, and separate the distance as possible (Example). Do not set through-holes next to each other after
ferrite beads (Bad Example).
Good Example 1
Good Example 2
3.6V-1.7V
BottomLayerthrough-hole

ferrite bead
bypasscapasitor

Close to power pin
as possible

39

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VDD
D8

AVDD

VDD

D7

D8

AVDD

VDD

Bad Example

D7

Example

D8

40

AVDD

41

D7

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Note1) Power On Sequence
Do not input clock or data before the THCV235(-Q) on in order to keep absolute maximum ratings.
2) Cable Connection and Disconnection
Do not connect and disconnect the LVCMOS and CML cable/connector, when the power is supplied to thesystem.

3) GND Connection
Connect the each GND of the PCB where the THCV235(-Q) and THCV236(-Q) are on it. It is better for
EMI reduction to place GND cable as close to LVCMOS and CML cable as possible.
4) Low Input Pulse into PDN1 and PDN0 Period Requirement
Do not Input Low Pulse within 1msec into PDN1 and PDN0.

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5) Multiple device connection
LOCKN signal is supposed to be connected proper for their purpose like the following figure.

LOCKN of Tx side can be simply split to multiple Tx.
There could be other applicable circuit like ‘OR gate of LOCKN’, ‘npn transistor with resistors as inverter’,etc.
Also possible time difference of internal processing time (please see the datasheet for details) on multiple
data stream must be accommodated and compensated by the following destination device connected tomultiple the THCV236(-Q), which may have internal FIFO.

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PCB Layout Considerations
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Use at least four-layer PCBs with signals, ground, power, and signals assigned for each layer. (Refer tofigure below.)
PCB traces for high-speed signals must be single-ended microstirp lines or coupled microstrip lines whose
differential characteristic impedance is 100Ω.
Minimize the distance between traces of a differential pair (S1) to maximize common mode rejection andcoupling effect which works to reduce EMI (Electro-Magnetic Interference).
Route differential signal traces symmetrically.
Avoid right-angle turns or minimize the number of vias on the high speed traces because they usually cause
impedance discontinuity in the transmission lines and degrade the signal integrity.
Mismatch among impedances of PCB traces, connectors, or cables also caused reflection, limiting the
bandwidth of the high-speed channels.
Using common-mode filter on differential traces is desirable to reduce EMI. Pay attention on data-rate
driven noise. For example, if data-rate is 1.5Gbps, common mode choke coil of 1.5GHz common mode
impedance is desired to be high, while 1.5GHz differential impedance is low.

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Notices and Requests
1.
2.

The product specifications described in this material are subject to change without prior notice.
The circuit diagrams described in this material are examples of the application which may not always apply
to the customer's design. We are not responsible for possible errors and omissions in this material. Please
note if errors or omissions should be found in this material, we may not be able to correct them
immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.
5. Product Application
5.1. Application of this product is intended for and limited to the following applications:audio-video device, office automation device, communication device, consumer electronics, smartphone,feature phone, and amusement machine device. This product must not be used for applications that
requireextremely
high-reliability/safetysuchasaerospacedevice, traffic
device,transportation device, nuclear power control device, combustion chamber device, medical
device related to critical care, or any kind of safety device.
5.2. This product is not intended to be used as an automotive part, unless the product is specified as a productconforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet.
THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than the Specified
Product for it not conforming to the aforementioned demands and specifications.
5.3. THine accepts liability for demands and specifications of the Specified Product only to the extent that theuser and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with acertain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged tohave sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary
to support warranty for performance of this product. Except where mandated byapplicable law or deemed necessary by THine based on the user’s request, testing of all
functions and performance of the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over theabsolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance.
The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safetymeasures by adding protection devices, such as fuses.

THine Electronics, Inc.
sales@thine.co.jp

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