THCS254_Rev.1.30_E

THCS254
IOHA:B 8B10B Serial Transceiver

1.

2.

Features

The THCS254 is a transceiver IC with serializer
and deserializer on a single chip that aggregates 20bit GPIO and 2-wire serial interface signals andconverts them into two pairs of differential signals fortransmission and reception.
The THCS254 has two modes: SYNC mode and
ASYNC mode. In SYNC mode, the uplink anddownlink high-speed transmission signals operate
synchronously, driven by the reference clock signal
from the primary chip side. In ASYNC mode, theuplink and downlink high-speed transmission signals
operate asynchronously, driven by the clock signals
from both the primary and secondary chips. The
reference clock can be selected from either theinternal OSC clock or the external input clock.



By accessing internal registers via the 2-wire serialinterface, the 20-bit GPIO direction and output buffer
type can be customized for each pin.
The 8B10B encoding and decoding used in the
THCS254 provides high robustness, DC balanced
signals, and easy connection to optical/wirelesscommunication devices.
The built-in adaptive equalizer allows for flexible
cable selection, and the CML driver with preemphasis allows for even longer cable transmissions.



Up to 20-bit GPIOs
Internal oscillator mode requires no external
clock signal input
Uplink and downlink synchronous mode with
one-sided reference clock drive
Uplink and downlink asynchronous mode withboth side reference clocks driven
Output buffer selectable between open-drain andpush-pull
2-wire serial interface fast mode can be bridgedStandby mode for low-power operation
Adaptive equalizer supports high-loss
transmission media
8B10B encoding/decoding
Digital noise filters can be set for input andoutputError detection and notification
External reference clock frequency: 15133.3MHz
Built-in spread spectrum clock generator
Single power supply operation: 1.7 V - 3.6 V
Operating ambient temperature range: -40°C to
85°C
Compliant with RoHS and REACH

3.

Overview















Block diagram
THCS254 (Primary Chip)

THCS254 (Secondary Chip)

REFEN

TXN
TXP

Rx
(Deserializer)
PLL

LDO

2-wire serial interface
SDA/SCL

LVCMOS I/O

RXN
RXP

RXP
RXN

Formatter2-wire serial interface
SDA/SCL

TXP
TXN

Tx
(Serializer)

GPIO D10/9･･D19/D0

Formatter

REFOUT

LVCMOS I/OGPIO D0/D19・・D9/D10

LDO

PLL
Tx
(Serializer)

SSCG

REFIN

Rx
(Deserializer)

OSC

GPIO D10/D9・・D0/D19
REFOUT
GPIO D19/0･･D10D0
REFIN

SSCG

OSC
REFEN
SYNCEN

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Contents
1.

Overview ......................................................................................................................................................... 1

2.

Features ........................................................................................................................................................... 1

3.

Block diagram ................................................................................................................................................. 1

4.

Pin configuration ............................................................................................................................................. 4

5.

Pin description ................................................................................................................................................. 5
5.1.

Pin setting and combination of chip mode .............................................................................................. 8

6.

Absolute maximum rating ............................................................................................................................... 9

7.

Recommended operatingconditions ................................................................................................................ 9

8.

Electrical characteristics ................................................................................................................................ 10
8.1.

Current consumption ............................................................................................................................. 10

8.2.

LVCMOS/Analog input DC specifications ........................................................................................... 12

8.3.

LVCMOS AC characteristics ................................................................................................................. 13

8.4.

CML DC characteristics ........................................................................................................................ 17

8.5.

CML AC characteristics ........................................................................................................................ 17

8.6.

2-wire serial interface DC/AC characteristics ....................................................................................... 21

9.

CML Line diagram ........................................................................................................................................ 22
9.1.

10.

CML input diagram ............................................................................................................................... 22
Function ..................................................................................................................................................... 23

10.1.

Function overview ............................................................................................................................. 23

10.2.

Power supply ..................................................................................................................................... 23

10.2.1.

Internal regulator output/input function (CAPOUT, CAPINA, CAPINP) .................................... 23

10.3.

Chip Operating state .......................................................................................................................... 24

10.4.

Chip operation mode ......................................................................................................................... 24

10.4.1.

Chip configuration ......................................................................................................................... 24

10.4.2.

Operating clock mode select.......................................................................................................... 25

10.4.3.

Operating clock select ................................................................................................................... 25

10.4.4.

Combination of operating modes .................................................................................................. 27

10.5.

REFIN frequency range and Internal OSC frequency ....................................................................... 30

10.6.

2-wire serial interface ........................................................................................................................ 31

10.6.1.

2-wire serial interface setting ........................................................................................................ 31

10.6.2.

Clock stretching ............................................................................................................................. 32

10.6.3.

Device Address .............................................................................................................................. 32

10.6.4.

2-wire serial controller / target register address space ................................................................... 33

10.6.5.

2-wire serial controller SCL frequency ......................................................................................... 33

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10.6.6.

2-wire serial interface watch dog timer setting.............................................................................. 33

10.6.7.

THCS254 internal register access protocol via 2-wire serial interface.......................................... 34

10.6.8.

2-wire serial expander ................................................................................................................... 41

10.7.

Direction of GPIO ............................................................................................................................. 42

10.8.

IO configuration ................................................................................................................................ 44

10.8.1.

I/O digital noise filter .................................................................................................................... 44

10.8.2.

LVCMOS Output buffer type configuration .................................................................................. 46

10.8.3.

5V tolerant IO ................................................................................................................................ 47

10.8.4.

LVSMOS Output drive strength setting......................................................................................... 47

10.8.5.

CML output swing voltage and pre-emphasis setting.................................................................... 47

10.9.

Clock configuration ........................................................................................................................... 48

10.9.1.

Sampling clock select .................................................................................................................... 48

10.9.2.

Clock edge select (RF_IN, RF_OUT) ........................................................................................... 49

10.10.

Spread spectrum clock generator and REFIN(pin) frequency ........................................................... 50

10.11.

PWM signal output function ............................................................................................................. 51

10.12.

CRC ................................................................................................................................................... 51

10.13.

Error detection and notification ......................................................................................................... 52

10.13.1.

READY signal ........................................................................................................................... 52

10.13.2.

INTN signal ............................................................................................................................... 52

10.14.

Standby mode: STANDBY(register)=1............................................................................................. 53

11.

Register map .............................................................................................................................................. 55

12.

Package...................................................................................................................................................... 59

13.

Reference land pattern ............................................................................................................................... 60

14.

Notices and Requests................................................................................................................................. 61

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SSEN

IDSEL0REFEN

RF_OUT/ OSCSEL1

OE

D19 / D0

D18 / D1

D17 / D2

D16 / D3

D15 / D4

VDD

Pin configuration

SYNCEN

4.

36

35

34

33

32

31

30

29

28

27

26

25

TEST2 37

24 D14 / D5

QFN-48AVDD 38

23 D13 / D6

CAPOUT 39

22 D12 / D7

RXP 40

21 D11 / D8

RXN 41

20 D10 / D9(TOP VIEW)
49EXPGND

CAPINA 42
TXN 4319 VDD
18 REFOUT

TXP 4417 REFIN

CAPINP 45

16 D9 / D10

INTN 46

15 D8 / D11

TEST1 47

14 D7 / D12

RESETN 48

13 D6 / D13
1

2

3

4

5

6

7

8

9

10

11

12

PSSEL

RF_IN / OSCSEL0

READY

SDA

SCL

D0 / D19

D1 / D18

D2 / D17 / PWMOUT

D3 / D16

D4 / D15

D5 / D14

VDD

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THCS254_Rev.1.30_E

5.

Pin description

Pin Name
TXP
TXN
RXP
RXN
RESETN

No.
44
43
40
41
48

Type
CO
CO
CI
CI
IL

PSSEL

1
IL

SYNCEN

36

IL

REFEN

33
ＩＬ

IDSEL034

RF_IN/
OSCSEL02ILIL

RF_OUT/OSECSEL1

32
IL

SDA
SCL
SSEN

4
5
35

BL
BL
IL

OE

31
IL

REFIN
REFOUT
READY

17
18
3

B
O
B

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Description
Differential P-ch output
Differential N-ch output
Differential P-ch input
Differential N-ch input
Chip reset
0: Chip reset
1: Chip operation
Chip mode select *Refer to SYNCEN
0: Primary chip mode
1: Secondary chip mode
Link mode selectWhen PSSEL=0 disable
When PSSEL=1 enable
0: AYNC mode
Driven by primary/secondary chip reference clocks
1: SYNC mode
Driven by primary chip reference clock
Reference clock select0: Internal oscillator clock
1: External reference clock
2-wire serial interface device address select*Refer to Table 12
RF_IN: Input clock edge select0: Falling edge
1: Rising edge
OSCSEL0: Internal oscillator clock select*Refer to Table 9
Output clock edge select0: Falling edge
1: Rising edge
OSCSEL1: Internal oscillator clock select*Refer to Table 9
SDA: SDA for 2-wire serial interface 0
SCL: SCL for 2-wire serial interface 0
Spread spectrum clock generator
0: SSCG PLL disable
1: SSCG PLL enable
Output enable
0: LVCMOS output Hi-Z
1: LVCMOS output enable
REFIN：External input clock
Pixel clock output
CML Link state
0: Unlock
1: Lock

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INTN

46
BO

D2/D17/PWMOUT

8BT

D4/D15, D5/D14,
D6/D13, D7/D12,
D8/D11, D9/D10
D10/D9, D11/D8,
D12/D7, D13/D6,
D14/D5, D15/D4,
D0/D19, D1/D18
D3/D16, D16/D3,
D17/D2, D18/D1,
D19/D0TEST1TEST2CAPOUT
CAPINA
CAPINP
VDD
AVDD
EXPGND10, 11,
13, 14,15, 16,20, 21,
22, 23,24, 26,6, 7
9, 27,
28, 29,
30
47
37
39
42
45
12, 19,
25
38
65

B

BT
IL
AI
PWR
PWR
PWR
PWR
PWR
GND

Interrupt output *When READY=1
0: Error occurred
1: (Pull-up) : No Error
D2: Primary chip mode data input/output
D17: Secondary chip mode data input/output
PWMOUT: PWM output
Primary chip mode data input and output / Secondary
chip mode data input and output
Left side of "/" is in primary chip mode
Right side of "/" is in secondary chip mode
Primary chip mode data input and output / Secondary
chip mode data input and output
Left side of "/" is in primary chip mode
Right side of "/" is in primary chip mode
Shall be tied to Ground
Shall be tied to Ground
Decoupling capacitor Pin, 1.2V output
1.2V Analog power supply input
1.2V Analog power supply input
1.7-3.6V Digital power supply input for LVCMOS I/O
1.7-3.6V Analog power supply input for on-chip regulator
Exposed Pad Ground. Must be tied to the PCB groundplane through an array of via holes

Pin type definition
Analog Buffer
CO: CML Output buffer
CI: CML Input buffer
AI: Analog Input buffer
LVCMOS buffer
IL: Low speed schmitt trigger LVCMOS Input buffer
B: LVCMOS Bi-directional buffer
BO: Open-drain LVCMOS Bi-directional buffer
BL: Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer
BT: Low speed 5V tolerant LVCMOS Bi-directional bufferPower/Ground
PWR: Power supply
GND : Ground

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THCS254_Rev.1.30_E
Table 1 Primary chip mode pin sharing
Pin number

1
33
register2
32
8Primary chip /Secondary chip
Sampling clock

PSSEL
REFEN
PWMEN
RF_IN/OSCSEL0
RF_OUT/OSCSEL1
D2/D17/PWMOUT

Primary chip mode
Internal OSC00{0}
OSCSEL0
OSCSEL1
D2/D1700{1}
OSCSEL0
OSCSEL1PWMOUT

External input

0
1
{0}
RF_IN
RF_OUTD2/D17

0
1
{1}
RF_IN
RF_OUTPWMOUT

Table 2 Secondary chip mode pin sharing
Pin number

1
33
register2
32
8Primary chip /Secondary chip
Sampling clock

PSSEL
REFEN
PWMEN
RF_IN/OSCSEL0
RF_OUT/OSCSEL1
D2/D17/PWMOUT

Secondary chip mode
Internal OSC

10{0}
OSCSEL0
OSCSEL1
D2/D171
0{1}
OSCSEL0
OSCSEL1PWMOUT

External input

1
1
{0}
RF_IN
RF_OUTD2/D17

1
1
{1}
RF_IN
RF_OUTPWMOUT

Setting value with brace (ex. {0}, {1}) requires register setting by 2-wire serial interface.
See following definition in each Tables.
Setting by Pin
Setting by register

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5.1.

Pin setting and combination of chip mode

The following is a list of modes that can be combined between Primary chip and Secondary chip.
Table 3 Primary Chip / Secondary Chip list of pair combination
PSSEL=0 : Primary chip mode（Pri）
REFEN

PSSEL=1 Secondary chip mode
(Sec)

0

1

SYNCEN

0

REFEN

0

SYNCEN

0

Pri

REFEN

1

I2C_T

SYNCEN

1

REFEN

-

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6.

Absolute maximum rating

Parameter
Supply voltage (VDD,AVDD)LVCMOS input voltage
LVCMOS output voltage
5V tolerant Bi-directional buffer input voltage
5V tolerant Bi-directional buffer output voltage
Open-drain output voltage
CML receiver input voltage
CML transmitter output voltage
Output current
Storage temperature
Junction temperature
Reflow peak temperature/time
θja (Junction to Ambient)Ψjt (Junction to Top of package)
Maximum power dissipation @+25°C

Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-50
-55
-

Typ
Max
4.0
VDD+0.3
VDD+0.3
VDD+2.5
VDD+2.5
4.0
CAPINA+0.3
CAPINP+0.3
50
125
125
260/1029.1 [*1]
1.1 [*1]
3.4[*1]

Unit
V
V
V
V
V
V
V
V
mA
°C
°C
°C/sec°C/W°C/W
W“Absolute maximum ratings” are those values beyond which the safety of the device cannot be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics” specify conditions for device operation.
*1: Thermal parameters are not guaranteed value. This value assists board and system level designers.

7.

Recommended operatingconditions
Parameter
Supply voltage (VDD,AVDD)
Operating ambient temperature

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Min
1.7
-40

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Typ
-

Max
3.6
85

Unit
V
°C

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THCS254_Rev.1.30_E

8.

Electrical characteristics

8.1.

Current consumption
SymbolIdd_w1

Idd_w2

Idd_w3

Idd_w4

Idd_w5

Parameter
Normal mode current
Primary chip
20bit Input (Full toggle40MHz)
REFIN mode(80MHz)
Normal mode current
Secondary chip
20bit Output (Fulltoggle40MHz)
REFIN=80MHz
Normal mode current
Primary chip
10bit Input (Full toggle40MHz)
10bit Output (Fulltoggle40MHz)
REFIN=80MHz
Normal mode current
Secondary chip
10bit Input (Full toggle40MHz)
10bit Output (Fulltoggle40MHz)
REFIN=80MHz
Normal mode current
Primary chip
10bitInput (Full toggle1MHz)
10bitOutput (Full toggle1MHz)
REFIN=80MHz
Normal mode current
Secondary chip
10bitInput (Full toggle20MHz)
10bitOutput (Fulltoggle20MHz)
REFIN=80MHz
Normal mode current
Primary chip
10bitInput (Full toggle1MHz)
10bitOutput (Full toggle1MHz)
REFIN=80MHz
Normal mode current
Secondary chip
10bitInput (Full toggle1MHz)
10bitOutput (Full toggle1MHz)
REFIN=40MHz
Normal mode current
Primary chip
10bit Input (Fulltoggle66.67MHz)
10bit Output (Fulltoggle66.67MHz)
REFIN=133.34MHz
Normal mode current
Secondary chip
10bit Input (Fulltoggle66.67MHz)
10bit Output (Fulltoggle66.67MHz)
REFIN=133.34MHz

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Type

Conditions

Min

Typ

Max

Unit

-

mA

-

mA

-

mA

-

mA

-

mA

116
PWR

AVDD=3.3V
VDD=3.3V

166

127

PWR

AVDD=3.3V
VDD=3.3V

-

127

114

PWR

AVDD=3.3V
VDD=3.3V

114

76
PWR

AVDD=3.3V
VDD=3.3V

76

166

PWR

AVDD=3.3V
VDD=3.3V

-

166

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Idd_w6

Idd_w7

Standby mode current
Primary chip
8bit Input(Full toggle6.25kHz)
Standby mode current
Secondary chip
8bit Output(Fulltoggle6.25kHz)
Standby mode current
Primary chip
8bit Output(Fulltoggle6.25kHz)
Standby mode current
Secondary chip
8bit Input(Full toggle6.25kHz)

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7PWR

AVDD=3.3V
VDD=3.3V

-

-

mA

-

mA

7

7
PWR

AVDD=3.3V
VDD=3.3V7

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8.2.

LVCMOS/Analog input DC specifications
SymbolParameter

Type

Conditions

Min
0.65
VDD
0.70
VDD
2.0
0.70
VDD

Typ

Max

Unit

-

VDD

V

-

VDD

V

-

VDD

V

-

VDD

V

1.7V≦VDD<2.0V

0-

2.0V≦VDD<3.0V0-

3.0V≦VDD≦3.6V

0

-

IL,BL

1.7V≦VDD≦3.6V

0

-

AI

1.7V≦VDD≦3.6V

0-

VDD 0.30

-

VDD

V

VDD 0.45

-

VDD

V

VDD 0.45

-

VDD

V

0

-

0.30

V

0

-

0.45

V

0

-

0.45

V

0

-

0.27

V

-10
-10

-

10
10

uA
uA

-10

-

10

uA

-10

-

10

uA

1.7V≦VDD<2.0V
VIH

High level input voltage

B,BT,
BO

2.0V≦VDD<3.0V
3.0V≦VDD≦3.6V

IL,BL

B,BT,
BO
VIL

VOH

VOL

Low level input voltage

High level output voltage

Low level output voltage

B,BT,
BL

B,BT,
BL

BO
IIH
IIL

1.7V≦VDD≦3.6V

1.7V≦VDD<2.0V
TTLDRV(register)={0}IOH=-2mA
1.7V≦VDD<2.0V
TTLDRV(register)={1}IOH=-4mA
2.0V≦VDD≦3.6V
IOH=-4mA
1.7V≦VDD<2.0V
TTLDRV(register)={0}IOL=2mA
1.7V≦VDD<2.0V
TTLDRV(register)={1}
IOL=4mA
2.0V≦VDD≦3.6V
IOL=4mA
1.7V≦VDD≦3.6V
IOL=2mA
VIN=VDD
VIN=0V

Input leak current HighIL
Input leak current Low
IL
Output leak current High in
B,BT,
IOZH
VIN=VDD
Hi-Z
BL,BO
Output leak current Low in
B,BT,
IOZL
VIN=0V
Hi-Z
BL,BO
AI: Analog Input buffer
IL: Low speed schmitt trigger LVCMOS Input buffer
B: LVCMOS Bi-directional buffer
BO: Open-drain LVCMOS Bi-directional buffer
BL: Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer
BT: Low speed 5V tolerant LVCMOS Bi-directional buffer

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0.35
VDD
0.30
VDD
0.8
0.30
VDD
0.15
VDD

V
V
V
V
V

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THCS254_Rev.1.30_E
8.3.

LVCMOS AC characteristics

SymbolParameter

tRSN

tTCIP

tTCH
tTCL

Conditions

RESETN low time-

REFIN period

1.7V≦VDD≦2.25V and
TTLDRV(register)={0}2.25V≦VDD≦3.6V or
TTLDRV(register)={1}

REFIN High time
REFIN Low time

Pin type: B

1.7V≦VDD≦3.6V
1.7V≦VDD<2.25V
2.25V≦VDD≦2.75V
2.75V<VDD≦3.6V

Min

Typ

Max

Unit

3

-

-

us

10

-

66.6

ns

7.5

-

66.6

ns

0.35
tTCIP
0.35
tTCIP
2.0
25
2.5
2.0

-

0.65
tTCIP
0.65
tTCIP
-

0.5 tTCIP
0.5 tTCIP

ns
ns
ns
ns
ns
ns

tTS

Data input setup to REFIN

Pin type:
BTtTH

Data input hold to REFIN

-

1.0

-

-

ns

tTPD

Power on to RESETN high
delay

-

0

-

-

ns

41.67

50

62.5

ns

20.84

25

31.25

ns

10.42

12.5

15.62

ns

-

tOSC

-

ns

REFEN(pin)=1

-

tTCIP

-

ns

REFEN(pin)=0

10.42

12.5

15.62

ns

36.2
tDCP
46
tDCP
53.4
tDCP
68.1
tDCP
-

tTCIP

ns

tDCP

61.3
tDCP
73.7
tDCP
82.1
tDCP
100.5
tDCP
-

tOSC

Internal oscillator clock
periodtDCP

Data sampling clock period

tFLTCK

Noise filter clock period

OSCSEL1(pin)=0
OSCSEL0(pin)=0
OSCSEL1(pin)=1
OSCSEL0(pin)=0
OSCSEL1(pin)=1
OSCSEL0(pin)=1
REFEN(pin)=0tRCP

REFOUT period

REFEN(pin)=1
Digital noise filter (in & out) disable
Refer to Table 19,Table 20
Digital noise filter (in & out) 4 taps
Refer to Table 19,Table 20
Digital noise filter (in & out) 8 taps
Refer to Table 19,Table 20
Digital noise filter (in & out) 16 taps
Refer to Table 19,Table 20-tRCH

REFOUT high time--

0.5 tDCP

-

ns

tRCL

REFOUT low time--

0.5 tDCP

-

ns

tDOUT

Data output period

-

-

tDCP

-

ns

tRS

Data output setup to
REFOUT-

0.45 tDCP- 0.675

-

-

ns

tRH

Data output hold to
REFOUT-

0.45 tDCP- 2.175

-

-

ns

-

-

-

1

ms

-

0

-

10

ms

-

0

-

10

ms

Input data to output data
delay
tTCD

tRRDY
tNRDY
tSRDY

Note : Transmission delay
between primary andsecondary chips is notincluded.

RESETN high to READY
high delay
STANDBY low to READY
high delay
STANDBY high to READY
high delay

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ns
ns
ns
ns
ns

THCS254_Rev.1.30_E
Clock , TTLDRV(register)={0}tTLH

Clock and data output low
to high transition time

Data(Pin type=B) ,TTLDRV(register)={0}
Data(Pin type=BT) ,TTLDRV(register)={0}
Clock , TTLDRV(register)={1}
Data(Pin type=B) ,TTLDRV(register)={1}
Data(Pin type=BT) ,TTLDRV(register)={1}
Clock , TTLDRV(register)={0}tTHLClock and data output highto low transition time

Data(Pin type=B) ,TTLDRV(register)={0}
Data(Pin type=BT) ,TTLDRV(register)={0}
Clock , TTLDRV(register)={1}
Data(Pin type=B) ,TTLDRV(register)={1}
Data(Pin type=BT) ,TTLDRV(register)={1}

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-

-

2.1

ns

-

-

4.2

ns

-

-

5.9

ns

-

-

1.1

ns

-

-

2.3

ns

-

-

3.0

ns

-

-

2.1

ns

-

-

4.3

ns

-

-

6.1

ns

-

-

1.1

ns

-

-

2.2

ns

-

-

3.0

ns

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THCS254_Rev.1.30_E
tTCIP
tTCH(RF=0)tTCL(RF=0)tTCL(RF=1)tTCH(RF=1)
RF=0

REFIN

VDD/2

VDD/2

VDD/2

RF=1
tTS

D0-D31

tTH

VDD/2

VDD/2

RD = 10Ω
Test Point

CL = 8pF

tRCP
tRCH(RF=0)tRCL(RF=0)tRCL(RF=1)tRCH(RF=1)
RF=0

REFOUT

VDD/2

VDD/2

VDD/2

RF=1
tRS

D31-D0

tRH

VDD/2

VDD/2

tDOUT

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THCS254_Rev.1.30_E

Primary chip mode Input
D0-D19DATA1Secondary chip mode Output
D19-D0

DATA2

DATA1

DATA3

DATA2

DATA3

tTCD
Secondary chip mode Input
D19-D0DATA1Primary chip mode Output
D0-D19

DATA2

DATA1

DATA3

DATA2

DATA3

tTCD

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THCS254_Rev.1.30_E
8.4.

CML DC characteristics

SymbolParameter

VTOD

CML differential output peak
to peak signal

PRE

CML pre-emphasis level

CML common mode output
voltage

VTOC

ITOH

CML output leak current
high

ITOS

CML output short current
CML differential input highthreshold
CML differential input low
threshold

VRTH
VRTL
IRIH

CML input leak current highIRIL

CML input short current low

IRRIH
IRRIL

CML input current high
CML input current low
CML differential input
resistance

RRIN

8.5.

Conditions
CMLDRV[1:0](register)={00}
CMLDRV[1:0](register)={01}(default)
CMLDRV[1:0](register)={10}PRE(register)={0} (default)PRE(register)={1}
CMLDRV[1:0](register)={00}PRE(register)={1}
CMLDRV[1:0](register)={01}

Min
266

Typ
400

Max
534

Unit
mVpp

400

600

800

mVpp

600
-

800
0

1000
-

mVpp
dB

-

6

-

dB

-

3.52

-

dB

PRE(register)={0} (default)-

1200 - 0.5
VTOD

-

mV

-

1200 - VTOD

-

mV

-

1200 - 0.75
VTOD

-

mV

-30

-

30

uA

-80

-

-

mA

-

-

-

50

mV

-

-50

-

-

mV

-10

-

10

uA

-10

-

10

uA

-6

-

2
-

mA
mA

80

100

120

Ω

Min

Typ

Max

Unit

-

50

-

150

ps

-

-

-

1
200

ms
ns

-

-

-

100

us

-

250

tDCP÷30
-

2222

ns
ps

PRE(register)={1}
CMLDRV[1:0](register)={00}PRE(register)={1}
CMLDRV[1:0](register)={01}RESETN(pin)=0
TXP/N(pin)=CAPINA(pin)RESETN(pin)=0
TXP/N(pin)=0V

RESETN(pin)=0
RXP/N(pin)=CAPINA(pin)RESETN(pin)=0
RXP/N(pin)=0V
RXP/N(pin)=CAPINA(pin)RXP/N(pin)=0V-

CML AC characteristics

SymboltTRF
tTPLL0tTPLL1
tTNP0
tTBIT
tRBIT

Parameter
CML output rise and fall time (20%80%)
RESETN=H to CML output delay
RESETN=L to CML output high fix
READY=L to training pattern output
delay
Output unit interval
Input unit interval

Copyright©2024 THine Electronics, Inc.

Conditions

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THCS254_Rev.1.30_E
75～200nF50Ω

75～200nF

50Ω

80%

80%

TXP

TXN

< 5mm

Vdiff = (TXP) - (TXN)
20%

20%

tTRF

tTRF

THCS254

THCS254

CAPINP

50Ω

50Ω

C=75～
200nF
TXP

C=75～
200nF
RXP

TXN

CML Receiver

RXN
Zdiff=100ohm
50Ω

50Ω

CML Transmitter

Vbias
GND

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THCS254_Rev.1.30_E
ASYNC mode
Training pattern output from the primary chip requires RESET=1 and REFIN frequency*1 input.
Training pattern output from the secondary chip requires RESET=1 and REFIN frequency*1 input as well as
training pattern receive from the primary chip.
*1: In internal oscillator clock mode with REFEN=0, RESET=1 only.
Primary Chip
VDD

REFIN

GPIO Inputs
D0-D19RESETNGPIO DatatTPDtTPLL0

tTNP1

tRRDY

READY

Training
pattern

TXP/N

GPIO Outputs
D19-D0Normalpattern

Training
pattern

Low

Valid GPIO

Hold

Low

Valid GPIO

Secondary Chip
VDD

REFIN

GPIO Inputs
D0-D19RESETNGPIO DatatTPDtTPLL0

tRRDY

READY

Training
pattern

TXP/N

GPIO Outputs
D19-D0tTNP1

Low

Copyright©2024 THine Electronics, Inc.

Normalpattern

Training
pattern

Valid GPIO

19/61

Hold

Valid GPIO

Low

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THCS254_Rev.1.30_E
SYNC mode
Primary Chip
VDD

REFIN

GPIO Inputs
D0-D19RESETNGPIO DatatTPDtTPLL0

tTNP1

tRRDY

READY

Training
pattern

TXP/N

GPIO Outputs
D19-D0Normalpattern

Low

Training
pattern

Valid GPIO

Hold

Low

Valid GPIO

Secondary Chip
VDD

GPIO Inputs
D0-D19RESETNGPIO DatatTPDtTPLL0

tRRDY

READY

Training
pattern

TXP/N

GPIO Outputs
D19-D0tTNP1

Low

Copyright©2024 THine Electronics, Inc.

Normalpattern

Training
pattern

Valid GPIO

20/61

Hold

Valid GPIO

Low

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THCS254_Rev.1.30_E
8.6.

2-wire serial interface DC/AC characteristics

Symbol
VIL
VIH

Parameter
Low level input voltage
High level input voltage

VOL

Low level output voltage

Ii
fSCL

Input current each I/O pin
SCL clock frequency
Setup time (repeated) START
condition
Hold time (repeated) START
condition

tSU;STAtHD;STAtLOW

Low period of the SCL clocktHIGH

High period of the SCL clock

tHD;DAT

Data hold time

tSU;DAT

Data setup time

tSU;STO

Setup time for STOP condition

tBUF
tr
tf

Bus free time between a STOP
and START condition
Rise time of both SDA and SCL
signals
Fall time of both SDA and SCL
signals

Condition
1.7V≦VDD≦3.6V
IOL=2mA
fSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHzfSCL>400kHzfSCL≦400kHz-Min
00.7 VDD

Typ-Max
0.30 VDD
-

Unit
V
V

0.00

-

0.26

V

-10
0
0.26
0.6
0.46
0.8
0.5
1.3
0.26
0.6
0
50
100
0.26
0.6
0.5
1.3

-

+10
1000
-

uA
kHz
us
us
us
us
us
us
us
us
us
ns
ns
us
us
us
us

-

-

300

ns

-

-

300

ns

-

SDA
tLOW

tSU;DATtHD;STAtBUF

SCLtHD;STA

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tHD;DAT tHIGH

tSU;STA

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tSU;STO

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THCS254_Rev.1.30_E

9.

CML Line diagram

9.1.

CML input diagram

1UI=1/(serial data rate)

B
Y

C

A

D

E

F

X
X=0 UI

Copyright©2024 THine Electronics, Inc.

Y=0mV

X=1 UI

A
B
C
D

X[UI]
0.25
0.3
0.7
0.75

Y[mV]
0
50
50
0

E

0.7

-50

F

0.3

-50

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THCS254_Rev.1.30_E

10. Function
10.1. Function overview
The THCS254 integrates a high-speed CML serializer and deserializer on a single chip. It is capable ofaggregating and de-aggregating up to 20-bit parallel GPIO signals and a 2-wire serial interface with full-duplex
communication using two pairs of differential signals with a minimum of external components.
standby mode supports up to 8-bit low-speed GPIO signals and 2-wire serial interface.

Low-power

In addition, the internal

oscillator mode does not require an external clock generator such as a crystal oscillator. Two THCS254s (onepair) can be used to monitor and control peripheral devices via a 2-wire serial interface or GPIO. In the event of
a communication error, the GPIO signal is held and an interrupt signal is used to notify the user.

10.2. Power supply
10.2.1. Internal regulator output/input function (CAPOUT, CAPINA, CAPINP)
The internal regulator generates 1.2V (CAPOUT) for internal use only. Do not use for other external loads.
CAPOUT should be bypassed to GND with 10uF as a power supply pin; AVDD should be bypassed to GND with
10uF or more.
CAPINP and CAPINA supply the reference voltage for the internal analog circuitry. To reduce high frequency
noise, CAPINP/CAPINA should be bypassed to GND with 0.1uF as a power supply pin. CAPOUT, CAPINA and
CAPINP should be wired as shown in the figure below.

THCS254
10uF

Power
SupplyAVDDCAPOUT

>10uF

0.1uF
CAPINA
VDD

0.1uF
CAPINP

Figure 1 Connection of CAPOUT, CAPINA, CAPINP and decoupling capacitor

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THCS254_Rev.1.30_E
10.3. Chip Operating state
Basic operating states related to power consumption of the THCS254, such as reset, OE, and standby.
Table 4 Operating mode setting
Operating modeRESETRESETN(pin)

Setting
STANDBY(register)

OE *1
(pin)

0

-

-

1

{0}

0

1

{0}

1

1

{1}

0

1

{1}

1

Normal operation

Standby operation

Description
Chip reset
2-wire serial interface disable
All outputs are Hi-Z
Normal operation
2-wire serial interface enable
All outputs are Hi-Z
Normal operation
2-wire serial interface enable
GPIO normal operation
Low power consumption/low frequency
sampling rate operation
2-wire serial interface enable
GPIO 8bit Hi-Z
Low power consumption/low frequency
sampling rate operation
2-wire serial interface enable
GPIO 8bit low speed communication
Enable*1 When OVERRIDE_OEN(register) = {1} is selected, the OE(pin) state is disabled.

10.4. Chip operation mode
10.4.1. Chip configuration
The THCS254 has two modes, Primary chip mode and Secondary chip mode, which are selected by the PSSEL
pin. The THCS254 is connected and used in a pair of Primary chip mode t and Secondary chip mode.
Table 5 Primary chip and Secondary chip selection
PSSEL (pin)01Copyright©2024 THine Electronics, Inc.

Description
Primary chip mode
Secondary chip mode

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THCS254_Rev.1.30_E
10.4.2. Operating clock mode selectThe THCS254 selects synchronous or asynchronous operation of downstream and upstream by the SYNCEN pin
selection in the secondary chip mode.
Synchronous mode
The primary chip samples data by its own clock. The secondary chip samples data using the CDR (Clock Data
Recovery) clock generated by the deserializer, and the downstream and upstream operate synchronously.
Asynchronous mode
Data sampling is performed with the clocks of both Primary chip and Secondary chip, and downstream andupstream operate asynchronously.
Table 6 Downstream / Upstream synchronous setting
SYNCEN(pin) of Secondary chip
0
1

Description
Asynchronous mode : Operates at both clocks
Synchronous mode : Operates at the clock of the
primary chip

10.4.3. Operating clock selectTHCS254 allows selection of the clock used to input data sampling and drive the serializer/deserializer.
Table 7 Operating clock select
REFEN(pin)01

Description
Internal Oscillator Clock Mode：20M/40M/80MHz
External reference clock mode：15-133MHz

Figure 2 Clock Tree diagram of Primary chip

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Figure 3 Clock Tree diagram of Secondary chip

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THCS254_Rev.1.30_E
10.4.4. Combination of operating modes
Transmit operation of the THCS254 is determined by the combination of the PSSEL, REFEN, and SYNCEN pins.
Asynchronous mode(SYNCEN=0 of secondary chip)／External reference clock mode(REFEN=1)
Data sampling and driven by the REFIN input of each primary chip/secondary chip.
Different frequencies can be input to the Primary chip and Secondary chip.
Downstream and upstream can be taken and output synchronized to their respective REFIN inputs.
Primary chipCML

REFOUT
I/O

Tx

CML
Rx

Formatter

I/O

REFOUT

Formatter

D0/D192-wire serial I/F

2-wire serial I/F

Formatter

Formatter

REFIN

D19/D0SCL/SDA

PLL

Rx

OSC

Secondary chip

Tx

REFEN=1
SYNCEN=0

PLL

D19/D0

D0/D19REFIN
OSC

SCL/SDASYNCEN=0
REFEN=1

Figure 4 ASYNC_MODE / Ext.REF_MODE Block diagram
Asynchronous mode(SYNCEN=0 of secondary chip)／Internal oscillator clock mode(REFEN=0)
Data sampling and driven by the internal oscillator clock of each primary chip/secondary chip.
Selectable from 20/40/80MHz by OSCSEL [1:0] pin setting.
Different frequencies can be selected for the internal oscillator of the Primary chip/Secondary chip.
All input data is asynchronous acquisition because of sampling by the internal oscillator. Output data is
synchronized with REFOUT.
Primary chip

REFOUT

Formatter

REFOUT
I/O

CML

Tx

Formatter

D19/D0CML

I/O

D0/D19SCL/SDA2-wire serial I/F

2-wire serial I/F

PLL

Formatter

Formatter

REFIN

Secondary chip
PLL

Rx

OSC

Rx

SYNCEN=0

Tx

REFEN=0

D19/D0

D0/D19REFIN
OSC

SCL/SDASYNCEN=0
REFEN=0

Figure 5 ASYNC_MODE / Int.OSC_MODE Block diagram

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THCS254_Rev.1.30_E
Asynchronous mode(SYNCEN=0 of secondary chip)／External reference clock mode(REFEN=1) andInternal oscillator clock mode(REFEN=0)
Data sampling and driven by the REFIN input of either the Primary chip or the Secondary chip.
Either the primary chip/secondary chip is driven and sampled by the internal oscillator.
Selectable from 20/40/80MHz by OSCSEL [1:0] pin setting.
The external reference clock drive side can be synchronized with the REFIN input for take-up and output.
The internal oscillator drive side is all asynchronous acquisition. Output data is synchronized with REFOUT.
Primary chip

CML

I/O

REFOUT

CML

Formatter

REFOUT

Tx

Formatter

I/O

D0/D192-wire serial I/F
Formatter

Formatter

REFIN

D19/D0SCL/SDA

PLL

Rx

OSC

Secondary chipRx

SYNCEN=0

Tx

REFEN=1

2-wire serial I/F

PLL

D19/D0

D0/D19REFIN
OSC

SCL/SDASYNCEN=0
REFEN=0

Figure 6 ASYNC_MODE / Ext.REF_MODE & Int.OSC_MODE Block diagram
Synchronous mode(SYNCEN=1 of secondary chip)／External reference clock mode(REFEN=1)
Driven and data sampling only by REFIN to the primary chip. (Input to REFIN of the secondary chip is prohibited)
Secondary chip uses the clock regenerated by the receiver for data sampling and driving the transmitter.
Downlink take-up and output synchronized with REFIN input.
The uplink is asynchronous acquisition due to sampling with the CDR-generated clock.
Primary chip

Formatter

REFOUT
I/O

CML

Tx

REFOUT

Rx

Formatter

D19/D0CML

I/O

D0/D192-wire serial I/F

Formatter

Formatter

REFIN

SCL/SDA

PLL

Rx

OSC

Secondary chip

Tx

REFEN=1
SYNCEN=x

D19/D0

D0/D19REFIN
SYNCEN=1

2-wire serial I/F

PLL

OSC

SCL/SDAREFEN=1

Figure 7 SYNC_MODE / Ext.REF_MODE Block diagram

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THCS254_Rev.1.30_E
Synchronous mode(SYNCEN=1 of secondary chip)／Internal oscillator clock mode(REFEN=0)
It is sampled and driven by the built-in oscillator of the primary chip.
Selectable from 20/40/80MHz by OSCSEL [1:0] pin setting.
Secondary chip uses the clock regenerated by the receiver for data sampling and driving the transmitter.
All input data is asynchronous acquisition because of sampling by the internal oscillator. Output data is
synchronized with REFOUT.
Primary chip

REFOUT

Formatter

REFOUT
I/O

CML

Tx

Formatter

D19/D0CML

I/O

D0/D192-wire serial I/F

2-wire serial I/F

PLL

Formatter

Formatter

REFIN

SCL/SDA

PLL

Rx

OSC

Secondary chipRx

SYNCEN=x

Tx

REFEN=0

D19/D0

D0/D19REFIN
OSC

SCL/SDASYNCEN=1
REFEN=1

Figure 8 SYNC_MODE / Int.OSC_MODE Block diagram

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THCS254_Rev.1.30_E
10.5. REFIN frequency range and Internal OSC frequency
The external reference clock frequency in each byte mode with REFEN (pin) = 1 and the operating frequency
with OSCSEL [1:0] (pin) setting when REFEN (pin) = 0 are shown below.
Table 8 External reference clock frequency range
REFIN frequency range
15~133MHz

CML data rate
450Mbps~4Gbps

Table 9 DATAWIDTH and OSCSEL[1:0] select
RF_OUT/OSCSEL1 (pin)RF_IN/OSCSEL0 (pin)

0
0
1
1

0
1
0
1

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OSC
frequency
20MHz±20%

CML data rate
480Mbps~720Mbps

40MHz±20%

960Mbps~1440Mbps

80MHz±20%

1920Mbps~2880Mbps

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THCS254_Rev.1.30_E
10.6. 2-wire serial interface
10.6.1. 2-wire serial interface setting
2-wire serial interface of the THCS254 is always enabled. The relationship between the settings, primarychip/secondary chip and I2C mode is shown below.

2-wire serial controller/target can be selected independently from Primary chip / Secondary chip mode settings.
Table 10 2-wire serial interface controller / target selectPSSEL(pin)0
1

I2C mode
TargetController

Accessible range of I2C.
Table 11 2-wire serial interface accessible range
Primary chip register

Secondary chip register

Remote device register

Accessible

accessible

accessible

Unaccessible

Unaccessible

accessible

Figure 9 2-wire serial interface accessible range

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THCS254_Rev.1.30_E
10.6.2. Clock stretching
2-wire serial controller device connected to the THCS254 must support clock stretching.
Access from the 2-wire serial target (control device side) to the 2-wire serial controller (remote device side) of the
THCS254 involves a clock stretch every 8 bits.
Clock stretching period:(Internal latency of THCS254) + (WRITE time to remote device) + (Response time of remote device
ACK/READ data) [ns](tDCP x 70 + 350) + (I2C controller bit rate* x 8) + Response time of remote device [ns]*Can be set by I2CPERIOD [1:0] register (Default 100kHz)
Effective I2C frequency = 1 / (Clock stretching period +SCL period)
SDA

A ・・・・

2-wire-Write

Control device side
THCS254 2-wire serial target
SCL

Clock stretchingSDA

2-wire-Write・・・・

A ・・・・

Remote Device Side
THCS254 2-wire serial control
・・・・

SCL

Figure 10 Clock stretching of I2C communication

10.6.3. Device Address
To access the THCS254 registers, IDSEL0 (pin) must be set and the device address must be selected. The device
address must be set only on the 2-wire serial target set to Primary chip mode. The device address set on IDSEL0
cannot be used as the device address of a remote device.
Table 12 Device ID setting
Setting
IDSEL0(pin)
01

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Device address [6:0](HEX) / (BIN)
0x0B / 000_1011
0x34 / 011_0100

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THCS254_Rev.1.30_E
10.6.4. 2-wire serial controller / target register address space
The THCS254 identifies the 2-wire serial target (on the control device side) and the 2-wire serial controller (onthe remote device side). Burst access across the boundary between the 2-wire serial target (control device side)and the 2-wire serial controller (remote device side) is prohibited.
Table 13 Register address configuration
Register address

Description

0x00 - 0x7F
0x80 - 0xFF

2-wire serial target (Control device side)
2-wire serial controller (Remote device side)
Register

THCS254 I2C Target(Control device side)

0x00
0x7F

Same
Device ID

0x80
・
・
・

THCS254 I2C Controller(Remote device side)

Address・・・

PSSEL = 00xFF

PSSEL = 1

Figure 11 Register address mapping

10.6.5. 2-wire serial controller SCL frequency
2-wire serial controller chip with CTSEL_I2C=1 can set the SCL frequency in the register. The default is 100 kbps.
Table 14 2-wire serial bitrate setting
Register Address

Name

Description

0x26

I2CPERIOD

2-wire serial controller bit rate setting (SCL）
10,000 / I2CPERIOD kbps

10.6.6. 2-wire serial interface watch dog timer setting
The 2-wire serial interface of the THCS254 has a watchdog timer function that resets the internal state if
communication stops for some reason, such as an external factor, and the internal state continues to not advance.
The time until the watchdog timer is activated can be set in an internal register.
Table 15 2-wire serial interface watch Dog Timer setting
Register Address

bit

Name

Description

7:4

I2C_WDT_STBY

3:0

I2C_WDT

0x28

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2-wire serial watch dog timer (standby)
0:Disable／50ms～1650s
2-wire serial watch dog timer (Normal mode)
Controller 0:Disable／0.0123ms - 403ms
Target 0:Disable／0.0246ms - 806ms

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THCS254_Rev.1.30_E
10.6.7. THCS254 internal register access protocol via 2-wire serial interface
The THCS254 2-wire serial interface protocol includes the following three types: (1) 2-wire serial target register
access, (2) 2-wire serial controller access, and (3) 2-wire serial remote device access.

(1) 2-wire serial target register accessFigure 12 2-wire serial target register accessS

Start condition

R

Read command

P

Stop condition

W

Write command

A

ACK

Access from 2-wire serial Controller of Control Device

A

NACK

Access from 2-wire serial Target of Remote Device

Repeated start condition

Access from THCS254

Sr

Single Byte write
Control Device SideS

THCS254
Device Address

Register
Address

A

W

A

A

P

Write Data
1

A

Write Data

IDLE

Remote Device Side

Burst write(0x0B / 0x34)

Control Device SideS

THCS254
Device Address(0x00-0x7F)

W

A

Register
Address

A・・・A

Write Data
#

A

P

IDLE

Remote Device Side

Figure 13-1 2-wire serial target register access protocol

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THCS254_Rev.1.30_E
Single Byte read with repeated start command(0x0B / 0x34)

Control Device SideS

THCS254
Device Address

Returns data at the address indicated by the address pointer (0x00-0x7F)(0x00-0x7F)

W

Register
Address

A

A

Sr

THCS254
Device Address

R

A

Sr

THCS254
Device Address

R

A

Read Data

A

P

IDLE

Remote Device Side

Burst read with repeated start command(0x0B / 0x34)

Control Device SideS

Returns data at the address indicated by the address pointer (0x00-0x7F)(0x00-0x7F)

THCS254
Device Address

W

Register
AddressA

A

Read Data 1

A

Read Data 2

A

・・・

A

Read Data #

A

P

A

P

IDLE

Remote Device Side

Burst read with stop and start command(0x0B / 0x34)

Control Device Side

Returns data at the address indicated by the address pointer (0x00-0x7F)(0x00-0x7F)

THCS254
Device Address

S

Register
Address

A

W

A

P

THCS254
Device Address

S

R

A

Read Data 1

A

Read Data 2

A

・・・

A

Read Data #IDLE

Remote Device Side

Single Byte read without repeated start condition
Returns data at the address indicated by the address pointer (0x00-0x7F)(0x0B / 0x34)

Control Device SideS

THCS254
Device Address

R

A

Read Data1

A

P

IDLE

Remote Device Side

Burst read without repeated start condition
Returns data at the address indicated by the address pointer (0x00-0x7F)(0x0B / 0x34)

Control Device SideS

THCS254
Device Address

R

A

Read Data 1

A

Read Data 2

A・・・

Read Data #

A

P

IDLE

Remote Device Side

Figure 14-2 2-wire serial target register access protocol

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THCS254_Rev.1.30_E(2) 2–wire serial controller register accessFigure 15 2-wire serial controller register accessS

Start condition

R

Read command

P

Stop condition

W

Write command

A

ACK

Access from 2-wire serial Controller of Control Device

A

NACK

Access from 2-wire serial Target of Remote Device

Repeated start condition

Access from THCS254

Sr

Single Byte write
Control Device SideS

THCS254
Device Address

W

Register
AddressA

Clock
Stretching

A

Clock
Stretching

Write DataPSSEL=1 chipA

P

PSSEL=1 chip

IDLE

Remote Device Side

Burst write(0x0B / 0x34)

Control Device Side

THCS254
Device Address

S(0x80-0xFF)

W

Register
AddressA

Clock
Stretching

Write Data
1

A

PSSEL=1 chip
IDLE

Remote Device Side

Clock
Stretching

A

・・・

A

Write Data#PSSEL=1 chip

Clock
Stretching

A

P

A

P

PSSEL=1 chipSingle Byte read with repeated start command(0x0B / 0x34)

Control Device SideS

THCS254
Device Address(0x80-0xFF)

W

A

Register
Address

Clock
StretchingA

Sr

PSSEL=1 chip

THCS254
Device Address

R

A

Clock
Stretching

Read DataPSSEL=1 chip

IDLE

Remote Device Side

Figure 16-1 2-wire serial controller register access protocol

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THCS254_Rev.1.30_E
Burst read with repeated start commandControl Device SideS

(0x0B / 0x34)(0x80-0xFF)

THCS254
Device Address

Register
AddressW

A

Returns data at the address indicated by the address pointer (0x80-0xFF)

Clock
Stretching

A

P

S

THCS254
Device Address

PSSEL=1 chip

A

R

A

・・・

Clock
StretchingA

Read Data 1

Read Data 2

PSSEL=1 chip

IDLE

Remote Device Side

Clock
Stretching

Clock
Stretching

PSSEL=1 chipA

Read Data #A

P

PSSEL=1 chip
IDLE

Burst read with stop and start command(0x0B / 0x34)

Control Device SideS

THCS254
Device Address

Returns data at the address indicated by the address pointer (0x80-0xFF)(0x80-0xFF)

W

Register
AddressA

Clock
Stretching

A

P

S

THCS254
Device Address

PSSEL=1 chip

A

R

A

・・・

Clock
StretchingA

Read Data 1

Read Data 2

PSSEL=1 chip

IDLE

Remote Device Side

Clock
Stretching

Clock
Stretching

Read Data #A

PSSEL=1 chipA

P

PSSEL=1 chip
IDLE

Single Byte read without repeated start condition(0x0B / 0x34)

Control Device SideS

THCS254
Device Address

Returns data at the address indicated by the address pointer (0x80-0xFF)

Clock
Stretching

A

R

A

Read Data1

PSSEL=1 chip

P

IDLE

Remote Device Side

Burst read without repeated start condition(0x0B / 0x34)

Control Device SideS

THCS254
Device Address

R

A

Clock
Stretching

Returns data at the address indicated by the address pointer (0x80-0xFF)
Read Data 1

A

PSSEL=1 chip

Clock
Stretching

PSSEL=1 chip

Read Data 2

A・・・

Read Data #PSSEL=1 chip

A

P

IDLE

Remote Device Side

Figure 17-2 2-wire serial controller register access protocol

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THCS254_Rev.1.30_E(3) 2-wire serial remote device access *Partially includes access to THCS254

Figure 18 2-wire serial remote device accessS

Start condition

R

Read command

P

Stop condition

W

Write command

A

ACK

Access from 2-wire serial Controller of Control Device

A

NACK

Access from 2-wire serial Target of Remote Device

Repeated start condition

Access from THCS254

Sr

Single Byte write
Control Device SideS

Remote Device
Address

Remote Device SideS

Clock StretchingW

Remote Device
Address

SCL Low

A

W

Clock Stretching

Register
Address

A

Register
AddressA

SCL LowA

Clock Stretching

Write Data

Write DataAP

SCL LowA

P

Burst write
Control Device Side

Remote Device
Address

S

Remote Device Side

Clock StretchingW

Remote Device
AddressS

SCL Low

A

W

Clock Stretching

Register
Address

A

Register
AddressA

A

Write Data
1

SCL Low

Clock Stretching

Write Data
1

A

A

・・・

・・・

A

A

Write Data#

SCL Low

Clock Stretching

Write Data
#

A

A

P

SCL LowP

I2C detect write command
Neither THCS254 nor remote device
Clock Stretching
N/A Device

Control Device Side

Remote Device SideS

AddressS

W

N/A Device
Address

W

A

SCL
Low

A

SCL
Low

P

(0x0B / 0x34)

P

IDLE

IDLE

S

RemoteDevice Address

S

W

RemoteDevice Address

Clock Stretching

W

A

A

P

SCL Low

・・・

P

S

P

・・・

P

THCS254
Device Address

W

A

P

Pull-up

If the remote device side is NACK for the bridged device address,
THCS254 will issue its own stop condition to release the I2C target device.

Figure 19-1 2-wire serial remote device access protocol

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THCS254_Rev.1.30_E
Single Byte read with repeated start condition
Control Device Side

Remote Device
Address

S

Remote Device SideW

Clock Stretching

Remote Device
AddressS

SCL Low

A

W

Clock Stretching

Register
Address

A

Register
AddressA

Remote Device
AddressSr

SCL LowA

Clock Stretching

R

Remote Device
Address

Sr

A

A

R

A

Read Data

SCL Low

Read Data

SCL
Low

P

SCL
Low

A

P

Single Byte read without repeated start condition
Control Device SideS

Remote Device Side

Remote Device
AddressS

Clock Stretching

R

Remote Device
Address

A

R

A

SCL
Low

A

Read Data 1

SCL Low

Read Data 1

A

P

SCL
Low

P

Burst read with repeated start condition
Control Device SideS

Remote Device
Address

Remote Device SideSW

Clock Stretching

Remote Device
Address

SCL Low

A

W

Clock Stretching

Register
Address

A

Register
Address

Clock StretchingAA

SCL LowA

SCL LowA

Clock Stretching

R

Remote Device
Address

Sr

Clock
StretchingA

Read Data 2

Read Data 2

Remote Device
Address

Sr

・・・

A

S

Remote Device
AddressA

R

Clock Stretching

・・・

A

SCL Low

Read Data 1

A

Read Data #SCL Low

Read Data #A

Read Data 1

SCL
Low

A

P

SCL
Low

P

Burst read with stop and start condition
Control Device SideS

Remote Device Side

Remote Device
AddressS

W

Remote Device
Address

Clock StretchingW

SCL Low

A

Register
Address

Clock Stretching

A

Clock Stretching

Register
Address

A

IDLE

P

SCL LowA

A

Read Data 2

Read Data 2

A

SCL LowP

Clock
Stretching

・・・

IDLE

Remote Device
AddressS

Clock Stretching

・・・

A

A

Clock Stretching

R

A

R

A

Read Data #SCL Low

Read Data #A

SCL Low

Read Data 1

SCL
Low

A

A

Read Data 1

P

SCL
Low

P

Burst read without repeated start condition
Control Device Side

Remote Device SideS

Remote Device
AddressS

R

Remote Device
Address

Clock Stretching

R

A

A

Read Data 1

Read Data 1

SCL LowA

Clock
StretchingA

Read Data 2

Read Data 2

SCL LowA

Clock
StretchingA・・・

Clock Stretching

・・・

A

Read Data #Read Data #A

SCL Low

SCL
Low

A

P

SCL
Low

Figure 20-2 2-wire serial remote device access protocol

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P

THCS254_Rev.1.30_E
I2C detect read commandControl Device SideS

Remote Device
Address

Remote Device SideSR

Clock Stretching

Remote Device
Address

Read data fromremote deviceA

SCL Low

Read data fromremote device

R

A

S

THCS254
Device Address

S

A

R

Address

IDLE

P

Read Data from
THCS254A

R

Neither THCS254 nor remote device
Clock Stretching
N/A Device

IDLE

P

SCL
Low

A

(0x0B / 0x34)
IDLE

SCL
Low

A

N/A Device
Address

S

A

R

SCL
Low

A

SCL
Low

IDLE

P

IDLE

P

If the remote device side is NACK for the bridged device address,
THCS254 will issue its own stop condition to release the I2C target device.

P

IDLE

2Byte addressing device read with repeated start condition
Control Device SideS

Remote Device
Address

Remote Device SideSW

Clock Stretching

Remote Device
AddressW

A

SCL LowA

Sr

SCL Low

Register
Address(MSB)

Remote Device
Address

Sr

Clock Stretching

Register
Address(MSB)R

SCL LowA

Clock Stretching

Remote Device
Address

Register
Address(LSB)

A

A

R

A

Clock Stretching

Register
Address(LSB)

Read DataAA

SCL Low

Read DataA

SCL Low

SCL
Low

P

SCL
Low

A

P

2Byte addressing device read with stop and start condition
Control Device Side

Remote Device SideS

Remote Device
AddressS

W

Remote Device
Address

Clock Stretching

W

A

Register
Address(MSB)SCL Low

A

IDLE

IDLE

S

Clock Stretching

Register
Address(MSB)

A

Remote Device
AddressR

S

Remote Device
Address

A

Register
Address(LSB)SCL Low

Clock Stretching

R

A

Clock Stretching

Register
Address(LSB)

A

40/61

A

Read Data

Read Data

SCL LowIDLE

P

SCL LowA

Figure 21-3 2-wire serial remote device access protocol

Copyright©2024 THine Electronics, Inc.

A

SCL
Low

A

IDLE

P

P

SCL
Low

P

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THCS254_Rev.1.30_E
10.6.8. 2-wire serial expander
The I2C_EXPAND (register) setting determines whether data transmission is performed through or used as an I2C
expander. When used as an I2C expander, the value set in GPIO_OUT_*(*...0~2) is output from the data pins.
The setting of GPIO_OBUF_*(*...0~2) is valid for the output buffer setting. Also, regardless of the I2C_EXPAND
setting, data input is stored in GPIO_IN_*(*...0~2) and can be checked by I2C read.
Table 16 GPIO type setting
Function

Register Name

GPIO
function selectI2C_EXPAND

Description
0: Through(Default)
1: I2C Expander

THCS254(2-wire target)

THCS254(2-wire controller)

GPIO_IN_0-2(reg)
Read fromI2C Master side
register

Data

Data
input

2-wireserialController

Tx

2-wireserialWrite toI2C Slave side
register2-wireserialTargetWrite toI2C Master side
registerDataoutput

1

0

Rx

1

GPIO_OUT_0-2(reg)

Read fromI2C Slave side
register

I2C_EXPAND (reg)

GPIO_OUT_0-2
(reg)
Rx

0

Data
output

Data
input

Tx

Data

GPIO_IN_0-2(reg)

I2C_EXPAND (reg)Figure 22 2-wire serial expander function

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THCS254_Rev.1.30_E
10.7. Direction of GPIOThe flow from the primary chip transmitter output to the secondary chip receiver input is defined as downstream.
The flow from the secondary chip transmitter output to the primary chip receiver input is defined as upstream.
By setting OVERRIDE_OEN (register) to 1, the GPIO direction can be freely set for each pin.
Table 17 GPIO direction for each example
OVERRIDE_OE(register)

A-1

A-2

0

1
External reference
clock mode
1/tTCIPx30
Internal oscillator
clock mode
1/tOSCx30

CML data rate

D0/D19(pin)D1/D18(pin)D2/D17(pin)D3/D16(pin)D4/D15(pin)D5/D14(pin)D6/D13(pin)D7/D12(pin)D8/D11(pin)D9/D10(pin)D10/D9(pin)D11/D8(pin)D12/D7(pin)D13/D6(pin)D14/D5(pin)D15/D4(pin)D16/D3(pin)D17/D2(pin)D18/D1(pin)D19/D0(pin)<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1<=> *1

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

D19/D0(pin)D18/D1(pin)D17/D2(pin)D16/D3(pin)D15/D4(pin)D14/D5(pin)D13/D6(pin)D12/D7(pin)D11/D8(pin)D10/D9(pin)D9/D10(pin)D8/D11(pin)D7/D12(pin)D6/D13(pin)D5/D14(pin)D4/D15(pin)D3/D16(pin)D2/D17(pin)D1/D18(pin)D0/D19(pin)Data pin of secondary chip

Data pin of primary chip

Mode

Setti
ng

Use case“=>" is downstream (GPIO input to the primary chip is GPIO output from the secondary chip)“<=" is upstream (GPIO input to the secondary chip is GPIO output from the primary chip)“<=>" is a pin whose directionality can be selected one by one by internal register setting.
*1 The setting that contradicts the pin relationship between the primary chip and the secondary chip indicated by the pin
name is not allowed.

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THCS254_Rev.1.30_E
The following table shows the mapping between pins and registers that can be set by setting OVERRIDE_OEN(register) to 1.
Table 18 GPIO OEN_0-3(register) mapping
Controlled terminal mapping
Register Name

GPIO_OEN_0(register)

GPIO_OEN_1(register)

GPIO_OEN_2(register)

bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]

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Description
Primary chip mode

Secondary chip mode

D0/D19(pin)D1/D18(pin)D2/D17(pin)D3/D16(pin)D4/D15(pin)D5/D14(pin)D6/D13(pin)D7/D12(pin)D8/D11(pin)D9/D10(pin)D10/D9(pin)D11/D8(pin)D12/D7(pin)D13/D6(pin)D14/D5(pin)D15/D4(pin)D16/D3(pin)D17/D2(pin)D18/D1(pin)D19/D0(pin)D19/D0(pin)D18/D1(pin)D17/D2(pin)D16/D3(pin)D15/D4(pin)D14/D5(pin)D13/D6(pin)D12/D7(pin)D11/D8(pin)D10/D9(pin)D9/D10(pin)D8/D11(pin)D7/D12(pin)D6/D13(pin)D5/D14(pin)D4/D15(pin)D3/D16(pin)D2/D17(pin)D1/D18(pin)D0/D19(pin)43/61

GPIO direction select{0} : Output{1} : Input

THine Electronics, Inc.

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THCS254_Rev.1.30_E
10.8. IO configuration
10.8.1. I/O digital noise filter
THCS254 has digital noise filters for GPIO input (CMOS input noise immunity) and output (CML line noise
immunity), and the digital noise filters can be set simultaneously by setting FILTSEL1 (pin) and FILTSEL0(pin). Each GPIO digital noise filter can be individually enabled by setting GPIO_I_FILTEN_0-2(register) andGPIO_O_FILTEN_0-2(register) with OVERRIDE_FILTEN (register)=1. The GPIO_I_FILTEN_0-2register) andGPIO_O_FILTEN_0-2register) settings enable each GPIO digital noise filter individually.
The digital filter is disabled until it is enabled by one of the above setting pins or registers.

The number of input/output filter tap can also be set by GPIO_I_FILTSET(register) andGPIO_O_FILTSET(register). The number of filter stages cannot be set for each pin individually.
The data width of (tap_num-1) tFLTCK or less is subject to filtering.
Table 19 Input digital noise filter setting
Setting
OVERRIDE_I_FILTEN(register){0}(default)

GPIO_I_FILTEN_0-2(register)

Function
digital noise filter
disabledigital noise filter
disable（Table 23）
digital noise filter
enable（Table 23）

{0}

{1}
{1}

Filternumber of taps
(tap_num)
GPIO_I_FILTSET(register)Setting

Table 20 Output digital noise filter setting
Setting
OVERRIDE_O_FILTEN(register){0}(default)

GPIO_O_FILTEN_0-2(register)

digital noise filter
disableDigital noise filter
disable（Table 23）
Digital noise filter
enable（Table 23）

{0}

{1}
{1}

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Function

44/61

Filternumber of taps
(tap_num)
GPIO_O_FILTSET(register)THine Electronics, Inc.

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THCS254_Rev.1.30_E
Table 21 GPIO_I_FILTEN_0-2(register) / GPIO_O_FILTEN_0-2(register) mapping
Controlled terminal mapping
Register name

GPIO_I_FILTEN_0(register)
GPIO_O_FILTEN_0(register)

GPIO_I_FILTEN_1(register)
GPIO_O_FILTEN_1(register)

GPIO_I_FILTEN_2(register)
GPIO_O_FILTEN_2(register)bit

Description
Primary chip mode

Secondary chip mode

D0/D19(pin)D1/D18(pin)D2/D17(pin)D3/D16(pin)D4/D15(pin)D5/D14(pin)D6/D13(pin)D7/D12(pin)D8/D11(pin)D9/D10(pin)D10/D9(pin)D11/D8(pin)D12/D7(pin)D13/D6(pin)D14/D5(pin)D15/D4(pin)D16/D3(pin)D17/D2(pin)D18/D1(pin)D19/D0(pin)D19/D0(pin)D18/D1(pin)D17/D2(pin)D16/D3(pin)D15/D4(pin)D14/D5(pin)D13/D6(pin)D12/D7(pin)D11/D8(pin)D10/D9(pin)D9/D10(pin)D8/D11(pin)D7/D12(pin)D6/D13(pin)D5/D14(pin)D4/D15(pin)D3/D16(pin)D2/D17(pin)D1/D18(pin)D0/D19(pin)

[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]

GPIO Input / output
digital noise filter{0}:Disable{1}:Enable

Table 22 Filter tap Setting
Register name

Description

GPIO_I_FILTSET(register)

Input digital noise filter setting
Number of filter tap(tap_num) = GPIO_I_FILTSET+1

GPIO_O_FILTSET(register)

Output digital noise filter setting
Number of filter tap (tap_num) = GPIO_I_FILTSET+1

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THCS254_Rev.1.30_E
10.8.2. LVCMOS Output buffer type configuration
The GPIO output buffer type can be selected between open-drain and push-pull.

All output pins can be switchedsimultaneously by OBUF (pin), or each pin can be set by GPIO_OBUF_0-2 (register) via 2-wire serial interface.
Table 23 Output buffer type configuration
Setting
GPIO_OBUF_0-2(register)

Function{0}

Set each GPIO output buffer type to open-drain{1}

Set each GPIO output buffer type to push-pull

Table 24 GPIO_OBUF_0-3(register) mapping
Controlled terminal mapping
Register name

GPIO_OBUF_0(regis
ter)

GPIO_OBUF_1(regis
ter)

GPIO_OBUF_2(register)

Description

Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]

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Primary chip mode

Primary chip mode

D0/D19(pin)D1/D18(pin)D2/D17(pin)D3/D16(pin)D4/D15(pin)D5/D14(pin)D6/D13(pin)D7/D12(pin)D8/D11(pin)D9/D10(pin)D10/D9(pin)D11/D8(pin)D12/D7(pin)D13/D6(pin)D14/D5(pin)D15/D4(pin)D16/D3(pin)D17/D2(pin)D18/D1(pin)D19/D0(pin)D19/D0(pin)D18/D1(pin)D17/D2(pin)D16/D3(pin)D15/D4(pin)D14/D5(pin)D13/D6(pin)D12/D7(pin)D11/D8(pin)D10/D9(pin)D9/D10(pin)D8/D11(pin)D7/D12(pin)D6/D13(pin)D5/D14(pin)D4/D15(pin)D3/D16(pin)D2/D17(pin)D1/D18(pin)D0/D19(pin)46/61

GPIO output buffer typeselect{0}:open-drain{1}:push-pull

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THCS254_Rev.1.30_E
10.8.3. 5V tolerant IO
Primary chip and Secondary chip are each equipped with 8 5V withstand voltage IOs.
Secondary chip mode (PSSEL=1)

Primary chip modeMaster mode (PSSEL=0)

5V Tolerant I/O

D0/D19D1/D18
D2/D17
D3/D16

Normal I/O

D4/D15...
D15/D4

5V Tolerant I/O

Downstream

D16/D3
D17/D2
D18/D1
D19/D0

TXP
TXN

RXP
RXN

RXN
RXP

TXN
TXP

D19/D0
D18/D1
D17/D2
D16/D3
D15/D4...
D4/D15
D3/D16
D2/D17
D1/D18
D0/D19

Upstream

Figure 23 5V tolerant IO

10.8.4. LVSMOS Output drive strength setting
The THCS254 can set the output drive strength of REFOUT, D0 (pin) – D19 (pin), and READY pin with the
TTLDRV (register). High drive setting is recommended when the reference clock frequency is 100 MHz or higher
in external reference clock mode with VDD = 1.8 V drive and REFEN(pin)=H
Table 25 LVCMOS output drive strength setting
Setting
TTLDRV(register)

Description{0}

Normal(default)

{1}

High

10.8.5. CML output swing voltage and pre-emphasis setting
The CML output driver pre-emphasis compensates for the loss of high-frequency signal due to long-distance or
high-speed transmission.

The CML output swing voltage and pre-emphasis can be set by setting CMLDRV(register) and CMLPRE (register).
Table 26 CML differential output and Pre-emphasis settings
Setting
CMLDRV [1:0](register)
{00}
{01}
{10}
{11}

CMLPRE(register)

CML differential
outputpeak to peakPre-emphasis

Description

{0}
{1}
{0}

400mVpp
400mVpp
600mVpp

0dB (0%)6dB (100%)0dB (0%)

Default{1}

600mVpp3.52dB (50%)-{0}800mVpp

0dB (0%)-{1}800mVpp

0dB (0%)

-

{0}
{1}

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10.9. Clock configuration
10.9.1. Sampling clock selectPrimary chip selects either external reference clock sampling or internal oscillator clock sampling with REFEN(pin).
Secondary chip uses SYNCEN (pin) to select whether to operate synchronously with the primary chip clock or
asynchronously with the primary chip.

If SYNCEN = 0 for asynchronous operation, REFEN (pin) is used to

select external reference clock sampling or internal oscillator clock sampling.

When an external reference clock is used, the data sampling clock edge can be selected with RF_IN/OSCSEL0(pin). Similarly, the data output clock edge is selected by RF_OUT/OSCSEL1 (pin). When internal oscillator
clock sampling is selected by REFEN (pin) = 0, the internal oscillator clock frequency can be selected by
RF_OUT/OSCSEL1 (pin) and RF_IN/OSCSEL0 (pin).

Table 27 Sampling Clock and RF_OUT/OSCSEL1, RF_IN/OSCSEL0 Function
PSSEL
(pin)

SYNCEN
(pin)

REFEN
(pin)

REFIN
(pin)

Invalid0-Invalid1

Ext.
reference
clock

0

-

1

Ext.
referenceclock

Invalid-

Invalid-001

RF_OUT/OSCSEL1(pin)

RF_IN/OSCSEL0(pin)

Description

Int. OSC clock sampling frequency setting(OSCSEL1, OSCSEL0)

Sampling with internal oscillator clock
Frequency set by OSCSEL1 and OSCSEL0 (pin)Output data
clock edge setting
RF_OUT

Sampling with external reference clock

Output data
clock edge setting
RF_IN

Int. OSC clock sampling frequency setting(OSCSEL1, OSCSEL0)

Sampling with internal oscillator clock
Frequency set by OSCSEL1 and OSCSEL0 (pin)Output data
clock edge setting
RF_OUT

Sampling with external reference clock

Output data
clock edge setting
RF_IN

Invalid

Sampling with CDR clock1
Invalid

Invalid

Sampling with CDR clock

Table 28 OSC Clock Sampling Frequency and External Clock Input frequency
REFEN
(pin)

RF_OUT/OSCSEL1(pin)

RF_IN/OSCSEL0(pin)

OSC. frequency /Input frequency

CML data rate

00

20MHz±20%

480Mbps - 720Mbps

01

960Mbps - 1440Mbps

01

40MHz±20%
1

0

1

1

80MHz±20%

1920Mbps - 2880Mbps--

15 - 133.3MHz

0.45 - 4.0Gbps

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10.9.2.

Clock edge select (RF_IN, RF_OUT)

When REFEN=1 (external reference clock is used), clock edge switching function is Enable.
The RF_IN/OSCSEL0 pin can be used to set the input data sampling edge when an external reference clock isused, and the RF_OUT/OSCSEL1 pin can be used to set the REFOUT output clock edge. The polarity of RF_IN
and RF_OUT is the clock edge that defines Setup/Hold timing.

When REFEN = 0, the RF_IN and RF_OUT pins are disabled and the clock edge cannot be switched. In this case,the device operates in Fall Edge mode.

Table 29 RF Function
Pin name

Description

RF_IN
RF_OUT

0 : Fall Edge (Default)
1 : Rise Edge

DATA

DATA

REFIN

REFOUT
RF_IN=1

RF_OUT=1

RF_IN=0

RF_OUT=0

Figure 24 RF_IN, RF_OUT Function

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10.10. Spread spectrum clock generator and REFIN(pin) frequency
THCS254 enables spread spectrum clock output by enabling SSCG PLL with SSEN (pin). When 2-wire serialinterface is enabled (ENI2C=1), the modulation frequency and modulation rate of the spread spectrum clock canbe set.
When SYNCEN (pin) = 1, the spread spectrum clock is set only on the transmitter clock side of the primary chip.
When SYNCEN (pin) = 0, it can be multiplied to both primary and secondary chips.
Primary chip

Secondary chip
TX
(Serializer)

OSC

SSCG PLLREFINRX(DeSerializer)

REFEN

REFOUTRegSDA/SSEN

SDA/SSENREFOUT

TX(Serializer)

RX(DeSerializer)

Reg

SSCG PLL

REFIN
OSC

REFEN

Figure 25 Spread Spectrum Configuration

Table 30 Spread Spectrum Setting
Register nameSPREAD[4:0] (register)
FMOD[3:0] (register)

Description
Modulation rate setting Modulation rate = SPREAD
Modulation frequency setting

The modulation frequency of the spread spectrum clock is determined by the following formula.

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10.11. PWM signal output function
The THCS254 can output PWM signals from the D2/D17/PWMOUT pins.
Access the PWMH [7:0] and PWML [7:0] registers via the 2-wire serial interface to set the L/H period in 256
steps, and enable PWMOUT with the PWMEN register.
PWM High period = (1/80MHz±20%) x PWMH(0～255)[ns]
PWM Low period = (1/80MHz±20%) x PWML(0～255)[ns]Except,When PWML = 0x00 and PWMH = 0x00, D2/D29/PWMOUT pin is fixed low.
When PWML = 0x00 and PWMH = 0x01, D2/D29/PWMOUT pin is fixed high.

10.12. CRC
THCS254 adds CRC data (CRC8) to GPIO signals and during 2-wire serial communication to avoid outputting
abnormal data when bit errors occur. The CRC is inserted once every 4 sampling clocks when DATAWIDTH=1
and once every 6 sampling clocks when DATAWIDTH=0. The CRC data insertion is shown in the figure below.

CLK
Byte0

7:0

I2C

Byte1
Byte2

119:112

CR C[7:0]

CR C[7:0]

239:232

127:120I2C

247:240

Figure 26 CRC data

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10.13. Error detection and notification
10.13.1. READY signal
The THCS254 notifies with READY(pin) when the link between the Primary chip and the Secondary chip isestablished and data transmission and I2C transmission are possible. When the transmitter's PLL, receiver's CDR,
and SSCG PLL (when the spread spectrum clock is enabled) are locked and normal pattern transmission is enabled,
READY(pin)=H is displayed.
When there is no link error such as clock error or off-lock, the READY signal is output high, and data error isnotified from INTN (pin). When a link error is detected, READY (pin) goes low and enters the re-link-up sequence.
During the READY(pin)=L period, data transmission, 2-wire serial communication across devices (access tointernal registers of secondary chip, access to remote device registers) is prohibited. Access to the internal registersof the chip set to the 2-wire serial interface target (Primary chip) is possible. Notification from READY (pin) is
possible for both Primary chip and Secondary chip.
Table 31 Operation of READY(pin)
READY
(pin)
L
H

Description
Link not established.
Data transmit and receive is inhibited.
I2C access to secondary chips or remote devices is prohibited.
Link established.
Data transmit and receive, I2C access available.

10.13.2. INTN signal
When the THCS254 detects errors in the CRC error check result on the CML line, it signals these as interrupt
causes through INTN (pin). INTN signal is a low active open drain output.
When the interrupt register is enabled, the INTN (pin) transitions from INTN (high) to low when an error thatcauses an interrupt occurs, and INTN (pin) = low is maintained until the interrupt status register is cleared.
When the interrupt register is disabled, INTN (pin) = L when any interrupt factor occurs.

INTN (pin) = L is

output until the data error is cleared, and returns to INTN (pin) = H (pull-up) when the data error is cleared. At
this time, the GPIO output signal updates the output data only when INTN (pin) = High, and holds the output
before the error occurs when INTN (pin) = Low.
The THCS254 detects CRC signals inserted in communication packets and notifies the user via INTN (pin).
There are two types of CRC signals: one is embedded in the downstream/upstream GPIO error detection byte andthe other is embedded in the 2-wire serial transmit/receive error detection byte.

Normally, the CRC for 2-wireserial transmission and reception is an invalid signal when 2-wire serial communication is not being used. However,
if noise is mixed in during transmission and the CRC data is corrupted, as it is during communication, a 2-wireserial communication CRC error may occur even if 2-wire serial communication is not being used.

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10.14. Standby mode: STANDBY(register)=1
Standby mode is an operation mode that enables data transmission at low sampling rate and low power
consumption. The transition from normal mode to standby mode and from standby mode to normal mode isinitiated by STANDBY (register) access via 2-wire serial.
target of primary chip.

STANDBY(register) exists only on the 2-wire serial

In standby mode, handshake communication is performed between the primary chip andsecondary chip. Operation can be selected between sampling and data transmission (polling) at intervals set by
STBY_CYCLE (register) and data transmission by detecting changes in the pins for standby mode or I2C input.
A maximum of eight GPIO signals can be used for data transmission. The number and direction of the number ofsignals used are set by the STBY_NUM_DS (register) and STBY_NUM_US (register) of the primary chip. The
number of pins in the downstream direction is set by STBY_NUM_DS (register) and the number of pins in the
upstream direction by STBY_NUM_US (register). Upon entry into standby mode, if the link was established innormal mode, the READY signal goes low once, and when handshake communication is established, the READY
signal goes high again to enable signal transmission. The interrupt status register (transmission error generationinterrupt, I2C interrupt, etc.) and INT are cleared during normal operation.

If the opposing device exits fromstandby mode or power down after the READY signal goes high, the primary chip side detects no response fromthe secondary chip and the secondary chip side detects a timeout in the request interval from the primary chip andsets the READY signal low.

The primary chip issues the first request command 1.5 ms (typ) after entering

standby mode. The sampling interval for polling operation can be changed by setting the STBY_CYCLE registeron the primary chip side. No setting is required on the secondary chip side.
Table 32 Standby Mode Operation Select
STNADBY(register)
0
1

STBY_MODE(register)Ignore0(default)

Description
Normal operation
Only polling operation

1

Polling and external trigger operation

1

1

1

1

0

4

4

4

4

4

8

8

8

0

0

1

2

7

8

8

0

1

2

7

8

0

1

8

Down

Down

Down

Down

Down

Up

Down

Down

Down

Down

Down

Down

Down

Down

Up

Up

Up

Down

Down

Down

Down

Down

Down

Down

Down

Up

Up

Up

Down

Down

Down

Down

Down

Down

Down

Down

Up

Up

Up

Down

Down

Down

Down

Down

Down

Down

Down

Up

Up

Up

Up

Down

Down

Down

Up

Up

Up

Normalterminal
handling

Up
Up

Up

Down

Down

Down

Up

Up

Up

Up

Up

Up

Up

Down

Down

Down

Up

Up

Up

Up

Up

Up

Up

Down

Down

Down

D0/D19D28/D3
D29/D2
D30/D1
D31/D0Normal terminal handlingD3/D28

Normal terminal handlingD2/D29

Normal terminal handlingD1/D18Up

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Normalterminal
handling

1

Normal terminal
handling

0

Normal terminal handling

Table 33 STBY_NUM_DS, STBY_NUM_US vs Standby mode data pin state example
STBY_NUM_DS(register)
STBY_NUM_US(register)Up

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Table 34 Output of normal data pin in standby mode
STBY_DOUT(register)0
1

Description
Hi-Z(Default)
Holds status before standby mode entry

Table 35 Standby Mode Sampling Rate Setting (Primary chip only)
Register
name

STBY_CYCLE(register)

Description
000：50ms
001：100ms(Default)
010：150ms
011：200ms
100：250ms
101：300ms
110：350ms
111：400ms
Values are Typical values. Guaranteed value is ±20% of theabove value due to OSC variation.

Table 36 Registers that need to be set in standby mode
Register Name

Primary chip

Secondary chip

STBY_DRVAs required

As required

STBY_NUM_DS

Required

Not Required

STBY_NUM_US

Required

Not Required

STBY_CYCLE

Required

Not Required

STBY_DOUT

As required

As required

STBY_MODEAs required

Prohibition

STANBY

Required

Required

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11. Register map
Targetaddress
(Hex)

0x00

0x01

Controller
address
(Hex)

0x80

-

Bit
#

R/W

Default（Hex）

Register name

3

R

-

STBY_READY

2

R

-

LINK_READY

0

R

-

INT

2

R/W

0

I2C_CRC

1

R/W

0

US_CRC

0

R/W

0

DS_CRC

2

R/W

0

I2C_CRC_EN

1

R/W

0

US_CRC_EN

0x02

-

0

R/W

0

DS_CRC_EN

0x03

0x83

0

R/W

0

Reserved

0x04

0x84

0

R/W

0

I2C_EXPAND

0x05
0x06
0x07

0x85
0x86
0x87

7:0
7:0
3:0

R
R
R

0x00
0x00
0x00

GPIO_IN_0
GPIO_IN_1
GPIO_IN_2

0x09

0x89

7:0

R/W

0x00

GPIO_OUT_0

0x0A

0x8A

7:0

R/W

0x00

GPIO_OUT_1

0x0B

0x8B

3:0

R/W

0x00

GPIO_OUT_2

0x0D

0x8D

7:0

R/W

0xFF

GPIO_OEN_0

0x0E

0x8E

7:0

R/W

0xFF

GPIO_OEN_1

0x0F

0x8F

3:0

R/W

0xFF

GPIO_OEN_2

0x11

0x91

0

R/W

0

OVERRIDE_OEN

0x12

0x92

7:0

R/W

0xFF

GPIO_OBUF_0

0x13

0x93

7:0

R/W

0xFF

GPIO_OBUF_1

0x14

0x94

3:0

R/W

0xFF

GPIO_OBUF_2

0x16

0x96

7:0

R/W

0x00

Reserved

0x17

0x97

7:0

R/W

0xFF

GPIO_I_FILTEN_0

0x18

0x98

7:0

R/W

0xFF

GPIO_I_FILTEN_1

0x19

0x99

3:0

R/W

0xFF

GPIO_I_FILTEN_2

0x1B

0x9B

7:0

R/W

0x03

GPIO_I_FILTSET

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Description
READY signal status in standby mode
0: READY=L or Normal mode
1: READY=H
READY signal status in normal mode
0: READY=L or standby mode
1: READY=H
INT status (INTN(pin) inversion)
0: No error
1: Error occurred
0: No error
1: 2-wire serial com error occurred
WRITE 1: Error clear
0: No error
1: Upstream error occurred
WRITE 1: Error clear
0: No error
1: Downstream error occurred
WRITE 1: Error clear
0: 2-wire serial come error interrupt enable
1: 2-wire serial come error interrupt disable
0: Upstream error interrupt enable
1: Upstream error interrupt disable
0: Downstream error interrupt enable
1: Downstream error interrupt disable
0 FixedI/O Expander mode
0: Disable（GPIO transceiver mode）
1: Enable
GPIO[7:0] input status monitor
GPIO[15:8]input status monitor
GPIO[19:16]input status monitor
GPIO[7:0] output setting (Applicable only
to I/O expansion mode)
GPIO[15:8] output setting (Applicable
only to I/O expansion mode)
GPIO[19:16] output setting (Applicable
only to I/O expansion mode)
GPIO [7:0] direction select0:output 1:input
GPIO [15:8] direction select0:output 1:input
GPIO [19:16] direction select0:output 1:input
GPIO_OEN setting method select0: Input/output default values per use case
1: Register setting GPIO_OEN_0-3
GPIO [7:0] Output buffer type select0:Open Drain 1:Pushpull
GPIO [15:8] Output buffer typeselect0:Open Drain 1:Pushpull
GPIO [19:16] Output buffer typeselect0:Open Drain 1:Pushpull
Must be 0
GPIO [7:0] input digital noise filter
0:Disable 1:Enable
GPIO [15:8] input digital noise filter
0:Disable 1:Enable
GPIO [19:16] input digital noise filter
0:Disable 1:Enable
Input digital noise filter setting
Number of filter tap = GPIO_I_FILTSET+1

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0x1C

0x9C

0

R/W

0

OVERRIDE_I_FILTEN

0x1D

0x9D

7:0

R/W

0xFF

GPIO_O_FILTEN_0

0x1E

0x9E

7:0

R/W

0xFF

GPIO_O_FILTEN_1

0x1F

0x9F

3:0

R/W

0xFF

GPIO_O_FILTEN_2

0x21

0xA1

7:0

R/W

0x03

GPIO_O_FILTSET

0x22

0xA2

0

R/W

0

OVERRIDE_O_FLTEN

0x23
0x24
0x25

0xA3
0xA4
0xA5

7:0
7:0
0

R
R
W

0x00
0x00
-

CRC_ERROR_COUNT[15:8]
CRC_ERROR_COUNT[7:0]
CRC_ERROR_COUNT_CLEAR

0x26

0xA6

7:0

R/W

0x64

I2CPERIOD

0x27

0xA7

7:0

R/W

0x64

Reserved

0x28

7:4

R/W

0x6

I2C_WDT_STBY

3:0

R/W

0xF

I2C_WDT

0xA8

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Input digital noise filter enable setting
method
1: GPIO_I_FILTEN_0-3(register)
GPIO[7:0] output digital noise filter
0:Disable 1:Enable
GPIO[15:8] output digital noise filter
0:Disable 1:Enable
GPIO[19:16] output digital noise filter
0:Disable 1:Enable
Output digital noise filter setting
Number of filter tap =GPIO_O_FILTSET+1
Output digital noise filter enable setting
method0: FILTSEL1(pin) and FILTSEL0(pin)1: GPIO_I_FILTEN_0-3(register)
Number of CRC error (MSB 8bit)
Number of CRC error (LSB 8bit)
1 Write : CRC ERROR COUNT[15:0] clear
I2C Controller Bit Rate
10,000/I2CPERIOD kbps
2-wire serial controller / target watch dog
timer (Standby)
0 : Watch dog timer disable
1: 50ms
2: 151ms
3: 352ms
4: 755ms
5: 1.56s
6: 3.17s
7: 6.39s
8: 12.8s
9: 25.7s
10: 51.5s
11: 103s
12: 206s
13: 412s
14: 825s
15 : 1650s
2-wire serial controller / target watch dog
timer (Normal operation)
Setting value of controller >= Setting valueof target
0: Watch dog timer disable
Controller
Target1:
0.0123ms
0.0246ms
2:0.0369ms
0.0738ms
3:0.0860ms
0.172ms
4:
0.184ms
0.368ms
5:0.381ms
0.762ms
6:0.774ms
1.55ms7:
1.56ms3.12ms8:3.13ms6.26ms9:6.28ms12.6ms
10: 12.6ms
25.2ms
11: 25.2ms
50.4ms
12: 50.3ms
101ms
13: 101ms
202ms
14: 201ms
402ms
15: 403ms
806ms

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0x29

4

R/W

0

STBY_DRV

3

R/W

0

CMLPRE

2:1

R/W

0x1

CMLDRV

0R/W

0TTLDRV

0xA9

0x2A

0xAA

0

R/W

0

Reserved

0x2B

0xAB

4:0

R/W

0x05

SPREAD

0x2C

0xAC

2:0

R/W

0x6

FMOD

0x2D

0xAD

1
0

R/W
R/W

0
0

Reserved
Reserved

0x2E

0xAE

7:0

R/W

0x00

PWMH

0x2F

0xAF

7:0

R/W

0x00

PWML

0x30

0xB0

0

R/W

0

PWM_EN

7:4

R/W

0x4

STBY_NUM_DS

3:0

R/W

0x4

STBY_NUM_US

0x31

0xB1

0x32

0xB2

2:0

R/W

0x1

STBY_CYCLE

0x33

0xB3

0

R/W

0

STBY_DOUT

0x34

0xB4

0

R/W

0

STBY_MODE

0x35

-

0

R/W

0

STANDBY

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Standby mode CML differential output
voltage setting
0: 200mV 1: 300mV
Normal mode CML differential Preemphasis setting
0:0dB (default) 1: Depends on the
CMLDRV
Normal mode CML differential output
voltage setting
0x0: 200mV
0x1: 300mV
0x2: 400mV
0x3: Prohibition
LVCMOS output drive strength setting
0: Normal
1: HighMust be 0
SSCG modulation rate setting
Modulation rate = SPREAD * ±0.1%
Maximum ±0.5%
SSCG modulation frequency(fmod)Setting
Maximum 30kHz

Must be 0
Must be 0
PWMH period
0x00: When PWML=0x00, L fixed
0x01: H period 1 clock, (WhenPWML=0x00, H fixed)~
0xFF: H period 255 clock
PWML period
0x00: When PWML=0x00, L fixed, When
PWMH=0x01, H fixed.
0x01: H period 1 clock,~
0xFF: H period 255 clock
PWM output enable
Number of Standby mode downstream
GPIO setting: Maximum 0x8(0x9-0xF is considered 0x8)
*Set primary chip only
Number of Standby mode upstream GPIO
setting: Maximum 0x8(0x9-0xF is considered 0x8)
*Set primary chip onlyStandby mode polling period setting*Set primary chip only
0x0: 50ms
0x1: 100ms
0x2: 150ms
0x3: 200ms
0x4: 250ms
0x5: 300ms
0x6: 350ms
0x7: 400ms
Standby mode static GPIO output status*Set by primary chip/secondary chip
respectively
0: Hi-Z (default)
1: Holds status before standby mode
entryStandby mode hand shake com start
condition
0: Polling operation
1: Polling operation and external trigger
0: Normal operation 1: Standby

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0x36

0xB6

0x37

0xB7

0x38
0x39
0x3A
0x3B
0x3C
0x3D

0xB8
0xB9
0xBA
0xBB
0xBC
0xBD

0
7:4
3:0
7:0
7:0
3:0
7:0
4:0
7:0

R/W
R
R
R/W
R/W
R/W
R
R
R/W

Copyright©2024 THine Electronics, Inc.

0
0
0
0x0F
0x1F
0x4
0
0
0x00

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

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Must be 0
Must be 0
Must be 0
0x0F fixed
0x1F fixed
0x4 fixed
Must be 0
Must be 0
Must be 0

THine Electronics, Inc.

SC: E

THCS254_Rev.1.30_E

12. Package
ccc C
A
A2
A3
A1
0.10

E

D

C

1 PIN INDEXTOP VIEWSEATING
PLANE

SIDE VIEW

D2
1.085

R

0.45

1.085

E2

1 PIN INDEX
0.20 R

Le

Lb

BOTTOM VIEW

Unit : mm
Symbol
A
A1
A2
A3
b
D
D2
E
E2
L
e
R
ccc

Items
Mounting HeightStandoffTerminal Width
Body Length
Exposed Length
Body Width
Exposed Width
Pitch
Coplanarity

Min.
0.80
0.00
0.60
0.18
3.93
3.93
0.35
0.09

Nom.
0.85
0.025
0.65
(0.20)
0.25
7.00 BSC
4.03
7.00 BSC
4.03
0.40
0.50 BSC
0.125
0.05

Max.
0.90
0.05
0.70
0.30
4.13
4.13
0.45
0.15

Figure 27 48-pin QFN package physical dimension

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THCS254_Rev.1.30_E

13. Reference land pattern

4.03

4.03

0.50

1.085

1.085

0.50

0.25

(Note)
Please carefully consider your SMT conditions (Material of substrate, Solder Composition, Reflow Condition and so on), and adjusts
the Land Pattern at your own risk.
If there is any inconsistency or conflict between the English and Japanese versions, the English version shall prevail.

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THine Electronics, Inc.

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THCS254_Rev.1.30_E

14. Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclear
power control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp
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