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SLES065 – DECEMBER 2002    FEATURES
D 27-MHz Master Clock Input
D Generated Audio System Clock (PLL1707):

D

D
D
D
D
D
D
D

– SCKO0: 768 fS (fS = 44.1 kHz)– SCKO1: 768 fS, 512 fS (fS = 48 kHz)– SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,
96 kHz)– SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2,
96 kHz)Generated Audio System Clock (PLL1708):– SCKO0: 768 fS (fS = 44.1 kHz)– SCKO1: 768 fS, 512 fS, 384 fS, 256 fS(fS = 48 kHz)– SCKO2: 256 fS (fS = 16, 22.05, 24, 32, 44.1,
48, 64, 88.2, 96 kHz)– SCKO3: 384 fS (fS = 16, 22.05, 24, 32, 44.1,
48, 64, 88.2, 96 kHz)
Zero PPM Error Output Clocks
Low Clock Jitter: 50 ps (Typical)
Multiple Sampling Frequencies (PLL1707):– fS = 32, 44.1, 48, 64, 88.2, 96 kHz
Multiple Sampling Frequencies (PLL1708):– fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2,
96 kHz3.3-V Single Power Supply
PLL1707: Parallel Control
PLL1708: Serial Control
Package: 20-Pin SSOP (150 mil), Lead-Free
Product

APPLICATIONS
D
D
D
D
D
D
D

HDD + DVD Recorders
DVD Recorders
HDD Recorders
DVD Players
DVD Add-On Cards for Multimedia PCs
Digital HDTV Systems
Set-Top Boxes

DESCRIPTION
The PLL1707† and PLL1708† are low cost, phase-locked
loop (PLL) multiclock generators. The PLL1707 and
PLL1708 can generate four system clocks from a 27-MHz
reference input frequency. The clock outputs of the
PLL1707 can be controlled by sampling frequency-control
pins and those of the PLL1708 can be controlled throughserial-mode control pins. The device gives customers bothcost and space savings by eliminating external
components and enables customers to achieve the very
low-jitter performance needed for high performance audio
DACs and/or ADCs. The PLL1707 and PLL1708 are ideal
for MPEG-2 applications which use a 27-MHz masterclock such as DVD recorders, HDD recorders, DVD
add-on cards for multimedia PCs, digital HDTV systems,
and set-top boxes.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible todamage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.
     ! "#$ !  %#&'"  ( $ (#" !
"  !%$"" ! %$ )$ $!  $*! ! #$ ! ! (( + ,(#"  %"$!!- ($!  $"$!!', "'#($ $! -  '' %$ $!Copyright  2002, Texas Instruments Incorporated

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SLES065 – DECEMBER 2002

FUNCTIONAL BLOCK DIAGRAM
(MS)
SR

(MC)
FS2

(MD)
FS1

CSEL

VCC AGND VDD1–3 DGND1–3

Mode Control Interface

Power Supply

Reset
PLL2
XT1
OSC

PLL1

XT2

MCKO1

( ): PLL1708

MCKO2

SCKO0

Divider

Divider

Divider

SCKO1

SCKO2

SCKO3

PACKAGE/ORDERING INFORMATIONPRODUCT

PACKAGEPACKAGE CODEOPERATIONTEMPERATURE
RANGE

PACKAGEMARKING

PLL1707DBQ

SSOP 20

20DBQ

–25°C
25°C to 85°C

PLL1707

PLL1708DBQ

SSOP 20

20DBQ

–25°C
25°C to 85°C

PLL1708

ORDERING
NUMBER

TRANSPORT
MEDIA

PLL1707DBQ

Tube

PLL1707DBQR

Tape and reel

PLL1708DBQTube

PLL1708DBQR

Tape and reel

ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PLL1705 AND PLL1706
Supply voltage: VCC, VDD1–VDD3

4V

Supply voltage differences: VCC, VDD1–VDD3±0.1 V

Ground voltage differences: AGND, DGND1–DGND3±0.1 V

Digital input voltage: FS1 (MD), FS2 (MC), SR (MS), CSEL

– 0.3 V to (VDD + 0.3) V

Analog input voltage, XT1, XT2– 0.3 V to (VCC + 0.3) V

Input current (any pins except supplies)±10 mA

Ambient temperature under bias

–40°C to 125°C

Storage temperature–55°C to 150°C

Junction temperature

150°C

Lead temperature (soldering)

260°C, 5 s

Package temperature (IR reflow, peak)
260°C(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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SLES065 – DECEMBER 2002

ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUT/OUTPUT
Logic input
VIH (1)
VIL (1)

Input logic level

IIH (1)
IIL (1)

Input logic current

CMOS compatible
0.7VDD
VIN = VDD
VIN = 0 V

Logic output
VOH (2)VOL (2)

3.6
0.3 VDD
65

100
±10

Vdc
µA

CMOS

Output logic level
PLL1707
SamplingSamling frequency
PLL1708

IOH = –4 mA
IOL = 4 mA

VDD – 0.4 V

Standard fS

32

Double fS
Half fS
Standard fS

Vdc
0.4
44.1

48

64

88.2

96

16

22.05

24

32

44.1

48

Vdc

kHz

Double fS
64
88.2
96
MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin)
Master clock frequency
VIH
VIL

Input level(3)

IIH
IIL

Input current(3)

26.73

±10

VIN = VCC
VIN = 0 V

±10

MHz
V
µA

3.5

Vp-p

Output rise time

20% to 80% of VDD

2.0

ns

Output fall time

80% to 20% of VDD

2.0

For crystal oscillation

Duty cycle

45%

For external clock51%
50

Power-up time (6)

0.5

SCKO1

PLL1707

SCKO2
Out ut system clock
Outputfrequency
q
y

SCKO1
SCKO3

ms

33.8688
24.576

256 fS

8.192

12.28836.86424.576384 fS12.28818.43236.86433.8688

Selectable for 48 kHz

12.28824.57636.864256 fS

4.096

12.28824.576384 fS

6.144

18.43236.864

Output rise time

20% to 80% of VDD

2.0

Output fall time

80% to 20% of VDD

2.0

Output duty cycleps
1.5

Selectable for 48 kHz

Fixed
PLL1708

SCKO2

ns
55%

50%

Clock jitter (5)PLL AC CHARACTERISTICS (SCKO0–SCKO3) (fM = 27 MHz, CL = 20 pF on measurement pin)
SCKO0
Fixed

SCKO0

27.27
0.3 VCC

Output voltage (4)

SCKO3

27

0.7 VCC

45

50

MHz

ns
ns
55

%

(1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)(2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1(3) Pin 10: XT1(4) Pin 11: XT2(5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.
(6) The delay time from power on to oscillation(7) The settling time when the sampling frequency is changed(8) The delay time from power on to lockup(9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.
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SLES065 – DECEMBER 2002

ELECTRICAL CHARACTERISTICS (continued)
all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)
PARAMETERTEST CONDITIONS

Output clock jitter (5)Frequency Settling Time(7)Power-up time (8)

TYP

MAX

UNIT

SCKO0, SCKO1

MIN

58

100

ps

SCKO2, SCKO3

50

100

ps

PLL1707, to stated output frequency

50

150

PLL1708, to stated output frequency

80

300

To stated output frequency

3

6

ms

3.3

ns

POWER SUPPLY REQUIREMENTS
VCC, VDD
IDD + ICC

Supply voltage range

3.6

Vdc

Supply current (9)VDD = VCC = 3.3 V, fS = 48 kHz
Power down(10)

2.7

19

25

mA

350

550

µA

Power dissipation

VDD = VCC = 3.3 V, fS = 48 kHz

63

90

mW

85

°C

TEMPERATURE RANGE
Operating temperature

–25

θJA
Thermal resistance
PLL1707/8DBQ: 20-pin SSOP (150 mil)
150
°C/W
(1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)(2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1(3) Pin 10: XT1(4) Pin 11: XT2(5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.
(6) The delay time from power on to oscillation(7) The settling time when the sampling frequency is changed(8) The delay time from power on to lockup(9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.

PIN ASSIGNMENTS
PLL1707(TOP VIEW)

VDD1
SCKO2
SCKO3
DGND1
FS1
FS2
SR
VCC
AGND
XT1

4

1
2
3
4
5
6
7
8
9
10

PLL1708(TOP VIEW)
20
19
18
17
16
15
14
13
12
11

VDD3
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
VDD2
CSEL
XT2

VDD1
SCKO2
SCKO3
DGND1
MD
MC
MS
VCC
AGND
XT1

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

VDD3
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
VDD2
CSEL
XT2

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SLES065 – DECEMBER 2002

PLL1707 Terminal Functions
TERMINAL
I/O

DESCRIPTION

NAME

NO.

AGND

9

–

Analog ground

CSEL

12

I

SCKO1 frequency selection control(1)

DGND1

4

–

Digital ground 1

DGND2

16

–

Digital ground 2

DGND3

17

–

Digital ground 3

FS1

5

I

Sampling frequency group control 1(1)

FS2

6

I

Sampling frequency group control 2(1)

MCKO1

14

O

27-MHz master clock output 1

MCKO2

15

O

27-MHz master clock output 2

SCKO0

18

O

System clock output 0 (33.8688 MHz fixed)

SCKO1

19

O

System clock output 1 (selectable for 48 kHz)

SCKO2

2

O

System clock output 2 (256 fS selectable)

SCKO3

3

O

System clock output 3 (384 fS selectable)

SR

7

I

Sampling rate control(1)

VCC

8

–

Analog power supply, 3.3 V

VDD1

1

–

Digital power supply 1, 3.3 V

VDD2

13

–

Digital power supply 2, 3.3 V

VDD3

20

–

Digital power supply 3, 3.3 V

XT1

10

I

27-MHz crystal oscillator, or external clock input

XT2

11

O

27-MHz crystal oscillator, must be OPEN for external clock input mode

(1) Schmitt-trigger input with internal pulldown.

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SLES065 – DECEMBER 2002

PLL1708 Terminal Functions
TERMINAL
I/O

DESCRIPTION

NAME

NO.

AGND

9

–

Analog ground

CSEL

12

I

SCKO1 frequency selection control(1)

DGND1

4

–

Digital ground 1

DGND2

16

–

Digital ground 2

DGND3

17

–

Digital ground 3

MC

6

I

Bit clock input for serial control(1)

MCKO1

14

O

27-MHz master clock output 1

MCKO2

15

O

27-MHz master clock output 2

MD

5

I

Data input for serial control(1)

MS

7

I

Chip select input for serial control(1)

SCKO0

18

O

System clock output 0 (33.8688 MHz fixed)

SCKO1

19

O

System clock output 1 (selectable for 48 kHz)

SCKO2

2

O

System clock output 2 (256 fS selectable)

SCKO3

3

O

System clock output 3 (384 fS selectable)

VCC

8

–

Analog power supply, 3.3 V

VDD1

1

–

Digital power supply 1, 3.3 V

VDD2

13

–

Digital power supply 2, 3.3 V

VDD3

20

–

Digital power supply 3, 3.3 V

XT1

10

I

27-MHz crystal oscillator, or external clock input

XT2

11

O

27-MHz crystal oscillator, must be OPEN for external clock input mode

(1) Schmitt-trigger input with internal pulldown.

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SLES065 – DECEMBER 2002

TYPICAL PERFORMANCE CURVESJITTERvsLOAD CAPACITANCEJITTERvsSAMPLING FREQUENCY
70

70

65

MCKO1

SCKO0

SCKO2

MCKO2

SCKO1

SCKO3

65
SCKO1
Jitter – psrms

Jitter – psrms

SCKO0

60

60

55

SCKO3

55
SCKO2

50

50

45

45
MCKO2

MCKO1
40

40
30

40

50

60

70

80

90

0

100

5

fS – Sampling Frequency – kHz

Figure 1

70

65

SCKO1

SCKO1

SCKO0

SCKO0
Jitter – psrms

Jitter – psrms

SCKO3

60

60

SCKO3
MCKO2

55
MCKO2
50

50

45

40
2.7

20

JITTERvs
FREE-AIR TEMPERATURE

70

55

15

Figure 2

JITTERvsSUPPLY VOLTAGE

65

10

CL – Load Capacitance – pF

3.0

3.3

VCC – Supply Voltage – V

Figure 3

45

MCKO1

SCKO2

3.6

40
–50

MCKO1

SCKO2

–25

0

25

50

75

100

TA – Free-Air Temperature – °C

Figure 4

NOTE: All specifications at TA = 25°C, VDD1–3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency(33.8688 MHz for SCKO0, 36.864 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin,
unless otherwise noted.

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SLES065 – DECEMBER 2002

DUTY CYCLEvsSUPPLY VOLTAGE

DUTY CYCLE
vsFREE-AIR TEMPERATURE

55

55

54

54
MCKO1

52
Duty Cycle – %

53

MCKO2
SCKO2

52
Duty Cycle – %

53

51
50
49
48

SCKO1

SCKO3

50
49
48

SCKO0

47

46

46
3.0

3.3

VCC – Supply Voltage – V

Figure 5

SCKO2

51

47

45
2.7

MCKO2
SCKO1

MCKO1

3.6

45
–50

SCKO0

–25

0

25

SCKO3

50

75

100

TA – Free-Air Temperature – °C

Figure 6

NOTE: All specifications at TA = 25°C, VDD1–3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency(33.8688 MHz for SCKO0, 36.864 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin,
unless otherwise noted.

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SLES065 – DECEMBER 2002

THEORY OF OPERATIONMASTER CLOCK AND SYSTEM CLOCK OUTPUT
The PLL1707/8 consists of a dual PLL clock and master clock generator which generates four system clocks and two
buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1707/8. The PLL isdesigned to accept a 27-MHz master clock.
SCKO3
384 fSCounter N
SCKO0–3
Frequency
Control

Phase Detector
andLoop Filter

Divider
VCO

Counter M
Divider
PLL2

PLL1

Counter M
Phase Detector
andLoop Filter

VCO

Counter N
OSC

XT1 XT2 MCKO1
27 MHzDivider

MCKO2
27 MHzSCKO033.8688 MHz

SCKO1
36.864/24.576 MHz(36.864/24.576 MHz)(18.432/12.288 MHz)

SCKO2
256 fS( ): PLL1708

Figure 7. Block Diagram

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SLES065 – DECEMBER 2002

The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to
XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,and Figure 9 illustrates the 27-MHz master clock timing requirement.

MCKO2

MCKO2

MCKO1

MCKO1

27-MHzInternal
Master
Clock

XT1
C1

CrystalCrystalOSC
Circuit

XT1

External
Clock

CrystalOSC
Circuit

XT2

27-MHzInternal
Master
Clock

XT2

C2
PLL1707/PLL1708

PLL1707/PLL1708
C1, C2 = 10 pF to 33 pF
Crystal Resonator Connection

External Clock Input Connection

Figure 8. Master Clock Generator Connection Diagramt(XT1H)
0.7 VCC
XT1
0.3 VCCt(XT1L)DESCRIPTIONSYMBOL

MIN

Master clock pulse duration HIGHt(XT1H)t(XT1L)

10

ns

10

ns

Master clock pulse duration LOW

MAX

UNIT

Figure 9. External Master Clock Timing Requirement
The PLL1707/8 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs
256 fS, 384 fS 512 fS, or 768 fS (fS = 48 kHz) which is selected by hardware or software control. The output frequency of
the remaining clocks is determined by the sampling frequency (fS) under hardware or software control. SCKO2 and SCKO3
output 256-fS and 384-fS system clocks, respectively. Table 2 shows each sampling frequency which can be programmed.
The system clock output frequencies for programmed sampling frequencies are shown in Table 3. The half sampling
frequencies on SCKO2 and SCKO3 and 256 fS and 384 fS on SCKO1 are supported only on the PLL1708.

Table 1. Generated System Clock SCKO1 FrequencyfS
256 fS†384 fS†SCKO1 FREQUENCY

512 fS

24.576 MHz

768 fS

36.864 MHz† PLL1708 only
10

12.288 MHz
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SLES065 – DECEMBER 2002

Table 2. Sampling Frequencies
SAMPLING RATESAMPLING FREQUENCY (kHz)Half sampling frequencies†

16

22.05

24

Standard sampling frequencies

32

44.1

48

Double sampling frequencies

64

88.2

96

† PLL1708 only

Table 3. Sampling Frequencies and System Clock Output Frequencies
256 fSSCKO2 (MHZ)

384 fS
SCKO3 (MHZ)

SAMPLING FREQUENCY (kHz)SAMPLING RATE

16†
22.05†
24†

Half

4.096

6.144

Half

5.64488.4672

Half

6.144

9.216

32

Standard

8.192

12.28844.1

Standard

11.2896

16.9344

48

Standard

12.28818.43264

Double16.38424.57688.2

Double22.5792

33.8688

96

Double24.57636.864† PLL1708 only

Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time fromsampling frequency change to SCKO settling is 300 ns maximum. Figure 10 illustrates SCKO transient timing in the
PLL1708.
MS

300 ns
1–2 Clocks of MCKO1, 2
SCKO2
SCKO3

SCKO0
SCKO1

StableClock Transition Region

Stable33.8688 , 36.864, or 24.576 MHz

Figure 10. System Clock Transient Timing
The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 11 illustrates SCKO transient
timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External buffers are recommended on
all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.

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SLES065 – DECEMBER 2002

SR
FS2, 1
CSEL
150 ns
50 ns
SCKO1
SCKO2
SCKO3

StableSCKO0

Clock Transition Region

Stable33.8688 MHz

Figure 11. SCKO Transient Timing

POWER-ON RESET
The PLL1707/8 has an internal power-on reset circuit. The mode register of the PLL1708 is initialized with default settingsby power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power-up time.
Initialization by internal power-on reset is done automatically during 1024 master clocks at VDD > 2.0 V (TYP). Power-on
reset timing is shown in Figure 12.
VDD
2.4 V
2.0 V
1.6 V

Reset
Internal Reset1024 Master Clocks
Master Clock

Figure 12. Power-On Reset Timing

12

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SLES065 – DECEMBER 2002

FUNCTION CONTROLThe built-in functions of the PLL1707 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1(pin 5) and FS2 (pin 6). The PLL1708 can be controlled in the serial mode (software mode), which has a three-wire interface
using MS (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4.

Table 4. Selectable Functions
SELECTABLE FUNCTIONPARALLEL MODESERIAL MODE

Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)

Yes

Yes

Sampling rate select (standard/double)

Yes

Yes

Sampling rate select (half)

No

Yes

Each clock output enable/disable

No

Yes

Power down

No

Yes

SCKO1 configuration

No

Yes

PLL1707 (Parallel Mode)In the parallel mode, the following functions can be selected:

Sampling Frequency Group SelectThe sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6).
FS2 (PIN 6)

FS1 (PIN 5)

LOW

LOW

SAMPLING FREQUENCY
48 kHzLOW

HIGH

44.1 kHz

HIGH

LOW

32 kHzHIGH

HIGH

Reserved

Sampling Rate SelectThe sampling rate can be selected by SR (pin 7)
SR (PIN 7)

SAMPLING RATELOWStandard

HIGH

DoubleSystem Clock SCKO1 Frequency SelectSystem clock SCKO1 frequency can be selected by CSEL (pin 12).
CSEL (PIN 12)

SCKO1 FREQUENCY

LOW

36.864 MHz

HIGH

24.576 MHz

PLL1708 (Serial Mode)
The built-in functions of the PLL1708 are shown in Table 5. These functions are controlled using the MS, MC, and MD serial
control signals.

Table 5. Selectable Functions
SELECTABLE FUNCTION

DEFAULT

Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)

48-kHz group

Sampling rate select (half, standard, double)

Standard

Each clock output enable/disable

EnabledPower down

Disabled

SCKO1 configuration

36.864 MHz, 24.576 MHz
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SLES065 – DECEMBER 2002

Program-Register Bit Mapping
The built-in functions of the PLL1708 are controlled through a 16-bit program register. This register is loaded using MD,
MC and MS. After the 16 data bits are clocked in using the rising edge of MC, MS is used to latch the data into the register.
Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in
Figure 13 and Figure 14, respectively.
MS

MC

MD

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 13. Serial Mode Control Formatt(MHH)t(MSL)MS

VDD/2

t(MSS)t(MCH)t(MCL)t(MSS)t(MSH)MC

VDD/2t(MCY)

MD

MSB

LSB

VDD/2

t(MDH)t(MDS)DESCRIPTIONSYMBOLMINt(MCY)t(MCL)

100

ns

40

ns

t(MCH)t(MDH)

40

ns

40

ns

t(MDS)t(MSL)

40

MS low-level time

16ns
MC clocks(1)MS high-level time
MS hold time(2)t(MHH)t(MSH)

200

ns

40

ns

MC pulse cycle time
MC pulse duration LOW
MC pulse duration HIGH
MD hold time
MD setup time

TYP

MS setup time(3)t(MSS)
40(1) MC clocks: MC clock period(2) MC rising edge for LSB to MS rising edge
(3) MS rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any MS rise time is accepted.

Figure 14. Control Data Input Timing

14

MAX

UNIT

ns

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SLES065 – DECEMBER 2002

Mode Register
D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

1

1

1

0

0

CE6

CE5

CE4

CE3

CE2

CE1

SR2

SR1

FS2

FS1

Table 6. Mode Register Mapping
REGISTER

Mode control

BIT NAME

DESCRIPTION

CE6

MCKO2 output enable/disable

CE5

MCKO1 output enable/disable

CE4

SCKO1 output enable/disable

CE3

SCKO3 output enable/disable

CE2

SCKO2 output enable/disable

CE1

SCKO0 output enable/disable

SR[2:1]

Sampling rate selectFS[2:1]

Sampling frequency selectFS[2:1]: Sampling Frequency Group Select
FS2

FS1

SAMPLING FREQUENCY0048 kHz (default)

01

44.1 kHz1

0

32 kHz1

1

Reserved

SR[2:1]: Sampling Rate Select
SR2

SR1

SAMPLING RATE

00Standard (default)

0

1

Double

1

0

Half

1

1

Reserved

CE [6:1]: Clock Output Control
CE1–CE6

CLOCK OUTPUT CONTROL

0

Clock output disable

1

Clock output enable (default)

While all the bits of CE [6:1] are 0, the PLL1708 goes into the power-down mode, all dynamic operation including PLLs
and the oscillator halts, but serial mode control is enabled for resumption.

15


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SLES065 – DECEMBER 2002

Configuration Register
D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

1

1

0

1

1

RSV

RSV

RSV

RSV

RSV

CFG1

RSV

RSV

RSV

RSV

Table 7. Configuration Register Mapping
REGISTER
Configuration

BIT NAME

DESCRIPTIONRSVReserved, must be 0

CFG1

SCKO1 configuration

CFG1: SCKO1 Configuration Control
CFG1

CONFIGURATION 1

036.864 MHz, 24.576 MHz for SCKO1 (default)

1

18.432 MHz, 12.288 MHz for SCKO1

The system clock SCKO1 frequency can be selected by CSEL (pin 12) and CFG1 (register).
CFG1(REGISTER)CSEL(PIN 12)

SCKO1

0

LOW

36.864 MHz

0

HIGH

24.576 MHz

1

LOW

18.432 MHz

1

HIGH

12.288 MHz

CONNECTION DIAGRAM
Figure 15 shows the typical connection circuit for the PLL1707. There are four grounds for digital and analog power
supplies. However, the use of one common ground connection is recommended to avoid latch-up or otherpower-supply-related troubles. Power supplies should be bypassed as close as possible to the device.

MPEG-2 APPLICATIONS
Typical applications for the PLL1707/8 are MPEG-2 based systems such as DVD recorders, HDD recorders, DVD players,
DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1707/8 provides audio system
clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, ADC(s), and DAC(s) from a 27-MHz video clock.

16


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SLES065 – DECEMBER 2002

3.3 V

(2)
PLL1707/8
1

VDD1

VDD3

20

2

SCKO2

SCKO1

19

3

SCKO3

SCKO0

18

4

DGND1

DGND3

17

5

FS1 (MD)

DGND2

16

6

FS2 (MC)

MCKO2

15

7

SR(MS)

MCKO1

14

8

VCC

VDD2

13

9

AGND

CSEL

12

XT2

11

(1)

(1)

(4)

(1)

(2)

(1)

10 XT1(3)(3)

Clock Outputs (5)(1) 0.1-µF ceramic capacitor typical, depending on quality of power supply and pattern layout(2) 10-µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout(3) 27-MHz quartz crystal and 10–33 pF × 2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2(4) This connection is for PLL1707 (parallel mode); when PLL1708 (serial mode) is to be used, control pins must be connected to serial interfaced
controller.
(5) For good jitter performance, minimize the load capacitance on the clock output. It is recommended to drive the clock outputs through buffers,
especially if there are heavy loads on SCKO0 and SCKO1, and to minimize mutual interference by separating them or inserting a guard pattern
between them.

Figure 15. Typical Connection Diagram

17


www.ti.com

SLES065 – DECEMBER 2002

BLOCK DIAGRAM OF DVD PLAYER APPLICATION
PLL1707/8
SCKO3

27 MHzCrystalSCKO2
MCKO1/2

384 fS

256 fS
27 MHz

SCKO0

Front
CD-DA/DVD DSP

MPEG/AC-3
Audio Decoder

Surround
PCM/DSD1608

Center, Subwoofer
Down Mix

BLOCK DIAGRAM OF HDD+DVD RECORDER APPLICATION

MPEG
Encoder

PCM1802

SCKO1
PLL1707/8
MCKO1/2

XTI

SCKO2, 3

MPEG
Decoder

PCM1742

27-MHz Master Clock

18

PACKAGE OPTION ADDENDUM
www.ti.com

3-Mar-2010

PACKAGING INFORMATION
Orderable Device

Status (1)Package
Type

Package
Drawing

Pins Package Eco Plan (2)Qty

Lead/Ball Finish

MSL Peak Temp (3)

PLL1707DBQ

ACTIVE

SSOP/
QSOP

DBQ

20

50

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMPLL1707DBQG4ACTIVE

SSOP/
QSOP

DBQ

20

50

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMPLL1707DBQR

ACTIVE

SSOP/
QSOP

DBQ

20

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMPLL1707DBQRE4ACTIVE

SSOP/
QSOP

DBQ

20

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMPLL1707DBQRG4ACTIVE

SSOP/
QSOP

DBQ

20

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMPLL1708DBQ

ACTIVE

SSOP/
QSOP

DBQ

20

50

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMPLL1708DBQG4ACTIVE

SSOP/
QSOP

DBQ

20

50

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMPLL1708DBQR

ACTIVE

SSOP/
QSOP

DBQ

20

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMPLL1708DBQRG4ACTIVE

SSOP/
QSOP

DBQ

20

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

11-Mar-2008

TAPE AND REEL INFORMATION*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
Diameter Width(mm) W1 (mm)

PLL1707DBQR

SSOP/
QSOP

DBQ

20

2000

330.0

PLL1708DBQR

SSOP/
QSOP

DBQ

20

2000

330.0

A0 (mm)

B0 (mm)

K0 (mm)

P1
(mm)

W
Pin1
(mm) Quadrant

16.4

6.5

9.0

2.1

8.0

16.0

Q1

16.4

6.5

9.0

2.1

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

11-Mar-2008*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

PLL1707DBQR

SSOP/QSOP

DBQ

20

2000

346.0

346.0

33.0

PLL1708DBQR

SSOP/QSOP

DBQ

20

2000

346.0

346.0

33.0

Pack Materials-Page 2

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