±5ppm, I2C Real-Time ClockDS3231M

General Description

The DS3231M is a low-cost, extremely accurate, I2C realtime clock (RTC). The device incorporates a battery input
and maintains accurate timekeeping when main power tothe device is interrupted. The integration of the microelectromechanical systems (MEMS) resonator enhances thelong-term accuracy of the device and reduces the piecepart count in a manufacturing line. The DS3231M is available in the same footprint as the popular DS3231 RTC.
The RTC maintains seconds, minutes, hours, day, date,month, and year information. The date at the end of themonth is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. Two programmable time-ofday alarms and a 1Hz output are provided. Address anddata are transferred serially through an I2C bidirectional
bus. A precision temperature-compensated voltage reference and comparator circuit monitors the status of VCC
to detect power failures, to provide a reset output, and toautomatically switch to the backup supply when necessary. Additionally, the RST pin is monitored as a pushbutton
input for generating a microprocessor reset. See theBlock Diagram for more details.

Applications

Benefits and Features●● Highly Accurate RTC With Integrated MEMS
Resonator Completely Manages All Timekeeping
Functions• Complete Clock Calendar Functionality Including
Seconds, Minutes, Hours, Day, Date, Month, andYear, with Leap-Year Compensation Up to Year2100
• Timekeeping Accuracy ±5ppm (±0.432 Second/Day)
from -45°C to +85°C• Footprint and Functionally Compatible to DS3231• Two Time-of-Day Alarms• 1Hz and 32.768kHz Outputs• Reset Output and Pushbutton Input with Debounce• Digital Temp Sensor with ±3°C Accuracy• +2.3V to +5.5V Supply Voltage●● Simple Serial Interface Connects to Most
Microcontrollers• Fast (400kHz) I2C Interface●● Battery-Backup Input for Continuous Timekeeping• Low Power Operation Extends Battery-Backup
Run Time●● Operating Temperature Range: -40°C to +85°C●● 8-Pin or 16-Pin SO Packages●● Underwriters Laboratories® (UL) RecognizedPower Meters

Typical Operating Circuit

Industrial Applications

Ordering InformationPART

TEMP RANGE

PIN-PACKAGE

DS3231MZ+-45NC to +85NC

8 SO

DS3231MZ/V+-45NC to +85NC

8 SO

DS3231M+-45NC to +85NC

16 SO+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.

+3.3V

I/O PORTCPU

19-5312; Rev 7; 3/15

SCL
SDA
32KHZ

INTERRUPTS

Underwriters Laboratories is a registered certification mark of
Underwriters Laboratories Inc.

+3.3V

VBAT

INT/SQW
RST
DS3231M

±5ppm, I2C Real-Time ClockDS3231M

Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND.........-0.3V to +6.0V
Operating Temperature Range........................... -45NC to +85NC
Storage Temperature Range............................. -55NC to +125NC

Junction Temperature......................................................+150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Package Thermal Characteristics (Note 1)
8 SO
Junction-to-Ambient Thermal Resistance (qJA).........120°C/W

16 SO
Junction-to-Ambient Thermal Resistance (qJA)...........90°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Recommended Operating Conditions(TA = -45NC to +85NC, unless otherwise noted.) (Note 2)
PARAMETER

MIN

TYP

MAX

VCC

2.3

3.3

5.5

VBAT

2.3

3.0

5.5

Logic 1

VIH

0.7 x
VCC

VCC +
0.3

V

Logic 0

VIL

-0.3

0.3 x
VCC

V

Supply Voltage

SYMBOL

CONDITIONS

UNITS
V

Electrical Characteristics—Frequency And Timekeeping(VCC or VBAT = +3.3V, TA = -45NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, andTA = +25NC, unless otherwise noted.)
PARAMETER
1Hz Frequency Tolerance

SYMBOL

CONDITIONS

Df/fOUT

Measured over R 10s interval

MIN

TYP

MAX

UNITS

Q5

ppm

1Hz Frequency Stability vs. VCC
Voltage

Df/V

Timekeeping AccuracytKA

Q0.432

Seconds/
Day

Df/fOUT

Q2.5%

32kHz Frequency Tolerance

ppm/V

Q1

DC Electrical Characteristics—General(VCC = +2.3V to +5.5V, TA = -45NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and TA =+25NC, unless otherwise noted.)
PARAMETERSYMBOL

Active Supply Current(I2C Active: Includes
Temperature Conversion Current)

ICCA

Standby Supply Current(I2C Inactive: Includes
Temperature Conversion Current)

ICCS

Temperature Conversion Current(I2C Inactive)

ICCSCONV

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CONDITIONS

MIN

TYP

MAX

VCC = +3.63V

200

VCC = VCCMAX

300

VCC = +3.63V

130

VCC = VCCMAX

200

VCC = +3.63V

575

VCC = VCCMAX

650

UNITS
µA

µA

µA

Maxim Integrated │ 2

±5ppm, I2C Real-Time ClockDS3231M

DC Electrical Characteristics—General (continued)(VCC = +2.3V to +5.5V, TA = -45NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and TA =+25NC, unless otherwise noted.)
PARAMETERSYMBOL

MIN

TYP

MAX

UNITS

2.45

2.575

2.70

V

IOL = 3mA

0.4

V

IOL = 1mA

0.4

V

-0.1

+0.1

µA

ILI

-0.1

+0.1

µA

IOL

-200

+10

µA

100

nA

Power-Fail Voltage

VPF

Logic 0 Output(32KHZ, INT/SQW, SDA)

VOL

Logic 0 Output
(RST)

VOL

Output Leakage(32KHZ, INT/SQW, SDA)

ILO

Input Leakage(SCL)
RST I/O Leakage
VBAT Leakage

IBATLKG

Temperature Accuracy

TEMPACC

CONDITIONS

25
VCC or VBAT = +3.3V

Q3

NC

Temperature Conversion Time

tCONV

10

ms

Pushbutton Debounce

PBDB

250

ms

Reset Active Time

tRST

250

Oscillator Stop Flag (OSF) DelaytOSF(Note 3)

125

ms
200

ms

DC Electrical Characteristics—VBAT Current Consumption(VCC = 0V, VBAT = +2.3V to +5.5V, TA = -45NC to +85NC, unless otherwise noted. Typical values are at VCC = 0V, VBAT = +3.0V, andTA = +25NC, unless otherwise noted.)
PARAMETERSYMBOL

Active Battery Current(I2C Active) (Note 4)

IBATA

Timekeeping Battery Current(I2C Inactive) (Note 4)

IBATT

Temperature Conversion Current(I2C Inactive)

IBATTC

Data Retention Current(Oscillator Stopped and I2CInactive)

IBATDR

CONDITIONS

MIN

TYP

MAX

VBAT = +3.63V

70

VBAT = VBATMAX

150

VBAT = +3.63V, EN32KHZ = 02

3.0

VBAT = VBATMAX, EN32KHZ = 0

2

3.5

UNITS
µA
µA

VBAT = +3.63V

575

VBAT = VBATMAX

650

TA = +25NC

100

nA

MAX

UNITS

µA

AC Electrical Characteristics—Power Switch(TA = -45NC to +85NC, unless otherwise noted.) (Figure 2)
PARAMETERSYMBOL

CONDITIONS

MIN

TYP

VCC Fall Time, VPFMAX to
VPFMIN

tVCCF

300

Fs

VCC Rise Time, VPFMIN to
VPFMAX

tVCCR

0

Fs

Recovery at Power-Up

tREC

www.maximintegrated.com(Note 5)

250

300

ms

Maxim Integrated │ 3

±5ppm, I2C Real-Time ClockDS3231M

AC Electrical Characteristics—I2C Interface(VCC or VBAT = +2.3V to +5.5V, TA = -45NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, andTA = +25NC, unless otherwise noted.) (Note 6, Figure 1)
PARAMETERSYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

400

kHz

SCL Clock Frequency

fSCL

0

Bus Free Time Between STOP
and START Conditions

tBUF

1.3

Fs

Hold Time (Repeated) START
Condition

tHD:STA

0.6

Fs

Low Period of SCL

tLOW

1.3

Fs

High Period of SCL

tHIGH

0.6

Data Hold TimetHD:DAT0

Data Set-Up TimetSU:DAT

100

ns

START Set-Up TimetSU:STA

0.6

Fs

SDA and SCL Rise TimetR

(Note 7)

20 +
0.1CB

300

ns

SDA and SCL Fall TimetF

(Note 7)

20 +
0.1CB

300

ns

STOP Set-Up TimetSU:STO

SDA, SCL Input Capacitance

CBIN

Fs
0.9

0.6
(Note 8)

Fs

Fs
10

pF

Note 2: All voltages are referenced to ground.
Note 3: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set.
Note 4: Includes the temperature conversion current (averaged).
Note 5: This delay applies only if the oscillator is enabled. If the EOSC bit is 1, tREC is bypassed and RST immediately goes high.
The state of RST does not affect the I2C interface or RTC functions.
Note 6: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with standard modeI2C timing.
Note 7: CB: Total capacitance of one bus line in picofarads.
Note 8: Guaranteed by design; not 100% production tested.

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Maxim Integrated │ 4

±5ppm, I2C Real-Time ClockDS3231M

Timing Diagrams

SDA
tBUF
tF

tLOW

tHD:STAtSPSCL

tHD:STAtHIGH

tR
tHD:DAT

STOP

START

tSU:STAtSU:STOtSU:DATREPEATEDSTARTNOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.

Figure 1. I2C Timing

tVCCF

tVCCR

VPFMAXVPFMIN
VCC

tREC

RST

Figure 2. Power Switch Timing

RST

PBDB

tRST

Figure 3. Pushbutton Reset Timing

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Maxim Integrated │ 5

±5ppm, I2C Real-Time ClockDS3231M

Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)

VBAT = 2.3V, EN32KHZ = 1, IOUT = 0mA

140

+85°C

120
110
100

+25°C

90

-40°C

80

INCREASE BELOW VPF
DUE TO INTERNAL PULLUPRESISTOR ON RST

7060

VCC = 0V, EN32KHZ = 1, BBSQW = 0

3.5
SUPPLY CURRENT (µA)

+85°C
3.0

+25°C

2.5
2.0
1.5

50

-40°C

1.0
2

3

4

5

6

2

3

SUPPLY VOLTAGE (V)

0.2
0.1

6

0.3
0.2
0.1

0
4

6

8

10

1

2

3

4

5

200

4

LIMITS

2
0
-2
-4
-6
-8
-10
0

50

TEMPERATURE (°C)

100

TA = +25°C

190
180
SUPPLY CURRENT (µA)

FREQUENCY ERROR (ppm)6

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2

4

6

SUPPLY VOLTAGE (V)

POWER-SUPPLY CURRENT
vs. SCL FREQUENCY
DS3231M toc06

VCC = 3.3V

-50

0

OUTPUT CURRENT (mA)

FREQUENCY ERROR
vs. TEMPERATURE
8

TRACKS WITH VCC
200

OUTPUT CURRENT (mA)

10

3

DS3231M toc07

2

4

1

0
0

VBAT = 3.0V,
TA = +25°C

5
OUTPUT VOLTAGE (V)0.3

6

RST OUTPUT VOLTAGE
vs. POWER SUPPLY VOLTAGE

VCC = 2.45V,
VBAT = 3.0V,
TA = +25°C

0.4
OUTPUT VOLTAGE (V)OUTPUT VOLTAGE (V)

0.4

0.5

DS3231M toc03

VCC = 2.3V,
VBAT = 0V,
TA = +25°C

5

RST OUTPUT VOLTAGE
vs. OUTPUT CURRENT
DS3231M toc04

INT/SQW OUTPUT VOLTAGE
vs. OUTPUT CURRENT
0.5

4
SUPPLY VOLTAGE (V)DS3231M toc05

SUPPLY CURRENT (µA)

130

4.0

DS3231M toc01

150

BATTERY-SUPPLY CURRENT
vs. BATTERY-SUPPLY VOLTAGE
DS3231M toc02

POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE

170

+5.5V

160
150
140
130
120

+2.7V

110
100
90
80

+3.5V

0

100

200

300

400

SCL FREQUENCY (kHz)Maxim Integrated │ 6

±5ppm, I2C Real-Time ClockDS3231M

Pin Configuration
TOP VIEW

32KHZ 1+16 SCLVCC 2
INT/SQW 3

TOP VIEW

15 SDADS3231M

14 VBAT

32KHZ

1

RST 4

13 GND

VCC

2

N.C. 5

12 N.C.

INT/SQW

N.C. 6

11 N.C.

RST

N.C. 7

10 N.C.

N.C. 8

9

+

8 SCL
7

SDA

3

6

VBAT

4

5

GND

DS3231M

SO

N.C.

SO

Pin Description
PIN

NAME

FUNCTION

8 SO

16 SO

1

1

32KHZ

32.768kHz Output (50% Duty Cycle). This open-drain pin requires an external pullup resistor.
When enabled with the EN32KHZ bit in the Status register (0Fh), this output operates on either
power supply. This pin can be left open circuit if not used.

2

2

VCC

DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1FF to 1.0FF
capacitor. Connect to ground if not used.

INT/
SQW

Active-Low Interrupt or 1Hz Square-Wave Output. This open-drain pin requires an external pullup
resistor connected to a supply at 5.5V or less. It can be left open if not used. This multifunction
pin is determined by the state of the INTCN bit in the Control register (0Eh). When INTCN is set tologic 0, this pin outputs a 1Hz square wave. When INTCN is set to logic 1, a match between the
timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the alarm isenabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults toan interrupt output with alarms disabled.

RST

Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative
to the VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds
VPF, for tRST, the RST pin is pulled high by the internal pullup resistor. The active-low, open-drain
output is combined with a debounced pushbutton input function. This pin can be activated by apushbutton reset request. It has an internal 50kI (RPU) nominal value pullup resistor to VCC. No
external pullup resistors should be connected. If the oscillator is disabled, tREC is bypassed and
RST immediately goes high.

3

3

4

4

—

5–12

N.C.

No Connection. These pins must be connected to ground.

5

13

GND

GroundVBAT

Backup Power-Supply Input. When using the device with the VBAT input as the primary power source,
this pin should be decoupled using a 0.1FF to 1.0FF low-leakage capacitor. When using the device
with the VBAT input as the backup power source, the capacitor is not required. If VBAT is not used,connect to ground. The device is UL recognized to ensure against reverse charging when used with a
primary lithium battery. Go to www.maximintegrated.com/qa/info/ul for more information.

6

14

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Maxim Integrated │ 7

±5ppm, I2C Real-Time ClockDS3231M

Pin Description (continued)
PIN

NAME

FUNCTION

15

SDA

Serial-Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain
pin requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of thevoltage on VCC.

16

SCL

Serial-Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize
data movement on the serial interface. The pullup voltage can be up to 5.5V, regardless of thevoltage on VCC.

8 SO

16 SO

7

8

Block Diagram
32KHZ
DIVIDER

DS3231M

N

INT/SQW
1Hz

TIME-BASERESONATOR

VBAT
VCC
RPU

POWER
CONTROL

INTERRUPT
OR 1Hz
SELECTN

DIGITAL
ADJUSTMENT

RST
TEMP
SENSORN

FACTORY TRIM

GND
SDA
SCL

Detailed Description

I2C
INTERFACE

CONTROL AND STATUS
REGISTERSThe DS3231M is a serial real-time clock (RTC) driven by
an internal, temperature-compensated, microelectromechanical systems (MEMS) resonator. The oscillator provides a stable and accurate reference clock and maintains the RTC to within Q0.432 seconds-per-day accuracy from -45NC to +85NC. The RTC is a low-power clock/calendar with two programmable time-of-day alarms. INT/SQW provides either an interrupt signal due to alarm
conditions or a 1Hz square wave. The clock/calendar
provides seconds, minutes, hours, day, date, month, andyear information. The date at the end of the month is automatically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates inwww.maximintegrated.com

CLOCK/CALENDAR
WITH ALARM

either the 24-hour or 12-hour format with an AM/PM indicator. The internal registers are accessible though an I2C
bus interface. A temperature-compensated voltage reference and comparator circuit monitors the level of VCC todetect power failures and to automatically switch to the
backup supply when necessary. The RST pin provides
an external pushbutton function and acts as an indicatorof a power-fail event.

Operation

The Block Diagram shows the device’s main elements.
Each of the major blocks is described separately in thefollowing sections.

Maxim Integrated │ 8

±5ppm, I2C Real-Time ClockDS3231M

High-Accuracy Time Base

+3.3V

The temperature sensor, oscillator, and digital adjustment controller logic form the highly accurate time base.
The controller reads the output of the on-board temperature sensor and adjusts the final 1Hz output to maintainthe required accuracy. The device is trimmed at thefactory to maintain a tight accuracy over the operating
temperature range. When the device is powered by VCC,
the adjustment occurs once a second. When the device
is powered by VBAT, the adjustment occurs once every
10s to conserve power. Adjusting the 1Hz time base lessoften does not affect the device’s long-term timekeeping
accuracy. The device also contains an Aging Offset register that allows a constant offset (positive or negative) tobe added to the factory-trimmed adjustment value.

VCC

VBAT

Figure 4. Single Supply (VCC Only)

Power-Supply Configurations

VCC

The DS3231M can be configured to operate on a single
power supply (using either VCC or VBAT) or in a dualsupply configuration, which provides a backup supply
source to keep the timekeeping circuits alive during
absence of primary system power.

VBAT

Figure 4 illustrates a single-supply configuration using
VCC only, with the VBAT input grounded. When VCC < VPF,
the RST output is asserted (active low). Temperature
conversions are executed once per second.

Figure 5. Single Supply (VBAT Only)

Figure 5 illustrates a single-supply configuration using
VBAT only, with the VCC input grounded. The RST output
is disabled and is held at ground through the connectionof the internal pullup resistor. Temperature conversions
are executed once every 10s.

+3.3V

VCC

Figure 6 illustrates a dual-supply configuration, using
the VCC supply for normal system operation and the
VBAT supply for backup power. In this configuration, thepower-selection function is provided by a temperaturecompensated voltage reference and a comparator circuitthat monitors the VCC level. When VCC is greater than
VPF, the device is powered by VCC. When VCC is lessthan VPF but greater than VBAT, the device is powered

VBAT

Figure 6. Dual Power Supply

Table 1. Power Control
CONFIGURATIONCONDITIONVCC Only(Figure 4)

VCC > VPF

VBAT Only(Figure 5)

EOSC = 0

Dual Supply(Figure 6)

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VCC < VPF
EOSC = 1
VCC > VPF
VCC < VPF

I/O ACTIVE

I/O INACTIVE

ICCA

ICCS

Active (Low)

IBATT

IBATA

Disabled (Low)

IBATDRICCA

RSTInactive (High)ICCS

Inactive (High)VCC > VBATICCA

VCC > VBATICCS

VCC < VBATIBATA

VCC < VBAT

IBATT

Active (Low)

Maxim Integrated │ 9

DS3231M

by VCC. If VCC is less than VPF and is less than VBAT, thedevice is powered by VBAT (see Table 1).
When VCC < VPF, the RST output is asserted (active
low). When VCC is the presently selected power source,
temperature conversions are executed once per second.
When VBAT is the presently selected power source, temperature conversions are executed once every 10s.
To preserve the battery, the first time VBAT is applied
to the device the oscillator does not start up until VCC
exceeds VPF or until a valid I2C address is written to
the device. Typical oscillator startup time is less than1s. Approximately 2s after VCC is applied, or a valid
I2C address is written, the device makes a temperature
measurement and applies the calculated correction tothe oscillator. Once the oscillator is running, it continues
to run as long as a valid power source is available (VCC
or VBAT), and the device continues to measure the temperature and correct the oscillator frequency. On the first
application of VCC power, or (if VBAT powered) when avalid I2C address is written to the device, the time anddate registers are reset to 01/01/00 01 00:00:00 (DD/MM/YY DOW HH:MM:SS).

Initial VBAT Attachment
During the initial battery attachment to the DS3231M, it
is important to eliminate the effects of contact bounce.
Contact bounce occurs when battery contact rapidly
and repeatedly alternates between connected and disconnected during the battery attachment before finallysettling to the connected state. This bounce can cause amomentary power interruption to the DS3231M that can
result in memory recall corruption in the device.
There are two recommended ways to eliminate theeffects of contact bounce on the device. The preferred
way uses power sequencing by applying VCC to the part
before performing the battery attachment. An alternate
method to eliminate contact bounce is to filter the signal
using a small capacitor between VBAT and ground. For
this method, capacitor values between 0.1nf and 1nf arerecommended for the supply filtering.

VBAT Operation
There are several modes of operation that affect theamount of VBAT current that is drawn. While the device
is powered by VBAT and the serial interface is active,
the active battery current IBATA is drawn. When theserial interface is inactive, the timekeeping current IBATT(which includes the averaged temperature-conversion
current IBATTC) is used. The temperature-conversion
current IBATTC is specified since the system must be

www.maximintegrated.com±5ppm, I2C Real-Time Clockable to support the periodic higher current pulse andstill maintain a valid voltage level. The data-retention
current IBATDR is the current drawn by the device when
the oscillator is stopped (EOSC = 1). This mode can beused to minimize battery requirements for periods when
maintaining time and date information is not necessary,e.g., while the end system is waiting to be shipped to acustomer.

Pushbutton Reset Function
The device provides for a pushbutton switch to be connected to the RST input/output pin. When the device is
not in a reset cycle, it continuously monitors RST for a
low-going edge. If an edge transition is detected, thedevice debounces the switch by pulling RST low. Afterthe internal timer has expired (PBDB), the device continues to monitor the RST line. If the line is still low, thedevice continuously monitors the line looking for a risingedge. Upon detecting release, the device forces RST
low and holds it low for tRST. RST is also used to indicate a power-fail condition. When VCC is lower than VPF,
an internal power-fail signal is generated, which forces
RST low. When VCC returns to a level above VPF, RST
is held low for approximately 250ms (tREC) to allow thepower supply to stabilize. If the oscillator is not runningwhen VCC is applied, tREC is bypassed and RST immediately goes high. Assertion of the RST output, whether
by pushbutton or power-fail detection, does not affectthe device’s internal operation. RST output operation andpushbutton monitoring are only available if VCC power isavailable.

Real-Time Clock (RTC)
With the 1Hz source from the temperature-compensatedoscillator, the RTC provides seconds, minutes, hours,
day, date, month, and year information. The date at theend of the month is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or the
12-hour format with an AM/PM indicator. The clock provides two programmable time-of-day alarms. INT/SQW
can be enabled to generate either an interrupt due to an
alarm condition or a 1Hz square wave. This selection iscontrolled by the INTCN bit in the Control register.

I2C Interface

The I2C interface is accessible whenever either VCC or
VBAT is at a valid level. If a microcontroller connectedto the device resets because of a loss of VCC or otherevent, it is possible that the microcontroller and device’s
I2C communications could become unsynchronized,

Maxim Integrated │ 10

±5ppm, I2C Real-Time ClockDS3231M

Table 2. Timekeeping Registers
ADDRESS

BIT 7
MSB

00h

0

10 Seconds

01h

0

10 Minutes

BIT 6

BIT 5

AM/PM
02h

0

12/24

20
Hours

03h

0

0

0

04h

0

0

05h

Century

0

06h

BIT 4

BIT 3

BIT 2

0

RANGE

Seconds

Seconds

00–59

Minutes

Minutes

00–59

Hour

Hours

1–12 +
AM/PM
00–23

0

Day

1–7

Date

Day

Date

01–31

Month

Month/Century

01–12 +
Century

Year

Year

00–99
00–59

10 Date
10
Month

0

BIT 0
LSB

FUNCTION

10
Hours

BIT 1

10 Year07h

A1M1

10 Seconds

Seconds

Alarm 1
Seconds

08h

A1M2

10 Minutes

Minutes

Alarm 1
Minutes

00–59

09h

A1M3

12/24

Hour

Alarm 1 Hours

1–12 +
AM/PM
00–23

0Ah

A1M4

DY/DT

0Bh

A2M2

0Ch

A2M3

12/24

0Dh

A2M4

DY/DT

0Eh

BBSQW

CONV

NA

NA

INTCN

A2IE

A1IE

0Fh

EOSC
OSF

0

0

0

EN32KHZ

BSY

A2F

A1F

Status

—

10h

SIGN

DATA

DATA

DATA

DATA

DATA

DATA

DATA

Aging Offset

81h–7Fh

11h

SIGN

DATA

DATA

DATA

DATA

DATA

DATA

DATA

Temperature
MSB

—

12h

DATA

DATA

0

0

0

0

0

0

Temperature
LSB

—

AM/PM
20
Hours

10
Hours

Day

Alarm 1 Day

1–7

Date

Alarm 1 Date

1–31

Minutes

Alarm 2
Minutes

00–59

Hour

Alarm 2 Hours

1–12 +
AM/PM
00–23

Day

Alarm 2 Day

1–7

Alarm 2 Date

1–31

Control—

10 Date10 Minutes
AM/PM
20
Hours

10
Hours

10 Date

Date

Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.

e.g., the microcontroller resets while reading data fromthe device. When the microcontroller resets, the device’s
I2C interface can be placed into a known state by toggling SCL until SDA is observed to be at a high level. At
that point the microcontroller should pull SDA low while
SCL is high, generating a START condition.

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Address Map
Table 2 shows the address map for the device’s timekeeping registers. During a multibyte access, when theaddress pointer reaches the end of the register space(12h), it wraps around to location 00h. On an I2C STARTor address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The

Maxim Integrated │ 11

±5ppm, I2C Real-Time ClockDS3231M

time information is read from these secondary registers,
while the clock can continue to run. This eliminates theneed to reread the registers in case the main registers
update during a read.

Clock and Calendar
The time and calendar information is obtained by reading
the appropriate register bytes. Table 2 shows the RTC
registers. The time and calendar data are set or initialized
by writing the appropriate register bytes. The contents ofthe time and calendar registers are in the binary-coded
decimal (BCD) format. The device can be run in either
12-hour or 24-hour mode. Bit 6 of the Hours register isdefined as the 12-hour or 24-hour mode select bit. Whenhigh, the 12-hour mode is selected. In the 12-hour mode,
bit 5 is the AM/PM bit with logic-high being PM. In the
24-hour mode, bit 5 is the 20-hour bit (20–23 hours).
The century bit (bit 7 of the Month register) is toggled
when the Years register overflows from 99 to 00. The
day-of-week register increments at midnight. Values that
correspond to the day of week are user-defined but must
be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries resultin undefined operation. When reading or writing the timeand date registers, secondary buffers are used to prevent
errors when the internal registers update. When reading
the time and date registers, the secondary buffers aresynchronized to the internal registers on any I2C START
and when the register pointer rolls over to zero. The time
information is read from these secondary registers, while

the clock continues to run. This eliminates the need toreread the registers in case the main registers update
during a read. The countdown chain is reset whenever
the seconds register is written. Write transfers occur on
the acknowledge from the device. Once the countdown
chain is reset, to avoid rollover issues the remaining timeand date registers must be written within 1s.

AlarmsThe device contains two time-of-day/date alarms. Alarm
1 can be set by writing to registers 07h–0Ah. Alarm 2
can be set by writing to registers 0Bh–0Dh. See Table 2.
The alarms can be programmed (by the alarm enable
and INTCN bits in the Control register) to activate the
INT/SQW output on an alarm match condition. Bit 7 ofeach of the time-of-day/date alarm registers are mask
bits (Table 2). When all the mask bits for each alarm
are logic 0, an alarm only occurs when the values inthe timekeeping registers match the corresponding
values stored in the time-of-day/date alarm registers.
The alarms can also be programmed to repeat every
second, minute, hour, day, or date. Table 3 shows thepossible settings. Configurations not listed in the table
result in illogical operation. The DY/DT bits (bit 6 of thealarm day/date registers) control whether the alarm
value stored in bits 0–5 of that register reflects the dayof the week or the date of the month. If DY/DT is written
to logic 0, the alarm is the result of a match with date of
the month. If DY/DT is written to logic 1, the alarm is theresult of a match with day of the week.

Table 3. Alarm Mask Bits
DY/DT

ALARM 1 REGISTER MASK BITS (BIT 7)

ALARM RATE

A1M4

A1M3

A1M2

A1M1

X

1

1

1

1

Alarm once a second

X

1

1

1

0

Alarm when seconds match

X

1

1

0

0

Alarm when minutes and seconds match

X

1

0

0

0

Alarm when hours, minutes, and seconds match

0

0

0

0

0

Alarm when date, hours, minutes, and seconds match

1

0

0

0

0

Alarm when day, hours, minutes, and seconds match

DY/DT

ALARM 2 REGISTER MASK BITS (BIT 7)

ALARM RATE

A2M4

A2M3

A2M2

X

1

1

1

Alarm once per minute (00 seconds of every minute)

X

1

1

0

Alarm when minutes match

X

1

0

0

Alarm when hours and minutes match

0

0

0

0

Alarm when date, hours, and minutes match

1

0

0

0

Alarm when day, hours, and minutes match

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Maxim Integrated │ 12

±5ppm, I2C Real-Time ClockDS3231M

Control Register (0Eh)
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

EOSC
0

BBSQW

CONV

NA

NA

INTCN

A2IE

A1IE

0

0

1

1

1

0

0

BIT 7

EOSC: Enable oscillator. When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is
stopped when the device switches to VBAT. This bit is clear (logic 0) when power is first applied. When thedevice is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit. When the oscillator is disabled, all register data is static.

BIT 6

BBSQW: Battery-backed square-wave enable. When set to logic 1 with INTCN = 0 and VCC < VPF, this bit
enables the 1Hz square wave. When BBSQW is logic 0, INT/SQW goes high impedance when VCC falls below
VPF. This bit is disabled (logic 0) when power is first applied.

BIT 5

CONV: Convert temperature. Setting this bit to 1 forces the temperature sensor to convert the temperature
into digital code and execute the temperature compensate algorithm to update the oscillator’s accuracy. The
device cannot be forced to execute the temperature-compensate algorithm faster than once per second. A
user-initiated temperature conversion does not affect the internal update cycle. The CONV bit remains at a 1
from the time it is written until the temperature conversion is completed, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. See Figure 7 formore details.

BITS 4:3

NA: Not applicable. These bits have no affect on the device and can be set to either 0 or 1.

BIT 2

INTCN: Interrupt control. This bit controls the INT/SQW output signal. When the INTCN bit is set to logic 0, a
1Hz square wave is output on INT/SQW. When the INTCN bit is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to a logic
1 when power is first applied.

BIT 1

A2IE: Alarm 2 interrupt enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, theA2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.

BIT 0

A1IE: Alarm 1 interrupt enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, theA1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.

www.maximintegrated.com

Maxim Integrated │ 13

±5ppm, I2C Real-Time ClockDS3231M

VCC POWEREDINTERNAL 1Hz
CLOCK

BSY

CONV

THE USER SETS THE CONV BIT

THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSIONHAS COMPLETED

BSY IS HIGH DURING
THE TEMPERATURE CONVERSIONVBAT POWERED10 SECONDSINTERNAL 1Hz
CLOCK

BSY

CONV

THE USER SETS THE CONV BIT

THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSIONHAS COMPLETED

Figure 7. CONV Control Bit and BSY Status Bit Operationwww.maximintegrated.com

Maxim Integrated │ 14

±5ppm, I2C Real-Time ClockDS3231M

Status Register (0Fh)
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OSF

0

0

0

EN32KHZ

BSY

A2F

A1F

1

0

0

0

1

X

X

X

OSF: Oscillator stop flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped forsome period and could be used to judge the validity of the timekeeping data. This bit is set to logic 1 any timethat the oscillator stops. This bit remains at logic 1 until written to logic 0. The following are examples of
BIT 7

BITS 6:4

conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are insufficient to support the oscillator.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the oscillator (i.e., noise, leakage, etc.).
Unused (0). These bits have no meaning and are fixed at 0 when read.

BIT 3

EN32KHZ: Enabled 32.768kHz output. This bit enables and disables the 32KHZ output. When set to a logic 0,
the 32KHZ output is high impedance. On initial power-up, this bit is set to a logic 1 and the 32KHZ output isenabled and produces a 32.768kHz square wave if the oscillator is enabled.

BIT 2

BSY: Busy. This bit indicates the device is busy executing temperature conversion function. It goes to logic 1
when the conversion signal to the temperature sensor is asserted, and then it is cleared when the device hascompleted the temperature conversion. See the Block Diagram for more details.

BIT 1

A2F: Alarm 2 flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If theA2IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A2F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.

BIT 0

A1F: Alarm 1 flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the
A1IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A1F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.

Aging Offset Register (10h)
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SIGN

DATA

DATA

DATA

DATA

DATA

DATA

DATA

0

0

0

0

0

0

0

0

The Aging Offset register takes a user-provided value to add to or subtract from the factory-trimmed value that adjusts theaccuracy of the time base. Use of the Aging Offset register is not needed to achieve the accuracy as defined in the Electrical
Characteristics tables.
The Aging Offset code is encoded in two’s complement, with bit 7 representing the SIGN bit and a valid range of ±127. One
LSB typically represents a 0.12ppm change in frequency. The change in ppm per LSB is the same over the operating temperature range. Positive offsets slow the time base and negative offsets quicken the time base.

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Maxim Integrated │ 15

±5ppm, I2C Real-Time ClockDS3231M

Temperature Registers (11h–12h)
Temperature Register (Upper Byte = 11h)
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SIGN

DATA

DATA

DATA

DATA

DATA

DATA

DATA

0

0

0

0

0

0

0

0

Temperature Register (Lower Byte = 12h)
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DATA

DATA

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Temperature is represented as a 10-bit code with a resolution of 0.25°C and is accessible at location 11h and 12h. The temperature is encoded in two’s complement format. The upper 8 bits, the integer portion, are at location 11h and the lower 2 bits,
the fractional portion, are at location 12h. For example, 00011001 01b = +25.25°C. Upon power reset, the registers are set toa default temperature of 0°C and the controller starts a temperature conversion. The temperature is read upon initial application of VCC or I2C access on VBAT and once every second afterwards with VCC power or once every 10s with VBAT power. The
Temperature registers are also updated after each user-initiated conversion and are read only.

When the RTC register values match alarm register settings, the corresponding alarm flag A1F or A2F bit is set
to logic 1. If the corresponding alarm interrupt enable
A1IE or A2IE bit is also set to logic 1, the alarm condition activates the INT/SQW signal if the INTCN bit is set
to logic 1. The match is tested on the once-per-second
update of the time and date registers.

I2C Serial Port Operation
I2C Slave Address
The device’s slave address byte is D0h. The first byte
sent to the device includes the device identifier, device
address, and the R/W bit (Figure 8). The device address
sent by the I2C master must match the address assigned
to the device.
LSB

MSB
1

1

0

1

DEVICEIDENTIFIER

Figure 8. I2C Slave Address Byte

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0

0

0

R/W
READ/
WRITE BITI2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive dataat the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle,
it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with aslave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 1 forapplicable timing.

Maxim Integrated │ 16

DS3231M

Repeated START Condition: The master can use
a repeated START condition at the end of one datatransfer to indicate that it immediately initiates a newdata transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a datatransfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 forapplicable timing.
Bit Write: Transitions of SDA must occur during thelow state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold time requirements (see Figure1). Data is shifted into the device during the risingedge of the SCL.
Bit Read: At the end of a write operation, the mastermust release the SDA bus line for the proper amountof setup time (see Figure 1) before the next risingedge of SCL during a bit read. The device shifts out
each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the risingedge of the current SCL pulse. Remember that themaster generates all SCL clock pulses including when
it is reading bits from the slave.
Acknowledge (ACK and NACK): An acknowledge(ACK) or not acknowledge (NACK) is always the ninth
bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmitting a 0 during the ninth bit. A device performs
a NACK by transmitting a 1 during the ninth bit.
Timing for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that thedevice is properly receiving data. A NACK is used toterminate a read sequence or as an indication that thedevice is not receiving data.
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (mostsignificant bit first) plus a 1-bit acknowledgment fromthe slave to the master. The 8 bits transmitted by themaster are done according to the bit write definition
and the acknowledgment is read using the bit readdefinition.
Byte Read: A byte read is an 8-bit information transferfrom the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of informationthat are transferred (most significant bit first) from theslave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data

www.maximintegrated.com±5ppm, I2C Real-Time Clockbytes. The master must NACK the last byte read toterminate communication so the slave returns controlof SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
device’s slave address is D0h and cannot be modified by the user. When the R/W bit is 0 (such as inD0h), the master is indicating it writes data to theslave. If R/W = 1 (D1h in this case), the master isindicating it wants to read from the slave. If an incorrect slave address is written, the device assumes themaster is communicating with another I2C device andignore the communication until the next START condition is sent.
Memory Address: During an I2C write operation, themaster must transmit a memory address to identify
the memory location where the slave is to store thedata. The memory address is always the second byte
transmitted during a write operation following theslave address byte.

I2C Communication

See Figure 9 for an I2C communication example.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowledgment during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes
the starting memory address, writes multiple databytes, and generates a STOP condition.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,the master generates a START condition, writes theslave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, andgenerates a STOP condition. However, since requiring the master to keep track of the memory address
counter is impractical, use the method for manipulating the address counter for reads.

Maxim Integrated │ 17

±5ppm, I2C Real-Time ClockDS3231M

TYPICAL I2C WRITE TRANSACTION
MSB
START

1

LSB
1

0

1

0

0

0

R/W

MSB
SLAVE
ACK

b7

LSB
b6

READ/
WRITE

SLAVE
ADDRESS

b5

b4

b3

b2

b1

b0

MSB
SLAVE
ACK

b7

LSB
b6

b5

b4

REGISTER ADDRESS

b3

b2

b1

b0

SLAVE
ACK

STOP

DATA

EXAMPLE I2C TRANSACTIONS
D0hA) SINGLE BYTE WRITE-WRITE CONTROL REGISTER
TO 44hSTARTB) SINGLE BYTE READ
-READ CONTROL REGISTERSTART 1 1 0 1 0 0 0 011010000
D0h

0Eh
SLAVE
00001110
ACK

0Eh
SLAVE
SLAVE
00001110
ACK
ACK

D0h
C) MULTIBYTE WRITE-WRITE DATE REGISTER
TO "02" AND MONTHREGISTER TO "11"D) MULTIBYTE READ
-READ ALARM 2 HOURSAND DATE VALUESSTART 1 1 0 1 0 0 0 0

04h
SLAVE
ACK

00000100

SLAVE
ACK

00001100

D0h
START 1 1 0 1 0 0 0 0

44h
SLAVE
01000100
ACK

SLAVE
ACK

STOP

D1h
REPEATED
START

DATA
VALUE

MASTER
NACK

00010001

SLAVE
ACK

STOP

SLAVE
ACK

VALUE

11010001

SLAVE
ACK
11h

02h
SLAVE
ACK

00000010

SLAVE
ACK

SLAVE
ACK

REPEATED
START

11010001

D1h

0Ch

STOP

DATA

DATA
MASTERACK

VALUE

MASTER
NACK

STOP

Figure 9. I2C Transactions

Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated START
condition, writes the slave address byte (R/W = 1),
reads data with ACK or NACK as applicable, andgenerates a STOP condition. See Figure 6 for a readexample using the repeated START condition to
specify the starting memory location.

improves performance, and ceramic capacitors tend tohave adequate high-frequency response for decoupling
applications.

Reading Multiple Bytes from a Slave: The read
operation can be used to read multiple bytes with asingle transfer. When reading bytes from the slave,the master simply ACKs the data byte if it desires toread another byte before terminating the transaction.
After the master reads the last byte it must NACK toindicate the end of the transfer and then it generates
a STOP condition.

The RST output is also open drain, but is provided withan internal 50kI pullup resistor (RPU) to VCC. External
pullup resistors should not be added.

Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3231M,
decouple the VCC and/or VBAT power supplies with
0.1FF and/or 1.0FF capacitors. Use a high-quality,
ceramic, surface-mount capacitor if possible. Surfacemount components minimize lead inductance, whichwww.maximintegrated.com

If communications during battery operation are notrequired, the VBAT decoupling capacitor can be omitted.

Using Open-Drain Outputs
The 32KHZ and INT/SQW outputs are open drain andtherefore require external pullup resistors to realize logichigh output levels. Pullup resistor values between 1kI
and 10MI are typical.

SDA and SCL Pullup Resistors
SDA is an open-drain output and requires an external
pullup resistor to realize a logic-high level.
Because the device does not use clock cycle stretching,a master using either an open-drain output with a pullup
resistor or CMOS output driver (push-pull) could be used
for SCL.

Battery Charge Protection
The device contains Maxim Integrated’s redundant battery-charge protection circuit to prevent any charging of
the external battery.

Maxim Integrated │ 18

±5ppm, I2C Real-Time ClockDS3231M

Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but thedrawing pertains to the package regardless of RoHS status.
PACKAGE TYPE

PACKAGE CODEOUTLINE NO.

LAND PATTERN NO.

16 SO

W16MK+1

21-004290-0107

8 SO

S8MK+121-004190-0096

www.maximintegrated.com

Maxim Integrated │ 19

±5ppm, I2C Real-Time ClockDS3231M

Revision History
REVISIONNUMBERREVISION
DATE

0

6/10

Initial release

5/11

Updated the Features section; moved the temperature accuracy limit from ±3°C (max)to ±3°C (typ) in the DC Electrical Characteristics—General table; added the PowerSupply Current vs. SCL Frequency graph to the Typical Operating Characteristics
section; changed the initial date information to international format in the Power-Supply
Configuration section

1, 3, 6, 10

2

10/11

Removed future status from the 8-pin SO package in the Ordering Information table;
updated the Typical Operating Circuit; added Note 7 to the CBIN parameter in the AC
Electrical Characteristics—I2C Interface table; clarified the 10h register range in Table
2 and the Aging Offset Register (10h) section; corrected the package codes for both
SO variants in the Package Information table

1, 4, 11, 15,
19

3

12/11

Added the automotive qualified 8-pin SO package to the Ordering Information table;changed the lead temperature from +260°C to +300°C in the Absolute Maximum
Ratings section

1, 2

4

9/12

Changed the operating temperature range from -40°C to +85°C to -45°C to +85°C

5

7/13

Added junction temperature and package thermal data

6

8/14

Added Initial VBAT Attachment section

10

7

3/15

Updated Benefits and Features section.

1

1

PAGES
CHANGEDDESCRIPTION—

1-4, 82

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

© 2015 Maxim Integrated Products, Inc. │ 20