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STATUS OF THE RFSoC-BASED SIGNAL PROCESSING FOR MULTIBUNCH AND FILLING-PATTERN FEEDBACKS IN THE SLS2.0
P. Baeta, B. Keil, G. Marinkovic, Paul-Scherrer-Institut (PSI), Villigen, Switzerland
Abstract
Having effectively evaluated the RF System-On-Chip(RFSoC) as a suitable technology for the SLS2.0 Filling
Pattern Feedback (FPFB) and Multi-bunch Feedback(MBFB), our current focus lies in realizing and expanding
the required real-time Digital Signal Processing (DSP) algorithms on an RFSoC evaluation board. This contribution
outlines the present status of our feedback systems, including recent outcomes derived from testing prototypes bothin the laboratory and with beam signals at the storage ring.

INTRODUCTION
The Swiss Light Source (SLS), a 3rd generation synchrotron light source at Paul Scherrer Institute (PSI), will
be upgraded by a cutting-edge storage ring magnet latticewith reverse bends. The new machine, the SLS2.0, will
provide a much lower emittance and higher beam energy,
ultimately increasing the hard X-ray brightness and making
the SLS competitive with other newer facilities [1]. Moreover, upgrading the SLS includes modernizing aging systems, such as the multi-bunch feedback (MBFB) and thefilling pattern feedback (FPFB). After we assessed the suitability of RF System-On-Chip (RFSoC) for implementing
the MBFB and FPFB of SLS 2.0 [2], we proceeded with
deploying the feedback systems on the ZCU111 evaluation
board from Xilinx/AMD, which features an RFSoC [3]. In
the hardware section of this paper, we present an overview
of the set-up installed at the SLS for testing the new MBFB
and FPFB designs, which includes an RF-front-end(RFFE) prototype and the RFSoC-based digital back-end.
The subsequent Firmware and Software section covers areal-time implementation of bunch-charge and arrival-timemeasurement for the FPFB, along with DSP firmware upgrades in the MBFB design. Lastly, we report prototype results from testing RFSoC-based systems in the laboratory
and at the SLS storage ring, utilizing RF beam position
monitor (BPM) signals.

HARDWARE
Figures 1(a) and 1(b) depict a block diagram of the
hardware set-up at the SLS storage ring for prototyping our
RFSoC-based solution of the FPFB and MBFB systems.
The signals from four capacitive electrodes of an SLS
beam position monitor (BPM) are connected to an RF hybrid network, yielding the sum signal (S), proportional tothe bunch charge, and the difference signals (X and Y), proportional to the bunch charge and the horizontal and vertical bunch position offsets. The RFFE module consists ofdigital step attenuators (DSAs) and RF amplifiers for conditioning the position signals S, X, and Y. Figure 1(a) presents the signal conditioning path for each of the three

MBFB planes. The RFFE prototype has a bandwidth of approx. 1000 MHz, online user-controllable gain/attenuation
adjustments, and on/off switching capabilities for each analog signal conditioning path. The previous MBFB at
SLS1.0 used a commercial RFFE that down-converted
BPM signals from 1.25-1.5 GHz to the baseband. The new
RFFE represents a transition toward direct sampling of S,
X, and Y signals. The digital back-end in Figure 1(b) comprises the ZCU111 evaluation board and two interface
boards. The ZCU111 is the core of the feedback systems,
performing the data acquisition and processing. The Xilinx/AMD FMC-XM500 card breaks out the nets of the
RFSoC data converters of the ZCU111. The ADCs acquire
the conditioned signals S, X, and Y from the RFFE. The
ZCU111 can control the RFFE signal gain and power witha second adapter board. In the context of the MBFB, theDACs generate the correction signals, closing the feedback
loop. The correction signals undergo amplification, including upconversion to 1.5 GHz in the longitudinal plane, before driving the MBFB kickers. As for the FPFB, embedded real-time software processes the sum signal (S), calculating bunch charge. This process concludes by providing
injection control information across successive top-up cycles, as needed, to close the filling pattern feedback loop.
RF-Amplifier[i][13dm][0.5-4000MHz]
RFFE[i]in

RFFE[i]o ut
DSA0[i][0-31.5dB][DC-4200MHz]

DSA1[i][0-31.5dB][DC-4200MHz]i = [BPMS,BPMX,BPMY](a)

RFFE[0]o ut
DACS
RFFE[1]o ut
DACX
RFFE[2]o ut
DACY

(b)

Figure 1: Block diagram of the FPFB and MBFB hardware
set-up. (a) RF Front-end (RFFE) module for conditioning
position signals from the SLS beam position monitor(BPM). (b) The Digital back-end module incorporates the
ZCU111 evaluation board for data acquisition, processing,and communication with the SLS control system.

FIRMWARE AND SOFTWARE
Figures 2 and 3 illustrate the firmware block diagramsfor the FPFB and MBFB systems implemented on the
RFSoC platform. The Xilinx RF Data Converter is the core
IP of the design. This IP configures the ADCs and DACsof the RFSoC and establishes the AXI stream data interface
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of each converter with the programmable logic (PL) [3].
The EPICS IOC, operating on one of the two ARM CPUof the RFSoC processing system (PS), handles the configuration and data transfer between the feedback and SLS
control systems via an Ethernet interface. The PS and PL
interfaces include AXI bus and PL to PS interrupts. The
I2C bus controls the on-board PLLs, which define theclock frequency of the RFSoC converters. The reference
clock of the design is received from the master generator
for the SLS storage ring high-power RF systems (𝑓=~500 MHz). For the MBFB system, all data converters
run in multi-tile synchronization (MTS) mode, guaranteeing temporal sample alignment among ADCs and DACs
and reproducible latency from ADC to DAC after a power
cycle. The PL clock and data converter clocks in the MBFB
firmware design are synchronized to the external reference
clock and, thus, to the electron beam revolution frequency.
In the FPFB design, the ADCs and PL operate in different
clock domains, realizing an interleaving scheme to increase the effective ADC sample rate.

ADCCLK[0]Event
Receiver

PS CLK

Ethernet
I2C

PS

DRAM

PL CLKADC CLK
TRIG GEN
rev_clock

AXIS_ADC[0:1]

ADC[0:1]

RF dataconverter

SFP

ADC[1]
FPFB
acq_trigger
ADC[0]SD CARD

rate of the ADC0 by a factor of M, 𝑓 is set such that afractional number of samples per turn is acquired, and thedata of M turns is interleaved.
× 8 × ( 𝑀 × 𝑁 – 1)
(1)
(𝑁 × 𝑀)In our prototype system, the interleave factor M is 16, resulting in an effective sampling rate of ~ 64 Gs/s.The
ADC0 samples the sum signal, S, which contains the bunchcharge and arrival-time information. The trigger generator
IP controls the data acquisition, providing a periodic trigger, 𝑎𝑐𝑞_𝑡𝑟𝑖𝑔𝑔𝑒𝑟, with a period of ~ 960 ns (480 bunches,or one beam turn) and synchronized with the machine revolution clock. The 𝑎𝑐𝑞_𝑡𝑟𝑖𝑔𝑔𝑒𝑟 is the reference for bunchindexing. The data corresponding to bunch zero is the firsteight samples after the rising edge of 𝑎𝑐𝑞_𝑡𝑟𝑖𝑔𝑔𝑒𝑟, andbunch 479 is the last eight samples before the acquisitionof a new turn. After acquiring the sum signal, S, over 16
turns, the ADC0 data stream is stored in a BRAM in PL,
and the data-acquisition block generates an interrupt request, 𝑖𝑟𝑞, to the Zynq UltraScale+ MPSoC Processing
System (PS) [3]. The PS is connected to the memory blockin the PL via the AXI bus and the Xilinx AXI BRAM controller IP. The real-time software for the FPFB, implemented in C, runs on the RPU0 CPU of the PS. The interrupt request, 𝑖𝑟𝑞, starts the interrupt handler function. First,
the raw data of the 16 turns is read from the BRAM andinterleaved, resulting in one interleaved turn. The data of
the interleaved turn is split into 480 bunch windows of 2 ns
(or 128 samples).
𝑓 =Figure 2: Firmware block diagram of the RFSoC-based
FPFB system.
MBFB CLK

AXIS_DAC[0:2]

DACCLK[0:2]
Ethernet
I2C
DRAM

ADC[2]
DAC[0:2]

AXIS_ADC[0:4]

ADCCLK[0:2]

RF dataconverter

MBFB (X)
ADC[0:2]

ti

ti+1

0

0.5×Ai%Full-scale

PS CLK𝑓

10

AXI Busirq

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0.5×Ai 0.5×Ai+1

0.5×Ai+1-10-20Algorithm 1
Algorithm 2
Algorithm 3-30

MBFB (Y)ADC[1]MBFB (S)
ADC[0]SD CARD
AXI BusFigure 3: Firmware block diagram of the RFSoC-based
MBFB.

Filling Pattern Feedback (FPFB) Systems
There are substantial changes in the firmware/software
implementation compared to the design presented inRef. [2]. The current FPFB firmware consists of a data-acquisition block that records the input data stream of the
ADC0 running at a sampling frequency, 𝑓 . The harmonic
number of the SLS ring is 480, and the SLS machine reference clock, 𝑓 , is approximately 500 MHz. For 𝑓 =8 × 𝑓 , the number of samples per bunch is 8, and per
turn is 𝑁 = 8 × 480. To increase the effective sampling

-40

0

50

100
150
#samples200

250

Figure 4: Sum signal, S, for two bunch windows of 2 ns,
illustrating bunch pulses of the bunch train. The area 𝐴
between the negative pulse (red curve) and the baseline(blue, yellow, and green curves) is used to estimate thecharge of the bunch 𝑏 . The Time 𝑡 , which splits 𝐴 in two
equal parts, is an estimate for the arrival time of 𝑏 .
Figure 4 shows the sum signal, S, for two bunch windows. For each bunch window, 𝐴 , is the area between thenegative pulse, the red curve, and the baseline. We considered three different algorithms for baseline calculation. The
first algorithm, the green curve, defines the baseline aszero. In the second algorithm, the baseline is the averageof the sum signal, S, over a single bunch window. In thethird algorithm, the baseline is the average value of the sumbunch winsignal, 𝑆, over the interval of 𝑘_dows defined by the user, aiming to reduce the effects of

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09 Data Acquisition and Processing Platforms12th Int. Beam Instrum. Conf.
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300Hz-20KHz BP

DDS IP core to excite a single or set of bunches, presently
with a fixed frequency. We foresee a bunch excitation
mode featuring a frequency sweep or phase noise within apredefined frequency range for the next firmware upgrade.
The excitation will allow the incorporation of advanced diagnostics tools, such as excitation-damping measurements,
betatron and synchrotron tune measures, and automatedtuning.

STATUS AND RESULTS
0.1

0.05

00

10
1

Gain
16-Tap FIR

16

Down-sampling

(a)

Gain

+

C

Up-sampling

16
LP
300Hz IIR

#bunch429 479(a)

DDS

20KHz IIR

LP

Algorithm 1
Algorithm 2
Algorithm 3
Ref Filling Pattern
Current SystemCbaseline fluctuations on the ADC recordings. The charge ofa bunch 𝑏 , with index 𝑖 , is the calculated area 𝐴 times awhich translates area, 𝐴 , into
common factor 𝑘bunch charge in Coulombs. The bunch arrival time of 𝑏 is
the time 𝑡 , which splits the area, 𝐴 , equally by two. Aftercalculating the bunch charge and arrival time, the RPU0
leaves the interrupt service routine, re-arming the data-acquisition block. The measurement is repeated at the next
rising edge of the 𝑎𝑐𝑞_𝑡𝑟𝑖𝑔𝑔𝑒𝑟. The filling pattern information and configuration parameters of the FPFB can beaccessed via EPICS channels. The electron bunches are
sorted by charge with the information the system provides,
and a list with sorted bunch indices is ready for control the
injections of the next top-up cycle. The execution time of
the interrupt sub-routine within the real-time software, encompassing the bunch-charge and bunch arrival measurements, alongside the statistics of the measurements (moving average and root mean square error), averages approximately 93 milliseconds. This implementation successfully
satisfies the requirements of the FPFB, given that top-up
injections occur at intervals of 320 milliseconds.

-3
Algorithm 1
Algorithm 2
Algorithm 3

Combiner

0.5

DDS

20KHz IIR
Gain

+

HP
8-Tap FIR

Combiner00#bunch429 479(b)(b)

Figure 5: Block diagram of the MBFB firmware. (a) Longitudinal and (b) transverse planes.

Figure 6: (a) Bunch charge measurement and (b) RMS
noise of the measurements with different algorithms.

Multi-bunch Feedback (MBFB) Systems

Filling Pattern Feedback (FPFB) Systems

In alignment with the firmware design presented inRef. [2], the interface between ADCs and PL in the latest
MBFB firmware operates at 𝑓 (~500 MHz), streaming
eight samples in parallel 𝑓 = 8 × 𝑓 (~4 Gs/s). In thesubsequent processing stage, the input data stream is decimated by a factor of eight. The user selects, via EPICS
channels, which of the eight samples, 𝑃 , of the position
signal is subjected to processing. Since the bunch window
containing the bunch-pulse has 2 ns or eight samples, the𝑃 selection is such that the sample is close to the pulse
peak, facilitating direct sampling. Figures 5(a) and 5(b)show the digital signal processing paths for the longitudinal and transverse planes of the MBFB, respectively. The
digital filters (DF) process the selected position data 𝑃 ofeach bunch 𝑖, generating the correction signals 𝐶 . The coefficients and gain of the digital filters are reconfigurable
via EPICS to inhibit coherent bunch oscillations. Furthermore, the latency of the DSP paths is adjustable in steps of
2 ns (bunch length), and in the output stage, the user canfine-tune with 250 ps resolution when applying the bunchcorrection signal 𝐶 to precisely kick the bunch 𝑖. In addition to the basic MBFB features, the new firmware design
features a multi-bunch excitation framework, which uses a

Figure 6(a) shows the measurement results of the bunchcharge obtained at the SLS storage ring using the current
FPFB system and with the RFSoC-based system.
Figure 6(b) compares the root mean square error (RMSE)of the different algorithms for bunch-charge measurement
realized on the RFSoC-based FPFB. Algorithm 3 hasslightly better performance. The baseline of Algorithm 3 isset as the average value of the sum signal, 𝑆, for eightbunch windows. Figure 7(a) shows the bunch arrival-timemeasurement results with the RFSoC-based system for thethree baseline algorithms. Figure 7(b) compares the root
mean square error (RMSE) in the bunch-arrival time measurement for each algorithm, where Algorithm 3 has thelowest RMSE. After successfully implementing the buncharrival time and bunch charge measurement in real-time
software, the next step is to accelerate the algorithms in PLsuch that the MBFB can use the bunch-arrival time to correct longitudinal bunch oscillations.

09 Data Acquisition and Processing Platforms

Multi-bunch Feedback (MBFB) Systems
The present firmware version of the RFSoC-based MBFB
has been designed to be functionally equivalent to the existing SLS MBFB based on 8-bit VMEbus ADC and DAC
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0a smaller RMS noise by reducing the effects of the baseline
fluctuations in the ADC recordings of the sum signal. Next,
we foresee the acceleration of the method in firmware suchthat the bunch-arrival time information can be used for thelongitudinal MFFB. Regarding the MBFB, we have conducted a functional verification of the firmware by comparing the hardware response of the VME-based and
RFSoC-based MBFB. Our next steps include testing the
MBFB feedback closed-loop in SLS and SLS 2.0 and integrating advanced diagnostic tools such as excitation-damping measurements, tune measurements, and automatic parameter tuning. Finally, tests with the new RFFE motivate
us to investigate a digital solution (ADC/DAC interleaving) for sampling the BPM signals and driving kicker amplifiers directly with simplified analog pre/post-conditioning, eliminating up/down conversion.
40
MBFB (RFSoC-based)
MBFB (VMEbus-based)

20%Full-scaleboards. The MBFB functionality was tested in the laboratory by comparing the open loop response of the VMEbased MBFB hardware versus the RFSoC MBFB system
for the same input signal and configuration parameters(digital filter coefficients and gains). Moreover, the digitaldelay control of the DSP processing path was adjusted suchthat the responses of both systems were aligned in time.
Figure 8 shows the open-loop response of the horizontal
plane for both systems. The higher ADC resolution of the
prototype MBFB system results in lower noise in the correction signal 𝐶 (DAC response). The MBFB prototype
system and the RFFE prototype have been tested withbeam signals at the SLS. Figure 9 compares the output signal from the existing commercial RFFE and the RFFE prototype for the storage ring filled with a single bunch. The
results show that for a single bunch, the signal-to-noise ratio of the correction signal allows the replacement of thepresent analog downconverter RF front-end (RFFE) for direct sampling of the BPM signals. However, further improvements to the new RFFE and signal processing areforeseen. We plan to use delay lines and interleave multiple
ADC channels to increase the effective sampling rate of thecurrent ADC running at 4 Gs/s, facilitating the direct sampling (sample the pulse peak) in a more realistic filling pattern scenarios of the storage ring, where phase slippage ofthe bunches are present as shown in Figure 7(b).

0
-20
-40
0

500

1000
ns

1500

2000

Figure 8: Comparison of the open-loop response (horizontal plane) between the RFSOC and the VMEbus-based
MBFB system.

-100

-200

-300 0#bunch429(a)%Full-scale

ps100
Algorithm 1
Algorithm 2
Algorithm 3

50

0

2.5
2

Algorithm 1
Algorithm 2
Algorithm 3

new RFFE
old RFFE
RFSoC MBFB Ci

-50
-5

1.5

0

1
0.5
00

5

ns

ps

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429

Figure 7: (a) Bunch arrival-time measurement and (b)RMS noise of the measurements with different algorithms.

CONCLUSION AND OUTLOOKWe have implemented the MBFB and FPFB real-time
DSP algorithms on an RFSoC platform (ZCU111). The
FPFB low-level software, utilized for bunch-charge and arrival-time measurements, meets the time constraints, as theexecution time of the algorithms is shorter than the top-up
cycles. Among the tested algorithms, Algorithm 3 exhibits

Figure 9: Comparison of the existing RFFE output signal(red) and the RFFE prototype (blue) for the storage ring
filled with a single bunch. The yellow curve is the feedback
response (horizontal plane) from the RFSoC MBFB.

REFERENCES[1] A. Streun, “SLS 2.0, the Upgrade of the Swiss Light Source”,
in Proc. IPAC'22, Bangkok, Thailand, Jun. 2022,
pp. 925-928.
doi:10.18429/JACoW-IPAC2022-TUPOST032[2] P. H. Baeta Neves Diniz Santos, B. Keil, and G. Marinkovic,“RF System-on-Chip for Multi-Bunch and Filling-Pattern
Feedbacks”, in Proc. IBIC'22, Kraków, Poland, Sep. 2022,
pp. 379-382. doi:10.18429/JACoW-IBIC2022-WE2C4[3] Xilinx, https://www.xilinx.com/products/boardsand-kits/zcu111.html

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