TUP46

STATUS OF THE RFSOC-BASED SIGNAL PROCESSING FOR MULTIBUNCH AND FILLING-PATTERN FEEDBACKS IN THE SLS2.0*
Pedro Baeta†, Boris Keil, Goran Marinkovic (PSI, Villigen, Switzerland)†pedro,baeta@psi.ch

Abstract
Having effectively evaluated the RF System-On-Chip (RFSoC) as a suitable technology for the SLS2.0 Filling Pattern Feedback (FPFB) and Multi-bunch Feedback(MBFB) [1], our current focus lies in realizing and expanding the required real-time Digital Signal Processing (DSP) algorithms on an RFSoC evaluation board. This
contribution outlines the present status of our feedback systems, including recent outcomes derived from testing prototypes both in the laboratory and with beam
signals at the storage ring. [1] P. Baeta et al., "RF System-on-Chip for Multi-Bunch and Filling-Pattern Feedbacks," Proc. IBIC'22

SLS 2.0 / Motivation

Hardware• Replacement of the SLS storage ring, providing up to 60-fold higher brightness for hard X-rays.
• Modernization of aging systems, including the Multi-bunch (MBFB) and Filling Pattern (FPFB)
Feedback Systems.
• Xilinx RFSoC as platform to implement the MBFB and FPFB for the SLS 2.0.
• 1st SLS 2.0 beam is planned for 2025.

RF-hybrids NetworkAB

RFFE[i]inC

DSA0[i][0-31.5dB][DC-4200MHz]D

Filling Pattern Feedback (FPFB)

I2C

Real-time Software10

acq_trigger

ADC[0]SD CARD

00.5×Ai%Full-scale

AXI Busirqti-40 050

100150#samplesBunch Charge-100#bunch10-3PL(DSP)

Kickers

FIRMWARE
MBFB CLK200250

ADC[0:2]
ADCCLK[0:2]
DACCLK[0:2]20KHz IIR

Ethernet
I2C

DRAM

HP

ADC[2]

DAC[0:2]
MBFB (Y)ADC[1]

Gain+Combiner

8-Tap FIRMBFB Longitudinal
300Hz-20KHz BPMBFB (S)

ADC[0]SD CARDDDSMBFB Transverse

AXI Bus

MBFB ADC/DAC clock period = 1/8of nominal bunch spacing.
(𝑓S = 8 × 𝑓RF = ~4Gs/s)

DDS

20KHz IIR
LP
LP
300Hz IIR

Gain

16-Tap FIR
16

Down-samplingUp-sampling

Gain

16+Combiner

GUI-200

429 479-300 0RMS Noise#bunch429

RMS Noise
Algorithm 1
Algorithm 2
Algorithm 31

CpsC00B

Control System
Network

ARM(EPICS)

Algorithm 1
Algorithm 2
Algorithm 3

0.1
Algorithm 1
Algorithm 2Algorithm 3
Ref Filling Pattern
Current System

ZCU111MBFB (X)

Bunch Arrival-time
0A

DAC2

BPM
Pickup

AXIS_DAC[0:2]• Area Ai below dynamic baseline
proportional to the bunch charge, andtime ti which splits Ai in half is an
estimate for bunch arrival time.
• Algorithm 1:baseline is 0. Algorithm 2:baseline is the average of the sum signal,S, over a single bunch-window.
Algorithm 3: baseline is the average of
S over 𝑘𝑏𝑢𝑛𝑐ℎ_𝑤𝑖𝑛𝑑𝑜𝑤𝑠 bunch-windows.

RESULTS

XRFFE

RF front-end(RFFE)

Algorithm 1
Algorithm 2Algorithm 3-30YRF Amplifiers

DAC1ADC2PS CLK-200.05

0.5×Ai+1-10GUIADC1Stabilize beam and avoid beam loss due to coupled-bunch instabilities ( ion instabilities, resistive wall
impedance, cavity HOM, etc.). Diagnostic tool: Identify source of beam instabilities; Excitation-damping
measurement; Parasitic (X/Y/S) tune measurement.

ti+1
0.5×Ai 0.5×Ai+1

DAC0

Multi-Bunch Feedback (MBFB)

ADC[1]PSDRAM

BPM sum signal (S) sampled by RFSoC ADCs and usedfor bunch charge & arrival time calculation.

FPFB

ADC0

D

AXIS_ADC[0:4]

Ethernet

TRIG GEN
rev_clock

FMC-XM500

DSA1[i][0-31.5dB][DC-4200MHz]ZCU111

RF dataconverter

ADCCLK[0]ADC CLK

AXIS_ADC[0:1]

RF dataconverter

ADC[0:1]

PL CLKZCU111 Evaluation Kit

SPSEventReceiver

SFP

Filling Pattern ADCs run at slightly different ADC clock,to acquire a fractional number of samples per beam turn,
Such that an interleaved sampling scheme increases theeffective sampling rate of the ADCs from 4Gs/s to64Gs/s.

PS CLK

RFFE[i]out

i = [S,Y,X]

Measure the charge and the arrival time of each RF bucket. Control the injection time, adjusting thecharge of each bunch given an user-defined pattern (filling pattern). Improves orbit stability (BPMs havefilling pattern dependent error). Avoid HOMs (that are filling pattern dependent).

FIRMWARE• 8 x 12-bit ADC @ 4Gs/s• 8 x 14-bit DAC @ 6.5Gs/s

RF-Amplifier[i][13dm][0.5-4000MHz]

2.5
2

Algorithm 1
Algorithm 2
Algorithm 3psC

1.5
1
0.500

#bunch429 47900• Algorithm 3 showslower RMS noise for𝑘𝑏𝑢𝑛𝑐ℎ_𝑤𝑖𝑛𝑑𝑜𝑤𝑠 = 𝟖.
#bunch429

Outlook & Next Steps• Finalize the transition towards direct (mixer-free) sampling of the BPM signals by adding adjustabledelay lines to the RFFE, and interleaving multiple ADC channels; Implementing a digital solution fordata acquisition that accounts for the phase slippage of the bunches on the bunch train, guaranteeing thecorrect position signal detection (bunch pulse detection).
• For the MBFB Longitudinal plane, we foresee an replacement of the analog upconverter (baseband to1.5 GHz conversion) with a digital solution (interleaved DACs), for driving the kicker amplifiers.
• Add advanced diagnostics features to the MBFB, such as: excitation-damping measurements, tune
measurement, automatic parameter tuning.
• Test closed-loop performance of the MBFB and FPFB systems at SLS and SLS 2.0.

RESULTS40

MBFB (RFSoC)
MBFB(Current)

20%Full-scale

0.5

0-20
-40
05001000
ns15002000• Comparison of the open-loop response of thehorizontal plane of the existing MBFB hardware
versus the RFSoC-based prototype. The improved
ADC and DAC resolution of the RFSoC
significantly improved the noise of the DAC
response.