TH1I02

A Novel Cavity BPM Electronics for SHINE
Based on RF Direct Sampling and Processing
Longwei Lai#, Rong Meng, Yimei Zhou,
Shanshan Cao, Jian Chen, Xiaoqing Liu
lailw@sari.ac.cn
SSRF, Shanghai Advanced Research Institute, Chinese Academy of Sciences
2023.9.14

Overview
 SHINE and Cavity BPM electronics
 Requirements of RF Direct sampling Electronic(RFDE) The RFDE for SHINE cavity BPM
 Performance evaluation and FPGA implementation
 Is it time to use the RFDE in large-scale?

SHINE Introduction

SSRF

SXFELSHINESHINE Beam Diagnostics Using Electronics
OPIOPIOPIEthernet
Interlock
Clock
TimingRF
Front-end

Stripline
BPM

RF
Front-end

ICTFaradyCup

RF
Front-end

RF-BAM

RF
Front-end

FBL

RFFront-end

RF
Front-end

Wire
ColdBPM
Scanner

RF
Front-end

RF
Front-end

RF
Front-end

CSR-BLM CavityBPM EO-BAM

SHINE BPMs
Φ35mm

Injector and sections
between cryomodule
SBPM Resolution
10 um@100 pC

Cryomodules in LINAC
Cold-BPM Resolution
50 um@100 pC

Φ8mm

Beam distributor & FEL
CBPM Resolution
Φ35mm, 1μm@100 pC ·±1mm
Φ8mm, 200 nm@100pC·±100μm

Electronics
Required Relative error ≦1.0×10-3

SHINE Cavity BPM
 The central frequency of Φ35mm is 3520.87MHz(same as RF-BAM).
 The central frequency of Φ8mm is 5254.2MHzParameters
Resonant frequency /MHzCavity radius / mm
Cavity length / mm
Decay time / ns
Bandwidth / MHz
Loaded Q
Qext
Q0
Normalized shunt
impedance
Sensitivity /V/nC

PositioncavityReferencecavity

51.9
9200
1.59
2212
3245
6951
0.175@1mm
0.575@1m
m

32.6
4.5
200
1.59
2212
5869
3550
50.65

3520.87Φ35mm

3520.87

7.26

Parameters

Position cavity

Resonant frequency /MHz
Cavity radius / mm5254.2
34.8

21.8

Cavity length / mm

95Decay time / ns200200

Bandwidth / MHz

1.59

1.59

Loaded Q

3301

3301

Qext5663

1268

Normalized shunt
impedance
Sensitivity /V/nC

0.56@1mm

82.6

1.15@1mm

9.4

Φ8mm

Referencecavity
5254.2

Cavity BPM System Cavity BPM generates narrow bandwidth at highU/Vfrequency signal when beam passes through Cavity BPM system including pickup, RF front-end,

signal processor

TM010
TM01TM020
TM02TM011
TM11f / GHz

U~QU~QrU~Q

𝑉𝑉𝑜𝑜𝑢𝑢𝑡𝑡 010 ∝ 𝑞𝑞, 𝑉𝑉𝑜𝑜𝑢𝑢𝑡𝑡 110 ∝ 𝑞𝑞𝑥𝑥

Courtesy D. Lipka, DESY

Cavity BPM SystemCavity BPM Signal

Architecture of Cavity BPM Electronics

Benefits

Challenges

Heterodyne

trusted and highperformance
Optimum spurious noise

Complicate, large
physical footprint.

Direct Sampling

No mixing
Practical at L-, S-, C-band
Flexible application

ADC input bandwidth
ENOB

Direct-conversion

Easier low-pass filter
Lower ADC requirements
Simplest digital processing

I/Q balance
LO leakage
DC and 1/f noise
One more ADC

Electronic StructurePeter Delos, A review of wideband RF Receiver architecture options, Analog Devices, IncSXFEL Cavity BPM System Heterodyne structure in SXFEL

Components

Parameters

PickupCentral Frequency: 4681 / 4689 / 4685 MHz
QL / Decay time: ~ 5000 / 320 ns
Sensitivity: 0.5 V / nC · mm / 5.4 V / nC

RF front-end

Dynamic range:± 2mm @ 500pC
NF @ position cavity: 12 dB
NF @ reference cavity: 25 dB
IF SNR = 90 dB @ 500 pC

DBPM

ADC bits：16
Sampling rate: 119 MSPS
ADC band width: 650 MHz
Processing rate :50Hz

Pickupposition expected / mm

0.46

RF front-end intunnel
LO synthesizer
Down converter
DBPM

0.440.420.4

Total Sample = 487 / 500
STD = 1.09 μm
Resolution = STD*GF = 0.88 μm
Dynamic range: ±800 μm

0.38
0.62

SXFEL DBPM

Position measured Vs. expectedLinear fitting

0.64

0.66
0.68
position measured / mm

0.7

880nm@500pC �±800μm

SHINE Cavity BPM Electronics
 Heterodyne structure, IF = 54MHz, fs=866.67MHz
 DBPM: 1U Stand alone structure containing SoC FPGA
carrier board, high speed ADC board, White Rabbit
timing board
 4 RF input channels, maximum sampling rate
1GSPS, 14bits, 2GHz band width,
ENOB=10.8@50Hz FinParameters

White Rabbit Channels
BoardWRNtimingADC

ADC bits
Bandwidth
Max ADCrate
FPGAClock
PL DDR4Trigger
Interlock
SFP
User GPIO
SoftwareFPGA board and ADC board

SHINE Cavity BPM Systemvalue
4142GHz
1GSPS
Xilinx ZCU15EG
Ext./Int.
8GB
Ext./Self/Period
Lemo×4, UDP&Aurora
×16,SMA&PMO
DLinux/EPICSSHINE Generic Processor

BPM Electronic

The Development of Electronics
 Moving signal processing from analog to digital is a long-term goal
Before YesterdayYesterday: Digital basebands
RFRF front end

Frequencytranslator

Demodulator

Digitalprocessing

ADC

Digital Out

Yesterday
Today: Digital IFRF

RF front end

Frequencytranslator

ADCDigitalprocessing

Digital OutToday
Tomorrow: Digital RF
RFRF front end

ADCDigitalprocessing

Digital Out

Electronic Development
Courtesy of Hermann Schmickler, CERN, IBIC 2015

Heterodyne VS
RF direct samplingBenefits from RF Direct Sampling Simplify electronics: no LO synthesizer and mixing module Improve system sensitivity: introduced signal loss and noise during down conversion is avoided
 Smaller system size and reduce power consumption
2856MHz÷94654.2MHz

BAM#1~40 m

LPF

÷3×5

SXFEL CBPM LO synthesizer

4685 MHz (RF)BAM#24720 MHz (LO)

RFFE

35 MHz (IF)

Downconversion

shielding wall

SXFEL Double cavity

LOSHINE Ф35 CBPM LOProcessor

SHINE Ф8 CBPM LOSXFEL Cavity BPM Electronic

Review of RFDE in Beam Signal Processing
 Applications: LLRF, TFB, BAM, Digitizer
 ADC boards sampling rate < 1GHz, band width < 2.5GHz
 XILINX RFSoC demo boards with multi number high speed ADC and DAC
Courtesy Z.Geng, DESY, THP102, LINAC08

ADC Band Sampling
WidthRate

Bits

Interface

ADS5474

1.4GHz400MHz

14LVDSAD9433

760MHz125MHz×412CMOSADS42LB69

900MHz250MHz

16LVDS

ADC12D500RF

2.4GHz500MHz

12LVDS

Courtesy J. Zink, DESY, TUPP002, IBIC2019;
THOA02, IBIC2018

4GHz×8

12RFSoC

Courtesy D. B. Li, IHEP, MOPAB390, IPAC2021

2.5GHz×16

14RFSoC

Courtesy E. Cicek, KEK, WEPAB297, IPAC2021

ZCU111ZCU216

6GHz

Courtesy T. Nakamura, JASRI/Spring-8, THPC128,
EPAC08Courtesy Zhou Zeran, NSRL,Vol.22, No.7 Jul., 2010, High Power Laser andParticle Beams
Courtesy Y.Okada, KEK, WE5PFP088, PAC09

Courtesy O.Manzhura, KIT, MOPOPT017, IPAC2022
Courtesy P.Baeta, PSI, WE2C4, IBIC2022
Courtesy J. Weber, LBNL, WEPP16, IBIC2020

ADC Performance ADCs band width > 6GHz, sampling rate > 2GHz, resolution ≧ 12bits
 High speed serial data link between converters and receivers(JESD204B 12.5Gbps)
TypeSamplingRateBits

BandwidthChannels

JESD
LANE

Year

AD96892.6GHz

14 bit9GHz

282017

AD9208

3GHz

14bit

9GHz

282017AD921310.25GHz

12bit

6.5GHz1162020

AD9209

4GHz

12bit

8GHz

482021

5.2G

126.3G

2162023

3.2G

128G2

48对LVDS
1.6Gbps

2018

AFE7444

3GHz

14bit

6GHz

482019

AFE7900

3GHz

14bit

7.4GHz

68*29.5Gbps

2022

AFE7950

3GHz

14bit

12GHz

6

8*29.5Gbps

2023

ADC12DJ5200SE
ADC12DL3200

https://www.analog.com/en/t
echnical-articles/what-isjesd204-and-why-shouldwe-pay-attention-to-it.html

ADC Performance SNR degrades with input frequency(fA) due only to aperture jitter(tJ)Ramon Gomez, Senior Member, IEEE, Theoretical Comparison of Direct-Sampling Versus Heterodyne RF Receivers
Noise Spectral Density: A New ADC Metric?

 ADC performance:
ADC1:ENOB=12,
fs=119MHz

Analog-to-digital conversion inthe early twenty-first century,P = 2 ENOB • f s
ADC2: ENOB=8,
fs=119*16MHz=1904MHz

Robert H. Walden, Member, IEEE,
Analog-to-digital converter survey
and analysis

SoC FPGA SoC FPGA with hard core ARMs and large logic resource simplify the electronic Supports high band width data transmission and complicate digital signal processing
algorithms

Zynq UltraScale+ MPSoC FPGA

ARM

Virtex50ZU15EG
Promotion
4×Cortex-A53 New

LUT
FF
DRAM
BRAM
DSP
UBRAM
GTH

28800
28800
480Kb
2160Kb480
12×6.6Gb/s

341280682560
11.3Mb
26.2Mb3528
31.5Mb
24×16.3Gb/s

×11.85
×23.70×23.50×12.13
×73.5
New×4.94

RFDE Design for SHINE
 An SoC FPGA based RF direct sampling processor has been developed A RFDE for SHINE cavity BPM can be built with the processor
Parameters

Channels
ADC bits
Bandwidth
Max ADC rate
FPGAClock
PL DDR4TriggerInterlock
SFP
User GPIO
Software
RF Direct Sampling Processor

value

4149GHz
2.6GSPSXilinx ZCU15EG
Ext./Int.
2GBExt./Self/Period
Lemo×4, UDP&Aurora
12Linux/EPICS

Block design of RFDE for SHINE Cavity BPM

System Noise Figure Noise figure (NF) is defined as the ratio of signal-to-noise ratio (SNR) at the input to the SNR at theoutput

Noise factor:

Noise figure:

NF=10*log10(F) NF is used to characterize the noise of RF amplifiers, mixers, etc., it’s a measure of the noise added by thedevice(degradation of the SNR from input to output).

 NF of cascaded device chain

ADC Noise Figure For passive devices NF≈Insertion Loss, such as Mixer, Filter, Attenuator,
 ADC’s NF calculation:

Tommy Neu, Direct RF conversion:
From vision to reality, TI
AD9265ADC9680

ADC9689

Sampling rate(FS)

125M

1G

2.6G

Input full-scale (Vpp)

2V

1.7

1.7

Signal-to-noise ratio

79@70MHz

67.2@10MHz

58.3@3300MHz

Input impedance (Zin)

200

100

100

Calculated noise
figure (dB)

21

25.4

30.1

Digital Signal Processing Gain
 Cavity BPM signal is narrow bandwidth(1.6MHz), much smaller than the Nyquist
bandwidth(fs/2=1.3GHz)
 Digital signal processing to filter out the signal will produce processing gain

IF processing gain:

10*log10(216.6*4/(2*1.6))=24.3dB

RFDE processing gain: 10*log10(216.6*12/(2*1.6))=29dB

SHINE Heterodyne System Performance Analyzing
 SNR of SHINE cavity BPM signal is 72dB, the calculated NF is 9.1dB, add processing gain is
24.3dB, the SNR of the system is 72-9.1+24.3=87.2dB, the system relative error is 5×10-5
NF=3.2
G=12

NF=6.0
G=23

NF=6.0G=19.2

NF=9.1G=19.2

ADC
NF:25.4Balun
BAL-0003SMG
IL:3.8

NF=19.9
G=7.2

RFDE Performance Analyzing – A Prototype ofRF Module

 A protype of RF module was built to evaluate the RFDE performance Assuming SNR of cavity BPM signal is 72dB, the calculated NF of DRFE is 15.9dB, add

processing gain 29dB, the SNR of the system is 72-15.9+29=85dB, the ideal system relative
error is 7×10-5
LNA
PMA3-83

3520MHz BPF

IN

B2

B1

A

Att.
0~10dB

Prototype of RF Module
NF:2.6
G:18.9

BPF

LNA

COUT
NF:2.66
G:14.4

NF:15.9
G:14.4AttADC
CF:3520MHz
BW:3470-3570MHz
IL:1.2

PMA3-83LN+
NF:1.4@3.520G
G:21.1@3.520G

0~-90dB
GKTSX-1-10-6-A1
IL:1Balun
BAL-0009SMG
IL:4.5

NF:30.1

Prototype of RF Module

RFDE Performance Evaluation
 A vector signal generator outputs phase locked decay RFsignal(simulate cavity BPM signal) and clock signal
 Amplitude relative error of single channel is 3.0×10-4
 Amplitude relative error between two channels is 2.0×10-4< 1.0×10-350Hz

Vector Signal Generator

TriggerDivider

0.01Splitter

Relative Error

ProtypeRF10Hz

ChC-ChD-37Single Channel Relative
Error = 2.6×10-4

0.006

1.3GHz1080.008

3.52087GHzClockDivider

90.0040.002

6Relative Error

10MHzSMW200A

Two Channels Relative
Error= 2.0×10-4

54
321

Clock
216.66MHz

RFD Processor

Lab test platform

Trigger

0-55-50-45-40-35-30

Input Amplitude/dBm-25-20-15-100-55-50-45-40-35-30

Input Amplitude/dBm-25-20-15-10

RFDE Performance Evaluation
 Single channel phase RMS 200fs(including jitter from signal source) Two channels relative phase RMS 14fs, better than 25fs CBAM requirement in SHINE
700

800

ChA-ChB

ChA
ChB

700

ChB-ChC

400

300200ChB-ChC
ChC-ChD
ChB-ChD

ChB-ChD

Relative Phase RMS/fs

Relative Phase RMS/fs

500

ChA-ChD

35

ChC-ChD

500

600

ChA-ChC

40

ChA-ChD

ChD

Phase RMS/fs

ChA-ChB

ChA-ChC

600

ChC

400

300

200

30252015100
10100-55-50-45-40-35-30

Input Amplitude/dBm-25-20-15-100-55-50-45-40-35-30

Input Amplitude/dBm-25-20-15-10-19-18-17Input Amplitude/dBm-16-15-14

Digital Signal Processing Algorithms
10ChB

5ChB

2500

ChB

6000

128

4000

64

Hilbert Amplitude

1500

DDC Amplitude

Spectrum Amplitude

5000

2000

101000

3000

2000

500

21000
0

1420

1430

1440

1450

1460

1470

1480

0

DFT Point Number

0500

1000

1500

2000

2500

3000

3500

4000

04500

Point Number
105108

1 point 4.5×10-4

3.5

5 points 2.8×10-4
7 points 2.7×10-4

2.5

9 points 2.6×10-4
0

20

40

60

80

100

500

1021000

1500

2000

2500

3000

3500

4000

4500

ChB

-3

1.8
1.6

6

Relative Error

43ChB-4

7

3 points 3.1×10-40

Point Number

1.4

Relative Error

4.5

Relative Error

ChB-4541.2
10.80.6

30.4

120

140

160

Spectrum Points

180

200

20500

1000

1500

2000

DDC Points

2500

3000

0.20500

1000

1500

2000

2500

Hilbert Points

Goertzel-DFT algorithm

DDC algorithm

Hilbert algorithm

3000

Goertzel-DFT FPGA Implementation
Accum.
JESD LANE0
Accum.

I0
Q0

JESD LANE7
Accum.
DDS7

ΣI…

…
Accum.

I7

…

DDS0

ΣQ

Q7

CORDI
CMag.

Phase

CLB LUTs

CLBRegisters

CLB

LUT asLogic

LUT asMemoryBlock
Ram Tile

DSP

Total Resources

34128068256042660

3412801843207443528

1 Point DFT CBPM
Position Cost28294

37778

4893

25633

2661

76.5

88

Percent

8.29%

5.53%

11.47%

7.51%

1.44%

10.28%

2.49%

Percent(3points)

24.9%

16.5%

34.5%

22.5%

4.5%

30.9%

7.5%

Is it time to use the RFDE in large-scale?
 Electronic technology is developing rapidly. Higher performance ICs(ADC, FPGA, PLL, DDR)
are becoming more common. Budgets of electronics that were ten years ago can now build
much higher performance electronics.
 RF Direct Sampling ADCs are more expensive than IF ADCs. But it is still cheaper comparedto the cost savings from heterodyne RF modules.
 Yes, it’s time to promote large-scale application of RFDEin beam diagnostics.
RF Direct Sampling Processor
Fs=2.6GHz，BW=9GHz

SHINE Generic Processor
Fs=1GHz，BW=2GHz

SSRF/SXFEL/DCLS SoC Processor
Fs=125MHz，BW=650MHz

SSRF/SXFEL/DCLS Processor
Fs=125MHz，BW=650MHz

Thanks for your listening!