LCLS-II Timing Systemand synchronous bunchdata acquisition
TH1I01Carolina Bianchini Mattison/ Senior Software Engineer / AD-EED
14th September 2023

Agenda
LCLS-II Timing System and synchronous bunch data acquisition
Beamline MAP
LCLS-II Timing System, DESIGN:• Timing Requirements• Timing Distribution• Timing Pattern Frame (individual pulse)
Timing Pattern Requirements
Beam Synchronous Acquisition services•

Beam Synchronous Acquisition (BSA)•

Beam Synchronous Scalar System (BSSS)

Timing Pattern Generator Graphical User Interface (TPGGUI)•Patterns Classification

Timing Pattern Receivers
Commissioning Experience
Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

2SLAC Accelerator Complex: LCLS/CLTS/LCLS-II
Beam Line Map of the two timing systems serving LCLS and LCLS-II

LCLS-II will add a superconducting accelerator, occupying one-third of SLAC’s original 2-mile-long linear accelerator
tunnel.
LCLS-II will provide a major jump in capability – moving from 120 pulses per second to 1 million pulses per second.
In addition to the new accelerator, LCLS-II requires a number of other cutting-edge components, including a newelectron source, a powerful cooling plant that produces refrigerant for the accelerator, and new undulators togenerate X-rays.
Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

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SLAC Accelerator Complex: LCLS/CLTS/LCLS-II
Beam Line Map of the two timing systems serving LCLS and LCLS-II
Map of LCLS / CLTS / LCLS-II highlighting the kickers and dumps

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

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LCLS-II TIMING SYSTEMDESIGN: REQUIREMENTS
Timing AttributeValue

Phase Reference (Linac RF)

1300 MHz

Clock (Gun RF = Linac RF/7)

185.71 MHz

Nominal Beam Rate (Clock/200)

0.92857 MHz

Fiducial Resync Freq (Clock/2600)

0.07143 MHz

Fiducial (Power Line Phase)360 HzStability - Standard (fiber)

0.4 nsStability – Phase reference line (PRL)

1 fs/sec, 1 ps/day

Jitter – Standard (fiber)

30 ps

Jitter – PRL (50Hz to 5kHz)

0.005º or 10.7 fs

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LCLS-II TIMING SYSTEM
Timing Pattern Receivers
Every control system crate has a timing receiver.
The hardware is ATCA or PCIe platform.
Timing Pattern is analyzed based on modules: tprTrigger, bsaDriver and other libraries.
The devices are triggered (total 16 configurable triggers) based on the appropriate filters for the given location,
defined in one of the 16 channels.

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

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LCLS-II TIMING SYSTEMDESIGN: REQUIREMENTS
AC Rate compatibility for some of the devices, like Klystrons (XTCAV and STCAV). The triggering system for thesedevices needs to be synchronized to the AC Power line timeslots and up to a max 120Hz.
The requirement of the diagnostics devices along the machine is to take clean measurements. Since
the performance of the above listed devices depends on the triggers being synchronized to the AC power line phase. If
this isn't aligned the Klystron impulse will have a jitter in amplitude, not producing a clean measurement.
An example is in the Diagnostic Line destination, just after the gun where we'll expect to trigger on AC patterns limited
to 120Hz.
The TCAV diagnostics provide a transverse kick of the electron beam. Their triggers must be aligned to the AC powerline to minimize jitter.

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LCLS-II TIMING SYSTEMDESIGN: TIMING DISTRIBUTION
LCLS-II Timing System is completely decoupled from LCLS-I Timing System.
Timing Pattern Generator (TPG) sends Timing Frames to each Timing Pattern Receiver (TPR) over a dedicated fiber
network at 1MHz.
Challenge: signal stability over this long fiber network. Active Fanout devices operate at three strategic locations along
the linac to provide drift compensation.

S2 (Timing Pattern Generator)

S20Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

B005 (Undulator area)
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LCLS-II TIMING SYSTEMDESIGN: TIMING DISTRIBUTION

Figure shows the drift over 6 channels in S20 due
to length and heat load.

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

9LCLS-II TIMING SYSTEMDESIGN: TIMING FRAME (at glance)
Timestamp
PulseID ->Label each pulse with global pulseID for correlation across devices
Destination -> destination tag for each pulse
Fixed Rates -> Fixed Rate Markers 0-9 one bit each computed by dividing 186MHz refclk by one of 1,13,91, 910,9100, 91000
o AC Rates -> Power Line Synchronized markers (req. option to sync to power line)o Beam Request -> Beam is requested by Inj guno Requested Charge [pC]o Machine Protection System (MPS) Valido Beam Containment System (BCS) Fault
o MPS Limitingo MPS Limitso Beam Synchronous Acquisition (BSA) fields ( Init; Active: AvgDone; Update) *o Sequence Control Bits 288*This will be explained in the next few slides
The timing pattern consists of a sequence of timing frames, which contains data set by firmware and software.
oooo

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

10LCLS-II TIMING SYSTEM
Timing Pattern Requirements

FIXED RATE Patterns

Burst Spacing

Burst bunch(es)

0Hz

2-20

100Single shot

92;5;10;20;50;100

1Hz

1,21;221;50;100;200;500;1000;2000

10000

210Hz
50Hz
100Hz
1KHz

AC RATE Patterns

10KHz

0Hz

100KHz

1Hz496KHz

10Hz

930KHz

30Hz
60Hz
110Hz

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

119Hz120Hz

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LCLS-II TIMING SYSTEM
Timing Pattern Requirements
Timing Pattern Generator has 3 main types ofEngines on FPGA:•Beam Engines: Schedule beam patterns•Allow Engines: Handshake MPS/Timing• Allow table – agreement on(spacing between pulses with beam,
charge and window to evaluate the pattern)•Experimental/Control Engines: Controls bits tosupport multi-destination beam, beam
synchronous acquisitions, experiments
requirements…

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LCLS-II TIMING SYSTEM
Timing Pattern Requirements

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

13LCLS-II TIMING SYSTEM
Timing Pattern Requirements – Compatibility lookup tableMode

SC10SC11SC12SC13SC14SC15SC16SC17SC18SC19Destination
Per modes

SC1 Laser

SC1 GunSC1 TDINJSC1 DIAG0SC1 DumpBSY

SC1TDUNDHXRSC1 TDUNDSXRSC1 DUMPHXRSC1 DUMPSXRSC1S30XL

SC10SC1 Laser-SC11SC1 Gun

SC12SC1 TDINJSC13SC1 DIAG0-

SC14SC1 DumpBSYComp, Interl.

-SC15SC1 TDUNDHXRComp, Interl.

Comp, Interl.

-SC16SC1 TDUNDSXR

Comp, Interl.

Comp, Interl.

Comp, Interl.

-SC17

SC1 DUMPHXR

Comp, Interl.

Comp, Interl.

Comp, Interl.

Comp, Interl.

-SC18

SC1 DUMPSXR

Comp, Interl.

Comp, Interl.

Comp, Interl.

Comp, Interl.

Comp, Interl.

-SC19

SC1 S30XL

Comp, Interl.

Comp, Interl.

Comp, Interl.

Comp, Interl.

Comp, Interl.

Comp, Interl.

Type Patterns MPS Allowed

Override All
Screen limit 10Hz-

Full rate and charge-AC Rates up to 120Hz
Full power but below 120KW

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

10Hz10Hz

Full rate
Full rate-Special case has 3 modes

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LCLS-II TIMING SYSTEM
BEAM SYNCHRONOUS DATA SERVICES
This is a Single Pulse machine: The data acquisition requirement is to have all devices acquiring on the same bunch
SC BSA provides data buffers time stamped by the SC Timing System (Timing Pattern Generator – TPG ).
SC BSA provides data filtering according to user needs.
SC BSA provides data buffers:
Maximum of 20000 data points.
Each data point can be an average of up to 8000 beam pulses
Maximum rate up to 1MHz
Beam Synchronous Scaler Service (BSSS) provides pulse by pulse scalers up to 100Hz for control room displays

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LCLS-II TIMING SYSTEM
BEAM SYNCHRONOUS DATA SERVICES
System BSA Buffer

Beam Destination(s)Beam Rate to beam destination(s)SCD1H

D= Diag0

1 Hz

SCDTH

D= Diag0

10 Hz

Example:SCDHH

D= Diag0

100 HzSCD1H =SCL1H

L=LINAC (= SC_BSYD OR SC_HXR OR SC_SXR)

1 Hz

SCLTH

L=LINAC (= SC_BSYD OR SC_HXR OR SC_SXR)

10 Hz

SCLHH

L=LINAC (= SC_BSYD OR SC_HXR OR SC_SXR)

100 HzSCB1H

B= SC_BSYD

1 Hz

SCBTH

B= SC_BSYD

10 Hz

SCBHH

B= SC_BSYD

100 HzSCH1H

H= SC_HXR

1 Hz

SCHTH

H= SC_HXR

10 Hz

SCHHH

H= SC_HXR

100 HzSCS1H

S= SC_SXR

1 Hz

SCSTH

S= SC_SXR

10 Hz• 29 User Defined Buffers• 15 SYS Buffers

SC -> Super Conducting
D -> Diag0
1H -> 1Hz

1H is for the archive
TH is for displays
HH is for physics apps

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch data
SCSHH
S= SC_SXR
acquisition

100 Hz16LCLS-II TIMING SYSTEM
Timing Pattern Generator
Patterns Classification:•Standard Patterns: Single destination patterns for Fixed Rates, AC Rates and bursts.

•Complex Patterns:• Pulse Stealing: all pulses with beam land on the Fixed Rate Markers distributed as part of the timing pattern.
In case of multiple destination requesting beam, destination priority assigns beam pulses• Interleaved Patterns: each destination is assigned an offset from the closest fixed rate marker to therequested beam rate. The subharmonic frequency that allows to lock the two LINAC (LCLS-I and LCLS-II) is
71.5KHz. Between two fixed rate pulses at 71.5KHz there are 13 empty pulses. The offset of empty pulses
from a Fixed Rate marker, per destination, is then selected to be one of the prime numbers <13. Such as: 3 for
DIAG0, 5 for HXR and 7 for SXR. This logic allows to resolve the beam request conflict when requesting
beam to two destination.

• Bunch Train: user defined interval between beam patterns (uses the patterns from the first and second bullet)

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

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LCLS-II TIMING SYSTEM
Timing Pattern Generator (TPG) Graphical User Interface (GUI)•The timing system sends out a timing pattern that contains relevant information
to trigger the LASER system to generate beam and to the timing clients anddevices along the SC LINAC.

Timing Frame•

The timing pattern consists of a sequence of timing frames, which contains data
set by firmware and software.

TPGGUI•The firmware defines information that is constantly sent out to identify frames,such as rate specific markers, pulse ID. Other bits in the timing frame aremachine operation sensitive and need to be configured at a higher level.

Firmware

The TPGGUI is the software tool used to program timing frames, updating
information to the timing pattern to fulfill Operation requirements.

MPS/BCS••

The TPGGUI allows operations to program more complex patterns and schedulebeam going to multiple destinations while meeting machine and personnel safety
requirements.
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LCLS-II TIMING SYSTEM
Timing Pattern Generator Graphical User Interface (TPGGUI)Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

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LCLS-II TIMING SYSTEM

Commissioning Experience: SC_DIAG0 and SC_BSYD pulse stealing

Equally spaced pattern where beam is schedule to both
destination in DIAG0 and BSYD.
BSYD having higher priority.
Scheduled pattern will be 100Hz to DIAG0 and 10Hz to BSYD
with result to have 90Hz to DIAG0 and 10Hz to BSYD.
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LCLS-II TIMING SYSTEM

Commissioning Experience: SC_DIAG0 and SC_BSYD Interleaved*Not* equally spaced pattern where beam is schedule toboth destination in SC_DIAG0 and SC_BSYD.
SC_DIAG0 is off by 3 pulses from Fixed Rate Marker 100Hz.
Scheduled pattern will be 100Hz to DIAG0 and 10Hz to
BSYD with result to have 100Hz to DIAG0 and 10Hz to BSYD.
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LCLS-II TIMING SYSTEM

Commissioning Experience: SC_HXR and SC_SXR Interleaved*Not* equally spaced pattern where beam is schedule to bothdestination in SC_HXR and SC_SXR.
SC_HXR here is off by 5 pulses from Fixed Rate Marker 1Hz andSC_SXR is on the mark.
Scheduled pattern will be 1Hz to SC_HXR and 1Hz to SC_SXR
with result to have 1Hz to SC_HXR and 1Hz to SC_SXR.
Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition

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Thank you
Carolina Bianchini Mattison
carolina@slac.stanford.edu

Carolina Bianchini Mattison (SLAC) LCLS-II Timing System and synchronous bunch dataacquisition23