東京大学大学院工学系研究科
附属システムデザイン研究センター
先端設計研究部門・先端デバイス研究部門（旧VDEC）基盤設計研究部門・基盤デバイス研究部門

令和６年度
ISSN 2436-6552

年 報

2024
Systems Design Lab, School of Engineering,(VLSI Design and Education Center), The University of Tokyo

Annual Report

Systems Design Lab, School of Engineering
The University of Tokyo 2024

Message from the Director of d.lab

Tadahiro Kuroda
Director
Systems Design Lab (d.lab)
School of Engineering, The University of Tokyo

In Februaryof thisyear,
the Ministryof Education,
Culture,Sports,and ofTechnology(MEXT)
issued amost
call for
proThebook ChipWar
by Chris
Miller has
won a wide
audience.
AsScience
its subtitle
The fight for
the world’s
criticalposals undersuggests,
their「次 世代X-nics半導 体 the創 成
拠 点of形the成 battles
事 業」(Translation:
Initiative
Establish
Centers fortechnology
it depicts
in detailhistory
between nations
into
thearea ofInnovation
semiconductors.
Next-Generation
X-nics Semiconductors).
Their ultimate
goal
is thecreation offor
groundbreaking,neXt-generation,novel
But Chip War describes
only one scenario;
there areotherpossibilities
the future. That
was the motivation
semiconductors
multi-disciplinary“X”),
much like thecreationvariousfunctional
devicforme to write throughthe bookthat I originallysynergy
called (multiplication
Semiconductor
Democracy.
Thebook ofwaseventually
published
esJapanesefrom spintronics
andphotonics,
novel
computingtechnologies
from neurophysiology
and quantum
mechanics, thatandinwith themodified
titleof TheSuper-Evolutionof Semiconductors– The Futureof the Technology
integrated devices
from novel materials based on topotronics.
Dominates
the World.
The future described in the book is as follows.

Regardless of the speciﬁc form of the novel semiconductor, a key requirement is the improvement of energy efﬁciency.◇◇◇◇◇◇◇◇In the last decade,while the amount
AI processing skyrocketed by 4 orders of magnitude, the energy efﬁciency of（Translated
from theofPostscript）
general-purpose
increased
only
antwo
order
of magnitude.
has
platform
providersas GAFAM
Semiconductorprocessors
democracy
and chipbywar
are
sides
of the sameThis
coin.
Indriven
this book,my focusis on suchsemiconductor
to develop their in-house specialized chips to achieve high energy efﬁciency. However, the development of specialized
democracy.
chips
requiresincreasingly
moretime andhigher cost.
Given therapid
in AI technology,
if ittakes acontemyear to
In the19th century,
Otto vonBismarck
explained
in a speechhowironadvancemade a nation.
Indeed, ironcreateddevelopa specialized
is alreadyobsolete by the time the development is complete. The strategy for growth in theporarycitiesand gavechip,birthit toweaponry.
DXToday,
age requires
rapid iteration(being agile)
the development-improvement
can be Whatachieved
LSI chips are
the technology
battlegroundis inofsemiconductors.
Semiconductorscycle.
makeThisa nation.
willifsemiconducdesigned
theway
softwareis written
prototyped
a programis compiled
tors
create,andwhatwill they
break?andIt willbe up to the
our way
imagination
andwisdom. to make them updatable like software.
Chip makers are engaged in fierce battles to dominate in the manufacturing of next-generation semiconductors.
However, semiconductors are evolving into such a giant collection of technologies that the challenges can no

A related
questionby
is how
to acceleratetechnology
The answer
canbe foundinof
theidea of a collective
longerbe overcome
a single
corporation
or even ainnovation.
single country.
We reallyshouldthink
semiconductors
as abrain expounded
globalcommons. by Joseph Henrich, Professor of Human Evolutionary Biology at Harvard University. The bigger thecollective
brain
is,should
the easieris toacceleratetechnology innovation.
For instance,
researchecosystems.
conducted on variAs a result,
wenotitbeinstigating
semiconductor
wars; instead,
we needthroughto be building
ous
Paciﬁc islands,
the paper“Population
Size Predicts
TechnologicalComplexity
in Oceania”
foundofa correlation
Technology
is getting
more andmore complex.
Therefore,
we must lookat the entire
forest instead
the individbetweenof variationin ﬁshingandthe population
theforest,island.orThe
that, even
witha arichsmallerbrainualtrees. theThesizechallenge
ahead
for thetools
world
is how
to nurtureofthe
in reasonother words,
createindustrial
than Neanderthals, Homo sapiens were able to invent and utilize various tools is also thought to be due to their integraecosystem.
tion
Thetheinternet
has enabled
Weintocanlarge
take groups.
hints frombotanical
world. a giant collective brain of 7.7 billion people. A platform that attracts
manypeople plants
will turninto a center
for accelerated
Nowadaysflourisheverywhereacross thetechnology
globe. Theinnovation.
revolution that created the world of today was started
by flower-bearing plants.

We
at d.lab proposed
an “Agile-X
forflowers
Democratizationofresulted
Innovative
Semiconductor
Technology.”
targetbyisA
co-existence
relationshipborn Center
betweenand insects
in theirco-evolution
where oneOur
evolveda 10-fold increasein thepopulation
ofvicechipversa.
designers. To that end, we will create an agile development platform topromotingevolutionin theother, andreducebothofthetime andcost forchip
development
and prototyping
by anoforderof magnitude. During the application
The birthflowers
providedthetrigger
for the accelerated
evolution
life forms.
process,
we wereasked bythe X-nics
review committee
what
X stands
answered
thattheir
it is theunknown
Accordingto Darwin’s
theoryof evolution,
only the fittest
survive
andfor.
areWe
able
to continue
familylines. Inofa“what” innovationwillchange theHowever,world. Nevertheless,we know “where”
the innovation
willuncovered
come from.
thenutshell,life is about
competition.
the hidden mechanismof evolutionthat is beingbyThatthe islatestplatforma largepopulation
peoplecongregate.
I ampleasedto saythat our toproposalhas other.
been accepted.
scienceis wherethat livingorganisms
not ofonly
competewith eachother
but also
cooperate
help eachThat is theIbelieve that,
intheory
addition
More Moore and More than Moore, More People will accelerate the creation of intellectual
essenceof theof tosuper-evolution.
value.
Similarly, to enrich the “semiconductor forest,” it is important to find its “flower.” It was with that thought in mind
that I set forth my theory of the super-evolution of semiconductors in this book.
I started by describing how high-performance semiconductors are developed from the standpoints of More Moore
and More than Moore.

1

Next, I shared my thoughts on what high-performance semiconductors can create from the standpoint of innovation, or in other words, the standpoint of More People.
Will we be able to find the “flower” that is needed to evolve semiconductors from the age of competition to theage of co-existence and co-evolution? It is going to take more than capital and Moore’s Law to make semiconductors
a global commons.
The need is to get many people involved. That is More People.
◇◇◇◇◇◇◇◇
One other point I would like to bring up is agility.
◇◇◇◇◇◇◇◇（Translated from Chapter 1, Section 4, “The Semiconductor Forest: Co-existence and Co-evolution”）
Eventually, flowers acquired new power.
It was the shortened lifecycle. The time from pollination to fertilization was shortened from one year to a few
hours. That resulted in accelerated evolution of all life forms.
y = a(1+r)nThat is the formula for calculating compound interest, where r is the interest rate and n the number of times
interest is compounded. Even if you start with a small principal a, the future value can grow large if you continue thecompounding for a long time.
If you replace n with 1/t, where t is the development cycle time, you get the fundamental equation for the digital
economy. The same equation applies to both the improvement in chip performance and the growth of a company.
Put differently, the strategy to grow the digital economy is to repeatedly iterate the improvement cycle at highspeed. Rather than the amount of improvement (r), the key is to increase the number of times improvement is made(n), or in other words, reduce the development cycle time (t).
That is why we want to be agile.
◇◇◇◇◇◇◇◇The book presents the fundamental thinking of d.lab. I would appreciate it if you would get hold of a copy andgive it a read.

2

2024
Systems Design Lab, School ofEngineering,(VLSI Design and Education Center),
The University of Tokyo
Annual Report

C

O

N

T

E

N

T

S

Message from the Director of d.lab ……… 1
Chapter 1

Introduction to d.lab………………………………………… 4

Chapter 2

d.lab Overview and FY2023 Annual Report……… 5

2.1
2.2
2.3
2.4
2.5

Advanced Design Research Division………5
Advanced Device Research Division………12
Platform Design Research Division………13
Platform Device Research Division………17
Activity Report of ADVANTEST D2T Research Department………21

Chapter 3

Research in d.lab………………………………………………… 24

Appendix……………………………………………………………………………… 41
A

A.1
A.2
A.3
A.4

Former VDEC contents………41
VDEC CAD Tools………41
Status of Chip Fabrication Support at Platform Design Research Division………42
Seminar………45
Venture companies related to VDEC………48

Chapter 1

1﻿
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Introduction to d.lab

The VLSI Design and Education Center (VDEC)Tokyo established the Systems Design Lab (d.lab) in

was established at the University of Tokyo in 1996. At

October of 2019 and formed a strategic alliance withthe time of its founding, Japan’s semiconductor industry

TSMC a month later. d.lab was formed by establish-

held a 50% share of the USD 50-billion global market,

ing the Advanced Design Research Division and theand engineers who could hit the ground running were

Advanced Device Research Division and adding themin high demand. VDEC has since provided unparalleled,to the existing Platform Design Research Division andoutstanding education to develop many high-caliber engi-

Platform Device Research Division which had been oper-

neers for the semiconductor industry.

ating VDEC and the Takeda Clean Room. Subsequently

However, have these graduates of VDEC been able toin October of 2020, d.lab started an industrial partner-

fully realize their potential? In the last quarter century,

ship program which has grown to include more than 40

even though the global semiconductor market enjoyedcorporate members.

a rapid 7% annual growth rate, Japan’s share continued

Furthermore, the Research Association for Advanced

to shrink, falling to the current level of about 10% of a

Systems (RaaS) was founded in August of 2020 to laymarket that is now approaching USD 500 billion.

out the framework for the university to collaborate with

The current semiconductor business is one of mass

both the industry and the government. Using d.lab andproduction of high volume, low margin general purpose

RaaS to realize a two-pronged strategy of open and closed

chips. General purpose chips have been able to achieve

collaboration respectively, the university is actively pro-large volumes because of the wide adoption of the vonmoting cooperation between academia and society as well

Neumann computer architecture constructed with theas collaborative creation with industry. Our research aims

combination of memory and processor chips. While

to boost the time-performance of semiconductors, withJapan led the world in memory device innovation, it lost

target goals of 10x increase in both energy and develop-

the business competition on capital investment.

ment efficiencies.

The mass production, mass consumption model has its

Japan is aiming to transition from the current indus-

limits. Because of the excessive burdens it places on thetrial/information society to Society 5.0, a human-centric

environment, the world is now facing an energy crisis. The

society where knowledge is value. In this knowledge-based

recent trend of applying AI to big data analysis is fuelingsociety, semiconductors will evolve from being a necessity

further growth in energy consumption.

of industry to the brain cell of society.

In the middle of this development, a game changer has

What strategy should the semiconductor industry

emerged. Recognizing that it is hard to compete by using

pursue to address this evolution? It is d.lab’s mission to

general purpose chips procured from semiconductor

find the answer.

makers, technology giants including GAFA have started
to develop their own specialized logic chips in-house.
In response to this paradigm shift, the University of

4Tadahiro Kuroda
Director, Systems Design Lab

Chapter 2

d.lab Overview and FY2023 Annual Report

2.1 Advanced Design Research Division
2.1.1

Division Overview

like to thank these members again for their participation.

consists of four professors, one associate professor, one

COVID-19 into a Class 5 infectious disease that lifted

lecturer, one project professor, and one senior fellow (joint

government-imposed restrictions on daily activities, inappointments included, as of Mar 2024). Its goal is toaddition to organizing various seminars in the form of

enable the design of integrated circuits with both highwebinars as in previous years, we were able to pursue ourenergy efficiency and high design efficiency.

original vision of not only sharing the research accomplish-

In August 2022, NEC Corporation, the University ofment of d.lab, but also hosting multiple in-person events

Tokyo, and Canon Inc. were selected to undertake theto enable program members to interact with renowned

research and development of versatile high-level synthesis

professors and students from the University of Tokyo,

technology and novel, general-purpose, data-flow com-with universities and research organizations from aroundputing mechanism by the New Energy and Industrial

the world, and with other industrial executives and lead-Technology Development Organization (NEDO) underers, as well as events to share information and knowledge

its Project for Innovative AI Chip and Next-Generationfrom international conferences, and to introduce and offer

Computing Technology Development, R&D Area

the chance to experience the most advanced technologies

4: Technology Development to Accelerate Industrialfrom the likes of Samsung Electronics. The remainder ofApplication of AI Edge Computing. The research isthe section summarizes the Partnership Program activities

scheduled to be completed by Mar 31, 2025.

of FY2023. As in previous years, our activities spanned

In addition to its research effort, the Advanced Design

almost the entire year from May 2023 to Mar 2024. Table

Research Division has two organizational responsibili-

2.1.2 summarizes the events and seminars we held inties. First, it operates the d.lab Partnership Program withFY2023.

help from other d.lab divisions. Second, it operates theWe held our first event of the fiscal year on May

Research Association for Advanced Systems. The follow-

31, 2023, in Ito Hall at the University of Tokyo which

ing section is the FY2023 report on these two operations.

featured a Program kickoff Meeting with special pres-

2-1

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CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCIn FY2023, because of the reclassification in May of

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The Advanced Design Research Division faculty

entations followed by a reception. With the start of a
2.1.2

d.lab Partnership Program Activities

new semiconductor era, advanced semiconductors have

The d.lab Partnership Program was launched in FY2020

become a strategic resource for economies of this century

to establish an international center of knowledge-valuethat is more important than oil was in the past. As awhere system designers and members of the semiconduc-

result, it is attracting a lot of investments and great expec-

tor industry meet to exchange information and ideas andtations. With that as the backdrop, the d.lab Partnershipto engage in open discussion of collaboration between aca-

Program Kickoff Meeting was honored to have Tetsuro

demia and society. The Program aims to create a hub that

Higashi, Chairman of the Board of Directors of Rapidus

brings together ideas from system designers in industries

Corporation, deliver a special presentation entitled “Theincluding IoT, AI, 5G, automated driving/control, andEstablishment of Rapidus and LSTC for the Sustainable

healthcare, advanced semiconductor technologies such as

Development of the Most Advanced Semiconductors,”

advanced CMOS processes and 3D integration technol-

where he provided an overview of Rapidus and LSTC andogies, as well as enablers of such technologies including

his expectations for the future of Japan’s semiconductormaterials and manufacturing equipment. In FY2023, a

industry. It was followed by an introduction to the four

total of 51 corporations joined the Program. Table 2.1.1

major R&D projects underway at d.lab, as well as an

contains the list of FY2023 corporate members. We would

overview of the research being pursued by d.lab’s faculty5members. The event was held in a hybrid format, accom-

the company’s foundry business strategy, advanced pack-modating both online and in-person participation at Ito

aging technology, and semiconductor equipment of theHall. After the meeting, in-person participants joined afuture, as well as its R&D strategy in Japan.

reception for networking and idea exchange.

2-1
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On Sep 25 and 26, the d.lab Partnership Program organ-

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On Jun 28, we hosted a seminar to report on the 2023

ized its first two-day, one-night field trip. The destination

IEEE 73rd Electronic Components and Technology

was the island of Kyushu, which is attracting the mostConference (ECTC2023). The conference is organizedattention in the revival of Japan’s semiconductor industry

by the IEEE Electronics Packaging Society to provide a

today. We started Day 1 with a visit to Tokyo Electron

forum for wide-ranging discussions of the science andKyushu, Ogic Technologies, and Rorze Corporation. That

technology of packages, components, and microelec-

was followed by a technical exchange meeting with mem-tronics systems. It is one of the world’s long-establishedbers of the Kumamoto 3D Consortium, where seminarsrdand foremost international conferences, held for the 73

and poster sessions stimulated in-depth discussions. The

time last year. It was held in Orlando, Florida, USA. The

night was spent in Kumamoto City. The following day, we

technology program covered the latest achievements intraveled by bus to Itoshima City, Fukuoka Prefecture, todevelopment and innovative technologies from across thevisit the 3D Semiconductor Research Center. In addition

full spectrum of packaging technology. Its main topics

to touring the facility, we listened to presentations on

included chiplets, hybrid bonding, modeling and simu-

the research accomplishments of the Center. We would

lation, interconnection, material and process, reliability,

like to thank everyone from the prefectural office who

and manufacturing technology. In our report, we focusedprovided consultation starting from the planning stage

on the latest trends and topics in advanced packagingof the trip, as well as everyone who welcomed us to theirtechnology and next-generation core technology.

organizations during this tour. Thanks to them we were

On Jul 12, we held another seminar to report onable to feel firsthand the passion and commitment of thethe 2023 VLSI Symposium on Technology & Circuits,

people of Kumamoto and Fukuoka to semiconductors inwhich took place from Jun 11 to 16 in Kyoto, Japan.

these two days.

Since 1987, this has been a premier international confer-

On Oct 25, we held a seminar entitled “The Latest

ence for the microelectronics industry on state-of-the-art

Devices and Processes Enabling AI and Logic LSI” where

semiconductor device and process technology, as well

we introduced the latest technologies and explored the pos-as semiconductor circuit technology, jointly held by thesibilities they enable. First, Associate Professor Kobayashi

IEEE Electron Device Society/Solid State Circuits Societyof d.lab presented nanosheet FET which is expected toand the Japan Society of Applied Physics (sponsored by the

replace FinFET starting with the 2nm generation. That

Institute of Electronics, Information and Communication

was followed by an introduction to nanobridge technol-

Engineers). Its location alternates between Kyoto, Japan,

ogy by Mr. Tada of NanoBridge Semiconductor, Inc.,and Honolulu, USA. In 2023 it was held in Kyoto. With

which enables post-fabrication circuits reconfiguration“Rebooting Technology and Circuits for a Sustainable

by embedding ultra-small switches within the multiple

Future” as its theme, the program covered the latest tech-wiring layers of logic LSI chips. The final presentation

nologies in advanced logic CMOS, memory, image sensor,

was delivered by Mr. Aiko on the cuLitho technology

photonics, machine learning, AI, digital, communication,from nVidia that is expected to both reduce power con-and analog. We focused our report on the technology

sumption and shorten turnaround time of photomask

trends and topics in the areas of circuit/communications

patterning, which is one of the bottlenecks in semicon-

system, AI/machine learning, advanced CMOS, advanced

ductor development today.

memory, and process technology for 3D integration.

6

On Nov 24, we held a technical exchange meeting for

On Sep 5, we welcomed Samsung Electronics, which

our corporate members in Takeda Hall of Takeda Building

is expanding its R&D activities in Japan, to Takeda Hallat the University of Tokyo. Presentations by nine of ourfor a series of presentations. Executives from the company

corporate members were followed by a poster session

headquarters and its Japan research center presented onin the foyer participated by eleven member companies.

The event was marked by a lively atmosphere with ourof imaging devices, memory, machine learning, RF, wire-

members not only networking with each other but alsoless, data converters, digital architecture, digital circuits,

engaging in discussions with our faculty members andpower management/analog, wireline, and technology

students.

directions.

We are in an era of fierce competition around the world to

COVID era, we organized a mix of remote seminars thatdevelop semiconductor-related technologies. Various pro-offer convenience to participants and in-person events

posals are being put forth to deliver system performance,that promote deeper exchange and relationship building.

including chiplet and 3D IC, which create diverse require-

We were able to incorporate entirely new activities like thements for semiconductor materials. In addition, there are

two-day field trip to tour the Kyushu area. In FY2024,

demands to shorten the development cycle all the way to

we plan to continue to organize events to promote active

productization. The seminar started with a presentation

intellectual exchange between our Program members andby Mr. Tamura from the Data-driven Algorithm Teamthe university community, as well as exchange among ourof the National Institute for Materials Science on the

Program members.

innovative approach to materials exploration that is basedon automated materials development and testing usingmaterials informatics. It was followed by a discussion of

2.1.3

Research Association for Advanced Systems Activities

the latest trends in semiconductor packaging delivered

The Research Association for Advanced Systems (RaaS)

by Mr. Ozaki of Namics Corporation, who is serving as

was established on Aug 17, 2020. The goal of RaaS is tovice-chairman of the JEITA Jisso Technology Roadmap

increase 10-fold the development efficiency of specialized

Advisory Committee, as well as chief of WG1 and deputy

chips, which are indispensable in a data-driven society,chief of WG3. The seminar ended with an introduction

by constructing a design platform for such chips and by

by Professor Mita of d.lab to the University of Tokyo’s

adopting an open architecture for hardware design. In

super-clean room that can be used to confirm the suita-

addition, RaaS aims to increase 10-fold energy efficiency

bility of materials developed through such R&D efforts.

by researching and developing 3D integration technology

At the beginning of the year on Jan 19, 2024, we heldand by stacking multiple chips manufactured in the latest

a seminar to report on IEDM2023. IEDM (International

RaaS believes that the driver of the semiconductor

conference on device technology organized by IEEE. The

industry is once again swinging back from general-pur-conference was held in a hybrid format – allowing bothpose to specialized chips, against the backdrop of thein-person and on-demand participation – from Dec 3 tounique energy crisis of the data society. The crisis is being

7. In our meeting, faculty members from d.lab provided

spurred by the exponential growth in data and thean overview of the conference and discussed the latest

increasing sophistication of AI processing. On the current

trends in device technology, focusing on advanced CMOS

trajectory, IT equipment alone is expected to consume

device technology and materials, non-volatile memory

close to twice the total available power of today by 2030,

technology, computing technology, and 3D integration

and about 200 times the total available power of today by

and implementation technology.

2050. It will be impossible to realize a sustainable future

Mar 18, 2024, to report on the 2024 International Solid-

C

7nm CMOS technology in a single package.

Electron Devices Meeting) is the world’s top international

We ended our FY2023 seminar series with a meeting on

2-1

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCIn FY2023, to meet the needs of the times in the post-

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On Dec 13, we held a seminar focused on materials.

if digital transformation consumes so much energy as todestroy the earth’s environment.

State Circuits Conference (ISSCC2024). The conference

Under such a condition, only those who can improve

was held from Feb 18 to 22 in San Francisco, USA. Theenergy efficiency 10-fold can afford to increase computer

papers presented this year had to go through an especiallyperformance 10-fold, or extend smartphone use 10-fold.

competitive selection process. Our faculty members pre-Compared to general-purpose chips which are required tosented an overview of the conference and summarized thehandle all tasks, specialized chips achieve orders-of-mag-keynote presentations as well as presentations in the areas

nitude improvement in energy efficiency by eliminating

72-1
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unneeded circuits. That is why specialized chips are intechnology. We aim to create a development platform todemand. In addition, since AI processing utilizes neuralrealize agile authentic prototyping where prototypes can

networks which process data in parallel, it is difficult

be created rapidly by innovating silicon compiler technol-

for von Neumann architecture designed for sequential

ogy to enable designing chips like writing software.

processing to deliver adequate performance. As a result,

Our technology goal is a 10-fold increase in both

specialized chips are being developed around the world

development efficiency and energy efficiency. We plan

to serve as AI accelerators. Furthermore, the slowing of

to improve development efficiency by creating an agile

Moore’s Law is providing additional tailwind for special-design platform and adopting an open architecture. In

ized chips.

addition, we aim to increase energy efficiency through

Unfortunately, specialized chips development requires
special skills and cannot be easily undertaken by everyone.

cess and implementation of 3D integration.

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The latest chips integrate more transistors than there are

We provide semiconductors as a service, rather than sell

people in the world. Development costs have skyrocketed

them as a product. It is the role of RaaS to develop thein recent years to approach $100 million. It will takenecessary technologies to achieve that goal.

even a team of several hundred designers several years to

In FY2021, RaaS applied to and was accepted

develop a specialized chip, which makes it difficult to keepby the “Project for Research and Development ofpace with today’s rapid technological advance.

Enhanced Infrastructures for Post 5G Information

In software development, bugs can be patched afterand Communications Systems / Development of

the fact. But hardware cannot be shipped unless it isAdvanced Semiconductor Manufacturing Technology

completely error-free. Compared to software, hardware(b) Development of Advanced Semiconductor Backend

development is indeed hard and carries more risk.

Processing Technology (More than Moore)” of the

If technologies similar to compilers used in software

New Energy and Industrial Technology Development

development are available to chip development, in other

Organization (NEDO). The development theme is “(b2)words, if silicon compilers become a reality, we can expect

Implementation Technology for Edge Computing.”

both hardware development cost and risk to drop. In

In system R&D, we welcomed new members Advantest

addition, more people can become hardware designers.

and Riken in FY2023 and commenced research under

Eventually, as the open-source culture takes root in hard-a new 3-year plan with new objectives. In technology

ware development and the supporting ecosystem expands

R&D, based on the NEDO project mentioned above,and develops into a multi-layer network, mass collabora-

RaaS focused its efforts on the establishment and imple-

tion will become possible. When that happens, one will bementation of technology for WoW (wafer-on-wafer)able to develop chips like writing software.

and CoW (chip-on-wafer) integration using Cu-Cu low

Alan Kay once said that “People who are really serious

temperature bonding as part of its direct bonding 3D

about software should make their own hardware.” Indeed,

integration technology development (equipment and pro-system development requires both hardware and software

cess development for WoW and CoW).

development.
Our goal at RaaS is to democratize access to silicon

8

manufacturing chips in the most advanced CMOS pro-Table 2.1.1 L ist of FY2023 d.lab Partnership Program
Members (in Japanese phonetic order)

2-1
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Aoha, Inc.
Asahi Kasei Microdevices Corporation
ADEKA Corporation
ADVANTEST CORPORATION (RaaS)
Analog Devices KK
Ushio Inc.
ORGANO CORPORATIONKIOXIA Corporation
Kobe Steel, Ltd.
Kobelco Research Institute, Inc.
Foundation for Promotion of Material Science and Technology of Japan
Samsung R&D Institute Japan
Siemens Electronic Design Automation Japan K.K.
JSR Corporation
JCU Corporation
Shin-Etsu Chemical Co., Ltd.
SCREEN Holdings Co., Ltd. (Raas)
Sumitomo Corporation
Socionext Inc.
Sony Corporation
Daikin Industries, Ltd. (RaaS)
Dai Nippon Printing Co., Ltd.
DISCO Inc.
DIPSOL CHEMICALS Co., Ltd.
Tokyo Electron Ltd.
TOKYO OHKA KOGYO CO., LTD.
Toyobo CO., LTD.
TORAY INDUSTRIES, INC.
Toppan Printing CO., LTD. (RaaS)
Nagase & Co., Ltd
NIKON CORPORATIONIBM Japan, Ltd.
Cadence Design Systems, Japan
Nihon Synopsys G.K.
JEOL Ltd.
NEXTY Electronics
Panasonic Industry Co., Ltd.
Panasonic Connect Co., Ltd. (RaaS)
Semiconductor Energy Laboratory Co., Ltd.
Hitachi, Ltd. (RaaS)
Fujitsu Ltd.
FUJIFILM Corporation (RaaS)
Micron Memory Japan, G.K.
Mitsubishi Chemical Corporation
Mitsubishi Electric Corporation
MIRISE Technologies Corporation (RaaS)
Murata Manufacturing Co., Ltd.
RIKEN (RaaS)
Renesas Electronics Corporation
Resonac Corporation
ROHM Co., Ltd.

9

Table 2.1.2
Date
5/31/2023

2-1
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6/28/2023

7/12/2023

9/5/2023

9/25-26/2023

10/25/2023

11/24/2023

10

List of FY2023 d.lab Partnership Program Seminars
Title
Presenter(s)FY2023 d.lab Partnership Program Kickoff with Special Presen- Tetsuro Higashi, Chairman of the Board, Rapidus
tations
Corporation
Tadahiro Kuroda, Professor, d.lab
Masaaki Niwa, Senior Fellow, d.lab
Kazutoshi Wakabayashi, Senior Fellow, d.lab
Tohru Mogami, Project Researcher, d.lab
Makoto Ikeda, Professor, d.lab
Yoshio Mita, Professor, d.lab
Masaharu Kobayashi, Associate Professor, d.lab
Tetsuya Iizuka, Associate Professor, d.lab
Atsutake Kosuge, Lecturer, d.lab
ECTC 2023 Report
Masaya Kawano, Project Researcher, d.lab
Takeshi Takagi, Principal Researcher, d.lab
Kazunori Yamamoto, Project Researcher, d.lab
Katsuya Kikuchi, Research Group Leader, 3D Integration System Group, AIST
2023 VLSI Symposium Report
Mototsugu Hamada, Project Professor, d.lab
Atsutake Kosuge, Lecturer, d.lab
Toshiro Hiramoto, Professor, d.lab
Shinichi Takagi, Professor, d.lab
Masaharu Kobayashi, Associate Professor, d.lab
Masaaki Niwa, Senior Fellow, d.lab
Samsung Day
Kim Seonsik, EVP at HQ & University Relations
Center (URC), Samsung Electronics
Jeong Gibong, EVP, Samsung Foundry
Park Cheolmin, VP, Advanced Package (AVP)
Songyun Kang, Master at Mechatronics Research
Hiroichi Kawahira,R&D Center Chief, Samsung Device Solutions
R&D Japan, & SVP, Samsung Japan
Kyushu TourTokyo Electron Kyushu
Ogic Technologies
Rorze Corporation
Kumamoto 3D Consortium
3D Semiconductor Research Center
The Latest Devices and Processes Enabling AI and Logic LSI
Tohru Mogami, Project Researcher, d.lab
Masaharu Kobayashi, Associate Professor, d.lab
Munehiro Tada, VP, NanoBridge Semiconductor,
Inc.
Hiroshi Aiko, Marketing Manager, nVidia
d.lab Partners Technical Exchange
Kobe Steel, Ltd.
Mitsubishi Chemical Corporation
Kobelco Research Institute, Inc.
JSR Corporation
Socionext Inc.
Renesas Electronics Corporation
IBM Japan, Ltd.
KIOXIA Corporation
Murata Manufacturing Co., Ltd.
Cadence Design Systems, Japan
Nihon Synopsys G.K.
ADEKA Corporation
Siemens Electronic Design Automation Japan
K.K.

Date
12/23/2023

ISSCC2024 Report

2-1

C

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

3/18/2024

IEDM2023 Report

Presenter(s)Kazunori Yamamoto, Project Researcher, d.lab
Ryo Tamura, Leader, Data-driven Algorithm
Team, National Institute for Materials Science
Yuji Ozaki, Vice-Chairman, JEITA Jisso Technology Roadmap Advisory Committee, Chief of
WG1, Deputy Chief of WG3, Manager, Namics
Corporation
Yoshio Mita, Professor, d.lab
Toshiro Hiramoto, Professor, d.lab
Shinichi Takagi, Professor, d.lab
Masaharu Kobayashi, Associate Professor, d.lab
Ken Takeuchi, Professor, d.lab
Takeshi Takagi, Principal Researcher, d.lab
Makoto Ikeda, Professor, d.lab
Ken Takeuchi, Professor, d.lab
Tetsuya Iizuka, Associate Professor, d.lab
Mototsugu Hamada, Project Professor, d.lab
Atsutake Kosuge, Lecturer, d.lab

CCCCCCCCC

1/19/2024

Title
d.lab Materials Seminar

11

2.2

2-2
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CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
12Advanced Device Research Division

Advanced Device Research Division is working forlamination technology (equipment and process devel-

the development of three-dimensional (3D) integration

opment for WoW and CoW)”. This project aims totechnology and advanced device technology aiming at ten

develop and implement key point technology related totimes higher energy efficiency of semiconductor systems

WoW (Wafer on Wafer) bonding technology and CoWin the data-driven systems.

(Chip on Wafer) bonding technology by low-temperature

In computing technologies such as AI, which require

hybrid bonding of Cu-Cu.

large amounts of data processing, energy consumption

This year is the third year of the project, and the main

associated with large and frequent data transfers between

equipment has been built up and basic performance has

memory and processors has become a major issue. As abeen confirmed. In addition, basic characteristics were

technology to solve such problems, we are focusing on

demonstrated in the development of elemental technol-

direct bonding 3D stacking technology that forms direct

ogy and the intermediate targets were achieved. RaaS

bonds at the chip level or wafer level, shortens the distancepassed the stage gate examination conducted in Januaryof data movement, and improves energy efficiency.

2024, and is accelerating research and development

In the NEDO project “Post 5G information com-

toward achieving the final goal in June 2026.

munication system infrastructure strengthening research

In addition, in collaboration with the Institute ofand development project / development of advanced

Industrial Science and the Department of Materials

semiconductor manufacturing technology (subsidy)”

Engineering, we proposed a new proposal to JST ALCA-

adopted in 2021, The Research Association for Advanced

Next titled “Development of 3DIC heat dissipation

Systems (RaaS), a technology research association on 3Dtechnology based on phonon engineering,” which was

integration technology operated by d.lab as the head-adopted. We plan to research and demonstrate 3DIC heatquarters, is working with member companies of RaaS

dissipation technology during the small phase leading up

on the theme of “Development of direct bonding 3D

to the stage gate scheduled for the end of 2026.

2.3 P latform Design Research Division (VDEC Function) FY 2023 Report
and FY 2024 plan
2.3.1

Overview of Platform Design Research Di-

conducted in the form of on-demand plus live Q&A

visionsessions to improve the convenience of participation. In

Education Center (VDEC) at the University of Tokyo has

chains of various companies are becoming more complex

been developing projects that contribute to integrated cir-and it is difficult to fully use the introduced tools, lectures

cuit design education at universities and technical collegeson the tool-chains recommended by each tool vendor

in Japan, based on the three major roles: ”spreading thewere also held in conjunction with the individual toollatest information on VLSI design and education,” ”pro-seminars. From the end of FY2019, we received permis-

viding licenses of CAD tools,” and ”supporting on VLSIsion from each EDA vendor to use EDA tools from home,chip fabrications for academic use.” On October 1, 2019,to avoid delay&slowdown in integrated circuit design

VDEC has been re-organized into Systems Design Lab

research and education in Japan.

(d.lab), Graduate School of Engineering, the Universityof Tokyo as part of an organizational restructuring aimed
at strengthening integrated circuit related activities in

2.3.2

Status of Education at Platform Design Research Division

the University of Tokyo's semiconductor integrated cir-

The LSI Design Flow Seminar is designed to educate

cuit-related activities. The Platform Design Research

the basic concepts of LSI design and to provide hands-on

Division of d.lab continues to carry out the functions ofexperience of practical design examples using multiple

the VDEC and continues “VDEC activities” seamlessly.

CAD tools. For this purpose, VDEC has been organ-

Here, the outline of “VDEC activities” of the FY2023 isizing LSI design education seminars as well as “Refresh

reported below.

Seminar” for re-education programs for engineers.

The missions of VDEC are for advancement of

In FY2022, we have canceled “Refresh Seminar,” butresearches and education on LSI design in public andrestarted it in FY2023 with help from adjunct professors

private universities and colleges in Japan and send manyof VDEC.

distinguished VLSI designers into industry. After 27 years

In addition to these seminars, VDEC holds the “VDEC

of VDEC establishment, educations on CAD software,

Designers’ Forum” once a year, mainly for young faculty

LSI design and design flow in universities have been

members and students. This is a workshop-style meeting,well established. On the other hand, advancement on

where participants bring their design cases and exchange

nano-meter CMOS technologies forces design flow andtheir successes and failures, in addition to invited lec-

CAD software complicated. We have been continuingtures from companies and universities. In FY2023, theCAD tool seminar by the lecturers from EDA vendors for

VDEC Designer Forum had been held in hybrid format

twice a year. We hold the seminar in VDEC and provide

at Kawatana Grand Hotel. Since FY2011, the “IEEE

distance learning through video streaming. We expect

SSCS Japan Chapter VDEC Design Award” has been

spread of the up-to-date LSI design methodology by usingpresented as an award for VDEC activities. The final

CAD tools.

judging and awarding of the “IEEE SSCS Japan Chapter

In order to make it more convenient for the partici-

VDEC Design Award” has been held at VDEC Designers’

pants, the seminars have been held only in Tokyo since

Forum since 2011, and in 2023, the IEEE SSCS Japan

2009, and at the same time, the seminars have been

Chapter VDEC Design Award will be presented to Mr. Y.

broadcasted to individual participating lab. The VDEC

Yamasaki of Tokyo Institute of Technology. Four VDEC

expects that the latest CAD use-case will be shared among

Design Award Excellence Awards, (Mr. Y. Yamazakilabs through the seminar organized by VDEC, and will be(Tokyo Institute of Technology), Mr. Y. Nakanishi (Naraa trigger to spread the technology nationwide. In FY2022,

Institute of Science and Technology), Mr. Li Shuowei

all seminars will be conducted online. Some items were(University of Tokyo), and Ms. Y. Shishido (Kyushu

2-3

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addition, in view of the current situation where the tool-

CCCCCCCCC

Since its establishment in 1996, the VLSI Design and

13Institute of Technology)) and two VDEC Design

contribution as a tool to demonstrate the basic idea of theAward Encouragement Prizes (Mr. R. Okada (Nara

research is also significant.

Institute of Science and Technology), Ms. A. Otani(Ritsumeikan University)), and two VDEC Design Award

2-3
CCCCCCCCC
C

2.3.4

Report on AI Chip Design Center

Commendation Prizes for Idea Contest (Mr. A. Roberto

VDEC and the AIST have been jointly commissioned(Yamagata University) and Mr. R. Hotta (Ritsumeikan

by NEDO to develop a common platform technology for

University)). This year, we also recognize three as the final-

accelerating AI chip development under the “Innovation

ist of VDEC Design Award (Mr. S. Tanabe (Shizuoka

Promotion Project for Accelerating AI Chip Development

University), Mr. K. Tatsuta (Ritsumeikan University), and/ R&D Item 2: Development of Common Platform

Mr. H. Zhang (University of Tokyo)).

Technology for Accelerating AI Chip Development” since

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

Although the educational system through such semi-

2018. In this project, we have established an EDA uti-nars and forums has enabled students to learn the basics

lization and design environment for venture companiesof LSI design, they still face various difficulties in actualand small and medium-sized enterprises(SMEs) in Japan,

LSI design situations. For beginners, setting up the CAD

and are working as an “AI chip design center(AIDC)”.

software is the biggest problem. Even after setting up

In this activity, in addition to the introduction of EDA

the software, they are often baffled by the “difficult error

tool licenses that allow venture companies and small andmessages” issued by the CAD software. VDEC users canmedium-sized companies to prototype up to engineering

register for the “CAD mail group” and the “Prototyping

samples, we have introduced IP for 40nm, 28nm, andTechnology User Group” on the VDEC website, where

12nm, and are also providing a large-scale, high-speed

they can post their questions and ask for help. The regis-

design and verification environment using a hardware

tered users of the mail groups are not obligated to respond,emulator, which was introduced with a subsidy from thebut in most cases they can get help from experienced users

Ministry of Economy, Trade and Industry at the start ofwithin a few hours or days. We hope that you will takethis project. In FY2020, we have designed a SoC platform

advantage of this system to help solve your problems.

with NoC, PCIe, DDR4, etc., and multiple functional
IP cores, and taped out the platform as a SoC with mul-

2.3.3

Publications related to Platform Design Re-

tiple AI IP cores designed by multiple users, and after

search Division

almost 1-year delay, we have received assembled chip in

Figure 2.3.1 shows the use of the VDEC facility in the
published literature related to VDEC. It can be confirmedthat CAD software is widely used in writing papers. Since
CAD software is often used not only in chip design but
also in the preparation stage of chip prototyping, its

Fig. 2.3.1 Trends of number of papers through VDEC activities.

14

Fig. 2.3.2

Number of papers related to VDEC facilities.

licenses for industrial applications. The main objective of

evaluate most of SoC functionalities and by the end of

this project is to provide small and medium-sized ven-

March 2022, almost all of IPs got fully verified. We haveture companies with a development environment for AI

also designed and taped out with 4 AI IP cores in 12nm

chip design, evaluation, and verification in order to accel-in June 2022, and all the IP cores have been success-erate the development of AI chips, but we also plan to

fully demonstrated by the end of March 2023. In orderimprove the environment for use by universities in orderto further strengthen this activity, we are accelerating

to promote university-originated companies in the field of

our research by establishing the "AIST-The University

AI-related integrated circuits.

of Tokyo AI Chip Design Open Innovation Laboratory"(AIDL) in the Takeda Building, Asano Campus, The

C

University of Tokyo on September 1, 2019.
Plan for FY 2024 “VDEC Activities” of Platform Design Research Division
In FY2024, we will continue the VDEC Activities foracademics as before.
【Design related information dispatching/Seminar】

We will continue holding the following seminars: (1)CAD tools seminars which have been continued since1997, (2) “Refresh seminar” since 1998, (3) “Designer’

CADUserLicense

Forum” since 1997. We will also continue seminars for
LSI tester usage at VDEC and sub-centers, workshops on
LSI testing technologies initiated by D2T.

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

2.3.5

2-3
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the beginning of Jan. 2022, and after one week we could【CAD tool support】

We will continue Cadence tools, Synopsys tools and
Mentor tools as the main stream design tools. We willcontinue analog ADS/EMPro/GoldenGate by Agilent,
C-based design environment, BachC by Sharp. In addition, we continue trial of several CAD tools, such aslayout platform, Lavis by TOOL. Design debugging platform from SpringSoft has merged into Cadence tools andwill be continued.

CADUser【Chip fabrication services】

We will continue chip fabrication services for 0.18µm
CMOS by Rohm, 0.8µm CMOS by JS Foundry (former
On-semiconductor-Sanyo/Motorola Japan), and IHP
SiGeBiCMOS 0.18um as the regular services.
In addition to the above. We will continue to developan "AIDC” activities, in collaboration with AIST. We
will introduce a logic emulator for large-scale AI digitalchip design verification, and maintain and operate EDA

CADLicense

15

Table 2.3.1

Chip fabrication schedule【CMOS 1.2μm 2P2M】 JS Foundry (Former On-Semiconductor/Motorola Japan)
2024#12024#2Chip application deadline
2024/7/16
2025/1/6

Design deadline
2024/9/24
2025/3/24

Chip delivery
2024/12/16
2025/6/23

Design deadline
2024/6/24
2024/9/2
2024/10/21
2025/2/3

Chip delivery
2024/10/9
2024/12/14
2025/2/18
2025/5/16【CMOS 0.18μm 1P5M(+MiM)】 Rohm
2-3
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CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
162024 #1
2024 #2
2024 #3
2024 #4

Chip application deadline
2024/4/1
2024/6/10
2024/7/29
2024/11/14

2.4

Platform Device Research Division

2.4.1

Mission“own” such large-scale facility and necessary budget byviding every researcher with three essential elements forother researchers in a platform, which is equally open to

research on new devices. The division is with around 30

everybody, they can “effectively own” the most advanced

staffs, empowered by Professor Yoshio Mita, the play-“open platform”, and thereby the cutting-edge researching division director who himself actively performs

activities can be held anywhere in Japan. This is the prin-experiments in the Cleanroom as a leading researcher,ciple of d.lab’s open device platform, which is in fact

and operated in collaboration with related departments

a lateral expansion of “shared economy model in VLSI

(such as Institute of Engineering Innovation, Electricaldesign and fabrication” to micro-nano fabrication andEngineering and Information Systems, and Mechanicalmeasurement research field, originally established byEngineering) in terms of human and budget resources.

VDEC for Japan in 1996.

Research in emerging fields of semiconductor electronics

Towards that end, d.lab Platform Device Researchdevices (such as integrated circuits), sensors and microsys-

Division takes full advantages of spaces (of its own andtems requires three essential elements: (1) fabricationof open rental) in Takeda Sentanchi Building. The build-machines with stupendous amount of budget, (2) richth
ing was inaugurated on 17 December 2003, thanks toaccumulation of fabrication technology knowledges,

the enormous donation in 2001 from Mr. Ikuo Takeda

and (3) research capability to develop new technologies(founder of Advantest) to the faculty of engineering

required for new devices. In Japan, these three elements(Dean was Professor Hiroshi Komiyama) as well as VDEC

had been prepared and kept in an individual research(director was Professor Kunihiro Asada). In the build-thgroup until the end of 20 century. However, due toing, a 600m2-square supercleanroom including “official

the technology trends towards advanced fabrication overISO3 (a.k.a. federal class 1. Once measured as ISO1)”larger-scale wafers, it has become almost impossible for aarea (Fig.1). The cleanroom and affiliated experimental

research group to purchase and maintain the cutting-edge

rooms are equipped with cutting-edge nanofabricationstfabrication machine line, in the 21 century. Originally,

and measurement machines, total valued over 5.0 billion

it was impossible for every research group in universities,

yens (32M euros, due to low JPY ratio). The users cancompanies, research institutes, and NPOs, to exclusively

openly use such nice machines really inexpensively.

2-4

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CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

themselves; If researchers wish to “cooperate” with the

CCCCCCCCC

D.lab platform device research division aims at pro-

建物
用地

寄付

超純水

購入

２００３
２００１

大型装置

購入

大型装置

寄付

２００４
２００５
2006 MITA,
YoshioFig.1

1Development of Takeda Sentanchi Supercleanroom

17

Clean Drafts

1. Cleaning, annealing

2. Material deposition

3. Lithography

2-4
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4. Etching

5. Dicing and bondingC

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6. Characterization

Fig.2

UV1
AQ-50

i-Miller(x2) EB-380
CFS-4ES Evap.(x2)Oxidation
SIH-450

RTA HP2-9
Inertgas OvenSCFDElectroplating(Au/Cu/Ni)

PM６ 4”CMP

Parylene
PECVD Cetus
ALD FlexAL

ZEP auto dev.
F5112 EB
MA-6 PEM-800
Spray coater×２＋ EB
F7000S＋
436/405/365nm
Automatic Liftoff
Beamer＋Tracer Mask Auto Dev.
DWL66+ 405nm HMDS Coater
V400ACE FIB
DWL66+ 375nm
Xvision200TB FIB
MUC-21 Pegasus NLD-5700Si
Ion
ShowerSamco 10NR
NE-550 ICP
Idonus VaporHF
Samco XeF2
CE-300I ICPSand blast
Samco FA-1
CE-S ICPDAD3460 diamond 7476D wedgebond 4700E autobond
DFL7340 stealth
7200C diebonder
Lambda2 flipchip
Suss BA8
Elite300 proberMSA-500
Electrical measurements
8” prober
Shield room

X1. In-line test
RegulusSU8230 SEM
TM3030 SEM+EDX
JSM-6610LV SEM+EDX+Analyzer
Crossection Polisher / PECS /Carbon Coater
Phi680 AES
Bruker Dimension Icon AFM L-traceII
Dektak, Tohospec,
OLS5000 Confocal
VHX-6000 Digital Microscope
Microscopes
VR-120S resistivity

X2. Package / Jigs
LPKF Protolaser U4/ProtoMat S62
60W CO2 laser cutter Universal VLS4.60
1kW Fiber Laser cutter HGCF0606
NC Roland MDX-40
Metal NC Kitmill NC Micro MC-1
3D Printer Afinia H+ / Projet MJP5500X
Eximer ablator Hamamatsu

List of equipment under d.lab Platform Device Research Division

Over 100 apparatuses are openly accessible (Fig.2),

can drastically minimize costs (personnel, budget, andincluding, “world’s fastest” large-area direct electron beamtime), which should have otherwise been totally covered(EB) writing machine Advantest F5112+VD01, whichby each researcher, and can directly jump into advanced

has been donated according to the wise decision of Mr

research. Key Performance Indicators of such benefits

Ooura, a chairman of Advantest, fine EB writer Advantest

are as follows: over 9.0 billion yens for installation cost

F7000S-VD02 and Silicon Deep Reactive Ion Etchingof building and equipment, over 350 million yens formachine SPTS MUC-21 ASE-Pegasus, both purchased

yearly operating cost, and reduction of over 20 years’by Japanese government’s supplemental budget (known

leading time to acquire know-hows in advanced fabrica-

as Abenomics, the first arrow), and the scanning electron

tions. These benefits have attracted many research groups.

microscope (SEM) Hitachi Regulus SU8230 that pro-

Since ten years, the number of research groups who sent

vides highest-class resolution among those obtainable byus the letter of consensus exceeded 780. Over 1128 mem-

research laboratory. The machines can cover most of thebers are yearly subscribed (including renewal and new

research steps in nanotechnology, which are cleaning, film

subscription).

deposition, lithography, etching, packaging and charac-

Operation principle is also “own help, public help,

terization. Not all apparatuses are yet installed in Takeda

and mutual help”. Budgetwise, each term of the principle

Building, however due to nationwide platform network,

corresponds to: (1) User’s payment to participate budget

researchers can access in another equivalent nanofabrica-

acquisition (charged according to the officially-approvedtion platform center(s).

d.lab’s internal rule), and (2) national budget allocated tod.lab platform research division, MEXT Nanotechnology

2.4.2

18

“Takeda Sentanchi Supercleanroom” coop-

Platform project, and (3) major laboratories (who rent

eration platform

space in Takeda Building for their research work) as well as

The platform is called “Advanced Research Infrastructure

research projects with d.lab operation laboratories (such as

on Materials (ARIM) UTokyo Nanofabrication site”

Mita Lab). Of course, each budget category is righteously

according to the MEXT’s national project, or simply

dispensed in perfectly following its own rule defined by“Takeda Sentanchi Cleanroom” (in short, Takeda CR).

corresponding laws and ordinances. The yearly opera-

The platform is widely open to those who share the “value

tion cost of 350 million yens are composed of equipmentof cooperation”. The most important understanding for

installation, electricity and water fees, maintenance, andevery user is the platform must not be considered as apersonnel. Recently electricity cost is drastically increas-

simple outsourcing agent; being understood the value ofing. National Universities have acquired budget flexibility“own help, mutual help, and public help”, the participant

since the date of private agency statuses. It helps a lot toensure staff employment as well as small to middle sized
equipment acquisition.

2.4.3

Activity Report 2023 of Platform Device
Research Division

Platform Device Research Division staffs acquire implicit【KPI】In FY2023, we had 195 active research groups,

information for future fabrication technologies, due tocomposed by company:external:UTokyo external:UTo-daily help to massively parallel research projects. The team

kyo Eng.dept = 1:1:1:1, with 1128 subscribers.

develops technologies with high demand and universality
and make them accessible by publishing papers.

For 43 top-used machines, 47% of usage rate (4422 daysfor 9404 available machine days) and 67.6% of external use
rate (2990 days for 4422 used days) have been obtained.

sion of d.lab, the team has been developed for over 10

This record highly oversatisfy the requirement of National

year, a reliable research scheme for integration of LSI and

ARIM project (30% external use), underlining that our site

MEMS devices, known as “Integrated MEMS researchis “one of the most democratic open platforms in the world”.

【Anniversary】”20th anniversary of Takeda Building”

through VDEC function of d.lab “LSI foundry”, a specific

was held on 20th December 2023 [3](Fig.3). Celebration

LSI circuit silicon wafers are fabricated through company

speeches included Professor Teruo Fujii (president of(such as Phenitec Semiconductor). Then the wafer is

UTokyo), Professor Yasuhiro Kato (dean of faculty of“post”-processed in an open nanofabrication platform

engineering), MEXT, METI, and Advantest Corporation.

including Takeda Sentanchi Supercleanroom. The critical

Resent activities were reported from platform design

advantage of such scheme is that researchers can “easily”

research division, advantest D2T endowment division,

obtain silicon wafers with transistor circuits, which has

and platform device research division, SONY semicon-

been really difficult for university cleanrooms to acquire

ductor solutions as a plenary talk, and two outstanding

reliability, and can fabricate by themselves specific MEMS

use award winners’ presentations (from Innovastella andthat no foundry company can provide. Namely, research-

Professor Tetsuo Kan of UEC). Participants celebrated

ers can produce “World’s first functionality” with “World’s

the anniversary with research poster session from partici-

highest quality”. Such a flexible scheme is unique in thepating laboratories, and the day was concluded by special

world. Yearly one multi-chip fabrication is performed

lecture from Professor emeritus Hiroshi Komiyama, pres-(pre-fixed participants upon request), including collabo-

ident of Mitsubishi Research Institute, “20 years with therative research works with industries.

country with advanced issues”[2] Y. Mita et al., Japanese Journal of Applied Physics, 56,
p. 06GA03, 2017 (2017) DOI: 10.7567/JJAP.56.06GA03

Fig.3

C

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

domain”. As summarized in a peer-reviewed journal [1],2-4
CCCCCCCCC

Moreover, taking full advantage that PDRD is a divi-[3] https://www.if.t.u-tokyo.ac.jp/~mita/TakedaAnniversary2023.pdf

 rofessor Hiroshi Komiyama (right) celebrating 20th anniversary with Professor Yoshio Mita (left), head of Platform Device ReP
search Division of d.lab.

19

2-4
CCCCCCCCCC

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC【High-level engineering exchange with worldwide

Infrastracture Symposium (ENRIS). Eight out of eight

Nanotech Platforms】Such cleanroom platform as anpresentations have been accepted, and the engineers as

open innovation base has been widely established, suchwell as professors of the team has been sent to C2N labo-

as National Nanotechnology Coordinated Infrastructure

ratory (Paris-Saclay). In total, 24 open facilities presented

in the USA, RTB-RENATECH operated by French

their cleanroom KPIs in terms of posters. Comparison

National Research Center (CNRS), Australian AIFF

was made in an efficient way (Fig.4). The benchmark-network. Our PDR division has especially close collabo-

ing has revealed that standard cleanroom size exceeds

ration relationship with RENATECH, and its European

1000 meter squares (UTokyo Takeda has only 600 meter

extension called EuroNanoLab, due to Pr Mita’s 25 years’squares), many cleanrooms have bigger amount of budg-

network. Two engineers (Hugues Granier and Davidets (UTokyo has got 8th place), but the number of users,

Bourrier) from LAAS laboratory that is one of the five

1100, is an outstanding number. As a post-conference“big” core facilities in France were invited to d.lab at

activity, the team has visited several research institutes suchthe end of FY2022. They worked for common interestas CNAM (Paris, France), IEMN (Lille, France), LAAS

in eletroplating. The engineering research knowledges(Toulouse, France), KU Leuven and IMEC (Belgium).

were then submitted to the European National Research

3000

Top: C2N-CNRS
2,900 m2

Cleanroom size [m2]2nd: CEITEC Czech
Tie: Uppsala Sweden
2,000 m2

2500
2000
1500

18th: UTokyo TakedaSCR
Tie: Lund University
600 m2

1000

Avg: 1017 m2

500
0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Users and its Portion
1200
1000
800
600
400

Avg: 215 users

200
0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SME

Fig.4

20

Big E

PublicSame Affil

Same Group

Unknown

Takeda SCR is categorized as “small” platform nowadays (top), however the number of users is remarkably big (bottom)

2.5

Activity Report of ADVANTEST D2T Research Department

2.5.1

Introduction of ADVANTEST D2T Research

testing is one of the most practical research topics in the

Department

industry. On the basis of these activities, our final goal is
to become a center of excellence of VLSI testing in Japan.

2.5.1.1 Aim of establishing ADVANTEST D2T Depart-D2T research division has spent a total of 15 years toment (former D2T research division)develop the first (Oct. 2007 – Sep. 2010), second (Oct.
2010 – Sep. 2013), third (Oct. 2013 – Sep. 2016), fourthin VDEC in October 2007. As the name suggests, it is(Oct. 2016 – Sep. 2019) and fifth (Oct. 2019 – Sep.

financially supported by ADVANTEST Corporation.

2022), phases. D2T activity report of 2022 presents the
1st financial year, i.e., Oct. 2022 – Sep. 2023, of the sixth

division was to promote the research and education envi-

phase. Systems Design Center, School of Engineering, theronment with regard to VLSI testing in all universities

University of Tokyo has been established in Oct. 2019,and colleges in Japan. “D2T” signifies that we consider

and Advantest D2T research department is within the

not only design but also testing. Through our activities,

center. D2T research department primarily focuses on

we hope to provide expertise in design and testing for the

D2T research activities and education. The sixth projectindustry. In addition, we are exchanging researchers withphase (Oct. 2022 onwards) of D2T project was com-those of other universities and research institutes both inmenced by courtesy of ADVANTEST Corporation. The

Japan and overseas. Moreover, D2T research division isdetails pertaining to the activities of our group are pre-suitable for collaborations with the industry because VLSI

sented in the following sections.

C

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The aim of establishing ADVANTEST D2T research

2-5
CCCCCCCCCADVANTEST D2T research division was established21

2.5.1.2 Members of ADVANTEST D2T Division
Project Professor

Makoto Ikeda

Postdoctoral research fellow Zolboo Byambadorj

2023, hybrid. This year, we will invite lecturers overseas,

Project Lecturer

Professor, Zhongrui Wang from Hong Kong University,

Akio Higo
Laboratories Ltd.)CCCCCCCCC
C

Report of the 17th D2T Symposium

The 18th D2T Symposium was held on September 8,

Researcher	Koji Asami (Advantest

2-5

2.5.2

Researcher	 M a s a h i r o

Reika Ichihara from Institute of Memory Technology
R&D, Kioxia Corporation, Associate Professor Shintaro

IshidaHisatake from Gifu University, Takahiro Nakamura,(Advantest Corporation)

Ph.D. from AIO Core Co., Ltd., Dr. Motoaki Hara,

Researcher

Takahiro Yamaguchi

Senior researcher from National Institute of Information

Assistant Clerk

Makiko Okazaki

and Communications Technology（NICT）, Lecturer

Atsutake Kosuge from Systems Design Lab. the University

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

of Tokyo, for their distinguished research topics.
We sincerely appreciate each participant for their contributions to the symposium. We look forward to greater
participation again at the 19th D2T symposium on Sep.
6 Fri. 2024.

18th D2T Symposium Program ONLINE

September 8, 2023

10:00 Opening Remarks

Tadahiro Kuroda (Director, d.lab, School of Engineering, the University of Tokyo)
Yoshiaki Yoshida (President & CEO, ADVANTEST CORPORATION)
10:15 Session 1 (Chairperson: Makoto Ikeda, d.lab, the University of Tokyo)
Classical Cryo-CMOS Systems for Quantum Computing: from a Wild Idea to Working Silicon
Edoardo Charbon, Professor (EPFL)
Digital neuromorphic computing systems featuring dendrite-spines in human cerebrum
Atsutake Kosuge, Lecturer (d.lab, University of Tokyo)
11:45 Free coffee and Tea break (KESCO supported)
14:00 Session 2 (Chairperson: Tetsuya Iizuka, d.lab, the University of Tokyo)

Boosting defect coverage for analog/mixed-signal ICs: machine learning to the rescue
Georges Gielen, Professor (KU Leuven)
Algorithm-Centric Design of Reliable and Efficient Deep Learning Processing Systems
15:30 Alex Orailoglu, Professor (University of California, San Diego)
15:45 15min break
Session 3 (Chairperson: Masahiro Fujita, the University of Tokyo)
Understanding Circuit Timing Marginalities that Cause Silent Data Corruption Ratio based Resistive Memory Cells for Low Error
Rate and High Energy Efficiency
Adit Singh, Professor Auburn University"Design, Architecture and Integration of Next-Generation Edge AI Chips: Challenges and Opportunities"
K.-T. Tim Cheng, Professor U-Tokyo Fellow (Hong Kong University of Science and Technology)
Session 4
Recent D2T research department progress
Akio Higo, Lecturer (d.lab, the University of Tokyo)
17:30 Closing Remarks
Makoto Ikeda (d.lab, School of Engineering, the University of Tokyo)

22

2.5.3

Research Activity Reports of the ADVANT-

High-Speed and High-Accuracy Multi-Pin Signal

EST D2T Research Department

Integrity CAL for ATE
Kazuki Shirahata, Masahiro Ishida, Tetsuya Iizuka,

High-Resolution

Analog-to-Digital

Converter

Based on Stochastic Comparators

Akio Higo, Toru Nakura, Makoto Ikeda
Automatic test equipment (ATE) for Semiconductors

Makoto Ikeda

output channels. It requires signal integrity calibration

This project aimed to explore new stochastic(CAL) to correspond the test signal outputs to the device

analog-to-digital converter (ADC) architectures. To

under the test (DUT). This research focuses on a high-reduce randomness and increase accuracy, an approach

speed and high-accuracy multi-pin signal integrity CAL

for robustly detecting level-crossing time via stochas-method applicable to ATE. This year, we decided researchtic median is investigated. A new theory for detecting

objectives and began investigating the signal integrity

LC-time using N “Comparator with ZERO Process

CAL method. First, we conduct a preliminary survey for

Variability” was developed and verified by Monte Carlosignal integrity CAL, and decided the research target toexperiments. It was shown, unlike a single comparator

establish the theory of the signal integrity CAL which(CP), this approach uses N ideal CPs in order to detect

includes transmission line characteristics estimation using

LC events of an input waveform, it has the accuracy limi-

time domain reflectometry (TDR) measurement andtation in detecting LC times.

waveform estimation at CAL point with the estimatedtransmission characteristics. Then we began considering

5G multi-channel/millimeter-wave signal meas-

the basic concept of the signal integrity CAL with TDR

urement

measurement, and showed that it is possible to calculate

Koji Asami, Zolboo Byambadorj, Ryogo Koike,transmission characteristics and signal waveform at a CAL

Sheng Guo, Nguyen Ngoc Mai-Khanh, Akio Higo,point from TDR waveforms for a known transmission

Tetsuya Iizuka, Masahiro Fujita, Takashi Matsumoto,line model by using circuit simulations and numerical

Makoto Ikeda

operations.

2-5

C

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

has thousands to tens of thousands of signal input and

CCCCCCCCC

Takahiro J. Yamaguchi, Akio Higo, Tetsuya Iizuka,

We study and develop fundamental research to measure the millimeter-wave signals in an over-the-air (OTA)

Development of Security-aware Test-driven Semi-

environment. A 4-channel planar antenna array has been

conductor Design

developed for the near-field measurements of the millim-

Genichi Tanaka, Kaoru Masada Kotaro Hasegawa,eter-wave antenna. Metasurface was fabricated to reduce

Manabu Kimura, Akio Higo, Makoto Ikeda

the coupling between antennas. Antenna probes were

We have studied the feasibility of a cryptographic

fabricated, and experiments are underway to confirm thearchitecture to ensure and guarantee the authenticity

characteristics and measure the antennas. In addition,and security of semiconductors in the semiconductor

to confirm the measurement algorithm, a commerciallytest process. The physical layout of the core circuit of theavailable horn antenna was used as a probe to measurearchitecture was designed and its feasibility is verified.

antennas for 5G. We confirmed that the far field can be
estimated accurately by correcting the influence of theprobe from the measured near field.

23

Chapter 3

Research in d.lab

Kuroda and Kosuge Lab(http://www.kuroda.t.u-tokyo.ac.jp/en/index.html)(https://klab.t.u-tokyo.ac.jp/en/research_theme/)

3
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C

TCI: ThruChip Interface

use wired-logic architecture to dramatically reduce power
consumption by minimizing access to memory including
DRAM and SRAM. However, area efficiency is a bottleneck since it requires the implementation of a large numberof elements on a chip. Therefore, we are developing three

T. Kuroda, M. Hamada, A. Kosuge, T. Shidei,

technologies to boost area efficiency: (1) a technology to

M. Okada, Wai-Yeung Yip, Y. Mitarai

optimize neural networks by removing unnecessary neu-

TCI is a 3D integration technology that employsrons and synapses, which is similar to pruning of theinductive coupling between coils created with on-chiphuman brain, (2) nonlinear neural network technology

metal line patterns for data communication across stacked

that incorporates the property of human neurons of using achips. It realizes the same or better performance as TSV

wide variety of nonlinear functions individually optimized(through-silicon via) but at a lower cost. This year, we pre-for each neuron to increase the representation capability ofsented research papers on TCI-based 3D SRAM stacking

the network in order to enable more drastic pruning thantechnologies and performed related research on archi-

ever before, so as to reduce the number of elements, andtecture and AI processing algorithms, as well as jointly(3) a convolutional wired-logic architecture that reuses cir-designed with RaaS an SRAM test chip for TCI-based 3D

cuits in processing of convolutional algorithms. This year,

integration. In addition, we developed design and verifi-

we studied the fundamental technology for classification

cation methodologies for TCI-based 3D integration. Ourof 10 general objects using the CIFAR-10 dataset, devel-

research results were published in international academic

oped the training algorithm, proved the concept throughjournals such as JSSC.

FPGA implementation, and published the results in IEEE
Micro, an international academic journal. In addition, we

TLC: Transmission Line Coupler

developed circuit technology to improve area efficiency

T. Kuroda, M. Hamada, A. Kosuge, Y. Hayashi

and an ASIC to confirm a 2048x power saving in voice

TLC is a data communication technique between

commands recognition compared to conventional GPUs,

circuit boards which utilizes electromagnetic coupling

and presented the results at VLSI Symposium 2023 andbetween transmission lines. It solves issues in conven-

SSCL. Our research earned high regards, mentions in news

tional connectors such as wear and tear, reliability against

releases, and recognition by JST as outstanding research.

vibration, and impedance mismatch and realizes low-cost,high-performance wireless connectors. This year, throughjoint research with a company, we conducted research anddevelopment of compact and high-density TLC mounting technology for connecting package substrates and

Takeuchi Laboratory(https://co-design.t.u-tokyo.ac.jp/)

Computation in memory (CiM)

PCBs, as well as fully sealed, non-contact connector tech-

Ken Takeuchi and Chihiro Matsui

nology for simultaneous wireless power delivery and TLC

We have developed a comprehensive Computation-communication by placing the couplers coaxially and in

in-Memory (CiM) simulation platform. The simulation

close proximity to each other.

platform has capability to emulate multi-level cell (MLC)and various memory device non-idealities such as uni-

Ultra Low Power AI Processor

24form/non-uniform conductance variation and shift. The

T. Kuroda, M. Hamada, A. Kosuge, R. Sumikawa,

simulation results address that the conductance shift has

K. Kobayashi

much more critical impact than conductance variation on

We are studying non-von Neumann AI processors thatinference accuracy in CiM.

Simulated Annealing

requests from SDN controller to SDN switch during

Ken Takeuchi, Chihiro Matsui and Naoko Misawa

communication, and from flow rules set in the SDN

Memory error tolerant ReRAM-based Computation-

switch.

in-Memory (CiM) to solve the knapsack problem, one
Coarse-Grain Reconfigurable Architecture

Proposed log-encoding simulated annealing (SA) on

Takuya Kojima, Hiroshi Nakamura

ReRAM CiM reduces the array area of ReRAM CiM by

Coarse-grained reconfigurable architectures (CGRAs)

97.6%. To co-design ReRAM device and SA, error injec-

are expected as a promising architecture for wide variety

tion is applied. As a result, the asymmetric ReRAM errorof computing including embedded systems and high-per-increases the acceptable bit-error rate (BER) by 10 times

formance computing due to its benefit of high-energy

and the acceptable bit precision to 5-bit.

efficiency and programmability. CGRA consists of anarray of numerous processing element and its efficiency

In-sensor Computing
Ken Takeuchi and Chihiro Matsui

heavily depends on the quality of compiler which maps

3
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of the combinatorial optimization problems, is proposed.

Capplications onto these PEs.

We have proposes an integration of event-based vision

To overcome this difficulty, we developed a mapping

sensor (EVS) and processor (e.g., computation-in-mem-

method dedicated to Elastic CGRA in which PEs exchangeory, CiM) for low-power processing. By using newly

data asynchronously using a handshake protocol. Duedefined characterization method of frame and EVS

to the asynchronous communication, complexity of thecamera, an event-driven SRAM CiM with partitioned

mapping problem is expected to be reduced.

word-line (WL) activation method is proposed for

We developed a new mapping method for Elastic

3D-integration of EVS. The multiple-bit synaptic weights

CGRA using ILP (Integer Linear Programming) and con-are stored in a set of SRAMs. The proposed CiM for EVS

firmed that mapping time is drastically reduced.

-6

achieves 10 times energy efficiency compared with CiM
for frame camera.

Lightweight Runtime Environment of ROS2 nodes
for Embedded Devices

Nakamura Laboratory(http://www.hal.ipc.i.u-tokyo.ac.jp/)

Hideki Takase, Hiroshi Nakamura
The Robot Operating System (ROS) and ROS2, thelatest version of ROS, have attracted attention as a design

IoT Network Security

platform for distributed robot software development.

Hiroshi Nakmaura

One of the drawbacks of ROS2 is that it is necessary

We considered a method for detecting scanning behav-

to employ high-performance and power-hunger devices

ior executed at the early stage of ransomware attacks

since it requires a Linux environment for operation. Thistargeting networks connected by IoT devices throughdrawback prevents ROS2 from being applied to embed-

SDN (Software Defined Network). SDN (Softwareded devices because they must be quick in response andDefined Networking) is an approach to network manage-

consumes less power. Thus, we have proposed a novel

ment where the control of packet forwarding and routing

solution called mROS2, which is a lightweight runtime

is separated into SDN controllers and SDN switches. One

environment of ROS2 nodes. One of the advantages ofadvantage is the ability to flexibly modify settings using

mROS2 is that it provides efficient communication mech-software. By making use of this advantage, we created aanisms with less memory consumption. Currently, we aredetection model based on machine learning that utilizes

designing software architecture for this communication

lightweight features derived from statistical information

flow. This work is expected to contribute to the power25

saving and real-time performance enhancement of mobile

researching implementations aimed at hardware integra-

robot systems.

tion with CRYSTALS-Dilithium, and have successfully
developed a number theoretic transform hardware that3
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C

Ikeda Laboratory(http://www.mos.t.u-tokyo.ac.jp)

can be used in both systems.
In addition to the accelerator used alongside
CRYSTALS-Kyber, standalone hardware targeting

Design of Functional Encryption Accelerator and

CRYSTALS-Dilithium for high resource compression andits automated design techniques

low clock consumption is also in progress. With a focus

M. Ikeda, A. Opasatian, K. Masada, M. Fukuda,

on extensive resource reuse and maximizing segmented

and Y. Suzuki

pipelining design, the achievement is poised to reduce

When implementing complex algorithms such as pair-clock requirements by over 30% compared to existinging operations, dedicated hardware development using

solutions, while maintaining nearly unchanged or even

ASICs and FPGAs is expected to achieve lower power

better resource consumption and maximum frequency

consumption and latency by taking advantage of paral-

conditions.

lelism, compared to software implementation on CPUs.

For SPHINCS+, we aimed to achieve low latency by

On the other hand, it takes a huge human and time cost

designing it with multiple hash processors for efficient

to explore suitable architecture and optimize parallel

computation. We demonstrated that, even in its min-processing in consideration of data dependencies. We

imal configuration, the deployed strategy can performhave therefore reduced the design time by automating theoperations faster than other ASIC implementations while

scheduling creation process. The higher-level synthesis

maintaining an equivalent area. By adjusting the number

methods by Python using libraries such as NumPy is alsoof cores, we achieved a further reduction in the area-delay

investigated to realize more flexible designs.

product.
In our research on SIKE, we have reconsidered the

Implementation of Post-Quantum Cryptography

computational paths of cryptographic computations with

M. Ikeda, Y. Takeshima, P. Sun, K. Nakamura,the goal of designing dedicated hardware. We designed aand Y. Nakamura

general-purpose hardware capable of executing all compu-

With the advent of practical quantum computing,tation paths. Within that hardware, we sought the optimal

there is a threat that classical cryptographic methods, suchcomputation path from the perspective of the area-delay

as RSA and elliptic curve cryptography, will be compro-

product. We have successfully found an optimal path that

mised. In response, researchers have developed several

differs from the one specified in the SIKE specification,

Post-Quantum Cryptography (PQC) algorithms, which

achieving a speedup of 3.5 times compared to the fastest

are resistant to quantum computing. Our team is working

hardware implementation in prior research.

on the acceleration through dedicated hardware for key
encapsulation mechanisms such as CRYSTALS-Kyber

26

Neural network and Its security

and SIKE, as well as digital signatures like CRYSTALS-

M. Ikeda, Z. Wang, Y. Miao, and B. Amartuvshin

Dilithium and SPHINCS+.

Spiking neural networks (SNNs), due to their potential

For CRYSTALS-Kyber, we have designed hardware

energy efficiency, are promising candidates for next-gen-capable of supporting multiple security levels througheration neural networks and are also expected to be able

pipelining and parallelization. This design has provento integrate with neuromorphic sensors for efficient

to be superior in terms of the area-delay product when

information processing. However, currently hardware

compared to existing hardware. Furthermore, we are

implementations of SNN face significant difficulties

mainly due to the additional membrane potentials intro-

Security Measures of Crypto-engine
M. Ikeda, S. Kikuoka, K. Masada, and Q. Wang

compression method for membrane potentials, which

It is important to start working on practical use now forallows, for the first time, the use of a reduced-precision

cryptography that is expected to be utilized in the future,

fixed-point format representation for membrane poten-

such as pairing-based cryptography with high scalability

tials in deep SNNs, thus achieving the lowest resource

to advanced functional cryptography and lattice-based

footprint and energy consumption of any FPGA-based

cryptography with resistance to attacks by quantum com-

SNN accelerators.

puters. We suggested method to estimate the security

On the other hand, the techniques of cloud computing

and hardware costs such as area and latency of hardware

have been used to overcome the huge computing cost of

implementation, that can calculate pairing operations

deep neural networks on personal computers, while itor lattice operations and that is implemented in ASIC,

suffers from the concern of data privacy. Homomorphic

based on logic synthesis results. And then the results wereencryption (HE), which enables encrypted computations,evaluated for optimal ate pairing and CRYSTALS-Kyber.

is a promising solution. However, the computation on

Also BLS signature has provable security which is cur-ciphertexts is typically slower than that on plaintexts

rently desirable. We estimated the computation cost of

by 1000-10000 times. In our research, fast computing

BLS signature on a curve chosen based on the tightness

schemes and customized hardware are designed to acceler-of reduction. Also, we compared the parameter sizes of

ate the HE computations. On computing scheme design,different signatures.

3
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duced by spiking neuron. To this end, we propose a losslessC

we propose a guideline of building bootstrapping-free
Gated Recurrent Unit (GRU) networks, by which fast

Research on Logic Locking

inference is achieved while the accuracy is almost pre-M. Ikeda, Z. Ye, J. Xin, T. Matsumoto

served. On hardware design, a ciphertext multiplier,

Logic locking is a technology that protects the intel-

including key switching, modular switching and NTT/

lectual property and security of integrated circuits by

INTT blocks, is designed to accelerate ciphertext multi-

incorporating specific logic gates into circuit designs. We

plication, which costs most computing time of HE-based

have applied post-quantum crypto-algorithm for the logic

NN inference on CPU.

locking to realize robust logic lock system resistant toquantum computing.

Implementation of secret sharing

The implementation of post-quantum crypto-algo-

M. Ikeda, and Y. Zhao

rithm(PQC) is becoming indispensable for cryptography

Secure multi-party computation (MPC) is a cryp-in IoT devices. In this study, we have investigated thetographic protocol enabling multiple parties to jointly

implementation of Crystals-Kyber accelerator, one of thecompute a function over their inputs while keeping

PQCs, in RISC-V, an open-source processor, aiming tothose inputs private. Compared with other approaches,guarantee the security of future IoT devices.

computing time of Secret Sharing Technique is fasterthan others, but its computing is sensitive to the network
latency and its communication round is increasing withthe computation depth. We have evaluated in systems likeclose-memory computation and on-chip secret-sharing
computation where communication resources is almost
unlimited.

27

Iizuka Laboratory(http://www.mos.t.u-tokyo.ac.jp/iizuka)

3
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C

modulators (DDSMs) within fractional-N frequency synthesizers. To solve the problem of spurs with low input

Phase-Locked Loop Circuit Techniques for Low

bit widths in conventional self-dithered MASH 1-1-1

Phase Noise

DDSMs employing shaped dithering, we introduce to use

Tetsuya Iizuka, Masaru Osada, Haoming Zhang,self-dithering in a MASH 1-1-1-1 structure. The novel

Yuyang Zhu

self-dithered MASH 1-1-1-1 structure suppresses frac-

Ring VCO is a good candidate as the oscillator in a PLL

tional spurs effectively, even with low input bits, and does

because it has smaller area, less coupling, and multiple

not require an external LFSR. This approach also offers

phases. However, its Phase Noise (PN) performance isan additional order of noise shaping, enhancing the PLL’s

generally much worse than the LC VCO, and requires thephase noise and spur performance.

PLL to have the very wide bandwidth (BW) to high-passfilter its noise. This contradicts with the necessity of theHigh-Speed and High-Precision Data Conversion

narrow BW required in the fractional PLL, because theCircuits and Design Automation Techniques

quantization noise is low-pass-filtered by the PLL. The

Tetsuya Iizuka, Shuowei Li, Ximing Wang,

Harmonic-Mixer (HM) -Based fractional-N PLL is good

Haoming Zhang, Yo Kumano, Ritaro Takenaka,candidate to use Ring VCO, because can achieve effective

Yunjie Chen, Yuhao Xu

quantization noise suppression without using calibration,

Standard cell-based analog circuits have many advan-

releasing the BW requirement to filter the quantization

tages, including high reusability, high integration,

noise. Nonetheless, the DSM operating frequency is low

compatibility with automated design, reliability, andin a common dual-feedback HM-PLL so that the quanti-

stability, making them highly promising for current

zation noise is still dominant when the main PLL BW isand future research. We have designed a new standard

high. Thus, in this research, we added a nested PLL aftercell-based synthesizable SAR ADC that employs a new

the fractional divider to raise the DSM operating fre-differential architecture. This architecture eliminates thequency and further filter the quantization noise. The chipneed for pre-biasing the DAC for each bit estimation,

has been successfully fabricated and the measurement

thereby reducing the CDAC power consumption. The

results has proven the effectiveness of our idea.

control logic has been simplified, which also reduces the

Although HM-PLL is effective for quantization noise

power consumption of the logic cells. Additionally, wesuppression, the downside of this architecture is that at

have introduced a new inverter-based switch whose per-least one extra PLL is required, potentially resulting informance matches that of CMOS switches with dummies.

noise and power overhead that leads to a degradation inThis new structure helps to suppress the nonlinear effects

terms of jitter-power performance. Our second work is toof the switches. The reference voltage converges to the

propose a feed-forward noise cancellation technique thatgeneral power supply with less significant bit estimation,

can be used inside the HM-based PLL to mitigate thereducing the performance requirements of the compara-noise and power overhead from the first-stage PLL andtor. The Walden Figure of Merit (FoMw) of this design

overcome its performance limitation. The proposed tech-

can achieve one-eighth of that of the previous design.

nique can also potentially be used in other cascaded PLLThis design is being experimented with using digitalarchitectures to reduce the overhead from having multiple

synthesis tools to generate the layout. Furthermore, we

PLLs. The chip has been designed successfully, and thehave introduced a standard cell-based amplifier that canmeasurement result has proven our proposal.

achieve a gain of over x60 while maintaining acceptable

We also focused on the enhancement of self-dithered

28

MASH (multi-stage noise shaping) digital delta-sigma

linearity. Based on this amplifier, we have also introduced

a synthesizable pipelined SAR ADC.
Dynamic circuit belongs to the digital circuit families

relationship between quantizer nonlinearity and integrator output amplitude.
High-speed and high-accuracy ADCs are required

unlike static CMOS digital circuit with both pull-up

in many applications such as wireless transceivers andand pull-down network, dynamic circuit is asymmetricradars. We focused on a high-resolution subranging ADC.

because it gets rid of one of the pull up/down network,

Compared with previous pipelined ADCs, this archi-

replacing it with a single transistor for faster speed. In

tecture is suitable for deeply scaled CMOS technology.

spite of the improved speed, the extra clock signal to

We proposed a reverse biased amplifier, which has thecontrol its operation phases (pre-charge and evaluation)

small non-linear input capacitance, and a power-effi-

has introduced huge difficulty in this timing character-

cient multiple-reference comparator. We also proposed a

ization. Thus, the dynamic circuit has never included

split-reference C-DAC, which reduces the on-chip decou-

into the automatic digital circuit design flow as the staticpling capacitors without an additional regulator. These

CMOS circuit up to now. To counter this trend, in thisideas are implemented in a 14bit, 500MS/s ADC. The

research we are aiming to provide a timing model for themeasurement results show the proposed ADC achieved

timing characterization of dynamic circuit, and a on-chip

the Schreier DR FoM of 179.4dB.

test structure to extract the timing parameters including

The standards of communication technology havedelays and setup/hold time after fabrication. The pro-evolved from 4G to 5G, and now research is being

posed timing model has been utilized and verified based

conducted towards the next generation, 6G. The new

on Synopsys Prime Time, a mature EDA used in modern

communication standards aim to feature ultra-wideband

industry. The chip of the test structure has been designed

capabilities, support a wider range of frequency bands,

with TSMC 65nm process and successfully fabricated.

and significantly improve data transfer speeds. As one of

The measurement results have well-proven our proposal.

the technologies enabling ultra-fast data communication,

For high-precision and high-power efficiency ADC

the research and development of ultra-high-speed digi-

design, we continued our research on fully dynamic

tal-to-analog converters (DACs) is urgently needed. Due

discrete-time Δ∑ ADC using the Floating Inverterto the internal parasitics and component characteristics

Amplifier (FIA) this year. Based on previous researchof a single DAC, further enhancing its performance isabout gain boost through CLS and noise cancellationdifficult. In recent years, interleaving techniques have

via SNC, we proposed a novel technique called Fast Self-

been frequently ultilized into DACs. Especially Time-

Quenching FIA reusing CRES for SNC to enhance theinterleaved DAC (TI-DAC). Previous work on TI-DAC

power efficiency of the integrator. We designed the cir-has uncovered some potential design issues in 4 channel

cuit and fabricated a chip for a second-order 5-level fullycase like aligining the phase error between different fre-dynamic discrete-time Δ∑ ADC, evaluating its perfor-

quency clock and extremely samll output scale. In thismance through practical measurements. Additionally, we

year’s work, we have proposed a 20 GHz time-interleaved

applied random dithering to the quantizer and analyzed

DAC which effectively addresses key issues in existing

the quantizer characteristics of the Δ∑ ADC based on

design, while maintaining the sampling rate and achiev-

the quantizer input histogram. Numerical analysis con-ing a comparable SFDR. The proposed TI-DAC features

firmed the correctness of the analytical approach, anda single-stage MUX and direct summation at the final

approximate analysis demonstrated reproducibility of key

output. It can sustain a SFDR of 63dB up to 65% ofelements. Furthermore, we highlighted an example of

the Nyquist frequency in ideal case while in contrast, theoptimal design points to minimize quantizer nonlinear-

existing TI-DAC can reach Nyquist frequency but suffers

ity in the second-order Δ∑ ADC, revealing a trade-off

a 8dB reduction in SFDR due to output power losses.

3
CCCCCCCCC CCCCCCCCCCCCCCCCC

which are used to realize digital logic function. However,

C

29

3
CCCCCCCCC CCCCCCCCCCCCCCCCC
C

This proposed structure replaces the second stage MUXcomponents is extremely challenging and poses significant

by directly adding outputs from two MUX TI-DACs

barriers for long-duration deep space missions. To address

together. This modification simplifies the clock design

this issue, it has been proposed to integrate the trans-significantly, reducing complexity while maintaining themitter, receiver, and digital signal processing units into aaccuracy of the system.

single chip. This approach not only reduces the overall size

We examined methods to avoid the speed performanceof the circuitry but also decreases the number of compo-

bottleneck caused by internal logic circuits in Successive

nents, thereby potentially enhancing the reliability of theApproximation Register (SAR) Analog-to-Digital

entire module.

Converters (ADCs) and optimize their performance by

In this study, X-band (7.2 GHz / 8.4 GHz) receiver andimproving sampling speed. Traditionally, logic circuits

transmitter circuit chips were designed and evaluated inhave been designed using static logic circuits, which areorder to realize the one-chip communication system for

simple to operate and easy to assemble. However, thisdeep space probes.

simplicity can cause the logic circuits to become a bot-A receiver front-end including a low noise amplifier andtleneck for the entire ADC. On the other hand, dynamic

down-conversion mixers was designed. A noise-cancelling

logic circuits offer faster speeds but are more complex totechnique for ultra-high sensitivity was demonstrated

operate, making logic synthesis difficult and requiringby simulations based on IHP SiGe 130 nm BiCMOS

time-consuming manual design In this study, we opti-

process. Besides, a prototype receiver front-end chip was

mized the speed and power consumption performance

fabricated using TSMC 65 nm CMOS process. Resultsof digital control circuits designed with static logic cir-of direct-probing measurements showed the noise figure

cuits by detecting critical paths in dynamic logic circuitsof 2.3dB and demonstrated that our CMOS receiverand replacing the circuits within these paths with fasterchip achieves comparable sensitivity to that of receivers

dynamic logic circuits. Using a 10-bit SAR ADC designed

mounted on past deep space proves. Moreover, the meas-

with a 28nm CMOS process as an example, we analyzed

ured input 3rd-order intercept point of −26 dBm proved

two designs using static logic circuits and demonstrated

that the receiver dynamic range of our chip is acceptableperformance improvements by replacing some of thefor operations in deep space explorations.

circuits with dynamic logic circuits. Furthermore, we

The overall structure of the X-band receiver was alsoorganized and verified the necessary conditions and work-

studied and analyzed. Since deep space probes move atflows for replacing static logic circuits with dynamic logic

high speeds, the frequency of the received signal is devi-

circuits to prepare for future automation of this replace-ated due to the Doppler effect. To compensate for this, wement process.

proposed an analog carrier tracking loop, which is suitable
for the CMOS one-chip implementation. The proposed

30

Design of Low-Noise Transceiver for Deep-Spacearchitecture was designed and analyzed in phase domain

Probesbased on the measured front-end performance, and its

Tetsuya Iizuka, Sota Kano, Taku Hamazaki

superiority over conventional digital processing using an

The demand for miniaturization of deep space probes

FPGA was discussed.

is increasing, with a particular emphasis on the min-A transmitter front-end including a single-stage power

iaturization, lightweight design, and cost reduction of

amplifier and an up-conversion mixer was designed andcommunication modules. Recent ultra-small planetaryfabricated using the TSMC 65 nm CMOS process,exploration probes use commercial off-the-shelf (COTS)

the operating frequency of which is 8.45 GHz for thecomponents primarily to reduce costs. However, ensur-

satellite communications. Our simulations and actual

ing the reliability of systems that extensively use COTS

measurements demonstrated that the power amplifiercould achieve approximately twice the efficiency com-design of the LIF neuron consists of MOS capacitors

pared to previous research on wideband power amplifiers

to do the integration, triggering P/N transistors to do

by narrowing the operating frequency band.

accumulations in excitations/inhibitions, and a VoltageControlled Oscillator (VCO) to emit the output pulses.

space environment, integrated circuits will be susceptible

The LIF neuron designs were tested in different sim-

to single event effects (SEE) and total ionizing dose effects

ulation environments (SPICE, Matlab, Python) of the(TID). Consequently, an evaluation printed-circuit-board

neuron and the network to verify the capability of learning

for the future irradiation test was designed.

of the circuit. This circuit was designed in a commercial
65nm CMOS technology from TSMC. The simulation

Design of Time-Domain Neuron Devices and Eval-

tests the capability of learning according to different

uation of Learning Systems

models using Reservoir computing. The reservoir consists

Tetsuya Iizuka, Byambadorj Zolboo,of the LIF neurons connected randomly or in specificCkristian Duran, Nanako Kimura

configurations. Each of the neurons must be measured inWith growing trends of Artificial Intelligence (AI),real time. With the weighted sum of the neurons, different

advancements are necessary to fit recent updates. Lately,

kinds of learning can be possible. Currently, the simu-

implementations of Large Language Models (LLM) likelations support simple tasks like Short-Term Memory

ChatGPT demonstrate the capabilities of AI to solve(STM) and eXclusive-OR(XOR), or more complex learn-complex problems. Unfortunately, the implementation

ing like waves at a certain range of frequencies and voiceof such models requires specialized computation equip-

recognition.

ment with very strong capabilities. This implementation

To implement the SNN, LIF neurons must be inter-

limits the usability of such AI to connect to a centralized

connected together. This interconnection should support

server. These limitations create problems such as privacy

different kinds of computing paradigms including

concerns due to sending and receiving data to a third

Reservoir computing. We designed a Field-Programmableparty. This creates also a dependency on the internet due

Gate Array (FPGA) architecture to enable random con-

to incapabilities in personal devices. Moreover, the energy

nectivity between neurons. This FPGA is composed of

consumption of such computation is too high to be sus-

Complex Logic Blocks (CLB) that contain the LIF neu-

tainable in the future. An alternative needs to be foundrons. The FPGA implementation is possible because thesuch that it improves both computation power and energy

signals can travel digitally due to the nature of pulses of

efficiency.

the input/output of the LIF neuron. Any kind of SNN

Analog computing is a solution to the previously men-can be translated into a schematic and be converted into ationed problem. A simple implementation of adders andbitstream which contains the network. This FPGA system

multipliers can be achieved with low area and low power.

contains helper elements like frequency counters to pro-

The caveat of using analog computers is precision due tovide the measurement of the neurons. Each frequency ismismatches and noise. Fortunately, implementations of

extracted from the neurons and converted back into a

Neural Networks (NN) have demonstrated that they dovoltage by an external device.

not require fine precision. Our chosen implementation

A neural network chip is implemented this year in aof analog computing is Spiking Neural Networks (SNN)

65nm CMOS technology from TMSC. The chip contains

using Integrate-Leakage and Fire (LIF) neurons. A LIF

the FPGA with 100 LIF neurons. This chip demonstrated

neuron performs calculations by integrating a series of

the random connectivity of 100 possible neurons. The

pulses. The state of the neuron leakages over time, andchip spans an area of 2000x2000µm. When implemented,

also determines the fire of pulses to other neurons. The

the neurons consume a total of 21.7 pJ/pulse. Due to3
CCCCCCCCC CCCCCCCCCCCCCCCCC

Due to the presence of high-energy radiation in the

C

31

3
CCCCCCCCC CCCCCCCCCCCCCCCCC
C

32

resource limitations of the FPGA, this implementation

firing mechanism and realized a circuit that consumes lessimplements a maximum of 50 neurons as a reservoir.

power by performing firing without using a comparator

We demonstrated the learning capabilities of waves inand using the leakage to drive the VCO.

feedback configuration, and simple tests like STM/XOR.

The neuron circuit was created last year and a simu-

Deep neural networks (DNNs), the second generation

lation of SNN with reservoir computing method wasof artificial neural networks (ANNs), have been actively

conducted using this circuit. However, there were two

used in recent years. However, their huge power con-issues. First, the simulation using the neuron circuit cre-sumption has become a major problem, and a solution

ated last year assumed the use of an ADC to read theto this problem is being sought. One promising solution

control voltage of the VCO. In order not to lose theis the spiking neural network (SNN), which is called theadvantage of the system, it is desirable to realize SNN

third generation of ANN. The brain is known to have

without using an ADC, which is generally considered to

low power consumption of about 20W, and SNNs arehave high power consumption. Therefore, this fiscal year,

thought to be able to reduce power consumption becausea counter was used to read the frequency of the VCO. In

they process information more like the brain. SNNs are

addition, the task performed in that simulation was thecomposed of neurons that change their state over time

auto-generation of a sine wave. In general, in reservoir

according to neuronal mechanisms and transmit infor-

computing, the properties required of reservoirs are short-mation by firing. The characteristic feature of SNNs is

term memory, nonlinearity, and high dimensionality. Itthat the information is not carried in the value itself, as in

is difficult to analyze to which extent the fact that a sineconventional ANNs, but in the timing of firing.

wave can be generated attributes to which performance.

From the perspective of electronic circuits, time-do-

Therefore, this fiscal year the task that was more appro-

main circuit technology has an affinity for SNNs. With

priate to explore the characteristics of the network was

the scaled transistors, the time delay of signal transitions

performed.

is decreasing, and an increase in operating speed is occur-

Based on the above modifications, simulation envi-

ring. The sharpening of signal transitions allows analog

ronment for SNN circuits was created with Python. To

information to be transmitted more efficiently in the time

simulate the behavior as close as possible to that of ainterval and time direction of the signal. Furthermore,

real circuit, a behavioral model based on the results ofsince time-domain circuits are often composed of inverters

Hspice simulations was created, and it was used to create

and logic gates, they have the advantage of not consuming

the environment. To test the short-term memory capa-

DC power. This is consistent with our policy of low power

bility, discrete input data was put into the system andconsumption.

it was checked how many steps before the input data

To construct an SNN in an electronic circuit, it iscould be replayed. In addition, a temporal XOR task wasnecessary to create neuron circuits and connect them

performed to verify the non-linearity and high dimen-

together. There are many ways to realize neuron circuits.

sionality of the system. As a result, we confirmed that the

There is a model called Leaky Integrate and Fire (LIF)

system has short-term memory, nonlinearity, and highmodel which is simple and often used for engineering pur-dimensionality. As an application, we also performed aposes. Circuits that follow the LIF model use comparators

speech recognition task for the numerical values 0-9. As afor setting threshold, which leads to an increase in area

result, we obtained a high accuracy which was comparable

and power consumption. Also, power is consumed forto other previous studies.

reproducing leakage without being utilized for anything.

Compared to other physical reservoir computing stud-

Therefore, this research group created a neuron circuit

ies, the advantage of our system is the use of CMOS,

that employs a voltage-controlled oscillator (VCO) as thewhich is widely used today. In addition, the results showthat performance increases as the number of neurons used

Design of High-Sensitivity On-Chip Network Ana-in the SNN is increased. We can say this system, whichlyzer Circuits

can be easily integrated with current processes, is promis-

Tetsuya Iizuka, Yuyang Zhu, Zhenyu Cheng,

ing for improving accuracy.

Jiaao Yu

Antenna Measurement and Testing Techniques forelectron spin. By the spin wave, the transmission andWireless Communications

control of information can be realized without the phys-

Tetsuya Iizuka, Mai Khanh Nguyen Ngoc,

ical movement. However, until now, there is no on-chip

Byambadorj Zolboo

detection system to detect the response of the spin-wave,

In 5G technologies, over the air (OTA) measurements

making it possible to be applied in next generation chips.

are necessary for 5G antennas due to the technologies rely

Consequently, we proposed a spin-wave detection system.

on millimeter-wave frequencies and small-sized terminals.

This circuit comprises several key blocks: a phase locked

The conventional OTA measurement is based on far-loop (PLL), a phase interpolator (PI), a low-noise ampli-

field measurement. However, the far-field measurement isfier (LNA), a lock-in amplifier (LIA), and analog-to-digital

almost infeasible in the millimeter-wave due to high pathconverters (ADCs).

loss and low measurement accuracy. Therefore, near-field

Until now, we have successfully designed and fabri-measurement takes place of OTA measurement in thecated chips for the blocks used in the system. For the

millimeter-wave range. The far-field measurement datatransmitter side of the proposed spin-wave detection

can be achieved from near-field measurement by using

system, we started by designing a wide-band inductor-

near-field to far-field methods.

less PI. Then proceeded to validate the design throughIn the past, we have used different types of antennas assimulations, ensuring its functionality and performancea probe and antennas under test (AUT). It is well known

for the intended application in the spin-wave detectionthat the measurement time and the probe design are thecircuit. Based on the measurement results, the PI chip was

most important factors in near-field measurement.

implemented in 65nm CMOS technology. SubsequentThis fiscal year, we successfully designed a dual-feedmeasurements were conducted to assess the function andmulti-probe with a target frequency of 28GHz. The mul-performance of the fabricated chips. Measurement results

ti-probe is capable of receiving dual-polarization signals

show a phase range of 0° to 360°, with DNL and INL atin multiple positions simultaneously. Based on the meas-

0.6LSB and — 5.17LSB, respectively. Additionally, the PI

urement results, we have confirmed that the polarizationcore consumes 1.89mW at 5GHz.

ratio was more than 20 dB.

3
CCCCCCCCC CCCCCCCCCCCCCCCCC

Spin waves (SWs) are the collective excitation ofC

Then we focus on the enhancement of self-dithered

Using this multi-probe, the near-field measurement

MASH (multi-stage noise shaping) digital delta-sigma

time can be significantly reduced by taking multiple

modulators (DDSMs) within fractional-N frequency syn-samples in the scanning space. To capture these multiple

thesizers. To solve the problem of spurs with low input

signals, a new capturing system has been developed as the

bit widths in conventional self-dithered MASH 1-1-1

typical VNA has only several ports. As a proof-of-concept

DDSMs employing shaped dithering, we introduce to use

for the system and the multi-probe, we have successfully

self-dithering in a MASH 1-1-1-1 structure. The novel

captured several AUT and reconstructed comparably

self-dithered MASH 1-1-1-1 structure suppresses frac-good far-field characteristics.

tional spurs effectively, even with low input bits, and does
not require an external LFSR. This approach also offers
an additional order of noise shaping, enhancing the PLL’sphase noise and spur performance.

33

3
CCCCCCCCC CCCCCCCCCCCCCCCCC
C

For the receiver side, we designed an LNA with adiscrete frequency tuning. However, this circuit config-

chopper-stabilized LIA for weak signal detecting anduration involves trade-offs. For instance, increasing theamplifying. According to the measurement, the proposed

varactor size to widen the tuning range also increases

LNA has demonstrated a maximum gain exceeding 31

the resonator’s capacitance, leading to a lower oscilla-dB in experimental measurements. Furthermore, the pro-tion frequency. Additionally, switches used for frequency

posed LNA achieves reasonable power consumption ofswitching require larger sizes to reduce on-resistance, but

11mW, occupied area of 0.066mm^2 , −3 dB bandwidth

this increases parasitic capacitance between drain andof approximately 1.2 GHz and minimum NF of approx-

source. In the millimeter-wave band, capacitor Q-factor

imately 3 dB during testing. Turning to the LIA, Withdegradation is significant, affecting phase noise perfor-

the determination of the phase relationship established,

mance. Promising techniques include multi-core VCOs

we proceeded to measure the output-input characteristics

and switching operation without transistor switch, whichof I/Q paths across various chopper frequencies. The pro-

we are currently investigating.

posed LIA achieves SNR greater than 0 dB at the listed

On the other hand, designing circuits operating in

chopper frequencies, which is proved to be feasible for 56

the millimeter-wave band poses challenges related to thethe measurement of the spin-wave device.

reliability of device models. Besides the effects of parasitic

The next step of the work aims to measure the pro-elements, foundries often lack verification for millime-

posed blocks with the real spin-wave device, verifying theter-wave characteristics, resulting in discrepancies between

function and performance of the proposed system. And

simulations and actual behavior. Even if we design the

do more improvements based on the existing version oflayout of elements and do the electro-magnetic simula-

the system.

tion, obtaining accurate device characteristics remains
difficult. Therefore, creating device models before circuit

Millimeter-Wave Integrated Circuit Techniques
Tetsuya Iizuka, Taizo Yuasa

design is essential in the millimeter-wave band.
To create accurate device models usable in the milli-

A Phase-Locked Loop (PLL) is a circuit that receives

meter-wave band, measurement results are necessary. In

a reference signal, synchronizes its phase, and outputs aour research, we designed a chip using the TSMC 28nm

signal with multiplied frequency. PLLs have diverse appli-

CMOS process, incorporating basic elements for analog

cations, and in this research, we aim to apply them to RF

circuit design (transmission lines, transistors, resistors).

testers. RF testers need to handle various high-frequency

Additionally, we included a single-stage common-source

devices, so stringent requirements exist for operating fre-amplifier circuit to validate model accuracy. By measuring

quency and jitter. Specifically, our goals include a tuning

this chip and creating device models from the obtained

range of 50~100 GHz with low jitter. Different PLL

results, we enable more precise circuit design.

architectures, such as Fractional-N PLL and Cascaded
PLL, exist, and the optimal architecture depends on theoperating conditions. Therefore, we determine the bestarchitecture for our application based on simulations andproceed with circuit design.
To widen the tuning range of PLLs, we need to expand
the tuning range of a Voltage Controlled Oscillator

34

Hiramoto & Kobayashi Laboratory(https://vlsi.iis.u-tokyo.ac.jp/, https://nano-lsi.iis.u-tokyo.ac.jp/)

Low Temperature Characteristics of Nano-Scale
CMOS Devices(VCO) inside PLLs. Typically, LC-VCOs use varactors

Toshiro Hiramoto and Masaharu Kobayashi

for continuous frequency tuning and capacitors/induc-

The quantum computing has attractive much attention

tors which can be switched with a transistor switch forfor a future computing technology that is fundamentallyis attractive because it can be formed in BEOL layers at

the quantum computing systems, conventional CMOS

low process temperature. Sputtering has been used for flat

circuits are utilized to control quantum bits. Therefore, itpanel display device of oxide semiconductor, but cannot

is essential to clarify and model CMOS transistor charac-

be used for conformal deposition on 3D structure. In thisteristics at low temperature. In this study, we revealed theresearch, we developed Atomic Layer Deposition (ALD)

origin of the increase of the variability in MOS transistors

process for nanosheet oxide semiconductor, which is nec-

at low temperature. Currently, we are evaluating random

essary for scaling oxide semiconductor transistors. Then,telegraph noise at low temperature.

we clarified the trade-off relation ship among mobility,
threshold voltage and bias-stress instability for device

Stacked Silicon quantum bits

design. Furthermore, we introduced double-gate device

Toshiro Hiramoto and Masaharu Kobayashi

structure and realized high mobility, normally-off opera-

Semiconductor, particularly, silicon quantum bit istion and high reliability.

getting attention as a quantum bit for quantum computing. For practical quantum computing, more than

Research on energy-efficient fabrication process

ten-thousands of quantum bit should be integrated.

and reliability for HfO2-based ferroelectric devices

In this laboratory, to realize highly scalable integrated

Masaharu Kobayashi, Toshiro Hiramotosystem, we are studying 3D integration by stacked silicon

Crystallization anneal is one of the most important

qubit structure. Stacked silicon quantum bit structure isprocess to form ferroelectric phase in HfO2-based fer-

proposed by simulation. Currently, we are prototyping

roelectric material. In this research, we employed LED

the device for demonstrating the feasibility.

anneal process which has high selectivity regarding wave

3
CCCCCCCCC CCCCCCCCCCCCCCCCC

different from classical computing by CMOS circuits. In

Clength instead of conventional rapid thermal anneal using
Silicon Power Devices

halogen light source. Then, we realized highly energy-ef-

Toshiro Hiramoto

ficient fabrication process by the LED light source which

Semiconductor power devices are fundamental prod-

has the same wavelength for light emission as ferroelectricucts for power electronics used in consumer products,

capacitors for light absorbance.

electric cars, and railways. Although new materials such as

We also developed an in-situ and non-destructive eval-

SiC or GaN are widely studied for power devices, it is stilluation method of ferroelectric property and laser PEEM

possible to increase performance of silicon power devices.

spectrum of HfO2 ferroelectric capacitors by collaborating

In this study, we are demonstrating insulate gate bipolarwith The Institute for Solid State Physics, the University

transistor (IGBT) with scaling and dual gate structure forof Tokyo. By using this method, we clarified the spatial

high performance. In addition, to integrate power devices

and temporal relationship between electrical dielectric

into CMOS circuits, we are studying new lateral super-

breakdown and PEEM spectrum.

junction power MOSFET.
Research on atomic layer deposition of oxide semiconductor and its application for 3D integrated
memory devices.
Masaharu Kobayashi, Toshiro Hiramoto
While 2D scaling is getting challenging, 3D monolithic

Takagi Laboratory(https://sites.google.com/g.ecc.u-tokyo.ac.jp/mosfet/)

Ge Metal-Oxide-Semiconductor (MOS) FETs andthe 3-dimensional integration
Shinichi Takagi, Xueyang Han,

integration that requires active device formation in BEOL

Kasidit Toprasertpong, Mitsuru Takenaka

layers is getting more attentions. Oxide semiconductor

We are investigating the technology to realize ultra-thin35

3
CCCCCCCCC CCCCCCCCCCCCCCCCC
C

Ge-On-Insulator (GOI) structures on Si substrates, thepulses. Furthermore, the low-voltage disturb character-

performance improvement of high-performance GOI

istics of FeFET memory and their physical mechanisms

CMOS using these structures, and the device physics

were investigated. It was clarified that the long-term

that determines the electrical characteristics, with the aim

disturb characteristics cannot be represented simply byof applying them to 3D integrated CMOS. In this fiscal

integrating it over applied total pulse time. Here, twoyear, we have been studying the fabrication of a (111)mechanisms are involved: the electric field modulation

GOI substrate, which is expected to have high electron

effect by charge de-trapping and the relaxation of themobility due to suppressed surface roughness scattering,polarization itself. Furthermore, we found that an imprint

and the demonstration of n-channel MOSFETs on it. The

phenomenon observed in MFM capacitors for FeRAM(111) GOI channel with excellent crystalline and inter-

applications is caused by charge trapping/de-trapping inface qualities can be formed by thinning the GOI layerelectrode/HZO interface regions.

formed by the smart cut method and then transferring
it to another Si substrate. This GOI channel is further

Reservoir computing based on ferroelectric devices

thinned by a digital etching method, and the operation

Shinichi Takagi, Kasidit Toprasertpong, Eishin Nako,of a (111) GOI n-channel MOSFET with a thickness of

Rikuo Suzuki, Mingxia Wan, Mitsuru Takenaka,

down to about 2 nm has been demonstrated.

Ryosho Nakane
Reservoir computing has recently attracted atten-

HfO2-based Ferroelectric devices
Shinichi Takagi, Kasidit Toprasertpong,load for learning. We have proposed that FeFETs and

Zuocheng Cai, Seong-Kun Cho, Masaki Ootomo,

FeRAMs with memory-in-logic and nonlinear analog

Zhenhong Liu, Kosuke Ito, Mitsuru Takenaka

computation capabilities are promising hardware for the

MOSFETs using ferroelectrics (FeFETs) with polariza-

physical implementation of reservoir computing. Thus,tion reversal as gate dielectrics and FeRAM using metal

we are searching for methods to improve AI performance

sandwich structures (MFM structures) as memory cells areof reservoir computing based on ferroelectric devices

expected to be future devices for ultra-low power memory

by examining operating schemes and device character-and logic. In particular, devices based on ferroelectric andistics. In this fiscal year, we systematically investigatedanti-ferroelectric materials such as Hf1-xZrxO2 and ZrO2,

the device operation conditions that maximize reservoir

which have been discovered recently, are of great interest

performance, and showed that reservoir performance canbecause of their extremely high compatibility with current

be improved by choosing the center value of polarization

Si CMOS technology. We are studying the properties

switching as the center voltage of gate input and usingof these ferroelectric thin films deposited by an ALD

an optimal drain voltage of about 1 V. For application tomethod, the device operation principle of FeFETs, andspeech recognition, we have improved the performance ofthe optimum device structures to realize excellent device

the proposed reservoir computing system for the spoken

characteristics. In this fiscal year, we systematically inves-

digit classification task using parallel-operation FeFET

tigated the effect of HZO film thickness scaling on FeFET

reservoirs and have achieved a classification accuracy ofcharacteristics to realize FeFET memory with low-voltage

98.1% by increasing the number of combinations of dif-

operation and high reliability. We found that low-voltage

ferent frequency channels.

operation can be realized by HZO thinning and thatthe degradation mode of memory window changes withlowering the operating voltage, leading to the recovery
of memory window degradation by applying recovery

36tion as an AI computation method with computational

Understanding of Si CMOS operation under ul-

Si photonic integrated circuit for AI

tra-low temperatures for quantum computing ap-

Mitsuru Takenaka, Rui Tang, Yuto Miyatake,plication

Jooyoung Yoo, Mingzhi Huang, Tomohiro Akazawa,
Masahiro Fujita, Yosuke Wakita, Tomohiro Anda

Kasidit Toprasertpong, Mitsuru Takenaka

We are advancing research on deep learning for AI

In quantum computing systems, Si CMOS circuits thatusing programmable optical circuits such as universal

can operate at cryogenic temperatures such as 4 K must

optical circuits. By using a new phase-change material,

be placed close to the qubit chip to improve the number

GeSbTeS (GSTS), at a wavelength of 1.55 µm, we suc-of qubits. For this purpose, we are conducting experimen-

cessfully demonstrated an optical intensity modulator

tal and theoretical studies to quantitatively describe thewith low insertion loss. Furthermore, by applying theelectrical characteristics of MOS transistors at cryogenic

GSTS optical modulator to optical computing circuits,temperatures and to clarify their physical mechanisms. In

we showed that it is possible to perform calculations forthis fiscal year, we experimentally evaluated the change inconvolutional neural networks.

3
CCCCCCCCC CCCCCCCCCCCCCCCCC

Shinichi Takagi, Yutong Chen, Zhao Jin,C

SS (sub-threshold swing) values from room temperature
to 4 K for Si n-MOSFETs and p-MOSFETs with different

Ge mid-infrared photonic integrated circuit

substrate concentrations. It was found that SS saturates

M. Takenaka, Yuto Miyatake, Tipat Piyapatarakul,

at temperatures below 10 K for n-MOSFETs, whereas

Chao Zhang

increases with decreasing temperature for p-MOSFETs.

We are advancing research on mid-infrared opti-

We have revealed that this result can be explained quan-cal integrated circuits using Ge waveguides formed ontitatively by considering the low-energy part of tail states

Ge-on-insulator (GeOI) substrates. By analyzing thenear the band edge as localized states and the high-energy

operating principles of avalanche photodetectors withpart as mobile states.

PIN junctions formed on Ge waveguides using GeOI
substrates, we theoretically demonstrated that they have

Takenaka Laboratory

higher sensitivity compared to Si.

(https://sites.google.com/g.ecc.u-tokyo.ac.jp/takenaka-lab/)

On-chip/Off-chip optical interconnect
Mitsuru Takenaka, Rui Tang, Yuto Miyatake,
Tipat Piyapatarakul, Tomohiro Akazawa,

Uchida Laboratory(http://www.ssn.t.u-tokyo.ac.jp)

In the Internet-of-Things (IoT) era, every physical

Sheng Fu, Hiroya Sakumoto, Dhruv Ishan Bhardwaj,

device will be connected to network. In this framework,

Kentaro Komatsu

any physical devices will have sensors that will continu-

We are advancing research on optical interconnects andously obtain various kinds of physical as well as chemical

I/O for LSIs using silicon photonics and other technolo-

information around us. We expect that big data consistinggies. By utilizing a high-sensitivity phototransistor withof these sensor outputs will be analyzed with AI and valu-

an InP thin film integrated on a Si waveguide, we suc-able information will be extracted to improve our quality

cessfully monitored the optical intensity in the waveguideof life. In our group, low-energy sensors and information

with low insertion loss. Simultaneously, we also succeeded

processing devices have been developed by pursuing phys-

in monitoring the output intensity of an optical switch

ics of nano-mateials and nano-devices. Recent research

driven by an integrated hybrid MOS phase shifter.

topics are as follows.
1. Metal nano-film sensors for breath diagnosis
2. T hermal transport analysis of nano-meterials for37

low-energy sensors

followed by chemical vapor deposition of parylene as the

3. Electron-phonon interactions at the interface of insula-

3
CCCCCCCCC CCCCCCCCCCCCCCCCC
C

tor and semiconductor

layer of dinaphthothienothiophene (DNTT) and gold

4. Supramolecular sensors

contact electrodes were formed by thermal evaporation.

5. Information processing devices beyond von Neumann

Finally, OTFTs on nanofilms were delaminated manuallyarchitecturefrom the supporting substrate to become free-standing
state. The fabricated transistors exhibited electrical char-

Someya-Yokota-Yamagishi Laboratory(http://www.ntech.t.u-tokyo.ac.jp/, https://fles.t.u-tokyo.ac.jp/)

Fabrication of Self-adhesive Organic Thin Film

acteristics comparable to those fabricated on conventional
substrates. They showed excellent yield (over 90%), with2

mobility of 0.19 ± 0.02 cm /Vs and maximum on/off
ratio of above 105.

Transistors on Elastomeric Nanofilms
Chika Okuda, Sunghoon Lee, Kento Yamagishi,
Tomoyuki Yokota, and Takao Someya
Devices that can be intimately contacted with our skin

Mita Laboratory(http://www.if.t.u-tokyo.ac.jp)

are increasingly gaining attention because of their huge

TopoMEMS: Development of Ideal Variable MEMS

potential in collecting long-term vital data for future

in view of Future Topological Quantum Computing

healthcare, nursing, or sports activities. One of the key

Y. Mita, R. Takahashi, K.Tsuji, A.-C.Eiler, S. Yasunaga,

components is flexible or stretchable transistors, sinceA.Higo, T.Iizuka, M.Ezawa (Dept. Applied Physics)

they are necessary for signal amplification close to the

Recently, new computation methods that use

body, or sensor matrixes to collect spatial data. Although

Topological nature are drawing much attentions in view

these devices can contact well to the human skin, adhe-of future Quantum computing. Calculation takes advan-

siveness and robustness needed improvement in order totages Topological natures existing in several different fields

achieve long-term signal collection. Nanofilms, which are

ex-pressed as Hamiltonian matrices. Our team, granted

below 2 µm thick and are made of elastomeric materials,

by JST CREST project, tries to explore electrical expres-have shown sufficient adhesiveness and robustness to besion of Hamiltonian matrices used for computation.

worn on skin for over a week. These elastomeric nanofilms

Team Mita will develop ideal variable electrical devices

has become a candidate for wearable devices’ interface,

as well as ideal MEMS devices. We named such devices

but only electrodes have been fabricated on them, due toand systems “TopoMEMS”. As an initiating study, we

difficulty in handling and adhesiveness issues during thehave taken Su-Schriffer-Heeger model. We have newly

fabrication.

proposed a method to make use of magnetic coupling

We fabricated novel device structure and process of

instead of electrostatic coupling to establish topologicalorganic thin film transistors (OTFT) on elastomericcircuit. The successful demonstration have been accepted

nanofilms. The substrate film is ultrathin with averagein an international conference. In parallel, a new concept

thickness of 1～2 µm, enabling the film to be self-adhe-of making use of MEMS movement directly for compu-

2

sive requiring ~130 µJ/cm for detachment from artificial

tation is granted as JSPS Kakenhi Kiban A. A three-stage

skin. This film was fabricated by dip-coating electrospun

bistable MEMS actuators have been successfully demon-

polyurethane nanofibers into polydimethylsiloxane solu-

strated and presented in the international conference.

tion. The film was then placed onto a flexible supporting
substrate with release agent. Bottom gate was formedby thermally evaporating gold through a shadow mask,38

dielectric layer. Subsequently, organic semiconducting

Study on LSI-MEMS energy-autonomous distrib-high electron dose and sharp edge due to cell (charac-

uted microsystemster) projection machine configuration is being examined.
The breakthrough in question is to extend the large-area

CNRS-UTokyo IIS / CNRS C2N)

EB lithography, whose pattern approximation have been

As one example of future integrated MEMS that islimited to rectangular shapes, into expressing free-form

expected to open new research and industrial applica-smooth shapes and a number of periodical small patterns.

tion fields, the authors are trying to show a top-downThis year, pattern and process design has been successful

application of energy-autonomous harmonized distrib-

to obtain gap structure less than 16-nm wide. The result

uted mi-crorobots. A number of identical tiny robots,

has been presented as a peer-reviewed journal.

sized below 1cm, will be released in an environment.
Individual robot can communicate with their neighbor,

Universities-Industries collaborative research on

stick each other, and share energy, to realize coopera-

highly-functional system by MEMS post-process

tive function. The French National Research Centerof CMOS-VLSI(ANR) grant that the PI received on behalf of host pro-Y. Mita, R. Shimamura, F. Sakuma,

fessor of CNRS laboratory in the Institute of Industrial

S. Yasunaga, T. Lévi(IMS-CNRS,Bordeaux),

Science (LIMMS, CNRS-IIS, UMI 2820), together with

G. Larrieu (LAAS-CNRS,Toulouse), Y.Ikeuchi (IIS),

FEMTO-ST Laboratory and PSA-Peugeot Laboratory,

A. Tixier-Mita (IIS), K.Saito (Nihon Univ.)

named Programmable Matter”, has concluded with some

The research targets are new sensor devices, made by

PoC devices. The project is fol-lowed by microrobots forpost-process at clearnrooms such as d.lab Takeda Super-

biological applications with Dr Gilgueng Hwang.

cleanroom and others, of VLSI wafer made through d.lab/

3
CCCCCCCCC CCCCCCCCCCCCCCCCC

Y. Mita, K.Misumi, G. Hwang (LIMMS,C

VDEC. The important finding has been that VLSI wafer
Integration of electrode devices on MEMS fluidic

acquired just after transistor fabrication could sustain pro-devicescesses even with heat treatment, such as deposition, ion

Y. Mita, A.-C. Eiler, A. Higo, E.Ota, A. Mizushima,

implantation, and drive-in. In 2016, a VLSI device madeN. Kawai, Y.Okamoto (AIST), N.Washizu (Advantest),

on Silicon-on-Insulator (SOI) wafer was successfully

M. Fujiwara, T.Sawamura

Deep-RIE processed. The industrial interest is its versatility

Towards the goal of production of brand-new sensor– many different types of application devices, which differ

devices with higher sensitivity and functionality, the team

one from another according to request of market, can be

is working on small-gap electrode fabrication process. Thisfabricated by using the same technology. More and more

year, we have developed a post-process on Ful-ly-Depletedcompanies are interested in the scheme and are working

SOI VLSI device for massively parallel measurement andon the technology on the collaborative research projects,

its integration is underway. Variation of I-V characteristics

including international cooperative research projects. Thishas been the issue but we could identify the root cause. In

year we have realized a new scheme “Bio-Chiplet” that

addition, additive (electroplating) fab-rication of micro

enables agile measurement system preparation. We haveand nano structure has been inisiated.

successfully demonstrated dual-modal measurement ofAlbumin and pH by composed chiplets. Also, in view ofFine Large-Area Electron Beam Lithography Expo-vertical (stack) integration, we have demonstrated “nanosure Methods

cone-shaped penetrator” that breaks isolation layers (bothA. Higo, Y. Ochiai, M. Fujiwara, T.Sawamura, Y. Mita

intentional and unintentional ones) between chiplet pads.

The team explores newly-acquired (in 2013) rapid

The fabrication and measurement results were presented

electron beam writer F7000S-VD02. The capability ofin IEEE MEMS conference (world’s top conference) and39

the presenter student (Mr. Shimamura) obtained IEEE
MEMS Outstanding Poster Presentation Award, which is
the top award in MEMS area.
3
CCCCCCCCC CCCCCCCCCCCCCCCCC
C

Test Structure for high-density CMOS-MEMS hybrid integrated Technology
Y.Mita, A.Mizushima, K. Misumi, H. Matsuoka,
M. Yamagata, A.Higo, R. Nakane,
K.Tsumura (Toshiba), T.Yoda (TITech),
K. Higashi (Toshiba), and Y.Ochiai
Chip-level highly-dense bonding integration is drawing
high attention to simply obtain high-functional system;
preventing slip misalignment is one of challenges towards
million-level micron-square pads bonding. We try to
introduce passive alignment mechanism inspired by teeth
clenching. Preliminary results have been accepted in aninternational conference.

40Appendix
A.1 VDEC CAD Tools
in Figure A.1.1. For each CAD tool, VDEC provides

to the registered researchers in universities and colleges in

10-1000 floating licenses. Those CAD tools can be uti-

Japan. The CAD tools we provided in 2024 through thelized only for research and education activities in national

activities of VDEC in Systems Design Lab (d.lab) areuniversities, other public universities, private universities,

shown in Table A.1.1. The researchers can use those CAD

and colleges. When one is going to use VDEC CAD tools

tools when their local machines, whose IP addresses are

and chip fabrication service, some faculty member of his/

registered in advance, are authorized by one of VDEC

her research group in a university or a collage needs to do

license server located in the ten VDEC subcenters shownuser registration.

Table A.1.1

A-1
Appendix

Since 1996, VDEC has provided CAD software licenses

VDEC CAD tools

Name
Cadence tool set

Siemens tool set

Function
Verilog-HDL/VHDL entry, Simlation, Logic synthesis,
Test pattern generation, Cell-based (including macros) place, route, and back-annotation, Interactive
schematic and layout editor, Analog circuit simulation, Logic verification, Circuit extraction
Verilog-HDL/VHDL simulation, Logic synthesis, Test
pattern generation, Cell-based (including macros)place, route, and back-annotation, Circuit simulation, Device simulation
Layout verification, Design rule check

Silvaco tool set
ADS/Golden Gate
Bach system
LAVIS

Fast circuit simulation
Design and verification of high-frequency circuits
BachC-based design, synthesis, and verification
Layout visualization platform

Synopsys tool set

VendorCadence Design Systems, Inc.

Synopsys, Inc.

Siemens Electronic Design Automation Japan K.K.
Silvaco Japan Co., Ltd.
Keysight Technologies
Sharp
TOOL

Fig. A.1.1 VDEC Subcenters

41

A.2

 tatus of Chip Fabrication Support at Platform Design Research
S
Division

As for the support for VLSI chip prototyping, in thepilot project in FY 1994 and 1995, there was only one
foundry, NEL's CMOS 0.5µm (the process was later
continued by Hitachi Hokkai Semiconductor). After theinauguration of VDEC in 1996, the 1.2-µm CMOS process of Motorola Japan (which was continued by ON
Semiconductor in 1999) started cooperation, and theA-2

0.6-µm CMOS process of ROHM was added in 1997.

Appendix

In 1997, CMOS 0.6µm from ROHM was added,
followed by 0.35µm from Hitachi, Ltd. in 1998, and
0.35µm from ROHM in 1999. In addition, as part of the
IP development project, a prototype of STARC 0.13µm(a) Trend of number of designs fabricated.

was developed. Since FY 2001, we have been providing services of CMOS 0.18µm from Hitachi, Ltd. In
2002, under the leadership of Dr. Iwata of Hiroshima
University, we conducted a trial trial fabrication service
in cooperation with VDEC and MOSIS. This service
provides overseas fabs such as TSMC and IBM at low costthrough MOSIS. Furthermore, under the leadership of
Dr. Shibata of the University of Tokyo, NEC Compound
Device, Inc. provided a prototype service for bipolar LSI.
In 2004, we started prototyping Oki Electric CMOS SOI
0.15µm process and ASPLA 90nm process as test prototypes, and the 90nm prototype was operated as a regular
prototype from 2005 in the form of public solicitation. In(b) Trend of designed area.

FY2006, we started trial production of 0.18µm process by
ROHM and test production of 0.25µm SiGeBiCMOS
by Hitachi, Ltd. In FY 2007, we started to study an
advanced process to succeed 90nm CMOS, which wasterminated in FY 2007, and in FY 2008, we started trial
production of eShuttle's 65nm CMOS. In addition, as
part of the METI-STARC project "Next Generation
Semiconductor Circuit Architecture Commercialization
Support Project," prototype production using Renesas
Electronics' 40nm CMOS was also started. On the other
hand, CMOS1.2µm was terminated in September 2011,
Renesas Electronics' 40nm CMOS prototyping was terminated in 2012, and eShuttle's 65nm CMOS prototyping
was terminated in August 2013. As a successor to CMOS
1.2µm, a test prototype of CMOS 0.8µm was conductedin October 2012 with the cooperation of Onsemi-Sanyo
Semiconductor Manufacturing Co.(now JS Foundry).

42(c) Trend of designed area normalized by design rule.
Figure A.2.1

T rend of number of designs and designed chiparea.b

As for the leading-edge prototyping, STMicroelectronics
started FD-SOI 28nm CMOS prototyping through CMP
of France in FY 2013. In addition, we started SOTB 65nm
CMOS prototyping by Renesas Electronics as a regular
prototyping in FY2015, and concluded in FY2022. In
FY2021, we started BiCMOS 0.18um prototypes underan agreement with IHP of Germany.
Fig. A.2.1(a) shows trends of number of chip designed
for VDEC chip fabrication. For the first 6 years until
2001, the number of designed chips shows steadyincrease, which means drastic improve of the effectivenessA-2

drastic increase of number of students related to LSI chip
design and education. During few years of stable number
around 400 chip designs per year, we can see transition

Figure A.2.2 T rend of number of processors and universities
fabricated chip.

Appendix

researches and education of LSI design, and we assumeof designs toward finer process. In 2007, we saw a large
drop, which was caused by sudden process transition from0.35µm CMOS to 0.18µm CMOS, and in 2008, we
also saw another drop by process transition from 90nm
CMOS to 65nm CMOS.
Fig. A.2.1(b) shows trends of designed chip area, whichshows much clear trends of drop by process migration.
On the other hand, Fig. 2.3.1(c) shows trends of designed
chip area normalized by design rule, which assume to bestrong relation with design efforts. Coming from the factthat the normalized chip area is still growing, we assume
the major reason for decrease of number of chips anddesigned area is increase of design effort per chip and perunit area due to process scaling.
Fig. A.2.2 shows trends number of professors and universities fabricated chip. Number of professors who havecontracted NDA for process technologies to access design
rules and design libraries are, 304, and 56, respectively, for0.18 µm CMOS, and 0.8um CMOS.
Table A.2.1 lists chip fabrication schedule in 2023.
Please refer to list in Appendix B for details of designers
and contents of chip designed.

43

Table A.2.1

Chip fabrication schedule in 2023

0.8 µm CMOS (JS Foundry (former On-Semiconductor – Sanyo))
2023#12023#2Chip application deadline
2023/7/3
2024/1/9

Design deadline
2023/9/25
2024/3/25

Chip delivery
2023/12/18
2024/6/24

Design deadline
2023/6/26
2023/9/4
2023/10/23
2024/2/26

Chip delivery
2023/10/13
2023/12/16
2024/2/9
2024/6/7

0.18 µm CMOS (Rohm)

A-2
Appendix
442023 #1
2023 #2
2023 #3
2023 #4

Chip application deadline
2023/4/3
2023/6/12
2023/7/31
2023/12/4

A.3 Seminar
Seminars are always needed as the advancement of

the CAD Seminar twice per year. In the CAD Seminar,

LSI design technology. In 2023, VDEC has held CAD

VDEC invites lecturers from venders including Cadence,

Seminar and Designer’s Forum, for academic circuit

Synopsys and Keysight to give tutorials on their CAD

designers.

tools. The seminar is held in VDEC, The University ofTokyo and VDEC sub-centers simultaneously in several

A.3.1 CAD Seminar for VDEC users

universities nationally, in March of one fiscal year. Each

Along with advancement of circuit design CAD tools,

tutorial takes one or two days.

tutorials on these tools are highly demanded. VDEC offers
A-3

CAD technical seminar in 2023 fiscal year

CAD Seminar I
Venue

Number of Applicants

8/17

Date

Cadence Virtuoso Schematic

Tutorial

online35

8/18

Cadence Virtuoso Layout

online37

8/22

Cadence Voltus-Fi

online10

8/30

Keysight EMPro-FEM

online20

9/4

Cadence Quantus

online15

9/14

Cadence Spectre

online26

9/15

Synopsys: PrimeSim SPICE/HSPICE

online11

9/28

Synopsys: ICC2 Q&A

online1～9/30

Synopsys: ICC2

on-demand

21

Venue

Number of Applicants

Appendix

Table A.3.1

CAD Seminar II
Date

Tutorial

3/11

Keysight ADS Fundamental

online28

3/15

Synopsys Design Compiler & IC Compiler II Q&A

online13

3/15

Synopsys StarRC Q&A

online11

3/21

Cadence Virtuoso Layout Editor

online51

3/22

Cadence Innovus Digital Implementation System

online23

3/25

Cadence Clarity 3D Solver

online16

3/26

Synopsys Sentaurus Q&A

online12～3/31

Synopsys Design Compiler

on-demand

29

～3/31

Synopsys IC Compiler II

on-demand

22

～3/31

Synopsys StarRC

on-demand

24

～3/31

Synopsys Sentaurus Basic & Post Basic

on-demand

18

～3/31

Synopsys Photonics Solutions

on-demand

1445

A.3.2 Refresh Seminar for industry and academia

invited to give lectures on circuit design, covering the topics

The fundamental and advanced knowledges are bothon analog, digital, RF, MEMs, and basic design flow. The

imperative to integrated circuit design. VDEC offers

seminar was originally launched in 1998, with the support

the Refresh Seminar for industrial and academic people.

of Ministry of Education Technical Education Division. It is

University professors and highly experienced engineers are

now being supported by several industrial/academic societies.

Table A.3.2
Date

CourseContents

9/5, 6MEMS I

Basics of MEMS
MEMS Simulation and Layout

Yoshio Mita
(Univ. of Tokyo)

6

9/11,
12,13

MEMS II

MEMS design
MEMS fabrication and measurement at
Takeda Cleanroom

Yoshio Mitai(Univ. ok Tokyo)

4Analog Circuit Design

Analog Circuit Design and simulation
Integrated Circuits Verification (LVS,DRC)

Masahiro Sugimoto(Chuo Univ.)
Tetsuya Iizuka(Univ. of Tokyo)
Koji Kotani(Akita Prefectural Univ.)

14

CMOS-RF Circuit
DesignModulation/Demodulation
Cascaded connection
Basic Performance
Transceiver Architecture
Circuit Element
Design Flow

Hiroyuki Ito(Tokyo Inst. of Tech.)

6

8/28, 29

A-3

Refresh Seminar

Appendix

8/31, 9/1

9/20, 21,22

9/25, 26

LectureAttendees
Kazutoshi Kobayashi
Digital circuit design flow using
VDEC Digital Circuit(Kyoto Institute of Technology)
VDEC-collaborated CAD environment
8
Design Flow
Ryo Kishida (Toyama Prefectural Univ.)and process
Shinichi Nishizawa (Waseda Univ.)
Custom circuit design flow using
Transistor-Level
Toru Nakura
7
VDEC-collaborated CAD environment
Circuit Design Flow
(Fukuoka Univ.)and process

Fig. A.3.1

46

Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

A.3.3 Designer’s Forum for academia
VDEC LSI designer forum intended for students andyoung teachers were held. The VDEC LSI designer forum
has aimed to sharing the information that generally hard
to be obtained common technical reports or academical papers, such as the failure an LSI designer had been
through and the solution, and the construction methodin the design milieu in the laboratory.

Table A.3.3

Program of Designers Forum in 2023

A-3
Appendix

9/29-30 Hybrid Attendees: On-Site 29, Online 2
9/29
13:00Reception
13:30-13:35
Opening
13:35-14:35
Keynote Speech
14:35-14:45
Break
14:45-16:05
Design Award Presentation I
16:05-16:10
Break
16:10-17:55
Design Award Presentation II
9/30
9:00-10:15
Idea Contest Presentation
10:15-10:25
Break
10:25-11:35
PhD Session
11:35Voting and Award Ceremony

47

A.4

Venture companies related to VDEC

Some professors related to VDEC started venture companies. The following is a list of the venture companies related to
VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (Representative Director)
Description of business : (1) LSI design service(2) Engineer dispatching service(3) Recruitment(4) Management consulting

A-4
Appendix[2] Synthesis Corporation(Merged with Soliton Systems on July 1st in 2017, http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)
Description of business : (1) System LSI development and design service(2) IP development and sales(3) Development and sales of IPs(4) Development of EDA tools[3] ASIP Solutions (http://www.asip-solutions.com/)
Related professor : Professor Masaharu Imai (Representative Director, CTO)
Description of business : (1) R&D, education and consulting of IoT application system(2) Sales of ASIP design tool and consulting of ASIP development[4] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Representative Director)
Description of business : (1) LSI design and development(2) Development of LSI CAD and LSI evaluation tools(3) Design consulting, etc.
[5] A-R-Tec Corp. (http://www.a-r-tec.jp/)
Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business : (1) Analog IC design and measurement(2) PCB noise analysis(3) Develop human resources, OJT, Lecture[6] Ishijima Electronics (http://ishi.main.jp/)
Description of business : (1) Electronic circuit and board development(2) Software development(3) Consulting48

System Design Lab (d.lab),
School of Engineering, The University of Tokyo
Annual ReportAugust, 2024
Published by
System Design Lab (d.lab), School of Engineering, The University of Tokyo
Tadahiro Kuroda
Address: Hongo 7-3-1, Bunkyo-ku, Tokyo, 113-8656, Japan
Printed in
SOHOKKAI co., Ltd. Tokyo Branch
Address: Koutoubashi 4-25-10, Sumida-Ku, Tokyo, 130-0022, Japan
Copyright Ⓒ by System Design Lab (d.lab), School of Engineering, The University of Tokyo

Systems Design Lab, School of Engineering, The University of Tokyo 2024