The development of a 128-channel ultra-low noise transimpedance amplifier system
Tian Wang, Zhixue Li, Kewei Gu, Tong Liu, Junxia Wu
Institute of Modern Physics, Chinese Academy of Science, Lanzhou, China
University of Chinese Academy of Sciences, Beijing , China
Email: wangtian@impcas.ac.cn

CONTENTS
1. Background and Significance2. System Structure
3. Analog Front-end Electronics
4. Digital Signal Processing
5. Electrical Performances
6. Beam Tests with MSIC
7. Conclusion

2

Background and SignificanceProton Radiation Effects Facility

PREF’s terminalParameterValue

Number of channels

128 (16×8)

Measurement range

25 pA ∼ 1.8 µA

Analog bandwidth

1 kHz

Sampling frequency

60 MHzMSIC: Multi-strip
Ionization Chamber

readout system

3System Structure
Data acquisition board and AFE

Data processing board

16 PIN connector

Ethernet

Trigger port

Serial port
AFE

Serial port
Kintex-7
FPGA

ADC1

JTAG

ADC2

DDR3

Clock
Fan-out

SD cardPowersupply

Flashmemory

High speed connectors

Zynq
FPGAPower
supplyDDR

Spartan-6
FPGA

OSC 60 MHz
4

System Structure
Data acquisition board and AFE* 8

Diagram of this multi-channel readout system

Data processing board

5Analog Front-end Electronics
Gain: 500 kΩ
Bandwidth: 3.9 kHz

Gain_1 : 1
Gain_2 : 10
Gain_3 : 100-3 dB frequency : 1 kHz
Stopband attenuation: -66 dB

Block diagram and the PCB board diagram of the AFE

6

TIA Circuit with the feedback capacitor
𝟏𝐂𝐟 =(𝟏 + 𝟏 + 𝟖𝛑𝐑 𝐟 𝐂𝐬 𝐟𝐆𝐁𝐖𝐏 )𝟒𝛑𝐑 𝐟 𝐟𝐆𝐁𝐖𝐏

a gain peak in the 150 kHz

7

Firmware of the Kintex-7 FPGA
480 Mbps

80 I/O ports

60 Msps

1 MspsReduced by 85%

80 Mbps

12 I/O ports8Zynq FPGA Firmware Design

Ethernet port

DDRSpartan-6Schematic of the Zynq FPGA firmware and the PCB board diagram.
9

ARM Embedded DesignControlparameter
Raw data

Profile arrays

One frame profile

Schematic of the ARM embedded design and the graphical user interface.
10Off-line test platform

Handshake signal
Control signal

Current signal

16 core shielded cable11Baseline Calibration Test

• Mean offset :-14.34 nA to 0.05 nA• FWHM:
10.01 nA to 0.75 nA.

The 128 channels’ DC-offsets before and after the offset calibration.

12Effective Number of Bits TestGain

Bin width

SINAD

SFDRENOB

500 kΩ

0.1 Hz74.10 dB

87.07 dB

12.0 bits

5 MΩ

0.1 Hz65.57 dB

79.55 dB

10.9 bits

50 MΩ

0.1 Hz61.40 dB

73.81 dB

9.9 bits

gain : 500 kΩ

gain : 5 MΩ

Noise spectral density of the readout electronics.

gain : 50 MΩ

13

Amplitude Linearity Test
Gain

Min amplitude

Max amplitude

StepNonlinearity

500 kΩ

0.1 μA

1.5 μA

0.1 μA< 0.09 %

5 MΩ

10 nA

150 nA

10 nA< 0.11 %

50 MΩ

1 nA

15 nA

1 nA

< 0.12 %Output amplitude linearity of the readout electronics.

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Channel Consistency Test
Mean : 7.36
σ : 0.04

gain : 500 kΩ

Mean : 66.98
σ : 0.36

gain : 5 MΩ

Mean : 660.40
It is Compensable!
σ : 5.04

gain : 50 MΩ

Statistical distribution of the K value in different gains.

15

Beam Test with MSIC in HIRFL-CSR
Beam:O6+, 60 MeV/u

Experimental
terminals

0.5 mm16.3 mm

13 mm

Beam profiles of the slow extraction in HIRFL-CSR.

-2.8 mm16

Beam Test in PREF - 60MeV proton beam
Unscanned beam

Scanning area:50 * 50 𝒎𝒎𝟐Waterfall

Beamcurrent
32.3 pA

ProfileScanning area:100 * 100 𝒎𝒎𝟐
Beamcurrent
19.4 pA

Scanning area:200 * 200 𝒎𝒎𝟐

Beamcurrent
9.3 pA

Uniformity
17

Beam Test in PREF – weak beams
60MeV proton beam

10MeV proton beam

Beam current ：0.14 pA

Beam current ：0.11 pA

Beam profiles of the slow extraction in PREF.

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Conclusion
1. A 128-channel readout system with 60 Msps.

2. A new I-V converter with a high dynamic of 25
pA–1.8 μA.
3. An adaptive decoding module to decode the 480
Mbps serial data.
4. An automatic calibration device.
5. Extend to other fast profile monitors.

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