Accepted Manuscript
Development of a monolithic pixel sensor based on SOI technology for
the ILC vertex detector
Shun Ono, Miho Yamada, Manabu Togawa, Yasuo Arai, Toru Tsuboyama,
Ikuo Kurachi, Yoichi Ikegami, Kazuhiko Hara, Taohan Li, Akimasa Ishikawa

PII:
DOI:
Reference:

S0168-9002(18)30810-6
https://doi.org/10.1016/j.nima.2018.06.075
NIMA 60936

To appear in:

Nuclear Inst. and Methods in Physics Research, A

Received date : 17 February 2018
Revised date : 25 May 2018
Accepted date : 20 June 2018
Please cite this article as: S. Ono, M. Yamada, M. Togawa, Y. Arai, T. Tsuboyama, I. Kurachi, Y.
Ikegami, K. Hara, T. Li, A. Ishikawa, Development of a monolithic pixel sensor based on SOI
technology for the ILC vertex detector, Nuclear Inst. and Methods in Physics Research, A (2018),
https://doi.org/10.1016/j.nima.2018.06.075
This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to
our customers we are providing this early version of the manuscript. The manuscript will undergo
copyediting, typesetting, and review of the resulting proof before it is published in its final form.
Please note that during the production process errors may be discovered which could affect thecontent, and all legal disclaimers that apply to the journal pertain.

*Manuscript
Click here to view linked References

Development of a monolithic pixel sensor based on SOI
technology for the ILC vertex detector
Shun Onoa , Miho Yamadaa , Manabu Togawaa, Yasuo Araia , Toru
Tsuboyamaa, Ikuo Kurachia , Yoichi Ikegamia , Kazuhiko Harab , Taohan Lic ,Akimasa Ishikawaca Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org. (KEK),

1-1 Oho, Tsukuba, Japanb Faculty of Pure and Applied Sciences, University of Tsukuba, 1-1-1 Tennodai, Tsukuba

305-8571, Japanc Department of Physics, Tohoku University, 6-3, Aramaki Aza-Aoba, Aoba-ku,Sendai

980-8578, Japan

Abstract
SOI detector SOFIST is a pixel sensor optimized for the International LinearCollider vertex detector. SOFIST stores both position and timing informationof charged particles. Our aim is to achieve 3 µm single-point resolution witha 20 × 20 µm2 pixel. The first prototype sensor SOFIST Ver.1 was evaluatedwith a 120 GeV proton beam at the FermiLab Test Beam Facility. The position
resolution was about 1.3 µm. We are currently evaluating the next version ofsensor, SOFIST Ver.2, which has an in-pixel comparator and timestamp.
Keywords: SOI detector, Vertex detector, ILC

1. Introduction
Silicon-on-Insulator (SOI) technology integrates both silicon sensor and readout electronics in the same wafer [1]. Pixel detectors based on the SOI technology have several advantages compared with conventional hybrid detectors which5are used for high energy physics experiments. The SOI detector realizes a low
material budget, small pixel size, and low detector capacitance owing to themonolithic structure without bump-bonding. In addition, the detector employs
Email address: onos@post.kek.jp (Shun Ono)

Preprint submitted to Elsevier

May 25, 2018

a double SOI structure to improve radiation tolerance and to reduce cross talkbetween circuits and sensors (Figure 1). The double SOI wafer has an additional
10

silicon layer for compensating the effect caused by the accumulation of holes in
the oxide layer [2].

Figure 1: Structure of the double SOI pixel sensor. The additional silicon layer is in themiddle of the buried oxide layer.

We are developing a new SOI pixel sensor for the vertex detector of theInternational Linear Collider (ILC) experiment. The ILC requires a new vertex
detector system with high spatial resolution in order to identify the decay ver15

tex of short-life-time particles for the precise measurement of Higgs boson andthe search for physics beyond the Standard Model. We are currently designing an SOI pixel sensor, SOi sensor for FIne measurement of Space and Time(SOFIST), which has a pixel circuit with high position resolution and fine timeresolution.

20

In this paper, we report the development and evaluation results of theSOFIST prototype sensors.

2. SOI sensor for ILC
The overview of the SOFIST sensor is shown in Figure 2. The following arerequirements for the SOFIST development [3].
25

• Single point resolution : 3 µm
• Identification of 1300 bunches in ILC beam collisions every 554 ns2

Timestamp memory
SW1
Timestampoutput
Ramp signal
SW2

SW1
DQSW2DQ

VthShift-register
Comparator

SW1
Signal output

Pre-ampSW2

Analog signal memory

Figure 2: SOFIST chip overview (left panel) and pixel architecture (right panel). The sensor chip has 500 × 3,125 pixels. The column-parallel ADC circuits are arranged along thelongitudinal direction of the sensor chip.

The pixel circuit of the SOFIST has an area of 20 × 20 µm2 . For each pixel,
the signal amplitude and timing information are stored in corresponding memories when the signal amplitude is higher than the threshold of the comparator.
30The timing information is used for the hit bunch identification. The timestamp
memory holds the voltage level of the ramping signal. The ramp voltage is proportional to the integration time and provided globally to all pixels in a chip.
This timestamp circuit records the hit timing as the ramp voltage. In order tohandle possible multiple hits during the signal accumulation, the pixel has mul-35

tiple sets of analog signal memories and timestamps. It is necessary to optimize
the implementation of these functions in a small pixel area. We are prototyping
step sensors for realizing this pixel circuit .

3. SOFIST Ver.1
The prototype chips were fabricated with the 0.2 µm Fully Depleted Silicon40

on-Insulator (FD-SOI) CMOS process of Lapis semiconductor [4]. The first chipis called SOFIST Ver.1. It has 50 × 50 pixels with a pitch of 20 µm (Figure 3).
The sensor thickness is 500 µm. Each pixel circuit has a pre-amplifier andmemory capacitors. The pre-amplifier is a charge sensitive amplifier with acommon-source stage and feedback capacitance. The sensor chip also has 8-bit345

Wilkinson-type ADC circuits of 50 channels.
Test input

Output amplifier
Pixel output
Pre-amp(Charge sensitive amplifier)Analog signal memory

Figure 3: Chip overview (left panel) and pixel schematic (right panel) of SOFIST Ver.1. Thesensor chip has 50 × 50 pixels.

The Ver.1 sensor was evaluated with a 120 GeV proton beam at the FermiLab
Test Beam Facility [5]. The detector setup consists of two SOFIST Ver.1 andfour FPIX, SOI Fine PIXel detector (Figure 5). The FPIX also acts as the SOI
detector and has small pixels with a pitch of 8 µm [6]. The FPIX sensors were50

used as the tracking detector for evaluating the SOFIST position resolution.
Since the collected charge signal is proportional to the depletion thickness,
we measured the backplane bias dependence of the SOFIST signal (Figure 4).
The SOFIST signal was saturated about -80 V, so the sensor layer of 500 µm

Peak signal [ADU]

was fully depleted at this voltage.

140120100806040200020406080100120140
Bias voltage (Absolute value) [V]Figure 4: The back plane bias dependence of the SOFIST signal. The bias voltage was applied
from -15 to -130 V. The signal saturation indicates full depletion of the sensor layer.

55

The SOFIST sensor data were taken with backplane biases of -130 and -15
V, which correspond to the sensor depletion thicknesses of 500 and 200 µm,

4respectively. The charge signal was digitized by 12-bit ADC on the readoutboard. The hit signal was reconstructed by clustering 5 × 5 pixels around thehit pixel. The hit position on the SOFIST chip was calculated from the weighted
60center of the cluster signal.

Figure 5: Detector setup for the beam test. The trigger signal was generated by a scintillator
and an ATLAS pixel detector with an FE-I4 readout chip.

We analyzed the position resolution by using the particle tracks. We extracted the track candidates from the hits of four FPIX sensors. There weresome spurious hit combinations due to the long integration time of FPIX. The
track with minimum chi-square to the straight line was chosen for the analysis.
65

We analyzed the residual of the hit position of the SOFIST to the reconstructed
track. Figures 6 and 7 show the residual distributions of X (horizontal) andY (vertical) directions at 500 µm and 200 µm depletion thickness, respectively.
The standard deviation of the residual distribution was evaluated as the position resolution. We obtained position resolutions of 1.37 in X direction and70

1.35 µm in Y direction at a depletion thickness of 500 µm. The residuals werestill narrow at a depletion thickness of 200 µm, and the position resolution is
1.33 µm in X direction and 1.32 µm in Y direction. The measured residual is
the sum of the squares of the intrinsic resolution of SOFIST Ver.1 and the track
uncertainty. The track uncertainty is expressed in terms of the FPIX resolution

75

and the geometrical position of the SOFIST. The FPIX is shown to have an intrinsic resolution of about 0.65 µm [6] and the track uncertainty on the SOFIST

5

sensor becomes about 0.65 µm. The SOFIST intrinsic resolution was extracted
about 1.2 µm.
!"#$!%&
C$%+5D2E,FI,'!"#$%&"'--/-//0</()*#+$%,,-./01$2),,
6*7,8$9,,,!-,:,)7;,,/30455>?)%*2)*,(7$)*%(9$)*%

C$%+7D2E,FI,',,-35-00./--/-//,0-3'<,:,=,--535,!,534

1$2),,,,, ,/3044<,!,/3/@<4
6+AB2,,,,,03@45,!,/3/@'04/()*#+$%,,-./0

1$2),,,! /30-/.

4*5,6$7,,,,,-389.

" -,:,)5;,,,003.,:,90B/<=)%*2)*,08/1$2),,,,, ,/3/8000,! ,/3/?>'/
4+@A2,,,,,-?03-, ! ,>39
,03?.B, ! ,/3/?'

0./

0-/

0-/

0//

0//

</B/

4/

8/././-//"0'!"#$%&"'-./-/"0/"'/'/!0'0/0'
C$%+7D2E,F,GDBH!0/!'/'0/0'
C$%+5D2E,F,GDAH

Figure 6: Residual distributions of X (left panel) and Y (right panel) at 500 µm depletion.
!"#$!%&!"#$%&'()*+),!"#$%&"'()*#+$%,-220$1),,.'2,-../,234.--

5*6,7$8,,,,,93:9;! 9,<,)6=,,4;39/,<,;>?)%*1)*,.22

1<"23#(8$)*%

B$%+6C1D,EH,'

5+@A1,,,,)45567"'2)))! 898444,

5,8:3%);"<)))" =)?)2%@))A898=)?)>,.;93-, ! ,423-

BC2#3'23)

5880$1),,,,, ,232'2/:,! ,2329/-/

9'2-./"#0.,123/$"#)

488)5>D9>) ! )A8957"'2))))) )898D>AD)! )898=684,43..4,! ,2329/:$EF')))))A95AG) ! )898=G=,8922=884'2A,8422

A88'22"4'))=9,>5,8

"42"'

2'

8!A,424'
B$%+6C1D,E,FCAG!A8!,

8,A8A,!"#$%&'()*)H&FI!"#$%&'()*+),

Figure 7: Residual distributions of X (left panel) and Y (right panel) at 200 µm depletion.

4. SOFIST Ver.2
80

Figure 8 shows the SOFIST Ver.2 sensor chip. The sensor has 80 × 64 pixels
with a pitch of 25 µm. Since ILC detector requires the sensor thickness less than
100 µm for reducing multiple scattering effect, the Ver.2 sensor layer is thinned
to 75 µm by grinding the back side of the chip. The Ver.2 pixel has a comparator
circuit for discriminating the signal exceeding the threshold voltage. We have85

designed two types of pixel circuits, namely Analog signal pixel and Timestamp
pixel (Figure 9).

6

Figure 8: Chip overview of SOFIST Ver.2. The sensor chip has 80 × 64 pixels, column-parallel
ADC circuits, and digital Zero-suppression logic.
Test input

Test input

ENEN
SW1

VthD

CDS

Q

SW2
DVthQ

Q

SW1

DQ

SW2

Comparator

Comparator

Pre-amp

DCDS

Pre-amp

Shift-register(Charge sensitive amplifier)

Shift-register(Charge sensitive amplifier)

CDS input

CDS input
SW1

SW1

Output amplifier

Output amplifier

Pixel output

Pixel output
Ramp signal input

SW2

SW2

Analog signal memory

Timestamp memory

Figure 9: The Ver.2 chip has Analog signal pixel (left panel) and Timestamp pixel (rightpanel).The Analog signal pixel stores the signal amplitude of the pre-amplifier output. The
Timestamp pixel stores the ramp voltage for the analog time-stamp.

We will verify in-pixel timestamp function and the degradation of the position resolution. The pixel circuit and size will be optimized for satisfying boththe timestamp and the resolution based on the evaluation of the Ver.2 sensor.
90The sensor production has been completed. We are currently evaluating theVer.2 pixel circuits. Figure 10 shows the responses of Analog signal and Timestamp pixel when a test pulse is inputted. The charge signal is input to the sensor
node of the pixel. The pixel memory holds the signal voltage when the input
signal exceeds the threshold level. Figure 11 shows the pixel timestamp signal

95with inputting test pulse at specific timings. The ramp signal was generated
with 1 mV per microsecond and delivered to each pixel. The slope of measured

7

timestamp became about 0.96 mV per microsecond. We have confirmed thefunctionality of Ver.2 pixel circuits.
Shift-register
Pixel reset

Input ramp-signal

Pixel output
Test pulse

Pixel output

Test pulse

Charge injection

Charge injection

Figure 10: Output responses of Analog signal pixel (left panel) and Timestamp pixel (rightpanel) when the input signal is over the threshold. The pixel signal is reset every 4 µs (magenta

Timestamp output [mV]line). The charge signal is injected at the falling edge of the test pulse (cyan line).

χ2 / ndf

600

1.289 / 8p0− 8.692 ± 0.2742

p10.9663 ± 0.0008837

500

40030020010000100200300

400500600
Test pulse input [ µs]Figure 11: The readout signal of in-pixel timestamp with inputting test pulse. Horizontal andVertical axis are the pulse input timing and the readout signal of the timestamp memory.

5. Conclusion and future prospect
100

We have developed two prototype chips for realizing a new SOI pixel sensor
SOFIST optimized for the ILC vertex detector. SOFIST Ver.1 chip has a pixel
area of 20 × 20 µm2 and column parallel ADC circuits. We evaluated theposition resolution with a 120 GeV proton beam at the Fermilab Test Beam
Facility. We obtained a position distribution of about 1.3 µm at a depletion

8

105

thickness of 200 µm. The SOFIST Ver.1 resolution meets the requirement for
the ILC experiment. SOFIST Ver.2 chip has a pixel area of 25 × 25 µm2 . We
designed an in-pixel comparator for storing the amplitude and timestamp of thehit signal. These pixel functions have been verified by inputting the test pulse.
We are planning a beam test for Ver.2 sensor in February 2018. We are also

110developing next sensors, Ver.3 and Ver.4, with full SOFIST functionality. The
pixel of Ver.3 sensor has both analog signal and timestamp memories within
30 × 30 µm2 . The Ver.4 sensor is to be processed with 3D stacking technology
in order to shrink the pixel size [7]. These sensor chips will be delivered byspring 2018.

115

Acknowledgement
This work was supported by MEXT KAKENHI Grant-in-Aid for Scientific
Research on Innovative Areas 25109006, the Japan/US Cooperation Programin the Field of High Energy Physics. We wish to thank the staff of Fermilab
Test Beam Facility for the support they provided for our beam test. This work120

was also supported by the VLSI Design and Education Center (VDEC), The
University of Tokyo, with the collaboration of Cadence Design Systems, Inc.,
Mentor Graphics Co.,Ltd., and Synopsys, Inc.

References[1] Y. Arai, T. Miyoshi, Y. Unno, T. Tsuboyama, S. Terada, Y. Ikegami,
125

T. Kohriki, K. Tauchi, Y. Ikemoto, R. Ichimiya, et al., Developments ofsoi monolithic pixel detectors, Nuclear Instruments and Methods in Physics
Research Section A: Accelerators, Spectrometers, Detectors and AssociatedEquipment 623 (1) (2010) 186–188.
[2] K. Hara, Y. Arai, S. Honda, I. Kurachi, T. Tsuboyama, N. Tobita,

130

T. Miyoshi, M. Asano, S. Mitsui, Initial characteristics and radiation damage
compensation of double silicon-on-insulator pixel device, PoS (2015) 033.

9

[3] H. Abramowicz, et al., The international linear collider technical design
report—volume 4: detectors, arXiv preprint arXiv:1306.6329.
[4] M. Okihara, H. Kasai, N. Miura, N. Kuriyama, Y. Nagatomo, T. Hatsui,
135

M. Omodani, T. Miyoshi, Y. Arai, Progress of fd-soi technology for monolithic pixel detectors, in: Nuclear Science Symposium and Medical Imaging
Conference (NSS/MIC), 2012 IEEE, IEEE, 2012, pp. 471–474.
[5] Fermilab test beam facility, url: http://ftbf.fnal.gov.
[6] K. Hara, D. Sekigawa, S. Endo, W. Aoyagi, S. Honda, T. Tsuboyama, M. Ya-

140

mada, S. Ono, M. Togawa, Y. Ikegmi, Y. Arai, I. Kurachi, T. Miyoshi,J. Haba, K. Hanagki, Fine-pixel detector fpix realizing sub-micron spatial
resolution developed based on fd-soi technology, Springer Proceedings inPhysics, Technology and Instrumentation in Particle Physics (TIPP2017).
[7] M. Motoyoshi, T. Miyoshi, M. Ikebec, Y. Arai, 3d integration technology for145

sensor application using less than 5m-pitch gold cone-bump connpdfection,
Journal of Instrumentation 10 (03) (2015) C03004.

10