Nuclear Instruments and Methods in Physics Research A 636 (2011) S97–S103

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Nuclear Instruments and Methods inPhysics Research A
journal homepage: www.elsevier.com/locate/nima

A silicon strip module for the ATLAS inner detector upgrade in the
super LHC collider
S. Gonzalez-Sevilla g,, G. Barbier g, F. Anghinolﬁ a, F. Cadoux g, A. Clark g, W. Dabrowski e, M. Dwuznik e,
D. Ferrere g, C. Garcia b, Y. Ikegami d, K. Hara f, K. Jakobs c, J. Kaplon a, T. Koriki d, C. Lacasta b, D. La Marra g,
S. Marti i Garcia b, U. Parzefall c, M. Pohl g, S. Terada d, Y. Unno d, M. Weber gaEuropean Organization for Nuclear Research, CERN CH-1211, Geneva 23, Switzerland
IFIC, Instituto de Fı́sica Corpuscular (CSIC-Universitat de Vale ncia), Ediﬁcio Investigación Paterna, Apartado 22085 46071 Valencia, SpaincPhysikalisches Institut, Universität Freiburg, Hermann-Herder-Str. 3, D-79104 Freiburg, GermanydKEK, High Energy Accelerator Research Organization, Oho 1-1, Tsukuba, Ibaraki 305-0801, Japane
AGH University of Sceince and Technology, Faculty of Physics and Applied Computer Science, Krakow, Polandf
University of Tsukuba, School of Pure and Applied Sciences, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-8571, Japang
DPNC, University of Geneva, CH 1211 Geneva 4, Switzerlandb

a r t i c l e in fo

abstract

Available online 4 June 2010

The ATLAS detector is a general purpose experiment designed to fully exploit the discovery potential of
the Large Hadron Collider (LHC) at a nominal luminosity of 1034 cm 2 s 1. It is expected that after
several years of successful data-taking, the LHC physics program will be extended by increasing thepeak luminosity by one order of magnitude. For ATLAS, an upgrade scenario will imply the complete
replacement of the Inner Detector (ID), since the current tracker will not provide the required
performance due to cumulated radiation damage and a dramatic increase in the detector occupancy.
In this paper, a proposal of a double-sided silicon micro-strip module for the short-strip region of
the future ATLAS ID is presented. The expected thermal performance based upon detailed FEA
simulations is discussed. First electrical results from a prototype version of the next generation readout
front-end chips are also shown.
& 2010 Elsevier B.V. All rights reserved.

Keywords:
ATLAS
UpgradeInner detector
Silicon
Strip module
Hybrid

1. Introduction
A luminosity upgrade of the LHC (Super LHC or SLHC) up to1035 cm 2 s 1 is planned for  2020. The expected integrated
1
luminosity per experiment of  3000 fb
will improve theprecision in different measurements within the Standard Model;
it will also enlarge the discovery region of particles predicted bysome supersymmetric theories and enhance the sensitivity to
low-rate phenomena inaccessible at the LHC energy scale [1].
The detectors will suffer of an increase in the number ofproton–proton interactions per bunch-crossing to  400 (depending on the sLHC ﬁnal bunch-spacing conﬁguration). A
completely new inner tracker for ATLAS is needed, with as basic
requirements in terms of design being radiation hardness andefﬁcient tracking capabilities with detector occupancies undercontrol (few percent). Although the ﬁnal layout has not been
decided yet, most probably the tracker will be an all siliconsystem with new detector technologies and increased granularity.

The current design of the barrel region has four pixel layers at
inner radii; ﬁve strip layers (three short and two long-strip layers)
cover the outer radii. Detailed Monte Carlo simulations withsignatures heavily dependent on the silicon tracker are currently
under study to determine the layout for best performance.
For the strip region, the baseline layout relies in the so-calledstave-concept, in which ﬂex-hybrids holding the front-end
electronics are directly glued to the silicon sensor. A bus tapeunderneath the detectors carries the required lines for control andreadout of the digital signals [2].
Based on the experience of the current ATLAS Semiconductor
Tracker (SCT), an alternative approach to that of the stave is being
investigated. A double-sided silicon strip-module is proposed as
the minimal modular unit to be assembled into larger structures.
A local support structure for 12 modules enabling full coverage inboth f and Z for the barrel region is being developed.

2. Module design
 Corresponding author.

E-mail address: Sergio.Gonzalez.Sevilla@cern.ch (S. Gonzalez-Sevilla).
0168-9002/$ - see front matter & 2010 Elsevier B.V. All rights reserved.
doi:10.1016/j.nima.2010.04.092

The double-sided module proposed for the short-strip regionof the upgraded ID is largely inspired in the current (barrel) SCT

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module. It consists of (see Fig. 1) two silicon microstrip sensors
glued to a Thermo-Pyrolitical-Graphite (TPG) baseboard, fourbridged-hybrids (each holding two rows of 10 front-end ASICS)
located in pairs on both sides, four AlN facings and six washers(two for precision mounting and four screws). The prototype
detectors [3,4] are  10  10 cm2 single-sided n-on-p detectors,
with 1280 channels and 74:5 mm strip-pitch. The sensor integrates
axial and stereo strips in the same wafer so that the 3D spacepoint (used during the pattern-recognition phase of trackreconstruction) is naturally created by gluing identical but 1801rotated wafers on the top and the bottom side.

The main digital blocks are input register, pipeline, derandomizer buffer, command decoder, readout buffer and datacompression logic. The length of the digital pipeline is 256 bits
or 6:4 ms latency time. A two-clock scheme allows to readout thechip at higher frequencies (80 MHz) than the main BunchCrossing (BC) clock. In the so-called double-clock mode, the output
data rate is 80 Mbps. Additionally, the ABCN allows read/write
operations in all registers, implements Single-Event-Upset (SEU)
detection and token/data passing mechanism.

2.1. Front-end electronics

Hybrids are kapton multi-layer ﬂex circuits holding the FE
ASICS. Two hybrid designs have been successfully developed by
the University of Liverpool [3] and KEK [7]. In both cases, 20
ABCN25 chips are arranged in two columns of 10 (see Fig. 3).

The current prototype of the front-end chip for the short strip
region (ATLAS Binary Chip Next or ABCN) has been produced in
0:250 mm IBM CMOS6 technology (so-called ABCN25) [5,6]. The
ASIC implements a binary readout architecture for 128 channels
and includes both analog and digital stages. Fig. 2 shows the block
diagram of the chip.
On the analog side, it comprises preampliﬁcation, shaping anddifferential discrimination. A serial regulator can provide theanalog voltage from a unique power source and two types ofshunt-regulators allow to test different powering schemes. The
ASIC has been designed to work with either positive or negative
signal polarities decoupling the front-end (FE) from the chosensensor technology.

Hybrids

2.2. Hybrid development

AlN facing
Washers

ABCN FE chips

Silicon sensor

Fig. 3. Picture of a fully populated KEK hybrid.

Fig. 1. Double-sided silicon micro-strip module concept.

Fig. 2. Block diagram of the ABCN25 front-end chip.

Fig. 4. Layout of the KEK hybrid. The four circuit layers are labelled L1 (top) to L4(bottom).

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The ABCN ASIC has an internal calibration circuit which allows
the simulation of a hit in a strip by the injection of test charges of
selectable amplitude (up to 10.2 fC equivalent charge). An
individual threshold correction per channel is implemented witha 5-bit DAC (TrimDAC) in order to compensate for possible
deviations in the threshold offsets, optimizing the uniformity
across the chip. The range of the TrimDAC is set by three bits inthe conﬁguration register, with 32 available steps within a given
range value.
After setting the optimum value of the delay between theinjection pulse with respect to the clock signal for each chip, a

103<μ> = 168.30 mV
σ = 0.90 mV

Entries / 1.1 mV

In the case of the KEK design, the hybrid is composed of two
double-sided ﬂexible polyamide sheets with four circuit layers(see Fig. 4). Each polyamide sheet is 25 mm thick with a 12 mm
thick laminated Cu layer on both surfaces. L1 includes the main
circuit lines with redundancy lines incorporated in L2. L3 and L4
are intended for power distribution and grounding, respectively. A
0.8 mm pitch miniature connector is mounted at one end of thecircuit layers for routing the LVDS signals.
A 400  100 mm2 carbon–carbon (CC) sheet underneath theﬂex circuit is designed to bridge over the silicon sensor avoiding
any interference with the detector surface. The CC bridge, with alarge thermal conductivity of 1400 W/m K, transfers the heatgenerated by the readout chips to the heat sink located at thebridge legs. The hybrid dimensions are 136 mm  28.0mm  0.260 mm, with a total weight (excluding electrical components) of 4.25 g, equivalent to 0.00425 X0 radiation lengths.

3. DAQ and ﬁrst electrical results
The Data Acquisition (DAQ) system used in this paper is
ABCNIDAQ [8], based on commercial components from National
Instruments (NI) and specially developed for testing ABCN chips.
The well-known SCTDAQ system [9], used for the characterizationof SCT modules (equipped with the ABCD3TA chips [10]) was also
adapted for ABCN and is being used by other groups [2].
ABCNIDAQ uses the high-speed (200/400 MHz in single/double
data-rate mode) NI PCI/PXI 6562 card, with 16 digital channels forinterfacing LVDS signals. The software has been written in
LabVIEW, with an object-oriented design and chip conﬁguration
parameters stored in XML ﬁles. Scripted-generation and multirecord acquisition are used to speed-up the data transfer.

S99<μ> = 149.29 mV

102

σ = 6.12 mV

10
100

120

140
160
Threshold (mV)

180

200

Fig. 6. Distribution of vt50 threshold points before trimming (dashed histogram)and after trimming (empty histogram) for all channels in one hybrid column. The
mean /mS and sigma s from a Gaussian ﬁt to each distribution are also shown.

1
M0

S1

S2

S3

S4

S5

S6

S7

S8

E9

0.9
0.8
0.7

160

0.6
0.5

140

0.4

Occupancy

Threshold (mV)

180

0.3

120

0.2
100

0.1
0

200

400

600

800

1000

1200

0

Channel number
1
200

M0

S1

S2

S3

S4

S5

S6

S7

S8

E9

0.8

180

0.7
0.6

160

0.5
140

0.4

Occupancy

Threshold (mV)

0.9

0.3

120

0.2
0.1

100
0

200

400

600

800

1000

1200

0

Channel number
Fig. 5. Threshold scan for a 1.5 fC input charge before trimming (top) and after trimming (bottom). Only results from one column of 10 chips (see Fig. 3) are shown.

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trimming procedure to correct the deviations of each channel
threshold offset is performed. Fig. 5 shows the results of athreshold scan in a fully populated bare hybrid before and after
trimming. For a given input charge (1.5 fC in this case), thedifferential threshold is varied, a certain number of triggers aresent and the occupancy in each channel is computed. All chips
have been trimmed to the same range, resulting in a very uniform
distribution across all channels.
From the projection of the occupancy plots to the thresholdaxis, the threshold corresponding to 50% occupancy is obtainedfor each channel (so-called vt50 point). Fig. 6 shows the
distribution of vt50 points for all channels of one column ofbare hybrid before and after the trimming procedure. The
threshold spread is reduced from  6:1 to  0:9 mV.
By performing threshold scans for several input charges, thegain and noise at the discrminator input can be determined(three-point gain scan). Fig. 7 shows the resulting distributions ofgain (mV/fC), offset (mV), output noise (mV) and corresponding
input noise (Equivalent Noise Charge or ENC) as a function ofchannel number. The results show an excellent agreement withthe gain speciﬁcation of 100 mV/fC and the estimated noise valueof  400 ENC for the ABCN chip.
The hybrids have also been tested in double-clock mode, withthe slow 40 MHz BC clock signal being generated on one of theoutput channels of the 6562 card. No signiﬁcant differences interms of analog performance have been observed.

4. Thermal simulations
Thermal performance is a key aspect of the module design
since the silicon sensors are affected by radiation. Radiation

140
Gain (mV/fC)

120
100
80
60
40
20

Offset (mV)

0
0

200

400

600
Channel number

800

1000

1200

0

200

400

600
Channel number

800

1000

1200

0

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Channel number

800

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1200

0

200

400

600
Channel number

800

1000

1200

40
35
30
25
20
15
10
5
0

Output noise (mV)

30
25
20
15
10
5

Input noise (ENC)

0

1000
900
800
700
600
500
400
300
200
100
0

Fig. 7. From top to bottom, distribution of gain, threshold offset, output and input noise from a three-point gain scan for 1.0, 1.5 and 2.0 fC input charges.

S. Gonzalez-Sevilla et al. / Nuclear Instruments and Methods in Physics Research A 636 (2011) S97–S103

damage in silicon detectors can be monitored by measuring theleakage current as it is linearly proportional to the ﬂuence and is
exponentially proportional to temperature [11]. If a power
balance is not maintained between the active cooling and heating
components, thermal runaway may occur. Detailed simulations
based on Finite Element Analysis (FEA) were performed
with ABAQUS [12] in order to study the thermal performanceof the module design. Fig. 8 shows the predicted temperature
distribution on a module for a chip power of 0.15 W and a coolingtemperature of
30 1C The maximum unpowered silicontemperature would be in this case  22 3 C.
The runaway is an analytic extrapolation of the maximum
silicon temperature that is deﬁned for the silicon power density at
0 1C. Fig. 9 shows the predicted runaway point as a function of thesilicon sensor power density and different scenarios for theS101

convection temperature. The detector power density expected at
the sLHC ﬂuence is also quoted. A thermal grease conductivity of
0.8 W/m2 K was taken into account in the simulation. This low
mass module design is shown to be satisfactory, the safety margin
is approximately a factor 4 to the runaway point.

5. Module assembly and testing
The assembly sequence of a single module can be splitted into
four main stages:

 assembly of the TPG baseboard and AlN facings;
 assembly of sensors to baseboard and washers;
 assembly of top-side hybrids; and assembly of bottom-side hybrids.
Since the module program for KEK and Geneva is focusing on
producing several module prototypes to prove their functionality
and to study their electrical and thermal performances, themechanical precision in the module assembly is not a primarytarget. At this stage, the sensors will be positioned from thedetector edges to the jig alignment pins. Fig. 10 shows some of thejigs already produced for the module assembly. Once the glue is
cured, the module is transferred for bonding.
A module interface board (MAB) has been designed andproduced to allow the testing of a full module equipped withfour hybrids (80 ABCN chips). The MAB holds several LVDS data/
clock distributors to fanout clock and command signals to the FEs.
Eight channels of the DAQ system are used for data acquisition(two lines per hybrid). Static signals are set by means of a DIP
switch. The information from each of the four NTC thermistors is
also available for temperature monitoring.
Fig. 11 shows a view of the four-module test box equippedwith four double-sided silicon micro-strip modules andcorresponding MAB cards. A common cooling pipe passing
through the individual module cooling-plates will dissipate theheat generated. A ﬂex-extender is used to surpass the aluminum
frame to route the signals between the hybrids and the readoutcards. A 4.2 mm stainless-steel pipe is intended to be used with
C3F8 cooling, but can be adapted for other options (e.g. CO2).

Fig. 8. Temperature distribution on the module based on FEA thermal simulations.
The minimum and maximum values in the temperature scale are
30 and21.7 1C, respectively.

Fig. 9. Simulation results for the thermal runaway for the module concept.

Fig. 10. Jigs for detector and AlN facings assembly (top) and hybrid positioning(bottom).

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hybrid kapton-flex
captive nut
kapton-flex
extenderModule adaptor
board

4.2 mm SS pipecooling plate
4-module test-frameFig. 11. View of the four-module test-box.

6. Local support structure
A local support (see Fig. 12) able to hold 12 modules has beendeveloped. The local structure allows the end insertion of the
support into the overall structure (e.g. barrel cylinders). The end
insertion concept has been fully adopted for either stave ofmodule concepts because of its ﬂexibility for integration,commissioning and rework. A demonstrator of the support has
been constructed, showing the feasibility of assembly, precision
mounting and insertion/integration to the barrel structure.

7. Irradiations
As part of our R&D program, a module prototype has been built
to be irradiated at the CERN-PS Irradiation facilities during the
October/November 09 irradiation period. Due to limited availability of components for the prototype assembly, the module
consists of one fully qualiﬁed sensor, one mechanical grade
sensor, two fully populated hybrids on one side and two carbonﬁbre bridges on the other side (for mechanical symmetry andstability). Fig. 13 shows a picture of the ﬁnal assembled prototype
module.
The total irradiation dose will be  4  1014 neq=cm2 . The
beam proﬁle has a size of  1 cm2 , and with the detectors being
almost parallel to the beam, 10 scan points will be needed to fully
cover the sensing area. During the irradiation, the sensors will bebiased and the front-end chips powered and clocked. The hybrid
temperature and the sensor current will be monitored continuously.

Fig. 12. Demonstrator with dummy modules for validation of the end-insertion
concept.

8. Summary
A new design of a double-sided silicon micro-strip module forthe short strip region of the upgraded ATLAS inner tracker has
been presented. Preliminary results on bare hybrids show
excellent performances of the ﬁrst prototype readout ABCN25
ASIC. The R&D program shared between KEK and the University ofGeneva is intended to demonstrate the competitiveness of theFig. 13. Prototype module for irradiation.

S. Gonzalez-Sevilla et al. / Nuclear Instruments and Methods in Physics Research A 636 (2011) S97–S103

proposed design through detailed evaluation of electrical andthermal performances of prototype modules.

Acknowledgments
The authors acknowledge the support of the funding authorities of the collaborating institutes, including the German Federal
Ministry of Education and Research (BMBF), the Japan Grant-inAid for Scientiﬁc Research (A) [Grant 20244038], Japan Priority
Area [Grant 20025007], the Polish Ministry of Science and Higher
Education, the Spanish National Program for Particle Physics[Grant FPA2006-13238-C02-01] and the Swiss National Science
Foundation and the Canton of Geneva.
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