寄附講座：パワーエレクトロニクス寄附研究部門（京三製作所）の 5 年間の活動報告
2024 年 3 月 31 日 寄附講座 河村
1．寄附講座の概要：
寄附研究部門の名称 ： パワーエレクトロニクス寄附研究部門
寄附金額（予定）
総額 100,000 千円（20,000 千円×3+2（延長）年間）
寄附の時期及び期間2019 年 4 月 1 日より 5 年間（2024 年 3 月 31 日まで）
（諸般の事情により、2021 年度は 13,000 千円に減額）
実際の金額は、93,000 千円（5 年間）
担当教員名及び職名
河村 篤男 寄附講座等教員（教授相当：2019 年 4 月 1 日～2024 年 3 月 31 日）
小原秀嶺

寄附講座等教員（講師相当：2019 年 4 月 1 日～2022 年 3 月 31 日）

Hadi Setiadi

寄附講座等教員（講師相当：2022 年 4 月１日～5 月 31 日）

Van-Ling Pham 寄附講座等教員（講師相当：2022 年10 月1 日～2023 年1 月31日）
設置目的
横浜国立大学におけるパワーエレクトロニクス関連の研究を一層活発化すると共に，
横浜国立大学の教育研究の国際化を更に促進し，その成果を社会に発信することにより，社是に則り，社会貢献するため。

2．5年間の活動報告：
2.1．研究関連：（１）2019 年 4 月 1 日～2022 年 3 月 31 日：
科学研究費基盤 S（効率 99.9%級のエネルギー変換が拓く持続的発展可能グリーン社会の実現：（資料 A：最初の 3 年間の寄附講座活動報告資料の資料 1））の研究実施期間の後半の3 年間と寄附講座の前半の 3 年間が重なったので、寄附講座の予算で主として人件費を支払
い、研究費は基盤 S の予算を当てた。提案している高効率 HEECS インバータを用いて、最高変換効率 99.827%±0.009%（1300W 出力時）を実測した。詳しい成果や公表論文など
は（資料 A の資料 1-2）を参照のこと。
（２）2022 年 4 月 1 日～2024 年 3 月 31 日：
最初の３年間で未解決の課題を遂行した結果、(A):さらに高い効率を実測し、効率99.836% ±0.006%( 1300W 出力時)のデータを得た。(B): 太陽光発電機器への応用として、力率制御を検討し、進み力率および、遅れ力率での運転を実証した。詳しい成果や公表論文などは（資料 B:2 年延長分の寄附講座活動報告の資料 1）を参照のこと。
12.2．国際化および社会貢献
国内外の招待講演および国外からの見学者受け入れなどを通じて、国際化及び社会貢献を実施した。前半3年間と後半２年間の詳しい資料は、（資料Aの資料2および、資料Bの資料2）を参照のこと。
2.3 研究成果発表の統計データ
上記の活動をまとめて、発表論文（ジャーナル論文、国際会議論文、口頭発表論文）および招待講演の数を表１に示した。
表１ 寄附講座の研究活動の統計資料
ジャーナル論文

国際会議論文

口頭発表論文招待講演

2019年度

5

3

3

5

2020年度

40

7

3

2021年度

4

1

11

3

2022年度

3

0

3

4

2023年度

2

1

4

7

計

18

5

28

22

3. 自己評価
当初の寄附講座の設置趣旨を十分遂行している。

添付資料一覧

資料A：最初の3年間の寄附講座：パワーエレクトロニクス寄附研究部門の活動の報告資料（全35頁）（構成は以下：）
本文
資料1-1：基盤研究（S）研究進捗評価
資料1-2：基盤研究（S）研究成果報告書
資料2：パワーエレクトロニクス寄附講座の招待講演および海外訪問者
参考資料：寄附講座延長の2年間の研究計画（2022-2023年度）

資料B：延長分２年間の寄附講座：パワーエレクトロニクス寄附研究部門の2年延長分の活動報告（全37頁）（構成は以下：）2

本文
資料1： 発表論文
資料2：パワーエレクトロニクス寄附講座の招待講演および海外訪問者など
添付資料：主要な論文；3編

（以上）

3

資料 A:
最初の 3 年間の寄附講座：パワーエレクトロニクス寄附研究部門（京三製作所）の活動の報告資料(35 頁)のカバーページ

寄附講座：パワーエレクトロニクス寄附研究部門（京三製作所）の活動の報告資料
2022 年 6 月 13 日 寄附講座 河村
1．寄附講座の概要：
寄附研究部門の名称 ： パワーエレクトロニクス寄附研究部門
寄附金額(施設設備等を併せて寄付する場合はその概要)
総額 60,000 千円（20,000 千円×3 年間）
寄附の時期及び期間2019 年 4 月 1 日より 3 年間（2022 年 3 月 31 日まで）
（諸般の事情により、2021 年度は 13,000 千円に減額）
実際の金額は、53,000 千円（3 年間）
担当教員名及び職名
河村 篤男 寄附講座等教員（教授相当）
小原 秀嶺 寄附講座等教員（講師相当）
設置目的
横浜国立大学におけるパワーエレクトロニクス関連の研究を一層活発化すると共に，
横浜国立大学の教育研究の国際化を更に促進し，その成果を社会に発信することにより，社是に則り，社会貢献するため。

2．3年間の活動報告：
2.1．研究関連：科学研究費基盤 S（効率 99.9%級のエネルギー変換が拓く持続的発展可能グ
リーン社会の実現）の実施
中間評価では、A 評価を受けた。（令和 2 年 10 月 8 日資料 1-1）また、最高変換効率 99.83%を実測し、研究プロジェクトは 2022 年 3 月末で終了した。（資料 1-2）なお、最終評価は、2022 年度後半の予定
2.2．国際化および社会貢献（資料2）
国内外の招待講演および国外からの見学者受け入れなどを通じて、国際化及び社会貢献を実施した。
３．自己評価当初の寄附講座の設置趣旨を十分遂行している。
参考資料：2022-2023年度の方針
2019-2021年度の寄附講座の枠組みを2年間延長する。研究としては、2022年3月時点(科研基盤S終了時)での未解決課題(変換効率99.90％の実証)を遂行する。(詳細は参考資料)

1

添付資料一覧

資料1-1：基盤研究（S）研究進捗評価
資料1-2：基盤研究（S）研究成果報告書
資料2：パワーエレクトロニクス寄附講座の招待講演および海外訪問者
参考資料：寄附講座延長の2年間の研究計画（2022-2023年度）

2

１版

様

式

Ｃ−１９、Ｆ−１９−１、Ｚ−１９ （共通）

科学研究費助成事業

研究成果報告書
令和

４ 年

５ 月

９ 日現在

機関番号： １２７０１
研究種目： 基盤研究(S)
研究期間： 2017 〜 2021
課題番号： １７Ｈ０６１４７
研究課題名（和文）効率99.9%級のエネルギー変換が拓く持続的発展可能グリーン社会の実現

研究課題名（英文）Realization of Sustainable Green Society Through 99.9% Class Efficiency ElectricPower Conversion
研究代表者
河村

篤男（KAWAMURA, ATSUO）

横浜国立大学・大学院工学研究院・名誉教授

研究者番号：８０１８６１３９
交付決定額（研究期間全体）：（直接経費）

138,000,000 円

研究成果の概要（和文）：5kW級のHEECSインバータにおいて、①損失の内訳を実測する損失分解法（測定精度0.
04％）を提案して、損失の内訳を明らかにした。②測定精度をさらに1桁高めた仮想トランス非同期同一機器損失測定法（VTALSM法）を提案した。③この測定法を用いて、パラメータの最適を行った結果、SiCパワーデバイ
スでは電力変換効率99.827%±0.009%を、GaNパワーデバイスでは、電力変換効率99.817%±0.004%を達成した。
④このインバータ回路の応用として、力率を自由に変えられ、かつ高速応答運転ができる系統連系動作を実現し、さらに三相HEECインバータによる高効率三相モータ駆動を実証した。

研究成果の学術的意義や社会的意義
我が国のエネルギー事情としては、省エネルギー化および再生可能エネルギーの利用が、持続可能な産業の発展に必須である。再生可能エネルギーの安定利用を実現するための基礎となる技術は、電気エネルギーの変換技術である。本プロジェクトでの成果である99.9％級の電力変換器は電力網のどこへでも配置することができるので、電気エネルギーの利用形態が画期的に変化する。その理由は、電気エネルギーの移動に伴う損失が無視できることにより、周波数、振幅、位相、接地といった電力の移動の制約から解放され、さらに損失が小さいので発熱の制約からも解放され、電力変換機器自体を小型化できるためである。
研究成果の概要（英文）：We proposed a loss decomposition method (measurement accuracy: 0.04%) andclarified the breakdown of losses. Furthermore, a virtual transformer based asynchronous loss
measurement method (VTALSM method) was proposed to improve the measurement accuracy by one order ofmagnitude. Using VTASLM method and the proposed HEECS inverter, we optimized various parameters andcontrols and achieved power conversion efficiencies and accuracy of 99.827% ± 0.009% for SiC powerdevices and 99.817% ± 0.004% for GaN power devices. As an application example, we proposed anddemonstrated a fast response of powering and regenerating control of grid connected operation. In
addition, it was demonstrated that the power factor was freely changed. We also demonstrated thebasis of a phase shifter in the power transmission line using the proposed HEECS inverters. As
another application a highly efficient three‑phase motor drive was demonstrated using three phase
HEECS inverter.

研究分野： 電気電子工学
キーワード： 電力変換

高効率インバータ

電力工学

電気機器

※科研費による研究は、研究者の自覚と責任において実施するものです。そのため、研究の実施や研究成果の公表等については、国の要請等に基づくものではなく、その研究成果に関する見解や責任は、研究者個人に帰属します。

１．研究開始当初の背景
東日本大震災後、我が国のエネルギー事情は苦しい状況に置かれ、省エネルギー化を推し進め、再生可能エネルギーの利用を促進することにより、持続可能な産業の発展を促す状況が続いている。再生可能エネルギーの安定利用を実現するための一番基礎となる技術は、電気エネルギーの変換技術である。例えば、直流を異なる電圧に変換するチョッパや直流電力を交流電力へ変換
する数 kW 級のインバータを、99.9％近い電力変換効率で運転できれば、この変換器を電力網のどこへでも配置できるので、電気エネルギーの利用形態が画期的に変化する。現状は効率が高いと言えども従来型の機器（変圧器、変圧器タップチェンジ、メカニカルな開閉器など）と比べて、エネルギーの変換効率が低い（現状の一般的な数 kW 級のインバータの効率は 95～96%程度、電力密度は 1～2kW/ℓ 程度である）ことが障害となっている。本研究では、電力エネルギー網のあり方を画期的に変革するための基礎技術（効率 99.9％級電力変換器）の実証と高効率かつ自由に
電気エネルギーが移動可能な電力配電系実現を明示することを目的とする。その結果、持続発展
可能なグリーン社会が実現される。
２．研究の目的
本研究では、電力エネルギー網のあり方を画期的に変革するための基礎技術（効率 99.9％級電力変換器）の実証と高効率かつ自由に電気エネルギーが移動可能な電力配電系実現を明示することを目的とする。
具体的には、５kW 級の電力変換器（インバータ）において、変換効率 99.9％に近い効率が実現可能であることを実証し、それを用いて電力配電ネットワークに分散電源を自由に配置できることを実証する。
第一段階では、効率 99.9％級の単相インバータ、第二段階では、効率 99.9％級の三相インバータの実現を実証する。第三段階では、このインバータで太陽光発電システムの高速潮流制御が可能なことを示す。第四段階では、このインバータを用いて低圧系の複数の分散電源（電気自動車バッテリ（V2G）、太陽光発電システム）の高効率連携運転を実証し、超高効率インバータで連系したマイクログリッドが、省エネかつ安定に電圧制御が可能なことを実証する。再生可能エネルギーなど時間変動の大きいエネ
ルギーの有効利用のための各種問題が解決される。
３．研究の方法
本研究では、電力配電網において自由なエネルギー移動を可能とするための効率 99.9％級の電力変換器の実現とその運用に関して、研究目的を５つの具体的な研究計画に分類し、逐次推進する。また、電気機器学、制御工学から電力工学の分野に精通した研究分担者と有機的に連携しながら、研究を効率的かつ効果的に推進する。平成 29 年度では、変換効率 99.9％級のインバータを具体化し、試作機 1 号機を製作する。平成 30 年度は三相インバータで効率 99.9％を実証する。平成 31 年度は高効率インバータで系統連系動作を確認する。令和 2 年度は、低圧系マイクログリッドにおいて、変動の激しい複数の分散電源のパワーと電圧の制御が高速に実現できることを実証する。令和 3 年度は、高効率電力変換により電力エネルギー網の構成を変革できることを示す。
具体的には、５年間の研究期間において、次のＡからＥまでの５つの研究計画に分類し、並列して段階的に研究を遂行することで、研究目的を確実に達成する。
研究計画Ａ：変換効率 99.9％級の 5kW 単相インバータの実現
研究計画Ｂ：変換効率 99.9％級の 8kW 三相インバータの実現
研究計画Ｃ：この変換器に適した系統連系動作の高速応答技術の確立
研究計画Ｄ：低圧系マイクログリッドでの実証実験
研究計画Ｅ：電気エネルギー配電網の改革の指針

４．研究成果
4.1 HEECS インバータの基本回路と基本動作提案する高効率インバータの基本回路と代表的な動作波形は図 1 に示した通りで、これはHEECS インバータと呼ばれている。3 レベルチョッパと折り返し回路の組み合わせによって、スイッ
チング損失と導通損失のトレードオフをできるだけ切り分けて設計でき、さらにフィルタは DC フィルタで済むので、出力波形は歪の少ない正弦波にできる特徴がある。試験装置の外観は図 2 に示した。

E2

E1

S4
S2

S3

L

vsw
S1

Vsw

iL

C

S7

S5

vdc

Vdc

Load

S6 vacS8

VacFig. 1 Two battery HEECS inverter.

図 1 HEECS インバータ回路（左）と代表的な実測波形（右）図 2 測定器を含む実験装置の外観

4.2 測定精度向上と実測した最大電力変換効率
4.2.1 損失分解法：
精度よく損失を測定する手法として、個別に全損失を測定する損失分解法を提案した。すべての要素の損失を測定するために、数多くの測定が必要になる。具体的には、1 動作点の効率を求めるために、スイッチングデバイスのスイッチング損および導通損など 9 種類（総測定数 500 点程度）のデータを測定し、各種演算して計算した。その結果、精度は±0.04％(従来法では、±0.36％)となることがわかり、効率としては 2.2kW 出力時に99.71％となった。
4.2.2 仮想トランス非同期同一機器損失測定法（VTALSM 法）：
効率が 99.9％に近付くと、さらに測定精度の良い損失測定法が求められる。図 3 に示すように、測定機器は 1 組だけ使用して、インバータの力行と回生の動作点で電力を測定することにより、インバータの力行と回生の損失を高精度で測定する手法を提案した。さらに測定精度の式を導出し、測定精度およびその誤差成分も求めた。この測定法の特徴は、①電力測定器の同一電力（例えば、力行運転時）の差電力測定が高精度に行えることを利用する点、②測定系は被試験機器と 1 組の測定器で構成できるので、測定は力行と回生を非同期で行えること、③測定精度の理論式が導出できたので、測定データごとに測定精度が求まること、④力行と回生の平均効率（平均損失）が求まること、などである。図 4（上）は測定効率の例であり、図 4（下）はその測定精度である。
4.2.3 パラメータ最適化による最大効率の追求：
この測定法を使って、各種パラメータの最適化を行い、損失の最小化を検討した。自由度を基
本仕様、前提条件、準仕様パラメータ、自由パラ
メータに分類して最適化を行った。

図4
図 3 VTASLM 測定系(上:力行、下:回生)

VTASLM 法による変換効率（上）とその測定精度（下）Average efficiency
Average efficiency (%)

99.83099.82899.82699.82499.82299.820
1000

1100

1200

1300

1400

1500

1600

1700

output P2m(W)図5SiC HEECS インバータの写真

4.2.3(1) SiC パワーデバイスでの最大効率：
工夫したパラメータは、パワーデバイスの選定、LC の選定、E1E2 電圧の配分比、ゲートド
ライバ回路、力行回生の電力制御、電流セン

図6

SiC HEECS インバータの最高効率測定
データ（最大効率 99.827%±0.009%）

Average efficiency
99.820

Average efficiency (%)

99.81999.81899.81799.81699.81599.81499.81399.81299.81199.810
1400

1500

1600

1700

1800

1900

2000

Output P2m (W)

図8
図7

定データ（最大効率 99.817%±0.004%）

GaN HEECS インバータの写真

最大効率（％）達成（公表時）の変遷
変換効率(%)

100.00(b)損失分解法

99.80(d)最適化

99.60(c)VTASLM

99.40
99.20
(a)直接法

99.00
2018

2019

2020

2021

2022

2023

年・月

図9

最大効率測定値の変遷図

測定精度(%)

測定精度（％）の時系列
10.1(a)直接法(b)損失分解法(c)VTASLM

0.01
0.001
2018

2019

2020

2021

2022

2023

年・月

図 10

GaN HEECS インバータの最高効率測

効率の測定精度の変遷図

サレス制御、PCB 基板の設計などである。その回路
基板は図 5 に示した。最大電力変換効率は図 6 に示したように、出力 1300W の時に 99.827%±0.009%を実測した。
（測定精度の図はスペースの制約で省略）
4.2.3(2) GaN パワーデバイスでの最大効率：工夫したパラメータは、前節の項目以外に、①GaN ベ
アチップの直接 PCB 配線、②ハイサイドとローサイドのデバイスのスイッチの無駄時間を負荷電流に依存した可変デッドタイム制御を実装した。特に、浮遊インダクタンスを低減するために、
図 7 に示したように、リフローという手法によりチップを実装した基盤を試作した。測定した
効率は、図 8 に示したように、出力 1800W の時に 99.817%±0.004%となった。（測定精度の図はスペースの制約で省略）
4.2.4. 最大効率および測定精度の変遷：本報告者のグループが達成したデータを図 9 および図10 に示した。目標値である効率 99.9％へ向かって向上しているが、本プロジェクト終了時では99.827％が最大となった。2022 年 3 月の時点での論文サーベイによると、最大効率の文献調査結
果は、図 11 となり、最大効率も測定精度も世界最高値と思われる。

Efficiency(%)
100.0
(8,9)

99.8
(7)

(1)

99.6

(4) (5)

99.4

The Barheightin the left
graph showsa range ofaccuracy.

(3)

(6)
(2)

99.2

1

10
Output power（kW)

図 12 HEECS インバータの系統連系の結線図
1004.3 2 種類の応用検討
4.3.1.系統連系インバータとしての力率制御：
図 11 インバータ最大効率の文献比較
HEECS インバータを系統連系に用いると図 12（番号は文献を意味する。1,7,8,9 が本報告者のグループ）のような結線図となる。デッドビート制御に基づく電流制御により、電力の力行から回生への変化は数 ms で実現される。この代表的な実験過渡波形を図 13 に示した。この図では、5ms で力行から回生へ急変している。この制御には、高速な過渡現象の制御と電力の制御が実装されている。また、力率が 1 以外でも動作する制御を考案して実装した。系統から見て遅れ力率動作（インバータから見て進み力率運転）は分散電源による受電端子電圧抑制の観点から重要な要求性能となる。提案制御による端子電圧抑制機能も確認した。さらに、3 相インバータを提案し、系統連系動作を行い、回生や力行動作が実現できることも実証したので、位相器としても動作できる。

図 13 力行から回生への高速制御波形（青：連系電流、赤：インバータ電圧、緑：電力指令値）

図 14

HEECS 三相 イ ンバ ータ に よ る
モータ駆動系の結線図

4.3.2.三相 HEECS インバータによるモータ駆動：
図 14 に示した新しい回路（三相インバータ）を提案した。特徴は、図１に示した LC フィル
タが必要ないことである。誘導機を駆動する装置を試作して、このインバータの高効率駆動の測定データ（99.52%）を取得した。
4.4.まとめ①損失分解法（測定精度 0.04％）を提案して、損失の内訳を明らかにした。さらに、測定精度を1 桁高めた仮想トランス非同期同一機器損失測定法（VTALSM 法）を提案した。
②この測定法を用いて、各種パラメータや制御の最適を行った結果、SiC パワーデバイスでは電力変換効率 99.827%±0.009%を、
GaN パワーデバイスでは、効率 99.817%±0.004%を達成した。
③応用として、系統連系時には高速応答を示す制御を提案し実証した。さらに、力率を自由に制御できる系統連系動作を確認した。さらに、3 相 HEECS インバータを提案し、系統連系動作を確認した。
④三相 HEECS インバータにより三相モータ駆動が高効率で実現できることを実証した。
⑤高効率で自由に電気エネルギーが移動可能な電力配電系実現の基礎（位相器）を実証した。
以上の結果を数行で要約する。電気エネルギーの形態を DC から AC へ変換するインバータにおいて、理学的な見地から損失最小化に挑戦した結果、現状の技術では、効率 99.827％±0.009％
が達成でき、2 種類の応用例を実証した。このような技術が実用化されれば、再生可能エネルギーなどの分散電源を多用した電力の配電システムの性能を大きく変えることができ、カーボン
ニュートラルな社会（持続的発展可能グリーン社会）が実現できる。

５．主な発表論文等〔雑誌論文〕 計21件（うち査読付論文 21件／うち国際共著 2件／うちオープンアクセス
１．著者名
Kawamura Atsuo、Nasu Yoshiki、Miguchi Yasuhiko、Setiadi Hadi、Obara Hidemine

21件）
４．巻
11

２．論文標題
５．発行年
Proposal of Virtual Transformer‑based Back‑to‑Back Asynchronous Loss Measurement using a Single
2022年
Set of Measurement Instruments for One Inverter and Experimental Verification
３．雑誌名
６．最初と最後の頁
IEEJ Journal of Industry Applications
175〜184

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.21008251

査読の有無

オープンアクセス

国際共著

有オープンアクセスとしている（また、その予定である）

−

１．著者名
Kahwa Almachius、Obara Hidemine、Fujimoto Yasutaka

４．巻

２．論文標題Minimization of DC‑Link Capacitance and Improved Operational Performance of a 5‑Level Hybrid
Multilevel DC‑Link Inverter
３．雑誌名IEEE Open Journal of Power Electronics

５．発行年
2022年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1109/OJPEL.2022.3160867

査読の有無

オープンアクセス

国際共著

3

６．最初と最後の頁
182〜196

有

オープンアクセスとしている（また、その予定である）

−

１．著者名
Setiadi Hadi、Obara Hidemine

４．巻

２．論文標題Multilevel Cascaded H‑Bridge Linear Amplifier with Unequal DC Capacitor Voltages Using a DC
Voltage Source
３．雑誌名
IEEJ Journal of Industry Applications

５．発行年
2022年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.21011915

査読の有無

オープンアクセス

国際共著

11

６．最初と最後の頁
522〜530

有

オープンアクセスとしている（また、その予定である）

−

１．著者名
Aboelsoud Hossam、Ikeda Naoya、Tsuji Takao、Hojo Masahide、Okada Naotaka

４．巻

２．論文標題Online voltage control of microgrids with different loading conditions using particle swarm
optimization
３．雑誌名
IEEJ Transactions on Electrical and Electronic Engineering

５．発行年
2022年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1002/tee.23567

査読の有無

オープンアクセス

国際共著
オープンアクセスとしている（また、その予定である）‑

６．最初と最後の頁‑

有−１．著者名Obara Hidemine、Ohno Tatsuki、Kawamura Atsuo

４．巻

２．論文標題Systematization of a Multilevel‑Topology‑Based Linear Amplifier Family for Noiseless DC?ACPower Conversion
３．雑誌名IEEE Access

５．発行年
2021年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1109/ACCESS.2021.3130681

査読の有無

オープンアクセス

国際共著

9

６．最初と最後の頁
159627〜159639

有オープンアクセスとしている（また、その予定である）

−

１．著者名
Obara Hidemine、Ohno Tatsuki、Katayama Masaya、Kawamura Atsuo

４．巻

２．論文標題Flying‑Capacitor Linear Amplifier With Capacitor Voltage Balancing for High‑Efficiency and Low
Distortion
３．雑誌名IEEE Transactions on Industry Applications

５．発行年
2021年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1109/TIA.2020.3034560

査読の有無

オープンアクセス

国際共著

57

６．最初と最後の頁
614〜627

有

オープンアクセスとしている（また、その予定である）

−

１．著者名
４．巻
9
Kosode Yoshiki、Obara Hidemine、Kawamura Atsuo、Hosoyamada Yu、Suenaga Toyoaki、Yuzurihara
Itsuo
２．論文標題
５．発行年
High Performance Transient Response of High/Low Pulse Voltage using Two‑Phase Interleaved DC‑DC
2020年
Buck Converter under Half Sampling Time Deadbeat Control
３．雑誌名
６．最初と最後の頁
IEEJ Journal of Industry Applications
444〜452

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.9.444

査読の有無

オープンアクセス

国際共著

有オープンアクセスとしている（また、その予定である）

−

１．著者名
Kawamura Atsuo、Nakazaki Satoshi、Ito Shogo、Nagai Sakahisa、Obara Hidemine

４．巻

２．論文標題Two‑Battery HEECS Inverter with over 99.7% Efficiency at 2.2kW Output and Measurement Accuracy
Based on Loss Breakdown
３．雑誌名
IEEJ Journal of Industry Applications

５．発行年
2020年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.20001291

査読の有無

オープンアクセス

国際共著
オープンアクセスとしている（また、その予定である）

9

６．最初と最後の頁
663〜673

有−１．著者名
Hosoyamada Yu、Fujimoto Yasutaka、Kawamura Atsuo、Yuzurihara Itsuo

４．巻

２．論文標題Individual Deadbeat Control for Three‑Phase Interleaved Buck DC/DC Converters

５．発行年
2020年

３．雑誌名
IEEE Transactions on Industry Applications

６．最初と最後の頁
5065〜5074

掲載論文のDOI（デジタルオブジェクト識別子）
10.1109/TIA.2020.2998672

査読の有無

オープンアクセス

国際共著

56

有

オープンアクセスとしている（また、その予定である）

−

１．著者名
Tamura Ayataro、Ishibashi Takayuki、Umihara Takuro、Tsuruta Yukinori、Obara Hidemine、Kawamura
Atsuo
２．論文標題Voltage Control of Intermittent Pulse Density Modulation for Two Battery‑operated HEECS
Choppers and its Application for Range Extension of Electric Vehicles
３．雑誌名
IEEJ Journal of Industry Applications

４．巻

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.8.787

査読の有無

オープンアクセス

国際共著

8

５．発行年
2019年
６．最初と最後の頁
787〜794

有

オープンアクセスとしている（また、その予定である）

−

１．著者名
Tsuruta Yukinori、Kawamura Atsuo

４．巻

２．論文標題Realization and Highly Precise Measurement of 50kW HEECS Chopper with 99.5% Efficiency

５．発行年
2019年

３．雑誌名
IEEJ Journal of Industry Applications

６．最初と最後の頁
843〜848

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.8.843

査読の有無

オープンアクセス

国際共著

8

有

オープンアクセスとしている（また、その予定である）

−

１．著者名
Ben‑Brahim Lazhar、Gastli Adel、Yoshino Teruo、Yokoyama Tomoki、Kawamura Atsuo

４．巻

２．論文標題
Review of Medium Voltage High Power Electric Drives

５．発行年
2019年

３．雑誌名
IEEJ Journal of Industry Applications

６．最初と最後の頁
1〜11

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.8.1

査読の有無

オープンアクセス

国際共著
オープンアクセスとしている（また、その予定である）

8

有

該当する

１．著者名Nagai Sakahisa、Oboe Roberto、Shimono Tomoyuki、Kawamura Atsuo

４．巻

２．論文標題Fast Force Control without Force Sensor Using Combination of aaKF and RFOB for In‑circuit Test
with Probing System
３．雑誌名
IEEJ Journal of Industry Applications

５．発行年
2019年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.8.152

査読の有無

オープンアクセス

国際共著

8

６．最初と最後の頁
152〜159

有

オープンアクセスとしている（また、その予定である）

該当する

１．著者名
Abeta Hiroyuki、Obara Hidemine、Kawamura Atsuo

４．巻

２．論文標題Multiple Source Input Isolated DC‑DC Converter with Simple Circuit

５．発行年
2019年

３．雑誌名
IEEJ Transactions on Industry Applications

６．最初と最後の頁
266〜275

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejias.139.266

査読の有無

オープンアクセス

国際共著

139

有

オープンアクセスとしている（また、その予定である）

−

１．著者名
Katayama Masaya、Ohno Tatsuki、Obara Hidemine、Kawamura Atsuo

４．巻

２．論文標題Application of Multi‑Level Converter for Fast Current Control in Small‑Scale DC Power Network

５．発行年
2019年

３．雑誌名
IEEE Transactions on Industry Applications

６．最初と最後の頁
1〜1

掲載論文のDOI（デジタルオブジェクト識別子）
10.1109/TIA.2019.2896839

査読の有無

オープンアクセス

国際共著

55

有

オープンアクセスとしている（また、その予定である）

−

１．著者名
Tamura Ayataro、Ishibashi Takayuki、Kawamura Atsuo

４．巻

２．論文標題EV Range Extender in a Two‑Battery HEECS Chopper‑Based Powertrain

５．発行年
2019年

３．雑誌名
World Electric Vehicle Journal

６．最初と最後の頁
19〜19

掲載論文のDOI（デジタルオブジェクト識別子）
10.3390/wevj10020019

査読の有無

オープンアクセス

国際共著
オープンアクセスとしている（また、その予定である）

10

有

−

１．著者名Liu Ben、Yoshino Teruo、Kawamura Atsuo

４．巻

２．論文標題Seamless Control of Grid‑Connected Inverter during Single Phase Disconnection after Single
Phase Fault in a Weak Grid
３．雑誌名
IEEJ Journal of Industry Applications

５．発行年
2018年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.7.506

査読の有無

オープンアクセス

国際共著

7

６．最初と最後の頁
506〜516

有

オープンアクセスとしている（また、その予定である）
１．著者名
Mohammad Bani.Shamseh, Teruo.Yoshino, Atsuo−
４．巻

Kawamura

65

２．論文標題Current‑Dependent Capacitor Voltage Control (CCVC) of Parallel Autonomous UPS Systems

５．発行年
2018年

３．雑誌名
IEEE Transactions on Industrial Electronics

６．最初と最後の頁
2873‑2882

掲載論文のDOI（デジタルオブジェクト識別子）
10.1109/TIE.2017.2752121

査読の有無

オープンアクセス

国際共著

有オープンアクセスとしている（また、その予定である）

−

１．著者名
Takuya Noguchi、Sakahisa Nagai, Atsuo Kawamura

４．巻

２．論文標題Electromagnetic Linear Actuator providing High Force Density per Unit Area without Position
Sensor as a Tactile Cell
３．雑誌名
IEEJ Journal of Industry Applications

５．発行年
2018年

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.7.259

査読の有無

オープンアクセス

国際共著

7

６．最初と最後の頁
259‑265

有

オープンアクセスとしている（また、その予定である）
１．著者名
Shamseh Mohammad Bani、Yoshino Teruo、Kawamura Atsuo

−
４．巻
6

２．論文標題
５．発行年
Load Current Distribution between Parallel Inverters based on Capacitor Voltage Control for UPS
2017年
Applications
３．雑誌名
６．最初と最後の頁
IEEJ Journal of Industry Applications
258〜267

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.6.258

査読の有無

オープンアクセス

国際共著
オープンアクセスとしている（また、その予定である）

有−１．著者名Mushi Aviti、Nagai Sakahisa、Obara Hidemine、Kawamura Atsuo

４．巻

２．論文標題Fast and Robust Nonlinear Deadbeat Current Control for Boost Converter

５．発行年
2017年

３．雑誌名
IEEJ Journal of Industry Applications

６．最初と最後の頁
311〜319

掲載論文のDOI（デジタルオブジェクト識別子）
10.1541/ieejjia.6.311

査読の有無

オープンアクセス

国際共著
オープンアクセスとしている（また、その予定である）〔学会発表〕 計68件（うち招待講演 13件／うち国際学会 26件）
１．発表者名河村篤男、Hadi Setiadi、味口泰彦、那須祥樹、小原秀嶺

２．発表標題高効率HEECSインバータの損失低減に関する一考察

３．学会等名
電気学会半導体電力変換研究会SPC‑22‑059
４．発表年
2022年
１．発表者名那須祥樹、Hadi Setiadi、味口泰彦、小原秀嶺、河村篤男

２．発表標題2電源HEECS三相インバータによる高効率モータ駆動

３．学会等名
電気学会半導体電力変換研究会SPC‑22‑097
４．発表年
2022年
１．発表者名味口泰彦、Hadi Setiadi、那須祥樹、小原秀嶺、河村篤男

２．発表標題超高効率単相連系インバータ（HEECS)の遅れ力率での運転

３．学会等名
電気学会半導体電力変換研究会SPC‑22‑096
４．発表年
2022年

6

有

−

１．発表者名
Hadi Setiadi, Yoshiki Nasu, Yasuhiko Miguchi, Hidemine Obara, Atsuo. Kawamura

２．発表標題Implementation of GaN‑based HEECS Inverter

３．学会等名IEEJ annual meeting
４．発表年
2022年
１．発表者名河村篤男、Hadi Setiadi、味口泰彦、那須祥樹、小原秀嶺

２．発表標題HEECSインバータの直流電源電圧比に関する最適化の検討

３．学会等名
電気学会全国大会
４．発表年
2022年
１．発表者名那須祥樹、Hadi Setiadi、味口泰彦、小原秀嶺、河村篤男

２．発表標題高効率HEECS三相インバータによる誘導器駆動と実機効率測定

３．学会等名
電気学会全国大会
４．発表年
2022年
１．発表者名味口泰彦、Hadi Setiadi、那須祥樹、小原秀嶺、河村篤男

２．発表標題
デッドビート電流制御を内蔵する電圧制御系の安定性の検証

３．学会等名
電気学会全国大会
４．発表年
2022年

１．発表者名
河村篤男、那須祥樹、味口泰彦、Hadi Setiad、小原秀嶺

２．発表標題仮想トランスに基づくBTB非同期同一機器損失測定法によるインバータの高精度効率測定法の提案と実測例

３．学会等名
電気学会産業応用部門大会
４．発表年
2021年
１．発表者名那須祥樹、味口泰彦、小原秀嶺、河村篤男

２．発表標題2電源HEECSチョッパを利用した高効率三相インバータの実験検証

３．学会等名
電気学会産業応用部門大会
４．発表年
2021年
１．発表者名味口泰彦、Hadi Setiadi、那須祥樹、小原秀嶺、河村篤男

２．発表標題超高効率単相連系インバータ（HEECS)の進み力率での運転

３．学会等名
電気学会産業応用部門大会
４．発表年
2021年
１．発表者名AROU ANYUAT JOHN,TAKAO TSUJI

２．発表標題Co‑ordinated Q‑V/P‑F Priority Control Strategy for PV Smart Inverter‑ Based Autonomous AC Microgrid

３．学会等名
電気学会 電力技術/電力系統技術合同研究会
４．発表年
2021年

１．発表者名
河村篤男、那須祥樹、味口泰、Hadi Setiadi, 小原秀嶺

２．発表標題高効率HEECSインバータの損失の高精度測定法に関する一考察

３．学会等名
電気学会半導体電力変換研究会SPC‑21‑37
４．発表年
2021年
１．発表者名那須祥樹、味口泰、Hadi Setiadi、小原秀嶺、河村篤男

２．発表標題2電源HEECS単相インバータによる回生動作と系統連系応用

３．学会等名
電気学会半導体電力変換研究会SPC‑21‑30
４．発表年
2021年
１．発表者名伊藤正悟、Hadi Setiadi、小原秀嶺、下野誠通、河村篤男

２．発表標題スルーレート制御アクティブゲート駆動を用いた広電流範囲にわたるSiC‑MOSFETターンオフ損失低減の検討

３．学会等名
電気学会半導体電力変換研究会SPC‑21‑33
４．発表年
2021年
１．発表者名Hadi Setiadi, Hidemine Obara, Atsuo. Kawamura

２．発表標題Study on advanced Modular Cascaded Linear Amplifier with Unequal Capacitor Voltage of H‑bridge Cells

３．学会等名IEEJ, Technical meeting on Static Power Conversion, SPC‑21‑34
４．発表年
2021年

１．発表者名
川井久尚, 辻隆男

２．発表標題離島マイクログリッドにおける風力発電のイナーシャ制御のための回転数最適化手法

３．学会等名
電気学会新エネルギ−・環境/高電圧 合同研究会
４．発表年
2021年
１．発表者名香山優太，辻隆男

２．発表標題配電系統のフリッカ抑制のためのSTATCOMの2自由度制御

３．学会等名
電気学会神奈川支所研究発表会，KNG‑21‑016
４．発表年
2021年
１．発表者名Almachius Kahwa, Hidemine Obara, and Yasutaka Fujimoto

２．発表標題̀Analysis and Implementation of a 5‑Level Hybrid Inverter with Reduced Switching Devices Using Phase‑Shifted PWM

３．学会等名IEEE Energy Conversion Congress and Exposition (ECCE)（国際学会）
４．発表年
2021年
１．発表者名河村篤男

２．発表標題電力変換効率99.9％のインバータ３．学会等名日本学術会議‑電気電子工学委員会制御・パワー工学分科会（招待講演）
４．発表年
2021年

１．発表者名
Atsuo Kawamura

２．発表標題
Challenge to 99.9 % efficiency electric power conversion and the applications

３．学会等名IEEE ICPES2021(International Conference on Power and Energy Systems) Keynote Speech（招待講演）（国際学会）
４．発表年
2021年
１．発表者名Atsuo Kawamura

２．発表標題Trend of Very High Efficient DC‑DC and DC‑AC Power Conversion

３．学会等名IEEE AEEEC 2021 (Asian Energy and Electrical Engineering Conference), Keynote Speech(Chengdu, China)（招待講演）（国際学会）
４．発表年
2021年
１．発表者名河村篤男、中崎智志、伊藤正悟、永井栄寿、小原秀嶺

２．発表標題効率99.71％2電源HEECSインバータの高精度効率測定

３．学会等名
電気学会半導体電力変換研究会SPC‑20‑142
４．発表年
2020年
１．発表者名那須祥樹、味口泰彦、小原秀嶺、河村篤男

２．発表標題2電源HEECS単相インバータによる構想潮流制御のシミュレーションによる実現

３．学会等名
電気学会半導体電力変換研究会SPC‑20‑188
４．発表年
2020年

１．発表者名
味口泰彦、那須祥樹、小原秀嶺、河村篤男

２．発表標題超高効率単相連系インバータ（HEECS)の電流制御

３．学会等名
電気学会半導体電力変換研究会SPC‑20‑128
４．発表年
2020年
１．発表者名中﨑智志、那須祥樹、伊藤正悟、永井栄寿、小原秀嶺、河村篤男

２．発表標題2電源HEECSインバータでの変換効率99.7%の実測

３．学会等名
電気学会全国大会
４．発表年
2020年
１．発表者名那須祥生・中崎智志・小原秀嶺・河村篤男

２．発表標題HEECSインバータによる三相モータ駆動のための基礎検討

３．学会等名
電気学会全国大会
４．発表年
2020年
１．発表者名小袖義貴、小原秀嶺、河村篤男、細山田 悠、末永豊昭、譲原逸男

２．発表標題High/Low電圧パルス出力のための二相インターリーブ降圧コンバータにおけるむだ時間補償型の半周期毎電流デッドビート制御

３．学会等名
電気学会全国大会
４．発表年
2020年

１．発表者名
Atsuo Kawamura

２．発表標題
Challenge to 99.9 % efficiency electric power conversion in a few kW power range

３．学会等名IEEE IPEMC‑ECCE‑Asia2020, Keynote Speech( Nanjing China)（招待講演）（国際学会）
４．発表年
2020年
１．発表者名Satoshi Nakazaki, Ito Shogo, Hidemine Obara, Atsuo Kawamura

２．発表標題Discussion on Loss Breakdown of 99.6% Efficiency Two Battery HEECS Inverter

３．学会等名IEEE 21th European Conference on Power Electronics and Application,EPE'19 ECCE Europe（国際会議）（国際学会）
４．発表年
2019年
１．発表者名Yoshiki Kosode, Hidemine Obara, Atsuo Kawamura, Yu Hosoyamada, Itsuo Yuzurihara

２．発表標題Experimental Realization of High Performance Transient Response for Two‑Phase Interleaved DC‑DC Buck Converter using Half
Sampling Time Deadbeat Control

３．学会等名IEEE 45th Annual Conference of the Industrial Electronics Society(IECON)（国際会議）（国際学会）
４．発表年
2019年
１．発表者名Takayuki Ishibashi,Hidemime Obara, Atsuo Kawamura

２．発表標題Proposal of SOC Unbalancing Solution Combined with Flux‑weakening Control for Two‑battery HEECS Chopper‑based EV Powertrain

３．学会等名IEEE IFEEC（国際会議）（国際学会）
４．発表年
2019年

１．発表者名
Sakahisa Nagai and Atsuo Kawamura

２．発表標題Sensorless Position Control for Compact Dual Solenoid Actuator Using Disturbance Observer

３．学会等名IEEE International Conference on Mechatronics（国際学会）
４．発表年
2019年
１．発表者名中崎智志、伊藤正悟、永井栄寿、小原秀嶺、河村篤男

２．発表標題LCフィルタの検討に基づく超高効率インバータの変換効率99.6％の実現

３．学会等名
電気学会全国大会
４．発表年
2019年
１．発表者名伊藤正悟、中崎智志、永井栄寿、小原秀嶺、河村篤男

２．発表標題超高効率電力変換を目指した2つの主回路トポロジーにおける損失の実測比較

３．学会等名
電気学会全国大会
４．発表年
2019年
１．発表者名見山友樹，小原秀嶺，下野誠通，河村篤男

２．発表標題T‑PWAM制御を用いた高効率GaN三相交流インバータの実機による検討

３．学会等名
電気学会全国大会
４．発表年
2019年

１．発表者名
Atsuo Kawamura

２．発表標題
Challenge to 99.9 % efficiency electric power conversion and the applications

３．学会等名IEEE ICRERA2019(International Conference on Renewable Energy Research and Applications), Keynote Speech（招待講演）（国際学
会）
４．発表年
2019年
１．発表者名河村篤男

２．発表標題直列チョッパ方式による自動車の走行距離延伸と変換効率99.9％の電力変換機器実現への挑戦のインパクト３．学会等名第9回スマートビークル研究センターシンポジウム（豊田工大）で招待講演（招待講演）
４．発表年
2019年
１．発表者名河村篤男

２．発表標題電力変換効率99.9％への挑戦とその研究の変遷

３．学会等名永守賞授賞式で招待講演（招待講演）
４．発表年
2019年
１．発表者名Atsuo Kawamura

２．発表標題
Challenge to 99.9 % electric power conversion efficiency

３．学会等名IEEJ SAMCON 2019（International Workshop on Sensing, Actuating, Motion Control, and Optimization）, Keynote Speech（招待講演）（国際学会）
４．発表年
2019年

１．発表者名
河村篤男

２．発表標題超高効率なDC‑DCおよびDC‑AC電力変換器に関する調査

３．学会等名
電気学会電力変換・モータドライブ研究会で招待講演（招待講演）
４．発表年
2019年
１．発表者名河村篤男

２．発表標題電力変換効率99.9％への挑戦

３．学会等名第49回 YJC実装技術セミナー（招待講演）
４．発表年
2019年
１．発表者名Ayataro Tamura, Takayuki Ishibashi, Takuro Umihara, Yukinori Tsuruta, Hidemine Obara, and Atsuo Kawamura

２．発表標題High efficiency chopper based EV range extender

３．学会等名The 31st International Electric Vehicles Symposium & Exhibition (EVS 31) & International Electric Vehicle Technology
Conference 2018（国際学会）
４．発表年
2018年
１．発表者名Hidemine Obara, Tatsuki Ohno, and Atsuo Kawamura

２．発表標題Multi‑level topology based linear amplifier family for realization of noise‑less inverters

３．学会等名The 2018 International Power Electronics conference (IPEC2018)（国際学会）
４．発表年
2018年

１．発表者名
Sakahisa Nagai, Atsuo Kawmaura

２．発表標題Position Sensorless Position Control for Dual Solenoid Actuator

３．学会等名The 2018 International Power Electronics conference(IPEC2018)（国際学会）
４．発表年
2018年
１．発表者名Sakahisa Nagai, Satoshi Nakazaki, Ito Shogo, Hidemine Obara, Atsuo Kawamura,

２．発表標題Full‑wave rectified waveform generation using dead‑beat voltage control for DC‑DC buck converters to realize high efficiency
inverter

３．学会等名20th European Conference on Power Electronics and Application(EPE2018)（国際学会）
４．発表年
2018年
１．発表者名Ayataro Tamura, Takayuki Ishibashi, Takuro Umihara, Yukinori Tsuruta, Hidemine Obara, and Atsuo Kawamura

２．発表標題Intermittent Pulse Density Modulation of Two Battery HEECS Chopper for Electric Vehicles

３．学会等名The 44th Annual Conference of the IEEE Industrial Electronics Society（国際学会）
４．発表年
2018年
１．発表者名Takuro Umihara, Ayataro Tamura, Takayuki Ishibashi, and Atsuo Kawamura

２．発表標題Proposal of Soft SOC Balancing Method to Two Battery HEECS chopper used for EV power train

３．学会等名The 44th Annual Conference of the IEEE Industrial Electronics Society(IECON2018)（国際学会）
４．発表年
2018年

１．発表者名
Sakahisa Nagai and Atsuo Kawamura

２．発表標題Sensorless Position Estimation with Thermal Compensation for Compact Dual Solenoid Actuator

３．学会等名The 44th Annual Conference of the IEEE Industrial Electronics Society(IECON2018)（国際学会）
４．発表年
2018年
１．発表者名Ben liu, Teruo Yoshino, Atsuo Kawamura

２．発表標題A Novel Control Method of Grid‑Connected Inverter during Multiple‑Phase Disconnection of Double Circuit Transmission Lineafter Multiple‑Phase Fault in a Weak Grid

３．学会等名IEEE PEAC 2018（国際学会）
４．発表年
2018年
１．発表者名劉 奔，吉野 輝夫，河村 篤男

２．発表標題Seamless Control of Grid‑Connected Inverter during Multiple Phases Disconnection of Double Circuit Transmission Line in a
Weak Grid

３．学会等名平成30年電気学会産業応用部門大会
４．発表年
2018年
１．発表者名大野 達樹，片山 正也，小原 秀嶺，河村 篤男

２．発表標題フライングキャパシタ形線形増幅回路におけるキャパシタ電圧バランス制御の基礎検討

３．学会等名平成30年電気学会産業応用部門大会
４．発表年
2018年

１．発表者名
田村 文太郎，石橋 隆之，河村 篤男

２．発表標題2電源HEECS チョッパへの間欠PDM制御導入による出力電圧制御の周波数特性

３．学会等名平成30年電気学会産業応用部門大会
４．発表年
2018年
１．発表者名Yue Zhuo, Takao Tsuji

２．発表標題
Analysis of Load Margin Improvement in Power System with Photovoltaics Considering PCS Capacity by Particle Swarm
Optimization

３．学会等名International Conference on Electrical Engineering (ICEE)（国際学会）
４．発表年
2018年
１．発表者名Yu Hosoyamada, Itsuo Yuzurihara, Yasutaka Fujimoto, and Atsuo Kawamura

２．発表標題High‑Speed High/Low Pulse Operation by Deadbeat Control Considering
Converter

Control Delay in Three‑Phase Interleaved DC/DC

３．学会等名IEEE Energy Conversion Congress and Exposition (ECCE2018)（国際学会）
４．発表年
2018年
１．発表者名伊藤 正悟，永井 栄寿，中﨑 智志，小原 秀嶺，河村 篤男

２．発表標題インバータの超高効率化に向けた主回路およびフィルタの効率に関する実験的検討

３．学会等名
電気学会全国大会
４．発表年
2018年

１．発表者名
中﨑 智志，永井 栄寿，伊藤 正悟，小原 秀嶺，河村 篤男

２．発表標題DC‑DCコンバータにおける全波整流出力波形生成のためのデッドビート電圧制御の実験検討

３．学会等名
電気学会全国大会
４．発表年
2018年
１．発表者名海原 拓朗，田村 文太郎，石橋 隆之，河村 篤男

２．発表標題2電源HEECSパワートレインにおけるSoCアンバランス問題解決に向けた制御手法の提案

３．学会等名
電気学会全国大会
４．発表年
2018年
１．発表者名石橋 隆之，田村 文太郎，海原 拓朗，弦田 幸憲，河村 篤男

２．発表標題2電源HEECSチョッパを用いたEVテストベンチでのモード走行効率測定

３．学会等名
電気学会全国大会
４．発表年
2018年
１．発表者名Atsuo Kawamura

２．発表標題Activities of IEEJ and IEEJ/IAS and research on High efficiency energy conversion on mobile vehicles

３．学会等名University Workshop at Chonnam National University and KERI（招待講演）
４．発表年
2018年

１．発表者名
Ayataro Tamura, Koji Kobayashi, Yukinori Tsuruta, Kazuaki Kojima, Hidemine Obara, and Atsuo Kawamura

２．発表標題Range Extension of Electric Vehicles by Two Battery HEECS Chopper based Power Train３．学会等名IEEE ECCE2017（国際学会）
４．発表年
2017年
１．発表者名Masaya Katayama, Tatsuki Ohno, Hidemine Obara, and Atsuo Kawamura:

２．発表標題Study on Application of Multi‑Level Converter to Realize Fast Current Control in DC Micro‑Grid with Extremely Low ImpedanceInterconnections

３．学会等名IEEE International Conference on Power Electronics and Drive Systems(PEDS)（国際学会）
４．発表年
2017年
１．発表者名Tatsuki Ohno, Masaya Katayama, Hidemine Obara, and Atsuo Kawamura

２．発表標題Flying‑Capacitor Linear Amplifier to Realize Both High‑Efficiency and Low Distortion for Power Conversion Applications
Requiring High‑Quality Waveforms

３．学会等名IEEE International Conference on Power Electronics and Drive Systems(PEDS)（国際学会）
４．発表年
2017年
１．発表者名Sakahisa Nagai, Robert Oboe, Tomoyuki Shimono, and Atsuo Kawamura

２．発表標題Fast Force Control Using Acceleration‑aided Kalman Filter and Reaction Force Observer for Probing Systems

３．学会等名IEEE IECON2017（国際学会）
４．発表年
2017年

１．発表者名
片山 正也，大野 達樹，小原 秀嶺，河村 篤男

２．発表標題マルチレベルコンバータによる直流マイクログリッドの擾乱抑制効果に関する基礎検討

３．学会等名平成29年電気学会産業応用部門大会
４．発表年
2017年
１．発表者名大野 達樹，片山 正也，小原 秀嶺，河村 篤男

２．発表標題フライングキャパシタ形線形増幅回路の実験検証

３．学会等名平成29年電気学会産業応用部門大会
４．発表年
2017年
１．発表者名島津 晃大，下野 誠通，河村 篤男

２．発表標題
リニアモータ用磁気浮上形軸受の基礎研究

３．学会等名平成29年電気学会産業応用部門大会
４．発表年
2017年
１．発表者名Atsuo Kawamura

２．発表標題High Efficiency energy Conversion for mobile vehicles

３．学会等名IEEE Workshop on Emerging technology of transportation electrification（招待講演）（国際学会）
４．発表年
2017年

１．発表者名
Atsuo Kawamura

２．発表標題High Efficient Energy Conversion for Mobile Vehicles

３．学会等名
Korean Institute of Power Electronics Annual Meeting（招待講演）（国際学会）
４．発表年
2017年
〔図書〕

計0件

〔出願〕 計1件
産業財産権の名称
多段直流チョッパ回路、および電力変換装置

産業財産権の種類、番号
特許、2017‑126044
〔取得〕

発明者
河村篤男、弦田幸
憲、小原秀嶺

権利者
横浜国立大学出願年
2017年

国内・外国の別
国内

計0件

〔その他〕
科研費基盤S：効率99.9％級のエネルギー変換が拓く持続可能グリーン社会の実現
http://www.kawalab.dnj.ynu.ac.jp/j̲page/kaken.html

６．研究組織氏名（ローマ字氏名）（研究者番号）

辻隆男

所属研究機関・部局・職（機関番号）
横浜国立大学・大学院工学研究院・准教授

研
究
分 (Tsuji Takao)
担者(00432873)
小原 秀嶺(12701)横浜国立大学・大学院工学研究院・准教授

研
究
分 (Obara Hidemine)
担者(50772787)(12701)

備考６．研究組織（つづき）
氏名（ローマ字氏名）（研究者番号）

藤本康孝

所属研究機関・部局・職（機関番号）

備考

横浜国立大学・大学院工学研究院・教授

研
究分 (fujimoto Yasutaka)
担者(60313475)
下野 誠通(12701)横浜国立大学・大学院工学研究院・准教授

研
究
分 (Shimono Tomoyuki)
担者(90513292)(12701)

７．科研費を使用して開催した国際研究集会〔国際研究集会〕 計1件
国際研究集会
Kakenhi final year workshop (科研費最終年度成果国際報告会)

開催年
2022年〜2022年

８．本研究に関連して実施した国際共同研究の実施状況
共同研究相手国

相手方研究機関

中国

清華大学

ノルウェー

SINTEFエネルギー研究所

寄附講座：パワーエレクトロニクス寄附講座の招待講演および海外訪問者など
2022 年 3 月 31 日現在 寄附講座 河村
1．河村の招待講演など(1) 河村篤男，「電力変換効率 99.9％への挑戦」、第 49 回 YJC 実装技術セミナー，招待講演、2019 年 6 月 11 日、横浜
(2)河村篤男，「電力変換効率 99.9％への挑戦とその研究の変遷」、永守賞授賞式で招待講
演、2019 年 9 月 8 日，京都
(3) 河村篤男，「直列チョッパ方式による自動車の走行距離延伸と変換効率 99.9％の電力
変換機器実現への挑戦のインパクト」、第 9 回スマートビークル研究センターシンポジウム（豊田工大）で招待講演，2019 年 10 月 24 日、名古屋(4) Atsuo Kawamura, ”Challenge to 99.9 % efficiency electric power conversion and theapplications”、 IEEE ICRERA2019(International Conference on Renewable Energy Research andApplications), Keynote Speaker at Plenary session, November 4, 2019 (Romania)(5) 河村篤男，「電気自動車の研究を通しての人材育成の事例紹介と自分で考える基礎俯瞰
教育の重要性」、2020 パワエレフォーラム，日本パワーエレクトロニクス協会、2020 年 10
月 30 日（オンライン）、基調講演(6) Atsuo Kawamura, “Challenge to 99.9 % electric power conversion efficiency for inverter in a
few kW power range”, IEEE ECCE-Asia (Energy Conversion and Expo), Plenary Invited Speaker,
November 30, 2020 (China) (on-line)(7) Atsuo Kawamura, “Trend of Very High Efficient DC-DC and DC-AC Power Conversion”, IEEE
Asian Energy and Electrical Engineering Symposium(AEEES2021), Plenary Invited Speaker, March
26-28, 2021, Chengdu, China (on-line)(8) 河村篤男、“電力変換効率 99.9％”のインバータ”、日本学術会議-電気電子工学委員
会制御・パワー工学分科会、2021 年 9 月 17 日
(9) Atsuo Kawamura, ”Challenge to 99.9 % efficiency electric power conversion and theapplications”、 IEEE ICPES2021(International Conference on Power and Energy Systems), Keynote
Speech, December 18-20, 2021 (Shanghai, China)(10) 河村篤男、“パワーエレクトロニクス”、KISTEC 電子技術科「半導体コース」 IoT／5G に向けた半導体の基礎と応用、2022 年 2 月 2 日
２．小原の招待講演など(1)小原秀嶺，「ノイズを発生しないパワーエレクトロニクス技術」,キョウデン 5G 時代を支えるための技術紹介セミナー（第一回）, 東京, 2019-11(2)小原秀嶺，「ノイズを発生しないパワーエレクトロニクス技術」,キョウデン 5G 時代を支えるための技術紹介セミナー（第三回）, 大阪, 2020-2

1

３．国外からの見学者（写真参照）(1) Prof. C. Worek from AGH University of Science and Technology, Poland, 2019-4-12(2) 13 students from Tsinghua University(清華大), 中国, 2020 年 1 月 16 日

写真１：Worek教授

写真2： 清華大学からの見学

４．その他の社会貢献
横浜パワーエレクトロニクスカレッジ(YPEC)を 2020 年 4 月開講、主催は特定非営利活動法人 YUVEC、2020 年 10 月実施のベーシックコース（実験を中心にしたカリキュラム、
3 日間）を河村・小原が監修。

写真３：YPEC 講義風景

写真４：YPEC 実験風景

2021 年度は、コロナ禍のため中止。2022 年度は再開予定。
(以上)

2

寄附講座延長更新後 2 年間の研究計画

2022-4-1 河村

１．2022 年 3 月時点(科研基盤 S 終了時)での未解決課題（１）HEECS インバータの電力変換効率が、99.90％には達しない。
・ただし、測定精度は 0.006％を実現できる手法を提案・実証できた。
(ジャーナル投稿中)。
・現状の 99.83％(ジャーナル投稿予定)は世界記録。
（２）応用としてのモータ制御の HEECS インバータ高効率運転の実証実験が未達。
・モータの考慮する必要がある。
（３）応用としての太陽光発電用 HEECS インバータ力率制御の過渡現象実験が未達。制御則が未完成。
２．2022 年 4 月から 2024 年 3 月までの研究課題など（１）効率 99.90％を実証する：（これが主テーマ）
手段：回路定数などの最適化。
制御：ロバストな制御。
回路トポロジー：いろいろとアイデアはある。
高精度測定技術：さらに、高精度化を狙う。
科研基盤Ｂが不採択となって、研究費不足となっている。
目標：99.90％が達成できれば、Engineering Science の成果として
Nature に論文を投稿したい(希望)。
（２）応用としての高効率モータ制御の実現
制御の準備ができれば、実験できそうだが、技術的に難しい。
（３）応用としての太陽光発電機器の力率制御の過渡現象実験の実現
制御の準備ができれば、実験する予定。
３．招待講演による SDG’s への社会貢献
引き続き、招待講演（2022 年 6 月現在、2022 年度 4 件、2023 年度 1 件の予定）を通じて、社会貢献する。
（以上）ࣁྋ %Ԉௗ෾͹̐೧ؔ͹‫ر‬෡ߪ࠴ʁϏϭʖΦϪέφϫωέη‫ر‬෡‫ڂݜ‬෨໵ʤ‫ࢀښ‬੣ࡠॶʥ͹̐೧ؔԈௗ෾͹‫׈‬ಊๅࠄ  น ͹ΩώʖϘʖζᐤ㝃ㅮᗙ㸸ࣃ࣮࢚࣡ࣞࢡࢺࣟࢽࢡࢫᐤ㝃◊✲㒊㛛㸦ி୕〇సᡤ㸧ࡢ 2 ᖺᘏ㛗ศࡢάືሗ࿌
2024 ᖺ 3 ᭶ 29 ᪥ ᶓ὾ᅜ❧኱Ꮫᐤ㝃ㅮᗙ Ἑᮧ1㸬ᐤ㝃ㅮᗙࡢᴫせ㸸ᐤ㝃◊✲㒊㛛ࡢྡ⛠ 㸸 ࣃ࣮࢚࣡ࣞࢡࢺࣟࢽࢡࢫᐤ㝃◊✲㒊㛛ᐤ㝃㔠㢠⥲㢠 40,000 ༓෇㸦20,000 ༓෇2 ᖺ㛫㸧ᐤ㝃ࡢ᫬ᮇཬࡧᮇ㛫
2022 ᖺ 4 ᭶ 1 ᪥ࡼࡾ 2 ᖺ㛫㸦2024 ᖺ 3 ᭶ 31 ᪥ࡲ࡛㸧ᢸᙜᩍဨྡཬࡧ⫋ྡἙᮧ ⠜⏨   ᐤ㝃ㅮᗙ➼ᩍဨ㸦ᩍᤵ┦ᙜ㸧
Hadi Setiadi  ᐤ㝃ㅮᗙ➼ᩍဨ㸦ㅮᖌ┦ᙜ 2022 ᖺ 4 ᭶㹼5 ᭶㸧
Van-Ling Pham ᐤ㝃ㅮᗙ➼ᩍဨ㸦ㅮᖌ┦ᙜ 2022 ᖺ 10 ᭶㹼2024 ᖺ 1 ᭶㸧タ⨨┠ⓗᶓ὾ᅜ❧኱Ꮫ࡟࠾ࡅࡿࣃ࣮࢚࣡ࣞࢡࢺࣟࢽࢡࢫ㛵㐃ࡢ◊✲ࢆ୍ᒙάⓎ໬ࡍࡿ࡜ඹ࡟㸪ᶓ὾ᅜ❧኱Ꮫࡢᩍ⫱◊✲ࡢᅜ㝿໬ࢆ᭦࡟ಁ㐍ࡋ㸪ࡑࡢᡂᯝࢆ♫఍࡟Ⓨಙࡍࡿࡇ࡜࡟ࡼ
ࡾ㸪♫᫝࡟๎ࡾ㸪♫఍㈉⊩ࡍࡿࡓࡵࠋ
2㸬2022ᖺ4᭶࠿ࡽ2024ᖺ3᭶ࡲ࡛ࡢάືሗ࿌ࡢࡲ࡜ࡵ
2.1㸬◊✲㛵㐃㸦㈨ᩱ 1 ࠾ࡼࡧῧ௜㈨ᩱㄽᩥཧ↷㸧(1) ຠ⋡ 99.90㸣ࡢᐇド᪂ࡋ࠸࢖ࣥࢲࢡࢱࢆ〇సࡋ࡚ࠊຠ⋡ࢆᐇ ࡋࡓࠋ99.836% ( 1300W ฟຊ᫬)ࡢࢹ࣮
ࢱࢆᚓࡓࠋᘬࡁࡘ࡙ࡁᦆኻపῶࡢᑐ⟇ࢆ᳨ウࡋ࡚࠸ࡿࠋ
(2) ᛂ⏝࡜ࡋ࡚ࡢኴ㝧ගⓎ㟁ᶵჾࡢຊ⋡ไᚚࡢ㐣Ώ⌧㇟ᐇ㦂ࡢᐇ⌧ኴ㝧ගⓎ㟁ჾࡢᛂ⏝࡜ࡋ࡚ࠊຊ⋡ไᚚࢆ᳨ウࡋࡓࠋ㐍ࡳຊ⋡㸦࢖ࣥࣂ࣮ࢱ࠿ࡽぢ࡚㸧ࢆᐇ⌧ࡋࠊ㐜ࢀຊ⋡㸦࢖ࣥࣂ࣮ࢱ࠿ࡽぢ࡚㸧ࡶᐇドࡋࡓࠋ
2.2㸬ᅜ㝿໬࠾ࡼࡧ♫఍㈉⊩㸦㈨ᩱ2ཧ↷㸧 ᅜෆእࡢᏛ఍࡛ࡢᣍᚅㅮ₇࠾ࡼࡧᅜእ࠿ࡽࡢぢᏛ⪅ཷࡅධࢀ࡞࡝ࢆ㏻ࡌ࡚ࠊᅜ㝿໬ཬࡧ♫఍㈉⊩ࢆᐇ᪋ࡋࡓࠋ
3㸬⮬ᕫホ౯㸦ῧ௜㈨ᩱࡢ◊✲ィ⏬ཧ↷㸧  ᙜึࡢᐤ㝃ㅮᗙࡢタ⨨㊃᪨ࢆ༑ศ㐙⾜ࡋ࡚࠸ࡿࠋ㈨ᩱ1㸸2022㸫2023ᖺᗘࡢᡂᯝࡢࡲ࡜ࡵ- Ⓨ⾲ㄽᩥ㈨ᩱ2㸸ࣃ࣮࢚࣡ࣞࢡࢺࣟࢽࢡࢫᐤ㝃ㅮᗙࡢᣍᚅㅮ₇࠾ࡼࡧᾏእゼၥ⪅࡞࡝ῧ௜㈨ᩱ㸸ᐤ㝃ㅮᗙᘏ㛗ࡢ2ᖺ㛫ࡢ◊✲ィ⏬㸦2022-2023ᖺᗘ㸧࠾ࡼࡧ୺せ࡞ㄽᩥ㸹3⦅
1

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͵͢ɽ㈨ᩱ㸰㸸ࣃ࣮࢚࣡ࣞࢡࢺࣟࢽࢡࢫᐤ㝃ㅮᗙࡢᣍᚅㅮ₇࠾ࡼࡧᾏእゼၥ⪅࡞࡝2022 ᖺ 4 ᭶ 1 ᪥࠿ࡽ 2024 ᖺ 3 ᭶ࡲ࡛    ᐤ㝃ㅮᗙ Ἑᮧ㸬Ἑᮧࡢᣍᚅㅮ₇࡞࡝
(1) Atsuo Kawamura, ”How to realize 99.9 % efficiency inverter and its applications”ࠊ IEEE
CPESE2022(Conference on Power and Energy Systems Engineering) Keynote speech, September
9-11, 2022, Kyoto (on-line)(2) Ἑᮧ⠜⏨㸪“ຠ⋡ 99.9%ࢆ┠ᣦࡍࣃ࣮࣡ࢥࣥࣂ࣮ࢱࡢᇶ♏◊✲”ࠊe ࣔࣅࣜࢸ࢕ࢩ࣏ࣥࢪ
࣒࢘㸦ᮾி⌮⛉኱㸧ࠊ2022 ᖺ 9 ᭶ 17 ᪥ࠊᣍᚅㅮ₇(3) Atsuo Kawamura, “Review of 99.9% Class Efficiency DC-AC Power Conversion andApplications”, VANJ Conference 2022 (Vietnamese Academic Network in Japan), Keynote
Speaker, November 26-27, 2022, Tokyo (on-line)(4) Ἑᮧ⠜⏨,”㟁ẼᏛ఍඲ᅜ኱఍ࢩ࣏ࣥࢪ࣒࣮࢘͆࢝࣎ࣥࢽ࣮ࣗࢺࣛࣝࡢ᫬௦࡟㟁Ẽࡀᯝࡓࡍᙺ๭㹼ᮍ᮶࡟ࡘ࡞ࡄክࢆㄒࢁ࠺㹼͇ࡢ㸰㒊ࣃࢿࣝࢭࢵࢩࣙࣥ͆C.N.♫఍࡟㟁Ẽࡀᣅࡃᮍ᮶ࡢክࢆㄒࡿ͇ࡢࣔࢹ࣮ࣞࢱࠊ2023 ᖺ 3 ᭶ 15 ᪥(5) Atsuo Kawamura, “How to Accurately Measure the Loss of 99.9% class Efficiency Inverter”,
ICMIE (International Conference on Measurement Instrumentation and Electronics), Keynote
Speaker, April 14-16, 2023, Hangzhou, China (on-line)(6) Atsuo Kawamura, ”Future Trend of 99.9% class Efficiency DC-AC Power Conversion and its
Applications”, ICPST2023(International Conference on Power Science and Technology), Keynote
Speech, May 5-7, 2023, Kunming, China (on-line)(7) Atsuo Kawamura, ”How can we achieve Inverters with an Efficiency level of 99.9%?”, Academic
annual Conference of the Power Electronics Committee of CES (China Electrotechnical Society),
Keynote Speech, May 13-15, 2023, Shanghai, China (on-line)(8) Atsuo Kawamura, ”How far have inverters with an efficiency of 99.9% been able to go ?”, IEEE
ICPE2023-ECCE-Asia (International Conference on Power Electronics), Plenary Speech, May 2225, 2023, Jeju, Korea(9) Atsuo Kawamura, ”Survey of 99.9% Class Efficiency DC-AC Power Conversion and its Future
Applications”, IEEE PSGEC2023 (Power System and Green Energy Conference), Keynote Speech,
August 24-26, 2023, Shanghai, China(10) Atsuo Kawamura, “Recent Survey on 99.9% Class Efficiency DC-AC Power Conversion
and the Grid Applications”, 2nd Asian Conference on Frontiers of Power and Energy(ACFPE 2023), Keynote Speech, October 20-22, 2023, Chengdu, China(11) Atsuo Kawamura, ”99.9% Class Efficiency DC-AC Power Conversion and its Application to
Grid Interconnection”, IEEE Energycon2024 (International Energy Conference), Keynote Speech,
March 4-7, 2024, Doha, Qatar


1㸰㸬ᅜෆእ࠿ࡽࡢぢᏛ⪅㸦෗┿ཧ↷㸧(1) Dr. Kalyan Gokhale, Technology Manager ABB Milwaukee, USA, 2December 5, 2022
Industrial seminar 10:00-11:00 on December 5࠾ࡼࡧຠ⋡ ᐃ࡟㛵ࡍࡿពぢ஺᥮෗┿㸯㸸Dr. Kalyan Gokhale        (2) ࣦ࢓ࣞ࢜ࢪࣕࣃࣥ࠿ࡽࡢぢᏛ㸦2023 ᖺ 9 ᭶ 6 ᪥㸧㸱㸬ࡑࡢ௚ࡢ♫఍㈉⊩(1) ᶓ὾ࣃ࣮࢚࣡ࣞࢡࢺࣟࢽࢡࢫ࢝ࣞࢵࢪ(YPECࠊ୺ദࡣ≉ᐃ㠀Ⴀ฼άືἲே YUVEC)ࡢ
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Published online in Wiley Online Library (wileyonlinelibrary.com). DOI:10.1002/tee.23728

Invited Review Paper
Survey of 99.9% Class Efﬁciency DC-AC Power Conversion
and Technical Issues
Atsuo Kawamura*a , Fellow
Yasuhiko Miguchi* , Member
Hadi Setiadi** , Member
Hidemine Obara* , Member
This study provides a survey overview of the literatures with the goal of maximizing the efﬁciency of DC-AC power conversion
from an engineering science perspective. With the advent of wide band gap power semiconductors, the published literature on
realizing high efﬁciency DC-AC converters has increased. Therefore, a literature survey of high-efﬁciency DC-AC inverters
was ﬁrst conducted. We demonstrated the importance of the measurement accuracy in measuring high efﬁciency losses, andthen presented the literature on new measurement methods, as well as examples of analysis of the breakdown of these losses.
Furthermore, we reviewed the literature on high-efﬁciency inverters. We presented measurement data (99.83%) on an inverter witha high efﬁciency energy conversion system circuit topology using Silicon Carbide (SiC) and Gallium Nitride (GaN) devices todemonstrate how the procedure was used to achieve loss minimization. We summarized the challenges hindering high efﬁciency.
© 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.
Keywords: high efﬁciency; loss measurement; virtual transformer; measurement accuracy; inverter

Received 24 June 2022; Revised 31 August 2022

1. Introduction
1.1. Objective of this paper To address the issuesof global warming and resource depletion, it is important toimprove the efﬁciency of power conversion. Higher-efﬁciency
power converters are used in several ﬁelds, such as electric vehicles
and renewable energy generation, for saving a considerable amountof energy. From an engineering perspective, the power density of
power converters (Ohashi [1], Google little box [2], Kolar [3])has been prioritized, and numerous studies have been conducted.
This is because, in practice, downsizing and weight reduction ofequipment reduce costs and can be applied in various applicationﬁelds. Few studies have been conducted on power loss reduction
from the perspective of engineering science, focusing only on
efﬁciency [4,5]. This is because, no matter how high the efﬁciency
is obtained, if the power conversion system becomes large, it will
be a problem in practical use. Therefore, it is important to identify
the upper limit of efﬁciency in the current wide band gap (WBG)
devices and clarify the obstacles in the future development of
power conversion from the view point of engineering science.
In particular, it is important to determine the upper limit of
efﬁciency when improving power density. Therefore, in this study,
we conduct a literature survey on how low the loss of DC-AC
power conversion can be, and how high the efﬁciency can be
a Correspondence to: Atsuo Kawamura. E-mail: kawamura@ynu.ac.jp* Department of Electrical and Computer Engineering, Yokohama National

University, 79-5, Tokiwadai, Hodogaya-ku Yokohama 240-8501, Japan
Corporate Laboratory, Nanyang Technological
University, Singapore** Rolls-Royce@NTU

achieved. In addition, we discuss the future trends and technicalissues in this challenge.
In the ﬁeld of DC-DC power conversion, it has been proven that,based on the principle of partial power conversion, the efﬁciency
can be maximally increased in principle if the input–output voltage
ratio is ﬁxed to a certain condition [6,7]. However, in DC-AC
conversion, this condition is not satisﬁed because the output
voltage varies from zero to positive and negative rated voltages.
Accordingly, the input–output voltage ratio varies. Therefore,
no general method to minimize losses can be found for DCAC power conversion [3]. Consequently, the authors proposed tosynthesize a full-wave rectiﬁed voltage waveform by a multilevel
DC-DC converter, which was then folded back to generate asinusoidal waveform by an unfolding inverter circuit topology
inverter called the two-battery high efﬁciency energy conversion
system (HEECS) shown in Fig. 1 [4], and then they published datawith efﬁciencies of over 99.8% [5]. This circuit is unique because it
can separate switching and conduction losses and simultaneously
minimize them [4,8,9]. As a result, it can achieve a very highefﬁciency. However, the disadvantage of this circuit topology isthat the output current includes a much larger distortion thanthat of conventional pulse width modulation (PWM) inverters
when the load power factor is not unity. However, the authors
proposed remedies for the problem [10,11], and by modifying
the control algorithm, the HEECS inverter manages to have a
low distortion in the output current for various power factors
while maintaining high efﬁciency. Comparison with efﬁciency
improvement using other circuit topologies and motor drive witha three-phase HEECS inverter [12] are discussed in Section 4.
To the best of our knowledge, no studies have been conducted© 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

E2

E1

In Ref. [25], it was reported that by the introduction of avirtual ideal transformer-based Back-to-Back (BTB) measurement,
an average efﬁciency of powering and regenerating operations of
inverter can be theoretically measured at the accuracy of 0.002%.
This idea was extended to the practical measurement aspect, and a
new approach was proposed, known as virtual transformer-based
BTB asynchronous loss measurement (VTASLM), using one set ofmeasurement instruments [19], and the accuracy of 0.006% wasreported. The measuring procedure is as follows. First, prepare
one set of measuring instruments and a power converter under
test. Second, calibrate the power measuring instruments. Finally,measure the losses of powering and regenerating operations. This
technique was employed in this study. This approach is brieﬂysummarized in Section 2. In addition, based on the measurementfrom the HEECS inverter loss with respect to the breakdown oflosses, we presented and discussed with respect to loss reduction
measures.

S4 iL
S2

S3

L

vsw
S1

C

S7

S5

vdc

Load

S6 vacS8

Fig. 1. Two battery HEECS inverter [4,5]1.3. Problems in the pursuit of high efﬁciency—
approaches and discussion as for loss reduction
Because the method for measuring losses electrically and withhigh precision has been established in Ref. [19], we need to establish a method to minimize losses and maximize efﬁciency. Various
approaches can be considered for such a method; however, a faircomparison of the maximum efﬁciency values cannot be obtained
unless common assumptions, such as ratings and circuit parameters are pre-determined. Therefore, in Section 3, we organize thesecommon preconditions, and then deﬁne various free parameters
for efﬁciency maximization. Subsequently, we summarize methods for obtaining maximum efﬁciency [5]. Thereafter, we survey
literatures on actual methods to seek the maximum efﬁciency of
HEECS inverters using SiC and GaN power devices. In addition,
Section 4 summarizes the discussions regarding the realizationof maximum efﬁciency from the perspective of the relationshipbetween the output capacitance Coss of the power device, and thesystem total resistance, as well as the comparison with other circuit
topologies [5].

Fig. 2. Survey of high efﬁciency inverters [5]that exceed the maximum efﬁciency achieved by this circuit
topology [5].

1.2. Literatures on high efﬁciency measurement of
inverters and importance of measurement accuracy
Several actual measurements of high efﬁciency of inverters
using WBG devices have been reported [5,13–20], and examplesof reported output and efﬁciency, including their measurement
accuracy, are shown in Fig. 2. Note that if there is no descriptionof the measurement accuracy in the literature, the accuracy is notindicated. The ﬁgure shows that DC-AC conversion efﬁcienciesof 99.5% or higher can be achieved with the latest WBG devices.
The height of the bars in the ﬁgure indicates the measurement
accuracy. When the conversion efﬁciency is close to 99.9%, thenthe measurement accuracy is critical. The highly efﬁcient dataset
in the upper left corner is a group from the authors’ literatures.
It is reported [13,14] that loss measurement by the direct
subtraction of the input and output power results in an efﬁciency
accuracy of 0.38%. To measure the total loss accurately, thecalorimetric method is adopted [14,21–24]. Historically, induction
motor loss was measured by this method [23,24]; however, theinsulation of the heat ﬂow was poor, and the leakage of the heat
was not well suppressed. Consequently, the measurement accuracy
was not high. In Refs. [14,21,22], the whole converter under
test was installed in a double-layer-structure of thermal insulatedchamber, and the loss was precisely measured by heat ﬂow inthis inner chamber. In DC-AC conversion, a high accuracy of
0.003% was reported in Ref. [14]. There are few other approaches
for the high accuracy. A loss breakdown approach [13] in allelectric measurement accuracy of 0.04% was reported for DCAC conversion. However, many types of data measurements are
required, and the data handling process is complicated.

2. High-Precision Measurement Method and Loss
Analysis of DC-AC Converters
2.1. VTASLM method If an ideal transformer can berealized with no voltage amplitude difference or phase shift
between the input and output terminals, and zero losses using
an electronic load and an AC voltage source, only the lossesof the power converter can be measured by the arrangement
shown in Fig. 3. To elaborate on this ﬁgure, two inverters
operating in powering and regenerating are connected via an
ideal transformer. At the DC voltage source terminals, the input
terminal on the power side and the output terminal on theregenerative side are connected. Therefore, only the poweringand regenerating operation losses are supplied from the DC
source, and if they can be measured, the total powering andregenerating losses can be obtained [25]. This is the ideal case;however, in reality, an ideal transformer does not exist. In
the absence of an ideal transformer, a method to measure thepowering and regenerating losses separately is considered, andthe detailed measurement procedure and measurement accuracy
are analyzed in the literature (19). According to this, as shownin Fig. 4, it is proposed to measure losses during powering and
7

IEEJ Trans 18: 6–14 (2023)

19314981, 2023, 1, Downloaded from https://onlinelibrary.wiley.com/doi/10.1002/tee.23728 by Cochrane Japan, Wiley Online Library on [22/03/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License

SURVEY OF 99.9% CLASS EFFICIENCY DC-AC

S1
0.13

S2
0.98

SiC-switching loss

SiC-conduction loss
1.54
24%

0.15,, 2%0.40, 6%

Fig. 3. A BTB loss measurement system based on virtual idealtransformer [19,25]

2.02
31%

Total loss
6.47 W

0.38
6% 0.38

S3
0.26
S4
0.65

1.59
25%

6%

S4
0.59

S1
0.05
S3
0.50

S2
0.45

Inductor fundamental
freq. iron loss
Inductor-carrier freq.
iron loss
Inductor-conductionloss
PCB-conduction loss

Unfolding inverterconduction loss

Fig. 5. Loss breakdown ratio of DC-AC conversion (2.2 kW) of
SiC-HEECS inverter (symbols S1, S2, S3, and S4 are the same as
those in Fig. 1) [13]conduction loss of unfolding inverter. The loss breakdown graphis shown in Fig. 5. Because it is necessary to measure the lossof each device, the number of acquired data is large, and thedata processing is also time-consuming. At an output of 2.2 kW,
a power conversion efﬁciency of 99.71%, and a measurement
accuracy of 0.04% were obtained.
From this ﬁgure, a policy for loss reduction can be discussed. The power device used in the chopper section is Rohm’s
SCT3017AL (conduction resistance: 17 m). First, it is necessary
to reduce the switching loss in the chopper section; however, it isclear that the selection of the device is important. Devices should
be selected from the viewpoints of (1) minimizing switching loss
by devising a gate drive system and (2) selecting a device witha minimum conduction loss. Next, unfolding inverters should beselected with a low conduction loss because switching losses canbe ignored as switching operations are performed only twice in
one cycle. Inductor loss consists of conduction loss, fundamental
frequency iron loss, and harmonic ripple iron loss. In addition, thematerial, switching frequency, and size of L should be properly
selected. Finally, the resistance of the printed circuit board (PCB)
substrate must be selected to be small. Currently, the thickness is
175 μm, and the loss ratio is small.

Fig. 4. Basic structure of virtual transformer-based BTB asynchronous loss measurement method using one set of measurement
instruments (VTASLM) [19]. (a) Powering power measurementand (b) Regenerating power measurement
regenerating operations asynchronously. However, the proposed
method has the following two problems: (1) measurement errors
due to the fact that the output of powering power and inputof regenerating power are not equal owing to asynchronous
operation between Fig. 4(a), (b). (2) measurement error of themeasurement instruments because the current ﬂow direction of
the current sensor between powering Fig. 4(a) and regenerating
Fig. 4(b) is the opposite of each other. A DC offset is observed
between the current readings. These problems were analyzed,
leading to a proposal of a practical accurate measurement [19] inwhich a SiC-HEECS inverter was selected as the converter under
test. The results showed that the power conversion efﬁciency is99.75%, and its measurement accuracy is 0.006% when the output
power is 1600 W. Furthermore, the breakdown of that 0.006%
measurement accuracy was analyzed in the discussion, and thecalibration error owing to the change in current direction is quite
large at approximately 60%, followed by a reading error in loss
measurement [26,27] at 20%, and a smaller measurement error
based on control stability at 15%. All errors were statisticallyprocessed, and the measurement accuracy was varied dependingon the measurement date.

3. Optimization of High Efﬁciency DC-AC Power
Conversion and Literature Review
The procedure for the loss optimization is as follows: (1) A
basic speciﬁcation is set so that a fair comparison is made, (2) acircuit topology is selected, (3) quasi-speciﬁcation parameters are
selected for this topology, and (4) free parameters are optimized.
Finally, the literature review and new data are introduced.

3.1. Basic speciﬁcations and other concepts for faircomparison A fair comparison of the actual measured valuesof the maximum efﬁciency obtained is not possible unless common
preconditions, such as ratings (voltage and current) and circuit
parameters, are pre-determined. Therefore, common preconditions
are organized, and then the preconditions, quasi-speciﬁcation
parameters, and free parameters for efﬁciency maximization are
selected and summarized with respect to the literature (5).

2.2. Breakdown of losses and loss reduction policy
A measured breakdown of the SiC-HEECS inverter losses has
been proposed [13]. All losses were obtained by measurement andtheoretical calculations. The losses were divided into (1) switchinglosses in the DC-DC chopper section, (2) conduction losses inthe DC-DC chopper section, (3) losses in the ﬁlter inductor, (4)conduction losses in the Printed Circuit Board (PCB), and (5)(1) Basic speciﬁcations—device voltage margin, switchingfrequency, and voltage total harmonic distortion (THD)8IEEJ Trans 18: 6–14 (2023)

19314981, 2023, 1, Downloaded from https://onlinelibrary.wiley.com/doi/10.1002/tee.23728 by Cochrane Japan, Wiley Online Library on [22/03/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License

A. KAWAMURA ET AL.

Table I. Basic speciﬁcation for inverter under test

Table II. Quasi-speciﬁcation parameters

Device voltage margin

50% of the output voltage

Chopper devices

Switching frequency
THD of output voltage

16 kHzApproximately 1%

Resistance of unfolding
inverter devices
Inductor L
Capacitor C

Because the output voltage is related to the rated voltage of thepower device, we decided that the voltage margin of the device
should be 0.5 times the peak output voltage. There are many ways
to make a choice regarding this part; however, if this decision is
not made, subsequent developments will be affected. Therefore,
we proposed this selection as a benchmark. Speciﬁcally, using
a device rated at 650 V, the output peak voltage v acpeak of theinverter is expressed byvacpeak = 650 ÷ 1.5 ≈ 433

Control
PCB

Ron = 17m (typ) SCT3017AL(Rohm)
Ron = 3.7m CAS325M12HM2(Wolfspeed)
1.25 mH (18 m) (Ferrite) (IPEC)
8 μF (3.5 m) (ﬁlm)(ARCOTRONICS)
DB(Deadbeat) Powering &regenerating
175 μm Cu thickness (a few m)(P-ban)Finally, the free parameters are the voltage ratio of the two
power supplies E 1 and E 2 , gate driver’s ingenious parts according
to the circuit topology (gate resistance and dead time between thehigh and low side of the chopper), and output (load) with the
maximum efﬁciency.
In the following, we focus on the case of SiC power devices,
and also introduce a literature for the case of GaN.

(1)

The sum of the voltages of the two power supplies E 1 and E 2 of
the HEECS inverter in Fig. 1 was ﬁxed at this value. Furthermore,
the switching frequency was set to 16 kHz, which is considered
to be the lowest limit of the non-audible range to humans.
Finally, the THD of the output voltage was determined to beapproximately 1%. Although IEC61727 [28], a regulation for gridinterconnection, speciﬁes, for example, a harmonic current (3rd to
9th order) of 4.0% (10 kW or less); the voltage was speciﬁed here.
These were considered suggestions for benchmarking in the next
section and beyond. The output rating was set at 5 kW. These aresummarized in Table I.

3.2. Case study—SiC
3.2.1. Quasi-speciﬁcation parameters

For the SiC
switching devices in the chopper section, we selected those withthe lowest possible on-state resistance Ron (highest possible
current rating). Similarly, the unfolding inverter is turned on andoff only twice per cycle; thus, we selected a device with thelowest possible on-resistance (highest possible current rating).
These are shown in Table II.
Next, ferrite and amorphous are the materials of choice forinductance. Preliminary comparison experiments were conducted
to determine the loss owing to differences in materials with similar
inductance, and we decided to use a ferrite inductor of 1.25 mH,
as shown in Table II. The material used for the capacitor was ﬁlm,
and its capacitance was selected as 8 μF based on preliminary
experimental measurements of loss. An improvement in efﬁciency
of approximately 0.001% for 4 μF was achieved compared tothat of 8 μF; however, the deadbeat (DB) control described
below worked stably in both powering and regenerating modes
when using 8 μF; thus, this value was used. There is room for
improvement in this selection. The VTASLM method requires both
powering and regenerating operations, and the open-loop control
of HEECS inverter exhibits a high THD in case of regeneration
operation. To guarantee stable operation of HEECS inverter in both
powering and regenerating conditions with small THD required in
the basic speciﬁcation in Section 3.1, this DB control was adopted[10,30]. The PCB (175 μm copper thickness) design was fabricatedin-house for the pattern, and the hardware was prototyped on a Pban. The conduction resistance of the circuit is a few m, although
the total conduction resistance varies depending on the pattern
through which the devices conduct [13].

(2) Circuit topology: reasons for selection of HEECS circuits
The prerequisite is the circuit topology, and the HEECS inverter
circuit shown in Fig. 1 was chosen for this study. This circuit
has the following three characteristics, judged from the scientiﬁcviewpoint of reducing losses [4,13]. (1) The DC-DC chopper
section is a multilevel power conversion, and the principle ofpartial power conversion inherently allows high power conversion
efﬁciency if the voltage conversion ratio is small [4,6,7]. (2)Because the output voltage operates to output a full-wave rectiﬁed
waveform, the fundamental ﬂux variation of the inductor is mostly
in the ﬁrst quadrant of the ﬂux density—ﬁeld intensity (B-H) plane[29], which is considered to have less loss than if the variations
were over four quadrants [13]; (3) In the unfolding inverter circuit,switching losses are negligible because the switching operation is
once every half cycle, and a device can be chosen to suppress
conduction losses. If a circuit topology other than this is chosen,
the ideas in the following discussion can be applied, but theprocedure will be different. Another circuit topology is discussed
in Section 4.2.
(3) Quasi-speciﬁcation parameters—circuit parameters andfree parameters.

3.2.2. Free parameters-E1 /E2 voltage ratio, gate driver,variable dead time control, and sensorless control The

The quasi-speciﬁcation parameters are the material of theswitching device of the chopper section (SiC, GaN, etc.), and its
voltage and current rating; the material of the LC ﬁlter inductor
and its inductance; the material of the capacitor and its capacitance;
the material of the unfolding inverter device and its voltage andcurrent rating; the output voltage control method; the PCB patternof the circuit.

remaining degrees of freedom were the voltage ratio of the two
power supplies E 1 and E 2 , ingenious part of the gate driveraccording to the circuit topology (gate resistance and dead time
distribution between the high side and low side of chopper), andload (resistive) parameters at maximum efﬁciency.
9

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SURVEY OF 99.9% CLASS EFFICIENCY DC-AC

E1 E2 ratio The output capacitance Coss of the power device
determines the magnitude of the current to be charged anddischarged for each switching operation, and the charging anddischarging power is a function of the voltage between the drainsource (DS) terminals. Switching losses are a function of theswitching voltage and current, which are also functions of thevoltage between DS terminals. Therefore, the loss owing to these
two factors is expected to have a minimum value by changing theratio of E 1 and E 2 [5,20].
Therefore, we qualitatively considered the following equations.
First, assuming EI/6 as an approximate formula for switching loss
E SW [31], the approximate ESW and the charge/discharge energy
loss E coss owing to the output capacitance Coss can be obtainedin the following formula.
Esw ∝ 1/6E1 θ00Ecoss ∝ 1/2Coss θ00

Iac dθ + 1/6E2

Fig. 7. Relation between loss and E1 (experiment) [5] π/2
Iac dθ

θ0

E12 dθ + 1/2Coss

 π/2
θ0

E22 dθ

(2)

(3)

where
sin (θ0 ) = E1 / (E1 + E2 )Plotting the magnitudes of (2) and (3) with E 1 as the variable
on the horizontal axis, both curves are convex downward. The
minimum point of Eq. (2) is located far to the right of (E 1 + E 2 )/2,
while that of (3) are located slightly to the right of (E 1 + E 2 )/2.
Figure 6 qualitatively illustrates this trend. Therefore, when E 1 isassumed as a variable and the total loss, including (2) and (3), ismeasured, it is expected that the total loss shows the minimum
point at the certain E 1 , which is slightly on the right side of(E 1 + E 2 )/2. Figure 7 depicts the measured loss as a function of
E 1 according to the direct method of measurement [13]. In thisexperiment, the total value of power supplies E 1 + E 2 was ﬁxed
at 433 V as speciﬁed in (1). From Fig. 7, it is observed that theloss is minimized when E 1 is 250 V. Based on the theoretical
discussion in this section and experimental results, the loss is
considered to be minimized when the free parameter E 1 is 250 V.
E 2 is 433–250 = 183 V.

Fig. 8. Measured average loss of SiC-HEECS inverter by
VTASLM [19]Reduced losses owing to improved gate drivers and control
laws Measures to reduce losses by adjusting the gate circuit
include (1) devising a suitable gate driver [32] and (2) variable adjustment of the dead time between the high side andlow side devices [33]. A BM6105FW-LBZ (Rohm) gate driver
was used. The use of an active gate drive was investigated [32];however, the most minimum switching loss was obtained by atrial-and-error approach on gate resistance of driver circuit forthe speciﬁc PCB. In addition, to match the switching characteristics, the characteristics of the devices were measured using a
curve tracer, and devices with uniform characteristics were used
for the PCB. In addition, the dead time between the high-side
and low-side switches’ on and off timing in the chopper circuit was considered as a variable to suppress the losses at the
body diode and the unregeneratable loss at Coss [33]. Furthermore, instead of using a current sensor to detect the inductor
current, a minimum order observer was used for DB control[30]. Consequently, power consumption at the current sensor was
reduced.
Measured loss, efﬁciency, and accuracy results Considering
the above improvement measures, the loss, power conversion
efﬁciency, and measurement accuracy are shown in Figs. 8–10 [5].
From these ﬁgures, an efﬁciency of 99.827% ± 0.009% (1300 W
output) was observed at SiC-HEECS inverter.

Fig. 6. Qualitative illustration on loss of Coss and switching
regarding E1 ((E 1 + E 2 )/2 = 216.5(V))

3.3. Case study—GaN Loss measurements were performed using a GaN high power device (GS-065-150-1-D2,
10

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A. KAWAMURA ET AL.

Fig. 9. Measured average efﬁciency of SiC-HEECS inverter by
VTASLM [19]Fig. 11. Measured average efﬁciency of GaN HEECS inverter by
VTASLM [19]Fig. 10. Accuracy of SiC-HEECS inverter efﬁciency measurement
by VTASLM

Fig. 12. Accuracy of GaN-HEECS inverter efﬁciency measurement by VTASLMGaN System) in the chopper section. The device is rated for 650 V,
150 A, and Ron = 10 m. Because it was only available as a barechip, a direct placement technique was employed by reﬂow method
on a PCB [33]; otherwise, the quasi-speciﬁcation parameters were
set the same as in the SiC case. First, the gate resistance wasadjusted by trial and error. Next, the optimum voltage ratio distribution of E 1 and E 2 was determined by the similar measurement
as in section 3.2.2.1, and E 1 was selected to be 260 V. Furthermore, owing to the operating mode, the dead time of the upperand lower side devices was adjusted because the voltage drop in
the body diode is large owing to WBG devices. Consequently, theloss owing to synchronous rectiﬁcation operation is signiﬁcantly
reduced, and simultaneously, the loss owing to the unregenerated
energy at Coss can be reduced; however, the control method could
be further improved [33,34] because there is a small phase shift
between the inductor current and output voltage due to the LC
ﬁlter in the HEECS-chopper stage, and this was ignored in thisexperiment [13]. Furthermore, the current sensorless control was
implemented for measurement.
Under these conditions, the efﬁciency and measurement accuracy were measured by the VTASLM measurement method and areshown in Figs. 11 and 12 [5]. From this ﬁgure, a maximum efﬁciency of 99.817% ± 0.0038% (1800 W output) can be read. Both
SiC and GaN had almost the same maximum efﬁciency; however,
GaN showed the maximum efﬁciency when the output power was
higher than that of SiC because the device conduction resistanceof GaN is smaller than that of SiC.

4. Discussions
4.1. Discussion on relations between output
capacitance Coss and minimum loss
4.1.1. Theoretical explanation of loss minimum condition
Assuming that the loss can be approximated by a second-orderpolynomial as a function of the output P 2 (deﬁned as x ), we deﬁne
the following equationy = a + bx + cx 2(4)where y is deﬁned as the loss (W) and x is the output power
P 2 (W).
The efﬁciency η can be obtained by dividing the loss by theoutput power and then subtracting it from 1, as shown below.
η = 1 − y/x= 1 − (b + a/x + cx)(5)This equation has a minimum when the third and fourth termson the right-hand side are equal. That is, when Equation (6) issatisﬁed,(6)x = a/c ,the maximum efﬁciency ηmax becomes (7),√ηmax = 1 − (b + 2 ac).
11

(7)

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SURVEY OF 99.9% CLASS EFFICIENCY DC-AC

4.1.2. Case study on SiC devices Applying the results ofthe previous section to the loss of SiC-HEECS inverter in Fig. 8,
the maximum efﬁciency is obtained by (7), which agrees well withthe measured data in Fig. 9. This implies the validity of (4) [5].
Because the output power is measured under the constant output
voltage condition, the output power P 2 (=x ) can be considered
to be proportional to the output current. The coefﬁcient a in(4) is constant regardless of the load, and corresponds to theloss owing to Coss discussed in section 3.2.2.1. The coefﬁcientb is for losses that are proportional only to current, such as
switching losses. The coefﬁcient c is related to the conduction
loss of the entire system, which is proportional to the squareof the current. The maximum efﬁciency increases as the second
and third terms√ on the right side of (7) reduces. Furthermore, thethird term 2 ac is approximately one order of magnitude larger
than the second term b; thus, the maximum efﬁciency (7) will
increase by suppressing this third term. Because the third term isthe product of a and c, it can be regarded as proportional to the
product of Coss, and the total system conduction resistance r onall .
Table III shows a survey on this product concerning available
devices from various companies. As Company A’s device is usedin this experiment, it is the smallest. This product is tentatively
named as “Efﬁciency Figure of merit” (EFOM), and is similar tothe high-frequency ﬁgure-of-merit (BHFFOM [35] and NHFFOM[36]) of the device itself [37]. These indices in Refs. [35–37]
were used to evaluate the high-frequency characteristics of thedevice alone; however, because the discussion here is concerning
increase of the maximum efﬁciency of the system, there is adifference between the efﬁciency of the device alone (EFOM) andthe system, in which the total system conduction resistance r onall
should be used as an evaluation of efﬁciency instead of the device
on-state resistance.

650 V–64 A

650 V–81 A

Ron (m)
Coss (pF)
EFOM (10–12) (s)material
company

17
148
2.5
SiC
A

22
262
5.8
SiC
B

15
189
4.3
SiC
C

Vout

Q3
Q2

E1

E1

Q2
Q1

(a)

Q1

(b)

Fig. 13. T-type and HEECS circuit topology [37]. (a) T-type and(b) HEECS
100

Efficien cy ηDC [%]

99.8
99.6
99.4

HEECS
99.2

T-type
99
0

100

200

300

400

Output voltage Vout [V]Fig. 14. Comparison of efﬁciency between T-type and HEECS[37]
owing to the amount of charge in Q1 , which is stored in the device
output capacitance Coss. In particular, when Q4 is turned on andoff, energy of voltage (E 1 + E 2 ) is charged and discharged in the
Coss of Q1 in the T-type; however, in the HEECS, the voltage
is distributed between Q3 and Q1 , resulting in less charge anddischarge energy. Furthermore, when the devices were parallelized
to lower the on-resistance, the loss unexpectedly increased further[40]. Therefore, charging and discharging energy of Coss increases
more than the reduced conduction loss. These phenomena usually
result in negligibly small differences in losses; however, in theregion of extremely-high efﬁciency, which is close to 99.9%, thisdifference becomes signiﬁcant.
From the view point of reduction of switching loss, previous
research suggests the use of modular multilevel cascaded converters (MMCCs) to achieve highly efﬁcient power conversion in
inverters [41,42]. Increasing the number of cells can reduce switching losses. However, because the number of series-connected
power devices increases, it is a trade-off between switching losses
and conduction losses. This is related to the basic speciﬁcation insection 3.1, and is an issue for future study. Additionally, if thebasic speciﬁcation is modiﬁed, another loss reduction method canbe implemented in a different circuit topology. Accordingly, an
efﬁciency of 99.26% at 100 kW output has been reported for a
Dual-Active-Bridge (DAB) [43].
Furthermore, there is a literature report [12] on a new circuit
topology for motor drive with 3 phase HEECS inverter, in which
only the loss of the inverter part is examined, and it showed
over 99.5% efﬁciency. However, to improve the efﬁciency ofthe motor drive system, it is necessary to reduce the loss of theinverter as well as that of the motor itself. Future studies fora new topology are still needed to improve the efﬁciency of asystem.

Table III. Efﬁciency ﬁgure of merits (EFOM): Product of Ron
and Coss
650 V–118 A

Q4

Q3
Vout

4.2. Possible circuit topologies A circuit similar to the
HEECS circuit conﬁguration is the T-type circuit; the HEECS and
T-type circuit topologies are shown in Fig. 13 [38]. A step-down
DC-DC converter operation was performed with identical ﬁlters
and load resistors connected as their output circuits, and the losses
were measured by the direct method [13]. SiC-MOSFETs with onresistance of 17 m were used for all switches. For each MOSFET,
a Schottky barrier diode was connected in parallel; the supply
voltages for E 1 and E 2 were determined by the method proposed
in Ref. [39].
Figure 14 shows the efﬁciency map of the power conversion
when the switching frequency is ﬁxed at 20 kHz, and the output
voltage is varied [38]. Comparing the HEECS with the T-type
circuit topology, the HEECS shows approximately 0.01% higher
efﬁciency over almost the entire measurement range. This may be

Voltage & current
ratings

E2

Q4

E2

12

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A. KAWAMURA ET AL.

5. Conclusions(12) Nasu Y, Setiadi H, Miguchi Y, Obara H, Kawamura A. High
efﬁciency three-phase inverter for motor drive using HEECS chopper.
IEEJ, Tech. Comm. Meet. On Semiconductor Power Conversion,
SPC-22-097; 2022.
(13) Kawamura A, Nakazaki S, Ito S, Nagai S, Obara H. Over 99.7% efﬁciency two battery HEECS inverter at 2.2kW output and measurement
accuracy based on loss breakdown. IEEJ Journal of Industry Applications 2020; 9(6):663–673. https://doi.org/10.1541/ieejjia.20001291.
(14) Anderson JA, Hanak EJ, Schrittwieser L, Guacci M, Kolar JW,
Deboy G. All-silicon 99.35% efﬁciency three phase seven levelhybrid neutral point clamped/ﬂying capacitor inverter. CPSS Trans.
On Power Electronics and Applications 2019; 4(1):50–61.
(15) Shi Y, Li H, Wang L, Zhang Y. Intercell transformer (ICT) design
optimization and interphase crosstalk mitigation of a 100-kW SiC
ﬁlter-less grid-connected PV string inverter. IEEE Journal of PowerElectronics 2020; 1:51–63.
(16) Zhu J, Kim H, Chen H, Erickson R, Maksimovic D. High efﬁciency
SiC traction inverter for electric vehicle applications. Proc. AppliedPower Electron. Conf ; 2018, 1428–1433.
(17) Rabkowski J, Peftitsis D, Nee H. Design steps towards 40-kVA SiC
inverter with an efﬁciency exceeding 99.5%. Proc. Applied PowerElectron. Conf ; 2012, 1536–1543.
(18) Miyazaki T, Otake H, Nakakohara Y, Tsuruya M, Nakahara K.
A fanless operating trans-linked interleaved 5 kW inverter using
SiC MOSFET to achieve 99% power conversion efﬁciency. IEEE
Transactions on Industria l Electronics 2018; 65(12):9429–9437.
(19) Kawamura A, Nasu Y, Miguchi Y, Setiadi H, Obara H. Proposalof virtual transformer based back-to-back asynchronous loss measurement using a single set of measurement instrument and experimental veriﬁcation. IEEJ Journal of Industry Applications 2022;
11(1):175–184. https://doi.org/10.1541/ieejjia.21008251.
(20) Kawamura A, Nasu Y, Miguchi Y, Setiadi H, Obara H. One
investigation on efﬁciency maximization of HEECS inverter. IEEJ,
Industry Application Society Annual Meeting, 4-055; 2022.
(21) Christen D, Badstuebner U, Biela J, Kolar JW. Calorimetric power
loss measurement for highly efﬁcient converter. Proc. of Int. Conf.
Power Electron. ECCE-Asia; 2010, 1438–1445.
(22) Aarniovuori L, Kosonen A, Sillanpaa P, Niemela M. Highpower solar inverter efﬁciency measurements by calorimetric andelectric methods. IEEE Transactions on Power Electronics 2013;28(6):2798–2805.
(23) Turner DR, Binns KJ, Shamsadeen BN, Warne DF. Accurate measurement of induction motor losses using balance calorimeter. Proceedings of the Institution of Electrical Engineers 1991; 138(5, pt.
B):233–242.
(24) IEC Publication 34-2A. Methods for determining losses and efﬁciency of rotating electric machinery for tests (excluding machines for
traction vehicles), measurement of losses by the calorimetric method.
1974 First supplement to Publication 34-2(1972) Rotating Electrical
Machines, Part2.
(25) Kawamura A, Setiadi H, Miguchi Y, Nasu Y, Obara H. Discussion
on a new high accuracy loss measurement method of high efﬁcient
HEECS inverter, IEEJ, Tech. Comm. Meet. On Semiconductor Power
Conversion, SPC-21-089; 2021.
(26) HIOKI PW6001 Manual, June 2017 revised edition.
(27) HIOKI CT6862 Manual, Oct. 2018 Revised edition 8.
(28) Kjaer SB, Pedersen JK, Blaabjerg F. A review of single-phase gridconnected inverters for photovoltaic modules. IEEE Transactions on
Industry Applications 2005; 41(5):1292–1306.
(29) Yamada N. Electromagnetism. book (Institute of Electrical Engineersof Japan); 1966, 222.
(30) Miguchi Y, Nasu Y, Obara H, Kawamura A. Current control of very
high efﬁcient single-phase grid-connected inverter (HEECS). IEEJ,
Tech. Comm. Meet. On Semiconductor Power Conversion, SPC-20128; 2020.

This study outlines the latest developments of high efﬁciency
DC-AC power conversion from the perspective of engineeringscience. Many literatures on high efﬁciency DC-AC inverters
exceeding 99.5% have been published; however, it has been
pointed out that the accuracy of the measurement method isimportant when the efﬁciency increases. The authors reviewed theliteratures on signiﬁcantly high-efﬁciency inverters published by
the authors’ group, and outlined the optimization procedure of loss
minimization using a HEECS inverter with SiC and GaN devices.
The highest efﬁciency is 99.83% using SiC devices. Finally, thisstudy discusses the future challenges for high efﬁciency, suchas the analysis on the device output capacitance Coss and total
system conduction resistance, and the investigation of new circuit
topologies.
The development of new devices with larger dielectric breakdown strength is expected in the future, leading to the developmentof higher efﬁciency inverters as the conduction losses in powerdevices are highly dependent on this physical constant of the WBG
material [44].

Acknowledgment
This work was supported by JSPS KAKENHI under Grant 17H06147.

References(1) Ohashi H. Trend of recent power devices. Journal of IEEJ 2002;
122(3):168–171.
(2) Google little box HP 2014-2016. https://en.wikipedia.org/wiki/Little_
Box_Challenge.
(3) Kolar JW, Drofenik U, Biela J, Heldwein ML, Ertl H, Friedli T,
Round SD. PWM converter power density barriers. IEEE Power
Conversion Conference; 2007.
(4) Kawamura A, Nagai S, Nakazaki S, Ito S, Obara H. A very highefﬁciency circuit topology for a few kW inverter based on partial
power conversion principle. Proceedings of IEEE Energy Conversion
Congress and Expo; 2018.
(5) Kawamura A, Setiadi H, Miguchi Y, Nasu Y, Obara H. Discussion on
Loss reduction of high efﬁcient HEECS inverter. IEEJ, Tech. Comm.
Meet. On Semiconductor Power Conversion, SPC-22-059 ; 2022.
(6) Kolar JW, Krismer F, Lobsiger Y, Muhlethaler J, Nussebaumer T,
Minibock J. Extremely efﬁcient power electronics. 7th International
Conference in Integrated Power Electronics (CIPS); 2012.
(7) Tsuruta Y, Kawamura A. Realization and highly precise measurementof 50kW HEECS chopper with 99.5% efﬁciency. IEEJ Journal ofIndustry Applications 2019; 8(5):843–848.
(8) Zhao Z, Xu M, Chen Q, Lai J-S, Cho Y. Derivation, analysis, and implementation of boost-buck converter based highefﬁciency PV inverter. IEEE Transactions on Power Electronics
2012; 27(3):1304–1313.
(9) Husev O, Matiushkin O, Vinnikov D, Roncero C, Romero-Cadaval E,
Kutt L. Buck-boost inverter as a novel solution for single-phase PV
systems. 44th Annual Conference of the IEEE Industrial Electronics
Society (IECON); 2018, 6116–6121.
(10) Miguchi Y, Setiadi H, Nasu Y, Obara H, Kawamura A. Control
scheme for leading power factor operation of single-phase gridconnected inverter using an unfolding circuit. IEEE Open Journal ofPower Electronics 2022; 3:468–480. https://doi.org/10.1109/OJPEL.2022.3190559.
(11) Miguchi Y, Setiadi H, Nasu Y, Obara H, Kawamura A. Lagging
power factor operation of very high efﬁciency single-phase gridconnected inverter (HEECS). IEEJ, Tech. Comm. Meet. On Semiconductor Power Conversion, SPC-22-096 ; 2022.
13

IEEJ Trans 18: 6–14 (2023)

19314981, 2023, 1, Downloaded from https://onlinelibrary.wiley.com/doi/10.1002/tee.23728 by Cochrane Japan, Wiley Online Library on [22/03/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License

SURVEY OF 99.9% CLASS EFFICIENCY DC-AC

(31) Kawamura A, Yokoyama T, Funato H, Hoshi N, Yoshino T,
Yoshimoto K, Obara H. Introduction to Power Electronics (rev. Ed).
Tokyo: Corona Pub. Co.; 2022.
(32) Ito S, Setiadi H, Obara H, Shimono T, Kawamura A. Study on
switching loss reduction for SiC-MOSFET in wide current range byactive gate drive with slew rate control. IEEJ, Tech. Comm. Meet. On
Semiconductor Power Conversion, SPC-21-085; 2021.
(33) Setiadi H, Nasu Y, Miguchi Y, Obara H, Kawamura A. Implementation of GaN-based HEECS inverter. IEEJ annual meeting(Okayama); 2022.
(34) Zhang Y, Chen C, Xie Y, Liu T, Peng H. A high-efﬁciency dynamic
inverter dead-time adjustment method based on an improved GaN
HEMTs switching model. IEEE Transactions on Power Electronics
2022; 37(3):2667–2683.
(35) Baliga BJ. Power semiconductor device ﬁgure of merit for highfrequency application. IEEE Transaction of Electronic Device Letters
1989; 10(10):455–457.
(36) Il-Jung K, Matsumoto S, Sakai T, Yachi T. New power device ﬁgureof merit for high frequency applications. Proc. 7th Int. Symp. Power
Semicond. Devices ICs; 1995, 309–314.
(37) Wang H, Wang F, Zhang J. Power semiconductor device ﬁgureof merit for high-power-density converter design application. IEEE
Transaction of Electronic Devices 2008; 55(1):466–470.
(38) Ito S, Nakazaki S, Nagai S, Obara H, Kawamura A. Loss measurement of two different topologies for extremely high efﬁciency power
conversion. IEEJ Annual Meeting (Sapporo); 2019.
(39) Kawamura A, Obara H. Scientiﬁc pursuit for feasibility of highefﬁcient inverter based on principle of partial power conversion. IEEJ
Annual Meeting (Fukuoka); 2018.
(40) Ito S. Study on loss reduction methods for extremely highly efﬁcient
inverter. Graduation Thesis, Yokohama National University; 2019.
(41) Peftitsis D, Tolstoy G, Antonopoulos A, Rankowski J, Lim J,
Bakowski M, Angquist L, Nee H. High-power modular multilevel
converters with SiC JFETs. IEEE Transactions on Power Electronics
2012; 27(1):28–36.
(42) Akagi H. Classiﬁcation, terminology, and application of the modular
multilevel Cascade converter (MMCC). IEEE Transactions on PowerElectronics 2011; 26(11):3119–3130.
(43) Haneda R, Akagi H. Design and performance of 850-V 100kW 16-kHz bidirectional isolated DC-DC converter using SiCMOSFET/SBD H-bridge modules. IEEE Transactions on PowerElectronics 2020; 35(10):10013–10025.
(44) Shinohe T. SiC power devices. Toshiba Review 2004; 59(2):49–53.

Yasuhiko Miguchi (Member) received Master’s degree from Kobe
University in 1979. He worked for Toshiba
Corporation, Fuchu Works, from 1979 to
1998. He was a visiting researcher at University of Missouri-Columbia from 1984 to
1986. He was a researcher at United Technologies Research Center, in East Hartford,
Connecticut, from 1998 to 1999. He worked
for Nippon Otis Elevator Company from2000 to January 2020. He is now a researcher at Yokohama
National University. His interests include power electronics andits control. He is a member of SICE (Society of Instrument andControl Engineers), ISCIE (The Institute of System, Control, andInformation Engineers), IEE of Japan, and IEEE.
Hadi Setiadi (Member) received the B.Eng. degree from theBandung Institute of Technology, Bandung,Indonesia, in 2014, and the M.Eng. and
Ph.D. degree from the Tokyo Institute ofTechnology, Tokyo, Japan, in 2016 and2020, respectively. From October 2020 to
May 2022, he was a postdoctoral researcher
and a lecturer at Yokohama National University, Yokohama, Japan. He is now a postdoctoral fellow at Rolls-Royce@NTU Corporae Laboratory, Nagyang
Technological University Singapore.
Hidemine Obara (Member) received the Ph.D. degree in electrical and electronics engineering from Chiba
University, Japan in 2015. From Oct. 2015 toMar. 2016, he was a postdoctoral researcher
at Tokyo Metropolitan University. Since
Apr. 2016, he has been with Yokohama
National University. He is currently an associate professor. His research interests include
circuit topology, system integration, andimplementation for multi-level power converters. Dr. Obara is amember of IEEE and IEE of Japan.

Atsuo Kawamura (Fellow) received the Ph.D. degree fromthe University of Tokyo in 1981. After his
ﬁve-year-stay at the University of MissouriColumbia, he joined Yokohama National
University in 1986. After he became a professor emeritus in 2019, he is a professorof power electronics endowed chair. His
main interests are in power electronics androbotics. He is a Fellow of IEE of Japanand IEEE.

14IEEJ Trans 18: 6–14 (2023)

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A. KAWAMURA ET AL.

Received 18 October 2023; revised 14 December 2023; accepted 2 January 2024. Date of publication 9 January 2024;
date of current version 26 January 2024. The review of this article was arranged by Associate Editor Q. Wei.
Digital Object Identiﬁer 10.1109/OJPEL.2024.3351147

Control Scheme for the Lagging Power Factor
Operation of a Single-Phase Grid-Connected
Inverter Using an Unfolding Circuit
YASUHIKO MIGUCHI (Life Member, IEEE), HIDEMINE OBARA (Member, IEEE),AND ATSUO KAWAMURA (Life Fellow, IEEE)
Yokohama National University, Yokohama, Kanagawa 240-8501, Japan
CORRESPONDING AUTHOR: HIDEMINE OBARA (e-mail: obara-hidemine-mh@ynu.ac.jp).
This work was supported by JSPS KAKENHI under Grant 17H06147.

ABSTRACTA single-phase grid-connected inverter with an unfolding circuit typically consists of a ﬁrststage dc/dc converter, which generates fully rectiﬁed sinusoidal waveforms, and a second-stage unfolding
inverter, which switches every 180° of the line frequency waveform. This converter exhibits low switchingloss and high efﬁciency, and the operating principle of the unfolding inverter typically includes synchronous
voltage and current. However, limited studies have focused on the operation of inverters with power factor(PF) less than unity. Such operations often result in large overshoots and oscillations in the output voltages.
To address this problem, we proposed a novel control scheme that enables leading PF operation without
additional circuitry and overcomes the aforementioned limitations in the previous literature. Thus, this paper
describes a novel control scheme that enables lagging PF operation. Notably, for a lagging PF, a phenomenon
in which the dc voltage inevitably increases immediately after unfolding is known to occur, and herein, thisphenomenon is used in reverse to rapidly decrease the dc current. Consequently, we develop a method to land
the circuit variables at normal mode steady-state value by using reverse-polarity pulse width modulation(PWM)/forward-polarity PWM combination of the unfolding inverter and a virtual PWM inverter in the
proposed controller. The control method is validated using simulations and experiments, and it is found to
facilitate the four-quadrant operation of the unfolding inverter.

INDEX TERMS High efﬁciency, power factor, lagging power factor, single-phase grid-connected inverter,

unfolding inverter, reverse- polarity PWM, virtual PWM inverter, four-quadrant operation.

I. INTRODUCTION

Typically, an inverter with an unfolding circuit consists of aﬁrst-stage dc/dc converter, which generates a fully rectiﬁed
sinusoidal voltage or current waveform, and a second-stage
unfolding inverter, which switches every 180° of the line
frequency waveform and generates a sinusoidal voltage orcurrent [1].
Notably, initial research on unfolding inverters primarily focused on the isolation and miniaturization of passive
components [1], [2], [3], [11], [12], [13], [14], [15], [16],[17], [18]. However, leveraging low switching losses of
unfolding inverters, several studies have now focused on realizing inverters with low total losses [4], [5], [6], [7], [20],[38].

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One example of an inverter application is a grid-connected
inverters used for photovoltaic power generation and other
distributed energy generations. Grid-connected inverters areoften required to provide reactive power as a system support
functions for grid stabilization [19]. Although the grid code is
known to differ across countries, a system may be required to
output reactive power that is 0.484 times the rated real powerwith leading or lagging power factor (PF), as depicted in Fig. 1[19]. This corresponds to PF of 0.9. In summary, providing
reactive power from a lagging PF of 0.9 to a leading PF of 0.9
is sufﬁcient in practice.
In unfolding inverters, inverter devices are switched every
half cycle in synchronization with the voltage zero crossing[1], [6], [7]. Thus, for a unity PF, synchronous voltage and© 2024 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License. For more information, see
https://creativecommons.org/licenses/by-nc-nd/4.0/

145

MIGUCHI ET AL.: CONTROL SCHEME FOR THE LAGGING POWER FACTOR OPERATION OF A SINGLE-PHASE GRID-CONNECTED INVERTERFIGURE 2. Grid-connected inverter based on the HEECS.

TABLE 1. Relationship Between DC/DC Converter Switch States and
Output Voltage
FIGURE 1. Reactive power requirements for distributed energy resources[19].

current zero crossing occur in unfolding inverters. By contrast,
for a non-unity PF, the voltage transient response becomes
oscillatory after unfolding [6], [20]; therefore, appropriate
control is required.
However, only limited studies have focused on the nonunity PF control of unfolding inverters. Some have incorporated external circuits to handle reactive power [8], [9], whilesome others proposed quasi-sinusoidal current reference,
however, the output has very large harmonic contents [10].
In [7], the authors used an unfolding inverter with a multilevel chopper called a high efﬁciency energy conversion
system (HEECS) in the ﬁrst dc/dc converter. Later, for a leading PF operation from the grid-connected inverter perspective(lagging PF from the grid perspective), a new method satisfying the International Electrotechnical Commission (IEC)harmonics regulation based on control alone while maintaining 99.75% class efﬁciency was proposed, and experimentallydemonstrated [39]. However, for a lagging PF from the inverter perspective, no studies have satisﬁed the requirementsof harmonic regulation while maintaining high efﬁciency
through control alone. Min et al. [35] and Han et al. [36]operated an inverter in the pulse width modulation (PWM)
mode for a time period before and/or after voltage zero crossing, which increased switching loss as well and decreased
efﬁciency. Generally, when an unfolding inverter is operated
with a lagging PF, a phenomenon in which the dc capacitor
voltage inevitably increases immediately after the voltage zerocrossing is known to occur, is generally difﬁcult to control.
Here, we propose the reverse use of this phenomenon. First,
the inverter is changed to the freewheeling mode to rapidly decrease the dc inductor current. Next, the dc capacitor voltage
is decreased using reverse/regular-polarity PWM to suppress
transients, and the circuit returns to a steady-state. We analyze
these control operations in detail, and ﬁnally, experiments
demonstrate that the HEECS circuit can be operated in alagging PF mode with high efﬁciency while the harmonics
remain within IEC limits.
The remainder of this paper is organized as follows. Section II reviews the HEECS circuit and its waveforms. In
addition, the control method DBCCL+VC is described [39].
146

Section III describes the problem with the lagging PF operation of an unfolding inverter and proposes a new control
scheme to solve this problem. Section III-A describes dc
voltage rise after unfolding. Section III-B proposes a newcontrol method based on this phenomenon. In addition,
Section III-C proposes a transient response improvement.
Section IV presents the effectiveness of the proposed control scheme using simulations and experiments. Section V
presents comparison with conventional schemes. Finally, Section VI concludes the paper.
II. CONTROL PRINCIPLE OF AN HEECS INVERTER
A. HEECS INVERTER OPERATION [6]Fig. 2 depicts an HEECS-based inverter circuit that is connected to the grid through an ac inductor [6], [21], [24].
Note that the multilevel dc/dc converter consists of switching devices S1 , S2 , S3 , and S4 as well as an LC ﬁlter. Table 1
summarizes the relationships between the switch states andoutputs of the switching network vsw .
If the voltage command to the dc/dc converter is smaller
than E1 , S1 and S2 operate in PWM mode. However, if thevoltage command is larger than E1 and smaller than E1 + E2 ,S2 is always ON; moreover, S3 and S4 operate in PWM mode.
The dc/dc converter is controlled such that the capacitor voltage vc follows the fully rectiﬁed sinusoidal reference voltage.
The unfolding inverter consists of switching devices Sap , San ,Sbp , and Sbn . It switches every 180° electrical degrees of theline frequency waveform. The inverter output voltage vinv isalso a sinusoidal waveform. The voltage waveforms for thecircuit in Fig. 2 are shown in Fig. 3.
B. CONTROL LAWS
1) DIGITAL CONTROL MODEL

Fig. 4 presents the equivalent circuit of an HEECS inverter[20], [21]. The resonance frequency of the LC ﬁlter is on theorder of kilohertz, which is considerably higher than the lineVOLUME 5, 2024

 
F11 F12g, G1 = eAT /2 B1 E = 11
F21 F22g12 g
G0 = A−1 eAT − I B0 = 01
(2)
g02


F = eAT =where F can be expressed as:⎡cos ωn T
F = eAT = ⎣− CL sin ωn T⎤

L
C sin ωn T ⎦cos ωn T

1ωn = √LC

FIGURE 3. Voltage waveforms of the HEECS: (a) dc/dc converter switchingcircuit output voltage, (b) dc capacitor voltage, (c) inverter output voltage.

The capacitor voltage vc can be controlled in two ways:
deadbeat voltage control law (DBVCL) [6], [20] and deadbeat
current control law plus voltage control loop (DBCCL + VC)[22], [23], which have been previously compared in [39]. The
DBVCL has higher gain and larger transient response than
DBCCL + VC; thus only DBCCL + VC is introduced here.
2) DBCCL

The pulse width T(k) of DBCCL is decided such that theinductor current iL (k + 1) at the next sampling instant (k +1)T matches the current reference iLref (k + 1) [22], [23], [24].
Considering the second row of (2), we obtain

FIGURE 4. Equivalent circuit of the HEECS.

iL (k + 1) = F21 vc (k) + F22 iL (k) + g12 T (k) + g02 idc (k)(3)
and solving for T(k) after replacing iL (k + 1) with iLref yields
DBCCL asT (k) = iLre f − F21 vc (k) − F22 iL (k) − g02 idc (k) /g12


1
g02
21
22
− Fg12x (k) +
= − Fg12
iLre f −idc (k)g12
g12

FIGURE 5. PWM pulse waveform.

frequency of 50 or 60 Hz. Furthermore, the sampling control
frequency of the dc/dc converter (20 kHz) is high. The acside transient phenomena are considerably slower than thoseon the dc side. Thus, the ac output circuit of the inverter isreplaced by a dc current source idc . The circuit equation [25],[26] for the equivalent circuit in Fig. 4 is:dx= Ax (t ) + B1 u (t ) + B0 idc
dt(1)

where  x(t ) = viLc (t(t )) , u(t) = output of switching network

A=






0
1/C
0
−1/C
, B1 =, B0 =
−1/L
0
1/L
0

The voltage pulse of the dc chopper is assumed to be centered at the sampling time, as shown in Fig. 5. The width isdeﬁned as T(k) during the sampling period (kT to (k+1)T).
Consequently, the sampled-data model [25], [26] of (1) isx [k + 1] = F x [k] + G1 T [k] + G0 idc [k]VOLUME 5, 2024

= K2 x (k) +1
g02
iLre f −idc (k)
g12
g12

(4)

The ﬁrst, second, and third terms in (4) represent the state
feedback, reference input, and disturbance feed-forward compensation, respectively. Furthermore, a voltage control loop is
added as an outer control loop, as discussed below.
3) DBCCL + VC LOOPA VC loop is added as an outer control loop around the current
control, as shown in Fig. 6. Current reference iLref is generatedusing a proportional controller, as follows:
iLre f = K pv vcre f − vc
(5)
The combination of (4) and (5) is designated as DBCCL +VC. For a more detailed analysis of the control system thatapplies DBCCL + VC, see Appendix B of [39].
Ac current control is also required for grid-connected inverters. A control block diagram is presented in Appendix A.
147

MIGUCHI ET AL.: CONTROL SCHEME FOR THE LAGGING POWER FACTOR OPERATION OF A SINGLE-PHASE GRID-CONNECTED INVERTERFIGURE 6. Control block diagram of DBCCL + VC.

FIGURE 8. Grid-connected inverter using a conventional PWM voltage
source inverter.

FIGURE 9. Simulated waveforms of the conventional PWM grid-connectedvoltage source inverter in lagging PF operation.

FIGURE 7. Simulation waveforms of an HEECS controlled by DBCCL + VC
in lagging PF operation (a) dc capacitor voltage vc , inverter output voltage
vinv , and grid voltage vg , (b) grid current reference iacref , and grid current
iac .

III. PROPOSED CONTROL METHOD AFTER VOLTAGE ZEROCROSSING OF AN HEECS INVERTER WITH LAGGING PFOPERATION
A. PROBLEM OF LAGGING PF OPERATION IN AN HEECSINVERTER AND ITS ANALYSIS

Fig. 7 presents the simulated waveforms of an HEECS controlled by DBCCL + VC during lagging PF operation. The
inverter is simply unfolded every 180°. Circuit conditions arereal power reference Pref = 1600 W, reactive power reference
Qref = −1200 var, PF of 0.8, and a grid voltage of 280 Vrms ,50 Hz. Immediately after unfolding, the dc capacitor voltage
rapidly increases. The voltage controller attempts to regulate
the dc voltage; however, its response is extremely fast, causing
oscillations. Accordingly, the grid current is highly distorted.
The total harmonic distortion (THD) of the grid current is29.8%.
The following section presents analysis of the phenomenon
after voltage zero crossing. For reference, the conventional
PWM voltage source inverter connected to the grid is displayed in Fig. 8, and the typical simulated waveforms ofthe grid voltage vg3 , ac current iac3 , and dc current idc3 ofthe circuit with lagging PF under ideal conditions are depicted in Fig. 9. In the PWM inverter waveforms presented
in Fig. 9, the dc current changes from positive to negative at
148

FIGURE 10. Current path before voltage zero crossing in the lagging PF
mode.

the voltage zero crossing owing to lagging PF. Because thevoltage zero crossing occurs twice during every period of theac line voltage, the voltage changes from negative to positiveat a 0° electrical angle and from positive to negative at 180°.
Here, the 180° case is discussed in detail.
Fig. 10 depicts the current path of HEECS just before thevoltage zero crossing (just before unfolding) during lagging
PF operation. The current ﬂows through the devices Sap and
Sbn . At the voltage zero crossing, the unfolding control circuitprovides ON gate signals to the devices San and Sbp . Fig. 11
depicts the current path immediately after the voltage zerocrossing (immediately after unfolding). Currents pass throughthe diode part of San and the diode part of Sbp , and the dc
capacitor is fed from the right by the current −idc , whose
magnitude is equal to the ac current at that point. By contrast,
the dc capacitor is fed from the left by the dc inductor current
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FIGURE 11. Current path just after voltage zero crossing in the lagging PF
mode.

iL . Currents ﬂow into the capacitor from both the left and rightsides, and the capacitor voltage increases sharply. The voltage
rise depicted in Fig. 7 originates from this circuit behavior,and the voltage increase after unfolding is inevitable. This
makes it difﬁcult to control unfolding inverters during lagging
PF operation; however we attempted to use this phenomenon
in reverse. The following subsection describes the control
sequence immediately after unfolding.
B. PROPOSED CONTROL SEQUENCE AFTER VOLTAGE ZEROCROSSING

Fig. 12 presents the control sequence timing chart after voltage zero crossing. As shown in Fig. 12, unfolding occurs at
t0 . In Section S1, the circuit is as shown in Fig. 11, the dc
capacitor voltage sharply increases. In Section S2, after t1 , theinverter is operated in the freewheeling mode, as shown in
Fig. 13. One purpose of this mode is to prevent the large dc
voltage from affecting the ac current. Another purpose of thismode is to control the dc inductor current independently of acside. In Fig. 13, ON gate signals are provided to the devices
in the upper arms; however, such ON gate signals can be
assigned to the devices in the lower arms. In Fig. 12, unfolding
is executed for only one cycle; however, unfolding can becontinued for two cycles to rapidly reduce the dc inductor
current in Section S2.
Fig. 14 presents the equivalent circuit of the dc/dc converterin section S2. For example, when the switching frequency is
20 kHz, the switching circuit in Fig. 14 can control the dc
inductor current by outputting pulses with a width T in therange of 0–50 μs as shown in Fig. 5 for each cycle.
In the ﬁrst cycle in Section S2, the circuit outputs a pulse
with T = 0, corresponding to the minimum voltage, thus
decreasing the dc inductor current rapidly by applying a voltage difference between the switching circuit output and theboosted dc capacitor voltage. The control objective of theSection S2 is to decrease the dc inductor current iL from theiac value at the start of unfolding to the –iac value, the same
absolute value as in the reverse polarity. When the dc inductor
current iL approaches –iac , the circuit outputs partial duty T2
so that iL matches – iac at the ﬁnal time t3 of Section S2.
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Then, in Section S3 of Fig. 12, the inverter is operated
by a combination of the reverse-polarity PWM and regularpolarity PWM modes. The reverse-polarity PWM mode outputs PWM pulses of the opposite polarity as the output
polarity of the unfolding inverter in the 180° section. The
regular-polarity PWM mode outputs PWM pulses of the samepolarity as the output polarity of the unfolding inverter in the
180° section. The current path in the reverse-polarity PWM
mode is shown in Fig. 15. For the original polarity of theunfolding inverter, ON gate signals are assigned to San and
Sbp . In the reverse-polarity PWM mode, ON gate signals are
assigned to Sap and Sbn . Current idc ﬂows to the right sideof the capacitor. In addition dc inductor current iL ﬂows to
the left side of the capacitor because the current polarity isalready reversed. Therefore, the capacitor voltage decreases
rapidly. When the capacitor voltage approaches the desired
value, reverse/regular-polarity PWM is used as needed. In
the regular-polarity PWM, the inverter outputs the originalpolarity. The current path of regular-polarity PWM is shownin Fig. 16. Note that the direction of the dc inductor current
is opposite to that immediately after unfolding described inFig. 11. Inverter gate pattern and capacitor voltage waveformin the reverse-polarity PWM mode are shown in Fig. 17. Here,U is pulse width of the unfolding inverter output pulse.
Current ﬂows out both to the left and right directions during
the section [tu1 , tu2 ]. To the right direction, current idc = + iac
ﬂows. Current iL ﬂows to the left direction. The dc inductor
current iL is controlled to reach abs (iac ) at the end of Section
S2. Therefore, the slope of the capacitor voltage during [tu1 ,tu2 ] is as follows:
dvc /dt = − 2 ∗ abs (iac ) /C
By contrast, sections [tu0 , tu1 ] and [tu2 , tu3 ] are in the freewheeling mode. Because idc = 0, the slope of the capacitor
voltage in these sections is
dvc /dt = − abs (iac ) /C
The average slope of the capacitor voltage over the entire
section [tu0 , tu3 ] is as follows:T − UU
abs (iac ) −abs (iac ) /C
−2
TT
By adjusting U from zero to T, the slope can be adjusted
from −abs(iac )/C to −2abs(iac )/C.
Fig. 18 presents the inverter gate pattern and capacitor
voltage waveform in the regular-polarity PWM mode. We
assume that the sign of U is positive for reverse-polarity
PWM, and negative for regular-polarity PWM. In section[tu1 , tu2 ], the input and output currents for the capacitor arebalanced; thus the capacitor voltage is constant. However,sections [tu0 , tu1 ] and [tu2 , tu3 ] are in the freewheeling mode,and the slope of the capacitor voltage in these sections is asfollows:
dvc /dt = − abs (iac ) /C
149

MIGUCHI ET AL.: CONTROL SCHEME FOR THE LAGGING POWER FACTOR OPERATION OF A SINGLE-PHASE GRID-CONNECTED INVERTERFIGURE 12. Timing chart after voltage zero crossing.

FIGURE 13. Freewheeling mode for Section S2.
FIGURE 14. Equivalent circuit of the dc/dc converter during Section S2.

The average slope of the capacitor voltage over the entire
section [tu0 , tu3 ] is as follows:
T + Uabs (iac ) /C−T
By adjusting U from zero to −T, the slope of the capacitor
voltage can be adjusted from −abs(iac )/C to zero.
Table 2 summarizes the inverter pulse pattern, capacitor
voltage behavior, and sign of U for various modes, including
the reverse-polarity PWM mode, no-pulse mode, regularpolarity PWM mode, and regular-polarity whole- pulse mode.
By adjusting U from T to −T, the slope of the capacitor
voltage can be continuously adjusted.
150

In practice, the capacitor voltage and dc inductor current
are governed by (2). In other words, this system controls
two outputs, namely the capacitor voltage and dc inductor
current, using two inputs, T and U, during Section S3, as
illustrated in Fig. 19. To make the capacitor voltage and dc
inductor current reach the target values at return to the normalmode, we need to solve for U and T. Appendix B describes
in detail the equation with U and T. In the ﬁnal cycle ofSection S3 in Fig. 10, we aim for a smooth transition to thenormal mode of Section S4 by using U and T obtained bysolving this equation.
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FIGURE 15. Current path of the reverse-polarity PWM mode in Section S3.

FIGURE 18. Waveforms in the regular-polarity PWM mode.

TABLE 2. Relation Between Inverter Pulse Pattern and Slope of Capacitor
Voltage

FIGURE 16. Current path of the regular-polarity PWM mode in Section S3.

FIGURE 17. Waveforms in the reverse-polarity PWM mode.

C. IMPROVEMENT IN TRANSIENT RESPONSE AFTERUNFOLDING
1) TRANSIENT RESPONSE

Fig. 20 presents an example of the simulation results obtainedusing the control sequence proposed in Section III-B. The
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circuit conditions are Pref = 1600 W, Qref = −1200 var, PF =0.8, and Vg = 280 Vrms . At the end of Section S3 in Fig. 12,
at t = t5 , the capacitor voltage reference vcref and dc inductor
current reference iLref in Fig. 6 are used as the target values forthe dc capacitor voltage and dc inductor current, respectively.
In Fig. 20, unfolding is executed over two cycles in Section
S1, and the capacitor voltage vc increases rapidly as shownin Fig. 11. In Section S2, freewheeling mode is conducted
for three cycles. The dc inductor current iL rapidly decreases
and reaches the target value −abs(iac ) at the end of Section
S2. Section III presents the reverse-polarity PWM, and thecapacitor voltage is decreased as intended.
151

MIGUCHI ET AL.: CONTROL SCHEME FOR THE LAGGING POWER FACTOR OPERATION OF A SINGLE-PHASE GRID-CONNECTED INVERTERFIGURE 19. Input/output relation in Section S3.

FIGURE 22. Circuit diagram of the proposed virtual PWM inverter.

Therefore, the target values to realize a smooth transition
to the normal mode without transients should not be vcref
and iLref , which were adopted in Fig. 20, but should be thenormal mode steady-state values of vc and iL at the end of
Section S3. However, the controller of this system controls theunfolding sequence and thus cannot predict the normal mode
steady-state values.
2) VIRTUAL PWM INVERTERFIGURE 20. Example of simulation result.

To solve this problem, we propose a virtual PWM inverter, anda circuit diagram is shown in Fig. 22. The differences with
the HEECS circuit diagram in Fig. 2 are as follows: (a) theLC ﬁlter in Fig. 2 is moved to the ac side in Fig. 22, and (b)the PWM function of the dc/dc converter in Fig. 2 is moved
to the PWM inverter in Fig. 22. To distinguish it from a realHEECS circuit, the capacitor voltage, inductor current, andac current of the virtual circuit are denoted as vc2 , iL2 , andiac2 , respectively. The discrete-time equation of this virtual
circuit is the same as in (2), except that idc changes to iac2 .
The equation is as follows:x2 [k + 1] = F x2 [k] + G1 T2 [k] + G0 iac2 [k]FIGURE 21. Simulation example: dynamics between vcref and vc .
(Conditions are the same as those for Fig. 20).

However, a small undershoot is observed in the capacitor
voltage waveform after returning to the normal mode in Section S4. Hereafter, this phenomenon is discussed. In Fig. 6, a
relationship can be established between the current reference
iLref and the current value iL . The transfer function from iLref
to iL is as follows:iL /iLre f = 1/z
as calculated in (A2-3) of Appendix A in [39].
In addition, a dynamic relationship exists between the capacitor voltage reference vcref and capacitor voltage vc . Itstransfer function is as follows:
K pv gr (z + 1)vc
= 2 vcre fz + K pv gr − 1 z + K pv gr
Although iL and vc follow the references iLref and vcref ,respectively, they do not exactly match, and a phase lag exists.
Fig. 21 shows a simulation example, in which a phase lag isobserved between vcref and vc .
152

where
x2 (k) =(6)
vc2 (k)iL2 (k)T2 is the pulse width of the virtual PWM inverter and canbe both positive and negative. Therefore, the same structure
control law, DBCCL + VC, described in (4) and (5), canbe used to control the capacitor voltage vc2 , and the samestructure control law can be used to control the ac current iac2 .
The virtual PWM inverter does not exhibit complex phenomena related to unfolding; thus, the circuit exhibits a smooth
waveform, even after the voltage zero crossing.
Fig. 23 shows the control block diagram, which includes
both the real HEECS inverter and the virtual PWM inverter. In
Fig. 23, part of the virtual PWM inverter + LC ﬁlter is realizedby calculating (6) within the controller. Part of the virtual gridtie circuit is calculated using a simple discrete equation.
T 
vc2 − vg
(7)
iac2 (k + 1) = iac2 (k) +Lg
This equation is deduced from the circuit equation of thevirtual grid-tie circuit illustrated in Fig. 24 by simple discretization. The ac current reference for the current controller
VOLUME 5, 2024

FIGURE 23. Control block diagram including both the real model and virtual model.

FIGURE 24. Circuit diagram of the virtual grid-tie circuit.

iacref is common for the upper real circuit and the lower virtual
circuit in Fig. 23. A second current controller is used to control
the virtual ac current iac2 . In addition, a second voltage controller is used to control the virtual PWM inverter capacitor
voltage. The structure and gains of the second current controller and voltage controller are the same as those of the realcontrollers. We propose adopting abs(vc2 ) and −abs(iL2 ) fromthe virtual circuit as target values of the dc capacitor voltage
and dc inductor current, respectively, at the end of Section S3
in Figs. 12 and 20.
Note that the circuit parameters in the virtual circuit
may differ from those in the real HEECS circuit owing tofabrication errors and age-related deterioration. In addition,
numerical errors may accumulate over long time of operationsin the virtual circuit. Thus, it is desirable that the variables ofthe virtual circuit be reset by the values of the corresponding
real circuit variables at every speciﬁed period to prevent numerical error accumulation.
Fig. 25 shows the simulation results when the target values
from the virtual circuit are adopted. At the start of the normalmode, the dc capacitor voltage and dc inductor current landat the target values determined from the virtual circuit, andtransients are not observed.
Fig. 26 shows the simulation results of the ac current reference and ac current. A large overshoot can be observed in
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FIGURE 25. Simulation result when the target values are determined fromthe virtual circuit.

FIGURE 26. Simulation result of ac current (the same condition as Fig. 25).

the ac current. To address this overshoot, another device isrequired, which is discussed in the next subsection.
3) UNFOLDING TIMING SHIFT

Fig. 27 presents magniﬁed waveforms near the voltage zerocrossing. The ac current iac increases in Sections S2 and S4,
153

MIGUCHI ET AL.: CONTROL SCHEME FOR THE LAGGING POWER FACTOR OPERATION OF A SINGLE-PHASE GRID-CONNECTED INVERTERFIGURE 27. Zoomed-in waveforms near the voltage zero crossing.

resulting in an overshoot. In Section S3, the inverter voltage
is manipulated to decrease the dc capacitor voltage rapidly,
and it is natural for the inverter voltage to exceed the gridvoltage. So far, we have been unfolding at the voltage zerocrossing. Owing to the small phase difference between the
inverter and grid voltages, after the inverter voltage crosses
zero and becomes negative, the grid voltage also becomes
negative. For leading PF operation, after unfolding at the inverter voltage zero crossing, an all-conduction mode occurs,
and the dc inductor current is rapidly increased during the
all-conduction mode. This means that unfolding at the voltage
zero crossing is required for a leading PF operation [39].
However, for lagging PF operation, no speciﬁc approach is
required for unfolding at the voltage zero crossing. Even if
the unfolding timing is shifted, once the ac current is positive
during unfolding, the dc capacitor voltage quickly increases,
and the control sequence described in Section III-B can be
executed.
Therefore, a shift in forward unfolding timing is proposed.
A sinusoidal wave observer with the inverter voltage as the
input is discussed as follows [39].
v (k)v
ix (k + 1)
(8)
= Fs ix+ Kixy (vinv − v
ix )
v
v
iy (k + 1)
iy (k)where
cos ωTFs =sin ωT− sin ωTcos ωTv

ix is the estimated value of vinv , and v
iy is the estimated valueof the orthogonal component. These components in steadystate can be expressed as sinusoidal functions as follows:vix = Vi cos (ωkT + ϕ)viy = Vi sin (ωkT + ϕ)154

FIGURE 28. AC current waveforms with unfolding timing shift:(a) two-cycle forward, (b) three-cycle forward, and (c) four-cycle
forward.

A sinusoidal wave that leads the inverter voltage by phase
ε can be expressed asv
i = Vi cos (ωkT + ϕ + ε)= vix cos ε − v
iy sin ε
By unfolding at the moment when this waveform crosses
zero, the unfolding timing can be shifted forward.
When the switching frequency is 20 kHz, one cycle is 50
μs. Ac current waveforms when unfolding is shifted forward
by two cycles (100 μs), three cycles (150 μs), and four cycles(200 μs) are shown in Fig. 28. In three-cycle forward case,ac current reaches the ac current reference exactly; thus threecycle forward is adopted.
Fig. 29 shows a small zoomed-out ac current waveformwith three-cycle forward unfolding shift. This is much better
than that shown in Fig. 26; however, a small overshoot is stillobserved.
As shown in Fig. 30, the current control block diagram, ac
current iac is input to the sinusoidal wave observer, then theorthogonal components are obtained, the d-axis and q-axis
VOLUME 5, 2024

FIGURE 29. AC current waveform with three-cycle forward unfolding
timing.

FIGURE 32. Simulation result.

FIGURE 30. Current control block diagram.

FIGURE 33. Experimental setup.

FIGURE 31. AC current signal selection to the sinusoidal wave observer in
Fig. 30.

components are calculated, and these are compared with thecurrent references idref and iqref ; the errors are then input toproportional-integral (PI) controllers. After unfolding, the ac
current inherently deviates from the ac current reference until
the system returns to the normal mode; thus the error is accumulated in the PI controllers. The accumulated errors cause asmall overshoot, as shown in Fig. 29.
We propose that during the unfolding control sequence ofSections S1, S2, and S3 in Fig. 12, we provide an ac current
signal as if the ac current is controlled sinusoidal. Fig. 31
presents an ac current signal selection block diagram. Here,
iac2 is the virtual ac current in Fig. 23. Switch SWiac is connected to the iac2 side during the unfolding control sequence;otherwise, it is connected to the iac side. Fig. 32 shows theVOLUME 5, 2024

FIGURE 34. Circuit under test.

simulation results when the scheme shown in Fig. 31 is used.
The overshoot shown in Fig. 29 is eliminated.
IV. SIMULATION AND EXPERIMENT RESULTS
A. SET-UP

Figs. 33 and 34 present the experimental setup and circuitunder testing, respectively. The test circuit is installed in athermostatic chamber. Table 3 lists the circuit parameters used
155

MIGUCHI ET AL.: CONTROL SCHEME FOR THE LAGGING POWER FACTOR OPERATION OF A SINGLE-PHASE GRID-CONNECTED INVERTERTABLE 3. Circuit Parameters

TABLE 4. List of Equipment

FIGURE 36. Simulation result: Zoomed-in waveforms near unfolding:(a) Capacitor voltage vc , grid voltage vg , and inverter voltage vinv ; (b) dc
inductor current iL and ac current iac .

FIGURE 37. Simulation result: Ac current reference iacref and ac current iac .
FIGURE 35. Simulation result in the steady-state: (a) Capacitor voltage vc ,grid voltage vg , and inverter voltage vinv ,; (b) dc inductor current iL , and ac
current iac .

in the simulations and experiments. Table 4 summarizes theequipment used in the experiments.
B. SIMULATION

Fig. 35 presents the steady-state simulation results for Pref =1600 W, Qref = −1200 var, PF = 0.8, and Vg = 280 Vrms .
Fig. 36 shows the magniﬁed waveforms near unfolding. During the unfolding sequence period (USP), two-cycle unfolding
mode, three-cycle freewheeling mode, reverse-polarity PWM
mode, and regular-polarity PWM mode are sequentially executed. At the end of the USP, the capacitor voltage and dc
inductor current settle at the target values, and transients inthe normal mode are not observed. Fig. 37 shows the ac current reference and ac current. Other than USP, the ac current
follows the ac current reference well, and the THD is 3.35%.
156

FIGURE 38. Experimental results: Steady-state waveforms.

This is much better than that shown in Fig. 7, where unfolding
is simply conducted.
C. EXPERIMENTAL VERIFICATION

Fig. 38 shows the steady-state experimental waveform. The
circuit conditions are the same as those shown in Fig. 35.
Fig. 39 shows the magniﬁed waveforms near unfolding. Similar to Fig. 36, the unfolding sequence is executed as intended.
VOLUME 5, 2024

FIGURE 39. Experimental results: Waveforms near zero crossing.

FIGURE 40. Experimental results: Zoomed-in ac current (in black) and ac
current reference (in blue).

FIGURE 43. Experimental results: Transient response.

FIGURE 41. Harmonic contents of the ac current (PF = 0.9).

FIGURE 42. Harmonic contents of the ac current (PF = 0.8).

Fig. 40 shows the ac current, and the THD is 4.15%. No
overshoot is observed in the ac current.
Table 5 lists the steady-state characteristics with various
real and reactive powers with a total VA = 2000 VA, withthe left and right halves of the table showcasing the powering and regenerating modes, respectively. The efﬁciency
is measured using a very accurate virtual transformer-based
VOLUME 5, 2024

back-to-back asynchronous loss measurement method [29].
The measurement accuracy is approximately 0.006%. The
efﬁciency decreases with decreasing PF, but still exceeds 99%
even with PF = 0.5.
The harmonic contents of the ac current for the cases of
PF = 0.9 and PF = 0.8 are described with upper limit values
speciﬁed by IEC61727 in Figs. 41 and 42, respectively. The
harmonic contents of the ac current without the new control
scheme is shown in each ﬁgure. The fundamental component(100%) is abbreviated. The black line shows the upper limits
by IEC61727. Harmonic contents with the control case arein blue, those without control are in orange. Therefore, theharmonic contents by the proposed scheme are well below
the limit. The harmonics without the new control scheme are
signiﬁcantly worse than those with the proposed scheme.
Fig. 43 illustrates the transient responses from Pref = 1600
W and Qref = −1200 var to Pref = −1600 W and Qref =−1200 var. As discussed in Appendix A, d- and q-axis current
control is achieved by estimating the virtual orthogonal component using a sinusoidal wave observer. The d- and q-axis
currents are shown in Fig. 43. The d-axis current follows thed-axis current reference within 7 ms.
V. COMPARISON BETWEEN THE CONVENTIONAL AND
PROPOSED SCHEMES

Table 6 shows comparison of non-unity power factor operation schemes. As already stated in the introduction section,
Tian et al. [8] and Fonkwe [9] need additional circuit to handle
reactive power. Han et al. [34] connects “dc link” circuit when157

MIGUCHI ET AL.: CONTROL SCHEME FOR THE LAGGING POWER FACTOR OPERATION OF A SINGLE-PHASE GRID-CONNECTED INVERTERTABLE 5. Experiment Result: Steady-State Characteristics (Total VA = 2000 VA)

TABLE 6. Comparison of Non-Unity Power Factor Operation of Unfolding Inverters

the inverter needs to output reactive power, and the inverter
operates as the conventional PWM inverter. Li et al. [10] uses
quasi-sinusoidal current reference, and it results in very large
distortion. Min et al. [35], Han [36], and Renaudineau et al.
[37] use partial PWM operation (a few milliseconds) before
or after voltage zero crossing, thus it increases switching loss.
158

Combining the leading pf operation previously reported in[39] and the lagging pf operation proposed in this paper, ourscheme achieves 0 to 1 leading/lagging pf operation without
additional circuit.
A comparison of the PF–THD relation is shown in Fig. 44.
Li [10] applied a quasi-sinusoidal waveform (QSW) current
VOLUME 5, 2024

different ratings in the same condition is difﬁcult. Nonetheless, the efﬁciency of the proposed inverter is signiﬁcantly
higher than those reported in previous studies.
VI. CONCLUSION

FIGURE 44. Comparison of THD.

FIGURE 45. Comparison of efﬁciency.

reference to handle the reactive power. The orange curve represents the theoretical THD obtained using the QSW scheme.
The green dot presents the experimental data obtained using
the QSW method with a PF = 0.95 and THD = 16.7%. The
blue curve shows a plot of the THD data in the powering modeof the proposed method in Table 5. For the QSW scheme, theTHD exceeds 5% with a PF > 0.995. Additionally, the range
of PF operation is limited to >0.86. By contrast, the THD of
the proposed method is <5% within the range of PF operationof 0.7–1.
Furthermore, research presenting efﬁciency data is scarce.
Fig. 45 depicts a comparison of the efﬁciency data. The orange curve shows the data reported by Min et al. [35], which
requires no additional circuit. The green curve shows the datareported by Han et al. [36], and the red curve shows that
by Renaudineau et al. [37]. The black dot shows one point
measurement by Zhao et al. [4]. The data in [4], [35], [36],and [37] are measured at a unity PF. The data in [37] containmeasurements for more than 3000 W, but these efﬁciency
values are lower and are omitted in this graph. The blue curveshows the data of the proposed scheme plotted using Table 5,with total VA = 2000 VA, indicating variable PF. For instance,
at 1617 W on the horizontal axis (real power), the PF = 0.809,
which can be veriﬁed from Table 5. The inverter ratings in[4], [35], [36], and [37] were 320, 500, 5600, and 1000 W,
respectively. Hence, comparing the efﬁciency of inverters withVOLUME 5, 2024

Theoretical analysis and simulations are performed to clarify
that the proposed novel control scheme can be used to operate grid-connected unfolding inverters with a lagging PF.
Furthermore, experiments are conducted to verify the simulation results. When the unfolding inverter is operated with alagging PF, and the inverter is unfolded at voltage zero crossing, dc voltage quickly increases. Using this phenomenon,
the dc inductor current is reduced to the opposite polarity
during the freewheeling mode, and the dc voltage is reduced inreverse-/regular-polarity PWM mode. Moreover, target values
for a smooth return to the normal mode are calculated using
a virtual PWM inverter. In addition, the unfolding timing isslightly shifted forward to reduce the ac current overshoot.
Compared with conventional methods, our proposed scheme
deals with reactive power using only control, and no additional circuit is required; however, only a few PWM cycles are
required. The THD of our scheme is much smaller than thatof conventional methods. Based on the reactive power operation range described in Fig. 1, grid-tie inverters are deemed
essential to operate from a lagging 0.9 PF to a leading 0.9
PF. Within this range, the THD of the inverter is within 5%.
If the THD constraint is to be neglected, the PF operation
range of our inverter covers the entire range from PF = -1
to PF = + 1, as shown in Table 5. Thus, an unfolding inverter
can be operated for both leading [39] and lagging PF. In
addition, both powering and regenerating are possible; thus,
it is veriﬁed that an unfolding inverter can be operated infour-quadrant operation. The harmonics are compliant withgrid code IEC61727. The efﬁciencies are 99.76% with PF =1.0 and 99.50% with PF = 0.5, which are very high.
APPENDIX A
CURRENT CONTROL OF A GRID-CONNECTED INVERTER

When an HEECS is applied to a grid-connected inverter, theinverter output voltage is synchronized with the grid voltage,
and the real and reactive output powers are controlled to matchthe command values, as shown in the control block diagram in
Fig. 46. The current reference generator calculates the current
references idref and iqref from the real power reference Pref , thereactive power reference Qref , and the grid electrical angle θ gdetected by the phase-locked loop (PLL). The ac current iac is
input into a sinusoidal wave observer [39], and the orthogonalcomponents are estimated and converted into id and iq . These
are compared with the current references idref and iqref , and theerrors serve as inputs for the current controllers. The output∗ , of the x-axis controller becomes the inverter voltsignal, vinv
∗ is used to select the switching
age command. The sign of vinv∗
pattern of the unfolding inverter. The absolute value of vinv
becomes the voltage reference to the voltage controller of the
dc/dc converter.
159

MIGUCHI ET AL.: CONTROL SCHEME FOR THE LAGGING POWER FACTOR OPERATION OF A SINGLE-PHASE GRID-CONNECTED INVERTERFIGURE 46. Control block diagram of current control for the grid-connected inverter based on HEECS.

The voltage control block shown in Fig. 46 generates a fullyrectiﬁed sinusoidal voltage that is synchronized with the gridvoltage. This block is realized by DBCCL + VC (Fig. 7).
APPENDIX BEQUATION OF U AND T FOR SMOOTH LANDING TO
THE NORMAL MODE

In general, a time delay exists between the detection andthe control pulse output, and a one-step state prediction isrequired. In other words, the controller detects state values at
t = kT, predicts state values at t = (k + 1)T, calculates thedesired output pulse width to be output in the time section [(k+ 1)T, (k + 2)T], sets the pulse width on the hardware registerat t = (k + 1)T, and aims for the control variable at t = (k +2)T to match the target value.
The state values at t = (k + 2)T can be predicted as follows:vc (k + 1)vc (k + 2)
=F 
+ G1 T + G0 i
dc (k + 1)iL (k + 2)
iL (k + 1)
(A-1)
The dc current when the reverse/regular-polarity PWM
mode is used is calculated using




(A-2)
i
dc (k + 1) = U/T · iac (k + 1)
Substituting this into (A-1),
 




T
g11 g01 iac (k + 1) /Tx̂ (k + 2) = F x̂ (k + 1) +Ug12 g02 iac (k + 1) /TT= Fx̂ (k + 1) + G̃
(A-3)
U
Replacing the predicted values at t = (k + 2)T with thetarget values xref (k + 2) and solving equation for T and U,
we obtain



T
(A-4)
= G̃−1 xre f (k + 2) − F x̂ (k + 1)
U
Here, a positive U is interpreted as reverse polarity, and anegative U is interpreted as regular polarity.
160

ACKNOWLEDGMENT

The authors express their appreciation to Dr. Pham Van Long
(Yokohama National University) for his contributions to theexperiments.

REFERENCES[1] S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, “A review of single-phasegrid-connected inverters for photovoltaic modules,” IEEE Trans. Ind.
Appl., vol. 41, no. 5, pp. 1292–1306, Sep./Oct. 2005.
[2] M. F. Schlecht, “A line interfaced inverter with active control of theoutput current waveform,” in Proc. IEEE Power Electron. Specialist
Conf., 1980, pp. 234–241.
[3] I. J. Pitel, “Phase-modulated resonant power conversion techniques forhigh frequency link inverters,” IEEE Trans. Ind. Appl., vol. IA-22, no. 6,
pp. 1044–1051, Nov. 1986.
[4] Z. Zhao, M. Xu, Q. Chen, J.-S. Lai, and Y. Cho, “Derivation, analysis,
and implementation of boost-buck converter based high-efﬁciency PV
inverter,” IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1304–1313,
Mar. 2012.
[5] O. Husev, O. Matiushkin, D. Vinnikov, C. Roncero, E. RomeroCadaval, and L. Kutt, “Buck-boost inverter as a novel solution for
single-phase PV systems,” in Proc. IEEE IECON 44th Annu. Conf. Ind.
Electron. Soc., 2018, pp. 6116–6121.
[6] A. Kawamura, S. Nagai, S. Nakazaki, S. Ito, and H. Obara, “A very highefﬁciency circuit topology for a few kW inverter based on partial power
conversion principle,” in Proc. IEEE Energy Convers. Congr. Expo.,
2018, pp. 1308–1313.
[7] A. Kawamura, S. Nakazaki, S. Ito, S. Nagai, and H. Obara, “Twobattery HEECS inverter with over 99.7% efﬁciency at 2.2kW output andmeasurement accuracy based on loss breakdown,” IEEJ J. Ind. Appl.,
vol. 9, no. 6, pp. 663–673, 2020, doi: 10.1541/ieejjia.20001291.
[8] F. Tian, K. Siri, and I. Batarseh, “A new single-staged bi-directional
high-frequency link inverter design,” in Proc. IEEE Ind. Appl. Soc.
Annu. Meeting, 2006, pp. 1663–1666.
[9] E. Fonkwe, J. Kirtley, and J. Elizondo, “Flyback micro-inverter withreactive power support capability,” in Proc. IEEE Workshop Control
Model. Power Electron., 2016, pp. 1–8.
[10] D. Li, C. N. M. Ho, L. Liu, and G. Escobar, “Reactive power control forsingle-phase grid-tie inverters with quasi-sinusoidal waveform,” IEEE
Trans. Sustain. Energy, vol. 9, no. 1, pp. 3–11, Jan. 2018.
[11] X. Li and A. K. S. Bhat, “A utility-interfaced phase-modulated highfrequency isolated dual LCL DC/AC converter,” IEEE Trans. Ind.
Electron., vol. 59, no. 2, pp. 1008–1019, Feb. 2012.
[12] U. R. Prasanna and A. K. Rathore, “Current-fed interleaved phasemodulated single-phase unfolding inverter: Analysis, design, and experimental results,” IEEE Trans. Ind. Electron., vol. 61, no. 1, pp. 310–319,
Jan. 2014.
VOLUME 5, 2024

[13] D. Meneses, O. Garcia, P. Alou, J. A. Oliver, and J. A. Cobos, “Gridconnected microinverter with primary-parallel secondary series transformer,” IEEE Trans. Power Electron., vol. 30, no. 9, pp. 4819–4830,
Sep. 2015.
[14] Y. Li and R. Oruganti, “A low cost ﬂyback CCM inverter for AC
module application,” IEEE Trans. Power Electron., vol. 27, no. 3,
pp. 1295–1303, Mar. 2012.
[15] R. Hernandez-Vidal, H. Renaudineau, and S. Kouro, “Sub-module
photovoltaic microinverter with cascaded ﬂybacks and unfolding Hbridge inverter,” in Proc. IEEE 26th Int. Symp. Ind. Electron., 2017,
pp. 1035–1040.
[16] Q. Surirey, R. Hernandez-Vidal, H. Renaudineau, S. Kouro, and B.
Cabon, “Sub-module photovoltaic microinverter with cascaded pushpull and unfolding H-bridge inverter,” in Proc. IEEE Southern PowerElectron. Conf., 2017, pp. 1–6.
[17] S. M. Tayebi, W. Xu, H. Wang, R. Yu, Z. Guo, and A. Q. Huang, “Asingle-stage isolated resonant SiC DC/AC inverter for efﬁcient highpower applications,” in Proc. IEEE Appl. Power Electron. Conf. Expo.,
2020, pp. 399–404.
[18] Y.-W. Cho, W.-J. Cha, J.-M. Kwon, and B.-H. Kwon, “High-efﬁciency
bidirectional DAB inverter using a novel hybrid modulation for standalone power generating system with low input voltage,” IEEE Trans.
Power Electron., vol. 31, no. 6, pp. 4138–4147, Jun. 2016.
[19] S. Xu, Y. Xue, and L. Chang, “Review of power system support
functions for inverter-based distributed energy resources-standards,
control algorithms, and trends,” IEEE Open J. Power Electron., vol. 2,
pp. 88–105, 2021.
[20] S. Nagai, S. Nakazaki, S. Ito, H. Obara, and A. Kawamura, “Full-wave
rectiﬁed waveform generation using deadbeat voltage control for DC/DC buck converters to realize high efﬁciency inverter,” in Proc. IEEE
20th Eur. Conf. Power Electron. Appl., 2018, pp. P.1–P.9.
[21] Y. Miguchi, Y. Nasu, H. Obara, and A. Kawamura, “Current controlof very high efﬁciency single-phase grid-connected inverter (HEECS),”in Proc. IEEJ Semicond. Power Converter Committee Meeting, 2020,
pp. 20–128.
[22] S. Mizushima, A. Kawamura, I. Yuzurihara, A. Takayanagi, and R.
Ohma, “Development of DC-DC converter for high/low pulse voltage
output using deadbeat control,” in Proc. IEEE Int. Future Energy Electron. Conf., 2015, pp. 1–6.
[23] Y. Kosode, H. Obara, A. Kawamura, Y. Hosoyamada, T. Suenaga, andI. Yuzurihara, “High performance transient response of high/low pulse
voltage using two-phase interleaved DC-DC buck converter under half
sampling time deadbeat control,” IEEJ J. Ind. Appl., vol. 9, no. 4,
pp. 1–9, 2020.
[24] Y. Miguchi, H. Setiadi, Y. Nasu, H. Obara, and A. Kawamura,“Leading power factor operation of very high efﬁciency single-phasegrid-connected inverter (HEECS),” in Proc. IEEJ Ind. Appl. Division
Meeting, 2021, vol. 1, pp. 127–130.
[25] K. P. Gokhale, A. Kawamura, and R. G. Hoft, “Dead beat microprocessor control of PWM inverter for sinusoidal output waveform synthesis,”IEEE Trans. Ind. Appl., vol. IA-23, no. 3, pp. 901–910, Sep. 1987.
[26] A. Kawamura, T. Haneyoshi, and R. G. Hoft, “Deadbeat controlled
PWM inverter with parameter estimation using only voltage sensor,”IEEE Trans. Power Electron., vol. 3, no. 2, pp. 118–125, Apr. 1988.
[27] A. A. Girgis, W. B. Chang, and E. B. Makram, “A digital recursive
measurement scheme for on-line tracking of power system harmonics,”
IEEE Trans. Power Del., vol. 6, no. 3, pp. 1153–1160, Jul. 1991.
[28] K. De Brabandere et al., “Design and operation of phase-locked loopwith Kalman estimator-based ﬁlter for single-phase applications,” inProc. IEEE 32nd Annu. Conf. Ind. Electron., 2006, pp. 525–530.
[29] A. Kawamura, Y. Nasu, Y. Miguchi, H. Setiadi, and H. Obara, “Proposalof virtual transformer-based back-to-back asynchronous loss measurement using one set of measurement instruments and the veriﬁcation,”
IEEJ J. Ind. Appl., vol. 11, no. 1, pp. 175–184, 2022.
[30] D. W. Novotny and T. A. Lipo, Vector-Control and Dynamics of AC
Drives. Oxford, U.K.: Clarendon, 1996.
[31] Y. Han, M. Luo, X. Zhao, J. M. Guerrero, and L. Xu, “Comparative
performance evaluation of orthogonal-signal-generators-based singlephase PLL algorithms–A survey,” IEEE Trans. Power Electron., vol. 31,
no. 5, pp. 3932–3944, May 2016.
[32] S. Golestan, J. M. Guerrero, and J. C. Vasquez, “Single-phase PLLs:
A review of recent advances,” IEEE Trans. Power Electron., vol. 32,
no. 12, pp. 9013–9030, Dec. 2017.

VOLUME 5, 2024

[33] Y. Lei et al., “A 2 kW single-phase, 7-level, GaN inverter with active energy buffer achieving 216W/in3 power density, 97.6% peak efﬁciency,”
in Proc. IEEE Appl. Power Electron. Conf. Expo., 2016, pp. 1512–1519.
[34] B. Han, M. Kim, and J.-S. Lai, “Hybrid-mode Cuk inverter withlow-voltage ride-through capability under grid-faults,” in Proc. IEEE
10th Int. Conf. Power Electron. Energy Convers. Congr. Expo., 2019,
pp. 2892–2898.
[35] G.-H. Min, K.-H. Lee, J.-I. Ha, and M. H. Kim, “Design and control of single-phase grid-connected microinverter with reactive power
support capability,” in Proc. IEEE Int. Power Electron. Conf., 2018,
pp. 2500–2504.
[36] B. Han, J.-S. Lai, and M. Kim, “Bridgeless Cuk-derived single power
conversion inverter with reactive-power capability,” IEEE Trans. PowerElectron., vol. 35, no. 3, pp. 2629–2645, Mar. 2020.
[37] H. Renaudineau, M. Aguirre, and S. Kouro, “Single-phase dual-modetime-sharing PV string inverter,” in Proc. IEEE Southern Power Electron. Conf., 2017, pp. 1–6.
[38] A. Kawamura, Y. Miguchi, H. Setiadi, and H. Obara, “Survey of 99.9%
class efﬁciency DC-AC power conversion and technical issues,” IEEJ
Trans. Elect. Electron. Eng., vol. 18, no. 1, pp. 6–14, 2023.
[39] Y. Miguchi, H. Setiadi, Y. Nasu, H. Obara, and A. Kawamura, “Control scheme for leading power factor operation of single-phase gridconnected inverter using an unfolding circuit,” IEEE Open J. PowerElectron., vol. 3, pp. 468–480, 2022.

YASUHIKO MIGUCHI (Life Member, IEEE) received the master’s degree in systems engineeringfrom Kobe University, Kobe, Japan, in 1979. From1979 to 1998, he was with Toshiba Corporation,
Fuchu Works, Tokyo, Japan. From 1984 to 1986,
he was a Visiting Researcher with the University ofMissouri-Columbia, Columbia, MO, USA. From1998 to 1999, he was a Researcher with United
Technologies Research Center, East Hartford, CT,
USA. From 2000 to 2020, he was with Nippon Otis
Elevator Company, Chiba, Japan. He is currently
a Researcher with Yokohama National University, Yokohama, Japan. His
research interests include power electronics and its control. He is a Member of
the Society of Instrument and Control Engineers (SICE), Institute of System,
Control, and Information Engineers (ISCIE), and IEE of Japan.

HIDEMINE OBARA (Member, IEEE) received
the Ph.D. degree in electrical and electronics engineering from Chiba University, Chiba, Japan, in
2015. From 2015 to 2016, he was a Postdoctoral
Researcher with Tokyo Metropolitan University,
Hachioji, Japan. Since 2016, he has been with
Yokohama National University, Yokohama, Japan.
He is currently an Associate Professor. His research interests include multi-level-topology-based
linear ampliﬁers, multi-level power converters, anddigital active gate drivers.

ATSUO KAWAMURA (Life Fellow, IEEE) received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan, in
1981. After a ﬁve-year-stay with the Universityof Missouri-Columbia, Columbia, MO, USA, asa Faculty member, he joined the Department ofElectrical and Computer Engineering, Yokohama
National University, in 1986. After he retired there
as a Professor Emeritus in 2019, he became a
Professor of power electronics endowed chair. His
research interests include power electronics, digital
control, electric vehicles, train traction control, and robotics. Dr. Kawamura isa Fellow of the IEE Japan. He was the recipient of several Transactions Paper
Awards from the IEEE and IEE of Japan and International Power Electronics
and Motion Control Conference (EPE-PEMC) Award.

161

PE㸫24㸫068
PSE㸫24㸫080
SPC㸫24㸫122㧗ຠ⋡ HEECS ࢖ࣥࣂ࣮ࢱࡢᦆኻపῶ࡟㛵ࡍࡿ᪂ࡋ࠸ᒎ㛤Ἑᮧ⠜⏨㸨 Van-Long Phamࠊ࿡ཱྀὈᙪࠊᑠཎ⚽ᕊ㸦ᶓ὾ᅜ❧኱Ꮫ㸧
New Direction on Loss reduction of high efficiency HEECS inverter
Atsuo Kawamura, Van-Long Pham, Yasuhiko Miguch, Hidemine Obara(Yokohama National University)

In order to reduce the losses of the HEECS inverter, we consider two methods, focusing on the inductors
and the capacitors losses. First, the inductance is changed and the inverter losses are measured using
the VTASLM method. Second, the capacitors are replaced and the losses are measured.
࣮࣮࢟࣡ࢻ㸸࢖ࣥࣂ࣮ࢱ㸪㧗ຠ⋡㸪 ᐃἲ㸪HEECS(Keywords: Inverter, High efficiency, Measurement, HEECS

1. ࡣࡌࡵ࡟
ⴭ⪅ࡽࡣࠊᅗ㸯࡟♧ࡋࡓ HEECS ࢖ࣥࣂ࣮ࢱ࡟ࡼࡿ㟁ຊኚ᥮ຠ⋡ 99.9㸣ࢆ┠ᣦࡋࡓ DC-AC 㟁ຊኚ᥮ࡢᐇ⌧ࢆ⌮Ꮫⓗ࡞
ぢᆅ࠿ࡽ᳨ウࡋ࡚ࡁࡓ(1)ࠋWBG(wide-band-gap)ࢹࣂ࢖ࢫࢆ⏝࠸ࡓ࢖ࣥࣂ࣮ࢱࡢ㧗ຠ⋡ᐇ
࡛ࠊࡑࡢ

ࡀ」ᩘሗ࿌

(1-8)

ࡉࢀ࡚࠸ࡿࡢ

ᐃ⢭ᗘࡀ᫂グࡉࢀࡓࡶࡢ࡟㛵ࡋ࡚ࡣࡑࢀࢆྵࡵ

࡚ࠊฟຊ࡜ຠ⋡ࡢ᭱᪂ሗ࿌౛ࢆᅗ 2 ࡟♧ࡋࡓࠋࡇࢀ࡟ࡼࡿ࡜
99.5㸣௨ୖࡢຠ⋡ࡀ᭱᪂ࡢ㧗ຠ⋡࢖ࣥࣂ࣮ࢱࡢືྥ࡜ゝ࠼ࡿࠋĨĨŝĐŝĞŶĐǇ;йͿ
ϭϬϬ͘Ϭ

;ϴͿ

ϵϵ͘ϴ
;ϳͿ

;ϭͿ

ϵϵ͘ϲ

;ϰͿ ;ϱͿϵϵ͘ϰᐃἲ㸦VTASLM

ᐃἲ㸧ࢆᥦ᱌ࡋ࡚ࠊ ᐃჾࡢ㍑ṇ࠾ࡼࡧᐃࢹ࣮ࢱࡢ⤫ィⓗ࡞ฎ⌮࡟ࡼࡾᦆኻࡢ

;ϮͿࡿࡇ࡜ࢆ♧ࡋࡓ

ϭᐃ⢭ᗘࡀ 0.006%⛬ᗘࡲ࡛㧗ࡵࡽࢀ(7)ࠋࡑࡢ

;ϯͿ

;ϲͿ

ϵϵ͘Ϯ

ⴭ⪅ࡽࡢࢢ࣮ࣝࣉ࡛ࡣࠊ ᐃ⢭ᗘࡢ㧗࠸dŚĞĂƌ
ŚĞŝŐŚƚŝŶƚŚĞůĞĨƚŐƌĂƉŚƐŚŽǁƐĂƌĂŶŐĞŽĨĂĐĐƵƌĂĐǇ͘ϭϬKƵƚƉƵƚƉŽǁĞƌ䠄ŬtͿϭϬϬᐃᡭἲ࡟ᇶ࡙࠸࡚ࠊᩥ⊩㸦9,10㸧

࡛ࡣࠊᦆኻࢆయ⣔ⓗ࡟᭱ᑠ໬ࡍࡿᡭἲࡀᥦ᱌ࡉࢀࡓࠋࡋ࠿

ᅗ㸰 㧗ຠ⋡࢖ࣥࣂ࣮ࢱࡢሗ࿌౛(ᩥ⊩␒ྕཧ↷)ࡋࠊᦆኻ᭱ᑠ໬ࡢࡍ࡭࡚ࡢᡭἲࡀ᳨ウࡉࢀ࡚ࡣ࠸࡞࠿ࡗࡓࠋ

Fig.2. Survey of high efficiency literatures on inverterࡑࡇ࡛ࠊᮏㄽᩥ࡛ࡣᮍ᳨ウࡢ᪉ྥ࠿ࡽࡢᦆኻపῶࡢ࢔ࣉࣟ

operation࣮ࢳࢆࡋࡓࡢ࡛ࠊሗ࿌ࡍࡿࠋ
2 ❶࡛ࡣࠊࡇࢀࡲ࡛ࡢᦆኻపῶࡢ⤒⦋ࢆᴫㄝࡍࡿࠋ3.1 ❶࡛ࡣࠊ࢖ࣥࢲࢡࢱࣥࢫࡢ᭱㐺໬࡟㛵ࡋ᳨࡚ウࢆ⾜࠸ࠊ3.2 ❶࡛ࡣࠊ࢟ࣕࣃࢩࢱࣥࢫࡢ᭱㐺໬࡟㛵ࡋ࡚ࡢ᳨ウࢆሗ࿌ࡍࡿࠋ
3.3 ❶ࡢ⪃ᐹ࡛ࡣࠊࡉࡽ࡞ࡿᦆኻపῶࡢ᪉ྥ࡟㛵ࡋ࡚⪃ᐹࢆ

2. ᦆኻ᭱ᑠ໬ࡢᡭἲ㸦9,10㸧ࡢ᚟⩦࡜ࡇࢀࡲ࡛ࡢ⤒⦋
2.1 ᦆኻ᭱ᑠ໬ἲࡢ᚟⩦ᩥ⊩(9,10)࡛ᥦ᱌ࡋࡓᦆኻ᭱ᑠ໬ᡭἲ࡛ࡣࠊඃඛ㡰఩ࢆ⪃៖ࡋ࡚ࠊ⮬⏤ᗘࢆ௨ୗ࡟♧ࡍ㡯┠㸯࠿ࡽ㸲࡟ศ㢮ࡋࡓࠋ㔜せ⾜࠺ࠋ4 ❶ࡣ⤖ㄽ࡛࠶ࡿࠋ

ᗘࡣࠊ㸯ࡀ㧗ࡃࠊ㸰㸪㸱㸪㸲࡜ඃඛᗘࡣୗࡀࡿ࡜⪃࠼ࡓࠋᚑ

E2

S4

iL

ࡗ࡚ࠊ㡯┠㸲࠿ࡽ㡯┠㸱࡟࠿ࡅ࡚ࠊ㡰␒࡟ࣃ࣓࣮ࣛࢱࡢ᭱㐺໬ࢆ⾜࠸ࠊ㟁ຊኚ᥮ຠ⋡ࡢ᭱኱໬ࢆᐇ⌧ࡋ࡚ࡁࡓࠋ

E1

S2

S3

L

vsw
S1

C

S7

S5

vdc

Load

S6 vac࠙㡯┠㸯ࠚ㸸๓ᥦ᮲௳࡜ࡋ࡚ࠊ⾲㸯࡟♧ࡍᇶᮏ௙ᵝࢆタᐃࡍࡿࠋ㸦ࢹࣂ࢖ࢫࡢ㟁ᅽవ⿱ࠊࢫ࢖ࢵࢳࣥࢢ࿘Ἴᩘࠊฟຊ㟁ᅽ
ࡢṍ⋡㸧

S8

࠙㡯┠㸰ࠚ㸸๓ᥦ᮲௳࡜ࡋ࡚ࡢᅇ㊰ࢺ࣏ࣟࢪ࣮ࢆ㑅ࡧࠊ௒ᅇࡣࠊᅗ㸯ࡢ HEECS ࢖ࣥࣂ࣮ࢱ࡜ࡋࡓࠋ௚ࡢᅇ㊰ೃ⿵ࡣࠊᩥ

ᅗ 1 2 㟁※ HEECS ࢖ࣥࣂ࣮ࢱࡢᅇ㊰ࢺ࣏ࣟࢪ࣮
Fig. 1. Two battery HEECS inverter.

⊩㸦9㸧࡟ヲࡋ࠸ࠋ࠙㡯┠㸱ࠚ㸸‽௙ᵝ࡜ࡋ࡚ࡢࢫ࢖ࢵࢳࣥࢢࢹࣂ࢖ࢫ㸦ࢳࣙࢵࣃ㒊࡜ᢡࡾ㏉ࡋ࢖ࣥࣂ࣮ࢱ㸧࡜ࢳࣙࢵࣃ㒊ࡢࣇ࢕ࣝࢱࡢᅇ
1㸭6

⾲㸯 ᦆኻ᭱ᑠ໬⿕ヨ㦂࢖ࣥࣂ࣮ࢱࡢᇶᮏ௙ᵝࡣࠊᅗ㸰࡟཯ᫎࡋ࡚࠸ࡿࠋ

Table 1 Conditions for inverter under testࢹࣂ࢖ࢫࡢ㟁ᅽవ⿱ฟຊ㟁ᅽࡢ 50%
16 kHzࢫ࢖ࢵࢳࣥࢢ࿘Ἴᩘ
ฟຊ㟁ᅽࡦࡎࡳ⋡1㸣⛬ᗘḟ❶࡛ࡣࠊࢳࣙࢵࣃ㒊ࡢᅇ㊰ࣃ࣓࣮ࣛࢱ࡛࠶ࡿ࢖ࣥࢲࢡࢱ
ࣥࢫ࡜࢟ࣕࣃࢩࢱࣥࢫ࡟㛵ࡋ࡚㡯┠㸱࡛ࣞ࣋ࣝࡢ᳨ウࢆ⾜࠺ࠋ

3. ⮬⏤ࣃ࣓࣮ࣛࢱ࡛࠶ࡿ࢖ࣥࢲࢡࢱࣥࢫ࡜࢟ࣕ
ࣃࢩࢱࣥࢫࡢ᭱㐺໬⾲㸰 ‽௙ᵝࣃ࣓࣮ࣛࢱ
Table 2 Quasi-free Parameters
Ron=17mΩ(typ)ࢳࣙࢵࣃࢹࣂ࢖ࢫ
SCT3017AL(Rohm)
Ron=3.7mΩ
ᢡࡾ㏉ࡋ࢖ࣥࣂ࣮ࢱ
CAS325M12HM2
ࢹࣂ࢖ࢫ(Wolfspeed)
1.25mH(18mΩ)࢖ࣥࢲࢡࢱ L(ࣇ࢙ࣛ࢖ࢺ)㸦IPEC㸧
8μF (3.5mΩ)࢟ࣕࣃࢩࢱ C(ࣇ࢕࣒ࣝ)(ARCOTRONICS)ไᚚDB㸦Deadbeat㸧ຊ⾜ཬࡧᅇ⏕㐠㌿ᩥ⊩(11)
PCB
175μ 㖡ཌ㸦ᩘ mΩ㸧(1)㸦P ᯈ㸧

3.1 ࢖ࣥࢲࢡࢱࡢᦆኻࡢ᭱ᑡ໬
࢖ࣥࢲࢡࢱࡢᦆኻࡣ㖡ᦆࠊᇶᮏἼ㕲ᦆࠊ㧗ㄪἼ㟁ὶᦆࡢ୕ࡘࡢᦆኻせ⣲࠿ࡽᵓᡂࡉࢀࡿ࡜⪃࠼ࡽࢀࡿ(1,12)ࠋᩥ⊩(1)࡛
ࡣࠊࡑࡢ㸱⪅ࡢ኱ࡁࡉࡣࠊ࡯ࡰ➼ࡋ࠸ࡇ࡜ࡀᐇ

ࡉࢀ࡚࠸ࡿࠋࡇࢀࡽࡢ࠺ࡕࠊ㖡ᦆࢆῶࡽࡍ࡟ࡣࠊᕳࡁ⥺᢬ᢠࢆపῶࡍ
ࡿࡇ࡜ࡀ㔜せ࡛࠶ࡿࠋ㖡⥺ࢆኴࡃࡍࡿ࡜ࠊ࢖ࣥࢲࢡࢱࡢయ᱁
ࡀ኱ࡁࡃ࡞ࡾࠊᇶᮏἼ㕲ᦆࡀቑຍࡍࡿ࡜⪃࠼ࡽࢀࡿࠋࡉࡽ
࡟ࠊ㧗࿘Ἴ㟁ὶᦆࢆῶࡽࡍ࡟ࡣࠊ㧗ㄪἼ㟁ὶࢆῶࡽࡍࡇ࡜ࡀ㔜せ࡛࠶ࡿࡀࠊࡑࡢࡓࡵ࡟ࠊ࢖ࣥࢲࢡࢱࣥࢫࢆቑࡸࡍᑐ⟇ࡀ⪃࠼ࡽࢀࡿࠋࡇࢀࡽ㸱ࡘࡢせ⣲ࡣࠊ࠾஫࠸࡟㛵㐃ࡋ࡚࠸࡚ࠊ
᭱኱ຠ⋡ࢆồࡵࡿሙྜࡣࠊ㏻ᖖࡢ㟁ຊᐦᗘࢆ᭱኱໬ࡍࡿࡼ
࠺࡞࢖ࣥࢲࢡࢱࡢタィ࡜ࡣ␗࡞ࡿ࢔ࣉ࣮ࣟࢳࡀᚲせ࡜࡞ࡿࠋ ࡑࡇ࡛ࠊᩥ⊩(8)࡛ࡣࠊᩥ⊩(9)ࡢ࢖ࣥࢲࢡࢱ㸦⾲㸰ࡢ࢖ࣥ⾲㸱࠙㡯┠㸲ࠚࡢ⮬⏤ࣃ࣓࣮ࣛࢱࡢ᭱㐺໬
Table 3 Free parameters on item 4ࢲࢡࢱ࡛࠶ࡾࠊࡇࢀࢆ㸡㸯࢖ࣥࢲࢡࢱ(#1L)࡜࿧ࡪࠋ㸧ࢆᨵⰋࡋ࡚ࠊᕳࡁ⥺᢬ᢠࡢᑠࡉ࠸ࡶࡢ〇సࡋ㸦ࡇࢀࢆ㸡㸰࢖ࣥࢲࢡ
ࢱ(#2L)࡜࿧ࡪ㸧ࠊᦆኻࢆᐇ

ࡋࡓࠋࡋ࠿ࡋࠊయ᱁ࡀ኱ࡁࡃ࡞

E1ͳE2͹ർིࡗ࡚ࠊᇶᮏἼ㕲ᦆࡢᦆኻࡀቑ኱ࡋࡓ࡜⪃࠼ࡽࢀࠊᦆኻࡢపῶ

䝗䝷䜲䝞ᅇ㊰ᐃᩘᖜࡣࢃࡎ࠿࡛࠶ࡗࡓࠋࡑࡇ࡛ࠊᮏㄽᩥ࡛ࡣࠊయ᱁ࡶ⪃៖ࡋࡓྍኚ䝕䝑䝗䝍䜲䝮ไᚚ᪂ࡋ࠸࢖ࣥࢲࢡࢱ㸦㸡㸱࢖ࣥࢲࢡࢱ(#3L)࡜࿧ࡪ㸧ࢆヨసࡋ༙ް‫;ٶ‬ໃްుྙ͹મఈ

ࡓ(13)ࠋࡇࢀࡽࡢᇶᮏ≉ᛶࢆࡲ࡜ࡵࡓࡶࡢࢆ⾲㸲࡟♧ࡍࠋ≉οϥρϏ෨͹ుླྀιϱγϪη੏‫ޜ‬࡟ࠊ☢㊰ࡢయ✚ẚࡀ㔜せ࡞ᣦᶆ࡛࠶ࡾࠊ㸡㸱࢖ࣥࢲࢡࢱ࡛
ࡣࠊᕳࡁ⥺᢬ᢠࡣ㸡㸰࡟ẚ࡭኱ࡁࡃ࡞ࡗࡓࡀࠊ☢㊰య✚ࢆ㸡㊰ࣃ࣓࣮ࣛࢱࢆ⪃࠼ࡓࠋࡉࡽ࡟ࠊPCB ࡢᑟయཌࡳࡢ᮲௳࡜

2 ࡼࡾࡶᑠࡉࡃタィࡋࡓࠋไᚚ᪉ᘧ㸦ຊ⾜࡜ᅇ⏕㐠㌿㸧ࡶࡇࢀ࡟ྵࡵࡓࠋࡇࢀࡽࢆ⾲㸰࡟♧ࡍࠋࢫ࢖ࢵࢳࣥࢢࢹࣂ࢖ࢫࡣࠊ㑅ᐃ᫬࡟ᕷሙ࡛ᚓࡽࢀࡿ
᭱ୖࡢ᮲௳࡟ྜ࠺ࡶࡢ࡜ࡋࡓࠋ
࠙㡯┠㸲ࠚ㸸௙ᵝ࡜ࡋ࡚ࡢ⮬⏤ࣃ࣓࣮ࣛࢱࡣࠊୖグ 㸬௨እࡢࣃ࣓࣮ࣛࢱ࡛࠶ࡾࠊලయⓗ࡟ࡣࠊ௨ୗࡢ  Ⅼ࡜࡞ࡿࠋ㸸 D ⾲㸲 㸱✀㢮ࡢヨస࢖ࣥࢲࢡࢱࣥࢫ
ᅗ 3 E1㸩E2Tableࡢྜィ್ࡀ୍ᐃ࡛
1 ࡀኚ໬ࡍࡿሙྜࡢ
4 3 kinds of E
inductors
Coss ࡜ࢫ࢖ࢵࢳࣥࢢ࡟ࡼࡿᦆኻࡢᐃᛶⓗ࡞࢖ࣛࢫࢺᅗ
R(mΩ
L(mH)
␒ྕ
ᮦ㉁
Fig.3
Quantitative illustration on
Loss of☢㊰య✚ẚ
Coss and( ࡜ ( ࡢẚ⋡ࠊ E ࢤ࣮ࢺࢻࣛ࢖ࣂᅇ㊰ࡢᐃᩘࠊ F ྍኚࢹ

#1
#2
#3

ࢵࢻࢱ࢖࣒ไᚚ࡜ࡑࡢᐃᩘࠊ G ࢖ࣥࣂ࣮ࢱ࡜⣔⤫࡜㐃⣔㸦ຊ⾜࠾ࡼࡧᅇ⏕㸧ࡍࡿ㟁ὶࡢ᭷ຠ࠾ࡼࡧ↓ຠ㟁ຊࡢẚ⋡ࠊ

1.27
15.06
ࣇ࢙ࣛ࢖ࢺ
switchingregardingE1
2.06
5.24 ࣇ࢙ࣛ࢖ࢺ
1.25
11.66 ࣇ࢙ࣛ࢖ࢺ

1.00
3.91
1.51

H ࢳࣙࢵࣃ㒊ࡢ㟁ὶࢭࣥࢧࣞࢫไᚚࠋࡇࢀࡽࢆ⾲㸱࡟ࡲ࡜ࡵࡓࠋࡇࢀࡽ㸱✀㢮ࡢ࢖ࣥࢲࢡࢱࡢ≉ᛶࢆᐇ࡟ࡲ࡜ࡵ࡚♧ࡋ࡚࠶ࡿࠋ

2.2 ࡇࢀࡲ࡛ࡢ⤒⦋ᩥ⊩(9)࡛ࡣࠊ
࠙㡯┠㸲ࠚࡢࡍ࡭࡚ࡢ㡯┠࡟㛵ࡋ࡚ࠊᦆኻࡢ
⢭ᐦ

ᐃἲ㸦VTASLM㸧ࡢᥦ᱌࡛࠶ࡿᩥ⊩(7)ࡢ

ࡋࡓ⤖ᯝࢆ⾲㸳

ᐃἲ࡟ᚑࡗ࡚᭱㐺໬ࡋࡓࠋࡉࡽ࡟ࠊᩥ⊩(8)࡛ࡣࠊᩥ⊩(9)ࡼࡾࡶ㋃ࡳ㎸ࢇ࡛ࠊ㡯┠㸱ࡢ᭱㐺໬ࡣ୍㒊ࡢࡳ᳨ウࡀ⾜ࢃࢀࡓࠋࡑࡢ⤖ᯝ

ࡲࡎࠊ50Hz ࡢṇᘻἼ㟁ὶࢆ࢖ࣥࢲࢡࢱ࡟ὶࡋ࡚ࠊ㟁ὶࢆࣃ࣓࣮ࣛࢱ࡟ྲྀࡾࠊ┤᥋ἲ࡟ࡼࡾࠊ඲ᦆኻࢆồࡵࡓࠋࡓࡔࠊ
ࡇࡢᐃ⢭ᗘࡣ㠀ᖖ࡟ᝏ࠸(1)ࠋࡉࡽ࡟ࠊᇶᮏἼ㕲ᦆࢆࠊࡇࡢ

ᇶᮏἼᑟ㏻ࡢ඲ᦆኻ࠿ࡽᑟ㏻ᦆ㸦LCR ࣓࣮ࢱ࡛

ᐃࡋࡓ᢬
2㸭6

ᢠ࠿ࡽィ⟬ࡋࡓࢪ࣮ࣗࣝᦆ㸧ࢆᕪࡋᘬ࠸࡚ồࡵࡓࠋ࡞࠾ࠊ㟁‫خ‬ຌഀಖଝͳ‫خ‬ຌഀరଝ

ὶ್ࡣࠊHEECS ࢖ࣥࣂ࣮ࢱ㐠㌿࡟࠾࠸࡚ࠊ1200W ࠿ࡽ
1700W ࡢฟຊ࡟ᑐᛂࡍࡿ㟁ὶ್ࢆ㑅ࢇࡔࡀࠊࡇࡢ࠺ࡕ 3 ㏻Ϭ͘ϰࡾࡢࢹ࣮ࢱࢆ⾲㸳࡟㍕ࡏࡓࠋϬ͘ϯϱ

⾲㸳 3 ✀㢮ࡢ࢖ࣥࢲࢡࢱࡢ≉ᛶᐇ

ϫηʤtʥ

Ϭ͘ϯ

⾲

Table 5 characteristics of 3 kinds of inductors
ుླྀ $

/

/



Ϭ͘Ϯ
Ϭ͘ϭϱ
Ϭ͘ϭ
Ϭ͘Ϭϱ



౵Ճड़ྙ :







‫خ‬ຌഀరଝ :





Ϭ
ϭϭϬϬ

ϭϮϬϬ

ϭϯϬϬ

ϭϰϬϬ

‫خ‬ຌഀಖଝ

ϭϱϬϬ

ϭϲϬϬ

ϭϳϬϬ

‫خ‬ຌഀరଝ

‫خ‬ຌഀಖଝ :





߶௒ഀଝ :







଎ఈ߻‫ ܯ‬:







ࣰ଎ްི 







Fig. 3. Joule and iron loss of #3L at the fundamental‫خ‬ຌഀరଝ :





frequency‫خ‬ຌഀಖଝ :





߶௒ഀଝ :







଎ఈ߻‫ ܯ‬:







ࣰ଎ްི 







‫خ‬ຌഀరଝ :





‫خ‬ຌഀಖଝ :  

߶௒ഀଝ :



଎ఈ߻‫ ܯ‬:





ࣰ଎ްི 







 

ᅗ㸱 #3L ࡢᇶᮏἼ㖡ᦆ࡜ᇶᮏἼ㕲ᦆ

By 50 Hz AC power and L-R load
By HEECS operation in powering mode
By HEECS operation in regenrating mode
0.6

0.5

Inductor loss (W)

/



Ϭ͘Ϯϱ

0.4

0.3

0.2

0.1

ḟ࡟ࠊ࢖ࣥࢲࢡࢱࢆ HEECS ࢖ࣥࣂ࣮ࢱ࡟⤌ࡳ㎸ࢇ࡛ࠊຊ⾜࡜ᅇ⏕ࡢ㐠㌿᫬ࡢ࢖ࣥࢲࢡࢱࡢᖹᆒ඲ᦆኻࢆ┤᥋ἲ࡛ᐃࡋࡓࠋࡑࡢᐇ

್࠿ࡽࠊ50Hz ࡛

0
1100

1200

1300

1400

1500

1600

1700

Power (W)ᐃࡋࡓᑟ㏻ᦆ࡜ᇶᮏ

Ἴ㕲ᦆࢆᕪࡋᘬ࠸ࡓࡶࡢࢆ㧗ㄪἼᦆ࡜ࡋ࡚௬ᐃࡋ࡚ࠊࡇࡢ
⾲࡟グධࡋࡓࠋࡇࡢ㧗ㄪἼᦆ࡟ࡣࠊ㧗ㄪἼ㟁ὶ࡟ࡼࡿᅗ 4 #3L ࡢᦆኻࡢẚ㍑

㟁ὶ㸦ᇶᮏἼࡢࡳࠊຊ⾜࠾ࡼࡧᅇ⏕㐠㌿㸧ᦆ࡜ࠊ㧗ㄪἼ㟁ὶ࡟ࡼࡿ㕲ᦆ㸦ࣄࢫࢸࣜࢩࢫᦆ㸧ࡀྵࡲࢀࡿࠋ
ࡲࡓࠊࡑࡢ᫬ࡢ VTASLM
グධࡋࡓࠋࡇࡢ
ࡇࡢ⾲࠿ࡽほᐃἲ࡟ᇶ࡙ࡃ඲㟁ຊኚ᥮ຠ⋡ࡶ

Fig. 4.

ᐃ⢭ᗘࡣ㠀ᖖ࡟㧗࠸(7)ࠋ
ࡉࢀࡿࡇ࡜ࡣࠊ௨ୗ࡜࡞ࡿࠋ

Loss of #3L at the fundamental frequency,
powering and regeneration operationࣇ࢙ࣛ࢖ࢺ࡛࠶ࡾࠊ㟁ὶࡢືసⅬࡣࠊᐃ᱁㟁ὶ㸦タィⅬ㸧ࡢ㸦㸯㸧㸡㸰࢖ࣥࢲࢡࢱ(#2L)ࡣࠊ㖡ᦆࡣᑠࡉ࠸ࡀࠊᇶᮏἼ

20㸣⛬ᗘ࡛࠶ࡿࡢ࡛ࠊ㕲ᦆࡣ㠀ᖖ࡟ᑠࡉ࠸ࠋᅗ㸲ࡣࠊHEECS㕲ᦆ࠾ࡼࡧ㧗࿘Ἴᦆࡀࠊ௚ࡢ 2 ✀㢮ࡢ࢖ࣥࢲࢡࢱ࡜ẚ㍑ࡋ

࢖ࣥࣂ࣮ࢱ࡟⤌ࡳ㎸ࢇࡔ᫬ࡢࢹ࣮ࢱ࡛࠶ࡿࡢ࡛ࠊ㧗ㄪἼ㟁࡚኱ࡁ࠸ࠋὶࢆྵࢇ࡛࠾ࡾࠊࡲࡓࠊᅇ⏕㐠㌿᫬࡟ࡣࠊ㟁ὶࡢྥࡁࡣ㏫࡟

㸦㸰㸧㸡㸱ࡢ࢖ࣥࢲࢡࢱ(#3L)ࡣࠊ㖡ᦆࡣ㸡㸯࡜㸡㸰ࡢ࢖࡞ࡗ࡚࠸ࡿࠋࡇࡢᅗ࠿ࡽほᐹࡉࢀࡿࡇ࡜ࡣࠊຊ⾜᫬࡟ࡣࣥࢲࢡࢱࡢ୰㛫࡟఩⨨ࡍࡿࡀࠊ㕲ᦆ࡜㧗࿘Ἴᦆࡣࠊ࡯ࡰ㸡㸯

50Hz 㥑ື᫬࡜࡯ࡰྠᵝ࡞≉ᛶࢆ♧ࡋ࡚࠸ࡿࡀࠊᅇ⏕᫬࡟ࡢ࢖ࣥࢲࢡࢱ࡜ྠ⛬ᗘ࡛࠶ࡿࠋ

ࡣࠊᅇ⏕㟁ຊࡀᑠࡉ࠸㡿ᇦ࡛ࡣࠊ㧗ㄪἼᦆࡀ኱ࡁࡃ࡞ࡗ࡚࠸

㸡㸱ࡢ࢖ࣥࢲࢡࢱࡣ㸡㸯ࡢ࢖ࣥࢲࢡࢱ࡟ẚ࡭࡚☢㊰ࡢయ

ࡿⅬ࡛࠶ࡿࠋࡑࡢཎᅉ࡜ࡋ࡚ࡣࠊࡇࡢ㟁ຊ㡿ᇦ࡛ࡣ㧗ㄪἼ㟁✚ࡀ 1.5 ಸ⛬ᗘ࡛࠶ࡿࡢ࡟ᑐࡋ࡚ࠊ㸡㸰ࡢሙྜࡣࠊ⣙ 3 ಸ࡜ὶࡀ኱ࡁࡃ࡞ࡗ࡚࠸ࡿྍ⬟ᛶࠊ࠾ࡼࡧ㟁ὶࢭࣥࢧࡢṇ᪉ྥ࡞ࡗ࡚࠸ࡿࠋࡋ࠿ࡋࠊ⾲㸳ࡢᦆኻࡢ኱ࡁࡉࡢ㛵ಀࡣࡇࡢࡼ࠺

࡜㈇᪉ྥࡢ

࡞ᐃᛶⓗ࡞ண᝿್࡜ࡣ୍⮴ࡋ࡞࠸ࠋ࢖ࣥࢲࢡࢱࡢ⥲ᦆኻࡢࢀࡿࠋᐃ್࡟ࡎࢀࡀ࠶ࡿྍ⬟ᛶ࡞࡝ࡢ⌮⏤ࡀ⪃࠼ࡽᐃἲࡣࠊ୧➃ࡢ㟁ᅽ࡜㟁ὶࡢ✚࠿ࡽᦆኻࢆồࡵࡿ┤᥋ἲ࡛࠶ࡾࠊࡑࡢ⢭ᗘࡀప࠸ࡓࡵ࡜ᛮࢃࢀࡿ(1)ࠋ
ࡑࡇ࡛ࠊ㸡㸱ࡢ࢖ࣥࢲࢡࢱ࡟㛵ࡋ࡚ࠊ㕲ᦆ࡜㧗࿘Ἴᦆ࡟㛵ࡋ࡚㏣ຍࡢᐃࢆ⾜ࡗࡓࡢ࡛ࠊࡑࡢ

ᐃࢹ࣮ࢱࢆᅗ㸱࡜ᅗ᭱ᚋ࡟ࠊᦆኻࡢ⢭ᐦᐃἲ࡛࠶ࡿ VTASLM ἲ(7)࡟ᇶ࡙࠸

࡚ࠊ㸡㸱ࡢ࢖ࣥࢲࢡࢱࣥࢫࢆ⏝࠸ࡓ HEECS ࢖ࣥࣂ࣮ࢱࡢ
ຠ⋡ࢆᐃࡋࡓࠋࡑࡢຠ⋡࡜ᐃ⢭ᗘࢆᅗ㸳࡜ᅗ㸴࡟♧ࡍࠋ㸲࡟♧ࡍࠋᅗ㸱ࡣ 50Hz ࡢ㟁ὶࢆࣃ࣮࣡࢔ࣥࣉ࠿ࡽὶࡋ࡚

ฟຊࡀ 1300㹕ࡢ᫬࡟ࠊኚ᥮ຠ⋡ 99.836s0.004%ࡀᐇ

ᐃࡋࡓࡶࡢ࡛ࠊ㧗ㄪἼ㟁ὶࡣྵࡲࢀ࡚࠸࡞࠸ࠋࡲࡓࠊᮦ㉁ࡀ

ࢀࡓࠋࡇࡢᐇ

ࡉ್ࡣࠊ㸡㸰ࡢ࢖ࣥࢲࢡࢱࡢ᫬ࡢຠ⋡ࡼࡾࡶࢃ3㸭6

iL : 5 A/divǀĞƌĂŐĞĨĨŝĐŝĞŶĐǇ
ϵϵ͘ϴϯϴ
ϵϵ͘ϴϯϳ

ɻĂǀĞ;йͿϵϵ͘ϴϯϲ

vdc
200 V/divϵϵ͘ϴϯϱ
ϵϵ͘ϴϯϰ

ϵϵ͘ϴϯϯ
ϵϵ͘ϴϯϮ

vac : 200 V/divϵϵ͘ϴϯϭ

THD: 0.4%ϵϵ͘ϴϯϬ
ϭϮϬϬ

ϭϯϬϬ

ϭϰϬϬ

ϭϱϬϬ

ϭϲϬϬ

ϭϳϬϬ

Time division:
5 ms/div

ϭϴϬϬ

WϮ;tͿ

ᅗ㸳 SiC-HEECS ࢖ࣥࣂ࣮ࢱࡢຠ⋡ᅗ㸵 HEECS ࢖ࣥࣂ࣮ࢱࡢྛ㒊ࡢἼᙧ(1)Fig. 7 Three kinds of waveforms at 2.2 kW
output of HEECS Inverter in Fig. 1(1)(#3L)
Fig.5 Measured efficiency of SiC HEECS Inverter with #3LĐĐƵƌĂĐǇ;йͿĐĐƵƌĂĐǇ
Ϭ͘ϬϬϱϬ͘ϬϬϰϱ
Ϭ͘ϬϬϰϬ͘ϬϬϯϱ
Ϭ͘ϬϬϯϬ͘ϬϬϮϱ
Ϭ͘ϬϬϮϬ͘ϬϬϭϱ
Ϭ͘ϬϬϭϬ͘ϬϬϬϱϬϭϮϬϬIL=SQRT(Iload2+Ic2)  

----

(1)

Ic=abs(jωCVac)

----

(2)

ࡓࡔࡋࠊ࢟ࣕࣃࢩࢱࡢ㟼㟁ᐜ㔞ࢆ Cࠊᢡࡾ㏉ࡋ࢖ࣥࣂ࣮ࢱࡢ
ฟຊ㟁ᅽࡢ᣺ᖜࢆ Vac ࡜ᐃ⩏ࡍࡿࠋࡉࡽ࡟ࠊ␲ఝຊ⋡ pfpseudo ࢆḟᘧ࡛ᐃ⩏ࡍࡿࠋ
ϭϯϬϬ

ϭϰϬϬ

ϭϱϬϬ

ϭϲϬϬ

ϭϳϬϬ

ϭϴϬϬ

WϮ;tͿ

Pfpseudo=abs(Ic/IL)
ᅗ㸴 SiC-HEECS ࢖ࣥࣂ࣮ࢱࡢຠ⋡------ (3)ᐃ⢭ᗘ(#3L)

Fig.6 Accuracy of SiC-HEECS Inverter efficiency

౛࠼ࡤࠊ8uF ࡢࣇ࢕࣒ࣝ࢟ࣕࣃࢩࢱࣥࢫ㸦RESR=3.5mȐ㸧ࢆ

measurement with #3L㑅ࢇࡔሙྜࠊฟຊ㟁ຊࡀ 1300W㸦at 302Vrms㸧ࡢ᮲௳࡛ࡣࠊ
Iload=4.3 (A)ࠊIc=0.76(A)࡜࡞ࡿࡢ࡛ࠊpfpsuedo=0.98 ࡜࡞ࡿࠋࡎ࠿࡟ྥୖࡋ࡚࠸ࡿࠋ ᐃ⢭ᗘࢆ຺᱌ࡋ࡚ࡶࠊ㸡㸰ࡢ࢖ࣥࢲྛ㒊࡛ࡢᑟ㏻ᦆࡣࠊIL ࡢ 2 ஌࡟ẚ౛ࡍࡿࡢ࡛ࠊC ࡣᑠࡉࢡࢱࡼࡾࡶ㸡㸱ࡢ࢖ࣥࢲࢡࢱࢆ⏝࠸ࡿ᪉ࡀ㧗࠸ຠ⋡ࡀᚓࡽ

࠸࡯࡝ᑟ㏻ᦆࡣῶᑡࡍࡿࡀࠊ㟁ᅽไᚚ࡜ࡋ࡚ࢹࢵࢻࣅ࣮ࢺ

ࢀࡓ࡜⪃࠼ࡽࢀࡿࠋ

ไᚚࢆ⾜ࡗ࡚࠸ࡿࡢ࡛ࠊC ࡀᑠࡉ࠸࡜୙Ᏻᐃ࡟࡞ࡿഴྥࡀ
࠶ࡿࡢ࡛ࠊ㟁ὶࡢ㧗ㄪἼᡂศࡀቑຍࡍࡿࠋ

3.2 C ࡢ᭱㐺໬ḟ࡟ࠊࢳࣙࢵࣃ㒊ࡢࣇ࢕ࣝࢱࡢ࢟ࣕࣃࢩࢱࡢ኱ࡁࡉ࡟㛵ࡋ᳨࡚ウࢆ⾜ࡗࡓࠋHEECS ࢳࣙࢵࣃ㒊ࡢ࢟ࣕࣃࢩࢱࡢᮦ㉁ࡣࠊࣇ࢕࣒ࣝ࡞ࡢ ᩥ⊩(7-9)࡛ࡣࠊC ࡣ 8ȣF ࡛ᅛᐃࡋ࡚ࡁࡓࡀࠊࡇࢀࢆ 8.0
ȣF,7.5ȣF,7.0ȣF,㸴.5ȣF ࡜ኚ໬ࡉࡏ࡚ᦆኻࢆ VTASLM ἲ(7)࡛

ᐃࡋࡓࡶࡢࢆᅗ㸶࡟♧ࡍࠋ࡞࠾ࠊࡇࡢᐇ㦂ࡢ㐣⛬࡛ࠊ᧯స࣑ࢫ࡟ࡼࡾࢫ࢖ࢵࢳࣥࢢࢹࣂ࢖ࢫ(ᅗ㸯ࡢ S3 ࡜ S4)ࢆ◚ᦆࡋࡓࡢ࡛ࠊࡇࡢ 4 Ⅼࡢ C ኚ໬࡟ࡼࡿຠ⋡ࡢᐃࢹ࣮ࢱ࡛ࠊ࢟ࣕࣃࢩࢱ࡛ࡢᦆኻࡣ㠀ᖖ࡟ᑠࡉ࠸࡜⪃࠼ࡽࢀࡿࠋࡴࡋ

ࡣࢫ࢖ࢵࢳࣥࢢࢹࣂ࢖ࢫࡀࠊ3.1 ⠇ࡢࢁࠊ࢖ࣥࢲࢡࢱࡢἼᙧࡣࠊᅗ㸵ࡢࡼ࠺࡞Ἴᙧ࡜࡞ࡿࡢ࡛㸦ᩥᑡࡋ␗࡞ࡗ࡚࠸ࡿࠋᚑࡗ࡚ࠊᅗ㸶ࢆ new PCB#5 ࡛ࡢ⊩㸯㸧ࠊᢡࡾ㏉ࡋ࢖ࣥࣂ࣮ࢱ࡛ࡢ㟁ᅽ࡜ẚ㍑ࡍࡿ࡜ࠊ㐍ࡳ㟁࣮ࢱ࡜࿧ࡪࡇ࡜࡟ࡍࡿࠋ

ὶࢆᢡࡾ㏉ࡋࡓࡼ࠺࡞ᙧ㸦༙Ἴᩚὶࡢ㟁ὶἼᙧ㸧࡜⪃࠼ࡽࢀࡇࡢᅗ࠿ࡽࠊC ኚ໬࡟ࡼࡿຠ⋡ྥୖࡣࠊX) ௜㏆࡛ࢃࡎ࠿ࡿࠋᚑࡗ࡚ࠊ࢟ࣕࣃࢩࢱࡢ㟼㟁ᐜ㔞ࡀ኱ࡁ࠸࡜ࠊ༙Ἴᩚὶࡢ

࡟ㄆࡵࡽࢀࡿࡀࠊࡑࢀࡣ

㟁ὶࡢᐇຠ್ࡀ኱ࡁࡃ࡞ࡿࠋࡑࡢ⤖ᯝࠊ࢖ࣥࢲࢡࢱࡸࢫ࢖ࢵ ⠇ࡢᅗ㸳࡛ࡣࠊ8μ㹄ࡢ C ࡛ࠊຠ⋡ 99.836%(at 1300W ฟࢳࣥࢢࢹࣂ࢖ࢫ࡛ࡢᑟ㏻ᦆࡀቑຍࡍࡿഴྥ࡜࡞ࡿ࡜⪃࠼ࡽ

ຊ ࢆᐇ

ࢀࡿࠋ

ࢹࣂ࢖ࢫࡣ␗࡞ࡗ࡚࠸ࡿࠋ

ᐃࢹ࣮ࢱ࡜ࡣࠊ್ࡀ
ᐃࢹᐃㄗᕪࡢ⠊ᅖෆ࡜ゝ࠼ࡿࠋ࡞࠾ࠊ

ࡋ࡚࠸ࡿࡀࠊࡇࡢᅗ㸳࡜ᅗ  ࡛ࡣ౑⏝ࡋࡓࣃ࣮࣡ ࡇࢀࢆᘧ࡛⾲⌧ࡍࡿ࡜௨ୗ࡜࡞ࡿࠋ50Hz ࡛ࡢࣇ࢙࢖ࢨ࣮
ࢆ⪃࠼ࠊຊ⋡㸯ࡢ㈇Ⲵ㟁ὶࡢ᣺ᖜࢆ Iloadࠊ࢟ࣕࣃࢩࢱࡢ㟁ὶࢆ Ic ࡜ᐃ⩏ࡍࡿ࡜ࠊ㈇Ⲵ㟁ὶࡀຊ⋡㸯࡛࠶ࢀࡤࠊ࢟ࣕࣃࢩ

3.3 ⪃ᐹ 㸰❶࡛ᴫㄝࡋࡓࠊᩥ⊩㸦9,10㸧࡛ᥦ᱌ࡉࢀࡓᦆኻ᭱㐺ࢱ㟁ὶ࡜ࡣ఩┦ࡀ 90 ᗘࡎࢀ࡚࠸ࡿࡢ࡛ࠊ࢖ࣥࢲࢡࢱࡢ㟁ὶ໬ࡢ࢔ࣉ࣮ࣟࢳ࡟㛵ࡋ࡚ࡣࠊᮏㄽᩥ࡛ࡍ࡭࡚ࡢ࠙㡯┠㸱ࠚࡢ᣺ᖜ IL ࡣࠊḟᘧ࡛㏆ఝ࡛ࡁࡿࠋ

࡜࠙㡯┠㸲ࠚࡢ⤌ࡳྜࢃࡏࢆ࡯ࡰ⤊஢ࡋࡓࠋṧࡾࡢᦆኻྥ
4㸭6

Hybrid Neutral Point Clamped Flying Capacitor Inverter”, CPSS

ĨĨŝĐŝĞŶĐǇǀƐĂƉĂĐŝƚĂŶĐĞ
ϵϵ͘ϴϯϲϬйTrans. On Power Electronics and Applications, Vol.4, No.1, pp. 50-61,ϵϵ͘ϴϯϱϴй

2019ĞĨĨŝĐŝĞŶĐǇ

ϵϵ͘ϴϯϱϲйϵϵ͘ϴϯϱϰй(3)Y. Shi, H.Li, L. Wang, Y. Zhang, “Intercell Transformer(ICT) Designϵϵ͘ϴϯϱϮй

Optimization and Interphase Crosstalk Mitigation of a 100-kW SiC

ϵϵ͘ϴϯϱϬй

Filter-Less Grid-Connected PV String Inverter”, IEEE OJ of Powerϵϵ͘ϴϯϰϴй

Electronics, Vol.1, pp.51-63, 2020ϵϵ͘ϴϯϰϲйϵϵ͘ϴϯϰϰй(4)J. Zhu, H. Kim, H. Chen, R. Erickson, D. Maksimovic, “Highϵϵ͘ϴϯϰϮй
ϲ

ϲ͘ϱ

ϳ

ϳ͘ϱ

ϴ

ϴ͘

ĂƉĂĐŝƚĂŶĐĞƵ&

ᅗ 8 ࢟ࣕࣃࢩࢱࣥࢫኚ໬᫬ࡢ᭱኱ຠ⋡(newPCB#5)
Fig. 8 Maximum efficiency when the capacitanceis changed(new PCB#5)
ୖࡢྍ⬟ᛶࡣࠊࣃ࣮࣡ࢹࣂ࢖ࢫࡢᨵⰋ࡟ࡼࡿࢫ࢖ࢵࢳࣥࢢ

efficiency SiC Traction Inverter for Electric Vehicle Applications”, pp.
1428-1433, APEC2018(5)J. Rabkowski, D. Peftitsis, H. Nee, “Design Steps Towards 140-kVA
SiC Inverter With an Efficiency Exceeding 99.5%”, APEC2012(6)T. Miyazaki, H. Otake, Y. Nakakohara, M. Tsuruya, and K. Nakahara:“A fanless operating trans-linked interleaved 5 kW inverter using SiC
MOSFETs to achieve 99% power conversion efficiency”, IEEE Trans.
Ind. Electron., Vol.65, Issue12, pp.9429-9437, 2018.

ᦆ࡜ᑟ㏻ᦆࡢపῶ࡜⪃࠼ࡽࢀࡿࠋ

(7) A. Kawamura, Y. Nasu, Y. Miguchi, H. Setiadi, H. Obara, “Proposal

4㸬ࡲ࡜ࡵ ᐃ⢭ᗘࡢ㧗࠸㟁ຊኚ᥮ჾࡢᦆኻ ᐃἲ㸦VTASLM
ᐃἲ(7)㸧ࢆ᥇⏝ࡋ࡚ࠊ㸰㟁※ HEECS ࢖ࣥࣂ࣮ࢱࡢᦆኻపῶ
ᡭἲ(9,10)ࡀᥦ᱌ࡉࢀࡓࡢ࡛ࠊࡇࡢ㸰ࡘࡢᡭẁ࡟ࡼࡗ࡚ࠊᦆ
ኻࡢ᭱ᑠ໬ࢆ㏣ồࡋࡓࠋࡍ࡛࡟ᵝࠎ࡞᭱㐺໬ࡀ᳨ウࡉࢀࡓࡢ࡛(8,9)ࠊᐇドࡀᮍ᳨ウ࡛ṧࡗ࡚࠸ࡿ㒊ศࢆ᳨ウࡋࡓࠋ≉࡟ࠊᮏㄽᩥ࡛ࡣࠊ࢖ࣥࢲࢡࢱ࡜࢟ࣕࣃࢩࢱࡢࣃ࣓࣮ࣛࢱ
ࢆ᭱㐺໬ࡍࡿࡇ࡜ࢆᐇ㦂ⓗ࡟᳨ウࡋࡓࠋ࢖ࣥࢲࢡࢱ࡟㛵ࡋ࡚ࡣࠊᕳࡁ⥺᢬ᢠࠊᇶᮏἼ㕲ᦆࠊ㧗ㄪἼᦆኻࡢ㸱ࡘࡀ㐃ືࡋ࡚࠸ࡿࡇ࡜࡟ὀ┠ࡋࠊ᪂ࡋ࠸࢖ࣥࢲࢡ
ࢱࢆヨసࡋ࡚ࠊᐇ

ࡋࡓࠋࡲࡓࠊ࢟ࣕࣃࢩࢱ࡟㛵ࡋ࡚ࡣࠊᑟ

㏻ᦆ࡜ไᚚᛶ⬟ࡀᦆኻ࡟㛵㐃ࡋ࡚࠸ࡿࡇ࡜࡟ὀ┠ࡋ࡚ࠊྛ✀࢟ࣕࣃࢩࢱࣥࢫࡢ್࡛ᦆኻࢆᐇ

ࡋࡓࠋࡑࡢ⤖ᯝࠊ⌧≧࡛ࡢ᭱㧗ຠ⋡࡜ࡋ࡚ࡣࠊ㟁ຊኚ᥮ຠ⋡ 99.836±0.004㸣㸦1300W
ฟຊ㸧ࡀᐇ

of Virtual Transformer based Back-to-Back Asynchronous Loss
Measurement using a Single Set of Measurement Instrument andExperimental Verification”, IEEJ Journal of Industry Applications,Vol.11, No.1, pp. 175-184, 2022 (DOI:10.1541/ieejjia.21008251)(8)ἙᮧࠊV. Phamࠊ࿡ཱྀࠊᑠཎࠊ͆HEECS ࢖ࣥࣂ࣮ࢱࡢ࢖ࣥࢲࢡ
ࢱࡢኚ໬࡟ࡼࡿຠ⋡ᨵၿ࡟㛵ࡍࡿ᳨ウ͆ࠊ㟁ẼᏛ఍඲ᅜ኱఍ࠊ
4-053ࠊ2023 ᖺ 3 ᭶(9)A. Kawamura, Y. Miguchi, H. Setiadi, H. Obara, “Survey of 99.9%
Class Efficiency DC-AC Power Conversion and Technical Issues”,
IEEJ TEEE, Vol.18, No.1, pp.6-14, 2023 (doi.org/10.1002/tee.23728)(10)ἙᮧࠊH. Setiadiࠊ࿡ཱྀࠊ㑣㡲ࠊᑠཎࠊ͆㧗ຠ⋡ HEECS ࢖ࣥࣂ࣮ࢱࡢᦆኻపῶ࡟㛵ࡍࡿ୍⪃ᐹ͇ࠊ㟁ẼᏛ఍༙ᑟయ㟁ຊኚ᥮◊✲఍ SPC-22-059ࠊ2022 ᖺ 3 ᭶(11) ࿡ཱྀࠊ㑣㡲ࠊᑠཎࠊἙᮧࠊ
͆㉸㧗ຠ⋡༢┦⣔⤫㐃⣔࢖ࣥࣂ࣮ࢱ㸦HEECS㸧ࡢ㟁ὶไᚚ͇ࠊ㟁ẼᏛ఍◊✲఍ SPC-20-128ࠊ2020࡛ࡁࡓࠋ௒ᚋࡢᦆኻ᭱ᑠ໬ࡢࡓࡵ࡟ࡣࠊࣃ࣮࣡ࢹࣂ࢖ࢫࡢᛶ⬟ྥୖࡢ㐍ᒎ࡟ࡼࡿ࡜ࡇࢁࡀ኱ࡁ࠸࡜⪃࠼ࡽࢀࡿࠋ࡞࠾ࠊHEECS ࢖ࣥࣂ࣮ࢱࡢ⣔⤫㐃⣔࡬ࡢᛂ⏝࡟㛵ࡋ࡚ࡣࠊᩥ⊩㸦14,15㸧࡟ヲࡋࡃࠊ㐜ࢀࡸ㐍ࡳࡢຊ⋡㈇Ⲵ࡛ࡶไᚚࢆᕤ
ኵࡍࢀࡤᏳᐃ࡟ືసࡍࡿࡇ࡜ࡀሗ࿌ࡉࢀ࡚࠸ࡿࠋᖺ(12) R. W. Erickson, D. Maksimovic, “Chapter 13: Basic Magnetic
Theory, Fundamentals of Power Electronics”, pp. 491-537, 2001,
Springer Link
(13) ἙᮧࠊV. Phamࠊ࿡ཱྀࠊᑠཎࠊ͆HEECS ࢖ࣥࣂ࣮ࢱࡢ࢖ࣥࢲࢡࢱࡢ෌〇స࡟ࡼࡿຠ⋡ᨵၿࡢᐇ㦂ሗ࿌͆ࠊ㟁ẼᏛ఍඲ᅜ኱఍ࠊ

ㅰ㎡㸸ᮏ◊✲ࡣ⛉◊㈝ 17H06147 ࠾ࡼࡧᐤ㝃ㅮᗙ㸦ࣃ࣮࢚࣡ࣞࢡࢺࣟࢽࢡࢫ㸧࡟ࡼࡾຓᡂࡉࢀ࡚࠸ࡿࠋ

K507-C3ࠊ2024 ᖺ 3 ᭶(14)Y. Miguchi, H. Setiadi, Y. Nasu, H. Obara, A. Kawamura, “Control
Schem for Leading Power Factor operation of Single-Phase GridConnected Inverter Using an Unfolding Circuit”, IEEE Open Journalᩥ   ⊩(1)A. Kawamura, S. Nakazaki, S. Ito, S. Nagai, H. Obara, “Over 99.7%
Efficiency Two Battery HEECS Inverter at 2.2kW Output and
Measurement Accuracy based on Loss Breakdown”, IEEJ Journal ofIndustry Applications, Vol.9, No.6, pp.663-673, 2020of Power Electronics, Vol.3,pp.468-480, 2022
(15) Y. Miguchi, H. Obara, A. Kawamura, “Control Schem for Lagging
Power Factor operation of Single-Phase Grid-Connected Inverter
Using an Unfolding Circuit”, IEEE Open Journal of PowerElectronics, Vol.5,pp.145-161, 2024

(2)J. A. Anderson, E.J. Hanak, L. Schrittwieser, M. Guacci, WJ.G. Kolar,
G. Deboy, “All-Silicon 99.35% Efficiency Three Phase Seven 3-Level
5㸭6