BUK9K13-60RA

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in
LFPAK56D using Repetitive Avalanche technology
2 December 2020

Product data sheet

1. General description
Dual, logic level N-channel MOSFET in an LFPAK56D package, using Application Specific(ASFET) repetitive avalanche silicon technology. This product has been designed and qualified to
AEC-Q101 for use in repetitive avalanche applications.

2. Features and benefits•••

Fully automotive qualified to AEC-Q101 at 175 °C
Repetitive Avalanche rated to 30 °C Tj rise:• Tested to 1 Bn avalanche events
LFPAK copper clip package technology:• High robustness and reliability• Gull wing leads for high manufacturability and AOI

3. Applications
•
•
•
•
•

12 V, 24 V and 48 V automotive systems
Repetitive avalanche topologies
Engine control
Transmission control
Actuator and auxiliary loads

4. Quick reference data
Table 1. Quick reference data
SymbolParameter

Conditions

Min

Typ

Max

Unit

VDS

drain-source voltage

25 °C ≤ Tj ≤ 175 °C

-

-

60

V

ID

drain current

VGS = 5 V; Tmb = 25 °C; Fig. 2

-

-

40

A

Ptot

total power dissipation

Tmb = 25 °C; Fig. 1

-

-

64

W

VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 14

6.1

10

12.5

mΩ

-

7.9

-

nC

Static characteristics FET1 and FET2
RDSondrain-source on-state
resistance

Dynamic characteristics FET1 and FET2
QGD

gate-drain charge

ID = 10 A; VDS = 48 V; VGS = 5 V;
Tj = 25 °C; Fig. 16; Fig. 17

BUK9K13-60RA

Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology

5. Pinning information
Table 2. Pinning information
Pin
SymbolDescription
1

S1

source1

2

G1

gate1

3

S2

source2

4

G2

gate2

5

D2

drain2

6

D2drain2

7

D1drain18

D1drain1

Simplified outline
8

7

6

Graphic symbol
5

D1 D1

S1

D2 D2

G1

S2

G2
mbk725

1

2

3

4

LFPAK56D; DualLFPAK (SOT1205)

6. Ordering information
Table 3. Ordering information
Type number
Package
BUK9K13-60RA

Name

Description

VersionLFPAK56D;
Dual LFPAK

plastic, single ended surface mounted package (LFPAK56D); 8
leads

SOT1205

7. Marking
Table 4. Marking codes
Type number

Marking code

BUK9K13-60RA

91360RA

8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
SymbolParameter

Conditions

Min

Max

Unit

VDS

drain-source voltage

25 °C ≤ Tj ≤ 175 °C

-

60

V

VDGR

drain-gate voltage

RGS = 20 kΩ

-

60

V

VGS

gate-source voltage

DC; Tj ≤ 175 °C

-10

10

V

-15

15

V

Pulsed; Tj ≤ 175 °C[1] [2]

Ptot

total power dissipation

Tmb = 25 °C; Fig. 1

-

64

W

ID

drain current

VGS = 5 V; Tmb = 25 °C; Fig. 2

-

40

A

VGS = 5 V; Tmb = 100 °C; Fig. 2

-

33

A

pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3

-

190

A

IDM

peak drain current

Tstg

storage temperature

-55

175

°C

Tj

junction temperature

-55

175

°C

Tsld(M)

peak soldering
temperature

-

260

°C

IS

source current

-

40

A

BUK9K13-60RA

Product data sheet

Tmb = 25 °C

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BUK9K13-60RA

Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology

SymbolISM

Parameter

Conditions

Min

Max

Unit

peak source current

pulsed; tp ≤ 10 µs; Tmb = 25 °C

-

190

A

[3] [4]
[5]

-

75.2

mJ

[6] [7]-

82

mJ

Avalanche ruggedness
EDS(AL)R

repetitive drain-source
avalanche energy

ID = 1.92 A; Vsup ≤ 60 V; RGS = 10 Ω; VGS=10 V; Tj(rise) ≤ 30 °C; unclamped; Fig. 4;
Fig. 5; Fig. 6

Avalanche Ruggedness FET1 and FET2EDS(AL)S

[1]
[2]
[3]
[4]
[5]
[6]
[7]

non-repetitive drainID = 40 A; Vsup ≤ 60 V; RGS = 50 Ω;source avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped;
Fig. 7

Accumulated Pulse duration up to 50 hours delivers zero defect ppm
Significantly longer life times are achieved by lowering Tj and or VGS.
Repetitive avalanche rating is limited by maximum junction temperature of 175 °C and junction rise of 30 °C
Refer to Fig. 5 for the limiting number of avalanche events
Refer to Fig. 6 Rdson at Vgs=5V will increase as a function of repetitive avalanche cycles
Refer to application note AN10273 for further information
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C
03aa16

120

ID
(A)

Pder
(%)

003aak109

50

40

(1)

80

30

20
40

10

0

0

50

100

150

Tmb (°C)

0200

Fig. 2.
Fig. 1.

Normalized total power dissipation as afunction of mounting base temperature

BUK9K13-60RA

Product data sheet

0

25

75

100

125

150 175
Tmb (°C)

200

Continuous drain current as a function ofmounting base temperature

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Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology
ID(A)

003aak108

103

Limit RDSon = VDS / ID
102

tp = 10 us
100 us

10

DC

1 ms

1

10 ms
100 ms
10-1
10-1

1

102

10

VDS (V)103

Tmb = 25°C; IDM is a single pulse
Fig. 3.
IAL(A)

Safe operating area; continuous and peak drain currents as a function of drain-source voltage
aaa-031580

102

aaa-031583

1010
No.
events

109

10

1
10-3

10-2

10-1

1

tAL (ms)

108

10

Tj is limited to 175 °C and Tj(rise) is limited to 30 °C
Repetitive avalanche rating; avalanche current
as a function of avalanche time
% Increase of Rdson at 5V Vgs

Fig. 4.

Fig. 5.

1

10102
EDS(AL) per event (mJ)

Repetitive avalanche rating; maximum numberof avalanche events as a function of avalancheenergyaaa-032338

50

40

30

20

10

0

Fig. 6.

1

10% of cycle limit

102

Percentage Rdson at 5V increase as a function of avalanche cycles

BUK9K13-60RA

Product data sheet

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Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology
IAL(A)

aaa-030544

102

10

1
10-3

10-2

10-1

1
tAL (ms)10

Tj (init) = 25 °C
Fig. 7.

Single pulse avalanche rating; avalanche current as a function of avalanche time

9. Thermal characteristics
Table 6. Thermal characteristics
SymbolParameter

Min

Typ

Max

Unit

Rth(j-mb)

thermal resistance from Fig. 8junction to mounting
base

Conditions

-

-

2.36

K/W

Rth(j-a)thermal resistance from Minimum footprint; mounted on ajunction to ambient
printed circuit board

-

95

-

K/W

003aaj748

10

Zth(j-mb)(K/W)δ = 0.5
1
0.2
0.1
0.05
10-1

P

0.02

δ=

single shot
tp
10-2
10-6

Fig. 8.

10-5

10-4

10-3

10-2

10-1

tp
T

t
T
tp (s)

1

Transient thermal impedance from junction to mounting base as a function of pulse duration

BUK9K13-60RA

Product data sheet

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Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology

10. Characteristics
Table 7. Characteristics
SymbolParameter

Conditions

Min

Typ

Max

Unit

drain-source
breakdown voltage

ID = 250 µA; VGS = 0 V; Tj = -55 °C

54

-

-

V

ID = 250 µA; VGS = 0 V; Tj = 25 °C

60

-

-

V

gate-source thresholdvoltage

ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 12;
Fig. 13

1.4

1.7

2.1

V

ID = 1 mA; VDS=VGS; Tj = 175 °C;
Fig. 12

0.5

-

-

V

ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 12

-

-

2.45

V

VDS = 60 V; VGS = 0 V; Tj = 25 °C

-

0.02

1

µA

VDS = 60 V; VGS = 0 V; Tj = 175 °C

-

-

500

µA

VGS = -10 V; VDS = 0 V; Tj = 25 °C

-

2

100

nA

VGS = 10 V; VDS = 0 V; Tj = 25 °C

-

2

100

nA

VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 14

6.1

10

12.5

mΩ

VGS = 5 V; ID = 10 A; Tj = 175 °C;
Fig. 14; Fig. 15

-

22

28.3

mΩ

VGS = 10 V; ID = 10 A; Tj = 25 °C;
Fig. 14

5.4

9

11.2

mΩ

-

22.4

-

nC

-

5.2

-

nC

-

7.9

-

nC

-

2215

2953

pF

-

225

270

pF

-

116

159

pF

-

13

-

ns

-

22.1

-

ns

Static characteristics FET1 and FET2
V(BR)DSS
VGS(th)

IDSS
IGSS
RDSon

drain leakage current
gate leakage current
drain-source on-state
resistance

Dynamic characteristics FET1 and FET2
QG(tot)total gate charge

QGSgate-source charge

QGD

gate-drain charge

Cissinput capacitanceCossoutput capacitanceCrssreverse transfer
capacitancetd(on)

turn-on delay timetrrise timetd(off)turn-off delay time

-

30.5

-

ns

tf

fall time

-

21.8

-

ns

ID = 10 A; VDS = 48 V; VGS = 5 V;
Tj = 25 °C; Fig. 16; Fig. 17
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 18

VDS = 48 V; RL = 5 Ω; VGS = 5 V;
RG(ext) = 5 Ω; Tj = 25 °C

Source-drain diode FET1 and FET2
VSD

source-drain voltage

IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 19

-

0.78

1.2

V

trr

reverse recovery time

-

22.7

-

ns

Qr

recovered charge

IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 30 V; Tj = 25 °C

-

18.9

-

nC

BUK9K13-60RA

Product data sheet

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Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology
ID(A)

003aak102

40

10 V

4.5 V

003aak101

50
RDSon
(mΩ)

2.8 V

32

40
VGS = 2.6 V

24

30

16

20
2.4 V

8

10
2.2 V

0

0

1

2

3
VDS (V)

0

4

0

2

4

6

8
VGS (V)10

Tj = 25 °C; tp = 300 μs
Fig. 9.

Output characteristics; drain current as a
Fig. 10. Drain-source on-state resistance as a function
function of drain-source voltage; typical valuesof gate-source voltage; typical values
aaa-016783

120
ID
(A)
100

003aah025

3
VGS(th)
(V)
2.5
max

80

2

60

1.5

40

1

typ

175°C

Tj = 25°C

20
0

0

1

2

3

4

VGS (V)

0.5
0
-60

5

Fig. 11. Transfer characteristics; drain current as afunction of gate-source voltage; typical values

BUK9K13-60RA

Product data sheet

min

0

60

120

Tj (° C)180

Fig. 12. Gate-source threshold voltage as a function ofjunction temperature

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Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology
003aah026

10-1
ID
(A)
10

003aak107

50
RDSon
(mΩ)

-2

2.6 V

2.8 V

40

min

10-3

typ

max

30

10-4

20

10-5

10

3V
4.5 V
VGS = 10 V

10-6

0

1

2

V GS (V)

0

3

0

5

10

15

20

25

30
35
ID (A)

40

Tj = 25 °C; tp = 300 μs
Fig. 13. Sub-threshold drain current as a function ofgate-source voltage

Fig. 14. Drain-source on-state resistance as a functionof drain current; typical values

003aaj816

2.4

VDS

a
ID

1.6
VGS(pl)0.8

VGS(th)
VGS
QGS2

0
-60

QGS1

0

60

120

Tj ( °C)

QGS

180

QGD
QG(tot)003aaa508

Fig. 16. Gate charge waveform definitions
Fig. 15. Normalized drain-source on-state resistancefactor as a function of junction temperature

BUK9K13-60RA

Product data sheet

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BUK9K13-60RA

Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology
VGS(V)

003aak104

10

8003aak105

104
C
(pF)

Ciss

VDS = 14 V
103

6
Coss
4

48 V

102
Crss

2

0

0

10

20

30

40
QG (nC)

10
10-1

50

10

VDS (V)102

Fig. 18. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typicalvaluesFig. 17. Gate-source voltage as a function of gatecharge; typical values

IS
(A)

1

003aak106

40

30

20

10

0

175°C

0

0.2

0.4

Tj = 25°C

0.6

0.8

1
VSD (V)

1.2

Fig. 19. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values

BUK9K13-60RA

Product data sheet

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Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology

11. Package outline
Plastic single ended surface mounted package LFPAK56D; 8 leads

E

SOT1205

A

A

b1

c1

L1

mounting
base

D

H

D1
D2

L
1

2

3

e

b
(8x)

4
w

X

c

A

E1
E2

A1

C
θ
Lp

detail X

0

2.5

mm

5 mm

scale

Dimensions
Unit

y C

D(1) D1(1)

D2
(ref)

E(1) E1(1)

E2

4.4

0.25 0.30 4.70 4.55

3.5

5.30

1.8

0.85

4.1

0.19 0.24 4.45 4.35

3.4

4.95

1.6

0.60

A

A1

b

b1

max 1.05
nom
min 1.02

0.1

0.50

0.0

0.35

c

c1

e
1.27

H

L

L1

Lp

6.2

1.3

0.55 0.85

5.9

0.8

0.30 0.40

Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OutlineversionReferences
IEC

JEDEC

JEITA

w

y

θ

0.25

0.1

8°
0°
sot1205_po

Europeanprojection

Issue date
14-08-21
14-10-28

SOT1205

Fig. 20. Package outline LFPAK56D; Dual LFPAK (SOT1205)

BUK9K13-60RA

Product data sheet

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Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology

12. Soldering
Footprint information for reflow soldering of LFPAK56D package

SOT1205

5.85
0.57

0.025

0.57

0.7

1.97

0.65

1.27

1.9
3.325
3.175

3.2
2.0
1.275

0.8
1.875

2.1
2.7

1.0

3.85

3.975
0.025

1.1

1.15

0.65

1.27
1.1

1.44

solder landsolder land plus solder paste

solder paste deposit

solder resist

occupied area

Dimensions in mm

Issue date

0.7

14-07-28
20-04-20

sot1205_fr

Fig. 21. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205)

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Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology
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13. Legal information
Data sheet status
Document status[1][2]

Product
status [3]Definition

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.

Objective [short]data sheet

Development

This document contains data fromthe objective specification for
product development.

Preliminary [short]data sheet

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This document contains data fromthe preliminary specification.

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or warranty that such applications will be suitable for the specified use
without further testing or modification.

Product [short]data sheet

Production

This document contains the productspecification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating orcompleting a design.
The term 'short data sheet' is explained in section "Definitions".
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Product data sheet

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2 December 2020

© Nexperia B.V. 2020. All rights reserved

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BUK9K13-60RA

Nexperia

Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche
technology

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking.......................................................................... 2
8. Limiting values............................................................. 2
9. Thermal characteristics............................................... 5
10. Characteristics............................................................ 6
11. Package outline........................................................ 10
12. Soldering................................................................... 11
13. Legal information......................................................12© Nexperia B.V. 2020. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 2 December 2020

BUK9K13-60RA

Product data sheet

All information provided in this document is subject to legal disclaimers.

2 December 2020

© Nexperia B.V. 2020. All rights reserved

13 / 13