Nuclear Instruments and Methods in Physics Research A 765 (2014) 118–124

Contents lists available at ScienceDirect

Nuclear Instruments and Methods inPhysics Research A
journal homepage: www.elsevier.com/locate/nima

Development of Nþ in P pixel sensors for a high-luminosity large
hadron collider
Shintaro Kamada a,n, Kazuhisa Yamamura a, Yoshinobu Unno b, Yoichi Ikegami babHamamatsu Photonics, 1126-1 Ichino-cho, Hamamatsu City 435-8558, Japan
Institute of Particle and Nuclear Study, KEK, Oho 1-1, Ibaraki, Tsukuba 305-0801, Japan

art ic l e i nf o

a b s t r a c t

Available online 27 May 2014

Hamamatsu Photonics K. K. is developing an Nþ in a p planar pixel sensor with high radiation tolerance
for the high-luminosity large hadron collider (HL-LHC). The Nþ in the p planar pixel sensor is acandidate for the HL-LHC and offers the advantages of high radiation tolerance at a reasonable pricecompared with the Nþ in an n planar sensor, the three-dimensional sensor, and the diamond sensor.
However, the Nþ in the p planar pixel sensor still presents some problems that need to be solved, suchas its slim edge and the danger of sparks between the sensor and readout integrated circuit. We are now
attempting to solve these problems with wafer-level processes, which is important for mass production.
To date, we have obtained a 250-μm edge with an applied bias voltage of 1000 V. To protect against highvoltage sparks from the edge, we suggest some possible designs for the N þ edge.
& 2014 Published by Elsevier B.V.

Keywords:
ATLAS
Pixel
N þ in p
Slim edge
Al2O3
Edge spark

1. Introduction
Several candidates exist to serve as pixel sensors for the highluminosity large hadron collider (HL-LHC), such as the N þ in a pplanar sensor, the N þ in an n planar sensor, the three-dimensional(3D) sensor, and the diamond sensor. Hamamatsu Photonics K. K.
has been developing an N þ in the p planar pixel sensor with highradiation tolerance for the HL-LHC.
The N þ in the p planar sensor offers several advantages, theﬁrst of which is its cost effectiveness. Because N þ in p planarsensors is fabricated by a simple wafer process with masks only ona single side, the process has good yield compared with othertypes of sensors. In addition, in the high radiation environment,
the lifetime of the N þ in p planar sensor is longer than that ofother P þ in n sensors fabricated via the single-side process [1].
Because the N þ in the p sensor does not rely on induced typeinversion after irradiation, it is possible to read signals even when
the sensor is partially depleted (i.e., after the full depletion voltage
has exceeded the bias voltage applied after irradiation).
However, N þ in p planar sensor type also has certain disadvantages, the ﬁrst of which involves the width of the inactive
edge, which is typically wider than the N þ in the n planar sensor[2] and the 3D sensor [3]. The second problem involves sparking
between the sensor and the readout application-speciﬁcnCorresponding author.
E-mail address: skamada@ssd.hpk.co.jp (S. Kamada).

http://dx.doi.org/10.1016/j.nima.2014.05.029
0168-9002/& 2014 Published by Elsevier B.V.

integrated circuit (ROIC), which occurs because the edge of N þin the p sensor is exposed to high voltage and the gap between
sensor and ROIC is only 20 μm. If we can overcome these
problems, the N þ in the p planar sensor would be very competitive. Herein, we report preliminary results of research that aims
to resolve these problems.

2. Slim edge
2.1. Previous results
Pixel sensors are located at the heart of large complex detectors
and serve to track signals close to the interaction point. This area
contains a lot of important signals, so detecting all tracks isdesirable. However, it is not realistically possible to detect all
tracks that cross a pixel sensor because of the dead area of sensors.
The edge of an ordinary pixel sensor constitutes such a dead area
because a certain distance is needed to prevent the depletion
region from contacting the dicing edge.
In a previous study [4], by shrinking the distance from theactive area to the dicing edge to 400 μm, we obtained a toleranceof over 1000 V (see Figs. 1 and 2). However, at 1000 V and withless than 400 μm from active area to dicing edge, the depletion
region contacted the dicing edge, and a signiﬁcant leakage current
ﬂowed from the dicing edge. Thus, 1000 V tolerance was notpossible with an edge distance of less than 400 μm.

S. Kamada et al. / Nuclear Instruments and Methods in Physics Research A 765 (2014) 118–124

N+P+

Guard Ring

Chip Edge

N+ active

320umt

P-sub

Vfd
~220V

P+

distancefrom active edge to dicing edge
232 μm / 272 μm / 312 μm /352 μm / 402 μm / 552 μm
Fig. 1. Cross-section of previous slim-edge trial. The edge was shrunk by a simple
planar process.
PIXEL-2nd trial (W2) Slim edge 4mm

MD

1.E-06

1.E-07ref) std(1000)

312um

232um

W2-232352um

1.E-08

W2-272

I (A)

272um

W2-312W2-352

1.E-09W2-402

1.E-10W2-552> 402um

1.E-11
0

200

400

600

800

1000

V (V)

Fig. 2. I–V curves from previous slim-edge trial. For an edge distance of less than
400 μm, the voltage tolerance was less than 1000 V.

WaferSiO2
ProcessALas usual

119oxide layer. The total thickness of Al2O3 was 30 nm. Al2O3 layer
made by ALD gives good coverage of the side wall. The Si–Al2O3
or SiO2–Al2O3 interface makes positive charges at the Si surface.
The depletion layer and negative space charge in the p-type
wafer are suppressed by the positive charges that accumulate
at the Si surface, and the depletion region does not touch
the sensor edge. Thus, no leakage current ﬂows from the sensoredge.
4. The ﬁnal process is dicing of non-slim edge lines.

2.3. Test pattern to evaluate minimum distanceTo evaluate the minimum distance, we fabricated a test patternconsisting of a 4-mm monitor diode with a single slim-edge side,
as shown in Figs. 4 and 5. We made four types, which weredistinguished by the distance from the active area to edge of 210,
250, 290, and 310 μm.
The current–voltage (I–V) results are shown in Fig. 6. The data
indicating a tolerance of 1000 V is obtained for over 250 μm fromthe active area to slim edge. In addition, we also conﬁrmed thepoor I–V characteristics and low voltage tolerance when Al2O3
passivation was not used. Thus, the Al2O3 charge effect contributed
to the good I–V characteristics, which implies that the depletion
region was not contacting the sensor edge.
For the 210-μm edge pattern, breakdown occurred at 700 V.
However, by observing the hot electrons [6], we conﬁrmed thatthe breakdown occurred between guard-ring N þ and edge Pþ .
This breakdown was induced by the strong electric ﬁeld across thenarrow PN gap, not by contact between the slim edge anddepletion region. Thus, by optimizing the design, we may obtaina tolerance of 1000 V with an edge of less than 200 μm. This workis planned for the near future.

P+

N+
N+ areaarea

2.3. Apply slim edge to a 20-mm pixel sensor for FE-I4
ATLAS-upgradeN+
N+ areaarea

N+
N+ areaarea
P-

As mentioned in the previous section, we conﬁrmed the 250-μm
slim edge by using a 4-mm monitor diode. Next, we applied thisP+

1 chip region
DRY etch penetration + Al2O3 coating
N+ area+++++N+ areaN+ area
+
+
+
+
+

+
+
+
+
+

+
+
+
+
+

P-

+
+
+
+
+

+
+
+
+
+

+
+
+
+
+

+
+
+
+
+

275 μmtP+

Fig. 3. Process ﬂow for slim-edge trial.

2.2. Slim edge process
To overcome this limit, a new technology had to be developed
to prevent the depletion region from contacting the sensor edge.
We based our approach on the sidewall Al2O3 passivation trial by
SCIPP [5] and expanded the technology to the wafer process. Notethat completing the process on wafer form is important for mass
production.
For our ﬁrst trial, we used a square 4-mm monitor diode andmade one side the slim edge. Fig. 3 shows the process ﬂow.
1. Fabricate PN junction and metallize as usual.
2. Penetrate through wafer by dry etching. In this trial, standard
trench width was 200 μm, and in addition, we conﬁrmed 20 μm
width trench also went well.
3. Deposit Al2O3 by atomic layer deposition (ALD). Just before thedeposition, we executed a process of eliminating a thin native

Fig. 4. Top view of test pattern consisting of 4-mm monitor diode and a single
slim-edge side.

N+ activeN+

P+

Guard Ring

Chip Edge +

P-sub
P+

+
+
+
+

distance from active area to dicing edge
210um/ 250um/ 290um/ 310um/ 350um
Fig. 5. Cross-section of test pattern.

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PIXEL-2nd trial (W17) Slim edge 4mm MD

1.E-06210um
1.E-07

W17-210
W17-250

1.E-08I (A)>250umW17-290
W17-310

1.E-09W17-350

1.E-101.E-11
0

200

400

600

800

1000

As shown in Fig. 7, slim-edge distances in this trial were 310
and 480 μm, which are wider than those for the trial described in
Section 2.3. The reason for the larger edges in this trial is that weapplied the edge-slimming process to existing wafers that were
not optimized for minimum-edge design. However, 310-μm edges
were sufﬁciently slim for our purpose. As mentioned in Section 2.1,
a 310-μm edge fabricated by the usual planar process has atolerance of only 400 V. Fig. 8 shows the I–V results for this trial.
The results conﬁrm the good I–V characteristics and the toleranceof over 1000 V.
Based on these results and those of Sections 2.3, we believe it ispossible to fabricate three-side slim-edge detectors with edges ofless than 250 μm. This study is planned for the near future.

V (V)Fig. 6. I–V curve for slim-edge trial. For 250 μm, 290 μm, 310 μm, and 350 μm from
active area to slim edge, a tolerance of 1000 V was obtained.

310 μm slim edge

480 μmslim edge

2.4. Reliability test of slim edge under UV irradiation
Thus far, we have discussed the desirable results regarding theinitial characteristics of the detector. However, we must guaranteethat these good characteristics still apply in the HL-LHC environment. To determine this, we used irradiation experiments tosimulate the HL-LHC environment. These experiments were doneat KEK and consisted of irradiating these samples by 70 MeV
protons. The results should be available in the near future and will
be reported in a future presentation.
To obtain results more rapidly, we tested the resistance of thesamples to UV irradiation. The samples consisted of 4-mm monitor
diodes with a single slim-edge side. However, these samples
differed from those described in Section 2.2 (those samples were
not available in time for irradiation tests). The samples used for
UV-irradiation experiments had a wafer thickness of 275 μm andtrench depth of 160 μm (i.e., not penetrated). We used deposited
Al2O3 and stealth dicing in various lines, as shown in Fig. 9.
The distance from the active area to trench was a constant 350 μm,
and that from the active area to dicing edge was 360, 400, and450 μm. Fig. 10 shows the initial I–V characteristics of the samples.

310 μm slim edge

D2 Lamp condition
λ p=200nm 6cm distanceFig. 7. Top view of a 20-mm pixel sensor. We fabricated slim edges on three sides.

UV

208

N+

N+ active

Guard Ring
P-sub

PIXEL-2nd trial (W18) FEI4-PIX

1.E-06

P++
Chip Edge
+
+

+++++

350um constantP+

W18-FEI4_PIX-P1

360um

W18-FEI4_PIX-P2

400um
450um

4mm Monitor Diode1 side slim edge

1.E-07

3 types dicing edge
(by Stealth Dicing)

I (A)Fig. 9. Cross-section of slim-edge pattern and setup for UV irradiation.

1.E-08

1.E-09
0

200

400

600

800

1000

V (V)
Fig. 8. I–V curves for the 20-mm pixel sensor with slim edges on three sides. The
voltage tolerance was greater than 1000 V.

technology to a real pixel sensor for the FE-I4 ATLAS upgrade. The
pixel sensor surface area is about 20  20 mm2 and the thickness is
275 μm. We fabricated slim edges on three sides by Si penetration
and Al2O3 passivation.

Fig. 10. I–V curves for test pattern from Fig. 9.

S. Kamada et al. / Nuclear Instruments and Methods in Physics Research A 765 (2014) 118–124

Radiant Intensity( W .cm-2 .nm-1 at 50cm)

Breakdown occurred at 600 V for the 360-μm edge. However,the 400 and 450 μm edges had a tolerance of over 1000 V. These
results indicate two things: ﬁrst, when the depletion region
reaches the trench, the leakage current did not increase by the
Al2O3 interface charge. Second, when the depletion region reached
the dicing edge, signiﬁcant leakage current ﬂowed from thedicing edge, which was the case for the 360-μm edge. Thus, thesamples with 400 and 450 μm edges had a tolerance of 1000 V
because of the Al2O3 interface charge and sufﬁcient distance to the
dicing edge.
Next, we describe the experimental conditions and discuss theresults of the UV irradiation experiment. The UV spectrum is shown in

121

Fig. 11. The peak wavelength was 200 nm and the irradiation intensity
was about 0.1 μW/cm2 at 50 cm from the source. In the experiments,
the UV source was about 6 cm from the sample.
We irradiated the Al2O3 side wall with UV light, as indicated inFig. 9. Irradiation time was up to 111 h. Fig. 12 shows the I–V
results for various irradiation times.
Ten hours of UV irradiation produced no change from the initial
result. However, after 25 h of UV irradiation, the leakage current
from 400- and 450-μm edges increased at about 600 V. After 111 hof UV irradiation, the I–V characteristics were essentially the same
as for 25 h of UV irradiation.
We attribute these results to the disappearance of the Al2O3
interface-charge effect, which allows the depletion region tocontact the trench edge. But the increase in the dark current forthe samples with 400- and 450-μm edges was more moderate
than for samples with a 360-μm edge, which we explain as
follows: for the 400- and 450-μm-edge samples, the depletion
region contacted only the trench edge (not the dicing edge), andthe trench edge is less damaged by the dry-etching process. As forthe disappearance of the Al2O3 interface-charge effect, we cannot
determine the cause, but we guess two possibilities. One is thechange of Al2O3 layer itself. Short wavelength light ( o300 nm)
may generate and accumulate holes to Al2O3 layer. The other cause
may be charge up of SiO2 under the Al2O3 layer. In any case, weneed to do irradiation test assumption for the HL-LHC.

3. Edge-spark protection

Wavelength (nm)Fig. 11. Spectrum of a D2 lamp used for reliability experiments.

We now discuss edge-spark protection, which is mainly in theplanning phase. Normally, N þ in p planar sensors has P þ edges toprevent depletion from spreading to the dicing edge. In addition,

Fig. 12. I–V curves after UV irradiation of samples for up to 111 h.

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high voltage (from a few hundred volts to 1000 V) is applied fromthe backside to obtain full depletion, and the voltage of the P þedge is high because the carrier types going from the back side to
the front side are all the same. However, the ROIC is near zero
volts, and the ROIC–sensor gap is only about 20 μm. Thus, sparks
may occur between sensor and ROIC, which destroys the device.
Various approaches have been taken to avoid this problem, forexample, inserting a dielectric adhesive [7]. In fact, inserting adielectric adhesive produces good results, but it needs to be done
after dicing, so it is not suitable for mass production.
To overcome this problem, we take a different approach, which
involves a countermeasure in the wafer process and so is suitable
for mass production. The concept is simple: make an N þ edge
(instead of P þ) and drop the edge voltage (as shown in Fig. 13). At
this point, this approach is at the stage of proof-of-principle test,
but in the near future experiments are planned to test it with apixel sensor.

3.1. Simulation of edge voltage
To roughly estimate the trend in edge voltage, we simulated
three types of N þ in p planar sensors:
Type A: standard P þ edge.
Type B: N þ edge with no isolation.
Type C: N þ edge with P-spray isolation (we suggest this type).
Types B and C are new types, and we suggest type C to solve theproblem of edge sparks.
The simulation conditions were as follows: assume a diodestructure with high voltage applied from the back side. The N þactive region was ground and the guard ring was ﬂoating.
The dicing edge was assumed to be an ideal clean surface tosimplify the simulation (i.e., we did not consider dicing damage).
Fig. 14 shows the results of the simulation of the edge voltage.

Conventional type

Trial type
Read out Chip

Read out Chip

GND

GND

20um gap
N+

N+

N+

N+

N+

P+

Guard Ring

Chip Edge

N+ pixel
Pstop

P-sub
P+

HV

N+

N+

N+

N+

N+

N+

Guard Ring

Chip Edge

N+ pixel
P-sub
P+

Fig. 13. Concept for protection of edge against high voltage.

Fig. 14. Simulation of edge voltage for sample types A, B, and C.

PsprayPotentialDrop

S. Kamada et al. / Nuclear Instruments and Methods in Physics Research A 765 (2014) 118–124

Type A
P+edge (std design)

Type C
N+edge (with Pspray)

Type B
N+edge (non isolation)

Psub Nedge 4mm

MD (std design)

MD (non isolation)

Psub Nedge 4mm MD

1.E-03

1.E-03

1.E-04

1.E-04

1.E-04

1.E-05

1.E-05

1.E-05

1.E-06

1.E-06

1.E-06

1.E-07I (A)1.E-03

I (A)

I (A)

Psub Pedge 4mm

1.E-07

1.E-07

1.E-08

1.E-08

1.E-08

1.E-09

1.E-09

1.E-09

1.E-101.E-101.E-101.E-11

1.E-11
0

200

400

600

800

1000

0

200

400

600

800

123

1000

1.E-11
0

200

400

V (V)

V (V)

600

800

1000

V (V)

almost same as type A

large leak current fromchip edge
Fig. 15. I–V curves for structure types A, B, and C.

Type A: edge voltage was equal to the backside voltage.
Type B: edge voltage was approximately 50% of the backside
voltage.
Type C: edge voltage was approximately 80% of the backside
voltage.

P+
Psubmending tape 60umt

P+

N+ or P+

3.2. I–V experiment for three types of structures
Initially, we fabricated structure types A–C as monitor diodes
by chance. This time, we measured the I–V characteristics (seeFig. 15). For all type, the distance between the active area and theedge implant was 320 μm.
Type A: ﬂat I–V curve up to 1000 V.
Type B: very large leakage current from chip edge even at 5 V.
Type C: almost same I–V curve as for type A.
Thus, based on these results and those presented in Section 3.1,
structure type C presents a good possibility because of both thevoltage drop and I–V characteristics.
3.3. Easy test for edge-spark protection
We used an easy test to evaluate edge-spark protection.
Ideally, the evaluation should be done with a real pixel sensor
that is bump bonded with an ROIC. However, because we did nothave a real pixel sensor with an N þ edge, we used the 4-mm
monitor diode mentioned in Section 2.2 instead. Thus, we used thetemporary setup shown in Fig. 16 to evaluate edge-spark
protection.
On the bottom side, we set types A–C 4-mm monitor diodeand applied the high voltage from the backside. On the top
side, we set the type A 4-mm monitor diode and applied theground from the back side. Between the lower and upper sensors,
we inserted a 60-μm-thick mending tape, so the gap was about

with Psprayor non isolation

N+

N+
GR

GND

P+

N+
activeN+
GR

N+ or P+PP+

0~-1000V
Fig. 16. Setup of easy test to evaluate edge-spark protection.

60 μm, which was wider than the 20 μm of the real bumpbonding gap.
The results were as follows:
Type A: edge spark occurred at 740 V.
Type B: no edge spark occurred, even at 1000 V.
Type C: edge spark occurred at 960 V.
As mentioned before, this is only a preliminary test, but theresult implies that an N þ type edge should work well for edgespark protection. We are currently processing wafers to produce
N þ edge pixel sensors and will demonstrate bump bonding andedge-spark evaluation. We expect results in the near future.

4. Summary
Hamamatsu Photonics K. K. has been developing N þ in pplanar pixel sensors with high radiation-tolerance for the HLLHC. For the slim edge, we applied Al2O3 sidewall passivation
technology for wafer processing and achieved a tolerance of1000 V with a 250-μm edge. The results also suggest that by

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S. Kamada et al. / Nuclear Instruments and Methods in Physics Research A 765 (2014) 118–124

optimizing the design, it would be possible to obtain less than 250
or 200 μm. This is our next step.
We used UV irradiation tests to evaluate the reliability of the
Al2O3 slim edge. After UV irradiation, the Al2O3 interface charge
disappeared. Other reliability tests are planned that simulate theconditions of the HL-LHC.
For edge-spark protection, we suggest using an N þ edge with
an isolation structure. Results on edge-spark protection are
expected in the near future.
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