QUALITY REPORT

Shaping the Future
Absolute Quality

This report showcases theaccomplishments of several of the
global Xilinx engineering teams
who are responsible for the many
milestones successfully reached at
28nm, 20nm and 16nm FinFET.

2

FOR XILINX, THIS YEAR WAS ALL ABOUT
BREAKTHROUGHS. BY SHATTERING RESTRICTIONSINHERENT WITH ASICs AND ASSPs, XILINX LEFTTHE COMPETITION BEHIND AND DELIVERED ON
THE PROMISE OF OUR ALL PROGRAMMABLE
VISION. THE ABSOLUTE QUALITY OF THE NEW
PORTFOLIO UNLEASHES THE POSSIBLE, AND
ENABLES OUR CUSTOMERS TO MOVE THEIRPRODUCTS A GENERATION AHEAD.

Xilinx’s commitment to excellence is exhibited by our continued execution with ABSOLUTE QUALITY.
We have delivered on this commitment across every family and every device in our product portfolio
spanning 28nm, 20nm, and 16nm. Our commitment is further demonstrated by the expansion of ourportfolio from FPGAs to the highest capacity 3D ICs, All Programmable dual core SoCs, and heterogeneous
multi-processing SoCs offering the highest levels of security and safety. Finally, from a design perspective,
our industry-leading ASIC-strength Vivado® Design Suite, expanded IP portfolio, ‘software defined’ SDx™
Development Environments, and UltraFast™ Design Methodology, incorporate design best practices for bothproductivity and quality of results. We are proud to say that we have successfully transformed Xilinx from an
FPGA company with implementation tools for hardware engineers, to an All Programmable company with
programming models required for hardware, software and systems engineers. As a result, Xilinx is enablingcustomers to rapidly create quality products that are smarter, connected and differentiated, and a generationahead of the competition.
These investments, engineering innovation, and unwavering commitment led to these successes, and we are
extremely pleased with the results. This Quality Report explains our results in terms of:

Execution

3D Packaging Innovation

SoC Integration

Design Tools Productivity

Quality that Builds Trust

16nm Leadership

Demonstrated with errata freeproducts through our 28nm
new product introduction andnow extended with 20nm and16nm results. We will continue
to drive leading quality, newproduct introduction (NPI), &advanced reliability success.

Redefining the FPGA
landscape with stacked-siliconinterconnect technology which
exceeds the capacity confinesof Moore’s Law, and advances
test and manufacturingmethodologies for knowngood die selection.

Pushing ease of use to newlevels through proven design
methodologies, predictable QoR,
and significantly improved user
experiences.

With knowledge sharing thatdrives quality for our suppliers,
partners, and customers, driving
success throughout the All
Programmable ecosystem.

Creating simplicity through
SoC solutions and elevating
the ability to achieve higher
quality at the system level.

Extending Xilinx momentum witha new generation of solutions
defined through intimacy withour customers and brought tomarket through close engineering
partnerships with industry leaders.

These are exciting times. As systems and networks evolve to be become more software defined andvirtualized, video is everywhere, more machines are connected and augmented with ‘vision’, wireless moves
to 5G, and ever more processing is performed in the cloud, Xilinx continues to deliver new generations of All
Programmable devices and design environments with Absolute Quality.
With confidence and pride,

MOSHE GAVRIELOV
President & CEOFirst to go “all in” at
28nm and 20nm

First to production
on 28nm with zeroproduction errata

VINCENT TONG
SVP, Global Operations & Quality“Zero-defect”
mindset extended
beyond silicon to
design tools and IP

First to deliver a rearchitected, SoC-strength
development environment
and tool suite3

Quality
Building Trust
Quality Proof Points• RMAs reduced by >68% since 2008
• 46% of customer RMA issues resolved in
the field• Customer scorecard has remained above
9.0 since Q1 2009
• No major excursions or recall for the past
eight years• All Xilinx products meeting <10PPM

Full-Circle Support and Feedback
Regardless of the amount of in-house testing, analysis, and issue
resolution, the most credible and meaningful measures of quality
are those that come back from customers. From top to bottom, Xilinx
executives, managers, and engineers diligently focus on customers
and continually refine Xilinx products, programs, training, andsupport to deliver optimal results. Key customer-centric feedback
includes:• Validated customer returns (RMAs), which are tracked against
products shipped and which show an overall rate of <10PPM (seeFigure 1).
• Since 2008, closed-loop customer root cause shows that less than
19% of RMA cases stem from Xilinx issues (see Figure 2).

Huawei - Gold Core Partner Award
Olympus - Supplier of the Year Award
Agilent - Best Supplier Award
Cisco - Security Award
Fujitsu - Distinguished Partner Award
Anritsu - Supplier Excellence AwardZTE - Excellent Partner Award
National Instruments - Quality Award• Customer feedback (NPS) based on RMA case data shows
exceptionally high customer satisfaction.
Frequent and extensive knowledge sharing also helps optimize
Xilinx customer successes. Discussions and information sharing,which often include partners and suppliers, provide a high level oftransparency through:• Unique device DNA for more timely device analysis.
• Design checklists and development methodology.
• Design margins, with validated results from design evaluation
samples.
• Design issue mitigations, offered at early stages and prior to
production release for early adopters.
Spartan FPGA
Product

Technology Node

PPM

Spartan-II/IIE

0.22µm/0.18µm/0.15µm

0.0Spartan-3

90nm

0.0

Spartan-3E

90nm

0.0

Spartan-3A/3AN

90nm

0.0

Spartan-6

45nm

0.1

PPM

Virtex FPGA

4

Product

Technology Node

Virtex /-E

0.25µm/0.18µm

0.0Virtex-II/llP

0.15µm/0.13µm

0.0Virtex-4

90nm

0.0

Virtex-5

65nm

0.59

Virtex-6

40nm

9.31

7 series

28nm

2.35

Figure 1: Based on
customer return data,
CY2014 product PPM
demonstrated the Xilinx
zero-defect mindset.

TRUST IS EARNED over time, by performing consistently and delivering results that exceed expectations.
Xilinx enjoys strong working relationships with customers because of an unwavering commitment to quality.
The evidence of this commitment— the true testimonial to Xilinx quality—is the real-world data that focuses on
end-user experiences and design results.

...
Unleashing Customer Confidence
No. CASES“With 7 series, UltraScale andVivado Design Suite, our quality wasachieved on the basis of work thatbegan with a clear strategy and achain of decisions made years ago.
The development teams all embracecomplete ownership of their results
and this ensures that quality
emanates from the very source of
the innovation. With UltraScale, we
maintain our position of being ageneration ahead and soon shipping
UltraScale+ MPSoC with 16nm
node.”

2008

2009

2010

2011

2012

NON-XILINX

2014

2013

YEAR

NO DEFECT FOUND

XILINX

Figure 2: Over the last four years, RMAs have been reduced by >60% versus 2008 levels as a result of product quality, customer
support, and direct engagements for issue resolution.

WAI KOOI WONG
Vice President, Corporate Quality

XILINX, INC.

The Bottom Line
Xilinx’s commitment to excellence is exhibited through our ongoing execution with quality, long term reliability,
functional safety, and security always at the forefront. Xilinx and customers—with support from technology suppliers
and partners—make up a tightly linked community. The entire ecosystem must succeed to drive up the quality of theend solutions enabled by Xilinx innovations. Periodic quality scorecards provided by customers are therefore the truemeasure of Xilinx quality (see Figure 3).
Additional Xilinx customer-facing quality hallmarks include:

AQR Page 13 figure 3 for Score card

• Closed-loop focus on root cause.

10• Transparent change managementand data reporting including horizon
reports, reliability, SEU, RMA, andautomatic notifications.
• Device DNA (eFuse) and 2D bar
coding to track device/die history.
• Executive commitment to improving
customer satisfaction.
• Robust control processes andcontinuous improvements are part of
Xilinx’s philosophy.

Customer Scorecards• On-line RMA portal for real-time
customer support.

9

8

2008

2009

2010

2011

2012

2013

2014

Figure 3: Top management focus on customer feedback and flawless results c ontinue to drive positive© Copyright2012 Xilinx
XILINXCONFIDENTIAL
customer results.

Page 13.

5

28/20nm
Execution

Execution Proof Points:
Zero Production Errata• 100% of goals met at each release
milestone, with very aggressive
specifications• Stable process, with excellent yield, quality
and reliability, and zero production errata• First silicon ahead of schedule, comparedwith prior generation• Scalable optimized architecture for rapid
rollouts• 50X more samples for verification andcharacterization compared with previous
generation

Leading Nodes and SoC Wins
Success starts with strong foundational disciplines. At each node,
this meant starting by matching the available processes with thetechnologies Xilinx needed to deliver. At 28nm, Xilinx chose theHigh-Performance Low-power (HPL) and SoC process at TSMC, andthereby avoided many of the pitfalls other companies experienced at
this node. More significantly, this continues to allow Xilinx to deliverindustry-leading performance per watt (see Figure 1). The tightly
controlled processes, earlier customer engagements, and real-world
design rules yield:• A proven supplier engagement model, including technicalengineering and executive-level involvement.
• Process and Performance Learning Vehicles (PPLVs), which
resolved many complex issues to accelerate NPI and increase
design confidence (see Figure 2).
• Functional margin, moving from 40nm tri-Tox to 20nm dual-Tox.
• A high-k/metal gate process with much lower gate current,
resulting in fewer issues and faster time to market.

Actual Hardware
Benchmark Results

UltraScale Kintex-7 FPGA
Estimator Results• System level characterization for morecustomer based evaluations• Lifetime goals met: 10 years @ 100°C Tj, or
20 years @ 85°C Tj• Defect densities leading those ofprior nodes

Figure 1: The Xilinx Power Estimator tool was tuned continuously using targeted simulation based on test vehicle
results and early architectural learning, giving designers highly accurate results.

6

NUMBERS TELL THE STORY. The results are in and have ended all debate:
Xilinx is a generation ahead at 28nm/20nm. The company embraced a hallmark zero-defect mentality,
going “all in” on the HPL/SoC process and one foundry partner. The Xilinx focus on quality andreliability—which spans design, process development, assembly, and test—was guided by fifthgeneration new product introduction (NPI) processes and the most stringent release criteria to date.

...

Driving Success Generation After Generation

Unleashing Silicon Development

Xilinx engineers have proven that they verify, characterize, test, and qualify
devices better and faster than anyone else in the industry. All while achieving
absolute quality. For five generations, Xilinx’s advanced NPI methodology andmilestone criteria (see Figure 2) have been tightened to keep ahead of increasing
device complexity. At 20nm, the advancements improved data collection,verification, and characterization with:“Our 7 series, UltraScale and Vivado
Design Suite deliver the leadershipvalue our customers have cometo expect from us. Our strategy ofdesigning our All Programmableproducts with TSMC’s leading
technology, together with ourscalable optimized architecture,and leveraging our industry-leading
SOC & stacked silicon interconnect
technologies have continued to put
Xilinx a full generation ahead of thecompetition. We have continued toco-optimize 7 series & UltraScale
product with the Vivado Design
Suite to deliver a high-quality,compelling user experience.
Delivering these multiple
breakthroughs is a testament to
our talented employees and theircommitment to creating high-value,high-quality innovative products forour customers.”• Highly automated design flows and timing analysis.
• Verification and characterization processes for earlier identification of issues
and earlier corner material (12 weeks sooner than previous generations).
• Test coverage exceeding 99.7%, with earlier data collection.

Number of Test Patterns• “Big data” analysis driving deeper insights into testing and sharing across teams.

First Silicon

Production Device

P0

P1
ES1

P2
ES2

VICTOR PENG
EVP and GM, Products
XILINX, INC.

P3
Production

Verification and Characterization Time

Figure 2: From first silicon to production material ship, Xilinx has redefined its verification andcharacterization process to drive early discovery to release with zero errata.

Robust Technology Reliability
Xilinx reliability methodologies continued to overcome the shrinking reliability margins at the 16nm process node. Byleveraging early learning and in-depth tools expertise, Xilinx engineers shortened development processes from months
AQRatPage
5 Qualification
figure3
to days, and accommodated the extra iterations required
28nm
and 20nm. AsDataa result,
Xilinx devices are meeting thestringent requirements of the most reliability-sensitive applications in industrial, automotive, aerospace, and defense
industries (see Figure 3):
16nm FF+• Enhanced Design-for-Reliability (DFR) guidelines
have proven a FIT rate less than 12 at
production.
• Improved outlier elimination and new DFR
methodology are combating the “shrinking
bathtub” curve at 20nm.
• Xilinx engineering and quality assurance
programs have yielded proven, predictable,
and very-low failure rates over extended device
lifetimes. The 20nm devices were released to
production with power and defect density (DD)beating previous estimations.

Item

Device
COREN
COREP

TDDB

Hot Carrier
Injection

BTI

LT [yr]
@125C
32
48

20nm SoC

28nm HPL[yr]
LT [yr]AQRLTPage
5 Qualification
Data figure3
Vmax[V]
Vmax [V]Vmax [V]

@125C

1.08
1.09

@125C

15.5
1450

1.06
1.18

150
4.02E+03

1.17
1.25

1.8V ION

1500

2.39

32

2.04

2.05E+04
2.38
16nm FF+

1.8V IOP

9.00E+06

2.69

1.20E+07

2.71

7.14E+05

COREN

375

1.16
1.16

COREP

84

1.8V ION
1.8V IOP
COREN
COREP

41
96
1.20E+07
2050

1.8V IOP

6270

Item

SM

2120
20

2.07
18
2.14
58
1.45
53
Gate Oxide TDDB
1.23
115
2.38

135

Test structure

1.19

6.60E+02[yrs]@125C
1.23

1.07
1.25 3 lots
Kelvin_Via
Via_Chain 2.20E+03
Zero Failures from
2.02

MG-M0
2.07

1.10

PO-MD1/2
1.11

3.75E+01
2.06
5.94E+03 300yr2.32
1.26E+02
1.2
2.06E+02 >1001.18

20nm SoC

28nm HPL

Result / LT

Result / LT[yrs]@125C[yrs]@125C

Zero Failures from 3 lots

Zero Failures from 3 lots

N/A

N/A

131

N/A

3550

3400

905

1000

Jmax > 2x

2x

2x

M0

Jmax > 4x

4x

N/A

M1 & 1xM

Jmax >> 2x

2x

2.5x

MxMx
2.13
VxMx
High-R Resistor

Electromigration© Copyright2012 Xilinx
XILINXCONFIDENTIAL

2.55

Result / LT

7.00E+03

2.33

300~600yr.

Figure 3: From 28nm to 16nm, wafer-level
reliability exceeds transistor and
XILINX CONFIDENTIAL
interconnect market requirements to deliver industry-leading device FIT.
© Copyright 2012 Xilinx
.

7

3D

PACKAGING
Innovation
Innovation Proof Points

More and More…than Moore• The microbumps (~200,000) and C4
bumps (~20,000) passed all criteria forreliability, older inelastic strain, andfatigue

More on a chip and more die integrated on a single device—for moreadvanced systems. The world’s first monolithic 3D FPGA (see Figure1), the Xilinx Virtex-7 FPGA V2000T and now the Virtex UltraScale
FPGA VU440, represent a breakthrough in all of these dimensions that
required very stringent qualification and test. The industry’s second
generation 3D IC required further advancements, including:• Virtex® UltraScale™ FPGA VU440 has~600,000 microbumps and C4 bumps(>20,000) with 19 billion working
transistors• UltraScale FPGA VU440 has passed all
qualification requirements including
power cycling at 20nm
• Proven known good die program to drive
manufacturing capabilities• Proven 2nd generation 3D packaging
solutionStressConditions

HTOL

T=125ºC, Vccmax, Dynamic

Criteria• Optimization of package substrate material and interposer
resistivity to achieve 33Gb/s system channel characteristics.
• Design and timing verification of high-performance inter-dieinterconnects.
• 3D thermal-mechanical modeling and analysis for package
reliability, addressing package co-planarity issues and stresses
introduced by the interposer.
To learn more about these Xilinx advancements, please visit
www.xilinx.com/quality.

3x Reflow
Ramp up 30ºC to 130ºC in 3 minutes
PC• Low loss organic packaging for robust board level reliability &optimal signal integrity.

Hot Dwell 6 minutes at 127ºC - 130ºC
Ramp down: 130ºC to 30ºC in 3 minutes
Cold Dwell: 6 minutes at 27ºC - 30ºC

THB

MSL4; Ta= 85ºC, RH= 85%,
Alternative BiasTH

MSL4; Ta= 85ºC, RH= 85%

HTS

3x Reflow, Ta= 150ºC

TC-B

MSL4, -55ºC / +125ºC

Pass

Microbumps• µBump Quality• µBump Structure• µBump Yield

CoWoS Assembly• µBump Joint Reliability• µJoint Yield• Underfill Process

Silicon Interposer• TSV Reliability• Backside Process
Flow & Yield• Handling
28nm FPGA Die 28nm FPGA Die 28nm FPGA Die 28nm FPGA Die

Si Interposer
Through
Silicon Vias

Package Substrate

C4 Bumps

BGA Balls

Figure 1: SSIT cross-section showing key quality considerations o n a typical qualified SSI device using
TSMC’s CoWoS process.

8

STACKING SILICON PUSHES THE LIMITS, and allows Xilinx to set new standards for capacity and performance. Xilinxinnovated Stacked Silicon Interconnect technology has driven devices beyond the confines of Moore’s Law, both formonolithic and heterogeneous devices. To mitigate the risks associated with stacked silicon and meet quality goals forbreakthrough 33Gb/s devices, Xilinx used early learning from lead-free flip-chip test vehicles (ranging from 90nm to20nm) and leading-edge modeling and manufacturing methodologies that address the increased complexity.

...

More Integration
Stacked silicon offers the inherent advantage of selecting “like” products interms of power consumption and speed, which means more predictable results
than monolithic silicon. A comparison of simulated and actual eye diagrams
demonstrates this exceptional quality (see Figures 2 and 3). The methodologies
behind the industry’s first 28nm (28Gb/s) 3D IC heterogeneous devices andnow extended at 20nm (33Gb/s) are fully integrated to meet performance andspecifications. Selection starts with solid test and manufacturing methodologies at
the assembly site, and includes:

Unleashing Stacked Silicon• Ensuring multiple-die performance by adding system timing checks tocharacterization process.

“To push beyond conventional
thinking and break through Moore’s
Law in delivering our 3D IC solution,
we continue to deliver a superb
level of engineering excellence.
In doing so, we opened up a newfrontier for combining technology
building blocks, from cost-effective
component die. This could not havebeen accomplished without a laser
focus on prevention and flawlessengineering execution from Xilinx
and our supply partners.”• DFM rules that provide performance advantages.

LIAM MADDEN• Enabling power die optimization during selection, through fully integrated
die testing at wafer sort, now standard across the 7 series, UltraScale, andUltraScale+™.

XILINX, INC.

CVP, FPGA Development and Silicon Technology• FPGA self-diagnostic capabilities for higher test coverage confidence.
• Reliability prediction, using a custom hierarchical, end-to-end tool that draws on
a Xilinx design database.
• Expanded wafer qualification using three additional elements for assembly
testing: electrical, thermal, and mechanical.

GTY UltraScale Jitter Tolerance at 32Gb/s
T=100C, VCC min, PRBS31, Noise Case, PPM=+/-200

1000

100

SJ (UI)

10

1

0.1

0.01
1.00E+03

1.00E+05

1.00E+07

1.00E+09

Modulation Frequency (Hz)Mask_VSR28G (IEEE OIF Std.)-200PPM+200PPM
Equipment Limitation

Figure 2: Heterogeneous SSIT
packaging makes it possible
to exceed IEEE standards forhigh-speed channel quality
in the Xilinx GTZ SerDes at
28Gb/s.
Figure 3: Collaborating with TSMC and using test vehicles to learn from real-world processdata allowed development modeling to achieve 28Gb/s design milestones as shown in thesimulated (upper) and actual (lower) eye diagrams.

9

SoC

Integration• Carried out under conditions thatalign with the most stringent customer
requirements• Block characterization improvements for
GTX and for BRAM:• New Verilog flow

Units Shipped(Millions)

SoC Characterization andVerification• Customization of build-in self-test(BIST) march sequence• Tests run using memory test boards,
varying attributes, and test conditions
that exceed specifications by 10%• Additional corner-case and volume
system testing with critical IPs• 3X increase in the number of targetedreference designs* (TRDs) compared withprevious generation• 3X increase for exercising non-processing
areas (connectivity, DSP, AMS, etc.)* The Vivado tools are used for design testing, whichmakes this testing part of the critical release criteria
for the tools themselves.

10

1HCY13

2HCY13

1HCY14

2HCY14

1HCY15Figure 1: Leveraging the FPGA learning from o ur scalable optimized architecture, Xilinx was able to de-risk the
Zynq SoC evaluation and to launch in record time.

Simplified Solutions
The Zynq® SoC and MPSoC devices replace chip-to-chip latencies
with high-speed FPGA-processor connections, giving designers
the latest Xilinx advancements such as 7 series and UltraScale+
SerDes to support maximum throughput and capacity for SoC
designs. Engineers and system architects can leverage SoC
capabilities, implement accelerators in the device’s processing
system or its programmable logic, and bring more complex designs
to market with confidence in the quality of the total solution.
Besides leveraging learning and enhancing design tools, Xilinx has
introduced new mechanisms for integrating system-level verificationof target specifications for the processor subsystem, logic, and IP(see Figure 1). The scalable optimized architecture and common
blocks across the 7 series FPGAs and SoCs contributed to absolute
quality and accelerated the rollout of devices. After verification of
the first Kintex®-7 325T based device, many 28nm devices wentstraight from first tape out to production.

IT TAKES MORE THAN LOGIC. Xilinx has redefined integration by wrapping industry-leading logic and I/O fabricaround an ARM® processor subsystem. This industry-first leveraged learning that began more than 10 years ago
with the Virtex-II Pro and continued through Virtex-4 and Virtex-5 PowerPC designs. Xilinx proprietary approaches
for testing and characterizing FPGA and processor interactions now yield an advanced, robust SoC that simplifies
design and unleashes future generations of All Programmable systems.

...

System-Level Quality

Unleashing Customer Acceleration

The role of FPGAs has evolved from “glue logic” and rapid prototyping to today
serving as the heart of advanced systems. Device testing has similarly evolved to
track more advanced applications, with system-level testing being a significant
component in the Xilinx quality equation. Zynq SoC quality, while benefitingfrom many proven practices, called for further refinements at every stage ofdevelopment and was driven by a balanced focus on silicon verification, systemlevel performance, and extensive, holistic testing:“As design complexity andintegration increase, ourcustomers demand top quality
system solutions to accelerate
their design capabilities. The Zynq
platform provides a fully verified
prebuilt processing systemcompletely validated along with
its associated software and tools.
With this platform, Xilinx delivers
the highest level of performanceand quality, which our customers
expect.”• Prior to silicon, extensive emulation leveraged the EDK platform and booted
operating systems such as Linux.
• Rearchitected verification and characterization approaches solidified the onchip FPGA fabric.

VAMSI BOPPANA
Vice President, Processor Development

XILINX, INC.

• Randomized continuous testing of the processor subsystem exercised the SoCunique feature set:
• Guidelines stem from the Xilinx embedded software initiative, aimed atprocessor-IP testing.
• Verification IP for all Xilinx interfaces (e.g. DDR, USB, Ethernet MAC, etc.).
• Constrained-random and random test generation.
• Compliance testing for interface standards.
• Results: catching more than just Xilinx device issues (external bugs inother components such as PCI Express® chipsets).
• Processor-FPGA interactions were tested,
during which the processor subsystem isthe master.
• Additional SoC-specific characterizationand verification were performed, such asOpen Verification Methodologies (OVM).
• Stringent coverage and metric-driven
verification performed on the SoC(see Figure 2).
• Expanded wafer qualification using three
additional elements for assembly testing:electrical, thermal, and mechanical.

PS Performance Characteristics
SYMBOL

CLOCK
RATIO

DESCRIPTION

Speed Grade
Specifications

Measured
-3

-2

-1

-3

-2

-1

Units

Guaranteed
By

FCPU_6X4X_621_MAX

Maximum CPU clock
frequency

891

784

667

800

733

667

MHz

Test

FCPU_3X2X_621_MAX

Maximum CPU_3X
clock frequency

446

392

333

400

367

333

MHz

Test

FCPU_2X_621_MAX

Maximum CPU_2X
clock frequency

297

261

222

267

244

222

MHz

Test

FCPU_1X_621_MAX

Maximum CPU_1X
clock frequency

149

131

111

133

122

111

MHz

Test

FCPU_6X4X_421_MAX

Maximum CPU clock
frequency

776

677

547

710

600

533

MHz

Char

6:2:1

Maximum CPU_3X
clock frequency

388

339

274

355

300

267

MHz

Char

FCPU_2X_421_MAX

Maximum CPU_2X
clock frequency

388

339

274

355

300

267

MHz

Char

FCPU_1X_421_MAX

Maximum CPU_1X
clock frequency

194

169

137

178

150

133

MHz

Char

FCPU_3X2X_421_MAX
4:2:1

Figure 2. Extended verification, characterization, and system-level verification
fully exercise the processor subsystem as well as FPGA-processor interactions
to ensure all Xilinx specifications are met.

11

Design Tools
Productivity

Ever Expanding Testing BaseBringing Design Vision to Life

Vivado Quality Initiatives

The Vivado Design Suite represents a major advancement in ease ofuse for All Programmable developers. Vivado accelerates integration,
implementation, verification and debug for 28nm, 20nm and 16nm
(see Figure 1). Vivado has been designed to handle exponential
growth in device densities reaching 10s of millions of logic cells.

• TL9000 audited standardized processes• High quality and continuous nightly
builds• Extensive daily regression suites withover 220,000 nightly tests• Weekly regression testing of over 50K
interactive, batch, formal checking,directive random and hardware testing• Robust release checklist and criteria• Functional safety certified in 2016

Vivado IP Quality Initiatives•

XVI - Xilinx Verification Initiative(Functional Verification) – UVM based
methodology• Viper - Next generation verification acrossall Vivado IP - 80,000+ IP test jobs per day• System Level Validation (SLV) - Over 120
different IP tested, over 1500+ systems
tested daily

Ecosystem Participation in
Release Testing• Early partner/ecosystem participation in
all releases• Real-time debugging, using partner IP, for
testing and improved quality• Extended requirements and tierdefinitions for ecosystem partners toinclude Vivado training and proficiency• Results: Hundreds of products alreadyon 7 series and UltraScale; more than 50
partner IP cores supporting AXI, several
vendors providing evaluation cores frominside the Vivado Design Suite

12

Figure 1: The Xilinx design suite was rearchitected to enhance the customer experience and provide
superior quality of results. Customer summary data reflects success based on these goals, and will drive
further advancement of Vivado.

• The UltraFast Design Methodology: Delivers the firstcomprehensive set of design methodologies in the programmableindustry. Xilinx collected the best practices of expert users anddistilled them into an authoritative set of methodology guidelines.
• Production proven: Used on 90% of all 7 series designs and 100%of UltraScale/UltraScale+.
• The Tcl API: Designers have the flexibility of working in a scripted
Tcl environment, an interactive Tcl shell, or a graphical project tool.
Tcl also allows much more in-depth testing (better coverage) ofVivado.
• TcL App Store: Xilinx, Alliance partner and customer Tcl Apps tostreamline development.

TIME IS MONEY. Even breakthrough innovations such as Xilinx All Programmable devices require the right tools to achieve
maximum value and deliver the highest level of quality. The Vivado Design Suite delivers a SoC-strength, IP-centric and systemcentric, next generation development environment that has been built from the ground up to address the productivity bottlenecks
in system-level integration and implementation. The Vivado Design Suite is a generation ahead in overall productivity, ease-ofuse, and system level integration capabilities. Vivado tools provide 4X faster implementation, 20% better design density and up to
3-speed grade performance advantage all while improving designer productivity with key features such as IP Integrator to rapidly
assemble Xilinx, customer and 3rd party plug-and-play IP and High Level Synthesis for C/C++ based IP generation.

...

Predictable User Experiences and Design Methodology
Unleashing FPGA Possibilities

The Xilinx zero-defect mindset was applied to the Vivado Design Suite fromthe beginning and feedback from customer scoring indicates that the qualityof the Vivado tools has consequently exceeded expectations (see Figure 2).
Stringent testing and release criteria has provided continuous improvement to
the tools and IP. In addition, the UltraFast Design Methodology for the Vivado
Design Suite enables project managers and engineers to accelerate productivity
and quickly tune their sources, constraints and settings to accurately predictschedules. Now in its second edition, the guide covers all the aspects of:Board and
Device Planning“As design complexity increases,in step with quantum increases
in capacity and performanceof integrated solutions, theneed for a revolutionary design
environment has becomecompelling. Our strategy inbuilding a completely new
platform of design tools
architected around a shared,
scalable data model haveshowed successful results.
Vivado has continued to provide
the highest-quality results andproductivity for all customers.”

Design Creation
and IP Integration

SALIL RAJE
VP, Software and IP Products Development

XILINX, INC.

Implementation
and Design Closure

Configuration andHardware Debug

Q Page 11 figure 2 Software Update

The Vivado Design Suite automates part of the UltraFast Design Methodology
by providing linting rules and templates for optimal HDL coding style, and XDCtiming and physical constraints.

10

Vivado Designs

97% Bug / Completion

Customer Designs

8

5
4
3
2
1
0

Q1
FQ3

Q2
FQ4

Q3

Q4

FQ1

FQ2

Customer Design Complete

Q5

FQ3

Q6

FQ4

Q7

FQ1

Q8

FQ2

% Bug / Completion

Figure 2: Earlier and more stringent testing and verification mitigate the risks that stem from increasing complexity. Testing withhigher-level customer designs increased the prerelease discovery and resolution of issues. With more issues identified during
development, the impact on customers is minimized and design cycles are accelerated for higher-quality products and an
improved user experience.
© Copyright2012 Xilinx
XILINXCONFIDENTIAL
.

13

16nm
Leadership

Building on 20nm Innovations
Proof Points• Leveraging 28nm learnings and a scalable,
optimized architecture• Second-generation 3D IC/PS architecture
leveraging proven technology• Second-generation high-k/MG reduced
process variation (i.e., gate-last, high-k-last)• NMOS elevated source/drain, PMOS eSiGe
to boost performance• Intact design, verification, and integration
teams to carry forward HPL expertise• UltraScale architecture for simple migration
between planar and FinFET nodes

Staying a Generation Ahead at 16nm
Xilinx began developing the 16nm UltraScale+ family in 2012. Before
shipping the first 20nm UltraScale device, our proven approach for
16nm was well under way. Since then, the lessons learned at 20nm
have helped Xilinx refine 16nm process and product qualification
methodologies, including extended temperature testing and arenewed focus on wear-out data and reliability estimations. In
addition, Xilinx is introducing major testing changes stemmingfrom early DFT specifications. The new opportunities for Xilinx
leadership and innovation at 16nm will include FinFET transistors,
double-patterning lithography, gate dielectric scaling, increasing I/O
and packaging complexity, scaling power, and overall changes totestability and reliability.

A World-Class TeamIn collaboration with TSMC and our supply chain partners, Xilinx
is driving solutions to all of the 16nm challenges. This extended
ecosystem will continue to play an expanding role in the introductionof the next-generation devices. In addition, our “Voice of the
Customer” initiative continues to grow as IP, design tools, and silicon
become more integrated solutions. Supporting the world-class Xilinx
extended team is a solid foundation of engineering achievements
based on learning from previous generations.

On Track
Xilinx, together with TSMC, is on track to deliver 16nm technology
products. Built on a proven foundation, including third-generation
SSIT and embedded ARM processor architecture, Xilinx is delivering asignificant boost in performance/watt from TSMC’s 16FF+ FinFET 3D
transistors. Optimized at the system level, UltraScale+ delivers value
far beyond a traditional process node migration – providing 2–5X
greater system level performance/watt over 28nm devices, far more
systems integration and intelligence, and the highest level of security
and safety.
In collaboration with TSMC, the journey continues with thedevelopment of the 7nm process and 3D IC technology for its next
generation of All Programmable FPGAs, MPSoCs, and 3D ICs. The
technology represents the fourth consecutive generation where
the two companies have worked together on advanced process
and CoWoS 3D stacking technology, and will become TSMC’s fourth
generation of FinFET technology. The collaboration will provide Xilinx
a multi-node scaling advantage and build on its outstanding product,
execution, and market success at 28nm, 20nm, and 16nm nodes.

14

CHALLENGES GIVE RISE TO INNOVATION. With the release of each generation of devices, Xilinx introduces technology advancesthat overcome existing limitations, allowing engineers to build more value into electronic systems. First to market with
UltraScale and 16nm FinFET UltraScale+ All Programmable FPGAs, 3D ICs and SoCs, Xilinx has built on the momentum andmarket leadership established at 28nm and has delivered for three consecutive generations All Programmable device innovationahead of the competition — a 3-Peat.

15

Corporate Headquarters
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
USA
Tel: 408-559-7778
www.xilinx.com
EuropeXilinx Europe
Bianconi Avenue
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Saggart, County Dublin
IrelandTel: +353-1-464-0311
www.xilinx.com
Japan
Xilinx K.K.
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1-2-2 Osaki, Shinagawa-ku
Tokyo 141-0032 Japan
Tel: +81-3-6744-7777
japan.xilinx.com
Asia Pacific Pte. Ltd.
Xilinx, Asia Pacific
5 Changi Business Park
Singapore 486040
Tel: +65-6407-3000
www.xilinx.com
India
Xilinx India Technology Services Pvt. Ltd.
Block A, B & C, 8th, 12th and 13th Floors,
Meenakshi Tech Park, Survey No. 39,
Gachibowli (V), Serilingampally (M),
Hyderabad – 500 084 India
Tel: +91-40-6721-4747
www.xilinx.com

For more information about Xilinx and its All Programmable solutions visit: www.xilinx.com© Copyright 2015 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the UnitedStates and other countries. All other trademarks are the property of their respective owners.
Printed in the U.S.A. WW102015