ARTICLE IN PRESS

Nuclear Instruments and Methods in Physics Research A 582 (2007) 861–865
www.elsevier.com/locate/nimaR&D of a pixel sensor based on 0:15 mm fully depleted SOI technology
Toru Tsuboyamaa,,1, Yasuo Araia, Koichi Fukudab, Kazuhiko Harac, Hirokazu Hayashib,
Masashi Hazumia, Jiro Idab, Hirokazu Ikedad, Yoichi Ikegamia, Hirokazu Ishinoe,
Takeo Kawasakif, Takashi Kohrikia, Hirotaka Komatsubarab, Elena Marting,
Hideki Miyakeh, Ai Mochizukic, Morifumi Ohnob, Yuuji Saegusae, Hiro Tajimai,
Osamu Tajimaa, Tomiaki Takahashie, Susumu Teradaa, Yoshinobu Unnoa,Yutaka Ushirodaa, Gary VarnergaKEK, High Energy Accelerator Research Organization, Japanb
OKI Electric Industry Co. Ltd., Japanc
University of Tsukuba, Japan
dJAXA, Japan Aerospace Exploration Agency, Japane
Tokyo Institute of Technology, Japan
fNiigata University, Japang
University of Hawaii, USAhOsaka University, Japani
Stanford Linear Accelerator Center, USA
Available online 31 July 2007

Abstract
Development of a monolithic pixel detector based on SOI (silicon on insulator) technology was started at KEK in 2005. The substrateof the SOI wafer is used as a radiation sensor. At end of 2005, we submitted several test-structure group (TEG) chips for the 150 nm, fully
depleted CMOS process. The TEG designs and preliminary results are presented.
r 2007 Elsevier B.V. All rights reserved.
PACS: 29.40.n; 29.40.Gx; 29.40.Wk
Keywords: Monolithic pixel sensor; SOI CMOS technology

1. Introduction
SOI (silicon on insulator) is a process that fabricates
CMOS circuitry atop a silicon-oxide layer (buried oxide,BOX) over a silicon wafer, as shown in Fig. 1. Since eachtransistor is isolated from the substrate and from eachother, the circuit has smaller parasitic capacitance than anormal (bulk) CMOS LSI device, enabling faster andlower-power operation. For the same reason, such an SOICorresponding author.

E-mail address: toru.tsuboyama@kek.jp (T. Tsuboyama).
This research was partially supported by the Ministry of Education,
Science, Sports and Culture, Grant-in-Aid for Scientiﬁc Research,18204027, 2006.
10168-9002/$ - see front matter r 2007 Elsevier B.V. All rights reserved.
doi:10.1016/j.nima.2007.07.111

device shows much smaller susceptibility to single-event
phenomena in high-energy physics or space applications. Ifwe adopt a high-resistivity silicon wafer as the substrate
and the signal induced in the substrate can be collected andprocessed by the CMOS circuit, SOI CMOS can be used asa radiation sensor. Pioneering work on this concept has
been done by the SUCIMA [1] project, which successfullyrecorded minimum ionizing particle signals with such a
device in a test beam. However, the process used is notcompatible with sub-micron CMOS technology. The KEKDetector Technology Project [2] started its activity in 2005
and a monolithic-pixel detector subgroup, SOIPIX, haschosen the SOI technology of Oki Electric Co. Ltd., 150 nm
fully depleted SOI CMOS process [3]. The merit ofcollaborating with a commercial LSI foundry is that theARTICLE IN PRESS
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T. Tsuboyama et al. / Nuclear Instruments and Methods in Physics Research A 582 (2007) 861–865

MOSFETs

Contact plugwith SiO2 layer. The contact to the substrate is made laterby the via holes and tungsten plugs.
3. Evaluation of test element group chips

BOX (Buried oxide)p+ implantn– bulk

Back side metalization
Fig. 1. Schematic view of an SOI CMOS device. p-type and n-type
MOSFETs are fabricated on a buried oxide layer (BOX). The pþ implantand contact plug is introduced in order to collect charge induced in thesubstrate.

Several test element group (TEG) designs were submitted to OKI in 2005. The designs and the results ofsubsequent evaluation are described in the following
sections.
3.1. Strip-detector TEG
In order to measure the basic characteristics of the PIN
diode in the SOI substrate, a strip-detector TEG wasfabricated in a 2:5  2:5 mm2 chip. The chip is divided into
eight regions. In each region, eight 460 mm long p-typea0.4(a) Leak current/striplb (nA)

0.3

0.2

0.1

Fig. 2. Cross-section of the pþ implant and the signal contact. A typical
MOSFET is also shown. Borders of BOX and SOI are emphasized withdotted lines.

00204060

Vb (V)

up-to-date technologies can be utilized in the device
designs.

b0.8

2. OKI FD SOI process
0.6lb (nA)The SOI wafers are fabricated by SOITEC [4] by using
their Smart-Cut technology [5]. The substrate is made from
650 mm thick, n-type FZ silicon. The resistivity of thesubstrate after silicon processing is measured to be about
700 O cm. The back side is thinned to 350 mm and sputteredwith 200 nm thick aluminum. The thickness of the BOXlayer is 200 nm. The CMOS transistor is made with 40-nm
thick Cz crystal with a resistivity of 30 O cm. The thicknessof the gate oxide is 2.5 nm. Five metal layers can be used inorder to accommodate complex CMOS circuits. Because ofthe thin silicon layer, the FETs can be fully depleted at lowgate voltage, which permits low-power operation. The
nominal power supply voltage is 1 V. Fig. 2 is a SEM
picture of the cross-section of the substrate contact. Thearea shown as ‘BOX window’ is etched out and ions are
implanted through to the substrate. Then the area is ﬁlled(b) Detector capcitance /strip

0.4

0.2

0020

4060

Vb (V)
Fig. 3. The (a) I–V and (b) C–V characteristics of the strip-detector TEG.
In (b) the measured data are plotted with white boxes. The solid line shows
the result of ﬁt.

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3.2. Pixel-type structure
A 32  32 matrix of 20  20 mm pixels is integrated
on a 2:5  2:5 mm2 chip in order to examine the potentialof the SOI as a radiation sensor [8]. Fig. 5(a) shows themagniﬁed view of a pixel. Signal induced in the substrate ispicked up with four octagonal shape 4  4 mm2 p-typeimplants. The aperture at the center is used for lightillumination. Four implants are connected in parallel andread out with a front-end circuit as shown in Fig. 5(b).
Charge induced in the p–n junction (D) is observed throughsource-follower by M2. M1 works as a protection diodefor the gate of M2. Charge accumulated due to leakage
current at the input is periodically reset by M0. M4 and C swork as a track and hold circuit while M3 is used todischarge C s . The analog output is multiplexed by M5 andM6 and recorded using an analog-to-digital converter.
The breakdown voltage of the p–n junction is foundto be about 100 V. However, because of the back-gate
effects, explained later, the evaluation of the pixel TEG is10(a) Relative charge collection
864200204060Vb (V)4030ADC count

implants are made in 50 mm pitch. There are regions withstrip widths of 10, 20 and 40 mm. The I–V and C–Vmeasurement is done for the 10 mm strip width (Figs. 3(a)and (b)). Four strips (every other strip) are connected
parallel in the measurement. Value shown here is normalized for one strip. The breakdown voltage is found to be60 V which is less than the expected full depletion voltage(700 V). The observation with an infrared camera
revealed the discharge takes place at the square corner ofthe strip implants. The solid line in Figs. 3(b) is ﬁtted with
C ¼ C 0 þ S=W , where C 0 , , S and W represent offset
capacitance, dielectric constant of silicon, area of strip
coverage and depletion depth, respectively. If the resistivityof silicon is ﬁxed to 700 O cm, the best ﬁt is obtained withS ¼ 2  50  460 mm2 . This suggests the ﬂoating strips
between measured strips fully contribute the C–V measurement through the inter-strip capacitance. The chip wasthen integrated into a readout system using an APV25
readout chip [6,7] and tested with a pulse laser. Everystrip (50 mm pitch) is wire-bonded to an APV25 readout
channel. The laser light (l ¼ 890 nm) is focused to diameterof s10 mm by a microscope and injected from top
surface. The bias voltage dependence and laser position
dependence of the observed charge are measured asfollows. Charge collected by a strip is measured as afunction of reverse bias voltage in Fig. 4(a). This charge is
not saturated at the breakdown voltage of 60 V,indicating the depletion region has not reached to thefull substrate thickness.A laser spot is then scanned
across several strips in 5 mm steps and the charge inducedin the readout channels are recorded with the result shownin Fig. 4(b). The charge around the beam spot is reasonably distributed around the laser spot position. The dipsaround x ¼ 70, 120 and 170 mm corresponds to the shadowof the readout metal traces. There are no strips forxo20 mm.

863

20100-10050100150

Spot position
Fig. 4. Response of strip-detector TEG to a laser light (l ¼ 890 nm).
(a) The output charge as a function of the detector bias voltage. (b) The
result of a laser-position scan. The dashed, dotted and dot-dashed lines
correspond to charge from the ﬁrst three readout channels. The solid line
shows the sum of the eight readout channels.

done at 10 V bias voltage. Fig. 6(a) shows an image
obtained with a 670 nm laser and a photomask. Several
channels insensitive to light or saturated without light
were identiﬁed in this laser light test. The mechanism ofsuch a failure is under investigation. Fig. 6(b) shows theresponse of a pixel channel to a b-ray source (90Sr) as afunction of time. The channel is reset repeatedly andthe analog output is observed with an oscilloscope. The
size of the voltage step, corresponding to the charge
induced by the b-ray deposition, is consistent with theexpected depletion depth ð44 mmÞ and the detector capacitance (8 fF).
3.3. Other test structures
In the circuit TEG, combinations of high-sensitivity preampliﬁers and time-over-threshold circuits areARTICLE IN PRESS
T. Tsuboyama et al. / Nuclear Instruments and Methods in Physics Research A 582 (2007) 861–865

864

Raw-Pedestal
05Row

1015

20253005

1015
Column202530Reset signal (500 mV/div)

Vdd

Read_selectColumn out (10 mV/div)

Store

M1
Sense

M2

M6
Column
Out
M5

M4

OutD
Reset
Detector
Bias

M0
M3

LoadCs100 fF

VresetFig. 5. (a) Detail view of a pixel. The 100 fF metal–insulator–metal
capacitor overlaps to the neighbor cell. (b) Schematic of the front-end
circuit within each pixel.

implemented. As a low-threshold, fully depleted CMOS
circuit has not been widely used, this trial is important todevelop analog circuits with large dynamic range [9]. The
circuits work well. The minor errors in the circuit design
are understood and will be ﬁxed in the next submission.
The radiation TEG is an array of MOSFET transistors
with various design parameters. Several chips have been
irradiated in a proton beam and radiation tolerance ismeasured [10]. Another type of pixel sensor is designed foruse in an imaging hard X-ray Compton polarimeter inspace [11].
4. Back-gate effect and TCAD simulation
In the SOI sensor, bias voltage is applied to the substratein order to establish the necessary depletion layer. TheTime (2msec/div)
Fig. 6. (a) Image observed by PIXELTEG. The laser light ðl ¼ 670 nmÞ isinjected to the sensor through a photomask. (b) The response of a pixel toa b source. The full scale of the horizontal axis is 20 ms. The unit ofvertical axis is 500 mV/div for ‘‘Reset’’ (upper curve) and 10 mV/div for‘‘Column out’’ (lower curve). The lower curve shows non-linearity in time,
this is because the integration time is much larger than the designed
dynamic range of the front-end circuit shown in (b).

potential induced in the substrate could affect the operation of the SOI MOS transistors through the BOX
dielectric (back-gate effect). Due to lower resistivity thanis usual for a detector-grade substrate, higher voltage isnecessary to obtain the depleted thickness. The back-gateeffect can be controlled with a ring-shaped p-type implantin the substrate (guard ring) around the MOSFET. In
order to limit silicon processing iterations, a simulation
study was done to optimize the guard-ring structure.
Silicon-processing and device simulations have been
performed using two TCAD (technology CAD) systems:
ENEXSS [12], which is a newly developed TCAD system
intended for 3-D simulations, and Silvaco [13]. In order tostudy the back-gate effect, the characteristics of an n-type

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5. Summary

0.4

The R&D effort toward a pixel sensor based on 150-nm SOICMOS technology started in 2005. Several TEG chips areprocessed and evaluated in 2006. With STRIPTEG, thecharacteristics of the SOI wafer as a radiation sensor isexamined and it is conﬁrmed that the substrate works as aposition sensitive detector. Using the 32  32 array of 20 mm 20 mm pixel sensor, we observe charge induced by laser lightand by minimum ionizing particles. The TCAD simulationshows that, if proper guard rings are prepared around
MOSFETs, the SOI circuit can be operated up to 90 V reverse
bias voltage in the substrate. As we conﬁrmed the possibility ofthe SOI technology as a radiation sensor, the R&D will be
continued to achieve pixel sensor for real applications.

Threshold Voltage

Vth (V)

0.2

080µ
5µ2µ

Acknowledgments-0.2
V_bias (V)
-0.4
020

4060

80

100Fig. 7. (a) The simulation condition of TCAD. (b) Result of the device
simulation. Solid, dotted and dashed curves correspond to the gate
threshold voltage of the MOSFET for the case where the guard-ring
implant is placed 2, 5 and 80 mm, respectively.

MOSFET are simulated with a bias voltage V b in thesubstrate, as shown in Fig. 7(a) using ENEXSS in 2-D
mode. Below the BOX, a p-type guard ring is implanted ata distance, d, whose potential is ﬁxed to the voltage of thesource of the MOSFET. The gate threshold voltage of theMOSFET is calculated for 0oV b o100 V and for distanced at 2, 5 and 80 mm. The result is shown in Fig. 7(b). If weallow a threshold voltage shift of 0.1 V, a bias voltage of 90,
15 and 1 V can be applied to the backside of the substratefor d ¼ 2; 5 and 80 mm, respectively. We conclude the SoI
pixel sensor works at 90 V bias voltage if proper guard
rings are prepared around MOSFETs.

The authors wish to thank F. Takasaki, T. Kondo and J.
Haba for their support to this project. We are also gratefulto Y. Sugimoto and K. Hirose (JAXA) for their fruitful
discussions.
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