Nuclear Instruments and Methods in Physics Research A 623 (2010) 186–188

Contents lists available at ScienceDirect

Nuclear Instruments and Methods inPhysics Research A
journal homepage: www.elsevier.com/locate/nima

Developments of SOI monolithic pixel detectors
Y. Arai a,, T. Miyoshi a, Y. Unno a, T. Tsuboyama a, S. Terada a, Y. Ikegami a, T. Kohriki a, K. Tauchi a,Y. Ikemoto a, R. Ichimiya a, H. Ikeda b, K. Hara c, H. Miyake c, M. Kochiyama c, T. Sega c, K. Hanagaki d,M. Hirose d, T. Hatsui e, T. Kudo e, T. Hirono e, M. Yabashi e, Y. Furukawa e, G. Varner f, M. Cooney f,H. Hoedlmoser f, J. Kennedy f, H. Sahoo f, M. Battaglia g, P. Denes g, C. Vu g, D. Contarato g, P. Giubilato g,L. Glesener g, R. Yarema h, R. Lipton h, G. Deptuch h, M. Trimpl h, M. Ohno i, K. Fukuda i, H. Komatsubara i,J. Ida i, M. Okihara j, H. Hayashi j, Y. Kawai j, A. Ohtomo ja

Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org., KEK, Tsukuba 305-0801, Japan
Institute of Space and Astronautical Science, JAXA, Sagamihara, Kanagawa 229-8510, Japan
Institute of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Ibaraki 305-8577, Japan
dOsaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043, Japan
eRiken, 1-1-1, Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148, Japanf
Department of Physics and Astronomy, University of Hawaii, 2505 Correa Rd., 96822 Honolulu HI, USA
gLawrence Berkeley National Laboratory, Berkeley, CA 94720, USA
hFermilab, Batavia, IL 60510-5011, USAiOki Semiconductor Co. Ltd., Higashiasakawa, Hachioji, Tokyo 193-8550, JapanjOki Semiconductor Miyagi Co. Ltd., Ohira-mura, Kurokawa-gun, Miyagi 981-3693, Japanbca r t i c l e in f oa b s t r a c t

Available online 3 March 2010

A monolithic pixel detector with 0:2 mm silicon-on-insulator (SOI) CMOS technology has beendeveloped. It has both a thick high-resistivity sensor layer and thin LSI circuit layer on a single chip.
Integration-type and counting-type pixel detectors are fabricated and tested with light and X-rays. The
process is open to many researchers through Multi Project Wafer (MPW) runs operated by KEK. Further
improvements of the fabrication technologies are also under investigation by using a buried p-well and
3D integration technologies.
& 2010 Elsevier B.V. All rights reserved.

Keywords:
SOIPixel
X-ray imaging
Particle tracking

1. Introduction
A monolithic pixel detector, in which both semiconductor
sensors and readout electronics are fabricated on the same wafer
has many attractive features for applications in high-energy
experiments, astrophysics, material analysis, medical imaging andso on. We have realized such a detector by using a SOI (silicon-oninsulator) technology which bonds wafer of thick, high-resistivity
Si and thin low-resistivity Si together (see Fig. 1) [1,2].
Some of the SOI pixel detector features are No mechanical bump bonding, so obstacles which will cause
multiple scattering are minimized and smaller pixel size ispossible.
 Parasitic capacitances of sensing nodes are very smallð  10 fFÞ, so large conversion gain and low noise is possible.
 Full CMOS circuitry can be implemented.
 Corresponding author. Tel.: + 81298796211; fax: +81298643284.

E-mail address: yasuo.arai@kek.jp (Y. Arai).
0168-9002/$ - see front matter & 2010 Elsevier B.V. All rights reserved.
doi:10.1016/j.nima.2010.02.190

 Cross-section of single event effects is very small.
 The technology is based on industry standards, so further
progress and low cost is envisaged.

 SOI transistors are shown to work over a very large
temperature range from 4 to 600 K.

2. SOI pixel process and MPW run
We have developed a 0:2 mm SOI pixel process in collaboration
with OKI Semiconductor Co. Ltd. The basic technology for
fabricating the pixel detector is OKI’s fully-depleted 0:2 mm
CMOS SOI process [3]. Additional processing steps to create
substrate implants and contacts between the implant nodes to thecircuitry were established. Main speciﬁcations of the process aresummarized in Table 1.
To reduce development cost of a design, we have beenorganizing MPW (Multi Project Wafer) runs. Two MPW runs
were completed and one run is being processed now. In eachrun, we have about 16 designs from our collaborators [4–6].
Photograph of the last MPW run wafer is shown in Fig. 2.

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187

Vdd
read_x
store

sens
rst

M2

M6
nstore

M0

M4
M3

M5

load
Cs
100fF
col_out

Fig. 1. Cross sectional view of a SOI pixel detector.
Table 1
SOI pixel process speciﬁcation.
Process
SOI wafer

BacksideFig. 3. Schematic of the integration type pixel (INTPIX2).

0:2 mm low-leakage fully-depleted SOI CMOS, 1 Poly, 4 metallayers, MIM Cap., DMOS options, Core (I/O) voltage ¼1.8 (3.3) V
Diameter: 200 mmf, Top Si: Cz  18 Ocm, p-type, 40 nm
thick. Buried Oxide: 200 nm thick,Handle wafer: Cz  700 Ocm, n-type, 725 mm thickThinned to 260 mm, and sputtered with Al (200 nm).

Fig. 4. X-ray image taken with the integration type pixel. The results are shownfor three space resolution patterns from 12.5 to 20 lp/mm.

3.2. Counting-type pixel

Fig. 2. Photograph of a Multi Project Wafer processed in 2008. In addition toJapanese laboratories and universities, there are designs from US institutions.

A pixel circuit of the CNTPIX2 is shown in Fig. 5. The
preampliﬁer circuit is same type proposed by Krummenacher[7] which contains leakage current compensation circuitry. Afterthe low and high threshold discriminator, the input signal iscounted in a 16-bit counter. Layout of the CNTPIX2 is shown inFig. 6. There are 128 x 128 pixels in a 10.2 mm square chip. A
metal plate image taken with 8 keV X-ray is shown in Fig. 7 andthe operation was conﬁrmed. We also see some crosstalk within apixel and inefﬁciencies, so detailed study is continuing.

3. Pixel detectors
4. On-going R&D
We are developing two kinds of pixel detectors. One is anintegration-type pixel called INTPIX2, and the other is a countingtype pixel called CNTPIX2. In these detectors, reverse bias voltage
is applied from the bottom surface or top n+ HV ring. Breakdown
voltage is observed between 50 and 230 V depending on the pixel
layout. Leakage current is less than 0:1 pA=mm2 .

3.1. Integration-type pixel
A schematic of the INTPIX2 is shown in Fig. 3. Chip size is 5 mm
by 5 mm and has 128  128 pixels each 20 mm square. Fig. 4
shows a test chart image taken by the INTPIX2 with 8 keV X-rays.
It indicates 20 lines/mm is well resolved. Each pixel has a window
to illuminate light from topside to ease testing. It is possible toshrink the pixel size to less than 10 mm square.

Since the sensor nodes and circuits are placed very close
together in the SOI pixel detector, there will be some interference
between them. One of the newly developed techniques is buriedp-well creation in the substrate. We implant p-type dopant
through the top Si layer and create a buried p-well (BPW) region
under the BOX. This BPW region will help to ﬁx the undersidepotential of the transistors and reduce the so called back gateeffect. The doping level of the BPW is about 3 orders lower thanthat of the p+ sensor node and drain/source region, so it does notaffect the transistor characteristics in the top Si layer. Anotherdirection is 3D vertical integration. We will bond two SOI wafers
face to face by using micro-bump technology of ZyCube Co. Ltd[8]. Minimum pitch of the bump is 5 mm. This will enable higher
circuit integration density and separate the sensitive circuit
regions from the sensors.

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Y. Arai et al. / Nuclear Instruments and Methods in Physics Research A 623 (2010) 186–188

Fig. 5. Circuit of the CNTPIX2 pixel.

Fig. 7. X-ray Image of a metal mask taken with the CNTPIX2.
Fig. 6. Layout of a pixel in the CNTPIX2 chip. The size of a pixel is 60 mm by 60 mm,and each pixel contains about 600 transistors.

5. Summary
We have developed SOI based pixel technology and organized
MPW runs by collecting designs from many laboratories anduniversities. The number of MPW runs will be increased totwice/year. We have demonstrated basic performance of the SOI
integration-type and counting-type pixel detectors. To reduce theback-gate effect and improve radiation hardness, we are trying
buried p-well technology and 3D integration technology.

Acknowledgements
The authors wish to thank F. Takasaki and J. Haba for theircontinuing support to this project. This work is supported by VLSI

Design and Education Center (VDEC), The University of Tokyo
with the collaboration of the Cadence Corporation and Mentor
Graphics Corporation.

References[1] SOIPIX collaboration. /http://rd.kek.jp/project/soi/S.
[2] Y. Arai, Electronics and Sensor Study with the OKI SOI process, in: Proceedings ofTopical Workshop on Electronics for Particle Physics (TWEPP-07), CERN-2007-007,pp. 57–63.
[3] K. Morikawa, Y. Kajita, M. Mitarashi, OKI Technical Review, Issue 196, 70(4)(2003) 60.
[4] M. Battaglia, et al., Nucl. Instr. and Meth. A 583 (2007) 526.
[5] D. Kobayashi, et al., IEEE Trans. Nucl. Sci. NS-55 (2008) 2872.
[6] K. Hara, et al., Nucl. Sci. Symp. Conf. Record (2008) 1369.
[7] F. Krummenacher, Nucl. Instr. and Meth. A 305 (1991) 527.
[8] M. Motoyoshi, M. Koyanagi, 3D-LSI technology for image sensor, 2009 JINST 4
P03009, doi:10.1088/1748-0221/4/03/P03009.