IEEE TRANSACTIONS ON ELECTRON DEVICES

1

Analysis of Effective Gate Length Modulationby X-Ray Irradiation for Fully Depleted
SOI p-MOSFETs
Ikuo Kurachi, Kazuo Kobayashi, Masao Okihara, Member, IEEE, Hiroki Kasai, Takaki Hatsui,
Kazuhiko Hara, Toshinobu Miyoshi, and Yasuo Arai, Member, IEEE

Index Terms— Fully depleted-silicon-on-insulator (FD-SOI),
gate length modulation, MOSFET, sidewall spacer, X-ray
radiation hardness.

I. I NTRODUCTION

F

composed in the SOI handle wafer. These advantages are
suitable for an X-ray imaging sensor of medical or science
used to achieve high resolution with smaller pixel size. Then,the X-ray sensors have been reported, utilizing the SOI
structures [1]–[5]. However, even though the SOI device hashigher immunity to the SEU, it is weak in the total ionizing
dose effect [6]. This is due to the existence of relatively
thick oxide underneath the MOSFET so-called buried oxide(BOX) in the SOI structure. It is well known that positive
charges are generated in oxide by the X-ray irradiation [7].
For the n-channel MOSFET (n-MOSFET) case, the generated positive charge in the BOX alters the back potential.
Consequently, the threshold voltages decrease, and the drainto-source leakage enhancement is observed due to the backchannel formation in the n-MOSFET by X-ray irradiation [8].
Because the n-MOSFET degradation is due to the positive
charge generation in the BOX, reducing the BOX thickness
is one of solutions to improve the radiation hardness [9].
Furthermore, a double SOI structure has been proposed to
improve the radiation hardness where the middle SOI layer isused as a compensation electrode for the generated positive
charges in the BOX [10], [11]. On the other hand, there
are a few studies about the FD-SOI p-MOSFET degradation by the X-ray irradiation, and we found that it shows
extremely high degradation. In this paper, the degradationof the FD-SOI p-MOSFET has been investigated. We alsopresent an analytical model for the degradation due to aneffective channel length modulation by the X-ray irradiation[12]–[14], utilizing the model of positive charge generation in
the sidewall spacers.

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Abstract— An X-ray irradiation degradation mechanism has
been investigated for fully depleted-silicon-on-insulator (FD-SOI)
p-channel MOSFETs (p-MOSFETs). It is found that the draincurrent degradation by the X-ray irradiation has gate length
dependence showing 20% degradation for L = 0.2 µm, while
8% for L = 10 µm after the 1.4 kGy(Si) X-ray irradiation. Using
Terada’s method, it was found that the degradation is not due tomobility degradation but due to radiation-induced gate length
modulation (RIGLEM) and the associated increase of sourceand drain parasitic resistance. The major cause of degradationinduced by the RIGLEM is explained by an analytical model,
assuming a positive charge generation in sidewall spacers. It canbe suggested that the X-ray irradiation degradation of FD-SOI
p-MOSFET can be improved by optimizing the lightly doped
drain region.

OR the requirements of advanced and future large
scale integrated circuit technologies, a fully depletedsilicon-on-insulator (FD-SOI) technology is the most promising candidate because of its scalability, reduction of
power consumption while keeping high-speed operation,
wide temperature range operation, and radiation hardness for single-event upset (SEU). In addition, the SOI
structure is one of 3-D devices when active devices are

Manuscript received April 21, 2015; revised June 1, 2015; accepted
June 3, 2015. This work was supported in part by the Grants-in-Aid for Scientific Research (KAKENHI) through the KEK Detector Technology Project
within the Ministry of Education, Culture, Sports, Science and Technology
under Grant 25109001, in part by the X-Ray Free Electron Laser Priority
Strategy Program through the Ministry of Education, Culture, Sports, Scienceand Technology, and in part by KAKENHI through the Japan Society for the
Promotion of Science under Grant 13321217. The review of this paper was
arranged by Editor E. Rosenbaum.
I. Kurachi, T. Miyoshi, and Y. Arai are with High Energy
Accelerator Research Organization, Ibaraki 305-0801, Japan (e-mail:kurachii@post.kek.jp; tmiyoshi@post.kek.jp; yasuo.arai@kek.jp).
K. Kobayashi and T. Hatsui are with the RIKEN SPring-8 Center,
Sayo 671-5148, Japan (e-mail: kkoba@spring8.or.jp; hatsui@spring8.or.jp).
M. Okihara is with Lapis Semiconductor Company, Ltd.,
Yokohama 222-8575, Japan (e-mail: okihara274@mnf.lapis-semi.com).
H. Kasai is with Lapis Semiconductor Miyagi Company, Ltd.,
Miyagi 981-3693, Japan (e-mail: kasai774@myg.lapis-semi.com).
K. Hara is with the Faculty of Pure and Applied Sciences, University ofTsukuba, Tsukuba 305-857, Japan (e-mail: hara@hep.px.tsukuba.ac.jp).
Digital Object Identifier 10.1109/TED.2015.2443797

II. E XPERIMENTAL P ROCEDURE
A test-element group of MOSFETs [15] were fabricatedusing a 0.2 μm node FD-SOI CMOS process technology fora radiation sensor application prepared by LAPIS Semiconductor Co., Ltd. [16]. Thicknesses of the BOX, the SOI layer, andthe gate oxide are 200, 40, and 4.4 nm, respectively. A channel
stop implantation into the sidewall of the SOI active edge was
employed to prevent the isolation edge effect by the X-ray
irradiation [17]. A conventional lightly doped drain (LDD)
structure was applied to reduce the hot-carrier and shortchannel effects. Co-salicided diffusion and gate poly werealso employed to reduce parasitic resistance and make the0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

2IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 1. p-MOSFET’s drain current degradation at the linear region as afunction of X-ray irradiation dose. For shorter gate length as 0.2 μm, thedegradation is around two times faster than that for longer gate length as
10 μm.

Fig. 2. Threshold voltage and transconductance changes after the 1.4 kGy(Si)X-ray irradiation as a function of the gate length. There is only 5 mV
difference in Vto among p-MOSFETs with shorter and longer gate length.
This means that the generated positive charges in the gate oxide have small
gate length dependence. On the other hand, about 15% difference is observedin the gm degradation.

by the generation of interface states between the gate oxide
and the silicon or positive charge generation in the gate oxide.
In both cases, the threshold voltage is also shifted. Then, theresults of Fig. 2 do not clearly show the actual cause of thedegradation.

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contact formation process reliable [18]. The designed gate
lengths are changed from 0.2 to 10 μm with the constantgate width of 10 μm. To evaluate the MOSFET characteristics
before and after the X-ray irradiation, Id –Vg curves with
Vds = −0.1 V were measured for p-MOSFETs. In all of
Id –Vg measurements, the body of MOSFETs was floating,and the substrate was connected to the ground. To estimate
the generated charge in the BOX, the I –V characteristics
against back gate were measured with the front gate grounded
before and after the X-ray irradiation for n-MOSFETs at
Vds = 0.1 V. X-ray irradiation was carried out at a constantdose rate of 0.018 Gy(Si)/s using a wafer-level X-ray irradiation system [15]. An X-ray generator with a rotary cathodetarget of molybdenum (RIGAKU: Ultra18X) was used as thesource at an acceleration voltage of 40 kV. An aluminum
filter with a thickness of 0.5 mm was inserted to suppress
X-rays below 10 keV. During the irradiation, all the pads for
MOSFETs were connected to the ground.
III. R ESULTS AND D ISCUSSION

A. Drain Current Degradation by X-Ray Irradiation

The drain current degradation in the linear region is
confirmed for p-MOSFETs of 0.2 and 10 μm in gate length,
as shown in Fig. 1. The drain currents decrease with the
X-ray irradiation dose. Note that similar degradation wasobserved for gamma-ray irradiation. Since X-ray was irradiated uniformly, the generated charge by X-ray must be
uniformly distributed in the channel, because all terminals
were grounded during the irradiation. Therefore, the draincurrent degradation rate should exhibit small gate length
dependence. However, the drain current degradation of 0.2 μm
MOSFETs is 20% after the 1.4 kGy(Si) irradiation, whereas
only 8% degradation for 10 μm MOSFETs. The gate length
dependence of threshold voltage shift, Vto , and transconductance degradation rate, gm_max /gm_max 0 , are also investigated after the 1.4 kGy(Si) X-ray irradiation, as shownin Fig. 2. Even though the gate length was varied from
0.2 to 10 μm, the threshold voltage shifts are distributed
from −0.045 to −0.050 V and the difference is only 5 mV.
This indicates that the generated charge in the gate oxideshould be almost uniformly distributed in the channel ofthese gate length varied MOSFETs. On the other hand, thetransconductance degradation rate depends strongly on the gate
length. In general, the transconductance degradation is caused

B. Degradation Mechanism Estimation by Terada’s Method
To clarify the degradation mechanism, carrier mobility, gate
length modulation, and source and drain parasitic resistanceare extracted using Terada’s method [19]. Assuming thatthe source and the drain parasitic resistances, Rs and Rd ,are connected to the MOSFET in series, the measured total
resistance, Rm = Vds /Ids , is given by
Rm = ρch

L eff+ (Rs + Rd )
Weff

(1)

where ρch is the channel sheet resistance and L eff and Weff
are the effective gate length and the width, respectively. It isnoted that the effective gate length is not the distance between
metallurgical junctions of the source and the drain, but theelectric effective gate length in which region the surface
potential can be modulated by the gate potential. Using thedesigned gate length, L drawn , the effective gate length is
L eff = L drawn + δL

(2)

where δL is the bias from the designed length to the effective
length. Substituting (2) into (1) and using Rext = Rs + Rd
yields


ρch
ρch
Rm =
L drawn + δL
+ Rext .
(3)
Weff
Weff

From the relation between Rm and L drawn , ρch /Weff andδLρch /Weff + Rext for different Vgs –Vto can be calculated.
Linear relations between ρch /Weff and δLρch /Weff + Rext are
confirmed for the samples before and after X-ray irradiation,
as shown in Fig. 3. From these relations, δ L and Rext

KURACHI et al.: ANALYSIS OF EFFECTIVE GATE LENGTH MODULATION BY X-RAY IRRADIATION FOR FD-SOI pMOSFETs

3

Fig. 3. Plot between δ Lρch / Weff + Rext and ρch / Weff calculated from (3)as a parameter of X-ray irradiation dose. Good linear relations for each doseare confirmed for all doses. The Y -intercept and gradient of the lines are
Rext and δ L, respectively.

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Fig. 5. Results by Terada’s method calculation for (a) mobility changes,(b) gate length bias changes, and (c) parasitic resistance changes of
p-MOSFETs as a function of X-ray irradiation dose. The relative changes
in mobility are small, whereas those in the gate length modulation and theparasitic resistance are large.

Fig. 4. Relation between 1/ρch and Vgs –Vto to extract the mobility of channelholes for the preradiation and 1.4 kGy(Si) irradiated samples. Almost no
difference in the mobility is observed by X-ray irradiation.

are extracted. On the other hand, the channel sheet resistancecan be described as
1
(4)
ρch =
μCox (Vgs − Vto )where μ is the carrier mobility, Cox is the gate capacitance,
and Vto is the threshold voltage. Reciprocals of ρch as afunction of Vgs–Vto are shown in Fig. 4 for preradiation and1.4 kGy(Si) irradiated samples. Then, using this method, μ,δ L, and Rext as a function of the X-ray irradiation doseare extracted and shown in Fig. 5. As shown in the figure,the mobility degradation by the X-ray irradiation is small.
On the other hand, the effective gate length and the parasitic
source and drain resistance increase with the X-ray dose.
This is quite interesting that the transconductance degradation
shown in Fig. 2 is not induced by the mobility degradation,
but by the effective gate length modulation, leading to thetransconductance degradation. Because the major factors ofthe degradation by the X-ray irradiation are related to the gate
length modulation and the parasitic source and drain resistanceincrease, the degradation phenomenon occurs at the edges of
the gate. Based on the knowledge that the X-ray irradiation
damages are positive charge generation in oxide and surface
state generation at the Si–SiO2 interface [7], the following
two degradation mechanisms are suspected. One is that thepositive charge generated in the BOX by the X-ray irradiation [20] modulates the LDD region, because the concentrationof LDD is as low as 1018 cm−3 order, and the resistance of
LDD layer may be easily changed by the generated positive
charge in the BOX. The other is that the generated positiveFig. 6. Degradation of drain current in the linear region by substrate bias for a
fresh p-MOSFET. The 6.5 V of Vsub is equivalent to the positive charge in the
BOX after the 1.4 kGy(Si) irradiation. Dashed line: drain current degradationby the 1.4 kGy(Si) X-ray irradiation.

charge in the sidewall spacers [21] may increase the absolute
threshold voltage at gate edge and cause the drain current
degradation.
C. Effect of Generated Positive Charge in the Box

The effect of the generated positive charge in the BOX
can be easily evaluated from the substrate bias (Vsub ) dependence of MOSFETs, because the positive charge generation in the BOX is equivalent to supplying the positive
bias to the substrate. Fig. 6 shows the Id_lin degradationby Vsub. In this figure, the Id_lin degradation after the
1.4 kGy(Si) X-ray irradiation is shown in Fig. 6 (dashedline). The indicated Vsub of 6.5 V is equivalent to thepositive charge in the BOX after the 1.4 kGy(Si) X-ray
irradiation, which was obtained from the backside gate
I –V for n-MOSFETs. The Id_lin degradation by the substratebias accounts for only 6.5% for Vsub = 14 V, whereas 20% for
the 1.4 kGy(Si) X-ray irradiation samples. The μ, δ L, and Rext

4

IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 8. Schematic cross section and an equivalent circuit to explain parasitic
p-MOSFETs at both the source and the drain sides. Effective gate length,
drain voltage, and threshold voltage of the center MOSFET are L eff2 , Vds2 ,and Vto , respectively. Those of the parasitic source or the drain side MOSFET
are L eff1 , Vds1 , and Vto1 or L eff1 , Vds3 , and Vto1 , respectively.

To simplify the calculation, Rext = 0 is assumed. Substituting(6)–(8) into (9) yields
Rm =

Vds
Ids



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Fig. 7. Results by Terada’s method calculation for (a) mobility changes,(b) gate length bias changes, and (c) parasitic resistance changes of
p-MOSFETs as a function of substrate bias. The 6.5 V of Vsub is equivalent
to the positive charge in the BOX after the 1.4 kGy(Si) irradiation.
Dashed lines: degradation by the 1.4 kGy(Si) X-ray irradiation similar to
Fig. 6. The mobility, gate length bias, and parasitic resistance changes evenat Vsub = 14 V are within those induced by the 1.4 kGy(Si) X-ray irradiation.

changes by Vsub are also extracted using Terada’s method
and shown in Fig. 7. There is no significant δL and Rext
degradations by Vsub. Therefore, it is concluded that thep-MOSFET degradation by the X-ray irradiation is not solely
due to the generated positive charge in the BOX.
D. Effect of Generated Positive Charge in Spacers

Considering the charge generation by X-ray irradiation, the
MOSFET structure can be divided into three regions, as shownin Fig. 8. The drain current of MOSFET through Region II iscontrolled by the gate potential and affected by the charge ingate oxide after the X-ray irradiation. On the other hand, thedrain current of MOSFETs in Region I and Region III, which
are in the edge portions of MOSFET, is affected additionallyby the positive charge in the sidewall spacers. When theeffective gate length of Region II MOSFET is L eff2 and thatof Region I or Region III is L eff1 , then the total effective gate
length, L eff , isL eff = L eff2 + 2L eff1 .

The drain currents of each MOSFET are described as
Weff
Ids =
μCox (Vgs − Vto1 )Vds1
L eff1Weff
μCox (Vgs − Vds1 − Vto )Vds2
Ids =L eff2Weff
Ids =μCox [Vgs − (Vds1 + Vds2 ) − Vto1 ]Vds3
L eff1andVds = Vds1 + Vds2 + Vds3 .

(5)

(6)
(7)
(8)

(9)

1
=
Weff μCox

L eff2
L eff1+
Vgs − Vto1
Vgs − Vds1 − Vto
L eff1.
+
Vgs − (Vds1 + Vds2 ) − Vto1

(10)

It is assumed that Vgs − Vto  Vds1 and Vgs − Vto1 Vds1 + Vds2 , then (10) becomes
2L eff1
1
L eff2Rm =+Weff μCox Vgs − Vto1
Vgs − VtoVgs − Vtoρch
L eff2 + 2L eff1
.
(11)
=
Weff
Vgs − Vto1
Comparing (11) with (1) yields

L eff = L eff2 + 2L eff1

Vgs − Vto.
Vgs − Vto1

(12)

If there are positive charges in the sidewall spacers,
Vto1 should shift to the negative. For p-MOSFET case, Vgs
is the negative. Then, Vgs–Vto1 decreases and L eff increases.
The L eff modulation factor is a fractional expression in thesecond term in the right-hand side of (12) and can be
rewritten as
Vgs − Vto
Vgs − Vto
1
=
=
(13)
Vgs − Vto1
Vgs − (Vto + V to1)
1 − V to1
Vgs −Vto

where Vto1 = Vto1–Vto . With the consideration of Vto value(|Vto| ∼ 0.8 V) and measurement conditions (|Vgs| ∼ 1.8 V),
Vgs –Vto can be approximated to be 1, and then (13) becomesVgs − Vto ∼1.
=
Vgs − Vto1
1 − V to1(14)

L eff after the X-ray irradiation with the dose of x is given by
L eff (x) = L eff2 + 2L eff11
1 − V to1(15)

KURACHI et al.: ANALYSIS OF EFFECTIVE GATE LENGTH MODULATION BY X-RAY IRRADIATION FOR FD-SOI pMOSFETs

Fig. 9. Trapped hole densities as a function of X-ray irradiation dose in the
BOX and the sidewall spacer. To calculate the number of the trapped holes
in the sidewall spacer, it is assumed that L eff1 is 0.01 μm and the thicknessof the sidewall spacer is 65 nm.

5the gm degradation by the X-ray irradiation was confirmed.
To investigate the mechanisms of the degradation, the analysis
based on Terada’s method was examined. It is found that thedegradation is due to the effective gate length modulation andthe external parasitic source and drain resistance but not due tothe mobility reduction. The effective gate length modulation iscaused by the generated positive charge in the sidewall spacers,
as concluded from the model of local Vt shift induced at thegate edges. Based on this model, the radiation hardness for
FD-SOI LDD p-MOSFET should be improved by higher LDD
implant dosage such that the gate overlap region of LDD isextended and consequently the gate edge transistors may also
be controlled solely by the gate potential, not by charges inthe sidewall spacers.
R EFERENCES

and that for the preradiation is also given by (5). Then, thevariation of δ L by the X-ray radiation, δL, is expressed byδ L = (L eff (x) − L drawn ) − (L eff (0) − L drawn )Vto1.
= L eff (x) − L eff (0) = 2L eff1
1 − Vto1

(16)

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When Vto1  1, (17) becomes[1] B. Dierickx et al., “Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers,” IEEE Trans.
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δL = 2L eff1 Vto1.

(17)

If the effective oxide thickness of the sidewall spacer
is Tox_sw , the effective generated charge in the sidewall spacer,Not_sw , isεSiO2
Not_sw =δL(18)
2q L eff1 Tox_sw

where q is the elementary electron charge and εsio2 is thepermittivity of oxide. Assuming L eff1 = 0.01 μm andTox_sw = 65 nm, Not_sw is calculated from measured δL,
as shown in Fig. 9, as a function of the X-ray irradiation
dose. In this figure, the generated positive charges in the BOX
calculated from the back gate Vt shift of n-MOSFETs arealso shown. It is confirmed that both trends for the estimatedgenerated charges in the sidewall spacer and the BOX arealmost the same. Based on these results, it is concluded
that the gate length modulation by the X-ray irradiation in
p-MOSFETs, which is the major cause of degradation, is the
local Vt shift at gate edges due to the generated positive
charge in the sidewall spacers. This effect must be enhanced
when the ON-state bias is used during the X-ray irradiation
instead of the OFF-state bias of this experiment. In addition,
we have confirmed that the higher LDD dosage suppresses thegate length modulation effect and improves the drain current
degradation by the X-ray irradiation. The detailed results will
be presented elsewhere in the future.
IV. C ONCLUSIONThe X-ray irradiation-induced drain current degradationof FD-SOI p-MOSFET has been studied. The drain current
degradation of 20% was observed in the linear region after
the 1.4 kGy(Si) X-ray irradiation for 0.2 μm transistors in thegate length, whereas 8% for 10 μm transistors. No obvious
gate length dependence of Vt shift but clear dependence of6IEEE TRANSACTIONS ON ELECTRON DEVICES[19] K. Terada and H. Muta, “A new method to determine effective MOSFET
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Takaki Hatsui received the B.S. and M.S. degrees
in chemistry from Kyoto University, Kyoto, Japan,
in 1994 and 1996, respectively, and the Ph.D. degreein science from the Graduate School for Advanced
Studies, Hayama, Japan, in 1999.
He was with the Institute for Molecular Science,
Okazaki, Japan, as an Assistant Professor. He joined
RIKEN SPring-8 Center, RIKEN, Hyogo, Japan, in
2007, and leading the development of X-ray detector
systems.

Kazuhiko Hara received the B.S. and Ph.D. degrees
in science from the University of Tsukuba, Tsukuba,
Japan, in 1980 and 1985, respectively.
He joined the University of Tsukuba in 1989,
where he was an Associate Professor of Particle
Physics. His current research interests include thedevelopment of radiation hard pixel detectors forparticle physics experiments.

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Ikuo Kurachi received the B.S. degree in applied
physics from the Tokyo University of Science,
Tokyo, Japan, in 1983.
He joined OKI Electric Industry Company, Ltd.,Tokyo, in 1983. He joined High Energy Accelerator
Research Organization, Ibaraki, Japan, in 2014, asa Professor. His current research interests include
interface property of Si-SiO2, MOSFET reliability, and process integration technology for memory,
logic, and sensor devices.

Hiroki Kasai received the B.S. degree from Niigata
University, Niigata, Japan, in 2001.
He joined Oki Electric Industry Company, Ltd.,Tokyo, Japan, in 2006. He has been with Lapis Semiconductor Miyagi Company, Ltd., Miyagi, Japan,
since 2011. He is currently involved in the processdevelopment of sensing devices.

Kazuo Kobayashi received the B.E. degree inelectronic engineering from Kobe University, Kobe,
Japan, in 1985.
He joined OKI Electric Industry Company, Ltd.,Tokyo, Japan, in 1985. He joined RIKEN SPring-8
Center, RIKEN, Hyogo, Japan, in 1995, and collaborated to launch SPring-8. He joined the Japan
Synchrotron Radiation Research Institute, Hyogo,
in 2009.
Mr. Kobayashi is a member of the Accelerator
Division.

Masao Okihara (M’12) received the B.S. and
M.S. degrees in physics from Ehime University,
Matsuyama, Japan, in 1988 and 1990, respectively.
He joined OKI Electric Industry Company, Ltd.,Tokyo, Japan, in 1990. He has been with Lapis
Semiconductor Company, Ltd., Yokohama, Japan,
since 2011, where he has been involved in thesensing devices development.

Toshinobu Miyoshi was born in Miyagi, Japan,
in 1973. He received the Ph.D. degree in Sciencefrom Tohoku University, Miyagi, in 2003.
He joined High Energy Accelerator Research
Organization, Ibaraki, Japan, in 2008, where he has
been involved in SOI monolithic pixel sensor.

Yasuo Arai (M’87) received the Ph.D. degree innuclear science from Tohoku University, Sendai,
Japan, in 1982.
He has been with High Energy Accelerator
Research Organization (KEK), Ibaraki, Japan, since1982. He has been involved in the development ofreadout LSI for radiation detector since 1987. He iscurrently a Professor with the Electronics System
Group, KEK.

IEEE TRANSACTIONS ON ELECTRON DEVICES

1

Analysis of Effective Gate Length Modulationby X-Ray Irradiation for Fully Depleted
SOI p-MOSFETs
Ikuo Kurachi, Kazuo Kobayashi, Masao Okihara, Member, IEEE, Hiroki Kasai, Takaki Hatsui,
Kazuhiko Hara, Toshinobu Miyoshi, and Yasuo Arai, Member, IEEE

Index Terms— Fully depleted-silicon-on-insulator (FD-SOI),
gate length modulation, MOSFET, sidewall spacer, X-ray
radiation hardness.

I. I NTRODUCTION

F

composed in the SOI handle wafer. These advantages are
suitable for an X-ray imaging sensor of medical or science
used to achieve high resolution with smaller pixel size. Then,the X-ray sensors have been reported, utilizing the SOI
structures [1]–[5]. However, even though the SOI device hashigher immunity to the SEU, it is weak in the total ionizing
dose effect [6]. This is due to the existence of relatively
thick oxide underneath the MOSFET so-called buried oxide(BOX) in the SOI structure. It is well known that positive
charges are generated in oxide by the X-ray irradiation [7].
For the n-channel MOSFET (n-MOSFET) case, the generated positive charge in the BOX alters the back potential.
Consequently, the threshold voltages decrease, and the drainto-source leakage enhancement is observed due to the backchannel formation in the n-MOSFET by X-ray irradiation [8].
Because the n-MOSFET degradation is due to the positive
charge generation in the BOX, reducing the BOX thickness
is one of solutions to improve the radiation hardness [9].
Furthermore, a double SOI structure has been proposed to
improve the radiation hardness where the middle SOI layer isused as a compensation electrode for the generated positive
charges in the BOX [10], [11]. On the other hand, there
are a few studies about the FD-SOI p-MOSFET degradation by the X-ray irradiation, and we found that it shows
extremely high degradation. In this paper, the degradationof the FD-SOI p-MOSFET has been investigated. We alsopresent an analytical model for the degradation due to aneffective channel length modulation by the X-ray irradiation[12]–[14], utilizing the model of positive charge generation in
the sidewall spacers.

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Abstract— An X-ray irradiation degradation mechanism has
been investigated for fully depleted-silicon-on-insulator (FD-SOI)
p-channel MOSFETs (p-MOSFETs). It is found that the draincurrent degradation by the X-ray irradiation has gate length
dependence showing 20% degradation for L = 0.2 µm, while
8% for L = 10 µm after the 1.4 kGy(Si) X-ray irradiation. Using
Terada’s method, it was found that the degradation is not due tomobility degradation but due to radiation-induced gate length
modulation (RIGLEM) and the associated increase of sourceand drain parasitic resistance. The major cause of degradationinduced by the RIGLEM is explained by an analytical model,
assuming a positive charge generation in sidewall spacers. It canbe suggested that the X-ray irradiation degradation of FD-SOI
p-MOSFET can be improved by optimizing the lightly doped
drain region.

OR the requirements of advanced and future large
scale integrated circuit technologies, a fully depletedsilicon-on-insulator (FD-SOI) technology is the most promising candidate because of its scalability, reduction of
power consumption while keeping high-speed operation,
wide temperature range operation, and radiation hardness for single-event upset (SEU). In addition, the SOI
structure is one of 3-D devices when active devices are

Manuscript received April 21, 2015; revised June 1, 2015; accepted
June 3, 2015. This work was supported in part by the Grants-in-Aid for Scientific Research (KAKENHI) through the KEK Detector Technology Project
within the Ministry of Education, Culture, Sports, Science and Technology
under Grant 25109001, in part by the X-Ray Free Electron Laser Priority
Strategy Program through the Ministry of Education, Culture, Sports, Scienceand Technology, and in part by KAKENHI through the Japan Society for the
Promotion of Science under Grant 13321217. The review of this paper was
arranged by Editor E. Rosenbaum.
I. Kurachi, T. Miyoshi, and Y. Arai are with High Energy
Accelerator Research Organization, Ibaraki 305-0801, Japan (e-mail:kurachii@post.kek.jp; tmiyoshi@post.kek.jp; yasuo.arai@kek.jp).
K. Kobayashi and T. Hatsui are with the RIKEN SPring-8 Center,
Sayo 671-5148, Japan (e-mail: kkoba@spring8.or.jp; hatsui@spring8.or.jp).
M. Okihara is with Lapis Semiconductor Company, Ltd.,
Yokohama 222-8575, Japan (e-mail: okihara274@mnf.lapis-semi.com).
H. Kasai is with Lapis Semiconductor Miyagi Company, Ltd.,
Miyagi 981-3693, Japan (e-mail: kasai774@myg.lapis-semi.com).
K. Hara is with the Faculty of Pure and Applied Sciences, University ofTsukuba, Tsukuba 305-857, Japan (e-mail: hara@hep.px.tsukuba.ac.jp).
Digital Object Identifier 10.1109/TED.2015.2443797

II. E XPERIMENTAL P ROCEDURE
A test-element group of MOSFETs [15] were fabricatedusing a 0.2 μm node FD-SOI CMOS process technology fora radiation sensor application prepared by LAPIS Semiconductor Co., Ltd. [16]. Thicknesses of the BOX, the SOI layer, andthe gate oxide are 200, 40, and 4.4 nm, respectively. A channel
stop implantation into the sidewall of the SOI active edge was
employed to prevent the isolation edge effect by the X-ray
irradiation [17]. A conventional lightly doped drain (LDD)
structure was applied to reduce the hot-carrier and shortchannel effects. Co-salicided diffusion and gate poly werealso employed to reduce parasitic resistance and make the0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

2IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 1. p-MOSFET’s drain current degradation at the linear region as afunction of X-ray irradiation dose. For shorter gate length as 0.2 μm, thedegradation is around two times faster than that for longer gate length as
10 μm.

Fig. 2. Threshold voltage and transconductance changes after the 1.4 kGy(Si)X-ray irradiation as a function of the gate length. There is only 5 mV
difference in Vto among p-MOSFETs with shorter and longer gate length.
This means that the generated positive charges in the gate oxide have small
gate length dependence. On the other hand, about 15% difference is observedin the gm degradation.

by the generation of interface states between the gate oxide
and the silicon or positive charge generation in the gate oxide.
In both cases, the threshold voltage is also shifted. Then, theresults of Fig. 2 do not clearly show the actual cause of thedegradation.

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contact formation process reliable [18]. The designed gate
lengths are changed from 0.2 to 10 μm with the constantgate width of 10 μm. To evaluate the MOSFET characteristics
before and after the X-ray irradiation, Id –Vg curves with
Vds = −0.1 V were measured for p-MOSFETs. In all of
Id –Vg measurements, the body of MOSFETs was floating,and the substrate was connected to the ground. To estimate
the generated charge in the BOX, the I –V characteristics
against back gate were measured with the front gate grounded
before and after the X-ray irradiation for n-MOSFETs at
Vds = 0.1 V. X-ray irradiation was carried out at a constantdose rate of 0.018 Gy(Si)/s using a wafer-level X-ray irradiation system [15]. An X-ray generator with a rotary cathodetarget of molybdenum (RIGAKU: Ultra18X) was used as thesource at an acceleration voltage of 40 kV. An aluminum
filter with a thickness of 0.5 mm was inserted to suppress
X-rays below 10 keV. During the irradiation, all the pads for
MOSFETs were connected to the ground.
III. R ESULTS AND D ISCUSSION

A. Drain Current Degradation by X-Ray Irradiation

The drain current degradation in the linear region is
confirmed for p-MOSFETs of 0.2 and 10 μm in gate length,
as shown in Fig. 1. The drain currents decrease with the
X-ray irradiation dose. Note that similar degradation wasobserved for gamma-ray irradiation. Since X-ray was irradiated uniformly, the generated charge by X-ray must be
uniformly distributed in the channel, because all terminals
were grounded during the irradiation. Therefore, the draincurrent degradation rate should exhibit small gate length
dependence. However, the drain current degradation of 0.2 μm
MOSFETs is 20% after the 1.4 kGy(Si) irradiation, whereas
only 8% degradation for 10 μm MOSFETs. The gate length
dependence of threshold voltage shift, Vto , and transconductance degradation rate, gm_max /gm_max 0 , are also investigated after the 1.4 kGy(Si) X-ray irradiation, as shownin Fig. 2. Even though the gate length was varied from
0.2 to 10 μm, the threshold voltage shifts are distributed
from −0.045 to −0.050 V and the difference is only 5 mV.
This indicates that the generated charge in the gate oxideshould be almost uniformly distributed in the channel ofthese gate length varied MOSFETs. On the other hand, thetransconductance degradation rate depends strongly on the gate
length. In general, the transconductance degradation is caused

B. Degradation Mechanism Estimation by Terada’s Method
To clarify the degradation mechanism, carrier mobility, gate
length modulation, and source and drain parasitic resistanceare extracted using Terada’s method [19]. Assuming thatthe source and the drain parasitic resistances, Rs and Rd ,are connected to the MOSFET in series, the measured total
resistance, Rm = Vds /Ids , is given by
Rm = ρch

L eff+ (Rs + Rd )
Weff

(1)

where ρch is the channel sheet resistance and L eff and Weff
are the effective gate length and the width, respectively. It isnoted that the effective gate length is not the distance between
metallurgical junctions of the source and the drain, but theelectric effective gate length in which region the surface
potential can be modulated by the gate potential. Using thedesigned gate length, L drawn , the effective gate length is
L eff = L drawn + δL

(2)

where δL is the bias from the designed length to the effective
length. Substituting (2) into (1) and using Rext = Rs + Rd
yields


ρch
ρch
Rm =
L drawn + δL
+ Rext .
(3)
Weff
Weff
From the relation between Rm and L drawn , ρch /Weff andδLρch /Weff + Rext for different Vgs –Vto can be calculated.
Linear relations between ρch /Weff and δLρch /Weff + Rext are
confirmed for the samples before and after X-ray irradiation,
as shown in Fig. 3. From these relations, δL and Rext

KURACHI et al.: ANALYSIS OF EFFECTIVE GATE LENGTH MODULATION BY X-RAY IRRADIATION FOR FD-SOI pMOSFETs

3

Fig. 3. Plot between δ Lρch / Weff + Rext and ρch / Weff calculated from (3)as a parameter of X-ray irradiation dose. Good linear relations for each doseare confirmed for all doses. The Y -intercept and gradient of the lines are
Rext and δ L, respectively.

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Fig. 5. Results by Terada’s method calculation for (a) mobility changes,(b) gate length bias changes, and (c) parasitic resistance changes of
p-MOSFETs as a function of X-ray irradiation dose. The relative changes
in mobility are small, whereas those in the gate length modulation and theparasitic resistance are large.

Fig. 4. Relation between 1/ρch and Vgs –Vto to extract the mobility of channelholes for the preradiation and 1.4 kGy(Si) irradiated samples. Almost no
difference in the mobility is observed by X-ray irradiation.

are extracted. On the other hand, the channel sheet resistancecan be described as
1
(4)
ρch =
μCox (Vgs − Vto )where μ is the carrier mobility, Cox is the gate capacitance,
and Vto is the threshold voltage. Reciprocals of ρch as afunction of Vgs–Vto are shown in Fig. 4 for preradiation and1.4 kGy(Si) irradiated samples. Then, using this method, μ,δL, and Rext as a function of the X-ray irradiation doseare extracted and shown in Fig. 5. As shown in the figure,the mobility degradation by the X-ray irradiation is small.
On the other hand, the effective gate length and the parasitic
source and drain resistance increase with the X-ray dose.
This is quite interesting that the transconductance degradation
shown in Fig. 2 is not induced by the mobility degradation,
but by the effective gate length modulation, leading to thetransconductance degradation. Because the major factors ofthe degradation by the X-ray irradiation are related to the gate
length modulation and the parasitic source and drain resistanceincrease, the degradation phenomenon occurs at the edges of
the gate. Based on the knowledge that the X-ray irradiation
damages are positive charge generation in oxide and surface
state generation at the Si–SiO2 interface [7], the following
two degradation mechanisms are suspected. One is that thepositive charge generated in the BOX by the X-ray irradiation [20] modulates the LDD region, because the concentrationof LDD is as low as 1018 cm−3 order, and the resistance of
LDD layer may be easily changed by the generated positive
charge in the BOX. The other is that the generated positiveFig. 6. Degradation of drain current in the linear region by substrate bias for a
fresh p-MOSFET. The 6.5 V of Vsub is equivalent to the positive charge in the
BOX after the 1.4 kGy(Si) irradiation. Dashed line: drain current degradationby the 1.4 kGy(Si) X-ray irradiation.

charge in the sidewall spacers [21] may increase the absolute
threshold voltage at gate edge and cause the drain current
degradation.
C. Effect of Generated Positive Charge in the Box

The effect of the generated positive charge in the BOX
can be easily evaluated from the substrate bias (Vsub ) dependence of MOSFETs, because the positive charge generation in the BOX is equivalent to supplying the positive
bias to the substrate. Fig. 6 shows the Id_lin degradationby Vsub. In this figure, the Id_lin degradation after the
1.4 kGy(Si) X-ray irradiation is shown in Fig. 6 (dashedline). The indicated Vsub of 6.5 V is equivalent to thepositive charge in the BOX after the 1.4 kGy(Si) X-ray
irradiation, which was obtained from the backside gate
I –V for n-MOSFETs. The Id_lin degradation by the substratebias accounts for only 6.5% for Vsub = 14 V, whereas 20% for
the 1.4 kGy(Si) X-ray irradiation samples. The μ, δL, and Rext

4

IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 8. Schematic cross section and an equivalent circuit to explain parasitic
p-MOSFETs at both the source and the drain sides. Effective gate length,
drain voltage, and threshold voltage of the center MOSFET are L eff2 , Vds2 ,and Vto , respectively. Those of the parasitic source or the drain side MOSFET
are L eff1 , Vds1 , and Vto1 or L eff1 , Vds3 , and Vto1 , respectively.

To simplify the calculation, Rext = 0 is assumed. Substituting(6)–(8) into (9) yields
Rm =

Vds
Ids



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Fig. 7. Results by Terada’s method calculation for (a) mobility changes,(b) gate length bias changes, and (c) parasitic resistance changes of
p-MOSFETs as a function of substrate bias. The 6.5 V of Vsub is equivalent
to the positive charge in the BOX after the 1.4 kGy(Si) irradiation.
Dashed lines: degradation by the 1.4 kGy(Si) X-ray irradiation similar to
Fig. 6. The mobility, gate length bias, and parasitic resistance changes evenat Vsub = 14 V are within those induced by the 1.4 kGy(Si) X-ray irradiation.

changes by Vsub are also extracted using Terada’s method
and shown in Fig. 7. There is no significant δL and Rext
degradations by Vsub. Therefore, it is concluded that thep-MOSFET degradation by the X-ray irradiation is not solely
due to the generated positive charge in the BOX.
D. Effect of Generated Positive Charge in Spacers

Considering the charge generation by X-ray irradiation, the
MOSFET structure can be divided into three regions, as shownin Fig. 8. The drain current of MOSFET through Region II iscontrolled by the gate potential and affected by the charge ingate oxide after the X-ray irradiation. On the other hand, thedrain current of MOSFETs in Region I and Region III, which
are in the edge portions of MOSFET, is affected additionallyby the positive charge in the sidewall spacers. When theeffective gate length of Region II MOSFET is L eff2 and thatof Region I or Region III is L eff1 , then the total effective gate
length, L eff , isL eff = L eff2 + 2L eff1 .

The drain currents of each MOSFET are described as
Weff
Ids =
μCox (Vgs − Vto1 )Vds1
L eff1
Weff
Ids =μCox (Vgs − Vds1 − Vto )Vds2
L eff2Weff
Ids =μCox [Vgs − (Vds1 + Vds2 ) − Vto1 ]Vds3
L eff1andVds = Vds1 + Vds2 + Vds3 .

(5)

(6)
(7)
(8)

(9)

1
=
Weff μCox

L eff2
L eff1+
Vgs − Vto1
Vgs − Vds1 − Vto
L eff1.
+
Vgs − (Vds1 + Vds2 ) − Vto1

(10)

It is assumed that Vgs − Vto  Vds1 and Vgs − Vto1 Vds1 + Vds2 , then (10) becomes
2L eff1
1
L eff2Rm =+Weff μCox Vgs − Vto1
Vgs − VtoVgs − Vtoρch
L eff2 + 2L eff1
.
(11)
=
Weff
Vgs − Vto1

Comparing (11) with (1) yields

L eff = L eff2 + 2L eff1

Vgs − Vto.
Vgs − Vto1

(12)

If there are positive charges in the sidewall spacers,
Vto1 should shift to the negative. For p-MOSFET case, Vgs
is the negative. Then, Vgs–Vto1 decreases and L eff increases.
The L eff modulation factor is a fractional expression in thesecond term in the right-hand side of (12) and can be
rewritten as
Vgs − Vto
Vgs − Vto
1
=
=
(13)
Vgs − Vto1
Vgs − (Vto + V to1)
1 − V to1
Vgs −Vto

where Vto1 = Vto1–Vto . With the consideration of Vto value(|Vto| ∼ 0.8 V) and measurement conditions (|Vgs| ∼ 1.8 V),
Vgs –Vto can be approximated to be 1, and then (13) becomesVgs − Vto ∼1.
=
Vgs − Vto1
1 − V to1(14)

L eff after the X-ray irradiation with the dose of x is given by
L eff (x) = L eff2 + 2L eff11
1 − V to1(15)

KURACHI et al.: ANALYSIS OF EFFECTIVE GATE LENGTH MODULATION BY X-RAY IRRADIATION FOR FD-SOI pMOSFETs

Fig. 9. Trapped hole densities as a function of X-ray irradiation dose in the
BOX and the sidewall spacer. To calculate the number of the trapped holes
in the sidewall spacer, it is assumed that L eff1 is 0.01 μm and the thicknessof the sidewall spacer is 65 nm.

5the gm degradation by the X-ray irradiation was confirmed.
To investigate the mechanisms of the degradation, the analysis
based on Terada’s method was examined. It is found that thedegradation is due to the effective gate length modulation andthe external parasitic source and drain resistance but not due tothe mobility reduction. The effective gate length modulation iscaused by the generated positive charge in the sidewall spacers,
as concluded from the model of local Vt shift induced at thegate edges. Based on this model, the radiation hardness for
FD-SOI LDD p-MOSFET should be improved by higher LDD
implant dosage such that the gate overlap region of LDD isextended and consequently the gate edge transistors may also
be controlled solely by the gate potential, not by charges inthe sidewall spacers.
R EFERENCES

and that for the preradiation is also given by (5). Then, thevariation of δL by the X-ray radiation, δL, is expressed byδL = (L eff (x) − L drawn ) − (L eff (0) − L drawn )Vto1.
= L eff (x) − L eff (0) = 2L eff1
1 − Vto1

(16)

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When Vto1  1, (17) becomes[1] B. Dierickx et al., “Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers,” IEEE Trans.
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δL = 2L eff1 Vto1.

(17)

If the effective oxide thickness of the sidewall spacer
is Tox_sw , the effective generated charge in the sidewall spacer,Not_sw , isεSiO2
Not_sw =δL(18)
2q L eff1 Tox_sw

where q is the elementary electron charge and εsio2 is thepermittivity of oxide. Assuming L eff1 = 0.01 μm andTox_sw = 65 nm, Not_sw is calculated from measured δL,
as shown in Fig. 9, as a function of the X-ray irradiation
dose. In this figure, the generated positive charges in the BOX
calculated from the back gate Vt shift of n-MOSFETs arealso shown. It is confirmed that both trends for the estimatedgenerated charges in the sidewall spacer and the BOX arealmost the same. Based on these results, it is concluded
that the gate length modulation by the X-ray irradiation in
p-MOSFETs, which is the major cause of degradation, is the
local Vt shift at gate edges due to the generated positive
charge in the sidewall spacers. This effect must be enhanced
when the ON-state bias is used during the X-ray irradiation
instead of the OFF-state bias of this experiment. In addition,
we have confirmed that the higher LDD dosage suppresses thegate length modulation effect and improves the drain current
degradation by the X-ray irradiation. The detailed results will
be presented elsewhere in the future.
IV. C ONCLUSIONThe X-ray irradiation-induced drain current degradationof FD-SOI p-MOSFET has been studied. The drain current
degradation of 20% was observed in the linear region after
the 1.4 kGy(Si) X-ray irradiation for 0.2 μm transistors in thegate length, whereas 8% for 10 μm transistors. No obvious
gate length dependence of Vt shift but clear dependence of6IEEE TRANSACTIONS ON ELECTRON DEVICES[19] K. Terada and H. Muta, “A new method to determine effective MOSFET
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[20] H.-F. Wei, J. E. Chung, and N. K. Annamalai, “Buried-oxide charge
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Takaki Hatsui received the B.S. and M.S. degrees
in chemistry from Kyoto University, Kyoto, Japan,
in 1994 and 1996, respectively, and the Ph.D. degreein science from the Graduate School for Advanced
Studies, Hayama, Japan, in 1999.
He was with the Institute for Molecular Science,
Okazaki, Japan, as an Assistant Professor. He joined
RIKEN SPring-8 Center, RIKEN, Hyogo, Japan, in
2007, and leading the development of X-ray detector
systems.

Kazuhiko Hara received the B.S. and Ph.D. degrees
in science from the University of Tsukuba, Tsukuba,
Japan, in 1980 and 1985, respectively.
He joined the University of Tsukuba in 1989,
where he was an Associate Professor of Particle
Physics. His current research interests include thedevelopment of radiation hard pixel detectors forparticle physics experiments.

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Ikuo Kurachi received the B.S. degree in applied
physics from the Tokyo University of Science,
Tokyo, Japan, in 1983.
He joined OKI Electric Industry Company, Ltd.,Tokyo, in 1983. He joined High Energy Accelerator
Research Organization, Ibaraki, Japan, in 2014, asa Professor. His current research interests include
interface property of Si-SiO2, MOSFET reliability, and process integration technology for memory,
logic, and sensor devices.

Hiroki Kasai received the B.S. degree from Niigata
University, Niigata, Japan, in 2001.
He joined Oki Electric Industry Company, Ltd.,Tokyo, Japan, in 2006. He has been with Lapis Semiconductor Miyagi Company, Ltd., Miyagi, Japan,
since 2011. He is currently involved in the processdevelopment of sensing devices.

Kazuo Kobayashi received the B.E. degree inelectronic engineering from Kobe University, Kobe,
Japan, in 1985.
He joined OKI Electric Industry Company, Ltd.,Tokyo, Japan, in 1985. He joined RIKEN SPring-8
Center, RIKEN, Hyogo, Japan, in 1995, and collaborated to launch SPring-8. He joined the Japan
Synchrotron Radiation Research Institute, Hyogo,
in 2009.
Mr. Kobayashi is a member of the Accelerator
Division.

Masao Okihara (M’12) received the B.S. and
M.S. degrees in physics from Ehime University,
Matsuyama, Japan, in 1988 and 1990, respectively.
He joined OKI Electric Industry Company, Ltd.,Tokyo, Japan, in 1990. He has been with Lapis
Semiconductor Company, Ltd., Yokohama, Japan,
since 2011, where he has been involved in thesensing devices development.

Toshinobu Miyoshi was born in Miyagi, Japan,
in 1973. He received the Ph.D. degree in Sciencefrom Tohoku University, Miyagi, in 2003.
He joined High Energy Accelerator Research
Organization, Ibaraki, Japan, in 2008, where he has
been involved in SOI monolithic pixel sensor.

Yasuo Arai (M’87) received the Ph.D. degree innuclear science from Tohoku University, Sendai,
Japan, in 1982.
He has been with High Energy Accelerator
Research Organization (KEK), Ibaraki, Japan, since1982. He has been involved in the development ofreadout LSI for radiation detector since 1987. He iscurrently a Professor with the Electronics System
Group, KEK.