ISSN 2186-7437

NII Shonan Meeting Report

No. 2012-11

The NII Shonan Configurable Computing
WorkshopPeter Athanas
Brad Hutchings
Kentaro Sano
November 12–15, 2012

National Institute of Informatics
2-1-2 Hitotsubashi, Chiyoda-Ku, Tokyo, Japan

The NII Shonan Conﬁgurable Computing
Workshop
Organizers:
Peter Athanas (Virginia Tech, USA)
Brad Hutchings (Brigham Young University, USA)
Kentaro Sano (Tohoku University, Japan)
November 12–15, 2012

1

Overview of the workshop

Description of the Workshop:
Conﬁgurable computing is an emerging technology proving to be capable of providing high computational performance on a diversity of applications, including 1-D and 2-D signal processing,simulation acceleration, computer graphics, and high-performance computing. High performanceis achieved by rapidly reconﬁguring the functionality and interconnectivity of the computing resources to match the computational requirements of speciﬁc applications. Rapid reconﬁguration
provides the illusion of having a much larger (virtual) hardware platform. With this approach,speciﬁc application properties, such as parallelism, execution proﬁle, and data resolution can be
exploited by creating custom operators, pipelines, and interconnection pathways.
In recent years a rapidly growing interest in using reconﬁgurable computing architectures
for realizing and developing application-speciﬁc computer systems has been observed. The advances in reconﬁgurable technologies, in algorithms for implementation approaches and in automatic mapping methods of algorithms into hardware and processor spaces form a new computing
Computing in Space AND in Time . This
paradigm of computing and programming, e.g.
requires diﬀerent and novel approaches in engineering for developing reconﬁgurable systems andimplementing complex algorithms, including theory, architecture structures, algorithms, design
systems and industrial applications that demonstrate the beneﬁts of this promising way of computing. The fast pace of development is not leaving industry enough time to develop the necessary
theoretical foundation that underpins CAD tools, OS, designs, architectures and circuit technologies. Traditional hardware and software design processes and the tools to support them are notadequate for the design of run time reconﬁgurable systems. Therefore, the plan for this seminaris to focus on the issues relevant to the development of support for run-time reconﬁgurable systems that can be attractive to industry. A special focus will be given to dynamically run-timereconﬁgurable (RTR) solutions, since system adaptation and the advantages of this technology
are highly visible.
Additional topics in this area of research include productivity and observability. Programmable
logic devices continue to nearly double in size with each new generation. Although computational
power used to grow at this same rate, this is no longer true. As such, compilation times for programmable technologies are getting longer, not shorter. Lengthy compilation time is one of themain drawbacks to this technology and it continues to limit its applicability to many problems. It

1

is very diﬃcult to debug complex programs when compile times are measured in hours. Current
devices continue to lack suﬃcient debugging capabilities. Programmers must wait for anotherlengthy compile each time they need to look at a new set of signals. Because of a general lackof observability simulation continues to be the debugging tool of choice even though it is at least
1,000,000 times slower than execution on a programmable chip.
The seminar covers: (1) architectures and techniques that support dynamic reconﬁguration,
productivity and debug, (2) circuit technologies, (3) system architectures, (4) physical CAD tools,(5) tools to aid in the design of RTR systems, domain-speciﬁc systems and related compilers andnew (6) application domains, particularly those that can eﬀectively exploit dynamically reconﬁgurable architectures. We are also interested in (7) novel approaches that enhance productivityand (8) improve observability in ways that aid in debug and veriﬁcation and that hold the promise
to dramatically reduce time-to-market for commercial endeavors. In addition, now that Conﬁgurable System-on-Chip devices are beginning to appear, we are interested in attracting researchthat (9) develops tools and design strategies to exploit the novel aspects of these devices and thatcan continue to reduce overall development time.
For this forum, we invited experts from these various research areas to present their workand opinions. In particular, we encouraged these experts to candidly describe those key research
problems that, until solved, continue to hinder advancement. The outcome of this workshop
should identify key problems along with proposed technical approaches to attack these problems.
We believe that researchers who attended this workshop would be able to not only help solve these
problems but would also help to advertise the importance of these problems to the larger researchcommunity. The seminar that we held was an excellent opportunity to discuss the results fromthe mentioned projects as well as research areas with researchers from Japan, Europe, UnitedStates, Canada, Asia, and Australia.

Interdisciplinary Seminar:
Researchers and practicing engineers alike need to be able to operate in interdisciplinary environments. Not only have boundaries largely disappeared between Computer Science and ElectricalEngineering, for example, but we also see that the boundaries between computing and many otherﬁelds such as computational biology, chemistry, etc., are continuing to soften. Actual surveys in
the EU Project MORPHEUS describe the increased request of the industry for multidisciplinary
skilled engineers. The summary of the feedback can be reported like this: software engineers needto understand new hardware paradigms (reconﬁgurable computing) and hardware engineers needto understand that software deﬁnes the product at the end. Supporting this trend, new workshops like the International Workshop on Reconﬁgurable Computing Education (RC-Education,
http://www.fpl.uni-kl.de/RCeducation08/) and the AETHER - MORPHEUS Workshop - Autumn School (AMWAS, http://www.alari.ch/ AMWAS08/) were established in order to bring
together people from diﬀerent research areas. But there is more activity required to bridge thesegaps. Apart from the example described above, interdisciplinary skills needs to be introduced
also for physicists, chip designers and hardware architecture specialists in order to master thechallenges coming up with future complex electronic systems. This seminar brought together
researchers from industry and academics with an excellent reputation and the required wide baseof disciplines which targets all areas of interest for future reconﬁgurable architectures.

22Overview of Talks

Can Coarse Grained Reconﬁgurable Architecture (CGRA) survive?
Hideharu AMANO, Keio University, Japan
Recently, a lot of projects for CGRA were canceled especially in Japan. CGRAs are competitive with SIMD architectures including GPU. Although current CGRAs are advantageous fromthe viewpoint of energy consumption, the performance is much lower. This talk tries to ﬁnd theway that CGRAs can survive as an acclererator in future SoCs or SiPs.

Disconnection between academic research priorities and industry needs
Neil BERGMANN, University of Queensland, Australia
Most research in conﬁgurable computing fails to make a signiﬁcant impact into the commercial
domain of FPGA-based system design. After more than 20 years of research into dynamic partial
reconﬁguration, there are still no mainstream commercial applications of the technology, at leastthat I am aware of. This is not a reﬂection on the technical quality of DPR research ? some of thebrightest technical researchers have developed sophisticated frameworks which have simpliﬁed thetask of building DPR systems. With such a depth and volume of research, if there was a simple
method for designing such systems, and a killer app that could make use of this method,then I think we would have found them. Large reconﬁguration times and ﬁle sizes, and complex
CAD tools might explain why DPR is not commercially widespread, but it does not seem to beenough to explain why it is non-existent in real products.
Today, one needs to question whether even more eﬀort to make DPR simpler/faster/smarteris providing an answer to a problem that commercially nobody is asking. One can make similar
observations about FPGA-based supercomputing. Despite decades of research on building highly
parallel, general-purpose, stream-based application accelerators, and some impressive speedups,
there does not seem to be widespread use of the technology except by conﬁgurable-computing
researchers, and then mostly the outcome is research papers. The situation is a little better than in
DPR ? There are commercial vendors of FPGA accelerator boards, but the applications (I believe)
tend to be single-use embedded products requiring massive computation (cryptography, softwaredeﬁned radio, radar processing). The best recent attempt to build a general, programmable
FPGA supercomputer (Maxwell, in Edinburgh) has run its course, with only limited use. On
the other hand, FPGAs are becoming ubiquitous in high-end electronic design, and designers
still struggle with adequate tools and frameworks to design, build and test hardware/softwaresystems. To me, this is where there is still substantial, commercially relevant research to be
done. Here s some questions still to be answered to enable mixed hardware/software design tobe easy:1. What are appropriate abstractions for cooperating hardware and software? (processes,
tasks, VMs, instructions, stream-based tasks).
2. What are appropriate interprocess communications methods for hardware/software ? (pipes,
messages, postboxes, shared memory, MPI…) How to automate these interfaces?
3. How to describe HW/SW systems using some generic framework before making partitioning
decisions (C-code, System-C, Petri-nets, state diagrams, …)
4. How to make these frameworks accessible to students and engineers? Tools, boards, textbooks, lecture notes.

3Advancing Reconﬁgurable Computing Requires a System-Level Perspective
Paul CHOW, University of Toronto, Canada
Reconﬁgurable computing technology is struggling to gain acceptance in the broader computing community. The main reason is that the tools used to design applications are not easily
accessible to the application experts that are developing the applications. Researchers have beenworking on tools for about 20 years and the tools are still diﬃcult to use. Why is this the case?
There is a large impedance mismatch at the architecture/hardware and tools boundary. Researchers need to take a system-level approach to the problem. The tools and the architecture
are all parts of the problem and they will be parts of the solution. Completely new approaches
to developing better tools and architectures must be taken.
A good example of the beneﬁts of taking new approaches is the development of RISC Architectures, which has led to the signiﬁcant computing performance we have available today.
What is often forgotten, because of the term RISC, is that the reduced instruction set is not thereason for the performance gains. Instead, dramatic performance gains were made as a resultof a system-level analysis of how the architecture, software, hardware and implementation technologies available interacted and aﬀected performance. The understanding how to leverage thestrengths of each aspect of the system and make the best trade oﬀs across the system has taken
us to the computing performance achievable today.
Current reconﬁgurable computing research is in an architectural rut. We have been trying tobuild reconﬁgurable computing systems on top of a fabric that was designed to represent gatesand interconnect. While this ﬁne-grain technology can be used to build any circuit, it is extremely
low-level and therefore results in the diﬃculties we currently experience: one must be a hardware
designer to use it and the tools take a long time, neither of which is conducive to a computing
environment.
Can we take another approach to discover a more suitable architecture for Reconfigurable
Computing? Might this lead to a new computer architecture? Will it still be called Reconfigurable
Computing? Can we break free of the von Neumann architecture that has brought us to where
we are today, but is now showing its limitations?
The RISC revolution started with the following questions and observations: What are compilers capable of doing and how should the hardware complement that? What can the technology
provide in terms of hardware? Compilers work best when they can generate fundamental operations where the optimizations are straightforward and the data operations can be managed withgood register allocation. Simple instructions can be pipelined and use less gates. Pipelines makeit possible to increase clock frequencies. Less gates leaves more room for caches. Decisions about
features are made by quantitative analysis.
Note that the early FPGA architecture studies and VPR research at the University of Toronto
were motivated by the above strategy.
Can we apply the same strategy for Reconfigurable Computing? What are the appropriatequestions and observations that can set Reconfigurable Computing research down a new andfruitful path? To gather data that can be used to inform our decisions, it would be helpful tohave an “input” language. For RISC processor design, the language was principally C. Or, do
we start with the capabilities of high-level synthesis (HLS) as the starting point, much like westarted with optimizing compilers for RISC architectures? Is HLS mature enough to deﬁne anarchitecture? If so, what does HLS do well, and does that suggest the architecture that will bean eﬃcient target for HLS? Any discussion must include the HLS experts.
The system-level perspective for Reconfigurable Computing is a much larger problem than it
was for RISC Computing. We must ﬁnd a way to make the problem easier to understand and4attack.
There have been very few fundamental leaps in computer architecture. The last was RISC
technology. Making Reconfigurable Computing work will be the next great achievement in computer architecture.

Towards high level design tools
Rene CUMPLIDO, INAOE,Mexico
The design complexity of current digital hardware systems has grown at the same pace as
the scale of integration of modern integrated circuits and the demand of functionality. This
complexity gave rise to diﬀerent design approaches at diﬀerent levels of abstractions, which has
resulted in a large number of methodologies and tools that were designed to exploit speciﬁccharacteristics of available technologies. Current design processes are not straightforward; design
engineers deal with the problem of having to create processing systems using a large variety oftools and methodologies.
Recently, there have been some eﬀorts to develop design methodologies that describe thefunctionality of digital hardware systems using languages and tools similar to the ones employed
to build software systems. The aim is to reduce complexity during the design of digital hardware
systems by means of high level tools that are based on UML-like modeling techniques. It is too
early to say if these methodologies and tools will achieve their goal of standardizing the designof custom processing systems, but as a community we would greatly beneﬁt as it would allow
complete design space exploration in far less time than current approaches.

It’s been said before: Future design methods need AI, and AI could
learn from us
Oliver DIESSEL, University of New South Wales,Australia
A current technology trend sees ever more switches being integrated on-chip. Consequently,
we will see ever-tighter on-chip integration of reconﬁgurable logic, processors, networks and memory. The number of custom design starts will continue to diminish as fewer, more generic, yetcustomizable platforms remain. The devices of the future will be distinguished by the relative
amounts of undiﬀerentiated resources and customized hard IP provided.
To eﬀectively utilize such devices, more eﬀective programming models and CAD tools areneeded. Far from being in a rut, our community faces a decisive challenge to create methodologies
that will allow systems to be engineered from the devices of the future. The solutions will need
to be eﬃcient, powerful, energy aware, ﬂexible, robust, scalable, and cheap. My guess is that wewill need to bring Artiﬁcial Intelligence to bear on solving this problem. And if we do so, we
might help to advance AI.

Using Reconﬁgurable Architecture as a Universal Computing Engine
Tetsuo HIRONAKA, Hiroshima City University, Japan
Using a reconﬁgurable architecture as a universal computing engine is a big challenge. To
reach the goal for these challenge two points must be achieved.
First point is to introduce a good parallel programming model. Reconﬁgurable Computing
will succeed only when unnatural sequential programming s are thrown away and switched to the5natural parallel programming model. To achieve this, we need to push more power in software
engineering for parallel programming.
The second point is to have a good method to evaluate the performance of a reconﬁgurable
architecture. Because a well written parallel program that extracts application’s parallelism
highly, the amount of parallel hardware you have scale up the performance you can achieve. So
just comparing absolute performance is not academic. The performance of the Reconﬁgurable
architecture must be evaluated by the eﬃciency of hardware usage and scalability. However,to evaluate the eﬃciency of hardware, we need a clear method to evaluate the amount of the
hardware used to achieve the performance. Which method is comprehensible enough to be used
for comparing diﬀerence architectures, including non-reconﬁgurable one. When the reconﬁgurable
architecture succeeds to triumph over the eﬃciency of the non-reconﬁgurable ones, it will become
the true next-generation computer.

Perspectives on the use of Hard-CPUs together with FPGAs
Andreas KOCH, Technische Universitat Darmstadt, Germany
In recent years, the use of CPUs integrated with FPGAs has been a topic of interest bothfor academic study and industrial use. After some early commercial devices such as Altera
Excalibur and Xilinx Virtex II Pro, intervening generations have not supported on-chip hard
processors (e.g., Xilinx Virtex 6 and 7, Altera Arria/Cyclone up to IV ). These devices reliedon soft-core processors instead, achieving improved ﬂexibility, but requiring more silicon areaand power due to the use conﬁgurable resources. Only recently have devices with integrated
hard-CPUs appeared again (Xilinx Zynq series, Altera Arria/Cyclone V). In my contribution, I
present three examples for the use of reconﬁgurable devices and examine their impact on the useof FPGA-integrated hard CPUs.
The ﬁrst example is HaLoMote, a wireless sensor node optimized for very low-power operation(possibly supplied by energy harvesting). In contrast to many other approaches employing puresoftware solutions running on ultra-low-power processors such as the TI MSP430, the key application of the HaLoMote is structural health monitoring (SHM) of bridges or other large structures,
where the distributed algorithms require suﬃcient compute capacity even in the nodes. Here, aprocessor such as the MSP430 is simply not able to provide the required peak compute performance. As a solution, we have employed a low-power 8b 8051-compatible processor on the radio
chip to handle just the very simple communication protocol, but provide the compute capacity
by a low-power Actel IGLOO FPGA that supports active power management. It is mostly left ina deep-sleep mode where it requires just microwatts to maintain state, and only awakens when astructure vibration event of suﬃcient magnitude occurs. Then, a non-trivial analysis algorithm isvery quickly executed in dedicated hardware to determine whether the event is suﬃciently important to merit a (energy intensive) radio transmission for further processing. By using dedicatedhardware, the FPGA can very quickly return to sleep again and achieves a signiﬁcantly better
energy balance than waking up a more powerful processor, but which would still be slower than
dedicated hardware (e.g., a low-power TI C55 DSP). It it were possible to have such a low-power
core present on the FPGA chip with separate power management, the energy balance of the system would improve signiﬁcantly, as the external processor actually requires most of the system
power when the radio is quiet and the FPGA is sleeping. An embedded soft-core would not help
us, since the radio protocols need to run continuously (if at a low rate) and would prevent theentire FPGA from powering down (it is not possible to selectively power-down just parts of thedevice).
The second example is an architecture for general-purpose reconﬁgurable embedded computing. Here, a mix between a full-capability operating system (embedded Linux, in our case)6

running on a suﬃciently capable processor, and a larger reconﬁgurable compute capacity is required. Our ACE-M5 architecture achieves this by relying on a Xilinx Virtex 5 FX device. The
embedded PowerPC 440 cores can easily handle all system management tasks. Furthermore,
due to the on-chip nature of both the processor(s) and the reconﬁgurable area, both units canbe integrated tightly for high bandwidth and low-latency signaling. For example, even withfull-scale Linux running, an accelerator computing on the reconﬁgurable area has access to 89%
of the bandwidth to shared memory, and accelerator-to-CPU signaling requires less than 10us.
This allows demanding real-time applications (e.g., robotics and image processing) far exceeding
the capabilities of much more powerful embedded processors. While soft-core processors such as
the Xilinx MicroBlaze CPU could have been used here (energy and area eﬃciency was only asecondary target), they would been signiﬁcantly slower than the 2x super-scalar PowerPC cores.
The ﬁnal example considers a high-performance computing architecture. The Convey HC-1ex
machine combines a quad-core Xeon CPU clocked at 2+ GHz with a reconﬁgurable subsystem
consisting of four large FPGAs and a high-bandwidth (80 GB/s) memory system. Both units
communicate over the Intel Front-Side Bus (FSB) which supports shared cache coherent virtual
memory. For selected bioinformatics applications, it has achieved speedups of 50x over twosocket x86 servers. However, despite the apparent power of the architecture, two limitationsaﬀect its performance in practice: Due to the use of FSB, which has been deprecated by Intel
since 2008, the processor models supported are no longer competitive with current-generation
CPUs (that now use QuickPath Interconnect, QPI), and can thus actually cause slow-downs overother machines that execute software-only, but on current, much faster processors. Second, while
the machine does support transparently shared use of memory attached to the CPU and thereconﬁgurable subsystem, the FSB with its bandwidth of just 8 GB/s and access latencies in thehundreds of nanoseconds actually becomes a bottleneck. Only by carefully copying (aided withhardware support in the machine) data between the two memory systems to the currently active
compute element can this slow-down be avoided.
- From the preceding examples, it should be obvious that the combination of a CPU andreconﬁgurable processing can be very useful, even for wildly diﬀerent application ﬁelds. As shownby the middle example, the tight on-chip integration of reconﬁgurable and software-programmablecomputing allowed eﬃciency gains that were not possible in either of the discrete approaches.
Both in the ﬁrst and third examples, having discrete CPUs and FPGAs led to a loss in eﬃciency.
For the ﬁrst case, the integration of a small low-performance low-power CPU with the FPGA,
supporting ﬁne-grained power management, would have led to higher board density, improved
bandwidth/latency in communications, and better power consumption. For the third case, atighter integration would have avoided the bottlenecks that appear even when linking the twoelements with a relatively high-performance bus such as FSB.
On the ﬂip-side, a tighter integration between CPUs and FPGAs also carries some verypractical problems: As shown above, diﬀerent application ﬁelds also impose wildly diﬀerent
requirements on their CPUs. For handling the wireless network protocols, even the slow 8051 core
was already over-designed. However, in the HPC area, the 2+ GHz quad core could sometimes notkeep up with the performance of the reconﬁgurable subsystem, and consequently led to decreased
speedups. Thus, it is highly desirable to always pick the most suitable CPU / FPGA combination
for the speciﬁc use-case. To actually fabricate and inventory a suﬃcient breadth of FPGA / CPU
combinations will prove quite challenging, however. To some extent, these diﬃculties might be
addressed by fabricating CPUs and FPGAs on separate dies and mixing-and-matching themusing 2.5-D and 3-D stacking technology as required just before packaging.

7

Partial Reconﬁguration is Ready for Takeoﬀ
Dirk KOCH, University of Oslo, Norway
For more than two decades, run-time reconﬁguration of FPGAs was preliminary an academic
niche but there is currently a strong trend that this technology will make its way into commercial products. For example, the 100ms setup time for PCIe can only be reached by usingbootstrapping on large FPGAs. Here, the PCIe related logic will be conﬁgured in a time critical
initial phase followed by the rest of the system in a second partial reconﬁguration phase. Partial
reconﬁguration has also several opportunities for general purpose computing. For instance, likerun-time libraries are commonly used in the software world, partial reconﬁguration can be used
to implement a similar concept in hardware by dynamically linking modules into a system withthe help of partial reconﬁguration.
The trend towards partial run-time reconﬁguration can also be observed inside the FPGAs
themselves, because all recent devices of the two major SRAM-based FPGAs are now fully
supporting partial reconﬁguration - and this holds for both, the high-end and the low cost devices.
The support for partial reconﬁguration has not only improved on the hardware side, also
design tools have signiﬁcantly improved. This includes FPGA vendor tools such as PlanAhead,
which provide basic functionality to implement reconﬁgurable systems, but also academic tools
such as OpenPR or GoAhead. The latter, for example, features module relocation and allows
implementing partial modules completely independent to any other part of the system.
Finally, the progress in silicon industry seams to continue and device capacity will soon exceed an order of magnitude more than what we see today. This will need new technologies which
are strongly related to partial reconﬁguration, such as FPGA virtualization or component-based
design. Here, complex systems will be rapidly composed upon fully physically implemented modules (including place and route), which is basically the static version of partial reconﬁguration.
Today, partial reconﬁguration is not ﬂying, but the mentioned trends is giving it the right thrust.

Foundations of Reconﬁgurable Computing
Wayne LUK, Imperial College,London, United Kingdom
Reconﬁgurable Computing can be regarded as a synergistic combination of two disciplines:
Reconﬁgurable Technology and Custom Computing. Custom Computing provides the abstractions for optimizing computations in space and in time to meet given requirements; Reconﬁgurable
Technology provides the physical means for realizing such abstractions eﬀectively.
While there has been much research in Reconﬁgurable Technology and in application studies
of Custom Computing, the scientiﬁc foundations of these disciplines are perhaps less obvious:
1. What are the guiding principles of Reconﬁgurable Computing that will stand the test of
time? What are the origins of such principles, and how can they be exploited?
2. What are the limits of capabilities of Reconﬁgurable Computing? How would such limits
be addressed, by Reconﬁgurable Technology and by Custom Computing?
3. How would Reconﬁgurable Computing be remembered in ﬁfty years’ time?
There is no doubt that Reconﬁgurable Computing is exciting. Addressing questions like theabove ones would provide insight to the origins of such excitement, which would also help ﬁnding
fundamental solutions to practical issues, such as:8

1. How to make the best use of available devices, systems and tools by improving design
eﬃciency and designer productivity?
2. How to explore novel devices, systems and tools that achieve given requirements in design
eﬃciency and designer productivity?
3. What new theories and algorithms would be needed to support the above?

Functional and constraint programming in combination with machinelearning to increase productivity and performance
Nele MENTENS, Katholieke Universiteit Leuven, Belgium
Electronic Design Automation (EDA) plays a central role in bridging the productivity gap
for designing complex electronic systems. Most existing tools generate hardware and embedded
software that satisfy the required functional speciﬁcations. However, for many applications,
it is also important that non-functional requirements are met, such as performance, resource
utilization and power consumption, either in a strict way (e.g. a maximum surface is given) or ina tradeoﬀ manner (e.g. low power consumption is more important than high performance). The
concept is generic, but to obtain a competitive solution, application-speciﬁc low-level components
are needed.
We propose to use functional programming to provide high-level descriptions of the components in the application-speciﬁc libraries and to easily integrate the generation of hardware andsoftware and the use of back-end synthesis and compilation tools. Further, we propose to use
constraint programming to take into account the non-functional requirements. In order to explore the design space in a smart manner, search algorithms and machine learning are applied tonarrow down the useful part of the design space early in the generation process.

Can FPGAs and/or reconﬁgurable devices be a common platform forhigh-performance computing?
Kentaro SANO, Tohoku University, JapanFPGAs/Reconﬁgurable devices can be common platform of high-performance computing but
they have to satisfy the three conditions related to device, applications, and programming, respectively. In general, device inﬂuences sustained performance (P), power consumption (W), cost
(C). Super-computing prefers devices for better P, P/W, and P/C. Looking at present devices,
FPGAs can achieve comparable P or better P/W in comparison with those of such accelerators
as GPUs and Intel MICs, while they depend on applications. On the other hand, the accelerators
provide much better P/C than FPGAs. However, the end of technology scaling and the darksilicon problem can be a tailwind for FPGAs.
Applications give operation (ﬂoating-point, ﬁxed-point, integer, logical one), parallelism (spatial/coarse or temporal/ﬁne), and performance characteristic (memory-bound or compute-bound)for computation. Today’s super-computing mainly demands computation with ﬂoating-point
operations, spatial/coarse parallelism, and memory-bound performance, and therefore present
processors and accelerators are designed for them except memory-bound performance. For suchcomputation, FPGAs also have comparable sustained performance, while they are not drastically
good. However, ﬂexible FPGAs are much better at non ﬂoating-point, temporal/ﬁne-parallel andmemory-bound performance than processors and accelerators. Some super-computing applications have such characteristics. Further advancement of FPGAs could give them more advantages
for computing.
9The biggest problem is an interface of programming for FPGAs to become a platform of supercomputing. In standard super-computing, users directly write and change a code for computation,
which is written in traditional languages (C or FORTRAN). Recently their extension (OpenMP,
OpenCL, MPI) is also necessary for super-computing. Since these languages and extensions
are common interfaces of super-computing, FPGAs also have to ﬁt them. Recently, FPGAs
already made a success for embedded super-computing as Maxeler’s story shows, where users do
not program codes, but just use softwares that are already programmed. For standard supercomputing on FPGAs, we need seamless tool-chain or compiler for traditional languages, andacceptable compilation time in addition to eﬃciency bringing suﬃcient performance to FPGAs.
To meet these conditions, I think that the key is abstraction layer which lies between reconﬁgurable devices (FPGAs) and software. We should deﬁne programmable hardware layer, which
can be based on application-domain architectures, such as architectures for each of OpenCL,
OpenACC, OpenMP, MPI, etc. Open question is: How eﬃcient is this approach for exploiting
the performance? and How we eﬃciently provide compilers to these architectures?

Programmable Architecture for Pattern Matching
Tsutomu SASAO, Kyushu Institute of Technology, Japan
Sasao invented a new architecture for pattern matching, that works great for limited applications. Some of results were presented at ICCAD 2008, DATE2012, ASPDAC2012, ARC2012,
and the book ”Memory-Based Logic Synthesis,” Springer 2011. Applications to IPV6 router will
be presented at ARC2013. Sasao is now improving the optimization algorithm.
Questions and answers are as follows: Q) Do we need fundamentally new architecture? A)
Yes. We need it. To continue to progress, to write papers, and to get research grant, we needfundamentally new architecture.

Bringing Reconﬁgurable Computing to the Mainstream
Hayden SO, University of Hong Kong, China
Despite years of demonstrated success in accelerating application across many demanding
domains, reconﬁgurable computing remains a niche that has limited reception in the mainstream
computing arena. There are two areas that deserve particular attention from the community inorder to bring reconﬁgurable computing to the mainstream: (1) improving design productivityand (2) integrate with the mainstream computer architecture.
Design productivity is a diﬃcult to deﬁne quantity. It can generally be thought as the timerequired to complete a design-test-debug iteration for application development. The shorter timeeach step takes, the more iteration may be completed per day, and the more likely that a deliverable design can be developed faster. To that end, the conventional software development
methodology is well-established after decades of evolution. Today, compilation of even the mostcomplex software application is swift; the runtime operating system is well designed, and there
are plenty of debugging tools and methodology for testing the resulting system. On the other
hand, there remains very little established industrial standard on application development forreconﬁgurable computers. Most system relies on low-level hardware design methodology thatwas originally designed for VLSI designs. Also, compiling such designs may take hours to days,
limiting the number of compile-debug cycle to close to one per day. Then, operating system
support for non-conventional computation model remains limited. Finally, debugging tools forreconﬁgurable computers are generally lacking. Without a high-productivity design methodology, it is diﬃcult to attract novel users to appreciate the beneﬁts of reconﬁgurable computers.
10Application designers who demand the highest performance may instead turn to other forms ofcompute accelerators, such as the use of GPU for the better development environment.
Apart from improving design productivity, it is also important to integrate reconﬁgurable
computers to the mainstream computer architecture. Most research projects on reconﬁgurable
computers, while achieving superior performance under a lab environment, rely on non-compatible
interfaces and techniques that are diﬃcult to apply to other scenarios. As such, the results fromone research group can rarely be reused in another setting, forcing many researchers to “reinvent the wheel” over and over. In order for reconﬁgurable computers to become mainstream,more eﬀorts must be devoted to integrating such non-conventional computer model with themainstream computer architecture. Finally, for sake of standardization and improving backward
compatibility, it is imperative for the industry and the academia to pay more attention to developing abstraction layers for reconﬁgurable computers, similar to the ISA layer of standard
computers.

Requirement of a standard programming model for reconﬁgurable processors
Kazuya TANIGAWA, Hiroshima City University, JapanA standard programming model for CPUs has been developed, and hence, any high-level
language and CPU conﬁguration can be chosen. For example, a program written in a high-level
language is executable on various CPUs. Moreover, various high-level languages are available
for developing a program that is executable on a target CPU. To develop such an environment,
CPUs and high-level languages need to be developed based on a standard programming model.
However, there is no standard programming model for Field Programmable Gate Arrays(FPGAs) or reconﬁgurable processors, and hence, in many cases, it is diﬃcult to port a program
written for a reconﬁgurable processor to other reconﬁgurable processors (here, a program constitutes circuit information executable on a target reconﬁgurable processor). Modifying a program
according to the target reconﬁgurable processor and high-level language is problematic.
Therefore, in my opinion, a standard programming model for reconﬁgurable processors is
required for the widespread use of such processors.

Creating Heterogeneous Design Tools; the missing link
John WATSON, Data IO Corporation, USA
Our goal should be that all hardware architectures are adaptable to match their applications;ﬁrst at the application level, then at the applet/subroutine level, and then at the algorithm level.
In moving down each of these, the reconﬁguration times get smaller and happen more often, untilin the end, the hardware is constantly being adapted ”in real time” with the software program
becoming more of a hardware scheduler as ”software processes” are called into action. Thesetypes of ideas have not caught on for two reasons, a) the lack of industrial understanding of data
ﬂow/data driven parallel processing eﬃciency and b) Moore’s law, whose historic price drops
have masked the need for eﬃciency. Since low cost is the market driver for technology, as longas Moore’s Law could schedule cost decreases no one looked for a better solution; resulting in
our current architectural and processing rut. Hence, our industry traded low cost and software”ease of use” for everything else. The focus became the short term solution and not necessarily
the right solution. We must get back on the right track and that won’t happen via Wall Street,
Venture Capitalists or Silicon Valley.
I feel two things are needed:111. Universities, community colleges and high schools that teach HW and SW eﬃciency.
Students need to realize that parallel is the natural way of everyday life, and that serial
processor structures are artiﬁcial, unnatural and the old way of thinking. All of the emerging ﬁelds; big data, cloud computing, informatics, biotech, robotics, autonomous vehicles,
mobile, etc. are worlds in which parallel is the dominant theme?
2. A Moore’s Law equivalent for FPGA/RC design productivity tools.
FPGAs ICs are ”designed” while processor ICs are ”programmed”. The line between design and program needs to be removed; the line between ”IP” and ”applications”, between”PAR” and ”compiler”, ”timing closure” and ”cycle count”, ”design veriﬁcation” and ”application testing,” etc. Furthermore, FPGA/RC/heterogeneous design tools must scale
across all applications and IC architectures, work across time and space, compile quickly
and provide a quantum leap in design reuse. A fab process shrink and the next larger wafer
size work across all CMOS chips. Where is the design tool equivalent? We should discuss
how to do this.
The battle to eradicate Fortran and Cobol as dominant languages took a decade. But themove from those old languages enabled the ﬁrst minicomputers, then PCs and then the mobile
market. Without moving away from those languages none of this would have been possible.

123Discussion on a Grand Challenge Vision for Computing

The objective of this discussion was to determine if there was a foundation for establishing acommunity-wide vision for conﬁgurable computing. The participants structured the discussion
progressing from the basic understanding of contemporary issues to a plan for future action.
The ﬁrst topic was an assessment on the current state of the computing world. The participants noted that there are many disparate uses for computing, many diﬀerent architectures, andmany scales of operation such as:
1. multi-core embedded processors
2. sensor networks
3. mobile computing
4. desktop computing
5. cloud computing
6. high performance computing
7. Internet infrastructure
From this point, the participants discussed what are the common links, and the distinguishinglinks. These were identiﬁed as follows:
1. all do computing
2. parallel computing
3. heading towards heterogeneous computing elements, if not already
4. power/energy issues
5. communications issues
6. data
7. memory
8. I/O
The issue examined was that the broad spectrum of computing systems all look the same at thislevel, yet each community has it’s own approach to solving problems. There are ineﬃciencies aseach struggles with similar problems independently.
The participants then examined the computing fundamentals as a basis for ﬁnding common
threads between the communities:
1. control
2. dataﬂow
3. computation
4. inter-{process, thread, processor, node} communication
5. I/OAll of these use the realm of “scale” diﬀerently. For example, solutions at a smaller scale may betotally irrelevant to those working at a much broader, higher scale. This is something that wemust all deal with.
The participants then discussed where this technology is taking us. There are many notableadvances that need consideration. In the long run, one must consider the possibilities well beyond
CMOS when the possibility of molecular/nano computing is realized. The discussion centered on
if the fundamentals of computing concepts would change.
The session concluded with a discussion on what is needed for the community. This was alengthy discussion that focused on the following topics:13

1. a common (unifying?) architecture model
2. build DSL’s on top of this
3. tools that take the application as an input constraint
4. optimize inter-{process,thread,processor,node} communication according to whether it is asensor network or a million-node HPC system
5. optimize power use accordingly
6. provide scalability and portability through the spectrum of targets
7. common design ﬂow and debugging framework
8. must account for heterogeneity
The participants then concluded with a plan to create a roadmap document with the supportof the conﬁgurable computing community as a whole.

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