24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage
Domains in VDDmin Limited Ultra Low Voltage Logic Circuits
Tadashi Yasufuku1, Koji Hirairi2, Yu Pu1, Yun Fei Zheng1, Ryo Takahashi1, Masato Sasaki1, Hiroshi Fuketa1,
Atsushi Muramatsu2, Masahiro Nomura2, Hirofumi Shinohara2, Makoto Takamiya1, Takayasu Sakurai1
1

2

University of Tokyo, Japan
Semiconductor Technology Academic Research Center (STARC), Japan
tdsh@iis.u-tokyo.ac.jp

Abstract
A post-fabrication dual supply voltage (VDD) control(PDVC) of multiple voltage domains is proposed for aminimum operating voltage (VDDmin)-limited ultra low voltage
logic circuits. PDVC effectively reduces an average VDD
below VDDmin, thereby reducing the power consumption oflogic circuits. PDVC is applied to a DES CODEC’s circuit
fabricated in 65nm CMOS. The layout of DES CODEC’s isdivided into 64 VDD domains and each domain size is 54m x
63.2m. High VDD (VDDH) or low VDD (VDDL) is applied toeach domain and the selection of VDD’s is performed based on
multiple built-in self tests. VDDH is selected in VDDmin-criticaldomains, while VDDL is selected in VDDmin-non-criticaldomains. A maximum 24% power reduction was measured
with the proposed PDVC at 300kHz, VDDH =437mV, and
VDDL=397mV.

to exceed the VDDmin limit is required. Reducing VDDmin at adesign phase, however, is difficult because VDDmin is mainly
determined by random variations of the threshold voltage oftransistors [5]. Furthermore, only one functional error of F/F orlogic gates increases VDDmin of a whole logic circuit. Therefore,
in order to reduce VDDmin, VDD must be controlled with multiple
domains. The conventional fine-grained VDD control at designphase [6] cannot solve the VDDmin problem, because the positionof the logic gate with the highest (=worst) VDDmin is random.
Thus, to achieve low power logic circuits with ultra low VDD, apost-fabrication dual supply voltage control (PDVC) for finegrained VDD domains is proposed in this paper. PDVC reduces
the power consumption of logic circuits effectively by reducing
VDD below VDDmin.

11-stage

101-stage

Keywords
Low voltage logic circuit, low power, dual supply voltage,fine-grain power supply voltage

10001-stage

Out(10001)

InOut(11) Out(101) Out(1001)(a)

1. Introductionn = 16, 64, 256, 1024, 4096

586

D Q

In

D Q

D Q

D Q

D Q

Out(n)

Clk1
Clk2

(b)

Fig. 1. Schematic diagram of chain circuits to measure VDDmin
fabricated in 65nm CMOS. (a) 2-input NAND chain. (b) F/F chain.
400

Measured
65nm CMOS

350
300
VDDmin [mV]

Reduction of the power supply voltage (VDD) is an effective
method for achieving ultra low power logic circuits since theactive power and the leakage power depend on VDD. Thus,
many works have been carried out on the low VDD operation oflogic circuits [1-2]. The VDD scaling is, however, limited by
the minimum operating voltage (VDDmin) of CMOS logic gates.
VDDmin is a minimum power supply voltage when the circuits
operate without function errors [3-4]. The dependence ofVDDmin of flip-flop (F/F), NAND, and NOR gates on thenumber of logic gates is investigated. Fig. 1 (a) shows aschematic diagram of a 2-input NAND chain for the VDDminmeasurement. The NAND chain has outputs from the 11thstage to the 10001th stage. Fig. 1 (b) is a schematic diagram of
a F/F chain. VDDmin is defined as VDD where the output of F/F is
stopped. Fig. 2 shows the measured dependence of VDDmin of
F/F, NAND, and NOR gates on the number of stages in 65nm
CMOS. Measurement of VDDmin is conducted with slow clock(1kHz). VDDmin increases as the number of stages increases.
VDDmin of F/F is much higher than that of NAND and NORgates. For example, VDDmin of F/F is 378mV at 4096 stages.
This result indicates that VDD scaling below 400mV in large
scale processors with 10M to 100M logic gates is difficult,because VDDmin of 10M to 100M logic gates is above 400mV.
In order to achieve ultra low VDD logic circuits, a new solution
978-1-4673-1036-9/12/$31.00 ©2012 IEEE

1001-stage

378mV@4096 stages

F/F

250
200

NAND

150
100
NOR

50
0

1

10

100

Number of stages

1k

10k

Fig. 2. Measured dependence of VDDmin on number of stages in
F/F, NAND and NOR.

13th Int'l Symposium on Quality Electronic Design

Section II shows test circuits divided into 64 VDD domains
for PDVC. Area penalty of PDVC is also discussed. Section III
presents experimental results. The power reduction by reducing
VDD below VDDmin with the proposed PDVC is also discussed.
Section IV concludes this paper.

Dual

SupplyFig. 3 illustrates a difference between a conventional dual
VDD control and PDVC. In the conventional dual VDD control,
VDD is common within a functional block and is independently
controlled in each block. In addition, level shifters are inserted
between functional blocks with different VDD’s. In contrast, inthe proposed PDVC, the layout of the whole logic circuit isdivided into many domains regardless of the functional blocks.
Although the layout of PDVC has connections between
different voltage domains, level shifters are not inserted,because the leakage current between different VDD domains is
negligible when the difference of VDD1 and VDD2 is small. In
the conventional dual VDD control, VDD of large functional
No Level shifter

Functional
block 1

Functional
block 2VDD1VDD2Functional
block 2Functional
block 1

Functional
block 3

Levelshifter

Functional block 3

Conventional

Proposed PDVC

Fig. 3. Comparison between conventional and proposed dual VDD
control.
VDDH

VDDL

Clk
64
Select_VDD

LinearFeedback 64
Shift
RegisterPreset key

VDDH > VDDL

DES
CODEC

64

(Encode)DES
CODEC(Decode)Multiple
64 Input
Signature
Register

64
Out

56
Logic circuit
divided into 64 VDD domains

516m

(a)

Layout of Logic circuitwith 64 VDD domains
2

3

4

5

6

7

Power switch row

VDDH
8
VDDL

9 10

Logic
circuit516m

1

VDDH > VDDLPower switch row

Select_VDD

n63.2mDomainn
960m

Statistics of gate counts

61 62 63 64

DES
CODEC’s

All gates

110,045

Flip-flop

4123

(b)

Fig. 4. (a) Block diagram of test circuit divided into 64 VDD
domains. (b) Schematic of layout of logic circuit with 64 VDD
domains and schematic diagram of domain n.

1260mFig. 5. Die micrograph and and layout of the DES CODEC’s
fabricated in 65-nm CMOS.

54m

Logic circuit

Logic circuit

Fig. 4 (a) shows a block diagram of the fabricated logic
circuit to demonstrate the proposed PDVC. The core circuits
are series-connected 64-bit data encryption standard codec’s(DES CODEC’s). These DES CODEC’s execute an encryption
and a decryption based on the preset key. The inputs of DES
CODEC’s are generated by a 64-bit linear feedback shift
register, and the outputs are compressed by a 64-bit multiple
input signature register (MISR). The outputs of MISR are readusing a scan chain and the result is compared to expectation
vectors. The logic circuit in Fig. 4 (a) is divided into 64 VDD
domains without relations to its function as shown in Fig. 3.
Fig. 4 (b) shows a schematic of a layout of the logic circuitwith 64 VDD domains. A schematic diagram of domain n is also
shown. The circuit is divided into 8 x 8 domains and eachdomain size is the same. Each domain has 2 power switches toselect high VDD (VDDH) or low VDD (VDDL). The power switches
are domain-by-domain controlled by Select_VDD signal from atester. Fig. 5 shows a die micrograph and a layout of thefabricated logic circuit (DES CODEC’s) in 65-nm CMOS. The
layout with 64 VDD domains was designed using a commercial
auto P&R tool. The die size is 960m x 1260m. The core areaof DES CODEC’s with 64 VDD domains is 516m x 516m.
Each domain size is 54m x 63.2m including 2 powerswitches. The domain size is smaller than that of [7] (100m x
100m). The area overhead of the 2 power switches is 7%.
Compared with a conventional single VDD design with a powerswitch for the power gating, however, the area overhead due toan additional power switch in PDVC is 3.5%. The area

50.4m

2. Proposed Post-Fabrication
Voltage Control (PDVC)

blocks cannot be reduced, because the probability of theexistence of F/F’s with high VDDmin within the functional blockincreases. On the other hand, VDD is reduced below VDDmin by
the proposed PDVC, because VDD of domains which does notinclude bad F/F’s (namely F/F’s with high VDDmin) is reduced.
[7] also shows a within-functional-block fine-grained adaptive
dual VDD control. In [7], VDD is controlled by the setup error
prediction signals generated by canary F/F’s. The VDD control
in [7], however, cannot reduce average VDD below VDDmin,
because the canary F/F’s also have function errors due to its
VDDmin. Therefore, the proposed PDVC is required in VDDminlimited ultra low voltage logic circuits.

3. Experimental Results

1G

Fail

500M
300M
100M
50M

Pass

30M
10M
Fails at any frequencies
below 400mV

5M
3M
1M
500k
0.4

0.5

0.6

0.7

0.8

0.9

1.0

Fig. 6. Shmoo plot of fabricated DES CODEC’s.
Table I. Measured VDDmin of 10 diesDie #VDDmin [mV]

1

399

2

404

3

424

4

424

5

426

6

430

7

431

8

433
435

10

437

High

9

(i) Assign all domains to VDDH, i = 0(v) While i < nFailed domain list
8

10 56

8

21

(ii-a) Calculate number (= a x ci) of
domains to be selected.

(ii-b) Calculate transition probability of eachdomains from failed domain list with w.

(ii-c) Randomly select domains except VDDL domains
based on transition probability and change theselected domains from VDDH to VDDL.
(iii) Run built-in test

Domain1

Transition
probability
ratio

1

Latest k domains
0 8
9
10
w2

1

w

VDDL domains are
not selected

HH L

HL H

HL L

L L H
64

(iv)
Passed?

FailPassAdopt newset of VDD(v) i++

Discard changes
Add failed domains
to failed domain list

1.1

VDD [V]

Low

Fig. 6 shows measured shmoo plot of the fabricated DES
CODEC’s from 0.4V to 1.2V. In this measurement, single VDD
is provided to all 64 domains. Maximum operating frequencyof the circuit is 630MHz at 1.2V. The maximum operating
frequency decreases as VDD is reduced. VDDmin of the DES
CODEC’s is 450mV, because the DES CODEC’s has function
errors below 400mV at any clock frequencies. In this paper, theclock frequency for the VDDmin measurement is fixed to 300kHz.
Table I summarizes measured VDDmin of 10 dies in ascendingorder. Minimum and maximum VDDmin in 10 dies are 399mV
and 437mV, respectively. Although VDDmin varies between die
to die, it is difficult to measure VDDmin of all fabricated dies interms of a test cost. The highest (=worst) VDDmin, however, canbe calculated [5]. Thus, VDDH is fixed to VDDmin of the worst die(437mV, in this case).
Fig. 7 shows a flow chart of an algorithm used for PDVC.
VDDH is selected in VDDmin-critical domains, while VDDL isselected in VDDmin-non-critical domains. A post-fabrication dieto-die dual VDD selection is inevitable, because the domains
where VDDmin is high are determined by random transistor
variations and the selection of VDDH or VDDL in each domain isdifferent between dies. In order to minimize the power of the
DES CODEC’s, the number of VDDL domains should be

Maximum frequency:
630MHz @ 1.2V

VDDminClock frequency [Hz]overhead due to the separation between 64 VDD domains is
negligible. The fabricated logic circuit (DES CODEC’s)
includes 110,045 gates and 4,123 F/F’s. As shown in Fig. 2,
VDDmin of this circuit is determined by F/F’s instead of
combinational circuits and will be around 400mV, because
VDDmin of F/F’s with 4096 stages is 378mV.

n : Max number of iterations
i : Current iteration countc : Constant (c < 1)
w : Weighting coefficient (w < 1)
k : Number of domains used from failed domain lista : Initial number

1.2

Explanation of the algorithm is shown in (i)-(v), where n(=100) is the maximum number of iterations, i is a current
iteration count, c (<1) is a constant, w (<1) is a weighting
coefficient, k is the number of domains used from a failed
domain list, and a is an initial number (>1).

Power reduction ratio [%]0
VDDH=437mV
VDDL=397mV
1 Die

-5
-10

(i) VDD of all domains are assigned to VDDH. The voltage of
VDDH is determined by the highest (=worst) VDDmin acrossdies. Next, the voltage of VDDL is determined. Optimal VDDL
in this algorithm will be discussed in Fig. 9.

-1510 trials

Average of 10 trials

-20
-25
-30

0

20

40

60

80

100

Iteration
Fig. 8. Measured dependence of power reduction ratio on
iteration counts in one die.

Power reduction ratio [%]0

VDDH=437mV
1 trial per die
After 100 iterations
10 dies

-5
-10

-20

(c) Domains are randomly selected by the transition
probability ratio calculated in (b). The selected VDDH
domains are changed to VDDL domains.

-25
Average of 10 dies

10

20

30

40

VDDH - VDDL [mV]

50

60

70

VDDH domains / All domains [%]50
VDDH=437mV
1 trial per die
After 100 iterations
10 dies(v) Increment i. While i < n, return to (ii).
Please note that a measurement of the power consumption
is not required in this algorithm. This is important because thisalgorithm has a potential to be embedded in the circuits.

30
20
10
0

0

10

20

30

(iii) Built-in self test is executed.
(iv) When the test is passed, adopt new set of VDD. Whenthe test is failed, discard changes and add failed domains to
the failed domain list.

(a)

40

(a) The number of domains to be selected is calculated.
Only VDDH domains are selected in this step (ii). The
number is aci. When iteration count is small, larger
number of domains is selected to reduce power
consumption rapidly. In contrast, when iteration count islarge, 1 domain is changed to approach optimal solution.
(b) Transition probability of each domain is calculated
based on a failed domain list and w. Latest k domains are
selected from the failed domain list. The failed domain list
saves past failed domains in the built-in self test. The pastfailed domains have a high possibility of including logic
gates with high VDDmin.

-15

-30
0

(ii) Domains with VDDH are selected and changed to VDDL
domain, and built-in test is executed. Prior VDDL domains are
not selected, because F/F’s with high VDDmin are not includedin the domain.

40

50

60

70

VDDH - VDDL [mV](b)
Fig. 9. (a) Measured dependence of power reduction ratio on
VDDH – VDDL. (b) Dependence of percentage of VDDH domains on
VDDH - VDDL.

maximized, because both the dynamic and leakage power of adomain is reduced by changing from VDDH to VDDL. Thus, analgorithm to efficiently find out VDDL (<VDDmin of each die)domains is required to shorten testing time.

Fig. 8 shows the measured dependence of power reduction
ratio on the number of iterations. 10 trials are executed for 1 die.
These 10 lines take different routes, because the algorithm
randomly selects domains. Power reduction of a chip is definedas average of 10 trials. In this case, the power reduction ratio
after 100 iterations is 24%. In order to determine an optimal
VDDL, Fig. 9 (a) shows the measured dependence of power
reduction ratio on the voltage difference between VDDH and
VDDL after 100 iterations in 10 dies. When VDDH - VDDL is
40mV or 50mV, the power reduction ratio is maximized. In thispaper, VDDH - VDDL of 40mV is used, because the average
power reduction ratio denoted by the dotted line in Fig 9 (a) is
minimized at 40mV. Fig. 9 (b) shows the measured dependenceof the percentage of VDDH domains on VDDH - VDDL. With
increasing VDDH - VDDL, the percentage of VDDH domains
increases, while the power consumption of VDDL domains
decreases. This is the reason why the power reduction ratio ismaximized at VDDH - VDDL of 40mV in Fig. 9 (a).

Power reduction ratio [%]0

VDDH=437mV
VDDL=397mV
10 dies-56.7%~17%
reduction@10 iterations-10

Average of 10 trials
per die

14%~24%
reduction@30 iterations

-15

1

2

3

4

5

6

7

8

9

Probabilityof VDDH in 10 dies
0
0%

0.2
20%
0.4
40%
0.6
60%
0.8
80%
100%

20%~24%
reduction@100 iterations

-20
-25

0

10

20

30

40

60

Iteration

80

62 63 64

100

Fig. 12. Averaged probability map of VDDH in 10 diesFig. 10. Measured dependence of average power reduction ratio
on iteration counts in 10 dies.

Fig. 10 shows the measured dependence of the power
reduction ratio on the number of iterations in 10 dies. Each line
denotes average of 10 trials in each die. VDDH is 437mV and
VDDL is 397mV. The power is reduced by 6.7% to 17% at 10
iterations, 14% to 24% at 30 iterations, and 20% to 24% at 100
iterations. As the number of iterations increase, the power
reduction ratio also increases. When the test cost of the 100
iterations is not acceptable, the 10 iterations or the 30 iterations
will be a reasonable choice.
In order to investigate the distribution of VDDH and VDDL in
64 VDD domains and to check the stability of the convergenceof the proposed algorithm in Fig. 7, Fig. 11 shows themeasured maps of the probability of VDDH in 64 VDD domains
for 10 dies. 10 trials are performed to measure the probabilityof VDDH per die. In 64 VDD domains of each die, the probabilityof VDDH is nearly 0% or 100%, which indicates that the
proposed algorithm is stable. The maps for 10 dies have nostrong correlations. In order to check the random andsystematic components in the distribution of VDDH and VDDL in
64 VDD domains, Fig. 12 shows the average of 10 maps in Fig.
11. The probability of VDDH across 10 dies is less than 40%,
which indicates that the position of F/F’s with high VDDmin is

Die 1
1 2 3 4 5 6 7 8
9

Die 2

Die 3

Table. II. Summary of key features.
Technology

65nm CMOS

Clock frequency for VDDmin 300kHz
Core area

516m x 516m

Average power
Before PDVC

18.4W

After PDVC

14.3W

Power reduction by PDVC

6.7% ~ 17%@10 iterations
14% ~ 24% @30 iterations
20% ~ 24% @100 iterations

almost random and the die-to-die PDVC is required to achieve
the low power logic circuits with ultra low VDD.
Table 2 summarizes the key features of the fabricated DES
CODEC’s. Power reduction up to 24% is achieved by the
proposed PDVC.

4. Conclusion
A post-fabrication dual supply voltage control (PDVC) of
multiple voltage domains is proposed for a VDDmin-limited ultra
low voltage logic circuits. PDVC effectively reduces an

Die 4

Die 5

62 63 64

Die 6

Die 7

Die 8

Die 9

Fig. 11. Probability map of VDDH of 10 dies in 10 trials

Die 10

Probabilityof VDDH
in 10 trials
0
0%
0.2
20%
0.4
40%
0.6
60%
0.8
80%
100%

average VDD below VDDmin, thereby reducing the power
consumption of logic circuits. PDVC is applied to the DES
CODEC’s circuit fabricated in 65nm CMOS. The layout of the
DES CODEC’s is divided into 64 VDD domains and eachdomain size is 54m x 63.2m. The area penalty of PDVC is3.5%. A maximum 24% power reduction at 30 iterations wasmeasured with the proposed PDVC at 300kHz, VDDH =437mV,and VDDL=397mV.

References

Acknowledgment[3]

This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial
Technology
Development
Organization(NEDO).

[1]

[2]

[4]

[5]

[6]

[7]

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