4-1

A 0.6-V Input 94% Peak Efficiency CCM/DCM
Digital Buck Converter in 40-nm CMOS with
Dual-Mode-Body-Biased Zero-Crossing Detector
Xin Zhang1*, Yasuyuki Okuma2, Po-Hung Chen1, Koichi Ishida1, Yoshikatsu Ryu2, Kazumori Watanabe2,Takayasu Sakurai1, and Makoto Takamiya1
1

University of Tokyo, Tokyo, Japan
Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan*
now with Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Singapore
2

Abstract—A 0.6-V input, 0.3-0.55V output buck converter isdeveloped in 40-nm CMOS, for low-voltage low-power wirelesssensor network systems. The buck converter is able toautomatically select DCM or CCM operation, therefore
improving the power efficiency and enlarging the output current
range, by virtue of the proposed low-power CCM/DCM
controller. A dual-mode-body-biased (DMBB) (forward bodybias & zero body bias) low-voltage zero-crossing detector isdesigned to enable DCM operation with both low supply voltage
and normal supply voltage. The proposed buck converter
achieves a peak efficiency of 94% with an output current rangeof 50μA to 10mA. Thanks to the DCM operation, the efficiency
at an output current of 100μA is improved by 20% and 9%,with an output voltage of 0.35V and 0.5V, respectively.

I. INTRODUCTION
With the widely use of near/sub-threshold digital circuits
in low-power systems like wireless sensor nodes and biomedical applications [1-2], there is a strong demand of voltage
converters which can regulate the power supply voltage atfrom 0.3V to 0.55V, with the output current of from 50μA to10mA. On the other hand, such low-power systems often
prefer a self-powered energy source, i.e., solar cells, than abattery, to avoid the trouble of frequent battery replacing. Fora typical single solar cell, the max power point is around 0.6V
as its output voltage. Therefore, a low-voltage high efficiency
step-down voltage converter which generates a 0.3V to 0.55V
output voltage (VOUT) from a 0.6V input voltage (VIN) is ofgreat importance to such low-power systems.
Low-dropout regulators (LDOs) are commonly used as astep-down voltage converter. However, due to the fact that theefficiency of LDO is limited by the ratio of VOUT over VIN,
there is considerable loss when adaptive power supply voltage(VDD) control is applied to the digital load [2-3].
The buck converter can have two modes of operation:
continuous conduction mode (CCM) and discontinuousconduction mode (DCM). In CCM, the inductor current isalways positive, while in DCM, the inductor current issometimes down to zero. This characteristic makes DCM ac
978-1-4799-0280-4/13/$31.00 2013
IEEEmore suitable mode of operation for a light load situation.
CCM operation at light load situation is undesirable, because
the reverse inductor current introduces additional losses.
Therefore, a buck converter with CCM for the heavy load
situation and DCM for the light load situation is strongly
required to achieve the high power efficiency across a wide
output current range.
Conventional buck converter either requires an external
control signal to switch between CCM and DCM [4], or uses acomplex synchronous logic circuit to realize CCM/DCM
selection [5]. The drawback of [4] is obvious that it relies on
external signal to switch modes. The drawback of [5] is thatthe complex logic circuit would increase the total gate number
and therefore increase the power consumption. So it is notsuitable for the light load situation. Moreover, in the lowvoltage synchronous logic circuit design, setup and hold errors
should be carefully avoided [6].
Ref. [7] is a low-voltage buck converter, but it has fixed
VIN due to delay chain based pulse width modulation (PWM),and it uses a large inductor (47mH) to accommodate lowinductor current, because it has only CCM operation. In thispaper, a low-voltage buck converter is presented with a newautomatic CCM/DCM controller. The CCM/DCM controller
composes of a simple combination logic circuit, thus it ispower efficient and suitable for low-voltage design. A dualmode-body-biased (DMBB) zero-crossing detector is also
proposed to enable low-voltage DCM operation.
This paper is organized as follows. The top-levelarchitecture and the operation sequences of the proposed buckconverter are described in Section II. Section III shows thedetailed circuit implementation of key building blocks. The
experimental results are shown in Section IV, followed by theconclusion in Section V.
II. SYSTEM ARCHITECTURE
The top-level block diagram of the proposed buckconverter is shown in Fig. 1. The proposed buck converter
consists of a clock generator, a CCM/DCM controller, a45

power stage, and a digital PWM controller. The system clock(CK1) frequency is 6.4MHz. A clock generator is employed togenerate different frequency for sub-blocks in the digital
PWM controller based on the main clock. CK1 of 6.4MHz isused by DFFs. CK2 of 100kHz is used by the clocked
comparator. CK3 is used by the bi-directional shift register(SR). The CCM/DCM controller is employed to automaticallygenerate the required gate signals (CKP and CKN) for MP and
MN either in CCM or DCM operation. It will be explained indetail in section III. The power stage consists of gate drive
buffers, power MOS (MP and MN), and a LC filter.
VINMP

CK_buck
VX

CK1 (6.4MHz)CK2 (100kHz)
CK3 (6.25kHz)

Proposedautomatic
CCM/DCMcontroller(Fig. 3)

CKP

IOUT

VOUT

CKN

MN

VX

Load

CK1(6.4MHz)

Clockgenerator

TDigital PWM controller

TSet

CK2
DFF0

DFF1

DFF2

DFF3

DFF63

CK1Reset
CK_buck
VIN
110
Q10
Q10
Q20

CK2

Q62

Bi-directional shift register (SR)
CK3

VOUT
VREF

Fig. 1. Top level diagram of proposed buck converter.

controller is shown in Fig. 3. In DCM, a zero-cross switchingis achieved to maximize the efficiency. The controller consistsof only digital standard cells and a proposed dual-mode-bodybiased (DMBB) zero-crossing detector. The zero-crossing
detector is used to compare VX with ground, therefore detect if
the voltage at VX has crossed 0V. The rest digital standard
cells generate the required gate driving signals (CKP andCKN), and automatically switch between CCM and DCM
operations. A pulse converter is realized with inverters andAND gate, to convert a clock signal IN1 into a pulse signal
OUT1. The pulse signals are used to set or reset the inputs of
the SR-latch to generate CKN. The timing diagram of theproposed automatic CCM/DCM controller is shown in Fig. 4.
In CCM condition (Fig. 4 (a)), when load current is high,inductor current (IL) is always larger than zero. CKP isapproximately equal to CK_buck. When CKP goes high,meaning MP is turned off, a Set1 signal is generated by thepulse converter, and then CKN is set to high, so MN is turnedon accordingly. When MP is turned off, VX is always less than
0V due to the conduction voltage drop of MN, and the outputof zero-crossing detector (ZCD) and Reset_DCM is always
zero. CKN is then reset to zero by Reset_CCM. In contrast, in
DCM condition (Fig. 4 (b)), IL sometimes drops to zero. CKN
is set to high by the similar way as CCM. Then at the zerocrossing point (VX = 0V when MP is turned off), a pulse isgenerated for Reset_DCM and then CKN is reset to zero. In
this way, the zero-cross switching (MN is turned off when IL
becomes zero) is accomplished.
CK_buck

CKP

CK1

Set1

S

Pulse converter

CK2
Reset_CCMCKNRSetVX

Variable delay: TReset

Proposed ZCD
Pulse converter
DMBB zerocrossing
detector
IN1(Fig. 5)

Reset_DCM

OUT1

CK_buck
IN1

Variable duty 0%~100%

OUT1Fig. 2. Timing diagram of digital PWM controller.

In order to fit with the low supply voltage (0.6V), a digital
feedback architecture is more attractive than an analog
feedback. The digital PWM controller plays an important rolein the buck converter, and the timing diagram is shown in Fig.
2. Set signal is generated from CK1 and CK2 by DFF0 andtwo logic gates. A comparator is used to compare VOUT withVREF, thereafter control the shifting direction of the bidirectional shift register (SR). The output of SR, i.e., Q1-62,
then enables one of the switches to select one of the DFFs’outputs to connect to Reset. Therefore, a variable delay “T” isobtained to generate variable duty cycle for CK_buck.
CK_buck carrying appropriate duty information is later usedto drive the power stage and to regulate VOUT towards VREF.

Fig. 3. Circuit diagram of the proposed automatic CCM/DCM controller.

CCM

DCMIL0mA
VIN
0V

VX
CK_buck㻃CKPONONON

Set1
Reset CCM
Reset DCMCKNONONON(a)III. KEY BUILDING BLOCKSThe circuit diagram of proposed automatic CCM/DCM46ONONON(b)Fig. 4. Timing diagram of the proposed automatic CCM/DCM controllerwith (a) CCM, (b) DCM operation.

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

A key building block of the proposed CCM/DCMcontroller is the zero-crossing detector, which is shown in Fig.
5. A dual-mode-body-biased (DMBB) low-voltage zerocrossing detector is proposed to enable DCM operation withboth low supply voltage (0.6V) and normal supply voltage.
The DMBB zero-crossing detector is based on a differentialamplifier. MP1 and MP2 serve as the differential input pair, MP3
provides bias current for the amplifier, MN1 and MN2 are themirroring components. At low VDD, a voltage headroom of theamplifier is quite limited. In order to have enough gm, eithertransistor size or bias current needs to be enlarged, which aredefinitely not desired for low-power design. A forward bodybias is therefore beneficial in this design to alleviate the lackof voltage headroom with VDD. The bodies of MP1-3 areconnected to ground to enable the forward body bias, therefore
reduce the threshold voltage of them.

450μm
450μm

1500μmCore area: 600μm㬍140μm
Fig. 7. Layout and die photo.

VREF =0.4V

VREF =0.25V

SEBiasMP3Fig. 8. Measured CK_buck waveforms of digital PWM controller withdifferent VREF.
IOUT=3mA CCM

MP1

CKP

0.5V

CKN

1V

VX

1V

MP2SE
ZCD

0 VTrigger

VOUT

20mV

IOUT=1mA DCM
MN1

VDD

IOUT=2mA DCM

VDD

Voltage detector
VX

VREF =0.1V

VIN =0.6VVDD SE
VDD

10μs
0.6V

CK_buck

However, such forward body bias is only applicable when
VDD is low, otherwise the body diode of PMOS would beturned on, and large forward current would flow through thediode. As shown in Fig. 6, IVDD of the zero-crossing detector
increases exponentially with VDD. In order to avoid the large
leak current from VDD, forward body bias must be turned off
when VDD is larger than 0.7V. An ultra low-power voltage
detector [8] is therefore employed to switch body connection
with regarding to different VDD, as shown in Fig. 5. VTrigger isset to around 0.7V in this design. Thus, when VDD is lower
than 0.7V, the DMBB zero-crossing detector is forward bodybiased. In contrast, when VDD is higher than 0.7V, the detector
is zero body biased. Therefore, the DMBB architecture
achieves both a fast voltage detection operation at low VDD
and small body diode leak current at high VDD.

1500μmIOUT=0.5mA DCM

MN2CKPFig. 5. Low voltage dual-mode-body-biased zero-crossing detector.

CKNVX14VOUT

12Bodydiode off

IVDD (μA)

10Bodydiode on10μsFig. 9. Measured waveforms of buck converter in CCM and DCM at VIN =0.6V and VOUT = 0.35V.

864

IV. EXPERIMENTAL RESULTS

2The proposed buck converter is fabricated with 40-nm
CMOS process. Fig. 7 shows the layout and the chip microphotograph. The active area is 0.084mm2.

00.4

0.6

0.8

11.2

VDD (V)
Fig. 6. Measured IVDD of zero-crossing detector when forward body bias isenabledFig. 8 shows the measured output signals of the digital
PWM controller, i.e., CK_buck, at different VREF. It isobserved that duty cycle of CK_buck changes as VREF changes,

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

47

DCM
100
Efficiency (%)

90

proposed buck converter achieves higher peak efficiency andlower VIN and VOUT. While compared with [7], the proposedbuck converter has wider VIN range and smaller inductor value.

CCM

VIN=0.6V

V. CONCLUSIONS80
VOUT=0.35V
VOUT=0.5V

70
9%

60
50
40
3010μA

Proposed20%

Conventional
1mA

100μA

10mA

IOUTFig. 10. Measured efficiency of proposed and conventional buck converter.
TABLE I. COMPARISON OF LOW-VOLTAGE BUCK CONVERTERS[4] JSSC
2011[5] VLSI
2010[6] ISSCC [7] VLSI
2007
2012

In this paper, a low-voltage low-power buck converter isproposed for wireless sensor network systems. An automatic
CCM/DCM controller is proposed to adaptively select CCM
or DCM operation, therefore improving the power efficiency
and enlarging the output current range. A low-voltage DMBB
zero-crossing detector is proposed to enable DCM operation
with both low supply voltage and normal supply voltage. A
digital PWM controller is implemented for voltage regulation.
By virtue of the low power controller, the proposed buckconverter achieves a peak efficiency of 94% with an output
current range of 50μA to 10mA. Thanks to the DCM
operation, the efficiency at an output current of 100μA isimproved by 20% and 9%, with an output voltage of 0.35V
and 0.5V, respectively.

This work

VIN (V)

2.8-4.2

1.8

1.2

0.45

0.6-1.1

ACKNOWLEDGMENT

VOUT (V)

0.6-1.2

0.575

0.5

0.34-0.440.3-0.55

IOUT

20μA100mA

0.7μA107μA

2μA200μA

0.67μA410μA

50μA-10mA

Peakefficiency

87.4%

90%

86%

97%

94%

This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy andIndustrial Technology Development Organization (NEDO).

L

10μH

-2μH

47mH

220μH

Switchingfrequency

2MHz--

20kHz

100kHz

DCM

CCM

CCM/DCM

Operatingmode

CCM/DCM CCM/DCM

meaning successful modulation of the pulse width of the buckconverter.
Fig. 9 shows the measured waveforms of the proposedbuck converter at VIN = VDD = 0.6V and VOUT = 0.35V withdifferent output current (IOUT). At IOUT of 3mA, the buckconverter is in CCM operation, because CKN is in the same
shape with CKP. At IOUT from 2mA to 0.5mA, CKN transits
to zero before CKP goes to zero, meaning both MN and MP are
turned off when IL is zero. The worst case output voltage
ripple is 11mV (peak-to-peak) at IOUT=2mA.
Fig. 10 shows the measured power efficiency of proposedbuck converter with both CCM and DCM operation, andconventional one with only CCM operation. VIN is set to 0.6V,and VOUT is set to 0.35V and 0.5V. When IOUT is larger than2mA, both proposed and conventional buck converters are in
CCM operation, therefore the same efficiency is achieved. Incontrast, when IOUT is less than 2mA, the proposed buckconverter is in DCM operation, therefore significant efficiency
improvement is achieved. The power efficiency at IOUT of
100μA is improved by 20% and 9%, at VOUT of 0.35V and0.5V, respectively. The peak efficiency of 94% is achieved bythe proposed buck converter at IOUT of 2mA, thanks to theproposed low-power CCM/DCM controller and the lowpower digital PWM controller.
Table I shows the comparison with the published lowvoltage buck converters [4-7]. Compared with [4-6], the48

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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)