Overcurrent Detection Method by Monitoring GateVoltage While Periodically Repeating Discharging
and Charging of Constant Gate Charge in IGBTs

2022 IEEE 7th Southern Power Electronics Conference (SPEC) | 979-8-3503-9988-2/22/$31.00 ©2022 IEEE | DOI: 10.1109/SPEC55080.2022.10058332

Haifeng Zhang1, Hiromu Yamasaki1, Katsuhiro Hata1, Ichiro Omura2, and Makoto Takamiya1
1
The University of Tokyo, Tokyo, Japan2
Kyusyu Institute of Technology, Fukuoka, Japan

Abstract— A new overcurrent detection method by“monitoring gate voltage while periodically repeating discharging
and charging of constant gate charge (MGDC)” is proposed, whichenables overcurrent detection while IGBTs are ON by measuringgate-to-emitter voltage (VGE). In MGDC, while the IGBTs are ON,
constant gate charge is periodically discharged and charged, andwhen VGE dropped by each discharge is less than the reference
voltage, it is detected as the overcurrent. In a single-pulse test of
an inductive load at 300 V for an IGBT with a pulse rating of 150
A, a current-source 6-bit digital gate driver IC was used toperform MGDC with 1.3-s cycle, and MGDC successfully
detected an overcurrent of 250 A with a relative loss increase ofonly 0.8 %.

63 parallel-connected
pMOSFETs and nMOSFETs

15 VnPMOS [5:0]
nNMOS [5:0]

D2300 VIC

6IG Q16VCE
D1VGE
Digital gate driver IC

Fig. 1: Circuit schematic of measurement setup.

Keywords—overcurrent, detection, gate voltage, IGBT

I. INTRODUCTION
The detection and protection of IGBT overcurrent areimportant technologies to realize reliable power electronicsystems. The target of this work is to develop an IGBT
overcurrent detection (OD) method measurable from gate
terminals while IGBTs are ON for large-current, short-pulse
current generator circuits with inductive load [1]. When OD isdone from the gate terminal of IGBTs, OD can be integrated into
the gate driver IC, thus enabling low-cost OD method.
Methods for detecting overcurrent by measuring collector
current (IC) [2-5], collector-to-emitter voltage (VCE) [3, 6], andgate-to-emitter voltage (VGE) [7-10] of IGBTs have been
proposed. IC measurement requires a current sensor, and VCE
measurement for desaturation detection requires a high-voltage
diode, which are expensive. All conventional OD methods by
VGE measurement [7-10] have the disadvantage that overcurrent
during ON of IGBTs cannot be detected because VGE is
measured during the turn-on transient. To solve the problems, inthis paper, a low-cost OD method by “monitoring gate voltage
while periodically repeating discharging and charging of
constant gate charge (MGDC)” that can detect overcurrent
during ON of IGBTs from VGE and can be integrated into gate
driver ICs is proposed.
II. PROPOSED OVERCURRENT DETECTION METHOD BY MGDC
Figs. 1 and 2 show a circuit schematic and a photo of themeasurement setup for a single-pulse test of an inductive loadof 34 H at 300 V for IGBT (SIGC57T120R3LE, 1200 V
979-8-3503-9988-2/22/$31.00 ©2022 IEEE

Digital gate
driver IC

Q1, D1

D2

Fig. 2: Photo of measurement setup.

rating) with a pulse rating of 150 A, respectively. The IGBT
module including IGBT (Q1) and the diode (D1:SIDC30D120H8, 1200 V, 50 A rating) was self-made. The
high-side diode (D2) is GB2X100MPS12-227 (1200 V, 1000 A
pulse rating). A current-source 6-bit digital gate driver IC [11],where the gate current (IG) is variable with 6-bit control signals(nPMOS [5:0] and nNMOS [5:0]) and IG is proportional to nPMOS andnNMOS which are integers from 0 to 63, is used to perform
MGDC.
Figs. 3 (a) and (b) show timing charts for OD of theconventional VCE measurement for desaturation detection andthe proposed MGDC, respectively. In the conventional
desaturation detection shown in Fig. 3 (a), overcurrent is
detected when VCE exceeds a reference voltage (VREF). In
contrast, the proposed OD method by MGDC has three steps:
gate discharging, VGE comparison, and gate charging. In theproposed MGDC shown in Fig. 3 (b), a constant gate charge

Authorized licensed use limited to: University of Tokyo. Downloaded on April 09,2023 at 07:07:49 UTC from IEEE Xplore. Restrictions apply.

VGE

15 V0VIC Rated IC0A

Overcurrent detection

300 V
VCE VREF
0V

Overcurrent protection(a)t1nPMOS 63

063nNMOS
IGt2

t1

t2

t2

t1

t2

t1

t2n1n200A

QC

Overcurrent detection

15 V

VGE VREF

0V

VDROP, INIT VDROP

VDROP

VDROP, OC

IC Rated IC
0A
300 VVCE

0V

Overcurrent protection(Not implemented in this work)(b)
Fig. 3: Timing charts for overcurrent detection. (a) Conventional VCE measurement for desaturation detection. (b) Proposed MGDC.

(QC) (= IG × t2) is periodically discharged with the t1 + t2 cycle,
and if the resulting drop in VGE (VDROP) is greater than VREF, it
is judged normal, and if VDROP is less than VREF, it is judgedovercurrent. VGE is recharged to 15 V in the t1 period after eachdischarge.

15 V

Point A (Start)

IC = I2

NormalVGEFig. 4 shows the principle of operation of the proposed OD
by MGDC with a schematic of VGE vs. gate charge (QG) curve.
The black graph shows the characteristics for IC = I1, the redgraph for IC = I2, and the blue graph for IC = I3, where I1 < I2 <I3 and I3 shows the overcurrent. When QC is discharged from
Point A of VGE = 15 V, the operating point changes from Point
A to Point B when the IGBT is normal, while the operating
point changes from Point A to Point C when the IGBT isovercurrent, because the gate capacitance decreases when theovercurrent occurs. Since VGE at Points B and C are different,
the overcurrent can be detected by comparing VGE and VREF
using a comparator.

I1 < I2 < I3

IC = I1

VREF
0V
−1

Point B

Overcurrent
Point CI C = I3

−QC

0Gata charge (QG) [a.u.]
Fig. 4: Principle of operation of proposed MGDC.

Authorized licensed use limited to: University of Tokyo. Downloaded on April 09,2023 at 07:07:49 UTC from IEEE Xplore. Restrictions apply.

III. MEASURED RESULTS
Fig. 5 shows the measured waveforms of the conventional
OD method by monitoring VCE. When IC exceeds 250 A, theIGBT enters the desaturation region and VCE increases rapidly.
In the conventional desaturation detection, the overcurrent isdetected by the VCE increases. The energy loss (ECONV) caused
by IC × VCE in Fig. 5 is 17.5 mJ, which is the value that will beused later as a reference for comparison with the proposal.
The proposed MGDC has four parameters (t1, t2, n1, and n2)
shown in Fig. 3 (b). n1 is nPMOS during t1 and n2 is nNMOS during
t2. The design guidelines for the parameters are as follows. The
measurement cycle (t1 + t2) should be shorter than the shortcircuit withstand time of the IGBTs so that the overcurrent is
not overlooked. QC, which is proportional to n2 × t2, is the mostimportant parameter in MGDC. If QC is too small, theovercurrent cannot be detected. If QC is too large, the energy
increase due to MGDC is excessive and unacceptable, because
in MGDC, VGE drops temporarily on a periodic basis,2 s/div

VGE

increasing the conduction losses of the IGBTs. Therefore, it isvery important to set QC to an appropriate value.
Fig. 6 shows the measured waveforms of the proposed OD
method by MGDC with different QC’s. QC is varied bychanging n2 from 10 to 60 at t2 = 300 ns. In this paper, t1 = 1

Overcurrent
VGE: 4 V/div 10 s/div

VCE: 100 V/div0Fig. 5: Measured waveforms of conventional overcurrent detection methodby monitoring VCE.

2 s/div

VGE

VCE

VCE

VCE
VDROP, INIT

VDROP, INIT
ICIC00

VCE: 100 V/div

VCE: 100 V/div0VGE

VGE

IC

IC

VDROP, OC

VDROP, OC

VCE

VCE
0(a) n2 = 10(b) n2 = 20 (Best design)

Overcurrent

10 s/div
VGE: 4 V/div0

VCE: 100 V/div2 s/div2 s/div

00

VGE: 4 V/div 10 s/div

VGE: 4 V/div 10 s/div

IC

VDROP, INIT

Overcurrent

Overcurrent

02 s/divVGE

2 s/div
VGE

IC

0

VDROP, OC
VCE(c) n2 = 60

Fig. 6: Measured waveforms of proposed MGDC with different QC’s. QC is varied by changing n2 at t2 = 300 ns. (a) n2 = 10. (b) n2 = 20 (best design). (c) n2 = 60.

Authorized licensed use limited to: University of Tokyo. Downloaded on April 09,2023 at 07:07:49 UTC from IEEE Xplore. Restrictions apply.

VDROP, INIT, VDROP, OC [V]

15t2 = 200 ns

VMIN, INITIAL

105VMIN, OC
00102030
n24050t2 = 300 nsBest designFig. 6 (b)00102030
n220405030
n2405060(a)EGD [J]

5Fig. 6 (c)43t2 = 300 ns

21 Fig. 6 (a)00Best design
Fig. 6 (b)102030n2t2 = 200 ns

405060(b)65Fig. 6 (c)43t2 = 300 ns

2Best design
Fig. 6 (b)Fig. 6 (a)100102030n2t2 = 200 ns

405060(c)30Fig. 6 (c)25201510Best design
Fig. 6 (b)Fig. 6 (a)5t2 = 300 nst2 = 200 ns

0.8%

000

10660

VDROP, INIT Fig. 6 (c)VDROP, OCt2 = 200 ns

Fig. 6 (a)0ETOTAL / ECONV [%]VDROP, INIT, VDROP, OC [V]

5Best design
Fig. 6 (b)2035Fig. 6 (a)10t2 = 300 ns

10(a)15Fig. 6 (c)30

EMAIN [mJ]

To discuss the optimal value of QC, Figs. 7 (a) and (b) show
the measured n2 dependence of VDROP, INIT and VDROP, OC at t2 =200 ns and 300 ns, respectively. Figs. 8 (a) to (d) show n2
dependence of the energy loss increase in gate driver (EGD) andthe energy loss increase in main circuit (EMAIN) caused by IC ×
VCE due to MGDC, total loss increase (ETOTAL (= EGD + EMAIN)),and relative loss increase (ETOTAL / ECONV) due to MGDC,respectively. The integration period for energy calculation isfrom the beginning of IC flow in Fig. 6 to just before theovercurrent region. EGD is calculated as IG × 15 V × t2 × numberof times of MGDC, where IG is proportional to n2. EMAIN is
obtained from the measured waveforms of IC and VCE. EGD issufficiently smaller than EMAIN hence EGD can be ignored. In Fig.
7, since VDROP, INIT >> VDROP, OC is required for stable OD, it isnecessary to set n2 ≥ 40 for t2 = 200 ns and n2 ≥ 20 for t2 = 300
ns. In contrast, as shown in Fig. 8, excess n2 leads to the loss

40

ETOTAL (= EMAIN + EGD) [mJ]s and n1 = 63 are fixed. As shown in Fig. 3 (b), the initial
VDROP is defined as VDROP, INIT, and the minimum value of VDROP
in the overcurrent region is defined as VDROP, OC. In Fig. 6 (a)with n2 = 10, VDROP increases with increasing IC since the Miller
plateau voltage increases, and VDROP, OC hardly decreases evenin the overcurrent region, thus failing to detect overcurrent. Incontrast, in Figs. 6 (b) and (c) for n2 = 20 and 60, VDROP
increases with increasing IC, and in the overcurrent region,
VDROP, OC decreases rapidly to around 0 V, indicating successfulOD. As a result, an overcurrent of 250 A in the IGBT with thepulse rating of 150 A is successfully detected.

60(b)Fig. 7: Measured n2 dependence of VDROP, INIT and VDROP, OC at (a) t2 = 200 nsand (b) t2 = 300 ns.

102030n2405060(d)Fig. 8: n2 dependence of (a) energy loss increase in gate driver (EGD), (b)energy loss increase in main circuit (EMAIN) caused by IC × VCE due to MGDC,(c) total loss increase (ETOTAL (= EGD + EMAIN)), and (d) relative loss increase(ETOTAL / ECONV) due to MGDC.

Authorized licensed use limited to: University of Tokyo. Downloaded on April 09,2023 at 07:07:49 UTC from IEEE Xplore. Restrictions apply.

increase. Thus, the best design point for detectable overcurrent
and minimum loss increase is at t2 = 300 ns and n2 = 20, where
the relative loss increase is only 0.8 %.
Table I shows a comparison table of OD methods. This paper
is the first work to achieve OD while IGBTs are ON bymeasuring from the gate terminal. MGDC can be integrated into
the gate driver IC, thus enabling low-cost OD method.
TABLE I.

COMPARISON TABLE OF OVERCURRENT DETECTION

Reference[2-5][3, 6][8-9][10]This work
Current Desatura Gate VGE at Miller
MGDC
monitortion
charge plateau
Measured valueICVCE
QG, VGEVGE
VGE
Measurementfrom gate
NoNo
Yes
Yes
Yes
terminal
Overcurrent
detection during
Yes
Yes
NoNo
YesON
AdditionalHigh
Constant
Current
Integrat
circuits except
voltage
Filtercharge
sensororcomparators
diodedischarger

Method[6]J. Kim and Y. Cho, “Overcurrent and short-circuit protection method
using desaturation detection of SiC MOSFET,” in Proc. IEEE PELS
Workshop on Emerging Technologies: Wireless Power Transfer, Nov.
2020, pp. 197-200.
[7] M. Kim, B. Park, R. Kim, and D. Hyun, “A novel fault detection circuit
for short-circuit faults of IGBT,” in Proc. IEEE Appl. Power Electron,Conf. Expo., Mar. 2011, pp. 359-363.
[8] T. Horiguchi, S. Kinouchi, Y. Nakayama, T. Oi, H. Urushibata, S.
Okamoto, S. Tominaga, and H. Akagi, “A short circuit protection method
based on a gate charge characteristic,” in Proc. International PowerElectronics Conference, May 2014, pp. 2290-2296.
[9] S. Yano, Y. Nakamatsu, T. Horiguchi and S. Soda, “Development andverification of protection circuit for hard switching fault of SiC MOSFET
by using gate-source voltage and gate charge,” in Proc. IEEE Energy
Conversion Congress and Exposition, Oct. 2019, pp. 6661-6665.
[10] X. Li, D. Xu, H. Zhu, X. Cheng, Y. Yu, and W. T. Ng, “Indirect IGBT
over-current detection technique via gate voltage monitoring and analysis,”IEEE Trans. on Power Electronics, vol. 34, no. 4, pp. 3615-3622, April
2019.
[11] K. Miyazaki, S. Abe, M. Tsukuda, I. Omura, K. Wada, M. Takamiya, andT. Sakurai, “General-purpose clocked gate driver IC with programmable63-level drivability to optimize overshoot and energy loss in switching bya simulated annealing algorithm,” IEEE Trans. Ind. Appl., vol.53, no.3,pp. 2350-2357, May-June 2017.

IV. CONCLUSIONSThe proposed OD method by MGDC with 1.3-s cycle
successfully detected the overcurrent of 250 A by measuring
VGE while IGBTs are ON with a relative loss increase of only
0.8 %. Since this paper only demonstrated the principle ofoperation of OD by MGDC, future research topics are (1) OD
using comparator circuits, (2) overcurrent protection, and (3)integration of MGDC into gate driver ICs.
ACKNOWLEDGMENT
This work was partly supported by JST-Mirai Program,Grant Number JPMJMI20E1, Japan.
REFERENCES
[1]

[2]

[3]

[4]

[5]

T. Murakami and K. Akatsu, “Principle verification of magnetization
reversal motor,” in Proc. European Conference on Power Electronics andApplications, Sep. 2017, pp. 1-7.
D. Rothmund, D. Bortis, and J. W. Kolar, “Highly compact isolated gate
driver with ultrafast overcurrent protection for 10 kV SiC MOSFETs,”
CPSS Transactions on Power Electronics and Applications, vol. 3, no. 4,
pp. 278-291, Dec. 2018.
S. Mocevic, L. Wang, R. Burgos, D. Boroyevich, C. Stancu, M. Jaksic,and B. Peaslee, “Comparison between desaturation sensing and Rogowski
coil current sensing for shortcircuit protection of 1.2 kV, 300 A SiC
MOSFET module,” in Proc. IEEE Appl. Power Electron, Conf. Expo.,
Mar. 2018, pp. 2666-2672.
H. Yoon and Y. Cho, “Application of the Rogowski coil current sensor
for overcurrent detection and blocking in power conversion systems,” inProc. International Conference on Power Electronics and ECCE Asia,May 2019, pp. 1-7.
Y. Kuwabara, K. Wada, J. Guichon, J. Schanen, and J. Roudet,“Overcurrent detection using an integrated Rogowski coil for an electricvehicles inverter,” in Proc. IEEE International Future Energy Electronics
Conference, Nov. 2019, pp. 1-5.

Authorized licensed use limited to: University of Tokyo. Downloaded on April 09,2023 at 07:07:49 UTC from IEEE Xplore. Restrictions apply.