A 1-V 299µW Flashing UWB Transceiver Based on Double Thresholding Scheme
Atit Tamtrakarn1, Hiroki Ishikuro2, Koichi Ishida1, Makoto Takamiya1 and Takayasu Sakurai1
1
2

Center for collaborative research, University of Tokyo, Tokyo, Japan

Toshiba Corporation, SoC Research and Development Center, Kawasaki, Japan

Abstract
This paper presents an Ultra-Wide-Band transceiver basedon a newly proposed double thresholding scheme. Thescheme does not require any precise synchronization and thus
is practical in ad-hoc networks. The proposed architecture hashigh noise and multi-path fading signal immunities. Allanalog blocks are activated in a short period called ‘flashing’to suppress total average power. A tested chip is manufactured
using 0.15µm FD-SOI CMOS technology. The measured
average power is 299µW at 25kbps data-rate over the distanceof 35cm.
Keywords: UWB, low-power, flashing, double thresholding
Introduction
Ad-hoc wireless sensor networks (WSN) are attracting
attention as a new field of VLSI applications. An
Ultra-Wide-Band (UWB) transceiver is suitable for the WSN
applications due to its low-power nature [1]-[2]. The0-960MHz band is more suitable for low-speed applications
like WSN than the 3.1-10.6GHz band in term of power[1][3]-[5]. The existing clocked correlator-based transceiver[1], however, shows more than a mW power which is not
ideal for the WSN. Moreover, the correlator-based transceiver
requires very precise synchronization which is very difficult
to implement in ad-hoc network environments. The proposedarchitecture does not require the precise synchronization
among distributed chips and thus practical and at the sametime achieves operation power of less than a mW.
Double thresholding architectureFig.1 shows the architecture of the proposed transceiver
which is based on bi-phase shift keying (BPSK) modulation
method. The transmitter is all digital and generates a signal
with positive and negative peaks shown in Fig.1 containing awide spectrum of frequencies. The out-of-band signal isfiltered out by a pulse filter and an antenna. The receiver side
is composed of front-end amplifiers, continuous-timecomparators, and a phase detector (PD).
An incoming pulse is amplified by the front-end amplifiers
and then the amplified pulse is compared with two thresholdlevels to detect peaks. The comparators generate V+ and Vsignal when positive and negative peaks are detected. Then,the PD determines the received bit (RxBit) as ‘1’ if V+ comes
earlier than V- (‘0’ otherwise) as shown in Fig.2. It is okay
even if either of V+ or V- is not detected and in this case
RxBit is interpreted as ‘1’ if only V+ is detected (‘0’otherwise). Consequently all multi-path signals which aredelayed signals are automatically neglected. Since the UWB
pulse width is few nanoseconds, the system can be reset after
the few nanoseconds to allow the system ready for the next

1-4244-0006-6/06/$20.00 (c) 2006 IEEE

pulse. The two threshold levels generate a noise gap, between
which any input is not recognized as a valid signal. Thus thenoise smaller than the gap is rejected by the system. Thus, theproposed architecture can handle both noise and multi-path
signal. Fig. 3 shows simulation results for bit error rate (BER)
which does not much affect by noise and multi-path signal.
Flashing analog circuits with staggered clocking scheme
A parallel common-gate input amplifier (CGA) shown inFig.4 is used as the front-end amplifier to obtain wideband
impedance matching. Since the proposed architecture hashigh noise immunity as described above, the resistive
termination which may increase input noise is used because it
consumes lower power than the transconductance (Gm)termination. DC voltage at the output node of the CGA isstabilized by the opamp. This opamp is designed to havesmall bandwidth of a few kHz to prevent feedback loop of
in-band signal. Three common-source amplifiers (CSA) arecascaded after the CGA for achieving total gain of 50dB.
Since the UWB pulse width is very short compared withthe transmission period, flashing concept is effective forpower reduction. In the training process, an interval of two
adjacent pulses is counted digitally and the counted value issaved as an approximate signal period (PCK). Analog part isin a power-down mode from the time just after a signal pulse
is detected and to the time before the next signal comes. The
margin is needed to handle variation of clock mismatchamong chips. This can be realized by setting the power-down
period as around 90% of the PCK. Small replica circuits ofamplifiers, called ‘bias keeper’, are used to keep the DC bias
point even when the amplifiers are cut off. It was found that 4
amplifier stages should be waked up in a staggered way.
Otherwise, a settling time is increased from 3.1µs to 5.5µs asshown in Fig. 5.
Measurement and comparison
A tested chip is fabricated with a 0.15µm FD-SOI CMOS
process (Fig.6) with a die area of 0.4mm2. Data rate of 25kbps
is measured over the distance of 35cm with power of 299µW.
The power consumption is almost independent from data rate
because duty cycle of the flashing clock is fixed. Powerbudget of the transceiver is listed in Table 1. BER andcomparison with previous works are shown in Fig.7.
Fig.8 shows effectiveness of each power reduction
approaches. Elimination of a power-hungry time-continuous
correlator, the adoption of low-power wide-band amplifies
and mostly digital scheme, and the flashing concept withstaggered activation reduced the power down to µW order.
Conclusions
A flashing UWB transceiver based on double thresholding

2006 Symposium on VLSI Circuits Digest of Technical Papers

method is proposed and implemented, which does not requireprecise synchronization and has high noise and multi-path
signal immunities. The fabricated test chips show the lowest
power consumption ever reported.

φ1VB

Voltage (mV)Q

All digital UWB pulse transmitter

Front-end
amplifier

V-viG

vin

Bit
holderREAD

V+Phasedetector
RxBit

Flashing clock
generator

n-bit
n-bit Data
Adjacent pulse
Counter n recorder n interval counter

φ2φ3φ40.0V0s

VSS

Staggered activation scheme

5µs

10µs

20µs

1.0V

Ф1vO

Ф20.5VФ33.1µsФ40.0V
Staggered scheme
0s
Non-staggered scheme

05µs

10µs

15µs

20µs

Pulse transmitter
CComparators
125µm
C
51525
Time (ns)-50Flashingclockgenerator

CPower spectrum
density-60
0200
400600Frequency (MHz)Output buffer
Phase detector

35FCC regulation-41.3

Power-gating
control block

15µs

Staggered power gating

LNA & Gain stages

Continuous-time
comparators

Gainstages

0.5V-200-400

Double thresholding UWB
receiver architecture

VTH VTLvOvO200(dBm/MHz)

φTX

1.0V

Fig. 5 Staggered activation scheme.

400Pulse
filterNon-staggered power gating

φ1

5.5µs

Transmitting pulse
Q

φ4M2

φ1

[1] T. Terada, S. Yoshizumi, Y. Sanada and T. Kuroda, IEEE VLSI Circuit
Symp., pp.30-33, Jun. 2005.
[2] Federal Communication Commission (FCC), “Ultra-wideband (UWB)
First Report and Order,” Feb. 2002.
[3] A. Ismail and A. Abidi, ISSCC. Dig. Tech. Papers, pp.208-209, Feb. 2005.
[4] S. Iida et al., ISSCC. Dig. Tech. Papers, pp.214-215, Feb. 2005.
[5] B. Razavi et al., ISSCC. Dig. Tech. Papers, pp.216-217, Feb. 2005.
[6] B. Otis, Y.H. Chee, J. Rabaey, ISSCC, pp. 396-397, Feb. 2005.

D

Wake-up time

φ3

M1

References

TxBit

VDD

φ2Pulseintervalcounter

Output buffer

5-bit data
recorder

210µm
520µm

RxBit
5-bit
counter

110

100

READ

Fig. 1 The proposed UWB architecture.
10V

V TH
ViG

V

VTL

The proposed UWB receiver

TL

V-VSYNCXXXXXXXXXXX

t+tMINMINVTHVTLV+READ

Vt-MIN

X = Not valid

Transmitting edge

Fig. 6 Chip photograph and measurement result.

V+V+

RxBit

715µm

TH

Multi-path
signalt+MIN

TABLE I
POWER BUDGET OF THE PROPOSED TRANSCEIVER
Static power (µW)
Dynamic power (µW)
Transmitter-<1
Front-end amplifier
157
13
CSA Gain stages
360
28
Comparators
1000
78
Bias & bias keeper
150
150
Digital blocks-30
Total (measured)
1667
299

Fig. 2 Operation of the architecture in fig.1.
100

Comparison with previous works
103 bps = bit/second[3]

BER vs Distance

100

Channel withoutmulti-path signal

10-1

cps = chip/second

10-1

10-3
10-4

10-3

Channel withmulti-path signal

10-5051015Signal-to-Noise Ratio (dB)

20Fig. 3 BER in channel with noise and multi-path signal.
Return loss (dB)0V DD
Replicabias

Biaskeeper

φ1M2

Flashing
Front-end
amplifier-5

M1

140MHz 1.9GHz-10

0.5VDD

10-1

35

No precise synchronizationis required[6](5kbps)*
This work(25kbps)
0 1 2 3 4 5 6 7 8 9 10
Area (mm2)Conventionalcorrelator
methodRemove correlator andrequirement of precisesynchronization

Proposeddouble
thresholding
method0VSS

10-5350MHz

10φ11001525Distance (cm)[4](1Gcps)[1](1Mbps)
101 Require very precise synchronization

10-45[5](480Mbps)*Require Bulk Acoustic Wave (BAW) resonator

vOUT

Gain (dB)102

Fig. 7 BER and power comparison with previous works.

-10vINPower (mW)

10-2BERBER

10-2

Low-power amplifiersFlashing transceiver

-20
10M

Fig. 4 Low-power front-end amplifier.

1-4244-0006-6/06/$20.00 (c) 2006 IEEE

100M
1G10G
Frequency (Hz)012345Power consumption (mW)

Fig. 8 Effectiveness of power reduction approaches.

2006 Symposium on VLSI Circuits Digest of Technical Papers