IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 1, JANUARY 2012301

A 100-V AC Energy Meter Integrating 20-V Organic
CMOS Digital and Analog Circuits With a Floating
Gate for Process Variation Compensation anda 100-V Organic pMOS Rectifier
Koichi Ishida, Member, IEEE, Tsung-Ching Huang, Member, IEEE, Kentaro Honda, Tsuyoshi Sekitani,
Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Member, IEEE, Takao Someya, Member, IEEE, andTakayasu Sakurai, Fellow, IEEE

Abstract—A 100-V ac energy meter based on the system-ona-film (SoF) concept, in which various devices are integrated ona flexible film, is presented. The system consists of 20-V organic
CMOS digital and analog circuits with a floating gate (FG) forprocess variation compensation, 100-V organic pMOS rectifiers
for generating a 50-Hz clock and 20-V dc power, and an organic
LED (OLED) bar indicator. The energy meter based on the SoF is
flexible and therefore can be installed to monitor each ac outlet simultaneously. The organic devices are printable, and it is expectedthat they can be formed using a low-cost printing process in the future. The energy meter can measure the accumulated energy of a100- rms ac lineup to a full-scale value of 360 Wh when a 500-W
target load is monitored. The flexible film is foldable and its total
area excluding the ac connector is 200 200 mm2 in the unfolded
form or 70 70 mm2 when folded.

V

Index Terms—Floating gate (FG), large-area electronics, mismatch compensation, operational amplifier, organic CMOS,
organic LED, pseudo-CMOS, system-on-a-film (SoF).

I. INTRODUCTION
SMART meter is essential for realizing a smart grid. To
further reduce the energy loss in the power grid, instead ofsimply replacing conventional energy meters with smart meters,
an extremely fine-grain power-monitoring system (e.g., powermonitoring of every electric outlet or battery) is desirable [1].
This will require an enormous number of low-cost energy meters. Existing energy meters, however, do not meet the requirements for this application in terms of their cost and form factor.

A

Manuscript received May 06, 2011; revised July 24, 2011; accepted
September 15, 2011. Date of publication November 07, 2011; date of current
version December 23, 2011. This paper was recommended by Guest Editor
Satoshi Shigematsu. This work was supported in part by JST/CREST andSpecial Coordination Funds for Promoting and Technology.
K. Ishida, K. Honda, and T. Sakurai are with the Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan.
T.-C. Huang was with the Institute of Industrial Science, University of Tokyo,
Tokyo 153-8505, Japan. He is now with the TSMC North America, San Jose,CA 95134 USA.
T. Sekitani and T. Someya are with the Department of Electrical Engineering
and Information Systems, School of Engineering, University of Tokyo, Tokyo
113-8654, Japan.
H. Nakajima and H. Maeda are with the Dai Nippon Printing Company, Ltd.,
Kashiwa 277-0871, Japan.
M. Takamiya is with the VLSI Design and Education Center, University ofTokyo, Tokyo 113-8654, Japan.
Digital Object Identifier 10.1109/JSSC.2011.2170634

Fig. 1. Overview of the organic 100-V ac energy meter.

On the other hand, printable organic devices on flexible films
have great potential to realize low-cost energy meters and a flexible energy meter can be installed to monitor each ac outlet simultaneously. In this context, a 100-V ac energy meter based on
the system-on-a-film (SoF) concept was proposed, and its feasibility was demonstrated [2].
In this paper, we describe the 100-V ac energy meter in detailand provide detailed measurement results and some discussion.
In Section II, we give an overview of the proposed energy meterand the SoF concept. In Section III, we describe the circuit design in detail. In Section IV, we present and discuss the experimental results. Finally, conclusions are given in Section V.
II. OVERVIEW OF 100-V AC ENERGY METER
Fig. 1 shows an overview of the 100-V ac energy meter, which
consists of four circuit blocks. For instance, a 3-W, 0.1- reis used assistor that can handle a current of up to 5.48
a current-sensing resistor. This component is suitable for, 500-W target load. An ac
the measurement of the 100of about 5
flows into the ac power line circuitcurrent
across the sensing resistor is amplified
loop. The voltage
and the power level is converted into a number of digital pulses
per unit of time. The counter accumulates the digital pulses andthe resulting measured energy is displayed by an organic LED(OLED) bar indicator. We use the OLED indicator since thisenergy meter is designed for domestic uses. When the energy
meter is used for large buildings, offices, and industry, either awired or wireless communication circuitry should be added tomonitor the measured data in real time. The organic rectifiers
supply both dc power with a maximum current of more than0018-9200/$26.00 © 2011 IEEE

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Fig. 2. Prototype of the organic 100-V ac energy meter on a flexible film.

2 mA and 50-Hz clock pulses to the circuit blocks in the energy
meter.
To handle both a small signal of approximately 0.5 V and aac at the same time, various organic
high voltage of 100
devices have been used to meet diverse design requirements.
Fig. 2 shows a photograph of the proposed organic 100-V ac
energy meter on a flexible film. The key components of the energy meter include: 1) a rectifier composed of a 100-V organic
pMOS for generating the 20 V DC power and clock pulses forthe energy meter; 2) analog circuits composed of 20-V organic
CMOS transistors with a floating gate (FG) like the operational
amplifier for sensing the ac current; 3) logic circuits composedof 20-V organic CMOS transistors for the frequency divider andthe counter accumulating the measured power; 4) an OLED [3]bar indicator for displaying the measured energy; and 5) an acconnector inserted between the power plug and the ac outlet anddiscrete passive components (capacitors and resistors for circuit
tuning) which are fully integrated on a 200 200 mm flexible
film. We name this type of system implementation an SoF. Theenergy meter based on the SoF is flexible and therefore can beinstalled to monitor each ac outlet simultaneously. The organic
devices are printable and will be manufactured using low-cost
printing process in the future. The entire sheet of the film can befolded and the total size of the proposed 100-V ac energy metercan be reduced to 70 70 mm . In this work, the system dimensions are mainly determined by the manufacturable sizes ofthe printable organic transistors. The system dimensions can befurther reduced by design-rule scaling of the printable organic
transistors.
III. CIRCUIT DESIGN
A. System Block Diagram and Target Specifications
Fig. 3(a) shows a block diagram of the 100-V ac energy
meter, which consists of four blocks. Rectifiers implemented
with 100-V organic pMOS transistors include a full-wave
rectifier for the dc power supplies and a half-wave rectifier forclock generation. The required dc supplies for the energy meter
20 V
0V
20 V are provided by

Fig. 3. Overview of the organic 100-V ac energy meter. (a) Block diagramof the ac energy meter. (b) Schematic of the half-wave rectifier used for clock
generation. (c) Timing chart.

50-Hz ac power to 20-V dc power
converting the 100using the full-wave rectifier. The 50-Hz clock pulses used forthe input of the 10 bit frequency divider are directly generated
50-Hz ac signal by a half-wave rectifier,from the 100which consists of five diode-connected pMOS transistors asshown in Fig. 3(b).
In this implementation, we do not use dc-to-dc converters or
voltage regulators, which require a voltage reference, to simis generated by a voltage divider, which
plify the circuitry.
consists of diode-connected pMOS transistors. Therefore, bothandare determined by the load current. To improve
the regulation of the output voltage, voltage regulators for the
power supplies should be added in a practical design.

ISHIDA et al.: 100-V AC ENERGY METER INTEGRATING 20-V ORGANIC CMOS DIGITAL AND ANALOG CIRCUITS WITH A FG

Analog circuits implemented with a 20-V organic CMOS
with an FG include an operational amplifier, a MOS diode, avoltage comparator, and a triangular-wave generator. The acbyload current is converted to a voltage of up to ac 0.5
input voltage,
the sensing resistor . To amplify the 0.5the input mismatch of the amplifier should be suppressed to well
below 0.5 V. The operational amplifier employs a mismatchcompensation scheme that exploits the transistor FG [4]. This
voltage than the normal
scheme requires three times higher
supply voltage to inject charges into the FG. If we used an FG for
100-V devices, 300 V or more would be required for FG operation, which is too high to be handled safely. Therefore, we use a
20 V CMOS process for the analog circuits. This 20-V CMOS
operational amplifier is used in linear gain region without feedback loop because of its small open-loop gain. The MOS diodeconverts the ac voltage at the output of the operational amplias shown in Fig. 3(a). Then,fier into the dc voltage
is compared with a 0.05-Hz triangular-wavebya comparator. The operational amplifier with the FG as shownin Fig. 3(c) is used for this comparator and its output is amplified by a pseudo-CMOS inverter [9]. The triangular-waveof the frequency divider. The output
generator is driven byof the comparator is connected to the enable pin of the 10-b
counter operating at 0.4 Hz ( of the frequency divider), which
is eight times higher than the frequency of the triangular-wave.
The output of the comparator, which depends on the input signal
polarity, enables or disables the 10 bit counter. Since the triangular-wave is symmetric, the dc voltage is evaluated with four
voltage steps (equivalent to 2-b resolution).
The logic circuits implemented with a 20-V organic CMOS
consist of a 10-b frequency divider and a 10-b counter. The
0.05-Hz clock for the input of the triangular-waveform generator and the 0.4-Hz clock for the 10-b counter are both generated
by the 10-b frequency divider. To measure the accumulated energy instead of obtaining instantaneous readings, the maximum
integration time of the energy meter is designed to be 43 minHzs , which is equivalent to 360 Wh with a
500-W load.
The five most significant bits in the 10-b counter are connected to the 5-b OLED bar indicator used for displaying themeasured results. By observing the OLED bar indicator, the user
can visualize the amount of electric power that he/she is using.
The minimum energy indicated by the OLED bar indicator is
Wh
bit .
11 Wh
In this implementation, the OLED indicator displays raw binary data to simplify the circuitry, that is, the OLED indicator
will be reset if the counter reaches 360 Wh. To avoid this inconvenience, the number of counter bits should be increased andthe maximum value should be stored in a practical design.

B. All-PMOS Full-Wave Rectifier
To supply dc power to the energy meter from a 100ac power source, we implemented a full-wave rectifier using a
100-V organic pMOS based on the semiconductor pentacene.
Since in our technology the driving capability of an organicnMOS is weaker than that of a pMOS by approximately an

303

Fig. 4. The 100-V organic all-PMOS rectifier. (a) Conventional pMOS dioderectifier. (b) Proposed cross-coupled pMOS rectifier. (c) Comparison of theoperation.

Fig. 5. The 100-V organic pMOS transistor. (a) Photograph. (b) Measured
I –V
characteristic.

order of magnitude, it is not practical to use an nMOS in therectifier. The total current consumption of our logic circuit istens of ìA, while our OLED-based bar indicator requires a total
current of 2 mA for all five OLED modules; thus, we use an
all-PMOS full-wave rectifier. For a typical rectifier using pMOS
diode-connected transistors as shown in Fig. 4(a), the power
efficiency is poor since each pMOS transistor operates at thepinch-off region. To increase the output current of the rectifier, two pMOS diodes are replaced with a pair of cross-coupled pMOS transistors operating in the linear region as shownfor the cross-coupled pMOS transistors isin Fig. 4(b).
(up to 100 V). These cross-coupled transistors areequal tostrongly on, andfor the diode-connected transistors in the
proposed rectifier is higher than that in the conventional solution
as shown in Fig. 4(c). Therefore, the output current can be larger
than that of conventional pMOS diode-connected transistors.
Both the conventional and proposed rectifiers have been implemented using pMOS transistors with a gate length and width of
20 m and 100 mm, respectively and the measurements results
will be shown in Section IV. These transistors can supply up to
2-W dc power as shown in Fig. 5, which is the highest power
level ever reported.

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Fig. 6. Measured V mismatch for a differential pair in 20-V CMOS process.
(a) Schematic. (b) Measured I –V characteristics.

Fig. 8. The 20-V organic CMOS operational amplifier with FG for variationcompensation. (a) Photograph. (b) Schematics.

Fig. 7. Device structure of 20-V organic CMOS transistor.

C. 20-V CMOS Organic Operational Amplifier With an FG
for Compensation
A major challenge in organic circuit design is to compensate
for the large process variations of organic devices. The offset
voltage in the differential pair of the operational amplifier due
to the device mismatch of organic devices can be much larger
than the sensing voltage generated by the sensing resistor in
Fig. 3. As discussed above, the maximum voltage expected on
the sensing resistor is 0.5 V. On the other hand, the measured
is 1.78 V at an
of 1
A in
standard deviation of
our 20-V organic CMOS process. Fig. 6 shows the worst-casemismatch for a differential pair in this work.
scenario of the
Various techniques for compensating for variation such as
back gate biasing [5], [6] have been reported. However, the backgate voltage of each organic device needs to be continuously
supplied throughout the operation time. To tackle this design
challenge, we employ FG pMOS technology [4] for the input
stage of the operational amplifier to compensate for process
variations.
The device structure of the 20-V organic CMOS transistor
with an FG is shown in Fig. 7. Polyimide is used for the substrate. Gold is used for both the gate and the FG, and is depositedon the substrate. The gate oxide material is parylene and the total
240 nm 240 nm . The orgate oxide thickness is 480 nm
ganic semiconductor materials used for the pMOS and nMOS
are DNTT [7] and NTCDI [8], respectively.

Fig. 8(a) shows a photograph of the 20-V organic CMOS
operational amplifier with an FG to compensate for variation.
Fig. 8(b) shows schematics of the operational amplifier and thecorresponding compensation scheme. The input differential pairof the operational amplifier is composed of two pMOS transistors (M1, M2) with an FG and five IO pads are added to compensate the mismatch.
Both the source and drain are fixed to 0 V during compensation. By applying 60-V, 100-ms-wide pulses to the gate terminal as shown in Fig. 8(b), positive charges are injected intoof the pMOS
the FG, which increases the absolute value ofwith an FG to compensate for variation. The key advantages,
compared with supplying back-gate voltages, include: 1) the
variation can be compensated for using a single high-voltage
source with a fixed voltage (e.g., 60 V in our case); 2) controllability can be achieved by varying the voltage pulsewidth(e.g., 100 ms) and the number of pulses; and 3) once the variation has been compensated for, no external dc voltage sources
are required throughout the operation time.
D. 20-V Pseudo-CMOS-Based 10-b Frequency Divider
A major design challenge in large-scale organic logic circuits
is to ensure a satisfactory noise margin. In our 20-V CMOS
technology, a DNTT-based pMOS has eight times higher carcm Vs than an NTCDI-based nMOS
rier mobility
cm Vs [7], [8]. As a result, the measured CMOS
inverter gain was only 3.2 at 20 V, as shown in Fig. 9(a). The
low gain may lead to retention errors in the latches used inlarge-scale organic logic circuits.
To solve this problem, we designed a frequency divider basedon high-gain pseudo-CMOS inverters [9] instead of CMOS inverters, as shown in Fig. 10. In the divider, nMOS transistors
are only used in CMOS transmission gates, where no gain is required. The pseudo-CMOS inverter uses only pMOS devices asshown in Fig. 9(b). A very high measured inverter gain of 148
and a static noise margin of 6.7 V, as well as a 156-Hz oscillation frequency for a three-stage ring oscillator, can be achieved
simultaneously at a 20-V supply voltage, as shown in Fig. 11.

ISHIDA et al.: 100-V AC ENERGY METER INTEGRATING 20-V ORGANIC CMOS DIGITAL AND ANALOG CIRCUITS WITH A FG

305

Fig. 9. Comparison of schematics and measured inverter gains. (a) CMOS inverter. (b) Pseudo-CMOS inverter.

Fig. 10. Schematic of the proposed pseudo-CMOS-based frequency divider.

Fig. 11. Three-stage ring oscillator with pseudo-CMOS inverter. (a) Photograph and schematic. (b) Measured waveform.

IV. MEASUREMENT RESULTS AND DISCUSSION
A. All-PMOS Full-Wave Rectifier
Both the conventional pMOS diode-connected rectifier andthe rectifier using a cross-coupled pMOS were measured. The
measured circuits are shown in Fig. 4. A comparison of the measurement results for these two rectifiers is shown in Fig. 12. The
pMOS diode rectifier supplies a 2.1-mA output current at 20
V, which is not sufficient for the target specification indicatedin Fig. 12. On the other hand, the cross-coupled pMOS rectifier
increases the output current by 24% to provide an output currentof 2.7 mA at an output voltage of 21.9 V, which is sufficient forour system.
Fig. 13(a) shows the measured waveform of the output
voltage of 21.9 V obtained using the cross-coupled pMOS
rectifier with an output-smoothing capacitance of 100 F. The
output ripple is less than 0.16 V (0.73% of the output voltage)at the target load current of 2.7 mA. Fig. 13(b) shows the measured waveform of the rectifier without the output-smoothing
capacitance. Although amplitude fluctuations due to device
variations are observed, the waveform demonstrates full-wave
50-Hz ac power supply.
rectification of the 100B. 20-V CMOS Organic Operational Amplifier With an FG
for Compensation
Fig. 14 shows the effect of the compensation of mismatch by
charactercharge injection to the FG on the measured

Fig. 12. Measured output voltage versus load current of conventional pMOS
diode rectifier and proposed cross-coupled pMOS rectifier in Fig. 4.

istics of M1 and M2. The measurement and the compensation of
mismatch was 1.5 to
M1 are performed 10 times. The initial
2.0 V, which is unacceptable for amplifying a sensing voltage of
below 0.5 V. Therefore, some kind of compensation of variation
for M1 can be monotonically moved towards
is required.
that for M2 by increasing the number of gate pulses as shown
characteristics of thein Fig. 14(b). As a result, theoperational amplifier can be modified as shown in Fig. 15. By

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 1, JANUARY 2012

0Fig. 15. Measured V
V characteristics of operational amplifier.
(a) Schematic. (b) Measured result.

Fig. 13. Measured waveform of the cross coupled pMOS full-wave rectifier. (a) With output-smoothing capacitance of 100 F. (b) Without outputsmoothing capacitance.
Fig. 16. Measured dependence of operational amplifier gain on the number ofpulses.

Fig. 14. Measured mismatch compensation of a pair of transistors.
(a) Schematic. (b) Measured result.

increasing the number of gate pulses, the characteristic monotonically shifts to the left until the offset is sufficiently small.
Fig. 16 shows the dependence of the differential voltage gain
15 V on the number of pluses derived fromatFig. 15(b). The initial gain of 2.7 (8.6 dB) can be increased to 4.9
200 ms . Fig. 17 shows the(13.8 dB) by applying two pulses
at
15 V on the number of
dependence ofis also shifted from 8.4 to 12.5 V by applying two
pulses.
pulses. In this way, the gain of the operational amplifier can be

Fig. 17. Measured dependence of output voltage of operational amplifier on
the number of pulses.

increased by 5.2 dB using the proposed FG programming, while
the offset is suitably reduced. To increase the differential voltage
gain, the differential transistors must be biased correctly. The
compensation of mismatch is also important for increasing theISHIDA et al.: 100-V AC ENERGY METER INTEGRATING 20-V ORGANIC CMOS DIGITAL AND ANALOG CIRCUITS WITH A FG

307

Fig. 18. Measured frequency response of operational amplifier.

Fig. 20. Measured retention of the compensation by the FG (operational amplifier gain).

Fig. 19. Measured retention of the compensation by the FG (I –V
in Fig. 14).

for M1

amplifier gain. The proposed compensation scheme of injecting
carriers into the FG compensates the device mismatch and improves the gain of the CMOS operational amplifier.
The frequency response of the operational amplifier withoutcompensation was also measured. A 1-V peak-to-peak, 16-V
dc offset sinusoidal wave and a 14.1-V dc signal were used forand, respectively. The measured open-loop gain is
5.5 dB, the bandwidth is 100 Hz, and GBW is approximately
150 Hz as shown in Fig. 18. Although the uncompensated bandwidth is higher than 50 Hz, the open-loop gain after the proposed compensation is still small. If the performance of the organic nMOS transistors such as the driving capability and thedrain current saturation characteristic can be improved, then theperformance of the CMOS operational amplifier will be further
improved.
The retention of the proposed compensation scheme was alsomeasured. Fig. 19 shows the measured time shift of thecharacteristics of M1.
for M1 shifted by 2 V in two
after a month was lower than its initial value. This
weeks.
means that the effectiveness of the compensation is reduced. On the other hand,by the time-dependent degradation of
the measured gain still exhibits good retention after a month asshown in Fig. 20. Once M1 is compensated and balanced with
M2, both M1 and M2 will track together in the same environ-Fig. 21. Pseudo-CMOS-based frequency(b) Schematic. (c) Measured waveform.

divider.

(a)

Photograph.

ment. Therefore, the proposed compensation scheme is still effective for increasing the amplifier gain.
C. 20-V Pseudo-CMOS-Based 10-b Frequency Divider
Fig. 21(a) shows a photograph of a 5-b pseudo-CMOS frequency divider. Fig. 21(b) shows a schematic of the pseudo-

308IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 1, JANUARY 2012

TABLE IKEY FEATURES AND SUMMARY OF PERFORMANCE[2] K. Ishida, T.-C. Huang, K. Honda, T. Sekitani, H. Nakajima, H. Maeda,
M. Takamiya, T. Someya, and T. Sakurai, “100-V AC power metersystem-on-a-film (SoF) integrating 20-V organic CMOS digital andanalog circuits with floating gate for process variation compensationand 100-V organic pMOS rectifier,” in IEEE ISSCC Dig. Tech. Papers,
Feb. 2011, pp. 218–219.
[3] H. Nakajima, S. Morito, H. Nakajima, T. Takeda, M. Kadowaki, K.
Kuba, S. Hanada, and D. Aoki, “Flexible OLEDs poster with gravure
printing method,” in Soc. Inf. Display Dig., May 2005, vol. XXXVI,
pp. 1196–1199.
[4] T. Sekitani, T. Yokota, U. Zschieschang, H. Klauk, S. Bauer, K.
Takeuchi, M. Takamiya, T. Sakurai, and T. Someya, “Organic nonvolatile memory transistors for flexible sensor arrays,” Science, vol.
326, no. 5959, pp. 1516–1519, Dec. 2009.
[5] M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T.
Sakurai, “An organic FET SRAM with back gate to increase static noise
margin and its application to braille sheet display,” IEEE J. Solid-State
Circuits, vol. 42, no. 1, pp. 93–100, Jan. 2007.
[6] H. Marien, M. Steyaert, N. Aerle, and P. Heremans, “An analog organic
ADC on a flexible plastic substrate with 26.5 dB
first-order CT
precision,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 136–137.
[7] T. Yamamoto and K. Takimiya, “Facile synthesis of highly  -extended heteroarenes, Dinaphtho[2,3-b:2’,3’-f]chalcogenopheno[3,2-b]chalcogenophenes, and their application to field-effect transistors,” J.
Amer. Chem. Soc., vol. 129, no. 8, pp. 2224–2225, Aug. 2007.
[8] H. E. Katz, A. J. Lovinger, J. Johnson, C. Kloc, T. Siegrist, W. Li,
Y.-Y. Lin, and A. Dodabalapur, “A soluble and air-stable organic semiconductor with high electron mobility,” Nature, vol. 404, pp. 478–481,
Mar. 2000.
[9] T.-C. Huang, K. Fukuda, C.-M. Lo, Y.-H. Yeh, T. Sekitani, T. Someya,
and K.-T. Cheng, “Pseudo-CMOS: A novel design style for flexible
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2010, pp. 154–159.

16

CMOS frequency divider used to divide the frequency by two.
Owing to the high gain of the pseudo-CMOS inverter, the divider successfully operates at 50 Hz and 20 V as shown in
Fig. 21(c).
Table I provides the key features and a summary of the performance of the proposed 100-V ac energy meter. The energy
meter consists of 609 transistors and its total area excluding
the ac connector is 200 200 mm (unfolded) or 70 70 mm(folded).
V. CONCLUSION
A 100-V ac energy meter based on the SoF concept, which
integrates various devices on a flexible film, was presented.
The system includes key technologies such as a 100-V pMOS
cross-coupled full-wave rectifier to improve the output current
by 24%, a 20-V operational amplifier that compensates theby charge injection into the FG, thus immismatch ofproving the gain by 5.2 dB, and a 20-V pseudo-CMOS-basedfrequency divider. The energy meter based on the SoF is
flexible and therefore can be installed to monitor each ac outlet
simultaneously. The energy meter is expected to be formed
using a low-cost printing process in the future. Organic SoF
integration is expected to pave the way for future low-cost andflexible electronics.
ACKNOWLEDGMENT
The authors would like to thank Prof. K. Takimiya of
Hiroshima University and Dr. H. Kuwabara and Dr. M. Ikeda
of Nippon Kayaku Co., Ltd., for providing the high-purity
DNTT.
REFERENCES[1] Y. Kim, T. Schmid, Z. M. Charbiwala, and M. B. Srivastava, “ViridiScope: Design and implementation of a fine grained power monitoring
system for homes,” in Proc. 11th Int. Conf. Ubiquitous Computing, Sep.
2009, pp. 245–254.

Koichi Ishida (S’00–M’06) received the B.S. degree
in electronics engineering from the University ofElectro-Communications, Tokyo, Japan, in 1998,
and the M.S. and Ph.D. degrees in electronics
engineering from the University of Tokyo, Tokyo,
Japan, in 2002 and 2005, respectively.
He joined Nippon Avionics Co., Ltd., Yokohama,Japan, in 1989, where he developed high-reliability
hybrid microcircuits for aerospace programs. Since
July 2007, he has been a Research Associate with theInstitute of Industrial Science, University of Tokyo,
Tokyo, Japan, where his research interests include low-voltage low-power
CMOS analog circuits, on-chip power supply circuits, and large-area flexible
electronics.
Dr. Ishida is a member of the Institute of Electronics, Information and Communications Engineers of Japan.

Tsung-Ching Huang (S’05–M’09) received the
Ph.D. degree in electrical and computer engineeringfrom the University of California, Santa Barbara, in
2009.
He is now a Senior Design Engineer with TSMC
North America, San Jose, CA. He was a Project
Research Associate with the Institute of Industrial
Science (IIS), University of Tokyo, Tokyo, Japan
from 2009 to 2011. From 2006 to 2008, he wasa summer Intern with ITRI, developing flexible
TFT circuits and displays, and with MediaTek fordeveloping radio frequency integrated circuits for cellular phones. His researchinterests include circuit design, EDA tool development and reliability analysis
for flexible electronics, and low-power mixed-signal VLSI design.
Dr. Huang received Best Paper Award from International Symposium for
Flexible Electronics and Displays in 2007.

ISHIDA et al.: 100-V AC ENERGY METER INTEGRATING 20-V ORGANIC CMOS DIGITAL AND ANALOG CIRCUITS WITH A FG

Kentaro Honda received the B.S. degree in electronic engineering from the University of Tokyo,
Tokyo, Japan, in 2010, where he is currently working
toward the M.S. degree.
His research interests are in the field of low-power
circuit design of the RF transceiver circuits and digital circuits.

Tsuyoshi Sekitani received the B.S. degree from
Osaka University, Osaka, Japan, in 1999, and the
Ph.D. degree in applied physics from the Universityof Tokyo, Tokyo, Japan, in 2003.
From 1999 to 2003, he was with the Institute for
Solid State Physics (ISSP), University of Tokyo.
From 2003 to 2009, he was a Research Associatewith the Quantum-Phase Electronics Center, University of Tokyo. Since 2011, he has been an Associate
Professor with the Department of Electrical andElectronic Engineering, University of Tokyo.

Hiroyoshi Nakajima received the Ph.D. degree inapplied electronic technology from Shizuoka University, Shizuoka, Japan in 2003.
In 2003, he joined Dai Nippon Printing Company,
Ltd., where he is working on development of the flexible organic electroluminescent displays.

Hiroki Maeda received the Ph.D. degree in self-organizing molecular semiconductors from the Tokyo
Institute of Technology, Tokyo, Japan.
Prior to his graduate work, he joined Dai
Nippon Printing Company, Ltd. (DNP) in 1991
as a Researcher with the R&D Center developing
printing-oriented novel LCD devices, such as plastic
LCDs (PLCDs). After five years’ involvement withthe development of backplane for plasma display
panels, he began studying organic semiconductive
materials in 1998. He is currently in charge of R&D
on plastic electronics, especially, device physics of OLED and OTFT.

Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Tokyo, Japan, in 1995,
1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high-speed
digital LSIs. In 2005, he joined the University ofTokyo, Tokyo, Japan, where he is an Associate Professor with the VLSI Design and Education Center.
His research interests include the circuit design ofthe low-power RF circuits, the ultra low-voltage
digital circuits, and the large area electronics with organic transistors.
Dr. Takamiya is a member of the technical program committee for the IEEE
Symposium on VLSI Circuits and the IEEE Custom Integrated Circuits Conference (CICC).

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Takao Someya (M’03) received the Ph.D. degree inelectrical engineering from the University of Tokyo,
Tokyo, Japan, in 1997.
In 1997, he joined Institute of Industrial Science(IIS), University of Tokyo, as a Research Associate
and was appointed a Lecturer of the Research Center
for Advanced Science and Technology (RCAST),
University of Tokyo, in 1998, and an Associate
Professor of RCAST in 2002. From 2001 to 2003,
he was with the Nanocenter (NSEC) of Columbia
University and Bell Labs, Lucent Technologies, asa Visiting Scholar. From 2003 to 2009, he was an Associate Professor with
the Department of Applied Physics and Quantum-Phase Electronics Center,
University of Tokyo. Since 2009, he has been a Professor of the electricaland electronic engineering with the University of Tokyo. His current researchinterests include organic transistors, flexible electronics, plastic integrated
circuits, large-area sensors, and plastic actuators.
Prof. Someya is a member of the IEEE Electron Devices Society, the Materials Research Society (MRS), and the Japanese Society of Applied Physics.

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan, in 1981.
In 1981, he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and SoC Solutions. He has worked extensively
on interconnect delay and capacitance modelingknown as the Sakurai model and alpha power-law
MOS model. From 1988 through 1990, he was a Visiting Researcher with the University of California,
Berkeley, where he conducted research in the field of
VLSI CAD. Since 1996, he has been a Professor with the University of Tokyo,
Tokyo, Japan, working on low-power high-speed VLSI, memory design,interconnects, ubiquitous electronics, organic IC’s and large-area electronics.
He has authored or coauthored more than 400 technical publications including
100 invited presentations and several books and filed more than 200 patents.
Dr. Sakurai is a Fellow of the Institute of Electrical, Information and Communication Engineers of Japan and a STARC Fellow. He will be an executive
committee chair for VLSI Symposia and a steering committee chair for IEEE
A-SSCC from 2010. He served as a conference chair for the Symposium on
VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chair for the
A-SSCC, and VLSI Symposium, an executive committee member for ISLPEDand a program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He was a recipientof the 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, the 2010
IEEE Paul Rappaport Award, the 2010 IEICE Electronics Society Award, the2009 Achievement Award of IEICE, the 2005 IEEE ICICDT Award, the 2004
IEEE Takuo Sugano Award, and the 2005 P&I Patent of the Year Award and four
product awards. He has given the keynote speech at more than 50 conferences
including ISSCC, ESSCIRC, and ISLPED. He was an elected AdCom member
for the IEEE Solid-State Circuits Society and an IEEE Circuits and Systems Society and IEEE Solid-State Circuits Society Distinguished Lecturer.