Reducing IR Drop in 3D Integration to Less Than 1/4
Using Buck Converter on Top Die (BCT) Scheme
Yasuhiro Shinozuka1, Hiroshi Fuketa1, Koichi Ishida1, Futoshi Furuta2, Kenichi Osada2, Kenichi Takeda2,
Makoto Takamiya1, and Takayasu Sakurai1
1
The University of Tokyo, Institute of Industrial Science, 4-6-1 Komaba, Meguro-ku, Tokyo, Japan
2
Association of Super-Advanced Electronics Technologies (ASET), Hachioji, Tokyo, Japan1
E-mail: {sinozuka, fuketa, mtaka, tsakurai}@iis.u-tokyo.ac.jp
Abstract
This paper proposes a method to reduce the supply
voltage IR drop of 3D stacked-die systems by implementing
an on-chip Buck Converter on Top die (BCT) scheme. The
IR drop is caused by the parasitic resistance of ThroughSilicon Vias (TSV’s) used in the 3D integration. The IR
drop reduction and the overhead associated with the BCT
scheme are modeled and analyzed. A 3D stacked-die system
is manufactured using 90nm CMOS technology with TSV’sand a silicon interposer. A chip inductor and chip capacitors
for the buck converter are mounted directly on the top die.
The reduction of the IR drop to less than 1/4 is verified
through experiments.

Keywords
3D integration, TSV, Stacked die, Buck converter, IR
drop, Power integrity, Power supply, DC-DC converter

1. Introduction

IR-drop normalized by VDDL (%)

Recently, 3-dimensional integration based on TSV’s
have been explored extensively for achieving low power andhigh performance to break the limit of single-chip 2D
integration. The TSV and associated bump connection
structure (TSV link) inherently have parasitic resistance andthus the supply voltage is exposed to IR drop due to the TSVlink resistance [1-4]. This is considered to be a stringent
issue in 3D integration since the IR drop quadraticallyincreases as the number of stacked dies increases, whose
detailed analysis is presented in Section 3 of this paper.

The increase of IR drop is shown in Fig.1. The IR drop is
calculated as a function of the number of stacked dies (N)and the total number of TSV’s per die (nL) used for power
delivery including both VDDL and VSS. If allowable IR dropis assumed to be 3% of the nominal power supply voltage(VDDL), it is seen from the figure that hundreds of TSV’s areneeded to make the IR drop within the tolerance. Part of thereason why the problem gets severe is that the IR drop in
VSS lines is additive to the VDD IR drop and the number of
total TSV’s required for the power delivery includes both
VDD TSV’s and VSS TSV’s. In this paper, the IR drop is
defined as the DC voltage drop across VDD lines and VSSlines.
In order to reduce the IR drop due to TSV, a Buck
Converter on Top die (BCT) scheme is proposed in Section
2. In Section 3, The IR drop reduction and the overhead
associated with the BCT scheme are modeled and analyzed.
A fabricated 3D stacked-die system is described in Section 4
and the measurement results are presented in Section 5followed by conclusions in Section 6.

2. Buck Converter on Top die (BCT) scheme
A typical 3D integration with the conventional power
supply scheme is illustrated in Fig.2. All the current is
supplied from a buck converter which is either implemented
on the bottom die or is implemented as a separate die
residing external to the 3D stacked dies. Since the top die
can be far from the power supply circuit, the IR drop getslarge as the current must go through many seriallyconnected TSV’s.

10
nL=50

8

nL=100

TSV’s for VDDL
nL=200nL=5004L

TSV = 30mΩ/via
VDDL = 1V
1

5

10

15

20

C

VDDH

25

Number of stacked dies (N)Fig. 1 Caluculated IR drop in 3D integration. nL is the total
number of TSV’s per die used for power delivery including
both VDDL and VSS TSV’s. Each die is assumed to consume1A.
978-1-4673-4953-6/13/$31.00 ©2013 IEEE

Die N-1

Chipinductor

3% tolerance

2
0

Die N

Chip
capacitor

6

210

Die 2
Buck

VDDL

Die 1

Silicon interposer

Fig. 2 Conventional power supply scheme. The buckconverter on the bottom chip could be on a separate die. The
TSV’s for VSS are omitted for simplicity.

14th Int'l Symposium on Quality Electronic Design

Proposed Buck Converter on Top die (BCT)

L C
Buck

Vdrop

TSV’s for VDDLrTSV( nL 2 )

VDDL

VDDH

Die N

Buck
converterrTSV( nL 2 )VDDLiDie N-1

i
rTSV

VDDH

Buck

VDDL

Die 1

Silicon interposer

Fig. 3 Proposed Buck Converter on Top die (BCT) scheme.
The TSV’s for VSS are omitted for simplicity.
The proposed BCT scheme is depicted in Fig.3. By
adding a buck converter on the topmost die (Die N), thecurrent to an upper half of the 3D integration (Die (N/2)+1 ~Die N) is delivered from the added BCT, while the current
for a lower half (Die 1 ~ Die N/2) is supplied from the buckconverter on the bottom. Each buck converter on the top die
and the bottom die stably supply the specified voltage andthe current to the furthest die (Die N/2, Die (N/2)+1) from abuck converter through less number of TSV’s comparedwith the conventional case. Thus, the maximum IR drop getssmaller and improved. Compared with the direct VDDL
power delivery to the topmost die, the TSV current for VDDH
in BCT is reduced to (VDDL/VDDH) times by the voltage
down conversion from VDDH to VDDL. thereby reducing therequired number of TSV’s for VDDH.
For a general case where each chip consumes different
amount of current, the IR drop improvement and theoverhead by the BCT scheme needs to be calculated case bycase. For example, if the topmost die consumes most of thetotal current, the BCT reduces the IR drop caused by TSV’s
to almost zero. The difficult case for both the conventional
and the BCT arises when all dies consume the same amountof current. This uniformly distributed current consumption
case can be treated theoretically and gives insight to thedesign trade-off of the BCT scheme. Thus, the detailed
discussion for the uniform case is given in Section 3 and it isshown that the maximum IR drop is reduced to less than 1/4of the one observed in the conventional approach.
The overhead of the BCT is the area overhead and thepower loss caused by the added TSV’s to bring the externalhigh voltage (VDDH) to the top die. In Section 3, thisoverhead is shown to be reasonably small. It should be notedthat if the IR drop has to be reduced to 1/4 in theconventional approach, the number of TSV’s should be
increased by a factor four.
A buck converter is used as a DC-DC voltage down
converter, since the buck converter provides high conversion
efficiency at rather high current output among different
types of DC-DC voltage down converters. Unfortunately
though, the buck converter requires a low-resistanceinductor and a large capacitor as a low-pass filter, whichcannot be realized by an on-chip coil and MOS capacitors.

( nL 2 )
Die 2

C

Die 1

L

rTSV

( nL 2 )

Die 2

i

Die N

TSV’s for VDDH

Fig. 4 Equivalent circuit for conventional scheme. Vdrop is
maximum IR drop and is defined in (1). rTSV is a resistanceof a single TSV, nL is the total number of TSV’s per die forboth VDDL and VSS.
Off-chip components, such as a chip inductor and a chipcapacitor, are needed as shown in Figs. 2 and 3. Only on the
top die, it is possible to directly mount the off-chipcomponents and thus in the BCT scheme, a buck converter
is added only on the topmost die.
Since the chip capacitor on the top die can provide µForder of capacitance, which is difficult to realize by on-chip
MOS capacitors, the BCT scheme has an added benefit of
improving dynamic power integrity although this benefit is
not the main target of this paper.

3. Design considerations
The theoretical background for the BCT scheme isestablished in this section. The IR drop reduction and theoverhead associated with the BCT scheme are modeled andanalyzed.

3.1. IR drop reduction by conventional power
supply scheme
The equivalent circuit for the conventional scheme (Fig.
2) is depicted in Fig. 4. The maximum IR drop due to TSV’s(Vdrop in Fig. 4) is given byrrr
Vdrop ( N , nL ) = ( N − 1) i TSV + ( N − 2) i TSV + " + i TSV
nL 2
nL 2
nL 2
rTSV
rTSV
r
+ ( N − 1) i
+ ( N − 2) i
+ " + i TSV
nL 2
nL 2
nL 2
2irTSV(1)=
N ( N −1) ,nL
where N is the number of the stacked dies, rTSV is a
resistance of a single TSV, nL is the total number of TSV’s
per die for both VDDL and VSS, and i is the load current ofeach die.
Equation (1) indicates that the IR drop is inversely
proportional to nL, and hence increasing nL can reduce theIR drop. On the other hand, the power dissipation of TSV’s
decreases by the TSV resistance reduction obtained by theincrease in nL. Therefore, the power of TSV’s is discussed
from here.

VdroprTSV( nL 2 )Buckconverter

Vdrop

rTSV
( nL 2 )rTSV( nL 2 )rTSV( nL 2 )

VDDL

VDDL
i

i
rTSV

i

i

rTSV

( nL 2 )
rTSV

rTSV

( nL 2 )( nL 2 )
rTSV

rTSV

rTSV

( nH 2 )IH( nH 2 )( nH 2 )( nH 2 )

i

i

rTSV

( nL 2 )Buckconverter

rTSV

rTSV

( nH 2 )( nH 2 )

Die N

Die 2

Die 1

Die N/2

rTSV( nH 2 )Die N-1

rTSV( nH 2 )Die N/2+1

VDDH

Fig. 5 Equivalent circuit for proposed BCT scheme. Vdrop is maximum IR drop. nH is the total number of TSV’s per die forboth VDDH and VSS.
Let PTSV,L be the power dissipation of the TSV’s for
VDDL and VSS. PTSV,L is written as
2 r
2 r
r
PTSV , L ( N , nL ) = {( N − 1) i} TSV + {( N − 2) i} TSV + " + i 2 TSV
nL 2
nL 2
nL 2
2 r
2 r
r
+ {( N − 1) i} TSV + {( N − 2) i} TSV + " + i 2 TSV
nL 2
nL 2
nL 2
=

2i 2 rTSV
N ( N − 1)( 2 N − 1) .
3nL

(2)

The total power dissipation of the N-stacked dies isexpressed as(3)
PLOAD = VDDL ⋅ Ni .
From (1), (2), and (3), the ratio of the TSV power to thetotal power of the stacked dies is derived as
PTSV , L 1 Vdrop ( N , nL ) 2 N − 1
(4)
= ⋅
⋅
PLOAD 3VDDL
N .
When N is sufficiently large, this equation can beapproximated to
PTSV , L 2 Vdrop ( N , nL )
(5)
 ⋅
.
PLOAD 3
VDDL
When nL increases by A times, the IR drop is reduced by
1/A times according to (1). In this case, the power loss dueto the TSV increase (PLOSS) is given by
PLOSS PTSV , L ( N , AnL ) − PTSV , L ( N , nL ) ⎛ 1 ⎞ PTSV , L== ⎜ − 1⎟
PLOAD
PLOAD
⎝ A ⎠ PLOAD⎛1⎞ 2 Vdrop ( N , nL )
 ⎜ − 1⎟ ⋅ ⋅VDDL⎝A ⎠ 3.

(6)

For example, in order to reduce the IR drop (Vdrop/VDDL)from 10% to 2.5% (A=4), PLOSS decreases by 5%, whereas
nL increases by 4 times (300%). This means that a huge area
overhead to reduce the IR drop is required in theconventional power supply scheme.

3.2. IR drop reduction by proposed BCT scheme
In the conventional power supply scheme, the TSV area
overhead is huge as described in the previous section. On
the other hand, the proposed BCT scheme can reduce the IR
drop with moderate overheads. The overheads in the BCT
scheme are discussed in this section.
In this paper, TSV’s for VDDH are added to the TSV’s for
VDDL, that is, the number of TSV’s for VDDL (nL) does notchange. Fig. 5 shows the equivalent circuit for the proposed
BCT scheme. Let Vdrop(conv) and Vdrop(prop) be the IR drops inthe conventional and the proposed scheme, respectively.
Vdrop(conv) and Vdrop(prop) are expressed using (1) as(7)
Vdrop (conv) = Vdrop ( N , nL )Vdrop (prop) = Vdrop ( N 2, nL ) =2irTSV N ( N − 2 )
.
nL
4

(8)

Therefore, from (7) and (8), the IR drop reduction is
given by

Vdrop (prop)
Vdrop (conv)=

N −2 11⋅ <N −1 4
4.

(9)This equation indicates that the BCT scheme can reduce theIR drop to less than 1/4.
In order to achieve such IR drop reduction, the following
overheads are required; 1) area overhead due to additional
TSV’s for VDDH and VSS, and 2) power loss caused by theadditional TSV’s. From here, these overheads areanalytically investigated.
Let PTSV,H be the power dissipation of the additional
TSV’s for VDDH and VSS. PTSV,H is given byr
4r
PTSV , H = 2 × TSV ( N − 1) ⋅ I H 2 = TSV ( N − 1) ⋅ I H 2 , (10)nH 2nH
where nH is the number of TSV’s per die for both VDDH and
VSS, and IH is the input current of the buck converter.

TSV area overhead nH/nL (%)

100
VDDH = 3.3V
VDDL = 1.2V

80

Die 2 (face-up)
Die 1 (face-up)

η=0.8
η=0.7

Silicon interposer

Vdrop (conv) VDDL = 10%(Vdrop (prop) VDDL = 2.5% )60

Vdrop (conv) VDDL = 5%
(Vdrop (prop) VDDL = 1.25%)

40
35%

20

3%
0
0

2

4

6

8

10

TSV power overhead PLOSS PLOAD (%)

TSVFig. 6 TSV area and power overheads in IR drop reduction
by BCT scheme. It is assumed that N is sufficiently large.

50μm

Die 2

The input power (Pin) and the output power (Pout) of thebuck converter are written as(11)
Pin = VDDH ⋅ I H ,Pout =PLOAD VDDL ⋅ Ni
=
,
2
2

(12)

Pout = η Pin ,(13)

where η is the efficiency of the buck converter. Strictly
speaking, the input voltage of the buck converter on the top
die is slightly lower than VDDH due to the resistance of
TSV’s for VDDH. For simplicity, the voltage drop is ignoredin this paper. From (11), (12), and (13), IH is expressed asP(14)
I H = LOAD
2ηVDDH .
Here, the power loss of TSV’s for VDDH is only
considered for simplicity. From (10) and (14), the ratio of
the power loss (PLOSS) to the total power is derived as
PLOSS PTSV , H rTSV PLOAD ( N − 1) ⎛ nL ⎞ 1
(15)
=
=
⎜
⎟ .
PLOAD PLOAD
η 2VDDH 2nn⎝ H⎠ LThe following equation is obtained from (3) and (12).
⎛ Vdrop (prop) ⎞1
2VDD 2=⎜⎟nL rTSV PLOAD ( N − 2 ) ⎝ VDDL ⎠ .

(16)

Therefore, the following equation is derived from (15) and(16).
2 N − 1 ⎛ Vdrop (prop) ⎞ ⎛ VDDL ⎞nH PLOSS
⋅
= 2⋅
⋅⎜
⎟⎜
⎟
nL PLOAD η N − 2 ⎝ VDDL ⎠ ⎝ VDDH ⎠2=

1 N − 2 ⎛ Vdrop (conv) ⎞⎛ VDDL ⎞
⋅
⋅⎜
⎟⎜
⎟
2η 2 N − 1 ⎝ VDDL ⎠⎝ VDDH ⎠ .

2

(17)
(18)

In this equation, nH/nL and PLOSS/PLOAD denote the area andpower overheads due to the additional TSV’s, and thisequation shows a trade-off relation between them. Withsufficiently large N, (17) and (18) can be approximated toFig. 7 Cross sectional view of 3D integrated system. The
upper photo is a global view and the lower photo is amagnified view around a TSV.
2 ⎛ Vdrop (prop) ⎞⎛ VDDL ⎞nH PLOSS
⋅
 2⎜
⎟⎜
⎟
nL PLOAD η ⎝ VDDL ⎠⎝ VDDH ⎠2=

1 ⎛ Vdrop (conv) ⎞ ⎛ VDDL ⎞⎜⎟⎜⎟2η 2 ⎝ VDDL ⎠ ⎝ VDDH ⎠ .

2

(19)
(20)

Fig. 6 illustrates the trade-off relation between the areaand power overheads with sufficiently large N when VDDH
and VDDL are 3.3 and 1.2V, respectively. For example, when
η is 0.8, the area of TSV’s increases by 35% with 3% TSV
power overhead to reduce the IR drop from 10% to 2.5%.
This indicates that the IR drop improvement by a factor offour is possible with a reasonable overhead by the BCT
scheme.

4. Fabricated 3D stacked-die system
The details of a fabricated 3D stacked-die system aredescribed in this section. First, the technology aspect issummarized. The cross sectional view of the fabricatedstacked dies and silicon interposer is shown in Fig. 7. Twoface-up dies are stacked on top of a silicon interposer with a
via-last process. The diameter of the TSV is 20μm and theminimum pitch of the TSV’s is 50μm. The resistance of a
TSV link is 29mΩ (typical). In this 3D integration
technology, all dies are face-up and the off-chip components
are mounted on the surface of the top die. When the top die
is face-down, the off-chip components will be mounted at
the back of the top die through TSV’s.

VDDL8

Die 8

VDDL7

Die 7

VDDL6

Die 5

VDDL4

Die 2

VDDL1

Buck
converter
and
load

Die 1

Silicon interposer(a) Actual stacked-die setup
VDDL8

VDDL6
VDDL4

VDDL2
Die 2

VDDL7
VDDH

Die 1

5mm

VDDL1

Fig. 10 Two stacked dies using TSV’s are mounted on topof a silicon interposer.

VDDL3
VDDL5

Silicon interposer(b) Emulated setup
Fig. 8 8-die stack is emulated by making current go
through TSV’s repeatedly. In the figures, many parallel
vias are expressed as one via for simplicity.
Buck converteron top die (BCT)
Controller

Off-chipDistributed loads among
8 stacked dies

VDDH

Chip capacitor (COUT)

RTSV1

Chip inductor (L)L

Clk

CIN COUT
RTSV2

5mm

Die 3

VDDL2

L C
Buck

2.1mm

Die 4

VDDL3

VDDH

SiliconInterposer

Die 6

VDDL5

3.0mm

L C
Buck

VDDL8 RTSV VDDL7 RTSVILOAD8ILOAD7

RTSV

RTSV

RTSV V

2 stacked dies
(90nm CMOS)

DDL1

ILOAD1

RTSV

Chip capacitor (CIN)
5mm

Silicon interposer

RTSV3

Fig. 9 Circuit diagram of 3D stacked-die system.
The technology used to implement circuits is 8-metal,
90nm CMOS. The typical operation voltage for logictransistors is 1.2V while I/O transistors accept typically
3.3V. Thus, 3.3V is used for VDDH and 1.2V for VDDL in the
3D stacked-die system design.
Although only two dies are stacked physically, 8-die
stack case (Fig. 8 (a)) is emulated by the daisy chain of
TSV’s in two stacked dies (Fig. 8 (b)), where the current go
through dies repeatedly. The circuit diagram of the 3D
stacked-die system is shown in Fig. 9. VDDH is 3.3V andVDDL8 is 1.2V. A constant current load is emulated by atransistor in the saturation region. Each VDDL (VDDL1 ~VDDL8) has a current load to emulate the current consumed
by the load circuits in each die. The typical current of thecurrent load is 200mA and the corresponding output currentof the buck converted is 1.6A (= 200mA x 8).
A microphotograph of the fabricated two stacked diesmounted on top of a silicon interposer is shown in Fig. 10.
The silicon interposer is needed to accept 50µm pitch TSV’s,
which cannot be realized by a PCB board whose design rule
is loose. The die size is 5.0mm x 5.0mm. Two identical buck

PCB

Fig. 11 Photograph of assembled system on a PCB board.
Chip inductor and chip capacitor are mounted directly on
top of stacked dies at the center of the photo.
converters are implemented on a die to expect yield
improvement in this 3D stacked-die system.
The photo in Fig. 11 shows an assembled 3D stacked-die
device. A chip inductor and two chip capacitors are directly
mounted on the top die. The blue part in the picture is asilicon interposer.
The chip inductor for a buck converter is 3.9nH in
inductance with 40mΩ parasitic resistance, whose size is 1.6
x 0.8 x 0.8mm3 and the chip capacitor is 1µF in capacitancewith the size of 1.0 x 0.5 x 0.5mm3. The same chip capacitor
is also placed at the input terminal of the buck converter
signified as CIN in Fig. 9. These values are chosen to
optimize the buck converter design following the design
theory described in [5].

IR drop from VDDL8 (mV)

0

-12mV
-10

Proposed

-78%

-20

-55mV

-30
-40

Conventional-50

Measured
Simulated-60
VDDL8 VDDL7 VDDL6 VDDL5 VDDL4 VDDL3 VDDL2 VDDL1

Position of VDDL

Fig. 12 Measurement setup.

Fig. 13 Measured IR drop and simulated results.

5. Measurement results
The whole measurement setup is shown in Fig. 12. The
estimated efficiency of the buck converter is 72% from themeasured data. The efficiency of the buck converter could
be further improved with more advanced design practice.
The chopping frequency of the buck converter is 62MHz.
The adopted control scheme for the fabricated buckconverter is simple without any feedback control.
Fig. 13 shows the measured and simulated data. The
simulation results are obtained using SPICE. Although thevoltage of only selected locations can be monitored in the
manufactured 3D stacked-die system due to TSV constraints,
the simulation results can be used to extrapolate themeasured points since the simulation results agree very wellwith the measured results as is seen in Fig. 13. It is shownthat the proposed scheme achieves 78% decrease in IR
voltage drop compared with the conventional approach. Thatis, the IR drop is reduced to less than 1/4 by introducing the
BCT scheme. The 78% reduction is consistent with (9) with
N = 8.

6. Conclusions
In this paper, the Buck Converter on Top die (BCT)
scheme is proposed and the theory for the IR drop
improvement and the overhead associated with the BCT
scheme is elaborated. It is revealed that the IR drop
improvement by a factor of more than four is possible with areasonable overhead by the BCT scheme. It is worth
mentioning that the number of TSV’s is to be quadrupled for
reducing the IR drop to 1/4 in the conventional approach.
A 3D stacked-die system is fabricated and theeffectiveness of the proposed BCT scheme is demonstrated
through measurements. For the future when the number ofstacked dies is increased, the importance of the proposed
scheme will become of much more importance.

Acknowledgements
This work was entrusted by NEDO “Development of
Functionally Innovative 3D-Integrated Circuit (Dream Chip)
Technology” project that is based on the Japanese
government's METI “IT Innovation Program”.

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[2]

[3]

[4]
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