3D-Structured On-Chip Buck Converter forDistributed Power Supply System in SiPs
Makoto Takamiya12, Kohei Onizuka2, and Takayasu Sakurai2

Abstract— An on-chip buck converter with 3D chip stacking is
proposed and the operation is experimentally verified. The
manufactured converter achieves a maximum power efficiency of
62% for an output current of 70mA with a switching frequency of200MHz and a 2x2mm on-chip LC output filter in 0.35µm CMOS.
The use of glass epoxy interposer to increase the maximum power
efficiency up to 71.3%, and the power efficiency dependence on
the filter inductor are also discussed.

3100

2.580

2Precision analog/RF

Performance analog/RF 40

1High performance logic

200.5

Lowpower logic

02005

I. INTRODUCTION
Recently System-on-a-Chip (SoC) and System-in-a-Package(SiP) are getting more and more interest as major integration
technologies. They are often used to integrate various types ofcircuit blocks from processors and memories to analog circuits.
Each block demonstrates a different optimum supply voltage(VDD) and the difference tends to increase as the technology
scales. For example, memory and analog circuits tend to preferhigher voltage compared with logic blocks. Fig.1 shows theVDD trends for precision analog/RF, performance analog/RF,
high performance logic and low-power logic with the design
rule trends according to the International Technology Roadmapfor Semiconductors (ITRS) 2006 Update [1]. Multiple-VDD
implementation is therefore required in low-power andhigh-performance systems. Moreover, supply voltage issometimes tuned in time to achieve lower power consumption,
which is called dynamic voltage scaling. The supply of manydifferent and dynamically scaled voltages from outside thepackage gives rise to much overhead in area. The power line
integrity, including IR drop and noise, becomes an issue as well.
The distributed on-chip power supply circuits are useful forsolving these problems. The concept of the distributed power
supply is shown in Fig.2. High voltage is distributed by a main
power grid and is then converted to the lower voltages at thevicinity of the target blocks by distributed on-chip voltage
converters. This approach reduces cost and power integrity
issues.
For DC-DC converters, linear regulator, buck converters andswitched capacitor converter are well known circuits. A buckconverter requires large passive elements of inductance andcapacitance (LC) for an output filter but it shows a higher
power efficiency than a linear regulator. A switched capacitor
converter also needs large capacitors and one more drawback isthat the output voltage levels are limited by the ratios ofprepared capacitors. That is not very suitable for low-power
dynamic voltage scaling systems.

978-1-4244-1811-4/08/$25.00 © 2008 IEEE60

1.5Design rule (nm)

VLSI Design and Education Center and 2Institute of Industrial Science, University of Tokyo, Tokyo, Japan

Power supply voltage (V)12010Year

2015

02020

Fig. 1. Supply voltage trend with design rule trend according to ITRS.
Interposer
L&C
cell array
Pads &bumps
Sensor, MEMS,High voltage
generation,
Analog, RF etc.
(3D stacked)

Power supply& other wires
Inductors
Capacitors
THV’s

Embedded

Package
Stacked memories(thinned)

Parallelprocessors withown DC-DC
converters

BasechipFig. 2. Concept of distributed power supply system.

In case of the buck converter, high switching frequency ispreferable for smaller L and C but the power efficiency isdegraded by the dynamic power dissipated by switchingtransistors at high frequency. Low quality factor (Q) of air-coreand on-chip inductors also degrades the power efficiency. High
inductance is good for high Q but is not easy to obtain on a chip
because of the area limitation and even if high magnetic
permeability material is introduced on a chip, high-µ property
is usually lost at high frequency. A couple of integrated buckconverters have been reported in recent years however, they are
to be sought through, focusing on cost issues and package
friendliness.
II. POWER EFFICIENCY ANALYSIS
A. Circuit Model
In order to implement on-chip buck converters for on-chip
power supply systems, the two following conditions should bemet. First, all elements of the converter must be integrated atleast in a package. Secondly, the implementation cost per one
voltage domain must be minimized while maintaining high

100

RS
LF

RN

CBVOUTZL

CFFig. 3. Simple circuit model of buck converter including parasiticelements.

power efficiency. To maximize the power efficiency, the power
loss must be minimized. The major components of power loss
are classified into three parts: dynamic switching loss of theswitching transistors, resistive loss of the switching transistors
and the resistive loss of the inductor as shown in Fig.3 [2].
The theoretical maximum power efficiency is derived asformula (1) [3].
POUTη=POUT + PLOSS==(1)V IN DI LRC
VIN DI L + V IN I L 3 24 0 0 D (1 − D )
τL

90
80
70

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Duty cycle D

1Fig. 4. Maximum power efficiency dependence on D and process
technology.
100

D=0.9
D=0.7
D=0.5
D=0.39080

D=0.1706050
01−1 / 3
1 + ατ L.

90nm
130nm
180nm
350nm

6050
0Power efficiency (%)

RPPower efficiency (%)

VINOn-chip
50Interposer
100

90nm CMOS

150200τL (ns)250300Fig. 5. Maximum power efficiency dependence on τL in several duty
cycles.

where
R0 C 0 =τL =( DR C + (1 − D )R C ) ,2PPNNLRS .

(2)
(3)

Here, POUT and PLOSS represent the output power and the totalpower loss. D denotes the duty cycle which equals to VOUT/VIN
where VIN and VOUT are input and output voltages. IL signifies
the load (output) current. α is a function of R0C0 and D, and canbe a constant when the process technology and D are fixed. CP,CN, RP, and RN represent parasitic capacitances and parasitic
series resistances per unit gate length of PMOS (high-side) andNMOS (low-side) switching transistors. τL is a figure of meritof the output filter inductor, L and RS being whose inductanceand parasitic series resistance.
B. Efficiency Dependence on Technology
As seen from (1), the smaller R0C0 and the larger τL are betterfor higher power efficiency. R0C0 is shown to be roughly
proportional to the product of effective conduction resistanceand effective switched capacitance per unit gate width ofswitching transistors. They reduce as the process technology
scales down. Fig.4 shows the calculation results of themaximum power efficiency dependence on D and process
technology (90, 130, 180, 350-nm CMOS) when τL=10ns
which is a nominal value for on-chip planar inductors. It would
be better to use the most scaled transistors for high conversion
efficiency.
For planar inductors, the maximum τL is fixed and mainly

978-1-4244-1811-4/08/$25.00 © 2008 IEEE

determined by the metal thickness. The thicker the metal layer
is, the larger the maximum τL is. Fig.5 shows the calculation
results of the maximum power efficiency dependence on τL inseveral duty cycles assuming 90nm CMOS technology.
Especially when D is small, it is valuable to use an inductor
whose τL is large. In case of an on-chip inductor, the maximum
value of τL is roughly 10ns independent of the process
technology. On the other hand, the values of τL larger than
100ns are achievable by applying interposers with thick metal
layers. Thus the inductor is not necessarily fabricated by using
the most advanced technology which is expensive.
In addition to the inductor, fabrication cost of on-chip MOS
capacitor per unit capacitance increases as technology scales.
III. CIRCUIT IMPLEMENTATIONS
A. “Two Chips” Implementation
According to the discussions in the previous section, it isreasonable to implement active elements and output filter on
separate die whose process technologies are different. By
stacking two chips face-to-face and connecting them via metal
bumps, a buck converter for on-chip distributed power supply
systems can be fabricated in a well balanced manner for best
cost and power tradeoff. To demonstrate the feasibility of thestacked-chip buck converter, an on-chip buck converter isdesigned in 0.35-µm CMOS for upper and lower chips. The
lower chip could be manufactured by 90-nm or more advanced
technology for the higher efficiency but this test chip is to show
the feasibility of the stacked-chip approach. Fig.6 shows thecircuit diagram of the test converter.

Output
RingOscillator
Triangular
Wave
Generator

Off-chipController

4.0Pads andMetal Bumps

3.0
2.0

Ripple<±10%
T = 5nsf = 200MHz

1.0

Vref+-[V] 0Upper
Chip

Lower Chip

Fig. 9. Output voltage waveform for VOUT=1.86V and IL=60mA.

Fig. 6. Test circuit diagram of stacked-chip implementation of buckconverter.

8070PAD
Efficiency (%)

602mmCap1nF

504030Measured200

Chip for output filter
ResinLower chip
(Active elements & load circuits)

Bumps

Chip foractive elements

Pads

(a)
(b)
Fig. 8. (a) 3D-structred buck converter and (b) its cross-sectional diagram.

The buck converter with the stacked-chip implementation was
fabricated and measured. Fig.7 shows the chip
microphotograph of the output filter on the upper chip. The
outer diameter of the filter equals to that of the filter inductor
dOUT, which is set at 2x2mm by assuming that 10mm-squarechip can have 25 voltage domains. 6.8x6.9mm chip with 7voltage domains has already been presented [4].
The inductance is estimated by a simple formula from [5] andthe calculated value in this work is 22nH when the sheet
resistance is about 0.02Ω/□. The open space at the center of theinductor is filled with a MOS capacitor for the output filter.
Area efficiency is more important than linearity for the filter
capacitor, because the output voltage does not change
dynamically in a normal operation. From that aspect, MOS
capacitor is more suitable than any other types of on-chip
capacitors like Metal-Insulator-Metal (MIM) capacitor orpolysilicon capacitor. The obtained capacitance is about 1nF.
Under those conditions, the switching frequency was chosen to200MHz. The gate widths of the switching transistors wereoptimized at IL=60mA.
Fig.8 shows the measurement setup and its cross-sectional
diagram. The pad size and the effective bump diameter of thisexperimental setup are 200x200µm and 150µm, respectively.
Micro bumps whose diameter is 30µm and whose resistance is978-1-4244-1811-4/08/$25.00 © 2008 IEEE

0204060
Output Current (mA)

80Fig. 10. Simulated and measured power efficiency for VOUT=2.3V and
f=200MHz.

Fig. 7. Chip microphotograph of the output filter.

Upper chip(Output filter)

Simulated(HSPICE)

10

as low as 14mΩ/bump have been realized in industry
environments [6] and can be used instead for further smallerarea.
The output waveform in Fig.9 shows VOUT=1.86V at IL=60mA.
The measured voltage ripple is smaller than ±10%. Fig.10
shows the simulated and measured power efficiency with
VOUT=2.3V for an output current range from 20mA to 70mA.
The maximum efficiency of 62% is achieved for 70mA output
current. The measurement results compare well with theHSPICE simulation results. The simulation considers all theparasitic elements including the inductor parasitic resistance of
2.5Ω, and the inductor input-to-ground capacitance of 25pF.
B. “Two Chips + Interposer” Implementation
In order to further increase the efficiency, it is effective to use
inductors whose τL is higher than that of the previous inductors.
A thin-film inductor surrounded by magnetic core material as
proposed in [7] can be a solution but is expensive.
Implementing the inductor on a glass epoxy interposer is aneffective yet inexpensive solution.
The structure shown in Fig.11 is assembled using a newly
introduced interposer and the same lower and upper chipspresented in the first half of this section. In this implementation,
only a capacitor is used on the upper chip.
Fig.12 shows an inductor array on generic Flame Resistant 4(FR-4) glass epoxy interposer with two metal layers. The
circled inductor in the array, which achieved the minimum
metal spacing in the trial manufacture, is used for themeasurement. The metal thickness on the interposer is 30µm,
the substrate thickness is 100µm, and the diameter of thethrough-hole via is 100µm. This implementation increases τLby 30 times compared with the case of an on-chip inductor. The
outer diameter of the inductor is increased by 10% to achieve
the same value of on-chip inductance because the minimum
spacing of metal lands on glass epoxy is larger than that ofon-chip interconnects. The permittivity of the glass epoxy isChip for
filter capacitor

80

Interposer for
inductor

Resin70

Resister+10%60

SubstrateMetalpattern
Bumps

Chip foractive elements

Efficiency(%)

Through-holevias
Pads

Fig. 11. Cross-sectional diagram of “two chips + interposer”
implementation.

50403020Glass epoxy inductor
On-chip inductor

10002040
60
Output Current (mA)

80

Fig. 14. Measured efficiency comparison between two types ofimplementations.

improved by 5-14% depending on the output current comparedwith the on-chip implementation. The maximum power
efficiency of 71.3% is achieved at an output current of 60mA.
The possible reason that the efficiency does not improve themost at 60mA, is that the switching transistors are not changed
optimally according to the τL characteristic of newly
implemented inductor.

≈2mm
Fig. 12. Manufactured inductor array on glass epoxy interposer.
1025ZB

Port1ZBZAPort2IV. CONCLUSIONS
Rs(Ω)

L(nH)

20
15

5

10
5000100 200 300 400 500
f (MHz)(a)(b)
Fig. 13. (a) Equivalent model for inductance and resistance extraction(b) Measured inductance and resistance of fabricated inductor.

generally more than four times higher than SiO2, however, theparasitic capacitance between both sides of the interposer canbe negligible. That is because the substrate thickness is large
enough compared with the line width. S-parameters of thefabricated inductor were measured using a test element group
and a network analyzer. Fig. 13 (a) shows the equivalent model
to extract the inductance and the parasitic series resistance of
the inductor from the measured S-parameters. Fig.13 (b) showsthe extracted characteristics of the inductor using formula (4).
Z A = Re Z A + j Im Z A = RS + jωL.

(4)

Measured inductance and τL were 18nH and 100ns at 200MHz,
respectively. The value of τL at DC is more than 20 times larger
than that of the previous on-chip inductor. The parasitic
resistance increases rapidly because of skin effect in the highfrequency region over 200MHz however, the characteristics
below 200MHz are important in this application. The skindepth of the metal wire at 500MHz is assumed to be smaller
than 3µm. The inductance decreases gradually as frequency
increases, because of the current concentration caused by skineffect.
Fig.14 shows the comparison of measured power efficiency
between two types of implementations of “two chips” and “twochips + interposer” for VIN=3.3V and VOUT=2.3V.
The power efficiency with the glass epoxy inductor is978-1-4244-1811-4/08/$25.00 © 2008 IEEE

An on-chip buck converter with stacked-chip implementation
which is suitable for low-cost low-power distributed power
supply systems has been designed and fabricated for the firsttime. The switching frequency is optimized and chosen to be
200MHz. 62% power efficiency is measured for an output
current of 70mA, which verifies the feasibility of this approach.
By utilizing a glass epoxy interposer for a filter inductor, it isshown by experiment that the power efficiency can beincreased to 71.3%.
ACKNOWLEDGMENT
This work is supported by VLSI Design and Education Center (VDEC), theUniversity of Tokyo in collaboration with Rohm Corporation, Toppan Printing
Corporation and Cadence Design Systems, Inc.

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