ISSCC 2002 / SESSION 11 / TD: RF/HIGH-SPEED TECHNOLOGIES / 11.2

11.2

An On-chip 100GHz-Sampling Rate 8-channel
Sampling Oscilloscope with Embedded Sampling
Clock Generator

Makoto Takamiya, Masayuki Mizuno, 1Kazuyuki Nakamura
NEC Corp., Kanagawa, Japan1
now with Kyushu Institute of Technology, Fukuoka, Japan
Signal-integrity degradation caused by such factors as supply(di/dt) noise, substrate noise, and crosstalk between interconnects
is a critical concern because it can restrict performance advancesin LSIs. To maintain signal integrity, on-chip signal waveforms
must first be accurately measured to get an in-depth perspectiveof the complicated physical phenomenon of LSIs. The bandwidthof on-chip signals, however, is too wide for an external oscilloscopealone to measure them reliably, making on-chip embedded measurement circuits, such as sampling oscilloscopes, indispensable.
For conventional sampling-type measurement circuits, an off-chippulse generator for a sampling clock is necessary [1,2]. In thiscase, it is difficult to maintain a high sampling rate, because thesampling rate is degraded by variations in the skew between sampling clock signal and signals to be measured. Furthermore, theinput range of conventional sampling-type measurement circuits
is limited by ground voltage levels and supply voltage levels [1].
Thus, such circuits are not suitable for signal-integrity checks,
because their voltage levels overshoot supply-voltage levels andundershoot ground-voltage levels. Conventional comparator-based
sampling-type measurement circuits are also unsuitable, because
they require complicated measurement procedures [2]. An easy-touse 100GHz-sampling-rate sampling oscilloscope macro addresses
these problems. It features 1) embedded small-area phase-interpolated sampling clock generators to achieve 100GHz sampling
rates, 2) charge-sharing sampling heads that are able to capture
waveform overshoots and undershoots, covering a wide range of
input-voltage levels.
Figure 11.2.1 shows a block diagram of the sampling oscilloscope
macro, which contains eight sampling heads (SH), a samplingclock generator (SCG), and an output buffer. The improved SH
compared with Reference [2] has S2, S3, and C2 that provide awide -0.3V to Vdd+0.3V input range. C1 samples measured voltage (Vmea), C2 reduces the range of Vmea to within the input range(Vamp) of the amplifier in its SH, and C3 holds the measured voltage level. When S1 and S3 are closed; S2 and S4 are opened, thevoltage in C1 becomes equal to Vmea, while that in C2 becomesequal to the bias voltage (Vbias ~ Vdd/2), which is the center valueof the input range of the amplifier in the SH. When S1 and S3are opened; S2 and S4 are closed, C1, C2, and C3 share theircharges among one another. By adjusting C1, C2, and C3, Vamp
can be made to lie within the input range of the amplifier in theSH. In this way, the SH is able to handle signals from -|Vtn| toVdd+|Vtp|. However, a calibration between Vmea and the output
voltage is necessary, because Vmea may be distorted by switchinginduced charge injection and by non-linearity of the amplifier.
Figure 11.2.2 shows frequency characteristics of the SH. The
bandwidth, determined both by the sampling-rate (1/∆Τ) and byswitches and capacitors in the SH, is 6.4GHz. Additional S2, S3,and C2 in Figure 11.2.1 achieve 2x bandwidth. Figure 11.2.2 also
shows simulated operation of the sampling oscilloscope macro.
As may be seen, 1) the sampling-clock cycle time must be ∆Τlarger than that of the input-signal cycle time (Τ) so that the output time scale is scaled up T/∆Τ times of the input signal, and 2)
the output waveform that can be obtained at one time is only aportion of the entire input-signal waveform. Here, the sampling• 2002 IEEE International Solid-State Circuits Conference

rate (1/∆Τ) must not be made dependent on input clock frequency. Instead of a PLL design for the SCG, a delay-line design asshown in Figure 11.2.3 is used, since this allows generation of aconstant ∆Τ irrespective of the input clock frequency, which cannot be done with a PLL design. Further, a PLL design offers lessportability and requires a larger area for a loop filter.
The measurements are carried out according to the following procedure: 1) the offset-delay generator (zero to 7ns in 1ns steps) sets
an offset delay of 0ns; the fine-delay shifter clips waveforms fromzero to 1.27ns (i.e., to 127 times the 10ps delay) by 10ps-step fromthe SH input waveforms as shown in Figures 11.2.2 and 11.2.3.
The waveforms from 1ns to 1.27ns is a tab for sticking. 2) The offset-delay generator sets an offset delay of 1ns. The fine-delay
shifter clips waveforms from 1ns to 2.27ns from the SH input
waveforms. The two sequential measurements overlap slightly(0.27ns). 3) Eight waveforms (A) through (H) in Figure 11.2.3 canbe successfully connected with tabs for sticking, thus eight iterations expand the range of measuring waveforms to 8.27ns (i.e., to1.27ns of the fine-delay shifter plus 7ns of the offset-delay generator). Here, 10ps delay (∆Τ) is generated by an interpolation of twosignals with a 160ps delay difference by two cascaded phase interpolators [3,4]. This 10ps delay shift corresponds to a 100GHz sampling rate. While average ∆Τ may deviate slightly from 10ps due
to wafer-to-wafer device variations or to environmental changes,
this is not a serious concern because the average ∆Τ is derived
experimentally by performing a calibration.
Figure 11.2.4 shows a micrograph of a chip fabricated using a
1.2V 0.13µm CMOS process with 6-layer Cu metallization. The
test chip contains the sampling oscilloscope macro and a noise
source. This noise source contains 4k flip-flops and 84k inverters
and its activation rate can be varied. Each SH probes one each of
the clock lines, the supply lines, and the ground lines. To prevent
supply noise and substrate noise from affecting the oscilloscope
macro itself, supply and ground lines are separated from thenoise source and 910pF on-chip decoupling capacitors are added.
SH area is 1,550µm2, while SCG area is 23,600µm2, which is only
one tenth to half of conventional PLLs. The sampling macro consumes 32mW at 500MHz.
Figure 11.2.5 shows a measured calibration function between SH
input voltage and oscilloscope output voltage. A wide input range
is demonstrated. Figure 11.2.6 shows the measured supply voltage noise and ground voltage noise. Both overshoot and undershoot are observed at the clock edges. This measurement shows
the result of adjusting the delay of the offset-delay generator tooverlap multiple time-shifted outputs. Figure 11.2.7 shows measured clock signals with and without the decoupling capacitors,
showing that the capacitors successfully reduce the noise.
References:[1] M. Nagata, et al., “Reduced Substrate Noise Digital Design for
Improving Embedded Analog Performance,” ISSCC Digest of TechnicalPapers, pp.224-225, Feb. 2000.
[2] R. Ho, et al., “Application of On-Chip Samplers for Test andMeasurement of Integrated Circuits,” Dig. of Symp. on VLSI Circuits,
pp.138-139, June 1998.
[3] K. Yamaguchi, et al., “2.5GHz 4-phase Clock Generator with Scalable
and No Feedback Loop Architecture,” ISSCC Digest of Technical Papers,
pp.398-399, Feb. 2001.
[4] B. W. Garlepp, et al., “A Portable Digital DLL for High-Speed CMOS
Interface Circuits,” IEEE J. of Solid-State Circuits, vol. 34, pp. 632-644,
May 1999.

0-7803-7335-9©2002 IEEE

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• 2002 IEEE International Solid-State Circuits Conference

Figure 11.2.6: Measured on-chip supply and ground voltages.

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• 2002 IEEE International Solid-State Circuits Conference

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• 2002 IEEE International Solid-State Circuits Conference

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• 2002 IEEE International Solid-State Circuits Conference

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• 2002 IEEE International Solid-State Circuits Conference

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