Proceedings of the 35st International Symposium on Power Semiconductor Devices & ICs
May 28 - June 1, 2023, Hong Kong, China

Gate Driver IC with Fully Integrated Overcurrent
Protection Function by Measuring Gate-to-Emitter
Voltage During IGBT Conduction
Haifeng Zhang1, Dibo Zhang1, Hiromu Yamasaki1, Katsuhiro Hata1, Keiji Wada2, Kan Akatsu3, Ichiro Omura4, and Makoto Takamiya1
1 The University of Tokyo, Tokyo, Japan
2 Tokyo Metropolitan University, Tokyo, Japan
3 Yokohama National University, Kanagawa, Japan
4 Kyusyu Institute of Technology, Fukuoka, Japan

MGDC is proposed, thereby achieving overcurrent protection
at low cost.

Abstract—To achieve low-cost overcurrent protection for
IGBTs without using external components such as high-voltage
diodes, a gate driver IC with a fully integrated overcurrent
protection function by measuring gate-to-emitter voltage (VGE)
during IGBT conduction is proposed. In the proposed gate
driver IC, while the IGBTs are ON, constant gate charge isperiodically discharged and charged, and when VGE dropped byeach discharge is less than the reference voltage, it is detected as
the overcurrent and the IGBTs are immediately turned off toprotect from the overcurrent. In a single-pulse test of aninductive load at 300 V for an IGBT with a pulse rating of 200
A, the proposed gate driver IC fabricated with 180-nm BCD
process successfully protected the overcurrent of 370 A with theprotection delay of 810 ns.

II. PROPOSED GATE DRIVER IC WITH FULLY INTEGRATEDOVERCURRENT PROTECTION FUNCTION
Fig. 1 shows an operation principle of the proposed gate
driver IC with a fully integrated overcurrent protection
function by measuring gate-to-emitter voltage (OPV) while
IGBTs are ON. Two functions, a periodic QC discharger andrecharger, and an overcurrent protection by VGE, are added tothe gate driver IC. While the IGBTs are ON, the periodic QC
discharger and recharger periodically discharges andrecharges QC. When VGE dropped by each discharge is lessthan VREF, it is detected as the overcurrent and the gate driver
is forced to turn off to complete the overcurrent protection.

Keywords— overcurrent, protection, gate driver, IC, gate
voltage, IGBT

Fig. 2 shows a circuit schematics of the proposed gate
driver IC with OPV. All circuits are integrated on a single chip
except for the isolated power supplies. To achieve the twofunctions shown in blue in Fig. 1, an OPV circuit is added toour previously developed 6-bit current-source type digital gate
driver [12, 13] with variable gate current (IG) in 64 levels,
where IG = nPMOS × 48 mA and nPMOS is an integer from 0 to
63 at turn-on. The 64-level IG control is achieved by
selectively turning on or off six pMOSFETs with binary
weighted gate widths (WP, 2WP, 4WP, 8WP, 16WP, 32WP) in theoutput stage depending on the 6-bit control signals for nPMOS[12, 13]. The exact same is true for turn-off by controllingnNMOS.

I. INTRODUCTION
The detection and protection of IGBT overcurrent areimportant technologies to realize reliable power electronicsystems. The target of this work is to develop a gate driver IC
with a fully integrated overcurrent protection function while
IGBTs are ON for large-current, short-pulse current generator
circuits with inductive load [1] to achieve low-cost
overcurrent protection for IGBTs without using externalcomponents such as high-voltage diodes.
Methods for detecting overcurrent by measuring collector
current (IC) [2-5], collector-to-emitter voltage (VCE) [3, 6], andgate-to-emitter voltage (VGE) [7-10] of IGBTs have been
proposed. IC measurement requires a current sensor, and VCE
measurement for desaturation detection requires a highvoltage diode, which are expensive. All conventional
overcurrent detection methods by VGE measurement [7-10]
have the disadvantage that overcurrent during ON of IGBTs
cannot be detected because VGE is measured during the turnon transient.

Fig. 3 shows a circuit schematics of the proposed OPVcircuits. The OPV circuits include a digitally controlled
oscillator (DCO) to determine charging and discharging timeand a VGE detector to detect the overcurrent by comparing VGE
and VREF. The three outputs of the OPV circuits (Alarm,IC

In [11], an overcurrent detection method by “monitoringgate voltage while periodically repeating discharging andcharging of constant gate charge (MGDC)” was proposed. InMGDC, while the IGBTs are ON, constant gate charge (QC)
is periodically discharged and recharged, and when VGE
dropped by each discharge is less than the reference voltage(VREF), it is detected as the overcurrent. In [11], however,neither overcurrent detection nor overcurrent protection
functions are implemented. In addition, MGDC in [11] is notpractical, because it requires many measuring instruments
such as a high-speed digital signal generator for timing controlof the discharging and the recharging and an oscilloscope todetect VGE drop. To solve the problems, in this paper, a gate
driver IC that fully integrates all the functions required for

978-8-3503-9682-9/23/$31.00 ©2023 IEEE

IN

Gate driver
Periodic QC
discharger& recharger

VGE

Over-IC protection
by VGE
Constant gate charge (QC)
Fig. 1. Operation principle of proposed gate driver IC with fully
integrated overcurrent protection function by measuring VGE (OPV).

76

Gate driver (GD) IC withover-IC protection by VGE (OPV)
5V

SIPO 24
3nPMOS
6PISOs

15 V

1WP
IO

32WP
32IO

IO

32IO

1WN

32WN

Level shifter
Scan In
Scan CLKIN
5V

VREF
ResetVGSIPO 24
10OPV6PISOsnNMOS3(Fig. 3)

ICIG
VGE

VCE

Serial-in parallel-out shift register (SIPO)
Parallel-in serial-out shift register (PISO)
Fig. 2. Circuit schematics of proposed gate driver IC with OPV.

Internal_ONOFF, and Pulse) are fed into the low-side andhigh-side PISOs in Fig. 2.

Figs. 5 and 6 show the timing charts of the conventional
and proposed overcurrent protection, respectively. Table I
shows the design specifications of the four parameters (t1, t2,I1, and I2) that can be digitally controlled by this IC to achieve
MGDC [11]. The discharging time (t2) in MGDC is digitallycontrolled by 5-bit T2 [4:0] of DCO from 0 s to 3.9 s in 125ns steps. The discharging gate current (|I2|) in MGDC isdigitally controlled by 6-bit I2 [5:0] of the digital gate driverfrom 0 A to 3 A in 48 mA steps. Similarly, the charging time(t1) in MGDC is digitally controlled by 5-bit T1 [4:0] of DCO
from 0 s to 19 s in 625 ns steps. The charging gate current(I1) in MGDC is digitally controlled by 6-bit I1 [5:0] of thedigital gate driver from 0 A to 3 A in 48 mA steps. Allparameters are written in advance to the on-chip memory (twoSIPOs in Fig. 2) by scan-in, eliminating the need for the highspeed digital signal generator to determine t1 and t2. In theconventional desaturation detection shown in Fig. 5,
overcurrent is detected when VCE exceeds a reference voltage(VREF). In contrast, in MGDC shown in Fig. 6, QC (= |I2| × t2)
is periodically discharged with the t1 + t2 cycle, and if theresulting drop in VGE is greater than VREF, it is judged normal,Fig. 4 shows a circuit schematics of the VGE detector. TheVGE detector includes an attenuator with an attenuation ratioof one-eighth to prevent the input gate voltage (VG) fromdamaging the clocked comparator with overvoltage, and a low
pass filter (LPF) with a cutoff frequency of 57 MHz to remove
high-frequency ringing of VG. When the attenuated and low
pass filtered VG drops below VREF, Alarm output changes from
low to high, forcing the IGBT to turn off.
Edgedetector

INT1 [4:0],
T2 [4:0] 10VREF
Reset
VG

Pulse

DCO

VGEdetector(Fig. 4)
DCO_out

AlarmInternal_ONOFF

Digitally controlled oscillator (DCO)

Fig. 3. Circuit schematics of proposed OPV circuits.

VG
R1 / R2 = 7
Clocked
R1comparator

5V
DQ

−R2

C1

Attenuator& LPF+VREF DCO_out

VGE

Alarm

15 V
0V

IC Rated IC

Reset

0A

Overcurrent detection

300 V
VCE VREF
0V

Reset

Overcurrent protection

Fig. 4. Circuit schematics of VGE detector.

Fig. 5. Timing charts of conventional overcurrent protection.

77

t1t2

OffIN
DCO_outt1t2t2t1t20

I1 [5:0]I2 [5:0]nNMOS630IG0A
15 V

VGE V

REF0V
IC Rated IC
0A
300 VVCE

I1SIPOnPMOS63

2.0 mmInternal_ONOFF

QC

|I2|

PISOs

6-bit
pMOS
drivers

PISOs

OPVAlarm

SIPO

On

6-bit
nMOSdrivers

2.5 mmOvercurrent detection

Fig. 7. Die photo of proposed gate driver IC with OPV fabricated with
180-nm BCD process.

IGBT
module0V

Overcurrent protection
Fig. 6. Timing charts of proposed overcurrent protection using
proposed gate driver IC shown in Fig. 2.

300 V
GD IC

TABLE I.

FOUR PARAMETERS FOR IC TO ACHIEVE MGDCParameters

Control bits

Range

Stept1T1 [4:0]

0 s to 19 s625 ns

t2

T2 [4:0]

0 s to 3.9 s 125 ns

I1

I1 [5:0]

0 A to 3 A

48 mA

IC

|I2|

I2 [5:0]

0 A to 3 A

48 mA

Fig. 8. Circuit schematic of single-pulse test.

IGVCE

VGE

and if the resulting drop in VGE is less than VREF, it is judged
overcurrent and the IGBTs are immediately turned off toprotect from the overcurrent. In the t1 period after eachdischarge, VGE is recharged to 15 V.
Fig. 7 shows a die photo of the proposed gate driver IC
with OPV fabricated with 180-nm BCD process. The die sizeis 2.0 mm by 2.5 mm.

IGBT module

III. MEASURED RESULTS
Figs. 8 and 9 show a circuit schematic and a photo of themeasurement setup for a single-pulse test of an inductive loadof 34 H at 300 V for the IGBT module (FF100R12RT4, 1200
V rating) with a pulse rating of 200 A, respectively.

Gate drive ICwith OPV

Figs. 10 and 11 show the measured waveforms of theconventional and proposed overcurrent protection,respectively. In the conventional desaturation detection in Fig.
10, the overcurrent is detected by the VCE increases. In Fig. 10,the IGBT is turned off manually. In the proposed Fig. 11,
where measured t1 = 2.6 s, t2 = 0.51 s, I1 = 1.6 A, and |I2| =0.62 A, “(1) QC discharge in t2, (2) comparison of VGE and VREF
at the end of t2, and (3) recharge to VGE = 15 V in t1”, isrepeated in t1 + t2 cycles. When VGE < VREF, overcurrent (IC =370 A) is detected, Alarm changes from low to high,Internal_ONOFF changes from high to low, and the gate
driver is forced to turn off to complete overcurrent protection.
The delay from overcurrent detection to protection completionis 810 ns.

Fig. 9. Photo of measurement setup.

Table II shows a comparison table of overcurrent
protection methods. This paper is the first work to fully
integrate overcurrent protection into a gate driver IC without
the need for external components such as high-voltage diodes.

78TABLE II.

10 μs/div

VGE: 3 V/div

Reference[2-5][3, 6][8-9][10][11]This work
Current Desatur
Gate
VGE at Miller
MGDC
MGDC
monitor ation
chargeplateau
Measured value
ICVCE
QG, VGE
VGE
VGE
VGE
Measurement
No
No
Yes
Yes
Yes
Yes
from gate
terminal
Overcurrent
Yes
Yes
No
No
Yes
Yes
detection
during ON
Fully integrated
overcurrent
No
No
No
No
No
Yes
protection
functionProtection
22 [2]
250 [3]
200
500
N/A
810
delay [ns]100 [3] 400 [6]AdditionalHigh
QC
Current
QC
Filtercircuits except
voltage Integrator
discharger,
sensordischarger
comparators
diode
DCO
Method

VCE: 100 V/div0COMPARISON TABLE OF OVERCURRENT PROTECTION

Enlarged vertical axis
10 μs/div

VCE: 2 V/div0
REFERENCES

Fig. 10. Measured waveforms of conventional overcurrent protection.
[1]IN

5 V/div

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10 μs/div

DCO_out
AlarmInternal_ONOFF

VGE
VCE0ICIN
2 μs/div

DCO_out
Alarm

Overcurrent protection

Internal_ONOFF

VCE: 100 V/div
370 A0

VGE: 3 V/div
IC: 100 A/div

Overcurrent detection

t1t2

t1t2810 nsFig. 11. Measured waveforms of proposed overcurrent protection using
proposed gate driver IC.

IV. CONCLUSIONS
A gate driver IC with a fully integrated overcurrent
protection function by measuring VGE while IGBTs are ON isproposed. This paper is the first work to fully integrate
overcurrent protection into a gate driver IC without the needfor external components such as high-voltage diodes. In asingle-pulse test of an inductive load at 300 V for an IGBTwith a pulse rating of 200 A, the proposed gate driver IC
fabricated with 180-nm BCD process successfully protected
the overcurrent of 370 A with the protection delay of 810 ns.
ACKNOWLEDGMENT
This work was partly supported by JST-Mirai Program,Grant Number JPMJMI20E1, Japan.

79