Equalization of DC and Surge Components of Drain
Current of Two Parallel-Connected SiC MOSFETs
Using Single-Input Dual-Output Digital Gate Driver
IC
Kohei Horii1, Ryuzo Morikawa1, Ryunosuke Katada1, Katsuhiro Hata1, Takayasu Sakurai1, Shin-Ichiro Hayashi2, Keiji Wada2,
Ichiro Omura3, and Makoto Takamiya1
1The University of Tokyo, Tokyo, Japan
2Tokyo Metropolitian University, Tokyo, Japan
3Kyushu Institute of Technology, Fukuoka, Japan

Abstract— A single-input, dual-output (SIDO) digital gate
driver (DGD) IC, integrating two 6-bit DGDs, two current
sensors, and a controller, is proposed to equalize the draincurrent (ID) variation of two parallel-connected SiC MOSFETs.
The DC and surge components of ID of each MOSFET are
equalized by digitally controlling the gate voltage amplitude andthe gate current at turn-on, respectively. In the double pulse test
at 300 V and 40 A using two parallel SiC MOSFETs withdifferent threshold voltages of 0.5 V, the proposed SIDO DGD
IC reduces the differences in the DC and surge components of
ID of the two MOSFETs from 2.6 A to 0.13 A by 95 % and from
1.9 A to 0.32 A by 83 %, respectively. The automaticequalization of the DC components of ID of the two MOSFETs
using SIDO DGD IC is also successfully demonstrated.

II. PROPOSED DRAIN CURRENT EQUALIZATION USING SIDO
DGD IC

Keywords— Parallel connected, SiC, DC current, Surgecurrent, Gate driverFig. 2 shows the circuit schematic of the current sensor tomeasure ID1,DC and ID2,DC. The current sensor cannot measure
the high-frequency ID1,SURGE and ID2,SURGE waveforms. Two
current sensors are integrated on SIDO DGD IC. In order toobtain the current waveform, the output of the PCB Rogowski
coil is integrated.

I. INTRODUCTION
In power electronics systems, when large current
exceeding the rated current of a power device is applied, it iscommon to connect multiple power devices in parallel. Due tovariations in the characteristics of the power devices, however,the current concentrates in part of the devices and the heatgeneration due to losses is localized, which degrades thereliability of the power devices. In the conventional method ofparallel connection of power devices, the characteristics of thepower devices are measured in advance, and power devices
with matching characteristics are selected for parallel
connection, which will increase the cost. Therefore, atechnology to automatically equalize the current of powerdevices connected in parallel is required. The problem withthe previous papers of current equalization is that they require
a lot of ICs including such as current sensors [1–2], timing
control circuits [1–4], and regulators for gate voltage
amplitude control [5–6], which will also increase the cost.
In this paper, a single-input, dual-output (SIDO) digital
gate driver (DGD) IC, integrating all necessary circuits
including two 6-bit DGDs, two current sensors, and acontroller, is proposed to automatically equalize the draincurrent (ID) of two parallel-connected SiC MOSFETs. DGD
that can digitally control the gate waveform is gaining
attention as a technology to reduce both loss and noise duringswitching of power devices [7]. The proposed SIDO DGD IC
will enable a high-performance power electronics systems
using SiC MOSFETs at low cost, because SiC MOSFETs withlarge variations can be connected in parallel without priortesting and selection.

978-1-6654-0688-8/22/$31.00 ©2022 IEEE

Fig. 1 shows a circuit schematic of the fabricated halfbridge circuit and SIDO DGD IC. The half-bridge consists ofthree SiC MOSFETs (Q1 – Q3 : SCT3030AL, 650V, 70A)
including the low-side two-parallel Q1 and Q2. In order toequalize DC (ID1,DC, ID2,DC) and surge (ID1,SURGE, ID2,SURGE)
components of ID of Q1 and Q2 (ID1, ID2) with variations indevice characteristics by controlling the gate waveforms,
SIDO DGD IC is newly developed. Except for two PCB
Rogowski coils [8], all the necessary circuits including two 6bit DGDs, two current sensors, and a controller are fully
integrated into a single chip.

SiC MOSFETs
Single-input, dual-output (SIDO)
digital gate driver (DGD) IC
Controller
IN
ControlnPMOS2 [5:0]
nNMOS2 [5:0]6nPMOS1 [5:0]
nNMOS1 [5:0]

6

DGD2

IG2

300 V

6

IG1

6

DGD1
ID2’

IL

Q3

ID1’

VTH1

VTH2

VGS1

Q1
ID1 VGS2

Q2
ID2

Current
probe

Current
sensors

Rogowski coils

Fig. 1. Circuit schematic of fabricated half-bridge circuit andproposed SIDO DGD IC.
Reset

PCB

IC
3 pF
VDD

ID

VDD
7.8 kΩ

Rogowski
100 nFcoil
30 Ω

100 kΩ
0.5VDD

I’D

0.5VDD

Voltage follower

Integrator

DC biasing

Fig. 2. Circuit schematic of current sensor to measure ID1,DC andID2,DC.

1406

Fig. 4 shows the timing chart of the proposed SIDO DGD
IC. In this paper, the threshold voltage of Q1 (VTH1) is assumed
to be lower than that of Q2 (VTH2). Among the eight parametersof nPMOS1, nNMOS1, nPMOS2, and nNMOS2 in the on and off statesof Q1 and Q2, nNMOS1 in the on state is controlled to equalize
ID1,DC and ID2,DC by digitally controlling the gate voltage
amplitude, and nPMOS2 in the on state is controlled to equalize
ID1,SURGE and ID2,SURGE by digitally controlling the gate current
at turn-on. Vice versa, if VTH1 > VTH2, nNMOS2 and nPMOS1 arecontrolled.

63
0

63
0

nNMOS nPMOS

nNMOS nPMOS

Fig. 5 shows the conventional gate driving and the
proposed gate driving to equalize ID1,DC & ID2,DC and ID1,SURGE& ID2,SURGE using SIDO DGD IC. In the conventional gate
driving where the gate drive is identical for Q1 and Q2 in Fig.
5 (a), ID1,DC > ID2,DC and ID1, SURGE > ID2,SURGE, because of VTH1
< VTH2. In order to equalize ID1,DC and ID2,DC, Fig. 5 (b) shows
the VGS1 amplitude control by increasing nNMOS1 from zero. Fig.
6 shows the principle of operation of the proposed DGD-based

63

nPMOS1 = nPMOS2

63

nNMOS1 = nNMOS2

VGS
VDD

0

ID1,SURGE
0

0

VGS

Different
ID1

Time

IO

2IO

4IO

8IO

16IO

32IO

WP

2WP

4WP

8WP

16WP

32WP

nNMOS1 [0] nNMOS1 [1] nNMOS1 [2] nNMOS1 [3] nNMOS1 [4] nNMOS1 [5]

IO

2IO

4IO

8IO

16IO

32IO

WN

2WN

4WN

8WN

16WN

32WN

IN

On

ID1,DC

ID2,SURGE

ID2,DCTimenNMOS1(a) Initial state w/o control(Conventional)

Q1

VGS1

ID1

63
0

63

63

nNMOS1 control for DC ID equalizationnPMOS2 0
nNMOS2nPMOS2 control for surge ID equalization
0
63

63
0

0

Fig. 4. Timing chart of proposed SIDO DGD IC.

nNMOS2063

nNMOS1 control

0

nNMOS2

VGS

VGS2

VDD

VGS1

Time

Different

nPMOS1nPMOS2 control

63

nNMOS1 control

0

IG1

Off

63

nPMOS1 0

VGS2
VGS1

0

ID

Equal

ID2

IG1 = nIO
= 0 A to 6 A
n = 0 to 63
IO = 95 mA

When VTH1 < VTH20ID

VDD = 18 V

Fig. 3. Circuit schematic of DGD1 for Q1.

nPMOS1 = nPMOS2

VDD

VGS1 = VGS2ID

0nPMOS1 [0] nPMOS1 [1] nPMOS1 [2] nPMOS1 [3] nPMOS1 [4] nPMOS1 [5]nNMOS nPMOSSIDO DGD IC has 24 bits of control bits. nPMOS1 [5:0] andnNMOS1 [5:0] control the gate current (IG1) for Q1, while nPMOS2[5:0] and nNMOS2 [5:0] control the gate current (IG2) for Q2. Fig.
3 shows the circuit schematic of DGD1 for Q1 in Fig. 1. IG1
can be varied in 64 levels at turn-on depending on 6-bit digital
signals nPMOS1 [5:0], which is defined as nPMOS1, where nPMOS1
is an integer between 0 and 63. The 64-level IG1 control from
0 A to 6 A in 95 mA increments at turn-on of Q1 is achievedby selectively turning on or off six pMOSFETs with binary
weighted gate widths (WP, 2WP, 4WP, 8WP, 16WP, 32WP) in the
output stage depending on nPMOS1 [5:0]. The same design isapplied to the turn-off of Q1 by controlling nNMOS1 [5:0].

Time
Equal

ID1

ID1

ID2

ID2
Time

(b) DC current equalization
by nNMOS1 control

0Time(c) Proposed DC and surge
current equalization by
nNMOS1 and nPMOS2 control

Fig. 5. Conventional gate driving and proposed gate driving to equalize ID1,DC & ID2,DC and ID1,SURGE & ID2,SURGE using SIDO DGD IC.

1407

VGS1 amplitude control. In the conventional gate driving in Fig.
6 (a), VGS1 is equal to the supply voltage (VDD), because nNMOS1
in the on state is zero. In contrast, in the proposed VGS1
amplitude control in Fig. 6 (b), VGS1 amplitude can be digitallycontrolled by nNMOS1 on the principle of a shunt regulator,
where all six pMOSFETs and some of the six nMOSFETs in
Fig. 3 are turned on. The IC includes a new circuit technologythat solves the large DC power of the shunt regulator. The
details, however, will not be discussed in this paper. Fig. 7
shows the flowchart to control nNMOS1 and nNMOS2 to equalize
ID1,DC and ID2,DC. The flowchart is implemented in thecontroller in SIDO DGD IC in Fig. 1. First, when ID1,DC isgreater than ID2,DC, nNMOS1 is incremented from 0. Next, asteady state is reached at the value of nNMOS1 where ID1,DC andID2,DC are equal. Similarly, when ID12,DC is smaller than ID2,DC,
nNMOS2 is incremented from 0. Then, a steady state is reachedat the value of nNMOS2 where ID1,DC and ID2,DC are equal. In Fig.
5 (b), ID1,DC and ID2,DC are adjusted to be equal, by reducing
VGS1 amplitude below VGS2 amplitude, while ID1,SURGE <ID2,SURGE, because IG1 < IG2 at turn-on due to the increased
nNMOS1. Please note that ID1,SURGE > ID2,SURGE, in Fig. 5 (a),while ID1, SURGE < ID2,SURGE, in Fig. 5 (b). In order to equalize
ID1,SURGE and ID2,SURGE, Fig. 5 (c) shows the proposed gate
driving by controlling nNMOS1 and nPMOS2. ID1, SURGE and
ID2,SURGE are equalized by decreasing IG2 at turn-on by
decreasing nPMOS2 from 63. In conclusion, ID1,DC and ID2,DC are
equalized by tuning nNMOS1, and ID1, SURGE and ID2,SURGE areequalized by tuning nPMOS2.
III.

MEASURED EQUALIZATION OF DC AND SURGECOMPONENTS OF DRAIN CURRENT

Fig. 8 shows a die photo of SIDO DGD IC fabricated with
180-nm BCD process. Fig. 9 shows a photo of PCB of the half
bridge. PCB is designed symmetrically so that the parasitic
Conventional

ProposedRP

inductances of Q1 and Q2 are equal. As shown in Fig. 1, ID1
and ID2 are measured using two commercial current probes(SS-284A, IWATSU) and our developed two current sensors
in DGD IC. The current probes are used in Figs. 11 – 17 tomeasure ID1 and ID2 waveforms, while the current sensors areused in Fig. 17 to automatically equalize ID1,DC and ID2,DC. Fig.
10 shows the measured ID – VGS characteristics of Q1 and Q2
at VDS = 10 V using a curve tracer, where VTH2 − VTH1 = 0.5 V.
ID1,DC, ID2,DC, ID1,SURGE, and ID2,SURGE are measured with the
double pulse test at 300 V and the load current (IL) of 5 A, 10
A, 20 A, and 40 A.
Figs. 11 – 13 show the measured nNMOS1 dependence of
VGS1 amplitude, ID1,DC and ID2,DC, and ID1,SURGE and ID2,SURGE atnPMOS2 = 63, respectively, corresponding to the DC current
equalization by nNMOS1 control shown in Fig. 5 (b). At IL = 40
A, by increasing nNMOS1 from 0 to 18, VGS1 amplitude reducesfrom 18 V to 15.9 V (Fig. 11) and the difference between
ID1,DC and ID2,DC reduces from 2.6 A to 0.13 A by 95 % (Fig.
12), while the difference between ID1,SURGE and ID2,SURGE
increases from 1.9 A to 9.8 A (Fig. 13). To equalize the surge,
Fig. 14 shows the measured nPMOS2 dependence of ID1,SURGE
and ID2,SURGE at nNMOS1 = 18, corresponding to the proposed
DC and surge current equalization by nNMOS1 and nPMOS2
control shown in Fig. 5 (c). At IL = 40 A, by decreasing nPMOS2
from 63 to 28, the difference between ID1,SURGE and ID2,SURGE
reduces from 9.8 A to 0.32 A by 97 %. Fig. 15 shows themeasured waveforms of VGS1 & VGS2 and ID1 & ID2
corresponding to Figs. 5 and 11 – 14 at IL = 40 A. Comparedwith the conventional gate driving (Fig. 15 (a)), the proposed
gate driving (Fig. 15 (c)) with nNMOS1 and nPMOS2 control
reduces the difference between ID1,DC and ID2,DC from 2.6 A to
0.13 A by 95% and the difference between ID1,SURGE and
ID2,SURGE from 1.9 A to 0.32 A by 83%.
Fig. 16 shows the measured waveforms of VGS1 & VGS2 andID1 & ID2 corresponding to Figs. 5 and 11 – 14 at IL = 20 A.

RP

VDD

VDD
RN

VGS1

RN

VGS1

VGS1

VGS1

VDD

VDD

0V

Time
(a) Constant VGS1

RN
V
RP+RN DD

Fig. 8. Die photo of SIDO DGD IC fabricated with 180-nm BCD
process.

0VTime(b) VGS1 amplitude control

Fig. 6. Principle of operation of proposed DGD-based VGS1
amplitude control.
Reset
nNMOS10
nNMOS20
ID1,DC>ID2,DC

No

Yes
No

nNMOS1 ≠ 0
Yes

nNMOS1nNMOS1−1

NoNo

ID1,DC>ID2,DC

ID1,DC<ID2,DC

Yes

Yes

nNMOS1 ≠ 63

nNMOS2 ≠ 63

Yes
nNMOS1nNMOS1+1

Yes

No

No

nNMOS2 ≠ 0No

YesnNMOS2nNMOS2−1

nNMOS2nNMOS2+1

Fig. 7. Flowchart to control nNMOS1 and nNMOS2 to equalize ID1,DC
and ID2,DC.

Fig. 9. Photo of PCB of half bridge.

1408

Compared with the conventional gate driving (Fig. 16 (a)), theproposed gate driving (Fig. 16 (c)) with nNMOS1 and nPMOS2
control reduces the difference between ID1,DC and ID2,DC from
1.3 A to 0.07 A by 95% and the difference between ID1,SURGE
and ID2,SURGE from 0.61 A to 0.05 A by 92%.
Finally, the automatic equalization of ID1,DC and ID2,DC by
the feedback control of nNMOS1 shown in Fig. 5 (b) using SIDO
VDS = 10 V

ID1, ID2 [mA]

80
ID1

60
40

ID2
20
0

ΔVTH = 0.5 V
3.4

3.6

3.8

4.0
4.2
VGS [V]

4.4

4.6

Fig. 10. Measured ID – VGS characteristics of Q1 and Q2 at VDS =10 V.

VGS1 amplitude [V]18

Table I shows a comparison table of DGD ICs. This workis the world's first IC that achieves ID equalization of twoparallel MOSFETs by integrating two DGDs, two current
sensors, and a controller.
IV. DISCUSSION ON CONDUCTION LOSS
In order to gain a better understanding of the advantages
and disadvantages of the proposed equalization of ID1,DC andID2,DC using SIDO DGD IC, the conduction losses of Q1 andQ2 are discussed. Fig. 18 shows the calculated conduction
Surge components of ID1and ID2 [A]100

DGD IC is demonstrated. Fig. 17 shows the measured
waveforms of VGS1 & VGS2 and ID1 & ID2 of the conventional
gate driving (Fig. 5 (a)) and DC current equalization by nNMOS1
control (Fig. 5 (b)) in multi pulse test at 300 V. In theconventional gate driving in Fig. 17 (a), VGS1 = VGS2 and ID1,DC− ID2,DC = 2.3 A. In contrast, in DC current equalization by
nNMOS1 control in Fig. 17 (b), VGS1 amplitude is automaticallyregulated to VGS2 − VGS1 = 1.8 V by the feedback control ofnNMOS1, achieving ID1,DC − ID2,DC = 0.24 A. The automaticequalization of ID1,SURGE and ID2,SURGE by the feedback control
of nPMOS2 using SIDO DGD IC is a future research topic,
because the current sensor in this work cannot accurately
measure the high-frequency ID1,SURGE and ID2,SURGE waveforms.

nPMOS2 = 63
2.1 V

17
16
IL = 40 A
IL = 20 A
IL = 10 A
IL = 5 A

15
14
13

0
5
0
(Conv.)(Fig. 5 (a))

10

15 18 20nNMOS1 (Fig. 5 (b))

25

0.13 AnPMOS2 = 63

2.6 A

20

IL = 40 A
15
IL = 20 A

ID1,DC
ID2,DC10IL = 10 A
50

IL = 5 A

0(Conv.)(Fig. 5 (a))

510

15 18 20nNMOS1 (Fig. 5 (b))

35
30
25

ID1,SURGE
ID2,SURGE

9.8 A
1.9 A

20
15
10
5
0

nPMOS2 = 63

0

5

10
15 18 20
25
nNMOS1 (Fig. 5 (b))

Fig. 13. Measured nNMOS1 dependence of ID1,SURGE and ID2,SURGE,
corresponding to DC current equalization by nNMOS1 control
shown in Fig. 5 (b).

Surge components of ID1and ID2 [A]DC components of ID1and ID2 [A]−95 %IL = 40 A
IL = 20 A
IL = 10 A
IL = 5 A

40(Conv.)(Fig. 5 (a))

Fig. 11. Measured nNMOS1 dependence of VGS1 amplitude,
corresponding to DC current equalization by nNMOS1 control
shown in Fig. 5 (b).

25

45

25

45

IL = 40 A
IL = 20 A
IL = 10 A
IL = 5 A

40
35
30
25

ID1,SURGE
ID2,SURGE
−97 %
9.8 A

0.32 A

20
15
10
5
0

nNMOS1 = 18
20

30

28

(Proposed)(Fig. 5 (c))

40nPMOS250

60

63(Fig. 5 (b))

Fig. 14. Measured nPMOS2 dependence of ID1,SURGE and ID2,SURGE
at nNMOS1 = 18, corresponding to proposed DC and surge current
equalization by nNMOS1 and nPMOS2 control shown in Fig. 5 (c).

Fig. 12. Measured nNMOS1 dependence of ID1,DC and ID2,DC,
corresponding to DC current equalization by nNMOS1 control
shown in Fig. 5 (b).

1409

63

63

nNMOS1 = nNMOS20nNMOS1

18

0

VGS1 = VGS2

20
10

0.5

1

1.5

30
20

0.5

30

2.6 A

ID1

ID1, ID2 [A]0

2Time [ms]1

1.5Time [ms]

1.9 A
0
0

1

0.5

1.5

2

nNMOS2
2.1 V

VGS2

VGS1

0
0

0.5

1

1.5

Time [ms]30

20.13 A

ID2

ID1

10

9.8 A
0
0

nNMOS1

0

20

ID1

10

10

18

30

2

0.13 A

ID2

20

ID2

nPMOS1nPMOS2

10

0ID1, ID2 [A]

0

28

20

VGS1

10

0

2.1 V

VGS2

20

0

63

nNMOS230

VGS1, VGS2 [V]30

VGS1, VGS2 [V]0nNMOS nPMOS

063

nPMOS1 = nPMOS2

VGS1, VGS2 [V]63nPMOS1 = nPMOS2

ID1, ID2 [A]nNMOS nPMOS

nNMOS nPMOS

63

0.5

1

1.5

2

0.32 A
0
0

0.5

1

1.5

2

Time [ms]Time [ms]Time [ms](a) Initial state w/o control (b) DC current equalization (c) Proposed DC and surge
current equalization by(Conventional)
by nNMOS1 control
nNMOS1 and nPMOS2 control
Fig. 15. Measured waveforms of VGS1 & VGS2 and ID1 & ID2 corresponding to Figs. 5 and 11 – 14 at IL = 40 A.

Q1 is increased by decreasing VGS1 from 18 V to 15.9 V toequalize ID1,DC and ID2,DC. The 10% increase of VDS from 0.60
V to 0.66 V agrees well with 9.5% increase of the total
conduction loss. If the increase of the total conduction loss is
not preferred, VGS1 is fixed to 18 V and VGS2 should be
increased more than 18 V to equalize ID1,DC and ID2,DC.

Table I Comparison table of DGD ICs.
TIA’17 [7]Target power device

Si IGBT &SiC MOSFET

Process

180 nm BCD

Number of outputs
Output voltage swing

1
15 V

Levels of IG

6 bit

Max. IG

5A

TPEL’21 [9]ISPSD’20[10]

ISPSD’21
This work[11]
SiC
GaN FETMOSFETGaN FETGaN FET

180 nm HV
CMOS
15V
8 bit (coarse),
6 bit (fine)

180 nmBCD
1
3.3 V

180 nmBCD
15V

180 nm
BCD
2
18 V

7 bit

6 bit

6 bit

5 V / 0.12 Ω= 42 A

3.3 V / 0.5 Ω= 6.6 A

5A

6A

Functions integrated
into IC

1 driver1 driver1 driver1 driver2 drivers,
2 current
sensors,
controller

Drain current
equalization of twoparallel MOSFETs

No

No

No

No

Yes

V. CONCLUSIONS

losses of Q1 and Q2 in the conventional gate driving (Fig. 15(a)) and the proposed gate driving (Fig. 15 (c)) at IL = 40 A.
The proposed gate driving reduces the difference between the
conduction loss of Q1 and that of Q2 from 1.57 W to 0.04 W
by 97%, while the proposed gate driving increases the total
conduction loss of from 24.1 W to 26.4 W by 9.5%. Therefore,variation of heat generation between Q1 and Q2 is reduced,
while total heat generation of Q1 and Q2 is increased.
The reason can be understood from ID – VDS characteristics.
Fig. 19 shows the measured ID – VDS characteristics of Q1 andQ2 at VGS = 18 V using a curve tracer. To achieve IL = 40 A,
ID1 + ID2 should be equal to 40 A. In the conventional gate
driving (Fig. 15 (a)), VDS = 0.60 V, while VDS = 0.66 V in the
proposed gate driving (Fig. 15 (c)) because on-resistance ofIn the switching measurements of two parallel SiC
MOSFETs at 300 V and 40 A, the proposed SIDO DGD IC
reduces the difference between ID1,DC and ID2,DC from 2.6 A to
0.13 A by 95% and the difference between ID1,SURGE and
ID2,SURGE from 1.9 A to 0.32 A by 83%. The automaticequalization of ID1,DC and ID2,DC by the feedback control ofnNMOS1 using SIDO DGD IC is also successfully demonstrated.
The proposed SIDO DGD IC will enable a high-performance
power electronics systems using SiC MOSFETs at low cost,because SiC MOSFETs with large variations can be connectedin parallel without prior testing and selection.

1410

ACKNOWLEDGMENT
This work was partly supported by NEDO (JPNP14004).

63

nNMOS1 = nNMOS2

VGS1 = VGS2

20

0.5

1

1.5

15

10
5
0
0

1.5

Time [ms]ID1
ID2
0.61 A
1

0.5

1.5

2

2.1 V

VGS2
VGS1

0
0.5

1

1.5

Time [ms]

2

20

ID2

15
10

nNMOS1nNMOS2

0

2

20

1.3 A

ID1, ID2 [A]ID1, ID2 [A]

20

18

0

10

1

nPMOS2

20

0
0.5

29

30

VGS1

0

2

Time [ms]

2.1 V

VGS2

0

63

nNMOS2

10

0
0

0

20

10

nNMOS1

18

30

VGS1, VGS2 [V]

VGS1, VGS2 [V]30

nNMOS nPMOS

0

0

63

nPMOS1 = nPMOS2

VGS1, VGS2 [V]63

63

nPMOS1 = nPMOS2

0.07 A

ID1

15

9.3 A
9.8 A
1

0.5

1.5

ID1

5

0.32
A A
0.05

0
0

2

0.07 A

ID2

10

5
0
0

ID1, ID2 [A]0nNMOS nPMOS

nNMOS nPMOS

63

1

0.5

1.5

2

Time [ms]Time [ms]Time [ms](a) Initial state w/o control (b) DC current equalization (c) Proposed DC and surge
current equalization by(Conventional)
by nNMOS1 control
nNMOS1 and nPMOS2 control

10
5
0
20

40
60
Time [ms]ID1, ID2 [A]

25
20
15
10
5
0

80

100

ID1
ID2
0

20

30
25
20
15
10
5
0
38

40
60
Time [ms]
30

ID1
ID2

39
40
Time [ms]

25
20
15
10
5
0
94

41
(a)

VGS2

15

VGS1

1.8 V

10
5
0
0

20

30

ID1, ID2 [A]

0

30

20

-5

80

100

ID1

2.3 A

25
20
15
10
5
0
0

ID2

95
96
Time [ms]

25
20
15
10
5
0
38

97

40
60
Time [ms]

80

100

40
60
Time [ms]
30

80

100

ID2

0.24 A

ID1
ID2
20

30

ID1, ID2 [A]-5

ID1, ID2 [A]Same

VGS1 = VGS2

ID1, ID2 [A]15

ID1, ID2 [A]

VGS1, VGS2 [V]20

VGS1, VGS2 [V]Fig. 16. Measured waveforms of VGS1 & VGS2 and ID1 & ID2 corresponding to Figs. 5 and 11 – 14 at IL = 20 A.

ID1
ID2

39
40
Time [ms]

25
20
15
10
5
0
94

41
(b)

ID1

95
96
Time [ms]97

Fig. 17. Measured waveforms of VGS1 & VGS2 and ID1 & ID2 in multi pulse test. (a) Conventional gate driving (Fig. 5 (a)). (b) DC current
equalization by nNMOS1 control (Fig. 5 (b)).

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−97%

20
15

0.04 W

1.57 W

Q1

Q2

Q1

Q2

Q1 +Q2

10
5

+9.5%

24.1W

25

Q1 +Q2

Conduction loss [W]

REFERENCES
26.4W

0Conventional(Fig. 15(a))

Proposed(Fig. 15(c))

Fig. 18. Calculated conduction losses of Q1 and Q2 inconventional gate driving (Fig. 15 (a)) and proposed gate driving(Fig. 15 (c)) at IL = 40 A.

25
Conventional

ID1, ID2 [A]

20
ID1
15
VGS = 18 V
10

Proposed

ID2

5
0
0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDS [V]

Fig. 19. Measured ID – VDS characteristics of Q1 and Q2 at VGS =
18 V.

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