IEEE 2009 Custom Intergrated Circuits Conference (CICC)

Switched Resonant Clocking (SRC) Scheme
Enabling Dynamic Frequency Scalingand Low-Speed Test
Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, and Makoto Takamiya
The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, JapanI. INTRODUCTION
Decreasing the power of a clock distribution system in
microprocessors and digital LSI’s is a keen interest ofdesigners, because the clocking power accounts for 10-40% of
the total power. A resonant clock scheme is recently proposed[1-3] aiming at the clocking power reduction. By using theresonance of the large clock-node capacitance with an added
inductor, the charging and discharging energy of the clock
node can be recycled by means of an LC tank network. This
results in the reduction of the clocking power. The effective
clock frequency range of the resonant clock, however, islimited to the higher frequency region. For example, themicroprocessor with the resonant clock in [3] successfully
reduced the clocking power by 5-25% compared to the nonresonant clock at the target clock frequency of 4-5GHz. Theresonant clocking in [3], however, showed much larger power
than the non-resonant case in the lower frequency region
below 3GHz. This is a problem when widely-used dynamic
frequency scaling (DFS) [4] is employed. Moreover, the clock
waveform is distorted and functional error arises at thefrequency range below 1.6GHz due to the double count of theclock frequency. This prohibits low-speed testing of LSI’ssuch as in wafer-level test. These two issues are obstacles forthe resonant clocking to be widely used.
In this paper, a novel switched resonant clocking (SRC)
scheme is proposed to solve both of the power increase andthe waveform instability at the lower clock frequency region,
while reducing the clock power at the target high frequency
where maximum power consumption is observed.

In order to confirm the power increase at low clock
frequency and the double switching, both the non-resonant
clock circuit and the conventional resonant clock circuit were
fabricated with 0.18µm CMOS. Cd and inductors wereimplemented with 330-pF chip capacitor and bonding wires,
respectively.
Fig. 2 shows the measured clock power of the conventional
resonant scheme. At 800MHz, the conventional resonant
clock circuit achieved a maximum power reduction of 11%
compared with the non-resonant clock circuit. At 150MHz,
however, the power of the resonant clock circuit is 8.4 times
larger than that of the non-resonant clock circuit.
Clock grid

CdPLL

D Q

Fig. 1 Conventional resonant clocking scheme adding inductor anddecoupling capacitor (Cd) to clocking grid.
150

90

Power
increase

60
30
00.0

Conv

resonant clockParallel
resonance
0.5
1.0
Clock frequency [GHz]1.5

Fig. 2 Problem of the conventional resonant clock (measured). Power
increases drastically at lower frequency.

Fig. 1 shows the conventional resonant clock distribution
network [3]. The clock grid is driven by an H-tree. Inductors
and decoupling capacitors (Cd) are added to the clock grid toresonate with the capacitance of the clock node [3].

4-5-1

Clk

Clk inL

Cload

Cd C
load << Cd

Parallelresonance@ fclk ≈II. PROBLEMS OF CONVENTIONAL RESONANT CLOCKING

978-1-4244-4072-6/09/$25.00 ©2009 IEEE

Series resonanceNon-resonant clock11% Powerreduction

120

Clock power [mW]

Abstract- A novel Switched Resonant Clocking (SRC) scheme is
proposed to solve two basic problems of the conventional
resonant clocking, that is, power increase and clock waveform
inability at the lower clock frequency region. The power increaseprohibits widely-used dynamic frequency scaling (DFS) and thewaveform instability hinders low-speed function tests. A test chipin 0.18µm CMOS is manufactured and measured to show that
the SRC suppresses power increase at low clock frequency andenables the low-speed tests, while reducing the clock power by8% at 1.5-GHz clock with an area penalty of 4.8%.

Clk inSeriesresonance

12π LCload@ fclk ≈Clk

Clk inZ=∞

12π LCdClk

Z=0Fig. 3 Equivalent circuits of the resonant clock33

shown to be a bad configuration because the main resonanttank includes the resistance of the added switch. Fig. 7 shows
the simulated clock frequency dependence of the clock power
for the non-resonant clocking, SRC and the mSRC where SW
is turned on.

Double switching

ClkClock grid

Clk inCd
PLLFig. 4 Measured waveforms of Clkin and Clk in the conventional resonant
clock in Fig. 2 with clock frequency of 20MHz. Double switching is observed.

Fig. 3 shows equivalent circuits of the resonant clock circuit
to explain the operation principle. At the resonant frequencyof 800MHz, the capacitance of the clock loads (Cload) isresonated with the inductance (L), and the high impedance by
the parallel resonance results in the lower power than the nonresonant clock as shown in Fig. 2. In contrast, at 150MHz, thelow impedance by the series resonance of Cd and L results inthe higher power than the non-resonant clock as shown in Fig.
2. The power increase at 150MHz is a serious problem of theresonant clock circuit if Dynamic Frequency Scaling is in use.
Fig. 4 shows the measured waveforms of Clkin and Clk
defined in Fig. 3 in the resonant clock at 20MHz. The double
switching at the rise edge of Clk is clearly observed. The
double switching is a serious problem, because it prevents
low-speed tests.

D Q

Added switch (SW)Fig.5 Proposed Switched Resonant Clocking (SRC).
Clk buffers
Clk

Clk inx8 x16 x32x64 x128x256

Clk loads
(F/F)

x1024
Clock grid(a) Non-resonant clock
Clk

Clk inLCd(b) Conventional resonant clock [3]III. SWITCHED RESONANT CLOCKING

Clk insel

LCd

Gate width (W)Switch (SW)(c) Proposed switched resonant clock (SRC).
Clk inClkselL

CdSW(d) Modified version of switched resonant clock (mSRC).
Fig. 6 Equivalent circuit of various clock distribution circuits.

250
Clock power [mW]

In order to solve the issues of the conventional resonant
clocking, the Switched Resonant Clocking (SRC) scheme isproposed, whose schematic diagram is shown in Fig.5. A
switch is added in between the inductor and the decoupling
capacitor (Cd). Usually adding a switch element in theresonant network is prohibited because it drastically reduces
quality factor and damages the whole resonant characteristics.
In this case, however, the major resonance is between theadded inductor and the clock-grid capacitor, the resistance ofthe switch element does not affect the overall characteristics
much.
Fig.6 shows equivalent circuit of various clock distribution
circuits. Figs. 6(a) and (b) show a normal non-resonant clock
circuit and the conventional resonant clock circuit,respectively. The tapered clock buffers represent the whole Htree clock distribution system. The clock loads represent theflip-flops. The numbers in Fig. 6(a) shows the size of thebuffers. In the conventional resonant clock circuit [3], Cd andthe inductor (L) for the resonance are added. The circuit in Fig.
6(b) stands for the clock distribution of Fig. 1.
In order to avoid the power increase and the double
switching at low clock frequency, it is necessary to separatethe inductor from the Clk node in Fig. 6(b) with a switch. Figs.
6(c) and (d) show two possible configurations of the switch(SW) location. Fig. 2(c) shows the proposed switchedresonant clocking (SRC) and Fig. 2(d) shows a modified
version of switched resonant clocking (mSRC). mSRC is

ClkmSRC (SW=on)

200
150
100
5000.0SRC (SW=on)
Non-resonant
0.5
1.0
1.5
Clock frequency [GHz]2.0

Fig.7 Simulated clock frequency dependence of the clock power for the nonresonant clock, SRC and mSRC in Fig. 6.

4-5-234

RTr. Fig. 9 shows the simulated clock frequency dependenceof the clock power for the non-resonant clock and SRC withW of 10mm, 2mm and 0.5mm. By controlling SW dependingon the clock frequency, the power increase problem of theresonant clock at low clock frequency is solved in SRC,
because SRC where SW is turned on and SRC where SW isturned off have different power peaks. For example, in Fig.
9(a), the proposed SRC achieves the low power by turning off
SW below 450MHz and turning on SW above 450MHz. The
double switching problem of the resonant clock at low clock
frequency is also solved in SRC.
In order to check the double switching characteristics, Fig.
10 shows the simulated waveform of Clk of SRC where SW isturned off at 450MHz clock with various W in Fig. 9. When
W is 10mm, the severe double switching (Fig. 10(a)) and thelarge power increase at 450MHz compared with the nonresonant clock (Fig. 9(a)) are not acceptable, although thepower reduction at 1.0GHz is large (Fig. 9(a)). In contrast,
when W is 0.5mm, the small power reduction compared with
the non-resonant clock (Fig. 9(c)) at high clock frequency is
not attractive, although the no double switching (Fig. 10(c)) isobserved.
Therefore, W of 2mm is adopted in this study in order toavoid the power increase (Fig. 9(b)) and the double switching(Fig. 10(b)) at low clock frequency, while reducing the clock
power at high clock frequency.

SW
RTr

Cload

CjS

CjD

Cd(a)
SW
RTr

Clk

Clk in

Cload

CjS

L
CjD

Cd(b)
Fig. 8 Equivalent circuits of (a) SRC and (b) mSRC in Fig. 6.

The power consumption of SRC is lower than that of themodified version at all frequency and lower than that of thenon-resonant clock above 700MHz. In contrast, the power
consumption of modified SRC is larger than that of the nonresonant clock at all frequency. The reason of the power
difference between mSRC and SRC is as follows. Fig. 8
shows the equivalent circuits of SRC and mSRC. RTr is theresistance of the transistor and CjS and CjD are source anddrain junction capacitance, respectively. As shown in Fig. 7,power consumption of SRC is lower than that of mSRC,
because CjS is directly added to Cload in mSRC (Fig. 8(b)),
while CjS is connected to Clk node via L in SRC (Fig. 8(a)).
Therefore, SRC instead of mSRC is adopted in this study.
It is also possible to insert SW in between Cd and theground, but Cd is made with MOS capacitor so the parasitic
capacitance may drastically increase.
The gate width (W) of the switch of SRC (Fig. 6(c)) is a
critical design parameter in SRC. Here, it is shown that there
is a trade-off in the choice of W between power reduction andwaveform stability. The large W leads to large CjS / CjD andsmall RTr ,while the small W leads to small CjS / CjD and large
Fig10(a)200

SRC(SW=Off)

150
100
50

SRC(SW=On)

00.0

Non-resonant

W=10mm

0.5
1.0
1.5
Clock frequency [GHz]Clock power [mW]

Clock power [mW]200

IV. EXPERIMENTAL RESULTS
Figs. 11 (a) and (b) show the layout and the micrograph of afabricated SRC test chip in 1.8V, 0.18µm CMOS respectively.
Both L and Cd are integrated on chip using top interconnect
layer and MOS capacitor. The die area is 0.8mm×0.93mm.
Table I shows a performance summary of SRC. In order tocalculate the area penalty, the clock loads are converted to an

SRC(SW=On)

200SRC(SW=Off)

150Fig
10(b)

100
50

Non-resonant
00.0

2.0

W=2mm

0.5
1.0
1.5
Clock frequency [GHz]Clock power [mW]Clk

Clk inL

SRC(SW=Off)
150 SRC(SW=On)
100Fig10(c)50Non-resonant

00.02.0

W=0.5mm0.5
1.01.5Clock frequency [GHz]2.02.02.0

1.5

1.5

1.5

1.00.50.00

W=10mm
123Time [ns]4Voltage [V]2.0

Voltage [V]Voltage [V]

(a)
(b)
(c)
Fig. 9 Simulated clock frequency dependence of the clock power of the non-resonant clock and SRC with the gate width (W) of (a) 10mm, (b) 2mm and (c)0.5mm in Fig. 2(d).

1.00.50.00

W=2mm
123Time [ns]41.00.5

W=0.5mm0.00123Time [ns]

4(a)
(b)
(c)
Fig. 10 Simulated waveform of Clk of SRC(SW=Off) at 450-MHz clock with W of (a) 10mm, (b) 2mm and (c) 0.5mm.

4-5-335equivalent logic circuit. The calculated area penalty for theSRC is 4.8% assuming that the area of the flip-flops is 5% of
the logic circuits.
Fig. 12(a) shows the measured clock frequency dependenceof the clock power for the non-resonant clock and SRC where
SW is turned on and off. By turning off SW below 850MHz
and turning on SW above 850MHz, the proposed SRC cansolve the power increase problem at low clock frequency andreduce the clock power at the target high clock frequency. Fig.
12(b) compares the measured clock frequency dependence ofthe clock power for the non-resonant clock, the conventional
resonant clock in Fig. 2 and the SW-controlled SRC in Fig. 12(a). Compared with the non-resonant clock, the proposed SRC
reduced the clock power by 8% at the target high clock
frequency of 1.5GHz. Compared with the conventional
resonant clock, the proposed SRC also reduced the clock
power by 93% at the 20-MHz clock for the low-speedfunction tests. Fig. 13 shows the measured waveforms ofClkin and Clk for the non-resonant clock and SRC at 250MHz(low clock frequency) and 1.5GHz (target high clockfrequency). The double switching was not observed.

Clock power [mW]

150Inductor

Clk buffers

0.93 mm(a)(b)
Fig. 11 Fabricated SRC test chip. (a) Layout. (b) Micrograph.

Original
circuits

1.8V, 0.18µm CMOS
Clk buffers
Clk loads
Equivalent
to logic area

SRC

Area Penalty(a) Non-resonant

Clock power [mW]

150 (b) Conventional
resonant

100(c) Proposed SRC
8% power reduction
from (a) to (c) at 1.5GHz50SRCSRC(SW=Off) (SW=On)

00.0

0.5
1.0
1.5Clock Frequency [GHz]2.0

93% power reduction from (b) to (c) at 20MHz(b)Fig. 12 Measured clock frequency dependence of the clock power. (a) Nonresonant clock and SRC where SW is turned on and off . (b) Non-resonant
clock, conventional resonant clock and SW-controlled SRC.

Nonresonant

250MHz

1.5GHz

SW=Off

SW=On

Clk inClk

Clk inSRC

Clk

The authors appreciate M. Hamada and H. Majima of Toshiba
Corporation for their support. The VLSI chips were fabricated in the chip
fabrication program of VLSI Design and Education Center (VDEC), theUniversity of Tokyo in collaboration with Rohm Corporation and ToppanPrinting Corporation.

[1]8736µm2
8930µm2
2741000µm2 (a)Inductor (1.6nH)

58750µm2 (b)Capacitor (Cd) (200pF)

64700µm2 (c)Switch(b) + (c) + (d)
× 100
(a )

8733µm2 (d)Maximum Power Reduction

2.0

REFERENCES

Table I Performance Summary
Area

0.5
1.0
1.5
Clock Frequency [GHz]ACKNOWLEDGMENTS

Clk loads

Technology

Non-resonantFig. 13 Measured waveforms of Clkin and Clk for the non-resonant clock andSRC at 250MHz and 1.5GHz.

0.8 mmSwitch50(a)Novel frequency scalable SRC circuits for high-speed
microprocessors are proposed to solve the problems of boththe power increase at low clock frequency in the DFS and theinability to perform low-speed tests in the conventional
resonant clock. The SRC test chips in 0.18µm CMOS reduces
the clock power by 93% at 20-MHz clock and suppresses
double switching at low clock frequency, while reducing theclock power by 8% at 1.5-GHz clock with an area penalty of
4.8%. The proposed SRC allows DFS and the low-speed tests,
which expands the range of application of the resonant clock
distributions.

250µm

10000.0

V. CONCLUSIONS

Cd

SRC(SW=Off)
SRC(SW=On)

[2]
[3]
[4]

4.8%
8% at 1.8V, 1.5GHz

4-5-4

F. O’Mahony et al., “A Low-Jitter PLL and Repeaterless ClockDistribution Network for a 20Gb/s Link,” 2006 Symp. on VLSI Circuits,
pp. 36-37, Jun. 2006.
L. Lee and C.K. Yang, “An Adaptive Low-Jitter LC-Based ClockDistribution,” IEEE International Solid-State Circuits Conference, pp.
182-183, Feb. 2007.
S. Chan et al., “A Resonant Global Clock Distribution for the Cell
Broadband-Engine™ Processor,” IEEE International Solid-State
Circuits Conference, pp. 512-513, Feb. 2008.
C. Lichtenau et al., “PowerTune: Advanced Frequnecy and Power
Scaling on 64b PowerPC Microprocessor,” IEEE International SolidState Circuits Conference, pp. 356-357, Feb. 2004.

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