IEICE TRANS. ELECTRON., VOL.E83–C, NO.2 FEBRUARY 2000

161

INVITED PAPER

Special Issue on Low-Power High-Speed CMOS LSI Technologies

Low Power and Low Voltage MOSFETs with Variable
Threshold Voltage Controlled by Back-Bias
Toshiro HIRAMOTO†,††a) , Member and Makoto TAKAMIYA†† , Nonmember

SUMMARY We have studied the characteristic trade-oﬀs in
low power and low voltage MOSFETs from the viewpoint ofback-gate control and body eﬀect factor. Previously reported
MOSFET structures are classiﬁed into four categories in termsof back-gate structures. It is shown that a MOSFET with aﬁxed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic
threshold MOSFET with body tied to gate is more enhanced withincreasing body eﬀect factor. We have proposed a new dynamic
threshold MOSFET, electrically induced body (EIB) DTMOS,
which has a very large body eﬀect factor at low threshold voltage
and high current drive at low supply voltage.
key words: MOSFET, low power, low voltage, variable thresh-

old voltage, back-bias, body e ect, DTMOS, SOI
1.

Introduction

Low power technology has become one of the mainstream technologies in VLSI device design. The powerof high-end microprocessors is now more than 40 W.
According to the International Technology Roadmap
for Semiconductors (ITRS) [1], the power will be morethan 180 W in 2014 in microprocessors with heat sink.
In order to reduce the power, the supply voltage should
be reduced down to less than 0.6 V in 2014. Moreover,
the rapid spread of battery-operated portable systems
strongly demands a radical reduction of not only active power but also stand-by power. Very high-speed
devices with ultra-low power will be essential for mostof the VLSI applications in the future. Using conventional MOSFETs, however, it will be very hard to meet
all the requirements of high-performance VLSIs.
One of the most promising ways to attain both
high speed and low stand-by power at low supply voltage is to vary the threshold voltage of MOSFETs bychanging back-bias. Many devices and circuits for thevariable threshold voltage conﬁgurations have been reported previously for ultra-low power applications [2]–[13]. In particular, the dynamic threshold MOSFET(DTMOS) conﬁguration where the gate electrode is directly connected to the body or well region [6]–[13] has
many advantages including ideal subthreshold swing,
Manuscript received August 16, 1999.
Manuscript revised October 12, 1999.
†
The author is with VLSI Design and Education Center,
The University of Tokyo, Tokyo, 113-8656 Japan.
††
The authors are with Institute of Industrial Science,
The University of Tokyo, Tokyo, 106-8558 Japan.
a) E-mail: hiramoto@nano.iis.u-tokyo.ac.jp

high current drive, and better short channel eﬀect immunity. The control of the threshold voltage will be
inevitable for high-performance and low-voltage VLSIs
with ultra-low power consumption.
The body eﬀect factor γ is one of the most important parameters in a MOSFET with controlled threshold voltage. In order to change the threshold voltage bysmall back-bias, a large body eﬀect factor is required.
In conventional MOS circuits, however, a small body effect factor has been generally preferable because a large
body eﬀect degrades the current drive and circuit performance. Therefore, the optimum device design would
not be necessarily the same for conventional MOSFETs
and variable threshold devices. It strongly depends onwhether the body eﬀect is positively utilized or not.
In this paper, characteristics of low power and low
voltage MOSFETs with variable threshold voltage controlled by back bias are studied. In particular, special
focus is placed on the body eﬀect factor γ, and theadvantages and disadvantages of back-bias control are
discussed in terms of the body eﬀect factor. First, thetrade-oﬀs in low voltage MOSFETs are reviewed. Next,
MOSFET structures are classiﬁed into four categories
in terms of the back-gate conﬁgurations and possible
device structures with back-gates are reviewed. Then,the limitations of conventional MOSFETs with a ﬁxed
back-bias are pointed out and the advantages of the
dynamic threshold conﬁguration are demonstrated bymeans of two-dimensional device simulation. Finally,a new dynamic threshold MOSFET with a large bodyeﬀect factor is analyzed and its superiority is shown.
2.

Trade-Oﬀs in Low Voltage MOSFETs

In this section, the characteristic trade-oﬀs in conventional MOSFETs are discussed. First, the general relation between power consumption and circuit speed isconsidered. Next, the short channel eﬀect and current
drive in a MOSFET with a ﬁxed back-bias are discussed
from the viewpoint of the body eﬀect factor.
2.1 Power and Speed
The total power Ptotal and gate delay tpd of a CMOS
circuit are given by
Ptotal = Pactive + Pstand−by

IEICE TRANS. ELECTRON., VOL.E83–C, NO.2 FEBRUARY 2000

162

tpd ∝

= f Cload Vdd 2 + Ileak Vdd(1)

Cload Vdd
Vdd
∝
α
Ion
(Vdd − Vth )(2)

where Pactive is active power, Pstand−by stand-by power,
f operation frequency, Cload total load capacitance, Vdd
supply voltage, Ileak total leakage current, Ion current
drive of MOSFET, and Vth threshold voltage of thedevice. α is a factor depending on the carrier velocity
saturation and is about 1.3–1.5 in advanced MOSFETs[14]. Based on Eq. (1), the most eﬀective way to reduce
the total power is to reduce the supply voltage.
However, the reduction of the supply voltage
causes the reduction of gate drive (Vdd - Vth ), andhence, the severe degradation of circuit speed, as shownin Eq. (2). Although lowering the threshold voltage enhances gate drive, it leads to an exponential increasein subthreshold oﬀ-current and stand-by power. If thethreshold voltage is deﬁned as gate voltage when draincurrent is 10−7 A/µm, the oﬀ-current is given byVthIoﬀ= 10−7− S A/µm
Wg(3)

where S is subthreshold factor and Wg gate width. Inorder to suppress the oﬀ-current at a given thresholdvoltage, S should be reduced. However, the smallest
limit of S at room temperature is 60 mV/dec and thisvalue is not scaled. At very low supply voltage, therefore, it is very hard to attain both the high speed andlow stand-by current.
2.2 Body Eﬀect Factor and Subthreshold Factor
In the following subsections, the body eﬀect factor in a
device with a ﬁxed back-bias is considered. When the
body eﬀect factor γ is deﬁned as the ratio of thresholdvoltage shift to back-bias, γ is given by ∆Vth tox
 = Cd ∼

(4)
γ≡
=3
∆Vbs  Cox
ld
where Vbs is the back-bias, Cd depletion layer capacitance, Cox gate capacitance tox gate oxide thickness,and ld depletion layer width. When the gate oxide
thickness is constant, a device with thinner depletion
layer width (i.e. with higher impurity concentration in
the case of bulk MOSFET) has larger γ.
The subthreshold factor S at room temperature isgiven by
dVg
dψs




Cd ∼
tox
= 60 1 +mV/dec (5)= 60 1 + 3
Coxld

S = 60where ψs is surface potential, when the gate length islong enough and the short channel eﬀect can be neglected. From Eqs. (4) and (5), the relationship between the body eﬀect factor and subthreshold factor isgiven by
S = 60 (1 + γ) mV/dec(6)

This equation shows that a device with a larger body effect factor has a larger subthreshold factor and that theideal subthreshold factor (60 mV/dec) can be achieved
when the body eﬀect factor is zero.
2.3 Short Channel Eﬀect and Body Eﬀect Factor
The short channel eﬀect is strongly aﬀected by the depletion layer width. If the gate oxide thickness and thesource/drain junction depth are constant, a device withthinner depletion layer width has better short channel eﬀect immunity. From Eq. (4), therefore, the shortchannel eﬀect is closely related to the body eﬀect factor. A device with larger γ has better short channel
eﬀect immunity.
2.4 Current Drive and Body Eﬀect Factor
One more severe trade-oﬀ in a MOSFET with a ﬁxed
back-bias is the relationship between current drive andbody eﬀect factor. It is well known that current driveof a device with a higher body eﬀect factor is degradedby the bulk charge eﬀect. Moreover, the mobility is alsodegraded due to the high vertical electric ﬁeld because
the device has thin depletion layer width. Current drive
further decreases because threshold voltage should be
set higher to suppress the oﬀ-current due to larger subthreshold swing.
Figure 1 illustrates the relations among the subthreshold swing, body eﬀect factor, short channel effect, and current drive. A device with ideal subthreshold swing has very small body eﬀect factor and highcurrent drive, but has worse short channel eﬀect. On
the other hand, a device with better short channel eﬀect
has larger body eﬀect factor, but has worse subthreshold swing and smaller current drive.
Some of the above-mentioned trade-oﬀs in a MOSFET with a ﬁxed back-bias can be overcome by dynamic control of threshold voltage by changing backbias. Detailed simulation results in devices with a ﬁxed
back-bias and a variable back-bias will be shown in
Sect. 4.
3.

Classiﬁcation of MOSFETs by Back-Bias

In this section, MOSFETs are classiﬁed into four categories according to back-gate structures and back-gate
potentials. For simplicity, only the back-gate structure
and potential are considered. Figure 2 shows the classiﬁcation of MOSFETs. Schematic cross-sections andequivalent capacitance circuits are shown. Some of theHIRAMOTO and TAKAMIYA: LOW POWER AND LOW VOLTAGE MOSFETs WITH VARIABLE THRESHOLD VOLTAGE

163

reported device structures are classiﬁed and their qualitative characteristics are discussed.
3.1 Four Basic Structures
There are two basic back-gate structures, as shown in
Fig. 2. The ﬁrst structure is “bulk,” where the wellor body works as a back-gate and the back-gate is
faced to the channel via the depletion layer capaci-

Fig. 1 A schematic illustration of the relationships among thesubthreshold swing, body eﬀect factor, short channel eﬀect, andcurrent drive.

tance. The depletion layer width is usually determinedby the impurity concentration and its proﬁle. This
category includes conventional bulk MOSFETs, deltadoped MOSFETs [15], and partially depleted (PD) SOIMOSFETs. An electrically induced body (EIB) structure [12] that is discussed later is also classiﬁed into
this category. The second structure is basically a fully
depleted (FD) SOI structure although there are many
variations. There is a buried oxide layer under the channel and the back-gate is faced to the channel via FD SOI
capacitance CSOI and buried oxide capacitance Cbox .
On the other hand, the way of applying back-biases
to the back-gate is also classiﬁed into two categories.
The back-bias is ﬁxed in the ﬁrst category as is generally used. In the second category, the back-gate is tied
to the front gate and the device acts as a DTMOS or a
double gate (DG) MOSFET.
Then, all the device would be classiﬁed into four
categories, as shown in Fig. 2. The four categories arerespectively named as “conventional MOS,” “FD SOI
MOS,” “DTMOS,” and “DG MOS.” In the following
sections, characteristics of classiﬁed MOSFETs are analyzed. In some variable threshold voltage conﬁgurations, two back-biases are used so that the thresholdvoltage is low in the active mode and high in the standby mode. This two-back-bias conﬁguration is often
called as variable threshold MOSFET (VTMOS) [2].
The VTMOS conﬁguration is eliminated in the analysis in this paper, because the characteristics strongly
depend on the diﬀerence in two back-biases. Detailed
investigations of the VTMOS conﬁguration will be reported elsewhere [16].
3.2 Variations of Conventional MOSFETs

Fig. 2 Classiﬁcation of MOSFETs in terms of back-gate structures and back-gate potentials. Schematic cross-sections andequivalent capacitance circuits are shown.

Figure 3 shows some variations of “conventional MOS.”
A bulk MOSFET with uniform well impurity concentration (uniform bulk MOSFET) is a typical structurein this category. The depletion layer width of uniform
bulk MOS is aﬀected only by the channel impurity concentration. The well acts as a back-gate.
A delta-doped MOSFET [15] has a steep channel
concentration proﬁle, where a surface layer with low
concentration is on a layer with high concentration.

Fig. 3 Schematic cross-sections of variations of “conventional MOS.” Uniformly doped
bulk MOSFET, delta-doped MOSFET, PD SOI MOSFET, and EIB MOSFET are shown.

IEICE TRANS. ELECTRON., VOL.E83–C, NO.2 FEBRUARY 2000

164

Although many types of MOSFETs with channel engineering have been reported including retrograde channel, super steep retrograde channel [17], and groundplane [18], the characteristics of these MOSFETs are
just between the uniform bulk MOSFET and deltadoped MOSFET. In a delta-doped MOSFET, the depletion layer width roughly corresponds to the thickness of the surface layer with low concentration. It isreported that at a given threshold voltage, the depletion layer width of delta-doped MOSFET is half of thatof uniform bulk MOSFET [15]. Therefore, the deltadoped MOSFET generally has better short channel effect immunity and larger body eﬀect factor but worse
subthreshold swing and smaller current drive.
A PD SOI MOSFET is classiﬁed into this category
because the body is faced to the channel via the depletion layer capacitance and the equivalent circuit is thesame as that of a bulk MOSFET. The body acts as a
back-gate in PD SOI MOSFETs. When the body is
ﬂoating, characteristics vary drastically [19]. The ﬂoating body PD SOI MOSFET is out of the range of thispaper.
One way to increase the body eﬀect factor is tomake an EIB structure as shown in the ﬁgure [12], [13],[20]. Large substrate bias is applied to SOI substrate
to induce carriers in back Si/SiO2 interface and thiselectrically induced body acts as a back-gate. Since
the back-gate is faced to the channel via the depletion
layer, the EIB structure is also categorized in the “conventional” MOSFET. The depletion layer corresponds
to the thickness of SOI layer. Therefore, the body effect factor can be very large if the SOI thickness is verythin.

3.3 Variation of DTMOS
If the back-gates of above mentioned devices are tied togate electrodes, they become DTMOS. Figure 4 shows
variations of DTMOS structures. Bulk DTMOS [8]–[10], PD DTMOS [6], [7], [11], and EIB-DTMOS [12],[13] are shown in the ﬁgure. Since the back-bias follows the gate voltage, the surface potential also follows
the gate voltage and ideal subthreshold swing can beobtained in DTMOS as shown in Eq. (5).
3.4 Variations of FD SOI MOSFETs
Figure 5 shows examples of FD SOI MOSFETs. Quitea few structures using FD substrate or buried backgates have been reported as shown in the ﬁgure. In
FD SOI MOS, one of the concerns is the suppression ofshort channel eﬀect [19], [21], [22]. Basically, the discussions and Eqs. (1)–(6) in Sect. 2 apply to FD SOI MOS.
In this case, the depletion layer capacitance Cd in theequations should be replaced to the serial connectionof SOI capacitance CSOI and buried oxide capacitance
Cbox . When the buried oxide is thick, subthresholdswing is good and body eﬀect factor is small, but theFig. 4 Schematic cross-sections of variations of DTMOS. Bulk
DTMOS, PD DTMOS, and EIB-DTMOS are shown.

Fig. 5 Schematic cross-sections of examples of FD SOI MOSFETs. Normal FD SOIMOSFET and some other structures with buried back-gates are shown.

HIRAMOTO and TAKAMIYA: LOW POWER AND LOW VOLTAGE MOSFETs WITH VARIABLE THRESHOLD VOLTAGE

165

Fig. 6

Schematic cross-sections of examples of DG MOSFETs.

short channel eﬀect is worse. The SOI thickness shouldbe thin to suppress the short channel eﬀect. Althoughsome devices have very thin buried oxide to suppress
the short channel eﬀect, the devices show large subthreshold swing and current drive is degraded. Some
devices are also focused on the control of threshold voltage [23] and variable threshold using two back-biases[3], [4].
3.5 Variations of DG SOI MOSFETs
Figure 6 shows examples of DG SOI MOSFETs [24]–[26]. The main interest in DG MOS lies in the enhanced
current drive, ideal subthreshold swing, and suppression of short channel eﬀect. DG MOS has a diﬀerent
operation principle and higher current drive than DTMOS, because DG MOS has two conducting channels
in a front interface and a back interface. The discussions and equations in Sect. 2 are not necessarily valid in
DG SOI, and the body eﬀect factor bears less meaning.
Moreover, it is still very hard to fabricate self-aligned
DG structures [24], [27]. This structure is eliminated in
the following discussion in this paper. Detailed analysis
has been reported in Ref. [19].
4.

Characteristics of a Fixed Back-Bias andDynamic Back-Bias Conﬁgurations

In this section, the characteristics of classiﬁed device
structures are calculated by a two-dimensional device
simulator [28]. It is shown that the basic characteristics are primarily determined by the body eﬀect factor
γ, irrespective of device structures. It is found that inorder to obtain higher current drive, the body eﬀect factor should be small in a ﬁxed back-bias while it should
be as high as possible in a DTMOS conﬁguration.
4.1 Limitation of MOSFETs with a Fixed Back-Bias
Figure 7 shows the current drive of MOSFETs withﬁxed back-bias as a function of body eﬀect factor. Theoﬀ-current is set to a constant value of 10−8 A/µm by
adjusting the gate workfunction. Uniform bulk MOS,
delta-doped MOS, and FD SOI MOS are shown, where
well impurity concentration, thickness of low concentration layer, and buried oxide thickness are varied, respectively, to change the body eﬀect factor. Two cases

Fig. 7 Simulated current drive of uniform bulk MOSFET,
delta-doped MOSFET, and FD SOI MOSFET with ﬁxed backbias as a function of body eﬀect factor. The supply voltage is
0.6 V. Gate oxide thickness is 3 nm and junction depth is 15 nm.
The oﬀ-current is set to a constant value of 10−8 A/µm by adjusting the gate workfunction. Two cases of constant Lg (0.2µm) and Lg = Lmin are shown. Lmin is deﬁned as gate length
at which the threshold voltage roll-oﬀ is 0.1 V.

are considered. One is the case where gate length Lg isconstant. The other is where the short channel eﬀect isconsidered and Lg is set to Lmin at which the thresholdvoltage roll-oﬀ is 0.1 V.
It should be noted that the simulated data of current drive do not so much depend on device structures
but almost only on body eﬀect factor. This result indicates that current drive and short channel eﬀect areprimarily decided by the body eﬀect factor. The further reduction of current drive observed in uniform bulk
MOS at large body eﬀect factor is caused by the enhanced impurity scattering due to high impurity concentration at the surface. When channel length is constant, current drive monotonously decreases with increasing body eﬀect factor, as is qualitatively explainedin Sect. 2.
When Lg is set to Lmin , there is a maximum valueof the current drive. In a device with very small bodyeﬀect factor, current drive is small because Lmin is long
due to severe short channel eﬀect. As body eﬀect factor increases, Lmin become shorter and current driveincreases. When body eﬀect factor increases further,
the eﬀects of a decrease in Lmin and a degradation ofcurrent drive due to large body eﬀect are balanced, andﬁnally current drive is degraded at a higher body eﬀect
factor. This behavior and explanation are basically thesame as the discussion in Ref. [29].
These results expose the limitation of a MOSFET
with a ﬁxed back-bias. When gate length is constant,current drive can not exceed that of a device with γ = 0.
Even if the short channel eﬀect is suppressed and gate
length is reduced, the large increase in current drive is
not expected and the current drive becomes even worsewith increasing the body eﬀect factor. In order to at-

IEICE TRANS. ELECTRON., VOL.E83–C, NO.2 FEBRUARY 2000

166

Fig. 8

Schematic characteristics of DTMOS.
(a)tain higher current drive with ﬁxed oﬀ-current at very
low supply voltage, a dynamic control of threshold voltage by back-bias is strongly required.
4.2 Operation Principle of DTMOS
Figure 8 shows schematic characteristics of DTMOS.
Since the body is tied to the gate electrode, thresholdvoltage decreases due to the body eﬀect as the gate
voltage increases. When the gate voltage is Vdd , thethreshold voltage shift is given by∆Vth = γVdd

(7)

and the gate drive increases by γVdd . In order to increase the current drive, therefore, the body eﬀect factor should be as high as possible. Since the body potential follows the gate potential, the vertical ﬁeld is
low and the mobility degradation is suppressed. The
circuit speed degradation in the serially stacked MOSFETs is also avoided. Even when body eﬀect factor islarge, subthreshold swing is always ideal (60 mV/dec).
Figure 9 (a) shows simulated current drive of DTMOS as a function of body eﬀect factor. Delta-doped
impurity proﬁle is assumed. Current drive of deltadoped MOS with a ﬁxed back-bias is also shown in theﬁgure for comparison. Figures 9 (b) and (c) show Lminand subthreshold factor as a function of body eﬀect factor. It is clearly shown that the current drive is drastically improved by connecting the body to the gate.
In DTMOS with a constant Lg , current drive is almost
constant, because the improvement by large body effect factor and the degradation by higher vertical electric ﬁeld are balanced. On the other hand, current
drive monotonously increases with increasing body effect factor when Lg = Lmin , because the Lmin decreases
with increasing body eﬀect factor due to suppressedshort channel eﬀect as shown in Fig. 9(b). These results
clearly demonstrate that trade-oﬀs in a device with aﬁxed back-bias are solved in the DTMOS conﬁgurationand that both the high current drive and small oﬀcurrent can be achieved in DTMOS with a large bodyeﬀect factor.

(b)

(c)
Fig. 9 (a) Simulated current drive of DTMOS as a functionof body eﬀect factor. An impurity proﬁle of delta-doping is assumed. The supply voltage is 0.6 V. Gate oxide thickness is 3 nm
and junction depth is 15 nm. The oﬀ-current is set to a constantvalue of 10−8 A/µm by adjusting the gate workfunction. Twocases of constant Lg (0.2 µm) and Lg = Lmin are shown. Deltadoped MOS with a ﬁxed back-bias is also shown. (b) Lmin and(c) subthreshold factor as a function of body eﬀect factor.

5.

DTMOS with a Very High Body Eﬀect Factor

In this section, a new DTMOS, EIB-DTMOS, with avery high body eﬀect factor at low threshold voltage

HIRAMOTO and TAKAMIYA: LOW POWER AND LOW VOLTAGE MOSFETs WITH VARIABLE THRESHOLD VOLTAGE

167

is proposed. The high performance of EIB-DTMOS isdemonstrated.
5.1 Threshold Voltage and Body Eﬀect Factor
A very high body eﬀect factor is easily realized in uniformly doped DTMOS with a very high impurity concentration. However, there is a remaining trade-oﬀ in
DTMOS: the relationship between threshold voltage
and body eﬀect factor. Since the operation voltage of
DTMOS should be low due to forwarded pn junction
current, threshold voltage should also be low in DTMOS. In uniformly doped DTMOS, body eﬀect factor
is given by
tox∝ tox NA
(8)
γ∼
=3
ld
where NA is impurity concentration. This equation indicates that as body eﬀect factor increases, thresholdvoltage also increases when the gate work function is
ﬁxed. A large body eﬀect factor with low thresholdvoltage is hard to attain in uniformly doped DTMOS.
The body eﬀect factor in previously reported DTMOS
is around 0.2–0.3, because threshold voltage is set to asmall value [6], [8]. Then, threshold voltage shift at the
supply voltage of 0.5 V is about 0.1–0.15 V from Eq. (7)and the improvement of current drive is not suﬃcient.

Fig. 10 Schematic cross-sections of EIB-DTMOS. Inversion
mode EIB-DTMOS and accumulation mode EIB-DTMOS are
shown. Diﬀerent substrate biases, Vsub1 and Vsub2 , are applied
to NMOS and PMOS, respectively. Vsub1 and Vsub2 are supplied
from the front via contact holes through the buried oxide.

5.2 EIB-DTMOS
We have proposed EIB-DTMOS [12], [13] as a solution
to this trade-oﬀ. Figure 10 shows a schematic structure of EIB-DTMOS. The advantage of EIB-DTMOS
is that body eﬀect factor and threshold voltage are
separately determined. The body eﬀect is determinedby the SOI thickness while threshold voltage is determined by the doping concentration and its polarity inthe body. When the body has the opposite polarity assource and drain (i.e. the body is p-type in NMOS),
it acts as an inversion mode where threshold voltage
is higher than the intrinsic body. On the other hand,when the body has the same polarity as source anddrain, it acts as an accumulation mode where threshold voltage is lower.
Figure 11 shows the relation between body effect factor and threshold voltage in uniformly doped
DTMOS and an inversion mode EIB-DTMOS with aslightly B-doped body region. In both devices, threshold voltage increases with increasing body eﬀect factor.
At a ﬁxed threshold voltage, however, EIB-DTMOS
has about two times as large body eﬀect factor as uniformly doped DTMOS. This is because the depletion
layer width of EIB-DTMOS is half of that of uniformly
doped DTMOS [13]. An experimental datum of inversion mode EIB-DTMOS is also shown in the ﬁgure [13].
The experiment and simulation are in good agreement.

Fig. 11 Relation between body eﬀect factor and thresholdvoltage obtained by simulation in DTMOS. Uniformly doped
DTMOS and an inversion mode EIB-DTMOS with a slightly Bdoped body region are shown. An experimental datum is plotted.
An accumulation mode EIB-DTMOS is also plotted.

5.3 Accumulation Mode EIB-DTMOS
Even in the inversion mode EIB-DTMOS, a large bodyeﬀect factor is not achieved in low threshold voltage andone can not take full advantage of high current drive of
DTMOS. This problem is solved by an accumulation
mode EIB-DTMOS [12]. When the impurity concentration in the body (the same polarity as source/drain)

IEICE TRANS. ELECTRON., VOL.E83–C, NO.2 FEBRUARY 2000

168

shown that in dynamic threshold MOSFET where thebody is tied to the gate, the improvement of current
drive is more enhanced with increasing body eﬀect factor. For a very large body eﬀect factor at low thresholdvoltage, a new dynamic threshold MOSFET with electrically induced body using thin SOI layer is proposed
and its superiority is demonstrated.
Acknowledgement

Fig. 12 Relation between current drive and oﬀ-current in uniformly doped DTMOS, inversion mode DTMOS, and accumulation mode DTMOS. Threshold voltage is ﬁxed at Lg = 0.5 µm,
and Lg is varied. Gate oxide thickness is 3 nm and junction depth
is 15 nm.

is high enough, threshold voltage can be reduced down
to 0.1 V, while the body eﬀect factor is set to as high as
0.9 with very thin SOI thickness, as shown in Fig. 11.
Figure 12 shows the relation between current driveand oﬀ-current in uniformly doped DTMOS, inversion
mode DTMOS, and accumulation mode DTMOS [12].
Thanks to very large body eﬀect factor and suppressedshort channel eﬀect due to thin SOI thickness, the accumulation mode EIB-DTMOS shows high current driveat very low oﬀ-current.
The superior ac characteristics of accumulation
mode EIB-DTMOS have been also conﬁrmed by mixedmode device simulation [12]. Since DTMOS generally has additional gate capacitance between body andchannel and parasitic capacitance between body andsource/drain, the improvement of gate delay is moreenhanced when load capacitance is larger. One of thedisadvantages of DTMOS using SOI is high body resistance by which the body potential does not follow
the gate voltage, resulting in degradation of gate delay.
To avoid this eﬀect, bulk DTMOS with smaller well resistance has been proposed [8]–[10]. In EIB-DTMOS,
since the body is electrically formed, the body resistance is higher than uniformly doped DTMOS and bulk
DTMOS. This problem can be resolved by parallel connection of divided MOSFETs to achieve smaller ratioof channel width to channel length [12]. Detailed analysis of body resistance in EIB-DTMOS will be reported
elsewhere [30].
6.

Conclusions

Characteristics of low voltage MOSFETs are reviewed
from the viewpoint of back-gate structures and bodyeﬀect factor. Previously reported device structures areclassiﬁed into four categories and the limitation of a
MOSFET with a ﬁxed back-bias is shown. It is also

The authors would like to express their sincere gratitude to Profs. T. Ikoma, H. Fujita, and T. Sakurai
for their fruitful discussions and continuous encouragement. This work was partially supported by the JSPS
Research for the Future Program.
References[1] International Technology Roadmap for Semiconductors, 1999 Edition, 1999. http://notes.sematech.org/ntrs/
PublNTRS.nsf[2] T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka,
K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako,
M. Kinugawa, M. Kakumu, and T. Sakurai, “A 0.9-V, 150MHz, 10-mW, 4mm2 , 2-D discrete cosine transform core
processor with variable threshold-voltage (VT) scheme,”
IEEE J. Solid-State Circuits., vol.31, no.11, pp.1770–1779,
Nov. 1996.
[3] I.Y. Yang, C. Vieri, A. Chandrakasan, and D.A. Antoniadis, “Back gated CMOS on SOAIS for dynamic thresholdvoltage control,” IEDM Technical Digest, pp.877–880, Dec.
1995.
[4] T. Kachi, T. Kaga, S. Wakahara, and D. Hisamoto, “Variable threshold-voltage SOI CMOSFETs with implanted
back-gate electrodes for power-managed low-power andhigh-speed sub-1-V ULSIs,” Symposium on VLSI Technology Digest of Technical Papers, pp.124–125, June 1996.
[5] T. Douseki, S. Shigematsu, Y. Yanabe, M. Harada,
H. Inokawa, and T. Tsuchiya, “A 0.5 V SIMOX-MTCMOS
circuits with 200ps logic gate,” ISSCC Digest of TechnicalPapers, pp.84–85, Feb. 1996.
[6] F. Assaderaghi, D. Sinitsky, S. Parke, J. Boker, P.K. Ko,
and C. Hu, “A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation,” IEDM Technical Digest, pp.809–812, Dec. 1994.
[7] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi,
and Y. Taur, “Channel proﬁle optimization and device
design for low-power high-performance dynamic-threshold
MOSFET,” IEDM Technical Digest, pp.113–116, Dec.
1996.
[8] H. Kotaki, S. Kakimoto, M. Nakono, T. Matsuoka,
K. Adachi, K. Sugimoto, T. Fukushima, and Y. Sato,“Novel bulk dynamic threshold voltage MOSFET (BDTMOS) with advanced isolation (SITOS) and gate toshallow-well contact (SSS-C) processes for ultra low power
dual gate CMOS,” IEDM Technical Digest, pp.459–462,
Dec. 1996.
[9] A. Shibata, T. Matsuoka, S. Kakimoto, H. Kotaki,
M. Nakono, K. Adachi, K. Ohta, and N. Hashizume, “Ultra
low power supply voltage (0.3 V) operation with extreme
high speed using bulk dynamic threshold voltage MOSFET(B-DTMOS) with advanced fast-signal-transmission shallow well,” Symposium on VLSI Technology Digest of Technical Papers, pp.76–77, June 1998.

HIRAMOTO and TAKAMIYA: LOW POWER AND LOW VOLTAGE MOSFETs WITH VARIABLE THRESHOLD VOLTAGE

169[10] H. Kotaki, S. Kakimoto, M. Nakono, K. Adachi, A. Shibata, K. Sugimoto, K. Ohta, and N. Hashizume, “Novellow capacitance sidewall elevated drain dynamic thresholdvoltage MOSFET (LCSED) for ultra low power dual gate
CMOS technology,” IEDM Technical Digest, pp.415–418,
Dec. 1998.
[11] T. Tanaka, Y. Momiyama, and T. Sugii, “Fmax enhancement of dynamic threshold-voltage MOSFET (DTMOS)
under ultra-low supply voltage,” IEDM Technical Digest,
pp.423–426, Dec. 1997.
[12] M. Takamiya and T. Hiramoto, “High performance electrically induced body dynamic threshold SOI MOSFET (EIBDTMOS) with large body eﬀect and low threshold voltage,”
IEDM Technical Digest, pp.423–426, Dec. 1998.
[13] M. Takamiya, T. Saraya, T.N. Duyet, Y. Yasuda, and T. Hiramoto, “High performance accumulated back-interface dynamic threshold SOI MOSFET (AB-DTMOS) with large
body eﬀect at low supply voltage,” Jpn. J. Appl. Phys.,vol.38, part 1, no.4B, pp.2483–2486, April 1999.
[14] T. Sakurai and A.R. Newton, “Alpha-power law MOSFET
model and its application to CMOS inverter delay andother formulas,” IEEE J. Solid-State Circuits., vol.25, no.2,
pp.584–594, April 1990.
[15] K. Noda, T. Tatsumi, T. Uchida, K. Nakajima,
H. Miyamoto, and C. Hu, “A 0.1-µm delta-doped MOSFET
fabricated with post-low-energy implanting selective epitaxy,” IEEE Trans. Electron Devices, vol.45, no.4, pp.809–
814, April 1998.
[16] H. Koura, T. Takamiya, and T. Hiramoto, “Optimum conditions of body eﬀect factor and substrate bias in variable
threshold voltage MOSFETs,” Extended Abstract of the1999 International Conference on Solid State Devices andMaterials, pp.446–447, Sept. 1999.
[17] D.A. Antoniadis and J.E. Chung, “Physics and technology
of ultra short channel MOSFET devices,” IEDM Technical
Digest, pp.21–24, Dec. 1991.
[18] R.H. Yan, A. Ourmazd, and K.F. Lee, “Scaling the Si MOSFET: From bulk to SOI to bulk,” IEEE Trans. Electron
Devices, vol.39, no.7, pp.1704–1710, July 1992.
[19] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to
VLSI, 2nd edition, Kluwer Academic Publisher, 1997.
[20] T. Shimatani, S. Pidin, and M. Koyanagi, “New electrically intrinsic-channel SOI MOSFET with 0.01 µm channel
length,” Extended Abstract of the 1996 International Conference on Solid State Devices and Materials, pp.494–496,
Aug. 1996.
[21] Y. Ohmura, S. Nakashima, K. Izumi, and T. Ishii, “0.1-µmgate ultrathin-ﬁlm CMOS devices using SIMOX substratewith 80-nm-thick buried oxide layer,” IEDM Technical Digest, pp.675–678, Dec. 1991.
[22] M. Horiuchi, T. Teshima, K. Tokumasu, and K. Yamaguchi,“High-current, small parasitic capacitance MOS FET ona poly-Si interlayered (PSI: Ψ) SOI wafer,” Symposium
on VLSI Technology Digest of Technical Papers, pp.33–34,
June 1995.
[23] H.-S. Wong, D.J. Frank, and P.M. Solomon, “Device design
consideration for double-gate, ground-plane, and singlegated ultra-thin SOI MOSFET’s at the 25 nm channel
length generation,” IEDM Technical Digest, pp.407–410,
Dec. 1998.
[24] H.-S. Wong, K.K. Chan, and Y. Taur, “Self-aligned (topand bottom) double-gate MOSFET with a 25 nm thick silicon channel,” IEDM Technical Digest, pp.427–430, Dec.
1997.
[25] J. Park, Y. Kim, I. Kim, K. Park, H. Yoon, K. Lee, and
T. Jung, “Performance characteristics of SOI DRAM for
low-power application,” ISSCC Digest of Technical Papers,

pp.434–435, Feb. 1999.
[26] T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, “Ultrafast
operation of Vth-adjusted p+ -n+ double-gate SOI MOSFET‘s,” IEEE Electron Device Lett., vol.15, no.10, pp.386–
388, 1994.
[27] D. Hisamoto, W. Lee, J. Kedzierski, E. Anderson,
H. Takeuchi, K. Asano, T. King, J. Boker, and C. Hu, “Afolded-channel MOSFET for deep-sub-tenth micron era,”
IEDM Technical Digest, pp.1032–1034, Dec. 1998.
[28] Medici Ver. 4.1, Avant! Corp., July 1998.
[29] C. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, “A
comparative study of advanced MOSFET concepts,” IEEE
Trans. Electron Devices, vol.43, no.10, pp.1742–1753, Oct.
1996.
[30] M. Takamiya and T. Hiramoto, unpublished.

Toshiro Hiramoto
received the B.S.,
M.S. and Ph.D. degrees in electronics
from University of Tokyo in 1984, 1986,
and 1989, respectively. In 1989, he joined
Device Development Center, Hitachi Ltd.,
Ome, Japan, where he was engaged in device and circuit design of ultra-fast BiCMOS SRAM. Since 1994, he has been an
Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo,
Japan. He has been also an Associate
Professor in VLSI Design and Education Center, Univerisity ofTokyo, Tokyo, Japan since 1996. His research interests include
low power device design, sub-100 nm CMOS devices, SOI MOSFETs, silicon single electron devices, and quantum eﬀects inscaled MOSFETs.

Makoto Takamiya
was born in
Hyogo, Japan, in 1973. He received the
B.S. and M.S. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 1995 and 1997, and is now
working towards the Ph.D. degree in Institute of Industrial Science, University ofTokyo. He has been engaged in the research of low power SOI CMOS devices.
His research interests include scaling of
MOSFET’s into sub- 0.1 µm region andultra low-voltage MOSFET’s. He received the Young ResearcherAward of 1999 International Conference on Solid State Devices
and Materials.