Investigation of Determinant Factors of Minimum Operating
Voltage of Logic Gates in 65-nm CMOS
Tadashi Yasufuku1, Satoshi Iida1, Hiroshi Fuketa1, Koji Hirairi2, Masahiro Nomura2,
Makoto Takamiya1, and Takayasu Sakurai1
12Institute of Industrial Science, University of Tokyo, Japan
Semiconductor Technology Academic Research Center (STARC), Japan
tdsh@iis.u-tokyo.ac.jp
stage, 101st stage and so on. The NAND chain has 100001(100k) stages of 2NANDs with similar ports. Fig. 1(c) shows adetailed schematic diagram of the inverters used in the inverter
chain of Fig. 1(a). The body-bias voltages of both the nMOS
transistors (Vbs(nMOS)) and the pMOS transistors (Vbs(pMOS)) can
be controlled. Note that when Vbs(nMOS) is positive the nMOS
transistors are forward biased, whereas when Vbs(pMOS) is

Abstract— Determinant factors of the minimum operating
voltage (VDDmin) of CMOS logic gates are investigated bymeasurements of logic-gate chains in 65nm CMOS. VDDmin
consists of a systematic component (VDDmin(SYS)) and a randomvariation component (VDDmin(RAND)). VDDmin(SYS) is minimized,
when the logic threshold voltage of logic gates equals to half
supply voltage (VDD). The tuning of the logic threshold voltage ofeach logic gate is achieved by the sizing of the gate width ofnMOS/pMOS. VDDmin(RAND) is minimized by reducing the random
threshold variation achieved by increasing the gate width or theforward body biasing. In addition, the temperature dependence
of VDDmin is measured for the first time. The temperature for the
worst corner analysis for VDDmin should be changed depending on
the number of gate counts of logic circuits.

11-stage

101-stage

1001-stage
10001-stage

VOUT(10001)

VIN
VOUT(11) VOUT(101) VOUT(1001)

(a)

I.

INTRODUCTION

11-stage

Reduction of power supply voltage (VDD) is an effective
method for achieving ultra low power logic circuits since active
power is proportional to VDD2 and leakage power is
proportional to VDD. Thus, many works have been carried out
on logic circuits operating at low VDD [1-2]. VDD scaling is,however, obstructed by the minimum operating voltage(VDDmin) [3] of CMOS logic gates. VDDmin is the minimum
power supply voltage when the circuits operate without
function errors. VDDmin increases with the number of logic gates
and CMOS technology down-scaling. Thus, reducing VDDmin of
logic circuits is important to achieve ultra low voltage (VDD <0.4V) logic circuits. Previously, there were no design guides toreduce VDDmin of circuits since the determinant factors of
VDDmin were not clarified. In this paper the determinant factorsof VDDmin in logic circuits are investigated, and the design
criteria to reduce VDDmin are presented. Also, temperaturedependency of VDDmin is measured, revealing for the first time,that the VDDmin under the worst condition depends on the gate
counts of logic circuits.

VIN

VOUT(100001)
VOUT(11) VOUT(101) VOUT(1001) VOUT(10001)

(b)
VDD
WP

WN
VSS
(c)

Vbs(nMOS)

Fig.1 Schematic diagram of fabricated chains to measure VDDmin. (a)Inverter chain. (b) 2 input NAND (2NAND) chain. (c) Inverter used in the
chain in (a).

0.8mm

100001-stage
2NAND chain

TEST CHIP DESIGN

Figs. 1(a) and (b) show schematic diagrams of the inverterand 2 input NAND (2NAND) chains of which the VDDmin aremeasured. The inverter chain has 10001 (10k) stages of
inverters and has monitoring ports branching out from the 11th

978-1-61284-660-6/11/$26.00 © 2011 IEEE

Vbs(pMOS)
OUT

IN

Section II discusses the design of the test chip. The circuit
schematics of the inverter and 2 input NAND chains are shown.
Section III shows experimental results of VDDmin. Determinantfactors of VDDmin, gate sizing and body-biasing to reduce
VDDmin, and temperature dependence is discussed. Section IV
concludes this paper.
II.

101-stage
1001-stage
10001-stage100001-stage

(a)

1mm
(b)

Fig.2 Test chip of 2NAND chain fabricated in 65-nm CMOS. (a) Layout.
(b) Chip micrograph.

21

positive the pMOS transistors are reverse biased. The gate
lengths of all transistors are fixed to the minimum of theprocess, and WN and WP are the gate widths of the nMOS andpMOS transistors, respectively. Fig. 2 shows the layout andchip micrograph of the test chip of the 2NAND chain. Both theinverter chain and the 2NAND chain circuits are fabricated in a
65nm CMOS process occupying 0.4mm x 0.6mm, and 1mm x
0.8mm, respectively.
III.

250

VDDmin [mV]200

EXPERIMENTAL RESULTS

2NAND(Measurement)
2NAND(Simulation)

150
Inverter(Measurement)

100

Inverter(Simulation)

50

A.

Determinant factors of VDDmin
Fig. 3 shows measured and simulated dependence of VDDminon the number of stages in the inverter and 2NAND chains.
The average VDDmin in the measured 17 dies for 2NAND and 20
dies for inverter is shown. Monte Carlo SPICE simulation
includes within-die random threshold voltage (VTH) variations
and the number of trials of the Monte Carlo simulation is 100
times. Fig. 3 indicates that VDDmin increases as the number ofstages increases. Note that the simulations are executed only up
to 1k stages due to the simulation time constraint. Since thesimulated results agree with the measurements in Fig. 3,
various simulations are conducted to clarify determinant factorsof VDDmin in the rest of this paper.

0

 pn
a

N
ln   c , b

 pn   p 2   n 2 ,

150

LW

,

10k

100k

Inverter

VDDmin [mV]

Simulation withrandom transistor variation(1)

Random variation
component(=VDDmin(RAND))

100

V DD min 

50

0Simulation without
random transistor variation

10

(2)

 pn
a

N
ln   c
 b

Systematiccomponent(=VDDmin(SYS))

100

Number of stages

1k

Fig.4 Simulated dependence of VDDmin on number of stages in inverter chain
with and without random VTH variation.
150

VDDmin [mV]

AVT

1k

Fig.3 Measured and simulated dependence of VDDmin on number of stages ininverter and 2NAND chains.

where N is the number of stages, p (n) is the standard
deviation of within-die VTH variations of pMOS (nMOS), a is
a constant determined by DIBL coefficient, b is a constantdetermined by yield, and c denotes the balance of the strengthof nMOS and pMOS. The standard deviation () of VTH
variation can be expressed as noted in [5],

100

Number of stages

A closed-form expression of the VDDmin described in [4] isshown as,V DD min 

10

(3)

where AVT is Pelgrom coefficient, L is the gate length, and W
is the gate width.
By using Eq. (1), determinant factors of VDDmin areinvestigated in this paper. Fig. 4 shows the simulated
dependence of VDDmin on the number of stages in the inverter
chain with and without random VTH variation. VDDmin consistsof the following two components; the systematic component(VDDmin(SYS)), and the random variation component(VDDmin(RAND)). VDDmin(SYS) is obtained by simulations without
within-die VTH variation represented as the lower line, while
VDDmin(RAND) is defined as the difference between two lines inFig. 4. While VDDmin(RAND) depends on the number of stages,
VDDmin(SYS) does not. Therefore, VDDmin(RAND) corresponds tothe first term in Eq. (1) and VDDmin(SYS) corresponds to thesecond term (=c) in Eq. (1). VDDmin(RAND) depends on the
random VTH variation and the number of stages of logic gates,
while VDDmin(SYS) is determined by the balance of nMOS andpMOS.

101-stage inverter
Simulation withrandom variation

Random variation
component

100(=VDDmin(RAND))

50 Simulation without
Minimum VDDmin
random variation

Systematiccomponent(=VDDmin(SYS))

0-120 -100 -80 -60 -40 -20

0

20 40

Weak

60

StrongThreshold voltage shift ofpMOS (VTP)[mV]

Fig.5 Simulated dependence of VDDmin of inverter chain on VTH shift ofpMOS (VTP) with and without random VTH variation.

B. Gate sizing to reduce VDDmin
In order to examine the dependence of VDDmin on thebalance of the drive strength of nMOS and pMOS, Monte
Carlo simulations for the 101-stage inverter chain are
conducted with various VTH of pMOS to change the balance.
Fig. 5 shows the simulated dependence of VDDmin of theinverter chain on VTH shift of pMOS (VTP) with and without

22

1.0
Inverter
2NAND
3NAND

Simulation

Logic threshold voltage
normalized by VDD

Logic threshold voltage
normalized by VDD

1.0

VDD=70mV
VDD=150mV

Half VDD

0.5

VDD=100mV
Minimum VDDmin@VTP= -30mV

0.0-120 -100 -80 -60 -40 -20 0 20 40
Threshold voltage shift ofpMOS (VTP)[mV]

VIN = VOUT =Logic thresholdvoltage60

4NAND
Optimized

0.5

Half VDD
3NOR
2NOR

VDD=100mV
Simulation

0.0

Fig.6 Simulated dependence of normalized logic threshold voltage on
VTP at different VDD without random VTH variation.

4NOR

0.1

1

(WP/WN)

10

Fig.8 Simulated dependence of normalized logic threshold voltage on
normalized WP/WN for 7 types of logic gates.

threshold voltage on VTP at different VDD is simulated without
random VTH variation as shown in Fig. 6. The definition of thelogic threshold voltage is shown in the inset of Fig. 6. The logic
threshold voltage is normalized by each VDD. When the logic
threshold voltage is equal to half VDD at each VDD, VTP is 30mV, where the minimum VDDmin is achieved as shown in Fig.
5. This result indicates that VDDmin(SYS) is minimized when the
logic threshold voltage is equal to half VDD.

VDDmin [mV]200

Fig. 7(a) shows the simulated dependence of VDDmin of 7
types of 101-stage chains with different logic gates. WP/WN of
all logic gates is constant which is defined as  in Fig. 7(a) andall logic gates operate as an inverter, i.e. one of the inputs ofeach logic gate is connected to the output of the previous stage
and other inputs are tied to VDD or VSS in NAND and NORgates, respectively. As shown in Fig. 7(a), VDDmin of each logic
gate is divided into VDDmin(SYS) and VDDmin(RAND). VDDmin(SYS)
increases as the number of inputs of the logic gates increases(e.g. 4NAND and 4NOR), because stacking and parallelingtransistors worsen the balance of the strength of nMOS andpMOS and hence the logic threshold voltages deviate from half
VDD. In contrast, VDDmin(RAND) decreases as the number of
inputs of the logic gates increases, because stacking andparalleling transistors decreases the transistor variations.

Systematic Component

Simulation, 101-stage
150 WP/WN=Optimized

100

50
66

0

83

94

102
83

94

102

Logic threshold voltages, however, can be tuned to half
VDD by changing the gate size (WP/WN) in each logic gate at adesign stage. Fig. 8 shows the simulated dependence of
normalized logic threshold voltage on the normalized WP/WN.
for 7 types of logic gates. For example, in 4NAND gate, when
WP/WN is 0.11 , the logic threshold voltage is half VDD, whichmeans that WN of 4NAND must be 8.8 WP to minimize
VDDmin(SYS). When too large or small WP/WN is not acceptable
due to the area constraint, the logic gates with a lot of inputs(e.g. 4NAND and 4NOR) should not be used in the design ofsubthreshold logic circuits. Fig. 7(b) shows the simulated
dependence of VDDmin(SYS) of 7 types of 101-stage chains withdifferent logic gates when WP/WN of each logic gate is
optimized to have the logic threshold voltage of half VDD as
shown in Fig. 8. For example, in 4NAND gate, VDDmin(SYS) canbe reduced from 162mV to 102mV by optimizing WP/WN. as
shown in Figs. 7(a) and (b). VDDmin(SYS) in Fig. 7(b) increases
with increasing number of inputs of the logic gates, because theInverter 2NAND 3NAND 4NAND 2NOR 3NOR 4NOR

Gate type(b)

Fig.7 Simulated dependence of VDDmin of 7 types of 101-stage chains withdifferent logic gates. (a) WP/WN of all logic gates is constant . (b) WP/WN
of each logic gate is optimized as shown in Fig. 8.

random VTH variation. In this simulation, VTP is shifted bychanging the parameter in SPICE. VDDmin(SYS) depends on VTP
and is minimum at VTP=30mV, where nMOS and pMOS arebalanced. On the other hand, VDDmin(RAND) is constant, because
 of within-die VTH variation does not depend on VTP. This
result indicates that VDDmin(SYS) is determined by the balance ofnMOS and pMOS, which is predicted by Eq. (1).
In [6], VDDmin(SYS) of subthreshold circuits is minimized bytuning the logic threshold voltage to half VDD. To confirm theeffect of this tuning, the dependence of the normalized logic

23

150

x4 inverter V
VDDmin(RAND)
DDmin(SYS)of all inverters

50

WP/WN = Simulation

10

100

Number of stages

ReverseNMOS body bias[mV]

x2 inverter

100

-300
-200
Initial

0
100
200

y
od
lb
a
tim
Op

300
400

s
bia

500
-400 -300 -200 -100 0

1k

375
355
335
315
295
275
255
235
215
195
175
155
135

100001-stage
2NAND
Measured-100

Forward

VDDmin [mV]x1 inverter

0

VDDmin [mV]

-400

100 200 300 400 500
ReverseForwardPMOS body bias[mV]Fig.9 Simulated dependence of VDDmin on number of stages in inverter
chains with 3 types of gate width.

Fig.11 Measured dependence of VDDmin in 100001-stage 2NAND chain on
body bias of nMOS and pMOS.

250
200

VDDmin [mV]

VDDmin [mV]

200 Wafer 1 (Same as Fig. 3)
150
100

Wafer 2150

Systematic Component, VDDmin(SYS)
Simulation
101-stage inverter
-88mV

100
-5mV

108

50
71

50
0

2NAND
Measurement

10

100

1k

10k

Number of Stages

-40mV
154

0

100k

TT

66

66

TT

(Compensated)@Vbs(pMOS) = 0.13V

SF

SF(Compensated)@Vbs(pMOS) = 0.72V

68

FS

FS

(Compensated)@Vbs(pMOS) = -0.32

SF nMOS: Slow, pMOS: FastFS nMOS: Fast, pMOS: Slow

Fig.12 Simulated VDDmin(SYS) with and without the compensation using
pMOS body-biasing in 101-stage inverter chain.

Fig.10 Measured dependence of VDDmin on number of stages in 2NAND
chains in 2 wafers with different process corner.

C. Body-biasing to reduce VDDmin
Fig. 10 shows measured dependence of VDDmin on thenumber of stages in 2NAND chains in 2 wafers with different
process corner. 17 dies in wafer 1 and 42 dies in wafer 2 aremeasured. The upper line is the same line depicted in Fig. 3 andthe lower line shows a different lot. These two lines aredifferent, because the balance of nMOS and pMOS differs
between the two lots due to die-to-die VTH variation. In order toreduce such VDDmin(SYS) due to the die-to-die VTH variation,body-biasing is effective to compensate for the die-to-die VTH
variation. In this section, the effect of body-biasing isinvestigated.

inverter gain is degrade in stacked transistors. It is noted that
VDDmin(SYS)’s of the number of inputs of the logic gates ( e.g.
2NAND and 2NOR) are the same, because the number of thestacked transistors is the same.
While VDDmin(SYS) is minimized by optimizing WP/WN,
VDDmin(RAND) is reduced by increasing WN and WP. Fig. 9 shows
the simulated dependence of VDDmin on the number of stages in
the inverter chain with 3 types of gate width. The gate widthsof nMOS and pMOS in “x2 inverter” are two times larger thanthose in “x1 inverter.” WP/WN is  in all the inverters. The gate
width does not affect the balance of the strength of nMOS andpMOS. Therefore, VDDmin(SYS)’s of the three types of gate
chains is completely identical as illustrated in Fig. 9. On theother hand, as the gate width increases, VDDmin(RAND) decreases,
 of within-die VTH variation is reduced, which is expressed in
Eq. (1). Consequently, VDDmin of the “x4 inverter” chain is thelowest.

Fig. 11 shows measured dependence of VDDmin in a 100001(100k)-stage 2NAND chain on the body bias voltage of nMOS
and pMOS. When nMOS and pMOS are well-balanced, VDDmin
is low as shown in the optimal body bias line. In contrast, whennMOS and pMOS are unbalanced, VDDmin increases. The initial
VDDmin is 189mV, when both body bias voltages are 0V. The
lowest VDDmin was 135mV at Vbs(NMOS)= 400mV and Vbs(PMOS)=

24

250

Next, the feasibility of the post-fabrication compensation at
unbalanced process corners is investigated with the 101-stage
inverter chain. Fig. 12 shows simulated VDDmin(SYS) with andwithout the compensation using pMOS body-biasing. The
unbalanced process corner conditions are SF and FS. SF means
slow nMOS (= high VTH) and fast pMOS, whereas FS means
fast nMOS (= low VTH) and slow pMOS. TT means typicalnMOS and pMOS, which is included as a reference. The
compensation using pMOS body-biasing reduces VDDmin(SYS) by
88mV (from 154 mV to 66 mV) and 40mV (from 108 mV to 68mV) in SF and FS conditions, respectively. The compensated
VDDmin(SYS)’s of the three process corners show almost samevalues, since the strength of pMOS and nMOS is well-balanced
by body-biasing. Thus, the increase in VDDmin(SYS) due to the dieto-die VTH variation is compensated by the post-fabrication
body-biasing.

200

VDDmin [mV]

-300mV. This indicates that balancing the nMOS and pMOS
using body-biasing is effective to reduce VDDmin(SYS).

Zero Body Bias
Reverse Body Bias

45mV

150
100

Forward Body Bias50
Measurement, 2NAND

0

100

1k

10k

100k

Number of stages

Fig.13 Measured dependence of VDDmin on number of stages in threebody-bias conditions in 2NAND chain.

In addition, the body-biasing also affects VDDmin(RAND).
Within-die VTH variation is reduced by forward body biasing [7].
Tuning of both VDDmin(SYS) and VDDmin(RAND) by the body-biasing
is demonstrated in the measurement. Fig. 13 shows measured
dependence of VDDmin on the number of stages in three bodybias conditions for the 2NAND chain. Table I summarizes the
body bias conditions. Zero body bias is the initial condition and
nMOS and pMOS are not balanced. On the other hand, the drive
strength of pMOS and nMOS are balanced by optimizing
forward body biasing or reverse body biasing as shown in Table
I. Fig. 13 indicates that VDDmin of both reverse and forward bodybias at 101 stages is lower than that of zero body bias, because
VDDmin(SYS) is minimized by the optimal body biasing. It is notedthat the gradient of the line shown in Fig. 13 of reverse andforward body bias is different. The gradient of the reverse bodybias is steep, while the gradient of the forward body bias isgentle, which indicates that VDDmin(RAND) is reduced by theforward body bias because within-die VTH variation is reduced.
For example, compared with the initial zero body bias,
measured VDDmin is reduced by 45mV from 193 mV to 148mV
by forward body biasing at 100k stages. Thus, the optimal bodybiasing minimizes VDDmin(SYS) and the forward body biasing
decreases VDDmin(RAND).

Table I Body bias conditions used in Fig. 13.

NMOS Body
Bias, Vbs(nMOS)PMOS Body
Bias, Vbs(pMOS)

Zero Body Bias

0V

0V

Forward Body Bias

0.1V

-0.25V

Reverse Body Bias

-1.0V

0.6V

200

VDDmin [mV]

10001-stage
25mV

150

100

1001-stage 101-stage

11-stage

10mV

50

Measurement, inverter

D. Temperature dependence of VDDmin
The temperature dependence of VDDmin is discussed in thissection. This is the first work to report the temperaturedependence of VDDmin. Fig. 14 shows the measured dependence
of VDDmin on temperature in various inverter chains. The
temperature dependence of VDDmin varies with the number ofstages of the chain. At 11-stage chain, VDDmin increases by
10mV as temperature increases from -40˚C to 110˚C. Thisphenomenon is considered as a result of increase in VDDmin(SYS),
since VDDmin(SYS) depends on the thermal voltage and the rise intemperature increases VDDmin(SYS) [4]. On the other hand, at
10001-stage chain, VDDmin decreases by 25mV as temperature
increases from -40˚C to 110˚C. This phenomenon implies that
VDDmin(RAND) decreases as the temperature increases, because
AVT decreases with increasing temperature [8]. As a result, theworst (=highest) VDDmin condition of logic circuits with small
gate counts is high temperature, while the worst VDDmin

0-40 -20

0

20

40

60

80 100 120

Temperature [ C]Fig.14 Measured dependence of VDDmin on temperature in various inverter
chains.

condition of logic circuits with large gate counts is the worst at
low temperature. Therefore, the temperature for the worst
corner analysis for VDDmin should be changed depending on thenumber of gate counts of logic circuits.
IV.

CONCLUSION

Determinant factors of VDDmin of CMOS logic gates areinvestigated and a design guide to reduce VDDmin are shown bymeasurements and SPICE simulations of logic-gate chains in
65nm CMOS. VDDmin consists of VDDmin(SYS) and VDDmin(RAND).

25

VDDmin(RAND) depends on the random VTH variation and thenumber of stages of logic gates, while VDDmin(SYS) is determinedby the balance of nMOS and pMOS and is minimized when the
logic threshold voltage is equal to half VDD. Therefore,
VDDmin(RAND) is reduced by increasing WN and WP, while
VDDmin(SYS) is minimized by optimizing WP/WN at a design stage.
The body-biasing is effective to compensate for the increase of
VDDmin(SYS) due to the die-to-die VTH variation. The optimal
body-biasing minimizes VDDmin(SYS) and the forward bodybiasing decreases VDDmin(RAND). In the measurement of VDDmin of
100k-stage 2NAND chain, VDDmin is successfully reduced by
45mV from 193mV to 148mV by the forward body biasing. The
temperature dependence of VDDmin is measured for the first time.
The worst (=highest) VDDmin condition of logic circuits withsmall gate counts is high temperature, while the worst VDDmin
condition of logic circuits with large gate counts is low
temperature. Therefore, the temperature for the worst corner
analysis for VDDmin should be changed depending on the numberof gate counts of logic circuits.

REFERENCES[1]

N. Lotz and Y. Manoli, “A 62mV 0.13μm CMOS standard-cell-based
design technique using schmitt-trigger logic,” International Solid-State
Circuits Conference (ISSCC), pp. 340-341, Feb. 2011.

[2]

M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw, and D. Sylvester, “A
0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with superpipelining,” International Solid-State Circuits Conference (ISSCC), pp.
342-343, Feb. 2011.

[3]

T. Niiyama, P. Zhe, K. Ishida, M. Murakata, M. Takamiya, and T.
Sakurai, “Increasing minimum operating voltage (VDDmin) with numberof CMOS logic gates and experimental verification with up to 1Megastage ring oscillators,” International Symposium on Low PowerElectronics and Design (ISLPED), pp. 117-122, Aug. 2008.

[4]

H. Fuketa, S. Iida, T. Yasufuku, M. Takamiya, M. Nomura, H.
Shinohara, and T. Sakurai, “A closed-form expression for estimating
minimum operating voltage (VDDmin) of CMOS logic gates,” ACM
Design Automation Conference, Session 53.1, June 2011.

[5]

M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of
MOS transistors,” IEEE J. Solid-State Circuits, vol.24, no.5, pp.14331440, May 1989.

[6]

M. Hwang, A. Raychowdhury, K. Kim, and K. Roy, “A 85mV 40 nW
process-tolerant subthreshold 8x8 FIR filter in 130 nm technology,”IEEE Symposium on VLSI Circuits, pp. 154-155, June 2007.

[7]

Y. Komatsu, K. Ishibashi, M. Yamamoto, T. Tsukada, K. Shimazaki, M.
Fukazawa, and M. Nagata, “Substrate-noise and random-fluctuations
reduction with self-adjusted forward body bias,” IEEE Custom
Integrated Circuits Conference (CICC), pp. 35-38, Sep. 2005.

[8]

T. Tsunomura, A. Nishida, and T. Hiramoto, “Investigation of thresholdvoltage variability at high temperature using Takeuchi plot”, Japanese
Journal of Applied Physics, Vol. 49, No. 5, 054101, May, 2010.

ACKNOWLEDGMENTS
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial
Technology Development Organization (NEDO).

26