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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

VDD-Hopping Accelerators for On-Chip Power
Supply Circuit to Achieve Nanosecond-Order
Transient TimeKohei Onizuka, Student Member, IEEE, Hiroshi Kawaguchi, Member, IEEE, Makoto Takamiya, Member, IEEE,and Takayasu Sakurai, Fellow, IEEE

Abstract—A DD -hopping accelerator for on-chip power supply
circuits is proposed and the effectiveness of the accelerator circuit is experimentally verified. The quick dropper with the linear
regulator enables nanosecond-order transient time in on-chip distributed power supply systems. The measured transition time isless than 5 ns with a load circuit equivalent to 25-k logic gates in
0.18- m CMOS. This is to be compared with the case without theaccelerator of the order of s and thus the acceleration by two orders of magnitude is achieved. Extensions of the basic approach arealso discussed including implementation of the quick dropper fora switching DC–DC converter, the control stability improvement,
automatic timing generation, and the parasitic element effects ofthe power lines.
Index Terms—DC–DC converter, linear regulator, mirror delay,parasitic elements, power supply, DD -hopping.

Fig. 1 Supply voltage trend.

I. INTRODUCTIONSYSTEM-ON-A-CHIP (SoC) and system-in-a-package(SiP) have become major integration technologies in recent
years. They are often used for integrating various types ofcircuit blocks like MPU, DRAM, SRAM, ROM, logic, andanalog circuits on a chip or in a package. The optimum and/or
for these types of circuit blocks
required supply voltages
trends of prediffer among themselves. Fig. 1 shows thecision analog/RF, performance analog/RF, high-performancelogic, and low-power logic with the design rule trends which
are extracted from the International Technology Roadmap for
Semiconductors (ITRS) 2005 [1]. Thus, integrating different
values in an SoC
types of circuit block needs various local
and an SiP. Supplying many different voltages from outside thepackage can be one solution, as shown in Fig. 2(a). However,this method gives rise to much overhead in area and brings
about the power line integrity issues including IR drop andnoise. The distributed on-chip power supply circuits as shownin Fig. 2(b) are useful for solving these problems.
On the other hand, for each circuit block, the highest performance may not be required all of the time. It has been known
Manuscript received February 17, 2006; revised July 28, 2006.
K. Onizuka and M. Takamiya are with the Institute of Industrial Science andCenter for Collaborative Research, University of Tokyo, Tokyo 153-8505, Japan(e-mail: kohei@iis.u-tokyo.ac.jp).
H. Kawaguchi is with the Department of Computer and Systems Engineering,
Kobe University, Kobe 657-8501, Japan.
T. Sakurai is with the Center for Collaborative Research, University of Tokyo,
Tokyo 153-8505, Japan.
Digital Object Identifier 10.1109/JSSC.2006.882882

Fig. 2. Concept of distributed power supply system.

when a required speed is slow decreases
that reducing
the power consumption of a block drastically. To implement-hopping has been introduced, where
this concept,
is changed among discrete levels adaptive to the required performance to reduce power consumption while maintaining the-hopping should be exereal-time feature [2], [3]. Since
cuted for each circuit block, the distributed power supply circuits should have the capability of changing the voltage in time.
An on-chip power supply converts the external
into the optimum internalof-hopping system,
the load circuit as shown in Fig. 3. In thetransition
the load circuit should not be used during thefrom one voltage level to another because the load circuit block
has not verified its operation between the voltage levels in thetest sequence. Therefore, high-speed transition among different

0018-9200/$20.00 © 2006 IEEE

ONIZUKA et al.:

-HOPPING ACCELERATORS FOR ON-CHIP POWER SUPPLY CIRCUIT TO ACHIEVE NANOSECOND-ORDER TRANSIENT TIME

Fig. 3. (a) Power supply and equivalent load diagram. (b) Desirable waveform (dotted line) and actual waveform (solid line) for V

levels is important not to steal much time for the voltage
hopping.
and
as is
The load circuit can be approximated as
represents all of the capacitance associatedshown in Fig. 3.
with the power supply node, including MOSFETs and interconrepresents the current sink capability of thenections, andload circuit. When an operation of the load circuit is stopped
transition, the circuit draws only leakage curduring theincreases up to more than kilo-ohm range. Thus,
rent and-hopping when the load cirin the transient period of thecuit stops operating, there is eventually no path to pull down theinternal voltage to the lower level and the transient becomes intolerably long. Fig. 3(b) shows an example of an ideal waveform
and the actual waveform. The long transition timeforsteals much time in the-hopping and hence reduces performance of the system. Added to this, if the transition time is long,it will be difficult to apply to very quick real-time systems suchas servomechanism control systems. In this paper, a technique to-hopping accelerator, isreduce the transition time, namely aproposed, and the effectiveness is verified through experiments.
In Section II, the basic concept of the accelerator is introduced,
followed by the implementation of the accelerator for a linear
regulator and a switching DC–DC converter in Sections III andIV, respectively. Sections V and VI are dedicated to discussions
and conclusions.
II. BASIC CONCEPT OF

Fig. 4. Basic concept of the V

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-hopping accelerator.

Fig. 5. Waveforms of quick raiser and quick dropper.

-HOPPING ACCELERATOR

Fig. 4 shows the basic concept of the-hopping accelerator. The PMOS/NMOS transistor labeled “quick raiser”/“quick
dropper,” which is added at the output of a distributed voltage-hopping process. The
regulator on a chip, accelerates thewith and without the quick
schematic waveforms ofraiser/dropper are shown in Fig. 5. The transition time depends
and the effective resistance of theon the RC time constant of. Since the quick dropper
quick raiser/dropper,
not aiming at
but aiming
charges/discharges
at much higher/lower voltage of, the charging/discharging time is highly accelerated. The acceleration will beandachieved without any extra power supply lines, since
are available as global power grids.
Basically, the acceleration is achieved by aiming at a goalthat is higher than the target value and stopping at the target
value. This “aim-high” is the basic concept for the acceleration. In order to quantitatively discuss the speed accelerationby the aim-high, let us introduce the following three parameters: a voltage overdrive factor , an achievement ratio , anda speed acceleration factor . Fig. 6 shows several fundamental
parameters for the case of a quick dropper. These parameters
are defined in a similar fashion for the case of a quick raiser.
indicates the voltage overdrive and is defined as(1)
The achievement ratio is the ratio of the full transition
voltage and the actual transition voltage when we say that thegoal is achieved. is needed because it takes forever to get to
the goal
when there is no overdrive

(2)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 8. (a) Basic circuit of quick dropper and (b) its waveforms.

Fig. 6. Definition of several values in the case of a quick dropper.

Fig. 9. Conventional linear regulator with quick dropper.

final voltage of
because there is delay
in switching
off the dropper. In order to take this delay into account,which sets the voltage at which the driver for the dropper starts
asthe turning-off process should be a little higher thanfollows:
Fig. 7. Speed improvement dependence on acceleration factor .

(4)shows the hopping-speed improvement with the aim-high,which is a function of the overdrive voltage and the achievement ratio as follows:(3)
Fig. 7 shows the speed acceleration factor for typical parameters. If the voltage is initially overdriven by 100% and thevoltage error of 5% is allowed, that is, the voltage overdrive
factor is 2.0 and the achievement ratio is 95%, then the speed
is accelerated by a factor of 3.65, which is a huge acceleration.
III.

-HOPPING ACCELERATOR FOR LINEAR REGULATOR

is supplied from external to the chip for the measurement, but self-aligned generation of the timing is also discussed
do not give muchlater in this paper. Lines to distributeoverhead in area because there is no need to draw current
through the line.
Fig. 9 shows the designed quick dropper with the conventional linear regulator in 0.18- m CMOS. The load circuit isdesigned to be equivalent to 25-k NAND gates. Fig. 10 shows theandsigschematic waveforms for the quick dropper.
nify the delay of the quick dropper driver to turn on and turnoff the dropper itself, respectively. To avoid the output voltage
ripple like a voltage overshoot and undershoot, a careful tuning
is required.
of

A. Circuit Topology

B. Simulation and Measurement Results-hopping accelerator,
To verify the effectiveness of thethe quick dropper for a linear regulator is designed and manufactured. Since the linear regulator has no path to pull down the
output voltage in principle, the load capacitance is discharged
only by the leakage current of the load circuit. Thus, the quick
dropper works more effectively for the linear regulator compared with a DC–DC switching regulator. Fig. 8 shows the basic
circuit and the waveforms of the quick dropper. Generally, thegate width of the quick dropper is large and buffers are neededto drive it and thus there is a delay. Therefore, the quick dropper
reaches themust be turned off slightly earlier before theFig. 11 shows the simulated waveforms of the linear regulator with and without a quick dropper using HSPICE. Here,the leakage power is assumed to be 1% of the dynamic loadandare equal to 2.0 and 1.5 V, recircuit power.
spectively. The transition time is defined the time from the start
to the time when thetrips 95% ofof the, that is, the achievement factor is 95%. As seenfrom Fig. 11, the transition time with the quick dropper is about
3 ns while that without the quick dropper is about 0.4 s. This
leads to a long wait before the load circuit can be operated. The
voltage ripple right after the transition is smaller than 2%, and,

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Fig. 12. Chip microphotograph of the fabricated linear regulator.

Fig. 10. Waveforms of a quick dropper controller.

Fig. 13. Measured waveform of V
gates.

for equivalent load of 25–k NAND

Fig. 11. Simulated waveforms of linear regulator with and without quick
dropper.

thus, it is possible to start the operation of the load circuit rightafter the transition. The simulated performance of line regulais smaller than 0.8% for
of
V
tion
and
of 1.2 V. The simulated performance of load reguis smaller than 5% for the maximum load curlationof 1.5 V. The performances of line
rent of 50 mA andand load regulations simply depend on the linear regulator circuit itself.
A chip microphotograph of the fabricated linear regulator
with the quick dropper is shown in Fig. 12. The quick droppermm, while the linear regulator area isarea ismm. The area overhead of the quick dropper canbe as small as 2% of the load circuit.
which coFig. 13 shows the measured waveform forincides well with the HSPICE simulation. It is seen that the trantois smaller than 5 ns, which ensition time fromables more than two orders of acceleration over the case without
the accelerator circuit.

Fig. 14. Buck converter with the VIV.

-hopping accelerator.

-HOPPING ACCELERATOR FORSWITCHING DC–DC CONVERTER-hopping accelerator for a
Implementation of theswitching DC–DC (buck) converter is presented in this section.
The conventional buck converter needs an inductor and acapacitor to filter out the switching ripples of the switchingfrequency. As technology advances, the switching frequency
is increased and the on-chip regulator is investigated because
the required value of and are reduced [4]–[7]. The energy
efficiency of a switching DC–DC converter is higher than thatof a linear regulator, and the buck converter is considered to
be a promising candidate for future on-chip distributed voltage
regulators.
A buck converter with a quick raiser and a quick dropper isshown in Fig. 14. A design is carried out assuming 0.18- m

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Fig. 15. Waveforms of (a) V
21 nH, C = 3 nF.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

and (b) inductor current I when L=

Fig. 17. Waveforms of (a) Vand (b) I when Fig. 18. Waveforms of (a) V

2:2 ns.

Fig. 16. Control timings of (a) V

to V

and (b) Vto V.

= 0 ns and  = 0 ns.

and (b) I when = 2 ns and =

and are set to 2 and 2.2 ns, respectively, the transition time
-totransition and 4 ns foris reduced to 6 ns for the-totransition, as is shown in Fig. 18. The output
thevoltage is stabilized by limiting the long-term fluctuation of theaverage inductor current. Thus, a careful tuning of the timing
offsets is considered to be effective in further reducing the transition time.
V. DISCUSSIONSCMOS, and the size of the on-chip filter of 2 2 mm. The circuitnH andnF andparameters are determined as
the switching frequency is set as 150 MHz by using optimization
theories [8]–[10]. Fig. 15 shows the simulated waveforms ofand the inductor current
without a
output voltage-hopping accelerator when
V and
V. Spurious voltage ringing occurs after voltage transitions
due to the LC resonance. The transition times to 5% of the final–
transition and 37 ns forvoltages are 64 ns for the–transition.
theFig. 16 shows the control timing of the-hopping accelerator for a buck converter. “Output voltage of switching transistors” indicates the output node voltage of switching transistorsof a buck converter. The duty ratio of the PWM signal is assumed to change at the falling edge of the PWM signal (dottedline), that is, the chopping clock. The gate voltage of the quick
andbefore the falling
dropper/raiser starts to change atedge of the chopping clock.
Fig. 17 shows the simulated waveforms for the case with the-hopping accelerator. The timing offset
andare setboth to 0 ns in this case. Transition time is about 25 ns for-toand-totransitions, which
both theis shorter than the case without the accelerator, but the spurious
ringing after the transitions is not negligible. If the timing offsets

Improved control methodologies in two ways and parasitic
element effects of the power lines are discussed in this section.
A. Stability Enhancement
The quick dropper shown in Fig. 9 requires a proper settingof. Whenis set to be lower than the expected value(higher for a quick raiser), the output voltage may overshoot,and oscillation may occur because there are two feedback loops,
one for the linear regulator and the other for the quick dropperand both loops operate at the same time and independently. The
cycle time of the oscillation depends on the total delay of thetwo feedback loops. On the other hand, the duration of the oscillation is the same as the active period of the quick dropper,
which is determined by the delay circuit in Fig. 9. Fig. 19 shows
the measured and simulated waveforms for the circuit shown in
is much lower than the proper value, where
Fig. 9 when
spurious oscillation is observed. By limiting the activation of
the quick dropper only once per transition, the oscillation canbe eliminated. Fig. 20 shows the improved version of the quick
dropper, where the activation is limited to once per transition.
The pulse generator1 activates the JK latch and the pulse generator2 inactivates at the end of the quick dropping operation.
Fig. 21 shows the simulated waveform using HSPICE when

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Fig. 19. (a) Measured and (b) simulated waveform of ringing by mis-setting ofV .

Fig. 22. Basic concept of the self-aligned generation of timings.

Fig. 20. (a) Modified controller circuit of quick dropper and (b) its waveforms.

Fig. 23. Basic circuit of a V -hopping accelerator with a self-aligned timing
generator based on a mirror-delay circuit.

Fig. 21. Simulated waveform of V
condition of Fig. 19.

for the circuit of Fig. 20 under theis much lower than the proper value. This one-time control approach is effective not only to the linear regulators but
also to other types of DC–DC converters.
B. Self-Aligned Timing Generation
sets the basis of critical timings for the-hopping
acceleration and is assumed to be provided from outside of adoes not carry current
package. This is doable since theline isand the area overhead is small even although thelines. The adjustshielded from adjacent signals by using
ment of, however, is critical to the accelerator operation
value is depenas is explained in Section III. The proper
dent on the load circuit as is expressed in (4). Again, it is doableby adjusting from the outside but, if the timing signals can begenerated on a chip indifferent from the load circuit, the applicability of the circuit in SoC/SiP environments will increase.
To address this issue, automatic generation of the timings in aself-aligned manner is considered here.
Fig. 22 shows the concept of the proposed approach. It is
possible to approximate the exponential voltage waveform bya linear transition. Therefore, once the delay required from theisstart of the transition to the half point of the trip toknown, the remaining transition time tois predictable.
The half voltage can be generated by a simple on-chip circuit.
is to be distributed but it is the same for all the circuit
is different for each circuit blocks.
blocks while
Fig. 23 shows the circuit diagram of a quick dropper with theproposed control. The timing sequence shown in Fig. 22 canbe implemented by a mirror-delay circuit which consists of two
capacitors C1 and C2. Fig. 24 shows the simulated waveforms ofthe circuit by HSPICE assuming 0.18- m CMOS with
V andV.
The mirror-delay circuit works as follows. At the start, both
. Then, charging of C1 is started
C1 and C2 are discharged towhen the time span ofpasses. The charging processreaches the middle voltage of
andends when. Then, charging of C2 begins. When the terminal voltageof C1 and C2 becomes equal, the turn-off process for the dropper

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Fig. 24. Simulated waveforms of self-aligned generation of timings.
Fig. 26. Diagrams of bonding wires and power grids for a distributed power
supply.

. Consequently, the change in current at the global grid
local
is directly connected tois less than the case where the local
the global grid without the voltage down regulator even though
the power fluctuation is the same amount. Thus, the trigger forthe noise on the global power grid is considered to be small.
On the other hand, the local power grid that is connected to the
output of the distributed regulator also has RLC components,
but they are small and will not generate the notorious long-term
noise.
Fig. 25. Simulated waveforms for various values of load capacitance.

VI. CONCLUSION
transistor is initiated. In this process, the delay adjustment foris required to compensate for the delay of the drivercircuit of the dropper transistor. This can be achieved with thehelp of a replica circuit as shown in the figure.
when theFig. 25 shows the simulated waveforms ofvaries from 15 to 30 pF. It is seen fromload capacitanceis achieved for a wide
the figure that the final voltage of
without changing the control circuit itself. Thus therange ofself-aligned feature is verified. It is possible to widen the range
furthermore by using variable capacitors for C1 and C2of
by using multiple capacitors in parallel and a digital control.
C. Parasitic Element Effects
The distributed voltage regulator with a-hopping accelerator is supposed to be on a global power grid as shownin Fig. 26. There are parasitic RLC components on the global
power grid on a chip, and, with package and board RLC components [11], [12], there may be a long-term oscillation on the
global power over several tens of clock cycles [13], which isconsidered to be the most severe issue related to power integrity.
The long-term noise generally occurs when a circuit block goesto sleep, wakes up, and changes the power status.
Although the global power grid has noise on it, the distributed
voltage regulator will reduce the noise on the output of the regulator. Thus, although a block changes its supply voltage in ashort time and a long-term noise is generated, the voltage flucis minimal. Moreover, it is supposed
tuation on a blockthat the global power grid distributes the higher voltage than theA-hopping accelerator for an on-chip distributed power
supply is proposed and a 5-ns transition time is experimentally
verified for a linear regulator with the load capacitance equivalent to 25-k NAND gates. This enables the performance imscaling systems by reducing steal
provement in dynamic
time caused by the transition between different voltage levels.
The transition time of 6 ns is also shown by simulation for thecase of a switching DC–DC converter. To further improve theeffectiveness of the accelerator, two novel controller circuits areproposed.
ACKNOWLEDGMENT
The authors would like to thank K. Mashiko, A. Hashiguchi,
Y. Ueda, M. Nomura, and H. Yamamoto, Semiconductor
Technology Academic Research Center (STARC), and
R. Krishnamurthy and S. Hsu, Intel Corporation, for valuable discussions. The chip fabrication was supported by the
VLSI Design and Education Center (VDEC), University ofTokyo, in collaboration with Hitachi Ltd. and the Dai Nippon
Printing Corporation.
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2005 [Online]. Available: http://www.itrs.net/Common/2005ITRS/
Home2005.htm[2] H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. D. Antono, D.
Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, and T. Sakurai, “A
0.5–V, 400-MHz, VDD-hopping processor with zero-VTH FD-SOI
technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers,
Feb. 2003, pp. 106–107.

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[3] M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A.
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[4] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Analysis
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[5] G. Schrom, P. Hazucha, J.-H. Hahn, V. Kursun, D. Gardner, S.
Narendra, T. Karnik, and V. De, “Feasibility of monolithic and
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[6] G. Schrom, P. Hazucha, J. Hahn, D. S. Gardner, B. A. Bloechel, G.
Dermer, S. G. Narendra, T. Karnik, and V. De, “A 480-MHz, multiphase interleaved buck DC-DC converter with hysteretic control,” inProc. 35th Annu. IEEE Power Electronics Specialists Conf., Jun. 2004,
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[7] P. Hazucha, G. Schrom, J.-H. Hahn, B. Bloechel, P. Hack, G. Dermer,
S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borker, “A 233
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[9] ——, “Efficiency analysis of a high frequency buck converter for
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[10] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Lowvoltage-swing monolithic DC-DC conversion,” IEEE Trans. Circuits
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[12] “Intel Pentium 4 Processor/Intel 850 Chipset Platform Design Guide,”Intel Corp., Feb. 2002 [Online]. Available: http://www.intel.com/design/Pentium4/documentation.htm[13] W. El-Essawy and D. H. Albonesi, “Mitigating inductive noise in SMT
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Kohei Onizuka (S’03) received the B.S. degree in information and communication engineering and the M.S. degree in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2003 and 2005, respectively. He is currently
working toward the Ph.D. degree at the University of Tokyo.
His research interests include high-speed V -hopping, on-chip
DC–DC converters, and chip-to-chip wireless power transmission forsystem-in-a-package applications.

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Hiroshi Kawaguchi (M’98) received the B.E. and M.E. degrees in electronicengineering from Chiba University, Chiba, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in engineering from the University of Tokyo, Tokyo,
Japan, in 2006.
He joined Konami Corporation, Kobe, Japan, in 1993, where he developed
arcade entertainment systems. He moved to the Institute of Industrial Science,
University of Tokyo, as a Technical Associate in 1996 and was appointed a Research Associate in 2003. Since 2005, he has been a Research Associate with
the Department of Computer and Systems Engineering, Kobe University, Kobe,
Japan. He is also a Collaborative Researcher with the Institute of Industrial Science, University of Tokyo. His current research interests include low-power
VLSI design, hardware design for wireless sensor networks, and recognition
processors.
Dr. Kawaguchi is a member of the Association for Computing Machinery. He
was a recipient of the IEEE ISSCC 2004 Takuo Sugano Award for Outstanding
Far-East Paper. He has served as a program committee member for IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips). He is a Guest
Associate Editor of the IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences.

Makoto Takamiya (S’98-M’00) received the B.S., M.S., and Ph.D. degrees inelectronic engineering from the University of Tokyo, Tokyo, Japan, in 1995,
1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where he was engaged in the circuit design of high-speed digital LSIs and developed the field of on-chip measurement macros to solve the power integrity issues. In 2005, he joined the University of Tokyo, where he is currently an Associate Professor with the VLSI
Design and Education Center. His research interests include power and signal integrity issues, low-power RF integrated circuits, and large-area electronics withorganic transistors.

Takayasu Sakurai (S’77–M’78–SM’01–F’03) received the Ph.D. degree inelectrical engineering from the University of Tokyo, Tokyo, Japan, in 1981.
In 1981, he joined Toshiba Corporation, where he designed CMOS DRAM,
SRAM, RISC processors, DSPs, and system-on-chip Solutions. He has worked
extensively on interconnect delay and capacitance modeling known as Sakurai
model and alpha power-law MOS model. From 1988 to 1990, he was a Visiting
Researcher with the University of California, Berkeley, where he conducted research in the field of VLSI CAD. Since 1996, he has been a Professor with the
University of Tokyo, where he has been involved with low-power high-speed
VLSI, memory design, interconnects, ubiquitous electronics, organic ICs, andlarge-area electronics. He has published more than 350 technical publications,
including 70 invited publications and several books, and has filed more than 100
patents.
Prof. Sakurai is a STARC Fellow, an elected AdCom member for the IEEE
Solid-State Circuits Society, and an IEEE Circuits and Systems Distinguished
Lecturer. He served as a conference chair for the Symp. on VLSI Circuits, and
ICICDT, a vice chair for ASPDAC, a TPC chair for the first A-SSCC, and VLSI
Symposium, and a program committee member for ISSCC, CICC, DAC, ESSCIRC, ICCAD, FPGA workshop, ISLPED, TAU, and other international conferences. He is a plenary speaker for the 2003 ISSCC. He was a recipient of the2005 IEEE ICICDT Award, the 2005 IEEE ISSCC Takuo Sugano Sward, andthe 2005 P&I Patent of the Year Award.