2.1 Times Increase of Drain Efficiency by Dual SupplyVoltage Scheme in 315MHz Class-F Power Amplifier
at Output Power of -20dBm
Shunta Iguchi1, Akira Saito2, Kazunori Watanabe2, Takayasu Sakurai1, and Makoto Takamiya1
12

University of Tokyo
Tokyo, JapanI.

Drain efficiency (DE) [%]Abstract—Dual power supply voltage (VDD) scheme is proposed
to increase the efficiency of a power amplifier (PA) with small
output power (POUT) for short-range wireless sensor networks(e.g. body area networks). At POUT of -20dBm, compared withthe conventional single VDD PA, the drain efficiency (DE) andthe global efficiency (GE) of the proposed dual VDD PA increaseby 2.1 times and 1.5 times, respectively. A class-F PA fabricatedin 40-nm CMOS with the proposed dual VDD (0.2V and 0.56V)
achieves the highest DE of 42% at POUT of -20dBm in thepublished PA’s. The PA is applied to a 315MHz OOK
transmitter (TX) and the TX achieves the highest GE of 28% at
POUT of -20dBm and the lowest energy of 36pJ/bit (=36μW@1Mbps) in the published TX’s.

80
Target of this workIn short-range wireless sensor networks (e.g. body areanetworks), an ultra low power transmitter (TX) with small
output power (POUT) is required. In this paper, the target POUT
is -20dBm and the target communication distance is 1m,assuming -25dB propagation loss at the 1-m distance, -5dB x
2 loss at TX/RX antennas, and -55dBm receiver sensitivity [1].
The target TX power consumption (PTOTAL) is less than 50μW
at 1Mbps and 315-MHz carrier frequency. In order to reduce
PTOTAL of TX less than 50μW at POUT of -20dBm (= 10μW),
the global efficiency (GE) (= POUT/PTOTAL) of a TX should belarger than 20% (= 10μW/50μW). Increasing the efficiency atsmall POUT, however, is a design challenge.
Fig. 1 shows the dependence of drain efficiency (DE) on
POUT in previously published power amplifiers (PA’s) [1-7].
As POUT decreases, DE also decreases, because various losses
become non-negligible. In PA’s [4,5] for the conventional
wireless communications (e.g. cell-phone and WLAN) where
the communication distance is 100m~1km, POUT is +20dBm ~+30dBm and DE is higher than 60%. In contrast, in PA’s [13,7] for the short-range wireless sensor networks (e.g. bodyarea networks) where the communication distance is 1m~10m,
POUT is -20dBm ~ -10dBm and DE is less than 30%. For
example, in our previous work [1], DE is 20% and GE is 16%,
which does not meet our design target (GE > 20%). Therefore,
the purpose of this paper is to achieve DE higher than 40%
and GE higher than 20% at POUT of -20dBm. A newly
proposed dual power supply voltage (VDD) scheme increases
DE and GE by 2.1 times and 1.5 times, respectively, comparedwith the conventional single VDD scheme [1].

[5]

[4]

60
[6]

Typical PA

40
[3]

200

INTRODUCTION

978-1-4673-2213-3/12/$31.00 ©2012 IEEE

Semiconductor Technology Academic Research Center
Yokohama, Japan[1][2] [7]Short(1m-10m)-20-10Communication
distance
010Long(100m-1km)
2030

Output power (POUT) [dBm]
Fig. 1. Dependence of drain efficiency on output power in previously
published PA’s and target of this work.

II.

DESIGN OF DUAL VDD CLASS-F POWER AMPLIFIER

In this section, the dual VDD scheme is introduced toincrease DE of PA at POUT of -20dBm. In this paper, a class-F
PA instead of a class-D or class-E PA is used, because theclass-F PA achieved the highest efficiency at our design target.
Fig. 2 (a) shows a schematic of the class-F PA. VDD1 is theamplitude of the input (In) and VDD2 is the power supply
voltage of PA. LDC is a choke coil, CDC is an AC-coupling
capacitor, L1 and C1 resonate at the fundamental frequency (=315MHz), and L3 and C3 resonate at the third harmonic (= 3 x315MHz). Fig. 2 (b) shows an equivalent circuit of Fig. 2 (a)[8]. A transformer is formed by the L and C networks in Fig. 2(a) equivalently. The transformer ratio is defined as n. POUT ofthe class-F PA in Fig. 2 (b) is given by [9]2⎛4⎞⎜ × VDD 2 ⎟2π⎠ ∝ ⎛ VDD 2 ⎞ .
POUT = ⎝ 2⎜⎟
2n × 50(Ω) ⎝ n ⎠(1)

Fig. 3 shows a dependence of POUT on VDD2 calculatedwith Eq. (1), when n is varied from 0.01 to 100. DE is thehighest at n = 1, because the loss of the transformer in Fig. 2(b) is proportional to n (n > 1) or 1/n (n < 1) [9]. Therefore, a
PA design with n = 1 is the best design. The PA design with345

POUT of -20dBm in this work is quite different from the typicalPA design with POUT of +20dBm ~ +30dBm. In the latter
design, n is less than 1, while n is larger than 1 in the former
design. In order to increase DE in the typical PA, VDD2 should
be increased and n should be increased to 1. In contrast, inorder to increase DE in the PA with POUT of -20dBm in thiswork, VDD2 should be decreased and n should be decreased to1. In the conventional PA’s with small POUT [2, 3], however,VDD2 is not decreased (= 1V) and large n is used, thereby DEis reduced. In this work, VDD2 is decreased to 0.2V and n isdecreased to 4.2, which will be shown in Fig. 5 (b). If VDD1 isalso decreased to 0.2V, the on-current of the transistor in Fig.
2 (a) is greatly reduced, because the transistor operates in thesub-threshold region. In order to solve the problem, the dual
VDD scheme is proposed in this paper.
VDD2L3LDCOutCDC

InC3VDD1L1C150Ω

0V(a)

VDD2
ZIN:50n2[Ω]Outn:1
In50Ω

VDD10V(b)Fig. 2. (a) Schematic of a class-F PA. (b) Equivalent circuit of (a).

Output power (POUT) [dBm]

DE: Drain efficiency

n=0.013020DEIn this section, the dual VDD scheme is optimized tomaximize GE of TX at POUT of -20dBm. Fig. 4 shows aschematic of TX including the dual VDD class-F PA. The
carrier frequency is 315MHz for a radio communication
standard of ARIB STD-T93 (315MHz band) in Japan and thedata rate is 1Mbps. As shown in Fig. 4, PTOTAL is the sum of
the buffer, the mixer, and the PA powers. In the PA design
with POUT of -20dBm, the buffer power is not negligible andthe PA-only (=DE only) design optimization is inadequate.
Therefore, GE is maximized at POUT of -20dBm by optimizing
n. In the design optimization, VDD1, VDD2, CDC, and LDC arevaried according to n, and L1, C1, L3, C3, and transistor size
are fixed.
Figs. 5 (a), (b), and (c) show the SPICE simulated ndependence in TX with POUT of -20dBm. Fig. 5 (a) shows thesimulated dependence of PTOTAL, the buffer power, and the PApower on n. Fig. 5 (b) shows the simulated dependence ofVDD1 and VDD2 on n. Fig. 5 (c) shows the simulated
dependence of CDC and LDC on n. CDC and LDC are decided byn and the impedance matching. The power consumption in Fig.
5 (a) is simulated at VDD1 and VDD2 shown in Fig. 5 (b) and
CDC and LDC shown in Fig. 5 (c). As shown in Fig. 5 (b), theconventional TX with single VDD is designed at n = 9.6 and
VDD1 = VDD2 = 0.47V. In contrast, as shown in Fig. 5 (a),PTOTAL is minimum at n = 4.2, thereby GE is maximum at n =4.2. The corresponding VDD1 = 0.56V and VDD2 = 0.2V. Table
I shows the optimum parameters in the conventional single
VDD design and the dual VDD design.
The reason for the optimum dual VDD is discussed. When n
is reduced from 10 to 2, VDD2 is reduced (Fig. 5 (b)) and thePA power is reduced (Fig. 5 (a)). In contrast, VDD1 is increased(Fig. 5 (b)) and the buffer power is increased (Fig. 5 (a)).
When n is reduced below 3, VDD1 drastically increases (Fig. 5(b)), because the transistor operation changes from thesaturation region to the linear region, thereby thecorresponding buffer power drastically increases (Fig. 5 (a)).
Therefore, PTOTAL is minimum at n = 4.2 (Fig. 5 (a)), thereby
GE is maximum at n = 4.2.
On-chip
VDD1HighHigh0DE
This work

0.5

1.0

L3OutCarrier(315MHz)
CDCC3LowVDD2 [V]Off-chip
VDD2LDCConv.
design-200.0

DESIGN OF TRANSMITTER WITH DUAL VDD POWERAMPLIFIER

Typical PA

Low

10-10III.

C1L1Data(1Mbps)
1.5

2.0

BufferPower amplifier (PA)GlobalFig. 4. Schematic of a dual VDD TX with a class-F PA.

Fig. 3. Dependence of output power on VDD2 calculated with Eq. (1).
Transformer ratio (n) in Fig. 2 (b) is varied from 0.01 to 100.

34650ΩIV.

To demonstrate the advantage of the proposed dual VDD
scheme, a test chip is fabricated in 1.1V, 40-nm CMOS
process. Fig. 6 shows the die microphotograph and the layout.
The die size is 0.5mm x 0.6mm and the core area of TX is
56μm x 22μm. The measured parameters of the conventional
and the proposed PAs are given in Table I, while the sametwo resonators are used as follows: L1 = 22nH, C1, = 11pF, L3,= 2.7nH, and C3 = 12pF.
Fig. 7 shows the measured GE and POUT of TX in theproposed dual VDD scheme, when VDD1 and VDD2 are varied.
At the target POUT of -20dBm, the maximum GE is 28% at
VDD1 = 0.56V and VDD2 = 0.2V, which consists with thesimulated results in Fig. 5. As POUT increases from -20dBm to-10dBm, the optimum VDD1 and VDD2 also increase. WhenVDD1 is below 0.52V, the buffer fails to work at the 315-MHz
carrier frequency.
Fig. 8 shows the measured output spectrum of the TX. The314MHz carrier is modulated by 1Mbps OOK. The measured
POUT of -20dBm meets the radio communication standard of
ARIB STD-T93 (315MHz band) which specifies the operating
frequency of 312-315.25MHz in Japan.

Conventional single VDD

60

Optimum dual VDD
Global40

PA200Buffer

POUT = -20dBm
124 5 6 7 8 9 10

3Transformer ratio (n)
(a)

2.0
1.5

Nominal voltage of transistors

Conventional single VDD
VDD1Optimum dual VDD

0.5

0.6 mmVDD20.01234 5 6 7 8 910

Transformer ratio (n)(b)
Conventional single VDD

10Fig. 6. Die microphotograph and layout of proposed dual VDD PA in 40-nm
CMOS.

100Optimum dual VDD

880
LDC

660

440220
POUT = -20dBm
234 5 6 7 8 910

Buffer fails to work

LDC [nH]

CDC

CDC [pF]

120

0.9

0.60(c)Fig. 5. SPICE simulated transformer ratio (n) dependence in TX with POUT of 20dBm. (a) Power consumption vs. n. (b) VDD1 and VDD2 vs. n. (c) CDC and
LDC vs. n.

0.47

0.2

CDC [pF]

13

LDC [nH]

100

6020%
10%
0%

POUT =-10dBm

0.40.3

POUT =-15dBm
POUT =-20dBm

0.1

Proposeddual VDD0.5630%0.50.2

TABLE I PARAMETERS IN CONVENTIONAL SINGLE VDD DESIGN ANDPROPOSED DUAL VDD DESIGN.

VDD2 [V]Max efficiency(= Optimum dual VDD)

0.7

Transformer ratio (n)Conventional
single VDD
VDD1 [V]0.47

Global efficiency
40%0.8

VDD2 [V]120
156 μm

0.5 mmVoltage [V]POUT = -20dBm

1.0

MEASUREMENT RESULTS

22 μm

Power consumption [μW]

80

0.0
0.5

0.6

0.7

VDD1 [V]0.8

0.9

Fig. 7. Measured contours of global efficiency (GE) and POUT, when VDD1 andVDD2 are varied. Gray levels represent the values of GE. The lines are thecontour of POUT. At target POUT of -20dBm, maximum GE is 28% at VDD1 =0.56V and VDD2 = 0.2V.

347

TABLE II COMPARISON WITH PREVIOUS PAPERS.
ARIB STD-T93 (312-315.25MHz)
CMOS technology

Unit
nm

Supply voltage

VFrequency
Data rate

MHzMbpsPA class-Output power (POUT ) dBm
Drain efficiency%Power consumptionμW
of TX (PTOTAL)
Global efficiency%(POUT /PT OTAL)
EnergypJ/bit
TX includes

Fig. 8. Measured output spectrum of the TX. The 314MHz carrier ismodulated by 1Mbps OOK.

Fig. 9 shows the measured dependence of DE and GE onPOUT. The conventional single VDD scheme and the proposed
dual VDD scheme are compared. In the single VDD PA, VDD1and VDD2 are varied with same value. In the dual VDD PA,
VDD1 and VDD2 are varied according to the optimum VDD1 andVDD2 in Fig. 7, respectively. At the target POUT of -20dBm,compared with the conventional single VDD PA, DE and GE ofthe proposed dual VDD PA increases by 2.1 times and 1.5times, respectively.
The design issue of the proposed dual VDD scheme is aDC-DC converter required for the additional VDD. If the power
conversion efficiency of the DC-DC converter is less than66%, GE of the proposed dual VDD PA with the DC-DC
converter has no advantage over the conventional single VDD
PA. For example, however, a 0.45-V input buck converterwith more than 90% efficiency from 2μW to 50μW [10] isreported. The proposed dual VDD PA is still available withsuch converters.
In Fig. 9 and Table II, this work is compared with thepreviously published TX’s with small POUT [1-3]. The
proposed dual VDD scheme achieves the highest DE of 42%
and the highest GE of 28%, thereby achieving the lowest
energy of 36pJ/bit (= 36μW@1Mbps) in the published TX’s.

-[2]
130

[3]
130

1

1300-450
400
0.10.2
EdgeEdgecombiner combiner-16-17
1630
400

90

[1]
40

315
1This work40
VDD1:0.56
VDD2:0.2
315
1Class F

Class F

-2120-20
4252

360.5

6.3

221628

4000

450

52

36Osc.+PLL+ Osc.+PLL+ Mixer+
Mixer+Mixer+PA Mixer+PA Buffer+PA Buffer+PA

V. CONCLUSIONS
The dual VDD scheme is proposed to increase theefficiency of PA with small POUT. At POUT of -20dBm,compared with the conventional single VDD PA, DE and GE of
the proposed dual VDD PA increases by 2.1 times and 1.5times, respectively. Compared with the previously publishedpapers, the proposed dual VDD PA achieves the highest DE of
42% and the highest GE of 28% at POUT of -20dBm, thereby
achieving the lowest energy of 36pJ/bit (= 36μW@1Mbps) inthe published TX’s.
ACKNOWLEDGMENTThis work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy andIndustrial Technology Development Organization (NEDO).
REFERENCES

A. Saito, K. Honda, Y. Zheng, S. Iguchi, K. Watanabe, T. Sakurai, andM. Takamiya, “An all 0.5V, 1Mbps, 315MHz OOK transceiver with38-μW carrier-frequency-free intermittent sampling receiver and 52μW Class-F transmitter in 40-nm CMOS, ” IEEE Symposium on VLSICircuits, pp. 38-39 June 2012.
[2] S. Rai, J. Holleman, J. Pandey, F. Zhang, and B. Otis, “A 500μW
neural tag with 2μVrms AFE and frequency-multiplying MICS/ISM
FSK transmitter,” IEEE International Solid-State Circuits Conference,
pp. 212-213, Feb. 2009.
[3] J. Pandey and B. Otis, “A sub-100μW MICS/ISM band transmitter
Drain efficiency (DE)based on injection-locking and frequency multiplication,” IEEE J.
Design target
Solid-State Circuits, vol. 46, no. 5, pp. 1049-1058, May 2011.
Global efficiency (GE)[4] J. Lindstrand, C. Bryant, M. Tormanen, and H. Sjoland, “A 1.6-2.6GHz5029dBm injection-locked power amplifier with 64% peak PAE in 65nm
Proposed dual VDD
CMOS,” European Solid-State Circuits Conference, pp. 299-302, Sept.
2011.
40[5] J. Fritzin, T. Sundstrom, T. Johansson, and A. Alvandpour, “Reliability
study of a low-voltage class-E power amplifier in 130nm CMOS,”
x2.1
IEEE International Symposium on Circuits and Systems, pp. 1907[3]DE301910, June 2010.
[6] K. Natarajan, J. S. Walling, and D. J. Allstot, “A Class-C powerx1.5
amplifier/antenna interface for wireless sensor applications,” IEEE
[3]GERadio Frequency Integrated Circuits Symp., pp. 1-4, June 2011.
20[7] G. Papotto, F. Carrara, A. Finocchiaro, and G. Palmisano, “A 90nm
[2]DECMOS 5Mb/s crystal-less RF transceiver for RF-powered WSN[1]GE Conv.
nodes,” IEEE International Solid-State Circuits Conference, pp. 452single VDD
10454, Feb. 2012.
[2]GE[8] B. Razavi, RF Microelectronics. Prentice-Hall, 1998.
[9] P. Reynaert and M. Steyaert, RF Power Amplifiers for Moblile
0Communications. Springer, 2006.
-25-20-15-10 [10] X. Zhang, P. Chen, Y. Ryu, K. Ishida, Y. Okuma, K. Watanabe, T.
Output power (POUT) [dBm]
Sakurai, and M. Takamiya, “A 0.45-V input on-chip gate boosted(OGB) buck converter in 40-nm CMOS with more than 90% efficiency
Fig. 9. Measured dependence of drain efficiency and global efficiency on
in load range from 2μW to 50μW, ” IEEE Symposium on VLSI
output power. Conventional single VDD PA and proposed dual VDD PA arecompared. Previous papers are also shown.
Circuits, 194-195, June 2012.

Efficiency [%][1]348