Jpn. J. Appl. Phys. Vol. 40 (2001) pp. 2854–2858
Part 1, No. 4B, April 2001c
2001
The Japan Society of Applied Physics

Optimum Device Parameters and Scalability of Variable Threshold Voltage
Complementary MOS (VTCMOS)
Toshiro H IRAMOTO1,2, ∗ , Makoto TAKAMIYA1 , Hiroshi KOURA1 , Takashi I NUKAI1 , Hiroyuki G OMYO1 ,Hiroshi K AWAGUCHI1 and Takayasu S AKURAI1,3
1 Institute of Industrial Science, the University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
2 VLSI Design and Education Center, the University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan
3 Center for Collaborative Research, the University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan(Received September 19, 2000; accepted for publication December 13, 2000)

The optimum device parameters of variable threshold voltage complementary metal oxide semiconductor (VTCMOS) havebeen investigated by means of device simulation and its scalability has been discussed. The optimum body effect factor depends
on the relationship between the substrate bias and the supply voltage. It is shown that the VTCMOS scheme aiming at extremely
low stand-by power will fail as the device size and the supply voltage are scaled. The advantage of VTCMOS will be its highspeed, and the VTCMOS will be essential in high-speed circuits operating at a low supply voltage in combination with anotherlow stand-by power scheme such as the insertion of leak cut-off switches.
KEYWORDS: variable threshold voltage complementary metal oxide semiconductor (VTCMOS), body effect factor, substratebias, lowpower, high-speed, scalability, metal oxide semiconductor fieldeffect transistor (MOSFET)

1. Introduction
Strong demands for high-speed and low-power very large
scale integrations (VLSIs) are rapidly growing for portableproduct applications. It is well known that there is a severe
trade-off between high-speed and low-power in metal-oxidesemiconductor field-effect transistors (MOSFETs). In orderto suppress the active power, the supply voltage (Vdd ) should
be suppressed. The threshold voltage (Vth ) should also be reduced to maintain the high speed. Then, the stand-by power
will increase exponentially due to the increased subthresholdcurrent. One of the solutions to this problem is the variable
threshold voltage complementary metal oxide semiconductor(VTCMOS) scheme.1–3)
In the VTCMOS scheme, Vth of MOSFETs is controlled bysubstrate bias (Vbs ) using the body effect. Vth is set to a highvalue in the stand-by mode and is set to a low value in the active mode to attain high speed and low stand-by power at thesame time. The characteristics of VTCMOS are strongly related to the Vth shift (Vth ), which depends on the body effectfactor γ and the substrate bias change Vbs . Therefore, γ andVbs are the most important device parameters in VTCMOS.
However, the optimum device design for VTCMOS has notbeen generally recognized and the scalability of VTCMOS is
an issue of great concern for future applications.
In this study, the optimum device design for VTCMOS
is systematically investigated by device simulation and thescalability of VTCMOS is discussed. It is suggested that,while VTCMOS aiming at ultra-low stand-by current does
not maintain its advantage as the device and the supply voltage are scaled, VTCMOS will be an essential device/circuit
scheme aiming at high-speed applications.
2. Optimum Device Parameters
2.1 Definition of body effect factor
In this study, the body effect factor γ is defined by4, 5)|Vth |,
(1)γ ≡|Vbs |

instead of the usual definition in device textbooks which isapplicable only to the MOSFET with uniformly doped channel profile. The definition of eq. (1) can be applied to all
MOS structures with any channel impurity profile, including
retrograde MOSFET, delta-doped MOSFET, counter-doped
MOSFET, and silicon-on-insulator (SOI) MOSFET. Then,the threshold voltage shift Vth is given by
Vth = γ |Vbs |,(2)

and is directly related to the body effect factor and substratebias change. Therefore, a larger body effect factor results
in a larger threshold voltage shift. On the other hand, thesubthreshold factor S is also related to γ , and a MOSFET
with a larger body effect factor has a degraded subthresholdswing.4, 5) Therefore, these two effects would determine theoptimum condition of γ once Vbs is determined.
2.2 Two modes in VTCMOS
The main target of VTCMOS has been considered as the
reduction of the stand-by off-current (Ioff ) while maintaining
the circuit speed. Figure 1(a) illustrates the characteristics
of VTCMOS aiming at a low stand-by current. While maintaining a high drive current by low threshold voltage in theactive mode, the substrate bias is changed in the negative direction to raise the threshold voltage resulting in the decreasein the subthreshold current at stand-by mode. We call thisconfiguration the “low-power mode”. In addition, there is another advantage of VTCMOS: speed enhancement. When thestand-by current is fixed, the on-current (Ion ) can be largely
enhanced by the body effect in VTCMOS. This configuration
is illustrated in Fig. 1(b). In the active mode, the substratebias is changed in the positive direction to reduce the threshold voltage resulting in the enhancement of on-current. Thisis called the “high-speed mode”. Therefore, VTCMOS has
two modes with different objectives.
2.3 Simulation results
In order to investigate the VTCMOS performances in thetwo modes, two-dimensional device simulation6) was per-∗ E-mail address: hiramoto@nano.iis.u-tokyo.ac.jp2854

Jpn. J. Appl. Phys. Vol. 40 (2001) Pt. 1, No. 4B

T. H IRAMOTO et al.

log Ids
activeIoff,active
Ioff,standby

Vth= | Vbs|
stand-byIoff,standby(A/ m)

Ion,active

Body Effect Factor,(a)| Vbs| = 5 V 3 V

2V
1.5 V

acti ve
Ion,standby

Ion,active

Ion,active

A/ m)

1100

(a)
log Ids

10-5
Tech. Node: 180 nm| Vbs| = 0 V
10-6 Ion,active = 1 mA/ m (const.)
-7
10
0.3 V
10-8
-9
0.5 V
10
10-10
0.7 V
10-11
1V
10-12
10-13
1.2
V
1.5 V
2V
10-14
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

1200

Vdd Vgs

1000

1.2 V

900

1V

800

0.7 V

700
0.5 V

600 Tech. Node: 180 nm
Ioff,standby = 0.1 pA m (const.)

Ioff,active
Vth= | Vbs|
stand-byIoff,standby
Vdd Vgs(b)
Fig. 1. Schematics of VTCMOS characteristics in the two modes. (a)Low-power mode where Ioff is reduced while maintaining Ion . Ioff in thestand-by mode (Ioff,standby ) is suppressed compared with that in the activemode (Ioff,active ) using body effect. Vbs in the active mode (Vbs,active ) is 0 V
in this study. (b) High-speed mode where Ion is enhanced while maintaining Ioff . Ion in the active mode (Ion,active ) can be enhanced compared withthat in stand-by mode (Ion,standby ).

formed assuming uniformly doped, delta-doped, and counter
doped MOSFETs.5) The device parameters are based on
the International Technology Roadmap for Semiconductors(ITRS).7) Figure 2 shows the dependences of VTCMOS characteristics on γ and |Vbs | at the 180 nm technology node.
The supply voltage is 1.8 V. The characteristics of the lowpower mode are shown in Fig. 2(a) where the on-current isfixed and the stand-by off-current is derived as a function ofγ and |Vbs |. The high-speed mode is shown in Fig. 2(b)where the off-current is fixed and on-current is derived as afunction of γ and |Vbs |.
In the devices with Vbs = 0 V, which are normal MOSFETs, the stand-by off-current increases (Fig. 2(a)) or the active on-current decreases (Fig. 2(b)) as γ increases, because
subthreshold factor S is degraded. However, by applying Vbs ,lower stand-by off-current or higher active on-current can beachieved. It is suggested in both modes that |Vbs | should be
set as large as the junction leakage permits. It is also shownthat when the values of γ and Vth can be designed at a fixed
Vbs , the optimum γ depends on the relationship between acertain voltage Vo and |Vbs |, where Vo is about 50–70% of
the supply voltage Vdd .5) As shown in Figs. 2(a) and 2(b),

2855

500
0.0

0.1

0.2

0.3

0.4

0V

0.3 V

0.5

0.6

0.7

Body Effect Factor,(b)Fig. 2. VTCMOS characteristics as a function of γ and |Vbs | at the
180 nm technology node. (a) Low-power mode. Ion,active is fixed at a constant value (1 mA/µm). Vbs,active = 0 V. There is a critical voltage Vo ,where the optimum γ changes. Vo is about 0.7–1.0 V in this case. When|Vbs | is larger than Vo , a device with larger γ gives smaller Ioff,standby ,which is similar to the result in the high-speed mode. (b) High-speed
mode. Ioff,standby is fixed at a constant value (0.1 pA/µm). Vbs,active = 0 V
in this case. When |Vbs | is smaller than Vo , a device with smaller γ gives
larger Ion,active than that with larger γ . In contrast, when |Vbs | is larger
than Vo , a device with larger γ gives larger Ion,active although Ioff,active also
increases.

smaller off-current and larger on-current can be attained ina device with larger γ when |Vbs | is larger than Vo (about
0.7–1 V in both modes) in the low-power mode and in thehigh-speed mode, respectively. Vo is an important parameterin VTCMOS. VTCMOS can take full advantage when applied |Vbs | is larger than Vo . At the 180 nm technology node,
Vdd is sufficiently high. Therefore, both low-power mode andhigh-speed mode are applicable. The optimum guidelines forγ and |Vbs | are the same for both the modes.
3. Scalability of VTCMOS
3.1 Scaling scenarios
In this section, the scalability of VTCMOS is discussed.
When the device size and Vdd are scaled, the VTCMOS characteristics significantly differ from those of the 180 nm technology node. Three scaling scenarios are assumed and discussed in the following subsections. The scaling scenarios
assumed are summarized in Fig. 3. In all Scenarios, Ion,active
is set constant (750 µA/µm) with Vbs,active = 0 V. Consequently, Ioff,active rapidly increases as technology advances.
Scenario A is based on the low-power mode. In order toattain extremely low stand-by power, the low off-current of
0.1 pA/µm is targeted. Scenarios B and C are based on thehigh-speed mode. In Scenario B, the reduction ratio of offcurrent is set to a constant value of two orders of magnitude,Jpn. J. Appl. Phys. Vol. 40 (2001) Pt. 1, No. 4B

T. H IRAMOTO et al.

Ion,standby

Ioff,standby= 0.1 pA/ m(const .)Ioff,active
Ioff,standby
1999

2002

(180 nm)2005(130 nm)2008(100 nm)(70 nm)2011(50 nm)2014

Uniformly Doped MOSFETs
0.5
1.5
0.4

Ioff, st andby / Ioff, acti ve= 0.01 (const .)Ioff,standby
2002(180 nm)2005(130 nm)(100 nm)

2008(70 nm)2011(50 nm)

2014

10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14

Ion( A/ m)

Ion,active
Ion,standby
Ion / Ion
= 20% (const. )Ioff,active
Ioff,standby
1999(180 nm)2002(130 nm)2005(100 nm)

2008(70 nm)2011(50 nm)

2014

10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14

2002

2005

(130 nm)2008(100 nm)

2011(70 nm)2014(50 nm)0.0(35 nm)5
Scenario A
Scenario B Uniformly Doped MOSFETs
Scenario C

4
3
2

Constant( = 0.2)

1
0

1999

2002

(180 nm)(130 nm)2005(100 nm)

2008(70 nm)2011(50 nm)2014(35 nm)Year (Technology Node)Ioff(A/ m)

Scenar io C

300
200
100
0

1999

Fig. 4. Relationship between Vdd and Vth . Vth rapidly increases in Scenario A. Vth is roughly constant in Scenario B. Vth decreases in proportion to Vdd in Scenario C.

10-3(35 nm)Uniformly Doped MOSFETs

800
700
600
500
400

0.5

(180 nm)Year (Technology Node)
(b)
1000
900

0.2

0.0

Ioff(A/ m)Ion( A/ m)

Ion,standby

1999

1.0

Year (Technology Node)

Uniformly Doped MOSFETs
Ion,active

Ioff,active

0.3(35 nm)Scenario B

800
700
600
500
400
300
200
100
0

Scenario A
Scenario B
Scenario C

0.1

Year (Technology Node)
(a)
1000
900

2.0

0.6

Vdd(V)

Ion,active

10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14

Vth(V)

Uniformly Doped MOSFETs

Required| Vbs| ( V)

Ion( A/ m)

Scenari o A
1000
900
800
700
600
500
400
300
200
100
0

Ioff(A/ m)

2856

Fig. 5. Required |Vbs | in three scenarios at each technology node. Broken lines show the simulation results for uniformly doped MOSFETs,
where γ decreases as the device is scaled. Solid lines show devices with aconstant body effect factor (γ = 0.2), which roughly corresponds to constant short channel effect. Even in the latter case, Scenarios A and B will
fail due to large |Vbs | compared with Vdd .

(35 nm)Year (Technology Node)(c)Fig. 3. Three scaling scenarios of VTCMOS. (a) Scenario A: Ioff,standby
is constant (=0.1 pA/µm) (low-power mode).
(b) Scenario B:
Ioff,standby /Ioff,active is constant (=0.01) (high-speed mode). (c) Scenario
C: current enhancement Ion /Ion is constant (=0.2) (high-speed mode).
Ion,active is set to 750 µA/µm and Vbs,active = 0 V in all cases. Uniformly
doped MOSFETs are assumed. Device parameters at each technology
node are based on ITRS. The simulation results (Ion,standby in Scenarios
A and B, and Ioff,standby in Scenario C) derived under the assumption ineach Scenario are also shown by a broken line.

in which the threshold voltage shift Vth is roughly constant.
In Scenario C, the enhancement ratio of on-current is set to a
constant value of 20%. The required Vth and |Vbs | are simulated at each technology node, assuming uniformly doped
channel MOSFETs. MOSFETs with a constant value of γ(γ = 0.2) are also assumed when the required |Vbs | is discussed.
3.2 Low-power mode
In the battery-operated portable system, the stand-by current required is less than 0.1 pA/µm. Then, Vth in the stand-bymode should be higher than 0.5 V. The low-power mode of
VTCMOS aims at this kind of low stand-by current. Figures 4
and 5 show the required Vth and |Vbs | at each technology
node. In Scenario A, Vth becomes larger as Vdd is scaled,and |Vbs | increases rapidly and would exceed breakdown
voltage. Therefore, the scaling scenario of low-power mode
will fail in the future. One of the reasons for this failure is
the reduction of the body effect factor in the uniformly doped
channel MOSFETs5) as the device is scaled. When γ is degraded, the short channel effect immunity is also degraded.4)
In the ideal device scaling, γ should be kept constant in orderto suppress the short channel effect. Therefore, a channel engineered MOSFET with a larger γ is strongly required in normal MOSFETs as well as in VTCMOS in the future.5) However, even when γ can be kept constant (0.2), the required|Vbs | will increase due to the increase of Vth , as shown in
Fig. 5, and Scenario A will fail.
3.3 High-speed mode
The high-speed mode of VTCMOS gives up the suppression of off-current but aims at a high on-current in the active
mode. Scenario B has almost constant Vth and Scenarios C
has Vth proportional to Vdd , as shown in Fig. 4. Since the enhancement of on-current is roughly determined by Vth / Vdd ,Scenario B has a rapidly growing enhancement ratio and Scenario C maintains a constant enhancement ratio of on-current.
However, the required |Vbs | should be also scaled with Vdd ,considering the breakdown voltage. Therefore, Scenario B
will fail due to constant |Vbs |, as shown in Fig. 5, evenwhen γ can be kept constant (0.2). On the other hand, inJpn. J. Appl. Phys. Vol. 40 (2001) Pt. 1, No. 4B

T. H IRAMOTO et al.

VDD

Ion,enhance( A/ m)

1000
800

0.5 V

0.4 V

0.6 V

VTCMOS circuits

0.3 V

600

- high speed
0.2 V

400

0.1 V

200
Tech. Node: 35 nm
Ioff,normal = 160 nA/ m

GNDV

Vbs= 0 V

Leak cut-off Switch(BGMOS,SCCMOS)0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Body Effect Factor,(a)Ioff,enhance(A/ m)

2857

10-4

Tech. Node: 35 nm
Ioff,normal = 160 nA/ m
0.6 V

0.5 V

GND

0.4 V
0.3 V

10-5

0.2 V
0.1 V

10-6

Vbs= 0 V

10-7
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Body Effect Factor,(b)Fig. 6. VTCMOS characteristics in the high-speed mode as a function ofγ and |Vbs | at the 35 nm technology node. Here, the two modes aredenoted by enhancement and normal modes, instead of active and stand-bymodes. Positive Vbs is applied in the enhancement mode and Vbs in thenormal mode (Vbs,normal ) is set to 0 V. Ioff in the normal mode (Ioff,normal )is fixed at 160 nA/µm. When |Vbs | is sufficiently large compared with Vo(Vo is about 0.2 V in this case), Ion in the enhancement mode (Ion,enhance )increases markedly, although Ioff,enhance also increases.

Scenario C, since the required Vth decreases, the explosionof the required |Vbs | in the uniformly doped channel MOSFETs is greatly suppressed. Furthermore, the required |Vbs |in a MOSFET with constant γ decreases in proportion to Vdd
as the device is scaled. Considering the scaling of breakdown
voltage, Scenario C with a channel engineered MOSFET will
maintain the advantage of VTCMOS.
The above results suggest that Scenario C will be the only
way in which the VTCMOS can survive as device and supply
voltage are scaled. It is also suggested that γ should be kept
at a high value by utilizing a steep channel profile. Although
the stand-by off-current cannot be suppressed, VTCMOS canenhance the circuit speed and the enhancement ratio of the
speed can be maintained even if the device is scaled.

- high Vth- thick Tox

Fig. 7. A device/circuit scheme in the future, where the high-speed VTCMOS and a leak cut-off switch such as BGMOS10) or SCCMOS11) are
combined. VTCMOS enhances Ion and leak cut-off switch reduces Ioff .

lower than 0.6 V. Forwarded pn-junction current is negligible because it flows in the enhancement mode. The highspeed mode can attain high on-current in the enhancementmode when γ is high and applied |Vbs | is larger than Vo ,which is about 0.2 V in the present case. Although the offcurrent is also enhanced in the enhancement mode as shownin Fig. 6(b), the off-current can be reduced in the normal modeby switching Vth .
However, in the high-speed mode (Scenario C), the standby power will be huge even in the normal mode. We certainly
need another method to suppress the stand-by current. Figure 7 shows a schematic of the device/circuit scheme where
high-speed mode VTCMOS is combined with a leak cut-off
switch such as boosted gate MOS (BGMOS)10) and super cutoff CMOS (SCCMOS).11) The high-speed VTCMOS in combination with a low stand-by scheme would be one of the mostpromising device/circuit schemes that can attain high-speed
and low stand-by power at the same time in the future.
5. Conclusions
The optimum device parameters and scalability of VTCMOS are discussed. The optimum body effect factor depends
on the relationship between the substrate bias and the supply
voltage. Although the scaling scenario of low stand-by power
VTCMOS will fail, high-speed VTCMOS will take advantage
in the combination with another low stand-by scheme.
Acknowledgements
This work was partly supported by the Japan Society for
the Promotion of Science (JSPS) Research for the Future Program.

4. Device/circuit Scheme in the Future
Figure 6 shows the dependences of VTCMOS characteristics on γ and |Vbs | at the 35 nm technology node in Scenario
C. The supply voltage is assumed to be 0.4 V. In the highspeed mode, “stand-by” and “active” are not suitable mode
names. We rename the modes as “normal” and “enhancement” modes, respectively. To reduce the junction leakage
current by back-bias, Vbs is 0 V in the normal mode and thepositive Vbs is applied in enhancement mode.8, 9) The positive
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