P-2-5
Through Silicon Capacitive Coupling (TSCC) Interface for 3D Stacked Dies
Katsuyuki Ikeuchi, Makoto Takamiya, and Takayasu Sakurai
University of Tokyo
4-6-1, Meguro-ku, Komaba, Japan
Phone: +81-3-5452-6253 E-mail: ikeuchi@iis.u-tokyo.ac.jp

Abstract
A Through Silicon Capacitive Coupling (TSCC) interface enabling face-to-back capacitive coupling data transferfor 3D stacked dies is proposed. TSCC has three features,(1) it allows stacking more than three chips, (2) it enables
easy access to the bonding pads for DC power supplies, and(3) it enables the capacitive coupling pads to be used as
bonding pads. TSCC channel models are assumed anddesign guidelines are given for transceiver design. Atransceiver designed and fabricated in 0.18μm CMOS successfully communicates through a 400μm silicon substrate
at 200Mbps. It is also shown that thinning the chip will
reduce the area overhead of the TSCC pad.

Die 1 (face down)
Die 2 (face up)

PCB
Power supply(Bonding wires)(a)Pads for Through Silicon
Capacitive Coupling (TSCC)

1.

2.

Through Silicon Capacitive Coupling (TSCC)
A conventional face-to-face capacitive coupling integration is shown in Figure 1 (a). Stacking more than twochips is impossible, and the bonding wire for DC power
pins is difficult [2].
Figure 1 (b) shows the proposed face-to-back TSCC.
The pads on the upper chip are facing up, so stacking more

-1-Die 1 (face up)
Die 2 (face up)

PCB
Power supply(Bonding wires)(b)

Figure 1(a) Conventional face-to-face, and (b) proposed
face-to-back integration.
than three chips is possible, and bonding the DC power
supplies is straightforward.
Figure 2 is the cross-section of the TSCC channel
showing the underlying layers of the silicon substrate beWiring region:
thickness ~10μm,
εSiO2 = 4.1

Introduction
Proximity communication using capacitive coupling
and inductive coupling is a low power and low cost alternative to TSV’s. There are some problems which hider theadoption of these interfaces.
Capacitive coupling channels have only been able to beintegrated in a face-to-face fashion [1-3]. Only two chips
can be stacked, and bonding wires to the chips is difficult toimplement [2] as shown in Figure 1(a).
Inductive coupling channels enable the chips to bestacked in a face-to-back fashion [4]. This enables stacking more than 3 chips but the interface needs inductors.
Since merging an inductor and a bonding pad is difficult,the interface cannot be shared with a normal bonding pad,requiring it to be used solely for the purpose of communication between 3D stacked dies.
The target of this work is a capacitive coupling interface which is capable of face-to-back communication.
This enables (1) more than 3 tiers of chips to be stacked, (2)easy access to bonding pads for DC power, and (3) sharingof the bonding pad and capacitive coupling pad.
In this paper, a Through Silicon Capacitive Coupling(TSCC) interface which sends data through silicon substrate using capacitive coupling is proposed.

Pads for capacitivecoupling

Metal (Receiver Pad)

VSS

CSiO2
P+

P WellRSi

Core Circuit(Receiver)
N Well
P WellDeep N Well

N WellCSi
Silicon Substrate : thickness 400μm, εSi = 11.8

CGlue

Glue (α-Cyanoacrylate): thickness ~ 5μm, εGlue = 3.5

Metal (Transmitter Pad)

P WellVSSCore Circuit(Transmitter)
P+ N Well
P WellDeep N Well

N WellFigure 2 Cross-section of TSCC channel with assumedchannel model.

this slope should be determined.
To clarify the determining factors of the channel characteristics in the lower resistance region, the channel is simulated with inputs with two groups of input waveforms, onewith a high slew rate and another with a lower slew rate.
Figure 4(a) shows the simplified simulated model and figure 4(b) shows the simulated effect of RSi on the amplitudeof the receiver input. This shows that the output voltageof the transmitter does not have significant impact on thechannel, but the slew rate and resistance value of the channel determines the input voltage of the receiver circuit.
Therefore sizing the transmitter circuit is very important for
TSCC unlike conventional capacitive coupling, while thesignal amplitude itself has little impact on the input voltage.

4035VINRX [mV]

30TSCC

252015

Capacitivecoupling1050
1

101001000

RSi [Ω]Figure 3 Simulated channel characteristics when pulse issent from the transmitter pad to the receiver pad in Figure 2
under various RSi values.
tween the transmitter pad and receiver pad. The silicon
substrate is both a dielectric and a conductor. The channel
model is approximated and also drawn in this figure.

Input voltage

Figure 3 shows the channel characteristics under various
resistance values. The plateau at higher resistance values
is determined by the coupling capacitance and parasitic
capacitance as is the case with conventional capacitive
coupling. The lower resistance region is where the proposed TSCC channel is used, so the factors determining
Through Silicon Capacitive
Coupling (TSCC) channelHigh slew rate
(1.8[V/10ps])

1.8V
1V
0.2V

OUTTX

CGlue

CSi

CSiO2

INRX

Input voltage

time
Lower slew rate
(1.8[V/100ps])
1.8V

RSiCPara

1V
0.2V

time

VINRX [V]

(a)
0.14

1.8V

0.12

1V

0.1

3.

Circuit DesignFigure 5 shows the TSCC transceiver circuit. The
transmitter is a CMOS buffer to drive the transmitter pad.
The receiver which is slightly altered from [5] but has astronger transmission gate to minimize the offset, amplifies
the input pulse with a CMOS inverter amplifier and storesthe data with a CMOS latch. The receiver circuit can bedivided into four parts; the first part is a low noise amplifier
and replica bias circuit biasing the input at the logical threshold voltage of the following inverter (Inv 2). This portion determines the maximum operational frequency of theoverall circuit. Inverter 2 is the second part. This inverter amplifies the signal and decouples the latch in the following part from the bias voltage of the first part. Thispart, if too weak, cannot change the data written in the latch
while if too strong, will overwrite the data latched regardless of the previous data, with the DC offset mismatch.
The third part, which consists of Inv 3 and Inv 4, is thelatch. The input of the smaller feedback inverter (Inv 4)
and the Inv 2 hold the input voltage of the main inverter(Inv 3) to a voltage either higher or lower than the logicalthreshold of the Inv 3. If the input of the main inverter
crosses the logical threshold, the feedback inverter willhold the voltage. The final part is Inv 5, which brings thesignal swing back to rail-to-rail. Detailed design optimization of this circuit will be discussed here on since theinput voltages of TSCC circuits are small due to the attenuation by the conductance of silicon.
All the main inverters in this architecture are usedaround their logic threshold and any differences in the logic

0.2V

0.08
0.06

Transmittercircuit

0.04
0.02

IN

Through Silicon
Capacitive Coupling(TSCC) channel
CGlue CSi CSiO2

OUTTX

Receiver circuit

Inv 1
INRX

Inv 2
A

Inv 3
B

Inv 5
COUT

0012345RSiRSi [Ω]Transmission
Inv 4gate(b)Figure 4(a) Simplified model of TSCC channel, and (b)simulated channel characteristics with different input voltages and slew rates.

-2-Figure 5 Schematics of TSCC transmitter and receivercircuits. Note the names of the nodes and inverters.

threshold between the inverters will negatively affect thesensitivity of the circuit. The P-N ratio of the inverter isdetermined first. WhenWPMOS : WNMOS  μNMOS : μPMOS , where WPMOS andWNMOS denote the width of the PMOS and NMOS transistors, μNMOS and μPMOS denote the mobility of NMOS andPMOS, the logic threshold becomes 1/2VDD and both thehigh pulses and the low pulses of the input are amplified
symmetrically, leading to low jitter and high sensitivity.
On the other hand, when

VOUT (Inv 5)
VIN (Inv 3)

the circuit is minimized, leading to maximum operationalfrequency. In this design, a PN ratio of 2:1 is used, whichis in-between these two cases. Next the sizing of each
inverter is discussed.
Inverter 5 simply recovers the output of the latch torail-to-rail swing, so a standard cell size inverter (x1 inverter) is used since it does not need large gain or need to havesmall WID (WithIn Die) variation.
Inverter 3 also does not need to be large since it is only
driving inverters 4 and 5, so a standard cell size inverter islarge enough gain wise, but since the overall circuit is very
sensitive to the mismatch of the logical threshold of thisinverter, a x4 size inverter is selected for this design.
For inverter 5 to be “high”, the input of inverter 3 mustbe smaller than a certain voltage. This voltage can be
determined by drawing a butterfly curve of inverter 3 and 5
as shown in figure 6. The voltage division of the channel
resistance of inverter 2 at 1/2VDD and inverter 4 fully
turned on, must be smaller than this voltage, determining
the minimum ratio of inverter 2 and 4. Inverter 4 is madeas small as possible, since this determines the size of inverter 2. In this design, minimum size transistor widths with
0.5μm length transistors are used to make it small while
reducing WID variation.
The size of inverter 2 is constrained by another factor.
The input signal must be amplified enough by inverters 1and 2, to be able to change the data stored in the latch.
Having equal gain in inverters 1 and 2 is the most energy
efficient so the size of inverters 1 and 2 are designed to be

Inv 3

Minimum
hysteresis
needed at B
for full swing
at OUT

Inv 5

VIN (Inv 5)
VOUT (Inv 3)

Figure 6 Illustration of butterfly curve of Inv 3 and Inv 5.

-3-

VDD

20mV

1/2VDD

1/2VDD

VDD

VINRX

Figure 7 Illustration of the voltage at node C when input ofwhole receiver (INRX) is swept.

1.2
Minimum TX swing [V]WPMOS : WNMOS  μNMOS : μPMOS , the RC delay ofV(C)

10.8

0.6
0.4

0.20012
Ltransmission gate [μm]3Figure 8 Simulated transmission gate gate length dependence on minimum detectable TX voltage swing.
the same size. The minimum input voltage that is detected must be determined by the thermal noise, ambientnoise, voltage fluctuation, WID variation. In this case,
20mV is selected. With the size of inverter 4 fixed, andusing the same sizes for inverter 1 and 2, monitoring node
C while sweeping the input voltage of INRX of the wholecircuit will reveal a hysteresis as shown in figure 7. The
size of inverters 1 and 2 are determined so that the hysteresis seen at 1/2VDD is 20mV. In this design, a x4 size isselected.
Finally, the size of the transmission gate is determined.
Since the transistors in the transmission gate are turned on,
while inverter 1 only works around 1/2VDD, similar to thecase of inverter 2 and 4, the width of the transistor is minimized, and the optimum gate length is searched for.
When the transmission gate is too weak, the input will not
return to 1/2VDD in time for the next signal, which willcause an offset which in turn will degrade the following
signal pulse, but if the transmission gate is too strong, thesignal will be attenuated. Figure 8 shows the simulation
results where inputs of varying amplitude but with a fixed
frequency are fed in to the TSCC. The gate length of thetransmission gate is swept. This reveals the gate lengthwith the highest sensitivity. Following these steps will

TX
coreRXcore

Pad forTSCC

750μm

750μm(a)(b)

850μm

Pad forTSCC

850μm

Received data (Out)Input data (In)
200Mbps

Figure 9 Chip micrograph of (a) transmitter, and (b) receiver with TSCC pads.

Figure 11 Measured input (bottom) and output (top) waveforms at 200Mbps.
1mm x 1mm

106

400μm thick
RX die (face up)
Pad area (μm2)

This work

TX die (face up)

500μm x 500μm

105

300μm x 300μm
200μm x 200μm

Coupling capacitanceof TSCC=160fF
104

Pad for TSCC

100μm x 100μm
1101001000

Distance of TSCC (=thickness of silicon substrate) (μm)

Figure 12 Calculated dependence of pad area on distanceof TSCC when coupling capacitance of pads is 160fF.
Figure 10 Photograph of 2-stacked dies for TSCC.
lead to a 20mV input receivable TSCC circuit.
4.

Measurement Results
A TSCC transceiver chip is fabricated in 0.18μm
CMOS. The chip micrographs of the transmitter and receiver circuits are shown in Figure 9. The pad for TSCC
is 850μm x 750μm. The core of the transmitter circuit is
40μm x 5μm, and the receiver circuit is 20μm x 5μm.
Figure 10 shows the stacked transmitter die and receiver die. The bottom die is the transmitter facing up, and thetop die is the receiver which is also facing up. To enable
TSCC, both transmitter and receiver circuits are in a deepn-well to make the silicon substrate floating and to keep thesubstrate contacts far away from the receiver pad so that thesubstrate resistance is high enough. The thickness of thereceiver chip, which is equal to the communication distance,
is 400μm. This means that the coupling capacitance (CC)of the TSCC interface is 160fF.
Figure 11 shows the measured input and output datawaveforms. A 27-1 PRBS data is sent at 200Mbps.
Correct data reception over the TSCC channel is confirmed.
Figure 12 shows calculated dependence of the pad areaon the distance of TSCC at CC of 160fF. Since this is afeasibility study, 850μm x 750μm pads are used to communicate through a 400μm thick substrate. To keep the am--4-

plitude of the received signal constant, if the substrate were
to be thinned to 50μm, the TSCC pad will be 280μm x280μm. When thinned to 10μm, the TSCC pad will be125μm x 125μm, so the more the substrate is thinned, themore the area overhead of the TSCC pad is reduced.
5.

Conclusions
A Through Silicon Capacitive Coupling (TSCC) interface enabling face-to-back capacitive coupling data transferfor 3D stacked dies is proposed. This allows multiple tierstacking, easy access to bonding pads on all tiers, and sharing of pads between conventional bonding pads and TSCC.
Channel characteristics of TSCC are modeled, revealingthat the input slew rate of the transmitter is important inTSCC as opposed to capacitive coupling. Design optimization of the circuit for maximum sensitivity is shown. A
transceiver designed in 0.18μm CMOS successfully demonstrated communication through a 400μm silicon substrate
up to 200Mbps.
Acknowledgements
The VLSI chips have been fabricated in the chip fabrication
program of VDEC, the University of Tokyo in collaboration withRohm Corporation, Toppan Printing Corporation, Cadence Design
Systems, Inc., and Synopsys, Inc.

References[1] R.Drost, et al., “Proximity Communication,” in IEEE J. Solid-State Circuits, Vol. 39, No.9, pp 1529-35, Sep. 2004.
[2] A. Fazzi, et al., “3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly,” in IEEE J. Solid-State
Circuits, Vol.42, No.10, pp 2270-2281, Oct. 2010.
[3] S. Mick, J. Wilson, and P. Franzon, “4 Gbps High-density AC
Coupled Interconnection,” in IEEE Custom Integrated Circuits
Conference (CICC), pp 133-140, May. 2002.
[4] M. Saito, N. Miura, and T. Kuroda, “A 2Gb/s 1.8pJ/b/chip
Inductive-couplingThrough-chip
Busfor128-Die
NAND-Flash Memory Stacking,” in IEEE Int. Solid-State
Circuits Conference (ISSCC), pp 440-441, Feb. 2010.
[5] S. Kuhn, M. Kleiner, R. Thewes, and W. Weber, “Vertical
Signal Transmission in Three-Dimensional Integrated Circuits
by Capacitive Coupling,” in Int. Symp. Circ and Sys
CAS ’95), pp 37-40, May 1995.

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