Half VDD Clock-Swing Flip-Flop with Reduced
Contention for up to 60% Power Saving in ClockDistribution
David Levacq1, Muhammad Yazid2, Hiroshi Kawaguchi3, Makoto Takamiya1, Takayasu Sakurai1
1

levacq@iis.u-tokyo.ac.jp
Center for Collaborative Research
University of Tokyo
Tokyo, Japan

2

Fujitsu Microsolutions
Kanagawa, Japan

Abstract— A new low clock swing flip-flop (F/F) is proposed.
The existing low clock-swing F/F’s consume high power,
introduce speed penalty due to contention currents or requirelarge silicon area due to separate well for substrate biasing. By
reducing contention currents, our proposal efficiently mitigates
those issues. Measurements and simulations are carried out
based on a 90 nm CMOS process, demonstrating reductions ofactive power by 71%, area by 36% and delay by 35% compared
to previous proposals. It is shown that the combination of a lowclock swing distribution tree with the new F/F can save up to60% of the total clock system power.

3Kobe University
Kobe, Japanthe chip: the first swinging from zero to half VDD to control
NMOSFETs, the second swinging from half VDD to VDD tocontrol PMOSFETs. While this technique has little impact onspeed, the requirement to distribute two clock signals presents
some difficulties regarding routing and skew adjustment.

I. INTRODUCTION
Reduction of power consumption of VLSI circuits is a
growing concern. A direct solution is to reduce the system
supply voltage VDD. However, this can only be done at theexpense of speed degradation, which can be unacceptable inhigh-performance systems. Another solution is to reduce theclock voltage swing without reducing VDD. This has beenshown to be an efficient approach to reduce power dissipation
because clock distribution is a major contributor to the power
dissipation in VLSI circuits (20 to 45% of the total chippower)[1]. If VDD for logic circuits is kept high, this technique
has little impact on speed, at the condition to have flip-flops(F/F) that can operate efficiently under reduced VCK.

The previously proposed Reduced Clock Swing F/F [1](RCSFF, Fig. 1b) requires only one clock signal swinging
between 0 and a low voltage VCK<VDD. However, it is clear
from Fig. 1b that when clock signal is high, the clocked
PMOSFETs cannot be efficiently turned off, resulting in a
direct current path from VDD to ground and high power
dissipation. This difficulty can be partially circumvented byconnecting the n-well of clocked PMOSFETs to a highvoltage bias to increase their threshold voltage (Vth) andthereby reduce the leakage. But this requires to layout thosetransistors in a separate well and to generate and distribute avoltage bias above the standard VDD, which complicates thedesign and increases the circuit’s area. Moreover, the voltagebias that can be applied to the separate well is limited byreliability constraints. Last but not least, the prechargedischarge cycles inside the F/F result in unnecessary power
dissipation when input signal is kept constant over several
clock cycles. The high power consumption of RCSFF
therefore strongly reduce the benefits of low clock swing toreduce the chip power dissipation.

A first simple idea is to insert low-to-high level converters
in front of conventional F/Fs to regenerate a full clock signal[2][3] (Low-to-High converter D-F/F (LHDFF), Fig. 1a).
Theoretically, neglecting clock skew issues, this techniquedoesn’t have any impact on the system performance since thelogic critical path is not affected. However, it doesn’t translate
in large power savings since voltage swings are reduced on theclock-tree distribution lines only while the high number of
low-to-high level converters consumes considerable power.
Therefore, a more efficient approach would be to implement
F/Fs that can directly receive a reduced swing clock. In [4],two separate half-swing clock signals are distributed acrossThe NAND-type Keeper F/F [5](NDKFF, Fig. 1c) doesn’t
require separate well and eliminates unnecessary signaltransitions inside the F/F for constant input. However, twointernal nodes are subject to contention. When QQ node is low
while D is high, there is a fighting (contention) between theON NMOSFETs pulldown network and the ON PMOSFET(in bold in Fig. 1c) to discharge node X at the clock risingedge. Similarly, there is a fight against the positive feedbackof the latch formed by inverters I6,7 to change the state ofnode QQ. Our simulations show that the required sizing toguarantee functionality across all process corners despite thosecontentions results in suboptimal speed performance.

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Figure 1. Low Clock-Swing F/F circuits (a: LHDFF [2],[3]; b: RCSFF [1]; c: NDKFF [5]; d: proposed CRFF). The numbers indicate the transistors widths inµm (unless otherwise explicitly stated, NMOSFETs widths=0.54µm, PMOSFETs widths=0.82µm, lengths=0.1µm).

In this paper we propose a new low clock-swing F/F thatcan operate under half-VDD clock swing. The F/F architecture
results in reduced contention currents, which guarantees highspeed and low power operation.
The rest of the paper is organized as follows. In Section II
we describe our new proposal. Simulations results arepresented in Section III where the properties of different low
clock-swing F/Fs are compared. Experimental results arediscussed in Section IV.
II. REDUCED CONTENTION FLIP-FLOPThe new proposal, the low clock-swing ContentionReduced F/F (CRFF), is shown in Fig. 1d. Its operation isillustrated by the timing diagram in Fig. 2. After the clock
signal CK goes high, there is a short time window where passtransistors N1,2,3,4 are all ON (transparency window).
Depending on the input data D, either node QQ or node QQ isdischarged. When N1,2 are turned off at the end of thetransparency window, the CMOS latch made of inverters I6,7
is activated in order to store the data. Contention currents arereduced in two ways. Firstly, the pull-up circuit (P1,2) iscontrolled by the input D through P3,4 to reduce thecontention with NMOS pass transistors. Secondly, clock-191

driven P5 and P6 disconnect the I6,7 CMOS latch from VDD
during the transparency window.
III. SIMULATION RESULTS
A conventional D-F/F preceded by a low-to-high level
converter (LHDFF), RCSFF, NDKFF and CRFF have been
designed on a 90 nm bulk CMOS technology (Fig. 1). The
F/Fs have been sized in order to provide highest speed while
minimizing their area and guaranteeing proper operation at allprocess corners. Since high-Vth (±0.3V ) and low-Vth (±0.2V ) transistors were available in this particular process,those have been adequately combined for the best delay/power
dissipation tradeoff. However, the F/Fs can be designed insingle-Vth technologies as well. NDKFF and CRFF are bothpulsed F/Fs. The clock pulsewidth must be long enough toguarantee that the NMOS drivers have enough time to develop
a sufficient signal on the internal nodes to flip the state of theF/F. On the other hand, a long pulsewidth results in a longer
transparency window of the latch and a longer hold time.
Optimal pulse was obtained with three cascaded high-Vthinverters. The different F/Fs have been simulated according to
the method described in [6]. 20fF capacitive loads at the data
input and at the inverting and non-inverting outputs simulate
the signals degradation due to other stages.

areas of RCSFF and CRFF are 39.23 µm2 and 25.25 µm2
respectively. The larger area of RCSFF is a consequence ofthe separate well for the clock PMOSFETs (Fig. 1b). The new
proposal therefore results in 36% area savings. A photographof the test chip is shown in Fig. 5.

The timing characteristic that best characterizes the speed
performance of a F/F is the minimum D-to-Q delay (tD-Q,min,[6]). Indeed, tD-Q,min represents the minimum portion of timethat the F/F takes out of the clock cycle in a pipeline chain.
The extracted tD-Q,min of the different F/Fs are plotted in Fig. 4.
As discussed before, the insertion of a LH converter doesn’t
degrade the optimal delay of the conventional D-F/F. RCSFF
features high speed performance as well, at the price of highpower dissipation. The delay of CRFF is kept to 1.6 times (i.e.
378 ps) that of the conventional high swing F/F, which isreasonable. It is 35% lower than the NDKFF delay.
IV. EXPERIMENTAL RESULTS
To verify the functionality of the CRFF and validate thesimulation results, test structures for RCSFF and CRFF havebeen implemented on a 1V 90nm CMOS technology. The

192568nW960nW

4.5
4.01350nW

24.6nW

23.9nW18LHDFF
RCSFF
NDKFF
CRFF

3.5
3.0
2.5
2.0

161412108

1.5
1.0

60.5
0.0

240

α=0

α=0.5

α=1

CK=0V

CK=VDDFigure 3. Simulated power dissipation of low clock swing F/Fs scaled to thepower dissipation of a conventional D-F/F operating under full clock swing(PDFF), for different activity ratios α ; VDD=1V, VCK=0.5V, fCK=100MHz.

3.0

tD-Q,min/tD-Q,minDFF

A first observation is that the insertion of a level converterin front of a conventional D-F/F results in a considerable
power increase, strongly mitigating the expected power
reduction due to low clock swing scheme. In all conditions,the new CRFF features the lowest power dissipation. By
contrast, RCSFF demonstrates a high power dissipation due tothe precharge cycles. Its very high static power dissipation
when clock is high is due to the leakage of the clocked
PMOSFETs that are not sufficiently turned off. For low
activity ratios, the power dissipation of CRFF is significantly
reduced compared to the conventional high clock swing DF/F. For minimum α = 0 , power dissipation is less than 50%of the conventional D-F/F and 71% lower than RCSFF. This
benefit adds to the power reduction in the clock tree resulting
from low voltage swing on the clock distribution lines(divided by 4 in the case of half-VDD clock swing).

P DF F :Static Pow e r (P/ P D F F)

The static power dissipation and the active power
dissipation of the different F/Fs have been extracted for
different input data activity ratio α , considering a 100MHzclock frequency. The results are plotted in Fig. 3. They werescaled to the power dissipation of a conventional D-F/F (i.e.
LHDFF of Fig. 1a without Low-to-High converter) operating
under full clock swing. For α = 0.5 , a pseudo-random data
input sequence has been applied. The extracted powerincludes the power dissipated by the buffers on switching theF/Fs data and clock input capacitances, and the internal power
dissipation of the F/F, excluding the power dissipated on
switching the output load capacitance [6].

Ac tive powe r ( P/PD F F )Figure 2. Timing diagram of CRFF

The clock-to-Q delay (tCQ) has been extracted thanks toring oscillator structures as illustrated in Fig. 6. During one
period, every F/F undergoes both high-to-low and low-to-hightransitions. The oscillation period is therefore determined by
the average tCQ of the F/F and by the delay introduced by theXOR gates. This delay is measured and subtracted thanks toanother ring oscillator made of XOR gates. Fig. 7 shows theextracted average tCQ of the F/Fs as a function of VCK.
Simulation results are plotted as well, demonstrating goodfitting with measured data. This validates the simulation
results from previous section.

tD-Q,minDFF =238ps

2.5
2.0
1.5
1.0
0.5
0.0

LHDFF RCSFF NDKFF CRFF

Figure 4. Simulated minimum D-to-Q delay (tD-Q,min)Figure 5. Microphotograph of test chip with power measurement and ringoscillators (RO) structures.

The power dissipation has been extracted by measuring 60
F/F in parallel. Fig. 8 shows the measured power supplied by
VDD for one F/F as a function of the clock frequency(VCK=0.6V) for maximum activity input data D (different
input on every clock cycle), and constant input (D=0). Despitea high voltage bias (Vwell=2V) for the separate well in RCSFF,
its power dissipation is strongly larger than CRFF. Moreover,as expected, RCSFF dissipates unnecessary power when theinput is constant. On the contrary, power dissipation of CRFF
is efficiently reduced when input data is kept constant.

Figure 6. Ring oscillator structure for tCQ measurement.
1800
1600
1400

Average tCQ [ps]V. CONCLUSION
A new F/F with low clock swing voltage has been
demonstrated and its performance compared with previously
proposed solutions by experimental measurements andsimulations. Former proposals either consume relatively highpower (LHDFF, RCSFF), or are slower due to contention
currents that require suboptimal sizing to be robust against
process variations (NDKFF). The new proposal demonstrates
36% area reduction, and up to 71% power savings compared
to previous solutions.

RCSFF Measurement
CRFF Measurement

1200

RCSFF Simulations

1000

CRFF Simulations

800

CRFF (proposed)

600
400
200

RCSFF

00.5

0.6

0.7

0.80.9

Typically, clock tree and F/Fs account for 60% and 30% of
the total clock distribution system of a VLSI chip respectively[2]. According to the results extracted in this paper, CRFF
with half-VDD clock swing can reduce clock system power by
50-60% depending on the data activity ratio (Fig. 9).
Considering a typical contribution of 40% for the clock
distribution circuits to the total chip power, this translates in a
reduction of total chip power by 20-25% The price to pay for
performance is very low, the insertion delay penalty of theCRFF being increased by less than 60% compared with aconventional high clock swing F/F while the logic critical pathremains unchanged.

1Clock Swing (VCK) [V]Figure 7. Measured average tCQ versus VCK250RCSFF200

Power [nW]

Varying input D(α=1)
150

CRFF

ACKNOWLEDGMENTS
This work is partially supported by MEXT andHitachi, Ltd. The test chip has been fabricated through thechip fabrication program of VLSI Design and Education
Center, the University of Tokyo, with the collaboration ofSTARC.

100Constant input D(α=0)

50

REFERENCES

0024681012[1]Figure 8. Measured power dissipation of F/F for different input data Dconditions (VDD=1V, VCK=0.6V, Vwell in RCSFF = 2V).

[2]

Clock Frequency [MHz][3]

Conventional-50%

Half-VDD clock
swing with CRFF
α=0.5[4]-60%clock tree
F/Fs
Root driver

Half-VDD clockswing with CRFF
α=00%

20%

40%

60%

80%

100%

[5]
120%

[6]
Figure 9. Different contributions to the clock distribution system power for
conventional case (i.e. full clock swing distribution with conventional F/Fs)
and for Half-VDD clock swing distribution with the proposed CRFF.

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