Combined Shared-Memory and Buffered-Crossbar Architecturefor High-Bandwidth Onboard Switching Fabric
Ling Zheng
Chen Yi

Weitao Pan
Huan Liu

lingzheng@xupt.edu.cn,chenyi0818@xupt.edu.cn
School of Communication and Information Engineering,
Xi’an University of Posts and Telecommunications
Xi’an, China

wtpan@mail.xidian.edu.cn,huanliu@stu.xidian.edu.cn
State Key Laboratory of Integrated Services Networks,
Xidian University
Xi’an, China

CCS CONCEPTS• Networks → Bridges and switches.

KEYWORDS
Satellite network; switching fabric; buffered crossbar
ACM Reference Format:
Ling Zheng, Chen Yi, Weitao Pan, and Huan Liu. 2021. Combined SharedMemory and Buffered-Crossbar Architecture for High-Bandwidth Onboard
Switching Fabric. In 5th Asia-Pacific Workshop on Networking (APNet 2021),
June 24–25, 2021, Shenzhen, China. ACM, New York, NY, USA, 2 pages.
https://doi.org/10.1145/3469393.3469672

1

INTRODUCTION

The space-air-ground integrated networks (SAGINs) [2] have envisioned to provide seamless network services to spatial, aerial andground users, satisfying the various future network requirements[4]. To enable the space-based systems to support and integrate
the applications on the ground, the satellite network needs to becompatible with terrestrial IP-based technologies and protocols.
The onboard packet switching has become an important part of thesatellite communication networks. The satellite onboard switches
is developing toward larger capacity and higher bandwidth, but
the hardware resource, memory capacity and power consumption
are greatly limited due to the environment in the space [1]. Design and implementation of high-performance satellite onboard
switching fabric while strictly controlling the resource consumption is essential for future communication networks. In this paper,
we propose a novel memory architecture called Combined Sharedmemory and Crosspoint Queuing (CSCQ) for onboard switchingfabric. A fixed number of input ports are multiplexed into one
internal bus, and multiple internal buses are interconnected by acrosspoint queued crossbar switching element. The memory size at
This work was supported in part by Scientific Research Program Funded by Shaanxi
Provincial Education Department(20JK0923), Natural Science Basic Research Programof Shaanxi Province(2021JQ-708), Scientific Research Program of Yulin City(YF-2020183) and National Natural Science Foundation of China(61306047).
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APNet 2021, June 24–25, 2021, Shenzhen, China© 2021 Association for Computing Machinery.
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https://doi.org/10.1145/3469393.3469672

the input side and the number of crosspoints can be reduced withno performance degradation. The proposed architecture aims at reducing the memory while maintaining high-bandwidth in resource
limited satellite onboard environment and is suitable for multi-port
and high-bandwidth onboard switching scenarios.

2ARCHITECTURE DESIGNThe CSCQ architecture consists of Shared-menory Input Modules(SIM), the Buffered Crossbar (BX) and the Output Arbitration Modules (OAM). In the input side, the SIM works as a traffic multiplexer.
Each input module multiplexes k input ports into one Input Bus(IB), where k is a constant which is determined by the system configuration. The input packets from those input ports are firstly
queued in the SIM in a shared memory form, and then scheduled
and transferred to the crossbar. For a N × N switching fabric, there
are N /k SIMs. The ith SIM is denoted as SIM(i) and the hth input
port in it is denoted as IP(i, h).
The BX element perform the data forwarding from the input
modules to the output modules. Each crosspoint has a buffer for
queuing packets. The crosspoint queue connecting SIM i and OAM
j is denoted as CQ(i, j), and there are totally (N /k)2 CQs in the BX
element. A packet from SIM i destined to OAM j can be scheduled
and sent to CQ(i, j) only when CQ(i, j) has a free buffer.
The OAM demultiplexes data from one Output Bus (OB) into
multiple output ports. When a packet arrives at the OAM, it delivers the packet to the corresponding output port according to thedestination address. There are N /k OAMs in an N × N switching
fabric, and the hth output port at jth OAM is denoted as OP(j, h).
In the SIMs, to avoid the Head of Line (HOL) blocking, the input packets are arranged as Virtual Output Queues (VOQs). EachSIM maintains a set of dedicated output queues (one queue for
one OAM). For QoS support, each VOQ can be further arranged asmultiple Virtual Output Priority Queues (VOPQs). A set of schedulers are used to control the data transmission in the switching
fabric. According to their locations, the schedulers in CSCQ include
priority scheduler, input bus scheduler, output bus scheduler andoutput port scheduler.
1) Priority Scheduler - Each VOQ in a SIM has a priority scheduler to provide differentiated services for different flows in the same
VOQ. The queue selected by the priority scheduler can send a transmission request to the input bus. A set of Request Queues (RQs)
are uesed to store the requests of packets that intend to occupy theinput bus. To support differentiated service, the priority schedulers
often adopt Strict Priority (SP), Weighted Round Robin (WRR), or
Weight Fair Queuing (WFQ) algorithms.

APNet 2021, June 24–25, 2021, Shenzhen, China

L. Zheng and C. Yi, et al.

Buffered Crossbar
Crosspoint Queue

SIM(0)IP (0,k-1)...
CQ (0,0)Packet Delay (us)CQ (0,N/k-1)

CQ (0,1)

IP (1,0)SIM(1)IP (1,k-1)...
CQ (1,N/k-1)

2000

800
600
400

...
CQ (N/k-1,1)

OP (N/k-1,1)

OP (N/k-1,k-1)

OP (N/k-1,0)

OP (1,k-1)

OP (1,1)

OP (1,0)OP (0,k-1)

...

...

OP (0,1)

1000

8121620
Switch Size, N

24283248121620
Switch Size, N

242832(b) CICQ

OAM
(N/k-1)...

OAM(1)...

OP (0,0)1500

Figure 2: Packet delay as a function of switch size for CSCQ
and CICQ architecture.

CQ (N/k-1,N/k-1)

Slice LUT as Logic (K)Slice Register (K)Slice LUT as Memory (K)Block RAM (Mb)

600

Figure 1: The CSCQ architecture.

500
400
300200The performances of the proposed CSCQ architecture are evaluatedby software simulations as well as hardware experiments. In thesimulations, we adopt a 16 × 16 switch, and each input/output port
has a bandwidth of 10 Gbps. The speedup ratio k = 4. That is to say,
4 input/output ports are merged into one internal bus, and only
a 4 × 4 crossbar is needed. The shared memory capacity for each
SIM is 4Mb, while the crosspoint queue size is fixed to 24kb. After
that, we generate different types of traffic flows as input loads toevaluate the performance of the proposal.
The packet delay as a function of switch size is shown in Fig. 2.
For comparison purpose, the CICQ [3] switching architecture isused under the same simulation parameters. Compared with CICQ
architecture, the queuing delay of CSCQ is much less. The reason is

Block RAM (Mb)

1600
1200

80008PERFORMANCE EVALUATION

Slice Register (K)Slice LUT as Memory (K)40002) Input Bus Scheduler - Each input bus has an input scheduler.
The function is to determine which RQ will occupy the input busand send data to the CQs of the corresponding crosspoint. Since
the switching fabric has the buffering capability, each scheduler
can make independent decisions based on the state of CQs on thisbus without concern for the request from other ports. Therefore,
the input bus scheduler can adopt simple unidirectional schedulingalgorithms such as SP, Round Robin (RR), Longest Queue First (LQF)
or Oldest Cell First (OCF). These algorithms can be executed inO(1) time, which can greatly reduce the time complexity.
3) Output Bus Scheduler - Each output bus has a individualscheduler, which schedules the CQs within an output bus in thevertical direction. An output bus scheduler often adopt some kindof fair algorithm such RR for the fairness amount different output
ports. An output bus scheduler select one CQ, then the output bus
is occupied by the selected CQ and the head of line packet is readout and sent to the destination OAM only when the corresponding
output port is free. The status of each output port in an OAM isreturned by the output port scheduler.
4) Output Port Scheduler - Each OAM also has an individualscheduler, which selects free OPs and reports the result to the output
bus scheduler on the same vertical line.

Slice LUT as Logic (K)
2000

100

3

CICQ with OCF(a) CSCQ

Output Port
Scheduling
OAM(0)

CICQ with WRR

CICQ with LQF

04SIM(N/k-1)

IP (N/k-1,k-1)
CQ (N/k-1,0)

CICQ with SP

500

0...

...

1000

Output Bus
Scheduling

IP (N/k-1,0)
IP (N/k-1,1)

CSCQ with OCF
2500

...

CQ (1,1)...

...

CQ (1,0)

CS&Q with WRRCSCQ with LQF

200

Number of Resources...

IP (1,1)

CSCQ with SP
1200

Number of Resources...

IP (0,1)

Input Bus Scheduling

Packet Delay (us)IP (0,0)162432
Switch Size, N(a) CSCQ

4048

8162432
Switch Size, N

4048(b) CICQ

Figure 3: FPGA resource cost as a function of switch size for
CSCQ and CICQ architecture.
that CSCQ architecture merges multiple ports into one input/output
bus, reducing the complexity of switching fabric significantly. Theinternal speedup also helps to improve the switching performance.
Compared with CICQ, the CSCQ can reduce the packet delay byabout 46% ∼ 69% for different switch size.
The proposed CSCQ architecture with k = 4 is then implementedin Xilinx Ultrascale+ VU13P FPGA platform. The resource cost are
obtained by the Vivado development tool as shown in Fig. 3. According to our experiments, compared with CICQ, the LUT resourceis saved by about 47% ∼ 68%, and the block RAM is saved by about
79% ∼ 85%. Using the state-of-the-art Xilinx VU13P FPGA, which
has 94.5Mb on-chip block RAMs and 1,728K LUTs, an up to 48 × 48switching fabric with 10 Gbps bandwidth per port can be achieved.
Such capacity is quit high for satellite onboard switching.

4CONCLUSION

We have presented a combined shared memory and crosspoint
queuing architecture for high-bandwidth switching fabric. Our
design provides scalability for multi-port onboard switching bytraffic multiplexing, memory sharing and hierarchical scheduling.

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