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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 11, NOVEMBER 2007

Stacked-Chip Implementation of On-Chip Buck
Converter for Distributed Power Supply
System in SiPs
Kohei Onizuka, Student Member, IEEE, Kenichi Inagaki, Member, IEEE, Hiroshi Kawaguchi, Member, IEEE,
Makoto Takamiya, Member, IEEE, and Takayasu Sakurai, Fellow, IEEE

Abstract—An on-chip buck converter which is implemented bystacking chips and suitable for on-chip distributed power supply
systems is proposed. The operation of the converter with 3-D chip
stacking is experimentally verified for the first time. The manufactured converter achieves a maximum power efficiency of 62% for
an output current of 70 mA and a voltage conversion ratio of 0.7
2 mm on-chipwith a switching frequency of 200 MHz and a 2
LC output filter. The active part and the passive LC output filter
are implemented on separate chips fabricated in 0.35- m CMOS
and connected with metal bumps. The use of glass epoxy interposer
to increase the maximum power efficiency up to 71.3% is also discussed.
Index Terms—Buck converter, distributed power supply, systemin-a-package (SiP), stacked chip.

I. INTRODUCTIONECENTLY, system-on-a-chip (SoC) and system-in-apackage (SiP) are getting more and more interest as
major integration technologies. They are often used to integrate various types of circuit blocks from processors andmemories to analog circuits. Each block demonstrates a difand the difference tends
ferent optimum supply voltage
to increase as the technology scales. For example, memory
and analog circuits tend to prefer higher voltage compared
trends for precision
with logic blocks. Fig. 1 shows theanalog/RF, performance analog/RF, high-performance logic,
and low-power logic with the design rule trends according to
the International Technology Roadmap for Semiconductors
implementation is therefore(ITRS) 2005 [1]. Multiplerequired in low-power and high-performance systems. Moreover, supply voltage is sometimes tuned in time to achieve
lower power consumption, which is called dynamic voltage
scaling. The supply of many different and dynamically scaled
voltages from outside the package gives rise to much overheadin area. The power line integrity, including IR drop and noise,
becomes an issue as well. The distributed on-chip power supply
circuits are useful for solving these problems. The concept ofthe distributed power supply is shown in Fig. 2. High voltage isR

Manuscript received February 19, 2007; revised May 29, 2007.
K. Onizuka, K. Inagaki, and M. Takamiya are with the Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan (e-mail: kohei@iis.utokyo.ac.jp).
H. Kawaguchi is with the Department of Computer and Systems Engineering,
Kobe University, Kobe 657-8501, Japan.
T. Sakurai is with the Center for Collaborative Research, University of Tokyo,
Tokyo 153-8505, Japan.
Digital Object Identifier 10.1109/JSSC.2007.906204

Fig. 1. Supply voltage trend with design rule trend according to ITRS.

distributed by a main power grid and is then converted to thelower voltages at the vicinity of the target blocks by distributed
on-chip voltage converters. This approach reduces cost andpower integrity issues.
For dc–dc converters, linear regulator, buck converters andswitched capacitor converter are well known circuits. A buckconverter requires large passive elements of inductance and capacitance (LC) for an output filter but it shows a higher power efficiency than a linear regulator. A switched-capacitor converter
also needs large capacitors and one more drawback is that theoutput voltage levels are limited by the ratios of prepared capacitors. That is not very suitable for low-power dynamic voltage
scaling systems.
In case of the buck converter, high switching frequency ispreferable for smaller L and C but the power efficiency is degraded by the dynamic power dissipated by switching transistors at high frequency. Low quality factor (Q) of air-core andon-chip inductors also degrades the power efficiency. High inductance is good for high Q but is not easy to obtain on a chip
because of the area limitation and, even if high magnetic permeability material is introduced on a chip, high- property is
usually lost at high frequency.
A couple of integrated buck converters have been reported
in recent years. Efficiency of 80%-87% was achieved at a highswitching frequency of 233 MHz for voltage conversion ratios of 0.75 and 0.79 with off-chip air-core inductors in 90-nm
CMOS process [2]. The air-core and surface-mount inductors
whose quality factors are over 20 contribute to higher power efficiency. However, the part cost, the assembly cost and area are

0018-9200/$25.00 © 2007 IEEE

ONIZUKA et al.: STACKED-CHIP IMPLEMENTATION OF ON-CHIP BUCK CONVERTER

Fig. 2. Concept of distributed power supply system.

problems and the approach is not suitable for on-chip distributed
power supplies where many inductors are required nearby.
On the other hand, 50% efficiency without zero voltage
switching (ZVS) and 65% with two-stage ZVS, at a switchingfrequency of 45 MHz with a voltage conversion ratio of 0.64,
have been demonstrated in 0.18- m SiGe process with on-chip
integrated output filter [3]. In this implementation, the output
filter is costly because it consumes large silicon area in a precious scaled process. Moreover, in this specific implementation,
metal thickness is chosen to be 10 m, which is again costly
and which is not usually available.
It is reported that 80% effective efficiency with ZVS implemented with an on-chip integrated output filter was achieved at
a very high switching frequency of 3 GHz, with a voltage conversion ratio of 0.52 in 90-nm CMOS [4]. In this implementation, the high effective efficiency is achieved by using clock-tree
charge-recycling. The raw efficiency of the converter itself isstill 48%.
Therefore, other approaches to implement buck converters for
distributed power supply systems are to be sought through focusing on cost issues and package friendliness.
II. BASIC CONCEPT OF STACKED-CHIP IMPLEMENTATION
In order to implement on-chip buck converters for distributed
power supply systems, the two following conditions should be
met. First, all elements of the converter must be integrated atleast in a package. Second, the implementation cost per one
voltage domain must be minimized while maintaining highpower efficiency.
To maximize the power efficiency, the power loss must be
minimized. The major components of power loss are classified
into three parts: dynamic switching loss of the switching transistors, resistive loss of the switching transistors, and the resistive
loss of the inductor. The total power loss is minimized under thecondition that the previous three parts are equal and is given by
the following expressions [5]:
(1)
where
(2)
(3)

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is the duty cycle whereandare theinput and output voltages, which is not a design parameter but issignifies the output current,,
given by the specification,,, anddenote effective conduction resistances andswitched capacitances of pMOS (high-side) and nMOS (loware the filter inducside) switching transistors, and andtance and its parasitic series resistance. For planar inductors, theis fixed and given by the technology. The thicker
maximumis.
the metal layer is, the smaller the maximum
and larger
are better
As seen from (1), smaller
is shown to be roughly
for higher power efficiency.
proportional to the product of effective conduction resistanceand effective switched capacitance
per unit gate width
is expressed as,of switching transistors. Here,andindicate the gate and junction capacitance
where
per unit width. As technology scales,
andscale asand, wheredenotes the scaling factor [6].
doubles when the technology scales down by half. Therefore,
it is better from the power-efficiency point of view to use themore advanced technology.
can be lower
One may argue, however, that the maximum
in the case of transistors with the smallest linewidth. Whenis higher than the maximum
for a certain technology, theswitching transistors must be cascaded to relax the voltage overincreases by a factor
stress. If two transistors are cascaded,decreases by a factor of 0.4 [5]. As a result, evenof 1.2 anddecreases as
though we have to use a cascaded structure,technology scales. Thus, it can be said that it would be better to
use the most scaled transistors for high conversion efficiency.
is mainly determined by the thickOn the other hand,ness of the metal wire, as described previously, and its dependence on process technology is small. Thus, the inductor is notnecessarily fabricated by using the most advanced technology,
which is expensive. In addition to the inductor, the fabrication
cost of on-chip MOS capacitor per unit capacitance increases
as technology scales. Thus, it is reasonable to implement active elements and output filter on a separate die whose process
technologies are different. Fig. 3 shows the basic concept of
the stacked-chip implementation of a buck converter. The lower
chip fabricated in the advanced technology contains the controller and switching transistors of a buck converter and target
circuits. The upper chip fabricated in conventional and cheap
process technology contains LC filter elements such as ’s and’s. By stacking two chips face to face and connecting them
via metal bumps, a buck converter for on-chip distributed power
supply systems can be fabricated in a well-balanced manner forbest cost and power tradeoff.
III. TEST CHIP DESIGN
A. Circuit Topology
To demonstrate the feasibility of the stacked-chip buck converter, an on-chip buck converter is designed in 0.35- m CMOS
for upper and lower chips. The lower chip could be manufactured by 90 nm or more advanced technology for the higher
efficiency, but this test chip is to show the feasibility of thestacked-chip approach. Fig. 4 shows the circuit diagram of the2406

Fig. 3. Basic concept of stacked-chip implementation of on-chip buckconverter.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 11, NOVEMBER 2007

Fig. 5.  dependence on d =dfor square inductor.

Fig. 4. Test circuit diagram of stacked-chip implementation of buck converter.
Fig. 6. Estimated power efficiency dependence on load current and switchingfrequency.

buck converter. Parameters are optimized for the power efficiency as described hereinbelow. Drivabilities of the taperedbuffers are set high enough and the inverter sizes are calculated
to minimize the on–on overlap time of switching transistors. The,
outer diameter of the filter equals that of the filter inductor
which is set at 2 2 mm by assuming that a 10 mm chipcan have 25 voltage domains. A 6.8 6.9 mm chip with sevendegrades asvoltage domains has already been presented [7].
the outer diameter of the inductor shrinks, however, the power
decreases as techefficiency can be kept high because
nology scales. The inductance is estimated by a simple formulafrom [8]. Narrow metal-to-metal spacing and a wide metal wire
are preferable in this application. is a function of theratio, which can be calculated using the inductance formula andthe sheet resistance. The inductance and the parasitic resistancefor a fixedratio, whereare roughly proportional tois the number of turns, considering that the space is negligibly
curve
narrow compared with the line width. The normalized
in Fig. 5 is therefore independent of . From the calculation reis decided to be about. Here, is decided as
sult,
3 to maximize the power efficiency. As a result, the calculated
inductance of this work is 22 nH when the sheet resistance is. The open space at the center of the inductor isabout 0.02
filled with a MOS capacitor for the output filter. Area efficiency
is more important than linearity for the filter capacitor, because
the output voltage does not change dynamically in normal operation. From that aspect, the MOS capacitor is more suitable thanany other types of on-chip capacitors like metal–insulator–metal(MIM) capacitor or polysilicon capacitor. The obtained capacitance is about 1 nF. Under those conditions, the power efficiency
dependence on the output current and the switching frequency
V and
V is plotted in Fig. 6 by modfor
is redefined in thisifying the duty cycle definition in [11].
study as follows to take the voltage drop caused by the filter inin
ductor into account, when it is simply set as[11]; by doing so, the estimation accuracy of several values is
improved:(4)
Here,denotes the load current which equals the dc part ofthe inductor current.
The output voltage ripple ratio is described as follows whenand denote switching frequency and output filter capacitance, respectively:(5)
It is impossible to choose a switching frequency under
100 MHz in this case because the output voltage ripple goesup above 10% for the chosen values. The gate width of thehigh-side and low-side transistors are designed to be 1000
and 500 m, respectively, under the load current condition of
60 mA using the optimum gate-width formulas in [11].

ONIZUKA et al.: STACKED-CHIP IMPLEMENTATION OF ON-CHIP BUCK CONVERTER

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Fig. 9. Cross-sectional diagram of the measurement setup.

Fig. 7. Chip microphotograph of the output filter.

Fig. 10. Output voltage waveform for V= 1:86 V and I = 60 mA.

Fig. 8. Measurement setup of the test chip.

B. Simulation and Measurement Results
The test buck converter with the stacked-chip implementation
was fabricated and measured. Fig. 7 shows the chip microphotograph of the output filter on the upper chip. Figs. 8 and 9 show
the measurement setup and its cross-sectional diagram. The padsize and the effective bump diameter of this experimental setup
m and 150 m, respectively. Micro bumps witharediameter 30 m and whose resistance is as low as 14 m bumphave been realized in industry environments [14] and can beused instead for further smaller area. The output waveform in
V at
mA. The measured
Fig. 10 shows
voltage ripple is smaller than 10%, which is comparable to theresult of the more expensive solution in [2]. Fig. 11 shows thesimulated and measured power efficiency withV
for an output current range from 20 to 70 mA. The maximum
efficiency of 62% is achieved for 70 mA output current. The
measurement results compare well with the HSPICE simulation
results. The simulation considers all of the parasitic elements,
including the inductor parasitic resistance of 2.5 and the inductor input-to-ground capacitance of 25 pF.

Fig. 11. Simulated and measured power efficiency for V

200 MHz.

= 2:3 V and f =IV. IMPLEMENTING FILTER INDUCTOR ON GLASSEPOXY INTERPOSER
In order to further increase the efficiency, it is effective to use
is higher than that of the previous inducinductors whose
tors. A thin-film inductor surrounded by magnetic core material
as proposed in [15] can be a solution but is expensive. Implementing the inductor on a glass epoxy interposer as shown in
Fig. 12 is an effective yet inexpensive solution. The thickness ofthe metal wire on an interposer is generally thicker than 10 m,
and the inductor on the interposer shows a much lower resistance than that on a silicon chip, where the metal thickness is
usually less than 1 m. A capacitor on the upper chip made witha conventional technology is connected to the lower chip manufactured by an advanced technology like 90 nm CMOS, throughthe through-hole vias in the interposer. By this implementation,

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 11, NOVEMBER 2007

Fig. 14. Cross-sectional diagram of the measurement setup.
Fig. 12. Another stacked-chip implementation to gain high  .

Fig. 15. Measured
implementations.

Fig. 13. Manufactured inductor array on glass epoxy interposer.

high efficiency and low cost are achieved at the same time. The
maximum power efficiency is derived as follows from (1):

(6)
Here,
indicates the output power. is a function ofand and can be a constant when the process technology
directly results inand are fixed. Therefore, simply higher
higher power efficiency.
The structure shown in Fig. 12 is assembled using a newly
introduced interposer and the same lower and upper chips presented in Section III. In this implementation, only a capacitor
is used on the upper chip. Fig. 13 shows an inductor arrayon generic Flame Resistant 4 (FR-4) glass epoxy interposerwith two metal layers. The circled inductor in the array, which
achieved the minimum metal spacing in the trial manufacture, is used for the measurement. The metal thickness on
the interposer is 30 m, the substrate thickness is 100 m,
and the dia-meter of the through-hole via is 100 m. Thisby 30 times compared with theimplementation increases
case of an on-chip inductor. The outer diameter of the inductor

efficiency

comparison

between

two

types

of

is increased by 10% to achieve the same value of on-chip filter
inductance because the minimum spacing of metal lands on
glass epoxy is larger than that of on-chip interconnects. The
permittivity of the glass epoxy is generally more than four times
higher than SiO , however, the parasitic capacitance between
both sides of the interposer can be negligible. This is because
the substrate thickness is sufficiently large compared with theline width. Fig. 14 shows the cross section of the stacked chips.
Fig. 15 shows the comparison of measured power efficiency
between two types of implementations of “two chips” and “twoV andV. Thechips + interposer” forpower efficiency with the glass epoxy inductor is improved by
5%–14% depending on the output current compared with the
on-chip implementation. The maximum power efficiency of
71.3% is achieved at an output current of 60 mA. The possible
reason that the efficiency does not improve the most at 60 mA
is that the switching transistors are not changed optimallycharacteristic of the newly implemented
according to the
inductor.
V. CONCLUSION
An on-chip buck converter with stacked-chip implementationthat is suitable for low-cost low-power distributed power supply
systems has been designed and fabricated for the first time. The
switching frequency is optimized and chosen to be 200 MHz.
A power efficiency of 62% is measured for an output current of
70 mA, which verifies the feasibility of this approach. By utilizing a glass epoxy interposer for a filter inductor, it is shown by
experiment that the power efficiency can be increased to 71.3%.

ONIZUKA et al.: STACKED-CHIP IMPLEMENTATION OF ON-CHIP BUCK CONVERTERACKNOWLEDGMENT
The authors would like to thank K. Osada, Hitachi, Ltd., and
S. Borkar, R. Krishnamurthy, S. Hsu, T. Karnik, and G. Schrom,Intel laboratories, for valuable discussions. The chip fabrication
was supported by VLSI Design and Education Center (VDEC),
University of Tokyo, with collaboration by Synopsys, Rohm
Corporation, and Toppan Printing Corporation.

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Kohei Onizuka (S’03) received the B.S. degree in
information and communication engineering and the
M.S. degree in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2003 and 2005, respectively. He is currently working toward the Ph.D.
degree at the University of Tokyo.
His research interests include high-speed
V -hopping, on-chip dc–dc converters, andchip-to-chip wireless power transmission for SiP
applications.

REFERENCES[1] The International Technology Roadmap for Semiconductors
2005 [Online]. Available: http://www.itrs.net/Common/2005ITRS/
Home2005.htm[2] P. Hazucha, G. Schrom, J.-H. Hahn, B. Bloechel, P. Hack, G. Dermer,
S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borker, “A 233MHz, 80%–87% efficient four-phase DC-DC converter utilizing aircore inductors on package,” IEEE J. Solid-State Circuits, vol. 40, no.
4, pp. 838–845, Apr. 2005.
[3] S. Abedinpour, B. Bakkaloglu, and S. Kiaei, “A multi-stage interleaved
synchronous buck converter with integrated output filter in a 0.18 m
SiGe process,” in IEEE ISSCC Dig. Tech, Papers, 2006, pp. 356–357.
[4] M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, and P. Palmer,“A 3 GHz switching DC-DC converter using clock-tree charge-recycling in 90 nm CMOS with integrated output filter,” in IEEE ISSCC
Dig. Tech. Papers, 2007, pp. 532–5533.
[5] G. Schrom, P. Hazucha, F. Paillet, D. S. Gardner, S. T. Moon, and T.
Karnik, “Optimal design of monolithic integrated DC-DC converters,”
in Proc. IEEE Int. Conf. IC Design Technology, 2006, pp. 65–67.
[6] T. Sakurai and R. Newton, “Alpha-power law MOSFET model andits applications to CMOS inverter delay and other formulas,” IEEE J.
Solid-State Circuits, vol. 25, no. 2, pp. 584–594, Feb. 1990.
[7] G. Uvieghara, M.-C. Kuo, J. Arceo, J. Cheung, J. Lee, X. Niu,
R. Sankuratri, M. Severson, O. Arias, Y. Chang, S. King, K.-C.
Lai, Y. Tian, S. Varadarajan, J. Wang, K. Yen, L. Yuan, N. Chen,
D. Hsu, D. Lisk, S. Khan, A. Fahim, C.-L. Wang, J. Dejaco, Z.
Mansour, and M. Sani, “A highly-integrated 3G CDMA2000 1X
cellular baseband chip with GSM/AMPS/GPS/Bluetooth/Multimedia
capabilities and ZIF RF support,” in IEEE ISSCC Dig. Tech. Papers,
2004, pp. 422–536.
[8] S. S. Mohan, M. del Mar Hershenson, S. P. Boyd, and T. H. Lee,
“Simple accurate expressions for planar spriral inductors,” IEEE J.
Solid-State Circuits, vol. 34, no. 10, pp. 1419–1424, Oct. 1999.
[9] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Efficiency
analysis of a high frequency buck converter for on-chip integration withmicroprocessor,” in Proc. Eur. Solid-State Circuits Conf.,
a dual-V
Sep. 2002, pp. 743–746.
[10] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Monolithic DC-DC converter analysis and MOSFET gate voltage optimization,” in Proc. 4th Int. Symp. Quality Electronic Design, Mar. 2003, pp.
279–284.
[11] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Analysis
of buck converters for on-chip integration with a dual supply voltage
microprocessor,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,
vol. 11, no. 3, pp. 514–522, Jun. 2003.
[12] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Lowvoltage-swing monolithic dc-dc conversion,” IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 51, no. 5, pp. 241–248, May 2004.
[13] G. Schrom, P. Hazucha, J. Hahn, D. S. Gardner, B. A. Bloechel, G.
Dermer, S. G. Narendra, T. Karnik, and V. De, “A 480-MHz, multiphase interleaved buck DC-DC converter with hysteretic control,” inProc. 35th Annu. IEEE Power Electronics Specialists Conf., Jun. 2004,
pp. 4702–4707.
[14] T. Ezaki, K. Kondo, H. Ozaki, N. Sasaki, H. Yonernura, M. Kitano,S. Tanaka, and T. Hirayarna, “A 160 Gb/s interface design configuration for multichip LSI,” in IEEE ISSCC Dig. Tech. Papers, 2004, pp.
140–141.
[15] G. Schrom, P. Hazucha, J.-H. Hahn, V. Kursun, D. Gardner, S.
Narendra, T. Karnik, and V. De, “Feasibility of monolithic and
3D-stacked DC-DC converters for mircoprocessors in 90 nm technology generation,” in Proc. ISLPED, 2004, pp. 263–268.

Kenichi Inagaki (M’00) received the B.S. and M.S.
degrees in earth and planetary sciences from theTokyo Institute of Technology, Tokyo, Japan, in
1997 and 1999, respectively.
Since 1999, he has been a Technical Associate with
the University of Tokyo, Tokyo. His current work isin the area of analysis of signal and power integrity
on VLSI circuits.

Hiroshi Kawaguchi (M’98) received the B.E. and
M.E. degrees in electronic engineering from Chiba
University, Chiba, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in engineering from the
University of Tokyo, Tokyo, Japan, in 2006.
He joined Konami Corporation, Kobe, Japan, in
1993, where he developed arcade entertainment systems. He moved to the Institute of Industrial Science,
University of Tokyo, as a Technical Associate in 1996
and was appointed a Research Associate in 2003. In
2005, he moved to the Department of Computer and
Systems Engineering, Kobe University, Kobe, Japan, as a Research Associate.
Since 2007, he has been an Associate Professor with the Department of Computer Science and Systems Engineering, Kobe University. He is also a Collaborative Researcher with the Institute of Industrial Science, University of Tokyo.
His current research interests include low-power VLSI design, hardware design
for wireless sensor network, and recognition processor.
Dr. Kawaguchi is a member of Association of Computing Machinery. He wasa recipient of the IEEE ISSCC 2004 Takuo Sugano Outstanding Paper Awardand the IEEE Kansai Section 2006 Gold Award. He has served as a Program
Committee Member for the IEEE Symposium on Low-Power and High-Speed
Chips (COOL Chips) and as a Guest Associate Editor of IEICE Transactions
on Fundamentals of Electronics, Communications and Computer Sciences.

Makoto Takamiya (S’98-M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Tokyo, in 1995, 1997,
and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high-peed
digital LSIs and developed the field of on-chip measurement macros to solve the power in-tegrity issues.
In 2005, he joined University of Tokyo, where he isan Associate Professor of VLSI Design and Education Center. His research interests include power andsignal integrity issues, low-power RF integrated circuits, and large-rea electronics with organic transistors.

2410IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 11, NOVEMBER 2007

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan, in 1981.
In 1981, he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and SoC solutions. He has worked extensively
on interconnect delay and capacitance modelingknown as the Sakurai model and alpha power-law
MOS model. From 1988 through 1990, he was a Visiting Researcher with the University of California,
Berkeley, where he conducted research in the field of
VLSI CAD. Since 1996, he has been a Professor wit the University of Tokyo,
working on low-power high-speed VLSI, memory design, interconnects,

ubiquitous electronics, organic ICs and large-area electronics. He has publishedmore than 350 technical publications, including 70 invited publications andseveral books, and has filed more than 100 patents. He served as a conference
chair for the Symposium on VLSI Circuits and ICICDT, a vice chair for
ASPDAC, a TPC chair for the first A-SSCC, and VLSI Symposium, and a
program committee member for ISSCC, CICC, DAC, ESSCIRC, ICCAD,FPGA Workshop, ISLPED, TAU, and other international conferences. He is aplenary speaker for the 2003 ISSCC.
Dr. Sakurai is a STARC Fellow, an elected AdCom member for the IEEE
Solid-State Circuits Society, and an IEEE Circuits and System Society
Distinguished Lecturer. He was a recipient of te 2005 IEEE ICICDT Award, te
2005 IEEE ISSCC Takuo Sugano Award, and te 2005 P&I Patent of the YearAward.