Automatic Generation of Gate Driving Vectors for
Digital Gate Drivers to Satisfy EMI Regulations
Ryuzo Morikawa, Toru Sai, Katsuhiro Hata, and Makoto Takamiya
The University of Tokyo, Tokyo, Japanrmori@iis.u-tokyo.ac.jp

I. INTRODUCTION

II. PROPOSED AUTOMATIC GENERATION METHOD OF GATEDRIVING VECTORS (AGGV)
The measurement setup and the gate waveform
optimization method for DGD are the same as [9] except for
the length of the gate driving vector for DGD, time step of
DGD, and the object function for the optimization. Fig. 1
shows a circuit schematic of the measurement setup for thedouble pulse test of IGBT (2MBI100TA-060-50, 600 V, 100A) at 300 V. In order to realize a programmable 63-level
drivability in DGD, 63 parallel transistors are connected to thegate of IGBT and a 6-bit control signal is applied to specify
300VControl signals:
nNMOS and nPMOSILOADIn the development process of power electronics
equipment, the electromagnetic interference (EMI) is atroublesome problem, because the EMI measurement tocheck pass or fail the EMI regulations is done after the final
product of the power electronics equipment is completed.
When the product fails the EMI regulations, two types ofmeasures, hardware-based approach and software-based
approach, are considered. In the hardware-based approach,several components including EMI filters and shield plates
are added to reduce EMI, which will increase the cost anddelay the product development schedule. Therefore, thesoftware-based approach, where the EMI spectrum is tuned
using a programmable hardware, is preferred, because it ischeaper and faster than the hardware-based approach.

978-1-7281-5826-6/20/$31.00 ©2020 IEEE

63 PMOSs
ICVCEVGE
63 NMOSs

IGBT moduleDigital gate driver ICFig. 1. Circuit schematic of measurement setup.
n1n2‥‥

n8 630tVGE

nNMOS

A programmable gate driver, which controls a gatedriving waveform of power transistors during turn-on / offtransients, is a promising candidate for the programmablehardware for the software-based approach. In order to checkpass or fail of the EMI regulations, the frequency-domain
evaluation instead of the time-domain evaluation is required,because the EMI regulations are defined in the frequencydomain. All previously reported programmable gate drivers[1-7], however, use the time-domain evaluation such as
dVCE/dt and d2VCE/dt2, where VCE is collector-to-emitter
voltage of IGBT, to control the gate driving waveforms. Inthe reduction of EMI, the switching loss (ELOSS) is also
should be considered, because EMI and ELOSS are in a tradeoff relationship [3].
To solve the problems, in this paper, an automatic
generation method of gate driving vectors (AGGV) for thedigital gate driver (DGD) IC [8] based on the frequencydomain evaluation of VCE is proposed for the first time. InAGGV, the gate driving vectors are automatically searched

15VnNMOS

Keywords—Gate driver, IGBT, EMI, Optimization

using a simulated annealing algorithm to meet the given EMI
regulation and to minimize the switching loss, thereby
achieving a highly efficient power electronics equipment
complying with EMI regulations.

ICt
VOVERSHOOTVCE
TSTEP = 200ns
8 time-segments
(a)

n0t

VGE

Abstract— To reduce the development period of powerelectronics equipment to satisfy EMI regulations, an automatic
generation method of gate driving vectors (AGGV) for thedigital gate drivers is proposed. In the proposed AGGV, thefrequency spectrum of the VCE waveform of IGBT is comparedwith the EMI limit and the gate driving vectors areautomatically searched using a simulated annealing algorithm
to meet the EMI limit and to minimize the switching loss. In theswitching measurement of IGBT at 20 A and 300 V and a given
EMI limit, compared with the conventional single step gate
driving, the proposed digital gate driving reduces the switchingloss by 22 %. An EMI reduction using the proposed digital gate
driving, which cannot be achieved by the conventional single
step gate driving, is also demonstrated.

tVOVERSHOOTICVCEtt(b)Fig. 2. Gate driving vectors and waveforms. (a) Proposed 6-bit
digital gate driver. (b) conventional single-step gate drive forcomparison.

4931

Double pulse test
6 μs

VCE (V)VGE (V)

MergedFliphorizontal

Time

・・・

Repeated
m times

FFTm cycles

VCE spectral amplitude [dBμV]

Extracted

AEXCESSEMI limit
Frequency [MHz](a)400350350

VCE (V)

300
300
250
250
200
200
150
150
100
100505000-50-50005050100100200200150150Time (μs)(b)Fig. 3. (a) Method to obtain spectrum from VCE waveform for the frequency-domain evaluation of VCE. AEXCESS is area shown yellow. (b)Example of repetitive waveform made from measured VCE waveform in Fig. 8 (b).

the number of activated PMOS (NMOS) transistors, nPMOS(nNMOS) [8]. In this paper, only turn-off is shown forsimplicity. Fig. 2 (a) shows the gate driving vectors andwaveforms in the 6-bit DGD for the turn-off of IGBT. In thispaper, the gate driving vectors are defined as (n1, n2, n3,…,n8) , where n1, n2, and n8 are integers from 0 to 63. In thispaper, eight 200-ns time steps for turn-off are used, because
four 400-ns time steps in [9] were not enough. Fig. 2 (b)shows the gate driving vectors and waveforms of theconventional single-step gate drive for comparison.

repetitive waveform. In order to check pass or fail of the EMI
regulations, a spectrum area (AEXCESS), where the VCE
spectrum exceeds an EMI limit, is defined as shown in Fig.
3 (a) and Eqs. (1) to (4). AEXCESS is the area shown yellow in
Fig. 3 (a) and setting AEXCESS to zero means that VCE
spectrum satisfies the EMI regulation.

Fig. 3 (a) shows a method to obtain a spectrum from VCE
waveform obtained in the double pulse test for thefrequency-domain evaluation of VCE. First, a VCE rise edge
waveform during turn-off is extracted from the double pulse
test, and it is flipped horizontally to make the fall edge
waveform. Then, the rise and fall edge waveforms aremerged and repeated m times (e.g. m = 20) to make arepetitive waveform. Fig. 3 (b) shows an example of therepetitive waveform made from the measured VCE waveformin Fig. 8 (b). Finally, a spectrum is obtained by FFT of the4932

AEXCESS = FEND

FSTART max(VACE ,VAEMI ) − VAEMI 
dF
VAEMI

(1)

 f

F = log10  1[ MHz ] 

(2)

 f

FSTART = log10  START  1[ MHz ] 
(3)

 f

FEND = log10  END  1[ MHz ] (4)VCE spectral amplitude [dBμV]

where VACE is the spectrum amplitude of VCE in units ofdBμV, VAEMI is the spectrum amplitude of the EMI
regulation in units of dBμV, and f is the frequency. fSTARTand fEND are the lower and upper limit frequency of the EMI
regulation, respectively. In this paper, fSTART is 1 MHz andfEND is 20 MHz. Object function (fOBJ) to be minimized in theoptimization using the simulated annealing algorithm [8-9]is defined as2

 ELOSS (5)f OBJ = C1 ⋅ AEXCESS + E
 LOSS,MAX 
where C1 is a constant (C1 = 10000) and ELOSS,MAX is themaximum ELOSS. In the optimization, the large C1 means thatthe first priority is to meet the given EMI regulation and thesecond priority is to minimize the switching loss. Comparedwith [9], only the definition of fOBJ is changed and theoptimization algorithm is the same. In the proposed AGGV,
the gate driving vectors (n1, n2, n3,…, n8) are globally andautomatically optimized by repeating the double pulse test
around 4000 times using LabVIEW and MATLAB, whichtakes 20 to 40 minutes.

160
160
140140EMI limit A

120
120
100100EMI limit B

8080
6060
4040
1010234518 101020

Frequency [MHz]Fig. 5. Two types of virtual EMI regulations named “EMI limit A”
and “EMI limit B”.
1.2
1.2

n=5

1.01

ELOSS [mJ]Fig. 4 shows the photo of the measurement setup. The
load current is 20 A. The double pulse test measurements
were made at room temperature.
III. MEASURED RESULTS
In this paper, two types of virtual EMI regulations named“EMI limit A” and “EMI limit B” defined in Fig. 5 are used
to demonstrate the generality of the proposed AGGV. In“EMI limit A”, the spectrum amplitude of VCE is 150 dBμV
between 1 MHz and 5 MHz, while the spectrum amplitudeof VCE is 110 dBμV between 5 MHz and 20 MHz. In “EMIlimit B”, the spectrum amplitude of VCE is 150 dBμV
between 1 MHz and 8 MHz, while the spectrum amplitudeof VCE is 80 dBμV between 8 MHz and 20 MHz. In this paper,
the relationship between EMI and ELOSS is analyzed in details,
because EMI and ELOSS are in a trade-off relationship [3].

n=80.80.8−22%0.60.6Conv. single-step

0.4
0.4

Proposed(Fig. 8 (d))

0.20.20000

120.002n = 6340.004

360.006

57

AEXCESS in EMI limit A [a.u.](a)Figs. 6 (a) and (b) show the measured ELOSS vs. AEXCESSof the conventional single-step gate drive in Fig. 2 (b) withvaried n from 5 (minimum in this paper) to 63 (maximum)
and the proposed gate drive in Fig. 2 (a) optimized for “EMIlimit A” and “EMI limit B”, respectively. AEXCESS of zeromeans that the VCE waveform meets the given EMI
regulation, while non-zero AEXCESS means that the VCE
waveform violates the given EMI regulation. In theconventional single-step gate drive in Fig. 6 (a), when n is

1.2
1.2

n=5

ELOSS [mJ]

1.01

Proposed(Fig. 8 (e))

0.8
0.8

0.6
0.6

Conv. single-step

0.4
0.4

n = 63

0.2
0.2

0000

0.005
0.005

0.01
0.01

0.015
0.015

0.02
0.02

AEXCESS in EMI limit B [a.u.](b)Fig. 4. Photo of measurement setup.

Fig. 6. Measured ELOSS vs. AEXCESS of conventional single-step gate
drive in Fig. 2 (b) with varied n from 5 (minimum in this paper) to63 (maximum) and the proposed gate drive in Fig. 2 (a) optimizedfor (a) “EMI limit A” and (b) “EMI limit B”.

4933

VCE spectral amplitude [dBμV]

VCE spectral amplitude [dBμV]

160

EMI limit A
140

Conv. single-step(n=63) (Fig. 8 (c))

Proposed120

ELOSS : 0.65 mJ(Fig. 8 (d))

100Conv. single-step (n=8)
ELOSS : 0.83 mJ(Fig. 8 (b))

80
60
40

2134

510160120

Conv.
single-step(n=63)(Fig. 8 (c))

Proposed(Fig. 8 (e))

100

20

Frequency [MHz]EMI limit B

140

Conv. single-step (n=5)(Fig. 8 (a))

80
60
40

123(a)

VCE spectral amplitude [dBμV]

45

810

Frequency [MHz]

20(b)

160
160

140
140

Proposed (EMI limit A)
ELOSS : 0.65 mJ(Fig. 8 (d))

120
120

Conv. single-step (n=63)
ELOSS : 0.36 mJ(Fig. 8 (c))

100
100

8080
6060
4040
1010Conv. single-step (n=5)
ELOSS : 1.24 mJ(Fig. 8 (a))

EMI limit A
EMI limit B

Conv. single-step (n=8)
ELOSS : 0.83 mJ(Fig. 8 (b))
Proposed (EMI limit B)
ELOSS : 0.78 mJ(Fig. 8 (e))

2345Frequency [MHz]101
1020(c)Fig. 7. (a) Measured spectrums of VCE in conventional single-step gate drive with n = 8 and 63 and proposed gate drive optimized for “EMIlimit A”. (b) Measured spectrums of VCE in conventional single-step gate drive with n = 5 and 63 and proposed gate drive optimized for“EMI limit B”. (c) Superimposed graph of (a) and (b).

increased from 5 to 63, AEXCESS is increased and ELOSS isreduced, which clearly shows the trade-off relationshipbetween EMI and ELOSS. In Fig. 6 (a), both the conventional
single-step gate drive with varied n from 5 to 8 and the

proposed gate drive meets “EMI limit A”. In Fig. 6 (b),however, only the proposed gate drive meets “EMI limit B”.
Fig. 7 (a) shows the measured spectrums of VCE in theconventional single-step gate drive with n = 8 and 63 and the4934

ELOSS : 1.24 mJ

Vce (V)

VGE:5 V/div

Vce (V)
Vge (V), Ic(A)IC:5 A/div

Vce (V)
Vge (V), Ic(A)IC:5 A/div

VGE:5 V/div

VCE:50 V/div

058Time(a)63nNMOSnNMOS

0nNMOS

IC:5 A/div

VGE:5 V/div

00Time(b)

(c)

Time

ELOSS : 0.78 mJ

ELOSS : 0.65 mJ
200 ns/div

200 ns/div

VCE:50 V/div

VCE:50 V/div
Vge (V), Ic(A)IC:5 A/div

Vce (V)
Vge (V), Ic(A)Vce (V)

200 ns/div

200 ns/div
VCE:50 V/div

Vge (V), Ic(A)

200 ns/div
VCE:50 V/div

IC:5 A/div

ELOSS : 0.36 mJ

ELOSS : 0.83 mJ

VGE:5 V/div

VGE:5 V/div
0052
19061 63
169 10200 ns63

90Time(d)636359nNMOSnNMOS

6337 3026

151200 ns

Time(e)Fig. 8. Gate driving vectors and measured waveforms of VGE, VCE, and IC. (a) - (c) show conventional single-step gate drives with n = 5, 8,63, respectively. (d) and (e) show proposed gate drives optimized for “EMI limit A” and “EMI limit B”, respectively.

1.2
1.2

n=5Conv.
single-stepELOSS [mJ]

1.01

A”. Fig. 7 (b) shows the measured spectrums of VCE in theconventional single-step gate drive with n = 5 and 63 and the
proposed gate drive optimized for “EMI limit B”. Fig. 7 (c)is the superimposed graph of Figs. 7 (a) and (b). In theconventional single-step gate drive, the high-frequency
components of VCE increases with increasing n.

n=80.80.8Figs. 8 (a) - (c) show the gate driving vectors and themeasured waveforms of VGE, VCE, and IC in the conventional
single-step gate drive with n = 5, 8, 63, respectively. Figs. 8(d) and (e) show the gate driving vectors and the measured
waveforms of VGE, VCE, and IC in the proposed gate drive
optimized for “EMI limit A” and “EMI limit B”,respectively.

Proposed(EMI limit B)
Proposed(EMI limit A)

0.6
0.6

0.4
0.4

0.2
0.2

n = 63

00
0

20
20

40
40

60
60

80
80

100
100

VOVERSHOOT [V]Fig. 9. Measured ELOSS vs. VOVERSHOOT of conventional single-stepgate drive with varied n from 5 to 63 and proposed gate drive
optimized for “EMI limit A” and “EMI limit B”.

proposed gate drive optimized for “EMI limit A”. Please
note that both the conventional single-step gate drive with n= 8 and the proposed gate drive just barely satisfy “EMI limitAs shown in Fig. 6 (a), in the conventional single-stepgate drive, when n is increased from 5 to 8, ELOSS is reducedwith satisfying “EMI limit A”. In contrast, when n isincreased above 9, the conventional single-step gate drive
violates “EMI limit A”, while ELOSS is reduced. As shown inFig. 6 (a) and Fig. 7 (a), compared with the conventional
single-step gate drive with n = 8 shown in Fig. 8 (b), theproposed digital gate driving shown in Fig. 8 (d) reduces theswitching loss by 22 % with satisfying “EMI limit A”.
As shown in Fig. 6 (b) and Fig. 7 (b), all conventional
single-step gate drives with varied n from 5 to 63 cannot

4935

meet “EMI limit B”, while the proposed driving shown inFig. 8 (e) satisfies “EMI limit B”, which clearly shows theadvantage of DGD.
The relationship between ELOSS and VOVERSHOOT is also
analyzed in details, because ELOSS and VOVERSHOOT are in a
trade-off relationship [9]. VOVERSHOOT is defined in Fig. 2. Fig.
9 shows the measured ELOSS vs. VOVERSHOOT of theconventional single-step gate drive with varied n from 5 to63 and the proposed gate drive optimized for “EMI limit A”
and “EMI limit B”. As shown in Fig. 9, compared with theproposed gate drive optimized for “EMI limit A” shown inFig. 8 (d), the proposed gate drive optimized for “EMI limit
B” shown in Fig. 8 (e) reduces VOVERSHOOT from 89 V to 35
V, while ELOSS is increased by 20 % from 0.65 mJ to 0.78
mJ. The reason for the reduction of VOVERSHOOT in Fig. 8 (e)is estimated to be n4 = 1, which suggests that the transient
small gate driving current during the overshoot of VCE
reduces VOVERSHOOT.
IV. CONCLUSIONSREFERENCES
[1]

[2]

[3]

[4]

[5]

[6]

AGGV is proposed to reduce the development period ofpower electronic equipment to satisfy EMI regulations. In
AGGV, the gate driving vectors are automatically searchedto meet the given EMI regulation and to minimize theswitching loss. In the switching measurement of IGBT at 20
A and 300 V and the given EMI limit, compared with theconventional single step gate driving, the proposed digital
gate driving reduces the switching loss by 22 %. An EMI
reduction using AGGV, which cannot be achieved by theconventional single step gate driving, is also demonstrated.

[7]

[8]

[9]4936

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