12.7-times Energy Efficiency Increase of 16-bit Integer Unit
by Power Supply Voltage (VDD) Scaling from 1.2V to 310mV
Enabled by Contention-less Flip-Flops (CLFF) and Separated
VDD between Flip-Flops and Combinational Logics
Hiroshi Fuketa1, Koji Hirairi2, Tadashi Yasufuku1, Makoto Takamiya1,
Masahiro Nomura2, Hirofumi Shinohara2, Takayasu Sakurai1
1Institute of Industrial Science, University of Tokyo, Japan
Semiconductor Technology Academic Research Center (STARC), Japan
E-mail: {fuketa, tdsh, mtaka, tsakurai}@iis.u-tokyo.ac.jp, {hirairi.koji, nomura.masahiro, shinohara.hirofumi}@starc.or.jp
2

In this paper, contention-less flip-flops (CLFF) andseparated VDD between flip-flops (FF’s) and combinational
logics are proposed in order to realize MEEO in LP CMOS.
The proposed technologies are applied to a 16-bit integer unit
(IU) for media processing, and the highest EEIF of 12.7 isachieved by reducing VDD from 1.2V to 310mV.

Abstract— Contention-less flip-flops (CLFF’s) and separated
power supply voltages (VDD) between flip-flops (FF’s) andcombinational logics are proposed to achieve a maximum energy
efficiency operation. The proposed technologies were applied to a
16-bit integer unit (IU) for media processing in a 65-nm CMOS
process. Measurement results of fabricated chips show that the
proposed CLFF reduces the minimum operating voltage of IU’s
by 64mV on average. By scaling VDD from 1.2V to 310mV withthe proposed CLFF, the maximum energy efficiency of1835GOPS/W and the highest energy efficiency increase of 12.7
times are achieved.

The remainder of this paper is organized as follows. Section
II describes the structure of the developed IU and the proposed
CLFF. Measurement results are shown in Section III. Finally,
Section IV concludes this paper.

Keywords -flip-flop, subthreshold circuit, variationsI.

INTEGER UNIT (IU) AND CONTENTION-LESS FLIP-FLOP(CLFF)II.

INTRODUCTION

A. Integer Unit (IU)
Fig. 2 shows a block diagram of the developed 16-bit IU
which has implemented popular media processing commands
as shown. In this paper, (1) the proposed CLFF and (2)separated VDD between the combinational logic (VDD(LOGIC))
and the FF’s (VDD(FF)) are implemented in IU. Two types of
IU’s with the conventional FF’s and the proposed CLFF’s aredeveloped for comparison in a 65-nm CMOS process. The chip
micrograph is shown in Fig. 3. The area penalty of theseparated VDD is 6%.

Energy efficient LSI’s including media processors arestrongly required with the growing market of mobile devices
such as smart phones. A lot of sub/near-threshold logic circuits
are reported [1-5], because reducing the power supply voltage(VDD) increases the energy efficiency of the logic circuits. Low
power (LP) CMOS process with low leakage current is used for
LSI’s in the battery-powered mobile devices. LP CMOS withhigh threshold voltage (VTH), however, brings a new design
challenge for the energy efficient sub/near-threshold logic
circuits.
Fig. 1 shows simulated VDD dependence of the energy
efficiency of 31-stage fan-out-4 2NAND ring oscillators in 2
types of 65nm CMOS with VTH difference of 0.2V. Maximum
energy efficiency operation (MEEO) is achieved at VDD
between 300mV and 400mV [1-4]. In this paper, an energy
efficiency improvement factor (EEIF) is defined as the
maximum energy efficiency normalized by the energy
efficiency at nominal VDD of 1.2V. EEIF is 9.1 in the highperformance (HP) CMOS process with low VTH, which isconsistent with [1]. In contrast, EEIF of LP CMOS is 11.4,
which is higher than that of HP CMOS. Minimum operating
voltage (VDDmin) of LP CMOS, however, is higher than that of
HP CMOS, because VDDmin increases with increasing VTH. In
LP CMOS, therefore, MEEO can't be achieved, because VDDminis higher than MEEO VDD of 310mV.

978-1-61284-660-6/11/$26.00 © 2011 IEEE

Energy efficiency
normalized at 1.2V

Low power (LP) CMOS process (VTH ~ 0.4V)(This work)
VDDmin of 11.4x
HP CMOS
109.1x
12

VDDmin of LP CMOS

8High performance (HP)
CMOS process (VTH ~ 0.2V)

6
4
2
0

300mV 310mV
0

0.2

0.4

0.6

0.8

Power supply voltage (VDD) (V)

1.0

1.2

Figure 1. Simulated VDD dependence of energy efficiency of 31-stage ringoscillators in two types of 65nm CMOS with VTH difference of 0.2V.

163

(1) Contention-less flip-flop

VDDmin= 450mV(2) Separated VDD
are proposed to achieve
max energy efficiency.

VDD(LOGIC)(1.2 - 0.34V)(1.2 - 0.22V)

FF

Inputswith carry-in
17

FF

17

1-bit L/R Shifter

16

Arithmetic andlogic operation unit

16

InputsFF

Outputs
with carry-out
17

80
70

Fails at any frequencies
below 450mV

60
50
40
30

Pass

20
10
5
350

Integer unit (IU)

100

- ADD/SUB with/without saturation

90

Clock frequency (MHz)- Universal logic operation- MIN/MAX operation- Absolute difference

Figure 2. Block diagram of developed 16-bit integer unit (IU) implemented
with the proposed flip-flops and separated VDD.
100 μmFFs Combinational
logic

450

VDD(FF) = 450mV

Implemented commands
in 16-bit ALU

0.9 mm

400

500

VDD(LOGIC) = VDD(FF) (mV)

550(a) VDD(FF) is equal to VDD(LOGIC)

Combinational logic

Clock

1.2 mmFail

90

Clock frequency (MHz)VDD(FF)

100

FFs

Fail

80
70
60
50

Pass

40
30

Further VDD scaling
is possible

20
10
5

70 μm

VDD(FF) = VDD(LOGIC)

350

400

450

VDD(LOGIC) (mV)

500

550

(b) VDD(FF) and VDD(LOGIC) are separated.
Figure 3. Chip micrograph. Two types of IU’s with the conventional
FF’s and the proposed CLFF’s are implemented.

Figure 4. Measured shmoo plot of IU with the conventional flip-flops (TBFF
in Fig. 5 (a)) fabricated in 65-nm CMOS.

FF’s. Therefore, reducing VDDmin of FF’s is required to achieve
MEEO.

Fig. 4 (a) shows the measured shmoo plot of the IU with theconventional FF’s. VDD(FF) is equal to VDD(LOGIC) in Fig. 4 (a),while VDD(FF) and VDD(LOGIC) are separated in Fig. 4 (b). In Fig.
4 (a), the IU does not operate correctly below 450mV even if
the clock frequency is reduced from 35MHz to 10kHz, whichindicates that VDDmin of IU is 450mV. In this case, MEEO can
not be achieved, because MEEO VDD is less than 450mV.
VDDmin is determined by the combinational logic or the FF’s. In
Fig. 4 (b), in order to identify which circuit, the combinational
logic or the FF’s, determines VDDmin, VDD(FF) is fixed to 450mV
and only VDD(LOGIC) is reduced when VDD(LOGIC) is less than
450mV. In this case, Functional VDD(LOGIC) is reduced to
350mV, which indicates that VDDmin of IU is determined by the

B. Contention-Less Flip-Flop (CLFF)
Fig. 5 (a) shows a schematic of a conventional tri-state
buffer based FF (TBFF) used in Fig. 4. VDDmin of TBFF is high,because the outputs of the two tri-state buffers are wired-OR
and the contention between the tri-state buffers will induce
functional errors [5]. Eliminating the wired-OR in TBFF isrequired to reduce VDDmin, and a classical NAND latch based
flip-flop (NLFF) shown in Fig. 5 (b) is one of the candidates.
The number of transistors in NLFF, however, increases by 67%
compared with TBFF and the corresponding area penalty is not
acceptable.

164

Contention occurs at the point of wired-OR.
Leakage current
Drive current

MasterCK2

Slave

Master

Slave

D

D

CK2

CKB

CKB

Q

CK2
CKB

CKB

CK2

(a) Conventional tri-state buffer based FF (TBFF).

D

CK2

CK

CK

d0

(b) Classical NAND latch based flip-flop (NLFF).

d1

D

CK

N1

CKB
tCK2 t

H

CK2

CK2

CK2
tDELAY
DB
tFB

CK2

tDB

CKB

Q

CK2

FB
Master

d0

QMB

CKB

d0

FB
QMB

DB

D

d0

P1

QMB

MUST be tDB > tFB

CK

CKB

CK2

Slave

(c) Proposed contention-less flip-flops (CLFF). N1 and P1 are added to mitigate the racing problem
Figure 5. Three types of flip-flops to compare VDDmin.

In order to solve the problems, this paper proposes an areaefficient CLFF shown in Fig. 5 (c) with low VDDmin byeliminating the contention. CLFF has master-slaved latches
which are implemented with NOR-type and NAND-type 2:1
multiplexers. When CK=0, the master latch accepts the input
data (D) and the slave latch retains data of the previous cycle.
In contrast, when CK=1, the master latch retains the latest data
and the slave latch accepts it. CLFF has smaller area than
NLFF, because 8 2NAND-gates in NLFF are replaced with 6
2NOR/2NAND-gates in CLFF.

ideal case without delay variations, tDB is larger than tFB,
because tDB - tFB equals to the delay of an inverter. In contrast,
in reality with the large transistor delay variations at low VDD,
tDB may be smaller than tFB and the write-error occurs. In order
to increase tDB - tFB, tCK2 or tDELAY should be increased.
Increasing tCK2 is not a good choice, because the hold margin(tH) is decreased. Therefore, tDELAY is increased to alleviate theracing problem by adding an nMOS (N1) in the 2NOR shownin gray in Fig. 5 (c) and increasing the propagation delay fromrising CK2 to falling DB.

However, reducing the gates creates a racing problem. It is
explained in the timing chart about the master latch of CLFF in
Fig. 5 (c). After the rising edge of CK, the inverted data on DB
is written to the feedback node (FB). Therefore, tDB should belarger than tFB, because a write-error occurs if tDB < tFB. In an

In the same way, a pMOS (P1) is added in the slave latch.
N1 and P1 do not increase the switching power of CLFF,
because they are normally ON transistors. As a result,compared with TBFF, the number of the transistors, total gate
width, and the area of the proposed CLFF is 1.4x, 3.9x, and

165

10-2

10-3

6

200

300

400

VDD(FF) (mV)

500

-210mV@ 10k FF’s

2
08

10M
0.2

0.4

0.6

0.8

1.0

6

VDD(FF) = 340mV4
2
06 6 7 7 7 7 7 8 8 8
6 8 0 2 4 6 8 0 2 4

1.2

Maximum clock frequency (Hz)

Number of dies

TBFF
Avg. 444mV

-64mV

5
4
3
2

100m

1
0

y
nc
ue
q
e
Fr
r
we
po
l
a
t
To

100M

10m

1m

100μ

10M

a
Leak

1M

w
ge po

er

10μ

1μ
100k
0.2

VDDmin of IU (mV)Max frequency (MHz)VDD(FF) = VDD(LOGIC)

2G
1G: CLFF (Proposed)

280 310 340 370 400 430 460 490 520

VDD = 0.5 V

Figure 8. Measured VDD dependence of maximum clock frequency of IU's
with TBFF and CLFF, and measured die-to-die maximum clock frequency
distributions of IU's with TBFF and CLFF at 1.0V and 0.5V.

: TBFF (Conv.)

6

50 860 8 70 880 89 0 900 9 10 92 0 93 0 940

Max frequency (MHz)
100M

Figure 6. Simulated VDD(FF) dependence of error probability of single FF. In
order to compare VDDmin among various flip-flops, 3000 times Monte Carlo
SPICE simulations were performed with random VTH variations. VDDmin of the
proposed CLFF is improved compared with VDDmin of the CLFF without N1
and P1, since adding N1 and P1 alleviates the racing problem.

CLFF
Avg. 380mVVDD = 1.0 V

4

VDD(FF) = VDD(LOGIC) (V)
10-4
100

: CLFF

Power dissipation (W)

10-1

25 C

1G

# of dies

Error probability of single FF-100mV@ 50 FF’s (this work)

2G# of dies

Same total W

1: TBFF: TBFF (Conv.): CLFF (Proposed)
Max clock frequency (Hz): TBFF (Conv.): TBFF (3.9x sized): CLFF (w/o N1&P1): CLFF (Proposed)

25 C

340mV (VDDmin of CLFF)
0.4
220mV

0.6

0.8

1.0

100n
1.2

VDD(LOGIC) (V)

Figure 9. Measured VDD(LOGIC) dependence of maximum clock frequency, total
power, and leakage power of IU with CLFF. VDDmin of CLFF is 340mV.

Figure 7. Measured die-to-die VDDmin distributions of IU's with TBFF and
CLFF derived as shown in Fig. 4 (a).

proposed CLFF (with added transistors N1 and P1) is reduced
by 40mV at the error probability of 10-4 compared with VDDminof the CLFF without N1 and P1, which implies N1 and P1
mitigate the racing problem and improve the robustness to thetransistor variations.

2.8x, respectively. Compared with NLFF, the number of thetransistor of CLFF is reduced by 15%.
In order to compare VDDmin between TBFF and CLFF, Fig.
6 shows the simulated VDD(FF) dependence of the error
probability of single FF. 3000 times Monte Carlo SPICE
simulations were performed with the random VTH variations. In
order to check the effect of circuit topology of FF’s and the
newly added transistors (N1 and P1) in CLFF, TBFF with thesame total gate width as the proposed CLFF and CLFF without
N1 and P1 are also included for the comparison. Comparedwith TBFF, VDDmin of CLFF is reduced by 100mV and 210mV
at the error probability of 0.02 (= 50 FF’s which is included in
IU in Fig. 2) and 10-4 (= 10k FF’s), respectively, whichindicates the VDDmin reduction is more effective at larger scale
digital circuits. At the same total gate width, VDDmin of CLFF islower than that of TBFF, which proves the superiority of thecircuit topology of CLFF over TBFF. In addition, VDDmin of the

III.

MEASUREMENT RESULTS

Fig. 7 shows the measured die-to-die VDDmin distributionsof IU's with TBFF and CLFF derived as shown in Fig. 4 (a).
By replacing TBFF with CLFF in IU, the average VDDmin is
reduced by 64mV.
Fig. 8 illustrates the measured VDD dependence of
maximum clock frequency of IU's with TBFF and CLFF.
Measurement results of die-to-die maximum clock frequency
distributions of IU's with TBFF and CLFF at 1.0V and 0.5V
are also depicted. Fig. 8 indicates that CLFF has no speed
penalty over TBFF.

166

VDD(FF) = 340mV
FF’s

2200

Total Power

Energy efficiency (GOPS/W)

VDD(FF) = 340mV

VDD(FF) = VDD(LOGIC)

10m

Total power

1m

100μ

Leakage power

10μ

10.4x

12.7x

1800

10.0x

1600

8.7x

1400
1200
1000
800

100n

Leakage power of FF’s increases due to voltage
difference between combinational logic and FF’s
10n
0.2

0.4

340mV (VDDmin of CLFF)

0.6

0.8

1.0

Separated VDD

10.0x
Replacing
FF

1600

8.7x

Proposed

Conv.

1400
1200
0.2

0.3

0.4

VDD(LOGIC) (V)-18% @ 1.2V
CLFF with VDD(FF) = VDD(LOGIC)

0.4

0.6

0.8

1.0

1.2

Figure 10. Measured VDD(LOGIC) dependence of breakdown of total power andleakage power of IU with CLFF. IU consists of the combinational logic andFF’s as shown in Fig. 2. VDDmin of CLFF is 340mV.

Fig. 11 shows the measured VDD(LOGIC) dependence of theenergy efficiency of IU’s with TBFF and CLFF. IU with TBFF
can not achieve MEEO due to 400-mV VDDmin, and EEIF is 8.7.
By replacing TBFF with CLFF, VDDmin of CLFF is reduced to
340mV at the cost of the 18% reduction of the energy
efficiency at 1.2V, because the power consumption of CLFF islarger than that of TBFF. IU with CLFF, however, can notachieve MEEO and EEIF of 10.0 based on IU with TBFF
(176.4GOPS/W, 6.5mW, and 1.15GHz at 1.2V). In order toachieve MEEO, separated VDD(FF) and VDD(LOGIC) is proposed.
In IU with CLFF, when VDD(LOGIC) is less than 340mV, VDD(FF)is fixed to 340mV and only VDD(LOGIC) is reduced. By
combining the proposed CLFF and the separated VDD, MEEO
is realized at VDD(LOGIC)=310mV and VDD(FF)=340mV, and1835GOPS/W (1.7μW and 3.2MHz) and the highest EEIF’s of
10.4 and 12.7 based on 1.2-V IU’s with TBFF and CLFF aresuccessfully achieved, respectively.

Fig. 9 shows the measured VDD(LOGIC) dependence of the
maximum clock frequency, the total power, and the leakage
power of IU with CLFF. The total power dissipation was
obtained when the add operation with random input patterns
was performed. Fig. 10 shows the measured VDD(LOGIC)
dependence of breakdown of total power and leakage power of
IU with CLFF. IU consists of the combinational logic and FF’s
as shown in Fig. 2. Fig. 10 indicates that the power dissipationof the combinational logic is larger than that of FF’s and theleakage power of FF’s increases with decreasing VDD(LOGIC) due
to the increase in the voltage difference between VDD(FF) andVDD(LOGIC) when VDD(LOGIC) is less than 340mV. The total
leakage power shown in Fig. 9, however, decreases as
VDD(LOGIC) is lowered. Therefore, the leakage power of FF’s dueto the separate VDD is not a serious problem.

TABLE I. COMPARISON WITH THE PUBLISHED SUB/NEAR-THRESHOLD LOGIC CIRCUITS.

[2]

[3]

[4]

This work

CMOS technology

65nm

65nm

45nm

32nm

65nm

Nominal (V)

1.2

1.2

1.1

1.0

1.2

Min. energy (mV)

320

400

300

340

310

VDD

[1]

Min. functional (mV)

Energy efficiency
improvement factor (EEIF)*
Circuit type

1.2

VDD(LOGIC) (V)

Figure 11. Measured VDD(LOGIC) dependence of the energy efficiency of IU’s
with TBFF and CLFF. By combining the proposed CLFF and the separated
VDD, MEEO is realized at VDD(LOGIC)=310mV and VDD(FF)=340mV, and1835GOPS/W (1.7μW and 3.2MHz) and the highest EEIF’s of 10.4 and 12.7
based on 1.2-V IU’s with TBFF and CLFF are successfully achieved,
respectively.

VDD(LOGIC) (V)Reference

0.5

TBFF with VDD(FF) = VDD(LOGIC) (Conv.)

0
0.2

25 C

10.4x

1800

400
200

1μ

2000

600

V
0m
34 mV
0
31
V
0m
22

Power dissipation (W)CLFF with separated VDD(FF) and VDD(LOGIC) (Proposed)

2000

Leakage PowerVDD(FF) = VDD(LOGIC)

Energy efficiency

Combinational
logic

230

N.A.

230

260

220

9.6x

8.3x

8x

5.7x

12.7x (**)
10.4x (***)

Motionestimation
accelerator

DCT &quantization

SIMD vector
processing
accelerator

Reconfigurable
arraysInteger unit(*) Energy efficiency improvement factor (EEIF) =(Energy efficiency @ Min. Energy VDD) / (Energy efficiency @ Nominal VDD)(**) EEIF based on 1.2-V IU with proposed CLFF(***) EEIF based on 1.2-V IU with conventional TBFF

167

Table I shows a comparison with the published sub/nearthreshold logic circuits. Developed IU achieved the highest
EEIF.
IV.

REFERENCES[1]

H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, R. Krishnamurthy,
and S. Borkar, “A 320mV 56μW 411GOPS/Watt ultra-low voltage
motion estimation accelerator in 65nm CMOS,” ISSCC Dig. of Tech.
Papers, pp. 316-317, Feb. 2008.

[2]

Y. Pu, J.P. Gyvez, H. Corporaal, and H. Yajun, “An ultra-lowenergy/frame multi-standard JPEG co-processor in 65nm CMOS with
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[3]

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[4]

A. Agarwal, S.K. Mathew, S.K. Hsu, M.A. Anders, H. Kaul, F. Sheikh,
R. Ramanarayanan, S. Srinivasan, R. Krishnamurthy, and S. Borkar, “A
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[5]

J. Kwong, Y. Ramadass, N. Verma, M. Koesler, K. Huber, H.
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CONCLUSION

In this paper, contention-less flip-flop (CLFF) andseparated VDD between FF’s and combinational logics were
proposed. The proposed technologies were applied to a 16-bit
integer unit (IU) for media processing. Two types of IU’s withthe conventional FF’s and with proposed CLFF’s were
fabricated in a 65-nm CMOS process. Measurement results
revealed that the proposed CLFF can reduce the average VDDmin
of IU’s by 64mV compared with the conventional FF’s, andthe maximum energy efficiency of 1835GOPS/W (1.7μW and
3.2MHz) at VDD(LOGIC)=310mV and VDD(FF)=340mV isachieved by combining the proposed CLFF and the separated
VDD. Consequently, IU with CLFF accomplished the highest
energy efficiency increase of 12.7 times.
ACKNOWLEDGMENTS
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial
Technology Development Organization (NEDO).

168