A Sampling Oscilloscope Macro toward Feedback Physical Design Methodology
Makoto Takamiya and Masayuki Mizuno
System Devices Research Laboratories, NEC Corporation1120, Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
E-mail: taka@mel.cl.nec.co.jp
Abstract
A sampling oscilloscope macro which is easily embedded
in an actually operating LSI in the field has been developed toenable practical use of the feedback physical design methodology. The macro features (1) a high-speed input-isolatedcomparator to measure signals on GHz-digital-LSIs, (2) avoltage-range converter to widen the input range to 2 V at a1-V supply voltage, (3) D/A converters to eliminate the use ofanalog I/O for the macro, (4) an on-chip power supply noise
filter to eliminate the need for a dedicated power supply, and(5) an embedded clock generator to eliminate the need for a
dedicated clock signal. By using the macro, the world's firstmeasurement of an undershooting waveform caused by an
on-chip inductive effect has been demonstrated.
Introduction
The rapid speed-up of digital LSIs, such as MPU andSerDes, has been accompanied by problems caused by signal
integrity degradation such as power supply noise, substratenoise, and an on-chip inductive effect. This is a serious
problem that delays development schedules because of theneed to investigate the cause of errors and increases the costbecause of unanticipated LSI re-fabrication. To avoid thissituation, the design margin has had to gradually become larger with the process scaling, resulting in undesirable constraints on LSI speed, increased area, or greater power consumption. The signal integrity degradation will become
more serious in the future, and it will become more difficult
to predict the problem, because the advances made in CAD
tools are not keeping up with the increasing complexity in therelevant physical phenomena and the increasing VLSI scale.
To solve this problem, a feedback physical design
methodology has been proposed [1]. In this methodology,
on-chip measurement macros are embedded in an actuallyoperating LSI in the field, simulated results are validated using the measured signal integrity degradation obtained fromthe macros, and calibrated design tools are then applied tofuture design. The on-chip measurement is necessary, because it is difficult to measure the on-chip waveform througha conventional probing method because of the difficulty ofprobing in the flip-chip package and the insufficient bandwidth. The measurement during the actual operations in thefield is important, because the degradation depends on thepackage, the application processing, and the layout of eachLSI.
A jitter measurement macro to demonstrate the methodology was discussed in [1]. This paper describes a sampling oscilloscope macro for the methodology, which cancapture high-speed waveforms. The conventional measurement macros [2-5] used to measure the on-chip waveforms
cannot be used for the feedback physical design methodology
because they fall short in one or more of the following circumstances.
1) GHz-clock operations.
2) An input voltage range greater than the supply voltage.

0-7803-8288-9/04/$20.00 © 2004 IEEE

3) No analog I/O. It is impossible to distribute a cleananalog signal in a noisy digital LSI.
4) No dedicated power supply. A dedicated power supply
raises the cost for the chip area and the package.
5) No dedicated clock signal. The dedicated clock signal
raises the package cost.
The proposed sampling oscilloscope macro is able to operate
under all of the above circumstances.
Sampling Oscilloscope Macro
Fig. 1 shows a block diagram of the proposed sampling
oscilloscope macro. The macro has been optimized tomeasure an overshooting/undershooting waveform caused by
the on-chip inductive effect in this design, however, it can beapplied to another high-speed waveform such as the power
supply noise and the substrate noise. To measure the overshooting/undershooting, an input voltage range larger than thesupply voltage is needed, so the voltage-range converter reduces the measured signal’s amplitude. The output of theconverter and the reference voltage are compared by a comparator. The comparator needs to operate at the same speed
as the clock of the high-speed digital LSI. An input-isolatedcomparator enables 68%-increase of the frequency of comparison. To increase the bandwidth of the sampling oscilloscope macro, a high sampling rate is needed. ∆T-step sampling is effectively achieved by sampling the measured signal
with a cycle time of T using a sampling clock with a cycle
time of T+ ∆T. In this design, the minimum ∆T is 5 ps,
which corresponds to a sampling rate of 200 Gsample/s.
The cycle time of the macro outputs are T2/ ∆T. The sampling clock need not be supplied from an off-chip pulse generator, because it is generated by the VCO in the macro.
Also, neither the reference voltage nor the control voltage for
the VCO needs to be supplied from an off-chip voltage source
because both are generated by D/A converters in the macro.
Therefore, all the inputs and the outputs for the macro aredigital signals, and analog I/O is not needed. To suppress
the power supply noise from the surrounding digital LSI toVdd=1V

Power-off
0.5V ± 1V

Measuredsignal

Power supply noise filter
0.66V ± 0.33V

Voltagerange
converter

Cycle=T

Referencevoltage(Vref)

0.68V ± 0.32V(10mV step)D/A converter

Fig. 1240

Input-isolatedcomparator

CompPFD

Up

Sampling clock

Cycle=T2/∆T

Cycle=T+∆T

VCO
Control voltage

0.5V ± 0.32V (10mV step)D/A converter

Sampling oscilloscope macro
Block diagram of the sampling oscilloscope macro

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Cycle=T2/∆T

Vref1> Vref2> Vref3
Cycle=T

Cycle=T

Vref1
Vref2
Vref3

MeasuredsignalRestored Waveformof the measured
signalComp

Timinginformation

Sampling clock
Cycle=T+∆TUp

Fig. 2 Procedure to restore the waveform of the measured signal byusing both the comparator output (Comp) and PFD output (Up)the macro, an on-chip power supply noise filter is embeddedin the macro; this eliminates the need for a dedicated power
supply for the macro.
Fig. 2 shows a procedure to restore the waveform of themeasured signal by using both the comparator output (Comp)and the phase-frequency-detector (PFD) output (Up). When
only Comp is used, the waveform of the measured signal
cannot be restored, because there is no timing information
between the Comp signals. We can, however, restore thewaveform when the PFD is used in combination with thecomparator. When the reference voltage is varied from Vref1
to Vref3, the duty-ratio of Comp changes. On the other hand,
Up indicates the timing information between the measured
signal and the sampling clock. We can restore the waveformof the measured signal by simultaneously measuring Compand Up for the various reference voltages and overlapping theComp waveforms by using the Up signals as a reference.
R-S latch

Clk

Building Blocks
A. Input-isolated Comparator
Fig. 3 (a) is a schematic diagram of the proposed input-isolated comparator. It compares an input voltage (In)and the reference voltage (Vref) at the moment when the Clk
signal changes from high to low. Fig. 3 (b) shows thesimplified circuits of the comparator. When Clk is high,both the input and the output of the inverters are shorted,which is the fastest condition for the two inverters to becomestable. When Clk is low, the output is fixed and is notaffected by the transition of In because the Reset-node isisolated from In. To demonstrate the speed advantage of theproposed comparator, we compared its performance with thatof a conventional comparator [6] shown in Fig. 4 (a). WhenClk is high, both the Reset-node and the Set-node are biased
to Vdd, which is the slowest condition for the two inverters tobecome stable. While Clk is low as shown in Fig. 4 (b), thecomparator output is always affected by the transition of In,
because the Reset-node is not isolated from In. Fig. 5 shows
the simulated dependence of the maximum clock frequency
on the voltage difference (∆V) between In and Vref for boththe conventional and the proposed comparators. As ∆Vincreases, the maximum clock frequency also increases. Ata fixed ∆V, the maximum clock frequency of the proposedcomparator is higher than that of the conventional comparator.
For example, at ∆V of 10 mV, the maximum clock frequencyof the conventional comparator is 2.38 GHz, while that of theproposed comparator is 4.0 GHz, which is 68% higher thanthat of the conventional comparator. Though the lower limitof ∆V of the conventional comparator is 8 mV, that of the
proposed comparator is less than 1 mV.

R-S flip-flop

Out

R

RS

OutS

Reset
Reset

Set
Clk

Set

Clk

Clk

Clk
In

Vref

Clk

Clk

Vref

In(a)

(a)
Clk

R-S latch
RS

R-S flip-flop
RS

Out

Reset

Set

Reset

Vref

In

Clk = highIn

Clk = low

OutSetVref

Clk = low(b)Fig. 4 (a) Schematic diagram and (b) Simplified circuit of theconventional comparator [6](b)Fig. 3 (a) Schematic diagram and (b) Simplified circuits of theproposed input-isolated comparator

241

2004 Symposium on VLSI Circuits
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Maximum clock frequency
for comparator (GHz)5

Proposed comparator

4+68%

3

Conventionalcomparator

2∆V∆V

1
01InVref(0.7V)

2510∆V (mV)

2030

50

Fig. 5 Dependence of the maximum clock frequency for theconventional and the proposed comparators on the voltage difference (∆V) between In and Vref

B. Voltage-range ConverterFig. 6 (a) shows a schematic diagram of the developed
voltage-range converter. The bias voltage, which can begenerated by an on-chip boosted-voltage-generator, is divided
into quarters through a cascade connection of four pMOSFETs. The MOS gate capacitors are used as the capacitors
for the converter. To avoid gate oxide breakdown due toexcess voltage, two MOS gate capacitors are connected inseries. The converter functions as a high-pass-filter and its
cut-off frequency is 20 MHz. At the frequencies higher than20 MHz, the capacitance of the two MOS gate capacitors is
not added to the measured signal. Fig. 6 (b) shows the relation between the input range and the output range of the converter. The converter reduces the voltage amplitude toone-third and shifts the DC-level from Vdd/2 to 2/3 x Vdd.
Therefore, the voltage-range of the measured signal from Vdd/2 to 3/2 x Vdd fits in with that of the reference voltage
from 1/3 x Vdd to Vdd.
C. D/A Converters
Both the reference voltage and the control voltage for theVCO are generated by the two 6-bit folded-string D/A converters[7]. The layout area of the D/A converter is as small
as 120 µm by 20 µm.
D. Power Supply Noise Filter
Fig. 7 (a) shows an equivalent circuit for the on-chip
power supply noise filter, and Fig. 7 (b) shows its circuit implementation. The power supply noise is blocked by inserting an RC low-pass-filter between a noisy Vdd for a digital
Power supply noise filter

Virtual Vdd

Noisy Vdd

180pF

8Bias = 3 x Vdd

Sampling
oscilloscope
macro(a)Power supply noise filter

MeasuredsignalNoisy Vdd+–+–n+n-wellp-sub

Output tocomparatorn+(b)Fig. 7 (a) Equivalent circuit and (b) Circuit implementation of
the on-chip power supply noise filter(a)

Output tocomparator

Referencevoltagex 1
3Noise propagation (Vref / Vdd )(dB)

MeasuredsignalSampling
oscilloscopemacroPower-offn-poly=Virtual Vdd

1.5 x Vdd

Vdd
2 xV
dd3
1 xV
dd
30V

– 0.5 x Vdd
Adjusted byVoltage-range converter(b)Fig. 6 Voltage-range converter. (a) Schematic diagram. (b)Relation between the input range and the output range of theconverter.

0w/o noise filter-5-10–15dB-15-20-25

with noise filter-30-35-40
10k

100k

1M

10MFrequency (Hz)100M

1GFig. 8 Frequency dependence of the noise propagation from thenoisy Vdd to the reference voltage2422004 Symposium on VLSI Circuits
Digest of Technical Papers

LSI and a virtual Vdd for the sampling oscilloscope macro.
MOS gate capacitors are used as the 180-pF capacitors, and apMOSFET is used as the resistor, which enables the samplingoscilloscope macro to power-off when not being used. Fig.
8 shows the simulated frequency dependence of noise propagation from the noisy Vdd to the reference voltage with andwithout the power supply noise filter. The cut-off frequencyof the noise filter was 2 MHz. The low-pass-filter characteristics without the noise filter was caused by the resistance-array for the D/A converter and the capacitance shownin Fig. 1. Use of the noise filter decreased the noise propagation by –15 dB at 10 MHz.

Table 1
Reference
Measuredtarget
CMOS
processClockfrequency
Input
range
Analog I/OExperimental Results and Discussions
Fig. 9 shows a micrograph of a sampling oscilloscope
macro fabricated with an 1.0 V 90-nm ASPLA CMOS process.
The macro area was 350 µm by 140 µm. To demonstrate theperformance of the macro, the signal integrity degradation
due to the on-chip inductive effect was measured. Fig. 10shows a measured circuit. The far-end of the 2mm-wire wasconnected to the sampling oscilloscope macro. The additional capacitance due to the sampling oscilloscope macro
was only 10 fF, which was less than 5% of the capacitance ofSamplingoscilloscope
macro

350µm
140µm

Chip micrographMeasured circuit

0.6

Calibrated voltage (V)2.2GHz clock
0.4

0.2

0.0– 0.2

Undershooting
050100150200250

VLSI2003[5]

This work

Power
Substrate Substrate supply&noisenoise
substratenoisePowersupply
noise

High-speed
signal

0.8 µm

0.6 µm0.13 µm

0.09 µm

0.09 µm

5 MHz

50 MHz800 MHz~GHz

ISSCC2000[4]–20 mV ~ –15 mV ~ –0.3 V ~2.2 GHz–0.5 x Vdd~

10 mV

15 mV

Vdd+ 0.3 V

Vdd / 2

Yes

Yes

Yes

NoYes

Yes

Yes

NoNo
need

On-chip
generation

External On-chipsupply generation

1.5 x Vdd
No

the 2mm-wire, and did not affect the original waveform.
Fig. 11 shows an undershooting waveform measured by
the sampling oscilloscope macro. The clock frequency was
2.2 GHz. The 0.2-V undershooting of clock signal causedby the on-chip inductive effect has been successfully measured.
Table 1 compares recently reported designs and the proposed sampling oscilloscope macro. The proposed macro
has the highest clock frequency and the widest input range.
Because the macro requires no dedicated power supply, noanalog I/O, and no dedicated clock signal, it is easily embedded in an actually operating LSI, and thus enables the feedback physical design methodology.

References

To sampling
oscilloscope
macro– 0.4[3]

ISSCC2002

DedicatedYes
power supply
Sampling
External
clock
supply2mm wire
Clock

Fig. 10[2]

JSSC96

Conclusions
The sampling oscilloscope macro fabricated with a 1.0 V
90-nm CMOS process occupies 350 µm x 140 µm andachieves 68%-increase of the operation frequency and theinput voltage range of 2 V. The macro is easy to be embedded in an actually operating LSI, because it requires no dedicated power supply, no analog I/O, and no dedicated clock
signal. By using the macro, the world's first measurement ofan undershooting waveform caused by an on-chip inductive
effect has demonstrated at 2.2-GHz clock.

2mm wire

Fig. 9Comparison of on-chip measurement macros

300350Time (ps)Fig. 11 Undershooting waveform measured by the sampling
oscilloscope macro[1] M. Takamiya, H. Inohara, and M. Mizuno, "On-chip jitter-spectrum-analyzer for high-speed digital designs," ISSCC
Dig. of Tech. Papers, Feb. 2004.
[2] K. Makie-Fukuda, T. Anbo, T. Tsukada, T. Matsuura, and M.
Hotta, "Voltage-comparator-based measurement of equivalently
sampled substrate noise waveforms in mixed-signal integratedcircuits", IEEE J. of Solid-State Circuits, pp. 726 – 731, May
1996.
[3] M. Nagata, K. Hijikata, J. Nagai, T. Morie, and A. Iwata, "Reduced substrate noise digital design for improving embedded
analog performance", ISSCC Dig. of Tech. Papers, pp. 224 –225, Feb. 2000.
[4] M. Takamiya, M. Mizuno, and K. Nakamura, "An on-chip,
100-GHz sampling rate, 8-channel sampling oscilloscope macrowith embedded sampling clock generator," ISSCC Dig. of Tech.
Papers, pp. 182–183, Feb. 2002.
[5] A. Muhtaroglu, G. Taylor, T. Rahal-Arabi, and K. Callahan,"On-die droop detector for analog sensing of power supply
noise," Dig. of Symp. on VLSI Circuits, pp. 193–196, June 2003.
[6] A. Yukawa, "A CMOS 8-bit high-speed A/D converter IC",IEEE J. of Solid-State Circuits, pp. 775 – 779, June 1985.
[7] A. Abrial, J. Bouvie, J.-M. Fournie, P. Senn, and M. Veillard, "A
27-MHz digital-to-analog video processor", IEEE J. ofSolid-State Circuits, pp. 1358 – 1369, Dec. 1988.

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2004 Symposium on VLSI Circuits
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