IEEE 2006 Custom Intergrated Circuits Conference (CICC)

Chip-to-Chip Inductive Wireless Power Transmission
System for SiP Applications
Kohei Onizuka1, Hiroshi Kawaguchi3, Makoto Takamiya1, Tadahiro Kuroda4 and Takayasu Sakurai2
1

Institute of Industrial Science and 2Center for Collaborative Research, University of Tokyo, Tokyo, Japan3
Department of Computer and Systems Engineering, Kobe University, Kobe, Japan
4
Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japankohei@iis.u-tokyo.ac.jp

Abstract— A chip-to-chip inductive wireless powertransmission system is proposed and the feasibility isexperimentally demonstrated for the first time. The circuit
realized 2.5mW power transmission at the output DC voltage
of 0.5V using 700x700µm on-chip planar inductors for thetransmitter and the receiver. Methods to optimize the circuitdesign about the maximum transmission power and thesimulated optimization results are discussed.

I.

INTRODUCTION

A System-in-a-Package (SiP) is getting a major 3D
integration approach in recent years. For data
communication among stacked chips in SiP’s, wireless datatransmission technologies have been investigated for highspeed, low power and low cost [1][2]. Power delivery inthese systems, however, is not wireless and is based on
bonding. Then, it is difficult to get two stacked chips close,
since the bonding needs several hundred microns separation
between chips. One solution is to skew the stacked chips but
this is difficult if the upper chip should be connected in the
middle of the lower chip and is covered by the topmost chip.
If the power is supplied wirelessly, the chips can be stacked
closely and the wireless data transmission performance will

Fig.2. Concept of system modification after fabrication of SiP’s/SoC’s.

be increased, since the data bandwidth and communication
reliability increases as the chip-to-chip distance is decreased
in wireless data communication. The cost is also decreased
due to the elimination of mechanical bonding. Furthermore,chip detachability can also be achieved by combining thewireless data and power transmission. This opens up a totallynew system customization scheme after the fabrication as wesometimes change a daughter board for system upgrade.
Fig.1 illustrates a proposed wireless power delivery scheme
based on inductive coupling between the lowest chip andupper chips. The shortest inductor-to-inductor distancedepends on the thinning of the chip thickness, which is as
small as 20 microns. If a face-to-face configuration ispossible, the distance is further reduced, which is used in themeasurement setup in this paper.

Fig.1. Concept of chip-to-chip wireless power transmission.

1-4244-0076-7/06/$20.00 ©2006 IEEE

Fig.2 shows the concept of system customization after thefabrication of an SiP to reduce mask set cost and to increase
post-fabrication system modification freedom. Chips likeaccelerators, special engines, analogs, memories are attachedwirelessly on top of the lower base chip. The lower chip
embedded in the package has a data transceiver and a “power

15-1-1575

transmitter”. The upper chip attached to the package has adata transceiver and a “power receiver”. This system maygive users the ability to upgrade the SiP’s like adaughterboard upgrade nowadays. The risk of ESD problem
is mitigated because this system eliminates the naked
interconnections and metal pads with coils for wirelesstransmission being covered by passivation layer.
II.

CIRCUIT TOPOLOGYFig.3 shows the circuit diagram of the proposed system.
The lower chip includes a transmitter circuit and an on-chipplanar inductor L1 for magnetic field generation. The
transmitter circuit generates an RF signal from the DC
supply voltage VDD and activates L1. The power istransmitted by magnetic fields rather than radio waves. Fig.4
describes a diagram of the adopted transmitter, where theoscillation frequency f of the ring oscillator is designed to bevariable for the experiments. The upper chip includes an onchip planar inductor L2, a full-wave rectifier circuit using
MOSFET-based diodes and a smoothing capacitor. Fig.5
shows the circuit diagram of the diode circuit whose two
PMOS transistors reduce the undesirable body effect of themain PMOS transistor [3]. k indicates the coupling factor ofthe inductors.

III.

SIMULATION AND MEASUREMENT RESUTLS

The system shown in Fig.3 was designed in 0.35-µm
CMOS and fabricated. Generally, on-chip planar inductors
have considerable parasitic capacitive and resistive elements
so that the Q factor is not high. Fig.6 shows the simulation
model of the planar inductors. RP and CP represent the seriesresistance and the parasitic capacitances of the inductor
respectively. The values of RP and CP are calculated byapproximation formulas and k is derived by Momentum
electromagnetic field simulator. The parasitic resistances ofbuffers, diodes and interconnections were be estimatedcarefully and minimized in design and layout process.
The outside diameter of the inductor is set to 700x700µm
and k is calculated to be 0.75. RF voltage generated between
two terminals of L2 is set to be twice the nominal VDD whenRL=∞. This RF voltage is better to be higher to reduce thediode voltage loss but it can not surpass twice the tolerant
voltage of the PMOS shown in Fig.5. Fig.7 shows
microphotographs of the fabricated power transmitter andreceiver chips. Fig.8 and 9 show the measurement setup. Thelower (upper) chip is mounted on the lower (upper) board
and the two chips gets closer together face-to-face.
RPL

Upper Chip

Lower Chip

DL L2
RF+ 1

D+CPRLTransmitterFig.6. Equivalent circuit of inductor with parasitic elements.

RF-kFig.3. Circuit diagram of proposed system.

Differential
BuffersRF+(a)RingOscillator(b)Fig.7.Chip microphotograph of (a) transmitter and (b) receiver.

RFFig.4. Circuit diagram of transmitter.

zD+xD-yFig.5. Circuit diagram of PMOS-based diode.

Fig.8. Whole image of measurement setup.

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UpperChip

Output Voltage (V)Lower Chip

Upper Board

Lower Board

1.6

0.80Fig.9. Closeup view of measurement setup.

Fig.10 shows the simulated and measured transmitted
power dependence on output DC voltage. HSPICE is usedfor the simulation. In this implementation, L1=1.0nH,
L2=9.3nH and the oscillation frequency is set to f = 330MHz
for this graph. Output voltage is varied by changing DC
output load RL. The peak transmitted power is observed
when RL is 100Ω, which is the equivalent source resistanceof the wireless power source. The simulated results coincide
well with the measured results. Thus the modeling accuracy
is considered to be sufficiently high.

Transmitted Power (mW)

Output Voltage (V)

1.6

0.8
0280
560 Δx (µm)

0Δy (µm) 280

Fig.13. Equivalent circuit of inductor with parasitic elements.

IV.

3CIRCUIT OPTIMIZATION

Although the feasibility of the wireless power delivery
system is demonstrated in the previous sections, it ispreferable to increase the transmittable power to further
increase the variety of applications. In this section, themethodology for further increasing the transmitted power isdescribed. Improvement can be achieved by adding
resonance capacitors C1 and C2 as shown in Fig.14. RS
represents
parasitic
resistancesoftransmitter

RL=100Ω
201200

Fig.12. Output voltage dependence on ∆z.

Figs. 11, 12 and 13 show the measured output voltage
dependence on frequency, ∆z (distance between chips) and∆x (misplacement in x direction) and ∆y (misplacement in ydirection) when the load is open which equals to RL=∞.

1800400Δz (µm)

Measured
Simulated

RS C10.2 0.4 0.6 0.8 1 1.2 1.4
Output Voltage (V)Ejω

Fig.10. Transmitted power dependence on output voltage.

R1

R2
L2 C2

L1

RL_AC

Output Voltage (V)

1.6kFig.14. Equivalent circuit of inductor with parasitic elements.

1.45

1.3
150

RL_DC250
Frequency (MHz)350
Fig.15. Equivalent circuit of inductor with parasitic elements.

Fig.11. Output voltage dependence on oscillation frequency f.

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interconnections and driving transistors. R1 and R2 indicate
series resistances of L1 and L2 respectively. Capacitances C1and C2 resonate with L1 serially and with L2 in parallel
respectively. RL_AC relates to the equivalent total impedanceof the rectifier, the smoothing capacitor and the DC load
resistance RL_DC as shown in Fig.15. RL_AC was shown to beapproximated as follows when the rectifier is ideal and thesmoothing capacitor is large enough [4].
R L _ AC ≈R L _ DC2(1).

Here, we assume the transmitted power is high (if notmaximized) when transmitter circuit is in resonance. That is,
C1 is expressed as follows. Although this condition does notgive the optimum condition, the resultant transmitted power
is at least achievable.
C1 =1.
4 π 2 f 2 L1(2)Under this condition, the values of C2 and RL expressed asfollows maximize the transmitted power, which is exact.
Here, ω=2πf.
C2 =( R 1 + R S )2 L 2((R + R )R + ω k L L ) + ω (R + R ) L
21S

22R L _ AC =212212S(R1 + R S )R2 + ω 2 k 2 L1 L2 .
(R1 + R S )(1 − ω 2 C 2 L2 )22.

[E 2 ω 2 k 2 L1 L2(4)]8 ω k L1 L2 + R 2 ( R1 + R S ) ( R1 + R S )
22.

(5)

The output AC voltage VOUT_AC of the load resistance RL_ACis
VOUT _ AC =2 PMAX R L _ AC .

(6)

L2 is determined so that VOUT_AC equals to twice the VDD
as is mentioned in section III. For the on-chip planarinductors, the relationship between RN and LN isapproximated as follows with ζ being a technology
parameter.

PMAX_AC is simplified as follows using (7) and theapproximation of RS=0.
E 2ω2k 2(8 ζL1 ζ 2 + ω 2 k 2)

.

R2

RL

27.3

43.6

29.1

transmitted power is increased to 21.6mW with output DC
voltage of 1.8V by simulation, which should be comparedwith 2.5mW without the resonant capacitors.
The improvement of the rectifier circuit is also effective andsimulation shows that the transmitted power is further
increased to 35mW if the new rectifying circuit proposed in[5] is employed. Under this condition, power breakdown
consumed by R1, R2, RL is calculated as shown in Table I. If
the area allowed for the wireless power delivery system canbe increased to 2.1mm square, 9 parallel power transceivers
each of which has 700x700µm in diameter can be
implemented and then more than 300mW powertransmission is considered to be possible.
V.

CONCLUSIONSACKNOWLEDGMENT
This work is supported by VLSI Design and Education
Center (VDEC), the University of Tokyo in collaboration
with Rohm Corporation, Toppan Printing Corporation andCadence Design Systems, Inc. This research was partially
supported by Japan Society for the Promotion of Science(JSPS), Grant-in-Aid for Scientific Research (KAKENHI)
16760271.
REFERENCES
[1]

[2]

(7)

R N ≈ ζL N .

PMax _ AC ≈Power(%)

R1

In summary, a chip-to-chip 2.5mW wireless powertransmission system was proposed and demonstrated by
0.35-µm CMOS technology. A possible increase to 300mW
power transmission is also discussed by introducing resonantcapacitors.

(3)

It is to be noted that this C2 is independent from RL, which isnice. Then, the available transmitted power is expressed as:
PMax _ AC =Table I. Power breakdown of R1, R2 and RL.

[3]

(8)
[4]

The value of L1 (or the outside diameter of L1) and k havestrong independence thus the maximum power and the valueof L1 is determined by the trade-off.
After all, the capacitances of the resonant capacitors arecalculated to be C1=281pF, C2=15pF. When these capacitors
are added to the original circuit configuration, the[5]15-1-4

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