An All 0.5V, 1Mbps, 315MHz OOK Transceiver with 38-μW Career-Frequency-FreeIntermittent Sampling Receiver and 52-μW Class-F Transmitter in 40-nm CMOS
Akira Saito1, Kentaro Honda2, Yunfei Zheng2, Shunta Iguchi2, Kazunori Watanabe1, Takayasu Sakurai2, and Makoto Takamiya2
1
Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan, 2University of Tokyo, Tokyo, Japan
Abstract
An all 0.5V, 1Mbps, 315MHz OOK transceiver in 40-nm
CMOS for body area networks is developed. Both a 38-pJ/bit
career-frequency-free intermittent sampling receiver with-55dBm sensitivity and a 52-pJ/bit class-F transmitter with-21dBm output power achieve the lowest energy in the
published transceivers for wireless sensor networks.
Introduction
A low power OOK transceiver for short-range wirelesssensor networks (e.g. body area networks) is developed in thispaper. The target receiver (RX) sensitivity and transmitter(TX) output power is -55dBm and -20dBm, respectively,
assuming -25dB propagation loss at the 1-m communication
distance and -5dB x 2 loss at TX/RX antennas. The target
power consumption is 50μW at 1Mbps. In order to reduce thepower, (1) sampling circuits are used instead of continuous
analog circuits, (2) the power supply voltage (VDD) is reduced
to 0.5V, (3) the RX input is directly sampled without LNA,
because high sensitivity is not required for the 1-m
communication, (4) low career frequency of 315MHz insteadof 2.4GHz is used to reduce the required bandwidth of thesampler, (5) a career-frequency-free (CFF) intermittent
sampling (IS) is newly proposed to reduce the number ofsampling, thereby reducing the power of the sampler to 1/315of that of the conventional continuous sampling.
Career-Frequency-Free Intermittent Sampling Receiver
A conventional continuous sampling [1-2] and theproposed IS concept for RX are compared in Fig. 1. The
proposed IS reduces the number of the sampling in 1 symbol
in order to reduce the power consumption of the sampler. Fig.
2 shows a block diagram of the proposed all 0.5V CFF IS RX.
Only 1-MHz clock instead of a 315-MHz career frequency issupplied to RX. RX input (VIN) is directly sampled byintermittent samplers without LNA. Fig. 3 shows a schematicof the intermittent sampler. Fig. 4 shows a timing chart of
CFF IS RX. VIN is sampled by quadrature 315-MHz clocks(φ0, φ90, φ180, and φ270). The timing difference of ΔT isgenerated by digitally controlled delay lines instead of aconventional quadrature 315-MHz PLL, thereby reducing thepower consumption. In the 315-MHz, 1-Mbps CFF IS RX,
the number of sampling of VIN per bit is 4, while that of theconventional continuous sampling is 4x315, thereby reducing
the power consumption of the sampler to 1/315. By the clockof φHPF, the sampled VIN’s are subtracted for a high pass filter
function in order to increase the RX sensitivity by 3dB [3].
The outputs of the samplers ( V1 , V1 , V2 , and V2 ) areamplified by 5-stage IF amplifiers with an offset cancellation[4]. Then, the outputs of the amplifiers (V2A) are compared byproposed variable offset comparators clocked by φCMP, andthe data is demodulated. V2A is not constant, because the DC
component is eliminated in the offset cancel amplifier [4]. In
CFF IS RX, the degradation of RX sensitivity due to ΔT
variations is a design concern. In order to clarify the effect ofΔT variations on the RX sensitivity, Fig. 5 shows a calculated
dependence of maximum amplitude of V1 or V2 on ΔT. In theideal case of ΔT=T/4=0.8ns, the amplitude is 1. The
amplitude, however, is reduced to 1/ 2 =0.7, when thesampling phase is changed. In CFF IS RX, the RX sensitivity
is determined by the worst case (=minimum) amplitude,
because the phase is not synchronized. The worst caseamplitude depends on ΔT. For example, at ΔT=T/2=1.6ns, the978-1-4673-0849-6/12/$31.00 ©2012 IEEE

worst case amplitude is 0, which is unacceptable. In order tosuppress the amplitude degradation within 10% and 50%, theΔT variation should be less than ± 11% and ± 41%,
respectively. In this design, ΔT variation is controlled within± 41% by the digitally controlled delay lines.
Building Blocks
In CFF IS RX, instead of a variable gain amplifier, theclocked variable offset comparator is used to keep thereceived signal amplitude constant with low power
consumption. The variable offset comparator eliminates theneed for a voltage reference circuit, which is very important,because the voltage reference circuit operating at 0.5V isdifficult to implement. Fig. 6 shows a schematic of thedigitally variable offset comparator. The comparator has 2
sets (CLEFT and CRIGHT) of 63 switched capacitors controlledby 6 bits to change the offset voltage. The offset of thecomparator itself can also be compensated by the digitalcontrol.
The design challenge of TX is to increase the efficiency at
the target low output power of -20dBm and 0.5V, because theefficiency of a power amplifier (PA) decreases with reducing
output power and VDD. A class-F PA instead of a class-D orclass-E PA is used in this work, because the class-F PA
achieved the highest efficiency at the target specification. Fig.
7 shows a schematic of a class-F transmitter. All inductors
and capacitors are implemented in off-chip.
Experimental Results
The proposed transceiver is fabricated in 40-nm CMOS
process. Fig. 8 shows a die photo and layout of RX and TX.
Table I shows a performance summary. Thanks to theproposed IS, the power consumption of the samplers in RX is3μW and the total RX consumes 38 μW. Without IS, thecontinuous sampler will consume 945μW (=3μW x 315).
Therefore, the proposed IS is a key technology to reduce theRX power consumption. Fig. 9 shows a measured dependenceof the offset voltage on the number of connected capacitors in
CRIGHT in the proposed digitally variable offset comparator.
CLEFT is fixed. The horizontal axis corresponds to the 6-bit
digital control. The measured tuning range of the offset is65mV. Fig. 10 shows measured waveforms of CFF IS RX.
1-Mbps data is successfully demodulated. Fig. 11 shows ameasured dependence of BER on RX input signal power. At
BER of 10-3, the RX sensitivity is -55dBm. Fig. 12 shows ameasured TX output spectrum. The TX output power is-21dBm at 315MHz. The TX efficiency is 16%. Fig. 13 shows
a comparison of power and data rate with publishedtransceivers [4-8] for wireless sensor networks. Both the38-pJ/bit CFF IS RX and the 52-pJ/bit class-F TX achieve thelowest energy to date.
Acknowledgment
This work was carried out as a part of Extremely Low
Power (ELP) project supported by METI and NEDO.
References[1] B. Staszewski, et al., ISSCC, pp. 272-273, 2004.
[2] M. Soer et al., ISSCC, pp. 222-223, 2009.
[3] M. Soer et al., JSSC, vol. 57, pp. 2618-2631, 2010.
[4] N. Pletcher et al., ISSCC, pp. 524-525, 2008.
[5] B. Cook, et al., ISSCC, pp. 370-371, 2006.
[6] M. Crepaldi et al., ISSCC, pp. 226-227, 2010.
[7] M. Vidojkovic et al., ISSCC, pp. 458-459, 2011.
[8] J. Pandey et al., ISSCC, pp. 460-461, 2011.

2012 Symposium on VLSI Circuits Digest of Technical Papers

38

φ180 φHPF

Sampler1
VIN(a) Conventional continuous sampling
1 symbolV1

φ90 φ270
Sampler2

Balun

φ01 symbol

V1Clk(1MHz)

Data(1Mbps)

“0”
1μs

“1”
1μs

V2

φHPF

Digitally controlled delay lines

Fig. 3. Schematic of intermittent sampler.

φ0 φ90 φ180 φ270 φHPF φCMP

“0”
1μs

φHPF

Out(b) Proposed intermittent sampling

Fig. 1. Proposed intermittent sampling (IS) concept.

φ180 or φ270
V2A+-+Sampler4

φHPF

Out InV2

φ90 φ270

φ0 or φ90+-+

φ180

Sampler3VIN=φCMP

Fig. 2. Block diagram of proposed all 0.5V
career-frequency-free (CFF) IS RX.

ΔT=0.8ns
1VIN

0T=3.2ns(=1/315MHz)
90
180
ΔT

φ0ΔT

Max. amplitude of V1 or V2 (a.u.)

VIN

a270
ΔT

φ90
φ180
φ270

T1>T

φHPF
V2

Ideal case

-0.5
-1

0.6

-50%-10%+11%00.8 1.6 2.4 3.24

4.8 5.6

Time (ns)

Worst case

ΔT=1.6ns

0.4

1+41%

0.5

0.2

0000.5

1.0

1.5

-0.5

2.0ΔT(ns)T2>T

φCMP00.8a/2

V2A

0.5

1-1
0

0.8 1.6 2.4 3.24

4.8 5.6

Time (ns)Fig. 5. Calculated dependence of max amplitude of V1 or V2 on ΔT in CFF IS RX.

OutFig. 4. Timing chart of CFF IS RX.

1.1 mm

VDD=0.5V

0.6 mm6

VDD=0.5V
100nH

2.7nH

0.5 mm

63 switched capacitors(CRIGHT)In-

φCMP

1.1 mmφCMP
63 switched capacitors(CLEFT)
In+

6

D Q
φCMP

Data(1Mbps)

Delay

On-chip

φCMP

Supply voltage
0.5V
Carrier frequency
315MHzData rate
1Mbps
RX1MHzClockfrequency
TX
315MHzModulation
OOK
RX sensitivity-55dBmTX output power-21dBmSampler
3μW
Amplifier
30μW
Comparator
2μW
RXPower
Delay lines
3μW
Total
38μW
TX
Total
52μW
RX
38pJ/bit
EnergyTX
52pJ/bitRX
156000μm2
Core area
TX
1230μm2

Offset voltage of comparator (mV)Fig. 6. Schematic of digitally variable offset comparator.
Table I Performance summary.
90
40nm

10pF
11pF

Carrier(315MHz)

φCMP

CMOS

1pF

Out

22nH

Off-chip

56 μm

Fig. 7. Schematic of 0.5V class-F TX.

473 μm(a)807050113010CLEFT is fixed.

010101020304050Out011000101060

Number of connected capacitors in CRIGHT

Fig. 10. Measured waveforms of CFF IS RX.

Fig. 9. Measured offset voltage of comparator.

10mW-3

10-4

10-5

10-6

10Power consumption-21dBm@315MHz

Rx
Rx
Tx
Tx

Fig. 12. Measured TX output spectrum.

[7]

/bnJ
10

[6]
[5]

1mW
J/b1n100μW

[4]

[7]

[5]

[8]

J/b0p
1010μW
100k-70 -65 -60 -55 -50 -45 -40

978-1-4673-0849-6/12/$31.00 ©2012 IEEE0V2A

20-2Input signal power (dBm)

0Clk(1MHz)

40000VIN6010Fig. 11. Measured dependence ofBER on RX input signal power.

(b)

Fig. 8. Die photo and layout of (a) RX and (b) TX.

-11022 μm

Digitalcontrol

329 μmDigitalcontrol

Bit error rate

VIN (a.u.)

φ0Variable offset
comparators

5-stage
amplifiersIntermittentsamplers

1 symbol

VIN (a.u.)

1 symbolThis work/bpJ
101M

Data rate (bps)

10MFig. 13. Comparison with published transceivers
for wireless sensor networks.

2012 Symposium on VLSI Circuits Digest of Technical Papers

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