An 85-mV Input, 50-μs Startup Fully Integrated
Voltage Multiplier with Passive Clock Boost Using
On-Chip Transformers for Energy Harvesting
Hiroshi Fuketa1, Youichi Momiyama2, Atsushi Okamoto2, Tsuyoshi Sakata2,
Makoto Takamiya1, and Takayasu Sakurai1
12

Institute of Industrial Science
University of Tokyo
Tokyo, Japan

Abstract— A fully integrated voltage multiplier with low
startup voltage (VSTART) and fast startup is developed for theenergy harvesting (e.g. thermoelectric energy harvester). The
generation of the high frequency clock signal with large
amplitude without using off-chip components is a key to achieve
the voltage multiplier. The proposed passive clock boost using
two on-chip transformers with the winding turns ratio of three
reduces VSTART. The 138-MHz clock generation with a fully
integrated LC oscillator enables the fast startup. The voltage
multiplier fabricated in 65-nm CMOS achieves the lowest cold
VSTART of 85mV in the published fully integrated voltage
multiplier and the shortest startup time of 50μs.

I.

INTRODUCTION

A wide variety of distributed tiny wireless devices
including sensor devices for Internet of Things (IoT), wearable
wellness devices, and implanted medical devices require theenergy autonomy. One of the key enabling technologies for theenergy autonomous systems is the energy harvesting [1]. The
output voltage of the energy harvester, however, is often too
low for the electronic devices. For example, the output voltageof the thermoelectric generator is in the range of 10mV/K to
50mV/K. For body-wearable applications, the output voltage isless than 100mV for the temperature difference of 2K. The
single-cell solar cell generates 500-600mV in the outdoor and100-200mV in the dark office environment. Therefore, a stepup DC-DC converter is required to boost the harvested (sub)100mV to above 1V for the electronic devices. The key
requirements for the low-input step-up DC-DC converter are(1) the fully integrated solution to reduce the size and the cost
due to the off-chip components, (2) sub-100mV cold startup
voltage (VSTART) for the thermoelectric generator and thesingle-cell solar cell in the dark office environment, and (3)sub-100μs startup time (tSTART) for the quick wake-up of theenergy autonomous systems.
Though the fully integrated solutions with the capacitive
voltage multiplier were reported [2-4], VSTART of them areabove 120mV, because they use CMOS ring oscillators togenerate the clock for the voltage multiplier and the lower limitof VSTART is determined by the minimum supply voltage(VDDmin) of the ring oscillators [5]. Theoretically, the lower
limit of VDDmin is 36 mV at room temperature [6], but actually

978-1-4799-5696-8/14/$31.00 ©2014 IEEE263

SoC Technology & Design Platform Development Dept.
Technology Development CenterFujitsu Semiconductor Ltd.
Tokyo, Japan

VDDmin is more than 100 mV due to manufacturing variations
and large subthreshold slope [7]. To solve the VDDmin problem,transformer-based oscillators and LC oscillators are proposedand boost converters with VSTART of less than 50mV werereported [8-10]. The boost converters, however, require a bulky
off-chip transformer [8, 9] or off-chip inductors [10], which are
not the fully integrated solution. tSTART of the boost converter is6ms [10], which is beyond our design target of sub-100μs,because the switching frequency of the boost converter is25kHz. To achieve tSTART of sub-100μs, the frequency should
be increased.
In this paper, a fully integrated voltage multiplier with apassive clock boost using on-chip transformers is proposed tosolve these problems. The voltage multiplier fabricated in a 65nm CMOS process achieves the lowest cold VSTART of 85mV
in the published fully integrated voltage multiplier and theshortest tSTART of 50μs.
This paper is organized as follows. The clock generation
techniques for the voltage multiplier with the passive clock
boost using on-chip transformers are described in Section II.
Section III shows the circuit implementation of the voltage
multiplier. The experimental results are shown in Section IV.
Finally, Section V concludes this paper.
II.

CLOCK GENERATION FOR VOLTAGE MULTIPLIER

Various low-voltage input step-up DC-DC converters
with a voltage multiplier have been proposed for the energy
harvester. The circuit architecture is illustrated in Fig. 1. The
clock signal (CLK) is generated with an oscillator using thelow DC input voltage (VIN). The n-stage voltage multiplier
boosts VIN to the output voltage (VOUT). Consequently, VOUT isgiven by VIN + nVCLK under the ideal condition, where VCLK isthe amplitude of CLK. Thus, large VCLK can reduce n required
to obtain a certain VOUT, such as 1V. The high frequency clock
signal is also required to reduce tSTART to sub-100μs. Therefore,
the generation of the high frequency clock signal with large
amplitude without using off-chip components is a key toachieve the voltage multiplier.
Fig. 2 summarizes various clock generation techniques forthe low-voltage input step-up DC-DC converters. In a ring

5-stage voltage multiplier

VIN (DC)
Clockgenerator(oscillator)

VS+n-stagevoltagemultiplier

CLK(AC)

V1

VIN

VOUT (DC)VOUTCOUT

VOUT = VIN + nVCLK

Amplitude: VCLKRLVS-Fig. 1. Circuit architecture of low-voltage input step-up DC-DC converterwith voltage multiplier.

3:1

1:3

VP+

VP-

MN1

MN2

Proposed passive clock boost
with on-chip transformers

VIN
VIN
CLK

VP+

VP-Low VTH

Standard VTH

LC oscillator
Fig. 3. Circuit schematic of proposed voltage multiplier with passiveclock boost using on-chip transformers.

CLK = VP+ - VP-CLKVIN
0V

Time

VIN less than 100mV can be directly boosted to above 1.0V.
This means the voltage multiplier can be removed. The offchip transformer, however, is the large overhead in terms of thesize and the cost.

VCLK = 2VIN

0V

Time

VCLK = VIN(a) Ring oscillator [2, 5](b) LC oscillator [10]VS+VIN

To solve the problems, the passive clock boost using onchip transformers is proposed. Fig. 2(d) shows the LCoscillator and two on-chip transformers for the proposed
passive clock boost. By adding two transformers to the LC
oscillator shown in Fig. 2(b), the amplitude of VCLK isincreased to 2NVIN. Compared with the transformer-based LC
oscillator in Fig. 2(c), the amplitude of VCLK of the proposed
Fig. 2(d) is doubled because of the differential outputs. The
overhead of the two transformers is alleviated by the on-chipintegration. In the on-chip transformer, it is difficult to achieve
high winding turns ratio. By using two transformers, theamplitude of VCLK is doubled, which is equivalent to doubling
the winding turns ratio. Therefore, the proposed passive clock
boost using two on-chip transformers is effective for the fully
integrated step-up DC-DC converter.

VSVIN
1:N

N:1

1:N

CLK

CLK = VS+ - VSCLKVCLK = 2NVIN
VCLK = NVIN
0VTime

0V

Time

III.

(c) Transformer-based
LC oscillator [8, 9](d) LC oscillator andtransformers(This work)

Fig. 2. Clock generation techniques for low-voltage input step-up DC-DC
converters with (b) ring oscillator, (c) LC oscillator, (d) transformer-based
LC oscillator, and (e) proposed LC oscillator with transformers.

oscillator in Fig. 2(a) [2, 5], it is suitable for the fully integrated
converter, since it can be implemented by only CMOS logicgates. The amplitude of VCLK in the ring oscillator, however, islimited to VIN. Another technique for generating VCLK is an LC
oscillator in Fig. 2(b) [10]. In this case, the amplitude of VCLKis 2VIN. To increase the amplitude, a transformer-based LC
oscillator in Fig. 2(c) is proposed [8, 9]. When N is the winding
turns ratio and the transformer is assumed to be ideal, theamplitude of VCLK is NVIN, In the conventional works [8, 9],
the off-chip transformers with N=60 and N=100 are used. Thus,

264

CIRCUIT IMPLEMENTATION

Fig. 3 shows the circuit schematic of the proposed voltage
multiplier with passive clock boost using on-chip transformers.
138-MHz clock signal is generated by the LC oscillator
operating at VIN. Low threshold voltage (VTH) transistors areused for MN1 and MN2 of the LC oscillator to increase thetransconductance at low VIN, which makes possible VSTART ofless than 100 mV. The clock signals (VP+, VP-) are triply
boosted by the proposed passive clock boost assuming thetransformers are ideal. The 5-stage cross-coupled MOSFET
voltage doublers with boosted clock signals (VS+, VS-) boost
VIN to VOUT.
Fig. 4 illustrates the SPICE simulated waveforms of theproposed voltage multiplier. When VIN is larger than VSTART,
the LC oscillator generates the clock signal (VP+). VP+ isboosted to VS+ by the proposed passive clock boost. The
amplitude of VS+ (VAS) is N times as large as VAP, where N isthe transformation ratio of the transformers. Ideally, N isequivalent to the winding turns ratio of 3. In the actual
implementation, N is 2.2 at 138MHz without load based

VIN
0V

VAP = VIN

VP+138MHz
0V

VAS = NVAP

VS+0V

VIN+2VAS

V10V

VOUT

Fig. 6. Measured output waveform of LC oscillator (VP+) in Fig. 3.

VIN+10VAS
0V

VOUT

VIN=120mVStartup time (tSTART)Fig. 4. Simulated waveforms of the proposed voltage multiplier.
1.2V

2.1 mmTransformer

Transformer

850 μmVIN

120mV

Startup time (tSTART) = 8μs(a)MN1 and MN2(200 x 90μm)

850 μm

VIN=85mV

VOUT

Voltage multiplier (200 x 400μm)

(a)
0.4V

Primary coil (3 turns)

VIN

Secondary coil (9 turns)

85mV

Startup time (tSTART) = 50μs(b)Fig. 7. Measured startup waveform when RL is 1MΩ at (a) VIN=120mVand (b) VIN=85mV.
7th metal

6th metal(b)Fig. 5. (a) Chip micrograph and (b) layout of on-chip transformer.

on the electromagnetic simulation (Momentum). The boosted
clock signal (VS+) is given to the 5-stage voltage multiplier.
The output voltage of the first stage of the voltage multiplier(V1) is VIN+2VAS. Consequently, the output voltage of the 5stage voltage multiplier is ideally given by

VOUT = VIN + 10 ⋅VAS = VIN + 10 ⋅ N ⋅VIN .

(1)

Strictly speaking, VAP is smaller than VIN at low VIN [10], andthe voltage drop is caused by the transistors of the voltage
doubler. Thus, actual VOUT is less than that calculated by (1)Fig. 5(a) shows a die photo of the proposed voltage
multiplier with the passive clock boost using on-chiptransformers. The chip is fabricated in a 65-nm CMOS process

265with 7 metal layers. The size of the transformer is 850μm
square. The core area including the two transformers is 2.1mm
x 0.85mm and the active area excluding the transformers is0.1mm2. Fig. 5(b) shows a layout of the on-chip transformer
with the 3-turn primary coil at the 7-th (top) metal layer and the9-turn secondary coil at the 6-th metal layer. The inductancesof the primary and secondary coils are 8.5 and 80 nH,
respectively.
IV.

MEASUREMENT RESULTS

Fig. 6 depicts the measured waveform of VP+ (Fig. 3). Themeasured frequency of the LC oscillator is 138MHz. It should
be noted that the amplitude of the measured VP+ is reduced dueto the output buffer. The measured power consumption of theLC oscillator is 280μW and 680μW at VIN of 85mV and120mV, respectively. Fig. 7 shows the measured startup
waveforms at VIN=120mV and VIN=85mV when the load

TABLE I COMPARISON WITH CONVENTIONAL LOW-VOLTAGE INPUT STEP-UP DC-DC CONVERTERS
LTC3108 [8]JSSC13 [10]External components

1 transformer

4 inductors

ASP-DAC12 [2]ISSCC14 [3]Voltage step-up mechanism

Transformer

Boost converter

CMOS process

NA

65 nm

65 nm

130 nm

0.78 mm2

0.066 mm2

This work

None (Fully integrated)
Voltage multiplier with
passive clock boost

Voltage multiplier

65 nm
1.8 mm2

Die areaNA

1.0 mm2

Minimum startup voltage(VSTART)

20mV

50mV

120mV

180mV

85mV

Frequency of boost converteror voltage multiplier

NA25 kHz

1 MHz / 20 MHz

250 kHz138 MHzNANA

8μs (@ VIN=120mV)
50μs (@ VIN=85mV)

6ms (*1)(Active area: 0.1 mm2)

Startup time (tSTART)NAMaximum
output power

600 μW

280 μW

3 μW

10 μW

10 μW

(@ VIN=500mV)(@ VIN=100mV / VOUT=1.2V)(@ VIN=120mV / VOUT=0.77V)(@ VIN=180mV / VOUT=0.5V)(@ VIN=120mV / VOUT=0.77V)(@ VIN=100mV)# of stages of voltage
multiplier (@ no load)

1035(VIN=120mV Æ VOUT=1.0V)(VIN=180mV Æ VOUT=0.62V)(VIN=120mV Æ VOUT=1.2V)(*1) Estimated from measured waveformin the published low-voltage input step-up DC-DC converters
thanks to the high clock frequency of 138MHz.

1.41.2

VIN=120mV

V. CONCLUSIONSIn this paper, the fully integrated voltage multiplier withlow VSTART and the fast startup was proposed for the energy
harvesting. The proposed passive clock boost using the two onchip transformers achieved the lowest VSTART of 85mV in the
published fully integrated voltage multiplier. The highfrequency (138MHz) clock generation with the LC oscillator
enables the shortest startup time of 50μs and 8μs at VIN of85mV and 120mV, respectively, in the published low-voltage
input step-up DC-DC converters.

VIN=110mV

VOUT (V)

1.00.80.610μW

VIN=100mV

VIN=85mV

0.4
0.200.1

110100REFERENCESOutput current (μA)[1]Fig. 8. Measured dependence of VOUT on output current.

resistance (RL) is 1MΩ and the output capacitance (COUT) is
10pF (Fig. 3). When VIN is 120mV (Fig. 7(a)), VOUT is 1.2V
and tSTART is 8μs. The lowest VIN (=VSTART) is 85mV. In thiscase (Fig. 7(b)), VOUT is 0.4V and tSTART is 50μs. Fig. 8 shows
the measured dependence of VOUT on the output current withvaried VIN. The maximum output power is 10μW when VIN is120mV and VOUT is 770mV.
In Table I, this work is compared with the previously
published step-up DC-DC converters for the energy harvesting.
Though the transformer-based LC oscillator [8] and the boost
converter [10] achieve VSTART of less than 50mV, they require
the off-chip components (transformer or inductors). In contrast,
this work provides the fully integrated solution. Compared withthe previously published fully integrated voltage multipliers [2,3], this work achieves the lowest VSTART of 85mV thanks to theproposed passive clock boost. Compared with [2] in the same
65-nm CMOS process and the same VIN of 120mV, themaximum output power is increased from 3μW to 10μW
thanks to the proposed passive clock boost, though the numberof the stages of the voltage multiplier is reduced from 10 to 5.
tSTART of this work is less than 1/1000 of [10] and the shortest

266

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