2022 IEEE Energy Conversion Congress and Exposition (ECCE) | 978-1-7281-9387-8/22/$31.00 ©2022 IEEE | DOI: 10.1109/ECCE50734.2022.9947890

Sub-0.5 ns Step, 10-bit Time Domain Digital Gate
Driver IC for Reducing Radiated EMI and Switching
Loss of SiC MOSFETs
Kohei Horii
The University of Tokyo
Tokyo, Japan

Ryuzo Morikawa
The University of Tokyo
Tokyo, Japan

Katsuhiro Hata
The University of Tokyo
Tokyo, Japankhata@iis.u-tokyo.ac.jp

Kenichi Morokuma
Mitsubishi Electric Corporation
Hyogo, Japan

Yukihiko Wada
Mitsubishi Electric Corporation
Hyogo, Japan

Yoshiko Obiraki
Mitsubishi Electric Corporation
Hyogo, Japan

Yasushige Mukunoki
Mitsubishi Electric Corporation
Hyogo, Japan

Makoto Takamiya
The University of Tokyo
Tokyo, Japanmtaka@iis.u-tokyo.ac.jp

Abstract— A sub-0.5 ns step, 10-bit time domain digital gate
driver (TD DGD) IC is proposed for SiC MOSFETs to reduce both
the radiated EMI and the switching loss (ELOSS). Unlike theconventional current-domain DGDs, the proposed TD DGD has
the advantage that the gate current is binary and only one period
is digitally changed, making it easy to search for the optimal gate
waveform that reduces both EMI and ELOSS. Using TD DGD IC
fabricated with 180-nm BCD process, the radiated EMI spectrums
from 30 MHz to 100 MHz and ELOSS are measured in the double
pulse test of a full SiC module at 600 V and 300 A. The proposed
active gate drive using TD DGD IC reduces ELOSS by 50 % and39 % compared with the conventional single-step gate drive whilesatisfying an EMI limit in turn-on and turn-off, respectively.
Keywords—EMI, switching loss, gate driver, time domain

I. INTRODUCTION
Fast switching of SiC MOSFETs reduces the switching loss
(ELOSS), while the radiated EMI increases. Active gate driver[1–2] and digital gate driver (DGD) [3–8], which digitallycontrols the gate driving current of power devices during turnon/off transients, are promising technologies to overcome thetrade-off between EMI and ELOSS. Addressing the radiated EMI
using conventional DGDs, however, has problems.
Two methods of implementing DGD can be considered, acurrent-domain (CD) DGD and a time domain (TD) DGD. Fig.
1 (a) shows CD DGD, where the time step (t) is fixed and thegate current (IG) is digitally n-bit controlled. All conventional
DGDs [3–8] are CD DGDs. Fig. 1 (b) shows TD DGD, where
IG is binary and each time step is digitally n-bit controlled. Since
the radiated EMI is generated at the moment when the SiC
MOSFET switches, in order to control the radiated EMI using
DGD, it is necessary to change IG using DGD precisely targetingthe moment of the switching. When the frequency range of theradiated EMI is from 30 MHz to 1 GHz, the range of time steps
required for DGD is from 0.5 ns (= 1 / 1 GHz / 2) to 17 ns (= 1
/ 30 MHz / 2). In the conventional CD DGDs, however, whent is reduced below 17 ns to control the radiated EMI, thenumber of steps (m) increases and the number of DGDparameter combinations explodes to (2n)m as shown in Fig. 1 (a).
For example, in DGD with n = 14 and m = 104 developed forIG(2n)m combinations
n-bit
i1

i2

(2n)m combinations

im

0A
t

IG

t

t

Time

m steps(a) Conventional current-domain
digital gate driver (CD DGD)

0A
t1

t2

tm

Time

n-bit
(b) Time-domain DGD (TD DGD)

Simplified

Simplified

2n combinations
IG

IG

Difficult to control EMI
i1

0A

2n combinations
EMI controllable

n-bit

Time

(c) Conventional current-domainstop-and-go gate drive

0A

Time
n-bit
t1
(d) Proposed time-domain stopand-go gate drive (TD SGG)

Fig. 1. Gate current (IG) waveforms in digital gate drivers.

the radiated EMI in GaN [8], it is extremely difficult to find the
optimal DGD parameters, because the number of DGDparameter combinations is (214)104. Therefore, in order to control
the radiated EMI with reducing the number of DGD parameter
combinations, TD DGD is better than CD DGD to change IG
precisely targeting the moment of the switching.
In addition, in order to reduce the number of DGD parameter
combinations from (2n)m to 2n, a current-domain stop-and-gogate drive shown in Fig. 1 (c) is reported in [9, 10], while this is
not suitable for the radiated EMI control, because the timing
control is not possible. To solve the problems, a time-domainstop-and-go gate drive (TD SGG) shown in Fig. 1 (d) is
proposed in this paper. By digitally controlling only t1 in 10-bit,
sub-0.5 ns steps, the proposed TD SGG reduces ELOSS by 50 %and 39 % compared with the conventional single-step gate drive(SSG) while satisfying an EMI limit in turn-on and turn-off,
respectively.

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II. TIME DOMAIN DIGITAL GATE DRIVER (TD DGD) IC
Figs. 2 and 3 show a circuit schematic and a timing chart ofthe proposed TD DGD IC, respectively. The output voltage
swing is 30 V to achieve VGS from − 15 V to 15 V for SiC
MOSFETs. In order to realize both the conventional SSG andthe proposed TD SGG, which will be explained later in Figs. 8
and 9, using the same gate driver IC and compare them, bothCD DGD and TD DGD functions are included in the developed
TD DGD IC. TD DGD IC has a total of 26 control bits including
T1 [9:0], T2 [3:0], I1 [5:0], and I2 [5:0]. By using the digitallycontrolled delay line (DCDL) in TD DGD IC, time of the firststep (t1) can be changed from 0 s to 470 ns in 10-bit, 459-ps
steps using T1 [9:0], and time of the second step (t2) can bechanged from 0 s to 90 ns in 4-bit, 6-ns steps using T2 [3:0]. The
circuit schematic of the 6-bit output stage in Fig. 2 is designedwith reference to [7]. IG can be digitally changed from 0 A to
22 A in 6-bit steps of 350 mA depending on I1 [5:0] and I2 [5:0].
nPMOS is an integer from 0 to 63 indicating IG at turn-on and IG= nPMOS × 350 mA. Similarly, nNMOS is an integer from 0 to 63
indicating IG at turn-off.

Fig. 5 shows the measured t1 vs. T1 [9:0] to verify the time stepand the linearity of DCDL. The 10-bit digital control of t1 in
sub-0.5 ns step from 0 s to 470 ns is successfully demonstrated.
The measured time step is 459 ps (= 470 ns / 1023).
III. MEASURED RADIATED EMI AND SWITCHING LOSS OF SIC
MOSFETS
A. Measurement Setup
In order to show the advantage of the proposed TD SGG
using TD DGD IC, the radiated EMI and ELOSS are measured
and compared with the conventional SSG. Figs. 6 and 7 show acircuit schematic and a measurement setup of the double pulse
test using the developed TD DGD IC and a full SiC module(FMF400BX-24A, 1200 V, 400 A) at 25 °C, 600 V, and 300 A,
respectively. In order to measure the radiated EMI, a magnetic
field probe (RS H400–1, HZ–15, Rohde & Schwarz) is fixed justabove the switching terminal of the SiC module and the probe
output voltage (VEMI) waveform at turn-on and turn-off ismeasured with a 1.25-GSa/s oscilloscope and Fouriertransformed. Figs. 8 (a) and (b) show timing charts for the turn-Fig. 4 shows a die micrograph of TD DGD IC fabricatedwith 180-nm BCD process. The die size is 4.5 mm by 3.1 mm.
Time-domain
digital gate driver (TD DGD) IC

Level
shifterIN
T1 [9:0]T2 [3:0]I1 [5:0]I2 [5:0]
Enable5V

15

SR

DCDL Timing

1WP
IO

15 V
32WP
32IO

SiC
IG

IO
nNMOS

32IO

VGS

1WN

32WN

15 V

SR

3.1 mm

nPMOS

5V

DCDL

4.5 mmDigitally controlled delay line (DCDL), shift register (SR)Fig. 2. Circuit schematic of proposed time domain digital gate driver (TDDGD) IC.

Fig. 4. Die micrograph of TD DGD IC fabricated with 180-nm BCD
process.

500
IN

On
T1 [9:0] T2 [3:0]

6-bit
pMOS
drivers

6-bit
nMOS
driversOff
T1 [9:0] T2 [3:0]

470 nsMeasured400

TimingI1 [5:0]0I2 [5:0]

63

nNMOS
IG

t1 [ns]63

nPMOS

I1 [5:0]0I2 [5:0]

0A
15 V

300
200

0
0

VGS 0 V
−15 V

t1

t2

t1

t2

Fig. 3. Timing chart of proposed TD DGD IC.

470 ns= 459 ps / step
1023

100

200

400

600
T1 [9:0]

800

1000

Fig. 5. Measured t1 vs. T1 [9:0] of digitally controlled delay line (DCDL) in
TD DGD IC.

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TD SGG, respectively. In SSG, I1 [5:0] is varied, which emulates
a conventional gate driver with varied gate resistance. In TD
SGG, T1 [9:0] is varied under the conditions of T2 [3:0] = 15,
corresponding to t2 = 90 ns (= 6 ns × 15), I1 [5:0] = 63, and I2[5:0] = 0.

Full-SiC
module
300 A
600 V
Magnetic
field probeIG

TD DGD IC

VDS

VGS

50 W
VEMI

ID

Fig. 6. Circuit schematic of double pulse test to measure radiated EMI.

TD DGD IC

Full-SiC module

Fig. 7. Measurement setup using TD DGD IC and full SiC module tomeasure radiated EMI.

Off
63

nPMOS

On
I1 [5:0]

0

63

IN

Off

0
T1 [9:0] 90 ns

63

nNMOS

0
(a) Conventional single-stepgate drive (SSG)

On

63

nPMOS

nNMOS

0
(b) Proposed time-domain stopand-go gate drive (TD SGG)

Fig. 8. Timing charts for turn-on measurements.

IN

On

Off

63
0
63

nNMOS

IN

On

Off

63

nPMOS

nPMOS
I1 [5:0]0(a) Conventional single-stepgate drive (SSG)

0
63

nNMOS

AEXCESS =

100 MHz

30 MHz max(VA, VALIMIT ) − VALIMIT −6df  10 (1)VALIMITMEASURE

where VAMEASURE and VALIMIT are the measured relative
voltage amplitude of VEMI and the voltage amplitude of the
EMI limit in units of dB, respectively, and f is the frequency.
Since measurements of the radiated EMI are made using amagnetic field probe rather than a standard antenna, this paper
discusses relative instead of absolute values of the radiatedEMI. In this paper, AEXCESS is defined in the range of 30 MHz
to 100 MHz, because the developed TD DGD IC is effective
for the radiated EMI from 30 MHz to 100 MHz. AEXCESS of zeromeans that the measured EMI spectrum satisfies the EMI limit.
In this paper, two types of VALIMIT’s are defined: “Limit 1” is
VALIMIT = − 15 dB and “Limit 2” is VALIMIT = − 5 dB.

Magnetic
field probe

IN

B. Definition of EMI Evaluation Indicator
In order to quantitatively evaluate EMI, an excessive
spectrum area (AEXCESS), where the EMI spectrum exceeds an
EMI limit, is defined as Eq. (1) [6].

0T1 [9:0] 90 ns(b) Proposed time-domain stopand-go gate drive (TD SGG)

Fig. 9. Timing charts for turn-off measurements.

on measurement of the conventional SSG and the proposed TD
SGG, respectively. Figs. 9 (a) and (b) show timing charts for theturn-off measurement of the conventional SSG and the proposed

C. Turn-On Measurements
In this section, the measured radiated EMI and ELOSS at turnon are shown. Figs. 10 (a) and (b) show the measured ELOSS vs.
AEXCESS in turn-on at Limit 1 and Limit 2, respectively. The
conventional SSG and the proposed TD SGG are compared. In
Fig. 10 (a), when I1 [5:0] is increased from 8 to 63 in theconventional SSG, AEXCESS is increased and ELOSS is reduced,
which clearly shows the trade-off relationship between EMI and
ELOSS. In Fig. 10 (a), when T1 [9:0] is increased from 100 to 400
in the proposed TD SGG, the measurement results circled
counterclockwise from the bottom right point and return to thebottom right point. In Fig. 10 (a), none of the measurement
points achieved AEXCESS = 0, while many measurement points
achieved AEXCESS = 0 in Fig. 10 (b), because Limit 1 is lower
than Limit 2. Please note that optimization of t1 with 459-ps
step is very important because, depending on the value of T1[9:0], there are both cases where the proposed TD SGG has
lower ELOSS and AEXCESS than the conventional SSG and cases
where TD SGG has higher ELOSS and AEXCESS than SSG [10]. In
this paper, the best gate drive is defined as the one that satisfies
Limit 2 (AEXCESS = 0) and has the lowest ELOSS in Fig. 10 (b). In
the following, three points including Point A, Point B, and PointC in Fig. 10 (b) will be focused on and are compared. Point A isthe best gate drive in the conventional SSG with I1 [5:0] = 27,
Point B is the best gate drive in the proposed TD SGG with T1[9:0] = 367, corresponding to t1 = 168 ns (= 459 ps × 367), andPoint C is the highest drivability in the conventional SSG withI1 [5:0] = 63. Compared with Point A, the proposed Point B
reduces ELOSS from 2.6 mJ to 1.3 mJ by 50 % at AEXCESS = 0.
Fig. 11 shows the measured radiated EMI spectrums of Point
A to Point C at turn-on. Point A and the proposed Point B satisfy
Limit 2, while Point C violates Limit 2. Figs. 12 (a) to (c) show

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10

Failed EMI
Conv. SSG
TD SGGI1 [5:0] = 8

ELOSS [mJ]8

Turn-onPoint A(I1 [5:0] = 27)

6
4

Point C(I1 [5:0] = 63)

2

1
2
3
4
AEXCESS @ Limit 1 [a.u.](a) Limit 1: VALIMIT = −15 dB

Passed EMI
10

Failed EMI

I1 [5:0] = 8

8

ELOSS [mJ]0−5Turn-on
Proposed Point B

Point C

Point A

Limit 2−10
−15

Limit 1

−20
−25
−30
30

40

50 60 70 80 90 100
Frequency [MHz]Proposed Point B

00Conv. SSG
TD SGG
Turn-on6
Point A(I1 [5:0] = 27)

420

Relative amplitude of VEMI [dB]

Passed EMI

Point C(I1 [5:0] = 63)−50%
Proposed Point B

0

0.2
0.15
0.1
AEXCESS @ Limit 2 [a.u.]
0.05(b) Limit 2 : VALIMIT = −5 dB
Fig. 10. Measured ELOSS vs. AEXCESS in turn-on at Limit 1 and Limit 2. The
conventional SSG and the proposed TD SGG are compared.

Fig. 11. Measured radiated EMI spectrums of Point A to Point C at turn-on.

the measured waveforms of VGS, VDS, ID, and VEMI and the timing
chart of nPMOS at turn-on in Point A, Point B, and Point C,
respectively. First, Point A and Point B are compared. Looking
at the waveforms of VDS and ID in Figs. 12 (a) and (b), it is clearthat ELOSS of Point B is smaller than that of Point A. Next, Point
B and Point C are compared. The large ringing of VEMI in Fig.
12 (c) is the cause of large EMI of Point C in Fig. 11. In Fig. 12(b), a temporary drop in VGS waveform caused by the proposed
TD SGG can be clearly seen. In Point B, the temporary drop in
VGS waveform reduces the ringing of VEMI in Fig. 12 (b), thereby
reducing EMI in Fig. 11.
D. Turn-Off Measurements
In this section, the measured radiated EMI and ELOSS at turnoff are shown. Almost similar results are obtained for turn-on
and turn-off. Figs. 13 (a) and (b) show the measured ELOSS vs.
AEXCESS in turn-off at Limit 1 and Limit 2, respectively. The
conventional SSG and the proposed TD SGG are compared. In
Fig. 13 (a), when I1 [5:0] is increased from 8 to 63 in theconventional SSG, AEXCESS is increased and ELOSS is reduced,
which clearly shows the trade-off relationship between EMI and
ELOSS. In Fig. 13 (a), when T1 [9:0] is increased from 100 to 400
in the proposed TD SGG, the measurement results circled
counterclockwise from the bottom right point and return to thebottom right point. In Fig. 13 (a), none of the measurement
points achieved AEXCESS = 0, while many measurement points
achieved AEXCESS = 0 in Fig. 13 (b), because Limit 1 is lower
than Limit 2. In this paper, the best gate drive is defined as theone that satisfies Limit 2 (AEXCESS = 0) and has the lowest ELOSSin Fig. 13 (b). In the following, four points including Point D to
Point G in Fig. 13 (b) will be focused on and are compared. Point
D is the best gate drive in the conventional SSG with I1 [5:0] =11, Point E is the best gate drive in the proposed TD SGG with
T1 [9:0] = 273, corresponding to t1 = 125 ns (= 459 ps × 273),
and Point F is the highest drivability in the conventional SSG
with I1 [5:0] = 63. Point G is the worst gate drive in the proposed
TD SGG with T1 [9:0] = 222, corresponding to t1 = 102 ns (=Authorized licensed use limited to: University of Tokyo. Downloaded on April 09,2023 at 06:44:06 UTC from IEEE Xplore. Restrictions apply.

ELOSS : 2.6 mJ

ELOSS : 1.3 mJ
ID: 125 A/div

ID: 125 A/div

VGS: 10 V/div
0

ELOSS : 1.3 mJ
ID: 125 A/div

VGS: 10 V/div

VGS: 10 V/div00

VDS: 150 V/div

VDS: 150 V/div
100 ns/div

100 ns/div
VEMI: 0.1 V/div

VDS: 150 V/div
100 ns/div

VEMI: 0.1 V/div

0

0

nPMOS

nPMOS
27

0

Time
(a) Point A

VEMI: 0.1 V/div
0

63

nPMOS

63

0
168 ns 90 ns(b) Proposed Point B

Time

63

0

Time
(c) Point C

Fig. 12. Measured waveforms of VGS, VDS, ID, and VEMI and the timing chart of nPMOS at turn-on in Point A to Point C.

459 ps × 222), which will be discussed later. Compared with
Point D, the proposed Point E reduces ELOSS from 12 mJ to 7.3
mJ by 39 % at AEXCESS = 0.
Fig. 14 shows the measured radiated EMI spectrums of Point
D to Point G at turn-off. Point D and the proposed Point E satisfy
Limit 2, while Point F and Point G violate Limit 2. Figs. 15 (a)to (d) show the measured waveforms of VGS, VDS, ID, and VEMI
and the timing chart of nNMOS at turn-off in Point D to Point G,
respectively. First, Point D and Point E are compared. Looking
at the waveforms of VDS and ID in Figs. 15 (a) and (b), it is clearthat ELOSS of Point E is smaller than that of Point D. Next, Point
E and Point F in Figs. 15 (b) and (c) are compared. In Fig. 15(b), a temporary rise in VGS waveform caused by the proposed
TD SGG can be clearly seen, which reduces the ringing of VDS,
ID, and VEMI, thereby reducing EMI in Fig. 14.
Interesting Point G which is the worst gate drive in the
proposed TD SGG is discussed here. Fig. 13 (b) shows that Point
G is the very worst point because it has more ELOSS than the pointof the conventional SSG with I1 [5:0] = 8, which has the largest
ELOSS in the conventional SSG, and more EMI than Point F,
which has the largest EMI in the conventional SSG. The worst
point is the same as the phenomenon observed in [10], whichclaims that "stop-and-go gate driving is a double-edged sword,"
and the discussion in [10] helps us understand the cause. As
shown in Fig. 15 (d), when the first gate drive of the stop-andgo drive (102 ns in Fig. 15 (d)) is insufficient, a halfway turn-off
occurs, resulting in increased ELOSS because VDS rises but ID
remains high during the 90-ns period. For practical use, theworst gate drive (Point G) should be avoided at all costs, making
the optimization of t1 very important in the proposed TD SGG.
Comparing the turn-on VEMI waveforms (Fig. 12) and theturn-off VEMI waveforms (Fig. 15), the turn-on VEMI waveforms
contain high-frequency ringing, while the turn-off VEMI
waveforms do not, which results in a significant difference inthe magnitude of the high-frequency components of the turn-on
EMI spectrum (Fig. 11) and the turn-off EMI spectrum (Fig. 14).
The reason for the difference is that the main circuit current
loops are different for turn-on and turn-off. In the measurements
at turn-on, the high-frequency ringing is observed in VEMI due tothe ESL of the main circuit capacitor in Fig. 6. As evidence, thehigh-frequency ringing in VEMI disappeared when the main
circuit capacitor was replaced with a capacitor with a smaller
ESL.
E. Comparison with Previous Works
Table I shows a comparison table of DGD ICs. Allconventional DGDs [4–5, 7–8] are CD DGDs, not TD DGD.
This work is the first time-domain DGD achieving 459-ps step,
10-bit timing control. The output voltage swing of this work is
the largest.
IV. CONCLUSIONSThis work is the first time-domain DGD achieving 459-ps
step, 10-bit timing control. In the measurement of the radiatedEMI spectrums from 30 MHz to 100 MHz in the full SiC
module at 600 V and 300 A, the proposed TD SGG using TD

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20
18
16
14
12

Failed EMI
Point GI1 [5:0] = 8

Point D(I1 [5:0] = 11)

10
Turn-off8
6 Proposed Point E
4
Point F
Conv. SSG
(I
[5:0]
= 63)
2
1
TD SGG0
0 0.5 1 1.5
2 2.5 3AEXCESS @ Limit 1 [a.u.](a) Limit 1: VALIMIT = −15 dB

Relative amplitude of VEMI [dB]

ELOSS [mJ]

Passed EMI

ELOSS [mJ]

20
18
16
14
12

Failed EMI

Point G

Point D(I1 [5:0] = 11)

10 −39%Turn-off8
6 Proposed Point E
4
Point F
Conv. SSG
(I
[5:0]
= 63)
1
2
TD SGG
0
0.2
0
0.1
0.3
AEXCESS @ Limit 2 [a.u.](b) Limit 2 : VALIMIT = −5 dB

Fig. 13. Measured ELOSS vs. AEXCESS in turn-off at Limit 1 and Limit 2. The
conventional SSG and the proposed TD SGG are compared.

Limit 2

Proposed Point E

Point D

−10

Point F

−15

Limit 1

−20
−25
−30
30

40

50 60 70 80 90 100
Frequency [MHz]Fig. 14. Measured radiated EMI spectrums of Point D to Point G at turn-off.
Table I. Comparison table of DGD ICs.
ISPSD’20[5]

ISPSD’21[7]

GaN FET

180 nm BCD

180 nm
BCD

15 V
No

TIA’17 [4]Target power
Si IGBT &device
SiC MOSFET

Outputvoltage swing
Time-domain
digital control
Timeresolution
Time steps

I1 [5:0] = 8

Point G

−5

Process

Passed EMI

Turn-off0

Levels of IG
Max. IG

TPEL’21 [8]This work

GaN FETGaN FET

SiC MOSFET

180 nmBCD

180 nm HV
CMOS

180 nm BCD

3.3 V

5V

5V

30 V

No

No

No

Yes

40 ns

0.3–3.0 ns

3.3 nsNo limit

8

16

6 bit

7 bit

6 bit

5A

3.3 V / 0.5 Ω= 6.6 A

5A

1.25 ns (coarse), t1: 459 ps×10 bit
100 ps (fine)t2: 6 ns×4 bit
104
8 bit (coarse),
6 bit (fine)
5 V / 0.12 Ω= 42 A

2
6 bit
22 A

DGD IC fabricated with 180-nm BCD process reduces ELOSS
from 2.6 mJ to 1.3 mJ by 50 % and from 12 mJ to 7.3 mJ by
39 % compared with the conventional SSG while satisfying the
EMI Limit 2 of − 5 dB in turn-on and turn-off, respectively.
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[1]

[2]

[3]

[4]

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a simulated annealing algorithm,” IEEE Trans. on Industry Applications,

ELOSS : 12 mJ

VDS: 300 V/div

ELOSS : 7.3 mJ

ELOSS : 7.1 mJ

VDS: 300 V/div

VDS: 300 V/div

ID: 125 A/div

ID: 125 A/div

ID: 125 A/div

VGS: 10 V/div

VGS: 10 V/div

VGS: 10 V/div

0

0

0

200 ns/div

200 ns/div

200 ns/div

VEMI: 0.1 V/div

VEMI: 0.1 V/div

VEMI: 0.1 V/div
0

0

nNMOS

nNMOS

0

11
Time

0

63

nNMOS

63

0

Time

125 ns 90 ns(b) Proposed Point E
ELOSS : 18 mJ(a) Point D

63

0

Time
(c) Point F

VDS: 300 V/div
ID: 125 A/div
VGS: 10 V/div0
200 ns/div
VEMI: 0.1 V/div
0
nNMOS
63

63

0
102 ns 90 ns(d) Point G

Time

Fig. 15. Measured waveforms of VGS, VDS, ID, and VEMI and the timing chart of nNMOS at turn-off in Point D to Point G.

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