A Charge-Domain Auto- and Cross-Correlation Based IR-UWB Receiver with Powerand Area-efficient PLL for 62.5ps Step Data Synchronization in 65nm CMOS
Lechang Liu, Takayasu Sakurai and Makoto Takamiya
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
Abstract
A 100Mb/s, 1.71mW DC-960MHz band impulse radio
ultra-wideband (IR-UWB) receiver is developed in 1.2V
65nm CMOS. A novel auto- and cross-correlation based
synchronization scheme is proposed to achieve 62.5ps step
data synchronization with a 2-GHz 8-phase PLL clock
generator. The developed UWB receiver with the proposed
power- and area-efficient PLL achieves the low energy
consumption of 17.1pJ/bit.
Introduction
Correlation-based receivers [1] attain superior noise
performance and robust narrowband interference suppression
at the expense of increased power consumption andincreased circuit complexity over their thresholding-based
counterparts [2]. To reduce the power consumption of thecorrelation-based receiver, a 1.28mW 100Mb/s UWB
receiver with charge-domain correlator and embedded
sliding scheme for data synchronization is developed in [1]where there is an inherent assumption that the timing
mismatch between the incoming signal and the template of
the correlator is zero when the synchronization is achieved.
Fig. 1 shows the simulated BER dependency on timing
mismatch. When the timing mismatch is reduced from 500ps
to 62.5ps, Eb/N0 can be improved by 7.8dB for the white
noise and 5.8dB for the narrowband interference.
To achieve 62.5ps timing mismatch, a 16-GHz PLL clock
generator and high resolution comparators are required in theconventional topology [1] and the receiver power
consumption will be increased by eight times. This work
aims to minimize this power consumption with 2-GHz8-phase PLL clock generator by a novel auto- andcross-correlation based synchronization scheme. To further
reduce the power consumption of the capacitance multiplierused in the conventional area-efficient PLL [3], a dual
charge-pump PLL is proposed to scale up the capacitance ofthe loop filter without extra charge-pump current.
Synchronization Scheme
The architecture of the proposed IR-UWB receiver isshown in Fig. 2. It consists of one dual charge-pump PLL formulti-phase clock generation and two coupled delay-locked
loops (DLL) for coarse and fine timing alignment. Fig. 3
shows the correlator output dependency on timing mismatch
ΔT between the signal and the templates of the correlators.
Data synchronization is achieved in two steps. When thetiming mismatch ΔT is larger than 0.5ns, the upper coarse
timing alignment loop is activated and the incoming signal isauto-correlated with a stored replica of the signal shape. The
upper loop can keep sliding the phase of the sampling clockwith the conventional unidirectional sliding scheme until theauto-correlation result Vcor1 is higher than the threshold of
the comparators. When the timing mismatch is equal to orless than 0.5ns, the lower fine timing alignment loop is
activated and the incoming signal is cross-correlated against
a stored replica of the derivative of the signal pulse shape.
This loop can keep switching the multi-phase output of thePLL until the timing mismatch ΔT is less than 62.5ps.
The incoming BPSK-modulated Gaussian first-orderderivative pulse and the discrete templates for the auto- andcross-correlators are shown in Fig.4 (a). The bandwidth of
the incoming pulse is from DC to 960MHz and it is sampled
at the rate of 2GSa/s. The charge-domain sampling correlator

978-1-4244-7641-1/10/$26.00 ©2010 IEEEin [1] is used for the auto-correlation directly. The derivative
operation in the cross-correlator can be implemented bychanging the values of the template capacitances andreconfiguring the addition and the subtraction circuits. Fig.
4(b) and Fig. 4(c) show the circuit schematics for thecross-correlator in sampling mode and summing mode. The
control units for coarse and fine tuning loops are shown in
Fig.5 (a) and Fig.5 (b), respectively. Fig. 6 shows the timing
chart for the entire synchronization process. In the worst casedata synchronization can be finished within nineteen phaseslides and four phase switches.
Dual Charge-Pump Phase-Locked Loop
Multi-phase PLL is a critical component for the samplingclock generation in the proposed UWB receiver. The loop
filter of the PLL is a barrier in fully integrating the receiverbecause of its large integrating capacitor. To reduce the chiparea of the PLL, a capacitance multiplier is proposed to scale
up the on-chip capacitor in [3]. The capacitance multipliercan be simplified to the dual charge-pump architecture in Fig.
7(a) noting that the capacitance Cp often remains below Cz
by roughly a factor of 15 and thus the current flowing
through Cp can be neglected. This architecture reduces thechip area at the cost of an extra (1-1/k)Ip charge-pumpcurrent consumption, where k is the capacitance scaling
factor and Ip is the normal charge-pump current. This extra
charge-pump current can be eliminated by reversing theorder of the resistor and the capacitor in the filter and biasing
the filter to VDD/2. As shown in Fig. 7(b), the total current of
the two charge-pumps is reduced to the normal value Ip while
the capacitance is multiplied by k times. In this work k isequal to 8 and a 28pF capacitance is scaled up to 224pF.
Experimental Results
The proposed UWB receiver without the front-end
amplifier was designed and fabricated in 1.2V 65nm CMOS
process. The chip micrograph and layout are shown in Fig. 8 .
Power consumption and area occupation are summarized inTable I. Loop stability of the proposed dual charge-pump
PLL can be verified by measuring the VCO control voltage
in Fig. 9 (a). Figure 9 (b) shows the measured jitter of 1.33ps(rms) and 15.76ps (peak-to-peak). To verify the fine-tuning
time step, the phase-switching loop with cross-correlation
was measured separately. As show in Fig.10 (a), with eachleft or right shifting control signal, the sampling clock period
is increased or decreased by 62.5ps from 10ns. Fig.10 (b)shows the measured waveforms when the synchronization isachieved. The comparison with the state-of-the-art
correlation-based IR-UWB receivers is shown in Table II.
The proposed UWB receiver with the area- andpower-efficient PLL achieves the energy consumption of
17.1pJ/bit with the 62.5-ps timing step for datasynchronization.
Acknowledgment
This work is partially supported by CREST/JST.
References[1] L. Liu, et al., Symp. on VLSI Circuits, pp. 146-147, 2009.
[2] L. Liu, et al., Symp. on VLSI Circuits, pp. 118-119, 2008.
[3] K. Shu, et al., JSSC, vol. 38, pp. 866-874, Jun. 2002.
[4] Y. Zheng, et al., ISSCC, pp. 116-117, 2006.
[5] J. Ryckaert, et al., ISSCC, pp. 114-115, 2006.
[6] M. Verhelst, et al., ISSCC, pp. 250-251, 2009.

2010 Symposium on VLSI Circuits/Technical Digest of Technical Papers

27Template

BPSKInterference([1]: ΔT=500ps)

0.01
10-2

White Noise(This work:ΔT=62.5ps)

Interference(This work:ΔT=62.5ps)
5.8dB

10-4
1E-4-30-30-20-20

01010LPF

φcCP CP

2GHz8PhaseVCOMUX

CLK

CLK’
φc

Cross-Correlator
with Discrete
Vcor2
Template:
Fig.4 (b) (c)7.8dB-10-10
E0b/N
Eb/N
(dB)
0 (dB)

Sliding-Scheme
Control: Fig.5(a)Sampling
Clock Gen.
Fig.5(a)

Vin

AMP

1E-3
10-3

Vcor1

Auto-Correlator
with Discrete
Template: [1].........

Incoming
SignalBER

TimingMismatch

Bit Error RateΔT:

Coarse Timing Alignment Loop [1]White Noise([1]: ΔT=500ps)

0.1-1
10REF

PFD

OUT
/N

Phase-Switching
Control: Fig.5(b)SELDual Charge
Pump PLL

Fine Timing Alignment Loop

Fig. 2. Proposed IR-UWB receiver with dual charge-pump PLL.

Fig. 1. Simulated BER dependency on timing mismatch (ΔT).

Incoming Signal
Voltage

Cross-correlation for fine alignment
Auto-correlation for
Auto-correlation forcoarse alignment
coarse alignment

Correlator Outputs (a.u.)

1.0

Vcor1: AutoCorrelation(Sliding Scheme)62. 5p-1.0-4-20
ΔT (ns)4
Bidirectional
Phase Switching

Q

Sampling Clock Generator

Sliding-Scheme Control Unit

CLK’/5D

OUT OUT

RM/4

SEL(100Mb/s)

SRDNφcC23φ3φ4φ5C23φrφrC24C23

φr

V /2-ΔVthVcor1 DD

101

Phase switching forfine alignment

Synchronizationachieved

00

10

11REF
DIV0Vctrl
PFD

VDD/2-ΔVd φc(1-1/k)Ip

Ip/k
10.5ns10ns

10.0625ns

REF
DIV

Vctrl
PFD

Cz/k
Rz

0OUT

10

10

1

Itotal=Ip/k+(1-1/k)Ip=Ip(b)

Fig. 5. (a) Sliding-scheme control unit and sampling clock generator. Fig. 6. Timing chart for coarse and(b) Phase-switching control unit.
fine timing alignment.

VCOCp

VDD/2(b)(a)Cp

Itotal=Ip+(1-1/k)Ip≈2Ip(a)

SR

Vcor2

VCORz

UP
RM

VDD/2+ΔVdC21(1-1/k)IpCz/k

φc

φ1 φ7 φc φrφr

φr
C22

Vcor2

CLK’

VDD/2+ΔVthφr

φr

φr

DOUT

C21(c)DN

Edge
Combiner

C22

Vcor2

Vcor2

Q Q

φ7φr

Vcor1

SL

OUT
UP

C24Fig. 4. (a) Incoming signal and templates. (b) Cross-correlator in sampling mode.
(b) Cross-correlator in summing and averaging mode.
Sliding scheme forcoarse alignmentVinφ6φ5Ip

Bi-DirectionalShift Register

Addition

φ4C23

Averaging(a)Fig. 3. Dependence of correlator output on timing mismatch (ΔT) forauto- and cross-correlation.

CLKC22

CLKφ1Vin
φ2 Addition
φ3φ4 Subtraction
φr
φ5φr
C22
C21
φ6
VDD/2
φ7 Addition
φc Comparison
φr
φr Summing&s

ΔT2

φ3(b)

0

Data “0”

φ2

C21
VDD/2

Crosscorrelation

C22
C21
C23
C24-ΔVTH
Vcor2: CrossCorrelation(Phase Switching )Cap. Discrete Templates
AutoC13
C12
correlation
C1１

Unidirectional
Sliding Scheme

ΔVTH

Subtraction

Addition
Vinφ1s0p50

ΔT0.0-0.56ns0

Data “1”

0.5

4ns

VDD/2

Fig. 7. Dual charge-pump PLL. (a) Conventional
topology. (b) Proposed topology.

Table. I
Performance summary.
Capacitor

PLL
Power(mW)

Sliding
Control

Auto-Correlator

Frequency Divider

Cross-Correlator

Bi-Directional Shift Register

Clock Switching
Generator Control

CoreCharge
Pump

0.48

VCO

0.52

Divider
&PFD

0.12

Total

1.12

Coarse &Fine Tuning
Loop Power (mW)

VCO

1.71

Energy per bit(pJ/bit)

17.1

Area(μm2)

Res

Capacitance

49900

Core9200

Fig. 8. Chip micrograph and layout.
1111000000VinVctrl

0.59

Total Power (mW)
ChargePump≈ 800ns(a)(b)

Fig. 9. Measurement results for PLL. (a) Measured VCO control voltage for frequency jump.
(b) Measured PLL output jitter.
Table. II Comparison with state-of-the-art
correlation-based IR-UWB receivers.

1 0 0 1 1 0 1 0Vin

REF

REF

SP

φ510.0625ns

Technology(CMOS)

20 Pulses

9.9375ns

SN

OUT

(a)

1 0 0 1 1 0 1 010ns(b)

ISSCC’06[4]

ISSCC’06[5]ISSCC’09[6]

ThisWork

0.18μm

0.18μm

0.13μm

65nm

Supply Voltage1.8V

1.8V

1.2V

1.2V

Data Rate

400 Mb/s

20 Mb/s

40 Mb/s

100 Mb/s

Frequency Band

0-960MHz

3-10GHz

3-10GHz

0-960MHzCoarse1ns1nsNA

500ps

Fine

100ps

60ps

800ps

62.5psPowerConsumption

81mW(with frontend)

11.1mW(w/ofront-end)

2.5mW(w/ofront-end)

1.71mW(w/ofront-end)

Energy per bit

202.5pJ/bit

555pJ/bit

62.5pJ/bit

17.1pJ/bit

Timing
Step

Fig. 10. Measurement results for IR-UWB receiver. (a) Phase switching for fine timing alignment.
(b) Measured waveforms in synchronization.

978-1-4244-7641-1/10/$26.00 ©2010 IEEE

2010 Symposium on VLSI Circuits/Technical Digest of Technical Papers

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