44th meeting of IFIP Working Group 10.4
on Dependable Computing and Fault Tolerance,
Workshop on "Hardware Design and Dependability"

June 28, 2003

Challenges to Dependable VLSIs
Makoto Takamiya
Silicon Systems Research Laboratories
NEC Corporation
taka@mel.cl.nec.co.jp

Outline• Technology trend of VLSIs• Dependability issues
 Power / signal integrity problems at design-phase Device variation problems at manufacturing-phase Degradation problems after shipping• Future Dependable VLSIs
 Autonomous Reconfigurable Cell Array (ARCA)• Summary2Clock frequency (MHz)MPU Clock Frequency Trend

33.2 GHz (now)↓310-ps clock cycle

Ref [1]Year• Pico-second timing-design is required.

4MPU Power-Supply Trend
700720 A !!
CurrentVoltage

1.2
1.0

600
0.8

500

0.6

400
300

0.4

200
1000

Power

0.2

MPU

2002 2004 2006 2008 2010 2012 2014 2016

Year

Power supply voltage (V)Power (W)Power supply current (A)

800

0.0
Ref [2]• Power-supply-current increases rapidly, even though the supplyvoltage decreases.
• Large current causes power-integrity and electro-migration problems.

Number of transistors per chip

MPU Transistor Count Trend

5

Comparable tothe populationof the world !!
(6 billion)

1.5x increase
per year

Ref [1]Year• A lot of functions are integrated on a chip.
• Design complexity increases.
• 7σ-control of device variations is required for 1 billion transistors.

MPU Feature Size Trend• Transistor size is aggressively scaled into nanometerregion.

6

7

MOS Transistor
Gate

Gate insulator

SourceDrain

Comparable to the lattice constant of silicon (0.54 nm)
Ref [1]• 50-nm gate length transistor with the atomic-level gateinsulator

Introduction of New Materials

8

From Al to Cu Interconnect for low resistance
From SiO2 to low-k dielectric
for low capacitance
Gate
From SiO2
to high-kgate dielectric
for low leakage
From Sito SiGe channel
for large current
Ref [1,3]• New materials are introduced to break through the scaling limit.
• New materials cause novel reliability problems.

9What Threatens the Dependability of VLSI?
Trend of VLSIs

Dependability issues

High speed

Power / signal integrity problems
at design-phasedeterministic

Low voltage
Large current
Many transistors
Atomic-level fabrication
New materialsDevice variation problems
at manufacturing-phasestatistical
Degradation problems
after shipping
time-dependent• The dependability of VLSI is threatened by a lot of problems at3-phases.
• All these problems are difficult to predict accurately.
• The prompt solutions to these problems are essential to keep
the continuous evolution of VLSIs.

Outline• Technology trend of VLSIs• Dependability issues
 Power / signal integrity problems at design-phase Device variation problems at manufacturing-phase Degradation problems after shipping• Future Dependable VLSIs
 Autonomous Reconfigurable Cell Array (ARCA)• Summary1011Power / Signal Integrity Problems at Design-Phase
Signal Integrity Problems

Power Integrity Problems
Power supply noiseVoltage

Real waveform

Vdd

Ideal

LRi

Gnd
10 ps

Package

LSITime• These problems could be ignored in the past, however,they increase the influence on the circuits performancewith the high-speed, low-voltage, and large-current trend.
• Now, they are the main cause of the failure of LSI design.

Power Integrity Problems
Vdd

LRVnoise = LiGnd
Package

LSI12di+ Ri
dtOn-chip
decouplingcapacitor(Cd)• Modeling of the power-supply-noise is difficult, because;(1) The power-supply-network is large-scale.
Ex.) 5000 pads for Vdd/Gnd,
Total length of Vdd/Gnd wires on 20 mm-square-chip is 1.1 km!!

(2) The supply-current changes with the operation of LSI.
• Typical measures against the noise is Cd, however, Cd occupies
20 % of a chip. → Increased chip area
• Verification of the model is also difficult, because themeasurement of the on-chip noise waveform is hard.
→ On-chip oscilloscope circuits is developed.

Off-Chip vs. On-chip Measurement
Techniques
Off-chip Measurement

On-chip Measurement
10 ns?
100 psLSI

OscilloscopeCircuits

LSILarge Parasitic L, C

Time scale of outputs isexpanded by sampling

Low BandwidthHigh Bandwidth• On-chip very fast waveforms can be measured by the onchip measurement using the oscilloscope circuits.

13

On-Chip Oscilloscope Circuits

141.2V, 0.13µm CMOS

Oscilloscope circuits
Noise
SourceSamplingheads(1550µm2x8)
Ref [4]

Measured Power-Supply-Noiseby Oscilloscope Circuits

151.6Calibrated Voltage [V]1.4

Vdd=1.2V

1.2
1.00.8SupplyVoltage

Off-chipSupplyVoltage

4.5 ns cycle

0.60.40.2

GroundVoltage

0.0-0.20246810Off-chip
GroundVoltage

Calibrated Time [ns]• These accurate measured results are used to calibrate thepower-supply-noise model.

16Signal Integrity Problems• Signal integrity problems contain;• Crosstalk between the interconnects (←not discussed here)• Inductive component of the interconnects• Inductive effect is especially-pronounced in the lowresistance interconnects for global clock distribution.
• Delay error due the inductive effect results in clock skew.

Impedance

RLC modelcnact

Ref [5]eudn
Iresistancefrequency

RC model (conventional)

Modeling of On-Chip Inductance17• Inductance is determined by the current-loop.
• Modeling of the on-chip inductance is difficult, because;(1) A on-chip signal line has no ground plane, and it has many
current-return-loops.
(2) Inductance and resistance depend on the frequency
because of the skin effect and the proximity effect.

inductanceresistanceProximity effect
Ref [6,7]

Outline• Technology trend of VLSIs• Dependability issues
 Power / signal integrity problems at design-phase Device variation problems at manufacturing-phase Degradation problems after shipping• Future Dependable VLSIs
 Autonomous Reconfigurable Cell Array (ARCA)• Summary18

19

Device Variation Problems at Manufacturing-Phase• Atomic-level control of the fabrication of billons oftransistors is a challenging task.
• The relative variation of the gate length (Lg) increases withtechnology scaling due to the fabrication difficulty.
Ex.) Lg = 350 nm±10% (past)→Lg = 50 nm±20% (now)→Large variations of the device characteristics• Intrinsic fluctuation in device characteristics due todiscrete dopant atoms is an essential problem.

Vth Fluctuation due to Discrete Dopant Atoms
Atomic 3-D process/device simulation

σVth ∝
Lg=Source

Gate

Drain

20tox
LgWg

Wg=

Number of Boron dopants = several hundreds

Ref [8]• Threshold voltage (Vth) fluctuation induced by the statistical nature of
the number and position of discrete dopant atoms.
• The only solution is the non-doped SOI devices.

Circuit Techniques
to Compensate for Device Variations

21Frequencyvariation (σ)
w/o Vsub control

4.1 %Same Vsub for a chip0.69 %Each Vsub for each region 0.21 %(chip is divided into 21 regions)Ref [9]• The substrate bias (Vsub) is controlled adaptively by using
the replica of the critical path to meet the frequency target.
• Intra-chip variations, as well as inter-chip variations, arecorrected, and the frequency variations are reduced.

Outline• Technology trend of VLSIs• Dependability issues
 Power / signal integrity problems at design-phase Device variation problems at manufacturing-phase Degradation problems after shipping• Future Dependable VLSIs
 Autonomous Reconfigurable Cell Array (ARCA)• Summary22

Degradation Problems after Shipping

23• Introduction of new materials to VLSI causes novel
reliability issues.
• Reliability of the high-k gate dielectric is not clearly
understood.
• Electromigration is mitigated by changing from Al to Cu
interconnects. However, it will be a serious problem,
because the current density increases rapidly.
• Stress-induced voiding is the most serious problem in Cu
interconnects.
CuViaVoidCu
Ref [10]

Outline• Technology trend of VLSIs• Dependability issues
 Power / signal integrity problems at design-phase Device variation problems at manufacturing-phase Degradation problems after shipping• Future Dependable VLSIs
 Autonomous Reconfigurable Cell Array (ARCA)• Summary24

Future Dependable VLSIs
with Feed-Back Design-Flow
Shipping

Yield
100 %

Present LSI

10 %1%

25

Check theperformance& optimize thecircuit parameters

Check theperformance& optimize
the transistorcharacteristics

Future LSI withthe proposed
feed-backdesign-flow
Check theperformance& replace
the blocks

Future LSI withthe conventional
feed-forward
design-flow

0.1 %0.01 %
Power / signal
integrity problems
at design-phase

Device variation
problems at
manufacturing-phase

Degradation
problems
after shippingTimeDependable VLSIs Design• Memory LSI has the simple function and the regular structure.
→ Redundancy and the error correcting code (ECC) are the maturetechnologies.
• Logic LSI has the various functions and the complicated structure.
→ Random logic LSI with the redundancy is hard to realize.
• FPGA has the regular structure.
→ FPGA is suitable for the logic LSI with the redundancy.

26

Autonomous Reconfigurable Cell Array (ARCA) 27
for Dependable Logic VLSIs

Ref [11]• SPLC is composed of the two-rail logic.
→ A fault is detected, when the signals of the two-rail logic are the same.
• Real-time online fault recovery is performed by the self-checking.

Autonomous Reconfiguration

28

Reconfiguration Sequence29

Chip Micrograph of ARCA
1.9 mm

1.6 mm145 µm160 µm8 x 8 ARCA LSI with 0.35-µm CMOS

30

Measured Reconfiguration(456 cycles)31

Overhead of ARCA

32

Improved Reliability by ARCA
Random logic LSI

1.0(1-million gates)

Reliability

ARCA(Effective 1-million gatesin 20-million gates)

0.5
FPGA
(Effective 1-million gatesin 10-million gates)

005

10

Operating time (years)• Reliability of FPGA is improved by ARCA.

33

Summary• The dependability of VLSI is threatened by;(1) The deterministic power / signal integrity problems at
design-phase(2) The statistical device variation problems at
manufacturing-phase(3) The time-dependent degradation problems aftershipping• The prompt solutions to these problems are essential
to keep the continuous evolution of VLSIs.
• Future dependable VLSIs should introduce the faulttolerant systems by the feed-back design-flow.

34References

35[1] M. Bohr, “High-performance logic technology and reliability challenges”, IEEE International
Reliability Physics Symposium, 2003.
[2] International Technology Roadmap for Semiconductors, 2002 Update. http://public.itrs.net/[3] N. Oda et al., “A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 µm
CMOS generation”, IEEE Symposium on VLSI Technology, pp. 34 – 35, 2002.
[4] M. Takamiya et al., "An on-chip, 100-GHz sampling rate, 8-channel sampling oscilloscope macro withembedded sampling clock generator", IEEE International Solid-State Circuits Conference, pp. 182 –183, 2002.
[5] M. Beattie et al., “Inductance 101: modeling and extraction”, Design Automation Conference, pp. 323– 328, 2001.
[6] R. Kao et al., “Frequency-independent equivalent-circuit model for on-chip spiral inductors”, IEEE
Journal of Solid-State Circuits, pp. 419 – 426, 2003.
[7] X. Huang et al., “Loop-based interconnect modeling and optimization approach for multigigahertz
clock network design”, IEEE Journal of Solid-State Circuits, pp. 457 – 463, 2003.
[8] T. Ezaki et al., “Investigation of realistic dopant fluctuation induced device characteristics variation
for sub-100 nm CMOS by using atomistic 3D process/device simulator”, IEEE International Electron
Devices Meeting, pp. 311 – 314, 2002.
[9] J. Tschanz et al., "Adaptive body bias for reducing impacts of die-to-die and within-die parametervariations on microprocessor frequency and leakage ", IEEE International Solid-State Circuits
Conference, pp. 422 – 423, 2002.
[10] K. Yoshida et al., “Stress-induced voiding phenomena for an actual CMOS LSI interconnects”, IEEE
International Electron Devices Meeting, pp. 753 – 756, 2002.
[11] A. Shibayama et al., "An autonomous reconfigurable cell array for fault-tolerant LSIs", IEEE
International Solid-State Circuits Conference, pp. 230 – 231, 1997.