11th International Conference on Power Electronics-ECCE Asia
May 22 - 25, 2023 / ICC Jeju, Jeju, Korea

Digital Gate Driver IC with Real-Time Gate
Current Change by Sensing Drain Current to
Cope with Operating Condition Variations of
SiC MOSFET
Dibo Zhang, Kohei Horii, Katsuhiro Hata, and Makoto Takamiya
The University of Tokyo, Tokyo, Japanchange of operating conditions, and (3) programmable
AGDs instead of fixed-function AGDs that require
individual optimization for different product varieties ofpower devices. In the closed-loop AGDs, however, noprevious paper has realized all of (1) to (3).
To solve the problems, a digital gate driver (DGD) IC
with real-time gate current change (RGC) by sensing draincurrent (ID) that realizes all of (1) to (3) was proposed in[22]. The design choices in [22] are shown in blue in Fig.
1. The IC [22] integrates all of a current-source based
digital gate driver which changes gate current (IG) in 6 bits,a dID/dt sensor to detect IG switching timing, and acontroller into a single chip. In [22], the operation wasdemonstrated for IGBTs. In contrast, in this paper, the
DGD IC with RGC [22] is applied to SiC MOSFETs forthe first time. It is shown that the IC always reduces ELOSS
and switching noise by always performing appropriate
active gate driving even when IL and TJ of an SiC
MOSFET change.

Abstract-- A digital gate driver IC with real-time gate
current (IG) change by sensing drain current (ID) is applied
to SiC MOSFETs, and it is demonstrated that the IC always
reduces switching loss and switching noise by always
performing appropriate active gate driving even when theoperating conditions of SiC MOSFETs, such as load current
and junction temperature, change. The IC integrates all of acurrent-source based digital gate driver which changes IG in
6 bits, a dID/dt sensor to detect IG switching timing, and acontroller into a single chip. In the turn-on measurement ofan SiC MOSFET at 600 V and 25 ˚C, when the load current
changes to 20 A, 70 A, and 120 A, compared with theconventional single-step gate drive, the active gate drive using
the developed IC reduced the switching loss by 17 %, 12 %,and 11 % under ID overshoot-aligned condition, respectively.
Index Terms-- Gate driver, switching loss, switching noise,
SiC.

I. INTRODUCTION
A lot of active gate drivers (AGDs), where the gate
driving waveform is controlled during the turn-on/off
transients, have been proposed to reduce both theswitching loss (ELOSS) and the switching noise of powerdevices. AGDs can be classified into two types, open-loop
control [1-6] and closed-loop control [7-20]. The closedloop AGDs are required instead of the open-loop AGDs,
because the optimal driving waveform changes dependingon the operating conditions (e.g. load current (IL) andjunction temperature (TJ)) [21]. Fig. 1 summarizes thedesign choices in conventional closed-loop AGDs. To
make the closed-loop AGDs practical, the following threepoints are required: (1) single-chip integration instead of
PCB implementation for lower cost, (2) real-time control
instead of iterative control to reliably handle dynamic
Sensorinput

ControlmethodControl
time

ImplementationdID
dt

Continuous
time
⚫ VGS

Real-timeIC

State change
⚫ IG
⚫ VGS
⚫ RG

Iterative

PCB

ID,

VDS, dVDS
dt

VGS, dVGS
dt

II. DIGITAL GATE DRIVER IC WITH REAL-TIME GATECURRENT CHANGE
Figs. 2 and 3 show a circuit schematic and a timing chartof the DGD IC with RGC [22], respectively. In thefollowing, turn-on is discussed, whereas the exact same istrue for turn-off. The IC includes dID/dt detector for thestate change, controller for RGC, and a 6-bit currentsource type digital gate driver with variable IG in 64 levels,
where IG = nPMOS × 48 mA and nPMOS is an integer from 0
to 63. At turn-on, an active gate driving is performed inthree slots from t1 to t3 with different IG of strong (n1) weak (n2) -strong (n3), and this driving method is definedas stop-and-go gate drive (SGGD) [23]. n1 to n3 are presetby a digital input (Scan In), while t1 and t2 areautomatically determined by RGC by sensing ID. An
important feature of this IC is the full integration of t1 andt2 real-time automatic control functions on a single chip.
The real-time control is completed only by the IC and theexternal FPGAs or MCUs are not required. The real-time
control of t1 and t2 is done by detecting dID/dt by sensing
the voltage (VsS) of the parasitic inductance (LsS) between
Kelvin source and power source in Fig. 2, because VsS = −LsS (dID/dt). Specifically, as shown in Fig. 3, the end timingof t1 is determined by detecting the negative VsS at the
beginning of ID flow using a comparator with the reference
voltage of VREFL, and the end timing of t2 is determined by

Fig. 1. Design choices in closed-loop AGDs. This work is shownin blue.

ⓒ2023 KIPE

374

detecting the positive VsS at the timing immediately after
ID overshoots using a comparator with the reference
voltage of VREFH. Fig. 4 shows a die photo of DGD IC
fabricated with 180-nm BCD process. The die size is 2.0
mm by 2.5 mm.

III. MEASURED RESULTS
A. Measurement Setup
Figs. 5 and 6 show a circuit schematic and ameasurement setup of the double pulse test using thedeveloped
DGD
IC
and
an
SiC
module(BSM120D12P2C005, 1200 V, 134 A), respectively. The
SiC module is placed on a hotplate for measurement under
different temperature. Figs. 7 (a) and (b) show timing
charts of the conventional single-step gate drive (SSGD)
and the proposed SGGD for comparison, respectively. In
SSGD, n1 is varied, which emulates a conventional gate
driver with varied gate resistance. In SGGD, (n1, n2, n3) arepreset to (30, 13, 27), and t1 and t2 are automaticallydetermined by RGC by sensing ID.
The reason for setting (n1, n2, n3) = (30, 13, 27) is
explained here. In SGGD, in principle, n1 should be set
large to reduce turn-on delay, n2 small to reduce the draincurrent overshoot (IOVERSHOOT), and n3 large to reduce

Digital gate driver (DGD) IC withreal-time gate current change
5V

18 V

nPMOS

SIPO 36
PISOs

1WP
IO

32WP
32IO

ID
IG

Level shifter
Scan In
Scan CLK
IN
5V
VREFH
VREFL

SIPO 36

6
PISOs

dID
dt
detector

IO
nNMOS

32IO

1WN

32WN

VDS
VGS
Kelvinsource(S)
LsSVsS

Serial-in parallel-out shift register (SIPO)
Parallel-in serial-out shift register (PISO)

Power source (s)SiC
moduleFig. 2. Circuit schematic of digital gate driver (DGD) IC with realtime gate current change (RGC).

IL
Real-time timing control by detecting dID/dt by sensing VsS
t1

IN

t3

t2

t4

On
63

nPMOS

n1

Digitalgate
driver

t6

t5

Off
n3

DGD

n2

0
63

n4

nNMOS

VGS

n6

18 V

ID

VGS
ID

LsS

VsS

0A

0V

VDs

n5

0

IG

600 V

IG

IOVERSHOOT

Fig. 5. Circuit schematic of double pulse test.

0A

VREFH
VsS 0 V
VREFL
600 V

VDS

Fig. 3.

Digital gate
driver IC

0V

Timing chart of DGD IC with RGC.

6-bit
pMOS
drivers

SiC module

2.0 mmFig. 6.

Photo of measurement setup.

IN

Off
63

nPMOS

6-bit
nMOS
drivers

On
n1

0
63

nNMOS

IN
nPMOS

2.5 mm0A(a) Conventional single-stepgate drive (SSGD)

Fig. 4. Die photo of DGD IC fabricated with 180-nm BCD
process.

Fig. 7.

375

Timing charts for turn-on.

On
30

13

t1

t2

27

0
63

nNMOS

0

IG

Off
63

0

IG

0A
(b) Proposed stop-and-gogate drive (SGGD) with
automatic t1 and t2 control

140
100
80
60
40
20

140
100
80
60
40
20

0
0

0
0

1000
500
Time [ns]TJ = 125 ˚C

IL
120 A
110 A
100 A
90 A
80 A
70 A
60 A
50 A
40 A
30 A
20 A

120

ID [A]

120

ID [A]

TJ = 25 ˚C

IL
120 A
110 A
100 A
90 A
80 A
70 A
60 A
50 A
40 A
30 A
20 A

1000
500
Time [ns](a)15

VGS [V]10
5

t2 @ IL = 20 A

0t1 t2 @ IL = 120 A

0

TJ = 125 ˚C

IL
120 A
110 A
100 A
90 A
80 A
70 A
60 A
50 A
40 A
30 A
20 A

IL
120 A
110 A
100 A
90 A
80 A
70 A
60 A
50 A
40 A
30 A
20 A

15
10

VGS [V]

TJ = 25 ˚C(b)

5t2 @ IL = 20 A
t1 t2 @ IL = 120 A

0

1000
500
Time [ns]5001000Time [ns]

0

(c)
(d)
Fig. 8. Measured waveforms in SGGD with RGC with varied IL from 20 A to 120 A in 10 A increments. (a) Measured ID waveforms at TJ = 25
˚C. (b) Measured ID waveforms at TJ = 125 ˚C. (c) Measured VGS waveforms at TJ = 25 ˚C. (d) Measured VGS waveforms at TJ = 125 ˚C.

the measured t2 vs. IL at TJ of 25 ˚C and 125 ˚C. It is clearlyobserved that as IL increases, t2 is automatically increased
by RGC. On the other hand, the TJ dependence of t2 isalmost negligible. In contrast, the TJ dependence of t2 wasclearly observed for IGBTs [22]. The reason why the TJ
dependence of t2 is almost negligible for SiC MOSFETs
can be explained by the smaller temperature dependenceof the SiC device characteristics compared to IGBTs [24].

ELOSS [23]. In the actual measurements, however, n1 = 30,
because if n1 is set to 31 or higher, ringing at the beginningof the t1 period of VsS waveform shown later in Figs. 12 (b),13 (b), and 14 (b) increases and exceeds VREFH and VREFL,
causing the dID/dt detector to make a false detection. In
addition, n3 = 27 was set for the measurements, because if
n3 is set to 28 or higher, the second overshoot of ID shownin Figs. 12 (b), 13 (b), and 14 (b) will be higher than thefirst overshoot of ID, and IOVERSHOOT will not be controlled
by n2. Finally, n2 is a parameter with a degree of freedom
in its setting. In the pre-preparation measurements, it was
confirmed that the proposed SGGD operates normally inthe range of n2 from 10 to 20. Setting n2 = 10 results in alarge ELOSS and small IOVERSHOOT, while setting n2 = 20
results in a small ELOSS and large IOVERSHOOT. In this paper,n2 = 13 was set to balance ELOSS and IOVERSHOOT.

250

TJ = 125 ˚C

t2 [ns]200

B. Proposed SGGD at Various IL and TJ
Figs. 8 (a) to (b) show the measured ID waveforms andFigs. 8 (c) to (d) show the measured gate-source voltage(VGS) waveforms in SGGD with RGC with varied IL from
20 A to 120 A in 10 A increments at TJ of 25 ˚C and 125
˚C, respectively. In Figs. 8 (c) and (d), the periods t1 and t2
can be estimated from the surges in VGS waveforms. t1 is
independent of IL, while t2 is dependent on IL. Fig. 9 shows

25 ˚C

150
100

50
0
0

20

40

80
60
IL [A]

100 120

Fig. 9. Measured t2 vs. IL at TJ = 25 ˚C and 125 ˚C extracted from
Figs. 8 (c) and (d).

376

C. Comparison of ELOSS and IOVERSHOOT between
Conventional SSGD and Proposed SGGD
Figs. 10 (a) to (c) show the measured ELOSS vs.
IOVERSHOOT of the conventional SSGD and the proposed5

TJ [˚C]25 125n1 = 5Conv.
SSGD
Proposed
SGGD

ELOSS [mJ]

4
−18%

3 A1
2 −17%B1

1
0

SGGD at IL = 20 A, 70 A, and 120 A, respectively. In eachgraph, TJ is varied to 25 ˚C and 125 ˚C. The blue curve,
which represents TJ = 25 ˚C, and red curve, which
represents TJ = 125˚C, show the trade-off curves of theconventional SSGD with varied n1 from 5 to 63. In allcases, the proposed SGGD has lower ELOSS and lower
IOVERSHOOT than the conventional SSGD. At TJ = 25 ˚C,when IL is varied to 20 A, 70 A, and 120 A, compared withthe conventional SSGD, the proposed SGGD reduces
ELOSS by 17 %, 12 %, and 11 %, respectively, under the
IOVERSHOOT-aligned condition, while it reduces IOVERSHOOT
by 17 %, 12 %, and 12 %, respectively, under the ELOSSaligned condition. At TJ = 125 ˚C, when IL is varied to 20
A, 70 A, and 120 A, compared with the conventional
SSGD, the proposed SGGD reduces ELOSS by 21 %, 10 %,and 9 %, respectively, under the IOVERSHOOT-aligned
condition, while it reduces IOVERSHOOT by 18 %, 11 %, and
5 %, respectively, under the ELOSS-aligned condition.
In Figs. 10 (a) and (c), Points A1 to A3, Points B1 to
B3, and Points C1 to C3 are defined for (IL, TJ) = (20 A,
25 ˚C), (120 A, 25 ˚C), and (120 A, 125 ˚C), respectively,−21% n = 63
1

−17%
C1

IL = 20 A
0

10

30
40
20
IOVERSHOOT [A]

50

(a)

35

20

TJ [˚C]25 125n1 = 5Conv.
SSGD
Proposed
SGGD

−11%

10
−12%

5

0
0

25

ELOSS [mJ]

ELOSS [mJ]

15

−10%

n1 = 63n1 = 520

TJ = 25˚C

15n1 = 635

IL = 70 A
30 40
20
IOVERSHOOT [A]

50

0

60

0

10

35

15
10

5

A2

B2
B3

−9%

10

60

n1 = 63n1 = 5

20

Conv.
SSGD
Proposed
SGGD

TJ = 125˚C15

n1 = 6310−12%

IL = 120 A
0025−5% A3
C3

−11%

50

IL [A]
20 70 120

30

Conv.
SSGD
Proposed
SGGD

ELOSS [mJ]

ELOSS [mJ]20

35

TJ [˚C]25 125n1 = 525

20 30 40
IOVERSHOOT [A]
(a)

(b)

30

Conv.
SSGD
Proposed
SGGD

10

−12%

10

IL [A]
20 70 120

30

5

C2

20
30 40
IOVERSHOOT [A]

50

0

60

0

10

20 30 40
IOVERSHOOT [A]

50

60

(b)
Fig. 11 Measured ELOSS vs. IOVERSHOOT of conventional SSGD andproposed SGGD at IL = 20 A, 70 A, and 120 A. (a) TJ = 25 ˚C. (b)TJ = 125 ˚C.

(c)Fig. 10. Measured ELOSS vs. IOVERSHOOT of conventional SSGD andproposed SGGD at TJ = 25 ˚C and 125 ˚C. (a) IL = 20 A. (b) IL = 70
A. (c) IL = 120 A.

377

where Points ”B”s are the proposed SGGD, Point “A”s are
the conventional SSGD with closest IOVERSHOOT comparing
to proposed ones, and Point “C”s are the conventional
SSGD with the closest ELOSS comparing to proposed ones.
The measured waveforms for these nine points are shown
later in Figs. 12 to 14.
Figs. 11 (a) and (b) show the measured ELOSS vs.
IOVERSHOOT of the conventional SSGD and the proposed
SGGD at TJ = 25 ˚C and 125 ˚C, respectively. In eachgraph, IL is varied to 20 A, 70 A, and 120 A. Similarly, ineach graph, the red curve, which represents IL = 120 A,
black curve, which represents IL = 70 A, and blue curve,
which represents IL = 20 A, show the trade-off curves of
the conventional SSGD with varied n1 from 5 to 63. The
proposed SGGD has advantage over conventional SSGD
on lower ELOSS and lower IOVERSHOOT.
Figs. 12 (a) to (c) show the measured waveforms of
Point A1, which represents the waveform of SGGD with
n1 = 13, Point B1, the proposed SGGD, and Point C1,
which represents the waveform of SGGD with n1 = 17 in
ELOSS : 1.9 mJ

ELOSS : 2.3 mJ

200 ns/div
VDs: 100 V/div

ELOSS : 1.9 mJ

200 ns/div

200 ns/div

VDs: 100 V/div

VDs: 100 V/div

VGS: 4 V/div
VGS: 4 V/div
VGS: 4 V/div
ID: 25 A/div

ID: 25 A/div0

ID: 25 A/div

0

0
VsS: 2 V/div

0

VREFH
0
VREFL

nPMOS

nPMOS

Time

0

(a) Point A1 (SSGD, n1 = 13)

VsS: 2 V/div
0

nPMOS
3013

13
0

VsS: 2 V/div

27

17

Time
103 ns 94 ns(b) Point B1 (Proposed SGGD)

0(c) Point C1 (SSGD, n1 = 17)

Fig. 12 Measured waveforms of Point A1, Point B1, and Point C1 in Fig. 10 (a) at IL = 20 A and TJ = 25˚C.

ELOSS : 12.0 mJ

ELOSS : 13.5 mJ

ELOSS : 11.7 mJ

VDs: 100 V/div
200 ns/div

VDs: 100 V/div

ID: 25 A/div

200 ns/div

200 ns/div

ID: 25 A/div

ID: 25 A/div

VGS: 4 V/div

VGS: 4 V/div

VGS: 4 V/div

VDs: 100 V/div
0

0

0
VsS: 2 V/div

0

VREFH
0
VREFL

nPMOS

nPMOS

Time
(a) Point A2 (SSGD, n1 = 13)

0

VsS: 2 V/div

0
nPMOS
30

13
0

VsS: 2 V/div

27

13

Time
103 ns 255 ns(b) Point B2 (Proposed SGGD)

150(c) Point C2 (SSGD, n1 = 15)

Fig. 13 Measured waveforms of Point A2, Point B2, and Point C2 in Fig. 10 (c) at IL = 120 A and TJ = 25˚C.

378

ELOSS : 12.5 mJ

ELOSS : 11.7 mJ

ELOSS : 11.4 mJ

VDs: 100 V/div

VDs: 100 V/div

ID: 25 A/div

200 ns/div

200 ns/div

200 ns/div
ID: 25 A/div

ID: 25 A/div

VGS: 4 V/div

VGS: 4 V/div

VGS: 4 V/div

VDs: 100 V/div
0

0

0
VsS: 2 V/div

0

VREFH
0
VREFL

nPMOS

nPMOS

nPMOS
27

13
Time

(a) Point A3 (SSGD, n1 = 13)

0

VsS: 2 V/div
0

30

13
0

VsS: 2 V/div

14

Time
103 ns 252 ns(b) Point B3 (Proposed SGGD)

0(c) Point C3 (SSGD, n1 = 14)

Fig. 14 Measured waveforms of Point A3, Point B3, and Point C3 in Fig. 10 (c) at IL = 120 A and TJ = 125˚C.

Fig. 10 (a), respectively, under IL = 20 A, TJ = 25˚C
condition. Fig. 12 (b) clearly shows that the start of ID flow
and ID overshoot are properly detected by comparing VsS
with VREFL and VREFH, and that SGGD is realized with t1
and t2 correctly controlled. Compared with theconventional SSGD (Point A1 and Point C1), the proposed
SGGD (Point B1) reduces ELOSS from 2.3 mJ to 1.9 mJ by
17 % under IOVERSHOOT-aligned condition and reduces
IOVERSHOOT by 17 % under ELOSS-aligned condition.
Figs. 13 (a) to (c) show the measured waveforms of
Point A2, B2, and C2 in Fig. 10 (c), as SGGD with n1 = 13,
the proposed SGGD, and SGGD with n1 = 15, respectively,
under IL = 120 A, TJ = 25˚C condition. Fig. 13 (b) clearlyshows that the start of ID flow and ID overshoot areproperly detected by VsS. Note also that comparing t2 in Fig.
12 (b) and Fig. 13 (b), where IL changed from 20 A to 120
A, t2 increased from 94 ns to 255 ns. The IL dependence of
t2 is successfully controlled automatically by the proposed
RGC. Compared with the conventional SSGD (Point A2
and Point C2), the proposed SGGD (Point B2) reduces
ELOSS from 13.5 mJ to 12.0 mJ by 11 % under IOVERSHOOTaligned condition and reduces IOVERSHOOT by 12 % under
ELOSS-aligned condition.
Similarly, Figs. 14 (a) to (c) show the measured
waveforms of Point A3, B3, and C3, as SGGD with n1 =13, the proposed SGGD, and SGGD with n1 = 14,
respectively, under IL = 120 A, TJ = 125 ˚C condition. In
Fig. 14 (b), automatic control of t1 and t2 has beensuccessfully achieved by detecting VsS comparing to VREFL
and VREFH. Compared with the conventional SSGD (Point
A3 and Point C3), the proposed SGGD (Point B3) reduces
ELOSS from 12.5 mJ to 11.4 mJ by 9 % under IOVERSHOOTaligned condition and reduces IOVERSHOOT by 5 % under
ELOSS-aligned condition.

379

TABLE ICOMPARISON TABLE OF CLOSED-LOOP AGDS
TPEL’15[11]

TPEL’18[12]

Target powerdevice

IGBT

IGBT

Sensor input

dIC / dt,
VCE

dIC / dt,
VCE

TimingFeedback control
VGE
of statetargetwaveformchangeReal-time control
Yes
Yes
Number of states4
per switching
Preset parameters
for each state
Levels ofparameter

Implementation
IC Process

IG

PCB

TPEL’21[14]SiC
MOSFET

ISSCC’19[13]

ISSCC’21[18]

This work

Si MOSFETGaN FETSiC
MOSFETdIC / dt

VDS

Timing ofstatechangeYes

Timing ofstatechangeNo

VDD of highside gate
driverTiming ofstatechangeNodID/dtTiming ofstatechange
Yes

3

3

3

3

VGS

RG

IG

IG

NA

2

PCB

PCB

2

3

6 bit

IC (Not fully
integrated)*
130 nm
HV CMOSIC (Fully
integrated)
500 nm,600 V SOI**IC (Fully
integrated)
180 nmBCD*Voltage divider for VDS is not integrated.
**High-voltage IC process with the same breakdown voltage as VCC of main circuit is required.

Table I shows a comparison table of the closed-loop
AGDs. The DGD IC with RGC [22] used in this work was
the first work achieving the fully integrated IC, the realtime control, and the programmable IG in the closed-loop
AGDs. In this paper, the DGD IC with RGC [22] is applied
to SiC MOSFETs for the first time.
IV. CONCLUSIONSThe DGD IC with RGC [22], integrating all of thecurrent-source based digital gate driver which changes IG
in 6 bits, a dID/dt sensor to detect IG switching timing, anda controller into a single chip, is applied to SiC MOSFETs
for the first time. The IC always reduces ELOSS and
IOVERSHOOT by the real-time control of t1 and t2 even when
IL and TJ of an SiC MOSFET change. In the turn-on
measurement of an SiC MOSFET at 600 V and 25 ˚C,when IL is varied to 20 A, 70 A, and 120 A, compared withthe conventional SSGD, the proposed SGGD reduces
ELOSS by 17 %, 12 %, and 11 %, respectively, under the
IOVERSHOOT-aligned condition, while it reduces IOVERSHOOT
by 17 %, 12 %, and 12 %, respectively, under the ELOSSaligned condition.
ACKNOWLEDGMENT
This work was partly supported by NEDO (JPNP21009).
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