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468

PAPER

Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era

An On-Chip Noise Canceller with High Voltage Supply Lines for
Nanosecond-Range Power Supply Noise
Yasumi NAKAMURA†a) , Student Member, Makoto TAKAMIYA† , and Takayasu SAKURAI† , Members

SUMMARY
An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the eﬀectiveness ofthe canceller is experimentally verified. The noise canceller is eﬀective
for nano-second order noise caused by circuit wakeup or step increase of
frequency in frequency hopping. The principle of the noise canceller isto reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage
drop across the VDD supply line is reduced. As additional current flowfrom higher supply, switching transistor has to be turned oﬀ not to increase
the power consumption. With turn-oﬀ time of 2L/R, this current can beturned oﬀ without inducting another droop due to the increase of current
flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic
gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and
3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without
wire overhead and to achieve same noise reduction with passive method, 77
times more C or 45 times less L is required. Too large switching transistor
results in saturated noise reduction eﬀect and higher power consumption.
A rule-of-thumb is to set the on-resistance to supply 100% of load current
when turned-on.
key words: power integrity, power gating, wake-up, dynamic voltage andfrequency scaling, noise canceller

1.

Fig. 1

Power gating and supply line noise.

Introduction

System-on-a-Chip (SoC) and System-in-a-Package (SiP)
have become major integration technologies in recent years.
They have various types of circuit blocks like MPU, DRAM,
SRAM, ROM, logic and analog circuits on a chip or ina package. These blocks often employ recent low power
VLSI design such as power gating, clock gating, and dynamic voltage and frequency scaling (DVFS), which generate rapid and large change of the power supply current at
the moment of the wake-up from the sleep mode to the active mode. This current induces noise on the power supply
line which is larger than IR-drop at steady state [1]–[5].
Figure 1 shows a schematic figure of power supply line
noise in power-gated circuit. Since there is inductance andresistance between external VDD and VDD of logic circuit andcapacitance between internal VDD and VSS , when the powerswitch is turned on, sudden increase of current induces voltage noise. This voltage droop slows down the operation
speed of logic circuits for 10 s to several 100 s of clock cycles. If there is only one power domain, this is not a probManuscript received August 7, 2008.
Manuscript revised November 14, 2008.
†
The authors are with the University of Tokyo, Tokyo, 1538505 Japan.
a) E-mail: spiegel@iis.u-tokyo.ac.jp
DOI: 10.1587/transele.E92.C.468

Fig. 2Multiple blocks share same power supply.

lem because the logic circuit can be kept waiting until VDD
settles. Though, in more realistic configuration with multiple power domains as shown in Fig. 2, this noise becomesa problem. In this case, when an “aggressor” block wakes
up, neighboring “victim” blocks suﬀer from reduced supply
voltage and causes malfunction, which makes it diﬃcult toeﬀectively sleep/wake-up circuit blocks at high frequency.
To quantitatively analyze this noise, the power supply
line can be approximated as R and L as shown in Fig. 3. C
represents all the capacitance connected to the power supply
node, including additional decoupling capacitor. I represents the load current. VDDINT is the eﬀective power supply
voltage with which the logic circuit works. The load current at wake-up is modeled as a step current of I0 . This stepcurrent induces a transitional noise caused by L and C to
VDDINT . Assuming R  1 Ω and neglecting damping eﬀect,
the minimum voltage of VDDINT can be approximated as

L
I0
(1)
VDDINT min ≈ VDD − RI0 −CThe third term, − CL I0 , is the most significant noisec 2009 The Institute of Electronics, Information and Communication Engineers
Copyright NAKAMURA et al.: AN ON-CHIP NOISE CANCELLER WITH HIGH VOLTAGE SUPPLY LINES

469

Fig. 3

Simple model of power supply noise.

when the circuit wakes up. From Eq. (1), less L, more C,
or less I0 can reduce this noise. Reducing L is equivalent toallocate more I/O pads for the power supply. This is diﬃcult
since 3 times more pads are required to reduce the noise to
50% and power supply already occupies large portion of thepads. Increasing C is also diﬃcult since large decoupling
capacitor is already added to the design, and adding moredecoupling capacitor directly increase the chip cost. There
are some techniques to increase virtual decoupling capacitance [6]–[8], though they are based on amplifier or comparator which consumes not negligible standby power. The
final possibility, decreasing I0 is to wake-up slowly dividing
into several
steps of I0 [9]. Since it takes several intervals√(∼ 2π LC) for VDDINT to settle, this approach results inslower wake-up.
In this paper, a technique to reduce the transition noisewith the aid of higher voltage supply to reduce I0 is proposed [10] and the eﬀectiveness is verified through experiments. In Sect. 2, the basic concept of the noise canceller isintroduced followed by the implementation of the noise canceller in Sect. 3. Sections 4 and 5 are dedicated for design
considerations and conclusions.
2.

Fig. 4

Basic concept of the noise canceller.

Basic Concept of the Noise Canceller

Figure 4 shows the basic concept of the noise canceller.
The transistor labeled MINJECT and power supply VDDH
which are added to the VDDINT node reduces power supply noise. The circuit configuration and schematic waveforms of VDDINT and I with and without noise canceller
are shown in Fig. 5. Neglecting the current supplied from
CDECOUPLING , as shown in Fig. 5(a), without noise canceller
all the load current I is supplied through the impedanceof power supply lines, namely
 ZVDD and ZVSS . Step increase of I induces noise of R + CL I0 as mentioned in
Sect. 1. Fig. 5(b) shows the waveforms of VDDHINT , VDDINT ,IVDD , and IVDDH with canceller. Detailed switch timing
will be explained in Sect. 4. When the logic circuit wakes
up, the PMOS switch between VDDHINT and VDDINT is also
turned on to pull up VDDINT . Since I = IVDD + IVDDH ,IVDD = I−IVDDH which means IVDD is reduced as in the rightfigure of Fig. 5(b) and this reduces the noise VDD − VDDINT =ZVDD × IVDD . Though VDDHINT has a large noise, the capacitance between VDDHINT and VDDINT is much smaller (parasitic only) than CDECOUPLING , and consequently this noise
does not aﬀect VDDINT .
The noise canceller requires an extra power supply line
for VDDH , though this line can be much smaller than the VDD
supply since the voltage drop across ZVDD can be as large as
VDDH − VDD + VDS SW , where VDS SW is the minimum drain-

Fig. 5 Configuration and schematic waveform of with and without noise
canceller.

source voltage of the MINJECT transistor to supply IVDDH .
In order to quantitatively discuss the noise reduction by
the canceller, let us introduce the following four parameters:a high voltage factor α, a higher voltage supply impedance
factor β, a ground impedance factor g, and a noise reduction
factor γ. Figure 4 also shows parameters α, β, g.
The noise reduction factor γ is defined as:(VDD − VLOCAL min )w canceller(VDD − VLOCAL min )w/o canceller
where VLOCAL = VDDINT − VSSINT ,and VLOCAL min is the minimum of VLOCAL .

γ=

(2)

Assuming Vmin = VDD − (1 + g) ZVDD I without canceller,, can bewith canceller IVDDH and new IVDD , namely IVDD
written as:αVDD + ZVDD IVDD,β ZVDDIVDD+ IVDDH = I.

IVDDH =


From Eqs. (3) and (4), IVDD
is

(3)
(4)

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Fig. 6

Fig. 7

High voltage factor vs noise cancelling eﬀect.

Schematic of the test chip.

α VDD
β
I−
.
1+β
1 + β ZVDD

 β


α
+ g ZVDD I
Thus, Vmin = 1 + 1+β
VDD − 1+β

IVDD
=


α
+
g
ZVDD I − 1+β
VDD
1+β

 β
γ =

(1 + g) ZVDD I
g
β
α
=
+
−
,
1 + g (1 + g) (1 + β) (1 + g) (1 + β) Δ
where
Δ = VDD − Vmin without noise canceller.

(5)

Figure 6 shows the noise reduction factor for typicalparameters (g = 0.86, Δ = 15%) with multiple α and β basedon Eq.(5). If α = 1(VDDH = 2VDD ), even if β is as large as
10, γ ∼ 40%, which is better cancelling eﬀect than β = 1
without high voltage. This means large noise reduction canbe achieved even with small overhead for additional VDDH
supply line.
3.

Simulation and Measurement Results

3.1 Circuit Topology
To verify the eﬀectiveness of the noise canceller, a test
chip with 530 k-gate equivalent dummy load is designed andmanufactured.
Figure 7 shows the measured circuit in 90-nm 1 V
CMOS. It uses normal VDD (1.0 V) and higher VDD , namely
VDDH (2.0 V). To confirm the proposed canceller can reduce
the noise with small wire overhead, only 1 I/O pad is allocated to VDDH while 5 are allocated to VDD and 6 are allocated to VSS . This is a = 1, b = 5 configuration in Sect. 2.
As a noise source, NMOS switch M2 with on-currentof 40 mA, and load capacitance and decoupling capacitance
Ccircuit of 2 nF are implemented to emulate 530 k-gate logic
circuit. This noise source is driven by external wake-up signal (Wake-up).
As a noise canceller, a PMOS switch M3 which supplies 32 mA of current from VDDH to VDD at steady state is
implemented. M3 is controlled by external control signal,

Fig. 8

VSS -VDD to VDDH -VDD level shifter.

namely ΦWAKEUP to test various combinations with Wakeup signal. A VSS -VDD to VDD -VDDH level shifter is also used
so that VSS to VDD level Wake-up signal can be also usedfor ΦWAKEUP , or the control signal can be generated on-chip
without higher-VDD tolerant transistors.
On-chip VDD is monitored through source follower M1
with external oscilloscope.
All the transistors here are normal-VDD tolerant transistors.
The level shifter implemented here is shown in Fig. 8.
As shown in Fig. 8(a), this level shifter converts VSS to
VDD level signal into VDDH to VDD level signal to control
MINJECT . Figure 8(b) shows the schematic. The tail transistor is switched by the input signal and since the right-side
transistor has larger width than the left-side one, VSWITCH
is pulled down to near VDD to turn on the cancelling transistor. VSWITCH is weakly pulled up to VDDH to completely
turn oﬀ the cancelling transistor when the tail transistor is
oﬀ. VTH drops of the two diode-connected PMOS are used
to avoid below-VDD VSWITCH output. Figure 8(c) shows thegate-source and gate-drain voltage trajectories of the level
shifter when 0 to 1.0 V pulse is applied to ΦWAKEUP . Thisshows that all the transistors operate within their gate oxide
tolerance.

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circuit.
3.2 Measurement Results
4.
Figure 9 shows the measured waveforms of the power supply line with and without the noise canceller. Without
noise canceller, the minimum voltage of VDDINT -VSSINT during wake-up is about 0.84 V where the steady state voltage with IR-drop is 0.92 V. On the other hand, with proposed noise canceller, the minimum voltage is improved
to about 0.89 V, which is 68% noise reduction and γ =(1 − 0.89)/(1 − 0.84) = 0.69.
A chip microphotograph of the fabricated test chip isshown in Fig. 10. Table 1 shows the specification of the test
chip. The noise canceller area is 0.022 mm2 , while the noise
source area is 0.21 mm2 . Since this noise source emulates
logic circuits with NMOS switch, this current consumption
is equivalent to 1.5 mm2 of 2NAND. Thus the area overheadof the noise canceller can be as small as 1.5% of the load

Fig. 9Measured noise waveform with and without noise canceller.

Design Consideration

Improved control methodologies for proposed canceller are
discussed in this section.
4.1 Turn-On Control
One straightforward method to control the cancelling transistor MINJECT is to compare VDDINT with a reference voltage
VREF and turns on if VDDINT < VREF . This method has several problems. One is its stability. If VDDINT exceeds VREF τdseconds after turning-on MINJECT , this circuit will oscillatewith the period of τd . To avoid this oscillation, hysteresis
with VREF ON and VREF OFF can be used.
Another problem is the detection delay. Since the noiseis relatively fast, turn-on delay of the canceller has a large
impact on noise reduction. Figure 11 shows the simulated
relationship between turn-on delay and noise cancelling effect, or 1 − γ. Cancelling eﬀect goes down to zero with 10 ns
of delay. To turn-oﬀ the cancelling transistor, VREF must be
lower than the steady state voltage, VDD -RI, whose delay isalso shown in Fig. 11 as “Steady state voltage.” Here, noise
cancelling eﬀect is approximately 2/3 of that without delay,
and if dual VREF is used, the eﬀect is further reduced.
To solve these problems, the transistor is turned on assoon as the circuit wakes up. In other words, in order toachieve the quickest turn-on, the transition of VSWITCH from
H to L should be as sharp as possible. This method does
not require a comparator, and is practical since the noise
canceller can know when the circuit wakes up.
4.2 Turn-Oﬀ Control
After the first droop is cancelled by the proposed canceller,
how should it be turned oﬀ? In a configuration where
IVDDH = I and IVDD = 0, if MINJECT is turned oﬀ as a step
function, IVDD results in step increase of I, which inducessame amount of noise without canceller. Thus, MINJECT has
to be turned oﬀ slowly enough not to induce another noise.
Figure 12 shows the measured waveforms of VDDINT VSSINT for several turnoﬀ slopes. tOFF is the time to turnFig. 10Chip micrograph and test setup.

Table 1

Specification of the test chip.

Fig. 11Turn-on delay vs noise cancelling eﬀect.

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472

Fig. 14
Fig. 12Fig. 13

Measured turn-oﬀ time vs noise.

A simple model to evaluate turn-oﬀ time.

oﬀ MINJECT . A, B, C and D have tOFF of 0 ns, 20 ns, 40 ns,
and 80 ns, respectively. A and B have 2nd noise which islarger than the cancelled noise, on the other hand, C and D
has smaller 2nd noise. From this, it is shown that slower
turn-oﬀ is necessary not to abandon cancelling eﬀect.
To quantitatively analyze tOFF , let us think of a simple model shown in Fig. 13. All power supply impedanceis approximated as L and R, and all circuit and decoupling
capacitance is approximated as C. Because decrease of
IVDDH is equivalent to increase of IVDD , turn-oﬀ of MINJECT
is modeledas increase of I. For simplicity, current of
I = I0 1 − e−kt is used. In this model, the condition thattransitional noise is smaller than IR-drop, or VDDINT MIN ≥VDD − RI0 is achieved when
R
k≤
.
2L
Assuming the noise is determined by largest dI/dt, this condition can be written as
tOFF ≥

2L.
R

Turn-oﬀ start time vs noise reduction eﬀect.

(6)

In the measured circuit, this value is around 60 ns. Figure 14
shows the measured Vmin for various tOFF and tON . As mentioned before, with tOFF of 0 ns, 2nd droop is larger than thecancelled noise in any tON . With tOFF of 40 ns and 80 ns, 2nd
droop is smaller than the cancelled noise and if tON > 10 ns,
noise reduction rate remains constant. From this, design oftOFF = 2L
R does not induce 2nd droop and still has margin
not to induce it. Since the canceller is not √susceptible to tON ,turning oﬀ after the 1st droop (tON ∼ π LC) is preferredbecause too large tON results in higher power consumption
and too small tON suﬀers from side-eﬀects.

Fig. 15

On-resistance of MINJECT vs noise cancelling eﬀect.

4.3 On-Resistance of the Switching Transistor
In the model of Sect. 2, on-resistance of MINJECT was treatedas zero. However, such a transistor tends to be very large
and not practical. On-resistance of MINJECT aﬀects the peak
IVDDH , which is
IVDDH =(α + Δ) VDD.
(1 + β)R + RON(7)

Figure 15 shows simulated noise RON vs noise cancellation
where IH/IL means IVDDH /IVDD . As IVDDH /IVDD increases,
noise cancelling eﬀect linearly increase up to IVDDH /IVDD= 1. After that point, cancellation eﬀect saturates and 2nd
droop becomes significant because long tOFF is required.
Furthermore, total power consumption when MINJECT isturned on is
VDD IVDD + (α + 1) VDD IVDDH(8)From Eqs. (4), (8) is equal to
VDD I + α VDD IVDDH .

(9)

From this, large IVDDH means large power consumption, IVDDH = IVDD is a optimum point for setting RON of
MINJECT .
4.4 Power and Area Overhead
Figure 16 shows the measured and calculated power overhead of the proposed noise canceller. Power overhead was

NAKAMURA et al.: AN ON-CHIP NOISE CANCELLER WITH HIGH VOLTAGE SUPPLY LINES

473

the same wire overhead as the proposed noise canceller,
while the proposed canceller reduces noise to 32%, which
is 64% noise reduction from same wire overhead.
5.

Fig. 16

Wake-up frequency vs power overhead.

Conclusions

A power supply noise canceller for transitional noise at
power gating or frequency hopping wake-up is proposed and
68% noise reduction is experimentally verified for load current and capacitance equivalent to 530 k NAND gates. This
enables the power consumption reduction in power gating
systems by frequent wake-ups without aﬀecting neighboring
blocks’ operation. To confirm the eﬀectiveness of the proposed canceller, general design methodologies are shown.
Acknowledgments
This work is supported by Intel Corporation. The VLSI
chips were fabricated through the chip fabrication programof VDEC with the collaboration by STARC.
References

Fig. 17

Fig. 18

Noise waveform of passive noise canceller.

Noise cancelling eﬀect comparison regarding wire overhead.

about 3% in 50 k wake-ups/s. Since the charge injectedfrom VDDH to VDDINT is constant, power overhead depends
on the frequency of sleep/wake-up. In the measured case,maximum frequency under power overhead of 5% is around
100 kHz, which is the upper bound frequency of practicalnoise cancelling with the proposed canceller.
Comparison with passive countermeasures is shown in
Fig. 17. Measured noise waveforms with and without proposed noise canceller and simulated waveforms which are fit
to the cancelled noise level with increasing C or decreasing
L are shown. To obtain same noise reduction, 77 times asmuch C or 45 times as small L is required, whose overhead
is to large to implement.
Comparison with same overhead is shown in Fig. 18.
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Yasumi Nakamura
received the B.S., and
M.S., degrees in electrical engineering from the
University of Tokyo, Japan in 2004, and 2006,
respectively, where he is currently working toward the Ph.D. degree. His research interests include the power integrity of digital circuits, thelow-power techniques for digital circuits, andthe collaboration with MEMS.

Makoto Takamiya
received the B.S.,
M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in
1995, 1997, and 2000, respectively. In 2000,
he joined NEC Corporation, Japan, where he
was engaged in the circuit design of high speed
digital LSIs. In 2005, he joined University ofTokyo, Japan, where he is an associate professor of VLSI Design and Education Center. His
research interests include the circuit design ofthe low-power RF circuits, the ultra low-voltage
digital circuits, and the large area electronics with organic transistors. He
is a member of the technical program committee for the IEEE Custom Integrated Circuits Conference (CICC).

Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at the
University of California Berkeley, where he conducted research in the field of VLSI CAD. From
1996, he has been a professor at the University of Tokyo, working on lowpower high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC’s and large-area electronics. He has published more than
400 technical publications including 100 invited presentations and several
books and filed more than 200 patents. He served as a conference chairfor the Symp. on VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a
TPC chair for the first A-SSCC, and VLSI symp. and a program committee
member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED,
and other international conferences. He is a recepient of 2005 IEEE ICICDT award, 2004 IEEE ISSCC Takuo Sugano award and 2005 P&I patentof the year award and four product awards. He gave keynote speech at morethan 50 conferences including ISSCC, ESSCIRC and ISLPED. He is consulting to startup and international companies. He was an elected AdCom
member for the IEEE Solid-State Circuits Society and an IEEE CAS and
SSCS distinguished lecturer. He is a STARC Fellow and an IEEE Fellow.