Misleading Energy and Performance Claims in Sub/NearThreshold Digital Systems
Yu Pu1 , Xin Zhang1 , Jim Huang1 , Atsushi Muramatsu2 , Masahiro Nomura2 , Koji Hirairi2 ,Hidehiro Takata2 , Taro Sakurabayashi2 , Shinji Miyano2 , Makoto Takamiya1 , Takayasu Sakurai1
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan1
Semiconductor Technology Academic Research Center, Japan2
Email: {ypu, zhangxin, jimhuang, mtaka, tsakurai}@iis.u-tokyo.ac.jp;{muramatsu.atsushi, nomura.masahiro, hirairi.koji, takata.hidehiro, sakurabayashi.taro, miyano.shinji}@starc.or.jp

Abstract— Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques
proposed by earlier papers. This paper investigates five major pitfalls
which are often not appreciated by researchers when claiming that
their circuits outperform others by working at a lower Vdd with ahigher energy-efficiency. These pitfalls include: i) overlook the impacts
of different technologies and different Vth definitions, ii) only emphasizeenergy reduction but ignore severe throughput degradation, or expect
impractical pipelining depth and parallelism degree to compensate thisthroughput degradation, iii) unrealistically assume that memory’s Vdd
and energy could scale as well as standard cells, iv) use the highest
temperature as the worst timing corner as in the super-threshold, but
in fact negative temperature becomes much more detrimental in the
sub/near threshold regime, v) pursue just-in-need Vdd to compensate
effects of PVT, but without considering the high energy loss on DC-DC
converters. Therefore, the actual energy benefit from using a sub/nearthreshold Vdd can be greatly overestimated. This work provides somedesign guidelines and silicon evidence to ultra-low-Vdd systems. The
outlined pitfalls also shed light on future directions in this field.

sub/near threshold Vdd can be greatly overestimated by some earlier
papers. This paper provides some guidelines and silicon evidence tothe design of ultra-low-Vdd systems. The readers please be awarethat it is not the intention of this paper to suggest that some earlier
works were misleading. In fact, because sub/near threshold design isa very new field, researchers need more effort to setup widely-agreed,
community-defined metrics. The outlined pitfalls also shed light on
future directions in this field.
II. P ITFALL 1: OVERLOOK THE IMPACTS OF DIFFERENTTECHNOLOGIES AND DIFFERENT Vth DEFINITIONSTABLE IA P ERFORMANCE C OMPARISON

Processors
45nm Accelerator [1]65nm SubJPEG [2]65nm MSP430 [3]I. I NTRODUCTION
The latest IEEE standards, such as WiMAX and 4G wireless communication, require SoCs on portable systems to handle
far more complex multimedia applications than ever before. Highcomputational-performance and high energy-efficiency are thus extremely crucial to the digital processors embedded in these SoCs. The
semiconductor industry expects the energy of consumer electronics
to be reduced by an order of magnitude in the next 5 years. An
emerging trend for lowering energy is to scale the supply voltage
Vdd to the sub/near threshold region, which brings not only quadratic
dynamic energy savings, but also super-linearly reduced leakage
current. However, we recognize that it is quite difficult to assess
the sub/near threshold circuit techniques proposed by earlier papers,
as the papers often do not appreciate five major pitfalls which
may cause impractically favorable results. These pitfalls include: i)overlook the impacts of different process technologies and different
Vth definitions, ii) only emphasize energy reduction but ignore severe
throughput degradation, or expect impractical pipelining depth andparallelism degree to compensate for this throughput degradation, iii)
unrealistically assume that memory’s Vdd and energy could scale aswell as standard cells, iv) assume that a higher temperature results in aworse speed. While this is true in the super-threshold, in fact negative
temperature is much more detrimental in the sub/near thresholdregion, v) pursue just-in-need Vdd to compensate effects of PVT on
performance and also in this way minimize Vdd guardbandings, but
without considering the high energy loss when converting a nominal
battery voltage to a sub/near threshold voltage.
To investigate the severity of these pitfalls, representative digital
circuits and DC-DC converters are fabricated in a 65nm CMOS
process. We conclude that the actual energy benefit from using a

978-1-4244-8192-7/10/$26.00 ©2010 IEEE

sub/near threshold
80MHz at 0.4V
2.5MHz at 0.4V
0.1MHz at 0.4V

nominal supply
2.3GHz at 1.1V
300MHz at 1.2V
300MHz at 1.2V aa The maximum frequency is not released. 300MHz at the nominal
1.2V is our estimation for the MIT’s MSP430-like DSP.

Table I compares the performance of three recent works: (a)Intel’s 45nm CMOS 300mV 4-Way sub-word parallel accelerator[1]; (b) SubJPEG [2], NXP’s 65nm ASIC JPEG co-processor; (c)MIT’s 65nm TI-MSP430-like DSP processor with embedded DC-DC
converter [3]. Table I clearly shows that the performance gap of (a),(b) and (c) at aggressively scaled Vdd s is much larger than at nominal
Vdd s. In fact, depending on the difference of Vth s, the on-current
Ion ratio between different technologies can be up to many orders ofmagnitude in the sub/near threshold region, in contrast to only a few
times at the nominal Vdd . We also note that, there lacks a clear andwidely-agreed definition of Vth in sub/near threshold design. Since
Vth is a non-existing and artificial parameter, it has many different
interpretations. Many previous works cite the Vth values from theirfoundries. However, for different foundries the definitions of Vth canbe arbitrary and quite different. As an example, for the 65nm lowpower(LP) CMOS process technology which is used throughout our
research, the foundry’s V th is about 0.3V, which is defined as the V gs
when I ds ≈ 2µA at 1.2V. However, the actual watershed between the
exponential region and the linear region of this process is around 0.6V
according to the simulation. Therefore, it is quite difficult to fairly
compare the sub/near threshold circuit techniques proposed by earlier
papers, unless we know their Vth definitions. Some “state-of-the-art”
circuits which are claimed to have functioned “at an even lower Vdd
than others” or “well-below the Vth ” are not really because of circuit

625

When the baseline circuit changes its pipelining depth from
N baseline to N, the corresponding logic depth becomes:

LdsurplusDFF

Ld = Nbaseline Lbaseline /N(1)

Fig. 1.

Stage N

Stage 2

Stage 1

T pipeline , the delay of each pipeline stage, is described as following:
Tpipeline = Ld TF O4 + TDF F(2)

Diagram of pipelined circuits with different Ld and N

technique improvements, but just because they rely on processes withlower Vth s or use different Vth definitions.
We hereby call for widely-agreed and community-defined metrics.
This is similar to a well-known problem in the field of parallel
computer architecture: to get more impressive performance thanothers, some architectures quote 8 or 16-bit results, not 32-bit results,
so later in the famous Roza graph [4] all processors’ performancemust be scaled to 32-bit operations, in order to give a fair performancecomparison.

We are aware that transistor-level simulations are not capable ofcharacterizing energy (especially various and complex mechanisms ofleakage current) at scaled Vdd s with high confidence, so we fabricatedthree cores: i) Core A, the baseline core, (Ld =24, N =9) ii) Core B,(Ld =18, N =12) iii) Core C, (Ld =12, N =18). The circuit schematics
are illustrated in Figure 1. Intuitively, the number of DFFs grows
linearly with the increased N. However, [11] argued that in reality thenumder of DFFs follows N ρ , where ρ is a factor indicating a superlinearly increased number of DFFs with the pipelining depth N on
datapaths (e.g., pipelining a multiplier). Following them, we choose
ρ= 1.2 in this research. Therefore, some surplus DFFs are inserted
intentionally in Core B and Core C, as also shown in Figure 1. The
cores’ layout view without I/O cells and pads, and the die photo areshown in Figure 2.

III. P ITFALL 2: OVERLOOK SEVERE THROUGHPUT DEGRADATION
When Vdd scales to the sub/near threshold region, the rapidly
diminished driving current causes a severe throughput degradation,
hence discouraging aggressive Vdd scaling from being applied tomedium/high throughput consumer electronics. Most of the existing
sub/near threshold prototype chips focused on pursuing optimum
energy points or improving functioning yield for KHz range sensor
applications, e.g., [3] [5] [6] [7]. Only [1] [2] [8] considered throughput as a serious issue. Many researchers believe this throughput
degradation is not a problem as it may be easily compensated bydeep pipelining and massive parallelism while maintaining an ultralow energy/operation. Therefore, one purpose of this research is toinvestigate the impacts of pipelining depth and parallelism degree on
the throughput and the energy in a sub/near threshold system.
To understand the lower bound of energy reduction by Vdd scaling,
we assume embarrassing pipelining and parallelism are used, meaningthat no performance penalty due to data and control dependencies
would be incurred from using deeper pipelining and more parallelism. This assumption is ideal for general-purpose CPUs, because
it completely neglects the overhead such as hazard control, branchprediction, parallel programming software issues for multi-threading
cores. Instead, this assumption suits better the computation-oriented
streaming processors, e.g., single-instruction multiple-data (SIMD)
processor which exploits the inherent data-level parallelism in manyalgorithms. To represent a high-performance processor, our baseline
circuit consists of 9 pipeline stages and each pipeline has 24×FO4
delay, i.e., (Lbaseline =24, N baseline =9). Choosing 24×FO4 delay per
stage is suggested by [9], because Intel’s high-end Pentium-4 has an
about 20×FO4 delay [10], the 24×FO4 delay is fairly representative
for processors with slightly shallower pipelining than the Pentium4. As N baseline increases, the effort to handle pipelining hazards
grows rapidly. A processor with less than 12×FO4 delay is not likely
to happen because the instruction stalls due to pipelining control
overhead can easily offset the increase in instruction throughput
achieved from having more pipelining stages.

(a)Fig. 2.

(b)Core A, Core B, Core C: (a) layout view (b) die photo

The energy per clock cycle can be modeled as following:
Ecycle = αEswitch (Vdd ) + Ileakage (Vdd )Tcycle(3)

where α is the average switching activity factor of all the internal
nodes, Eswitch (Vdd ) is the Vdd dependent switching energy per cycle.
Ileakage (Vdd ) is the total leakage current which is also dependent
on Vdd , and Tcycle is the fastest achievable operating clock cycle
time. Among these parameters, Eswitch (Vdd ) is insensitive to process
variations (PV), but Ileakage (Vdd ) and Tcycle are strongly influenced
by PV. The measured Eswitch (Vdd ) and Ileakage (Vdd ) are shown in
Figure 3 and Figure 4. Since low-power (LP) process is used in our
implementation, the leakage energy is quite small compared to theswitching energy.
To probe the internal signals on the wafer, the prototype chip uses
analog I/O cells and pads. Unfortunately, these I/O cells and pads
present very heavy loadings to the output signals, hence preventing
us from measuring the achievable Tcycle , in spite of the fact that all
the three cores can reach 2GHz at 1.2V Vdd . In the following analysis
simulation results are used to resolve this issue. Our simulation isbased on the recently released PSP model from Philips, which claims
superior accuracy over the BSIM4 when modeling Ion at low Vdd .
We do not expect the Tcycle difference between silicon measurement
and simulations to change our conclusions significantly.
In Figure 5, assuming α = 30%, the energy-efficiency of each coreat different Vdd s are normalized to the energy-efficiency of the baseline core (Core A) at 1.2V Vdd . For multimedia processors α = 30%

626

100

1

20

90
0.8

80

4
0.6

Eswitch (nJ)3Parallel Degree

3.5
0.4
0.4

2.5

0.5

0.6

2
1.5

70

10

60

5

50

Core A

15

Core B
Core C

0

40
30

1

20

0.5

10

0

0

Vdd (V)

Fig. 3.

Fig. 6. The associated parallel degree of core (A),(B),(C) at different
Vdd s from simulation

critical parallelism degree according to the famous Amdahl’s Law[13] [14]. The speedup from having more parallelism than this criticaldegree will saturate. For example, only 32× speedup is observed on
a 128-core system [15]. Therefore, making a good trade-off between
the parallelism degree and the energy-efficiency becomes extremely
cruicial at the sub/near threshold region. At 0.5V Vdd , Core C,
which has the deepest pipelining, still needs 10 units performing inparallel to satisfy the throughput, meanwhile gaining about 5× energy
reduction. Recall that the control overhead caused by pipelining andparallelism has been completely ignored, so this 5× reduction canbe far beyond what we could reach in a real processor. While many
papers claim a near 10× higher energy-efficiency, they usually do
not appreciate these difficulties to maintain a high throughput.

Measured Ileakage at different Vdd s and process conditions

Fig. 4.
987Energy Reduction

Measured switching energy Eswitch at different Vdd s

6
5
4

5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1

Core A
Core B
Core C

IV. P ITFALL 3: ASSUME MEMORY ’ S Vdd AND ENERGY COULDSCALE AS WELL AS STANDARD CELLS

3
2
1
0

Vdd (V)

Fig. 5. Normalized energy-efficiency of core (A),(B),(C) at different
Vdd s (α= 30%)

is quite common, and for general purpose processors α is typicallysmaller due to very low activity on memories and caches [12]. From
Figure 5, it is clear that the lower the Vdd , the higher the energyefficiency. However, to compenstate for throughput degradation, theassociated parallelism degree from simulations is shown in Figure 6.
Once Vdd scales to below 0.5V, the number of needed parallel units
increases sharply. A larger parallel degree implies a larger silicon area
and an increased layout difficulty (e.g., global/semi-global routing).
It also means a further degraded yield since the fabrication defects
increase in an exponential way when the silicon area increases, i.e.,
Y ield ∝ e−Area . Assume the imperfect dice for circuits having only
one unit is 100 p.p.m (part per million), then the imperfect dicefor circuits having 100 parallel units quickly goes to 10000 p.p.m.
In addition, depending on the targeted applications, there is also a

When analyzing the energy of an ultra-low-Vdd processor, someresearchers assume that memory’s Vdd and energy could scale aswell as standard cell based logic in their performance modelingtools. However, current practice is that memory is not as resilient
as standard cells to Vdd scaling. Commercial 6-T SRAMs which
achieve high density fail at 2/3 of the nominal supply due to static
noise margin (SNM) degradation [16] [17]. The data stored in bitcell is susceptible to a very small injected bitline noise and may
flip. Some recent SRAM chips can scale reliably to below 0.4V [18][19] [20] [21] [22]. To improve SNM, these works either add extra
devices within bit-cell or enlarge bit-cell’s size. However, they also
introduce considerable area and performance overheads compared tocommercial SRAMs. As an example, to build a SRAM block with thesame dimension, the MIT 10-T SRAM realization is 66.7% bigger
and 3× slower (at 0.7V and above) than SRAMs that are synthesizedwith a commercial low-power memory generator. The low density,
low speed and high energy consumption in the super-threshold modeare big limitations for these proposed works [23] to be applied in
medium/high speed consumer electronics.
SRAMs bitcells’ energy accounts for more than 80% of SRAMs’
total energy, while other components such as sense-amplifiers, wordline/bitline drivers, address decoders and writing circuits only occupy
less than 20% [24]. Therefore, SRAMs bitcells’ energy is the mainconcern in our analysis. We approximate the delays of logic celland SRAM bitcell by Equations (4) and (5). Equation (6) and (7)are also our approximation for switching energy of logic cell and627

Vswing

logic

memory
2.5X

2.7X

2.9X

3.2X

excessive swing

V
0.6
ry
mo .5Vme ic 0
log
V
1.2
ry
mo .2Vme ic 1
log

V
0.6
ry
mo .5Vme ic 0
log
V
1.2
ry
mo .2Vme ic 1log

Fig. 7.

V
0.6
rymo .5Vme ic 0
log
V
1.2
ry
mo .2Vme ic 1
log

Vdd

V
0.6
ry
mo .5Vme ic 0
log
V
1.2
ry
mo .2Vme ic 1log

required swing(a) R = 70/30(b) R = 60/40(c) R = 50/50(d) R = 40/60

Illustration: the actual and required bitline swings when Vdd

scalesFig. 8.
The normalized energy vs. R from simulation. R signifies(M emory energy) / (Logic energy) at the non-scaled 1.2V.

SRAM bitcell in one clock cycle. Cload is the loading capacitances
including both gate and interconnection wire capacitances. Idrive isthe average charging/discharging currents. Cbitline and Ibitline are
the loading capacitance and the average current on a SRAM bitline.
Vswing is the bitline swing, which must exceed a minimum magnitude(e.g., 10% nominal Vdd ) required by sense-amplifiers to make correct
decisions.
ST DCelldelay ∝ Cload Vdd /Idrive(4)

SRAM Bitcelldelay ∝ Cbitline Vswing /Ibitline(5)

EST DCell ∝ Cload Vdd Vdd(6)

ESRAM Bitcell ∝ Cbitline Vdd Vswing(7)

Vswing cannot scale with Vdd . Contrarily, according to our simulation, the actual Vswing may even increase because of process
variations. The required minimum Vswing also increases slightly
due to degradation on sense-amplifiers’ sensitivity, as illustrated in
Figure 7. From Equation (4) to Equation (7) we can conclude that :1) when Vdd scales, SRAMs’ speed deteriorates faster than standard
cells. In other words, if both SRAMs and logic scale to the same Vdd ,the SRAMs will become the performance bottleneck. 2) SRAMs’energy can only scale (sub-)quadratically with Vdd , in contrast to
standard cells’ quadratic relationship with Vdd . These conclusions caninterpret the simulation results provided in [16], and they hold true
for both differential and single-ended SRAMs. Our SRAM models
in Equation (5) and (7) are quite simple, so they can be used as arule-of-thumb for quick estimation.
For processors operating at the non-scaled Vdd , it sometimes
happens that the memory’s energy dominates the total processor’s
energy, e.g., 70% of video processors’ energy is consumed by frame
memory [23], 95% of NoC (Network-on-Chip)’s energy is consumed
by memory hierarchy and foreground memory [25]. Even for embedded microprocessors, the energy contribution of instruction and data
memories can be up to 40% [26]. We introduce a factor R, which
represents the ratio between memory’s energy and logic’s energy inapplication benchmarks at the non-scaled 1.2V. Let us assume that
the Vdd of logic scales to 0.5V and the Vdd of memory scales to 0.6V,
otherwise memory’s speed becomes the system bottleneck. Figure 8
depicts the normalized energy when R changes from 70/30 to 40/60.

From this figure, a 3× higher energy-efficiency can be a realistic
expectation for processors consisting of both memory and logic.
V. P ITFALL 4: ASSUME HIGHEST TEMPERATURE AS THE WORST
TIMING CASE

Temperature directly affects digital gate’s delay. For commercial
standard cell library which operates at nominal Vdd , the worst timing
corner case happens at the highest temperature (e.g., 125 ◦ C). We
notice that some sub/near threshold works still report the performanceat high temperature as the worst timing case. However, an inversed
worst case happens at ultra-low Vdd s, i.e., low temperature (e.g.,−25 ◦ C) becomes worst case corner instead of traditional hightemperature.
The driving current of an nMOSFET is modeled as:

Ion ∝


(Vgs −Vth (T )) µ(T )eS(T )µ(T )(Vgs − Vth (T ))β

(Vgs < Vth )(8)(Vgs ≥ Vth )where µ(T ) is the carrier mobility that is intrinsic to the process,β is the velocity saturation effect factor and S(T ) is the subthreshold swing. µ(T ), S(T ) and Vth (T ) are temperature dependent
parameters.
As temperature dereases, the carrier mobility µ(T ) increases,
which tends to increase the driving current. Meanwhile, Vth (T )increases and sub-threshold swing S(T ) reduces, which tend to
reduce the driving current. In the super-threshold region, both µ(T )and Vth (T ) have near linear effects on Ion . The influence from µ(T )is slightly stronger, so the combined effect results in an increased
Ion and hence digital gates run faster. In the sub-threshold region,
Vth (T ) and S(T ) have an exponential and dominant influence on Ion .
As a result, the combined effect shows a significantly reduced Ion
hence digital gates run much slower. Figure 9 shows the simulated
gate delay at varied temperature, which is normalized to the delay
at 125 ◦ C temperature. As seen, from 125 ◦ C to −25 ◦ C, the gate
which operates at nominal Vdd gains speedup by 12%, however, thegate operating in the sub-threshold region becomes up to 16× slower.
This means that negative temperature can be even as detrimental as
process variations to the sub/near threshold designs! It is thus ofgreat importantance to have standard cell libraries characterized at
low temperatures and use the lowest temperature case as the worst
corner in sub/near threshold designs.

628Normalized delay

Normalized delay

A: PMOS
B: NMOS
C: CMOSFig. 11.
temperaturetemperature

(a)

(b)

Logarithm to base 10 of Normalized Delay

Fig. 9. Simulated gate delay at different temperatures, with normalization
to delay at 125 ◦ C (a) at 0.5V Vdd (b) at 1.2V nominal Vdd
3.5
3
2.5
2
1.5
1
0.5
0
-0.5

Vdd (V)

Fig. 10. Simulated delay of Core C at different Vdd s under TT, SS, FF
conditions, with normalization to its delay at 1.2V under TT condition

VI. P ITFALL 5: PVT COMPENSATION USING JUST- IN - NEED Vdd
WITHOUT CONSIDERING LOSS ON DC-DC
The Tcycle in a processor is limited by the slowest pipelining
stage. Temperature changes and process variations (including die-todie (D2D), within-die (WID) and random variations) result in a very
wide spread of delay in the sub/near threshold region. According to
the Monte-Carlo simulation, for the three cores introduced in Section
III, 50mV Vdd guardbanding is enough for compensating the effects
of WID and random variations in the sub/near threshold region. In
addition, logic paths with longer logic depth Ld has smaller delay
variability because the total delay attempts to average out timing
variability from each individual gate. However, targeting at the worst
case, i.e., the SS corner, more guardbandings must be reserved.
Taking Core C as an example, its delays at the scaled Vdd s under
different process conditions are normalized to its delay at the 1.2V
Vdd under TT condition, and the logarithm results are plotted in
Figure 10. As seen, at the SS corner, the Vdd should be increased toaround Vdd + 100mV to meet the speed at Vdd under TT condition,
so the energy-efficiency will decrease. If temperature change is also
considered, the guardbandings should be increased further.
To reduce the guardbandings hence the energy, many papers
propose to use just-in-need Vdd with delay sensing schemes. Someof them also propose to use bulk-biasing with variable Vp−well and
Vn−well , e.g., [27]. With these approaches, the most appropriate
voltages can be employed for each individual die, e.g., a lower Vdd

Diagram of T6 DC-DC converter

can be used for faster chips while a higher Vdd can be used for
slower chips. However, researchers often do not care the energy
overhead to generate these ultra-low Vdd power supplies. Ideal power
supplies with 100% efficiency were assumed. This assumption canbe accepted for conventional Vdd scaling from nominal Vdd to 2/3
nominal Vdd because DC-DC efficiency can be easily above 90%
within this region. However, the MIT’s MSP430-like DSP [3], which
is so far the only sub/near threshold Vdd system that has an embedded
DC-DC converter, observed that the low efficiency for converting
voltages from a off-chip battery level to a sub/near threshold level isa major bottleneck limiting system energy reduction.
In our study we exploited the MIT’s switched capacitor DC-DC
converter architecture [28]. This architecture is the most suitable forultra-low-Vdd conversion. Other two well-known architectures, i.e.,
Low-Dropout (LDO) and Buck-Boost, are not good options in ourcase, because (1) LDO cannot perform well when the gap between
input and output voltages is large; (2) Buck-Boost needs big inductor,
so it is difficult to be integrated fully on-chip unless some special
techniques such as bondwire spriral inductor [29] or 3-D stacked
process can be used.
The theoretical maximum efficiency that can be achieved by thisarchitecture is:η = 1 − ∆V /VN L(9)The VN L is the no-load output voltage and the ∆V is thedifference between the actual ouput voltage Vout and VN L , i.e.,∆V = VN L − Vout . Therefore, the higher the ∆V , the lower the
maximum achievable conversion efficiency. The difference between
the MIT’s and our designs is that we use only the T6 topology since
we need a narrow output voltage band (0.4V∼0.6V), whereas theMIT’s design switches among T4 ∼T12 topologies to cover also superthreshold output voltage range. The T4 , T6 , T8 , T9 and T12 aredifferent topologies to generate VN L s of VBattery /3, VBattery /2,
2VBattery /3, 3VBattery /4 and VBattery . The diagram of T6 topology is shown in Figure 11.
Although we had employed the state-of-the-art DC-DC architecture, we still saw a low efficiency for converting an off-chipbattery voltage to the sub/near threshold region. This is because theresistances of power switch transistors become exceedingly large ata very low Vdd such that a high ∆V is unavoidable. In addition
to the fundamental energy loss on power switch transistors, theoverheads from bottom-plate parastic capacitors, control circuits andgate-drive loss also decrease the efficiency. We fabricated two DCDC converters, one with on-chip capacitors and the other with offchip capacitors. The layout views and die photos of the two DCDC converters are shown in Figure 12 and Figure 13. The measured

629

Efficiency

Efficiency

Iout = 4 mA

Iout = 4 mA

Iout = 8 mA

Iout = 8 mA

Iout = 12 mA(a)On-chip cap
Vbattery = 1.2V(b)Off-chip cap
Vbattery = 1.2V(b)

Switched capacitor DC-DC converters with on-chip capacitors(a)layout view (b)die photoFig. 12.

Efficiency(a)Vout (V)

Efficiency

Vout (V)

Iout = 12 mA

Iout = 4 mA

Iout = 4 mA

Iout = 8 mA
Iout = 12 mA(c)
On-chip cap
Vbattery = 1.5V

Iout = 8 mA(d)Off-chip cap
Vbattery = 1.5V

Vout (V)

Iout = 12 mA

Vout (V)Fig. 14. Efficiency of DC-DC converters: (a) with on-chip capacitor,
VBattery = 1.2V (b) with off-chip capacitor, VBattery = 1.2V (c) withon-chip capacitor, VBattery = 1.5V (d) with off-chip capacitor, VBattery= 1.5V(a)(b)

Switched capacitor DC-DC converters with off-chip capacitors(a)layout view (b)die photoFig. 13.

conversion efficiency from 1.2V and 1.5V battery voltages to thesub/near threshold region with varied output current loads is plottedin Figure 14. This figure shows that: 1) Vout can never reach VN L
due to the fundamental conduction loss on power switches. 2) When
Vout increases, the conduction loss reduces linearly, so the conversion
efficiency gradually grows and eventually reaches a peak. After thatthe efficiency quickly decreases because the energy overhead fromcontrol circuits dominates the total energy. 3) The energy loss due tobottom-plate parasitic capacitors for DC-DC with on-chip capacitors
is quite severe, which can be more than 10%.
The achievable peak conversion efficiency from a battery voltage
to a near-threshold voltage is around 70%, which is close to themeasurement results from the MIT group. Therefore, unlike operatingprocessors near the non-scaled voltage where DC-DC efficiency canbe constantly over 90%, the DC-DC energy cost becomes a big
challenge for sub/near threshold designs. Although we will continue
improving the efficiency, the headroom for further improvement isalready rather limited by the intrinsic energy losses on the powerswitch transistors and the bottom-plate parasitic capacitors.
Taking the DC-DC converter’s efficiency also into account, theachievable energy gain from using a sub/near threshold Vdd decreases
by 30% immediately. In addition, when exploiting a just-in-need
Vdd to reduce guardbandings, one should also pay attention to thelinearly decreased DC-DC efficiency as Vdd decreases. The growing
DC-DC energy loss largely counteracts the energy savings obtained
from lowering the Vdd of processors. Since there are cases where theenergy consumption of SoCs is dominated by SRAMs whose energy

consumption is almost linearly dependent on Vdd , it may not be ofuse to further lower the Vdd . Besides, if the overhead of complicated
PVT sensing schemes is also included, the energy benefit from using
a just-in-need Vdd in a real system with embedded DC-DC converters
can be greatly exaggerated in some earlier papers.
VII. C ONCLUSION
Scaling Vdd to the sub/near threshold is the way to ultra-low
energy processors. However, many of us doing research in this fieldrecognize that it is necessary to have reflections on existing sub/nearthreshold circuit techniques. This paper has carefully investigated five
pitfalls often not appreciated by researchers. These pitfalls lead to an
overestimation of the actual energy benefit from using a sub/nearthreshold Vdd in many earlier papers. To make the dream of 10×energy reduction for consumer electronics come true, more efforts
should be made other than aggressive Vdd scaling alone. The future
directions in this field are, but not limited to:630

Currently conventional super-threshold processes are being used
to demonstrate subthreshold circuit ideas. Devices that are
optimized for sub/near threshold regime with larger Ion andlower Vth variability) are preferred. For example, compared tousing conventional bulk CMOS processes, fully depleted siliconon-insulator (FDSOI) CMOS technology shows lower RDF andsmaller subthreshold swings. For instance, a RISC processor
in FDSOI process which operates at ultra-low-Vdd with greatly
enhanced computational energy efficiency has been introducedin [30].
• For logic-centric circuits whose energy almost depends quadratically on Vdd , it is worthwhile exploring a lower Vdd eventhough the linear energy loss on the DC-DC converter is taken
into account. To recover throughput, architecture-level solutions(e.g., efficient parallelism) can be helpful but must be used withcautious.
• Make memory’s energy super-linearly dependent on Vdd , being
different from its present form where the energy depends linearly•

on Vdd . Otherwise Vdd scaling cannot be very effective for thosememory-centric SoCs whose energy is dominated by memories.
• Explore more energy-efficient DC-DC converters whose conversion efficiency can be almost independent of output Vdd . In
this paper we used on-chip switched capacitor DC-DC for afair comparison. Following which, buck-boost DC-DC with 3-D
stacked inductors is marked on our roadmap.
ACKNOWLEDGMENT
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the New Energy and Industrial
Technology Development Organization (NEDO).
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