Variable Gate Current Range Digital Gate Driver IC
Always Providing 6-bit Controllability
in Various IGBTs
Haoxi Zhou, Toshiaki Inuma, Dibo Zhang, Katsuhiro Hata, and Makoto Takamiya
The University of Tokyo, Tokyo, Japan
Abstract— To eliminate the need to redesign digital gate
driver (DGD) ICs for each of a wide variety of power devices,
the world’s first variable gate current (IG) range DGD (VIRDGD) ICs with variable maximum IG and resolutions areproposed. The innovation of VIR-DGD ICs is that a variable
resistor on PCB allows one-bit IG (I1BIT) to be freely varied,
thereby maintaining 6-bit controllability of DGD at all times fora wide variety of power devices. A 6-bit VIR-DGD IC withvariable maximum IG from 0.51 A to 5.1 A and I1BIT from 8.1
mA to 81 mA has been developed. The trade-off problem
between loss and noise during turn-on has been successfully
solved by an active gate driving using the VIR-DGD IC for twotypes of IGBTs with twice the rated current.

II. PROPOSED VARIABLE IG RANGE DIGITAL GATE DRIVERICFigs. 1 and 2 show a circuit schematic and a timing chart ofthe proposed VIR-DGD IC, respectively. In the following,turn-on is discussed for simplicity, whereas the exact same istrue for turn-off. This 6-bit DGD IC is based on the DGD IC
in [6], and differs from [6] in the following two points: (1) theability to change VGS (PMOS) amplitude of the 6-bit pMOSFETs
in the output stage with an analog voltage (CONTPMOS) via a
variable resistor (R2) on PCB to realize a variable IG function,and (2) the addition of tON, tOFF generator (TGEN), which
generates the timing signals that define the time slots (tON) ofthe DGD using on-chip voltage controlled oscillators. Theequation for IG is shown in Fig. 1. The innovation of the VIRDGD IC is that it can always achieve 6-bit controllability fora wide variety of power devices, because the 1-bit IG (I1BIT) isvariable. As shown in Fig. 2, IG can be varied 9 times with 6bits ( = 64 levels) in a tON time slot. Fig. 3 shows a die photoof VIR-DGD IC fabricated with 180-nm BCD process.

Keywords— IGBT, IC, surge current, energy loss, active gatedriver

I. INTRODUCTION
Digital gate drivers (DGD) ICs, which digitally change thegate current (IG) multiple times in fine time slots during theswitching period of power devices, are attracting attention asa technology that can solve the trade-off problem between loss
and noise during power device switching [1-8]. In allconventional DGD ICs [1-8], the IG range and steps are fixed
for each IC. Different power devices require different IG
ranges and steps, which means that DGD ICs must beredesigned for each power device, which has been one of thechallenges for the practical application of DGD ICs. Forexample, in a 6-bit DGD IC, when more than half of themaximum IG is not needed, one bit of MSB is not used, andthe IC operates as a 5-bit DGD, thereby preventing DGD fromfully utilizing the original 6-bit IG controllability. To solve theproblem, in this paper, a world’s first variable IG range DGD(VIR-DGD) IC is proposed.

III.

MEASURED RESULTS

Fig. 4 shows the measured nPMOS dependence of IG at threedifferent I1BIT values of 81 mA (maximum value), 41 mA, and0.51 mA (minimum value), where nPMOS is a 6-bit control bitof IG and is an integer from 0 to 63. To measure IG, a 10 F
capacitor is connected to the output of DGD. As shown in Fig.
1, R1 on PCB is fixed at 27 k, and by varying the variable
resistor R2 on PCB, VGS(PMOS) amplitude is varied to change
I1BIT. Specifically, VGS(PMOS) amplitudes are 5.0 V, 3.0 V, and
1.7 V when I1BIT is 81 mA, 41 mA, and 0.51 mA,respectively.Variable IG range and I1BIT are demonstrated.

Variable IG range
digital gate driver (VIR-DGD) IC
5V

R1VGS(PMOS)SIPO 108
PISOs

R2CONTPMOS

Level shifternPMOS 1WP
IO

15 V
32WP
32IO

Pre-drivers

CONTNMOS
5V

R3R4VGE

IO

Scan In
Scan CLKIN

SIPO 108

CONTON
CONTOFF

TGEN

nNMOS
1WN
6PISOsSerial-in parallel-out shift register (SIPO)
Parallel-in serial-out shift register (PISO)
tON, tOFF generator (TGEN)

VGS(NMOS)

32IO
32WN

VCE

15 V

IG = nPMOS×I1BITnPMOS : Integer from 0 to 63
I1BIT : Any number between 8.1 mA and 81 mA

Fig. 1. Circuit schematic of proposed variable IG range DGD (VIR-DGD) IC.

979-8-3503-1664-3/24/$31.00 ©2024 IEEEICIG1125

tON tON tON tON tON tON tON tON
INtON tONtOFF tOFF tOFF tOFF tOFF tOFF tOFF tOFF
OffOn

On

63nPMOS

063nNMOS0

IG 0 A
15 V

VGE
−15 V

IC

IOVERSHOOTIL
0A
600 V

VCE
0V

Fig. 2. Timing chart of proposed VIR-DGD IC.

IGBTmodule2.0 mmPredrivers

IL

6-bit
pMOSdrivers

600 V

VIR-DGDIG
VGE

Predrivers

6-bit
nMOSdrivers

VCEIC

Name

Model numberRatingIL

I1BIT

IGBT1 FS100R12N2T4P 1200 V, 100 A 40 A 81 mA
IGBT2 FS50R12KT4_B11 1200 V, 50 A 20 A 41 mA

2.5 mmFig. 5. Circuit schematic of double pulse test.

Fig. 3. Die photo of VIR-DGD IC.

6Measured

5.1 A

5IGBT module

IG [A]

43VIR-DGD IC

2.6 A

21000.51 A
10203040nPMOS50Fig. 6. Measurement setup.

60

Fig. 4. Measured nPMOS dependence of IG at three I1BIT values.

Figs. 5 and 6 show a circuit schematic and a measurement
setup of the double pulse test using the developed VIR-DGD
IC and IGBT modules, respectively. To demonstrate thefunctionality of the VIR-DGD IC, VIR-DGD IC with varied
I1BIT is applied to two types of IGBTs (IGBT1 and IGBT2)

with twice different current ratings, as shown in the table inFig. 5. Figs. 7 (a) and (b) show timing charts of theconventional single-step gate driving (SGD) and the proposed
active gate driving (AGD) at turn-on for comparison,respectively. In SGD, n is varied, which emulates aconventional gate driver with varied gate resistance. In AGD
with 140 ns × 4 slots and last long slot, four parameters (n1 ton4) are varied.

1126

IGOnn6300A(a) Conventional single-stepgate driving (SGD)

Off
n1nPMOS 63

n2Conv. SGD

0.8

10IN

0.7

Point A

8 0.6
0.5

640.3
0.2

On2n3

0−50%

0.4

Point B
−39%
Point C
Point D

0.1 Proposed AGD

n4010

20030

40

6050

IOVERSHOOT [A] IOVERSHOOT, MAX(a)0AELOSS, MAX

IGIGBT1IL = 40 A

12ELOSS [mJ]nPMOSOffELOSS, MAXIN

140 ns(b) Proposed active gate
driving (AGD)

ELOSS [mJ]Figs. 8 (a) and (b) show the measured switching loss(ELOSS) vs. collector current overshoot (IOVERSHOOT) of theconventional SGD and the proposed AGD in IGBT1 (loadcurrent (IL) = 40 A, I1BIT = 81 mA) and IGBT2 (IL = 20 A, I1BIT= 41 mA), respectively. The black curves show the trade-offcurves for SGD with varying n. In this paper, an evaluation
function (fOBJ) shown in Eq. (1) [1-2, 8] is defined as aperformance index of gate driving, and it is discussed that agate driving with small fOBJ is an excellent gate driving withsmall ELOSS and IOVERSHOOT.
20.8
4 0.7

Fig. 7. Timing charts at turn-on. (a) Conventional single-step gatedriving (SGD). (b) Proposed active gate driving (AGD).

Conv. SGD

0.6
30.4

210

Point E

0.5

0.3

0

Point F−28%

0.2

Point H−20%
Point G

0.1

Proposed AGD
102030

IOVERSHOOT [A]4050
IOVERSHOOT, MAX(b)2 ELOSS   I OVERSHOOT f OBJ =  +  ,E
 LOSS, MAX   I OVERSHOOT, MAX IGBT2IL = 20 A

5Fig. 8. Measured ELOSS vs. IOVERSHOOT. (a) IGBT1 (IL = 40 A, I1BIT = 81mA). (b) IGBT2 (IL = 20 A, I1BIT = 41 mA).

()

where the subscript MAX signifies the maximum of thecorresponding quantity. The dotted concentric curves in Fig.
8 show the contour of fOBJ. In the the proposed AGD, thedouble pulse tests are repeated more than 2500 times, and eachtime ELOSS and IOVERSHOOT are measured to calculate fOBJ
defined in Eq. (1), and the combination of the four parameters(n1 to n4) that minimizes fOBJ is searched using the simulated
annealing algorithm [1].
In Fig. 8 (a), Points C and D are the best points with thesmallest fOBJ obtained by repeating the search for two trials.
Since the simulated annealing algorithm cannot find the true
optimal point, the optimal point obtained by the simulated
annealing algorithm is different each time. Since Points C andD are nearly identical in Fig. 8 (a), this confirms that the search
for the combination of the four parameters (n1 to n4) using thesimulated annealing algorithm is reasonable. Points A and B
are the conventional SGD points with IOVERSHOOT and ELOSS
approximately the same as the proposed Point C, respectively.

As shown in Fig. 8 (a), compared with SGD, the proposed
AGD (Point C) reduces ELOSS by 50 % under IOVERSHOOTaligned condition and reduces IOVERSHOOT by 39 % nder ELOSSaligned condition.
Fig. 8 (b) for IGBT2 (IL = 20 A, I1BIT = 41 mA) is exactly
the same as Fig. 8 (a) for IGBT1 (IL = 40 A, I1BIT = 81 mA).
Points G and H are the best points with the smallest fOBJ
obtained by repeating the search for two trials. Points E and F
are the conventional SGD points with IOVERSHOOT and ELOSS
approximately the same as the proposed Point G, respectively.
As shown in Fig. 8 (b), compared with SGD, the proposed
AGD (Point G) reduces ELOSS by 28 % under IOVERSHOOTaligned condition and reduces IOVERSHOOT by 20 % nder ELOSSaligned condition.
Figs. 9 and 10 show corresponding measured waveformsof Points A to D in Fig. 8 (a) and Points E to H in Fig. 8 (b),respectively. In Fig. 9 (c), the proposed AGD (Point C)
achieves low ELOSS and IOVERSHOOT by setting nPMOS to 1 just1127

ELOSS : 8.7 [mJ]

ELOSS : 2.6 [mJ]

VCE： 100 V/div

500 ns/div

Point A

Point E

500 ns/div

IC: 15 A/div
VGE: 15 V/div

IC: 15 A/div

00nPMOSnPMOS

VGE: 15 V/div
20(a) Point A (Conv. SGD, n = 2)
ELOSS : 4.3 [mJ]

VCE： 100 V/div
40(a) Point E (Conv. SGD, n = 4)
ELOSS : 1.9 [mJ]

500 ns/div

500 ns/div

Point B

Point F

IC: 15 A/div
VGE: 15 V/div60

VGE: 15 V/div0

VCE： 100 V/divnPMOSnPMOS0

IC: 15 A/div(b) Point B (Conv. SGD, n = 6)

VCE： 100 V/div
70(b) Point F (Conv. SGD, n = 7)
ELOSS : 1.8 [mJ]

ELOSS : 4.3 [mJ]
500 ns/div

500 ns/div

Point C

Point G

IC: 15 A/div
VGE: 15 V/div01525441

VCE： 100 V/div

063nPMOSnPMOS0

IC: 15 A/div

140 ns×4 slot(c) Point C (Proposed AGD)

VGE: 15 V/div
VCE： 100 V/div
04130
429140 ns×4 slot(c) Point G (Proposed AGD)
ELOSS : 2.0 [mJ]

ELOSS : 4.2 [mJ]
500 ns/div

500 ns/div

Point D

Point H

IC: 15 A/div
VGE: 15 V/div

IC: 15 A/div

VCE： 100 V/div

63570

VGE: 15 V/div

0

VCE： 100 V/div
13063nPMOS

nPMOS

063

140 ns×4 slot(d) Point D (Proposed AGD)

6033032863

140 ns×4 slot(d) Point H (Proposed AGD)

Fig. 9. Measured waveforms of Points A to D in Fig. 8 (a).

Fig. 10. Measured waveforms of Points E to H in Fig. 8 (b).

1128

before the timing of IOVERSHOOT. As shown in Figs. 9 (c) and(d), the optimal n1 to n4 for Points C and D obtained in the twotrials are different, while ELOSS and IOVERSHOOT of Points C andD are almost identical as shown in Fig. 8 (a). Similarly, as
shown in Figs. 10 (c) and (d), the optimal n1 to n4 for Points Gand H obtained in the two trials are different, while ELOSS andIOVERSHOOT of Points G and H are almost identical as shown inFig. 8 (b).

[4]

In this paper, the measured results of turn-off are notdiscussed, because the trade-off curves as shown in Figs. 8 (a)and (b) for ELOSS and VCE overshoot at turn-off were notobserved. Table I shows a comparison table of DGD ICs. This
work is the first to realize 6-bit DGD ICs with variablemaximum IG from 0.51 A to 5.1 A and I1BIT from 8.1 mA to81 mA, while achieving the 30 V output voltage swing
required to drive IGBTs.

[6]

[5]

[7]

[8]
TABLE I.

COMPARISON TABLE OF DGD ICS

TPEL’21[4]
Target powerdeviceProcess
Max output
voltage swing
IG change perswitching

TPEL’21[3]

ECCE’22 TPEL’23
This work
[5]
[7]
SiC
SiC
Si IGBTMOSFET MOSFET
180 nm
500 nm
180 nmBCD
HV CMOSBCD

GaN FETGaN FET

180 nm BCD

180 nm HVCMOS

4.8 V

5V

30 V

18 V

30 V

8104

330

98 bit (coarse),
Levels of IG
7 bit
6 bit (fine)
IG range
Fixed
Fixed
4.8 V / 1.1 Ω 5 V / 0.12 Ω
Max IG= 4.4 A= 42 A1 bit of IG (I1BIT)
35 mA
2.6 mA

6 bit

3 bit

6 bit

FixedFixed

Variable

22 A

3.6 A

0.51–5.1 A

340 mA

510 mA

8.1-81 mA

IV. CONCLUSIONSThe VIR-DGD ICs, which can always achieve 6-bit DGD
controllability for a wide variety of power devices, areproposed to provide active gate driving with appropriate IG
steps at all times. To demonstrate the functionality of the VIRDGD IC, VIR-DGD IC with varied I1BIT is applied to twotypes of IGBTs icluding IGBT1 (100 A rating, IL = 40 A, I1BIT= 81 mA) and IGBT2 (50 A rating, IL = 20 A, I1BIT = 41 mA).
In the turn-on measurements of IGBT1 and IGBT2 at 600 V,
compared with the conventional SGD, the proposed AGD
using VIR-DGD IC reduces ELOSS by 50 % and 28 % under
IOVERSHOOT-aligned condition and reduces IOVERSHOOT by 39 %and 20 % under ELOSS-aligned condition, respectively.
ACKNOWLEDGMENT
This work was partly supported by NEDO (JPNP21009).
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