P-5

A Design Methodology of Chip-to-ChipWireless Power Transmission SystemKohei Onizuka1, Makoto Takamiya1, and Takayasu Sakurai2
1Institute of Industrial Science and 2Center for Collaborative Research, University of Tokyo, Tokyo, Japan

Abstract— A design methodology to transmit power using achip-to-chip wireless interface is proposed. The proposed powertransmission system is based on magnetic coupling, and the powertransmission of 5mW/mm2 was verified. The transmission
efficiency trade-off with the received power is also discussed.

Upper Chip

Lower Chip

DL L2
RF+ 1

D+RL

TransmitterRF-kFig. 2. Circuit diagram of proposed system.

A. Circuit Topology
Fig.2 shows the circuit diagram of the proposed system. The
lower chip includes a transmitter circuit and an on-chip planarinductor L1 whose outer diameter is 700µm for magnetic field(a)(b)
Fig. 1. Concept of chip-to-chip wireless power transmission (a) assisting
wireless interchip communication and (b) for system modification afterfabrication.

xyLower Chip
UpperChip

Upper Boardz(a)(b)
Fig. 3. (a) Whole image and (b) closeup view of measurement setup.

generation. The transmitter circuit generates an RF signal fromthe DC supply voltage VDD and activates L1. The power istransmitted by magnetic fields rather than radio waves. Theupper chip includes an on-chip planar inductor L2, a full-wave
rectifier circuit using MOSFET-based diodes and a smoothing
capacitor.
B. Simulation and Measurement Results
The system shown in Fig.2 was designed in 0.35-µm CMOS
and fabricated. Fig.3 shows the measurement setup. The lower(upper) chip is mounted on the lower (upper) board and the twochips gets closer together face-to-face. Fig.4 shows thesimulated and measured received power dependence on output
DC voltage. In this implementation, L1=1.0nH, L2=9.3nH andthe oscillation frequency is set to fTX= 330MHz for this graph.
Output voltage is varied by changing DC output load RL. The
peak transmitted power 2.5mW which equals to 5mW/mm2 isobserved when RL is 100Ω, which is the equivalent source
resistance of the wireless power source. Fig.5 show themeasured output voltage dependence on ∆x and ∆y, and ∆z
when the load is open which equals to RL=∞.
Transmitted Power (mW)

II. TEST CIRCUIT

Lower Board

I. INTRODUCTION
A System-in-a-Package (SiP) is getting a major 3D
integration approach in recent years. For data communication
among stacked chips in SiP’s, wireless data transmission
technologies have been investigated for high speed, low power
and low cost [1]. Power delivery in these systems, however, is
not wireless and is based on bonding. Then, it is difficult to get
two stacked chips close, since the bonding needs several
hundred microns separation between chips. One solution is toskew the stacked chips but this is difficult if the upper chipshould be connected in the middle of the lower chip and iscovered by the topmost chip.
If the power is supplied wirelessly, the chips can be stacked
closely and the wireless data transmission performance will beincreased, since the data bandwidth and communication
reliability increases as the chip-to-chip distance is decreased inwireless data communication. The cost is also decreased due tothe elimination of mechanical bonding. Furthermore, chip
detachability can also be achieved by combining the wirelessdata and power transmission. This opens up a totally new
system customization scheme after the fabrication as wesometimes change a daughter board for system upgrade. Fig.1
illustrates the proposed concepts.

3RL=100Ω
210Measured
Simulated
0.2 0.4 0.6 0.8 1 1.2 1.4
Output Voltage (V)Fig. 4. Transmitted power dependence on output voltage.

0.800Δy (µm) 280

RS C1

1.6
Output Voltage (V)Output Voltage (V)

1.6

280
560 Δx (µm)

R1R2

L10.8

L 2 C2RL_AC

800400Δz (µm)

1200(a)(b)
Fig. 5. Output voltage dependence on ∆x and ∆y, and ∆z.

RXEjω

k0

RYRS+R1Ejω

(a)(b)
Fig. 6. (a) Simplified circuit model and (b) equivalent circuit underresonance condition.

III. CIRCUIT OPTIMIZATION
80150

L _ AC2.

Here, we assume the transmitted power is high (if notmaximized) when transmitter circuit is in resonance. That is, C1
is expressed as follows. Although this condition does not givethe optimum condition, the resultant transmitted power is atleast achievable.
(2)
1C1 =

4 π 2 f TX2 L1 .

On the other hand, C2 resonates under the following condition
and the circuit model can be converted to a simple resistancemodel as shown in Fig.6 (b).
(3)
4 π 2 f TX2 R L2 _ AC L2 C 22 − R L2 _ AC C 2 + L2 = 0.
RX and RY are the transformed impedances of R2 and RL. In thissystem, high power efficiency is as important as the transmitted
power to increase the variety of applications. The powertransmission efficiency for RY is maximized when
RS + R1
(4)
R =R.
YX

RS + R1 + R X

In case of on-chip planar inductors, the relationship between
RN and LN is approximated as ζ=LN/RN with ζ being atechnology parameter because both RN and LN are roughly
proportional to the square of turns. The optimum values of C2and RL_AC are calculated as functions of k, fTX, ζ, RS, R1, R2 byusing formulas (3) and (4). Fig.7 shows the calculatedtransmitted power and power efficiency η when fTX=900MHz,

850

24L1 (nH) 64810η(%) 757065826L2 (nH)64L1 (nH) 610 24 L2 (nH)8102(a)(b)Fig. 7. Calculated (a) received power and (b) efficiency dependence on L1and L2.

4.8

5.8

6.8
L2 (nH)

7.8

8.8

0
9.8

300

200
50100
Optimizedat 900MHz
0450

600

750

900
1050
fTX (MHz)

1200

Received power (mW)

Efficiency (%)

100
Optimal(Theory)

Received power (mW)

200
500
3.8

100

300

100

Efficiency (%)

A. Circuit Model
Although the feasibility of the wireless power delivery system
is demonstrated in the previous sections, it is preferable toincrease the transmittable power and to maximize the power
efficiency to further increase the variety of applications.
Improvement can be achieved by adding resonance capacitors
C1 and C2 as shown in the equivalent circuit model in Fig.6 (a).
RS represents parasitic resistances of transmitterinterconnections and driving transistors which equals to theinternal impedance of the transmitter. R1 and R2 indicate series
resistances of L1 and L2 respectively. Capacitances C1 and C2
resonate with L1 serially and with L2 in parallel respectively.
RL_AC relates to the equivalent total impedance of the rectifier,the smoothing capacitor and the DC load resistance RL_DC.
RL_AC was shown to be approximated as follows when therectifier is ideal and the smoothing capacitor is large enough[2].
R L _ DC
(1)
≈R

10PRY 100(mW)

01350(a)(b)
Fig. 8. Simulated results on received power and efficiency when (a) L2 and(b) fTX are varied.

k=0.75 and ζ=2.6×10-9 and RS=2 assuming 90-nm CMOS
technology with input voltage of 2.5V. In this design region,
the power efficiency improves as the value of L1 increases
although the transmitted power degrades. On the other hand,both the power efficiency and the transmitted power are
independent of the value of L2. To verify the optimization
theory, two types of simulations were performed. Fig.8 shows
the simulated results on received power and power efficiency
using HSPICE around the theoretically optimal values of L2and fTX. In both cases, the optimal values correspond well withthe simulated results.
IV. CONCLUSIONSIn summary, a chip-to-chip 5mW/mm2 wireless powertransmission system was demonstrated by 0.35-µm CMOS
technology. Maximization of the power efficiency is also
discussed.
ACKNOWLEDGMENT
This work is supported by VLSI Design and Education Center (VDEC), theUniversity of Tokyo in collaboration with Rohm Corporation, Toppan Printing
Corporation and Cadence Design Systems, Inc.

REFERENCES[1][2]

N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M.
Fukaishi, T. Sakurai, and T. Kuroda, IEEE JSSC, Vol.42, No.1,
pp.111-122, Jan. 2007.
G.A.Kendir, Liu Wentai, Wang Guoxing, M.Sivaprakasam,R.Bashirullah, M.S.Humayun, J.D.Weiland, IEEE Transactions onCircuits and Systems I Volume 52, Issue 5, May 2005.

A Design Methodology of Chip-to-ChipWireless Power Transmission SystemKohei Onizuka, Makoto Takamiya, andTakayasu Sakurai
University of Tokyo, Tokyo, Japan

Wireless power transmission over chips• Improvement in assembly flexibility & data link performance• Detachable structure for system upgrade by users
2Circuit implementation (pulse-based)
Lower chip

Upper chip

DRF+

D+
RL

Trans-mitter
RF-

CR

L1 L2
Differential
buffers
Ringoscillator
Transmitter

RF+

D+

D-RFRectifier unit
3

Fabricated chip & measurement setup
700μm
Upper chip
(Receiver)

Lower chip
(Transmitter)

xy

Whole setup

Lower chip
Upperchip

Upper boardz

Lower board

L2=9.3nH

L1=1.0nH

Close-up view
4

Measured results

Received power (mW)

350nm 1P3M CMOS for TX/RX, fTX=330MHz
3

RL varied

2

1
Measured
Simulated
00.7
Output voltage (V)1.4

Maximum transmitted power: 2.5mW (5mW/mm2)
when Vout=0.5V, RL=100, z=05

Alignment error tolerance
1.6

1.6

0.800280
560 Δx (µm)

280
Δy (µm)zyRXxTX

Output Voltage (V)Output voltage (V)Dependence on Δx,Δy

Dependence on Δz0.80800
400Δz (μm)

1200

• Measurement results when RL=∞
• Half value breadth
Δx,Δy < 200μm
Δz < 300μm[P5] K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, IEEE CICC, 2006.
6

Introducing resonance capacitors
RS C 1 R 1• For higher receivedpower, transmission
efficiency

Ejω

R2

L1k

L2 C2

RL_AC

C1,C2: Resonance capacitors
RS,R1,R2: Parasitic resistances of transmitter, L1 and L2
RL_AC: Equivalent load resistance including rectifier
Under resonance condition
RY• RX and RY: Functions of R2 and RL_AC
RS+R1• When power efficiency maximized:Ejω

RX

RY = RXRS + R1
RS + R1 + RX .

[P6] K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, IEEE ICICDT, 2007(Invited).
7

Optimization & verification
Theoretical
calculationwhenτL=2.6×10-9,
RS=2.0,VDD=2.5V,
fTX=900MHz,k =0.75.

Powereffic.

ReceivedpowermW
150
100
50
1%
8075
10 7065
1L2(nH)
L1(nH)

10L2(nH)
L1(nH)

10 1

10130020050
Optimal(Theory)

100003.8 4.8 5.8 6.8 7.8 8.8 9.8
L2 (nH)

100

Simulated 300
20050
Optimized 100
at 900MHz00450 600 750 900 1050 1200 1350
fTX (MHz)

Received power (mW)

Simulated

Efficiency (%)

Efficiency (%)

100

Received power (mW)

• L1 Î Power and efficiency balancing, L2 Î Voltage adjustment8

SummaryFirst-time wireless power transmission over chips
Received power 2.5mW/0.5mm2 measured
Optimal design methodologies on power & efficiency
derived
Received power up to 100mW-order/mm2 estimated9