11-6

IEEE Asian Solid-State Circuits Conference
November 8-10,2010 / Beijing, China

0.6V Voltage Doubler and Clocked Comparator for
Correlation-based Impulse Radio UWB Receiver in65nm CMOS
Lechang Liu, Takayasu Sakurai, and Makoto Takamiya
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japanllch@iis.u-tokyo.ac.jp
Abstract—This paper presents a 0.6-V voltage doubler and a 0.6V clocked comparator in 65nm CMOS. For the multi-phasesampling application, such as charge-domain correlator for
impulse UWB receivers or analog-to-digital converter, theproposed voltage doubler can reduce the power consumption
and the chip area by half compared to the conventional one. The
non-overlapping complementary clock generator used in theconventional voltage doubler can be eliminated by simply
swapping the input clock order in the voltage doubler. The
proposed 0.6-V clocked comparator can operate at 100-MHz
clock with the proposed voltage booster.

I.

INTRODUCTION

The market and the need to develop efficient electronicequipment have pushed the industry to design circuits withvery low power supply voltage, and also often constrained tolow power consumption. This work targets to develop a 0.6V
voltage doubler and a 0.6V clocked comparator for the multiphase sampling application, such as correlation-based ultrawideband (UWB) receiver or analog-to-digital converter(ADC).
As an application example, the proposed voltage doubler
and the clocked comparator are used for the impulse UWB
receiver. Impulse UWB refers to a radio technology fortransmitting information by means of extremely short duration
pulses without radio frequency modulation. Ideal targets forimpulse UWB system are low power, low cost, high data rates,and extremely low interference, which makes it an attractive
option for ad hoc and sensor network where groups of wirelessterminals are located in a limited area and communicate in an
infrastructure-free fashion without any central coordinating
unit or base-station.
Conventional impulse UWB transceivers usually require
1.2V supply voltage or above [1-3]. However, in the single
solar cell powered ad hoc and sensor network, the maximum
available supply voltage is less than 0.6V. Figure 1 shows theapplication of the proposed circuits in the impulse UWBreceiver. To verify the performance of the proposed 0.6V

978-1-4244-8298-6/10/$26.00 ®2010 IEEE

VDD=0.6V

100Mb/s
BPSK

VDD=1.2V

VHCorrelator

OUT

Vcor

Vin

Latch
VL

AMP

Discrete Template

Comparators

Voltage Doubler
ϕ0 ~ϕ7, ϕr

CLK(2GHz)

Clock Removal
for Sliding Scheme

20-Phase Sampling
Clock Generator

Figure 1. Block diagram of inpulse radio UWB receiver. 0.6-V voltage
doubler supplies boosted voltage to charge-domain correlator and comparator.

Addition

Subtraction

Vin
φ1C1φ2φr

C2φ3φrVDD=0.6VC3φ5C3φr
φr

φ5φ6C2φrφr

φ6φ7C1φrφrφrφr

φ7VcorFigure 2. Charge-domain sampling correlator.

voltage doubler and the 0.6V clocked comparator, the 1.2V
sampling clock generator and the synchronization control
circuits are also implemented in the same chip.
Section II presents the circuit implementations of thevoltage doubler. The 0.6V voltage comparator is described inSection III. Experimental results are presented in Section IVand Section V concludes the paper.
II.

VOLTAGE DOUBLER

Figure 2 shows the circuit schematic of the charge-domain
sampling correlator used in the UWB receiver [2]. The
sampling correlator circuits make use of two basic building

blocks, namely the capacitor and the switch. Lowering thesupply voltage of the correlator has implications on theoperation of some building blocks. The functional property ofa capacitor, namely its capacitance, is in fact independent of
the supply voltage. The most problematic issue in low voltage
sampling correlator design is the switch driving problem. One
effective way to cope with the low supply is to apply voltage
multiplication. This technique uses circuits which convert thevoltage from the available supply to another one. The
conversion factor is larger than unity and the up-converted
voltage is a multiple of the available supply voltage.
A. Conventional Voltage Doubler
Various circuits have been proposed and used in literature
to implement voltage multiplication. Originally monolithic
voltage multipliers stem from non-volatile memory circuits
where a relatively high potential is needed to write or erase
information [4]. A conventional voltage doubler from DRAM
applications is found in [5] and shown in Fig.3 (a). The key
feature of this voltage doubler is to use feedback technique toobtain a boosted voltage of 2VDD even at low operating
voltage. When one clock is high, the bootstrapped voltage ishigh enough to turn on the other NMOS, which charges theother capacitor to VDD. In the next phase the roles areexchanged. This feedback technique can eliminate a voltage
loss due to a threshold voltage of MOSFET.
The required clock signals used in the conventional
voltage doubler can be generated by the non-overlapping
complementary clock generator show in Fig.3 (b). This circuittakes a clock signal and generates a two-phase nonoverlapping clock. The amount of separation is set by thedelay through the NAND gate and the two inverters on theNAND gate output. When driving a large capacitance, wherethe rise time of the signals can be significant, a large numberof inverters are required as part of the delay which will
dominate the power consumption of the voltage doubler.

φ0VDD

ϕ0VDD

φ00
VDD
02VDD
VDD

ϕ0φ0

ϕ0

ϕ02VDD
VDD

φ0(a)

ϕin

ϕ0
ϕ0(b)

Figure 3. Conventional voltage doubler [5]. (a) Circuit schematic andwaveforms. (b) Non-overlapping complementary clock generator.

φ1φ4φ2φ5φ3φ60~0.6V: ϕ1ϕ4ϕ2ϕ5ϕ3ϕ60.6~1.2V:

CLK (2GHz)
ϕc Comparison
ϕ1ϕ2Addition
ϕ3ϕ4ϕ5
Subtraction
ϕ6Figure 4. Simplified circuit schematic of the proposed voltage doubler forthe sampling correlator.

B. Proposed Voltage Doubler
In the sampling correlator, the complementary clock
signals are not required. If the conventional voltage doublers
are directly used to generate the 20-phase sampling clocks forthe correlator in Fig.1, half of chip area and power dissipationof the voltage doublers will be wasted due to thecomplementary clock signals. To overcome this problem, theproposed voltage doubler for the multi-phase samplingcorrelator is shown in Fig.4. The non-overlapping requirementon the adjacent input signals can be satisfied by simply
swapping the clocks ϕ1, ϕ2, ϕ3, ϕ4, ϕ5, ϕ6 to ϕ1, ϕ4, ϕ2, ϕ5, ϕ3,
ϕ6, thus eliminating the non-overlapping complementary clock
generator.
III.

CLOCKED COMPARATOR

Comparators are used for synchronization control and data
decision in the proposed UWB receiver as shown in Fig. 1.
For 0.6-V supply voltage, it doesn’t suffice to force anexisting circuit to operate at 100-MHz clock. It requires thedevelopment of dedicated circuits.
A. Conventional Clocked Comparator
Fig. 5 shows the circuit schematic and the simulated
waveforms of the conventional clocked comparator [6] at 1.2V power supply voltage. The reset is done to the meta-stablestate and the regeneration is satisfied by two MOS inverters inpositive feedback configuration. When clock is low, the drainsof the two inverters (O1, O2) are charged to Vcor or Vref
(creating an imbalance). When clock goes high, the imbalancecauses the circuit latch high or low depending on the state ofthe inputs. The conventional clocked comparator operates with
100-MHz clock at 1.2-V power supply voltage, while it fails
to operate at 0.6-V power supply voltage.
B. Proposed Clocked Comparator
To make the conventional clocked comparator operate at
100MHz with 0.6V supply voltage, in the proposedcomparator, supply voltage is doubled from 0.6V to 1.2V
when clock goes high. Figure 6 shows the complete circuit
schematic of the proposed voltage doubler for both thesampling correlator and the clocked comparator where
φ1, φ2, ......, φ6 are used for the sampling clock of the correlator

and φcmp is used for the supply voltage of the comparator.
Figure 7 shows the circuit schematic and the simulated
waveforms of the proposed comparator. The proposed clocked
comparator operates with 100-MHz clock at 0.6-V power
supply voltage. When φclk is low, the circuit outputs are notvalid logic signals but rather, ideally, track the input signals.
This form of the latch has the advantage of lower power
dissipation because no current is flowing when the latch is inreset mode.

φclk
φcmp

φcmp
VO2VO1φcmp

Vcor

φclk

ϕcVref
Vout
φclk

φclk

(a)

VDD=1.2V
Vo1 Vo2
1VVout

O2

O1
Vcor

Vref

01V

Vo1 0.5V
01V

φclk

Vo2 0.5V0(a)

1V

φclk
1V

φcmp

Vo1 0.5V

01V
0.5V
001V

1V

Vref

Vcor 0.5V

Vo2 0.5V000102030406050

Time (ns)

1V

φclk

(b)
01V

Vcor 0.5V201030405060856μm

Figure 5. Conventional clocked comparator [6]. (a) Circuit schematic. (b)Waveforms.

856μm(b)Comp.
Clock Gen.
& Sync.

φcmp126μm

Voltage Doubler
For Correlator

Time (ns)

Voltage Doubler
For Correlator

106μm

0

Charge-Domain
Correlator

0Figure 7. Proposed clocked comparator. (a) Circuit schematic. (b)Waveforms.

Vref

Voltage Doubler
for Comparators

ϕcFigure 8. Chip micrograph and layout of UWB receiver.
φ1φ4ϕ1φ2ϕ4ϕ2φ5ϕ5φ3IV.

φ6ϕ3ϕ6Figure 6. Complete circuit schematic of the proposed voltage doubler forboth the sampling correlator and the clocked comparator.

MEASUREMENT RESULTS

The proposed UWB receiver without the front-end
amplifier was designed and fabricated in 1.2V 65nm CMOS
process. The chip micrograph and layout are shown in Fig. 8.
To verify the performance of the proposed 0.6V voltage
doubler and the 0.6V clocked comparator, the 1.2V level

Vin
VDC=0.6V,Vpp=40mV

CLK

Frequency: 2GHz

φ6Frequency: 95.2MHz

OUT

outputs of the clock generator are down-shifted to 0.6V for theinput in Fig. 1. Fig. 9 (a) shows the measured waveforms
before synchronization is achieved, where Vin is the incoming
UWB pulse, CLK is the 2GHz input clock, φ6 is the sixth
sampling clock and OUT is the output data. The same sliding
scheme-based synchronization mechanism as [1] is used.
Before synchronization is achieved, due to the clock-swallow
sliding scheme, for every incoming UWB pulse one input
clock is swallowed and the period of the sampling clock
generator output is increased to 10.5ns which corresponds tothe frequency 95.2MHz. Fig. 9 (b) shows the measured
waveforms when synchronization is achieved. Because thesliding scheme for timing alignment is inactivated, thefrequency of the sampling clock returns to 100MHz and theUWB receiver receives 100-Mbps data correctly.
The receiver performance is summarized in Table I.
Compared to the conventional 1.8V UWB receiver [2], thetotal power consumption is reduced by three times. The power
consumption of the correlator and the comparators is reduced
by 93% (from 0.75mW to 0.05mW) by reducing the power
supply voltage from 1.8V to 0.6V.

(a)

VinV.

VDC=0.6V,Vpp=40mV

CLK

Frequency: 2GHz

φ6Frequency: 100MHzOUTCONCLUSIONS

A 0.6-V voltage doubler and a 0.6-V clocked comparator
are presented in 65nm CMOS. Compared to the conventional
voltage doubler, the proposed doubler can reduce the required
capacitance area by half and eliminate the non-overlapping
complementary clock generator. The proposed 0.6-V clocked
comparator can operate at 100-MHz clock with the proposed
voltage booster. Compared to the conventional UWB receiver[2], the power consumption of the correlator and thecomparators is reduced by 93% by reducing the power supply
voltage from 1.8V to 0.6V.

(b)

ACKNOWLEDGMENT

Figure 9. Measurement results of UWB receiver. (a) Sliding scheme fortiming alignment. (b) Measured waveforms in synchronization.

This work was carried out as a part of Extremely Low
Power (ELP) project supported by the New Energy andIndustrial Technology Development Organization (NEDO).

TABLE I.

RECEIVER PERFORMANCE SUMMARY AND COMPARISONREFERENCES
[1]

[2]

This WorkCMOS Technology

180nm

65nm

Supply Voltage

1.8V

0.6V,1.2V

Data Rate

100Mb/s

100Mb/s

Clock FrequencyPower2GHz

2GHz

Correlator &Comparators

0.75mW@1.8V

0.05mW@0.6V

Clock Gen. &Sync Control

0.53mW@1.8V

0.34mW
@1.2V

Total

1.28mW

0.39mW

Energy per bit

12.8pJ/bit

3.9pJ/bit

Core Area

5561 μm2(w/o Volt.
Doubler)

13356 μm2
(with Volt.
Doubler)

[2]

[3]

[4]

[5]

[6]

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