ISSCC 2005 / SESSION 3 / BACKPLANE TRANSCEIVERS / 3.6

3.6

12Gb/s Duobinary Signaling with ×2
Oversampled Edge Equalization

Kouichi Yamaguchi1, Kazuhisa Sunaga1, Shunichi Kaeriyama1,Takaaki Nedachi1, Makoto Takamiya1, Kouichi Nose1,
Yoshihiro Nakagawa1, Mitsutoshi Sugawara2, Muneo Fukaishi1
1NEC, Sagamihara, JapanNEC, Santa Clara, CA2

In recent chip-to-chip and backplane data transfers on printed
circuit boards, data-rates are limited not by the operating speedsof the circuits in the transceiver LSIs, but by the bandwidth ofthe transmission media. Duobinary [1] is a type of partial
response signaling that can be helpful in reducing the required
bandwidth, because it allows for a controlled amount of ISI to beremoved afterward. Figure 3.6.1 shows the transfer function forduobinary signaling, as well as channel loss and the frequency
response of the combined channel and transmitter/receiver equalizers. In duobinary signaling, the resulting ISI may be expressedin the z-domain as 1+z-1. Transmitter/receiver equalization
results in binary input data (1, 0) being output as a duobinarydata (2, 1, 0).
Figure 3.6.1 also shows the transfer functions of PAM-2 andPAM-4 [2], as well as the respective eye-heights of duobinary,PAM-2, and PAM-4 signals (Eduobin, EPAM-2, and EPAM-4). Each ofthese signals is equalized along the same channel loss curve withrespect to a corresponding Nyquist frequency: fnyq (PAM-2), fnyq/2(PAM-4) and 2fnyq/3 (duobinary), where fnyq is half the symbol rateof PAM-2. The relationship between Nyquist frequency and eyeheight is calculated from theoretical transfer curves for each of
PAM-2/4 (cosine roll-off) and duobinary (1+z-1). The eye-height of
the PAM-4 signal is 7.4dB below the gain at fnyq/2 due to four-levelsignaling. In contrast, the eye-height of a duobinary signal withthree levels is only 1.6dB below the gain at 2fnyq/3. This is due tothe fact that a PAM-4 signal includes the maximum transition
between the lowest and the highest levels, however, the duobinary signal only includes the transitions between adjacent levels.
Thus, duobinary signaling has better immunity tocrosstalk/reflection than PAM-4 and that is proportional to themaximum transition.
At each Nyquist frequency, when the channel loss difference
between duobinary and PAM-2 is larger than 3.7dB, duobinary
eye-height will be larger than that of PAM-2. Similarly, when thedifference between duobinary and PAM-4 is less than 5.8dB,duobinary eye-height will be larger than that of PAM-4. However,when the difference is larger than 5.8dB, duobinary eye-opening
will be comparable to that of PAM-4; because a lower roll-off factor of the PAM-4 transfer function, caused by lower PAM-4 gain
at duobinary Nyquist frequency, results in horizontal eye closure.
Specifically, the duobinary eye-height is estimated to be 3dB larger than that of PAM-2/4 in 12Gb/s signaling over a 75cm trace ona low-ε PCB.
Figure 3.6.2 shows the proposed duobinary signaling system. The
resulting duobinary signal is sampled by four-way decision circuits; two for data decisions and the rest for clock recovery (CR).
In data decisions, duobinary signals are compared with reference
voltages at the symbol rate and the comparison results are decoded into binary data.
In adaptive equalization, error information based on a comparison of expected and actual amplitudes of equalized output isindispensable to the optimization of equalizer filter coefficients.
In PAM-2/4, this requires a dedicated reference voltage and anadditional comparator. Neither is required in duobinary signal-70

ing, because the sampled transition-edge value used by the CR toextract the input-signal timing information can also be utilized toprovide the required error information. Figure 3.6.3 shows that
although superposition of a duobinary single-bit responses having an optimum Nyquist interval of 1.5Tsymbol (where Tsymbol is thesymbol interval for PAM-2/duobinary) results in a zero value atthe sample point, a larger Nyquist interval has a non-zero value
at this point. This sample-point value can serve as the error
information needed to optimize the transmitter equalizer in an
iteration procedure based on the Sign-Sign-LMS algorithm.
Figure 3.6.4 shows the ×2 oversampled equalizer essential for theproposed duobinary signaling. The single-bit responses of duobinary signals have their peak values at the intermediate point
between symbol-rate sampling points. To achieve this kind of single-bit response, the waveform to be transmitted has to be filtered by means of oversampled equalization. The multi-phaseclock in the proposed system eliminates the need for doubling thesampling clock frequency of the filter, typically required by theoversampled equalization in an ordinary FIR filter. A test chip
containing a 12Gb/s 10-tap ×2 oversampled equalizer, uses a3GHz 8-phase clock. The equalizer itself consists of two 5-tap
equalizers with shorted outputs and is used to transmit combined
output through the channel. Each 5-tap equalizer uses a 4-phaseclock to multiplex one-fourth-rate parallel data from its tap controller. The clock phase difference between these equalizers is 45degrees, which corresponds to a half-width of one symbol.
Figure 3.6.5 shows CR in duobinary signaling. For high-speed
operations, the CR employs conventional ×2 oversampled
method, as is used in PAM-2. Unlike PAM-4, the duobinary signals have only one cross-point between symbols, which meansthat the circuitry required by PAM-4 to select sampled edges inorder to assure accurate CR is not needed here. In CR, phasedetection is performed by comparing the sampled value withrespect to the center threshold at timing φc with the value at φd.
However, when a 1-bit toggle data sequence is transmitted, aduobinary signal with small amplitude cannot be sampled correctly at φc. This means that CR may not work at all. This problem can be overcome by using a data encoder that ensures 2-bit
transition in the data sequence to be transmitted. Since 2-bit
transition eye-height at φc will be roughly the same as that of aduobinary signal at φd, correct sampling can be achieved. It isconfirmed that 2-bit-transition-ensured 8B10B-like coding can beachieved by adding 2 bits to the input data.
Figure 3.6.6 is a micrograph of a backplane transceiver employing duobinary signaling, fabricated in a 6M 90nm CMOS process.
It includes the circuit components inside the dashed box of Fig.
3.2.2. The transmitter consumes 133mW and the receiver consumes 97mW. Circuit areas are 0.18mm2 (transmitter) and0.055mm2 (receiver). Figure 3.2.7 shows measurement resultsthat are monitored through 75cm low-ε PCB trace. The eye-diagram at the top of Fig. 3.6.7 is for PAM-2 signaling; a 49mV ×35ps opening indicates horizontal ISI caused by steep roll-off. Theeye diagram at the bottom is for duobinary signaling and shows
a 73.5mV × 52ps opening, which is 2.2-times larger than that ofPAM-2.
References:[1] A. Lender, “The Duobinary Technique for High-Speed DataTransmission,” IEEE Trans. Commun. Electron., vol. 82, pp. 214-218, May,
1963.
[2] J. L. Zerbe et al., “Equalization and Clock Recovery for a 2.5-10Gb/s 2PAM/4-PAM Backplane Transceiver Cell”, IEEE J. Solid-State Circuits,
vol. 38, pp. 2121–2130, Dec., 2003.

• 2005 IEEE International Solid-State Circuits Conference

0-7803-8904-2/05/$20.00 ©2005 IEEE.

ISSCC 2005 / February 7, 2005 / Salon 7 / 4:15 PM
Channel loss

Gain

PAM-4 (cosine roll off)

ChannelTransmitter
equalizer

2fnyq/3

Frequency

fnyq+

Response to (0110)
i.e. sbit+sbit*z-1

Response to (0110)

5Tapcontroller

Sampled edge

Single bit
response

Single bitresponseSample
Timing

Data
input
44444

Mux
Mux
Mux
4:1
Mux

data
φaφa+90

Tsbit

Sampled edge
= Error Sig.
Equalizer
controller

Tapweights

φd5Tapcontroller

4Mux
4Mux
4Mux
4Mux
4:1
4Mux
4

From CDR To CDR

Figure 3.6.3: Edge equalization.

Even phase
outputOutbuf

φ0 φ90 φ180 φ270

Combined
outputChannel

Odd phase equalizer

SS-LMS
adaptation Logic

SS-LMS
adaptation logic

Channel4

Duobinary
signalφdDataout

4:1Mux

4>00Tsbit

φdEven phase equalizer

Sampled edge

Tsymbolφd φcFigure 3.6.2: Block diagram of duobinary signaling system.

(b) Optimum eq. (Tsbit = 1.5 Tsymbol)
Sampled edge = 0

Sampled edge > 0φcDuobinarysignal(2, 1, 0)

Figure 3.6.1: Transfer functions of duobinary, PAM-2, and PAM-4.

Not optimum eq. (Tsbit > 1.5 Tsymbol)

Vref

inbφd-φd φcEqualizer
controller

Receiverequalizer

Channelout+Vref0

Binarysignal(1, 0)

φdRxeqlz.

-Vreffnyq/2outbinDuobinary signal

Nyquist freq. of PAM-20(a)Outputbuf+2.1dB

Epam-4PAM-4Epam-2
PAM-2

PAM-2 (cosine roll off)

Transmitterw/ x2
oversampling
equalizer

On-Chip
sampling osillo.

1+z-1

CDR

Eduobin

PRBS gen.
w/ 1bit-transition
control

DecoderNyquist freq. of Duobinary

Data
in

50ome

-7.4dB

-1.6dB

Nyquist freq. of PAM-4

PrecoderDuobinary (1+z-1)

Tsymbol
Single bit responseof duobinary signal
Outbuf

φ45 φ135 φ225 φ315

Odd phase
outputFigure 3.6.4: x2 oversampled equalizer.

(b) 2bit transition(a) 1bit transition
1100
Outputdata sequence= 1010001010011

φdφc

Outputdata sequence

φdφc

Phase
interpolator

1+z-1

Up/Downcounter

Demuxn+2
Demux

2bittransitionensure
encoding

XOR

Clock recovery

TX
Data ninput

φdφc

For data recovery

Figure 3.6.5: Clock recovery in duobinary signaling.

Figure 3.6.6: Chip micrograph.

Continued on Page 585
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