IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 3, MARCH 2019613

An 11-nW CMOS Temperature-to-Digital Converter
Utilizing Sub-Threshold Current at Sub-Thermal
Drain Voltage
Teruki Someya , Member, IEEE, A. K. M. Mahfuzul Islam , Member, IEEE, Takayasu Sakurai, Fellow, IEEE,
and Makoto Takamiya, Senior Member, IEEE

Abstract— A fully integrated CMOS temperature-to-digitalconverter utilizing MOSFETs in the sub-threshold region is proposed. The temperature-to-digital converter achieves the ultralow power operation required for Internet of Things (IoT) nodes.
The proposed principle takes the ratio of the sub-thresholdcurrents of two nMOSFETs whose drain voltages are maintained
well above and well below the thermal voltage, respectively. The
proposed circuit implementation of the temperature-to-digitalconverter achieves ultra-low power consumption of 11 nW atroom temperature of 25 °C. Measurement results of the proposed
temperature sensor fabricated in a 180-nm CMOS process
show −0.9/+1.2 °C peak-to-peak inaccuracy over a temperature
range of −20 °C to 80 °C after a two-point calibration whileachieving a resolution of 145 mK.
Index Terms— Internet of Things (IoT), low power, subthermal drain voltage (STV), temperature sensor, temperatureto-digital converter.

I. I NTRODUCTIONC

MOS-COMPATIBLE smart temperature sensors that canbe integrated into a system-on-chip (SoC) have becomeof great value because of their low cost and ease of use.
Applications such as the thermal management of processors or SoCs [1]–[3], ambient temperature monitoring [4], andbiomedical devices [5]–[7] are some examples. Recently, withthe emergence of the Internet of Things (IoT), the need forsensors with as low-power consumption as possible to extend
the battery life has become a focus of research. The low power
operation is also required in an IoT node with a battery that has
a large internal resistance RBAT . The maximum instantaneous
current from a battery (IMAX ) is limited owing to the voltage
drop caused by the internal resistance RBAT . In the case of a

Manuscript received June 30, 2018; revised September 26, 2018,
December 12, 2018, and December 20, 2018; accepted December 20, 2018.
Date of publication January 29, 2019; date of current version February 21,
2019. This paper was approved by Guest Editor Nan Sun. (Corresponding
author: Teruki Someya.)
T. Someya was with the University of Tokyo, Tokyo 153-8505, Japan. He
is now with Tokyo Institute of Technology, Tokyo 152-8550, Japan (e-mail:someya@ssc.pe.titech.ac.jp).
A. K. M. M. Islam was with the Institute of Industrial Science, Universityof Tokyo, Tokyo 153-8505, Japan. He is now with the Department of Electrical Engineering, Graduate School of Engineering, Kyoto University, Kyoto
615-8510, Japan.
T. Sakurai and M. Takamiya are with the University of Tokyo, Tokyo
153-8505, Japan.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2019.2891718

miniature size IoT node with a solid-state bare die battery [8],IMAX is limited to only 1.7 μA after 1000 cycles owing to theincreased RBAT when the acceptable voltage drop is 100 mV.
Therefore, reducing the average current of a temperature
sensor to less than 1% of IMAX (= 17 nA) is desirable for
an IoT node with the battery [8]. Another desirable featureof the temperature sensor for IoT nodes is proportional-toabsolute-temperature (PTAT) output with a digital interface.
PTAT output is beneficial for realizing low-power, real-timethermal management because complicated off-chip processing
is not required.
This paper describes a fully integrated CMOS temperatureto-digital converter with power consumption of only 11 nW.
This paper is an extension of a previous conference paper [9].
The key extensions of this paper over [9] are: 1) a detailed
description of the operating principle; 2) a detailed analysisof the error sources; and 3) new chip design and fabrication
including digital interface circuits.
The key techniques in our proposed temperature-to-digitalconverter are as follows: 1) a new temperature-sensing principle that utilizes a sub-threshold current at a sub-thermal drain
voltage (STV) and 2) a circuit implementation of the proposed
principle in a 180-nm CMOS process which enables thetemperature sensor to achieve ultra-low power consumptionof 11 nW at 25 °C. The measured resolution is 145 mK, andthe measured inaccuracy is −0.9/+1.2 °C for nine samples ina temperature range of −20 °C to 80 °C.
The remainder of this paper is organized as follows.
Section II reviews the state-of-the-art of temperature sensors.
Section III introduces the operation principle of the proposed temperature-sensing mechanism. Section IV proposes
an ultra-low-power circuit implementation of the proposed
temperature-to-digital converter. Section V demonstrates somemeasurement results of our temperature-to-digital converter.
Section VI concludes this paper.
II. S TATE - OF - THE -A RT T EMPERATURE S ENSORS
An on-chip temperature-to-digital converter that consistsof a temperature sensor, its bias circuitry, and an ADC, allintegrated into the same die, is often called a smart temperature
sensor. For temperature sensing in a CMOS process, the deviceof choice is a parasitic bipolar junction transistor (BJT),
which can be realized using the same diffusions as those used

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for MOSFETs. A BJT-based temperature sensor is generally
self-referenced because a self-generated bandgap voltage isused to digitize the base-to-emitter voltage (VBE ) difference
between two BJTs biased by different collector currents. The
voltage difference, VBE , is PTAT thus providing an onchip digital representation of temperature with the use ofan ADC. These sensors are also called bandgap temperature
sensors and provide accuracy of less than ±0.1 °C under thetemperature range of −55 °C to 125 °C with one-point calibration [10], [11]. One disadvantage of bandgap temperature sensors is that they require high-accuracy ADC circuits to achieve
an accurate temperature sensing, which increases their power
consumption [12].
To realize a sub-1-V temperature sensor, the replacement of
BJTs with diode-connected MOSFETs was proposed in [13].
With the help of a zoom ADC, temperature inaccuracy of±0.4 °C was achieved after one-point calibration with a power
consumption of approximately 600 nW (excluding the digitalbackend). Temperature-sensing mechanisms using the logic
gate delay of CMOS have also been proposed, facilitating
ease-of-design [14]. Such sensors require calibration with
two or three points and also require a nonlinear master curve.
Thus, the generation of an on-chip digital output requires
further processing that consumes power.
MOSFET sub-threshold current can also be used as areplacement of BJTs to achieve temperature sensing. Subthreshold MOSFET-based temperature sensors enable a low
voltage and low power consumption. Although they sufferfrom lower accuracy and typically require a two-point calibration, they are expected to be beneficial for many practicalapplications where the need for high accuracy and resolution
can be relaxed. Recently, a new class of temperature sensors
utilizing MOSFET sub-threshold current has been proposed. A
current-to-frequency converter (CFC)-based temperature sensor, where the frequency of an oscillator becomes exponential
to the absolute temperature, was proposed in [12]. To obtaina PTAT digital value, the logarithm operation is required.
Furthermore, nonlinear fitting is used to achieve an accuracyof −0.76/+0.76 °C. In [15], a 113-pW temperature-to-digitalconverter with a temperature range of only −20 °C to 40 °C,
which is too limited for many applications, was proposed.
Although a 120-nW temperature sensor was also proposed in[16], the covered temperature range was only −10 °C–30 °C,
and the topology requires an external reference clock, which
increases the additional power consumed by its generation.
To realize an inherent on-chip PTAT quantity, in [17], a linear approximation of the exponential function, exp(x), wasutilized by choosing the x carefully. The required x was
realized by taking the ratio of the sub-threshold currents of
two MOSFETs biased at different VGS values. The linearityof the sensor was dependent on the optimum value, which mayvary because of mismatch.
In this paper, we take a similar approach to that used in [17]but use a different physical phenomenon to obtain the PTAT
quantity. We keep the VGS value the same but apply different
VDS values to the two MOSFETs. By setting the VDS for one
MOSFET much larger than the thermal voltage VT and setting
VDS for the other MOSFET below VT , the corresponding

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 3, MARCH 2019

Fig. 1.

Flowchart of the proposed temperature-to-digital converter.

Fig. 2.

Mechanism of the conventional temperature sensing [17].

current ratio provides better linearity and sensitivity than thoseobtained by the mechanism proposed in [17].
III. P ROPOSED T EMPERATURE -S ENSING M ECHANISM
Fig. 1 shows a flowchart of the proposed temperature-todigital converter. The process of conversion from the temperature to a PTAT digital output has three steps: 1) generation of
two sub-threshold currents obtained from a pair of nMOSFETs
with different drain voltages (I1 , I2 ); 2) current-to-frequency
conversion ( f 1 , f 2 ); and 3) frequency ratio ( f 2 / f 1 ) calculation
for the PTAT digital output (DPTAT ). The key point here is thatthe current ratio I2 /I1 shows a PTAT characteristic in the target
temperature range of −20 °C to 80 °C. The details of theprinciple of achieving a PTAT I2 /I1 are described in the next.
A. Temperature Sensing Mechanism
A PTAT I2 /I1 is required to realize the proposed
temperature-to-digital converter shown in Fig. 1. Fig. 2 shows
the temperature-sensing principle of a conventional work [17]that achieves a PTAT I2 /I1 by approximating an exponentialfunction by a linear function. In [17], two identical nMOSFETs in the sub-threshold region with different gate voltagesof VGS1 and VGS2 were implemented to achieve a PTAT I2 /I1 .
The current ratio of I2 to I1 is expressed as


VGS
I2
= exp
(1)
I1
nVT
where VGS = VGS2 − VGS1 , VT (= kT /q) is the thermal
voltage, k is Boltzmann’s constant, q is the electron charge, T
is the absolute temperature, and n is the sub-threshold swing

SOMEYA et al.: 11-nW CMOS TEMPERATURE-TO-DIGITAL CONVERTER

615

Fig. 4.

Sensitivity of I2 /I1 .

becomes a function of VDS1 and T as follows:
I2
1
.

=
I1
1 − exp −VDS1

(4)

VT

Assuming that VDS1 is sufficiently smaller than VT , I2 /I1 isapproximated as
I2
VT
=
+C
I1
VDS1

Fig. 3.
Proposed temperature-sensing mechanism. (a) VDS biasing of
MOSFETs. (b) Theoretical and measured I2 /I1 for a single transistor.

parameter. In (1), I2 /I1 has an optimum VGS that maximizes
the linearity of I2 /I1 in a temperature range. For a typical nof 1.4, the optimum VGS is −72 mV in the temperature rangeof −20 °C to 80 °C. The sensitivity of I2 /I1 is calculated tobe 0.0009/°C when VGS is −72 mV.
Fig. 3(a) shows the operating principle of our proposed
temperature-sensing mechanism. Two identical nMOSFETs
MA1 and MB1 operating in the sub-threshold region are biased
with different VDS values. An STV less than the thermal
voltage VT (= 26 mV at 27 °C) is applied to VDS1 , while
above thermal drain voltage (ATV) more than 3 VT is applied
to VDS2 . As a result, drain currents of MA1 and MB1 areexpressed as follows [18]:
 



−VDS1
VGS1 − VTH· 1 − exp(2)
I1 = K · exp
nVT
VT


VGS1 − VTH
I2 = K · exp(3)nVT
where K is a technology-related parameter and VTH is thethreshold voltage of the transistors. The current ratio I2 /I1(5)

where C is a temperature-independent constant. Equation (5)shows that the sensitivity of I2 /I1 to T can be improvedby reducing VDS1 . I2 /I1 in (4) with VDS1 of 8 mV isplotted in Fig. 3(b) along with the measured I2 /I1 in thetemperature range of −20 °C to 80 °C using a single
nMOSFET implemented in a 180-nm CMOS process. The
theoretical slope (= sensitivity) of I2 /I1 obtained from (5) is0.0107/°C, whereas the measured slope of I2 /I1 is 0.0108/°C.
The measured and theoretical slopes agree within an errorof 1%. Fig. 4 shows the theoretical sensitivity of I2 /I1
obtained from (5). The proposed principle has over ten times
higher sensitivity than that in [17] when VGS in (1) is
set to −72 mV and VDS1 in (5) is set to 8 mV. Fig. 5(a)shows the adjusted R2 for (4) versus VDS1 in the temperature
range of −20 °C to 80 °C with the adjusted R2 in (1)obtained when VGS = −72 mV. Theoretically, the proposed
temperature sensing mechanism shows higher linearity when
VDS1 < 12 mV. Fig. 5(b) shows the peak-to-peak inaccuracyof I2 /I1 in the temperature range of −20 °C to 80 °C. Twopoint calibration is performed by reading I2 /I1 at 0 °C and
60 °C. The proposed temperature sensing mechanism enables
both higher sensitivity and better linearity than those in [17].
B. Mismatch Effect
The matching of MA1 and MB1 is important in the proposed
temperature sensing principle. A mismatch between MA1
and MB1 may affect the linearity of I2 /I1 . Considering themismatch between MA1 and MB1 , (4) is modified to


I2
−VTH
1


= exp
I1
nVT
1 − exp −VVDS1
T= K 0 (T )1
1 − exp −VVDS1
T

(6)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 3, MARCH 2019

Fig. 7.
Overall block diagram of the proposed temperature-to-digitalconverter.

where AVT is the slope in Pelgrom plot [19]. Using a typical
AVT of 3.3 mV·μm for a 180-nm CMOS process [20],we set W and L for the transistors as 8.0 and 1.5 μm,
respectively, which give σVTH of 0.95 mV. Thus, according
to Fig. 6, an additional peak-to-peak error of 0.3 °C may occur
considering the 3σVTH value of the VTH mismatch.
Fig. 5. (a) Adjusted R2 of I2 /I1 . (b) Inaccuracy of the temperature-sensing
calculated from I2 /I1 .

Fig. 6. Effect of the transistor mismatch on the accuracy of the temperaturesensing.

where VTH = VTH2 − VTH1 . When VTH  nV T , K 0 (T ) is
approximated as 1 and I2 /I1 shows the PTAT characteristicsin (5). Conversely, when VTH is not sufficiently smaller
than nVT , the accuracy of I2 /I1 is affected by the mismatch. Fig. 6 shows the VTH dependence of the inaccuracyof I2 /I1 after a two-point calibration obtained from (6) in thetemperature range of −20 °C to 80 °C. n of 1.4 obtained
from a SPICE simulation was used for the analysis. The errorof 0.07 °C at VTH = 0 is the inherent inaccuracy of I2 /I1
when VDS1 is set to 8 mV as shown in Fig. 5(b). These results
show that the mismatch of the transistor pair may reduce theaccuracy of I2 /I1 .
VTH for a pair of MOSFETs is described by the standard
deviation
AVT
σVTH = √(7)
WL

IV. D ESIGN OF T EMPERATURE - TO -D IGITAL C ONVERTER
Fig. 7 shows a block diagram of the proposed temperatureto-digital converter. The current generators generate currents
I1 and I2 obtained from nMOSFETs with different drain
voltages. Two clock signals, CLK1 and CLK2, are generatedusing CFCs based on relaxation oscillators. The corresponding
frequencies f 1 and f 2 are linear to the currents I1 and I2 ,respectively. As a result, f 2 / f 1 shows the same PTAT characteristic as I2 /I1 . The counter-based scheme in [21] is used
to readout the PTAT digital output. CLK1 and CLK2 are fed
to two asynchronous binary counters that enable the on-chip
digital conversion of f 2 / f 1 (= I2 /I1 ) without any external
clock references. CLK2 edge is counted until CLK1 edge has
been counted up to a predefined number N. When CLK1 has
been counted to N, the value of Counter 2 (= DPTAT ) is
latched and converted to a 16-bit serial output (S_DATA).
In our design, N can be programed in the range of 10–13 bits.
The programmability of N enables the programing of theresolution of the temperature-to-digital converter. The resolution has a tradeoff relationship with the conversion time, i.e.,m times finer resolution requires m times larger conversion
time. Designers or users should select the highest resolution
while meeting the required conversion time in the usage.
In our temperature-to-digital converter, a voltage reference isimplemented to supply a constant voltage VREF for the analog
components. The voltage reference makes the temperature-todigital converter free from external references. In our design,
a two-transistor-based on-chip voltage reference presented
in [22] is used.
A. Current Generators
In the proposed principle shown in Fig. 3(a), a circuit
implementation that regulates VDS1 to an STV and VDS2 toan ATV is required. In particular, a temperature-independent

SOMEYA et al.: 11-nW CMOS TEMPERATURE-TO-DIGITAL CONVERTER

617

Fig. 8. Circuit schematic of the current generators using STV and ATV
MOSFETs.

VDS1 is indispensable for MA1 . The temperature dependence
of VDS1 decreases the linearity of I2 /I1 . Moreover, the offset
voltage in VDS1 may decrease the sensitivity of I2 /I1 . We cancalculate the effect of the offset voltage on the sensitivity of
I2 /I1 from (5). For example, when the target VDS1 is 8 mV,
offsetting VDS1 by ±5% (= 0.4 mV) increases/decreases thesensitivity of I2 /I1 by ±5%. Therefore, we propose a circuit
implementation to realize the accurate VDS1 while maintaining
the low power operation.
Fig. 8 shows a circuit schematic of the proposed current
generators including the VDS1 bias circuitry. A reference
voltage (VREF ) supplied by the VREF generator shown in
Fig. 7 is equally divided by a 50-stage diode chain, where thevoltage drop across each diode is V (= VREF /50 ≈ 8 mV).
The operation principle of the current generator for I2 isbased on the voltage subtraction mechanism proposed in [22].
We assume that MB1 and MB2 are identical nMOSFETs withdrain voltages of over 3 VT . The gate-to-source voltagesof these transistors must be the same since the currentsof MB1 and MB2 are identical, which forces VDS2 to be
VA − VB . In Fig. 8, VDS2 is 128 mV because VA and VB
are 248 and 120 mV, respectively. Thus, MB1 acts as the ATV
MOSFET shown in Fig. 3(a). Realizing a drain–source bias
voltage to be below the thermal voltage is challenging as the
STV MOSFET MA1 must operate in the deep triode region.
When the stack number k is 1, VDS1 does not converge toV and has a temperature-dependent offset voltage (VOS ).
However, with increasing k, VDS1 gradually converges toV . Fig. 9(a) and (b) shows the simulated temperature characteristics and temperature coefficient (TC) for VDS1 againstk, respectively. VOS for VDS1 is over 10 mV with a TC
of 47 μV/°C when k = 1. The offset and TC decrease theFig. 9. (a) Temperature characteristics of VDS1 . (b) TC of VDS1 with variousk.

sensitivity and accuracy of I2 /I1 . We solve the problem byincreasing the stack number k to obtain a VDS1 value of V
and reduce the temperature dependence of VDS1 . Although VOS
occurs in the source node of MAK+1 owing to the differencein the operating regions between MAK+1 and MAK , the effectof VOS on VDS1 is mitigated by the stacked nMOSFETs (M2to MAk ) and VDS1 converges to V . The simulation results asshown in Fig. 9(a) and (b) confirm that VDS1 approaches Vwith increasing k, and the TC is also reduced consequently.
However, increasing k results in a larger area. Thus, the VDS1
accuracy and the circuit area are in a tradeoff relationship. The
current of the voltage divider ID must be sufficiently lower
than the output current limit of the voltage reference. In ourdesign, ID is set to less than 10 pA in room temperature.
The simulated currents of I1 and I2 at room temperatureare 80 pA and 260 pA, respectively. The total current of thecurrent generators is 350 pA.
To estimate an appropriate value of k, the effect of thetemperature dependence of VDS1 on the inaccuracy of I2 /I1
is considered. As shown in Fig. 9(a), the temperature characteristic of VDS1 in the proposed current generator shows amonotonic increase for each value of k. Assuming that VDS1
has a temperature coefficient of α ppm/°C and expressed as
VDS1 =

VREF(1 + α(T − TR ) × 10−6 )
M

(8)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 3, MARCH 2019

Fig. 10. Dependence of the inaccuracy of the temperature sensing on thetemperature coefficient of VDS1 when the target VDS1 = 8 mV.

Fig. 11. Process corner analysis of the inaccuracy of the temperature sensing.

where M is the number of diodes in the voltage divider,
VREF /M (= V ) is the target VDS1 , and TR is a reference
temperature, I2 /I1 is given as
I2
1

.
=
1+α(T −T R )×10−6
I1
1 − exp −V

(9)

VT

Fig. 10 shows the peak-to-peak temperature errors using I2 /I1
in (9) after two-point calibration when TR = −20 °C, and thetarget temperature range is −20 °C to 80 °C. As shown in
Fig. 10, an increase in the temperature dependence of VDS1
increases the error. In our design, k = 16 is selected, resulting
in α = 2.2 μV/°C and, in theory, to a 0.6 °C inaccuracy
in I2 /I1 when V = 8 mV. Fig. 11 shows the simulated
inaccuracy of I2 /I1 for our designed current generators fordifferent process corners. The worst simulated peak-to-peakinaccuracy is 0.84 °C in the process corners. The obtained
simulated results relatively differ from the theoretical error
obtained from (9) at high temperatures. One possible reason
is that the theoretical error shown in (9) is introduced under
the condition that the TC of VDS1 is first order. If we can
include higher order factors, the model will be improved
to match the actual characteristics. The accuracy of I2 /I1
can be further improved by increasing k at the cost of theFig. 12. (a) Concept of the CFC. (b) Schematic of the delay cell. (c) Timing
diagram of the delay cell.

increased area. Thus, the proposed technique achieves a constant VDS1 and VDS2 with a small current overhead of 350 pA.
B. Current-to-Frequency Converter
In Fig. 7, the oscillation frequency of CLK1 (CLK2) mustbe highly linear to I1 (I2 ). The proposed CFCs are based ona relaxation oscillator as shown in Fig. 12(a). The oscillation
period of CFC1 is expressed as
C VREF2+ tC,FALL + tC,RISE(10)
TOSC,1 = NCELL
I1
where NCELL (= 3 in our design) is the number of delay cells
in CFC1, and tC,FALL and tC,RISE are the propagation delays ofthe proposed delay cell in the CFCs. VREF2 is a fixed voltage
for the comparators in the delay cells obtained from the diodechain in Fig. 8. The oscillation period of CFC2 (= TOSC,2 ) is
also obtained from (10) by exchanging I1 with I2 . tC,FALL andtC,RISE should be sufficiently small compared with CVREF2 /I1
so that TOSC,1 becomes proportional to CVREF2 /I1 . In this case,f 2 / f1 (= TOSC,1 /TOSC,2 ) gives the same PTAT characteristics
as I2 /I1 . In the delay cell shown in Fig. 12(b), the first stage isa differential amplifier with a pMOSFET current mirror load
acting as a comparator. The negative input is biased at VREF2(<VTH ). In the second stage, a common-source amplifier
with a large load resistor is implemented to reduce tC,RISE .

SOMEYA et al.: 11-nW CMOS TEMPERATURE-TO-DIGITAL CONVERTER

Fig. 13.

619

Chip photograph of the proposed temperature-to-digital converter.

The load resistor is implemented with an OFF transistor.
To achieve sub-1-nW static power consumption in the delay
cell, the resistor (R) should be large (e.g., 5 G). However,the large R increases tC,FALL owing to the limited current IR .
To reduce tC,FALL , we utilize a split-output scheme [23] that
decouples the comparator stage from the pull-down path.
A feed-forward path composed of SW1 and SW2 is addedin the second stage in Fig. 12(b). When IN changes from low
to high, the propagation through the first stage and the second
stage in the comparator is bypassed and OUT is pulled down
by SW2, which leads to the reduction of tC,FALL . In thesimulation, tC,RISE and tC,FALL are reduced to less than 2%
and 0.1% of CVREF /I1 , respectively, in the temperature rangeof −20 °C to 80 °C at VDD = 0.8 V.
The frequencies of the CFCs are set to over 1 kHz to makethe conversion within 1 s at room temperature when N = 10
bits in Fig. 6. The frequencies of CFCs are temperaturedependent that makes the conversion time of the temperature
sensor temperature-dependent. In our measurement, f 1 ranged
from 100 Hz to 10 kHz in the temperature range of −20 °C
to 80 °C. If the temperature sensor is used in the wide
temperature range especially in lower than 0 °C, designers
must consider that the temperature sensor meets the demandfor conversion time. The conversion time can be improved at
the cost of the power consumption or resolution by reducing
N in Fig. 7.

Fig. 14. (a) Frequencies of the CFCs. (b) Inaccuracy of the temperature
sensors calculated from f 2 / f 1 [9].

C. Voltage Reference
In the temperature sensor, a voltage reference is required toachieve the current generators shown in Fig. 8. In this paper,
two-transistor-based voltage reference presented in [22] isapplied to the current generators which operate with nW power
consumption. On the other hand, a standard voltage VREF
supplied by two-transistor voltage reference has temperaturedependence due to the mismatch [24]. We assume that VREF
with a temperature coefficient β ppm/°C is given by
VREF = VREF,R + βVREF,R (T − TR ) × 10−6

(11)where VREF,R is VREF when T is a reference temperature TR .
By substituting (11) into (8), VDS1 is expressed as
VDS1 ≈

VREF,R(1 + (α + β)(T − TR ) × 10−6 ).
M(12)Fig. 15.
verter.

Measured waveforms of the proposed temperature-to-digital con-

The peak-to-peak temperature inaccuracy obtained from I2 /I1 ,under the condition that VREF has a TC of β, TR = −20 °C,
and VREF,R /M = 8 mV, can then be estimated from Fig. 10 byreplacing α with α + β. Overall, temperature affects VDS1 in
two ways. The first effect comes from the VREF itself. The
second effect comes from the current generators as shownin Fig. 9. Thus, the TC variability of VDS1 is a statistical sumof TCs of V and the current generator as shown in (12). The
reported absolute TC of a two-transistor voltage reference [24]without trimming is ranged from 17 to 231 ppm/°C. In theworst case, i.e., when VREF has a TC of 231 ppm/°C, thepeak-to-peak inaccuracy of I2 /I1 is 1.2 °C in our simulation.

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Fig. 16.
nine dies.

Fig. 17.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 3, MARCH 2019

Measured (a) DPTAT and (b) temperature inaccuracy among

Measured temperature inaccuracy of 100 reading.

Post-fabrication one-temperature point trimming is an effective
method of reducing the TC of VREF [24]. In [24], the 2T
voltage reference utilizing the trimming method reduces theworst TC of VREF to less than 47 ppm/°C, which reduces thesimulated peak-to-peak inaccuracy of the proposed temperature sensing to less than 0.9 °C. By implementing trimming forthe voltage reference, the accuracy of the temperature sensor
can be improved.
V. M EASUREMENT R ESULTS
The proposed temperature-to-digital converter including a
voltage reference [22] and digital backend is fabricated in a
180-nm CMOS process.

Fig. 18.

Power consumption of the temperature-to-digital converter.

Fig. 19.

VDD dependence of the temperature inaccuracy.

Fig. 13 shows a chip photograph of our temperature-todigital converter. The total area of the temperature-to-digitalconverter including the digital backend is 0.074 mm2 . In [9],to measure the inaccuracy of the temperature sensor, f 1 and f2
were measured with an oscilloscope as shown in Fig. 14(a),and the inaccuracy was estimated by taking f 2 / f1 as shownin Fig. 14(b). In this paper, the digital serialized DPTAT(= S_DATA in Fig. 7) is read for the samples to measure the accuracy and resolution of the temperature sensor.
Fig. 15 shows the waveforms of CLK1, CLK2, S_CLK, and
S_DATA shown in Fig. 7 at 0.8 V and 25 °C. Fig. 16(a)shows the obtained DPTAT of nine samples in the temperature
range of −20 °C to 80 °C, while Fig. 16(b) shows theinaccuracy of the temperature-to-digital converters. After a
two-point calibration, the peak-to-peak inaccuracy of the ninesamples in this paper is −0.9/+1.2 °C. The counter-resolution,
which is the LSB associated with the 10-bit conversion of thetemperature-to-digital converter, among the measured samples
is 94 mK. Owing to the thermal noise, the sampled countervalue DPTAT varies in each measurement. To evaluate thesensory resolution, DPTAT is measured 100 times at a fixed
temperature (25 °C in this paper) [25]. Fig. 17 shows the
100 samples of the temperature inaccuracy. The standard
deviation of the samples is 1.54 LSB, which corresponds to anoise-limited resolution of 145 mK. Fig. 18 shows the power
consumption of the entire circuit and each component in thetemperature-to-digital converter. The power consumption of
the entire circuit is 10.6 nW at room temperature (25 °C).

SOMEYA et al.: 11-nW CMOS TEMPERATURE-TO-DIGITAL CONVERTER

621

TABLE IC OMPARISON W ITH P REVIOUSLY P UBLISHED MOSFET-BASED L OW-P OWER T EMPERATURE S ENSORSThe current generators and CFCs consume 6.9 nW, VREF
generator and digital backend consume 1.9 and 1.8 nW,
respectively. The power consumption of the voltage reference
is increased from that of [9] so that it is less affected by
the switching noise from the digital circuits. Even when thetemperature increases to 80 °C, the power consumption of
the entire circuit is 100 nW. Fig. 19 shows the measured
VDD dependence of temperature inaccuracy for five samples
at 25 °C. The inaccuracy over a VDD range from 0.7–1.5 V
is −1.5/+1.6 °C which results in a VDD sensitivity of 3.8 °C/V.
In Table I, the performance of the proposed temperatureto-digital converter and the previous MOSFET-based lowpower temperature sensors are summarized and compared. The
proposed temperature-to-digital converter has the lowest power
consumption of 11 nW at 25 °C in Table I, while achieving acompetitive inaccuracy of −0.9/+1.2 °C among nine samples
and a resolution of 145 mK.
VI. C ONCLUSION
In this paper, an 11-nW ultra-low power temperature-todigital converter is proposed. A new principle of the temperature sensing based on the sub-threshold operation at
STV contributes to realizing a linear PTAT digital output
while achieving a competitive resolution. A circuit implementation of the current generators and CFCs realizes the
proposed sensing principle under the ultra-low power operation. The circuit implementation of the temperature-to-digitalconverter achieves the lowest power consumption of 11 nWamong the temperature sensors that covers the temperature
range of −20 °C to 80 °C. Measurement results of the test

chips fabricated in a 180-nm CMOS process show that thetemperature-to-digital converter realizes −0.9/+1.2 °C inaccuracy over a temperature range of −20 °C to 80 °C with aresolution of 145 mK.
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Teruki Someya (S’16–M’18) received the B.S.,
M.S., and Ph.D. degrees in electrical and electronicengineering from the University of Tokyo, Tokyo,
Japan, in 2013, 2015, and 2018, respectively.
He is currently a Researcher with Tokyo Instituteof Technology, Tokyo. His research interests include
energy efficient ultra-low power circuits for Internetof Things (IoT) applications.

A. K. M. Mahfuzul Islam (S’11–M’14) received
the B.E. degree in electrical and electronics engineering, the M.E. degree in communications andcomputer engineering, and the Ph.D. degree in
informatics from Kyoto University, Kyoto, Japan,
in 2009, 2011, and 2014, respectively.
From 2013 to 2015, he was a Research Fellow ofJapan Society for the Promotion of Science. In 2015,
he joined the Institute of Industrial Science, University of Tokyo, Tokyo, Japan, as a Research Associate. Since 2018, he has been a Junior Associate
Professor with the Department of Electrical Engineering, Kyoto University.
His research interests include characterization and modeling of transistor
noise, low-power CMOS sensor circuits, and low-power design methodology.
Dr. Islam was a recipient of the Best Paper Award at ICMTS’2017 and theStudent Design Award at A-SSCC’2013.
Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan,
in 1981.
In 1981, he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and system-on-chip (SoC) solutions. He
has worked extensively on interconnect delay andcapacitance modeling known as Sakurai model andalpha power-law MOS model. From 1988 to 1990,
he was a Visiting Researcher with the Universityof California at Berkeley, Berkeley, CA, USA, where he conducted research
in VLSI CAD. Since 1996, he has been a Professor with the Universityof Tokyo, working on low-power high-speed VLSI, memory design,interconnects, ubiquitous electronics, organic IC’s, and large-area electronics.
He has authored or co-authored over 600 technical publications including
100 invited presentations and several books and filed over 200 patents.
Dr. Sakurai is an IEICE Fellow. He was a recipient of the 2010 IEEE
Donald O. Pederson Award in Solid-State Circuits, the 2009 and 2010 IEEE
Paul Rappaport Award, the 2010 IEICE Electronics Society Award,
the 2009 IEICE Achievement Award, the 2005 IEEE ICICDT Award,
the 2004 IEEE Takuo Sugano Award, and the 2005 P&I patent of the year
award and four product awards. He is the Executive Committee Chair of
VLSI Symposia and a Steering Committee Chair of the IEEE A-SSCC. He
served as the Conference Chair of the Symp. on VLSI Circuits and ICICDT,the Vice Chair of ASPDAC, the TPC Chair of the A-SSCC and VLSI Symp.,
an Executive Committee Member of ISLPED, and a Program Committee
Member of ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, andother international conferences. He delivered keynote speech at more than
50 conferences including ISSCC, ESSCIRC, and ISLPED. He was an Elected
AdCom Member of the IEEE Solid-State Circuits Society and an IEEE CAS
and SSCS Distinguished Lecturer. He is also a domain research Supervisor
for nano-electronics area in Japan Science and Technology Agency.

Makoto Takamiya (S’98–M’00–SM’14) received
the B.S., M.S., and Ph.D. degrees in electronicengineering from the University of Tokyo, Tokyo,
Japan, in 1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high-speed
digital LSI’s. In 2005, he joined the University ofTokyo, where he is currently an Associate Professor
of VLSI Design and Education Center. From 2013 to2014, he was a Visiting Scholar with the Universityof California at Berkeley, Berkeley, CA, USA. His
research interests include the integrated power management circuits for wireless powering and energy harvesting for Internet of Things (IoT) applications,and the digital gate driver IC for power electronics.
Dr. Takamiya is a Technical Program Committee Member of the IEEE
International Solid-State Circuits Conference. He was a recipient of the2009 and 2010 IEEE Paul Rappaport Awards and the Best Paper Awardin 2013 IEEE Wireless Power Transfer Conference. He formerly served on
the Technical Program Committees of IEEE Symposium on VLSI Circuits
from 2009 to 2017 and IEEE Custom Integrated Circuits Conference from2006 to 2011.