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PAPER

Special Section on Analog Circuits and Related SoC Integration Technologies

A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse RadioUWB Transceiver in 90 nm CMOS
Lechang LIU†a) , Yoshio MIYAMOTO†† , Zhiwei ZHOU†† , Kosuke SAKAIDA†† , Jisun RYU†† , Nonmembers,
Koichi ISHIDA†† , Makoto TAKAMIYA† , and Takayasu SAKURAI†† , Members

SUMMARY
A novel DC-to-960 MHz impulse radio ultra-wideband(IR-UWB) transceiver based on threshold detection technique is developed. It features a digital pulse-shaping transmitter, a DC power-free pulse
discriminator and an error-recovery phase-frequency detector. The developed transceiver in 90 nm CMOS achieves the lowest energy consumptionof 2.2 pJ/bit transmitter and 1.9 pJ/bit receiver at 100 Mbps in the UWBtransceivers.
key words: impulse radio ultra-wideband (IR-UWB), digital pulseshaping, pulse discriminator, error-recovery phase-frequency detector

1.

Introduction

UWB communication systems can be broadly classified as
impulse radio UWB (IR-UWB) and multi-carrier UWB.
For IR-UWB, multi-user detectors (MUD) and hybrid
RAKE/MUD-UWB transceivers for robust narrowband interference suppression are becoming popular [1]. However,a simple, single clocked-correlator transceiver or thresholddetector can also be used for short distance and high SNR
environments [2], [3].
In this paper a novel DC-960 MHz impulse radio UWB(IR-UWB) transceiver is proposed for the low power adhoc wireless sensor networks [4], [5]. These ubiquitous networks require that the individual nodes are tiny, easily integratable into the environment, and have negligible cost. The
proposed transceiver features a digital pulse-shaping transmitter, a DC power-free pulse discriminator and an errorrecovery phase-frequency detector (PFD), thereby achieving
extremely low power consumption at 100 Mbps.
2.

Digital Pulse-Shaping Transmitter

Gaussian first derivative or second derivative pulse is often
used as IR-UWB pulse signals. In this work, a novel digital pulse-shaping technique is proposed to generate BPSK
modulated Gaussian first derivative pulse. The first-orderderivative Gaussian impulse can be expressed as
 2 
t
t
(1)
G1 (t) = −A exp − 2σ2σManuscript received October 16, 2008.
Manuscript revised December 27, 2008.
†
The authors are with VLSI Design and Education Center, theUniversity of Tokyo, Tokyo, 113-0032 Japan.
††
The authors are with Institute of Industrial Science, the University of Tokyo, Tokyo, 153-8505 Japan.
a) E-mail: llch@iis.u-tokyo.ac.jp
DOI: 10.1587/transele.E92.C.769

Fig. 1 (a) Conventional UWB pulse generator. (b) Modulated transmit
spectrum.

where A is the pulse amplitude, t is time, and σ is time constant.
Digital pulse shaping in UWB transmitters (TX’s) is a
power eﬃcient technique [6]. All the previously reported
digital pulse-shaping TX’s, however, were developed forabove-3 GHz band and no TX for DC-960 MHz band has
been reported [7]–[10]. Figure 1(a) shows the simplified
topology of the conventional digital pulse-shaping TX. It
consists of a triangular pulse generator and an output stage
driving 50 Ω load. The input signal and the inverted input
generate the upper and the lower pulses respectively.
The simulated transmit spectrum of the conventional
UWB pulse generator is shown in Fig. 1(b). The spectrum can not satisfy the FCC EIRP spectrum mask above
1-GHz frequency. To suppress the spectrum above 1-GHz
frequency, sequentially operated eight drivers are proposed
to shape one pulse. As shown in Fig. 2, the upper and thelower pulses are divided to eight parts respectively and every
part is shaped by diﬀerent drivers. For example, the first partof the upper pulse is only shaped by the driver 0 while thesecond part is shaped by the driver 0 and driver 1 simulta-

c 2009 The Institute of Electronics, Information and Communication Engineers
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Fig. 2 (a) Proposed UWB pulse generator. (b) Digital pulse-shaping
waveforms.

Fig. 4 (a) Waveform comparison between conventional and proposed
TX. (b) Modulated transmit spectrum of the proposed TX.

shaper and lower shaper respectively.
Figure 4(a) shows the waveform comparison between
the conventional TX in Fig. 1(a) and the proposed TX in
Fig. 3(a). Simulated transmit spectrum is shown in Fig. 4(b).
The developed digital pulse-shaping transmitter with eight
drivers can satisfy the FCC mask. With the increased
number of the pulse-shaping drivers, the transmit spectrum
above 1-GHz frequency can be further suppressed but thepower consumption will be increased. Compared to theeight-driver pulse shaper, the four-driver pulse shaper can’tsatisfy the FCC mask and therefore in this work eight drivers
are used to shape the pulse.
3.

Fig. 3 (a) Overall view of the proposed digital pulse-shaping transmitter.
(b) Timing chart.

neously. Figure 3(a) shows the overall view of the proposed
digital transmitter. It consists of two pulse shapers for data
“1” and data “0” respectively and each shaper is composedof eight drivers. The timing of the drivers is determined by
the 32-tap delay line. The timing chart of the whole transmitter is shown in Fig. 3(b). The transmitted data serves as
the selection signal for the input clock. For the transmitted data “1” and “0,” the input clock can pass to the upper

Receiver with DC Power-Free Pulse Discriminator

An ultra low-power solution for BPSK demodulation isleading edge detection (LED) technique. The LED receiver(RX) is also known as threshold detection-based receiver[2]. The threshold receiver consists of a circuit fast enoughto detect the presence of the IR-UWB pulse, and some typeof pulse stretcher circuit that outputs a pulse which is longenough for slower logic or analog circuits to process. Figure 5 is the basic block diagram of threshold detection-based
receiver. The receiver sets a threshold at the receiver, andany incoming pulse that crosses the threshold is detected anddemodulated.
The proposed asynchronous threshold detection-based
receiver is shown in Fig. 6(a). It consists of four blocks: afront-end amplifier, a DC power-free pulse discriminator, anerror-recovery phase-frequency detector (PFD) and a ResetSet Flip-Flop (RSFF). Figure 6(b) shows the timing chart ofthe proposed receiver. The received signal is first amplified
by the front-end amplifier and each BPSK symbol is split

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Fig. 5Block diagram of threshold detection-based UWB receiver.

Fig. 7 DC power free pulse discriminator. (a) Operation principle. (b)Simulated waveforms.

Fig. 6 (a) Circuit schematics of proposed threshold detection-based
receiver. (b) Timing chart.

into two pulses V0 and V1 by the DC power-free pulse discriminator. Then the first incoming edge of the two pulses
is detected by the PFD and the RSFF converts the detection
result to the corresponding data bit.
3.1 DC Power-Free Pulse Discriminator
Conventionally, an amplifier and a comparator are combined
as a threshold detector. The major disadvantage of this
topology is large DC power dissipation that occurs even for
no AC input. In the transmitted BPSK signal, the circuit
spends long periods of time with no AC signal. Power dissipated in these periods is wasted. In this study, a novel DC
power-free pulse discriminator is proposed to discriminate
the received signal.
The proposed pulse discriminator is based on the conventional CMOS inverter. As shown in Fig. 7(a), two inverters InvH and InvL are employed to detect the positive
pulse and negative pulse respectively. The source of the inverter InvH is biased to VL (=ΔV) while the drain of theinverter InvL is biased to VH (=VDD − ΔV). The gate inputsof the two inverters are both biased to VDD /2. The logicalthresholds of the two inverters are labeled as VT H,InvH and
VT H,InvH respectively. When the amplitude of the received
signal is larger than VT H,InvH or less than VT H,InvL , the pulse
is detected and the power is only consumed on this period.
The simulated waveforms of the received signal and power
supply current of the two inverters are shown in Fig. 7(b).
The proposed DC power free pulse discriminator consumes
essentially zero power dissipation for no AC input.
3.2 Error-Recovery Phase-Frequency Detector
The received signal can be demodulated by detecting thefirst incoming edge of the two pulses V0 and V1 . Figure 8 (a)shows the conventional PFD implementation to detect thefirst incoming edge of the discriminator output. It consistsof two edge-triggered D flip-flops with D input tied to logical ONE. The output of the pulse discriminator, V0 and V1 ,serves as the clocks of the flip-flops. As shown in Fig. 8(b),if the PFD output UP and DN are low and V0 goes high, thesignal UP rises. If this is followed by a rising transition on
V1 , the signal DN will go high and the AND gate will reset
both flip-flops. In other words, to generate the reset signal
RST, UP and DN are simultaneously high for a short time
which should be avoided as the input signal for the following RSFF. To eliminate the simultaneous high output, twodelay cells with delay time t0 , placed on the XOR gate inputs, are used to compensate the time delay of the AND gate
[11].
The conventional PFD employs sequential logic to create three-status and respond to the rising edges of the two

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Fig. 9 Proposed error-recovery phase-frequency detector. (a) Circuit
schematics. (b) Error-recovery operation (RXout is shown in Fig. 6).

Fig. 8 Conventional PFD. (a) Circuit schematics. (b) Normal operation(RXout is shown in Fig. 6). (c) Error propagation due to distorted signal.

inputs. The output of sequential circuits depends not only
on the current inputs, but also on the previous values. The
bit error in the previous cycle will be carried over to the subsequent cycles. Figure 8(c) shows the bit error propagation
due to distorted signal. At the third data bit, the AND gateof the PFD is failed to generate the reset signal because V1 ismissed by the pulse discriminator due to the distorted signal“1.” The reset signal RST generated by the following risingedge of V1 in the next period changes the time sequence of
the PFD and causes bit error.
To avoid the bit-error propagation due to the distorted

received signal, an auxiliary reset signal RST , as shown in
Fig. 9(a), is fed back to the PFD input to force the reset operation in every period. The error-recovery circuits consistof a delay cell, an edge detector and two OR gates. The
auxiliary reset signal RST is generated by combing the delayed rising edges of the output UP and DN. In this design,
since the pulse width is 4 ns and the pulse period is 10 ns,
the delay time of the delay cell should be larger than 4 ns
and less than 10 ns. Figure 9(b) shows the simulated waveforms for the distorted data “10100.” Compared to Fig. 8(c),two rest signals are employed to reset the flip-flops for thenormal data bit in every period. For the distorted data bit“1,” the primary reset signal RST is missed by the pulse discriminator but the auxiliary reset signal RST resets the PFD
output to zero and blocks the potential bit-error propagation.
However, if V0 is missed by the pulse discriminator due tothe distorted signal, the PFD output UP will keep low and it
cannot set the output of the following RS-latch to high level.
In this case, one bit error will occur but the potential bit error propagation can still be blocked by the auxiliary reset
signal.

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4.

Experimental Results

The proposed digital pulse-shaping transmitter and the DC
power-free receiver without front-end amplifier were de-Fig. 10 Chip micrographs and layout. (a) Transmitter. (b) Receiver
without front-end amplifier.

Fig. 11 Measured transmitter output at 100 Mbps. (a) Waveform. (b)Spectrum.

signed and fabricated in 90 nm CMOS process. Figure 10
shows the micrograph and the layout of the transceiver. The
core area of the transmitter and the receiver are 9075 μm2
and 576 μm2 respectively.
Figure 11(a) shows the measured waveform of thetransmitter. The measured pulse amplitude is 115 mV andthe pulse period is 10 ns. The measured BPSK modulatedtransmit spectrum is shown in Fig. 11(b). It can be seenthat the proposed digital pulse-shaping transmitter can suppress the spectrum above 1 GHz and satisfy the FCC EIRP
spectrum mask. Figure 12 shows the measured waveformof the receiver. To verify the error-recovery PFD, the fifth
bit of the input data is distorted intentionally. As indicatedin Fig. 9(b), the potential error propagation due to distorted
signal “1” is blocked by the auxiliary error-recovery reset

Fig. 12

Measured receiver waveforms for distorted data “10100.”

Fig. 13 Measured receiver characteristics. (a) BER vs. Amp. (b) Power
vs. data rate.

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Table 1

Performance summary.

Figure 14 shows energy and power comparison with stateof-the-art UWB transceivers. The proposed digital pulseshaping transmitter and the DC power-free receiver achieves
the lowest energy consumption of 2.2 J/bit and 1.9 pJ/bit respectively at 100 Mb/s, and potentially a promising technology for low-complexity wireless communications.
5.

Conclusions

A novel DC-to-960 MHz impulse radio UWB (IR-UWB)
transceiver with digital pulse-shaping transmitter, DC
power-free pulse discriminator and error-recovery phasefrequency detector is proposed for ad-hoc wireless sensor
networks. The digital pulse-shaping transmitter shapes one
pulse with eight sequentially operated drivers to suppress
the spectrum above 1 GHz. The proposed pulse discriminator has essentially zero power dissipation for no AC
input and the error-recovery phase-frequency detector canblock the error propagation due to distorted received signal. Therefore, the transceiver in 90 nm CMOS achieves thelowest energy consumption of 2.2 J/bit TX and 1.9 pJ/bit RX(without front-end amplifier) in the state-of-the-art UWBtransceivers at 100 Mbps, and potentially a promising technology for low-complexity wireless communications.
Acknowledgments
This work is partially supported by CREST/JST. The VLSI
chips were fabricated through the chip fabrication programof VDEC with the collaboration by STARC.
References

Fig. 14 Comparison with the state-of-the-art UWB transceivers. (a)Transmitter. (b) Receiver.

signal. The measured BER at diﬀerent threshold of pulse
discriminator are shown in Fig. 13(a). Figure 13(b) shows
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threshold of pulse discriminator. The tradeoﬀ relationshipbetween the receiver sensitivity and the power consumption
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Lechang Liu
received the B.S. degreefrom Shandong University, China in 2000, theM.S. degree from Harbin Institute of Technology, China in 2002, and the Ph.D. degree inelectronic engineering from Shanghai Jiao Tong
University, China in 2006. In 2007, he joined
the University of Tokyo, Japan, where he is a
postdoctoral researcher of VLSI Design and Education Center. His research interests include
signal processing and mixed-signal circuit design for low-power wireless communications.

Yoshio Miyamoto
received the B.S. and
M.S. degrees in electronic engineering from the
University of Tokyo, Japan, in 2006 and 2008,
respectively. His research interests include thecircuit design of the low-power RF transmittercircuits. He is now with Kansai Electric Power
Co., Inc.

Zhiwei Zhou
received the M.S. degree inelectronic engineering from the University ofTokyo, Japan in 2008. His research interests include the circuit design of the low-power RF receiver circuits. He is now with Sony Corporation.

Kosuke Sakaida
received the B.S. degree inelectronic engineering from Kyoto University,
Japan in 2007. He is currently working toward
the M.S. degree in electronic engineering of the
University of Tokyo. His research interests include the circuit design of the low-power clocking circuits.

Jisun Ryu
received the B.S. degree
in electronic engineering from the University
of Electro-Communications, Tokyo, Japan, in
2006. He is currently working toward the M.S.
degree in electronic engineering of the University of Tokyo. His research interests include thecircuit design of the high-speed RF circuits.

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Koichi Ishidareceived the B.S. degree
in electronics engineering from the University
of Electro-Communications, Tokyo, Japan, in
1998, and received the M.S. and Ph.D. degrees
in electronics engineering from the Universityof Tokyo, Tokyo, Japan, in 2002 and 2005, respectively. He is currently working at Instituteof Industrial Science, the University of Tokyo as
a research associate. His research interests include low-voltage low-power CMOS analog circuit and RF wireless-communication circuit.

Makoto Takamiya
received the B.S., M.S.,
and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995,
1997, and 2000, respectively. In 2000, he joined
NEC Corporation, Japan, where he was engaged
in the circuit design of high speed digital LSIs.
In 2005, he joined University of Tokyo, Japan,
where he is an associate professor of VLSI Design and Education Center. His research interests include the circuit design of the low-power
RF circuits, the ultra low-voltage digital circuits,
and the large area electronics with organic transistors. He is a member of
the technical program committee for IEEE Symposium on VLSI Circuits
and IEEE Custom Integrated Circuits Conference (CICC).

Takayasu Sakurai
received the Ph.D.
degree in electrical engineering from the University of Tokyo, Japan, in 1981. In 1981,
he joined Toshiba Corporation, where he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has worked
extensively on interconnect delay and capacitance modeling known as Sakurai model and alpha power-law MOS model. From 1988 through1990, he was a visiting researcher at the University of California, Berkeley, where he conducted
research in the field of VLSICAD. Since 1996, he has been a Professor at
the University of Tokyo, working on low-power high-speed VLSI, memory
design, interconnects, ubiquitous electronics, organic IC’s and large-area
electronics. Dr. Sakurai has published more than 350 technical publications including 70 invited publications and several books and filed morethan 100 patents. He served as a conference chair for the Symposium on
VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chair for
the first A-SSCC, and VLSI symp. and a program committee member for
ISSCC, CICC, DAC, ESSCIRC, ICCAD, FPGA workshop, ISLPED, TAU,
and other international conferences. He is a plenary speaker for the 2003
ISSCC. He is a recipient of 2005 IEEE ICICDT Award, 2005 IEEE ISSCC
Takuo Sugano Award and 2005 P&I Patent of the Year Award. He is anIEEE Fellow, a STARC Fellow, an elected AdCom member for the IEEE
Solid-State Circuits Society, and an IEEE CAS distinguished lecturer.