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PAPER

Special Section on Low-Power, High-Speed LSIs and Related Technologies

An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint
on Future Scaled Transistors
Koichi ISHIDA†∗a) , Member, Atit TAMTRAKARN†∗∗ , Hiroki ISHIKURO†† , Makoto TAKAMIYA††† ,and Takayasu SAKURAI† , Nonmembers

SUMMARY
An opamp design with outside-rail output relaxing a lowvoltage constraint on future scaled transistors is presented. The proposed
opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-µm standard CMOS process. The 3-V-output
operation is experimentally verified. The outside-rail output design withscaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The
chip area is estimated to be 47% of the conventional opamp using a 0.35µm CMOS and about an order of magnitude smaller compared with theconventional inside-rail 0.18-µm CMOS design due to reduced capacitor
area. The proposed design could be extended to n-tuple VDD operation
and applied to circuits with a feed back loop such as gain stage and filters.
The extendibility of n-tuple VDD operation and its application are discussedwith simulation results.
key words: outside-rail, opamp, scaling

1.

Introduction

Signal-to-noise ratio (SNR) is a key performance factor for
analog circuits. Since the SNR is proportional to the signal
swing, scaled CMOS technology, which tolerates only low
voltage, tends to give negative impact to the SNR. In particular, the scaled CMOS technology would considerablyincrease both circuit area and power consumption of analog circuits in order to keep SNR and gain bandwidth (BW)constant. Thus scaling has not been pursued extensively inanalog designs.
On the other hand, for the forthcoming ubiquitous electronics applications, realizing smaller electronic systems is
becoming important, and combining digital and analog on achip is a promising solution. Therefore, analog circuit implementation using the advanced digital process whose supply voltage is sub-1 V is getting essential. The area and costof analog circuits, however, have dominated the total chiparea and cost of system-on-a-chip (SoC) in recent CMOS
technology [1].
If analog circuits can be operated with a signal swing
Manuscript received August 15, 2006.
Manuscript revised November 7, 2006.
†
The authors are with Center for Collaborative Research, The
University of Tokyo, Tokyo, 153-8505 Japan.
††
The author is with Department of Electronics and ElectricalEngineering, Keio University, Yokohama-shi, 223-8522 Japan.
†††
The author is with VLSI Design and Education Center, The
University of Tokyo, Tokyo, 113-0032 Japan.
∗
Presently, with Integrated Research Institute, Tokyo Instituteof Technology.
∗∗
Presently, with Sony Corporation.
a) E-mail: ishida@lsi.pi.titech.ac.jp
DOI: 10.1093/ietele/e90–c.4.786

higher than the standard VDD , that is, if outside-rail design
is possible, the scaled CMOS technology is beneficial evento analog circuits. In this context, several outside-rail designs have been published recently [2]–[5]. An open-drain
I/O buﬀer based on double-cascode structure [2], [3] and apush-pull buﬀer were presented [4]. They are, however, designed as digital output buﬀers. For analog circuits, an RF
power amplifier based on double-cascode structure [5] wasdiscussed but it is limited to non-push-pull output amplifier
without diﬀerential input stages which is not directly applicable to widely used opamp design.
Although an opamp is a mainstream analog component, outside-rail opamp designs have not been published.
There was a report on a high-voltage opamp [6] but does
not realize outside-rail output swing. Thus it is not eﬀective
for improving the SNR.
In this context, we proposed a high-voltage tolerant
opamp with outside-rail output swing in order to relax thelow-voltage constraint of future scaled transistors [7]. In
this paper, Sect. 2 briefly reviews issues on the conventional
analog scaling and introduces the concept of the outsiderail design with another analog scaling. Section 3 presents
details of the proposed outside-rail output opamp. Section 4 demonstrates experimental results from the test chipthat manufactured in a 0.18-µm standard CMOS process,and discusses comparison with conventional opamps, extendibility to n-tuple VDD operation, and its application. Finally, the conclusions are given in Sect. 5.
2.

Analog Scaling and Outside-Rail Concept

2.1 Conventional Analog Scaling
This section briefly reviews area and power issues on theconventional analog scaling. At first, some preconditions of
this work are mentioned. The drain current ID of the scaled
short-channel transistors is given by (1) with the alphapower law [8].
ID =W
PC (VGS − VT H )α ,L

(1)where PC is process dependent parameter and the alpha isalso a process dependent parameter ranging from 1 to 2 andnot simply scaled. VGS -VT H is typically around 0.2 V andhard to be scaled. Therefore, both the alpha and VGS -VT H
can be assumed to constants for the area estimation basedc 2007 The Institute of Electronics, Information and Communication Engineers
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Fig. 2The concept of the outside-rail amplifiers with scaled devices.

π(k2C)G BW (VGS − VT H )
k
V 
DD
=
(4)
(k2 IBias ) = kP,kwhere G BW is gain bandwidth. Thus the process scaling has
not been pursued extensively in the conventional analog designs so far.
P =Fig. 1 Scaling on metal-insulator-metal capacitor with parallelinterconnection configuration.

on gate oxide thickness tOX , W, and L since whose result
is almost equal to the result by the square law. Thus, thearea comparison is made using the square law in this work.
Another precondition is the scalability of an on-chip capacitor. If the metal thickness, line space, and line width are
scaled with the factor k and permittivity is constant, an onchip metal-insulator-metal capacitor such as a comb capacitor can be realized with 1/k of the area of the un-scaled caseas shown in Fig. 1.
For digital circuits, the process scaling brings benefits
such as lower power, shorter delay, and smaller area [9]. On
the contrary, power, delay, and area in analog circuits are determined by SNR and BW. Assuming that the signal bandwidth equals to circuit bandwidth, the SNR of the analog
circuit is expressed as
S NR =v2O,=
kB T/C
v2N
v2S

(2)

where v2S is the signal power proportional to the square of
the output voltage swing, v2N is the thermal noise power, v2O
is the output voltage swing, which has a close relation to the
supply voltage, kB is the Boltzmann’s constant, T is the absolute temperature, and C is the load capacitor of the circuit[10]. Thus, the load capacitance is expressed as
C=

kB T
.
v2N

(3)

When the supply voltage VDD is lowered by the processscaling with factor k, the signal dynamic range is limited toapproximately 1/k of the un-scaled signal dynamic range.
In order to keep the SNR constant, kB T /C noise should be
suppressed and consequently the load capacitor of the scaled
circuit must be k2 times the load capacitor of the un-scaled
circuit. The area of the load capacitor scaled by k, therefore,
would be k times the area un-scaled although an area of an
on-chip capacitor could be shrunk by the process scaling aspreviously mentioned. In addition, the power consumptionof the scaled circuit, P , is k times the power of the un-scaled
circuit, P, in order to charge the larger load capacitor, k2C,in the same BW as expressed as

VDD

2.2 Concept of Out-Side Rail Design and Another Analog
Scaling
If analog circuits could be operated with larger output swing
exceeding the standard VDD , in other words, if an outsiderail design is possible, the process scaling is beneficial evento analog circuits. Figure 2 shows the concept of an outsiderail design. VDD is a typical supply voltage for an unscaled device. The conventional inside-rail design can handle the signal whose dynamic range is up to VDD . On theother hand, the outside-rail design consists of scaled devices. Each scaled MOSFET tolerates only VDD /k due to thegate oxide reliability. The signal dynamic range, however,achieves VDD that is equal to un-scaled inside-rail design
since the voltage stress is relaxed by the staking structure.
In other words, the outside-rail design can almost double
the output voltage. Since the signal dynamic range is kept
constant, the same load capacitance is required in order torealize the same SNR. Therefore the area of capacitors in
the outside-rail design is given byAC = AC /k(∵ C  = C),(5)where Ac is the area of capacitors in the scaled outside-rail
design and Ac is the area of the un-scaled inside-rail design.
Similarly, the total area of MOSFET’s is given by(W/k2 )PC (VGS − VT H )LAM = (W/k2 )L = A M /k2
A M  total = kAM = A M /k,gm = gm /k2 =(6)where gm and gm are mutual conductance of the outsiderail design and the inside-rail design respectively and AM
and A M are the area of the MOSFET used in the outside-rail
design and the inside-rail design respectively.
Both the area of capacitors and area of MOSFETs in
the outside-rail design can be reduced while keeping power
consumption, SNR, and BW constant. That is, the scaled
CMOS technology is beneficial even to analog circuits withthe outside-rail design. Table 1 summarizes the analog scaling by both the conventional un-scaled inside-rail design andthe proposed outside-rail design.

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Table 1 Summary of the analog scaling with the conventional inside-rail
design and the outside-rail design.

Fig. 33.

A schematic of proposed opamp with outside-rail output swing.

Circuit Design

In order to realize outside-rail output design, the voltage
over-stress on gate oxide is to be overcome. On the other
hand, junction breakdown problem is not that severe since
the breakdown voltage of the drain-substrate junction is typically 3–4 times higher than that of the gate oxide [2].
A schematic of the proposed outside-rail output opamp
is depicted in Fig. 3. The first stage of this opamp should
accept twice the standard VDD as a power supply. M2 , M5 ,and M6 are added to solve the gate over-stress problem on
M1 , M3 -M4 , and M7 -M8 . Since the output swing of the firststage is limited by the additional transistors, a level shifterand an output buﬀer are added. The level shifter driving
class AB push-pull output buﬀer consists of stacked current sources, M9 and M12 , and resistors R1 -R2 . In order
to avoid over-stress problem, M10 -M11 are added and R1 -R2
are made of n-well. The double-cascode structure based on[2] is adopted for the push-pull analog output buﬀer to realize outside-rail output swing. The top pmos transistor M13
and the bottom nmos transistor M22 operate in the saturation region, and the remaining stacked transistors M14 -M15
and M20 -M21 , dynamically switched by M16 -M18 , operate
as resistors in the linear region. The drivability of the output
buﬀer is, therefore, dominated by output load capacitanceand mutual conductance of M13 and M22 .
In order to show that the circuit solves over-stress problem, SPICE simulation is carried out using 0.18-µm 1.8-V
standard CMOS process assuming 3.6-V input and 3.6-V
power supply. Figure 4 shows the schematic of an inverting amplifier using the double VDD opamp and the resultof transient analysis. VGS -VGD trajectories extracted fromthe transient analysis including the initial settling states areplotted in Fig. 5. As is seen form the figure, all VGS -VGD
trajectories are within −1.8 V to 1.8 V and this verifies thateach transistor is free from over-stress voltage across gate
oxide even in transients with the output swing of the circuit
being twice the standard VDD .

(a)

(b)
Fig. 4 (a) A schematic of an inverting amplifier using the outside-rail
opamp. (b) SPICE simulation result of transient analysis.

(a)

(b)

Fig. 5 Simulated VGS-VGD trajectories whose output swing is twice thestandard VDD. (a) Input stage and level shifter. (b) Output buﬀer.

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4.

Measurement Results and Discussions

4.1 Measurement Results
A test chip is designed and fabricated using 1.8-V 0.18µm standard CMOS process without thick-oxide transistors.
The microphotograph of the test chip is shown in Fig. 6, andthe chip area is 100 µm × 160 µm. Measured open loop frequency response is plotted in Fig. 7. In this design whichaims at audio applications, the measured open loop gainis 45 dB and the gain bandwidth is 13 MHz with the phasemargin of 60 degrees at 20-pF load capacitance. The open
loop gain is slightly low due to stability and power requirement. The open loop gain, however, could be achieved toaround 60 dB with this topology by either increasing gain
bandwidth of output stage or inserting additional resistor in
the phase-compensation loop. The area of the opamp will be
still smaller than that of un-scaled opamp design, although
the total area of the opamp may be increased by a few tens
percent because of either the additional resister or widened
MOSs in order to improve the open loop gain.
A schematic of an inverting amplifier using proposed

opamp and the measured large-signal waveform are shownin Fig. 8. The chip works successfully with 3-V outsiderail sinusoidal wave, with 0.9% total harmonic distortion.
Although the stack structure tends to increase distortion, areasonable performance can be realized with the outside-rail
design.
4.2 Area Comparison
An area comparison is made with conventional design
choices as shown in Fig. 9. The proposed outside-rail design is smaller than un-scaled 0.35-µm and scaled 0.18-µm
CMOS designs with the conventional two-stage opamp configuration keeping the SNR constant. Table 2 summarizes
an area and power comparison among design choices. The
values are measured for the proposed outside-rail design andestimated for other design options using SPICE.
The outside-rail design can almost double the output
voltage compared with the scaled inside-rail design, andconsequently the requirement of noise floor can be relaxed
up to double the vS . Therefore the load capacitance can be(a)Fig. 6 A chip microphotograph of the proposed opamp implemented by
a 0.18-µm 1.8-V standard CMOS process.

(b)
Fig. 8 (a) A schematic of an inverting amplifier using proposed opamp.
Gain is −1. (b) Measured large signal inverting output. Input signal is 1.5kHz sinusoidal wave with amplitude of 3 VPP. An outside-rail output swing
is achieved.

Fig. 7 Measured open loop frequency response. The gain bandwidth is
13 MHz with the phase margin of 60 degrees.

Fig. 9 Chip areas comparison with other design choices. The
conventional cases are designed but not manufactured.

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Table 2 Comparison between proposed opamp (0.18-µm) andconventional opamp(0.35-µm, 0.18-µm).

Fig. 10

reduced to a quarter. This decreased capacitance reduces required gm of transistors and the compensation capacitor in
the condition that a GBW is kept constant. The reduced gm
and the compensation capacitor are beneficial to reduce botharea and power compared with the inside-rail design.
On the other hand, compared with the un-scaled insiderail design, the outside-rail design needs the same gm of the
input transistor in order to achieve the same SNR and GBW,
since gm is proportional to SNR × GBW. The area of the input pair can be reduced to 1/4 because gm of each transistor
is proportional to (1/tOX ) × (W/L) where W, L and tOX are
scaled as W × 2 × (1/2), L × 1/2, and tOX × 1/2 respectively
to achieve the same gm . The same eﬀective gm of the output stage is required to achieve the suﬃcient stability. Thiscan be implemented by using double stacked structure of
W × 1/2, L × 1/2, and tOX × 1/2 transistors. Thus, area of theoutput stage is reduced by almost 2. Considering that mostof the circuit area is based on stacked structures including
the telescopic configuration of input stage, the total area canbe reduced to 1/2. Since the VT H variation is generally proportional to tOX and inversely proportional to square root of
W × L, the VT H variation is not an issue for the outside-rail
design. Since the current of the circuit is also proportional to(1/tOX ) × (W/L) of the input transistor pair, the total currentof the circuit is almost the same as in the un-scaled design.
An area of an opamp includes a MOS area and a capacitor area. The ratio of the MOS area to the capacitor area
is varied by several factors such as process rules and circuit preciseness. The outside-rail opamp design, however,can reduce both the MOS area and the capacitor area, and iseﬀectual in various applications.
4.3 Extendibility of n-Tuple VDD Outside-Rail Opamp
The proposed opamp can be extended to an opamp withthe output swing of n times the standard VDD as shownin Fig. 10. The additional stacked transistors in the output
buﬀer behave as resistors in the phase compensation loop
from the viewpoint of the stability. The drain-source resistance of the additional transistors must be suﬃciently low
to meet the application-specified stability. When the drain-

Extendibility of n-tuple VDD opamp with outside-rail output.

(a)

(b)
Fig. 11 (a) A schematic of an inverting amplifier using the triple VDD
opamp. (b) Simulation result of transient analysis. The output swing
achieves three times the standard VDD .

substrate junction breakdown voltage is an issue, for example 4 times the standard VDD , each well voltage should becontrolled dynamically by a similar way to the gate-voltage
control. In that case, the proposed outside-rail opamp shouldbe implemented into the process with well-isolation structure such as triple well or implemented into SOI that is inherently free from the drain-substrate junction breakdown
issue. SPICE simulation is carried out using the aforementioned 0.18-µm CMOS process assuming 5.4-V input
and 5.4-V power supply. Simulated output waveform and
VGS -VGD trajectories of an opamp with three times the standard VDD are shown in Fig. 11 and Fig. 12 respectively. The
output swing achieves three times the standard VDD as show

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791

(a)

(b)

Fig. 12 Simulated VGS -VGD trajectories of which output swing is threetimes the standard VDD . (a) Input stage and level shifter. (b) Output buﬀer.
Each transistor is free from the gate-oxide stress.
Fig. 14 Simulated frequency response of the second-order Sallen-Key
filter with the triple VDD opamp.

and applied to various analog building blocks with a feedback loop such as gain stage and filters. Thus, the proposed
outside-rail opamp is beneficial to reduce area of the circuit
in future scaled transistors designs.
Acknowledgment
Fig. 13 A schematic of an of the Sallen-Key active low-pass filter as anapplication of the proposed outside-rail opamp.

in the figure. All VGS -VGD trajectories extracted from thetransient simulation are shown to be within −1.8 V to 1.8 V
and this verifies that each transistor is free from voltage
over-stress across gate oxide even when the output swingof the circuit is three times the standard VDD . Thus the extendibility to higher voltages is shown and it could be said
that the proposed approach is promising in the further scaled
environments where each transistor tolerates the lower voltages.
4.4 Application of the Outside-Rail Opamp
Figure 13 depicts a schematic of the Sallen-Key active lowpass filter as an application of the proposed outside-rail
opamp. Figure 14 shows a simulation result of the secondorder Sallen-Key filter designed for sound processing circuitry whose cutoﬀ frequency is 10 kHz using the triple VDD
opamp, and the 1 dB compression point is 10.8 dBm. The
simulation results verifies that the proposed opamp could beapplied to various analog building blocks with a feed backloop such as gain stage, integrators, filters and so forth.
5.

Conclusion

An opamp with 3-V outside-rail output swing in a 1.8-V
0.18-µm standard CMOS process is presented and verified
by measurement. The outside-rail opamp shows smallerarea with the same SNR and power consumption comparedwith the un-scaled option and inside-rail design style. The
outside-rail design could be extend to n-tuple VDD opamps

The VLSI chip in this study has been fabricated in the chip
fabrication program of VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Hitachi Ltd. and Dai Nippon Printing Corporation.
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1.9 GHz PA in standard CMOS,” ProRISC2002, pp.141–145, Nov.
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May 2004.
[7] K. Ishida, A. Tamtrakarn, H. Ishikuro, and T. Sakurai, “An outsiderail opamp design targeting for future scaled transistors,” IEEE
Asian Solid-State Circuits Conference, pp.73–76, 2005.
[8] T. Sakurai and A. Newton, “Alpha-power law MOSFET model andits application to CMOS inverter delay and other formulas,” IEEE J.
Solid-State Circuits, vol.25, no.2, pp.584–594, April 1990.
[9] R. Dennard, F. Gaensslen, H. Yu, V. Rideout, E. Bassous, andA. LeBlanc, “Design of ion-implanted MOSFET’s with very small
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[10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill, 2001.

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Koichi Ishidareceived the B.S. degree
in electronics engineering from the University
of Electro-Communications, Tokyo, Japan, in
1998, and received the M.S. and Ph.D. degrees
in electronics engineering from the Universityof Tokyo, Tokyo, Japan, in 2002 and 2005, respectively. He joined Nippon Avionics Co., Ltd.
Yokohama, Japan in 1989, where he developed
high-reliability hybrid microcircuits applied toaerospace programs. He joined Center for Collaborative Research (CCR), the University ofTokyo, Tokyo, Japan in 2005, where he worked on low-voltage low-power
CMOS analog circuit designs. In 2006, he joined in the Integrated Research Institute (IRI), Tokyo Institute of Technology, Tokyo, Japan as a
research associate. His research interests include low-voltage low-power
CMOS analog circuit and RF wireless-communication circuit.

Atit Tamtrakarn
was born in Bangkok,
Thailand, in February 1979.
He received
the B.Eng. and M.Eng. degrees in electrical engineering from Chulalongkorn University,
Bangkok, Thailand, in 2000 and 2002, and the
Ph.D. degree in electronics engineering from the
University of Tokyo, Tokyo, Japan, in 2006, respectively. He joined Sony Corporation, Atsugi,
Japan, in 2006, where he is currently working
on analog mixed-signal circuit design. He also
has interested in low-power CMOS analog/RF
circuit design.

Hiroki Ishikuro
received the B.S., M.S.
and Ph.D. degrees in electrical engineering fromthe University of Tokyo, Tokyo, Japan, in 1994,
1996, and 1999, respectively. In 1999, hejoined the System LSI Research and Development Center, Toshiba Corp., Kawasaki, Japan,
where he was involved in the development of
CMOS RF and mixed-signal LSI’s for wirelessapplications. From 2006, he is an assistant professor at the Keio University. His current research interests lie in the mixed-signal circuitdesign and transceiver architecture for software defined radio.

Makoto Takamiya
received the B.S.,
M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in
1995, 1997, and 2000, respectively. In 2000, hejoined NEC Corporation, Japan, where he wasengaged in the circuit design of high speed digital LSIs and developed the field of on-chip measurement macros to solve the power integrity
issues. In 2005, he joined University of Tokyo, Japan, where he is an Associate Professor
of VLSI Design and Education Center. His research interests include power and signal integrity issues in LSIs, lowpower RF integrated circuits, low-power digital circuits, and large area
electronics with organic transistors.

Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at the
University of California Berkeley, where he conducted research in the field of VLSI CAD. From
1996, he has been a professor at the University of Tokyo, working on lowpower high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC’s and large-area electronics. He has published morethan 350 technical publications including 70 invited publications and several books and filed more than 100 patents. He served as a conference
chair for the Symposium on VLSI Circuits, and ICICDT, a vice chair for
ASPDAC, a TPC chair for the first A-SSCC, and VLSI symposium and a
program committee member for ISSCC, CICC, DAC, ESSCIRC, ICCAD,FPGA workshop, ISLPED, TAU, and other international conferences. He
is a plenary speaker for the 2003 ISSCC. He is a recipient of 2005 IEEEICICDT award, 2005 IEEE ISSCC Takuo Sugano award and 2005 P&I
patent of the year award. He is an IEEE Fellow, a STARC Fellow, anelected AdCom member for the IEEE Solid-State Circuits Society and an
IEEE CAS distinguished lecturer.