IEEE Asian Solid-State Circuits Conference
November 14-16, 2011 / Jeju, Korea

A 80-mV Input, Fast Startup Dual-Mode
Boost
978-1-4577-1785-7/11/$26.00 ©2011 IEEEConverter with Charge-Pumped Pulse Generator forEnergy Harvesting
Po-Hung Chen1, Koichi Ishida1, Xin Zhang1, Yasuyuki Okuma2, Yoshikatsu Ryu2,
Makoto Takamiya1, and Takayasu Sakurai1
1

2

The University of Tokyo, Tokyo, Japan
Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan

Abstract—A low startup-voltage and fast startup dual-mode
boost converter for energy harvesting applications is developedin 65-nm CMOS. Comparing with the previous work [6], thestartup-time, the minimum startup voltage, and the programtime are greatly improved. (1) A startup by the boost converter
instead of a charge pump reduced the startup-time to 4.8ms
which is 1/56 of [6] and the shortest to date. (2) The proposed
sub-1nW charge-pumped pulse generator (CPPG) enabled thelowest startup voltage of 80mV to date without mechanicalswitch. (3) The proposed threshold-voltage-tuned oscillator with
hot-carrier injection (HCI) for CPPG to compensate for the dieto-die process variations reduced the program time to 3min
which is 1/20 of [6], thereby reducing the test cost.

problems. (1) It uses charge pump (CP) to charge the large
output capacitor (COUT) and 262ms of startup time is required,(2) the leakage current shown in Fig. 1 limits the startup
voltage to 95mV, and (3) the fixed-charge threshold voltage(VTH) programming is applied but it takes 60min to adjust theminimum operation voltage (VDDMIN) from 125mV to 82mV.
The 60-min programming time is too long, because the VTH
programming is performed at a pre-shipment test tocompensate for the die-to-die variations and the long machinetime of a tester raises a test cost.
VIN(=95mV)
Fixed-charge VTH
tuned oscillator
CKCP

I. INTRODUCTIONIEEE Asian Solid-State Circuits Conference
November 14-16, 2011 / Jeju, Korea

978-1-4577-1785-7/11/$26.00 ©2011 IEEE

Pulse generator
for operation
Drainleakage
VC

VOUT(~0.9V)

COUT

Fig. 1. Conventional boost converter [6]. Startup is achieved by charging
COUT using charge pump.
VIN(=80mV)

Proposed

VTH-tuned oscillator
with hot-carrier
injection (HCI)(Fig. 6)CKCP
Charge pumped
pulse generator(CPPG) (Fig. 5)

φ1

L1

No drainleakageMS

Pulse generator
for operation

φ2
VCMN

MP
COUT

VOUT (~1.3V)
LoadThe key challenge of the low-input step-up DC-DC
converter for energy harvesting applications is to develop astartup mechanism, which kick-starts operation of the systemfrom extremely low voltage. Until now, several startup
techniques were reported [3]-[6]. In [3], it achieved the startup
voltage of 35mV but an additional mechanical switch which isactivated by motion vibration is required. In [4-5], the systemis startup by a battery or an initial high voltage and theapplication is limited. In [6], a 95-mV startup voltage without
using mechanical switch is realized by the capacitor pass-on
scheme, as shown in Fig. 1, however, there still exists some

0.5V

Load

Recently, the wireless sensor networks are widely
employed in various applications including environmental
monitoring, energy consumption monitoring, and bio-medicalapplications. The self-powered power management circuit
applying energy harvester enables maintenance free sensorsand extends their applications [1]-[2]. The thermoelectric
generator can generate the output voltages in the range of
10mV/K to 50mV/K. For body-wearable applications, theoutput voltage is less than 100mV for temperature differenceof 2K. The single-cell solar cell generates 500-600mV in theoutdoor and 100-200mV in the dark office environment. The
step-up DC-DC converter is required to boost the harvested
energy to usable output because the harvested voltages are too
low to power electronic devices.

Charge pump

Fig. 2. Proposed dual-mode boost converter. Startup is achieved by charging
COUT by boost converter with CPPG.

In this paper, a 80-mV dual-mode boost converter ispresented to solve these problems. The block diagram of theproposed dual-mode boost converter is shown in Fig. 2. The
sub-1nW charge-pumped pulse generator (CPPG) is designed
to activate the boost converter at startup mode. The lowest
startup voltage of 80-mV with 56 times faster startup istherefore achieved. We also proposed a VTH-tuned oscillator
trimmed with hot-carrier injection (HCI) for CPPG tocompensate for the die-to-die process variation. The VDDMIN ofthe oscillator can be reduced from 130mV to 80mV within 3minutes which is 20 times shorter than previous work [6].
This paper is organized as follows. The systemarchitecture and the operation sequences of the proposed boost
converter are described in Section II. Section III shows thecircuit implementation of key building blocks in detail. The
experimental results are shown in Section IV. Finally,
conclusion will be drawn in Section V.
II. SYSTEM ARCHITECTURE
The proposed dual-mode boost converter consists of aboost core, a VTH-tuned oscillator with HCI, a CPPG and apulse generator for operation. The pulse generator is used togenerate a pulse signal with fixed duty cycle and the output
voltage is not regulated. The boost core includes powertransistors MP, MN, and an additional power transistor MS forstartup. Comparing to the conventional approach [6], theproposed circuit startup by switching the transistor MS insteadof charging COUT by charge pump. In addition, the leakage
current of the power transistors is eliminated because CPPG
only drives the gate of MS.
The startup sequences and waveforms of the proposed dualmode boost converter are illustrated in Figs. 3 and 4. Fig. 3(a)shows the startup mode with low startup voltage and Fig. 3(b)shows the operation mode with high conversion efficiency.
These modes can be automatically changed by detecting thecapacitor voltage (VC).
VIN(=80mV)
VTH-tunedoscillator withHCI

Pulse generator

φ2

CKCP~200kHzCPPG

VC (0VÆ0.5V)

φ1
φ1MS

COUT

2kHz(a)VIN(=80mV)
VTH-tunedoscillator withHCI

Pulse generator

φ2

CKCPCPPGφ1

VC (0.5VÆ1.3V)

5MHz

VOUT (~1.3V)
MPMS

COUTLoad

L1LoadL1

VOUT (=0V)MP(b)

Fig. 3. Dual mode in the proposed boost converter (a) Startup-mode(VC≤0.5V). (b) Operation mode (VC>0.5V) with high efficiency.

Startup mode

Operation mode
80mV
0V

VIN

0.5V

φ10V
1.3V
0.5V
0V

VC

1.3V

φ20V
Startup time

VOUT

1.3V
0V

Fig. 4. Waveforms in startup sequences of dual-mode boost converter.

At the startup mode in Fig. 3(a), the VTH-tuned oscillator
with HCI provides the clock signal (CKCP) to CPPG at the low
input voltage (VIN=80mV). CPPG converted VIN to the highamplitude pulse signal (φ1) to activate the power transistor MS.
When φ1 is high, MS turns on and makes inductor current
increases. When φ1 changes from high to low, the current
stored in inductor L1 flow through the diode connected PMOS
transistor MP and charges COUT, as shown in Fig. 4.
When VC is charged to the preset trigger voltage (0.5V),
the boost converter changes the mode from startup mode tooperation mode as shown in Fig. 3(b). VC is detected byapplying the voltage detector presented in [6]. At operationmode, the charge stored in COUT activates the pulse generator
and the pulse generator starts driving the power transistors MN
and MP to achieve high efficiency.
III. CIRCUIT IMPLEMENTATION
A. Charge-Pumped Pulse Generator (CPPG)The CPPG is the key building blocks in the proposed dualmode boost converter. It converts the low VIN to the highamplitude pulse signal (φ1) to activate the power transistor MS
exceeding the amplitude of trigger voltage (~0.5V). The
proposed CPPG provides a solution for generating 0.5-V
amplitude pulse signal with sub-1nW at low VIN using CMOSprocess.
Fig. 5(a) shows the circuit schematic of the proposed
CPPG. It includes a Dickson charge pump and a 0.5-V voltage
detector (VD1) [6]. The trigger voltage of VD1 is determinedby transistor size [6] and VD1 limits the output voltage of
CPPG to be 0.5V. The charge pump is used to boost VIN.
Since the amplitude of CKCP is 80mV, only 1nW output power
can be extracted from the charge pump. The power
consumption of the conventional CMOS ring oscillator islarger than 10nW and can not be used in this application.
Therefore, the CPPG is proposed to generate the pulse signal
with sub-1nW power consumption.
Fig. 5(b) shows the simulated waveform of the proposed
CPPG. Initially, VCP is smaller than the trigger voltage of VD1
and VG provides low. The charge pump charges the node VCP
and φ1. During the charging cycle, since all the transistors areturned-off, the power consumption is very small while VCP

programming and the programming time can be reduced to3min.

VCP(V)0.6

CKCP (200kHz)
VIN=80mV~1nW

Dicksoncharge pump

0.5
0.4
0.3
0.2
0.1
0VCP
VCP

VCP

VCP

VG(V)

0.6

3

412

34

0.4
0.3
0.1
0
0.6
0.5

Delay
φ1(V)

VG

20.2

φ1

VD
MF

1

0.5

0.4
0.3
0.2
0.1

0.5-V voltage
detector

0.0

12

3

4

Time (ms)(b)(a)

Fig. 5. Porposed sub-1nW charge-pumped pulse generator (CPPG). (a)Circuit schematic. (b) Simulated waveform.
11 stages

Output buffer

CKCP

Program_enable
VTH-tuningby HCI

In(~0.1V)

VIN

VIN VNWELLVNWELL(80mV) (80mV)(1V) (8.5V)

Out(~0.1)

OutIn

MNP

MNP

Program_enable (1V)

Program_enable (0V)(a) Program mode(b) Normal mode

In PMOS post-fabrication programming by HCI, the highreverse body bias is applied to PMOS transistors(VNWELL=8.5V) while the input voltage and the 1-V program
enable signal are applied. The transistor MNP is used to pull
down the input and output voltages to 0V to draw a large DC
current through the PMOS transistors. These bias conditions
create hot carriers injection condition for PMOS transistors
and increases ￨VTP￨.
After programming, the circuit is operating under normal
mode as shown in Fig. 6(b) and only an 80-mV input voltage
is applied. The injected holes are still fixed in the PMOS
transistor and VTP is now balanced with VTN and VDDMIN of theoscillator can be reduced.
IV. EXPERIMENTAL RESULTS
The test chips were fabricated using 65-nm standard
CMOS technology. The microphotograph of the proposeddual-mode boost converter is shown in Fig. 7 with active areaof 0.25mm2. Fig. 8 shows the measured dependences ofVDDMIN of the VTH-tuned oscillator on program time using HCI.
To verify VDDMIN reduction, three test dies were measured. As
can be seen, VDDMIN can be reduced to 80mV with 3-minuteprogram time. The VDDMIN is improved by 45% within 10minute program time. By using the proposed method, the test
time can be reduced by 1/20 comparing to [6]. Therefore, theprogramming time and the test cost can be significantlyreduced.

Fig. 6. Circuit schematic of proposed VTH-tuned oscillator with hot-carrierinjection (HCI) for short program time. (a) Program mode. (b) Normal mode.

B. Threshold Voltage (VTH)-Tuned Oscillator with HCIThe VDDMIN of an oscillator is usually limited by VTH
unbalance between NMOS and PMOS caused by process
variation [7]. The within-die variation can be solved byincreasing the transistor size. To make sure the circuit
functions even under die-to-die process variation, we proposed
a VTH-tuned oscillator which trims the VTH by HCI.
The detail circuit schematic is shown in Fig. 6. In themeasured chips, since the VTH of NMOS (VTN) was higher
than that of PMOS (VTP). We illustrate PMOS programming
only to simplify the schematic. Compared with theconventional approach [6] which uses AC pulse current for
programming and requires 60min to adjust the VTH, theproposed scheme in Fig. 6(a) provides DC current path for

Charge pumped
pulse generator(CPPG)

Pulsegenerator

700µmFig. 7. Chip micrograph of dual-mode boost converter in 65-nm CMOS.

140

VDDMIN of Osc. (mV)can still rise. As the VCP is charged to the preset trigger
voltage (0.5V) of VD1, VG turns to high within 10µs andpulls down the voltage φ1 to low. The delay cell is also addedto guarantee that the φ1 is discharged to low.

PowerTr.

VTH-tuned oscillatorwith HCI

350µm

0.7

120

45% reduction

100Target= 80mV

80
60
40
2000Die 1Die 2Die 33 min

2468Program Time (min)10Fig. 8. Measured dependence of VDDMIN of VTH-tuned oscillator with HCI inFig. 6(a) on program time for 3 dies.

VCStartup time= 4.8ms

VOUT

VOUT=1.3VVC

implementation by using CMOS process [6], it achieves 56
times shorter startup time. The proposed circuit also achieves
the lowest startup voltage except for [3], which requires
mechanical switch to assist startup. We also provide a solution
for addressing die-to-die process variations using postfabrication trimming with short program time. Therefore, theproposed circuit is practical for low-voltage energy
scavenging applications.

VINV. CONCLUSIONSVOUTStartup voltage= 80mV

Startup mode

Operation mode

Fig. 9. Measured startup waveforms of proposed dual-mode boost converter.

70

Efficiency (%)

60504030A low startup-voltage and fast startup dual-mode boost
converter is developed for energy harvesting applications. It
provides the maximum conversion efficiency of 60% at
0.5mA load current with 80mV input voltage. Compared withthe previous work [6], the proposed circuit greatly improves
the startup-time, the minimum startup voltage, and theprogram time. The key features of the proposed work includes:(1) the startup time is reduced to 4.8ms which is 1/56 of [6]and is the shortest to date, (2) the lowest startup voltage of80mV without using mechanical switch is achieved, and (3)the proposed VTH-tuned oscillator with HCI to compensate forthe die-to-die process variation reduced the program time to3min which is 1/20 of [6], thereby reducing the test cost.

20

ACKNOWLEDGMENT

10This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy andIndustrial Technology Development Organization (NEDO).

VIN=80mV

0
0.0

0.5

1.0

1.5

2.0

2.5

Load Current (mA)

REFERENCES

Fig. 10. Measured dependence of conversion efficiency on load current.
TABLE I. COMPARISON WITH PUBLISHED LOW-STARTUP VOLTAGE STEP-UP
DC-DC CONVERTER
Startup
RefMechanism

Min.
Startup
Voltagetime

Boost converterwith mechanicalswitch35mV[6]Charge pump

95mV

[4]

External Voltage 650mV[3]This Boost converter
workwith CPPG

80mV

Peak
Efficiency

Program
CMOS
time forprocess
Osc.

58%@
VIN=50mV▬262ms72%@
VIN=100mV

60min

65nm

N/A

75%@
VIN=100mV

▬

130nm

4.8ms

60%@
VIN=80mV

3min

65nm

18ms

[1]

[2]

350nm

[3]

Fig. 9 shows measured startup waveforms of the proposeddual-mode boost converter with CPPG under 80mV input. The
proposed dual-mode boost converter reduces the startup time
to 4.8ms, which is 56 times shorter than [6]. Fig. 10 shows themeasured dependence of conversion efficiency on different
load current. The proposed circuit provides the maximum
efficiency of 60% at 80mV input voltage.
The performance comparison with recently published lowstartup voltage boost converters applying startup mechanism
is shown in Table I. The proposed startup mechanism achieves
the fastest startup time. Compared with the previous

[4]

[5]

[6]

[7]

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