Two Stop-and-Go Gate Driving to Reduce Switching
Loss and Switching Noise in Automotive IGBT
Modules

2022 IEEE 7th Southern Power Electronics Conference (SPEC) | 979-8-3503-9988-2/22/$31.00 ©2022 IEEE | DOI: 10.1109/SPEC55080.2022.10058383

Toshiaki Inuma1, Katsuhiro Hata1, Toru Sai2, Wataru Saito3, and Makoto Takamiya1
1
The University of Tokyo, Tokyo, Japan
2
Tokyo Polytechnic University, Kanagawa, Japan
3
Kyushu University, Fukuoka, Japan

Abstract— A new active gate driving method of “two stop-andgo gate driving (2S&G)” is proposed to reduce both the switchingloss (ELOSS) and the collector current overshoot (IOVERSHOOT) in theturn-on of automotive IGBT modules. 2S&G includes two gate
current zeros during turn-on and has only two parameters for adigital gate driver, which means low test cost for parameter
optimization. Five different gate driving methods, including theconventional single-step gate driving (CSG), the conventional one
stop-and-go gate driving, and digital gate drivings with 100 ns × 4
slots and 20 ns × 20 slots, are compared in the double pulse test
using a 6-bit digital gate driver IC at 300 V and 150 A, and the
proposed 2S&G showed the best performance. Compared with
CSG, the proposed 2S&G reduces ELOSS by 42 % under
IOVERSHOOT-aligned condition and reduces IOVERSHOOT by 18 %under ELOSS-aligned condition.
Keywords— active gate driving, switching loss, switching noise,
IGBT

II. MEASUREMENT SETUP AND DEFINITION OF DIFFERENTGATE DRIVE METHODS
Figs. 1 and 2 show a circuit schematic and a photo of themeasurement setup of the double pulse test for the automotive
IGBT module at 300 V and 150 A, respectively. 6-bit DGD IC
includes 63 parallel-connected pMOSFETs and 63 parallelconnected nMOSFETs. A 6-bit control signal nPMOS [5:0] andnNMOS [5:0] control how many of the 63 parallel-connected
pMOSFETs and nMOSFETs are turned on, respectively. In thispaper, the number of turned-on pMOSFETs and nMOSFETs
are defined as nPMOS and nNMOS, respectively, where they areintegers from 0 to 63. At turn-on, nNMOS = 0 is fixed and nPMOS
is varied; the design value of IG = nPMOS × 79 mA. At turn-off,nPMOS = 0 is fixed and nNMOS is varied; the design value of IG =nNMOS × 79 mA.

I. INTRODUCTION
Digital gate drivers (DGDs), which digitally change the gate
current (IG) multiple times in fine time slots during the switching
period of power devices, are attracting attention as a technologythat can solve the trade-off problem between loss and noise
during power device switching [2-8]. DGDs have the advantagethat the IG waveform can be flexibly changed by software, while
they have the disadvantage that the driving parameters of DGDs
(defined as gate vectors in this paper) have too many degrees of
freedom, making it difficult to determine the optimal gate vector.
For example, in [9], the optimal gate vector is searched by 15min measurements using the particle swarm optimization among(26)60 ( > 10180) possible combinations of a 60-slot 6-bit DGD,
while the high test cost for the optimization is a challenge forpractical applications. To reduce the test cost, a one stop-and-gogate driving (1S&G), which reduces the gate vector to one
parameter, has been proposed and reported to show almost thesame switching loss and noise reduction performance as a 4-slot
digital gate driving in a small capacity IGBT (600 V, 100 A
rating) [1]. This paper shows that the conventional 1S&G does
not work effectively in the turn-on of a large-capacity
automotive IGBT (1200 V, > 200 A rating), and proposes a newactive gate driving method of “two stop-and-go gate driving(2S&G)” to solve the problem.
979-8-3503-9988-2/22/$31.00 ©2022 IEEE

63 parallel-connected
pMOSFETs and nMOSFETs

nPMOS [5:0]
15 V

nNMOS [5:0]

150 A
300 V

IC

6

IG

6

VCE
VGE

Digital gate driver IC

IGBT module

Fig. 1: Circuit schematic of double pulse test for automotive IGBT module.

Digital gate
driver IC

Automotive
IGBT module

Fig. 2: Photo of measurement setup.

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2S&G with two parameters (n1 and n3), where the uneven four
slot lengths are determined by analyzing the best gate vector of
21DG shown later in Table I . The name of 2S&G comes fromthe inclusion of two gate current zeros (nPMOS = 0).

A. Turn-on
At turn-on, five different gate driving methods shown in Fig.
3 are compared, and it will be shown that the proposed 2S&G
shows the best performance. The 6-bit DGD IC is used toachieve five different gate driving methods shown in Fig. 3 withdifferent time slot lengths and gate vectors (n1 to n21 are integers
from 0 to 63) during 400 ns at turn-on. Fig. 3 (a) shows theconventional single-step gate driving (CSG) with one
parameter, which emulates the conventional fixed gate
resistance gate driving method. Figs. 3 (b) and (d) show 1S&G
with one parameter, where the uneven two slot lengths are
determined by [1], and a 5 variable digital gate driving (5DG)
with 100 ns × 4 slots and last long slot, respectively, which areproposed in [1]. Fig. 3 (e) shows a 21 variable digital gate
driving (21DG) with 20 ns × 20 slots and last long slot as theultimate digital gate driving. Fig. 3 (c) shows the proposed

Off

B. Turn-off
At turn-off, four different gate driving methods shown in
Fig. 4 are compared, and it will be shown that the proposed
2S&G is not required. The 6-bit DGD IC is used to achieve four
different gate driving methods shown in Fig. 4 with different
time slot lengths and gate vectors (n1 to n21 are integers from 0
to 63) during 800 ns at turn-off. Fig. 4 (a) shows CSG. Figs. 4(b) and (c) show 1S&G [1], and 5DG with 200 ns × 4 slots andlast long slot, respectively. Fig. 4 (d) shows 21DG with 40 ns ×
20 slots and last long slot as the ultimate digital gate driving.

On

nPMOS
Conventional
single-step gate
driving (CSG)

n1

(a)

0
nPMOS

(b)

n1
0

nPMOS
(c)

0
140 ns

260 ns
n1

0

nPMOS
(d)

Time
63
1 stop-and-gogate driving(1S&G)
Time0

240 nsn1

63
0

40 ns 40 ns 80 ns
n3
n4

n2

0

n3

Time
n5
Time

nPMOS
(e)

100 ns×4 slot = 400 ns
n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21

0
Time

nNMOS
63

Proposed 2
stop-and-go gate
driving (2S&G)
5 variable
digital gate
driving (5DG)
21 variable
digital gate
driving (21DG)

20 ns×20 slot = 400 ns
0
Time
VGE

0V
IOVERSHOOT

VCE

Time

IC

400 nsTime

Fig. 3: Five different gate driving methods compared at turn-on. (a) Conventional single-step gate driving (CSG). (b) One stop-and-go gate driving (1S&G). (c)Proposed two stop-and-go gate driving (2S&G). (d) 5 variable digital gate driving (5DG). (e) 21 variable digital gate driving (21DG).

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On

Off

nPMOS
63
0
nNMOS

Time

Conventional
single-step gate
driving (CSG)

n1

(a)

0
nNMOS

(b)

0

0
400 ns

nNMOS
(c)

Time
63
1 stop-and-gogate driving(1S&G)
Time

n1

n1

400 ns
n3

n2

0

n4

n5

Time
nNMOS
(d)

200 ns×4 slot = 800 ns
n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21

0

Time
VGE

5 variable
digital gate
driving (5DG)
21 variable
digital gate
driving (21DG)

40 ns×20 slot = 800 ns

0V

Time
VOVERSHOOT

IC
VCE

Time

800 nsFig. 4: Four different gate driving methods compared at turn-off. (a) Conventional single-step gate driving (CSG). (b) One stop-and-go gate driving (1S&G). (c)5 variable digital gate driving (5DG). (d) 21 variable digital gate driving (21DG).

III. MEASURED COMPARISON OF DIFFERENT GATE DRIVE
METHODS
A. Turn-on
Fig. 5 shows the measured switching loss (ELOSS) vs.
collector current overshoot (IOVERSHOOT) at turn-on. The fivedifferent gate driving methods are compared. In this paper, anevaluation function (fOBJ) shown in Eq. (1) is defined as aperformance index of gate driving, and it is discussed that a gate
driving with small fOBJ is an excellent gate driving with small
ELOSS and IOVERSHOOT.
2 ELOSS   I OVERSHOOT 
f OBJ =  + 

E
 LOSS, MAX   I OVERSHOOT, MAX 

2()

where the subscript MAX signifies the maximum of thecorresponding quantity. The dotted concentric curves in Fig. 5

show the contour of fOBJ. Table I shows the details of Points A to
F in Fig. 5 and the ranking of fOBJ. The black curve in Fig. 5
shows the trade-off curve of CSG with varied n1 from 3 to 63.
Points C and D are the best points that achieved the smallest fOBJ
with all search measurements of n1, n1 and n3 in 1S&G and
2S&G, respectively. The analysis of (26)2 measurements showsthat n1 optimization is important for 2S&G, while n3
optimization is not. Therefore, the test cost of 2S&G is low
because the optimization of n3 can be omitted and only the
optimization of n1 is needed. Points E and F are the best points
where the smallest fOBJ is achieved by repeatedly measuring andsearching for n1 to n5 and n1 to n21 using the simulated annealing
algorithm [2] for 5DG and 21DG, respectively. Specifically,
21DG took 14411 measurements (note that this is much smaller
than the number of 6421 ( > 1037) combinations) over 12 hours
and 30 minutes to complete the search. As shown in Table I, fOBJ
ranks the proposed 2S&G in first place, 21DG in second place,
5DG in third place, and 1S&G in fourth place, with the proposed
2S&G showing the best performance. Points A and B are CSG

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ELOSS, MAX

CSG
Point A

0.8

6

Point C
(1S&G)−42%

っx

ELOSS [mJ]

0.7
0.6
0.5

4

0.4

Point F (21DG)
Point D
−18%
(Proposed
2S&G) Point E
(5DG)

0.3

2

0.2
0.1

0

0

Point B

20

40

60

80

100

IOVERSHOOT [A]120
IOVERSHOOT, MAX

Fig. 5: Measured ELOSS vs. IOVERSHOOT at turn-on. Five different gate driving
methods are compared.
TABLE I.

DETAILS OF POINTS A TO F IN FIG. 5 AT TURN-ON

Gate driving
ELOSS IOVERSHOOT
Ranking
Gate vectors
fOBJ
method[mJ][A]
of fOBJ
Point A
CSG
n1 = 4
6.0
101
1.06
6th
Point B
CSG
n1 = 8
3.6
121
0.99
5th
Best point
Point Cn1 = 41
5.3
88
0.93
4th
in 1S&G
Best point
Point D in proposed (n1, n3) = (20, 44)
3.5
99
0.83
1st
2S&G
Best point (n1, n2, n3, n4, n5) =Point E
3.3
107
0.88
3rd
in 5DG(32, 39, 0, 35, 52)
Best point
Point F
3.8
99
0.86
2nd
in 21DGn1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21

ELOSS, MAX

0 25 32 60 37 11 14 59 60 46 0

0 24 00 35 37 62

CSG
Point A

0.8

6

Point C
(1S&G)
1S&G

っ
x

0.7

ELOSS [mJ]

0 33 5

0.6
0.5

4

0.4

Point F (21DG)
Point D
(Proposed
2S&G) Point E
(5DG)

0.3

2

0.2
0.1

0

0

Point B

20

40

60

80

100

IOVERSHOOT [A]120
IOVERSHOOT, MAX

Fig. 6: Measured ELOSS vs. IOVERSHOOT at turn-on. In 1S&G, n1 is varied from0 to 63. Red numbers indicate n1.

points with IOVERSHOOT and ELOSS approximately the same as the
proposed Point D, respectively. As shown in Fig. 5, comparedwith CSG (Points A and B), the proposed 2S&G (Point D)
reduces ELOSS from 6.0 mJ to 3.5 mJ by 42 % under IOVERSHOOTaligned condition and reduces IOVERSHOOT from 121 A to 99 A by
18 % under ELOSS-aligned condition.
To analyze 1S&G in detail, Fig. 6 shows measured ELOSS vs.
IOVERSHOOT of the five different gate driving methods. In 1S&G,
n1 is varied from 0 to 63. Red numbers in Fig. 6 indicate n1. Since
the trajectory of 1S&G is far from the proposed 2S&G (Point D),
it is clear that 1S&G is inferior to 2S&G.
Fig. 7 shows the gate vectors and measured waveforms from
Points A to F. Here the reasons why ELOSS of 1S&G (Point C) islarger than that of the proposed 2S&G (Point D) are discussed.
In 1S&G in Fig. 7 (c), the negative dIC / dt during the 260-ns
nPMOS = 0 period causes VCE overshoot, resulting in large ELOSS,
while the proposed 2S&G in Fig. 7 (d) successfully reduces
ELOSS by inserting a slot with nPMOS = 44 during 160 ns toincrease VGE and decrease VCE rapidly.
B. Turn-off
Fig. 8 shows the measured ELOSS vs. collector-to-emitter
voltage overshoot (VOVERSHOOT) at turn-off. The four different
gate driving methods are compared. In this paper, an evaluation
function (fOBJ) shown in Eq. (2) is defined as a performanceindex of gate driving, and it is discussed that a gate driving withsmall fOBJ is an excellent gate driving with small ELOSS and
VOVERSHOOT.
2 ELOSS   VOVERSHOOT 
f OBJ =  + 

E
 LOSS, MAX   VOVERSHOOT, MAX 

2()

where the subscript MAX signifies the maximum of thecorresponding quantity. The dotted concentric curves in Fig. 8
show the contour of fOBJ. Table II shows the details of Points G
to K in Fig. 8 and the ranking of fOBJ. The black curve in Fig. 8
shows the trade-off curve of CSG with varied n1 from 3 to 63.
Point I is the best points that achieved the smallest fOBJ with all
search measurements of n1 in 1S&G. Points J and K are the best
points where the smallest fOBJ is achieved by repeatedly
measuring and searching for n1 to n5 and n1 to n21 using thesimulated annealing algorithm [2] for 5DG and 21DG,
respectively. Specifically, 21DG took 3098 measurements over
2 hours and 40 minutes to complete the search. As shown in
Table II, fOBJ ranks 5DG in first place, 21DG in second place,
1S&G in third place, which is a similar result to [1] in that fOBJ’sof 5DG and 1S&G are almost the same. Points G and H are CSG
points with VOVERSHOOT and ELOSS approximately the same as
Point J, respectively. As shown in Fig. 8, compared with CSG(Points G and H), 5DG (Point J) reduces ELOSS from 21.2 mJ to
12.4 mJ by 42 % under VOVERSHOOT-aligned condition andreduces VOVERSHOOT from 162 A to 85 A by 48 % under ELOSSaligned condition.
To analyze 1S&G in detail, Fig. 9 shows measured ELOSS vs.
VOVERSHOOT of the four different gate driving methods. In 1S&G,
n1 is varied from 0 to 63. Red numbers in Fig. 9 indicate n1. Since
the trajectory of 1S&G passes close to 5DG (Point J), theAuthorized licensed use limited to: University of Tokyo. Downloaded on April 09,2023 at 07:01:07 UTC from IEEE Xplore. Restrictions apply.

ELOSS : 3.6 [mJ]

ELOSS : 6.0 [mJ]

200 ns/div

200 ns/div
VGE: 4 V/div

VGE: 4 V/div

IC: 100 A/div

IC: 100 A/div
0

4

0

0
VCE： 100 V/div

nPMOS

8

0

(b) Point B (CSG, n1 = 8)(a) Point A (CSG, n1 = 4)
ELOSS : 3.5 [mJ]

ELOSS : 3.3 [mJ]

200 ns/div

200 ns/div

200 ns/div

ELOSS : 3.8 [mJ]
200 ns/div

VGE: 4 V/div

VGE: 4 V/div

VGE: 4 V/div

VGE: 4 V/div

IC: 100 A/div

IC: 100 A/div

IC: 100 A/div

IC: 100 A/div

0

63

41

nPMOS

nPMOS

VCE： 100 V/div00

140 ns 260 ns(c) Point C (1S&G)

VCE： 100 V/div0

44
20 0 063

240 ns 160 ns(d) Point D (Proposed 2S&G)

0

nPMOS

0

ELOSS : 5.3 [mJ]

VCE： 100 V/div

032 39 35
052

100 ns×4 slot(e) Point E (5DG)

0

nPMOS

nPMOS

VCE： 100 V/div

VCE： 100 V/div
62
0

20 ns×20 slot(f) Point F (21DG)

Fig. 7: Gate vectors and measured waveforms from Points A to F at turn-on.

ELOSS, MAX

TABLE II.

Point G
20

0.8

CSG

ELOSS [mJ]

0.7
15

0.6

0.5

10

0.4
0.3

っ
K
xPoint(21DG)−42%
Point I
(1S&G)

Point H−48%

Point J
(5DG)

n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21

0

25

0

0

0

0 48 50

6

performance of 1S&G and 5DG is almost identical and 1S&G is
more practical than 5DG because of the lower test cost, which isthe same conclusion as [1].

0.10Gate driving
ELOSS VOVERSHOOT
Ranking
Gate vectors
fOBJ
method[mJ][V]of fOBJ
Point G
CSG
n1 = 4
21.2
96
1.03
5th
Point HCSG
n1 = 10
12.3
162
0.97
4th
Best point
Point In1 = 45
13.3
82
0.70
3rd
in 1S&G
Best point (n1, n2, n3, n4, n5) =Point J
12.4
85
0.67
1st
in 5DG( 63, 33, 0, 3, 18)Best point
Point K
12.6
89
0.69
2nd
in 21DG

33 53 20 32 36 9 60 41 25 63 26 45 1

0.2

5

DETAILS OF POINTS G TO K IN FIG. 8 AT TURN-OFF

50

75

100

125

VOVERSHOOT [V]

150 175
VOVERSHOOT, MAX

Fig. 8: Measured ELOSS vs. VOVERSHOOT at turn-off. Four different gate driving
methods are compared

Fig. 10 shows the gate vectors and measured waveforms
from Points G to K. A common trend among Points I to K is toset nNMOS to zero just before VOVERSHOOT occurs, thereby
successfully achieving both low ELOSS and low VOVERSHOOT,
which is the same conclusion as [1]. Here the reasons why the
proposed 2S&G is required for turn-on, but not for turn-off, arediscussed. At turn-on of 1S&G shown in Fig. 7 (c), during the260-ns nPMOS = 0 period, IC does not increase monotonically, but

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the proposed 2S&G is not required for turn-off, where IC change
is monotonic.

CSG

IV. CONCLUSIONS

20

0.8

This paper shows that the conventional 1S&G does notwork effectively in the turn-on of the large-capacity automotive
IGBT (1200 V, > 200 A rating), and proposes a new active gate
driving method of 2S&G to solve the problem. It is concluded
that the proposed 2S&G is required for turn-on, where ICchange is not monotonic, while the proposed 2S&G is not
required for turn-off, where IC change is monotonic. In the turnon measurements, compared with CSG, the proposed 2S&G
with low test cost reduces ELOSS by 42 % under IOVERSHOOTaligned condition and reduces IOVERSHOOT by 18 % under ELOSSaligned condition at 300 V and 150 A.

ELOSS [mJ]

0.7

15

0.6

1S&G

0.5

10

0.4

Point I

Point K (21DG)

0.3 (1S&G)

5

Point J
(5DG)

0.2
0.1

0

0

100

50

150

200

ACKNOWLEDGMENT

250

VOVERSHOOT [V]Fig. 9: Measured ELOSS vs. VOVERSHOOT at turn-off. In 1S&G, n1 is varied from0 to 63. Red numbers indicate n1.

This work was partly supported by New-generation PowerElectronics and System Research Consortium Japan (NPERCJ), FS research (PJ-08).

drops once in the middle. In contrast, at turn-off of 1S&G shownin Fig. 10 (c), during the 400-ns nNMOS = 0 period, IC decreases
monotonically. Thus, it is concluded that the proposed 2S&G isrequired for turn-on, where IC change is not monotonic, while
ELOSS : 12.3 [mJ]

ELOSS : 21.2 [mJ]

200 ns/div

200 ns/div
VGE: 4 V/div

VGE: 4 V/div

VCE： 100 V/div

IC: 100 A/div
0

0
VCE： 100 V/div
nNMOS

nNMOS

IC: 100 A/div

4

10

0

(b) Point H (CSG, n1 = 10)(a) Point G (CSG, n1 = 4)
ELOSS : 13.3 [mJ]
200 ns/div

0

VCE： 100 V/div
63

45
0

0
400 ns 400 ns(c) Point I (1S&G)

IC: 100 A/div
0

VCE： 100 V/div
63

33

200 ns/div

VGE: 4 V/div

IC: 100 A/div

nNMOS

nNMOS

0

200 ns/div

VGE: 4 V/div

IC: 100 A/div

ELOSS : 12.6 [mJ]

0

3

18

200 ns×4 slot(d) Point J (5DG)

nNMOS

VGE: 4 V/div

ELOSS : 12.4 [mJ]

VCE： 100 V/div
63

60

53
33

32
20

25
9

48

45

41

36

26
1 0 0 0 0506

40 ns×20 slot(e) Point K (21DG)

Fig. 10: Gate vectors and measured waveforms from Points G to K at turn-off.

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