A 100Mbps, 0.41mW, DC-960MHz Band Impulse UWB Transceiver in 90nm CMOS
Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Ryu Jisun, Koichi Ishida,
Makoto Takamiya and Takayasu Sakurai
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, JapanAbstract
A low power impulse ultra-wideband (UWB) transceiverfor DC-960MHz band is proposed in this paper. It features adigital pulse-shaping transmitter, a DC power-free pulse
discriminator and an error-recovery phase-frequency detector.
The developed transceiver in 90nm CMOS achieves thelowest energy consumption of 2.2pJ/bit (TX) and 1.9pJ/bit(RX) at 100Mbps.
Introduction
UWB communication systems can be broadly classified as
impulse UWB and multi-carrier UWB. For the impulse UWB,
multi-user detectors (MUD) and hybrid RAKE/MUD-UWB
transceivers for robust narrowband interference suppression
are becoming popular. However, a simple, single
clocked-correlator transceiver [1] or threshold detector [2]can also be used for short distance and high SNR
environments.
In this paper a novel DC-960MHz impulse UWBtransceiver [2, 3] is proposed for the low power ad-hoc
wireless sensor networks. These ubiquitous networks requirethat the individual nodes are tiny, easily integratable into theenvironment, and have negligible cost. The proposedtransceiver features a digital pulse-shaping transmitter, a DC
power-free pulse discriminator and an error-recovery
phase-frequency detector (PFD), thereby achieving extremely
low power consumption at 100Mbps.
Digital Pulse-Shaping Transmitter
Digital pulse shaping in UWB transmitters (TX’s) is a
power efficient technique. All the previously reporteddigitally pulse shaped TX’s [4-7], however, were developed
for above-3GHz band and no TX for DC-960MHz band has
been reported. Fig. 1(a) shows the proposed digitalpulse-shaping TX. The TX generates the FCC-compliant first
derivative Gaussian pulse with multi-drivers. Fig. 1(b) shows
the operation principle of TX. Sequentially operated 8 drivers
shape a pulse. The 32-tap delay line determines the timing forthe drivers. Fig. 2 shows the reason why the pulse shaping
with multi-drivers is required for the DC-960MHz band. The
conventional TX’s with a single driver per pulse do not passthe FCC mask, because the pulse width of the DC-960MHz
band is long. In contrast, the developed pulse shaping with 8drivers satisfies the FCC mask.
Receiver with DC Power-Free Pulse Discriminator
An ultra low-power solution for BPSK demodulation isleading edge detection (LED) technique [2]. The LED
receiver (RX) sets a threshold at the receiver, and any
incoming pulse that crosses the threshold is detected anddemodulated. The proposed asynchronous threshold detector
is shown in Fig. 3. It consists of four blocks: a front-end
amplifier, a DC power-free pulse discriminator, anerror-recovery PFD and a Reset-Set Flip-Flop (RSFF). The
received signal is first amplified by the front-end amplifier
and each BPSK symbol is split into two pulses V0 and V1 by
the DC power-free pulse discriminator. Then the firstincoming edge of the two pulses is detected by the PFD and
the RSFF converts the detection result to the corresponding
data bit.
Conventionally, an amplifier and a comparator can be usedas the threshold detector. The major disadvantage of this
topology is large DC power dissipation that occurs even for
no AC input. In the transmitted BPSK signal, the circuit

978-1-4244-1805-3/08/$25.00 © 2008 IEEE

spends long periods of time with no AC signal. Powerdissipated in these periods is wasted. The operation principleof the proposed DC power-free pulse discriminator is shownin Fig. 4(a). Two unbalanced inverter InvH and InvL areemployed to detect the positive pulse and negative pulse
respectively. To tune the threshold of the pulse discriminator,
variable bias voltages VL for the source input of the top
inverter and VH for the bottom inverter are used. As shown inFig. 4(b), the proposed pulse discriminator has essentiallyzero power dissipation for no AC input.
A spurious-free PFD [8] is used to avoid simultaneous highinput to the RSFF. One problem with this topology is that thebit error in the previous cycle due to signal distortion will be
carried over to the subsequent cycles. To remove the error
propagation, in the proposed error-recovery PFD shown inFig.5, an additional RESET signal is fed back to the PFD
input after certain time-delay in every cycle. Fig. 6 shows thesimulation results for the data “10100” with and without theerror-recovery circuit.
Experimental Results
Both TX and RX without the front-end amplifier were
designed and fabricated in 90nm CMOS process. The
micrograph is shown in Fig. 7. Fig. 8 shows the measured
waveform and spectrum of TX output at 100Mbps, which
satisfies the FCC mask. Fig. 9 shows the measured
waveforms of RX. The potential error propagation due todistorted signal “1” is blocked by the error-recovery RESET
signal. The measured BER and RX power dependence on data
rate at different bias voltage are shown in Fig. 10. The bias
voltage can tune the tradeoff between the sensitivity andpower. DC power-free pulse discriminator enables the data
rate dependent power. Table I summaries the performance ofthe whole chip. The developed transceiver consumes 220μW(TX) and 190μW (RX) at 100Mbps. Fig. 11 shows thecomparison with the state-of-art UWB transceivers. Both TX
and RX achieved the lowest energy per bit.
Conclusions
The transceiver in 90nm CMOS achieves the lowest
energy consumption of 2.2pJ/bit (TX) and 1.9pJ/bit (RXwithout the front-end amplifier) at 100Mbps.
Acknowledgment
This work is partially supported by CREST/JST. The
VLSI chips were fabricated through the chip fabrication
program of VDEC with the collaboration by STARC.
References[1] T. Terada et al., Symp. on VLSI Circuits, pp. 30-33, 2005.
[2] A. Tamtrakarn et al., Symp. on VLSI Circuits, pp. 250-251, 2006.
[3] I. O’Donnell et al., Symp. on VLSI Circuits, pp. 248-249, 2006.
[4] D. D. Wentzloff et al., ISSCC, pp. 118-119, 2007.
[5] J. Ryckaert et al., ISSCC, pp. 120-121, 2007.
[6] V. Kulkarni et al., CICC, pp. 647-650, 2007.
[7] T. Norimatsu et al., ESSCIRC, pp. 267-270, 2005.
[8] L. Liu et al., Electronics Letters, pp. 918-920, 2004.
[9] S. Lo et al., ISSCC, pp. 118-119, 2006.
[10] T. Aytur et al., ISSCC, pp. 124-125, 2006.
[11] Y. Zheng et al., ISSCC, pp. 114-115, 2007.
[12] J. R. Bergervoet et al., ISSCC, pp. 112-113, 2007.
[13] A. Medi et al., Symp. on VLSI Circuits, pp. 58-59, 2007.
[14] T. Terada et al., Symp. on VLSI Circuits, pp. 86-87, 2007.
[15] J. Ryckaert et al., ISSCC, pp. 114-115, 2006.
[16] F. S. Lee et al., ISSCC, pp. 116-117, 2007.

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(b)

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(c)(a)

VDD=1V
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VH

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InvH

UP

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Fig. 3 Proposed RX with DC power-free pulse discriminator.

FCC mask-60-70-80
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Fig. 5 Error-recovery PFD.

(b)

Table. I Performance summary.

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Fig. 4 Pulse discriminator. (a) Operation
principle. (b) Simulated waveforms.
(a)5Fig. 2. Simulated TX output. (a)Waveforms. (b) Conv. TX with single
driver. (c) Proposed TX with 8 drivers.

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165 μmTechnology

90nmCMOS

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Data Rate

100Mbps

Power@ TX
100Mbps RX

220μW

Energyper bit

TX

2.2pJ/bit

RX

1.9pJ/bit

Core
Area

TX

55μm×165μm

190μW

RX

18μm×32μm

Modulation

32 μm

BPSK

Fig. 7 Chip micrographs and layout. (a) TX. (b) RX.

Fig. 6 Simulated waveforms of PFD. (a) Without error-recovery
reset. (b) With error-recovery reset.

Distortion
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80100

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Amplitude of In (V)Fig. 10 Measured RX characteristics. (a) BER vs. In. (b) Power vs. data rate.

978-1-4244-1805-3/08/$25.00 © 2008 IEEE

1200.1mW
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100k

[15]

This Work

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Fig. 11 Comparison with the published UWB transceivers. (a) TX. (b) RX.

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