ESSCIRC 2002

A 6.7-fF/µm2 Bias-Independent Gate Capacitor (BIGCAP) with Standard
CMOS Process and its Application to the Loop Filter of a Differential PLL
Makoto Takamiya, Takeshi Fukumoto, and Masayuki Mizuno
Silicon Systems Research Laboratories, NEC Corporation
1120, Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japantaka@mel.cl.nec.co.jp

A linear bias-independent gate capacitor (BIGCAP)
with large intrinsic capacitance and low parasitic capacitance, which needs no additional fabrication process steps, is proposed. Measured results with 0.13-µmstandard CMOS technology show that the intrinsic capacitance is 6.7 fF/µm2 (6.7 times bigger than that oftypical MIM capacitors) and the parasitic capacitance is
1.9% of the intrinsic capacitance (one-fifth that of typical MIM capacitors). The linearity is ±2.9% and capacitance variation across a wafer is as small as σ =0.096%.
Applying BIGCAP to the loop filter of a differential
PLL reduces the gate area of the MOS capacitor for theloop filter to only 35% of that of the conventional design
without degrading the performance of the PLL. Themeasured jitter at 840 MHz was 7.0 ps (rms) and 74.4 ps(p-p) for 1.5-V supply.

1. Introduction
Bias-independent (i.e., linear) capacitors are needed
for many applications such as the loop filter of a PLL,
level-shift in I/O buffers, switched-capacitor circuits,phase-compensation in operational amplifiers, data converters, and mixers. Most of these applications employ
MIM or poly-to-poly capacitors to retain high linearity at
the cost of additional process steps and a large area dueto the low capacitance-per-unit area (~ 1 fF/µm2). Various MIM capacitors [1-2] that require no additional
process steps show very low capacitance (0.2 ~ 0.3
fF/µm2). Though the capacitance-per-unit area of theconventional MOS gate capacitors is one or two ordersof magnitude higher, MOS gate capacitors cannot beapplied to these applications because of their large nonlinearity.
This paper presents a linear area-efficient MOS gate
capacitor with low parasitic capacitance that can be fabricated using a standard digital CMOS fabrication process. The bias-independent gate capacitor (BIGCAP) isapplied to the loop filter of a differential PLL.

2.

BIGCAP concepts and configurations

Figure 1 shows the configuration of BIGCAP, whichis composed of a pair of accumulation-mode n-poly gate
capacitors in an n-well and a pair of pMOS gate capacitors. The n-poly gate capacitors can be fabricated byreplacing the p-well for nMOS by an n-well for pMOS
in the standard CMOS process. In order to obtainsymmetrical bias-dependence, i.e., bipolarity, both the npoly gate capacitors have the same layout and only theconnections are reversed. The same is true of the pMOS
gate capacitors. As shown in Fig. 2(a), the pair of npoly gate capacitors shows its maximum capacitance at 0V, while the pair of pMOS gate capacitors (Fig. 2(b))
shows its minimum capacitance at 0 V. Therefore, byappropriately adjusting the area ratio between the n-polyand pMOS gate capacitors, we can achieve a very low
dependence of capacitance on bias.

1st. terminal (T1)+-Abstract+
2nd. terminal (T2)n-poly gate capacitor
T1
T2
T2
n-polyn+n+pMOS gate capacitor
T1p-polyn+p+p+n-welln-well
p-substrate

Figure 1. Configuration of BIGCAP. The bias
dependence of the capacitance of the n-poly andpMOS gate capacitors cancel each other out.

139

+--++-

Bias voltage [V](a)Capacitance [pF]

10-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

at fixed n-poly capacitor

250
200x=150

pMOS cap. arean-poly cap. area

x 100 [%]

100Lgate=25 µm0-2.0-1.5-1.0-0.50.00.5

1.01.52.0Bias voltage [V]Figure 3. Measured C-V characteristics ofBIGCAP for various values of x at a fixed area ofthe n-poly gate capacitors.

110Linearity [%]Bias voltage [V](b)Figure 2. C-V characteristics. (a) The pair of npoly gate capacitors. (b) The pair of pMOS gatecapacitors.

Max cap. - Min cap.
Average cap. x 2765432Best

10Experimental results of BIGCAP051015202530pMOS/n-poly ratio (x) [%]Figure 4. Dependence of the linearity on x extracted from Fig. 3.
T1

T2

Gate
capacitance(intrinsic)

n-well / p-substratecapacitance(parasitic)

Figure 5. Equivalent circuit of BIGCAP.
Parasitic capacitance[%]
Cpara=Intrinsic capacitance

Figure 3 shows the dependence of the capacitance ofBIGCAP on bias as measured at 100 kHz. The ratio (x)of the n-poly gate capacitors’ area to that of the pMOSgate capacitors was varied by changing the area of thelatter. Figure 4 shows the linearity extracted from Fig. 3.
The smallest dependence of capacitance on bias appeared with ±2.9% linearity from -2 V to 2 V, when theratio (x) was 15%. This optimum ratio depends on each
CMOS process. The intrinsic capacitance of BIGCAP
was 6.7 fF/µm2, which is 70% of the gate capacitance of
9.6 fF/µm2 at inversion and 6.7 times as large as thetypical MIM capacitor’s value of 1.0 fF/µm2.
Figure 5 shows an equivalent circuit of BIGCAP.
The measured parasitic capacitance between the n-welland p-substrate of BIGMOS is as small as 1.9% of theintrinsic gate capacitance, which is smaller than the 11%reported in [1] and 6% reported in [2]. Figure 6 shows
the calculated dependence of the relative parasitic capacitance (Cpara) on the intrinsic capacitance (Cint) for
various gate lengths (Lgate). Here, Cpara is the parasitic
capacitance over the intrinsic capacitance in percentage.
Measured data is also plotted, and it fits the calculated
results very well. A long Lgate achieves the smallest Cpara
for a large Cint, while a short Lgate achieves the smallest
Cpara for a small Cint, because, in the long-and-narrow
layout, the area of the n-well is much larger than the gatearea. These results indicate that there is an optimum

Linearity = -+-80-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

140x=
25
2015105093.

100 kHz300

50

2Capacitance [a.u.]

Lgate to achieve the smallest Cpara for a given Cint When
Cint is larger than 100 fF, Cpara is less than 4%.
350+-Capacitance [a.u.]

214x =15%

12108Lgate=1 µm

64201f5 µm

Calculated25 µm10f100f

1p

10p

Measured
100p1nIntrinsic capacitance (Cint) [F]Figure 6. Calculated dependence of the relative
parasitic capacitance on the intrinsic capacitance.

Fig. 7 shows the dependence of the Q-value of
BIGCAP on frequency as measured with a network analyzer. The Q-value was 4 at 50 MHz and 217 pF. The
Q-value normalized by frequency and capacitance was
43 / (f (GHz) C (pF)), which is sufficient for mostapplications.
The measured capacitance variation across the wafer
was σ = 0.096%, which is much smaller than the 1.5%
reported in [1], because the capacitance of BIGMOS isdetermined by the gate oxide thickness, unlike the MIM
capacitors. Figure 8 shows the measured bias dependence of the BIGCAP capacitance for different pMOSthreshold voltages as the n-well doping concentration
was changed. The capacitance variation was only σ =0.69% for a 0.1 V threshold voltage variation.
5Bias = 0V
C = 217pF
Lgate = 5 µm

Q-value

43Q=
2- Im(Zin)
Re(Zin)100100200300400500600

Frequency [MHz]Figure 7. Measured Q-values of BIGCAP as afunction of frequency.

low. The common-mode feedback circuit keeps thecommon-mode of the differential control voltages.
Here, we discuss the capacitance of the LF in a differential PLL. Figure 10(a) shows the conventional configuration of the LF of a differential PLL, and Fig. 10(b)shows the proposed configuration. The conventional LFin Fig. 10(a) requires twice as much capacitance as theLF of a single-ended PLL. Therefore, the PLL area isnearly twice as large, because it is generally determinedby the large capacitance of LF which is shown as CY inFig. 10. If the capacitor used in the LF is biasindependent, CY can be inserted between Vcnt and Vcntb
as shown in Fig. 10(b). In this case, the capacitanceneeded to achieve the same transfer function as in Fig.
10(a) is only CY/2 by the mirror effect, which is onefourth the size of that in Fig. 10(a) and half the size ofthat of the single-ended PLL. However, the n-poly gate
capacitor, which is widely used in LF, cannot be inserted
between Vcnt and Vcntb, because the capacitance of the npoly gate capacitor changes dramatically depending onwhether the bias voltage is positive or negative. It has
been reported that the proposed LF in Fig. 10(b) can bemade by using a bias-independent poly-to-poly capacitor[3]. However, the area of the PLL is very large, because
the capacitance-per-unit-area of the poly-to-poly capacitor is about one-tenth that of the n-poly gate capacitor.
To solve this problem, BIGCAP is applied to the proposed LF in Fig. 10(b).
Ref.
clockup

1.04

PFD

Capacitance [a.u.]

1.03

down

1.02
1.01

Vcnt

ChargepumpOut

Loopfilter

Charge
pump

VCO

Vcntb

Outb

Common-mode
feedback

1.00
0.99
0.98
0.97

σ = 0.69%

0.96

100 kHz

0.95

Lgate=25 µm

0.94
-2.0

-1.5

-1.0-0.5∆Vth(PMOS)

1/2 divider= 0.1 V

Figure 9. Block diagram of the differential PLL.

x = 15%
0.0

0.5

1.0

1.5

2.0

Vcnt

Bias voltage [V]CX

Figure 8. Measured C-V characteristics ofBIGCAP for various pMOS threshold voltages.

4. Application of BIGCAP to the loop filterof a differential PLL
Recently, the differential PLLs are often used toavoid an increase in jitter due to the supply-noise. Figure 9 shows a block diagram of a differential PLL. Twooutputs (Vcnt, Vcntb) of the two charge pump circuits aredifferential control voltages of VCO. The loop filter(LF) is connected between Vcnt and Vcntb. When one ofthe differential control voltages goes high, the other goesVcnt
CXRCY/2

CYVcntb

RVcntbCXRCXCY(a)R(b)=CY
CYn-poly gatecapacitor
BIGCAP

Figure 10. Configuration of the loop filter of thedifferential PLL. (a) Conventional configuration.
(b) Proposed configuration. BIGCAP was usedfor CY in (b), and n-poly gate capacitors wereused for the other capacitances.

141

A PLL with the proposed LF in Fig. 10(b) was fabricated by 1.5-V 0.13-µm CMOS. Figure 11 shows a micrograph of the fabricated PLL. BIGCAP was used for
CY, and the n-poly gate capacitor was used for CX in Fig.
10(b). Parameters of the fabricated LF were CX = 5 pF,
R = 0.5 kΩ, and CY/2 = 250 pF. As shown in Fig. 12,
the measured jitter of the PLL with the proposed LF at840 MHz was 7.0 ps (rms) and 74.4 ps (peak-to-peak)
for a 1.5-V supply. Table 1 summarizes the gate area ofthe MOS capacitor for the LF for different LFs shown inFig. 10. The area of the proposed LF is only 35% ( =0.5 × 0.70) of that of the conventional LF. It is 70% ofthat of a single-ended PLL. Therefore, by applying theBIGCAP to the LF, we can avoid an increase in PLL
area when changing from the single-ended design to thedifferential design.

5.

Conclusions

VCOBIGCAP(250pF)

CPDivider
100 µmFigure 11. Micrograph of the fabricated PLL withthe proposed loop filter shown in Fig. 10(b).

The proposed BIGCAP showed good linearity of ±2.9%, large capacitance of 6.7 fF/µm2, and as low as
1.9% relative parasitic capacitance without any additional fabrication processes on 0.13-µm standard CMOS
technology. The Q-value was 43 / (f (GHz) C (pF)) andcapacitance variation across a wafer was as small as σ =0.096%.
By applying BIGCAP to the loop filter of a differential PLL, we reduced the gate area of MOS capacitor forthe loop filter to only 35% of that of the conventional
design without changing the transfer function of the PLL.
BIGCAP is widely applicable to many other circuits
such as I/O buffers, switched-capacitor circuits, operational amplifiers, data converters, and mixers.

6.

Acknowledgements

We would like to thank M. Yamashina and S. Ohyafor their helpful suggestions.

7.

References[1] H. Samavati, A. Hajimiri, A. R. Shahani, G. N. Nasserbakht, and T. H. Lee, "Fractal capacitors," IEEE J. ofSolid-State Circuits, vol. 33, pp. 2035-2041, Dec. 1998.
[2] K. T. Christensen, "Design and characterization of verticalmesh capacitors in standard CMOS," Dig. of Symp. on
VLSI Circuits, pp. 201-204, June 2001.
[3] H. Djahanshahi and C. A. T. Salama, "Differential CMOS
circuits for 622-MHz/933-MHz clock and data recovery
applications,” IEEE J. of Solid-State Circuits, vol. 35, pp.
847-855, June 2000.

142

Figure 12. Measured jitter of the PLL with theproposed loop filter. The jitter at 840 MHz was
7.0 ps (rms) and 74.4 ps (p-p) for a 1.5-V supply.
Table 1. Summary of the gate area of MOS capacitor for the loop filter for the different loop filters shown in Fig. 10.

Gate area of MOS
capacitor for LF

Conventional LF
w/o BIGCAP
0.104 mm2
(100%)

Proposed LF
with BIGCAP
0.0373 mm2(35%)