1986

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 8, AUGUST 2013

Increase of Crosstalk Noise Due to Imbalanced
Threshold Voltage Between nMOS and pMOS in
Subthreshold Logic Circuits
Hiroshi Fuketa, Member, IEEE, Ryo Takahashi, Student Member, IEEE, Makoto Takamiya, Member, IEEE,
Masahiro Nomura, Member, IEEE, Hirofumi Shinohara, and Takayasu Sakurai, Fellow, IEEE

Abstract—An abnormal increase in crosstalk noise in subthreshold logic circuits is observed for the first time. When the) of nMOS and pMOS are imbalanced
threshold voltages (and the on-resistance of the aggressor driver is much lower thanthat of the victim driver, large crosstalk noise is observed, because the on-resistance has an exponential dependence onin the subthreshold region being different from normal voltage
operations. A simple crosstalk noise model is also proposed andverified with SPICE simulations. In a crosstalk noise test chipwith a 1.5-mm interconnect in 40-nm CMOS at a power supply) of 0.3 V, the measured noise amplitude increases
voltage (from 32% of
to 71% of, whenimbalance isrealized by tuning body bias in pMOS. This body bias tuning canbe used to mitigate the crosstalk problem in chip designs. For
noise induced by a rising edge, the noise becomes largest under
the slow-nMOS/fast-pMOS corner condition, while for noise
induced by a falling edge, the noise becomes largest under the
fast-nMOS/slow-pMOS corner condition, which is explained by
the proposed model.
Index Terms—Crosstalk, manufacturing variability, noise measurement, signal integrity, subthreshold circuit.

I. INTRODUCTIONSUBTHRESHOLD circuits, which operate at a supply) lower than threshold voltage (), arevoltage (one of the promising solutions to achieve ultra-low power
operation [1]. The delay of subthreshold circuits, however,variation, since transistor
shows large variations due tocurrent in the subthreshold region shows an exponential de. Therefore, many researchers have focused
pendence on
on investigating circuit techniques to cope with such a large
delay variation [2], [3]. In contrast, there are few reports oncrosstalk noise in subthreshold circuits [4], although many papers have been published on crosstalk noise in above-thresholdcircuits [5]–[7]. In these works, the dependence of crosstalk
Manuscript received November 29, 2012; revised February 14, 2013; accepted March 21, 2013. Date of publication May 13, 2013; date of current version July 19, 2013. This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy, Trade and Industry(METI) and the New Energy and Industrial Technology Development Organization (NEDO). This paper was approved by Guest Editor Ken Suyama.
H. Fuketa and R. Takahashi are with the Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan (e-mail: fuketa@iis.u-tokyo.ac.jp).
M. Takamiya is with the VLSI Design and Education Center, Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan.
M. Nomura and H. Shinohara are with the Semiconductor Technology Academic Research Center (STARC), Kanagawa 222-0033, Japan.
T. Sakurai is with the Institute of Industrial Science, University of Tokyo,
Tokyo 153-8505, Japan.
Digital Object Identifier 10.1109/JSSC.2013.2258831

noise onhas not been clarified. If the crosstalk noisein subthreshold circuits is larger than the crosstalk noise inabove-threshold circuits, a new sign-off condition for crosstalkcheck should be developed.
Therefore, in this paper, interline-coupled crosstalk noise insubthreshold circuits is measured in a 40-nm CMOS test chip.
In addition, a new crosstalk noise model is proposed and verified with SPICE simulations. An abnormal increase in crosstalknoise in the subthreshold operation is observed for the first time.
This abnormal noise is caused by the pMOS/nMOS strength imbalance. The major cause of such imbalance in the subthresholdand nMOS.
region is the difference between pMOS
imbalance mainly comes from within-die
variThisvariation. The within-die variation
ation and/or die-to-die
can be reduced by employing wider MOSFET’s but die-to-die
variation is difficult to reduce by a designers’ practice otherthan making use of adaptive body biasing. It should be notedbalance is perfect in the above-thresholdthat although theimbalance may develop in the subvoltage region, thethreshold region by the imbalance of the drain induced barrier
lowering (DIBL) effect between pMOS and nMOS. As such,cares must be taken for the abnormal crosstalk noise increase in
the subthreshold region.
The preliminary work of this paper is presented in [8]. The
contributions of this paper beyond the preliminary work are as
follows: 1) rising crosstalk noise is investigated with measurements and simulations in addition to falling noise, 2) the detailed
derivation of the crosstalk noise model proposed in this paper
is explained and the accuracy of the model is discussed, 3) the
accuracy of the noise peak detector, which is a circuit block formeasuring the peak voltage of crosstalk noise in the test chip, is
explained, and 4) an impact of crosstalk noise on signal delays
is investigated.
This paper is organized as follows. Section II describes thesilicon measurements of crosstalk noise and shows its dependifference. To investigate the dependence, adence on the
new crosstalk noise model for subthreshold circuits is proposed
in Section III. An impact of crosstalk noise on signal delays isevaluated in Section IV. Finally, Section V concludes this paper.
II. MEASUREMENT OF CROSSTALK NOISE
A. Test Chip Design
andTo measure the dependence of crosstalk noise ons of nMOS and pMOS, a crosstalk noise test chip is designed and fabricated in a 40-nm CMOS. Fig. 1 shows a circuit
diagram for measuring the peak noise voltage induced by

0018-9200/$31.00 © 2013 IEEE

FUKETA et al.: IMBALANCED THRESHOLD VOLTAGE BETWEEN nMOS AND pMOS IN SUBTHRESHOLD LOGIC CIRCUITS

1987

Fig. 1. Circuit diagram of crosstalk noise measurement circuit.

crosstalk. In this paper, rising and falling crosstalk noises aredefined as the noises induced by a rising edge and a fallingedge, respectively, as shown in Fig. 1. The measurement
circuit consists of a noise test circuit (NTC), which includes
1.5-mm coupled wire lines, and a noise peak detector (NPD).
A long (1.5 mm) wire is used in the measurement, because theresistance of the wire is much smaller than that of the driverin the subthreshold region, and hence many repeaters are notrequired. Crosstalk noise is measured over a wide range ofsupply voltages of the NTC (). In this measurement
circuit, rising and falling crosstalk noises can be measured. The
rising crosstalk noise is induced by asserting the inputs of theaggressor line drivers () while the input of the victim line
driver () is kept to be the ground. In contrast, the fallingcrosstalk noise is caused by negating the inputs of the aggressorline drivers () while the input of the victim line driver() is kept to be. In addition, the body-bias
voltage of the wire line drivers can be controlled to investigate
the dependence of thedifference between nMOS andpMOS on crosstalk noise.
Fig. 2 shows a schematic of the NPD, which detects the peakvoltage of crosstalk noise. The Schmitt trigger buffer converts
a noise that exceeds the logical threshold voltage of the buffer(or) to a pulse.
andare used for detecting the peak voltages of risingand falling noises, respectively. A rising crosstalk noise thatexceeds
is converted to a rising pulse and thepulse is captured by the NOR RS latch. Consequently, theoutput of the latch () becomes high. On the other
hand, a falling crosstalk noise that dips below
is converted to a falling pulse and the pulse is captured by
the NAND RS latch. Then, the output of the latch ()
becomes high. The Schmitt trigger buffer is used to widen thepulse. Reset_R and Reset_F signals in Fig. 2 reset the latches.
The voltage difference between the supply voltage ()
and the ground () of the NPD is fixed to 1.1 V
regardless of
.
and
are
varied by changing bothand. As shownin Fig. 3, falling noise peak voltage () is measured by
the following procedure:1)
andare set to low voltages;

Fig. 2. Schematic of noise peak detector (NPD) in measurement circuit shownin Fig. 1.

2) a falling transition signal is given to aggressor lines, whilethe victim line is kept high;3) if the output of the latch () becomes high,–is the peak noise voltage(). On the other hand, if
remains low, we
increaseandto raise.
Then, steps 2 and 3 are repeated until the noise is detected.
The peak voltage of the rising noise can be measured in a similarmanner.
andmust be calibrated to measure, because they are fluctuated due to die-to-die variations. Fig. 4 shows the calibration flow of. During
the calibration, no crosstalk noise is generated. Therefore, theexact
is measured by sweeping bothand, becauseis equal toatthe rising edge of.
is calibrated in a similar manner.

1988IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 8, AUGUST 2013

Fig. 5. Simulated relative errors between actual crosstalk noise voltage andnoise voltage detected by NPD (Fig. 2).

Fig. 3. Timing chart for detecting peak voltage of falling crosstalk noise. Risingnoise can also be measured by a similar mechanism.

Fig. 6. Cross section of coupled wire lines in NTC.

Fig. 7. Chip micrograph in 40-nm CMOS.

B. Measurement Results
Fig. 4. Calibration flow fora similar manner.

.

can be calibrated in

The noises occurring in the subthreshold region are slow, andhence they can be easily measured with the NPD. However,
it is difficult to accurately measure the peak voltages of fastand sharp noises that often occur in the nominal supply voltage
region. Fig. 5 shows the simulated relative error between theactual crosstalk noise voltage and the noise voltage detectedby the NPD. The relative error is less than 4% below 0.5 V,
whereas it is around 10% above 0.7 V. Such error in the nominal supply voltage region is not critical, since the dependenceof crosstalk noise on the supply voltage is investigated and especially crosstalk noise in the subthreshold region is focused onin this work.
Fig. 6 shows the cross section of the coupled wire lines in
NTC. The orthogonal lines (M2-5 and M7) are inserted asdummy metals. The output resistances of the drivers are around160
at. The chip micrograph is shown in
Fig. 7. The measurement circuit was fabricated in a 40-nm
CMOS process with seven metal layers.

Fig. 8(a) and (b) show the measured and simulated peakvoltages of the rising and falling crosstalk noises as functionsof the supply voltage, respectively. The SPICE simulations are
conducted with the parasitic wire resistance and capacitance
extracted from the layout data.
used in the simulations
is based on the measured single transistors provided by thefoundry. The simulation results agree with the measurement
results. Fig. 8 indicates thatsharply decreases as
is reduced for the rising crosstalk noise,whileslightly decreases for the fallingcrosstalk noise. Details of these dependences will be discussed
in Section III.
In order to examine how thedifference between nMOS
and pMOS affects peak noise voltage, the dependence of peaknoise voltage on the body-bias voltage of the victim driver ismeasured. The measurement results are illustrated in Fig. 9.
The body-bias voltages of the aggressor line drivers do notchange. As body-bias voltage of n-well of the victim line driver(–) increases,of pMOS of the victim line
driver decreases, which enlarges thedifference between
pMOS and nMOS. Fig. 9 shows that the peak noise voltage at

FUKETA et al.: IMBALANCED THRESHOLD VOLTAGE BETWEEN nMOS AND pMOS IN SUBTHRESHOLD LOGIC CIRCUITS

1989

III. MODELING OF CROSSTALK NOISE INSUBTHRESHOLD REGION
A. Crosstalk Noise in Coupled Wire Lines With One Aggressor
First, crosstalk noise by one aggressor line is investigated forsimplicity. Fig. 10 illustrates the equivalent circuit of the coupled wire lines with one aggressor and one victim, where
denotes the wire capacitance andrepresents the coupling capacitance between the aggressor and the victim.
In this paper,
(
) and
(
) are the equivalent
resistances of nMOS (pMOS), and the definition for nMOS is
explained in Fig. 11.
andare pentode resistances (onresistances) given by
(1)
where
is the drain-source current of nMOS (pMOS),
which is a function of drain voltage () and gate voltage().
andare triode resistances defined as(2)

Fig. 8. Measured and simulated peak voltages () as functions of supply). (a) Rising noise. (b) Falling noise.
voltage of NTC (Fig. 9. Measured and simulated dependences of peak noise voltage ()
on the n-well body-bias voltage of victim driver. Noise peak voltage is signifibalance in subthreshold circuits.
cantly sensitive to thea nominal supply voltage of 1.1 V hardly depend on the n-wellbody-bias voltage of the victim driver, whereas the peak noisevoltage atof 0.3 V significantly increases as reverse
body-bias becomes large. Noise amplitude increases from 32%
ofto 71% of, when theimbalance is realizedby tuning the body bias in pMOS. This indicates that peak noisevoltage is extremely sensitive to the balance ofbetweennMOS and pMOS in subthreshold circuits. The reason why
the balance ofsignificantly affects peak noise voltage isdiscussed in the next section.

For the rising noise, the drain-source voltage of pMOS of theat first, and hence
defined inaggressor line driver is(1) is used as the equivalent resistance of pMOS. In contrast, thevictim line is pulled down by nMOS of the victim line driverand the drain-source voltage of the nMOS is less than.
In this paper, the critical peak noise voltage is assumed to be
half. Therefore,
defined in (2) that is the resistanceat, which is an intermediate voltage between
half
and the ground, is used as the equivalent resistanceof nMOS of the victim line driver for the rising noise. For thefalling noise,is used as the equivalent resistance of nMOS
of the aggressor line driver andis used as the equivalent
resistance of pMOS of the victim line driver.
In the nominal supply voltage region, the equivalent resistances of the wire line drivers (
,
,
, and
) are sosmall that the wire resistance () must be taken into consideration, as shown in Fig. 10(a). On the other hand,
can beignored in the subthreshold region, since
,
,
, and
are much larger than
. Therefore, the equivalent circuitin the subthreshold region can be easily analyzed as illustrated
in Fig. 10(b).
Letbe the voltage of the victim wire line. When the
input of the aggressor line driver is asserted at, as shownin the upper panel of Fig. 10(b), the rising noise is induced on
the victim line, and in this case,is expressed as

(3)
where
.
and
(
solutions to the following quadratic equation) are the

(4)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 8, AUGUST 2013

Fig. 10. Equivalent circuit of coupled wire lines with one aggressor and one victim. (a) Nominal supply voltage region (conventional). (b) Subthreshold voltage
region (this work).

Consequently, peak noise voltage (is expressed as) for the rising noise(7)

Fig. 11. Definition of equivalent resistance of nMOS.

where.
is defined as the time when thenoise voltage becomes maximum peak and is given by

for the falling noise can be derived in the samemanner. When the input of the aggressor line driver is negatedat, as shown in the lower panel of Fig. 10(b),isexpressed as(5)
Therefore,

is derived as
(6)

(8)

FUKETA et al.: IMBALANCED THRESHOLD VOLTAGE BETWEEN nMOS AND pMOS IN SUBTHRESHOLD LOGIC CIRCUITS

1991

Fig. 13. Equivalent circuit of coupled wire lines with two aggressors and one
victim. This circuit can be converted to a circuit with one aggressor.

Fig. 12. Peak noise voltage (proximated value (with one aggressor.

) obtained using (7) and (10) and its ap) calculated using (11) for coupled wire line
is a good approximation of
.

where
and
(
following quadratic equation) are the solutions to the
(9)

where
derived as. Thus,shown. When the wire capacitances of the victim and aggressors
are identical (), the voltage of the victim
line () is given by

(12)
where
.
and
(
solutions to the following quadratic equation

for the falling noise is) are the(13)

. Thus, peak noise voltage (
) in
where
coupled wire lines with two aggressors for the rising noise isderived as(10)Equations (7) and (10) are too complicated to discuss thedependence on. A simple expression of a boundof
has been derived in [9]. In this paper, a modification
to the expression is introduced for more accurate approximationof.
for the rising noise given by (7) is approximated as
(11)

(14)
and
are used instead ofand
For the falling noise,in (14), respectively, whereandare the solutions to
the following quadratic equation(15)

For the falling noise, is used instead of .
Fig. 12 showsandto discuss the accuracy of the approximation model. This figure indicates that the
proposed model is a good approximation of. The relative error () is less than 3.2%
under the conditions of,and.
Using the expression described in [9], the relative error is lessthan 8.5%, and hence the proposed expression in (11) is a better
approximation of. When the lines are partially coupled,for example, the coupling capacitance ( ) decreases. In thiscase,is reduced, because
decreases, as
indicated by (11).
B. Crosstalk Noise in Coupled Wire Lines With Two Aggressors
Crosstalk noise in coupled wire lines with two aggressors canbe derived in the same manner. The equivalent circuit in thesubthreshold region is depicted in Fig. 13. The equivalent circuitwith two aggressors is converted to that with one aggressor, as.
where
Also for the crosstalk noise with two aggressors,
given by (14) can be approximated as(16)
For the falling noise, is used instead of .
Fig. 14 showsand. The relative error() is less than 4.5% under theconditions of,and.
If the wire capacitances of the victim and aggressors are different, a slight modification of (16) is required. For example,
when the wire capacitance of the aggressor is two times larger
than that of the victim (),
can be approximated using a power of 1.5 instead of 1.3 in (16). In thiscase, the relative error is less than 5.8% under the conditions of
,
and
.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 8, AUGUST 2013

Fig. 14. Peak noise voltage () obtained using (14) and its approximated) calculated using (16) for coupled wire line with twovalue (
aggressors.

C. Dependence of Peak Noise Voltage on

Imbalance

According to [10], in the subthreshold region,and (2) is given byin (1)(17)
where is the subthreshold slope parameter, is the DIBL coefficient,is the thermal voltage,isof nMOS,andis the technology-dependent parameter.
From (1), (2), and (17), and can be expressed as
(18)
(19)
where
is
of pMOS. These equations indicate thatand have exponential dependences on the
difference between nMOS and pMOS. According to (11) and (16), peak noisevoltage () depends on and , and is enlarged by increases in and . Thus, peak noise voltage is strongly affectedby thedifference between nMOS and pMOS. is maximized at the SF (slow-nMOS/fast-pMOS) process corner, while
is maximized at the FS (fast-nMOS/slow-pMOS) process
corner. Therefore, crosstalk noise is especially crucial at process
corners, such as the SF corner for the rising noise and the FS
corner for the falling noise.
Fig. 15(a) and (b) show the simulated peak noise voltage
on the 1.5-mm coupled wire line with one victim and two aggressors under a typical process condition (TT) and the cornerconditions (SF and FS) for the rising noise and falling noise,respectively.
at 0.3 V is 1.1 times larger thanat 1.1 V for the rising noise under the SF cornercondition and 1.4 times larger for the falling noise under the FS
corner condition. The approximated peak noise ()
calculated using (16) is also shown, and it agrees with the simulation results. The measured
dependences shown in
Fig. 8 are different from thedependences obtained by

Fig. 15. Peak voltage of crosstalk noise on 1.5-mm coupled wire line with two
is obtained
aggressors and one victim at TT, FS, and SF process corners.
is calculated using the proposed apby SPICE simulations andproximation model equation. (a) Rising noise. (b) Falling noise.

simulations shown in Fig. 15 because thebalance of themeasured chip is between TT and SF.
As shown in Fig. 15, crosstalk noise in the nominal supply
voltage region hardly depends on thebalance. This is because 1) the dependence of the equivalent resistances of thedrivers on
is much smaller than that in the subthresholdregion, and 2) the influence of wire resistances is not ignored.
In contrast, peak noise voltage in the subthreshold region ismuch more sensitive to thebalance. This is because peaknoise voltage depends on equivalent resistance ratios ( and), which have an exponential dependence on the
difference between nMOS and pMOS, as indicated in (18) and (19).
Therefore, designers must consider the process corners, such as
the SF and FS corner conditions, as the worst-case conditions
for signal integrity in subthreshold circuits.
IV. DELAY DEGRADATION DUE TO CROSSTALK NOISE INSUBTHRESHOLD REGION
In this section, an impact of crosstalk noise on signal delays isinvestigated. For analyzing the peak voltage of crosstalk noise(), the input signal of the victim line driver is fixed to
the ground or
as shown in Fig. 10. In contrast, the victim
line is also driven for analyzing the influence of crosstalk noise
on delays as shown in Fig. 16(a), and the signal delay on thevictim line is evaluated. Fig. 16(b) illustrates a timing chartwhen the falling transition signal is input to the aggressor line
driver () (crosstalk noise is induced) oris kept

FUKETA et al.: IMBALANCED THRESHOLD VOLTAGE BETWEEN nMOS AND pMOS IN SUBTHRESHOLD LOGIC CIRCUITS

1993

1.0 and 0.3 V. The delay increase is derived by dividing the
maximum delay increase, which is induced by crosstalk noise,by the delay without crosstalk noise. The delay increase at
is much more sensitive to process variations thanthat at. The delay increase of the rising transitionis largest under the FS corner condition and smallest under the
SF corner condition, since the falling crosstalk noise is largest
under the FS corner condition and smallest under the SF cornercondition as shown in Fig. 15(b). On the other hand, the delay
increase of the falling transition is largest under the SF cornercondition and smallest under the FS corner condition. Thismeans
imbalance causes the large delay increase in thesubthreshold region.
V. CONCLUSIONS

Fig. 16. (a) Circuit diagram for evaluating signal delays and (b) timing chart.

In this paper, the dependence of the peak noise voltage
induced by crosstalk on the
difference between nMOS
and pMOS in subthreshold circuits was presented. The large
crosstalk noise due to theimbalance was measured in thetest chip with 1.5-mm coupled wires fabricated by a 40-nm
CMOS process. A new crosstalk noise model was proposed andverified with SPICE simulations. The proposed model indicatesthat peak noise voltage is significantly sensitive to thedifference. Simulation results show that the rising crosstalknoise is largest under the SF corner condition, while the fallingnoise is largest under the FS corner condition. In the worst-case
FS corner simulation, noise amplitude increased by 1.4 times
when
was reduced from 1.1 to 0.3 V. These results wereexplained by the proposed model. In addition, the impact ofcrosstalk noise on signal delays was investigated. Simulation
results show that the delay increase due to crosstalk noise at
is much more sensitive to process variations
andimbalance causes the large
than that atdelay increase in the subthreshold region.
REFERENCES

Fig. 17. Simulated maximum delay increase due to crosstalk noise 1.5-mm
coupled wire line with two aggressors and one victim under TT and process
corners. (a) Delay increase of rising transition. (b) Delay increase of fallingtransition.

(crosstalk noise is not induced). The rising transition delayon the victim line increases due to the crosstalk noise. For evaluating the falling transition delay, the rising transition signal is
input to. The falling transition delay also increases dueto the crosstalk noise.
Fig. 17 shows the simulated maximum delay increase on the
1.5-mm coupled wire line with one victim and two aggressors
under TT and process corners (FS, SF, SS, FF) whenis[1] A. Wang, B. Calhoun, and A. Chandrakasan, Sub-Threshold Design for
Ultra Low-Power Systems. New York, NY, USA: Springer, 2006.
[2] K. Hirairi, Y. Okuma, H. Fuketa, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, “13% power reduction in 16 b
integer unit in 40 nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully
integrated digital LDO,” in Int. Solid-State Circuits Conf. Dig. Tech.
Papers, 2012, pp. 486–487.
[3] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, “Adaptive
performance compensation with in-situ timing error prediction for subthreshold circuits,” in Proc. Custom Integr. Circuits Conf. (CICC),
2009, pp. 215–218.
[4] M. Nanua and D. Blaauw, “Investigating crosstalk in sub-threshold circuits,” in Proc. Int. Symp. Quality Electron. Des. (ISQED), 2007, pp.
539–646.
[5] T. Sakurai, “Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs,” IEEE Trans. Electron Dev., vol. 40, no.
1, pp. 118–124, Jan. 1993.
[6] S.-C. Wong, G.-Y. Lee, and D.-J. Ma, “Modeling of interconnect
capacitance, delay, and crosstalk in VLSI,” IEEE Trans. Semicond.
Manuf., vol. 13, no. 1, pp. 108–111, Feb. 2000.
[7] T. Sato, D. Sylvester, Y. Cao, and C. Hu, “Accurate in situ measurement of peak noise and delay change induced by interconnect coupling,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1587–1591,
Oct. 2001.
[8] H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and
T. Sakurai, “Increase of crosstalk noise due to imbalanced thresholdvoltage between NMOS and PMOS in sub-threshold logic circuits,” inProc. Custom Integr. Circuits Conf. (CICC), 2012, pp. 1–4.

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[9] A. Vittal and M. Marek-Sadowska, “Crosstalk reduction for VLSI,”IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 16, no. 3,
pp. 290–298, Mar. 1997.
[10] M. Alioto, “Understanding DC behavior of subthreshold CMOS logic
through closed-form analysis,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1597–1607, Jul. 2010.
Hiroshi Fuketa (S’07–M’10) received the B.E.
degree from Kyoto University, Kyoto, Japan, in
2002 and the M.E. and Ph.D. degrees in information
systems engineering from Osaka University, Osaka,
Japan, in 2008 and 2010, respectively.
He is currently a Research Associate with Institute of Industrial Science, the University ofTokyo, Tokyo, Japan. His research interests include ultra-low-power circuit design and variation
modeling.
Dr. Fuketa is a member of IEICE and IPSJ.

Ryo Takahashi (S’12) received the B.Eng. degree inelectrical engineering from Tokyo Institute of Technology, Tokyo, Japan, in 2009, and the M.S.E.E. degree from the University of Tokyo, Tokyo, Japan, in
2011. He is currently working toward the Ph.D. inelectrical engineering at the University of Tokyo.
His research is focused on the design of
low-voltage low-power circuits.

Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995, 1997,
and 2000, respectively.
In 2000, he joined NEC Corporation, Japan,
where he was engaged in the circuit design of highspeed digital LSI’s. In 2005, he joined Universityof Tokyo, Japan, where he is an Associate Professor
of VLSI Design and Education Center. His researchinterests include the circuit design of the low-power
RF circuits, the ultra low-voltage logic circuits, thelow-voltage DC-DC converters, and the large area electronics with organic
transistors.
Dr. Takamiya is a member of the technical program committee for the IEEE
Symposium on VLSI Circuits. He received the 2009 and 2010 IEEE Paul Rappaport Awards.

Masahiro Nomura (M’96) received the B.E. and
M.E. degrees in electrical engineering and the
Ph.D. degree in information sciences from Tohoku
University, Sendai, Japan, in 1989, 1991, and 2007,
respectively.
He joined NEC Corporation, Sagamihara, Japan,
in 1991. He was initially engaged in the researchand development of high-speed video signal processors, high-speed microprocessors, and low-power
multiprocessors. He transferred to NEC Electronics
Corporation and Renesas Electronics Corporationin 2008 and 2010, respectively, and has been a Senior Researcher at the LSI
Research Laboratory, Renesas Electronics Corporation, Kawasaki, Japan. Since
2009, he has been concurrently serving as a Manager of logic design at the
Semiconductor Technology Academic Research Center. His current researchinterests include low-power, high-speed circuit techniques and reconfigurable
circuit techniques.
Dr. Nomura is a member of the Institute of Electronics, Information, andCommunication Engineers (IEICE) of Japan and the IEEE Solid-State Circuits
Society. He served as a technical program committee member of the A-SSCC
in 2005, 2006, 2007, 2008, and 2009, and the Symposium on VLSI Circuits in2009 and 2010.

Hirofumi Shinohara received the B.S. and M.S. degrees in electrical engineering and the Ph.D. degree
in informatics from Kyoto University, in 1976, 1978,
and 2008, respectively.
In 1978, he joined the LSI Laboratory of Mitsubishi. Electric Corporation, where he was involved
in research and development of MOS SRAMs,
embedded memory compilers and logic blocks.
From 2003 to 2009 he was a Manager of basic logic
and memory circuits development department inRenesas Technology Corporation. In 2009 he moved
to STARC, where he has been managing a joint research project on extremely
low power circuits and systems with universities in Japan. His research interests
include advanced SRAM, low-power circuits, and variation-aware design.
Dr. Shinohara is a member of IEICE.

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan, in 1981.
In 1981 he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and SoC Solutions. He has worked extensively
on interconnect delay and capacitance modelingknown as Sakurai model and alpha power-law MOS
model. From 1988 through 1990, he was a visiting
Researcher at the University of California Berkeley,
where he conducted research in the field of VLSICAD. From 1996, he has been a Professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic IC’s and large-area electronics. He has published morethan 400 technical publications including 100 invited presentations and several
books and filed more than 200 patents.
He is a Fellow of STARC and IEICE. He gave keynote speech at more than
50 conferences including ISSCC, ESSCIRC, and ISLPED. He was an elected
AdCom member for the IEEE Solid-State Circuits Society and an IEEE CAS
and SSCS Distinguished Lecturer. He is an executive committee Chair for the
VLSI Symposia and a steering committee Chair for the IEEE A-SSCC since2010. He served as a conference Chair for the Symposium on VLSI Circuits,
and ICICDT, a Vice Chair for ASPDAC, a TPC Chair for the A-SSCC, and VLSI
Symposium, an executive committee member for ISLPED, and a program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED,
and other international conferences. He is a recipient of the 2010 IEEE Donald
O. Pederson Award in Solid-State Circuits, the 2009 and 2010 IEEE Paul Rappaport Awards, the 2010 IEICE Electronics Society Award, the 2009 Achievement
Award of IEICE, the 2005 IEEE ICICDT Award, the 2004 IEEE Takuo SuganoAward, the 2005 P&I patent of the year award, and four product awards.