IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 1, JANUARY 2013255

Insole Pedometer With Piezoelectric Energy
Harvester and 2 V Organic Circuits
Koichi Ishida, Member, IEEE, Tsung-Ching Huang, Member, IEEE, Kentaro Honda, Yasuhiro Shinozuka,
Hiroshi Fuketa, Member, IEEE, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Member, IEEE,
Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Member, IEEE, Makoto Takamiya, Member, IEEE,
Takao Someya, Member, IEEE, and Takayasu Sakurai, Fellow, IEEE

Abstract—A shoe insole pedometer, which consists of a piezoelectric energy harvester and a 2 V organic pedometer circuit, hasbeen developed as a first step toward the application of flexible
large-area energy harvesting. A pseudo-CMOS 14 bit step counterrecords the number of steps up to 16383 steps using the harvested
power. To increase the noise margin of the pseudo-CMOS logic circuits, a negative voltage is generated by an organic charge pump
circuit and is applied to the pseudo-CMOS inverters and transmission gates in the flip-flops in the step counter. A pseudo-CMOS
Schmitt trigger inverter used to feed clean square pulses to the step
counter is presented. This paper describes the details of the insole
pedometer and provides measurement results and some discussion.
Index Terms—Charge pump, energy harvesting, organic largearea electronics, piezoelectric film, pseudo-CMOS, PVDF.

I. INTRODUCTIONE

NERGY harvesting is an enabling technology for realizing
an ambient power supply for wireless sensor nodes and mobile devices. Using flexible photovoltaic cells and piezoelectricfilms, we can readily harvest ambient energy if flexible energy
harvesters can be realized. This type of integration will broaden
the range of applications of flexible, large-area electronics.
Conventional silicon circuits, however, are not the best candidates for realizing flexible large-area energy harvesters beManuscript received May 05, 2012; revised June 10, 2012; accepted August24, 2012. Date of current version December 31, 2012.This paper was approved
by Guest Editor Uming Ko. This work was supported in part by JST/ERATO
and Special Coordination Funds for Promoting and Technology.
K. Ishida was with the Institute of Industrial Science, University of Tokyo,
Tokyo 153-8505, Japan, and is now with Dresden University of Technology,
01069 Dresden, Germany (e-mail: koichi.ishida@tu-dresden.de).
T.-C. Huang was with the Institute of Industrial Science, University of Tokyo,
Tokyo 153-8505, Japan, and is now with TSMC North America, San Jose, CA
95134 USA.
K. Honda was with the Institute of Industrial Science, University of Tokyo,
Tokyo 153-8505, Japan, and is now with NTT Microsystem Integration Laboratories, Atsugi 243-0198, Japan.
Y. Shinozuka, H. Fuketa, and T. Sakurai are with the Institute of Industrial
Science, University of Tokyo, Tokyo 153-8505, Japan.
T. Yokota, T. Sekitani, and T. Someya are with the Department of ElectricalEngineering and Information Systems, School of Engineering, University ofTokyo, Tokyo 113-8654, Japan.
U. Zschieschang and H. Klauk are with Max Planck Institute for Solid State
Research, 70569 Stuttgart, Germany.
G. Tortissier was with the Research Center for Advanced Science and Technology, University of Tokyo, Tokyo 153-8904, Japan, and is now with the Nikon
and Essilor International Joint Research Center, Kawasaki 213-0012, Japan.
H. Toshiyoshi is with the Research Center for Advanced Science and Technology, University of Tokyo, Tokyo 153-8904, Japan.
M. Takamiya is with the VLSI Design and Education Center, University ofTokyo, Tokyo 153-8505, Japan.
Digital Object Identifier 10.1109/JSSC.2012.2221253

cause they are mechanically hard, and therefore difficult to fit
to curved surfaces such as shoes. In energy-harvesting applications, the harvested power is small and the voltage is low (e.g., 2V) owing to the limited capability of harvesters. Organic circuits
typically consume less power, since their operation speed is low.
In addition, self-aligned monolayer (SAM) technology [1] realizing 2 V operation is available. Organic circuits are therefore
suitable for energy-harvesting applications.
The stable pMOS semiconductor material DNTT [2] canbe used in organic circuits. However, the mobility of organicnMOS transistors is almost one order of magnitude smaller
than that of pMOS transistors in our current technology. In
organic circuit design, all-pMOS circuits are often used. A
pseudo-CMOS inverter, one of the all-pMOS circuits, hasbeen proposed [3]. The output transistors in the pseudo-CMOS
inverter operate complementarily. The pseudo-CMOS inverter,
therefore, has high gain, but it requires a negative voltage bias.
The operation of all-pMOS circuits without a negative voltage
bias is not robust, and the noise margin is small because of theirrationed-logic nature. Thus, the main challenge in the design oforganic circuits for piezoelectric energy harvesting is the robust
operation (e.g., the signal integrity in counters) of all-pMOS
circuits at a low supply voltage.
To address this challenge, we have proposed an organic insole pedometer with a piezoelectric energy harvester as the firststep toward ambient energy harvesting using organic electronics[4]. To increase the noise margin of all-pMOS logic circuits
based on pseudo-CMOS inverters, a negative voltage is generated by an organic charge pump circuit and applied as the biasof pseudo-CMOS inverters. A pseudo-CMOS Schmitt trigger
inverter used to feed clean square pulses to the logic circuits
is also proposed. This paper describes the details of the insole
pedometer and provides measurement results and some discussion. In Section II, we give an overview of the proposed insole
pedometer. In Section III, we give a detailed description of thecircuit design. In Section IV, we present the experimental results
and discussion. Finally, conclusions are given in Section V.
II. OVERVIEW OF INSOLE PEDOMETER
Fig. 1 shows an outline of the proposed insole pedometer. A
polyvinylidene difluoride (PVDF) sheet is used as a piezoelectric energy harvester. Since the output current of the harvesteris proportional to its area, the sheet is cut into small pieces androlled to increase the total area. One of the PVDF rolls is used forpulse generation to detect steps. Each time the insole is pressedby the foot during walking, the PVDF roll generates a pulse. The

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Fig. 3. Block diagram of the insole pedometer.

Fig. 1. Outline of the proposed insole pedometer.

Fig. 4. Device structure of the 2 V organic pMOS transistor.

Fig. 2. Photograph of the prototype insole pedometer.

remaining PVDF rolls are used in the power supply for the organic circuits. The organic circuits are implemented with a 2 V
pMOS process and are located under the array of PVDF rolls toshape the detected pulses into clean square waves and count the
number of steps.
Fig. 2 shows a photograph of the prototype insole pedometer,
including the piezoelectric energy harvester and 2 V organic circuits. Twenty-one PVDF rolls are embedded on the plastic baseboard. To show the organic circuits under the rolls, two rectangular areas have been cut out. The 2 V organic circuits are implemented separately and connected to each other by a flexible
PCB. The total length of the pedometer is 22 cm.
A block diagram of the insole pedometer is shown in Fig. 3.
The system consists of four circuit blocks. An all-pMOS
full-wave rectifier supplies a voltage
of approximately
2 V to all circuit blocks. The output current is approximately 10. The pulse-shaping circuit, which consists ofa pseudo-CMOS Schmitt trigger inverter, shapes the pulses
obtained by the PVDF roll into clean square waves and feeds
them to both the all-pMOS negative voltage generator and a
14 bit pseudo-CMOS step counter with gate-boosted pMOS
switches. The pseudo-CMOS 14 bit step counter records thenumber of steps up to 16383 steps using the harvested power.
To increase the noise margin of the pseudo-CMOS logic

Fig. 5. Schematic of the all-PMOS full-wave rectifier.

circuits, the all-pMOS negative voltage generator provides a
voltage(e.g.,) to the pseudo-CMOS inverters andtransmission gates in the flip-flops in the step counter. The
circuit design of each building block is discussed in Section III.
In this work, we use an organic pMOS process with SAM
technology and the semiconductor material DNTT as shown in
Fig. 4. SAM technology enables a total gate oxide thickness of
6 nm and 2 V operation. DNTT is a stable material with a highmobility of 1.0. The minimum gate length is 20
inthe negative voltage generator and 50
in other circuit blocks.
III. CIRCUIT DESIGN
A. All-pMOS Full-Wave RectifierFig. 5 shows a schematic of the all-pMOS full-wave rectifier,which was presented in our previous work [5]. In the left branch,

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257

Fig. 6. Schematic of the proposed all-PMOS negative voltage generator.

diode-connected pMOS transistors (M1, M2) are used. On theother hand, the right branch consists of a pair of cross-coupledpMOS transistors (M3, M4) to increase the output current [5].
The maximum target output voltage is 2 V with a maximum
output current of 10, while the rectifier in [5] supplies a 20 V,
2 mA output. Their gate width and length are 7200
and50
, respectively. Although the minimum gate length of 20
is better for obtaining high driving capability, a gate lengthof 50
instead of 20
is chosen here in consideration of
the process yield.
B. All-pMOS Negative Voltage Generator
An organic Dickson-type DC to DC converter was presented
in [6]. The converter in [6] handles an output current of 10 nA,
while our negative voltage generator provides 10. Furthermore, our voltage generator must operate at a low frequency(e.g., from 1 to 10 Hz). We, therefore employ 470 nF MIM capacitors for the charge pump circuit. To switch these large capacitors with a high on/off ratio, a high-gain pseudo-CMOS inverter and two diode-connected depletion pMOS transistors areused as shown in Fig. 6.
To charge/discharge the left capacitor (C1), the output bufferof the pseudo-CMOS inverter consists of transistors with widthsof 2 mm () and 6 mm (). The performance of the negative voltage generator strongly depends on
the threshold voltage of the pMOS diode-connected transistors.
To reduce the reverse leakage current, the gate width of each
diode-connected transistor is smaller () than that of
the inverter. These parameters are carefully determined througha SPICE simulation.
C. Pulse-Shaping Circuit (Pseudo-CMOS Schmitt Trigger
Inverter)
To generate clean square waves from the noisy input pulses
obtained by the PVDF energy harvester, a Schmitt trigger inverter is required as shown in Fig. 7. Here, a Schmitt trigger inverter based on pseudo-CMOS logic is proposed. Fig. 8 showsa schematic of the proposed Schmitt trigger inverter and its
DC output characteristics obtained by SPICE simulation. Unlike conventional CMOS Schmitt trigger inverters, which canuse both pMOS and nMOS transistors to generate hysteresis, inthe proposed pseudo-CMOS Schmitt trigger inverter, the first

Fig. 7. Schematic of the pulse-shaping circuit.

stage is used to adjust the lower-bound () of the hysteresis, while the second stage is used to adjust the upper-bound().
When the input signal is swept from low to high, the top
pMOS transistor of the second stage (M1), which is controlled
by the third-stage pseudo-CMOS inverter output (A), pulls up
the voltage of node (B), and therefore moves the high-to-low
switching point to the right, as can be seen in Fig. 8(c). The
upper-bound transition point is determined by the ratio of M1
to M2. On the other hand, when the input is swept from highto low, the ground-connected pMOS transistor (M3) of the firststage weakens the pull-up force of the top two pMOS transistors (M4, M5), which forces the low-to-high switching point tomove to the left and widens the hysteresis, as shown in Fig. 8(c).
The lower-bound transition point is determined by the ratio of
M3 to M6.

D. 14 bit Pseudo-CMOS Step CounterTo count the number of steps taken while walking, we designed a pseudo-CMOS binary counter. The counter employs
gate-boosted pMOS switches (M1-M4), while our previous
counter in [5] employs CMOS transmission gates. Fig. 9(a)shows a schematic of a single-stage 2 V pseudo-CMOS binary
counter with asynchronous reset. By connecting fourteen suchstages, we can build a 14 bit binary counter for the proposed
pedometer. On the basis of a divide-by-two frequency divider,a new gate-boosting technique is applied in this counter tocompensate for the poor conductivity of the pMOS switches forthe signal around thelevel. By employing a level-shifted
clock buffer, as shown in Fig. 9(b), we can effectively overdrive
pMOS switches by applying negative voltages though theterminal in the clock buffer.

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Fig. 8. All-pMOS negative voltage generator. (a) Overall schematic. (b) Schematic of pseudo-CMOS inverter. (c) DC characteristics of the Schmitt trigger inverterobtained by SPICE simulation.

IV. MEASUREMENT RESULTS AND DISCUSSION
A. All-pMOS Full-Wave Rectifier
The proposed all-pMOS full-wave rectifier is fabricated bya 2 V organic pMOS process. Fig. 10(a) shows a chip photograph of the proposed full-wave rectifier. The chip area is
13.8 24.9. Fig. 11 shows the measured waveform of the2 V full-wave rectifier without a smoothing capacitor (C1 in
Fig. 5); the output current is less than 1. The input signal() is a 4 V peak-to-peak sinusoidal wave. To clearly show
the rectified waveform, we choose 1 Hz as the input frequency.
Full-wave rectified waveforms () are clearly observed.
The output frequency is 2 Hz, and the amplitude of the rectifier
is approximately 2 V peak-to-peak when 1 Hz, 4 V peak-to-peaksinusoidal input signals are applied. Fig. 12 shows the measured
output voltage versus the output current of the rectifier witha1smoothing capacitor. The proposed all-pMOS rectifier
provides up to 12
power with 59% power efficiency. Fig. 13

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Fig. 12. Measured output voltage versus the output current of the rectifier withsmoothing capacitor.
a1Fig. 9. Schematics of a single-stage 2 V pseudo-CMOS binary counter with
asynchronous reset. (a) Binary counter. (b) Level-shifted clock buffer.

Fig. 13. Measured waveforms of 20
vester and the rectified output.

28

sheet of the PVDF energy har-Fig. 10. Chip photographs. (a) Full-wave rectifier. (b) Negative voltage generator. (c) Pseudo-CMOS Schmitt trigger inverter. (d) 2 bit pseudo-CMOS step
counter.

Fig. 14. Optimization of the output voltage of the PVDF sheet. (a) In-phase
operation of parallel PVDF harvesters. (b) Ant phase operation. (c) Implementation with distributed rectifiers. (a) In-phase. (b) Anti-phase. (c) Implementation with distributed rectifiers.

Fig. 11. Measured waveform of the 2 V full-wave rectifier without a smoothing
capacitor.

shows the measured waveforms of the 20 28
sheet of the
PVDF energy harvester and the rectified output. Here, the harvester is pressed by hands and the frequency is approximately
4 Hz, which is intended to be a typical operation speed of the pedometer. The 1
smoothing capacitor can be charged by providing a mechanical force to the PVDF energy harvester. The
output voltage is approximately 1.3 V with a current of 8.

The maximum conversion efficiency of the rectifier is 59%,
which is an acceptable performance for the insole pedometer.
However, if the conversion efficiency of the energy harvester
can be improved, its range of applications will be wider. In this
implementation, twenty-one PBDF rolls are set in parallel, andonly one large rectifier is used for simplicity. When each PVDF
sheet is pressed at the same time, the output voltage is maximized as shown in Fig. 14(a). In contrast, in the case of ananti phase, the PVDF outputs mutually conflict and the voltage
is canceled out as shown in Fig. 14(b). To avoid such conflict,the rectifiers should be distributed in a certain area as shown in260IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 1, JANUARY 2013

Fig. 15. Measured waveforms of the negative voltage generator.
Fig. 17. Measured DC characteristic of the pseudo-CMOS Schmitt trigger
inverter.

Fig. 16. Measured output voltage versus the output current of the negative
voltage generator.

Fig. 18. Measured waveforms of the pseudo-CMOS Schmitt trigger inverter.

Fig. 14(c). In addition, low-cost, large-area organic electronics
are suitable for implementing distributed rectifiers.
B. All-pMOS Negative Voltage Generator
Fig. 10(b) shows a chip photograph of the negative voltage
generator. The chip area is 21.9 16.0
. Two 470 nF MIM
capacitors (C1 and C2 in Fig. 6) occupy most of the chip area.
The measured waveforms and output voltage versus the output
current are shown in Figs. 15 and 16, respectively. An input
frequency of 10 Hz is chosen to show the maximum output
power and the power efficiency at the highest operation speedof the pedometer. The output voltage () of the negative
voltage generator isin the case of 10 Hz square pulses.
Thanks to the pseudo-CMOS-inverter-based switches, the proposed negative voltage generator provides a maximum powerof 12with 65% power efficiency.
C. Pulse Shaping (Pseudo-CMOS Schmitt Trigger Inverter)
Fig. 10(c) shows chip a photograph of the pseudo-CMOS
Schmitt trigger inverter. The chip area is 6.4 16.7
. On
the basis of the measured DC characteristic in Fig. 17, we findthat the switching points for the high-to-low and low-to-hightransients have a difference of approximately 0.25 V (inFig. 17); this characteristic plays a key role in supplying clean
clock signals to the counter. Fig. 18 shows the measured waveform of the pseudo-CMOS Schmitt trigger inverter. The PVDF
output is emulated with a 2 V peak-to-peak triangular wave. The
frequency is 1 Hz to clearly show the hysteresis characteristics.
The measured hysteresis characteristic is clearly observed withthe 1 Hz triangular wave input.

Fig. 19. Schematic of the pseudo-CMOS Schmitt trigger inverter with floating
gates.

For the lower-bound transition point in Fig. 17, the measurement result closely agrees with the simulation result (dashedline). On the other hand, the measured upper-bound transition
point is lower than the simulated result by approximately
0.15 V. This difference originates from the variation ofin M1 and M2 in Fig. 8. When the variation is critical, acompensation scheme based on the floating-gate programming[7] is also effective for the Schmitt trigger inverter. In such acase, M1 to M4 should be implemented with a floating-gatelayer as shown in Fig. 19. SPICE simulation results for thecompensation are shown in Fig. 20. When theof M1 isincreased by floating-gate programming, the upper-bound transition point () is shifted to the left as shown in Fig. 20(a).
On the other hand, the lower-bound transition point is stable.
When theof M2 is increased,
is moved to the rightas shown in Fig. 20(b). In M3 and M4, both the upper-boundISHIDA et al.: INSOLE PEDOMETER WITH PIEZOELECTRIC ENERGY HARVESTER AND 2 V ORGANIC CIRCUITS

Fig. 20. Simulation results of261

programming. (a) M1. (b) M2. (c) M3. (d) M4.

Fig. 21. Simulation results of the enhancement of hysteresis by programming
M2 and M4.

Fig. 22. Measured waveforms of the step counter. (a) Without gate boosting.
(b) With gate boosting.

D. 14 bit Pseudo-CMOS Step Counter() and lower-bound () transitions are modified asshown in Fig. 20(c) and (d), respectively. This floating-gate
programming can be used for not only compensation but also
the improvement of hysteresis. For instance, by programming
both M2 and M4, a wider hysteresis is realized as shown in
Fig. 21.

Fig. 10(d) shows a chip photograph of the pseudo-CMOS step
counter. Note that only two stages are shown in the photograph.
and the chip area is 25.5 46.8
Fig. 22 shows measured waveforms of the single-stage step
counter. The frequency of the input (IN) is 1 Hz to clearly show
the signal integrity. The waveform in Fig. 22(a) is for operation

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ACKNOWLEDGMENT
The authors thank Prof. K. Takimiya of Hiroshima University
and Dr. H. Kuwabara and Dr. M. Ikeda of Nippon Kayaku Co.,
Ltd., for providing high-purity DNTT.

Fig. 23. Measured waveforms of 2 bit step counter.
TABLE IKEY FEATURES AND PERFORMANCE SUMMARY.

without the gate-boosting technique. Owing to the poor driving
capability of the pMOS switches without gate boosting, large
dips are observed. Using the gate-boosting technique, the signal
integrity of Q1 in Fig. 22(b) is greatly improved and robust operation is achieved. Note that Fig. 22 only shows the signals
from output Q1, while QB1 in Fig. 9(a) is used for connecting
to the next stage of the binary counter. Fig. 23 shows the measured waveform of the 2 bit step counter. The frequency of the
input pulses is 4.4 Hz, which is the maximum measured operation speed of the counter. Although each output swing is slightly
degraded, the pseudo-CMOS step counter successfully operates
at 4.4 Hz, that is, the counter can handle up to four steps per
second.
Table I gives the key features and a performance summary of
the proposed insole pedometer. The pedometer consists of 462
transistors and its total area is 22 7.
V. CONCLUSIONS
A shoe insole pedometer, which consists of a piezoelectricenergy harvester and a 2 V organic pedometer circuit, has beendeveloped as a first step toward the application of flexible
large-area energy harvesting. Its feasibility is demonstrated bymeasurement. A pseudo-CMOS 14 bit step counter records thenumber of steps up to 16383 steps using the harvested power.
A negative voltage generator based on an organic charge
pump circuit provides 12
power with 65% efficiency. A
pseudo-CMOS Schmitt trigger inverter with a 0.25 V hysteresis
is also proposed. The integration of organic circuits and flexible
energy harvesters will broaden the rnge of applications offlexible, large-area electronics.

REFERENCES[1] H. Klauk, U. Zschieschang, J. Pflaum, and M. Halik, “Ultralow-powerorganic complementary circuits,” Nature, vol. 445, pp. 745–748, Feb.
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Maeda, M. Takamiya, T. Someya, and T. Sakurai, “A 100-V AC
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[6] H. Marien, M. Steyaert, E. van Veenendaal, and P. Heremans, “DC-DC
converter assisted two-stage amplifier in organic thin-film transistor
technology on foil,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2011, pp. 411–414.
[7] T. Yokota, T. Sekitani, T. Tokuhara, U. Zschieschang, H. Klauk, T.-C.
Huang, M. Takamiya, T. Sakurai, and T. Someya, “Sheet-type organic
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Koichi Ishida (S’00–M’06) received the B.S. degree
in electronics engineering from the University ofElectro-Communications, Tokyo, Japan, in 1998,
and received the M.S. and Ph.D. degrees in electronics engineering from the University of Tokyo,
Tokyo, Japan, in 2002 and 2005, respectively.
He joined Nippon Avionics Co., Ltd. Yokohama,Japan in 1989, where he developed high-reliability
hybrid microcircuits for aerospace programs. From2005 to 2007, he worked for CMOS analog and RF
circuits at Tokyo Institute of Technology, Yokohama,Japan. From 2007 to 2012, he worked for on-chip power supply circuits and organic electronics circuits at the Institute of Industrial Science, the University ofTokyo, Tokyo, Japan. Since July 2012, he has been working at Chair for Circuit Design and Network Theory, Dresden University of Technology, Dresden,
Germany. His research interests include low-voltage low-power CMOS analog
circuits, on-chip power supply circuits, and large-area flexible electronics.
Dr. Ishida is a member of IEICE.
Tsung-Ching Huang (S’05–M’09) received the B.S.
degree in Electrical and Control Engineering from
National Chiao-Tung University, Taiwan, in 2001,
and the Ph.D. degree in electrical and computerengineering from University of California, Santa
Barbara in 2009.
He is currently a member of technical staff with
TSMC San Jose Design Center. He worked as aproject research associate at the Institute of Industrial
Science (IIS), the University of Tokyo, Japan from2009 to 2011. From 2006 to 2008, he worked as asummer intern with ITRI, Taiwan, for designing flexible circuits and displays,
and with MediaTek Inc., Taiwan, for designing radio frequency circuits forcellular phones. Dr. Huang received Best Paper Award from International
Symposium for Flexible Electronics and Displays in 2007. His research interests include circuit design, EDA tool development and reliability analysis forflexible electronics, and low-power mixed-signal circuits in advanced CMOS.

ISHIDA et al.: INSOLE PEDOMETER WITH PIEZOELECTRIC ENERGY HARVESTER AND 2 V ORGANIC CIRCUITS

Kentaro Honda received the B.S. and M.S. degrees
in electronic engineering from the University ofTokyo, Tokyo, Japan, in 2010 and 2012, respectively.
In 2012, he joined the NTT Microsystem Integration Laboratories, Kanagawa, Japan. He is currently
working on the development of high-speed LSIs for
optical communications.

Yasuhiro Shinozuka received the B.S. degree
in electronic engineering from the University ofTokyo, Japan, in 2011. He is currently studying in
the Department of Electrical Engineering and Information Systems, Graduate School of Engineering,
University of Tokyo.
His research interests are in the field of in-package
DC/DC converters and 3D integrated circuits.

Hiroshi Fuketa (S’07–M’10) received the B.E.
degree from Kyoto University, Kyoto, Japan, in
2002, and the M.E. and Ph.D. degrees in information
systems engineering from Osaka University, Osaka,
Japan, in 2008 and 2010, respectively.
He is currently a Research Associate with Instituteof Industrial Science, the University of Tokyo. His
research interests include ultra-low-power circuit design and variation modeling.
Dr. Fuketa is a member of IEICE and IPSJ.

Tomoyuki Yokota was born in Tokyo, Japan, in
1985. He received the M.S. degree in applied physics
in 2010 from the University of Tokyo, Tokyo, Japan,
where he is currently working toward the Ph.D.
degree in applied physics.
His research interests include printed electrical devices, large-area electronics, organic memories, andorganic transistors.

Ute Zschieschang received the Diplom-Ingenieur
degree in mechanical engineering from Mittweida
University of Applied Sciences, Germany, in 2000
and the Ph.D. degree in chemistry from the Technical
University Bergakademie Freiberg, Germany, in2006.
Since 2005, she has been a scientist in the Organic
Electronics group at the Max Planck Institute for
Solid State Research, Stuttgart, Germany.

Hagen Klauk (S’97–M’99) received the Diplom-Ingenieur degree in electrical engineering from Chemnitz University of Technology, Germany, in 1995 andthe Ph.D. degree in electrical engineering from thePennsylvania State University in 1999.
From 1999 to 2000, he was a Postdoctoral Researcher with the Center for Thin Film Devices at thePennsylvania State University. In 2000, he joined
Infineon Technologies, Erlangen, Germany. Since
2005, he has been head of the Organic Electronics
group at the Max Planck Institute for Solid State
Research, Stuttgart, Germany.

263

Gregory Tortissier was born in 1982 in Enghien,
France. He received the Master degree in materialscience from Graduate School of Chemistry andPhysics of Bordeaux, France, in 2006. He received
the Ph.D. degree in microelectronics from the IMS
laboratory (formerly IXL) in 2009 and worked in
the field of surface acoustic wave sensors for gas
detection in high temperature environments.
He then worked as a JSPS post doctoral fellowship (until December 2011) in flexible large MEMS
area in Hiroshi Toshiyoshi Laboratory, University ofTokyo, Japan. He then joined the Nikon and Essilor International Joint ResearchCenter in Kanagawa, Japan, and is currently working on materials for opticalapplications.

Tsuyoshi Sekitani received the B.S. degree from
Osaka University, Japan, and the Ph.D. degree inapplied physics from the University of Tokyo, Japan,
in 1999 and 2003, respectively.
From 1999 to 2003, he was with the Institute for
Solid State Physics (ISSP), University of Tokyo.
From 2003 to 2009, he was a Research Associate of
the Quantum-Phase Electronics Center, Universityof Tokyo. Since 2011, he has been an Associate Professor in the Department of Electrical and Electronic
Engineering, University of Tokyo.

Hiroshi Toshiyoshi (M’97) received the M.S. and
Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1993 and 1996,
respectively.
From 1999 to 2001, he was a Visiting Assistant Professor at the University of California, Los
Angeles. Since 2002, he has been an AssistantProfessor with the Institute of Industrial Science,
University of Tokyo. From 2002 to 2007, he was a
Codirector of the Laboratory for Integrated Micro
Mechatronic Systems (UMI 2820), an international
joint laboratory with the Centre National de la Recherche Scientifique and theInstitute of Industrial Science, University of Tokyo. From 2005 to 2008, he wasthe Project Leader of the Optomechatronics Project at Kanagawa Academyof Science and Technology, Kawasaki, Japan. Since May 2009, he has beena Professor with the Research Center for Advanced Science and Technology,
University of Tokyo. His research interest is optical and radio-frequency
microelectromechanical systems.

Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995, 1997,
and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high-speed
digital LSIs. In 2005, he joined University of Tokyo,
Japan, where he is an Associate Professor of VLSI
Design and Education Center. His research interests
include the circuit design of low-power RF circuits,
ultra-low-voltage logic circuits, low-voltage DC-DC
converters, and large area electronics with organic transistors.
Dr. Takamiya is a member of the technical program committee for IEEE Symposium on VLSI Circuits. He received 2009 and 2010 IEEE Paul RappaportAwards.

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Takao Someya (M’03) received the Ph.D. degree inelectrical engineering from the University of Tokyo,
Japan, in 1997.
In 1997, he joined Institute of Industrial Science(IIS), University of Tokyo, as a Research Associate
and was appointed to be a Lecturer of the ResearchCenter for Advanced Science and Technology(RCAST), University of Tokyo, in 1998, and an
Associate Professor of RCAST in 2002. From 2001
to 2003, he worked for the Nanocenter (NSEC)
of Columbia University and Bell Labs, Lucent
Technologies, as a Visiting Scholar. From 2003 to 2009, he was an Associate
Professor of the Department of Applied Physics and Quantum-Phase Electronics Center, University of Tokyo. Since 2009, he has been a Professor of
the Electrical and Electronic Engineering, University of Tokyo. His current
research interests include organic transistors, flexible electronics, plastic
integrated circuits, large-area sensors, and plastic actuators.
Prof. Someya is a member of the IEEE Electron Devices Society, the Materials Research Society (MRS), and the Japanese Society of Applied Physics.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 1, JANUARY 2013

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Japan, in 1981.
In 1981 he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and SoC Solutions. He has worked extensively
on interconnect delay and capacitance modelingknown as Sakurai model and alpha power-law MOS
model. From 1988 through 1990, he was a visiting
researcher at the University of California Berkeley,
where he conducted research in the field of VLSICAD. Since 1996, he has been a Professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic ICs and large-area electronics. He has published morethan 600 technical publications including 100 invited presentations and several
books and filed more than 200 patents.
Dr. Sakurai is the executive committee chair for VLSI Symposia and asteering committee chair for the IEEE A-SSCC. He served as a conference chairfor the Symp. on VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC
chair for the A-SSCC, and VLSI Symposium, an executive committee member
for ISLPED and a program committee member for ISSCC, CICC, A-SSCC,
DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He
was a recipient of the 2010 IEEE Donald O. Pederson Award in Solid-State
Circuits, 2009 and 2010 IEEE Paul Rappaport awards, 2010 IEICE Electronics
Society award, 2009 IEICE achievement award, 2005 IEEE ICICDT award,
2004 IEEE Takuo Sugano award, 2005 P&I patent of the year award, andfour product awards. He has delivered the keynote speech at more than 50
conferences including ISSCC, ESSCIRC and ISLPED. He was an elected
AdCom member for the IEEE Solid-State Circuits Society and an IEEE CAS
and SSCS distinguished lecturer. He is an IEICE Fellow and IEEE Fellow.