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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 10, OCTOBER 2011

Capacitively Coupled Non-Contact Probing
Circuits for Membrane-Based Wafer-Level
Simultaneous Testing
Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto,
Kunihiko Iizuka, Member, IEEE, Katsuyuki Ikeuchi, Student Member, IEEE, Gil Su Kim, Member, IEEE,
Makoto Takamiya, Member, IEEE, and Takayasu Sakurai, Fellow, IEEE

Abstract—A capacitively coupled probing circuit with a novelde-skewer, a low-pass filter and a high-sensitivity receiver is
proposed to realize a membrane-based wafer-level simultaneous
testing robustly. The de-skewer can be designed by only digitalcore transistors and has stable feed-forward architecture. The
receiver with the low-pass filter can suppress the undesirable
ringing caused by the complex wiring structure in the probe card.
A probe chip and a 300 mm DUT-wafer are fabricated in a 1.2 V
90 nm technology and the measured power consumption of RX
core is 0.5 mW at 1 Gbps operation. The BER is improved below
over almost all UI range when the de-skewing function isturned on.
Index Terms—Wafer test, capacitive coupling, crosstalk, receiver, de-skewer.

I. INTRODUCTIONTHE development of three-dimensional system in package(3D-SiP) technologies has been accelerated to improve
the LSI performance. In the 3D-SiP, many dies are stacked andif the yield of die is low, the yield of 3D-SiP falls dramatically.
Thus it is important to obtain the Known Good Die (KGD) effectively. Wafer-level simultaneous testing (WLST) where all
chips on a wafer are tested and burned in at the same time ispreferable in reducing the cost of selecting KGDs. At present,
however, it is difficult to realize the WLST because a huge load
is required for the stable contact of all test pins on the wafer.
Recently, a low-cost membrane-based wafer-level testing technique has been disclosed which makes use of the atmosphericpressure and 700 kg of force can be uniformly distributed overa 300 mm wafer [1]. Yet, assuming that one bump needs 4 g
of force to make a stable contact, the probing equipment has
to distribute 1.2 ton of force over the 300 mm wafer uniformly
as shown in Fig. 1. One promising technique to reduce the required load from 1.2 ton to 700 kg is the combination use of theManuscript received November 15, 2010; revised May 18, 2011; accepted
May 24, 2011. This paper was approved by Associate Editor Ken Shepard. This
work was supported by NEDO (New Energy and Industrial Technology Development Organization) entrustment project.
M. Daito, Y. Nakata, S. Sasaki, H. Gomyo, H. Kusamitsu, Y. Komoto, andK. Iizuka are with the Association of Super-Advanced Electronics Technologies(ASET), Yokohama 230-0046, Japan.
K. Ikeuchi, G. S. Kim, M. Takamiya, and T. Sakurai are with the Universityof Tokyo, Tokyo 113-0033, Japan.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2011.2160790

contacting bumps for power supply and the non-contact interfaces such as the capacitively coupled interfaces (CCIs) [2]–[6],the inductively coupled interfaces (ICIs) [7]–[9] and the RF interfaces (RFIs) [10]–[12] for digital pins. Non-contact probing
techniques for the WLST [7], [11], [12] have been proposed, butthey are costly because they need probing chips built specific toa certain product.
In this paper, we propose the capacitively coupled non-contact probing circuit for the low-cost membrane-based WLST.
Section II compares the non-contact interfaces for the WLSTand discusses the effect of cross talk. Section III describes the
proposed WLST with the CCI. Section IV explains the novelde-skewer and shows simulation results. Section V presents thedetails of the receiver circuit. Section VI summarizes experimental results, and Section VII concludes the paper.
II. NON-CONTACT INTERFACES FOR WLSTFig. 2 compares non-contact interfaces for the WLST. The
required number of pads per channel is two for the ICI, and one
for the RFI and the CCI. Considering the interconnect congestion in the probe card and the pad-limited nature of the chip,
the RFI and the ICI are prohibitive. This situation also hinders
the use of differential signaling [5]. Although the RFI and the
ICI can be implemented in the chip, they need probing chips
built specific to a certain product and cannot be adopted for the
low-cost WLST.
The CCI has the advantage of being able to use the bonding
pads for a part of the non-contact interface and a coupling padcan be made by just a metal plate, so a fine process is not needed.
On the other hand, the RFI and the ICI require special antennas
and coils, respectively. These facts also indicate that the area
overhead of the CCI in the device-under-test (DUT) will be nil
when the TX and RX can be made under the bonding pads, but
the RFI and the ICI need extra footprints for a pair of TX andRX, e.g., 0.13 mm [10] and 0.03 mm [8], because they require
special antennas and coils, respectively.
All interfaces have achieved the data rate over 1 Gbps, which
is sufficient to cover the at-speed test for most of the next-generation SoC’s for mobile and/or consumer digital applications.
The only disadvantage of the CCI is its short transmission
distance. In the proposed WLST, however, the distance between
the pads is almost zero as described in Section III, so the transmission distance does not become a problem. Moreover, the almost-zero-distance pads make the CCI tolerant to cross talk.

0018-9200/$26.00 © 2011 IEEEDAITO et al.: CAPACITIVELY COUPLED NON-CONTACT PROBING CIRCUITS FOR MEMBRANE-BASED WAFER-LEVEL SIMULTANEOUS TESTING

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Fig. 1. Conventional membrane-based wafer-level testing technique.

Fig. 2. Comparison of non-contact interfaces.

Fig. 3(a) illustrates the simplified interface models of the ICI
and the CCI. The parameter is the coupling distance between
the interfaces which have the base length and the height .
The parameter is the separation distance between adjacent interfaces. In the ICI, assuming only the magnetic field coupling
for simplicity, the signal transfer S21 and the cross talk S31 andS41 are approximated as
(1)
(2)
(3)
,
,
and
are the number of turns,
is thewhere
output impedance and is the transmission signal frequency.
In the CCI, assuming that the parasitic capacitanceis muchlarger than the coupling capacitance, the signal transfer S21 andthe cross talk S31 and S41 are approximated as
(4)
(5)
(6)
The calculation results are shown in Fig. 3(b) with the typicalparameters (m,m andm) for the

WLST. The differences between S21 and S31 in the ICI and the
CCI are 13 dB and 46 dB when the separation distance is 10 m,
respectively. It is sufficient to ignore the effect of cross talk for
the CCI. These results show that the CCI can place pads moreclosely and is more area-efficient for the WLST than the ICI.
III. WAFER-LEVEL SIMULTANEOUS TESTING
The probe card for the proposed WLST consists of five layers
including a main board, anisotropic conductive elastomers(ACE1, ACE2), an interposer and a polyimide membrane
as shown in Fig. 4. The tester chips and the probe chips aremounted on the main board. The tester chip implements simple
tester functions and the probe chip has CCI. ACE1 and ACE2
can remove the differences in level between the main board andthe interposer and between the interposer and the polyimide
membrane, respectively. The polyimide membrane is very thinfilm which has the thickness of 25 m, and has contacting
bumps and non-contact pads. The contacting bumps can beused not only for power supply but also for testing ultra-highspeed interfaces and analog and RF functions if needed. The
expensive main board is common to all products and the inexpensive organic interposer and polyimide membrane are to be
re-designed and built when a product under test is changed, andthereby the total cost of the probe card for WLST can be kept
low.
To ensure the stable non-contact probing, a two-stage depressurization technique is developed. Pumping the air out of thespace between the probe card and the wafer, the probe card ispressed to the wafer by 10 N/cm of the atmospheric pressure.
This technique makes it possible to distribute 700 kg of force

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Fig. 3. (a) Simplified interface models and (b) calculation results withIEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 10, OCTOBER 2011

m,

m and

m.

Fig. 4. Proposed wafer-level simultaneous testing technique with the capacitively coupled interface.

over the 300 mm wafer uniformly [1]. When the spaces between
the interposer and the polyimide membrane and between thepolyimide membrane and the wafer are equally depressurized
to 1 N/cm , non-contact pads on the membrane stay away fromthe pads on the wafer. As turning the vacuum valve to depressurize the space between the interposer and the polyimide membrane to 2 N/cm , the polyimide membrane adheres to the wafer.
Then the distance between the non-contact pads becomes almost
zero, but the surface oxide of the wafer prevents them from connecting electrically. Since the almost all force is distributed tothe contacting bumps, the non-contact pads are pressed softly to
the wafer and have no reliability issue.
Fig. 5 shows the system block diagram of the proposed
WLST. The tester chips implement simple tester functions

including timing and control signal generation, test patternbuffing and test results compression, reducing the power andcost of communication between the main tester equipment
and the probing system. The tester chip also has power-supply
disconnecting functions for breakdown chips. The TXs on theprobe chip and the DUT-wafer are simple CMOS drivers toshare the bonding pads with the normal I/Os. The pads on thepolyimide membrane and the DUT-wafer form the coupling
capacitance. The signals travel between the probe chip and the
DUT-wafer through the complex wiring structure depicted inFig. 4. The total length of the wiring ranges around 20 mm anddiverse reflections occur at interfaces among layers. Consequently, de-skewing function should be implemented for each
digital channel.

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Fig. 5. System block diagram of proposed WLST.

Fig. 6. Block diagram of feed-forward all-digital de-skewer.

IV. FEED-FORWARD ALL-DIGITAL DE-SKEWER
To remove the skews between channels, a low-power andsmall-area de-skewing circuit, namely, Feed-forward All-digitalDe-skewer (FAD) in Fig. 6 is proposed. The FAD has two advantages over conventional de-skewing methods such as a clock
data recovery [13]. One is that the FAD can be designed using
only digital core transistors and the other is the feed-forward

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 10, OCTOBER 2011means that the skews between data are removed. Fig. 8 also indicates the advantages of the FAD that the FAD does not needs
the special calibration patterns to remove the skews and the adequate output switch can be selected quickly.
V. RECEIVER CIRCUIT

Fig. 7. Output waveforms of flip-flops in FAD.

architecture which makes the FAD fast and stable. The FAD isbased on a time-to-digital converter [14], and uses delay elements not only detecting the phase error but also delaying thetiming of input data to remove the skews between channels. The
delay element is constantly adjusted to show one eighth of aclock cycle by a simple delay-locked loop. A bubble error corrector and a third order moving average filter are implemented
to mitigate the effect of undesired signals by accidental errors.
For a certain channel, if the rising edges of delayed
and CLK match at Flip-Flop “”,
is considered to riseabout a half clock cycle before the CLK rising edge, because
the delay element is constantly adjusted to show one eighth
should be delayed about a halfof a clock cycle. Then,clock cycle to maximize the margin in synchronization which” by using CLK bar. Thus, after theoccurs at Flip-Flop “
bubble error corrector and the third order moving average digital filter, the LUT-based adaptive switch selector selects the” andis delayed a half clock cycle forswitch “
by the delay elements. On the other hand, if
risingedge comes a bit earlier (later), the matching edge is captured”(“”) and the switch “
”(“
”) is
at location “
selected. Thus, the rising edge ofis always delayed ahalf clock cycle for the rising edge of the CLK. When the FAD” or “receives continuous same data streams like “”, the switch “” or “” is incorrectly selected, because
all Flip-Flops output 0 or 1 as shown at the timing (i) or (ii)in Fig. 7, respectively. To avoid such a consequence, Flip-Flop” is added. Since the delay element is constantly adjusted“
to show one eighth of a clock cycle, there is one clock cycle” and “”. Theredelay between the data at Flip-Flops “fore when the same data is captured at the location “
” and
“
”,
is considered to be the continuous same data. Thenthe third order moving average digital filter does not capture theoutput of the bubble error corrector and the correct switch is
kept selecting.
SPICE simulations have been performed to verify the effectiveness of the proposed de-skewing circuit using the three difps, 0 ps and 350 ps, as shown
ferent delayed data such asshows the same delay as. Afterin Fig. 8. At first,
become almost same, which
a few cycles, the edges at

Another point of difficulty in the membrane-based CCI overa chip-to-chip interface lies in the transmission nature of wiring
and the smaller received signal due to the large capacitanceof the transmission line up to 2 pF. To overcome the issue, alow-pass filter (LPF), which consists of the poly resistor and thecapacitance of the electrostatic discharges (ESDs), is inserted
before a preamplifier as shown in Fig. 9. The LPF can suppress
the undesirable ringing caused by the diverse reflections because the frequencies of the reflections are usually higher than
the signals in the proposed WLST. A DC-cutting capacitor isinserted to eliminate the interference between precharger1 andprecharger2 even if the precharge levels are different due toprocess variations.
A high-sensitivity receiver circuit is introduced, denoted as
weak-feedback receiver in Fig. 9. The previously reported receiver in [4] is robust but needs intermittent resetting of circuits
which is difficult to implement in the test environment. In the
proposed RX circuit, the feed-back node is not connected directly to the signal path compared to the conventional RX which
has the direct feed-back path [6] as shown in Fig. 10. So theeffect of the feed-back in the proposed RX becomes weaker.
The minimum receivable input amplitude of the proposed RX
is smaller than the conventional inverter cross-coupled RX, thatis, the proposed RX has the higher sensitivity over large PVTvariations. While receiving a same signal continuously, the nodeN2 of RX in Fig. 9 comes close to VDD or VSS and the sensitivity degrades at the next data change. The inverter connected
an input with an output makes the voltage of N2 to leave slightly
away from VDD or VSS and improves the sensitivity at suchsituation. As a result, the minimum receivable amplitude of the
proposed RX is 50 mV.
VI. EXPERIMENTAL RESULT
Fig. 11 shows a full view of the proposed WLST. A 300 mm
wafer is loaded under the probe card from a cassette and thenpads on the wafer and the polyimide membrane are automatically aligned. When test is running, the probe card is put on thewafer and is pressed by the atmospheric pressure. For the sakeof the flexible evaluation, FPGAs are mounted on the probe card
as a substitute for tester chips.
The probe chip and the DUT-wafer are fabricated with a
90 nm 1.2 V CMOS technology. Two types of pad are implemented as shown in Fig. 12: one is an uncovered pad andthe other is an insulator covered pad both of which worked
successfully. Two versions of pad size, 80 m 80 m and
160 m 160 m, are tried but turned out that 80 m 80 m
is sufficient even with the maximum alignment error which ism over the whole 300 mm wafer. The probe chipless thanhas the pseudo-random bit sequence (PRBS) generator and the

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Fig. 8. Simulation result of FAD.

Fig. 9. (a) Proposed receiver circuit and (b) Simulation results.

bit error-rate (BER) tester for the high-speed signal test and the
DUT-wafer has a simple function for the loop-back test.
Fig. 13 shows the measured output waveforms of the proposed receiver which indicate that the circuit can receive up to
1 GHz clock and 1 Gbps data. The 4-channel 1 Gbps data canbe received successfully without cross talk between channels. In
the single-ended interface, the power line noise is transformed
into the RX input noise and degrades the BER. To avoid suchsituation, a large amount of on-chip and off-chip decoupling capacitors is placed in this prototype WLST. In the production environment, since there is little space to place the decoupling capacitors, the technique to make the RX insensitive to the powerline noise and the scheme to decrease the power line impedance
will be necessary.
The power consumption is 0.5 mW/channel for a RX core at
1.2 V 1 Gbps operation as shown in Fig. 14.
Two transmission lines which have the different lengths of
10 mm and 20 mm are implemented in the probe card to confirm
the effectiveness of the FAD as shown in Fig. 15. When signals
bypass the FAD, there is about 150 ps skew between signals (A)and (D). On the other hand, when signals go through the FAD,
the skew between signals (B) and (C) is removed successfully.
Fig. 16 shows the measurement results of the BER at 1 Gbps
operation. When the de-skewing function (FAD) is turned off,

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 10, OCTOBER 2011

Fig. 10. Comparison of RX cores. (a) Conventional RX, (b) Proposed RX, and (c) Minimum receivable input amplitude for PVT variations.

Fig. 11. Full view of proposed WLST. (a) Head plate open and (b) Head plate close.

Fig. 12. Microphotographs of probe chip, DUT-wafer and polyimide membrane.

the BER is measured to be larger thanbut the BER isover almost all unit-interval (UI) range
improved below
when the FAD is turned on. Fig. 16 indicates that the FAD canalso enhance the jitter tolerance.

Table I shows the performance summary. The power consumption of the proposed RX at 1 Gbps operation is 0.7 mW
for the probe chip and 0.5 mW for the DUT-wafer. RX for
DUT is smaller in size than RX for a probe chip because the

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Fig. 13. Measured output waveforms of proposed receiver.

Fig. 14. Measured power consumption.

Fig. 15. (a) Block diagram of test setup and (b) Measured waveforms at 1 Gbps operation.

LPF is not needed for the latter since there is no long interconnect after the coupling capacitor. Since all functions are realized
by digital core transistors and the feed-forward control is employed, the area is as small as 0.004 mm /channel and the mea-

sured power is 1.2 mW/GHz/channel, which should be compared with 0.3 mm /channel of area and 6.4 mW/GHz/channelof estimated power achieved by a previously-reported DLLbased clock de-skewer [15].

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REFERENCES

Fig. 16. Measured bit error rate at 1 Gbps operation.
TABLE IPERFORMANCE SUMMARY

VII. CONCLUSION
The proposed wafer-level simultaneous testing system has
two features. One is the low-cost membrane based probing
technique with use of the atmospheric pressure and the otheris the capacitively coupled non-contact probing circuit. The
FAD consumes 1.2 mW/GHz/channel and the BER is improved below
over almost all UI range when the FAD
is turned on. The weak-feedback receiver with the LPF has
higher sensitivity over large PVT variations and consumed
0.5 mW/channel at 1.2 V 1 Gbps operation. The overhead areaof the DUT-wafer for using the proposed non-contact scheme
is only 128 m /channel because the bonding pad can be used
for the signaling.
The proposed techniques make it possible to test all chips on
the wafer simultaneously and reduce the test cost dramatically.
Yet the power supply requires the contacting bumps and thefurther work will focus on developing the capacitively coupled
non-contact power supply.
ACKNOWLEDGMENT
Advantest Corp., Sharp Corp., Panasonic Corp. and YamaichiElectronics kindly offered existing technologies and helped indefining the specifications. Valuable discussions by Shigeru
Matsumura and Shigeru Kannari from Advantest are appreciated.

[1] S. Sasaki and Y. Nakata, “A challenge of 150 k probes on 300 mm,” inIEEE SW Test Workshop, San Diego, CA, Jun. 2009, Session 1-4.
[2] M. Daito et al., “Capacitively coupled non-contact probing circuits
for membrane-based wafer-level simultaneous testing,” in 2010 IEEE
ISSCC Dig. Tech. Papers, Feb. 2010, pp. 144–145.
[3] G. S. Kim, M. Takamiya, and T. Sakurai, “A 25-mV-sensitivity 2-Gb/s
optimum-logic-threshold capacitive-coupling receiver for wirelesswafer probing systems,” IEEE Trans. Circuits Syst. II, vol. 56, no. 9,
pp. 709–713, Sep. 2009.
[4] A. Fazzi et al., “3-D capacitive interconnections for wafer-level anddie-level assembly,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp.
2270–2282, Oct. 2007.
[5] L. Luo et al., “3 Gb/s AC coupled chip-to-chip communication using
a low swing pulse receiver,” IEEE J. Solid-State Circuits, vol. 41, no.
1, pp. 287–296, Jan. 2006.
[6] S. A. Kühn et al., “Vertical signal transmission in three-dimensional
integrated circuits by capacitive coupling,” in Proc. 1995 IEEE Int.
Symp. Circuits Syst. (ISCAS), Apr. 1995, vol. 1, pp. 37–40.
[7] Y. Yoshida et al., “An inductive-coupling DC voltage transceiver for
highly parallel wafer-level testing,” IEEE J. Solid-State Circuits, vol.
45, no. 10, pp. 2057–2065, Oct. 2010.
[8] N. Miura et al., “A high-speed inductive-coupling link with burst transmission,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 947–955,
Mar. 2009.
[9] H. Ishikuro, T. Sugahara, and T. Kuroda, “An attachable wireless chip
access interface for arbitrary data rate using pulse-based inductive-coupling through LSI package,” in 2007 IEEE ISSCC Dig. Tech. Papers,
Feb. 2007, pp. 360–361.
[10] K. Kawasaki et al., “A millimeter-wave intra-connect solution,” in2010 IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 414–415.
[11] C. Sellathamby et al., “Wireless probe card,” in IEEE SW Test Workshop, San Diego, CA, Jun. 2004, Session 7-4.
[12] B. Moore et al., “Non-contact testing for SoC and RCP (SIPs) at advanced nodes,” in Proc. IEEE Int. Test Conf., Oct. 2008, pp. 1–10,
paper 23.3.
[13] C. Kromer et al., “A 25-Gb/s CDR in 90-nm CMOS for high-density interconnects,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.
2921–2929, Dec. 2006.
[14] P. Dudek, S. Szczepanski, and J. V. Hatfield, “A high-resolution
CMOS time-to-digital converter utilizing a vernier delay line,” IEEE
J. Solid-State Circuits, vol. 35, no. 2, pp. 240–247, Feb. 2000.
[15] A. Agrawal, P. K. Hanumolu, and G. Y. Wei, “An 8x5 Gb/s parallel
receiver with collaborative timing recovery,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3120–2130, Nov. 2009.
Mutsuo Daito received the B.S. and M.S. degrees
in mechanical engineering from Kyoto University,
Kyoto, Japan, in 2000 and 2002, respectively.
In 2002, he joined Sharp Corporation, Nara, Japan,
where he developed mixed-signal LSIs. From 2008
to 2010, he was with the Association of Super-Advanced Electronics Technologies, Yokohama, Japan,
where he worked on research and development of test
systems.

Yoshiro Nakata received the B.S. degree inelectronics engineering from Nagoya Institute ofTechnology, Nagoya, Japan, in 1980.
In 1980 he joined the Semiconductor ResearchLaboratory, Matsushita Electric Industrial Co., Ltd.
(now Panasonic Corporation), Osaka, Japan, where
he was engaged in research on the reliability of
MOS devices. Since 1989 he has been engaged in
the development of high-density CMOS memory
devices. Since 1994 he has been engaged in the
research and development of WLBI technology. In
1999 he introduced 8-inch WLBI system to semiconductor factory. In 2002 hedeveloped and introduced 300 mm WLBI system to the factory. Since 2007, hehas been with the Association of Super-Advanced Electronics Technologies,
Yokohama, Japan, where he is engaged in the research and development ofwafer level test and burn-in technology.

DAITO et al.: CAPACITIVELY COUPLED NON-CONTACT PROBING CIRCUITS FOR MEMBRANE-BASED WAFER-LEVEL SIMULTANEOUS TESTING

Satoshi Sasaki received the B.S. degree in electronics engineering from Chiba University, Japan, in
1988.
From 1988 to 1991, he was with Uniden Corporation, Chiba, Japan, where he was engaged in
the development of pagers, satellite tuners, andcordless telephones. From 1991 to 1998, he was with
Sumitomo Metal Mining Co., Ltd., where he wasengaged in production engineering and developmentof the PZT IR detector. From 1998 to 2004, he waswith Matsusita Communication Industrial Co., Ltd.,
where he was engaged in the research and development of WLBI technology.
From 2005 to 2008, he was with Matsushita Electric Industrial Co., Ltd., Osaka,
Japan, where he was engaged in the development of the Production facilityof the plasma display panel. Since 2008, he has been with the Associationof Super-Advanced Electronics Technologies, Yokohama, Japan, where he isengaged in the research and development of full-wafer level test and burn-in
technology.
Hiroyuki Gomyo received the B.S. and M.S. degrees in electronic engineering from the Universityof Tokyo, Tokyo, Japan, in 1999 and 2001, respectively.
In 2001, he joined Panasonic Corporation, Japan,
where he was engaged in the testing of LSIs. In
2008, he joined the Association of Super-Advanced
Electronics Technologies, Yokohama, Japan, where
he worked on research and development of test
systems.
Hideki Kusamitsu received the B.S.E.E. degreefrom the Matsue Technical Collage, Japan.
He is a Chief Researcher with the Association ofSuper-Advanced Electronics Technologies (ASET),
Yokohama, Japan. He is responsible for electrical design, evaluation, and electrical stimulation of highspeed connector. Also, he has researched wireless interconnect technology at ASET.

Yoshio Komoto is a Researcher of the Association ofSuper-Advanced Electronics Technologies (ASET),
Yokohama, Japan. He has researched the test systemwith wireless interconnect technology at ASET.
Also, he has been engaged in the development of
test systems at Advantest Corporation.

Kunihiko Iizuka (M’94) received the B.S. and M.S.
degrees in mathematics from Osaka University,
Osaka, Japan, in 1979 and 1981, respectively. He
continued his study of mathematics as a postgraduate
at Osaka University from 1981 to 1984. Later, he
was enrolled in a postgraduate course of electronicengineering at the Tokyo Institute of Technology,
Tokyo, Japan, from 2006 to 2009, and received the
Ph.D. degree from the same university in 2009 on
the subject of RF and analog integrated circuits for
television broadcast receivers.
In 1984, he joined Sharp Corporation, Japan, where he was involved in the
research of computer simulation systems. From 1991 to 1993, he was at theCenter for Adaptive Systems, Boston University, Boston, MA, as a visiting researcher, working on neural network systems. Since 1993, he has been working
on research and development of analog and mixed signal LSI circuits for highprecision ADCs, vision systems, and wireless systems with Sharp Corporation.
Dr. Iizuka was a member of the ISSCC program committee from 2001 to 2008
and was the ISSCC Far East regional subcommittee chair for ISSCC 2005 and2006. He has been a member of the A-SSCC program committee since 2006.
Currently, he is the chair of the A-SSCC data converter subcommittee and thechair of IEEE SSCS Kansai Chapter.

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Katsuyuki Ikeuchi received the B.S. and M.S., degrees in electronics engineering from the Universityof Tokyo, Tokyo, Japan, in 2007, and 2009, respectively. He is currently pursuing the Ph.D. degree atthe University of Tokyo, also in electronics engineering. His research interests include low-voltage
low-power circuits and proximity communication.

Gil-Su Kim received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in
2002, and the Ph.D. degree in electronics engineeringfrom Korea University in 2008.
In 2008, he joined the University of Tokyo, Japan,
as a postdoctoral researcher. In 2010, he joined
the Samsung Electronics Corporation, Korea. His
research interests include the circuit design of wired
and wireless high-speed I/O interfaces.
Dr. Kim received the HumanTech Thesis Contest
Bronze Award from Samsung Electronics Corporation (2006), the Semiconductor Engineering Contest Award from the KoreanIntellectual Property Office (2006), and the IEEE Seoul Section Student Paper
Contest Silver Award (2007).
Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995, 1997,
and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high speed
digital LSIs. In 2005, he joined University of Tokyo,
Japan, where he is an associate professor of VLSI
Design and Education Center. His research interests
include the circuit design of the low-power RF circuits, the ultra low-voltage digital circuits, and thelarge area electronics with organic transistors.
Dr. Takamiya is a member of the technical program committee for IEEE
Symposium on VLSI Circuits and IEEE Custom Integrated Circuits Conference(CICC).
Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Japan, in 1981.
In 1981 he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and SoC solutions. He has worked extensively
on interconnect delay and capacitance modelingknown as Sakurai model and alpha power-law MOS
model. From 1988 through 1990, he was a visiting
researcher at the University of California Berkeley,
where he conducted research in the field of VLSICAD. From 1996, he has been a Professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic ICs and large-area electronics. He has published morethan 400 technical publications including 100 invited presentations and several
books and filed more than 200 patents.
Dr. Sakurai is the executive committee chair for VLSI Symposia and asteering committee chair for the IEEE A-SSCC. He served as a conference chairfor the Symp. on VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC
chair for the A-SSCC and VLSI Symposium, an executive committee member
for ISLPED and a program committee member for ISSCC, CICC, A-SSCC,
DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He isa recipient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits,
2010 and 2011 IEEE Paul Rappaport award, 2010 IEICE Electronics Society
award, 2009 IEICE achievement award, 2005 IEEE ICICDT award, 2004 IEEE
Takuo Sugano award and 2005 P&I patent of the year award and four productawards. He has given keynote speeches at more than 50 conferences including
ISSCC, ESSCIRC, and ISLPED. He was an elected AdCom member for theIEEE Solid-State Circuits Society and an IEEE CAS and SSCS distinguishedlecturer. He is an IEICE Fellow and IEEE Fellow.