Bond Wire Lift-off Sensor Circuit for Power
Devices Integrated in Gate Driver IC
Yaogan Liang, Hiroki Yano, Haoxi Zhou, Katsuhiro Hata, and Makoto Takamiya
The University of Tokyo, Tokyo, Japan
Abstract-- To achieve low-cost detection of bond wire liftoff for power devices without sensor circuits made of discrete
components on PCB, the world’s first fully integrated bondwire lift-off sensor (BWLS) compatible with existing gate
driver IC is proposed. When several bond wires in the emitterof an IGBT lift off, the increased parasitic inductance leads
to a higher induced voltage, which raises the transient-state
turn-on gate-to-emitter voltage (VGE). The proposed BWLS
detects bond wire lift-off by tracking and holding thevariating transient-state turn-on VGE. The BWLS is designed
to automatically find the optimal capturing timing because
the maximum sensitivity is achieved if the VGE is held whencollector current varies the most. For function verification, agate driver IC with integrated BWLS is fabricated with 180
nm BCD process. Double pulse test results at 20 A and 80 A
show that the proposed circuit successfully detects thereduction in the number of bond wires from the initial valueof six to one in an IGBT module and achieves an averagesensitivity of 54 mV per wire.
Index Terms-- Bond wire, lift-off detection, gate-emitter
voltage, track-and-hold.

I. INTRODUCTION
In power devices, die-to-die and die-to-pin connections
are built using bond wires. Therefore, the bond wire liftoff detection for power devices is an important technology
to realize reliable power electronic systems [1-15]. The
target of this work is to develop a bond wire lift-off sensor(BWLS) that (1) can be fully integrated into a gate driver
IC without external components for low cost and low area
consumption, and (2) does not require the power device tobe under special voltage or current conditions for bondwire lift-off sensing. Table I shows a summary of previous
works. Methods for detecting bond wire lift-off from onstate voltage drop [11], bond wire parasitic inductance
TABLE I.

[12], collector-emitter resistance [13], short circuit current[14], and reverse body diode voltage drop [15] have been
proposed. However, collector current (IC) measurement
requires a current sensor, and collector-emitter voltage(VCE) measurement requires a high-voltage diode, which
are not suitable for integration into ICs. In addition, [11,14, 15] require special voltage or current conditions, suchas auxiliary power supplies, for bond wire lift-off sensing,which is a problem because it can interfere with theoriginal operation of the power converters. Since there is
no existing study that has achieved the above targets, theBWLS that fulfills both targets is proposed in this paper.
II. PROPOSED FULLY INTEGRATED BOND WIRE LIFT-OFFSENSOR
In this paper, the lift-off of bond wires from the IGBT’s
emitter is discussed. Fig. 1 shows a simplified schematic
illustration of the bond wire lift-off detection. When bondwire lifts off from metal pad, the gate-to-emitter voltage(VGE) waveform varies accordingly due to the parasitic
signal path between gate and emitter. Therefore, it ispossible to design a circuit that senses the VGE variationand then detects bond wire lift-off. Fig. 2 shows the overall
schematic of the proposed IC with integrated BWLS. Agate driver (GD) is included for driving the IGBT moduleand the BWLS senses the voltage difference (VGSS)
between gate terminal of IGBT and IC ground, which is 15
V higher than VGE, and outputs a voltage signal(Sensor_out) that is related to the number of lifted off bondwire. Since VGSS rises rapidly during turn-on, a circuit thattracks and holds VGSS is needed. The track-and-hold circuit
should track VGSS when a turn-on signal arrives and holdthe sensor output at the moment that VGSS varies the mostdue to bond wire lift-off.

COMPARISON TABLE OF BOND WIRE LIFT-OFF
DETECTION METHODS

Reference

[11]

[12]

[13]

[14]

[15]

This work

Target powerdevice

IGBT

IGBT

IGBT

IGBT

SiC MOSFET

IGBT

Physicalquantity thatchanges

RWIRE

LWIRE

RWIRE

RWIRE

RWIRE

LWIRE

Measured value VCE(ON), VF

VGE

VCE(ON), IC, VTH

ISC

VSD

VGE, VeE

Special voltage
or current
conditions

NONO

YES

YES

NO

Discrete

Discrete

Discrete

DiscreteFully
integrated

YES

Implementation Discrete
Sensitivity

VGE

Bond wirelift-off

53 mV/wire 2.8 mV/wire 0.32 mΩ/wire 0.38 A/wire 3.5 mV/wire 54 mV/wire

Fig. 1.

Schematic illustration of bond wire lift-off.

Gate driver (GD) IC with integrated BWLS
15 VINIC

IGBT module

VCeGD
VGE_INT

5V

VeSS

VGE

Bond
wire
lift-off
sensor(BWLS)(Fig. 3)

Sensor_out
T/H_control
VREF
VGSS

Bond
wiresn15 V

Kelvinemitter (E)

LeE

VeE

VSS
VeSS = VeE + 15 V
Fig. 2.

LE(n)Poweremitter (e)VGSS = VGE + 15 V

Overall schematic of gate driver IC with integrated BWLS.

dVeSS/dt
Rising edge
detector

INATT(1/6)

VeSS

Diff

T/H_control

COMP

VREF
ATT(1/8)

VGSS

BUF

BUF

Attenuator (ATT)
Differential circuit (Diff)
Comparator (COMP)
Voltage buffer (BUF)

Sensor_out

Track-and-hold (T/H)

Fig. 3. Circuit schematic of proposed BWLS.

IN
Fig. 5.

VGE, VGSS

Gate driver IC with integrated BWLS.

IGBT
moduleVCeIL

IC
VeE = − LeE

VeE, VeSS
VREF
dVeE/dt, dVeSS/dt

VeE
 dI = − LeE  C dt
 dt Track

T/H_control

2Varies with ntTRACK

GD

VCeVGEtHOLDTiming chart of proposed BWLS.

Figs. 3 and 4 show the detailed circuit schematic andtiming chart of the proposed BWLS, respectively. The
principle of operation of BWLS is explained below.
Eq. (1) describes the relationship between the VGSS andthe number of remaining bond wires (n).
dI
(1)
VGSS = VGE_INT + LE ( n ) C + 15 ,
dt

100 V

LE(n)
…

Hold

Sensor_out

Fig. 4.

Gate driver IC

dI C
dt

Bondwire
lift-off
sensorLeE
VeEICFig. 6. Circuit schematic of double pulse test.

where VGE_INT is the internal gate-emitter voltage, which is
not measurable, LE(n) is the parasitic inductance of bondwires, which is a function of the remaining bond wires’number n, and t is the time variable. A 15 V is added
because BWLS senses voltage between IGBT’s gate
terminal and IC ground.

Fig. 7. Measurement setup.
30 V

VGSS

30 V

15 V
0V
100 V

VCe
ICVeSS0V
40 A
20 A
0A
20 V
15 V
10 V

T/H_control

VGSS

Number of bond wires (n)
n=1
n=2
n=3
n=4
n=5
n=6IL = 20 A

15 V

VCeICVeSS

5V0V
80 A

Steady-state voltage varies with n

Sensor_out

1000

2000

3000

4000

5000

0

Time (ns)28.5 VICVeSS

VGSS

27.5 V
100 V

High sensitivity zone

0V
40 A
20 A
0A
20 V
15 V
10 V

T/H_control

Steady-state voltage varies with n

3V0VCe5V
0V

Sensor_out 4 V

2.5 V

VGSS

IL = 80 A

0A
20 V
15 V
10 V

T/H_control

0V

3.5 V

Number of bond wires (n)
n=1
n=2
n=3
n=4
n=5
n=60V
100 V

VeSS

Hold

5V0V

IC

3.5 V

Sensor_out

2.5 V
300

500

Time (ns)

600

700

4000

5000

Time (ns)High sensitivity zone0V80 A

Hold timing

0A
20 V
15 V
10 V

Sensor_out
400

3000

27.7 V
100 V

T/H_control

Track

2000

28.7 VVCe

Hold timing

1000

Hold5V0VTrack

4V
3V
300

400(a) IL = 20 A

500

Time (ns)600700(b) IL = 80 A

Fig. 8. Measured turn-on waveforms of BWLS with varied n from 6 to 1.

BWLS holds the transient-state turn-on VGSS thatvaries with the change of LE(n), then n can be estimatedfrom the variation of the steady-state track-and-holdoutput named Sensor_out. According to Eq. (1), theBWLS is designed to hold VGSS when dIC/dt is maximum
for the theoretically best sensitivity.
VeE is the voltage difference between Power emitter andKelvin emitter and VeSS is that between Power emitter andIC ground. Instead of VeE, the proposed circuit takes VeSS
as a trigger for holding output, as shown in Figs. 3 and 4.
According to the equations in Fig. 4, the moment whendIC/dt achieves maximum is the same as that when dVeSS/dt= 0, which is detected by a comparator. Then the fallingedge of T/H_control signal is triggered, and the attenuated
VGSS is held. The proposed circuit is compatible with mostof the gate driver IC. In this work, the proposed circuit iscombined with our previous work [16]. For function
verification, a gate driver IC integrated BWLS isfabricated with 180-nm BCD process, and the die photo isshown in Fig. 5. The die size is 2.0 mm by 2.5 mm.
III. MEASURED RESULTS
Fig.6 shows the circuit schematic of the double pulse
test measurement setup. The voltage supply of the powerloop is 100 V. Fig. 7 shows the photo of the measurement
setup. An IGBT module (FS100R12N2T4P, 1200 V, 100A) is selected as the test object and is mounted on a
specially designed PCB. The internal structure of the IGBT
is exposed for easier handling. The load current (IL) ismeasured by the Rogowski coil.

Steady-state Sensor_out (V)

270 mV
Average sensitivity =5= 54 mV/wire

3.2

3.1

3.0

IL = 80 A

270 mV

2.9

IL = 20 A
2.812

3

4

56

Number of bond wires (n)Fig. 9. Measured n dependence of steady-state Sensor_out.

To demonstrate the functionality, BWLS is measured indouble pulse test with the IL of 20 A and 80 A. The initialvalue of n is 6, and n is changed by manually cutting off
the bond wires one by one to emulate the gradual bondwire lift-off failure.
Fig. 8 (a) and (b) shows the measured turn-on
waveforms of BWLS with varied n from 6 to 1 at IL = 20
A and 80 A, respectively. The gate driver uses 15 V forturning on and -15 V for turning off the IGBT module andthe proposed circuit senses the VGSS between gate of IGBTand IC ground, which is 15 V higher than VGE. The VGSSwaveforms almost overlap together except for the IC risingphase, which verifies that the induced voltage across theparasitic inductance LE(n) appears on the VGSS. Whenzooming in the time scale and vertical scale of VGSS, the ndependence of VGSS is clearly observed in the area named
high sensitivity zone, where IC is rising. The blue VGSS
curve, for example, shows the VGSS waveform when there
is only one bond wire left (n = 1).
Although BWLS output varies during turn-on phasebecause of the transient noise and interference, the steadystate Sensor_out clearly shows the waveform dependency
on n, which tells that the BWLS achieves the goal of bondwire detection in a single IC. Comparing the measured
VGSS waveforms at IL = 20 A and 80 A, it can be seen thatIL takes more time to climb to 80 A. Except for theextension of high sensitivity zone, the circuit’s operationis the same for both IL = 20 A and 80 A.
Obviously, as predicted by Eq. (1), the high sensitivity
zone is observed where dIC/dt is approaching maximum
value and VeSS is close to the minimum value at IL = 20 Aand IL = 80 A. The BWLS is designed to achieve highsensitivity by detecting the maximum dIC/dt, which istheoretically the optimal timing for holding VGSS. As
shown in Figs. 3 and 4, the BWLS takes VeSS as input, andthen obtains dVeE/dt (equal to dVeSS/dt), which corresponds
to IC’s second derivative with respect to time, from theattenuated VeSS. Then the maximum dIC/dt is detectedaccording to the zero-crossing point of dVeE/dt. The fallingedge of T/H_control is triggered and indicates the holdtiming, which is depicted as a blue dashed line in Fig. 8 (a)and (b).
Although the noisy transient-state Sensor_out occurs

immediately after the output holding, n can be estimatedfrom the steady-state Sensor_out. Fig. 9 shows themeasured n dependence of steady-state Sensor_out at IL =20 A and 80 A. Sensor_out increases when n decreases,
and the voltage swing of Sensor_out for both IL conditions
is almost the same. With larger IL, Sensor_out tends to behigher. Therefore, n can be estimated more efficiently
from Sensor_out by recording the initial value with n of
six and comparing the measured Sensor_out with theinitial record.
Because of the parallel nature of inductors, the total
inductance does not change much when the first few
bonding wires are cut off. Therefore, the Sensor_out
changes slightly, even the measurement error and noise
could be larger than the voltage difference of Sensor_out.
In this paper, the ratio between the swing of Sensor_out(270 mV) and the number of cut-off bond wires (n = 5) isdefined as the average sensitivity (54 mV/wire) of the bondwire lift-off detection method. Table I shows thecomparison of existing bond wire lift-off detection
methods. This work is the first one that achieves the fully
integrated bond wire lift-off detection in a single IC that
does not require discrete components and special voltage
or current conditions for bond wire lift-off sensing.
IV. CONCLUSIONS
The fully integrated BWLS, which can detect bond wire
lift-off from the VGSS waveform and does not require
special voltage or current conditions, is proposed. The
functionality of BWLS is shown by the double pulse testwith the voltage of 100 V and the current of IL = 20 A and80 A. To increase the sensitivity of BWLS, the turn-on
VGSS waveform is tracked and automatically captured
when VeSS is minimum, concurrently with dIC/dt reachingits maximum value. The captured VGSS is a DC signal,
which is convenient for read-out.
ACKNOWLEDGMENT
This work(JPNP21009).

waspartly

supportedby

NEDO

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