2-2

IEEE Asian Solid-State Circuits Conference
November 8-10,2010 / Beijing, China

A 1-V Input, 0.2-V to 0.47-V Output SwitchedCapacitor DC-DC Converter with Pulse Density andWidth Modulation (PDWM) for 57% Ripple Reduction
Xin Zhang1, Yu Pu1, Koichi Ishida1, Yoshikatsu Ryu2,Yasuyuki Okuma2, Po-Hung Chen1,
Kazunori Watanabe2, Takayasu Sakurai1, and Makoto Takamiya1
1. The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
2. Semiconductor Technology Academic Research Center (STARC), 3-17-2 Shin Yokohama,Kohoku-ku, Yokohama 222-0033, Japanzhangxin@iis.u-tokyo.ac.jp

I.

INTRODUCTION

For emerging ultra-low power SoCs which utilize nearthreshold or sub-threshold supply voltages and draw less than
10mA of current [1-2], a switched-capacitor (SC) DC-DC
converter is a viable choice for its tunable output voltage andthe probability of on-chip full integration [3]. However, thepreviously reported SC DC-DC converters [3-6] often
overlook the effect of output ripple on the sub-thresholddigital circuits.
With the trend of the power supply voltage (VDD) scaling,
power supply ripple is extremely detrimental to their digitalbuilding blocks. This is because the delay of logic circuits isinfluenced by VDD in an exponential way in the sub-thresholdregion. The net result is that a very small amount of injected
ripple can cause a very large delay uncertainty. Fig. 1 clearlyshows such impact of power supply ripples (VRipple) on thefrequency of an FO4-per-stage ring oscillator. The central
frequency fcenter is obtained at VDD = 200 mV. The upper andlower bounds of the frequency, i.e., fmax and fmin, are obtainedat VDD = 200mV + VRipple/2 and VDD = 200mV - VRipple/2,respectively. Note that in Fig. 1, fmax and fmin are normalized tofcenter. As seen, an 80 mV ripple can result in a more than
200% delay uncertainty.

978-1-4244-8298-6/10/$26.00 ®2010 IEEE

In the super-threshold region, the ripple of the DC-DC
converter and ground-bounce noise (also referred to as Ldi/dt
noise) are two major sources of power supply noise at digitalblocks. As VDD scales to the sub-threshold region, the transientcurrent of digital blocks also scales rapidly, in this way
mitigating the ground-bounce noise. However, the problem of
the ripple of the DC-DC converter remains and it even goesseverer with the decreasing output voltage.

Normalized frequency (%)

Abstract—To effectively reduce output ripple of switchedcapacitor DC-DC converters which generate variable output
voltages, a novel feedback control scheme is presented. The
proposed scheme uses pulse density and width modulation(PDWM) to reduce the output ripple with low output voltage.
The prototype chip was implemented using 65nm CMOS
process. The switched-capacitor DC-DC converter has 0.2-V to0.47-V output voltage and delivers 0.25-mA to 10-mA output
current from a 1-V input supply with a peak efficiency of 87%.
Compared with the conventional pulse density modulation(PDM), the proposed switched-capacitor DC-DC converter with
PDWM reduces the output ripple by 57% in the low output
voltage region with the efficiency penalty of 2%.

VDD = 200mV ± VRipple/2350300

fmax

250200150

Conventional
design10050fmin

Target of this work0020406080

VRipple (mV)

100120Fig. 1. Normalized ring oscillator frequency at different power supply
ripples and the target of this work.

Motivated by the above concerns, it is of great importanceto look for solutions which can reduce the output ripple ofswitched-capacitor DC-DC converter which supplies variable
output voltages to the sub-threshold digital circuits.
Interleaving techniques can also be employed for lower ripples[7], however, this method comes with the cost of increased
component count and complicated timing control. Therefore,exploring a more effective control scheme to reduce output
ripple of switched-capacitor DC-DC converter with thevariable output voltages for sub-threshold digital circuits is thefocus of this study.

II.

PROPOSED PDWM CONTROL SCHEME OF SC DC-DCCONVERTER

φCKB
VIN

Fig. 2 shows the architecture of the SC DC-DC converterwith conventional pulse density modulation (PDM). The coreof the system is a switch matrix which contains the chargetransfer capacitors and the charge-transfer switches. A PDM
based control scheme is used to regulate the output voltage tothe desired value with a suitable clock density. The PDM
works as follows: a comparator clocked by the clock (CK) is
used to compare VOUT and VREF. When the output voltage
VOUT is above VREF, the output of comparator, CKpulse is set to0, which means switching signals φCK and φCKB are paused.
When VOUT falls below VREF, the comparator triggers a pulse
on CKpulse, which will be transported to φCK and φCKB, thuscharges up the output load capacitor. The non-overlap clockgenerator is used to prevent any overlap between φCK and φCKB.
The clock buffers are employed to provide drive ability to theswitches in the switch matrix.

φCK

φCKB
C1

φCKB

φCKB

VREF

φCK φCKBφPWVoutLookup
tableIout

Pulse width ctrl
4bits
Buffers

CK
VOUT
VREF

CKpulseNonoverlap
clock
generator

φCK

Pulse
widthcontrol

φPW

(PWM)

φCKB

(PDM)

FabricatedFig. 3. Schematic of proposed method with PDWM.
VREFH >VREFL
VOUT

VOUT

VREFH

VREFL

CKCK

CKpulse(a) Conv. with high VREF

CKpulse(b) Conv. with low VREF
VOUT
VREFH

VREFH >VREFL

VOUT
VREFL

CK

CK

CKpulse

CKpulse(d) Proposed with low VREF

Fig. 4. Waveforms of conventional and proposed method. (a) conventional
PDM with high VREF, (b) conventional PDM with low VREF, (c) proposed
PDWM with high VREF, (b) proposed PDWM with low VREF.

Buffers

CKpulseCOUT ROUT IOUT(c) Proposed with high VREF

φCK φCKBφCK(PWM)

VOUT

C2

VOUT

VOUT

C2

COUT ROUTCK

φCKB
C1With the PDM control scheme, pulse densities of φCK andφCKB are effectively adjusted. The switches are switched lessfrequently as IOUT decreases, thereby reducing the switchinglosses and the power consumed by control circuit. With thePDM control scheme, this converter is able to achieve a highpower efficiency with a wide output current range.
VIN

φPW

Nonoverlap
clock
generator

φCK

φCKB(PDM)

Fig. 2. Schematic of conventional method with only PDM.

However, the conventional PDM architecture suffers fromthe problem of large ripple at low output voltage region. Fig. 3
shows the proposed architecture which employs both PDM
and pulse width modulation (PWM) in the control scheme. In
the proposed scheme, a pulse width control block and a lookup table (LUT) are introduced to the control circuit. Only oneof the switches connected to VIN is controlled by a modulated
pulse signal φPW, because by controlling the pulse width of thisswitch, the power transferred from VIN to the capacitors at
every circle can be precisely controlled. The pulse width ofφPW is modulated by the pulse width control block. A 4-bitcontrol signal is read from a LUT to determine the pulse widthfor φPW, according to different IOUT and VOUT.
Figs. 4 (a) and (b) show the waveform of conventional
method with different VREF’s, and Figs. 4 (c) and (d) show
proposed method. By comparing Figs. 4 (a) and (b), it isobserved that lower VREF causes bigger ripple, because VOUT

is charged to a VIN/2 at every pulse of CKpulse. This implies
that the ripple problem goes severer with the decreasing VREF.
On the other hand, as shown Figs. 4 (c) and (d), proposed
PDWM has a much lower ripple due to the PWM control.
Because variable pulse width can be applied to drive φPW,
shown in Fig. 3, VOUT is now able to be charged to a lower
value than in Figs. 4 (a) and (b), thus reduce the ripple
significantly.
Fig. 5 shows the pulse width control circuit of propose
DC-DC converter. The pulse width is controlled by a delay
generator, with a 4-bit digital input signal. Post-layout
simulation results show that the pulse width control circuit
generates an output with pulse width from 2.7ns to 32.8ns,
with 2.1-ns step.

Delayed timeIN

Delaygenerator

C3 C2 C1 C0Fig. 5. 4-bit pulse width control circuit.

Pulse widthOUT

III.

MEASUREMENT RESULTS AND DISCUSSION
80mV

The proposed SC DC-DC converter is fabricated with
65nm CMOS process, except for the LUT as shown in Fig. 3.
Capacitors C1, C2, and COUT shown in Fig. 3 are implemented
using off-chip ceramic capacitors with values of 4.7nF, 4.7nF,and 47nF, respectively. Fig. 6 shows the chip microphotograph and the layout. The active area of the DC-DC
converter is 0.074mm2.

VOUT=0.2V
Pulse width=33.33ns

100mV
2us(a) Conventional (PDM)

Fig. 7 shows the measured dependence of the power
efficiency on the output current at 0.47-V output voltage. TheDC-DC converter delivers 0.25mA to 10mA output current
from a 1V input supply, with an efficiency higher than 82%,
and a peak value of 87%.

34mV
VOUT=0.2V
Pulse width=2.73ns

100mV
2us

Fig. 8. Measured transient waveform of VOUT of conventional DC-DC
converter and proposed DC-DC converter.

100240μmFig. 6. Chip microphotograph and layout.

Efficiency (%)

0.2V
0.25V
0.3V
0.35V
0.4V
0.45V

57% reduction

604023 mV

2090

VOUT=IOUT=1mA f=15MHz80Ripple (mV)

320μm(b) Proposed (PDWM)

Conv. PDM
(50% duty cycleof 15MHz clock)

Proposed PDWM

87%08505108015 2025 30

3540 45

Pulse width of φPW (ns)75Fig. 9. Measured ripple v.s. pulse width with various VOUT.

VOUT=0.47V f=15MHz7065

Conv. PDM (50% duty cycle) VOUT=

100246LoadIOUT
current(mA)(mA)

8Long10Fig. 7. Measured efficiency v.s. output current with proposed PDWM.

Fig. 8 shows the measured transient waveform of VOUT ofboth conventional and proposed DC-DC converters with 0.2V output voltage and 1-mA output current. Significant ripple
reduction is achieved by the propose DC-DC converter.
Fig. 9 shows the measured output ripple with different
pulse width. The conventional PDM with a 15MHz clock(equals to 33.3ns pulse width) is shown in the right of thegraph. As seen, compared with the conventional PDM, theproposed PDWM greatly suppresses the output ripple,
especially with low output voltage region, because the pulse
width of PDM is too wide for transporting required power tothe output. Fig. 10 shows the same measured ripple of Fig. 9,with regarding to power efficiency. The degradation ofefficiency with lower output voltage is due to the series
resistance of output switches, which can be alleviated bysizing the output switches at different output voltage. As
shown in Fig. 10, the ripple is reduced by narrowing the pulse

Ripple (mV)

080
6040

0.2V
0.25V
0.3V
0.35V
0.4V
0.45VIOUT=1mA
f=15MHz

Pulsewidth
Short

20

Proposed PDWM (Optimum pulse width)

0020

40

60

80

100120Efficiency (%)
Fig. 10. Measured ripple v.s. power efficiency with various VOUT.

width, at the cost of slightly degraded power efficiency. Thatis because narrowing the pulse width also increases the pulse
density, thus increases the power consumption slightly.
Therefore, a group of practical optimum choice on pulse width
was defined by allowing a 2% degradation on power
efficiency as shown in Fig. 10.

The measured optimum pulse width for different IOUT andVOUT is shown in Fig. 11. As observed, the optimum pulse
width tends to increase with increasing IOUT and VOUT, because
there is a larger need of power delivered by the switch matrix,
thus demanding a wider pulse on the switch. The selected
pulse width information is then stored in the LUT. Therefore,for different IOUT and VOUT, the SC DC-DC converter will beconfigured to the optimum output ripple and power efficiency.
10Optimum pulse
width (ns)

IOUT (mA)

8

2.0
3.5
5.06.5
8.0
9.5
11.0
12.5
14.0

64
201
0.20 0.25 0.30 0.35 0.40 0.45

VOUT (V)Fig. 11. Contour of optimum pulse width with regarding to IOUT and VOUT.

Fig. 12 shows the measured output ripple of conventional
and proposed PDWM DC-DC converters with regarding toIOUT and VOUT. Significant reduction of the output ripple isobserved in the whole range of IOUT and VOUT. Moreover, theoutput ripple is more effectively reduced in low output voltage
region (to a peak of 57%). Recall that ripple has a larger
impact on digital circuits at a lower voltage, the proposed DCDC converter provides a promising solution for sub-thresholddigital circuits. The performance the proposed PDWM SC
DC-DC converter is summarized in Table I.
IV.

CONCLUSIONA SC DC-DC converter with PDWM control scheme forhigh power efficiency and low output ripple is proposed andimplemented using 65nm CMOS process. A control scheme
using both PDM and PWM is introduced to enable a highefficiency with wide output current range, and suppress theoutput ripple with low output voltage, respectively. The
proposed SC DC-DC converter has 0.2-V to 0.47-V output
voltage and delivers 0.25-mA to 10-mA output current from a1-V input supply with a peak efficiency of 87%. Comparedwith the conventional PDM, the proposed SC DC-DCconverter with PDWM reduces the output ripple by 57% in thelow output voltage region with the efficiency penalty of 2%.
ACKNOWLEDGMENT

Conventional
（PDM）

80

Proposed(PDWM)

6050

REFERENCES[1]404I OUT)
(m A

1086Ripple (mV)70This work was carried out as a part of Extremely Low
Power (ELP) project supported by the New Energy andIndustrial Technology Development Organization (NEDO).

257% reduction
0 0.20

0.25

0.30

0.40

0.35300.45

V OUT (V)

[2]

[3]

Fig. 12. Measured ripple of conventional and proposed DC-DCconverters with regarding to IOUT and VOUT.
[4]
TABLE I.

PERFORMANCE SUMMARY OF THE PROPOSED CONVERTER
Process

1.2V 65-nm CMOS

Active area

0.074 mm2

Clock frequency

15MHz

Input voltage

1V

Output voltage

0.2~0.48V

Output current

0.25~10mA

Max efficiency

87%

Min output ripple

23mV

[5]

[6]

[7]

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