16-2
315MHz Energy-Efficient Injection-Locked OOK Transmitter and 8.4μW
Power-Gated Receiver Front-End for Wireless Ad Hoc Network in 40nm CMOS
Lechang Liu, Takayasu Sakurai and Makoto Takamiya
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, JapanAbstract
A 315MHz injection-locked OOK transmitter and a powergated receiver front-end for wireless ad hoc network aredeveloped in 40nm CMOS. The developed injection-locked
frequency multiplier for carrier generation by edge
combining achieves 11μW power consumption at 315MHz.
The proposed power-gated low noise amplifier with current
second-reuse technique achieves the lowest power
consumption of 8.4μW with 7.9dB noise figure and 20.5dB
gain in state-of-the-art designs.
Introduction
An ad hoc wireless sensor network refers to a group of
spatially distributed sensors, or nodes, linked by a wirelessmedium to report on the physical world. Sensor nodes areusually powered either by batteries or through energy
harvesting and thus each of the nodes should be implemented
at a minimal power level.
Fig.1 shows the block diagram of the proposed low-powertransceiver for wireless sensor network. The transceiver
operates in a single channel centered at 315 MHz andemploys on-off keying (OOK) modulation. The receiver uses
an envelope detection based architecture that eliminates theneed for a local oscillator and therefore most of the power isconsumed by the front-end low noise amplifier (LNA) andthe carrier generator. In this work a power-gated LNA withcurrent second-reuse technique and an injection-locked
frequency multiplier (ILFM) by edge combining for carrier
generation are proposed to minimize the power.
Power Gated Amplifier with Current Second-Reuse
To archive low noise figure and 50-Ω input match, a large
current is required at the first stage of the front-end amplifier.
Current reuse technique can halve the current by stacking
NMOS and PMOS transistors as amplifying devices [1]. As
shown in Fig. 2, this current can be further reduced to 1/3 byoverlapping the NMOS and PMOS pairs. The outputs of thetwo overlapped MOS pairs are summed in the second low
DC-current stage. Fig. 3 shows the circuit implementation ofthe front-end shunt-feedback LNA with the proposed current
second-reuse technique. Shunt feedback topology can not
only prevent amplitude distortion and self-bias at the firststage but also eliminate the bias voltage generator for thesecond stage. The width of the overlapped transistors in thefirst stage is half of the top and the bottom transistors so the
DC voltages at the overlapped points are VDD/3 and 2VDD/3
respectively which can be used as voltage bias for the second
summing stage.
Power gating is an effective low-power design techniquewhich originally stems from logic circuits where a circuit
block is cut off from voltage supply when the block is notswitching. In [2] power gating is introduced to the design offront-end LNA for pulse receiver. To keep the DC bias point
when the amplifier is cut off, a replica of the amplifier, calledbias keeper is used which dominates the power consumptionofthe receiver [2]. This bias keeper can be eliminated by two
─φ PG controlled capacitors in Fig.3. During start-up, thevoltage of the two capacitors is charged to VDD/3 and 2VDD/3
respectively. When the amplifier is cut off, DC bias voltage
is held on the capacitors dynamically. As shown in Fig.4, this164978-4-86348-165-7

technique can also be applied to the mixer design to enable
fast modulation and thus high energy efficiency.
Injection-Locked Frequency MultiplierPrinciple of conventional injection-locked frequency
multiplier is shown in Fig.5 (a) [3]. Assuming that thenatural running frequency of the oscillator is very close to
the Nth harmonic of the reference, the oscillator will lock tothat harmonic by injecting a stream of current pulses to theoscillator. Problems of conventional ILFM are narrowlocking range and high power consumption. Without off-line
tuning Vtune, the locking range of an 8x 315MHz ILFM inthis way is less than 1MHz. To address these issues, anedge-combing based ILFM is proposed in Fig.5 (b). Fig.6
shows the circuit implementation. The 315MHz output
frequency is achieved by combining the 16-phase edges ofthe eight delay cells. Each of the delay cells [4] operates at
39.375MHz and thus the power is reduced to 1/8 ofconventional way. Since the delay-cell frequency is the sameas reference frequency, wide locking range can be achieved
by full-period forced oscillation instead of narrow-pulse
injection-locked oscillation.
Experimental Results
The proposed injection-locked transmitter and powergated receiver front-end without inductors were designed andfabricated in 40nm CMOS process. Chip micrographs andlayouts of LNA and ILFM are shown in Fig. 7. Fig.8 shows
the measured LNA noise figure and gain. At 315MHz, thenoise figure and gain are 7.9dB and 20.5dB respectively. The
measured transmitter waveforms and receiver front-endwaveforms with 3.12% power-gating duty are show in Fig.9and Fig.10 respectively. The 9.7ns settling time enables fast
modulation in transmitter and fast power-gating in receiver.
As shown in Fig.11, the measured power consumption of theLNA is reduced linearly with the power-gating duty andthereby achieves 8.4μW at 3.12% duty. The frequency
multiplier spectrum and waveforms are shown in Fig.12. The
measured power consumption and locking range of thefrequency multiplier at VDD/2 are 11μW and 5MHz
respectively. Table I and Table II show the comparisons withstate-of-the-art transmitter and receiver front-end LNA. The
proposed power-gated LNA with the current second-reusetechnique achieves the lowest power consumption of 8.4μW
with 7.9dB noise figure and 20.5dB gain.
Acknowledgment
This work was carried out as a part of Extremely Low
Power (ELP) project supported by the New Energy andIndustrial Technology Development Organization (NEDO).
References[1] A. N. Karanicolas, JSSC, vol. 31, pp. 1939-1944, 2002.
[2] A. Tamtrakarn et al., Symp. on VLSI Circuits, pp. 250-251, 2006.
[3] S. D. Toso, et al., JSSC, vol. 43, pp. 2844-2852, 2002.
[4] Y. A. Eken, et al., JSSC, vol. 39, pp. 230–233, 2004.
[5] D. C. Daly, et al., JSSC, vol. 42, pp. 1003–1011, 2007.
[6] D. Linten et al., Symp. on VLSI Circuits, pp. 372-375, 2004.
[7] P. Mak et al., Symp. on VLSI Circuits, pp. 278-279, 2009.
[8] A. Balankutty et al., Symp. on VLSI Circuits, pp.183-184, 2010.

2011 Symposium on VLSI Circuits Digest of Technical Papers

Conventional [1]This Work
LNA

ADC

AMP

Power-Gated
Front-EndCurrent:

RX DataThis Work
Mixer
PA

ILFM

PowerAmplifier

Frequency
Multiplier

Data

Wn/2L

Data

φPG

Data

φPG

Data

VRX

Output

PA

Data

REF+

φ2φ2-2-108μm+......

φ7--7+

φ8 ++

φ8-8Fig. 5. ILFM. (a) Pulse injection. (b) Edge combining.

81μm

103μm

...... φ7 ++(b)Fig. 4. Proposed fast-settling OOK transmitter.

63μm

--Out

Mixer

......

1

φ1∩φ2

Data

Frequency
Reference(39.375MHz)

φ1

φ2

Data

DC Voltage
Holding

Fig. 3. Proposed power-gated receiver front-end.

(a)
InjectedPulse(=φ1)

PowerAmplifierProposed

φPG

InjectedPulse

Vtune

InjectedPulse

VTX

ILFM

CReference

VDD/3

φ1

Wn/3

(a)
(b)
(c)
Fig. 2. Shunt-feedback LNA. (a) Typical. (b) Current reused. (c) Current second-reused.

φPG

φPG

Wn/2

Conventional[3]2VDD/3

Wn/6

Reference

DC Voltage
Holding

φPG

++I/3

I/2

I/2

39.375MHz

315MHzFig. 1. Injection-locked OOK transmitter and power-gated receiver.

++

I/3

I/2

I

Envelope
Detector

Input
Matching

Proposed

I/2+I/2=I

7.9dB+

315MHz......

......

......

......

856μm......

607μm......

......

20.5dB

Edge Combiner
Out (315MHz)

957μm

Fig. 6. Circuit implementation of proposed ILFM.

653μm

Fig. 8. Measured LNA noise figure and gain.

Fig. 7. Chip micrographs. (a) LNA. (b) ILFM.

6001μsPower Consumption (μW)

Data

31.2ns

φPG

120mV

300mV

VRX

VTX

…

VTX

VRX

…

500
400
300
200
1000Settling Time: 9.7ns

...

…

0

2040

60

80

100

Power Gating Duty (%)

Fig. 9. Measured transmitter waveforms.

Fig. 10. Measured LNA waveforms with 3.12% duty.
Table I. TX performance summary.
JSSC’07[5]

ThisWork

Technology

0.18μm

40nm

Voltage

1.8V

1.2V

REF
39.375MHz
OUT
315MHzCarrier

916MHz315MHzData Rate

1Mb/s

1~2Mb/s

Modulation

OOK

OOK

Carrier
Gen.

0.8mW

11μW
@0.6V

Mixer

2.5mW

320μW

Settling Time

270ns

9.7ns

Power

Fig. 12. Measured ILFM spectrum and waveforms.

Fig. 11. Measured LNA power dependency on duty.

Table II. LNA performance summary and comparison.

Technology(CMOS)

VLSI’04[6]

VLSI’09[7]

VLSI’10[8]ThisWork

90nm
90nm

90nm
90nm

65nm
65nm

40nm
40nm

Supply Voltage

0.6V

2V0.6V

1.2V

Frequency

5.5GHz470MHz

900MHz315MHz

Noise Figure

3.2dB

3.9dB

9.9dB

7.9dB

Gain

11.2dB

26.2dB

32.6dB

20.5dB

Architecture
Architecture

Differential
Differential
1-Stage
1-Stage

SingleEnded
2-Stages

Differential
Differential
1-Stage
1-Stage

SingleEnded
2-Stages

Power

2.1mW

10mW

4.8mW

8~598μW

2011 Symposium on VLSI Circuits Digest of Technical Papers

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