Jpn. J. Appl. Phys. Vol. 38 (1999) pp. 2483–2486
Part 1, No. 4B, April 1999c°1999
Publication Board, Japanese Journal of Applied Physics

High-Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET(AB-DTMOS) with Large Body Effect at Low Supply Voltage
Makoto TAKAMIYA1, ∗ , Takuya S ARAYA1 , Tran Ngoc D UYET1 , Yuri YASUDA1,2 and Toshiro H IRAMOTO1,3
1 Institute of Industrial Science, University of Tokyo, 7-22-1 Roppongi, Minato-ku, Tokyo 106-8558, Japan
2 Faculty of Science and Engineering, Chuo University, Kasuga, Bunkyo-ku, Tokyo 112-8555, Japan
3 VLSI Design and Education Center, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan(Received October 6, 1998; accepted for publication December 10, 1998)

A high-performance accumulated back-interface dynamic threshold silicon-on-insulator metal-oxide-semiconductor field
effect transistor (AB-DTMOS) with a large body effect at low supply voltage (Vdd < 0.5 V) is proposed for low-power applications. In AB-DTMOS, the back interface between the non-doped thin SOI and the buried oxide is accumulated by a large
negative substrate bias, and the gate electrode is connected to this electrically induced body. AB-DTMOS realizes an ideal
low/ultrahigh step channel profile electrically and achieves the maximum body effect. At fixed Vth , the body effect factor (γ )of AB-DTMOS is twice as large as that of the conventional uniformly doped channel DTMOS, because the channel depletion
layer width of AB-DTMOS is half that of the conventional DTMOS. Experimental results show a steep subthreshold slope, ahigh current drive due to a large Vth shift, and a suppressed short channel effect.
KEYWORDS: dynamic threshold MOSFET (DTMOS), SOI MOSFET, body effect, low voltage, low power, high performance,
accumulated back-interface

1. Introduction
The most effective approach for reducing power consumption of LSI is supply voltage scaling. The dynamic threshold metal-oxide-semiconductor field effect transistors (DTMOSs) are attractive for very low power applications dueto the ideal subthreshold slope and the high current drive atvery low supply voltage (Vdd < 0.5 V).1–7) In DTMOS, thegate electrode is tied to the body. When the gate is turned
on, Vth is lowered by 1Vth due to the positive body bias andthe current drive is enhanced. Therefore, in order to design
a high-performance DTMOS, a large body effect for large
1Vth is essential. In this paper, we propose a novel accumulated back-interface dynamic threshold silicon-on-insulator
MOSFET (AB-DTMOS), in which a very large body effectis achieved by a thin SOI thickness.
2. AB-DTMOS
Figure 1 shows a schematic view of the proposed ABDTMOS. The back interface between the non-doped thin SOIand the buried oxide is accumulated by a large negative backbias. The buried oxide thickness is determined by a balance
between the source/drain parasitic junction capacitance andthe back bias for the accumulation of back-interface. The
gate electrode is connected to this electrically induced body.
In the pMOS case, all the polarity shown in Fig. 1 is reversed.
In CMOS application, the back gates below the buried oxide
can be fabricated by the ion implantation through the buriedoxide.8, 9) The body effect factors (γ ) of the conventional DTMOS and AB-DTMOS are expressed as eqs. (1) and (2), respectively:¯¯¯ 1Vth ¯tfox¯¯ = CD ∼(1)γ(conventional DTMOS) ≡ ¯=3¯1VClbsfoxchannel depletion layer width, tSOI is the SOI thickness, andtfox is the gate oxide thickness. In the conventional DTMOS, auniformly doped channel profile is assumed, and the channel
depletion layer width is reduced by the high channel doping.
In AB-DTMOS, the channel depletion layer width is equal tothe SOI thickness. Therefore, by thinning the SOI thickness,
AB-DTMOS can reduce the channel depletion layer widthand realize a larger γ , thus, achieving a higher current drive
than the conventional DTMOS.
The accumulated back-interface devices with suppressedshort channel effect have already been proposed as electrically thinned intrinsic channel (ETIC)-SOI MOSFETs,10) in
which the gate is not connected to the body. They have: (1)poor subthreshold slope (> 100 mV/dec) due to a small channel depletion layer width, (2) low current drive due to very
high vertical electric field resulting from low mobility, and(3) severe floating body effect due to accumulated holes atthe back interface. By connecting the gate to the body, ABDTMOS overcomes all the above drawbacks and realizes:(1) an ideal subthreshold slope (60 mV/dec), (2) a high cur-n+ poly-Si
n+n++ + + + ++buried oxidep+ subDC SOI ∼ tfox
(2)
=3C foxtSOI
where C fox is the gate oxide capacitance, C D is the channel
depletion capacitance, C SOI is the SOI capacitance, lD is theVsubγ(AB-DTMOS) =∗ E-mail address: taka@nano.iis.u-tokyo.ac.jp

p-Fig. 1. A schematic view of AB-DTMOS. The back interface between thenon-doped thin SOI and the buried oxide is accumulated by a large negative substrate bias. The gate electrode is connected to this electricallyinduced body.

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Jpn. J. Appl. Phys. Vol. 38 (1999) Pt. 1, No. 4B

rent drive due to a large Vth shift and a high mobility, and(3) no floating body effect. Therefore, the AB-DTMOS has
the advantages of both the ETIC-SOI MOSFET and the conventional DTMOS. In addition, AB-DTMOS suppresses theshort channel effect better than ETIC-SOI MOSFET, because
the drain depletion layer width is reduced by the forward bodybias in DTMOS.
3. Experimental
The AB-DTMOS and the ETIC-SOI MOSFET are compared in the experiment. The devices measured are fully depleted (FD) SOI devices fabricated on a Separation by IMplanted OXygen (SIMOX) wafer.11, 12) The thicknesses ofthe gate oxide, SOI, and buried oxide are 10 nm, 40 nm, and100 nm, respectively. An n+ poly Si gate is used and the channel doping concentration is of the order of 1016 cm−3 . Thedevices have body contact terminals. In order to show theadvantages of AB-DTMOS, we have measured a single device in the three modes shown in Table I. When Vbs = 0 Vand Vsub = 0 V (depleted back-interface), the devices operate in the FD SOI MOSFET mode. When Vbs = 0 V andVsub = −20 V (accumulated back-interface), they operate inthe ETIC-SOI MOSFET mode. When the gate is tied to thebody (Vbs = Vgs ) and Vsub = −20 V, they operate in theAB-DTMOS mode. Figure 2 shows the subthreshold characteristics in the three modes. Vth of ETIC-SOI MOSFETis too high and that of FD SOI MOSFET is too low, but Vthof AB-DTMOS is just between them. Figure 3 shows thesubthreshold characteristics of AB-DTMOS and ETIC-SOIMOSFET where Vbs is varied by 0.1 V steps. The body current of AB-DTMOS is also shown. AB-DTMOS has the sameγ as ETIC-SOI MOSFET, because they have the identical device structures. Therefore γ of AB-DTMOS is derived fromthe Vbs dependence of Vth in ETIC-SOI MOSFET. Derived
γ from Fig. 3 is as high as 0.8, because the ratio of the gate

oxide thickness to the SOI thickness is high. Figures 4 and5 show the Vth rolloff and the subthreshold slope degradationby the short channel effect. The definition of Vth is shownin the inset of Fig. 4. AB-DTMOS has an ideal subthreshold slope and suppresses the short channel effect very well.
In Fig. 6, the on/off characteristics are compared. In this figure, the supply voltage is not 0.5 V but 1.5 V, because Vth ofETIC-SOI MOSFET is 0.9 V. In each device, the gate length
is changed. AB-DTMOS shows a high current drive and alow off-current, while ETIC-SOI MOSFET shows a low current drive and FD SOI MOSFET shows a high off-current.
4. Comparison with the Conventional DTMOSγ of AB-DTMOS and the conventional DTMOS are compared analytically. In the conventional DTMOS, a uniformly
doped channel profile is assumed. Vth for both devices areexpressed as a function of γ ,|VFB1 |(3)Vth (conventional DTMOS) = 2φF1 −1 + 2γ
|VFB2 |(4)Vth (AB-DTMOS) = 2φF2 −1+γ

Ids ,I b (A/ µm)

2484-610Vbs =0.7V
AB-DTMOS-910Ib
L g =1µm
Vds =0.5V
Vsub =-20V0V-12100.00.3

Vgs (V)

Table I. Three operation modes of the devices measured.
Operation mode

Vbs

Fig. 3. Subthreshold characteristics of AB-DTMOS and ETIC-SOI MOSFET where body voltage (Vbs ) is varied from 0 V to 0.7 V by 0.1 V steps.
Body current (Ib ) of AB-DTMOS is also shown. Derived γ is as high as0.8.

VsubFD SOI MOSFET0V0VETIC-SOI MOSFET0V−20 V

AB-DTMOS= Vgs

−20 V

0.6

1.0

ETIC
AB-DTMOSFD-610FDETIC-910AB-DTMOS
L g =0.8 µ m-12Vds =0.5V

10-0.50.00.51.0
V gs (V)

1.5

Fig. 2. Subthreshold characteristics of the FD SOI MOSFET, ETIC-SOI
MOSFET, and AB-DTMOS shown in Table I. The gate length is 0.8 µm.

V th (V)Ids (A/µm)

0.5
0.0

-0.5
-1.00.1

Vth ≡ Vgs @ I ds =W× 10−7 (A)LVds =0.5V
0.31L g( µ m)

Fig. 4. Dependence of Vth on gate length. AB-DTMOS has appropriate
Vth and suppresses the short channel effect well. The definition of Vth isshown in the inset.

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Jpn. J. Appl. Phys. Vol. 38 (1999) Pt. 1, No. 4B

Vds =0.5V
ETIC

100

FD

AB-DTMOS

0.6

Conv.

DTMOS

Vth (V)S (mV/dec)

1502485(t fox =3nm)

0.4

Experiment(t fox =10nm)

0.2

AB-DTMOS+(t fox =10nm) n poly-SiGate

600.1

10.3Lg (µ m)

I off (Vgs =0V)(A/ µm)

Fig. 5. Dependence of subthreshold slope on gate length. AB-DTMOS has
an ideal subthreshold slope and suppresses the short channel effect well.

10-410-610-810-1010-1210-14000.5

1.0body effect factor ( γ )Fig. 7. Dependence of Vth on γ by the simulations for the conventional DTMOS (gate oxide thickness is 3 nm), and AB-DTMOS (gate oxide thickness is 3 nm or 10 nm). In the conventional DTMOS, a uniformly doped
channel profile is assumed. Experimental data (Vth = 0.45 V, γ = 0.8) is
also plotted. γ of AB-DTMOS is twice as large as that of the conventional
DTMOS at a fixed Vth .

FDETIC AB-DTMOS
Vds =1.5V
100 150 200

050Ion (Vgs =1.5V)( µ A/µm)

Fig. 6. On/off characteristics of FD SOI MOSFET, ETIC-SOI MOSFET,and AB-DTMOS. The gate length is varied. AB-DTMOS shows a highcurrent drive and a low off-current. However, ETIC-SOI MOSFET showsa low current drive and FD SOI MOSFET shows a high off-current.

where φF1 and φF2 are Fermi potentials and VFB1 and VFB2 arework function differences. At a fixed Vth , it is expected that γof AB-DTMOS will be twice as large as that of the conventional DTMOS, because the channel depletion layer width ofAB-DTMOS is half that of the conventional DTMOS.13) The
reduction of the channel depletion layer width also leads to a
suppressed short channel effect.
Figure 7 shows the dependence of Vth on γ calculated bysimulation. To vary Vth and γ , the channel doping concentration is changed in the conventional DTMOS and the SOI
thickness is changed in AB-DTMOS. In both devices, the increase in γ leads to an increase in Vth . As discussed above,
AB-DTMOS has a larger γ at a given Vth . It should be notedthat the experimental result (Vth = 0.45 V, γ = 0.8) fits thesimulation very well. The retrograde channel profile has already been proposed in the conventional DTMOS for low Vthand large γ .3) However, the retrograde channel profile always
has a lower γ than that of AB-DTMOS at fixed Vth , because
AB-DTMOS realizes an ideal low/ultrahigh step channel profile electrically and achieves a maximum γ .
The mobility of AB-DTMOS is compared with that of theconventional DTMOS. DTMOS operates at a lower vertical electric field than the conventional MOSFET, because thebody is tied to the gate.1, 2) At a low vertical electric field,

impurity scattering is dominant. An AB-DTMOS with anon-doped channel is possible, because the channel depletion
layer width is determined by the SOI thickness and the channel impurity is not essential. Therefore, AB-DTMOS also
shows a higher mobility than the conventional DTMOS due
to a less impurity scattering. Both large γ and high mobilityin AB-DTMOS result in a higher current drive.
5. Conclusions
We have proposed a high performance AB-DTMOS witha large body effect at low supply voltage. AB-DTMOS hasa thin depletion layer width corresponding to the SOI thickness and an ideal low/ultrahigh channel profile, resulting in
the maximum body effect. Experimental results show a steep
subthreshold slope, a high current drive due to a large Vthshift, and a suppressed short channel effect.
Acknowledgements
This work was partly supported by Japan Society for thePromotion of Science (JSPS) Research for the Future Program and by Grant-in-Aid for Scientific Research on Priority Areas, “Ultimate Integration of Intelligence on Silicon
Electronic Systems” from the Ministry of Education, Science,Sports, and Culture.

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