Session_15_Penmor

1/7/065:00 PMPage 276

ISSCC 2006 / SESSION 15 / ORGANIC DEVICES AND CIRCUITS / 15.4
15.4

An Organic FET SRAM for Braille Sheet Display
with Back Gate to Increase Static Noise Margin

Makoto Takamiya1, Tsuyoshi Sekitani1, Yusaku
Hiroshi Kawaguchi2, Takao Someya1, Takayasu Sakurai1

Kato1,

1

University of Tokyo, Tokyo, Japan
Kobe University, Kobe, Japan

2

Flexible and low-cost organic FETs (OFETs) are suitable forlarge-area applications. An integrated system of OFETs andpressure sensors was reported in [1], and that of OFETs and photodetector was reported in [2]. In this paper, an integrated system of OFETs and plastic actuators is proposed, and a Braillesheet display is demonstrated. Device and process technology ofthe OFETs and the actuators are shown in [3]. This paper presents a newly developed back-gated OFETs SRAM and the circuits
technology for the Braille sheet display to enhance speed, yieldand life time, which will be essential for future large-area electronics made with OFETs. The transition time of the actuator isabout 1s. The Braille sheet display has an actuator array. Whenthe actuator is sequentially driven, it takes more than 1 minuteto change the Braille, which is impractical. The OFETs also haveseveral problems. Manufacturing variation within a plastic filmfor the OFETs is large, which is inherent in large-area applications. OFETs are chemically degraded by the oxygen and moisture in the atmosphere. Threshold voltage (VTH) control process
technology such as an ion implantation is not yet established for
OFETs. To increase the speed of the actuator, OFET SRAM andoverdrive techniques for a driver transistor is proposed. Toachieve a reliable and stable SRAM operation, a VTH control technology using a back gate is developed. A 5-transistor SRAM cellis also developed to reduce the number of bit lines and cell area.
Figure 15.4.1a shows the developed Braille sheet display. Braillecharacters in a 6×4 array are shown on the 4×4cm2 display. Each
Braille character consists of 2×3 dots, and the display has a totalof 144 dots. The Braille character is changed by moving the dots
up and down by means of the actuator, depending on the input
data. As shown in Fig. 15.4.1b, four films (frame, actuator,OFETs driver, and OFETs SRAM) are stacked in the Braille sheet
display. Each Braille dot has an OFET SRAM to compensate forthe slow transition of the actuator. After the input data are written to all SRAMs within 2s, all the actuators are driven at once
using the drivers depending on the data. In this way, the timerequired to change the whole Braille display is reduced from 144s
to 3s.
Figure 15.4.2 shows the circuit of the SRAM and the driver for
one actuator. Only pMOS OFETs are used, because the performance of nMOS OFETs is commonly worse than pMOS. The
OFETs for SRAM have back gates [4] to control VTH. A write-only
SRAM is enough for our Braille application, because the actuatormoves depending on the hold data (DATA, DATAb) and a SRAM
read-operation is not required. Therefore, to save film area, a 5transistor SRAM cell is developed. Compared with a conventional 6-transistor SRAM cell, a 5-transistor SRAM cell reduces thenumber of the bit lines by one-half and reduces the SRAM cellarea by 20%. Figure 15.4.1c shows a micrograph of the 5-transistor SRAM cell. The cell area is 3.7×2.0mm2. The whole cell is covered with the back gate.
In the 5-transistor SRAM cell, of primary concern is the slow
write-time of DATAb, because DATAb has no access transistors.
Our design target for the write-time of the whole SRAM (=144cells) is within 2s. Figure 15.4.3a shows the measured waveforms of DATA and DATAb during a write-operation. When BL islow, the transition time of DATAb is 2ms. In contrast, when BLis high, the transition time of DATAb is 40ms, because the drive
current of M1 in Fig. 15.4.2 is small. This slow transition time
can be hidden in the SRAM system-level by pipelining the writeoperation. Figure 15.4.3b shows the timing chart for the pipeline.
By pipelining, the total write-time for the 12×12 SRAM cells is
reduced from 5.76s (=40 ms×144) to 1.47s (=10ms×143 + 40ms),

276

which satisfies our design target. When row-by-row simultaneous writing is available, the total write-time is reduced from480ms (=40ms×12) to 150ms (=10ms×11 + 40ms).
The VTH control technology using a back gate is shown to compensate for the immature VTH control process technology and toachieve a reliable SRAM operation. Figure 15.4.4a shows themeasured butterfly curves of the SRAM. Back gate voltage(VBGATE) is varied. The inverter gain is 2.7. It is difficult to obtaina larger inverter gain, because the SRAM uses only pMOSOFETs. Figure 15.4.4b shows the measured VBGATE dependenceof the static noise margin (SNM). The power supply voltage, VDD,
is varied and when VDD is 40V, SNM increases as VBGATE increases. In contrast, when VDD is 20V, an optimum VBGATE of 25Vachieves the maximum SNM, because there is an optimum |Vth|for OFETs. Compared with SNM at VBGATE = 0V, by adjusting
VBGATE, SNM increases 2.4 and 2.6 times when VDD is 40V and30V, respectively.
The VTH control technology is also applied to compensate for thechemical degradation of the OFETs and to achieve a reliable
SRAM operation. Figure 15.4.5a shows the measured aging characteristics of the inverter in the SRAM. The OFETs were kept ina nitrogen atmosphere except for the measuring time. As time
passes, the inverter characteristics show a rightward shift due tothe reduced |Vth| of the OFETs. Figure 15.4.5b shows the measured aging characteristics of the inverter compensated by theback gate. Figure 15.4.5c shows the aging characteristics of SNM
calculated based on Figs. 15.4.5a and b. By compensating thereduced |Vth| of OFETs due to the chemical degradation withthe back gate, a constant SNM can be achieved. Because thechemical degradation is inherent in OFETs, the proposed compensation technology is essential to OFET applications.
Manufacturing variation within a plastic film for the OFETs canalso be compensated by dividing the back gate and applying different VBGATE.
Our design target for the transition time of the actuator is within 2s. As shown in Fig. 15.4.2, the actuator has a large capacitance (100µF). The breakdown voltage of the actuator is 3V.
Figure 15.4.6 shows the measured waveforms of the actuator
voltage (VACT) and the actuator displacement. The step voltage
height (VX) of VPL is varied. The required displacement by Brailleusers is 0.2mm. When VPL is equal to the breakdown voltage of 3V, the transition time is 34s, which exceeds our design target. Inorder to reduce the transition time, VPH and VPL overdrive techniques are proposed. By increasing VX from -3V to -10V, the transition time is reduced from 34s to 2.0s, which satisfies our designtarget. In order to avoid a breakdown of the actuator, the overdrive period is determined by the time when VACT is within ±3V.
Finally, an operation of the Braille sheet display is demonstrated.
Figure 15.4.7 shows the measured waveforms of the driver andthe actuator for a Braille dot. Movement of the Braille dot, bothup and down, has been successfully demonstrated. By using
overdrive techniques in VPH and VPL, a 1.6s actuator transition
time is achieved.
Acknowledgements:
The authors acknowledge Prof. M. Doi, University of Tokyo, and Dr. K. Asaka,AIST, for the sheet-type soft actuator made of perfluorinated polymer electrolyte. This work is partially supported by JST, IT program, MEXT, and NEDO.
References:[1] T. Someya et al., “Cut-and-Paste Organic FET Customized ICs forApplication to Artificial Skin,” ISSCC Dig. of Tech. Papers, pp. 288-289, Feb.,
2004.
[2] H. Kawaguchi et al., “A Sheet-Type Scanner Based on a 3D Stacked OrganicTransistor Circuit with Double Word-Line and Double Bit-Line Structure,”
ISSCC Dig. of Tech. Papers, pp. 580-581, Feb., 2005.
[3] Y. Kato et al., “A Flexible, Lightweight Braille Sheet Display with Plastic
Actuators Driven by an Organic Field-Effect Transistor Active Matrix,” IEDM
Tech. Dig., pp. 105-108, Dec., 2005.
[4] S. Iba et al., “Control of Threshold Voltage of Organic Field-Effect Transistors
with Double Gate Structure,” Applied Physics Letters, 87, 023509, July, 2005.

• 2006 IEEE International Solid-State Circuits Conference

1-4244-0079-1/06/$20.00 ©2006 IEEE

Session_15_Penmor

1/7/065:00 PMPage 277

ISSCC 2006 / February 7, 2006 / 10:15 AM

(a)

BL(b)

WL

VDD

4000/50

W/L = 4000Pm/50Pm

DATA

DATAb
OFETs
SRAM

OFETs
driverActuator

M1

OFETs
SRAM

100/50100/50VACT

OFETs
driver

(c)

VPH

BIAS

VSS

Frame

VBGATEpMOS withback gate

4000/50

49000/20

49000/20

Braille dot

100PF

VPL

2.0 mmActuatorEquivalent circuitof actuator

3.7 mmFigure 15.4.2: Circuit of OFETs SRAM and the driver for one actuator.

Figure 15.4.1: (a) (b) Braille sheet display. (c) SRAM cell.

5Ȁ1015Time (ms)(b)

35DATAb

10 ms(10% – 50% delay)
50Time (ms)144 SRAM cells

100

40ms
40ms
40ms
Total write-time = 5.76 s

w/o pipelining
with pipelining

2040ms
40ms
10 ms

(b)

Ȁ
VBGATE– VDD = 0V

40

Static noise margin (SNM) (V)DATA(a)DATA
40 ms (10% – 90% delay)

302520Ȁ

2 ms

BL = highDATAb, DATA (V)Voltage (V)DATAb151050-5-10-15-20-25-300Ȁ

BL = low

151050-5-10-15-20-25-300ȀVoltage (V)(a)VBGATE – VDD = 40V

1510500

VDD = 40V,
VSS = 0V, BIAS = -20V,BL, WL = floating
51015202530

615

52.4x43

VDD = 40V

2.6x21

VDD = 30V
VDD = 20V

0-40 -30 -20 -1035 40010 2030 40

Effective back voltage
VBGATE – VDD (V)DATA, DATAb (V)

74% delay reduction
40ms

1.47 sFigure 15.4.3: (a) Measured write-operation. (b) Pipelining for write-operation.

001020In (V)after 15days(with comp.)

103040001020In (V)3040

VPL (V)

with comp.

VPLDATAb(-20V)

w/o comp.
051015Braille dot

20

Time after fabrication(day)
VDD = 40V, VSS = 0V, BIAS = -20V, BL, WL = floating
w/o compensation : VBGATE – VDD = 0V
with compensation : VBGATE – VDD = 40V

049000/20

VACT

VX

Actuator-1

VX = –3V-2–20V-4
0.8

–20V

0.6

–10V
–5V

17x speeding up

0.40.2

VX = –3V00Figure 15.4.5: Measured aging of inverter and compensation for the aging.

–5V–10V-3

Ȁafter 0 day(w/o comp.)(c)

VPH = floating0Ȁ

1020

8765432
10

VACT (V)after 0 day
7 days10 days
15 days

SNM (V)

Out (V)

30

Ȁ

20(b)

40

Displacementof actuator (mm)Chemicaldegradation30

Out (V)w/o Ȁcomp.

Ȁ(a)

40

Figure 15.4.4: Measured butterfly curves and SNM of SRAM.

51015

20Time (s)

2530

35

40

Figure 15.4.6: Measured accelerated actuator by overdrive techniques.

Continued on Page 653

DIGEST OF TECHNICAL PAPERS •277

ISSCC 2006 PAPER CONTINUATIONSDATADATAb

Displacementof actuator (mm)Voltage (V)

10VPH

VACT

50-5

VPL-100.4

Braille dot isUp

0.2
0-0.2
-0.4
0Down

0.74 s

1.6 s

51015

2025Time (s)Figure 15.4.7: Measured Braille sheet display operation.

653• 2006 IEEE International Solid-State Circuits Conference

1-4244-0079-1/06/$20.00 ©2006 IEEE