IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 59, NO. 6, JUNE 2012

361

A 1-V-Input Switched-Capacitor Voltage
Converter With Voltage-Reference-Free
Pulse-Density Modulation
Xin Zhang, Member, IEEE, Yu Pu, Member, IEEE, Koichi Ishida, Member, IEEE, Yoshikatsu Ryu,Yasuyuki Okuma, Po-Hung Chen, Student Member, IEEE, Kazunori Watanabe,Takayasu Sakurai, Fellow, IEEE, and Makoto Takamiya, Member, IEEE

Abstract—A 1-V-input 0.45-V-output switched-capacitor (SC)voltage converter with voltage-reference-free pulse-density modulation (VRF-PDM) is proposed. The all-digital VRF-PDM scheme
improves the efficiency from 17% to 73% at 50-µA output current
by reducing the pulse density and eliminating the voltage reference
circuit. An output voltage trimming by the hot-carrier injection to
a comparator and a periodic activation scheme of the SC voltage
converter are also proposed to solve the problems attributed toVRF-PDM. The proposed voltage converter is fabricated in 65-nm
CMOS and achieves an efficiency value of 73%–86% at 50 µA–
10 mA output current range.
Index Terms—Offset canceling, pulse-density modulation(PDM), switched capacitor (SC), voltage converter, voltage
reference.

I. I NTRODUCTION

IN RECENT years, exploiting near-threshold and subthreshold circuits has become a major trend in low-power applications, which puts forward more critical requirements for
low-output-voltage, small-area, and high-efficiency voltage
converters. In modern system on chips (SoCs), multiple power
domains are required for various circuit blocks. Fig. 1 shows anexample of an energy-efficient SoC that utilizes energy-efficientnear-threshold logic circuits. Targeting low-power applications,
the SoC system uses a 1-V power supply for the overall system.
The 1-V power supply is directly supplied to analog/RF and I/Ocircuits. In order to utilize near-threshold operation, a voltage
converter is required to generate a 0.5-V power supply from the1-V input for the logic circuits, with 50-µA to 10-mA output
current range and high power efficiency.
Compared with buck/boost dc–dc converters that use inductors, switched-capacitor (SC) voltage converter is a preferable
solution for low-voltage power supplies because of great potential to be fully integrated on-chip. The design challenges
Manuscript received November 9, 2011; revised February 6, 2012; accepted
March 17, 2012. Date of publication May 22, 2012; date of current version
June 12, 2012. This work was carried out as a part of the Extremely Low Power
Project supported in part by the Ministry of Economy, Trade and Industry and inpart by the New Energy and Industrial Technology Development Organization.
This brief was recommended by Associate Editor E. Bonizzoni.
X. Zhang, Y. Pu, K. Ishida, P.-H. Chen, T. Sakurai, and M. Takamiya arewith the Institute of Industrial Science, University of Tokyo, Tokyo 153-8505,
Japan (e-mail: zhangxin@iis.u-tokyo.ac.jp).
Y. Ryu, Y. Okuma, and K. Watanabe are with the Semiconductor Technology
Academic Research Center, Yokohama 222-0033, Japan.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2012.2195056

Fig. 1. Power plan of energy-efficient SoC.

of the SC voltage converter are: 1) the degraded efficiency at
low output current IOUT ; and 2) the implementation of 0.5-V
voltage reference circuit (VREF) and the power penalty due
to VREF. In addition, the design of sub-1-V VREF is difficult because a typical VREF operates above 1 V. In order tosolve the problems, a low-voltage high-efficiency SC voltage
converter with voltage-reference-free pulse-density modulation(VRF-PDM) is proposed for high power efficiency at low IOUT
by both reducing the pulse density and eliminating VREF [1].
II. VRF-PDM
Two major types of conventional SC voltage converters areshown in Fig. 2(a) and (b). The first type in Fig. 2(a) uses
constant pulse density (CPD) for the switch matrix [2]–[4]. In
this scheme, a nonoverlap clock generator is employed to drive
the switch matrix with a fixed clock frequency, as shown inFig. 2(c). Therefore, it suffers from severe efficiency drop when
output current decreases due to excessive clock pulses for small
current demand. Fig. 2(b) shows the other type of conventional
SC voltage converter, which relies on VREF and a comparator
for pulse-density modulation (PDM) [5]–[9]. The comparator
compares the output voltage with the reference voltage to perform PDM. Therefore, the pulse density is adjusted according
to different IOUT , thus preventing the efficiency drop due toexcessive clock pulses, as shown in Fig. 2(c). Note that theVREF is often omitted in the previous works by simply using anoff-chip voltage supply. This way, the power loss introduced by
the VREF is overlooked. Moreover, a sub-1-V voltage reference
may bring extra design complexity to the voltage converter.
Therefore, this scheme costs extra power and area, and it makes
the circuit design complicated with low power supply voltage
due to the use of an on-chip voltage reference.
Fig. 3 shows the proposed VRF-PDM voltage converter anda timing diagram. The key concept of VRF-PDM is to replace1549-7747/$31.00 © 2012 IEEE

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 59, NO. 6, JUNE 2012

Fig. 2. (a) Conventional SC converter with CPD. (b) Conventional SC converter with PDM. (c) Pulse density and efficiency of (a) and (b).

the reference voltage in Fig. 2(b) with the past output voltage
VOUT , thereby eliminating VREF. The proposed scheme uses
two sampling clocks, i.e., CK and CKUPDATE , to sample output
voltage at different times. VOUT is sampled as VNOW andVPAST at each falling edge of CK and CKUPDATE , respectively.
Then, sampled voltages VNOW and VPAST are compared by
a comparator with an offset voltage of ΔV . When VPAST −VNOW is larger than ΔV , the comparator output COMP_outis set to high, and then an expanded pulse signal is generated
as SC_enable. Applying an AND gate to CK and SC_enable,
a pulse signal SC_clock is to be generated and then fed tothe nonoverlap clock generator to drive the switch matrix.
The CKUPDATE generator is used to generate the required
CKUPDATE from CK and SC_enable.
Fig. 4 illustrates the operation of the proposed VRF-PDM
voltage converter with different IOUT conditions. Two cases oflarge IOUT and small IOUT are shown in Fig. 4(a) and (b),respectively. In both cases, VOUT is at first sampled by CKand CKUPDATE and stored as VNOW and VPAST , respectively.
Then, VOUT goes down due to the current load. VNOW always
tracks VOUT with the sampling frequency of CK. A comparator
with offset voltage ΔV is used to compare VNOW and VPAST
with the sampling frequency of CK. Whenever VPAST − VNOW
is bigger than ΔV , a pulse of SC_enable is generated to evoke
the switch matrix. Note that the pulse of SC_enable is expandedby the pulse expander shown in Fig. 3 so that VOUT is assured tobe fully charged up within each SC_enable pulse signal. At theend of each SC_enable pulse signal, CKUPDATE is generated
by the CKUPDATE generator to store the recharged VOUT as a
new VPAST . Comparing Fig. 4(a) and (b), it is clearly observedthat the pulse density of the switch matrix is modulated by theproposed VRF-PDM.
However, in the case of a very small or no output current, VRF-PDM will be problematic because the leak current
on the sampling capacitor of VPAST will not be negligible,
then the stored VPAST will slowly go down. As shown inFig. 5(a), VPAST is slowly decreasing together with VNOW ;hence, VPAST − VNOW is always less than ΔV and SC_enable
will be never triggered by the comparator. As a result, there will
be no pulse for the switch matrix and VOUT will continuously
go down to 0 V due to the output current.

Fig. 3. (a) Block diagram of proposed SC voltage converter with VRF-PDM.
(b) Timing diagram.

Fig. 4.

Operation of proposed SC voltage converter with different IOUT .

In order to avoid abnormal VOUT lowering, a periodic activation scheme (PAS) of the SC voltage converter is proposed. Thetiming diagram of the proposed PAS in VRF-PDM is shownin Fig. 5(b). A 5-bit counter is embedded in PAS; even if
COMP_out is always low, SC_enable and CKUPDATE pulses
are generated at every 32 clock cycles. Because the SC_enable
pulse activates the switch matrix, VOUT is charged up to VIN /2.
After this, CKUPDATE is generated and VPAST is refreshed to
the new VOUT . This way, the output voltage will be recharged
rather than smoothly lowering to 0 V, preventing the abnormal
VOUT lowering problem. Fig. 6 shows the pulse density ofVRF-PDM with PAS in comparison with the conventional
CPD [see Fig. 2(a)] and PDM [see Fig. 2(b)]. Three dots inFig. 6 correspond to Figs. 4(a) and (b) and 5(b). The proposed

ZHANG et al.: SWITCHED-CAPACITOR 1-V-INPUT VOLTAGE CONVERTER WITH VRF-PDM

Fig. 5. (a) Abnormal VOUT lowering problem. (b) Proposed PAS to solve theVOUT lowering problem.

Fig. 6.

363

Fig. 7. Comparator with offset trimming by hot-carrier injection.

Analysis of pulse density of conventional and proposed schemes.

VRF-PDM with PAS has the same pulse density with theconventional PDM except for a lower bound at very low IOUT .
III. O FFSET T RIMMING BY H OT-C ARRIER I NJECTION
In the proposed VRF-PDM converter, VOUT is determined
by ΔV because the trigger voltage is set by the offset voltage
ΔV of the comparator. In order to enable VOUT tuning andthe compensation for the random mismatch of the comparator
without fuse trimming, a novel trimming method with a hotcarrier-injected (HCI) comparator is proposed. Fig. 7 shows aschematic of the HCI comparator. A clocked comparator withcross-coupled latches is employed because of its low staticpower consumption. Transistors (M3–M5) and two NAND gatesare added to trim the offset between M1 and M2. Two current
paths through input differential pair M1 and M2 are formed by
M4 and M5. By applying a large current through M4 or M5,
the threshold voltage VTH of M2 or M1 is increased due toHCI, respectively. Fig. 8 shows a flowchart of the trimmingwith the HCI comparator using a tester, and Table I shows biasconditions for Fig. 8. The goal of the trimming is to make thecomparator to flip at IN1 = IN2 + ΔV . At first, the comparator
trip point is checked at IN1 = IN2 + ΔV . Depending on thecomparator output (OUT), VTH of M1 or M2 is increasedusing HCI by applying a high voltage to 1.2-V 65-nm CMOS
transistors. HCI is repeated with a time iteration of 5 s until
the comparator output flips, meaning trimming is finished. Thisway, VOUT trimming is achieved, and the random mismatch ofthe comparator is compensated without the fuse.
On the other hand, the proposed HCI comparator is also effective in terms of offset canceling. By applying HCI trimming
according to the flowchart shown in Fig. 9, ΔV of the comparator can be effectively canceled out. At first, the comparator

Fig. 8. Flowchart of offset trimming with HCI comparator using a tester.
TABLE IB IAS C ONDITIONS FOR FIG. 8

trip point is checked at IN1 = IN2. Depending on the output,
VTH of M1 or M2 is increased using HCI repetitively until thecomparator output flips, meaning offset canceling is finished.
IV. M EASUREMENT R ESULTS AND A NALYSISThe proposed VRF-PDM converter is fabricated with a
65-nm CMOS process. Fig. 10 shows the die micrograph. The
active area of the proposed voltage converter is 240 µm ×330 µm. Off-chip capacitors C1 and C2 in Fig. 3(a) of 4.7 nF
are used in this design due to limited chip area. For fully
integrated implementation in the future, capacitor size should
be reduced by increasing the clock frequency. The proposed

364IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 59, NO. 6, JUNE 2012

Fig. 9. Flowchart of offset canceling with HCI comparator using a tester.
Fig. 11. Measured results of conventional SC converter with CPD and proposed SC converter with VRF-PDM: (a) output voltage; (b) pulse density; and(c) output ripple.

Fig. 10. Chip micrograph.

VRF-PDM can be easily extended to any other switch matrices
with no matter on- or off-chip capacitors. Fig. 11(a) shows
the measured dependence of the pulse density on the output
current of the proposed VRF-PDM converter. The pulse density
linearly goes with the output current until the output current
reaches 3 mA, which indicates good PDM function. Fig. 11(b)shows the measured output voltage versus the output current.
By connecting SC_clock to CK and muting other control blocks
for proposed VRF-PDM, the conventional SC voltage converterwith CPD is also measured for comparison. Fig. 11(c) shows
the measured dependence of the output ripple on the output
current compared with the conventional SC voltage converterwith CPD. A less-than-3-mV ripple increase is imposed to carryout PDM in the proposed VRF-PDM converter.
Fig. 12 shows the measured waveforms of VOUT andSC_enable at different IOUT . Since SC_clock is generated
from CK and SC_enable by an AND gate, the duty cycle of
SC_enable is exactly equal to the pulse density of SC_clock. Byobserving the duty cycle of SC_enable, the pulse density of theSC voltage converter is clearly observed. As IOUT decreases,
the duty cycle of SC_enable also decreases, which shows thePDM operation and corresponds to Fig. 11(a). A ripple of14 mV is observed, which shows ΔV of the measured converter.
Fig. 13 shows the measured trimming of the offset voltage ofthe HCI comparator and the retention characteristics for 6 dies.
The 6 dies are trimmed to different target offset voltages of 50,
100, 150, and 200 mV, respectively. Good linearity is observed
within the total stress time, indicating good controllability oftrimming. The retention after trimming is finished is also measured, and no significant retention is observed. Fig. 14 shows

Fig. 12. Measured waveform of VOUT and CK_enable. (a) IOUT = 0.5 mA;
pulse density = 26%. (b) IOUT = 1 mA; pulse density = 47%.

measured offset canceling of the HCI comparator of 10 dies.
Before offset canceling, due to random mismatch and withindie variation, comparators have large offset varying from −75
to 90 mV. After offset canceling is finished, the offset voltagesof 10 dies are reduced to −3.1 to 3.3 mV. The retention afteroffset canceling is also measured, and no significant retention isobserved. The offset of the comparator due to random mismatch
and within-die variation is effectively reduced.
Fig. 15 shows the measured efficiency versus the output
current of the proposed and conventional schemes. The efficiency of the conventional SC voltage converter with PDM iscalculated based on the measured efficiency of the proposed
scheme, with subtraction of the power consumed by state-ofthe-art low-voltage and low-power (14-µW) band-gap voltage
reference [10]. Severe efficiency degradation is observed on
the conventional scheme with CPD at less than 3-mA output

ZHANG et al.: SWITCHED-CAPACITOR 1-V-INPUT VOLTAGE CONVERTER WITH VRF-PDM

365

TABLE IIP ERFORMANCE S UMMARY

Fig. 13. Measured trimming of offset voltage of HCI comparator (see Fig. 8)
and retention characteristics for 6 dies.

CMOS. By virtue of the proposed VRF-PDM, efficiency issignificantly increased at low IOUT by reducing the pulse
density and eliminating the VREF. A PAS of the voltage
converter is proposed to solve the problem of VOUT abnormal
lowering to 0 V. A comparator with offset trimming by HCI isalso proposed for output voltage trimming. Both offset voltage
trimming and offset canceling have been proven effective bymeasurement with 16 dies. The proposed VRF-PDM voltage
converter provides above 73% efficiency over the output current
range from 50 µA to 10 mA, with a peak value of 86%. An
improvement of efficiency from 17% to 73% is achieved at
50-µA output current.
R EFERENCES

Fig. 14. Measured offset canceling of HCI comparator (see Fig. 9) andretention characteristics for 10 dies.

Fig. 15. Efficiency of (1) conventional SC converter with CPD (measured),(2) conventional SC converter with PDM [calculated from (1)], and(3) proposed SC converter with VRF-PDM (measured).

current. In contrast, the proposed VRF-PDM converter achieves
above 73% efficiency over the IOUT range from 50 µA to
10 mA, with a peak value of 86% at 3 mA. Compared withthe conventional scheme with CPD, an efficiency improvementfrom 17% to 73% is obtained at 50-µA IOUT . The performancesummary of the proposed VRF-PDM converter is shown inTable II.
V. C ONCLUSION
In this brief, a VRF-PDM voltage converter with 1-V input
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