ISSCC 2012 / SESSION 28 / ADAPTIVE & LOW-POWER CIRCUITS / 28.5
28.5

13% Power Reduction in 16b Integer Unit in 40nm
CMOS by Adaptive Power Supply Voltage Control
with Parity-Based Error Prediction and Detection(PEPD) and Fully Integrated Digital LDO

Koji Hirairi1, Yasuyuki Okuma1, Hiroshi Fuketa2, Tadashi Yasufuku2,
Makoto Takamiya2, Masahiro Nomura1, Hirofumi Shinohara1,Takayasu Sakurai2
1

Semiconductor Technology Academic Research Center, Tokyo, Japan,
University of Tokyo, Tokyo, Japan2

Scaling power supply voltages (VDD’s) of logic circuits down to the sub/nearthreshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large
timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower VDD, adaptive VDD control tocope with PVT variations is indispensable for ultra-low voltage circuits. In thispaper, an adaptive VDD control system with parity-based error prediction anddetection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.
In conventional adaptive VDD control systems [1], a critical-path replica is used
for the PWM controller of a Buck converter to control VDD. In ultra-low voltage
logic circuit design, however, the replica approach is not effective, because thedelay mismatch between the actual data path and the critical-path replica is large
due to within-die random delay variations. To address such problems, this paper
proposes an adaptive VDD control managed by PEPD. Figure 28.5.1 shows ablock diagram of the proposed adaptive VDD control system with PEPD andDLDO. Adaptive VDD control is applied to a 16b integer unit (IU). 20 IU’s areimplemented, and the VDD’s of 20 IU’s (VDD(IU)) are regulated by DLDO operating at an external supply voltage (VDD(EXT)). An LDO instead of a Buck converter
or a switched capacitor DC-DC converter is used, because an LDO does not
require an off-chip inductor and provides precise control of the output voltage.
The timing margin of the IU is monitored with PEPD, and a setup error warning
is generated when timing slack is not sufficient. The setup error warning rate iscalculated with a warning rate calculator and an up/down signal from the calculator is given to DLDO to control VDD(IU), according to the warning rate. In thisway, adaptive VDD control at a constant setup error warning rate is achieved. TheDLDO in [2] requires a voltage reference and a comparator, while the proposed
adaptive VDD control is a fully-digital approach, because a voltage reference isnot required, which is important in the ultra-low voltage design.
Figure 28.5.2 shows the proposed PEPD and conventional techniques to predict
setup errors and to detect functional errors in FFs. The proposed PEPD combines a conventional setup error prediction FF and error detection by parity. The
setup error prediction FF [3] is used to monitor the timing margin and predicttiming errors before they actually occur. In adaptive VDD control systems forultra-low voltage logic circuits, high path coverage of in-situ setup error prediction is required, because within-die random delay variations increase as VDD isreduced. The conventional setup error prediction FF, however, can only predicttiming errors on paths where the FF is inserted. In order to achieve high pathcoverage for setup error prediction, many setup error prediction FFs arerequired, resulting in significant area overhead. In contrast, the proposed PEPD
achieves 100% path coverage of setup error predictions, with a 29% increase in
FF count. In addition, functional errors in FFs are also a severe problem in ultralow voltage logic circuits, because such errors determine the minimum operating voltage (VDDmin) [4]. Therefore, the in-situ functional error detection for FFs
is required. By utilizing the parity generators and checkers for setup error prediction, the proposed PEPD also can detect any functional error amongst eachgroup of 4 FFs. The error detection granularity is thus finer than in the conventional parity case, which detects errors among groups of 17 FFs.

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Figure 28.5.3 shows the measured dependence of error or warning rate of the IU
on VDD(IU) at 1.5MHz. In order to check the validity of the setup error warning,
the real setup error is measured with a tester. As VDD(IU) increases, error orwarning rates decrease exponentially. As temperature increases, the required
VDD(IU) decreases. At a fixed rate, VDD(IU) of the setup error warning is higher
than that of the real setup error, because the setup error warning has timing margins of T1+T2, where T1 and T2 represent the delays of the parity generator anddelay buffers in the PEPD shown in Fig. 28.5.2, respectively. Similarly, at a fixedrate, VDD(IU) of the FF error detection is also higher than that of the real setuperror, because the FF error detection has a timing margin of T1. These timingmargins enable accurate prediction of timing errors. In the proposed adaptive
VDD control system with PEPD, VDD(IU) is adaptively controlled such that thesetup error warning rate is held steady at 2×10-4 for a given clock frequency. For
example, when temperature changes from 0°C to 25°C, VDD(IU) adaptively
changes from 407mV to 375mV.
Figure 28.5.4 shows the measured adaptive VDD(IU) control with DLDO at thefixed setup error warning rate of 2×10-4. Dependence of VDD(IU) on clock frequency and temperature are shown in Figs. 28.5.4 (a) and (b), respectively. In Fig.
28.5.4 (a), as the clock frequency increases, VDD(IU) increases. In Fig. 28.5.4 (b),as the temperature increases, VDD(IU) decreases at a fixed clock frequency of6MHz. In this case, the highest VDD(IU) is 560mV in the worst case (slow die and–50°C).
Figure 28.5.5 shows the measured adaptively-controlled VDD(IU) waveform at different clock frequencies of the IU. VDD(IU) with a 5MHz clock is 412mV, while
VDD(IU) with a 6MHz clock is 421mV. When the clock frequency changes from
5MHz to 6MHz, the setup error warning rate sharply increases, which produces
the rise in VDD(IU) by 9mV. In Figs. 28.5.4 and 28.5.5, successful operations ofthe proposed adaptive VDD control are demonstrated.
Finally, we consider the power characteristics of the proposed adaptive VDD control using PEPD and DLDO. In conventional worst-case design, the worst case(=highest) VDD(IU) is 560mV at 6MHz, as shown in Fig. 28.5.4 (b). Therefore,
560mV is applied to all dies in conventional worst-case design. Figure 28.5.6 (a)shows the measured power comparison between conventional worst-casedesign and the proposed adaptive VDD(IU) control with PEPD and DLDO in a typical die at 6MHz and 85°C. The power dissipation of the IU with the proposed
adaptive VDD control is reduced by 38% compared with conventional worst-casedesign. As shown in Fig. 28.5.6 (b), the power and gate overheads of the proposed adaptive VDD control are 7.9% and 12.5%, respectively. When the LDO
switch loss is included, 13% power reduction was achieved. Figure 28.5.7
shows a die micrograph in 40nm CMOS and a performance summary.

Acknowledgements:
This work was carried out as a part of the Extremely Low Power (ELP) project
supported by METI and NEDO.
References:[1] S. Sridhara, et al., “Microwatt Embedded Processor Platform for Medical
System-on-Chip Applications,” IEEE Symp. VLSI Circuits, pp. 15-16, 2010.
[2] Y. Okuma, et al., “0.5-V Input Digital LDO with 98.7% Current Efficiency and2.7-mA Quiescent Current in 65nm CMOS,” IEEE Custom Integrated Circuits
Conf., pp. 323-326, 2010.
[3] T. Nakura, et al., “Fine-Grain Redundant Logic Using Defect-Prediction FlipFlops,” ISSCC Dig. Tech. Papers, pp. 402-403, 2007.
[4] H. Fuketa, et al., “A 12.7-times Energy Efficiency Increase of 16-bit Integer
Unit by Power Supply Voltage (VDD) Scaling from 1.2V to 310mV Enabled byContention-less Flip-Flops (CLFF) and Separated VDD between Flip-Flops andCombinational Logics,” IEEE International Symp. Low Power Electronics andDesign, pp. 163-168, 2011.

978-1-4673-0377-4/12/$31.00 ©2012 IEEE

ISSCC 2012 / February 22, 2012 / 3:15 PM

Figure 28.5.1: Block diagram of a proposed adaptive supply voltage control based on
setup error prediction.

Figure 28.5.2: Proposed parity-based setup error prediction and function error of FF’s(PEPD).

Figure 28.5.3: Measured dependence of error or warning rate of integer unit (IU) onVDD(IU) at 1.5MHz and 0°C, 15°C, and 25°C.

Figure 28.5.4: Measured adaptive VDD(IU) control with on-chip digital LDO at fixed setup
error warning rate.

Figure 28.5.5: Measured adaptively-controlled VDD(IU) waveform at different clock frequencies of IU in Fig. 28.5.4 (a).

Figure 28.5.6: (a) Measured power comparison in typical die. (b) Overhead summary.

DIGEST OF TECHNICAL PAPERS •487

28ISSCC 2012 PAPER CONTINUATIONSFigure 28.5.7: Die micrograph and summary.

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978-1-4673-0377-4/12/$31.00 ©2012 IEEE