26-4
A Voltage-Reference-Free Pulse Density Modulation (VRF-PDM) 1-V Input
Switched-Capacitor 1/2 Voltage Converter with Output Voltage Trimming byHot Carrier Injection and Periodic Activation Scheme
Xin Zhang1, Yu Pu1, Koichi Ishida1, Yoshikatsu Ryu2, Yasuyuki Okuma2, Po-Hung Chen1, Kazunori Watanabe2,Takayasu Sakurai1, and Makoto Takamiya1
1
University of Tokyo, Tokyo, Japan, 2Semiconductor Technology Academic Research Center (STARC), Yokohama, JapanAbstract
A 1-V input, 0.45-V output switched-capacitor (SC) 2:1
voltage converter is developed in 65-nm CMOS. A proposed
voltage-reference-free pulse density modulation (VRF-PDM)
increased the efficiency from 17% to 73% at 50-μA output
current by reducing the pulse density and eliminating thevoltage reference circuit. An output voltage trimming by the
hot carrier injection to a comparator and a periodic activation
scheme of the SC converter are also proposed to solve theproblems attributed to VRF-PDM.
Introduction
Fig. 1 shows an example of block diagram of an energy
efficient SoC. The power supply voltage (VDD) of 1V isconverter to a 0.5-V energy efficient near threshold logic
circuit by a 1/2 voltage converter, while VDD of 1V is directly
supplied to analog/RF and I/O circuits. Instead of a buckconverter, a switched-capacitor (SC) converter is developed,
because the SC converter has a potential to be fully
integrated on a chip. Target of this paper is to develop a 1-V
input 1/2 voltage converter with the output current (IOUT)
from 50μA to 10mA. The design challenges of the 1/2
voltage converter are (1) the degraded efficiency at low IOUT
and (2) the implementation of 0.5-V voltage reference circuit(VREF) and the power penalty due to VREF. Note that
VREF is often omitted in the previous works [1-7] by simply
using an off-chip bias. In addition, design of sub-1V VREF
[8] is difficult, because typical VREF operates above 1V. In
order to solve the problems, a voltage-reference-free pulse
density modulation (VRF-PDM) is proposed to increase theefficiency at low IOUT by reducing the pulse density andeliminating VREF.
Voltage-Reference-Free Pulse Density Modulation
Fig. 2(a) shows a conventional SC 1/2 voltage converterwith a constant pulse density (CPD) [2-4] clock. CPD suffersfrom severe efficiency degradation when IOUT decreases due
to excessive clock pulses. Fig. 2(b) shows an otherconventional SC 1/2 voltage converter, which rely on VREF
and a comparator for pulse density modulation (PDM) [5-7].
VREF has above-mentioned problems. Figs. 2(c) and 3 show
a block diagram and a timing chart of the proposed
VRF-PDM converter, respectively. The key concept ofVRF-PDM is to replace the reference voltage in Fig. 2(b)with the past output voltage (VOUT), thereby eliminating
VREF. VOUT is sampled as VNOW and VPAST at each fallingedge of CK and CKUPDATE, respectively. Then VNOW andVPAST are compared by a comparator with an offset voltageof ΔV. When VPAST – VNOW is larger than ΔV, a pulse of
SC_enable is generated by the comparator to drive the switch
matrix. ΔV determines both the pulse density and VOUT.
VRF-PDM, however, has a risk of VOUT to decreases to 0V,
because VPAST may decrease to 0V due to the leakage currentof the sampling capacitor when IOUT and the pulse density
are very small. In order to avoid the abnormal VOUT lowering,a periodic activation scheme (PAS) of the SC converter isproposed. Fig. 4 shows a concept of PAS in VRF-PDM incomparison with the conventional CPD (Fig. 2 (a)) and PDM(Fig. 2 (b)). 3 dots in Fig. 4 correspond to Fig. 3. In PAS,even if COMP_out is always low, SC_enable pulse isgenerated at every 32 clock cycles as shown in Fig. 3 (c).
Because the SC_enable pulse activates the switch matrix inFig. 2 (c), VOUT goes to VIN/2. After that CKUPDATE is280978-4-86348-165-7

generated and VPAST is refreshed to VOUT. In this way, PAS
prevents the abnormal VOUT lowering problem.
Output Voltage Trimming by Hot Carrier Injection
In the proposed VRF-PDM converter, VOUT is determined
by ΔV. In order to enable VOUT tuning and the compensation
for the random mismatch of the comparator without the fusetrimming, a novel trimming method with a hot carrier
injected (HCI) comparator is proposed. Fig. 5 shows aschematic of the HCI comparator. Transistors (M3-M5) areadded to a clocked comparator to trim the offset between M1and M2. Fig. 6 shows a flowchart of the trimming with theHCI comparator using a tester and Table I shows bias
conditions for Fig. 6. The goal of the trimming is to make thecomparator to flip at IN1=IN2+ΔV. At first, the comparator
trip point is checked at IN1=IN2+ΔV. Depending on thecomparator output (OUT), threshold voltage (VTH) of M1 or
M2 is increased using HCI by applying a high voltage to1.2-V 65-nm CMOS transistors. Until the trimming isfinished, HCI is repeated. In this way, VOUT trimming isachieved without the fuse.
Experimental Results
The VRF-PDM converter is fabricated with a 65-nm
CMOS. Fig. 7 shows the die micrograph. Off-chip capacitors
C1 and C2 in Fig. 2(c) of 4.7nF are used. Fig. 8 shows themeasured dependence of the pulse density, VOUT, and theoutput ripple on IOUT. In VRF-PDM, the pulse density
decreases with the reduced IOUT. ΔV of 25mV is observed inVRF-PDM. Compared with CPD, 3-mV ripple increase isobserved in VRF-PDM due to PDM. Fig. 9 shows themeasured waveforms of VOUT and SC_enable at different
IOUT. As IOUT decreases, the pulse density of SC_enable also
decreases, which shows the PDM operation and corresponds
to Fig. 8(a). Fig. 10 shows the measured trimming of theoffset voltage of the HCI comparator and the retention
characteristics for 6 dies. The offset voltage linearly changes
with the stress time, which indicates a good controllability.
The retention is good for 1 week. Fig. 11 shows themeasured dependence of efficiency on IOUT. The efficiency
of conventional SC converter with PDM is calculated basedon the measured efficiency of the proposed scheme, withsubtraction of the power consumed by state-of-the-art low
voltage and low power (14μW) BGR [8]. Severe efficiency
degradation is observed on the conventional scheme with
CPD at less than 3-mA output current. In contrast, theVRF-PDM converter achieves above 73% efficiency over
IOUT range from 50μA to 10mA, with a peak value of 86% at3mA. Compared with the conventional scheme with CPD, anefficiency increases from 17% to 73% at 50-μA IOUT. Table
II shows the performance summary.
Acknowledgment
This work was carried out as a part of Extremely Low
Power (ELP) project supported by NEDO.
References[1] X. Zhang, et al., A-SSCC, pp. 61-64, 2010.
[2] H. Le, et al., ISSCC, pp. 210-211, 2010.
[3] A. Richelli, et al., ISSCC, pp. 522-523, 2007.
[4] D. Somasekhar, et al., Symp. VLSI Circuits, pp. 196-197, 2009.
[5] J. Kwong, et al., ISSCC, pp. 318-319, 2008.
[6] Y. Ramadass, et al., ISSCC, pp. 208-209, 2010.
[7] T. V. Breussegem, et al., Symp VLSI Circuits, pp. 196-197, 2009.
[8] A. J. Annema, et al., ISSCC, pp. 332-333, 2009.

2011 Symposium on VLSI Circuits Digest of Technical Papers

1VVINφ

Energy efficient SoC

1/2 voltage
converter(This work)
0.5V 50μA-10mA
Near-threshold
Analog/RF
Logic

φB

I/O

Sampled at the falling edge of
CK in Fig. 2(c)CK

Sampled at the falling edge of
CKUPDATE in Fig. 2(c)

OUT

φ φB

VIN

φ

12φB

ΔVOUT1SC_enable

2OUT(c) Small IOUT：φ φB

232 cycles

SC_clockT

CKSwitchmatrix

SC_enable

T×n

CKUPDATE
generator

COMP_out
2T

CK
VPAST

IN1ΔV

IN2VNOWCOMP_out Comparator with

SC_enable

CKUPDATE

SC_enable
T/2

CKUPDATECK

SC_clockoffset trimming by
hot carrier injection

4(c)Fig. 2. (a) Conventional SC converter with constant pulse density (CPD). (b)Conventional SC converter with pulse density modulation (PDM). (c) Proposed SC
converter with voltage-reference-free pulse density modulation (VRF-PDM).

3CKUPDATE

Fig. 3. Timing diagram of proposed SC converter with VRF-PDM.

CK1
CKStart trimming: target offset=ΔV

CK2

Trim_enable

Compare @IN1=IN2+ΔV

VDD

Pulse density (%)

CK1
M4

Periodic activation scheme (PAS)Conventional CPD (Fig. 2(a))

1000

Trim_enable
IN1_selyb

Trim_enable

TABLE I Bias conditions for Fig. 6Compare
Increase VTH of M1 Increase VTH of M2@IN1=IN2+ΔV (HCI to M1 for 5s) (HCI to M2 for 5s)1

2.5

IN1 (V)

0.5 + ΔV

2.50

IN2 (V)

0.502.5

Trim_enable

LHHHH

CK1LL

IN1_sel

XHL

IN2_selXLH

240μm

330μm

00.5

PDM

11.5

22µs(a)2.5

33.5

44.50.5

1141210864201.5233.5

44.55810410000(c)

Conventional with CPD
0123100000

44030
1010μA
0.01

100μA
0.1

SC_enable(b)Fig. 9. Measured waveform of VOUT andSC_enable. (a) IOUT=0.5mA, pulse density=26%.
(b) IOUT=1mA, pulse density=47%.

PDM
with VRF-TABLE II Performance summary
ProcessMPDCP
Dithlwna
iot
ennv
Co

PDM

1mA
1Output
current
Outputcurrent

VOUT

5ith

50

By removing
voltagereference

60

20106

1000000

Totaltime(s) TimeTime
stressafter after
stress(s) (s)Totalstressstresstime

Fig. 10. Measured trimming of offset voltage ofHCI comparator and the retention characteristics
for 6 dies.

70

Proposed

By PDM

Efficiency(%)(%)
Efficiency
1105

14mV
1.0V

Co
nv
ent ionalw

2-500 0 2020 4040 6060

2µs(b)
2.5

Proposed with
VRF-PDM80

ek
we

SC_enable

Output current (mA)

90urs urs
ho 4 ho1021.0V

5VOUT(a)Proposed with
VRF-PDM

200ursho14mVΔV0OUT=L

OUT=H

100% pulse density

1000OUT?

Fig. 6. Flowchart of trimming with HCI comparator
using a tester.

Output current (mA)
Conventionalwith CPD

0.4

50

OUT?
OUT=L

Proposed with
VRF-PDM

0.35

100

Compare @IN1=IN2+ΔV

Finish trimming

Conventionalwith CPD

0.45

150

Compare @IN1=IN2+ΔV

CK2

0.5

0.3

Increase VTH of M2(HCI to M2 for 5s)

OUT

yb

Output current (mA)
Fig. 8. Measured results of conventional SC converter with CPD
and proposed SC converter with VRF-PDM: (a) output voltage (b)pulse density (c) output ripple.

Fig. 7. Chip micrograph.

Offset voltage of comparator (mV)

120100806040200Output ripple (mV)

CK22.5

Output voltage (V)VDD (V)

IN1(=VPAST)OUT=H

Increase VTH of M1(HCI to M1 for 5s)

OUT=H

Fig. 5. Comparator with offset trimming by hot carrier
injection (HCI).
Pulse density (%)

Fig. 4. Concept of periodic activation
scheme (PAS) in VRF-PDM.

yM1

IN2(=VNOW)

M3

Output current (IOUT)

ModeyM2

OUT=LOUT?

M5

Trim_enable
IN2_selProposed VRF-PDM(Fig. 2(c))
Fig. 3(a)Fig. 3(b)Fig. 3(c)Conventional PDM (Fig. 2(b))

Voltagereference

VOUT

Pulse
expander

0.5V
ΔV

Referencevoltage(b)

Non-overlap
clkgen432 samples

SC_enable

CK

COUT ROUT3CKUPDATE

Non-overlap
clkgenSC_clock

0.5V(b) Medium IOUT：

SwitchmatrixC1

C2

3

CKUPDATE

φ φB

φB

4

COUT ROUT

C2(a)

ΔV

VOUT

φB
C1

φB

CK

0.5V

SC_enable

φSwitchmatrixNon-overlap
clkgenVPAST(a) Large IOUT：

VIN

COUT ROUT

C2Fig. 1. Block diagram of energy efficient SoC.

VNOWVOUTφB
C1100%pulse
density

10mA
1065-nm CMOS

Input voltage

1.0V

Output voltage

0.45V

Output current

50μA-10mA

Max. output ripple

14mV

Max. power efficiency

86% at 3mA

Frequency

10MHz

Active area

0.079mm2

Fig. 11. Efficiency of (1) conventional SC converter with CPD(measured), (2) conventional SC converter with PDM (calculated from(1)), and (3) proposed SC converter with VRF-PDM (measured).

2011 Symposium on VLSI Circuits Digest of Technical Papers

281