IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 8, AUGUST 2021

9273

0.55 W, 88%, 78 kHz, 48 V-to-5 V Fibonacci Hybrid
DC–DC Converter IC Using 66 mm3 of Passive
Components With Automatic Change of Converter
Topology and Duty Ratio for Cold-Crank Transient
Yoshitaka Yamauchi , Member, IEEE, Toru Sai , Member, IEEE, Katsuhiro Hata ,and Makoto Takamiya , Senior Member, IEEE

Abstract—For 48 V mild hybrid vehicles, a sub-0.5 W, 48 V-to-5 V
dc–dc converter fulfilling: 1) high efficiency with small volume;2) constant switching frequency of less than 500 kHz to avoid the frequency band of AM radio; and 3) constant output voltage (VOUT )against the sudden drop of input battery voltage (VIN ) under cold
cranking is required. To meet the requirements, a 0.55 W, 88%,
78 kHz, 48 V-to-5 V Fibonacci hybrid (FH) dc–dc converter IC
using 66 mm3 of passive components is proposed. In the FH dc–dc
converter, by adding an inductor and an output capacitor to a 1/5
Fibonacci switched-capacitor (SC) dc–dc converter, the SC dc–dc
converter also works as a buck converter without adding powertransistors. When VIN drops from 48 V to 20 V in 1 ms in theautomotive cold cranking, the FH dc–dc converter cannot keep
5-V VOUT , because the output voltage of the internal 1/5 SC dc–dc
converter drops from 9.6 to 4 V and the internal buck converter
cannot generate 5-V VOUT from 4 V. To solve the problem, a newcontrol method named automatic change of converter topology andduty ratio (ACCD) is proposed. In ACCD, when VIN drops less than
31 V, the converter topology automatically changes from 1/5 SC
dc–dc converter to 1/3 SC dc–dc converter and the duty ratio of thepulsewidth modulation signal automatically decreases 3/5 times,
thereby achieving the constant 5-V VOUT under cold cranking.
To reduce the volume of the FH dc–dc converter, all transistors
and diodes, including ten power transistors, gate drivers, bootstrap
circuits, and the controller, are fully integrated on 4.6 mm × 2.3 mm
IC fabricated with 180 nm BCD process. In the measurements, theproposed 0.55 W, 48 V-to-5 V FH dc–dc converter IC achieved
the highest efficiency (88%) with the smallest volume of passive
components (66 mm3 ) at the lowest switching frequency (78 kHz)
compared with previous publications.
Index Terms—Automotive, BCD technology, cold cranking,Fibonacci, hybrid dc–dc converter.
Manuscript received June 13, 2020; revised October 5, 2020 and December
23, 2020; accepted January 27, 2021. Date of publication February 10, 2021;
date of current version May 5, 2021. Recommended for publication by Associate
Editor T. Qian. (Corresponding author: Yoshitaka Yamauchi.)
Yoshitaka Yamauchi is with the Institute of Industrial Science, The Universityof Tokyo, Tokyo, Japan. He is now with Taiwan Semiconductor Manufacturing
Company (TSMC), Hsinchu, Taiwan (e-mail: yyama@iis.u-tokyo.ac.jp).
Toru Sai is with the Institute of Industrial Science, The University of Tokyo,
Japan. He is now with Tokyo Polytechnic University, Tokyo, Japan (e-mail:sai@iis.u-tokyo.ac.jp).
Katsuhiro Hata and Makoto Takamiya are with the Institute of Industrial Science, The University of Tokyo, Tokyo, Japan (e-mail: khata@iis.u-tokyo.ac.jp;
mtaka@iis.u-tokyo.ac.jp).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TPEL.2021.3058207.
Digital Object Identifier 10.1109/TPEL.2021.3058207

I. INTRODUCTION
HE target of this article is to develop a sub-0.5 W, 48 Vto-5 V step-down dc–dc converter IC for 48 V mild hybrid
electric vehicles. In the mild-hybrid system, the battery voltagechanges from conventional 12 to 48 V, while ECUs (electronic
control units), including processors, memories, and sensors forthe automobile, still require 5 V with less than 100 mA load
current. Therefore, the conventional 12 V-to-5 V dc–dc converter
should be replaced with the 48 V-to-5 V dc–dc converter. The
required step-down ratio increases from 2.4:1 to 9.6:1.
Fig. 1 shows the requirements for the sub-0.5 W, 48 V-to-5 V
dc–dc converter IC for the 48 V mild hybrid vehicles. The highefficiency is required because the heat generation due to the lossof the dc–dc converter will increase the cost and the volume
for the heat sink. The small volume of the dc–dc converter
is also required because the number of ECUs is increasing
with the evolution of cars, though the total space for ECUs isconstant. For sub-0.5 W output power, highly integrated dc–dc
converter IC including power transistors is an effective choice
to achieve the small volume. For the automotive applications,dc–dc converters with the switching frequency (fSW ) of less than
500 kHz [1]–[3] or fSW of more than 2 MHz [4]–[6] are required
to avoid the electromagnetic interference (EMI) with an in-car
radio receiver using the AM frequency band of 500 kHz–1.6
MHz [7], [8]. Constant fSW is also required because fluctuating
fSW in the pulse frequency modulation (PFM) control for thedc–dc converter makes EMI countermeasures difficult [9]. The
most challenging problem for the automotive dc–dc converters
is the undervoltage transients of the input battery voltage (VIN ).
The most severe of the undervoltage transients is known as acold crank, which occurs when the engine is initially started.
As defined in the test standard of the cold cranking for the
automotive dc–dc converters [10], VIN drops from 48 to 20 V
in 1 ms, when the starter motor begins turning over the engine
from a dead stop. Once the engine starts, VIN recovers to its
nominal voltage of 48 V. During the cold-crank transients, theautomotive dc–dc converters must keep the constant 5-V output
voltage (VOUT ).
Table I summarizes possible options to realize a sub-0.5 W,
48 V-to-5 V dc–dc converter IC fulfilling the above-mentioned

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Fig. 1. Requirements for sub-0.5 W, 48 V-to-5 V dc–dc converter IC for 48 V
mild hybrid vehicles.
TABLE IPOSSIBLE OPTIONS TO REALIZE SUB-0.5 W, 48 V-TO-5 V DC–DC CONVERTERIC FULFILLING REQUIREMENTS IN FIG. 1

Fig. 2.

Circuit schematic of 1/8 ladder SC dc–dc converter.

requirements. In Table I, five topologies of the dc–dc converters
are compared from seven separate points of view, including thestep-down ratio in a switched-capacitor (SC) dc–dc converter,
the numbers of power transistors, inductors (L), and flying
capacitors (CFLY ), high efficiency with small volume, regulation
at constant fSW , and constant VOUT under VIN drop from 48 to20 V. The most commonly used buck converter does not achieve
the high efficiency with small volume, because the efficiency
and the volume are the tradeoffs in the buck converter. fSW ofless than 500 kHz requires large inductance, which results in alarge volume inductor. The tradeoffs will be shown in Fig. 20.
In addition, in the buck converter with 5-V VOUT , the efficiency
decreases with increasing VIN from 12 to 48 V, because theswitching loss increases roughly 16 times.
The 48 V-to-5 V SC dc–dc converter will achieve the highest
efficiency with the smallest volume [11], [12] because the energy
density of SMD capacitors is much higher than that of SMD
inductors [13], [14]. As an example, Fig. 2 shows a circuit
schematic of the 1/8 ladder SC dc–dc converter. The SC dc–dc
converter, however, does not achieve the VOUT regulation atconstant fSW and the constant VOUT under VIN drop, because
the step-down ratio is intrinsically determined by the converter
topology.

Fig. 3.

Circuit schematics of (a) 3-level buck converter and (b) ICH [29].

Hybrid dc–dc converters [4], [15]–[28], where inductive dc–
dc converter and capacitive dc–dc converter are merged, arethe strong candidates for the converter fulfilling the abovementioned requirements because the hybrid dc–dc converters
solve the tradeoffs between the efficiency and the volume in thebuck converter. Among a variety of the hybrid dc–dc converters,
a three-level buck converter [4], [26]–[28] and LTC7821 [29]are shown in Table I. In this article, LTC7821 is named as
ICH because an inductor is connected to the half VIN switchingnode in an SC dc–dc converter. Fig. 3 (a) and (b) shows thecircuit schematics of the three-level buck converter and ICH[29], respectively. In Fig. 3(a) and (b), VIN /2 is generated
by a 1/2 SC dc–dc converter and the switching node (VSW )changes between VIN /2 and 0 V. As shown in Table I, in the 48
V-to-5 V conversion, the efficiency of ICH will be higher thanthat of the three-level buck converter, because the number ofserially connected turn-ON power transistors of the three-levelbuck converter when VSW is connected to 0 V, is more than thatof ICH. Specifically, the number of turn-ON power transistors in
Fig. 3(a) is two, while that in Fig. 3(b) is one. In ICH, however,the VSW amplitude of VIN /2 is still too large and a smaller
VSW amplitude will be required for the 48 V-to-5 V conversion
because the required step-down ratio is 9.6:1.
To solve the problems of the previous converters and to meetthe requirements shown in Fig. 1, a 0.55 W, 88%, 78 kHz, 48 Vto-5 V Fibonacci hybrid (FH) dc–dc converter IC using 66 mm3of passive components is proposed in this article.
This article has three major proposed solutions including
topology, control, and implementation of the dc–dc converter.
1) A new converter topology of the FH dc–dc converter is
proposed to achieve a highly efficient 48 V-to-5 V dc–dc
converter with a small volume and a constant fSW of lessthan 500 kHz.
2) A new control method named automatic change of converter topology and duty ratio (ACCD) for the FH dc–dc
converter is proposed to achieve the constant 5-V VOUT
under the cold cranking at constant fSW .
3) A new implementation of the FH dc–dc converter is
proposed. All transistors and diodes of the FH dc–dc
converter, including ten power transistors, gate drivers,
bootstrap circuits, and the controller, are fully integrated

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YAMAUCHI et al.: 0.55 W, 88%, 78 KHZ, 48 V-TO-5 V FH DC–DC CONVERTER IC USING 66 MM3 OF PASSIVE COMPONENTS

Fig. 4. Circuit schematics of (a) 1/5 Fibonacci SC converter, (b) buck converter, (c) cascaded converter, and (d) proposed 48 V-to-5 V FH dc–dc converter.

on IC fabricated with 180 nm BCD process to reduce thevolume of the dc–dc converter.
As shown in Table I, because of the three proposed solutions, the proposed FH dc–dc converter successfully meetsthe requirements shown in Fig. 1. In the measurements, theproposed 0.55 W, 48 V-to-5 V FH dc–dc converter IC achieved
the highest efficiency (88%) with the smallest volume of passive
components (66 mm3 ) at the lowest switching frequency (78kHz) compared with previous publications.
In this article, in Section II, the concept of the proposed FH dc–
dc converter is shown and the operation is analyzed to comparewith conventional converters. In Section III, the circuit designof the proposed FH dc–dc converter IC, including the bootstrap
circuits for gate drivers and ACCD for the cold-crank transient,is shown. In Section IV, chip implementation and measured
results of the proposed FH dc–dc converter IC are shown. In
Section V, the proposed FH dc–dc converter IC is comparedwith the state-of-the-art 48V-to-5V dc–dc converter ICs where
the power transistors are integrated on IC. Finally, Section VI
concludes this article.
II. PRINCIPLE OF PROPOSED FH DC–DC CONVERTER
Fig. 4 shows the circuit schematics of the proposed 48 V-to5 V FH dc–dc converter, merging a 1/5 Fibonacci SC dc–dc
converter and a buck converter. Note that the proposed FH
dc–dc converter is not the cascade connection of the SC dc–dc
converter and the buck converter, as shown in Fig. 4(c). In thecase of the naive cascade connection, the converter’s overall
efficiency is simply determined by the SC efficiency times thebuck efficiency. In the proposed FH dc–dc converter, by adding
an inductor (L) and an output capacitor (COUT ) to VSW of9275

the 1/5 Fibonacci SC dc–dc converter, the SC dc–dc converter
also works as the cascaded converter without adding powertransistors. Compared with the 12 power transistors in Fig. 4(c),the proposed FH dc–dc converter can achieve higher efficiency
because the number of power transistors is ten in Fig. 4(d). The
concept of adding an inductor to the lowest voltage switchingnode in an SC dc–dc converter is similar to ICH in Fig. 3(b). In
this article, the concept is named as ICL, because an inductor isconnected to the lowest voltage switching node in an SC dc–dc
converter, and ICL is shown in Table I. ICL is important toachieve high efficiency in the 48 V-to-5 V conversion, because
the number of turn-ON power transistors is one when VSW isconnected to 0 V, and the conduction loss is minimum. The
difference between ICH and the proposed FH dc–dc converter
is the VSW amplitude. Compared with ICH, the VSW amplitudeof the proposed FH dc–dc converter is reduced from VIN /2 to
VIN /5 to achieve higher efficiency with smaller volume by replacing 1/2 SC dc–dc converter with the 1/5 Fibonacci SC dc–dc
converter. The design procedure of the topology’s selection fromthe system point of view is as follows.
Step 1: The target step-down ratio is 5V/48V = 1/9.8.
Step 2: The proposed hybrid dc–dc converter combining theSC dc–dc converter and the buck converter has adesign constraint that the SC dc–dc converter and thebuck converter need to operate in the same duty cycle.
The typical duty ratio for hybrid dc–dc converters isdetermined as 50%, because the SC dc–dc converter
usually works at a duty ratio of 50%.
Step 3: The conversion ratio of the buck converter inside thehybrid dc–dc converter is half at the duty ratio =50%. Therefore, the conversion ratio for the SC dc–dc
converter inside the hybrid dc–dc converter should be
1/4.8.
Step 4: It is needed to select the SC dc–dc converter topology
with a step-down ratio close to 1/5 and the minimum
number of external CFLY s to minimize the volumeof the off-chip passive components. 1/5 Fibonaccidc–dc converter shown in Fig. 4(a) is the selected
topology with the least number of CCFLY s [30], [31].
The operation principle of the proposed FH dc–dc converter is
explained and analyzed to compare with the conventional buckconverter and ICH. The reason why the two are selected for thecomparison is because in all topologies, the number of seriallyconnected turn-ON power transistors when VSW is connected to
0 V is one. Note that as for multilevel buck converters, such as
3-level converter, the number is two. Hence, it is not included in
the analytical comparison here.
Fig. 5 shows two states of operations of the proposed FH
dc–dc converter. 3/5 VIN is applied to CFLY1 , 2/5 VIN is applied
to CFLY2 , and 1/5 VIN is applied to CFLY3 and CSCOUT . VSW is
1/5 VIN in state A, while VSW is 0 V in state B. Assuming thatthe duty ratio (D) is ideally controlled between 0 and 1, VOUT
is regulated between 1/5 VIN and 0 V. The conversion ratio (M)is shown as follows:
M = VOUT /VIN = D/5.

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(1)

9276

Fig. 5.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 8, AUGUST 2021

Two states of proposed FH dc–dc converter in 1/5 mode.

Note that M is limited between 0.2 and 0 in the proposed FH
dc–dc converter. The inductor current ripples in the conventional
buck converter ΔIL, Buck , that in ICH ΔIL, ICH , and that in the
proposed FH dc–dc converter ΔIL, Proposed , are expressed asfollows:
ΔIL,Buck =VIN(1 − M ) M
LfSW

(2)

ΔIL,ICH =VIN(1 − 2M ) M
LfSW

(3)

ΔIL,Proposed =VIN(1 − 5M ) M.
LfSW

(4)

Fig. 6(a) shows the calculated M dependence of the normalized inductor current ripple (ΔIL ) of the three converters at thesame VIN , L, and fSW . Compared with the conventional buckconverter and ICH, at the target M of 0.1, the proposed FH dc–dc
converter reduces ΔIL by 44% and 38%, respectively. Reduced
ΔIL suggests that the conduction loss due to power transistors
and the inductor is reduced, thereby achieving high efficiency.
Another interpretation of (2)–(4) is possible. The switchingfrequency ratios (KICH and KProposed ) of ICH and the proposed
FH dc–dc converter normalized to the conventional buck converter at the same ΔIL , VIN , and L are defined as follows:
KICH =

fSW,ICH1 − 2M=
fSW,Buck
1−M

KProposed =fSW,Proposed
1 − 5M.
=
fSW,Buck
1−M

(5)
(6)

Fig. 6(b) shows calculated M dependence of KICH and
KProposed at the same ΔIL , VIN , and L. At the target M of 0.1,
KICH and KProposed are 0.89 and 0.56, respectively. Reduced
KProposed suggests that the same efficiency is achieved with the
reduced fSW , which is important to achieve the requirements
shown in Section I.

Fig. 6. (a) Calculated M dependence of normalized inductor current ripple(ΔIL ) of three converters at same VIN , L, and fSW . (b) Calculated M dependenceof KICH and KProposed at same ΔIL , VIN , and L.

III. CIRCUIT DESIGN OF PROPOSED FH DC–DC
CONVERTER IC
A. Architecture
Fig. 7 shows a block diagram of the proposed FH dc–dc
converter IC. The power converter topology is the same as Fig. 4.
VIN of 48V is converted to VSCOUT of 9.8 V by the 1/5 Fibonacci
SC dc–dc converter, and VSCOUT is converted to VOUT of 5 V
by the buck converter (M10 , M8 , and L). VOUT is fed back to
a voltage mode PWM controller with a type-III compensatorfor the regulation of VOUT . The PWM signals are distributed toten power transistors (M1 –M10 ) via the gate signal logic, level
shifters, and the gate drivers. All power supply voltages of thegate drivers for power transistors (M1 , M2 , M4 , M6 , M7 , M9 ,M10 ) are generated by bootstrap circuits, which will be explainedin Section III-B. The ACCD controller and the programmableramp generator are used for ACCD to achieve the constant5-V VOUT under the cold cranking at constant fSW , which
will be explained in Section III-C. All the reference voltages(VREF1 –VREF5 ) are generated by a VREF generator. As shownin Table I, compared with the conventional buck converter, one ofthe design challenges of the proposed FH dc–dc converter is theincreased number of power transistors from two to ten. To avoid
the large volume due to the ten power transistors and related gate

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YAMAUCHI et al.: 0.55 W, 88%, 78 KHZ, 48 V-TO-5 V FH DC–DC CONVERTER IC USING 66 MM3 OF PASSIVE COMPONENTS

Fig. 7.

9277

Block diagram of the proposed FH dc–dc converter IC.

drivers and bootstrap circuits, all transistors and diodes in Fig. 7
are fully integrated on IC to reduce the volume of the dc–dc
converter. All voltages and signals, except for the 5-V power
supply voltage (VDD ) for the controller and the clock signal
for the bootstraps (CLKCP ), are generated on IC. In contrast,
inductor L and all capacitors and resistors, including those forthe compensator, are discrete components placed in the PCB,
which will be explained in Section IV.

B. Bootstrap Circuits for Gate Drivers
One of the design challenges of the proposed FH dc–dc converter is how to generate seven different power supply voltagesof the gate drivers for the power transistors (M1 , M2 , M4 , M6 ,M7 , M9 , and M10 ) because the source voltages of the powertransistors is not 0 V. For each power transistor (M1 , M2 ,M4 , M6 , M7 , M9 , and M10 ), the power supply voltage for thegate-to-source voltage of 5 V is required.
In the previously published 1/5 Fibonacci SC dc–dc converter[33], ten isolated dc–dc converters are used to generated thepower supply voltages of the gate drivers for ten power transistors, which is unacceptable in this article, because ten bulkytransformers will increase the volume of the dc–dc converter.
In the previously published 1/11 SC dc–dc converter [11], an
additional fully integrated ladder SC dc–dc converter is used
to generate the power supply voltages of the gate drivers. The
large area overhead due to the ladder converter, however, is not
acceptable, because the ladder converter occupies roughly half

the die area of the main 1/11 SC dc–dc converter, which will
increase the cost of IC.
To solve the problems, in this article, a new integrated bootstrap circuit for the FH dc–dc converter IC is proposed. In
Fig. 7, two types of bootstrap circuits are required. For the powertransistors (M4 , M7 , and M10 ), the conventional bootstrap circuit
works, because the source voltages of the power transistors areconnected 0 V in state A or state B, as shown in Fig. 5. In
contrast, for the power transistors (M1 , M2 , M6 , and M9 ), theconventional bootstrap circuit does not work, because the source
voltages of the power transistors are not connected 0 V and a newbootstrap circuit is required. For example, VBOOT1,M1 for M1
in Fig. 7 should be 53 V (= 48 V + 5 V) when VC1,POS is 48 V
in state A in Fig. 5, while VBOOT1,M1 should be 33.8 V (= 28.8
V + 5 V) when VC1,POS is 28.8 V (= VIN x 3/5) in state B.
To generate VBOOT1,M1 of 33.8 V, a new bootstrap circuit is
proposed.
Fig. 8 shows the proposed bootstrap circuit for the powertransistors (M1 , M2 , M6 , and M9 ). Fig. 8 (a)–(c) shows the circuit
schematic, input and output connections of the bootstrap circuit,and operating waveforms, respectively. In Fig. 8(a), high-voltage
Schottky diodes are also integrated on IC. For example, in orderto generate VBOOT1,M1 of 33.8 V for M1 , the input of Fig. 8(a)is connected to VC2,POS in Fig. 7, and the output of Fig. 8(a) isconnected to VBOOT1,M1 in Fig. 7. VC2,POS changes between
2/5 VIN and 3/5 VIN , as shown in Fig. 8(b) and (c). In Fig. 8(a),the maximum voltage of the input (VSW ) is sampled in CB,1 andthe maximum voltage is equal to 3/5 VIN (= 28.8 V). Using CB,2and the 800-kHz clock signal (CLKCP ), VY changes between

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Fig. 9. Converter topology change from 1/5 mode to 1/3 mode in the proposed
FH dc–dc converter.

Fig. 8. Proposed bootstrap circuit for power transistors (M1 , M2 , M6 , andM9 ). (a) Circuit schematic. (b) Input and output connections of the bootstrap
circuit. (c) Operating waveforms.

28.8 and 33.8 V (= 28.8 V + 5 V), as shown in Fig. 8(c). The
maximum voltage of VY is sampled in CB,3 and the output
voltage (VBOOT1,M1 ) of 33.8 V is successfully obtained. Ina similar way, VBOOT1,M2 , VBOOT1,M6 , and VBOOT1,M9 are
obtained by changing the input connection, as shown in Fig. 8(b).
The proposed bootstrap circuit for VBOOT1,M6 , and VBOOT1,M9
is shared.
A sophisticated point of the proposed bootstrap circuit is thatexisting switching nodes in the FH dc–dc converter are used forthe input of the bootstrap circuit. For example, VC2,POS is used
for VBOOT1,M1 , and note that M1 is far from VC2,POS , as shownin Fig. 7.
C. ACCD for Cold-Crank Transient
As shown in Section I, the most challenging problem for the
automotive dc–dc converters is the cold-crank transients where
VIN drops from 48 to 20 V in 1 ms. During the cold-crank transients, the automotive dc–dc converters must keep the constant5-V VOUT . As shown in Fig. 9, one of the issues of the proposed
FH dc–dc converter is that the FH dc–dc converter cannot keep
5-V VOUT under cold cranking, because VC3,NEG drops from
9.6 V (= 48 V/5) to 4 V (= 20 V/5) and the buck converter (M10 ,
M8 , and L) cannot generate 5-V VOUT from 4 V.

To solve the problem, ACCD is proposed. In ACCD, when
VIN drops less than 31 V, both the converter topology and the
duty ratio of the PWM signal automatically change. Specifically,
the converter topology changes from 1/5 SC dc–dc converter to
1/3 SC dc–dc converter and the duty ratio of the PWM signal
decreases 3/5 times, thereby achieving the constant 5-V VOUT
with constant fSW under cold cranking. The duty ratio change,
as well as the converter topology change, is required, because
the converter topology change suddenly increases VC3,NEG 5/3
times and VOUT is suddenly increased. Subsequently, when VIN
recovers more than 31 V, the converter topology changes from
1/3 SC dc–dc converter to 1/5 SC dc–dc converter and the duty
ratio of the PWM signal increases 5/3 times. As shown in Fig. 7,
VIN drop is detected by the ACCD controller by monitoring
VSCOUT , and the ACCD controller gives the topology control(TC) signal to a gate signal logic and a programmable ramp
generator to change both the converter topology and the duty
ratio.
The circuit implementation of ACCD is explained. Fig. 9shows the converter topology change from 1/5 mode to 1/3
mode in the proposed FH dc–dc converter. By always turning
ON M1 and M3 and turning OFF M4 , 1/5, the Fibonacci SC dc–dc
converter changes to 1/3 Fibonacci SC dc–dc converter. In 1/3
mode, under cold cranking, the FH dc–dc converter can keep 5-V
VOUT under cold cranking, because the amplitude of VC3,NEG
of 6.7 V (= 20 V/3) is larger than 5 V. In 1/3 mode, the proposedbootstrap circuit, shown in Fig. 8, still works. In 1/3 mode,though the efficiency of the FH dc–dc converter is degradedby the always-ON M1 , the efficiency degradation is not an issue,
because cold cranking is an instant event.
Fig. 10 shows a circuit schematic of the ACCD controller. To
detect VIN drop, resistor-divided VSCOUT is sample-and-heldand compared with VREF3 by a clocked comparator, because
VC3,NEG is the most important node for the buck converter, andAuthorized licensed use limited to: University of Tokyo. Downloaded on August 19,2021 at 23:32:03 UTC from IEEE Xplore. Restrictions apply.

YAMAUCHI et al.: 0.55 W, 88%, 78 KHZ, 48 V-TO-5 V FH DC–DC CONVERTER IC USING 66 MM3 OF PASSIVE COMPONENTS

Fig. 10.

Circuit schematic of ACCD controller.

Fig. 11.

State machine in ACCD controller.

VSCOUT is the dc voltage that determines VC3,NEG . VREF3 isdesigned to detect 80% duty ratio of VC3,NEG , which corresponds to VIN of 31 V (= 5 V/0.8 × 5). Fig. 11 shows a statemachine in the ACCD controller. At first, the state machine isin 1/5 mode and TC = 0. When VIN drops less than 31 V, X1changes from 0 to 1 and TC changes from 0 to 1. As a result, thestate machine changes from 1/5 mode to 1/3 mode, the converter
topology changes from 1/5 SC dc–dc converter to 1/3 SC dc–dc
converter, and the duty ratio of the PWM signal decreases 3/5
times. When VIN recovers more than 31 V, X2 changes from 0
to 1, TC changes from 1 to 0, and the state machine changes
from 1/3 mode to 1/5 mode.
Fig. 12(a) shows a circuit schematic of the programmableramp generator, which is a relaxation oscillator where a capacitor(CRAMP ) is charged by a constant current (IRAMP ), and theoutput (VRAMP ) is reset to 0 V when VRAMP crosses VREF4 or
VREF5 . The design target of the programmable ramp generator
is to change the duty ratio of the PWM signal 3/5 times or
5/3 times with constant fSW depending on the TC signal. For
example, to decrease the duty ratio of the PWM signal 3/5 times
at constant fSW , both the gradient and the amplitude of VRAMP
is increased 5/3 times. The gradient of VRAMP is increased
5/3 times by increasing IRAMP 5/3 times and the amplitude of
VRAMP is increased 5/3 times by changing VREF4 to VREF5(= 5/3 × VREF4 ). Fig. 12(b) shows a timing chart of the FH
dc–dc converter with and without the proposed duty ratio change
under cold cranking. When VIN drops less than 31 V under cold
cranking, TC changes from 0 (1/5 mode) to 1 (1/3 mode) and
VSCOUT increases 5/3 times. Without the proposed duty ratiochange, VOUT shows overvoltage transient due to the increaseof VSCOUT . In contrast, with the proposed duty ratio change,
VOUT shows small overvoltage transient, because the increaseof VSCOUT is canceled by the 3/5 times duty ratio change.
Fig. 13 shows the simulated VOUT waveforms with andwithout the proposed duty ratio change under cold cranking. The
proposed duty ratio change successfully reduces VOUT transientfrom +490 mV/−0 mV to +81 mV/−200 mV.

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Fig. 12. (a) Circuit schematic of programmable ramp generator. (b) Timing
chart of FH dc–dc converter with and without the proposed duty ratio change
under the cold cranking.

Fig. 13. Simulated VOUT waveforms with and without the proposed duty
ratio change under topology change during cold cranking.

IV. CHIP IMPLEMENTATION AND MEASUREMENTS
Fig. 14 shows a micrograph of the proposed FH dc–dc converter IC, including ten power transistors, gate drivers, bootstrap
circuits, and the controller, fabricated with a 180-nm BCD
process. To reduce the volume of the FH dc–dc converter, alltransistors and diodes are fully integrated on a 4.6 mm × 2.3

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Fig. 14. Micrograph of the proposed FH dc–dc converter IC fabricated with180 nm BCD process.
TABLE IIDETAILS OF INDUCTOR AND CAPACITORS

Fig. 15. DC bias dependence of capacitance of 10-µF capacitors used for
CFLY1 , CFLY2 , and CFLY3 .

Fig. 16. Partly enlarged photograph of PCB for the proposed FH dc–dc
converter IC.

mm IC. In the IC implementation, three types of transistors
are used. Lateral double-diffused MOSFETs (LDMOSs) with the
60-V rated drain-to-source voltage and the 5-V rated gate-tosource voltage are used for nine power transistors except forM8 . LDMOS with the 20-V rated drain-to-source voltage andthe 5-V rated gate-to-source voltage are used for M8 because
the drain-to-source voltage of M8 is less than 9.8 V (= 1/5 VIN )and the 20-V rated LDMOS has lower ON-resistance than the
60-V rated LDMOS at a fixed IC area. MOSFETs with the 5-V
rated drain-to-source voltage and the 5-V rated gate-to-source
voltage are used for all circuits except ten power transistors.
An inductor (L) and all capacitors are put on PCB. In total,
21 capacitors shown in Figs. 7 and 8 are used. Table II shows
the model number, value, rating, size, and equivalent series
resistance (ESR) of the inductor and the capacitors. The sizeof the capacitors is 1.6 mm × 0.8 mm × 0.8 mm. Note that ESRof L is much higher than that of the capacitors, which indicatesthat using a lot of capacitors will not degrade the efficiency ofthe hybrid dc–dc converter.
Also note that the capacitance value in Table II is not actually available in the FH dc–dc converter, because the ceramic
capacitors have bias-dependence [11]. Fig. 15 shows the dc bias
dependence of the capacitance of the 10-µF capacitors used for
CFLY1 , CFLY2 , and CFLY3 . The 10-µF capacitor is the maximum capacitance in the 35-V-rated 1608 ceramic capacitors. A

substantial decrease from the initial value (10 µF) is observed,
0.61 µF at 28.8 V (= 3/5 VIN ) for CFLY1 , 0.95 µF at 19.2 V(= 2/5 VIN ) for CFLY2 , and 1.9 µF at 9.6 V (= 1/5 VIN ) for
CFLY3 . While the capacitance dependence on dc bias voltage isunavoidable in every ceramic capacitor, the choice of identical
10 µF capacitors results in CFLY1 : CFLY2 : CFLY3 = 0.61 µF:
0.95 µF: 1.9 µF. As stated in [11], interestingly, the ratio isaccidentally similar to the optimal ratio of CFLY1 : CFLY2 : CFLY3= 1:1:2 derived from the charge vector analysis theory [32].
Fig. 16 shows a partly enlarged photo of the PCB for the
proposed FH dc–dc converter IC. Note that CFLY1 , CFLY2 , and
CFLY3 are placed on the backside of the PCB to minimize theparasitic resistance of PCB.
A. Efficiency
Fig. 17 shows the measured output current (IOUT ) dependenceof the efficiency of the proposed FH dc–dc converter IC at VINof 48 V, VOUT of 5.08 V, and fSW of 78 kHz. IOUT is varied from10 to 110 mA. The quiescent power of the controller of 6.3 mW(= 5 V × 1.26 mA) is included in the efficiency measurement.
Peak efficiency of 88% is obtained at IOUT of 90 mA. At thedesign target of IOUT of 100 mA, the efficiency is 87%.
Fig. 18(a) and (b) shows the measured waveforms of VIN ,VOUT , VRAMP , and VC3,NEG at IOUT of 20 and 100 mA,

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YAMAUCHI et al.: 0.55 W, 88%, 78 KHZ, 48 V-TO-5 V FH DC–DC CONVERTER IC USING 66 MM3 OF PASSIVE COMPONENTS

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Fig. 17. Measured IOUT dependence of efficiency of the proposed FH dc–dc
converter IC.

Fig. 18. Measured waveforms of VIN , VOUT , VRAMP , and VC3,NEG at
IOUT of (a) 20 mA and (b) 100 mA.

respectively, at VIN of 48 V and fSW of 78 kHz. VOUT is
successfully regulated to 5.08 V at IOUT of 20 and 100 mA.
Note that the duty ratio of VC3,NEG increases from 50.8% [seeFig. 18 (a)] to 52.3% [see Fig. 18 (b)] for the VOUT regulation.
B. VOUT Regulation Under Cold Cranking
To demonstrate the effectiveness of the proposed ACCD
control to achieve the constant 5-V VOUT under cold cranking atconstant fSW , VOUT is measured under cold cranking. Fig. 19(a)and (b) shows the measured waveforms of VIN , VOUT , VRAMP ,and VC3,NEG under the cold cranking at IOUT of 10 mA without
and with the proposed ACCD, respectively. VIN drops from48 to 20 V in 1 ms as the defined test specification of cold
cranking [10]. Without the proposed ACCD in Fig. 19(a), after
VIN crossed 25 V (= 5 × 5 V), VOUT drops to 0 V, because theduty ratio of VC3,NEG reaches 100% and the PWM regulation
loop fails to work, as explained in Section III-C. In contrast, withthe proposed ACCD in Fig. 19(b), when VIN drops less than 31 V,
the converter topology automatically changes from 1/5 mode to
1/3 mode and the duty ratio of VC3,NEG automatically decreases
3/5 times by increasing both the gradient and the amplitude of
VRAMP 5/3 times, as explained in Section III-C. Note that thecold-crank transient is a phenomenon in which the input voltage
VIN drops from 48 to 20 V in 1 ms [10]. Thus, VIN does not keepa constant voltage around 31 V. Even if VIN remains around 31 V,

Fig. 19. Measured waveforms of VIN , VOUT , VRAMP , and VC3,NEG undercold cranking at IOUT of 10 mA. (a) Without ACCD (neither topology change
nor duty change). (b) With proposed ACCD (both topology change and dutychange).

mode transitions between 1/5 mode and 1/3 mode continue tooccur because trigger signals in the mode transitions X1 andX2 are generated from different threshold voltages VREF2 andVREF3 , as in Fig. 10. Thus, the proposed ACCD controller does
not cause the output voltage disturbance. In Fig. 19(b), the sudden increase of VC3,NEG because of the topology change, and thesudden increase of VRAMP because of the increased amplitude
are clearly observed. Because of the proposed ACCD control, theconstant 5-V VOUT with constant fSW under the cold cranking
is achieved. In Fig. 19(b), the measured VOUT transient is +214
mV/−323 mV. The VOUT transient discrepancy between themeasurement in Fig. 19(a) and SPICE simulation in Fig. 13(solid line) is due to the dc bias dependency of flying capacitors
CFLY1 , CFLY2 , CFLY3 , and CSCOUT . For example, in the cold
crank, as shown in Fig. 9, the circuit topology switches from

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TABLE IIICOMPARISON WITH STATE-OF-THE-ART 48 V-TO-5 V DC–DC CONVERTER ICS WHERE POWER TRANSISTORS ARE INTEGRATED ON IC∗ Recommended in evaluation board.

1/5 mode to 1/3 mode, and the dc voltage applied to CSCOUT
changes from 6 V (= 31 V/5) to 10 V (= 31 V/ 3). As a result,due to the dc voltage dependence of the MLCC capacitanceshown in Fig. 15, the capacitance of CSCOUT changes from 3.4
to 1.8 µF. Unfortunately, the SPICE model for capacitors taking
into account the dc voltage dependence is not available, andSPICE simulation in Fig. 15 was performed with a constantcapacitance of CSCOUT = 1.9 µF for the nominal 1/5 modecondition. SPICE simulation with the dc voltage dependenceof capacitance is a future design challenge.

V. COMPARISON WITH CONVENTIONAL 48 V-TO-5 V DC–DC
CONVERTER ICS INTEGRATING POWER TRANSISTORSIn Table III, the proposed FH dc–dc converter IC is comparedwith the state-of-the-art 48 V-to-5 V dc–dc converter ICs where
the power transistors are integrated on IC. The volume of passive
components is calculated by the volume of inductors for thebuck converters, capacitors for the SC dc–dc converters, andinductors and capacitors for the hybrid converters. Note thatto simplify the comparison, we discuss the volume of external
passive components necessary in the main circuit and gate
drivers in Table III, excluding external passive components forcompensators. In this work, the volume of passive components,
including one inductor and 21 capacitors, is 66 mm3 .
As described in Section I, the SC dc–dc converter does notachieve the VOUT regulation at constant fSW , though the SC
dc–dc converter [11] achieves the highest efficiency with thesmallest volume. The buck converters [4]–[6] in Table III withfSW of above 2 MHz suffer from the efficiency degradation.
Compared with previous publications, the proposed 0.55
W, 48 V-to-5 V FH dc–dc converter IC achieved the highest

Fig. 20. Efficiency of 48 V-to-5 V dc–dc converters at IOUT of 100 mA andvolume of passive components in commercially available buck converter ICs[1]–[3] and proposed FH dc–dc converter IC.

efficiency (88%) with the smallest volume of passive components (66 mm3 ) at the lowest switching frequency (78 kHz).
Fig. 20 shows the efficiency of the 48 V-to-5 V dc–dc converters at IOUT of 100 mA and the volume of passive components inthe commercially available buck converter ICs [1]–[3] and the
proposed FH dc–dc converter IC. As described in Section I, thebuck converter ICs show a clear tradeoff between the efficiency
and the volume. In contrast, the proposed FH dc–dc converter
IC solves the tradeoff. Compared with the conventional buckconverter, the required voltage rating of the power transistors in
the hybrid dc–dc converters is reduced, and the loss due to thepower transistors is also reduced [34].

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YAMAUCHI et al.: 0.55 W, 88%, 78 KHZ, 48 V-TO-5 V FH DC–DC CONVERTER IC USING 66 MM3 OF PASSIVE COMPONENTS

VI. CONCLUSION
To meet the requirements for 48 V mild hybrid vehicles, a 0.55
W, 88%, 78 kHz, 48 V-to-5 V FH dc–dc converter IC is proposed.
The proposed ACCD enables the constant 5-V VOUT under cold
cranking. Compared with previous publications, the proposed 48
V-to-5 V FH dc–dc converter IC achieved the highest efficiency(88%) with the smallest volume of passive components (66mm3 ) at the lowest switching frequency (78 kHz).
ACKNOWLEDGMENT
The authors would like to thank J. Nagata, R. Miura, and Y.
Tomonaga of DENSO Corporation for technical discussions on
automotive dc–dc converters.
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[31] T. Tanzawa, “On two-phase switched-capacitor multipliers with minimum
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Yoshitaka Yamauchi (Member, IEEE) received the
B.S., M.S., and Ph.D. degrees in electrical engineering from The University of Tokyo, Tokyo, Japan, in
2014, 2016, and 2020, respectively.
In 2019, he was a Research Intern with IBM T.
J. Watson Research Center, New York, NY, USA.
In 2017, he was with Integrated Device Technology,
San Jose, CA, USA, as a PMIC Design Engineering
Intern. Since 2020, he has been with the Memory
Solution Division, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, where
he is currently engaged in the development of nonvolatile embedded memory
circuit technology for low-power, high-performance applications.

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Toru Sai (Member, IEEE) received the B.S., M.E.,
and Dr.Eng. degree in electrical engineering from
Chuo University, Tokyo, Japan, in 1986, 1988, and2012, respectively.
In 1988, he joined the Research and Development
Center, Yokogawa Electric Company, Tokyo, Japan.
From 2016 to 2020, he was a Project Research Associate with The University of Tokyo, Tokyo, Japan. He
is currently an Associate Professor with Tokyo Polytechnic University, Tokyo, Japan. His current researchinterests include dc–dc converters, gate drivers, andA/D converters.
Dr. Sai was the recipient of the Best Paper Award of the 2019 IEEE International Future Energy Electronics Conference.

Katsuhiro Hata received the M.S. and Ph.D. degrees
from The University of Tokyo, Tokyo, Japan, in 2015
and 2018, respectively.
He is currently a Research Associate with the Institute of Industrial Science, The University of Tokyo.
His research interests include hybrid dc–dc converters, digital gate driving, wireless power transfer, ande-mobility for transportation.
Dr. Hata is a member of the Institute of ElectricalEngineers of Japan (IEEJ), the Institute of Electronics, Information and Communication Engineers (IEICE), and the Society of Automotive Engineers of Japan (JSAE).

Makoto Takamiya (Senior Member, IEEE) received
the B.S., M.S., and Ph.D. degrees in electronic engineering from The University of Tokyo, Tokyo, Japan,
in 1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Tokyo, Japan,
where he was engaged in the circuit design of highspeed digital LSIs. In 2005, he joined The Universityof Tokyo, where he is now a Professor with the Institute of Industrial Science. From 2013 to 2014, he waswith the University of California, Berkeley, Berkeley,
CA, USA, as a Visiting Scholar. His research interests
include integrated power management circuits for wireless powering and energy
harvesting for wearable and IoT applications, and digital gate driver IC for powerelectronics.
Prof. Takamiya is a Distinguished Lecturer of IEEE Solid-State Circuits Society. He is a member of the Technical Program Committee of IEEE Symposium on
VLSI Circuits. He was formerly a member of the Technical Program Committeesof the IEEE International Solid-State Circuits Conference (ISSCC) from 2015
to 2020 and IEEE Custom Integrated Circuits Conference from 2006 to 2011.
He was a Far East Regional Chair in ISSCC 2020. He was the recipient of the2009 and 2010 IEEE Paul Rappaport Awards and the Best Paper Award of the2013 IEEE Wireless Power Transfer Conference.

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