2015 European Conference on Circuit Theory and Design (ECCTD)

Analysis to Optimize Sensitivity of RF Energy
Harvester with Voltage Boost Circuit
Dan Luo, Hiroshi Fuketa, Kenichi Matsunaga*, Hiroki Morimura*, Makoto Takamiya, and Takayasu Sakurai
Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, Japan, 153-8505*) NTT Device Technology Laboratories, NTT Corporatione-mail: {luodan, tsakurai}@iis.u-tokyo.ac.jp
Abstract— Analytical theory and simulation-based analysis
for optimizing sensitivity of RF energy harvester are discussed. Atarget harvester is a widely-used MOSFET Dickson chargepump harvester from a small-signal RF power with a voltage
booster at the front end. Charging time is also analyzed. Derived
expressions show good match with simulation results. The results
provide an insight for design optimization based on circuit anddevice parameters.
Keywords—Energy harvester, Voltage booster, Modeling,
Subthreshold slope, Optimization

RL
CC

VRFsinZt

CC

CC
VOUT

VINsinZt

C

CC

R

CC

COUT

C
CC

VRFsinZt
L

CC

CC
VOUT

VINsinZt
CC

CC

COUT

LIST OF SYMBOLS

I. INTRODUCTION
Recently, energy harvesting from small RF signal isdrawing attention as a possible energy source for Internet ofThings (IoT) nodes [1]. Input RF signal is as small as -30dBm,
which corresponds to 7mV if antenna resistance is 50:.
Modeling and optimization of the harvester are discussed inthis paper. The harvesters under consideration are based on
Dickson charge pump circuit with a voltage booster of, either
LC-type or CL-type, in the front-end, which are depicted inFig.1.

978-1-4799-9877-7/15/$31.00 ©2015 IEEE.

II. MODELING
A. Modeling of MOSFET
Since the input RF voltage is small, the MOSFET in acharge pump circuit is operated in a subthreshold region, andthus the I-V characteristics of a MOSFET with a forwardbiased junction used in the charge pump is modeled as follows.
VGS VTHI DSVDSI 0 e nUT (1  e mUT )(1)
Introduction of m is necessary to fit the SPICE MOS model
calculation. As an added benefit, m makes it possible to model
steep-S devices including a Tunneling FET based circuits inthe future [2, 3]. Two types of transistors are used in this paper
namely Zero-VTH and Low-VTH, to show the generality of theanalysis. I-V characteristics are shown in Fig. 2.
61.2
D

10-5

Zero-VTH

0.8

10-60.4 n=1.66
m=1.90
Low-VTH0Low-VTH
10-7

10-80

SPICE simulation
VDS=0.3V

0.05

0.1

0.15 0.2
VGS [V]G

0.25 0.3

-0.4

4VDS
S2
Zero-VTH
n=3.570
m=4.00IDS [nA]

Z1Fig. 1. Dickson charge pump with an LC booster (top) and a CL booster(bottom) considered in this paper. Phases of sinusoidal waves are omitted asthey are not relevant in this paper.

IDS [μA]

Z

Equivalent capacitance of one charge-pump MOS
Equivalent capacitance of total charge pump
Coupling capacitance in charge-pump circuit
Frequency of input RF signal
Current coefficient of charge-pump MOS
Drain current of a charge-pump MOS
Inductance of an inductor in booster
Subthreshold drain voltage coefficient
Subthreshold gate voltage coefficient
Number of MOS stages of charge pump
Charge transferred in one cycle by one charge-pump stage
Equivalent resistance of antenna
Equivalent resistance of charge-pump MOS
Equivalent resistance of total charge pump
Cycle time
Thermal voltage
Drain-Source voltage of charge-pump MOS
Gate-Source voltage of charge-pump MOS
Amplitude of input signal to charge pump
DC voltage of single charge-pump stage
Output DC voltage after charge pump
Amplitude of input RF signal
Threshold voltage of charge-pump MOS
Angular frequency of input RF signal
Effective impedance of one charge-pump stage

IDS [A]

C1
CNCC
f
I0
IDS
Lmn
N
Q1
R
R1
RN
T
UTVDSVGS
VIN
VO
VOUTVRFVTH-2

Analytical

Simulation-0.8-40-20020VDS [mV]

40-4(a)(b)
Fig. 2. Employed MOSFETs are two types for 0.25μm CMOS, namely zeroVTH and low-VTH. (a) Subthreshold I-V characteristics by SPICE model and(b) analytical model (1) fitted to SPICE model of diode-connected MOSFET.
Fitted parameters are shown in the figure. Both of the gate width and length
are the allowed minimum. All SPICE simulations in this paper use the samegate length and width as they are supposed to be appropriate for achieving thebest sensitivity.

V010-30T1T2T

t10-4 -1
10VTH

V1I 0 e nUT (1  e mUT )dt  ³

TT /2

V1 VTH

V1I 0 e nUT (1  e mUT )dt (2)V1 VIN sin Zt  VO(3)Putting x (VIN / UT )sin Zt and y VO / UT , and considering
only the sign of the sinusoidal wave changes between theformer half and the latter half of a cycle, the following holds.
VTH yx y xy xªº(1  e m )  e n (1  e m ) » dt (4)«0¬¼When the function in the integral is expanded in terms of x andy around zero assuming both x and y are small, the following
expression holds.
I 0 e nUT ³Q1V THnUTV THnUT

§ VIN
§ x
TI 0V ·2y ·e O ¸ (5)¨¨¸ dt
2mUT ¹© mn m ¹© 4nUT
By setting Q1=0, output DC voltage VO is solved as follows.
Q1 | I 0 e

³T /2

2

VOUT1 § VIN ·¨¸4n © U T ¹(6)The above expression is simple yet excellent in reproducing thesimulation results as is seen in Fig. 4. This expression for the
first time explains the importance of steepness, n, in thesubthreshold region and steep-S devices for a harvester.
When VIN gets very large, the above approximation is not
valid any more. In that case, though, it can be understood froma physical consideration that VO asymptotes to VIN, that is,
VO~VIN. Connecting this linear dependence of VO on VIN and thequadratic dependence (6) smoothly, the expression which isvalid for all range of VIN is derived as follow whose
effectiveness is shown in Fig.4.

VOUTV IN ·VIN §¨1  e 4 nUT ¸¸UT ¨©
¹(7)102Fig. 4. Comprison of theoretical calculation using (6) and (7) and simulation
results for output DC voltage of single charge-pump stage.

One more thing that is necessary to model the single
pumping stage is to obtain an equivalent impedance, Z1, which
is seen from a booster circuit. It turns out that Z1 can be
expressed as a parallel connection of resistance, R1, andcapacitance, C1 as is shown in Fig.5. This situation is verifiedfrom Fig. 6, where the real part of 1/Z1 is shown to be constantand the imaginary part is proportional to f. R1 is expressed as
below using the device parameters in (1).
dI DS (VGS VDS
dV1R1CC2VV)
V 0Z1

I 0  nUTHT
emUT

R1

CC
2(8)

C1Fig. 5. Comprison of theoretical calculation and simulation results for output
DC voltage of single charge-pump stage.
10-4

10-4

02

101
VIN/UT

T /2

2100

Re[1/Z1]

10-5

10-6

108

Im[1/Z1]
Zero-VTH(Simulation)
C1=2.59fF
R1=75.0kΩ
Frequency f [Hz]109Admittance [S]021 § VIN ·¨¸4n © U T ¹
VIN·VIN §4 nUT¨1 - e¸¨¸UT ©
¹Simulation (f=920MHz)

VIN

When input swing is very small, VO is small andthus T1 | T / 2 and T2 | T hold. In this case, the chargetransferred from right to left in one cycle, Q1, is calculated asfollows. Q1 should be zero at the steady state.

³Zero-VTH

10-1

VOCC2T /2

Low-VTH

10010-2(a)(b)
Fig. 3. (a) One charge-pump stage and (b) input waveform to diodeconnected MOSFET. T1 and T2 denotes the time when V=0.

Q1101

V1 = VIN sinZt + VOIV1102

Admittance [S]CC2103

VO/UTB. Modeling of One Charge-Pump StageA Dickson charge pump circuit in Fig. 1 consists ofmultiple of diode-connected MOS transistor stages whose
single stage is depicted in Fig. 3(a). Since CC is chosen to bevery large, it is transparent to RF signal and then the input
waveform to a MOS diode is schematically shown in Fig. 3(b).
Obtaining an expression for the DC voltage, VO, and an
equivalent impedance for one charge-pump stage are the aimsof this section.

10-5
10-6

10-7

10-8 810

Im[1/Z1]

Low-VTH(Simulation)
C1=1.05fF
R1=19.1MΩ
Re[1/Z1]
Frequency f [Hz]109(a)(b)
Fig. 6. Frequency dependence of real and imaginary part of 1/Z1 for (a) ZeroVTH MOSFET and (b) Low-VTH MOSFET.

C. Modeling of Charge pump with Voltage Booster
Now, a total harvester is modeled. Two types of a voltage
booster are considered here, namely LC type and CL type,whose equivalent circuit is shown in Fig. 7. RN and CN
respectively represent total equivalent resistance andcapacitance of a charge-pump circuit consisting of N stages, orin other words, N diode-connected MOSFET’s. RN and CN canbe expressed as follows. Note that RN is not NR1 but R1/N.

L

RC

CN80

CRN

CN

RN(b)

§ L·R
L(C  CN ) s 2  ¨
 R C  CN ¸ s 
1RN
© RN
¹LCs 2(11)2

1s '2  s '/ Q  1 s ' jZ '1(1  Z '2 )2  Z '2 / Q 2(12)Z '4(13)

22H CL vs '232as '  s '  s '/ Q  1 s ' jZ '(1  Z ' )  (1 / Q  aZ '2 ) 2 Z '22 2|H|2200.9

2H VRF 2 .

1.1

1.2

00.8

0-1-1(15)0.9Z'

a=0.05-2-3-4% error of |H|

2

4

1

1.1

1.2

Q

8

a=0.1
a=0.05a=0.1-2-3-4

6% error of |H|2% error of Z that gives |H|2 peak

10-52

46Q

810(a)(b)
Fig. 9. Relative error of approximated maximum and true maximum of |H|2for (a) LC-type booster using (12) and (b) CL-type booster using (13).

Output DC voltage, VOUT, of the total charge pump consistingof N stages is expressed as a simple sum of each single-stage
DC voltage.
(16)
VOUT NVO
Using above formulas and (6) yield the following expression
for VIN and VOUT.
1(17)VIN , LCVRF§ LR ·Z¨N 2 ¸
© R1 LZ ¹2

VIN 2

1Z'

VIN ,CLSeeing (6), |H| should be maximized to get the best boosting
effect but unfortunately the exact condition to maximize |H|2 isdifficult to express analytically. It is found, however, acondition that the real part of the denominator of H is zero canbe a good approximation for maximizing |H|2, whose situationis shown in Figs. 8 and 9.
This condition corresponds to Z ' 1 in (12) and (13). The
relative error of the approximated |H|2 value is within 3%
compared with the exact maximum when Q value is more than
3. This range of Q value is usually adopted since the voltage
boosting effect is expected anyway when a booster is deployed.
Considering R1 values in Fig. 6 and R|50:and using (9), it
is seen that R / RN 1 holds. In this situation, |H|2 maximizing
condition becomes the following for both LC and CL types.
L(C  NC1 )Z 2 1(14)This can be achieved by tuning L and C with circuit techniques.
Input AC voltage to a charge pump block, VIN, is calculated asa=0.1, 0.05, 0
from top tobottom

400-52The subscript LC and CL correspond to the booster type.
Square of the absolute value of the transfer function, |H|2, has
the following form with s', Z', Q, a, being normalized Laplace
variable, normalized angular frequency, Q value, and a real
number, respectively.
240

Q=460

-% error of Z that gives |H|2 peak

§ R·§ L·RLCCN s 3  ¨LC  L C  CN ¸ s 2  ¨ RC ¸ s  1RR
© N¹
© N
¹

H LC v60

Q=6(a)(b)
Fig. 8. |H|2, square of the absolute value of transfer function for (a) LC-type
booster using (12) and (b) CL-type booster using (13).

% errorTransfer function of boosters, H, from VRF to VIN in Fig. 1
can be written as follows.
1(10)
HH CL

Q=400.8Fig. 7. Equivalent circuit of total harvester with (a) LC-type booster and (b)CL-type booster

LC

Q=880

Q=620

L(a)

100
Q=8% error

R100|H|2(9)RN R1 / N , CN N C1
Output capacitance, COUT, in Fig. 1 comes in series to RN andCN and thus can be neglected as in Fig. 7, when COUT is large,
which is the case in consideration here.

VOUT , LCUT

L 1  NLC1Z 2 Z
NL2Z 2 / R1  R 1  NLC1Z 2N § VIN ·¨¸4n © U T ¹22(18)VRF2§ VRF · (19)1N¨¸24n § LR · 2 © UT ¹Z¨N 2 ¸
© R1 LZ ¹
2VOUT ,CLUT2§· §L 1  NLC1Z 2 ZN¨¸ ¨ VRF ·¸ (20)4n ¨ NL2Z 2 / R  R 1  NLC Z 2 2 ¸ © UT ¹11©
¹

VOUT is a function of number of charge-pump stages, N.
Differentiating by N and putting the derivative to zero, theoptimum stage count, NOPT, can be obtained as follows.
RR1(21)NOPT , LC
L2Z 2
L / R1  2 RC1  L / R1 L / R1  4 RC1(22)
NOPT ,CL2 RLC12Z 2
There is an optimum value for N because if N increases, RN
gets small and this in turn decreases the voltage boosting
efficiency although the charge pump multiplies VIN more.
When NOPT is employed, output voltage of the harvester ismaximized and reaches following VOUT,OPT for both of LC andCL. This corresponds to the sensitivity of a harvester for small

RF signal with R1/4R being a voltage boosting effectunderstood from (6).

TIII. COMPARISON WITH SPICE SIMULATION AND CONCLUSION
Analytical expressions for VIN, a boosted AC voltage which
is an input to a charge pump, and VOUT, a DC output voltage ofan energy harvester, are obtained as (17) through (20). These
analytical calculations are compared with SPICE simulation
results in Figs. 10-13 for two boost types and MOS types.
f=920MHz and L=100nH. Overall agreement is satisfactory forboosting efficiency, VIN/VRF, and sensitivity of a harvester,
VOUT/VRF. Hence, the optimum number of stages, NOPT, is alsoin accordance with SPICE simulation. Charging time (25) alsofits very well with simulation as shown in Fig. 14.

0.04

0.02
00

Zero-VTH
LC boost
VRF=7mV

Simulation
VOUT [V]

VIN [V]

0.06

Analytical

0.06

Zero-VTH
LC boost
VRF=7mV
100.040.02
Analytical

20
N

30040

Simulation
01020
N

30400.1

100.088VOUT [V]

VIN [V](a)(b)
Fig. 10. Comparison of analytical expressions, (17) and (19), and SPICE
simulation results. for (a) VIN and (b) VOUT for LC-type voltage boost with
Zero-VTH MOS.

0.06
0.040.02
00Low-VTH
LC boost
VRF=7mV100

Analytical
Simulation
N200300

6Low-VTH
LC boost
VRF=7mV00Analytical
100

N200300(a)(b)Fig. 11. Comparison of analytical expressions, (17) and (19), and SPICE
simulation results. for (a) VIN and (b) VOUT for LC-type voltage boost with
Low-VTH MOS. For this configuration, N can not be very large as C becomes
minus in (14).

20N

30

040

0.16

030

1020
N3040

VOUT [V]Low-VTH
CL boost
VRF=7mV0.0820Low-VTH
CL boost
VRF=7mV

100.040

Analytical
Simulation

0.12

Analytical

Simulation
0100

N20000300100

N200300(a)(b)Fig. 13. Comparison of analytical expressions, (18) and (20), and SPICE
simulation results. for (a) VIN and (b) VOUT for CL-type voltage boost with
Low-VTH MOS. Broken line in (b) is analytical calculation using more
complex but more accurate expression (7).
33

COUT=1nF

2.5 VIN=7mV
N=2022

1.5
11Analytical

Analytical
W=NR1COUT

Simulation@92MHz

0.5

Simulation

Simulation@920MHZ

0012345time [ms]67891000(a)10N203040(b)Fig. 14. (a) Simulated waveform of charging COUT and (b) comparison ofanalytical expression and SPICE simulation results.

Several simple yet useful analytical expressions such as (6),(23), and (25) are obtained for a widely-used charge-pumpbased RF energy harvester. As they reproduce well the SPICE
simulation results, they can be used in optimizing a harvester atthe early stage of the design.
REFERENCES[1]

4Simulation

10Simulation(a)(b)
Fig. 12. Comparison of analytical expressions, (18) and (20), and SPICE
simulation results. for (a) VIN and (b) VOUT for CL-type voltage boost with
Zero-VTH MOS.

[2]

2

VOUT [V]00NR1tt§· ·§(25)
VOUT (t ) VOUT ¨1  e NR1COUT ¸ VOUT ¨1  e W ¸¨¸©
¹©
¹
The charging time constant W is NR1COUT, which turns out to be
independent from f.

0.02

Analytical

VOUT [mV]

dt

0.04

0.04

W [ms]D. Modeling of Charging Time.
Charging waveform, VOUT(t), of the output capacitance,COUT, can be derived by using (2) and (5) while noting that VO
obtained in (6) is a final steady state value but in general VO
changes in time. Assuming COUT very large, the followingholds.
dV (t )Q (V VOUT / N )
1
 1 O

COUT OUT
VOUT (t )  VOUT (24)Zero-VTH
CL boost
VRF=7mV

Simulation

0.02

VIN [V]1 R1 § VRF ·(23)¨¸16n R © U T ¹
UTWhen VRF is considerably large, (7) instead of (6) should beused and the numerical calculation is needed rather than pureanalytical treatment but for most of the cases, (6) is sufficiently
good because the RF signal is usually less than 5UT.
VOUT ,OPT

VIN [V]

20.06

Analytical

Zero-VTH
CL boost
VRF=7mV

0.06[3]

S. Oh and D. D. Wentzloff, “A -32dBm Sensitivity RF Power Harvester
in 130nm CMOS,” IEEE Radio Frequency Integrated Circuits
Symposium, pp.483-486, 2012.
H. Fuketa, K. Yoshioka, K. Fukuda, T. Mori, H. Ota, M. Takamiya, andT.Sakurai, "Design Guidelines of Steep Subthreshold TFET to Minimize
Energy of Logic Circuits," International Conference on Solid State
Devices and Materials (SSDM), pp. 832-833, Sep. 2014.
H. Fuketa, K. Yoshioka, K. Fukuda, T. Mori, H. Ota, M. Takamiya, andT. Sakurai, "Design Guidelines to Achieve Minimum Energy Operation
for Ultra Low Voltage Tunneling FET Logic Circuits," Japanese Journalof Applied Physics, vol. 54, no. 4S, 04DC04, Apr. 2015.