A 13nW Temperature-to-Digital Converter
Utilizing Sub-threshold MOSFET Operation atSub-thermal Drain Voltage
Teruki Someya, A.K.M. Mahfuzul Islam, Takayasu Sakurai, and Makoto Takamiya
The University of Tokyo, JapanAbstract— A new principle of temperature sensing based on asub-threshold MOSFET operation at sub-thermal drain voltage isproposed. The proposed external-reference-free temperature-todigital converter with on-chip proportional-to-absolutetemperature (PTAT) digital output achieves the lowest power
consumption of 13nW at 0.8V. The proposed principle takes theratio of two sub-threshold currents with different drain voltages.
The principle is implemented using op-amp-free current
generators and relaxation oscillator based current-to-frequency
converters for ultra-low power operation. Measurement resultsfrom 8 chips fabricated in a 180-nm CMOS process achieve
110mK resolution and -0.7/+1.3°C inaccuracy over a temperature
range of -20°C to 80°C.
Keywords—Temperature
sensor;Temperature-to-digital converter;

temperaturesensing;

I. INTRODUCTION
Real-time thermal management using a temperature sensor
is one of the typical applications in the Internet of Things (IoT).
Recently, thin-film batteries have been developed for IoT
devices. One key feature of these batteries is the large internal
resistance RBAT (e.g., 60kΩ after 1000 cycles [7]) that limits themaximum supply current. Assuming that RBAT is 60kΩ and theacceptable voltage drop is 100mV, the maximum instantaneous
current from the battery (IMAX) is limited to only 1.7μA. In suchsituations, reducing the maximum current of the IoT node
becomes critical. As a temperature sensor is just one among
many components in the system, reducing the average current of
the sensor to less than 1% of IMAX (=17nA) is a challenging issue.
Recently, ultra-low power temperature sensors that convert thetemperature to time or frequency without ADC to reduce thepower consumption [1,2,4,5] have been proposed. [4] shows thata reference-free current-to-frequency converter (CFC) based
temperature sensor with an appropriate fitting model canachieve high accuracy of -0.76/+0.76°C. [4], however, requires
off-chip processing due to the nonlinear fitting model,
preventing real-time thermal management. [1,2] propose onchip sensors with PTAT digital output that does not require offchip processing. [1] utilizes a proportional to absolutetemperature (PTAT) voltage generator, while [2] utilizes a linear
approximation of the ratio between two sub-threshold currents
operating at different gate voltages. Though [5] presents 113pW temperature-to-digital converter, the temperature rangeof -20°C to 40°C does not fit our target temperature rangeof -20°C to 80°C.

,(((Temperature (T)Sub-threshold current (I1) at

Sub-threshold current (I2) at

sub-thermal drain voltage

above thermal drain voltage

Frequency (f1)

Frequency (f2)Asynchronous counter
based ratio (Δ(f2/f1)Δ(I2/I1)ΔT)
DPTAT

Fig. 1 Flow chart of proposed temperature-to-digital converter.

In this paper, a sub-14nW temperature-to-digital converterwith PTAT digital output is proposed. We report: (1) a newtemperature sensing principle that is highly linear to temperature,(2) a new sub-thermal drain voltage (VDS) based current
generator, and (3) relaxation oscillator based current-tofrequency converter and asynchronous counter based frequency
ratio computation for digital output. The temperature-to-digitalconverter achieves the lowest power consumption of 13nW at
0.8V supply with 110mK resolution and -0.7/+1.3°C inaccuracy
over the temperature range of -20°C to 80°C.
II. DESIGN OF PROPOSED TEMPERATURE-TO-DIGITALCONVERTER
Fig. 1 shows the flowchart of the proposed temperature-todigital converter. The sensor includes generation of two subthreshold currents with different drain voltages (I1, I2), thecurrent conversion into frequencies (f1, f2), frequency ratio(f2 / f1) calculation for PTAT digital output (DPTAT).
A. Proposed temperature sensing mechanism
Figs. 2 show the operating principle of our proposed
temperature sensing mechanism. A pair of MOSFETs operatingin sub-threshold region is biased with two different VDS values.
A sub-thermal drain voltage (STV) less than the thermal voltage
VT (=26mV at 27°C) is applied to VDS1 of MA1, while above
thermal drain voltage (ATV) more than 3VT is applied to VDS2 ofSub-thermal
drain voltage (STV)

VREF (400mV)

Above thermal
drain voltage (ATV)

Same size

VGS1 < VTH

MA1

I1

MB1

∆V = VREF/50 = 8mV

D1

VB1

I2
Mk+1

VDS2 > 3VT

VDS1 < VT

I2

VA(248 mV)

16 stacked(k = 16)

I2

IDS [a.u.]

MB2MAk∆V

1
MA20.5

VGS1 < VTH

I1∆V

0 VDS10.1
VDS2
VDS [V]

MB1
I2

I1

STV MOSFET0.2

Measured

Voltage divider(a)30I2
I1
VDS1 [mV]47μV/ºCk≈ 0.02 [/ °C]
qVDS1(b)Fig. 2. Proposed temperature sensing mechanism. (a) VDS biasing of MOSFETs
for deep triode and saturation region operation, and sub-threshold drain current
vs VDS. (b) Measured I2/I 1 of a single transistor.

MB1. As a result, drain currents of MA1 operating in the deeptriode region and MB1 operating in the saturation region areexpressed as follows:

I2 = K ⋅ eq (VGS1 −VTH )nkTq (VGS1 −VTH )nkT− qVDS1⎛⎞⋅ ⎜1 − e kT ⎟⎜⎟⎝⎠(1)− qVDS1⎛⎞⋅ ⎜1 − e kT ⎟⎜⎟⎝⎠(2)

where k is the Boltzmann constant, q is the electron charge, T is
the absolute temperature, n is the sub-threshold swingparameter, VTH is the threshold voltage, and K is a preexponential factor that is dependent on the temperature. Thecurrent ratio of I2/I1 becomes a function of VDS1 and T as follows:

I2
=I1

1
1− e− qVDS1kT≈

kT+CqVDS1(3)

Simulated
k=1
k=2

20

k=4
k=810

∆VTemperature [ºC]

I1 = K ⋅ e

ATV MOSFET

D50(a)VGS1
GS = 100 mV
VDS1 = 4 mVVDS2 = 256 mVVDS1 = ∆V (8mV) VDS2 (128mV)

MA1VB(120 mV)

Simulated0I1VB2

2.2μV/ºC

k=160-200204060
Temperature [ºC]80(b)Fig. 3. (a) Circuit schematic of current generator using STV and ATV
MOSFETs. (b) Temperature dependence of VDS1.

where C is a temperature-independent constant that can beremoved by calibration. Eq. (3) shows that Δ(I2/I1) is
proportional to ΔT which is confirmed by a single transistor
current measurement in Fig. 2(b). With a VDS1 value of 4 mV,
the current ratio has a high sensitivity of 0.02/°C. The theoreticalslope (=0.0215/°C) matches with the measured slope. Thissensitivity is 15 times larger than that reported by [2]. The highsensitivity enables higher resolution with lower power
consumption compared with that of [2].
B. Current generators
To implement the proposed principle of the temperature
sensor shown in Fig. 2(a) and Eq. (3), temperature and supply
voltage-independent VDS1 is required. We propose an op-ampfree VDS1 bias circuit required for a sub-14nW temperature-todigital converter. Fig. 3(a) shows the proposed op-amp-freecurrent generator including the VDS1 bias circuit. Firstly, areference voltage (VREF) is divided by a 50-stage diode chain togenerate small ∆V (=VREF/50) value of around 8 mV. ∆V is thencopied as VDS1 of the STV MOSFET (MA1) utilizing stacked

VB1

f1
CLK1

CFC 1 *

VB1(Fig. 5 (a))

CLK1Counter 1(10-bit)

I1
I1
VREFgen.

VB2

Statemachine

VREF

13
CFC2

CLK2

Counter 2(13-bit)
f2

I2

VB1

13DPTATff1

I
I1

C. Proposed temperature-to-digital converter
Fig. 4 shows the overall block diagram of the proposed
temperature-to-digital converter. Two CFCs along with twocounters provide on-chip digital conversion of I2/I1 without thehelp of external clock reference. The current ratio I2/I1 isconverted into f2/f1 using two CFCs. CLK2 edge is counted until
CLK1 edge is counted 1024 times achieving a resolution ofaround 110mK. The output of counter 2 is then latched and kept
until the next measurement.
For high accuracy and wide supply operation, the oscillation
frequency needs to be highly linear to I1 or I2. This is achievedby employing relaxation oscillator based CFCs as shown inFig. 5(a). The oscillation period of the CFC1 is expressed asfollows:⎛ CVREF2TOSC,1 = NCELL ⋅ ⎜⎝I1⎞+ tC,FALL + tC,RISE ⎟⎠(4)

where NCELL is the number of the delay cells in the CFC1, tC,FALL
and tC,RISE are propagation delays in Fig. 5 (b). VREF2 is thethreshold voltage for comparators in the delay cells obtained
from the diode chain in Fig. 3(a). The oscillation period of theCFC2 (=TOSC,2) is also achieved from (4) by exchanging I1 withI2. tC,FALL and tC,RISE need to be as small as possible since it
decreases the linearity of the temperature-to-digital converter.
Fig. 5(a) shows a delay cell used in the CFCs that utilizes a twostage op-amp. Fig. 5(b) shows the timing diagram of theproposed delay cell in the CFCs. In the op-amp, the 1st stage isVMOUTCIRVREF2RSW2Comparator
Feed-forward path to reduce tC,FALLFig.4. Overall block diagram of proposed temperature-to-digital converter.

MOSFETs. As the STV MOSFET operates in the deep triode
region, VDS1 does not settle to ∆V for the case where only one
stacked device (k=1) is used. By increasing the stack number (k),the VDS1 value becomes closer to ∆V and the temperaturedependence gets reduced. Fig. 3(b) shows the simulated
temperature characteristics of VDS1 with various k. The stackvalue of k=16 achieves a temperature dependence of 2.2μV/°C
which is small enough not to affect the sensor accuracy. As theATV MOSFET (MB1) operates in the saturation region, VDS2 isequal to VA –VB which is around 128 mV. Thus, the proposed
technique achieves constant VDS1 and VDS2 without the use ofpower-hungry op-amps.

SW1VC
IN

DPTAT = 210 × 2 = 210 × 2*CFC: Current-to-frequency converter

Fig. 3 (a)

I1

(a)

IN

CVREF2
I1

VREF2

VC
OUT
t C,RISEt C,FALL(b)
Fig.5 Current-to-frequency converter. (a) Schematic. (b) Timing diagram.

a common-source amplifier with a pMOSFET current mirror
load working as a comparator. The negative input is biased atVREF2 (<VTH) so that the threshold voltage of the comparator isset to VREF2. In the 2nd stage, a common-source amplifier withlarge load resistor is implemented to reduce tC,RISE. In order toachieve sub-1nW static power consumption in the delay cell, theresistor (R) should be large (e.g., 5GΩ) which is implemented
with an off-transistor. However, the large R increases tC,FALL due
to the limited current IR. To reduce tC,FALL, a feed-forward pathcomposed of SW1 and SW2 is added in the 2nd stage in Fig. 5(a). When IN changes from low to high, OUT is pulled down by
SW2 and tC,FALL is reduced. In the temperature range of -20°C to80°C, simulated peak-to-peak temperature inaccuracy using I2/I1
from our current generator is 0.48°C after 2-point calibration.
After the conversion to frequency ratio (f2/f1) using the CFCs ofFig. 5(a), the peak-to-peak inaccuracy degrades only to 0.58°C.
Thus, ultra-low-power frequency conversion has been achieved
without the degradation of temperature sensing accuracy.
The voltage reference for VREF generator in Fig. 4 is a key
circuit that makes the temperature-to-digital converter
reference-free and insensitive to VDD. In our design, a 2transistor based on-chip voltage reference [6] with stacked
devices for better line and temperature sensitivity is used.
III. MEASUREMENT RESULTS
To verify the proposed temperature-to-digital converter,
analog blocks shown in Fig. 4 are fabricated in 1.8V, 180-nm
CMOS. f1 and f2 are measured with the oscilloscope and thetemperature characteristics are obtained from f2/f1. The digital
blocks in Fig. 4 are designed with the standard cells and the1.3mm

21

VREF generator

Error [ºC]

1.1mm

260μm
170μm

0-1-280μm
Current generator
and CFC

3 chips measured at 20°C,40°C, 60°C and 80°C

-3
0.8

11.4

Fig. 8 VDD dependence of temperature inaccuracy.

2

Error [ºC]

1.2
VDD [V]

Fig. 6 Die photo of proposed temperature-to-digital converter.

8 samples

VDD = 0.8V

TABLE I.

1[1][2][3][4]CMOS process [nm]1806565180180

PTAT digital output

Yes

Yes

Yes

NoYes

Area [mm2]

0.09

0.022

0.004

0.220.065

Supply voltage

1.20.40.85 ~ 1.05

1.2

0.8 ~ 1.4

Power [nW]

71

280

154000570

13

Energy/conversion [nJ]

2.27

3.4

4.6

11

Temp. range [ºC]

0 ~ 100

0 ~ 100

0 ~ 100-20 ~ 80

-20 ~ 80

Inaccuracy [ºC]-1.4/+1.5(2-point)-1.6/1.0(2-point)-0.9/0.9(2-point)-0.76/0.76(2-point)-0.7/1.3(2-point)

0-1-2-20

0204060

COMPARISON WITH PREVIOUSLY PUBLISHED MOSFET BASEDLOW POWER TEMPERATURE SENSORS

80

Temperature[ºC]
Fig. 7 Measured temperature inaccuracy.

power consumption of the digital block is simulated. Fig. 6shows a die photo of the proposed temperature-to-digitalconverter. The sensor has a total area of 0.065 mm2. Fig. 7 shows
the measured temperature inaccuracy for 8 chips operating at
0.8V. After a 2-point calibration, the peak-to-peak inaccuracy
is -0.7/+1.3°C. Fig. 8 shows the measured VDD dependence oftemperature inaccuracy for 3 chips at 20°C, 40°C, 60°C and80°C. Taking f2/f1 at 0.8V as reference, peak-to-peak inaccuracy
over a VDD range from 0.8 to 1.4 V is -2.7/+1.3°C for a wide
temperature range of 20 to 80°C. The worst peak-to-peak line
sensitivity among 3 chips for different temperature
measurements is 4.6°C/V.
TABLE I summarizes the measurements and compares
MOSFET based temperature sensors. The proposed sensor
consumes the lowest power of 13nW at room temperature of25°C while achieving inaccuracy of -0.7/+1.3°C. Current
generators and CFCs consume 6.2nW, VREF generator anddigital backend consumes 0.24nW and 6.4nW, respectively.

Resolution [mK]30025030090110Resolution FoM [nJ·K2]

0.19

0.44

0.3

0.037

0.14Resolution FoM = (Energy/Conversion) × (Resolution)2

generation circuits. Measurement results show that the proposed
temperature-to-digital converter fabricated in 180-nm CMOS
realizes -0.7/+1.3°C inaccuracy over a temperature rangeof -20°C to 80°C with a resolution of 110mK.
REFERENCES[1][2]

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[4]

IV. CONCLUSIONSIn this paper, an ultra-low power external-reference-freetemperature-to-digital converter utilizing sub-threshold
MOSFET operation at sub-thermal drain voltage was proposed.
The proposed temperature-to-digital converter realizes PTAT
digital output that eliminates off-chip processing with anonlinear fitting model. The total power consumption is 13nW
at room temperature, which is the lowest power consumption
among previous publications thanks to our current-ratio based
temperature sensing principle and op-amp-free current

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[6]

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Datasheet of CBC005, Cymbet corporation.