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PAPER

Special Section on Analog Circuits and Related SoC Integration Technologies

0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7%
Current Eﬃciency in 65 nm CMOS
Yasuyuki OKUMA†a) , Koichi ISHIDA†† , Members, Yoshikatsu RYU† , Xin ZHANG†† ,Po-Hung CHEN†† , Nonmembers, Kazunori WATANABE† , Makoto TAKAMIYA†† , Members,
and Takayasu SAKURAI†† , Fellow

SUMMARY
In this paper, Digital Low Dropout Regulator (LDO) is
proposed to provide the low noise and tunable power supply voltage tothe 0.5-V near-threshold logic circuits. Because the conventional LDO
feedback-controlled by the operational amplifier fail to operate at 0.5 V,
the digital LDO eliminates all analog circuits and is controlled by digital
circuits, which enables the 0.5-V operation. The developed digital LDO in
65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage
with 98.7% current eﬃciency and 2.7-µA quiescent current at 200-µA load
current. Both the input voltage and the quiescent current are the lowest values in the published LDO’s, which indicates the good energy eﬃciency ofthe digital LDO at 0.5-V operation.
key words: low dropout regulator, digital control, low voltage

1.

Introduction

Very low-voltage operation of VLSI’s is eﬀective in reducing both dynamic and leakage power and the maximum
energy eﬃciency is achieved at low power supply voltage (VDD ) below 0.5 V (e.g., 340 mV [1] and 320 mV [2]).
Thus, many works have been carried out on the sub/nearthreshold logic circuits [1]–[5]. Stable and tunable VDD(e.g., 320 mV±50 mV [2]) is required in the near-thresholdlogic circuits, because the gate delay in the near-thresholdlogic circuits is very sensitive to VDD and the process variations. Therefore, a 0.5-V LDO enabling the low ripple andtunable VDD is strongly required. The conventional analog
LDO, however, fails to operate at 0.5 V. In order to solve theproblem, the digital LDO [6] enabling the 0.5-V operation is
proposed and demonstrated in this paper. The concept andthe circuit implementation of the proposed digital LDO isshown in Sect. 2. Measurement results from 65-nm CMOS
test chips are described in Sect. 3.
2.

Proposed Digital LDO

2.1 Concept and Schematic of the Proposed Digital LDO
In order to explain the concept of the proposed digital LDO,
Fig. 1 shows the circuit schematic of the digital LDO in contrast with the conventional analog LDO. The conventional
Manuscript received October 14, 2010.
Manuscript revised January 17, 2011.
†
The authors are with Semiconductor Technology Academic
Research Center (STARC), Yokohama-shi, 222-0033, Japan.
††
The authors are with Institute of Industrial Science, The University of Tokyo, Tokyo, 153-8505 Japan.
a) E-mail: ookuma.yasuyuki@starc.or.jp
DOI: 10.1587/transele.E94.C.938

Fig. 1(a) Conventional analog LDO. (b) Proposed degital LDO.

analog LDO shown in Fig. 1(a) consists of an operational
amplifier and a power transistor. The conventional LDO
fails to operate at 0.5 V, because the operational amplifier
does not operate at 0.5 V and cannot control the analog gate
voltage of the power transistor. In order to solve the problem, the digital LDO shown in Fig. 1(b) is proposed. The
digital LDO includes a switch array, a comparator, and adigital controller. The analog controlled power transistor is
replaced with the switch array and the number of turnedon switches is changed digitally by the controller. The output voltage (VOUT ) is monitored by the comparator insteadof the operational amplifier. Thus, the digital LDO eliminates all analog circuits and is controlled by digital circuits,
which enables the 0.5-V LDO operation, because the digital
circuits including the comparator can operate at 0.5 V.
Figure 2 shows the circuit schematic of the fabricateddigital LDO. The digital LDO consists of a comparator, aserial-in parallel-out bi-directional shift register, and switchc 2011 The Institute of Electronics, Information and Communication Engineers
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Fig. 2

Fig. 3Circuit schematic of the fabricated digital LDO.

Fig. 4 Circuit implementation of serial-in parallel-out bi-directional shift
register.

Circuit schematic of clocked comparator used in digital LDO.

array of 256 pMOS FET’s. In order to reduce the ripple dueto the switching of the switches, in this implementation, theshift register is used as the controller, because the numberof switching in the switch array is only one at each clockedge. The typical input voltage (VIN ) and VOUT are 0.5 V
and 0.45 V, respectively. The typical clock frequency of thecomparator and the shift register is 1 MHz. The oﬀ-chip
decoupling capacitor is 100 nF and the typical load current(ILOAD ) is 200 µA, because most of sub/near-threshold logic
circuits can be operated below 200 µA [2], [4], [5]. The current source is used for the static output load in the measurement in Figs. 8, 9 and 12-14, and the resistance of 2.2 kΩ or
22 kΩ is used for the transient output load in the measurement in Fig. 10 and 11. Figure 3 shows the circuit schematicof the clocked comparator used in the digital LDO. In the design of LDO with ILOAD of 200 µA, low quiescent current isvery important, because the large quiescent current degrades
the current eﬃciency of LDO. In order to reduce the quiescent current, the clocked comparator is used in the digital
LDO, because the clocked comparator can operate at 0.5 V
and consumes no DC-power.
2.2 Digital Controller for the Proposed Digital LDO
Figure 4 shows the circuit implementation of the serial-inparallel-out bi-directional shift register for the digital controller in the proposed digital LDO. The bi-directional shift
register consists of selectors and D-FF’s. In order to achievea superior transient response of the digital LDO at various
ILOAD, two control modes including “up-down control”
and “reset control” are implemented in the shift register.

Fig. 5 (a) Up-down control of bi-directional shift register for large
ILOAD . (b) Reset control of bi-directional shift register for small ILOAD .

When Mode is low, the shift register operates with up-down
control. In contrast, when Mode is high, the shift register
operates with reset control. The shift-right or the shift-leftoperation of the bi-directional shift register is determined by
the comparator output (CompOut). When CompOut is low,each QK except Q1 moves to QK+1 , and Q1 is set to “0”,which achieves the shift-right operation. In contrast, when
CompOut is high, each QK except Q256 moves to QK−1 , andQ256 is set to “1”, which achieves the shift-left operation.
Figure 5(a) shows the operation of the bi-directional
shift register in the up-down control mode. At first, all 256
bits are set to “1” in order to turn oﬀ all pMOS switches. After that, when CompOut is low, which means VOUT is lower
than the reference voltage (VREF ), all 256 bits are shifted
toward right in order to increase the number of turned-on
switches. In contrast, when CompOut is high, which means

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VOUT is higher than VREF , all 256 bits are shifted toward leftin order to decrease the number of turned-on switches. Similarly, Fig. 5(b) shows the operation of the shift register inthe reset control mode. Unlike the up-down control mode,
when CompOut is high, which means VOUT is higher than
VREF , all 256 bits are set to “1” in order to turn oﬀ all pMOS
switches.
In this up-down control mode, the ideal DC voltage
gain of the feedback loop achieves infinity, because the shift
register achieves the integrated operation. Therefore, PSRR
is good when the power supply noise frequency is lower thanthe clock frequency of the digital LDO.
Figure 6 shows the schematic of the transient of thenumber of turned-on switches in order to explain the feedback control of the digital LDO with the up-down control
mode and the reset control mode. ILOAD is large and smallin Figs. 6(a) and (b), respectively. The digital LDO controls the number of turned-on switches at each clock edge
depending on CompOut. At first, the number of charged
to VREF (=target voltage) and ILOAD is supplied turned-on
switches increases until the output capacitor is through theswitches. After that, when VOUT equals to VREF , the number of turned-on switches is equals to ILOAD and changes up
and down by 1-bit, which determines the ripple of the digitalLDO.
As shown in Fig. 6(a), when ILOAD is large, the overshoot of VOUT is suppressed with the up-down control
mode, because the charging current of the output capacitor isFig. 6 Schematic of the transient of the number of turned-on switches inorder to explain the feedback control of the digital LDO with the up-down
control mode and the reset control mode. (a) Load current ILOAD is large.
(b) Load current ILOAD is small.

smaller than ILOAD . In contrast, as shown in Fig. 6(b), when
ILOAD is small, the overshoot of VOUT is large with the updown control mode, because the charging current of the output capacitor is larger than ILOAD . The measured overshootwaveforms VOUT with the up-down control mode will beshown in Fig. 11. In order to reduce the overshoot of VOUT at
small ILOAD , the reset control mode is proposed. As shownin Fig. 6(b), when ILOAD is small, the overshoot of VOUT
is reduced with the reset control mode, because all pMOS
switches are turned oﬀ, when VOUT is higher than VREF . In
contrast, as shown in Fig. 6(a), when ILOAD is large, the ripple of VOUT is large with the reset control mode, because
all pMOS switches are turned oﬀ. The measured waveforms
VOUT with the reset control mode will be shown in Fig. 11.
Therefore, in this paper, in order to achieve superior transient characteristics, the up-down control mode is proposed
for large ILOAD and the reset control mode is proposed forsmall ILOAD .
3.

Measurement Results and Discussion

To demonstrate the advantage of the proposed digital LDO,
a test chip is fabricated in 65 nm CMOS. Figure 7 shows thechip microphotograph and the layout. The total chip area
including pads is 0.9 × 0.8 mm2 and the active area of thedigital LDO is 0.042 mm2 .
In the following measurements, the up-down control
mode is used except Fig. 11. Figure 8(a) shows measured
VOUT –VIN characteristics at ILOAD of 200 µA. VREF is varied
from 0.35 V to 0.55 V by 0.05-V step. The digital LDO successfully regulates VOUT from 0.35 to 0.45 V at VIN of 0.5 V.
At the design target of VIN of 0.5 V and VOUT of 0.45 V, thedropout voltage is 50 mV and the measured line regulationis 3.1 mV/V. Figure 8(b) shows measured VOUT –VIN characteristics at VREF of 0.45 V. ILOAD is varied from 20 µA to
200 µA. The LDO achieves a successful load regulation of
0.65 mV/mA with VIN from 0.5 V to 1.2 V.
Figure 9 shows the measured ILOAD dependence of thecurrent eﬃciency and the quiescent currents at 1-MHz and
10-MHz clock. Thanks to the digital LDO architecture,
the measured quiescent current does not depend on ILOAD ,though the quiescent current increases with ILOAD in theconventional analog LDO. At 1-MHz clock, the measured
quiescent current is 2.7 µA, which is the smallest quiescentFig. 7

Chip microphotograph and layout.

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Fig. 10 Measured transient waveform of VOUT when VREF changes from
0 V to 0.45 V at 1-MHz and 10-MHz clock and ILOAD of 200 µA.

Fig. 8 (a) Measured VOUT -VIN characteristics. (a) VREF is varied from
0.35 V to 0.55 V at ILOAD of 200 µA. (b) ILOAD is varied from 20 µA to
200 µA at VREF of 0.45 V.

Fig. 9 Measured ILOAD dependence of the current eﬃciency and thequiescent currents at 1-MHz and 10-MHz clock.

current in LDO’s to the author’s knowledge. The current
eﬃciency is 98.7% at ILOAD of 200 µA.
Figure 10 shows the measured transient waveform of
VOUT when VREF changes from 0 V to 0.45 V at 1-MHz and
10-MHz clock and ILOAD of 200 µA. The settling time of
VOUT at 1-MHz clock is 590 µs. By increasing the clock
frequency from 1-MHz to 10-MHz, the settling time canbe reduced by 60% from 590 µs to 240 µs at the cost ofincreasing quiescent current from 2.7 µA to 15 µA and thecorresponding degradation of the current eﬃciency by 5%
at ILOAD of 200 µA as shown in Fig. 9. The tunable performance by changing the clock frequency is the advantage ofthe digital LDO.
Figures 11(a) and (b) show the measured transient
waveforms of VOUT with the up-down control mode and thereset control mode when VREF changes from 0 V to 0.45 V at
1-MHz clock and ILOAD of 200 µA and 20 µA, respectively.
As shown in Fig. 11(a), the overshoot of VOUT is suppressedwith the up-down control mode and ILOAD of 200 µA. As
shown in Fig. 11(b), however, the 50-mV overshoot of VOUT
and 600-µs settling time are observed with the up-down control mode and ILOAD of 20 µA as shown in Fig. 6(b). In orderto solve the problem, the reset control mode clearly eliminates the overshoot of VOUT and reduces the settling timefrom 600 µs to 230 µs. As shown in Fig. 11(a), however, thereset control mode generates the 90-mV ripple at ILOAD of
200 µA as shown in Fig. 6(a). Therefore, in this paper, inorder to achieve superior transient characteristics, the updown control mode is proposed for large ILOAD and the reset
control mode is proposed for small ILOAD .
Figure 12 shows the measured transient waveformof VOUT when VREF changes between 0.4 V to 0.45 V at
100 Hz. The clock frequency is 1-MHz and ILOAD is 200 µA.
Figure 13 shows the measured transient waveform of VOUT
when ILOAD changes between 0 A to 200 µA at 100 Hz.
VOUT is 0.45 V and the clock frequency is 1-MHz. The
measured undershoot and overshoot of VOUT are 40 mV and
30 mV, respectively. As shown in Figs. 12 and 13, these results show reasonable performance of the digital LDO to be

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Fig. 13 Measured transient waveform of VOUT when ILOAD changes between 0.4 A to 200 µA at 100 Hz. VOUT is 0.45 V and the clock frequency
is 1-MHz.

Fig. 11 Measured transient waveform of VOUT when the up-down control mode and reset control mode when VREF changes from 0 V to 0.45 V
at 1-MHz clock. (a) Load current ILOAD is 20 µA. (b) Load current ILOAD
is 20 µA.

Fig. 12 Measured transient waveform of VOUT when VREF changes between 0.4 V to 0.45 V at 100 Hz. The clock frequency is 1-MHz and ILOAD
is 200 µA.

applied to the power supply for near-threshold logic circuit.
Since the switch array in the digital LDO is switched
digitally, the clock-related digital noise may cause LDO

Fig. 14 Measured waveform of VOUT and 1-MHz clock. VOUT is 0.45 V
and ILOAD is 200 µA.

output ripple. To evaluate the ripple caused by the digitalnoise, output ripple is measured as shown in Fig. 14. VOUT
is 0.45 V and the clock frequency is 1-MHz. The ripple of
VOUT is less than 3 mV. The measured VOUT shows no significant ripple at clock edges and its harmonic tones, whichindicates that the clock-related digital noise does not aﬀect
the LDO output ripple in the developed digital LDO.
The key performance summary of the proposed digital LDO and comparison with some previous regulators arelisted in Table 1. The digital control is proposed in [7]. The
regulator in [7], however, is not LDO but a half VDD generator. In this paper, both the digital LDO and 0.5-V LDO
are demonstrated for the first time. The developed digital
LDO achieved the 0.5-V input voltage and 0.45-V output
voltage with 98.7% current eﬃciency and 2.7-µA quiescentcurrent at 200-µA load current. Both the input voltage andthe quiescent current are the lowest values in the published
LDO’s.
4.

Conclusion

In this paper, the digital LDO enabling the 0.5-V operation

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Table 1 Key pwerformance summary of the proposed digital LDO andcomparison with previous regulators.

is proposed and demonstrated for the first time. In order toachieve superior transient characteristics, both the up-down
control mode for large ILOAD and the reset control mode forsmall ILOAD are proposed. The developed digital LDO in
65 nm CMOS achieved the 0.5-V input voltage and 0.45V output voltage with 98.7% current eﬃciency and 2.7-µA
quiescent current at 200-µA load current. Both the input
voltage and the quiescent current are the lowest values in
the published LDO’s, which indicates the good energy eﬃciency of the digital LDO at 0.5-V operation.
Acknowledgments
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial Technology Development Organization (NEDO).

Takamiya, and T. Sakurai, “0.5-V input digital LDO with 98.7% current eﬃciency and 2.7-µA quiescent current in 65 nm CMOS,” IEEE
Custom Integrated Circuits Conference, pp.323–326, Sept. 2010.
[7] P. Hazucha, S.T. Moon, G. Schrom, F. Paillet, D.S. Gardner, S.
Rajapandian, and T. Karnik, “A linear regulator with fast digital control for biasing integrated DC-DC converters,” IEEE International
Solid-State Circuits Conference, pp.536–537, Feb. 2006.
[8] P. Hazucha, T. Karnik, B.A. Bloechel, C. Parsons, D. Finan, and S.
Borkar, “Area-eﬃcient linear regulator with ultra-fast load regulation,” IEEE J. Solid-State Circuits, vol.40, no.5, pp.933–940, April
2005.
[9] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced lowquiescent current low-dropout regulator with buﬀer impedance attenuation,” IEEE J. Solid-State Circuits, vol.42, no.8, pp.1732–
1742, Aug. 2007.
[10] Y.H. Lam and W.H. Ki, “A 0.9 V 0.35 µm adaptively biased CMOSLDO regulator with fast transient response,” IEEE International
Solid-State Circuits Conference, pp.442–443, Feb. 2008.

Yasuyuki Okuma
received the B.S. and
M.S. degrees in electrical engineering from
Tokyo University of Science, Japan in 1997 and
1999, respectively. In 1999, he joined Central Research Laboratory, Hitachi, Ltd., Japan,
where he was engaged in the research and development of low power analog circuit techniquesfor HDD driver and RF-IC. From 2003 through2006, he was a visiting researcher at YRP Ubiquitous Networking Laboratory, doing researchin the field of low-power circuits and systems
for ubiquitous computing. Currently, he is visiting researcher at Extremely
Low Power LSI Laboratory, Institute of Industrial Science, the Universityof Tokyo from 2009. He is interested in power supply circuits and systems
for extremely low power LSI circuits and systems.

References[1] A. Agarwal, Amit, S. Mathew, S. Hsu, M. Anders, H. Kaul, F.
Sheikh, R. Ramanarayanan, S. Srinivasan, R. Krishnamurthy, and
S. Borkar, “A 320 mV-to-1.2 V on-die fine-grained reconfigurable
fabric for DSP/Media accelerators in 32 nm CMOS,” IEEE International Solid-State Circuits Conference, pp.328–329, Feb. 2010.
[2] H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, R.
Krishnamurthy, and S. Borkar, “A 320 mV 56 µW 411GOPS/Wattultra-low voltage motion estimation accelerator in 65 nm CMOS,”IEEE International Solid-State Circuits Conference, pp.316–317,
Feb. 2008.
[3] B. Calhoun and A. Chandrakasan, “Ultra-dynamic voltage scaling(UDVS) using sub-threshold operation and local voltage dithering,”
IEEE J. Solid-State Circuits, vol.41, no.1, pp.238–245, Jan. 2006.
[4] S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M.
Minuth, J. Olson, L. Nazhan-dali, T. Austin, D. Sylvester, and D.
Blaauw, “Performance and variability optimization strategies in a
sub-200 mV, 3.5 pJ/inst, 11 nW subthreshold processor,” IEEE Symposium on VLSI Circuits, pp.152–153, June 2007.
[5] M. Hwang, A. Raychowdhury, K. Kim, and K. Roy, “A 85 mV
40 nW process-tolerant subthreshold 8 × 8 FIR filter in 130 nm technology,” IEEE Symposium on VLSI Circuits, pp.154–155, June
2007.
[6] Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P. Chen, K. Watanabe, M.

Koichi Ishidareceived the B.S. degree
in electronics engineering from the University
of Electro-Communications, Tokyo, Japan, in
1998, and received the M.S. and Ph.D. degrees
in electronics engineering from the Universityof Tokyo, Tokyo, Japan, in 2002 and 2005, respectively. He joined Nippon Avionics Co., Ltd.
Yokohama, Japan in 1989, where he developed
high-reliability hybrid microcircuits applied toaerospace programs. Since July 2007, he has
been working at Institute of Industrial Science,
the University of Tokyo as a research associate. His research interests include low-voltage low-power CMOS analog circuits, RF wirelesscommunication circuits, and on-chip power supplies. He is a member ofIEEE.

IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011944

Yoshikatsu Ryu
graduated from Kobe City
College of Technology in 1992. In 1992, hejoined SHARP Corporation, Nara, Japan. From1992 to 2001 he was involved in the development of semiconductor processing technology,
and from 2001 to 2009 he was engaged in thecircuit design of analog LSIs. Currently, he
is visiting researcher at Extremely Low Power
LSI Laboratory, Institute of Industrial Science,
the University of Tokyo from 2009. His current interests are low-voltage low-power CMOS
charge pump circuits.

Xin Zhangreceived the B.S. degree in electronics engineering from Xi’an Jiaotong University, Xi’an, China in 2003, the Ph.D. degree inmicroelectronics from Peking University, Beijing, China in 2008. Since 2008, he has been a
project researcher with the Institute of Industrial
Science, the University of Tokyo, Japan. His
current research interests include low-voltage
low-power analog circuit and power supply circuit.

Po-Hung Chenreceived the B.S. degree
in electrical engineering from National Sun Yatsen University, Kaohsiung, Taiwan, R.O.C., in2005 and the M.S. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 2007. He
is currently working toward the Ph.D. degree
in electronic engineering at the University ofTokyo, Tokyo, Japan. His current research interests focus on millimeter-wave circuits, lowvoltage low-power CMOS analog circuits andlow-voltage CMOS DC/DC converters.

Kazunori Watanabe
graduated from theTomakomai technical college in 1975. In 1975,
he joined Matsushita Communication IndustrialCo., Ltd. (present Panasonic Mobile Communications Co., Ltd.), Yokohama, Japan. He
was engaged in development of a digital system for pager. From 1997 through 2003, he has
managed development of the technology for cdmaOne cellular-phone. From 2003, he was engaged in system design development of using
high frequency semiconductor integrated circuitin Panasonic Corporation Semiconductor Company, Kyoto, Japan. He is
visiting researcher at Extremely Low Power LSI Laboratory, Institute ofIndustrial Science, the University of Tokyo from 2009. He is interested inanalog circuits, power supply circuits and wireless communication systems
for extremely low power LSI circuits and systems.

Makoto Takamiya
received the B.S., M.S.,
and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995,
1997, and 2000, respectively. In 2000, he joined
NEC Corporation, Japan, where he was engaged
in the circuit design of high speed digital LSIs.
In 2005, he joined University of Tokyo, Japan,
where he is an associate professor of VLSI Design and Education Center. His research interests include the circuit design of the low-power
RF circuits, the ultra low-voltage digital circuits,
and the large area electronics with organic transistors. He is a member of
the technical program committee for IEEE Symposium on VLSI Circuits
and IEEE Custom Integrated Circuits Conference (CICC).

Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at
the University of California Berkeley, where heconducted research in the field of VLSI CAD.
From 1996, he has been a professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic IC’s and large-area electronics. He has published morethan 400 technical publications including 100 invited presentations and several books and filed more than 200 patents. He will be an executive committee chair for VLSI Symposia and a steering committee chair for IEEE
A-SSCC from 2010. He served as a conference chair for the Symp. on
VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chair for the
A-SSCC, and VLSI symp., an executive committee member for ISLPEDand a program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He is arecipient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits,
2010 IEEE Paul Rappaport award, 2010 IEICE Electronics Society award,
2009 achievement award of IEICE, 2005 IEEE ICICDT award, 2004 IEEE
Takuo Sugano award and 2005 P&I patent of the year award and four product awards. He gave keynote speech at more than 50 conferences including
ISSCC, ESSCIRC and ISLPED. He was an elected AdCom member for
the IEEE Solid-State Circuits Society and an IEEE CAS and SSCS distinguished lecturer. He is a STARC Fellow and IEEE Fellow.