20-ns Short-Circuit Detection Scheme with High
Variation-Tolerance based on Analog Delay
Multiplier Circuit for Advanced IGBTs
Koutaro Miyazaki*, Ichiro Omura†, Makoto Takamiya* and Takayasu Sakurai**†University of Tokyo, Tokyo, Japan
Kyushu Institute of Technology, Japan

Abstract— Advanced IGBTs need to be shut off when a shortcircuit occurs within less than 0.5-µs as the current density ofIGBTs increases. In this paper, a circuit design and themeasurement results are described for an IC chip which enables
the short-circuit detection within 20-ns. The circuit detects theshort-circuit condition by checking the existence of a plateau in agate drive waveform. The proposed scheme can provide muchhigher variation-tolerance compared with the conventional
scheme by introducing adaptive threshold-time determination.
This adaptive feature is realized for the first time using a novel
analog delay multiplier circuit. The chip was fabricated in 0.18µm TSMC high-voltage CMOS technology. The measurements
are carried out and the short-circuit detection operation is
successfully verified even though the gate driving waveform slope
is varied 10 times. The slope variation is cased possibly due to thevariation of the gate drive current and/or the gate capacitance(CGE+CGC). Added to the benefits described above, it does notneed any special off-chip component such as an IGBT with aKelvin emitter, a parasitic inductor, and an inherently slow
current monitor. Thus, it can be applicable to a wide range ofpower circuits with advanced IGBTs.
Keywords—IGBT;
multiplier;short-circuit

detection;

analog

Programmablegate driver
15V 63 PMOSs

VINVDD

978-1-5090-1545-0/16/$31.00 ©2016 IEEEICVSHORT

VGE

Short-CircuitDetector

VGVCEIG(a)Short

VG
VREF

I. INTRODUCTION

VGH

63 NMOSsdelay

A short-circuit detector (SCD) for IGBTs whose typicalconfiguration is shown in Fig. 1(a) has been pursued
extensively but most of the proposals were slow and can’t meetthe need for the future advanced IGBTs which demands lessthan 0.5-µs detection delay. In the figure, VG is generated bydividing VGE using resistors and monitored by the SCD. A
relatively fast SCD was previously reported based on theexistence of a Miller plateau in a gate waveform when shortcircuit does not occur, which achieved 1-µs detection delay [4].
The detection scheme is shown in Fig. 1(b). In this scheme,VREF, above the Miller plateau voltage, VMiller, is preset. Thetime when VG crosses VREF, is signified as tcross. If tcross is earlier
than a certain preset threshold time, tthreshold, that is, tcross falls
in the red Fail region, the short-circuit condition is met and theshort-circuit flag, VSHORT, is asserted. On the other hand, if tcrossfalls in the green Safe region, VSHORT is negated. This scheme
works fine as far as there is no variability in the VG slope.

VDC

VMiller

FailSafe

Normaltcross tthresholdtcrossTime(b)Fig. 1 (a) Example of short-circuit detector setup and (b)conventional short-circuit detection scheme
II. PROPOSED VARIATION-TOLERANT SCHEME
Suppose that there is a VG slope variation as shown in Fig.
2(a) due to the IGBT gate capacitance variation and/or thegate turn-on current variation. If tthreshold is preset as shown in1Fast case
ShortFailVG
VREF

Slow caseNormalVMiller

Short

Safe
NormalConventional: tthreshold is fixed and can’t be chosen properly under variability.
tcross tthresholdtcrosstcross’(a)Fast case
Short
FailSafe

VG
VREF2

Time

Slow case
Short
Safe

FailNormal

VMiller
VREF1tcross’

NormalProposed: tthreshold is adaptively determined.

t1 ’

t1

tthreshold(=αt1)(b)tthreshold’(=αt1’)

TimeFig. 2 (a) Conventional and (b) proposed SCD operation concept with VG slope variation

Short

VG
VDD

VSHORT

VDD

I1
VREF1
VG

α: 4-bit tunable
I2 = I1 / α̶̶+V1+̶Fail

VREF2+

VREF2

NormalVREF1

V1, V2VG

V1>V2V1

CMIM1 CMIM2≤20ns

VINt1(a)

V2>V1

V2V2
VSHORT

VIN

Safe

VSHORTVSHORTtcrosstcross tdetect tthreshold(=αt1)(b)Time

Fig. 3 (a) Circuit diagram of proposed scheme and (b) operation waveforms

2

Fabricated IC(b)Short-Circuit Detector (layout)

Short-Circuit
Detector board

IGBT
Circuit board

100μm

Short-Circuit Detector (photo)

CMIM x 2(a)Comparators& other circuits

200μm(d)(c)

Fig. 4 (a) Test board, (b) chip with pad photo, (c) photo of chip main part and (d) layout of chip main part20
IG=756mA IG=432mAIG=72mA

IG=756mA IG=432mA

IG=72mAVoltage [V]15
VREF2’
10

VREF1’

54ns 11ns

VGE
VSHORT

20ns
VGE
VSHORT

0050

100

150250200
Time [ns]

300

350

400 0

50100150200
Time [ns]250300Fig. 5 Measured VG and VSHORT waveforms for (a) normal case and (b) short-circuit casethe figure, VSHORT is always negated for the slow case sincetcross’ always falls into the green Safe region. If tthreshold is presetat much later time, it is proper for the slow case while it isunacceptable for the fast case. Since there is no overlap
between the yellow region and the sky blue region, it is
impossible to choose a proper tthreshold in this conventional
scheme. Even if the VG slope variation is not that large, theconventional scheme suffers from small margins. In order tocope with this problem, tthreshold is adaptively determined in theproposed scheme as is conceptually shown in Fig. 2(b). Acertain voltage, VREF1, is preset below VMiller. The time whenVG crosses VREF1 is signified as t1. tthreshold is set as αt1 where
the multiplier α is digitally tunable from 1 to 16 using 4-bit
control signals. When VG is slow, t1 is large and tthreshold (=αt1)
is also large. On the other hand, when VG is fast, t1 is small

and tthreshold (=αt1) is also small adaptively. In this way, tthresholdis properly determined in a self-aligned manner even if the VG
slope has variability as shown in Fig. 2(b).
The circuit to realize the above-mentioned concept isshown in Fig. 3(a) together with the operation waveforms inFig. 3(b). When VIN turns on, the MIM capacitors, CMIM1 andCMIM2, start to be charged by I1 and I1/α, respectively. CMIM1
stops to be charged when VG crosses VREF1, that is, at t1. CMIM2
stops to be charged when VG crosses VREF2, that is, at tcross. Attcross, V1 and V2 are compared. If V1 > V2, VSHORT is asserted.
On the contrary, if V1 < V2, VSHORT is negated. The thresholdtime corresponds to the condition that V1 = V2, and thus tthresholdis calculated to be αt1. In this way, the required adaptivity oftthreshold is implemented. This novel analog delay multiplier
circuit using two capacitors multiplies t1 by α to generatetthreshold.

3

TABLE I: Comparison among Short-Circuit Detection Schemes

Reference

[1]

[2]

[3]

[4]

[5]

This work

Detection
delay

2-μs

1.5-μs

3-μs

1-μs

50-ns

20-ns

Additional
components

VCE
sensorNo

Kelvinemitter

NoKelvinemitter

No

VariationtoleranceNANANANANA>10x VG slope(IG: 72mA~756mA)

III. MEASUREMENT RESULTS
The test board photo, the IC photo and the IC layout are
shown in Fig. 4. A double pulse test circuit is built with Si
IGBT (IRG7PH46UPbF) and SiC diode (C4D10120D) as
depicted in Fig.1, which is driven by a programmable driver ICwith 64-level current resolution and 40-ns minimum time step[6]. A single pulse test is employed for the short-circuit
condition. Although only low side was measured here, the SCD
is easily applied for the high side with proper high-voltage
isolators. VDC is set to 50V in order for the short-circuit current
to be not so high. The fabricated chip is covered with dummy
metal patterns and as a result, the circuit pattern is not clearlyvisible. Thus, layout of the circuit is also shown in Fig. 4(d).
Fig. 5 shows the measured waveforms without and with theshort circuit. If there is no short circuit, the Miller plateau ispresent and VSHORT is negated, while when a short circuit
exists, VGE and VG are rising sharply without the Miller plateauand VSHORT is asserted. The circuit successfully functions overwide range of IG variation from 72mA through 756mA, whichcorresponds to more than 10 times the VG slope variation. The
maximum measured short-circuit detection delay is 20ns.
IV. CONCLUSIONS
A novel short-circuit detection scheme is proposed. The
circuit is designed and fabricated using widely used highvoltage CMOS technology. The measurement shows 20-ns
detection delay and 10 times VG slope tolerance.
TABLE I shows the comparison of this work with othershort-circuit detection schemes. It is seen from the table thatthe proposed circuit is demonstrated to provide the fastest andthe most robust short-circuit detection scheme without
additional off-chip components. Consequently, the scheme canbe widely applicable to the power circuits with IGBTs for thefuture.
ACKNOWLEDGMENT
This work supported by the New Energy and Industrial
Technology Development Organization (NEDO) of Japan.
REFERENCES
[1]

[2]

[3]

[4]

[5]

[6]

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