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General-Purpose Clocked Gate Driver IC With
Programmable 63-Level Drivability to Optimize
Overshoot and Energy Loss in Switching by a
Simulated Annealing Algorithm
Koutarou Miyazaki, Student Member, IEEE, Seiya Abe, Masanori Tsukuda, Ichiro Omura, Member, IEEE,
Keiji Wada, Member, IEEE, Makoto Takamiya, Senior Member, IEEE, and Takayasu Sakurai, Fellow, IEEE

Abstract—A general-purpose clocked gate driver integrated
circuit (IC) to generate an arbitrary gate waveform is proposed to provide a universal platform for fine-grained gate waveform optimization handling various power transistors. The fabricated IC with a 0.18 µm Bipolar-CMOS-DMOS process has 63
P-type MOS (PMOS) and 63 N-type MOS (NMOS) driver transistors on a chip whose activation patterns are controlled by 6-bit
digital signals and 40 ns time step control. In the 500 V switching measurements with a manual gate waveform optimization, theproposed gate driver reduces the IC overshoot by 25% and 41%,and the energy loss by 38% and 55% for Si-insulated-gate bipolartransistor and SiC-MOSFET, respectively, which demonstrate thefeasibility of driving various power devices with the same driver.
An automatic optimization by simulated annealing algorithm isintroduced to fully utilize the benefit of the gate driver, and thefurther reduction of IC overshoot by 26% and the energy loss by
18% are achieved over the manual optimization.
Index Terms—Gate driver, insulated-gate bipolar transistor(IGBT), SiC, simulated annealing (SA).

I. INTRODUCTIONGATE driver is a key technology for the switching ofdevices to minimize the switching loss and the current
overshoot. The conventional gate drivers, however, have two
problems: 1) customized design to each power transistor (e.g.,
Si-insulated-gate bipolar transistor (IGBT), SiC-MOSFET) increases the development cost and turnaround time (TAT); and2) limited programmability [2]–[10] prevents a precise gateA

Manuscript received April 18, 2016; revised August 6, 2016 and November
12, 2016; accepted January 20, 2017. Date of publication February 23, 2017;
date of current version May 18, 2017. Paper 2016-PEDCC-0315.R2, presented
at the 2016 Applied Power Electronics Specialists Conference, Long Beach, CA,
USA, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRYAPPLICATIONS by the Power Electronic Devices and Components Committee of
the IEEE Industry Applications Society.
K. Miyazaki, M. Takamiya, and T. Sakurai are with the University of Tokyo,
Tokyo 113-8654, Japan (e-mail: koutaro@iis.u-tokyo.ac.jp; mtaka@iis.utokyo.ac.jp; tsakurai@iis.u-tokyo.ac.jp).
S. Abe, M. Tsukuda, and I. Omura are with the Kyushu Institute of Technology, Fukuoka 804-8550, Japan (e-mail: s_abe@life.kyutech.ac.jp; tsukuda@
ele.kyutech.ac.jp; omura@ele.kyutech.ac.jp).
K. Wada is with the Tokyo Metropolitan University, Tokyo 192-0364,
Japan (e-mail: kj-wada@tmu.ac.jp).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2017.2674601

Fig. 1.

Schematic diagram of general-purpose CGD IC.

waveform optimization for the low noise and the low loss ofthe power transistors. To solve these issues, a general-purpose
clocked gate driver (CGD) integrated circuit (IC) is proposed
to provide a universal platform for fine-grained gate waveform
optimization handling various power transistors including SiIGBT and SiC-MOSFET, thereby reducing the development
cost and TAT for the gate drivers. The programmability of the
proposed gate driver is the finest compared with the previous
gate drivers [1]–[10] and it is shown that the finer programmability realizes the better performance. However, in order to fully
enjoy the benefit of the fine granularity of the proposed gate
driver, a manual optimization may not be sufficient as the degreeof freedom is much increased. Thus, in this paper, an automatic
optimization based on simulated annealing (SA) is introduced
and shows the possibility of the further increase in performance.
II. SYSTEM IMPLEMENTATIONThe schematic diagram of the implemented general-purpose
CGD IC is shown in Fig. 1 [15]. CGD IC is developed
for the switching of power devices at VDC = 500 V. In order to realize programmable 63-level drivability, 63 parallel
drivers are connected to the gate of the power device anda 6-bit binary control signal, BPM OS (BNM OS ), is applied
to specify the number of activated P-type-MOS (PMOS) [Ntype MOS (NMOS)] driver transistors, NPM OS (NNM OS ). A
pair of 6-bit signals (BPM OS and BNM OS ) are latched by

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MIYAZAKI et al.: GENERAL-PURPOSE CLOCKED GATE DRIVER IC WITH PROGRAMMABLE 63-LEVEL DRIVABILITY TO OPTIMIZE

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Fig. 3. Operation waveforms for 63 PMOS transistors to pull up V G in
CGD IC.

Fig. 2.

Binary to thermometer-code decoder.

the clock (CK) and activate the final 63 PMOS (NMOS)
transistors. CK frequency is 25 MHz and 40 ns time step control of the drivability is achieved. The power supply voltage(VDRIVE ) of CGD IC is 10–18 V, and VDRIVE of 15 V is used in
the following measurements. The voltage swing of input digital
signals (BPM OS , BNM OS , and CK) is 5 V, and the swing is increased to VDRIVE by level-shifters. By adjusting the predrivervoltage swing, VPD PM OS and VPD NM OS , from 1.2 to 5 V, theoutput drivability of a single-driver metal-oxide-semiconductor(MOS) transistor can be tuned from 3 to 80 mA. The peak drivability is 63 times of the single driver, which corresponds to the
maximum peak current of the gate current (IG ) from 0.19 A ( =3 mA × 63) to 5 A ( = 80 mA × 63). VPD PM OS andVPD NM OS of 1.8 V are used in the following measurements.
The binary-coded input is indispensable since 63 × 2 input
pins are too many to handle. The binary signals, however, maycause glitch problems in the gate voltage (VG ). The glitch will
break down the power transistors. For example, when the binary
input changes from 011111 (31) to 100000 (32), there is a possibility that the state goes from 011111 (31) to 111111 (63) to100000 (32) causing a few nanoseconds glitch at the predriver,
if there are variability of devices and interconnection designs
which make the most significant bit change faster than the otherbits. This is the cause of the glitch problems. To prevent thisproblem, a small-sized binary to thermometer-code decoder in
Fig. 2 is employed.
Fig. 3 shows operation waveforms for 63 PMOS transistors topull up VG in CGD IC. The operation for 63 NMOS transistors topull down VG is similar. An arbitrary IG waveform is generated
by applying a control bit pattern (BPM OS (BNM OS )) in eachclock cycle with 40-ns step and digitally specifying time andcurrent pairs of ti and IG i (i = 1, 2, 3, . . . , n).
Here, the modeling of the 63-parallel drivers in Fig. 1 is discussed. In the previous segmented gate drivers [10], the transistors in the segmented gate drivers [see Fig. 4(a)] were modeled
as a resistor [see Fig. 4(b)]. The transistors in the segmented
gate drivers, however, are to be modeled as a current source [seeFig. 4. Modeling of gate drivers. (a) Original gate driver. (b) Conventional
resistor model. (c) Proposed current-source model.

Fig. 5. SPICE simulated pull-up and pull-down waveforms of VG with twomodels in Fig. 4. VPD_PMOS and VPD_NMOS are 5 and 1.8 V in (a) and (b),respectively.

Fig. 4(c)] instead of a resistor [see Fig. 4(b)]. Fig. 5 shows thesimulation program with integrated circuit emphasis (SPICE)
simulated pull-up and pull-down waveforms of VG with twomodels in Fig. 4. The capacitance in Fig. 4 is 22 nF emulating the gate capacitance of the power devices. VPD PM OS andVPD NM OS are 5 and 1.8 V in Fig. 5(a) and (b), respectively. It

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Fig. 6.

Die photograph of gate driver IC.

Fig. 7.

Photographs of PCB.

is seen that the gate driver behaves more like a constant-current
driver [see Fig. 4(c)] rather than a resistor [see Fig. 4(b)] becauseof the high output resistance of MOS transistors in a saturation
region. Still, the behavior of a MOS driver is fundamentally similar to a resistor, which has been used for a long time in driving
the power devices. A minor difference is that when considering
the switching between two different driver strength states, thedriver current is the more predictable for MOS drivers whose
driving current is independent from the voltage of the switching,while the driving current is dependent on the switching voltage
and thus timing for a driver based on resistors
The proposed general-purpose CGD IC is fabricated with
40 V, 0.18 µm Bipolar-CMOS-DMOS process. Fig. 6 showsa die photograph of CGD IC. The core size is 2300 µm by
730 µm. The total chip size is 2.5 mm2 , which is determinedby the foundry, although the core size is much smaller than the
total chip size. Fig. 7 shows photographs of printed circuit board(PCB). The 2.5 mm2 CGD IC is placed on the top side of PCB.
Si-IGBT and SiC diodes are placed on the reverse side of PCB.
III. MEASUREMENT RESULTS
Turn-on and turn-off characteristics are measured witha double-pulse setup shown in Fig. 1 with SiC diodes

Fig. 8. Three types of gate waveforms. (a) No active gate drive. (b) Nine-level
active gate drive. (c) Proposed 63-level active gate drive.

(C4D10120D, 1200 V, 18 A) at VDC = 500 V. To demonstrate
the versatility of the proposed general-purpose CGD IC, both
Si-IGBT (IRG7PH46UPbF, 1200 V, 75 A) and SiC-MOSFET(SCH2080KE, 1200 V, 40 A) are driven by CGD IC. Although
in Fig. 1, an IGBT symbol is used for a power device, the IGBT
is replaced by SiC-MOSFET when SiC-MOSFET is under test.
Notations such as IC and VC are used even for the SiC-MOSFET
device just for simplicity. Turn-off characteristics are described
only for Si-IGBT in Section III-B as the results basically do notchange much for the SiC-MOSFET.
A. Turn-on CaseTo show the advantage of the proposed CGD IC with programmable 63-level drivability, three types of gate waveforms
shown in Fig. 8 are compared. Fig. 8(a) shows a conventional“no active gate drive” [11]. To show the tradeoff between the

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TABLE IPARAMETERS USED IN MEASUREMENTS FOR SI-IGBT AND SIC-MOSFET

m
t1
t2

Si-IGBT turn on

SiC-MOSFET turn on

Si-IGBT turn off

31
160 ns160 ns

63
40 ns
80 ns

32
400 ns
400 nsFig. 9. Measured energy loss versus IC overshoot in turn-on characteristics at
500 V switching for Si-IGBT. The load current IL is set to be 15.4 A.

Fig. 10. Measured energy loss versus IC overshoot in turn-on characteristics
at 500 V switching for SiC-MOSFET. The load current IL is set to be 15.4 A.

turn-on energy loss and IC overshoot, IG to pull-up VG is varied
by NPM OS in the measurement. Fig. 8(b) shows a conventional“9-level active gate drive” emulating the 9-level segmented gate
drivers [10]. This waveform is based on [5], [7], [9], and [12].
At the turn on, NPM OS changes from 0 to m and keeps m fort1 . Then, NPM OS changes from m to 9 level of i (i = 2–58 withseven increments in between) and keeps i for t2 . Finally, NPM OS
changes from i to m. Fig. 8(c) shows the proposed “63-level active gate drive.” Fig. 8(c) is the same as Fig. 8(b) except for i.
In Fig. 8(c), i is from 0 to 63 with one increment in between.
Table I shows m, t1 , and t2 in the measurements for Si-IGBT
and SiC-MOSFET, respectively.
Figs. 9 and 10 show measured energy loss versus IC overshootin turn-on characteristics at 500-V switching with the three gate
waveforms shown in Fig. 8 for Si-IGBT and SiC-MOSFET,
respectively. In the no active gate drive, the tradeoff between

Fig. 11. Measured waveforms for Si-IGBT corresponding to Fig. 9. (a) No
active gate drive at the same IC overshoot to (c). (b) No active gate drive at thesame energy loss to (c). (c) Proposed 63-level active gate drive.

the turn-on energy loss and IC overshoot is observed. By using
63-level active gate drive, however, the loss-overshoot tradeoff
can be optimized more compared with cases of nine-level active
gate drive [10] and no active gate drive. In Figs. 9 and 10, theblue open triangle points near the optimum point are observedby changing just one turn-on transistor count (NPM OS ) for thetime segment t2 . It is seen from these figures that the change inthe loss and overshoot by just one step in 63 levels is visible andthus providing 63 levels of driving strength if justified.
The proposed 63-level active gate drive reduces the measured
energy loss at the same IC overshoot by 38% (see Fig. 9) and
55% (see Fig. 10) for Si-IGBT and SiC-MOSFET, respectively.
Similarly, the proposed 63-level active gate drive reduces the2354

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Fig. 12. Measured waveforms for SiC-MOSFET corresponding to Fig. 10.
(a) No active gate drive at the same IC overshoot to (c). (b) No active gate driveat the same energy loss to (c). (c) Proposed 63-level active gate drive.

Fig. 14. Measured waveforms for Si-IGBT corresponding to Fig. 13. (a) No
active gate drive at the same VC overshoot to (c). (b) No active gate drive at thesame energy loss to (c). (c) Proposed 63-level active gate drive.

Fig. 13. Measured energy loss versus VC overshoot in turn-on characteristics
at 500-V switching for Si-IGBT. The load current IL is set to be 52 A.

measured IC overshoot at the same energy loss by 25% (seeFig. 9) and 41% (see Fig. 10) for Si-IGBT and SiC-MOSFET, respectively. The corresponding measured waveforms of NPM OS ,VG , VC , and IC for Si-IGBT and SiC-MOSFET are shown in
Figs. 11 and 12, respectively. The 25% and 41% reduction of
IC overshoot is clearly shown in Figs. 11 and 12, respectively.
In this paper, the search for the best driving waveform iscarried out manually through trial and error by confining thesearch space and by reducing the waveform choices. In general,
however, more time segments can be used and the number of

MIYAZAKI et al.: GENERAL-PURPOSE CLOCKED GATE DRIVER IC WITH PROGRAMMABLE 63-LEVEL DRIVABILITY TO OPTIMIZE

Fig. 15.

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Setup for automatic optimization (yellow part is hardware and blue part is software).

turn-on transistors in each time segment can be selected out of 64
choices. Thus, the search complexity becomes huge and may not
be done manually. For this kind of general case, a machine-based
search method can be effective. An example of the machinebased search using the SA algorithm is reported elsewhere [13].
Even though this paper confined the search space compared withthe more general search space, much improvement is found as
is described above and it can be said that the scheme is effective.
B. Turn-off Case
For the measurements of the turn-off case, the gate drivability
optimization is achieved by changing the turn-on NMOS count,
NNM OS , instead of NPM OS for the turn-on case. One moredifference between the turn-on case and turn-off case measurements is that the voltage overshoot, VC , is taken as the overshootinstead of the current overshoot, IC , in the turn-on case. Similar to the turn-on case in Section III-A, three types of gate
waveforms shown in Fig. 8(a)–(c) are compared.
Fig. 13 shows measured energy loss versus VC overshoot inturn-on characteristics at 500 V switching with the three gate
waveforms shown in Fig. 8 for Si-IGBT. The proposed 63level active gate drive reduces the measured energy loss at thesame VC overshoot by 46%. Similarly, the proposed gate drive
reduces the measured VC overshoot at the same energy loss
by 30%. The corresponding measured waveforms of NPM OS ,VG , VC , and IC for Si-IGBT are shown in Fig. 14. The 30%
reduction of VC overshoot is clearly seen from the figure.
The optimized gate driving waveform is driving relatively
strongly at first and then, reducing the driving strength just before the gate voltage reaches the threshold voltage of the IGBT,
and increasing the strength again. This reduces the sharp voltage
overshoot. The qualitative strategy for the optimized waveform
is consistent with the previous publications [9], [14] and theadvantage of the proposed driver is to achieve the quantitative
optimization by digital control.
IV. OPTIMIZATION BY SA
As is described in the previous section, it is possible to improve the performance of the circuit by the manual optimizationof the gate waveforms by confining ourselves to try the waveforms as shown in Fig. 8. By exploring the wider search space,eight time segments in this case, it may be possible to further

improve the performance. Thus, an automatic optimization isapplied by combining real measurements and a software optimization loop as shown in Fig. 15.
Any strength of drivability from 0 to 64 (× 12 mA) can bechosen for each of eight time segments of 40 ns. Thus, 648 (>1014 ) number of waveforms need to be tried for an exhaustive
search, which is impractical. Thus, SA is applied in this paper.
The target is to minimize the object function, fOBJ , defined asfollows:
fOBJ = E  loss 2 + I  C oversho ot 2
where the energy loss Eloss and IC overshoot IC oversho ot arenormalized as follows:⎧
lo ss, m in⎨E  loss = E E l o s s −E−E
lo ss, m a x
l o s s , m in⎩I  C oversho ot = I C o v e r s h o o t −I C o v e r s h o o t , m i n .
I C o v e r s h o o t , m a x −I C o v e r s h o o t , m i n
The subscript min (max) signifies the minimum (maximum) of
the corresponding quantity. For example, Eloss,m in is set to 0
as an ideal minimum value. On the other hand, Eloss,m ax is themeasured Eloss when the gate drive waveform is the slowest,that is, all of n1 , n2 , . . . , n8 are 1. Here, ni signifies the numberof turn-on NMOS of the gate driver in ith time-segment in
Fig. 1. Likewise, the minimum (maximum) overshoot values
are obtained either by the slowest or the fastest gate driving
waveform. The values of IC oversho ot,m in and IC oversho ot,m ax are
set similar to Eloss,m in and Eloss,m ax . After the normalization,
all of the normalized quantities vary between 0 and 1.
First, a PC randomly generates a new trial waveform, that is,a new waveform vector (n1 . . . n8 ) using MATLAB and sends
control signals to the gate driver through LabVIEW, and thenthe digital oscilloscope receives the measured voltage and current from the board and sends the digital data back to the PC.
Depending on the measured value of fOBJ , the PC generates thenext trial waveform according to the SA algorithm described inFig. 15. The optimization iterations continue until no gain in observed. One physical measurement of about 2 s is needed in one
SA iteration loop and less than 2000 measurements are needed
to complete the optimization, and thus it takes about an hour for
the whole process. No destructive breakdown of power devices
was observed in the optimization process. A greedy optimization algorithm, that is, the hill descending algorithm is also tried
but it stops at a suboptimal point, which is even worse than no2356

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Fig. 16. Measured optimization result by the SA algorithm in turn-on characteristics at 500 V switching for Si-IGBT. The load current IL is set to be
15.4 A.
TABLE IICOMPARISON WITH PREVIOUS GATE DRIVERS

timing control and 63-level drivability, thereby enabling the gate
waveform optimization for both Si-IGBT and SiC-MOSFET.
The time programmability is achieved for the first time andthe 63-level drivability is the largest number of the drivability
levels.
The general-purpose gate driver IC to generate an arbitrary
gate waveform is the universal platform for fine-grained gate
waveform optimization handling various power transistors. The
40-ns step timing programmability is achieved for the first time
and the 63-level drivability is the largest number of the drivability levels in the previously published gate drivers. In the 500 V
turn-on measurements, the proposed CGD reduces the IC overshoot by 25% and 41% and the energy loss by 38% and 55% for
Si-IGBT and SiC-MOSFET, respectively. For a turn-off case,the measurement for Si-IGBT shows that VC overshoot and theenergy loss are reduced by 30% and 46%, respectively. Not only
for the case of turn on, the improvement is also observed for theturn-off case of Si-IGBT.
An automatic optimization by the SA algorithm is introduced
to fully utilize the benefit of the gate driver and the further reduction of IC overshoot by 26% and the energy loss by 18% areachieved over the manual optimization for a Si-IGBT case. The
automatic optimization method can open up a way to effectively
optimize the driving waveform of power devices for the better
circuit performance.
The proposed driver and the optimization method can be used
as a platform for the driving waveform optimization of various
power devices by providing fine tunability.
REFERENCES

active control case. Consequently, it is concluded that a global
optimization algorithm such as SA should be used.
In Fig. 16, the optimization result by the SA algorithm isshown together with the human manual search results. IC overshoot and the energy loss are better than the human manual
search results (see Fig. 9) by 26% and 18%, respectively. Generally speaking, the optimized waveform is a function of several
parameters such as VDC and IL , and a table lookup approach
will be implemented in the future to cope with the parameter
dependence. The optimization is executed in the development
stage. Some may argue that a dynamic on-the-fly optimization ismore suitable but applying a new trial waveform may be risky ina product in operation and moreover when the aforementioned
parameters change from cycle to cycle, as is observed in multilevel converters, it is difficult to optimize on the fly due to theshort time period permitted for optimization.
V. CONCLUSION
Table II shows a comparison of the proposed CGD IC
with previous gate drivers. This work achieved the 40-ns step

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Koutarou Miyazaki (S’16) received the B.S. and
M.S. degrees in electrical engineering and information systems from the University of Tokyo, Tokyo,
Japan, in 2012 and 2014, respectively, where he iscurrently working toward the Ph.D. degree in electronics engineering and information systems.
His research interests include insulated-gate bipolar transistor gate drivers and short-circuit detectors.

Seiya Abe received the M.E. and Dr.Eng. degrees inelectronics from Kyushu University, Fukuoka, Japan,
in 2002 and 2005, respectively.
In 2005, he became a Research Assistant in the Department of Electrical and Electronic Systems Engineering, Graduate School of Information Science andElectrical Engineering, Kyushu University, where in2006 he became a Research Associate and then an
Assistant Professor. In 2010, he became a Research
Assistant Professor at the International Centre for the
Study of East Asian Development. He is currently
an Associate Professor with Kyushu Institute of Technology, Fukuoka. His research interests include switch-mode power supplies.

Masanori Tsukuda received the B.S. degree in electrical engineering from the Shibaura Institute of Technology, Tokyo, Japan, in 2000, and the Ph.D. degree
in engineering from the Kyushu Institute of Technology, Fukuoka, Japan, in 2013.
He is currently with the Green Electronics Research Institute, Kitakyushu, Japan, and with the
Kyushu Institute of Technology as a Visiting Associate Professor. His main research interests include
advanced power semiconductor devices and reliability of power modules/packages.

Ichiro Omura (M’01) received M.S. degree in mathematics from Osaka University, Osaka, Japan, in
1987, and the doctoral degree in electrical engineering from ETH Zurich, Zürich, Switzerland, in 2001.
He was at Toshiba Corporation, Tokyo, Japan, involved in research on power semiconductors, Minatoku, Tokyo, Japan. Since 2008, he has been with
the Kyushu Institute of Technology, Fukuoka, Japan,
where he is the Director of the Next Generation PowerElectronics Research Center.

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Keiji Wada (S’99–A’00–M’01) was born in
Hokkaido, Japan. He received the Ph.D. degree
in electrical engineering from Okayama University,
Okayama, Japan, in 2000.
From 2000 to 2006, he was a Research Associate at Tokyo Metropolitan University, Tokyo, Japan,
and the Tokyo Institute of Technology, Tokyo. Since
2006, he has been an Associate Professor with Tokyo
Metropolitan University. His research interests include medium-voltage inverter, electromagnetic interference filters, and active power filters.
Makoto Takamiya (S’98–M’00–SM’14) received
the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan,
in 1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was involved in the circuit design of high-speed
digital large-scale integration. In 2005, he joined the
University of Tokyo, where he is currently an Associate Professor of the very large-scale integration(VLSI) Design and Education Center. From 2013 to2014, he was at the University of California Berkeley, Berkeley, CA, USA, as a Visiting Scholar. His research interests include thedesign of low-power Radio Frequency circuits, ultra-low-voltage logic circuits,
low-voltage power management circuits, and large-area and flexible electronics
with organic transistors.
Dr. Takamiya is a member of the technical program committee of the IEEE International Solid-State Circuits Conference and the IEEE Symposium on VLSI
Circuits. He received the 2009 and 2010 IEEE Paul Rappaport Awards, and theBest Paper Award in 2013 from the IEEE Wireless Power Transfer Conference.
Takayasu Sakurai (S’77–M’78–SM’01–F’03) received the Ph.D. degree in electrical engineering fromthe University of Tokyo, Tokyo, Japan, in 1981.
In 1981, he joined Toshiba Corporation, Tokyo,
where he designed CMOS dynamic random accessmemory, static random access memory, reduced instruction set computer processors, digital signal processor, and system on chip Solutions. He has worked
extensively on interconnect delay and capacitancemodeling known as Sakurai model and alpha powerlaw metal-oxide-semiconductor model. From 1988
through 1990, he was a Visiting Researcher at the University of California
Berkeley, Berkeley, CA, USA, where he conducted research in the field of verylarge scale integration (VLSI) computer-aided design. Since 1996, he has beena Professor with the University of Tokyo, working on low-power high-speed
VLSI, memory design, interconnects, ubiquitous electronics, organic IC’s andlarge-area electronics. He is also a Domain Research Supervisor for nanoelectronics with the Japan Science and Technology Agency, Kawaguchi-shi,
Saitama, Japan. He has published more than 600 technical publications including 100 invited presentations and several books, and has filed more than 200
patents.
Dr. Sakurai is the Executive Committee Chair for the VLSI Symposia andis a Steering Committee Chair for the IEEE Asian Solid-State Circuits Conference (A-SSCC). He served as a Conference Chair for the Symposium on
VLSI Circuits and IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), a Vice Chair for the Asia and South Pacific
Design Automation Conference, a Technical Program Committee (TPC) Chair
for the A-SSCC and VLSI Symposium, an Executive Committee Member for
the International Symposium on Low Power Electronics and Design (ISLPED),
and a Program Committee Member for the IEEE International Solid-State Circuits Conference (ISSCC), the IEEE Custom Integrated Circuits Conference,
A-SSCC, the IEEE Design Automation Conference, the European Solid-State
Circuits Conference (ESSCIRC), the International Conference on ComputerAided Design, ISLPED, and other international conferences. He received the2010 IEEE Donald O. Pederson Award in Solid-State Circuits, the 2009 and2010 IEEE Paul Rappaport Award, the 2010 Institute of Electrical, Information,
and Communication Engineers (IEICE) Electronics Society Award, the 2009
IEICE Achievement Award, the 2005 IEEE ICICDT Award, the 2004 IEEE
Takuo Sugano Award, the 2005 Patent and Innovation Patent of the Year Award,
and four product awards. He delivered keynote speeches at more than 50 conferences including ISSCC, ESSCIRC, and ISLPED. He was an elected AdCom
Member for the IEEE Solid-State Circuits Society and an IEEE Circuits andSystems and Solid-State Circuits Society Distinguished Lecturer. He is an IEICE Fellow.