14-3
A 1.28mW 100Mb/s Impulse UWB Receiver with Charge-Domain Correlator andEmbedded Sliding Scheme for Data Synchronization
Lechang Liu, Takayasu Sakurai and Makoto Takamiya
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
Abstract
A 1.8V 1.28mW 100Mb/s impulse UWB receiver in
0.18ȝm CMOS for DC-960MHz band is developed. The
proposed receiver features a DC power-free charge-domain
sampling correlator and an embedded sliding scheme for datasynchronization, thereby achieving the lowest energy of
12.8pJ/bit in the state-of-the-art correlation-based UWB
receivers.
Introduction
Impulse radio ultra-wideband (IR-UWB) receiver can beclassified as threshold-detection based receiver [1, 2] andcorrelation based receiver [3]-[5]. Performance comparisonof different topologies is shown in Fig.1. Figs. 1(a) and (b)show the simulated UWB environments with narrowband
interference and band-limited white noise in frequency
domain and time domain, respectively. The simulated BER ofvarious topologies is shown in Fig.1 (c). When the amplitudeof the interference and the noise are much larger than thereceived UWB pulse as shown in Fig. 1(b),threshold-detection based receiver can’t work at all. In
contrast, correlation based UWB receiver can still attainsuperior BER due to the correlation between the received
signal and the template signal of the correlator.
To achieve the correlation operation, the template of thecorrelator must be synchronized with the received signal.
Conventionally, synchronization circuits are implementedwith PLL or DLL at the expense of increased circuit
complexity and increased power consumption [5]. In thispaper, low power correlation based receiver with acharge-domain correlator and an embedded sliding circuits
for data synchronization is proposed.
Receiver Architecture
The proposed topology of the receiver is shown in Fig. 2.
The received signal is first amplified by the front-end
amplifier and then correlated with the discrete template of thecharge-domain correlator. Correlation results are detected by
the following comparators and SR latch convert thecomparison results to the corresponding data bit. If theamplitude of the correlator output Vcor is not large enough totrigger the comparators, data synchronization process will beactivated. The proposed sliding scheme can slide the phasesof sampling clocks until synchronization is achieved.
DC Power-Free Charge-Domain Correlator
One low-power solution for analog design is discrete-timecharge-domain technique. In the literature [6] and [7],addition-based charge-domain technique is introduced to thedesign of mixer and filter. In this work, a novel chargedomain correlator based on both addition and subtraction isproposed. Fig. 3(a) shows the operation of the correlator. Thereceived DC-960MHz band Gaussian first-order derivative
pulse is sampled at 2GSa/s and correlated with the discrete
template determined by the capacitor value in the correlator.
Since the pulse is odd symmetric and the pulse width is 4ns,
only six sampling points are non-zero and six capacitancevalues C1, C2, C3, -C3, -C2 and -C1 can be used to represent thediscrete template for 100Mb/s date rate correlation. As shownin Fig. 3(b), sampling operation is implemented by turning on
the switches controlled by clocks I1, I2…I7 sequentially andsampling results are stored in the capacitors as V1, V2…V7respectively.ҏ In Fig. 3(c), the stored voltages are weighted

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978-4-86348-010-0

summed and averaged by turning on all the Ir controlledswitches. Subtraction operation is implemented byexchanging the two plate connections of the capacitors. Aftersumming and averaging, the correlator output is reset to VDD/2
by clock Ir .
Sliding Scheme for Data Synchronization
Unlike the data synchronization by using the tapped
delay-lines [3] or the digital baseband [5], the proposedsliding scheme enables the data synchronization with simple
circuits by utilizing the 2GHz clock for the samplingcorrelator. The circuits and the timing chart of the proposed
sliding scheme are shown in Fig.4 and Fig.5 respectively.
Before the synchronization is achieved, Vcor is small and is notdetected by the DC-power free comparators [1]. In this case,neither UP nor DN is generated and the clock removal signal(RM) is generated to increase the period of I0 from 10ns to
10.5ns. The sliding scheme finishes the synchronization
process within 19 slides, because the period of input signal isequals to 10ns and differs with I0 by 0.5ns. After thesynchronization is achieved, Vcor is large and is detected by
the comparators. In this case, either UP or DN is generated
and RM is not generated, which keeps the I0 period 10ns. The
20-phase clock is generated by combining the output edges ofthe divide-by-5 divider and the divide-by-4 divider.
Experimental Results
The proposed receiver without front-end amplifier wasdesigned and fabricated in 0.18ȝm CMOS process. The
micrograph is shown in Fig. 6 and the performance issummarized in Table I. Fig. 7 shows the measured waveforms
at 100Mb/s with synchronization circuits disabled andenabled respectively. As indicated in Fig. 5, with and without
synchronization circuits, the sampling clock (I3) period varies
from 10ns to 10.5ns. The measured power dependence ondata rate and the measured BER dependence on the amplitudeof Vin at different bias voltage 'V are shown in Fig. 8(a) andFig. 8(b) respectively. Small 'V achieves high sensitivity atthe expense of high power consumption. Fig. 9 shows energy
and power comparison with the state-of-the-art correlation
based UWB receivers. The proposed UWB receiver withcharge-domain correlator and embedded sliding scheme fordata synchronization achieves the lowest energy consumptionof 12.8pJ/bit at 100Mb/s.
Conclusions
The receiver in 0.18Pm CMOS achieves the lowest
energy consumption of 12.8pJ/bit at 100Mbps in thestate-of-the-art correlation-based UWB receivers.
Acknowledgment
This work is partially supported by CREST/JST.
References[1] L. Liu, et al., Symp. on VLSI Circuits, pp. 118-119, 2008.
[2] A. Tamtrakarn et al., Symp. on VLSI Circuits, pp. 250-251, 2006.
[3] T. Terada et al., Symp. on VLSI Circuits, pp. 30-33, 2005.
[4] J. Ryckaert et al., ISSCC, pp. 114-115, 2006.
[5] Y. Zheng et al., ISSCC, pp. 116-117, 2006.
[6] K. Muhammad, et al., ISSCC, pp. 268-269, 2004.
[7] A. Yoshizawa and S. Iida, ISSCC, pp. 68-69, 2008.
[8] Y. Zheng et al., ISSCC, pp. 118-119, 2008.
[9] F. S. Lee et al., ISSCC, pp. 116-117, 2007.
[10] J. R. Bergervoet et al., ISSCC, pp. 112-113, 2007.
[11] I. O’Donnell et al., Symp. on VLSI Circuits, pp. 248-249, 2006.

2009 Symposium on VLSI Circuits Digest of Technical Papers

200200(c)

00

-1
10
㪇㪅㪈

100

Transmitted Pulse

-90
0.0

0.3

0.6

0.9

1.2

1.5

Frequency (GHz)

500

100

200

300

400

500

300

400

500

300
300

400
400

500
500

time, nsec

00

100200White Noise(Correlation)

White Noise(Thresholding)10-2㪇㪅㪇㪈10-3㪈㪜㪄㪊Interference(Correlation)

10㪈㪜㪄㪋
-30㪄㪊㪇㪄㪉㪌

Interference(Thresholding)time, nsec

00-350-350

freq, GHz40000-300-300
350 0350-70300
time, nsec

-200-200
300 0300-50200

㩷

White Noise
Eb/N0=-5dB

BER-200-200200 0200-30

Bit Error Rate

dBm(GaussianPulseSpectrum)dBm(InterferenceSpectrum)
Power (dBm/MHz)dBm(NoiseSpectrum)(b)

Interference
Eb/N0=-15dB

Received Interference White Noise Transmitted
Signal (mV)
(mV)
(mV)
Pulse (mV)R e c e iv e rIn p u t,inmteVrfe re n c e , NmoVis e O u tp u t,P umlsV e rO u tp u t, m V

㩷-10(a)

-400

100
100

200200-20㪄㪉㪇-10㪄㪈㪇㪄㪈㪌time, nsec
Time(ns)

㪇0㪄㪌

10㪈㪇㪌

Eb/N00(dB)
(dB)
Eb/N

Fig. 1. Simulated UWB environments with narrowband interference and white noise. (a) Frequency domain. (b) Time domain. (c) BER vs. Eb/N0.
SR
Latch

Comparator

Vin

VH

OUT

Capacitance
C3
C2
C14ns

Voltage

VL

6ns
Vin

TemplateVin (Data “1”)VDD/2Discrete
Template

Clock Removal
for Sliding Scheme

CLKFig. 4

Comparators
High level thresholding

VinI0I0
DIV410100110.5ns 10.5ns 10.5ns10ns10ns10ns

01083 Pm

Fig. 6. Micrograph and layout.
Table. I Performance summary.

1 0 1 0 1 1 0 0VinCLKCLKI3

I320 Pulses

10ns

1 0 1 0 1 1 0 00.0㪇㪉㪋㪍㪏
Data Rate (Mb/s)

100mW

10-3284mV

10-5
㪈㪇

050

100

150

200

RX Signal Vin Amplitude (mV)

10nJ/bit'V=268mV 276mV

Clock
Generator

0.53mW

10mW
[3]

[4]
[9]

[11]
1mW
100k

1M

0.12mW
1.28mW
12.8pJ/bit
5561Pm2

[10]

[8]

J/bit

10-2

10-4'V = 284mV

1.8V100Mbps
2GHzBPSK

1n'V = 276mV

Supply Voltage
Data Rate
Clock Frequency
Modulation

Comparator
Total
Energy per bit
Core Area

Power Consumption

0.9BER

Power Consumption (mW)

1.20.18Pm
CMOS

PowerFig. 7. Measurement results at 100Mb/s. (a) Without sliding scheme. (b) With sliding scheme.

10-1

Technology

Correlator &0.63mW
Synchronization

OUT

100Ir

Ir

1.02 mm

1OUT

(b)

1.5

C1Ir

Ir

In Sync

CLK’

10.5nsC2VcorFig. 5. Timing chart of sliding scheme.

'V = 268mVIr

CLKVinIr

67 Pm

DIV5C3Ir
C3Ir
C2RM

CLK(2GHz)0 1 1 0 0 1 0 10.3

I7

I020-Phase Sampling Clock Generator

0.6

I61.02 mm

UP

RM

CLK’19 Pulses

I5

Vcor

DN

Fig. 4. Circuits for sliding scheme.

OUT

C1(b)

Vcor

Clock Removal
UP&DN
DN

(a)

I7

C2(c)

Out of Sync (Sliding Scheme)

Edge
Combiner

C3

I6

C3Fig. 3. Charge-domain correlator. (a) Timing chart. (b&c) Circuit schematics in(b) sampling operation and (c) summing and averaging operation.

OUT

VL='V

I7Ir

I5(a)

SRLatchPulse-WidthLimiter
UP

I0

I3

C2

CLK
I0 Trigger
I1
I2VinAddition
I3
I5Ir
I6 Subtraction
C1V/2
I7DD
Ir Summing&Ir
Averaging

Fig. 2. Impulse UWB receiver with charge-domain correlator andsliding scheme.

Low level thresholding

I2

Subtraction

Ir

100MHz 20-Phase
Sampling Clock Generator

VH=VDD-'V

I1

C1
VDD/2

Time

I0 ~I Ir

Vcor

Addition

10M

10pJ/b
it

Vcor

0p
J/b
it

AMP

Charge-Domain
Correlator

10BPSKThis Work(w/o Amp)

100M

1G10G

Data Rate (bps)Fig. 8. Measurement results. (a) Power vs. data rate. (b) BER vs. amplitude of Vin. 䋨'V is defined in Fig. 4.䋩 Fig. 9. Comparison with correlation based UWB receivers.

2009 Symposium on VLSI Circuits Digest of Technical Papers

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