Device-Circuit Interactions in Extremely Low Voltage CMOS Designs (Invited)
Hiroshi Fuketa1, Tadashi Yasufuku1, Satoshi Iida1, Makoto Takamiya1,Masahiro Nomura2, Hirofumi Shinohara2, Takayasu Sakurai1
1Institute of Industrial Science, University of Tokyo, Japan
Semiconductor Technology Academic Research Center (STARC), Japan

2

Email: {fuketa, tdsh, mtaka, tsakurai}@iis.u-tokyo.ac.jp, {nomura.masahiro, shinohara.hirofumi}@starc.or.jp

Introduction

Minimum Operating Voltage (VDDmin)
Fig. 2 shows a closed-form expression of VDDmin of logicgates when the number of gates is relatively large [3]. VDDmincan be expressed as a linear function of square-root oflogarithm of the number of logic gates. This means that
VDDmin rises as the number of logic gates increases. The slopeof the function is proportional to the standard deviation of
the within-die variation in the threshold voltage (VTH)difference between pMOS and nMOS transistors (σpn), andthe intercept depends on the balance between intrinsic
strengths of pMOS and nMOS transistors (β), device

978-1-4577-0505-2/11/$26.00 ©2011 IEEE

10-2
10-3
10-4
10-51.0Power

10-8
10-9

0.8Delay

0.6
0.4

10-10

Energy10-1110-12
0.1 0.2(PD product)

Vopt

0.4

0.6

0.2
01.00.8

Eopt

Fig. 1: Simulated dependence of power, delay, and energy of CMOS
logic circuit on supply voltage in 65nm CMOS process. Energy has its
optimum value (Eopt).

ln⁄
ln

Slope:- Within-die VTH variation- Device parameter (η)

VDDminExtremely-low-voltage operation in VLSI’s is quite
effective in reducing the power dissipation [1]. Fig. 1 shows
simulated delay, power, and energy (power delay product) ofa CMOS logic circuit. As the supply voltage (VDD) is
reduced, the delay increases, whereas the power dissipation
dramatically decreases. Therefore, extremely-low-voltage
operation has been considered to be suitable for low-power
applications in which circuit speed is not a primary concern
or can be compensated by parallelization. For suchapplications, an energy per instructions is a key metric. As
shown in Fig. 1, the energy has its optimum value (Eopt), andVopt is defined as VDD at which the energy becomes optimum.
Since the operation at Vopt can achieve the most energyefficiency, Vopt is the target supply voltage for ultra-lowpower applications.
VDD reduction, however, could cause functional errors [2],which might make it impossible to operate at Vopt. Therefore,
investigations on the minimum operating voltage (VDDmin),which is the supply voltage where the first functional error
occurs, are essential for extremely-low-voltage CMOS
designs.
In this paper, what determines VDDmin is explained first, andthen the dependences of VDDmin and energy on device
parameters, such as threshold voltage, subthreshold swing
parameter, and DIBL coefficient, are discussed.

10-1

10-7

NAND2 FO1 Delay (s)Normalized power

100

Normalized energy

Abstruct
In this paper, energy and minimum operating voltage(VDDmin) are investigated for extremely-low-voltage CMOS
logic designs. The dependences of energy and VDDmin ondevice parameters, such as threshold voltage, subthresholdswing parameter, and DIBL coefficient, are examined basedon simulations and measurements.

⁄⁄ ): Intrinsic strength (: Subthreshold swing parameter([mV/dec])∆)(η: DIBL coefficient∆: Thermal voltage: Within-die VTH variation

Intercept:- Balance between pMOS and nMOS
- Device parameter (n, η)- Temperature (UT)/

( : the number of stages)

Fig. 2: Closed-form expression of median VDDmin of logic gates wherepMOS and nMOS are not perfectly balanced. N must be relatively large(more than 10-100). σpn represents standard deviation of within-die VTHvariation.

parameters, such as subthreshold swing parameter (n) andDIBL coefficient (η), and temperature (UT).
Fig. 3 illustrates VDDmin’s with various configurations ofwithin-die VTH variation obtained by Monte Carlo SPICE
simulations and the closed-form expression (Fig. 2).
Simulated results indicate VDDmin is proportional to squareroot of logarithm of the number of logic gates. Fig. 4 shows
the dependence of VDDmin of inverter chain on σpn. As thenumber of gates increases, the rise in VDDmin due to withindie VTH variation is enlarged. This means mitigating VTH
variation is effective in reducing VDDmin, especially for large-25.1.1

IEDM11-559

: Monte Carlo SPICE sim.
: Equation

INV 2NAND

300

250

Inverter chain
N stages

σpn=1.5 (a.u.)150
σpn=1.0 (a.u.)100

σpn=0.4 (a.u.)

500

10ln ( N / 2 )101

22NAND chain

200

VDDmin (mV)

VDDmin (mV)

250
200

Measurement
Equation (with fitting)

2102

100
50

3103

N stages150

INV: 20 dies
2NAND: 14 dies

00

104

100M gates

102

103 104 105

3NAND chain

4NAND chain

N stages

N stages250

250
200-87mV

200

150

1k gates

VDDmin (mV)

VDDmin (mV)

101

3.5

Fig. 5: Measured and calculated VDDmin’s of inverter and 2-input NANDchains in 65nm process.

350

1005000.5

1.0

σpn (a.u.)

1.5150100(standard deviation of within-die VTH variation)

0: 2NAND: 4NAND: INV: 3NAND

50Fig. 4: Dependence of VDDmin’s of inverter chain on σpn, whichrepresents standard deviation of within-die VTH variation in 65nm
process. If σpn is reduced by 50%, VDDmin of 100M inverters decreases
by 87 mV.

021ln ( N / 2 )

101

2102

3103

104

Number of stages (N)scale circuits. For example, VDDmin of 100M inverters
decreases by 87 mV if σpn is reduced by 50%.
In addition, various gate chains were fabricated in a 65nm
CMOS process, and VDDmin’s of them were measured. Themeasurement results of the inverter and 2-input NAND
chains are shown in Fig. 5. The closed-form expression (Fig.
2) also agrees with the measurement results.
Fig. 6 shows simulated VDDmin’s of the inverter andNAND chains. VDDmin’s of logic gates containing the larger
number of stacked/paralleled transistors are much higher.
This is because stacking and paralleling transistors containedin the NAND gate worsen the balance of the strength ofpMOS and nMOS, which corresponds to the increase inparameter |b| in the closed-form expression (Fig. 2).
Although VDDmin can be reduced by adjusting the balance

IEDM11-560

3

Number of stages (N)Fig. 3: VDDmin’s of inverter chain obtained by Monte Carlo SPICE
simulations and closed-form expression (Fig. 2) with various σpn’s in
65nm process. σpn’s are normalized by nominal value of this process.

02ln ( N / 2 )2

Number of stages (N)300

1Fig. 6: Simulated VDDmin’s of inverter and 2-, 3-, 4-input NAND chains.
Slope is hardly affected by the number of transistor stacks.

between the strength of pMOS and nMOS, it is usually
impractical, since the gate sizes of either pMOS or nMOS
transistors must be significantly enlarged for the adjustment,
and hence it is not acceptable due to the area constraint [4].
Therefore, the logic gates with a lot of inputs should not be
used in the design of extremely-low-voltage CMOS logic
circuits.
In Fig. 6, it should be noted that the increase in thenumber of transistor stacks does not affect the slope which isproportional to σpn. It is well known that σpn is proportional
to 1 L × W [5]. For gate delays, transistor stack helps
average gate delay variations induced by within-die VTH

25.1.2

: Thermal voltage
η: DIBL coefficient: Active time ratioLeakagepower

D ∝ VDD I ON
Simplified energy model

E = P⋅D2∝ VDD (ξ + I OFF I ON )
ξ ∝a1.0Memory( ~ .

0.80.6)Logic( ~ . )

0.4
0.2
000.2

0.4

0.6

0.8

32
100

VTH=0.3-0.6V
0.2 0.4 0.6 0.8 1.0

VDD (V)(a) Logic ( ~ . )Initial0100200300400500-400 -300 -200 -100

VTH=0.2V

3200Reverse

Fig. 9: Measured dependence of VDDmin in 100k-stage 2NAND chain on
body bias of pMOS and nMOS in 65nm process.

n=1.5
η=0.1

: n=0.5 (S=30mV/dec): n=1.0 (S=60mV/dec): n=1.5 (S=90mV/dec): n=2.0 (S=120mV/dec)
540.2 0.4 0.6 0.8 1.0

VDD (V)(b) Memory ( ~ .

100 200 300 400 500PMOS body bias[mV]

VTH=0.4-0.6V
VTH=0.3V

10Forward

1.0

Energy (a.u.)

4
VTH=0.2V-200

Vopt (logic) VDD (V)Energy (a.u.)

Energy (a.u.)

4n=1.5
η=0.1-300-100

Vopt (memory)

Fig. 7: Simplified energy model and dependence of energy on activity
factor (a). Active time ratio ξ is introduced to express dynamic power,
and is considered constant for simplicity.
5Reverse⎛ ηVDD −VTH ⎞⎜⎜⎟⎟nU T⎝⎠VDDmin [mV]
375355335315295275255235215195175155
135

100k-stage
2NAND
Measured32100)

Dependences of Energy and VDDmin on Device
Parameters
In order to comprehend the dependence of energy on VDD,
a simplified energy model shown in Fig. 7 is introduced.
Figures regarding energy shown in this section are obtainedby this energy model. Fig. 7 illustrates the normalizedenergies of a typical logic circuit and memory. Vopt depends
on activity factor. Vopt’s of circuits with higher activity
factors, such as logic circuits, are lower and may becomeless than 0.3V.
Fig. 8 shows the dependence of energy on VTH. As long as
Vopt is less than VTH, Vopt and Eopt hardly depend on VTH [7].
In this case, lower VTH is preferable, since the decrease in
VTH can improve the circuit speed without any energypenalties.
On the other hand, VTH itself does not determine VDDmin.
Fig. 9 illustrates the measured dependence of VDDmin in

n=1.0
VTH=0.4V
η=0.1

0.2 0.4 0.6 0.8 1.0

VDD (V)

Fig. 8: Energy dependence on VTH. Vopt and Eopt do not depend on VTH aslong as Vopt is less than VTH.

variation, since the number of active transistors contributing
the gate delay increases [6]. In contrast, no such averaging
effect is observed for the dependence of VDDmin on thenumber of transistor stacks as shown in Fig. 6.

n=2.0(a) Logic ( ~ . )Energy (a.u.)

Dynamicpower

I OFF ∝ e

NMOS body bias[mV]P ∝ ξI ONVDD + I OFFVDD

Normalized energy⎛ (1+η )VDD −VTH ⎞⎧⎜⎟⎟(VDD < VTH )⎪ e ⎜⎝ nUT⎠I ON ∝ ⎨α⎪⎩((1 + η )VDD − VTH ) (VDD > VTH )-400

Forward: Carrier saturation index: Subthreshold swing parameter: Activity factor

n=2.043

VTH=0.4V
η=0.12n=1.01000.2 0.4 0.6 0.8 1.0

VDD (V)(b) Memory ( ~ .

)Fig. 10: Energy dependence on subthreshold swing parameter (n;S = 60 × n mV/dec). Vopt and Eopt strongly depend on n, and they are
reduced as n decreases.

100k-stage NAND2 chain on body bias of pMOS and nMOS
[4]. When pMOS and nMOS are well-balanced, VDDmin islowest as shown in the optimal body bias line. In contrast,
when pMOS and nMOS are unbalanced, VDDmin increases.
This is because VDDmin does not depend on the absolute valueof VTH but is determined by the relative relation between
pMOS and nMOS, which is represented by parameter |b| inthe closed-form expression (Fig. 2).
Fig. 10 shows the dependence of the energy on
subthreshold swing parameter (n). Eopt and Vopt are reduced
as n decreases. Fig. 11 illustrates the dependence of VDDmin’sof logic circuits on n obtained by the closed-form expression(Fig. 2). The decrease in n also reduces VDDmin.
Fig. 12 depicts the dependence of the energy on DIBL
coefficient (η). While the energy does not depend on η forlogic circuit, Eopt is reduced as η decreases for memory, since
the influence of leakage energy increases as the activity
factor (a) is lowered.

25.1.3

IEDM11-561

: η=0: η=0.15: η=0.1

η=0.1

250

n=2.0

η=0-0.2
VTH=0.4V
n=1.50.2 0.4 0.6 0.8 1.0

η=0.232
1 V =0.4VTH0n=1.50

VDD (V)(a) Logic ( ~ . )1500212ln ( N / 2 )
101

103

34105

η=00.2 0.4 0.6 0.8 1.0

VDD (V)(b) Memory ( ~ .

)Fig. 12: Energy dependence on DIBL coefficient ( η = ΔVTH ΔVDS ).
Although energy does not depend on η for logic circuit, Eopt is reducedas η decreases for memory. This is because influence of leakage energy
in memory is much larger than that in logic circuit.

n=1.0100
50

References
[1]

107

(N: the number of stages)[2]

Fig. 11: VDDmin dependence of logic gates on subthreshold swing
parameter (n; S = 60 × n mV/dec) obtained by closed-form expression
shown in Fig. 2. Decrease in n reduces VDDmin, since intercept of VDDmin
expression is proportional to n.

[3]Conclusion
In this paper, energy and VDDmin in extremely-low-voltage
circuits were discussed. Insights obtained from thediscussions are; (1) VDDmin is expressed as a function of thenumber of logic gates and its slope depends on within-die
VTH variation. Thus, a mitigation of within-die VTH variation
can significantly reduce VDDmin. (2) The decrease insubthreshold swing parameter, that is, making thesubthreshold slope steeper, is effective in reducing both theoptimum energy (Eopt) and VDDmin. (3) The decrease in DIBL
coefficient (η), that is, mitigating the short-channel effectcan reduce Eopt of circuits with lower activity factors, such asmemory.

[4]

[5]

[6]

[7]

Aknowledgements
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy andIndustrial Technology Development Organization (NEDO).

IEDM11-562

100200032: η=0.24Energy (a.u.): n=1.0 (S=60mV/dec): n=1.5 (S=90mV/dec): n=2.0 (S=120mV/dec)

300

VDDmin (mV)

Energy (a.u.)4

25.1.4

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