0.35V, 4.1W, 39MHz Crystal Oscillator
in 40nm CMOS
Akira Saito1, Yunfei Zheng2, Kazunori Watanabe1, Takayasu Sakurai2, and Makoto Takamiya2
1

Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan,
2

University of Tokyo, Tokyo, Japan1{saito.akira, watanabe.kazunori}@starc.or.jp, 2{yfzheng, tsakurai, mtaka}@iis.u-tokyo.ac.jp
multiplier [6], and the generated frequency of 315MHz is used as
the carrier frequency.

ABSTRACTA design methodology for sub-0.5V crystal oscillators is shown torealize an all-sub-0.5V ultra low power RF transceiver for
wireless sensor networks. To reduce the minimum operating
voltage (VDDmin) of the crystal oscillator, both the optimization of
the gate width of the CMOS inverter in the crystal oscillator andthe reduction in gate length by CMOS technology scaling are
required. In accordance with the developed design methodology,
a 39MHz crystal oscillator is designed and fabricated in a 40nm
CMOS. The measured power consumption is 4.1W at 0.35V and
39MHz, and the power supply voltage is the lowest among thepreviously reported crystal oscillators.

The remainder of this paper is organized as follows. Section 2
presents the design of the sub-0.5V crystal oscillator. Section 3
presents the measured results of the crystal oscillator in a 40nm
CMOS. Finally, Section 4 presents the conclusion of this paper.

ZQ

Quartzcrystal(a)Categories and Subject Descriptors

C2

B.7.1 [Hardware]: Integrated Circuits, Types and Design Styles–Advanced technologies

C1

General Terms

ZC

Measurement, Performance, Design

Keywords
Crystal oscillator, Pierce oscillator, Sub-threshold characteristics,
Low Power, Low Voltage, Wireless Sensor Networks

RS

(b)

1. INTRODUCTION

C2

CS
CP

LS

An ultra low power RF transceiver is required for wireless sensor
networks. Reducing the power supply voltage (VDD) is effective
for reducing the power consumption of the transceiver. Sub-0.5V
RF receiver circuits [1-4] have been reported. VDD is 0.5V in [1-3]and 0.25V in [4]. A sub-0.5V FBAR oscillator using a forwardbiasing bulk has been reported [5]. A sub-0.5V crystal oscillator,
however, has not yet been reported. Without a sub-0.5V crystal
oscillator, all-sub-0.5V low power RF transceiver cannot berealized. The feasibility of the sub-0.5V operation of a crystal
oscillator, however, has not yet been clarified. Therefore, thepurpose of this study is to clarify a design methodology for the
sub-0.5V crystal oscillator and to demonstrate the sub-0.5V ultra
low power operation of the crystal oscillator in a 40nm CMOS.
The target frequency of the crystal oscillator is 39MHz. Thisfrequency is multiplied by 8 by a 0.6V injection-locked frequency

C1

RS

(c)

CS

Re( Z C )   R N
ZCLS

Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies are
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ISLPED’12, July 30– August 1, 2012, Redondo Beach, California, USA.
Copyright 2012 ACM 978-1-4503-1249-3/12/07...$10.00.

Figure 1: Pierce crystal oscillator. (a) Basic circuit (biasing
omitted). (b) Equivalent circuit. (c) Equivalent circuit of (b).

333

Figure 1, assuming that gm in Equation (4) is determined by theparallel connection of the nMOSFET and pMOSFET.

2. DESIGN FOR SUB-0.5V CRYSTALOSCILLATOR
2.1 Principle of Pierce Oscillator

2.2 Design Strategy for Sub-0.5V Operation

In the design of a crystal oscillator, the negative resistance is an
important design parameter. An oscillator circuit oscillates whenthe magnitude of the negative resistance is larger than theresistive loss in the quartz crystal. However, an MOS transistor
itself does not exhibit I-V characteristics with a negative
resistance as observed in a tunnel diode. The Pierce oscillator
produces a negative resistance with a transistor and capacitors,
and is a typical crystal oscillator.

In this section, a design strategy for the sub-0.5V crystal oscillator
is discussed. Figure 3 shows the relationships between thecondition required for oscillation and the circuit parameters in the
Pierce crystal oscillator. The crystal oscillator oscillates when it
satisfies the condition

R N  RS ,(5)

where RS is the parasitic resistance of the quartz crystal shown in
Figure 1(b). Equation (2) shows that RNQ is proportional to gm.
Equation (4) also shows that RN depends on gm. In the abovethreshold region, where the gate-to-source voltage (VGS) is larger
than the threshold voltage (VTH), gm of the MOSFET is expressedasFigure 1(a) depicts the Pierce crystal oscillator. The quartz crystal
and load capacitors (C1 and C2) are connected to an nMOSFET.
Figure 1(b) shows an equivalent circuit of the Pierce oscillator.
The quartz crystal is represented as a serial connection of RS, CS,
and LS, and a shunt capacitor (CP). In the Pierce oscillator, thecircuit impedance ZQ excluding that of the quartz crystal, isexpressed as [6]

gm 

 1 
 1 
1
1
  g m  
 ,

 
ZQ 
jC1 jC2  jC1 
 jC2 W
VGS  VTH  ,L(6)

where L is the gate length and W is the gate width. When VDD and
VGS are reduced, gm and RN decrease, terminating the oscillation.
To keep gm constant when VDD is reduced, W/L should be linearly(1)where  is the angular frequency of oscillation and gm is thetransconductance of the transistor. The real part of ZQ corresponds
to the negative resistance (-RNQ, RNQ >0) observed from thequartz crystal. -RNQ is expressed as [7]

VDD

 1 
 1 
g
  g m     2 m   RNQ .
ReZ Q   
 C1C2
 jC1  jC 2 
(2)On Chip

The negative resistance is realized by the multiplication of 1/jC1
and 1/jC2. To increase RNQ, gm should be increased and C1 andC2 should be decreased.

C1

Figure 1(c) shows a circuit equivalent to that in Figure 1(b). The
total impedance, excluding RS, CS, and LS, is denoted as ZC. ZC
consists of ZQ and CP, and is thus expressed as [8] 1 
 // Z Q .
Z C   jC P 

Off ChipRF

C2

Figure 2: Pierce crystal oscillator with CMOS inverter.
CPARA

(3)
Oscillation condition

R N  RSThe real part of ZC is the negative resistance (-RN, RN >0)
observed from the serial connection of RS, CS, and LS. By
substituting Equations (1) and (2) into Equation (3), RN is
expressed as [6]C1

Equation (4)g m C1C2
ReZ C     RN22
g mCP    C1C2  C P C2  C P C1 2
.

C2

CPARA

gm

C PARAC PARA  W

(4)

gm 

W
VGS  VTH 
L(Above threshold)gm W q VGS  VTH  
exp 

L
nkT


(Sub-threshold)

When CP =0, Equation (4) is equal to Equation (2).

W

In chip implementation, a Pierce oscillator with a CMOS inverter
is often used. Figure 2 shows a Pierce crystal oscillator with a
CMOS inverter. The nMOSFET in Figure 1(a) is replaced with
the CMOS inverter and a feedback resistor (RF). RF induces half
VDD biasing to the CMOS inverter. The Pierce oscillator with the
CMOS inverter in Figure 2 is equivalent to the Pierce oscillator in

L

V DD

Circuit parameters

Figure 3: Relationships between condition required foroscillation and circuit parameters in Pierce crystal
oscillator.

334

minimize VDDmin. The reduction of L increases gm, and theminimum L is determined by CMOS technology. CMOS
technology down scaling also reduces CPARA, thereby increasing
RN.

increased approximately proportionally to 1/VDD. In contrast, inthe sub-threshold region, where VGS is smaller than VTH, gm of the
MOSFET is expressed as

gm W q VGS  VTH   ,
exp

L
nkT



(7)

2.3 Gate Width Optimization
In this section, optimization of the gate width (W) to reduce
VDDmin for the crystal oscillator is discussed. Figure 4 shows thesimulated dependence of the negative resistance (RN) normalized
by RS on VDD in the crystal oscillator. In this SPICE simulation,
the W values of the nMOSFET and pMOSFET are the same. L is
fixed to 40nm. The resonant frequency of the quartz crystal is39MHz. The other simulation conditions are RS=60C1=C2=5pF,
and RF=500k. The crystal oscillator can oscillate when RN/RS >1. This figure clearly shows that an increase in W reduces VDDmin.
In the case of W  1 m, the crystal oscillator requires VDD above
1.0V to oscillate. The sub-0.5V oscillation requires W  100 m.
For example, in the case of W  100 m, VDDmin (= VDD at RN/RS= 1) is 0.49V and the maximum operating VDD (VDDmax) (= VDD
when RN/RS = 1) is 0.97V. The operating range of VDD is 0.48V(=VDDmax-VDDmin).

where q is the elementary electric charge, n is constant (1<n<2), k
is the Boltzmann coefficient, and T is the absolute temperature.
To keep gm constant when VDD is reduced, W/L should be
exponentially increased approximately proportionally to
1/exp(VDD). When W is increased, the parasitic capacitance of thetransistor (CPARA) also increases because

C PARA  W .

(8)

Normalized negative resistance(=RN/RS)

According to Equation (4), RN decreases as CPARA increases,
because CPARA is added to C1 and C2. Therefore, a large W
increases RN by increasing gm, while it reduces RN by increasing
CPARA. The trade-off relation suggests that an optimal W exists to

In Figure 4, RN/RS at W = 1m monotonically increases with VDD,
because the transistors operate in the above-threshold region. As
shown by Equation (6), gm linearly depends on VGS, and RN
monotonically increases with VGS, as shown by Equation (4). In
contrast, RN/RS at W > 10m does not monotonically increase
with VDD, because the transistors operate in the sub-thresholdregion. As shown by Equation (7), gm exponentially depends on
VGS, and RN increases in the low-VDD region and decreases in thehigh-VDD region with increasing VGS, as shown by Equation (4).

10
VDDmin

W=100m

W=10m
W=1m

W=1mm
W=10mmVDDmax1

Figure 4 also shows that an increase in W reduces the peak valueof RN/RS. As W increases, both VDDmin and VDDmax decrease andthe VDD range (VDDmax-VDDmin) also decreases. At W  20 mm,
the crystal oscillator cannot oscillate for all values of VDD. Thiscan be explained by the increased CPARA caused by the increases
in W, because CPARA is added to C1 and C2.

VDD range @ 100m
W=20mm

0.1
0

0.2

0.6

0.4

0.8

1.0

1.2

1.4

Figure 5 shows the simulated dependence of VDDmin on W. The
squares at high VDDmin values (in the above-threshold region) can
be fitted as

VDD (V)

Figure 4: Simulated dependence of negative resistance (RN)
normalized by RS on VDD in crystal oscillator. The crystal
oscillator can oscillate when RN/RS > 1.

V DDmin  a

1.8
1.6

V DDmin  a

VDDmin (V)1.4

VDDmin  c log W  d ,1.0
sub-threshold

0.6
VDDmin  c log W  d

0.2
0
0.1m

CPARA
1m

10m

100m

1mm

(10)

at W > 1m, as shown by the dotted line in Figure 5, where c andd are constants. Equations (9) and (10) can be derived from
Equations (6) and (7), respectively, assuming that gm is constant.
This curve fitting means that VDDmin at W  1 m is determinedby the above-threshold operation, while VDDmin at W > 1m isdetermined by the sub-threshold operation. A VDD of 0.8V is
twice of the threshold voltage. At the gate width W  200 m, thesquares shift away from the dotted line. This shift can be
explained by the reduced negative resistance caused by theincrease in CPARA with increasing W. This results in the lower
VDDmin limit of 0.28V.

above threshold

0.8

(9)

at W  1 m, as shown by the dashed line in Figure 5, where aand b are constants. The squares at low VDDmin values (in the subthreshold region) can be fitted as

1
b
W

1.2

0.4

1
b,
W

10mm

Gate Width (W)Figure 5: Simulated dependence of VDDmin on W at
L=40nm.

335

2.4 CMOS Technology Scaling

2.5 Low Power Design

In this section, reduction of the gate length (L) by CMOS
technology scaling to reduce VDDmin for the crystal oscillator is
discussed. Figure 6 illustrates the SPICE-simulated dependence ofVDDmin on W in the case of three different CMOS technologies.
The L values are 40nm, 160nm, and 360nm in the 1.1V 40nm,
1.8V 160nm, and 3.3V 360nm CMOSs, respectively. The curve of
the 1.1V 40nm CMOS is the same as that in Figure 6. As L
decreases, VDDmin decreases at a fixed W, because gm is
proportional to 1/L, as shown in Equations (6) and (7). As
discussed for Figure 5, the lower limit of VDDmin is determined by
CPARA. The lower limit of VDDmin in the 40nm, 160nm, and 360nm
CMOSs are 0.28V, 0.41V, and 0.78V, respectively. In thismanner, the lower limits of VDDmin is reduced by CMOS
technology scaling, because CPARA is reduced by CMOS
technology scaling. Therefore, the CMOS technology scaling iseffective for reducing VDDmin for the crystal oscillator. For
example, to achieve a sub-0.5V crystal oscillator, a 40nm or
160nm CMOS is required, as shown in Figure 6.

In this section, the reduction of power by reducing VDDmin for the
crystal oscillator is discussed. Figure 7 depicts the SPICEsimulated dependence of the power consumption at VDDmin on W
for three different CMOS technologies. The power consumption
is minimum at W  1 mm in all three different CMOS
technologies. At W  1 mm, although VDDmin is constant, as shownin Figure 6, the power consumption increases with increasing W,
because CPARA increases and the relevant switching power also
increases.
In summary, as shown in Figure 7, the design strategy to reduce
VDDmin for the crystal oscillator involves (1) the optimization of
W and (2) the reduction of L by CMOS technology scaling. W
has an optimum value, because the large W increases RN by
increasing gm, but it reduces RN by increasing CPARA. The
reduction of L increases gm and reduces CPARA, thereby increasing
RN and reducing VDDmin, as shown in Figure 3.

3. MEASUREMENT RESULTS
3.1 Chip Implementation
In accordance with the developed design methodology, a 39MHz
crystal oscillator is designed and fabricated in a 1.1V 40nm
CMOS. Figure 8 shows the chip microphotograph and layout of
the crystal oscillator. The core area is 80m x 130m. The worst-

3.0

80m

2.0
1.5
1.0
0.5
0
0.1m

1m

10m

100m

1mm

10mm

Gate Width (W)670mFigure 6: Simulated dependence of VDDmin on W for threedifferent CMOS technologies.

Power consumption at VDDmin

130m

630m

VDDmin (V)2.5

Figure 8: Chip photograph and layout of crystal oscillator.

100W

W optimization

10W

0.35V
CMOS scaling

1W
0.1m

1m

10m

100m

1mm

10mm

Gate Width (W)Figure 7: Simulated dependence of power consumption at
VDDmin on W for three different CMOS technologies.

Figure 9: Measured output waveform of 39MHz crystal
oscillator at VDD= VDDmin = 0.35V.

336

Table I: Performance comparison with previous crystal
oscillators.

case RS of the quartz crystal shown in the spec sheet is 60. The
value of W for the crystal oscillator is optimized to 220m byconsidering the worst-case RS and the oscillator margin for
tolerances. This chip is implemented in a PCB with off-chipcomponents such as capacitors (C1=C2=5pF).

3.2 Measurements
The measured VDDmin of the 39MHz crystal oscillator is 0.35V.
Figure 9 shows the measured output waveform of the 39MHz
crystal oscillator at VDDmin = 0.35V. It shows a clear sinusoidal
waveform with full swing. Figure 10 shows the measured
spectrum of the 39MHz crystal oscillator at VDDmin = 0.35V.

Reference

[9]

[10]

[11]

[12]

This
Work

Frequency MHz

2.1

2.1

2.1

19

39

CMOS
process

m

3.0

NA

2.0

0.1

0.04

VDD

V

1.5

1.3

1.8

1.2

0.35

Power

W

1.4

3.0

0.7

21.6

4.1

the measured RS is 10 which is less than the worst-case RS of60 shown in the spec sheet. The smaller than expected RS
results in the wider measured VDD range than that obtained bysimulation.

In the measurement, oscillation was observed in the VDD range
from 0.35V to 1.1V. The measured VDD range is wider than thesimulated VDD range from 0.45V to 0.85V at W=220m. The
mismatch is due to the error in RS. In the S-parametermeasurement of the quartz crystal using a vector network analyzer,

Figure 11 shows the measured dependence of the power
consumption on VDD in the 39MHz crystal oscillator. The curve
exhibits an exponential dependence on VDD due to the subthreshold operation. The power consumption is 26W and 4.1W
at VDD values of 0.5V and 0.35V, respectively.
Table I shows a performance comparison with previously reported
crystal oscillators [9-12]. In this work, VDD is the lowest among
the previously reported crystal oscillators.

4. CONCLUSION
In this paper, the design methodology for sub-0.5V crystal
oscillators is shown to realize an all-sub-0.5V low power RFtransceiver for wireless sensor networks. To reduce VDDmin for the
crystal oscillator, both the optimization of the gate width (W) and
CMOS technology scaling are required. The optimum W isdetermined by gm and the parasitic capacitance of the transistors.
In accordance with the developed design methodology, a 39MHz
crystal oscillator is designed and fabricated in a 40nm CMOS.
The measured power consumption is 4.1W at 0.35V and 39MHz,
where both the power supply voltage is the lowest among thepreviously reported crystal oscillators.

Power consumption

Figure 10: Measured spectrum of 39MHz crystal oscillator.

5. ACKNOWLEDGMENTS

1mW

This work was carried out as a part of the Extremely Low Power(ELP) project supported by the Ministry of Economy, Trade andIndustry (METI) and the New Energy and Industrial Technology
Development Organization (NEDO).

100W

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26μW@0.5V

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VDD (V)
Figure 11: Measured dependence of power consumption on
VDD in 39MHz crystal oscillator.

337

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