2554

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 11, NOVEMBER 2012

An 80 mV Startup Dual-Mode Boost Converter by
Charge-Pumped Pulse Generator and Threshold
Voltage Tuned Oscillator With Hot Carrier Injection
Po-Hung Chen, Student Member, IEEE, Xin Zhang, Member, IEEE, Koichi Ishida, Member, IEEE,
Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Member, IEEE, and Takayasu Sakurai, Fellow, IEEE

Abstract—This paper presents an 80 mV startup-voltage
dual-mode boost converter for energy harvesting applications.
The charge-pumped pulse generator enables a startup operationof the boost converter from the input voltage of 80 mV. The
threshold voltage tuned oscillator for the clock generator of theboost converter compensates for the die-to-die process variation
by a hot carrier injection (HCI), thereby reducing the minimum
operation voltage (V) of the clock generator by 45% witha trimming time of 10 minutes. The proposed step-up converter
achieves the lowest startup voltage without using a mechanicalswitch or a large transformer.
Index Terms—Charge-pumped pulse generator, dual-mode
boost converter, energy harvesting, hot carrier injection, low-tuned oscillator.
voltage, startup,
Fig. 1. Power management unit for energy harvesting applications.

I. INTRODUCTIONR

ECENTLY, wireless sensors are widely employed in various applications including environmental monitoring,energy consumption monitoring, and implantable medical
sensors. There is a strong demand that those sensors could
be self powered where direct power supply is inefficient andbattery replacement is difficult. Various battery-free energy
harvesters have been developed for such self powered applications [1]–[3]. One of the most critical problems of these energy
harvesters is that the voltage provided by them is significantly
less than the voltage required by most of the modern integrated
circuits. Thus, it greatly limits the use of energy harvesters
with integrated circuits like wireless sensors in a self poweredsystem. For example, the thermoelectric generator can generate
the output voltage that is proportional to the difference of thetemperatures on both sides of it, in the range of 10 mV/K to
50 mV/K. For body-wearable applications, the output voltage
Manuscript received February 03, 2012; revised May 05, 2012; accepted June21, 2012. Date of publication September 11, 2012; date of current version October 26, 2012. This paper was approved by Guest Editors Shen-Iuan Liu andTsung-Hsien Lin. This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy, Trade and Industry(METI) and the New Energy and Industrial Technology Development Organization (NEDO).
P. Chen, X. Zhang, K. Ishida, and T. Sakurai are with the Institute of Industrial
Science, University of Tokyo, Tokyo 153-8505, Japan.
Y. Okuma and Y. Ryu are with the Semiconductor Technology Academic
Research Center (STARC), Yokohama 222-0033, Japan.
M. Takamiya is with the VLSI Design and Education Center, University ofTokyo, Tokyo 113-8654, Japan.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2012.2210953

is less than 100 mV for temperature difference of 2 K. The
single-cell solar cell generates 500–600 mV in the outdoor andbecomes as low as 100–200 mV in the dark office environment.
With such low output voltages of the energy harvesters, thestep-up DC-DC converter that can accommodate low input
voltage and boost the harvested energy to usable output voltage
is of great importance for a self powered system.
Fig. 1 illustrates the power management unit for energy
harvesting applications. It up-converts the harvested energy
and provides a higher voltage to wireless sensors or healthcare
devices. On-chip startup mechanism is applied for low-cost,compact applications because no additional off-chip devices
toare required. It provides high-voltage stimulus
the step-up DC-DC converter and kick-start the system from.
extremely low input voltage
In this paper, an 80 mV startup-voltage dual-mode boost converter is proposed [4] for energy harvesting applications. Dualmode operation means that the startup mode and the operation
mode are both realized by an inductive step-up DC-DC converter. A charge-pumped pulse generator (CPPG) provides alarge amplitude pulse signal to the power transistor and startup
in 4.8 ms. It achieves the maximum
the system from 80 mV
conversion efficiency of 72% at 0.5 mA output current with.A-tuned oscillator with HCI (DC-stress) com50 mV
pensates for the die-to-die process variation and the programtime can be 20 times shorter than the conventional AC-stressof the oscil[5], thereby reducing the test cost. The
lator is reduced from 128 mV to 80 mV in 3 minutes and can be

0018-9200/$31.00 © 2012 IEEE

CHEN et al.: AN 80 mV STARTUP DUAL-MODE BOOST CONVERTER BY CHARGE-PUMPED PULSE GENERATOR

as low as 70 mV after 10 minutes of programming. The proposed circuit demonstrates the feasibility of countermeasuresof a CMOS
for the process variation that limits thering oscillator.
This paper is organized as follows. Startup techniques in low
input voltage DC-DC converters are introduced in Section II.
Section III shows the system architecture of the proposed-tuneddual-mode boost converter. Section IV explains theoscillator with HCI. Section V describes the circuit implementation of the proposed charge-pumped pulse generator. The
experimental results and comparison with the state-of-the-art
are shown in Section VI. Finally, a conclusion is given in
Section VII.

2555

Fig. 2. Simulated leakage current of PMOS power transistor versus.
(a) Drain leakage. (b) Drain leakage current with PMOS super cut-off. (c) Gateleakage.

II. STARTUP TECHNIQUES IN DC-DC CONVERTERS
The key challenge of the power management unit for energy
harvesting applications is to develop a startup mechanism [6].
The startup mechanism is used to generate a high-voltage stimulus to kick start the step-up DC-DC converter (Fig. 1). Oncethe converter starts working, the control circuits in the converter
can be powered by the output
and the converter functions evenis lower than startup voltage.
Until now, several startup techniques were reported [7]–[11]for low voltage operation. A 650 mV external voltage and a
2 V battery are directly provided to the output of the power
management unit in [7] and [8], respectively. For battery-free
applications, however, no auxiliary voltage can be provided tothe system. A battery-less 35 mV startup boost converter in [9]uses a vibration activated mechanical switch instead of the auxiliary voltage. The mechanical switch requires a non-standard
process and the vibration requirement limits the applications. A
completely electronic startup step-up converters using a transformer with a large turn ratio was presented in [10], [11]. The
transformer is not well suitable for portable applications and it
also causes larger conduction loss.
To alleviate these problems, the completely electronic,
on-chip startup techniques without a mechanical switch or atransformer were presented in [12] and [5]. In [12], an on-chipcharge pump (CP) was designed as a startup mechanism andprovides a high voltage to the boost converter. The startup
voltage of the DC-DC converter is limited to 180 mV because
the load circuits of CP consume too much power. In [5], a95-mV startup voltage step-up DC-DC converter was realized
by the capacitor pass-on scheme with PMOS super cut-off
technique. An on-chip CP charges the output capacitor
during startup and its load circuits are minimized to reduce theoutput current of the CP. The available output current of the
CP depends on
and the output voltage decreases as
decreases. Even though it uses PMOS super cut-off techniqueto reduce the drain leakage of the power transistors, the startup
voltage is still limited to 95 mV.
Fig. 2 shows the simulated leakage current of PMOS powertransistor versus
under a temperature of 300 K for different configurations. The drain leakage is around 1 A at 0.5 V
and becomes as low as 0.2 nA by applying PMOS
super cut-off technique. The gate leakage current is approximately 10 times smaller than the drain leakage current withPMOS super cut-off. Therefore, charging the gate of power transistor during startup is a possible solution to reduce the output
current of the on-chip charge pump, which limits the startup
voltage of the boost converter.
In this paper, a dual-mode boost converter is proposed to further reduce the startup voltage. Fig. 3 shows the operation concept of the startup mechanism.
and
built
up the conventional boost converter while
is an additional
power transistor for startup. The startup circuit charges and discharges the gate of power transistor
with high amplitude( 0.5 V). The energy is stored in in charging phase and transferred toin discharging phase. Comparing with startingby the on-chip charge pump [5], the proposed inductive startup
mechanism provides larger current toduring startup because
turns on well. Therefore, the startup time can be significantly reduced. The proposed scheme eliminates the draincurrent problem in [5] and the startup voltage can be reduced to
80 mV.
III. SYSTEM ARCHITECTURE
The detailed block diagram of the proposed dual-mode boost
converter is shown in Fig. 4. The switch status in this figure
represents the initial state.
andare the control signals
for the switches. The proposed dual-mode boost converter consists of the conventional boost converter, a-tuned oscillator with HCI, a charge-pumped pulse generator (CPPG), twovoltage detectors[5], and a pulse generator for
operation. An additional power transistor
is designed forstartup. The-tuned oscillator with HCI generates the clock
signalsfor CPPG under 80 mV. CPPG provides
a high-amplitude high-duty clock signal to
and kicks start
the boost converter. The pulse generator for operation is used toprovide a pulse signal with fixed duty cycle to the power transistorsandduring operation. In our design, the target is toverify the on-chip startup mechanism in DC-DC converter. The
pulse-width modulation circuit is not included in this schemeand the output voltage is not regulated.
The size of the external components
is determined by the design specification. The target, the output ripple, and theswitching frequency
are 80 mV, 1.3 V, 1 mA, 0.1 V, and2556

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 11, NOVEMBER 2012

Fig. 5. Dual mode in the proposed boost converter (a) Startup mode (V) with low input voltage. (b) Operation mode (V) with highefficiency.

Fig. 3. Operation concept of proposed startup mechanism. (a) Charging of the. (b) Discharging of the gate of.
gate ofductor ripple and inductance offollowing equation:

can be calculated from the

(3)
(4)

Fig. 4. Proposed dual-mode boost converter. Startup is achieved by charging
by driving power transistor
with CPPG.

2 MHz, respectively. The estimated conversion efficiency
at
80 mV is 60%. Therefore,
is approximately
derived from the following equation:(1)
where the duty cycle (D) can be calculated from(2)
depends on the inductor ripple.
The inductance ofGenerally, the inductor ripple range is 20% to 40% of the maximum input current and we use 30% for calculation. The in-

Therefore, an off-chip inductor of 6.8 H and an off-chip capacitor of 10 nF are applied in this design.
The dual mode operation of the proposed boost converter isillustrated in Fig. 5. Fig. 5(a) shows the startup mode with low
startup voltage and Fig. 5(b) shows the operation mode withhigh conversion efficiency. These modes can be automaticallychanged by detecting the capacitor voltage
by. WhenV,provides “low” signal and the converter isoperating under startup mode. Otherwise,provides “high”
and the converter is in operation mode.
turns on the switchwhen
is higher than 0.6 V. The trigger voltage ofis slightly higher than that of
to make sure the load is connected toafter the boost converter starts working and theoutput can be boosted smoothly. An additional switch, however, reduces the conversion efficiency of the boost converter.
To reduce the conduction loss caused by, the transistor sizeofis designed to be twice of. If the load current increases andis smaller than 0.6 V,
will turn on and
off repeatedly.
The waveforms illustrating the circuit operation sequences
are illustrated in Fig. 6. During startup, the-tuned oscillator
with HCI provides the clock signal
to CPPG at 80 mV. CPPG is designed to convert an 80 mV input to a high-amplitude high-duty clock signal to drive the power transistor.
The amplitude ofis designed to be 0.5 V, which is higher
than the threshold voltageof the power transistors. Highduty-cycle is required to store the enough energy in the inductor

CHEN et al.: AN 80 mV STARTUP DUAL-MODE BOOST CONVERTER BY CHARGE-PUMPED PULSE GENERATOR

2557

Fig. 7. Simulation results ofof CMOS ring oscillator under different
process corners. SS means slow NMOS and slow PMOS, SF means slow NMOS
and fast PMOS, and so on.

Fig. 6. Waveforms illustrating the circuit operation sequences.

during startup. Whenis high,turns on and the inductor
current increases. Ifchanges from high to low,turns off
and the current stored in the inductor flows through the diodeconnected PMOS transistor. Therefore,
is charged by
the inductor current andincreases.
When
is charged to the preset trigger voltage of, thestate changes and the boost converter is operating under operation mode. During operation mode, the charge stored in
activates the pulse generator and the pulse generator drives thepower transistors
andwith high amplitude
toachieve high conversion efficiency. Whenis higher than thepreset trigger voltage of, the switch
turns on to power
the load circuits.
IV.

-TUNED OSCILLATOR WITH HOT CARRIE R INJECTION

The-tuned oscillator with HCI is used to generate theclock signals for CPPG. The startup mechanism fails if theoscillator does not function. Therefore, the minimum operation
voltageof the oscillator also limits the startup
voltage of the boost converter in standard CMOS process.
Theof an oscillator is usually limited byunbalance between NMOS and PMOS transistors. Fig. 7 shows
the simulation results ofof CMOS ring oscillator
under different process corners. SS means slow NMOS andslow PMOS. SF means slow NMOS and fast PMOS, and so on.
The simulation results show thatof lower than 80 mV
can be achieved if theof NMOS and PMOS transistors
are well balanced. If we can adjust theof transistors, forexample, by adjusting fast NMOS slow PMOS to slow NMOS
slow PMOS;
can be reduced from 173 mV to 73 mV.
unbalance in CMOS technology is usually caused bywithin-die and die-to-die process variations. The within-die
process variation issue can be easily solved by increasing thetransistor width in this design. The die-to-die process variation
is usually adjusted by controlling the body bias of the transistors. In the startup circuit, however, the body-biasing circuit

Fig. 8. Circuit schematic of conventionalin [5]. (a) Program mode. (b) Normal mode.

-tuned oscillator with AC stresswould not function before the system startup because only the
input voltage exists in the system. Therefore, the die-to-die
process variation limits thein our applications. One
possible way to compensate for the die-to-die process variationis trimming the transistors in post-fabrication process. In thisprocess, the ideal power supply is available to program thetransistors. A-tuned oscillator trimmed by AC stress isfirstly reported in [5], as shown in Fig. 8. In program mode,the oscillator functions under 1 V input voltage and AC current
draws through the transistor. PMOS transistor is trimmed
by applying high reverse body bias (8.5 V) andincreases. It requires 60 minutes for programming because
only AC current draws in program mode.
To reduce the program time, we proposed a-tuned oscillator with HCI (DC-stress), as shown in Fig. 9. The circuit
consists from an 11-stage inverter-based ring oscillator and inverter-based output buffers. The transistors
andareadded to provide DC current path for programming. To avoid

2558

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 11, NOVEMBER 2012

Fig. 10. Measured dependences of body current.

Fig. 9. Circuit schematic of proposed-tuned oscillator with HCI (DCstress). (a) Program mode. (b) Normal mode.

the within-die process variation, the transistor width of the inverter is designed to be 64 times larger than standard cell. In thefollowing, only the PMOS programming will be introduced foreasier understanding.
In program mode, a high reverse body bias is applied to
PMOS transistors (8.5 V) while the body of
NMOS transistors are connected to its source. The enable
signalof 1 V is applied toand the output
voltage (Out) is pulled-down to low ( 0.1 V). In this scheme,
the input (In) is the output of the previous stage and the input
voltage is also low ( 0.1 V). Therefore,is turned on anda large DC current flows through. During program mode,is much higher thanbecause the high reverse
body bias is applied to PMOS transistors and the input/output
voltages remain low even bothandturn on. A highreverse body bias ofenables the positive charges injected
into the gate dielectrics of transistors. The injected charges are
fixed in the dielectrics and increases
even the high reverse
body bias is removed. Note thatshift shows nonvolatile
characteristics and does not require any additional process
steps. Since the body of NMOS transistors are connected
to its source,
is not programmed. Comparing with AC
stress, DC stress increases the current flowing throughandreduces the program time significantly.
Whenis balanced with, the post-fabrication programming is stopped. The circuit is then operating under normal
mode and only an 80 mV input is provided without any reverse
body bias. The injected positive charges are still fixed in PMOS
transistors even the high reverse body bias is removed. Therefore,
is still balanced withandof the oscillator is reduced. In our design, the-tuned oscillator needs tooperate under 80-mV
and provide clock signals to CPPG.
Fig. 10 shows the measured dependences of body current
on the well voltage. From the measurement, the breakdown voltage of p-n junction is between 8.5 V
to 9 V. The program time is related to the bias condition of

on the well voltage

the PMOS transistor and a higher reverse body bias reduces
the program time. To reduce the program time, we manually
increase
until
reaches 1 mA. Therefore, an
8.5-V
is applied for this programming. The reverse
body bias is limited by the p-n junction breakdown voltage andthe supply voltage is limited by the gate breakdown voltage because of reliability consideration. In both AC and DC stress,andof the transistors are lower than the gate breakdown voltage andis 8.5 V.
The program time also depends on. A higher
increases the DC current and reduces the program time.
islimited by gate breakdown voltage and available DC current. A
large DC current occurs during programming because the transistor width of the output buffer is large. Therefore,
is selected to 1 V in our design. This bias condition is the same as
AC stress and is easier to compare the program time between
these two methods.
In this session, we focus on PMOS programming to compensate for the die-to-die process variation. If
is higher thanin fabricated chips, NMOS programming is also available.
needs to turn on to provide a DC path and a high reverse
body bias can be provided to
to increase.
V. CHARGE-PUMPED PULSE GENERATORThe CPPG is the key building block in the proposed dualmode boost converter. It converts a low
to a high-amplitude high-duty pulse signal
to activate the power transistor. The conventional approach uses a Dickson charge pump[13], a ring oscillator, and a duty cycle generator, as shown in
Fig. 11. The Dickson charge pump converts
to a higher
level ( 0.5 V). Fig. 12 shows the simulated output voltages of
the 30-stage Dickson charge pump under different output currents and input voltages. The capacitance of each flying capacitor in the charge pump is 1 pF.
is provided from an
on-chip 11-stage CMOS oscillator and the clock frequency depends on. The duty cycle of the clock signal is 50% and theclock frequency is 200 kHz when
80 mV. Even though
the clock amplitude provided to the circuit is much smaller than
, there still exists the current difference between
and. Therefore, the charge pump can still build up the highoutput voltage from
if the output current is small enough.
From the simulation, the output current of the charge pump islimited to 4 nA. To generate a high-amplitude pulse signal with

CHEN et al.: AN 80 mV STARTUP DUAL-MODE BOOST CONVERTER BY CHARGE-PUMPED PULSE GENERATOR

2559

Fig. 11. Block diagram of conventional approach to generate a high-amplitude
high-duty clock signal for boost converter.

Fig. 13. Block diagram of the proposed sub-1 nW charge-pumped pulse generator (CPPG).

Fig. 12. 30-stage Dickson charge pump. (a) Circuit schematic. (b) Simulated
dependence of output voltage on output current under different input voltage.

such a low output current, we proposed a charge-pumped pulse
generator (CPPG). Fig. 13 shows the block diagram of the proposed circuit. It consists from a Dickson charge pump, a 0.5-V
voltage detector[5], and some switches. The conceptof this scheme is to charge the node
without dynamic current and automatically pull
to 0 V by detecting. The
trigger voltage ofis designed to be 0.5 V to limit the pulse
amplitude.
Fig. 14 shows the simulated waveforms of the proposed
CPPG. Initially,is smaller than the trigger voltage ofandis low. The charge pump charges the nodeand . During the charging cycle, the load current of
the charge pump is limited andpumps up. Whenreaches the preset trigger voltage of(0.5 V),
providesa pulse signal and pulls the node
to low. The delay cell isadded to guarantee that theis discharged to low whilestill remains high and the charging time ofis reduced. Comparing with the conventional approach, the proposed charge
pumped pulse generator generates the pulse signal only when
the output voltage of the charge pump achieves 0.5 V. Therefore, the power consumption can be reduced. The proposed
CPPG provides a solution for generating a 0.5-V pulse signal
with sub-1-nW power consumption in CMOS process.

Fig. 14. Simulated waveform of the proposed charge-pumped pulse generator.

VI. EXPERIMENTAL RESULTS
The test chip was fabricated using 65-nm standard CMOS
technology. The microphotograph of the proposed dual-mode
boost converter is shown in Fig. 15. The active area including
the-tuned oscillator with HCI, CPPG, the pulse generator
and the boost converter is 0.25 mm . The circuit is measured
with an off-chip inductor of 6.8 H and an off-chip capacitorof 10 nF. The number of the off-chip components is same as
the typical boost converter without startup mechanism and no
additional off-chip devices are required.
Fig. 16 shows the measured dependence ofof the-tuned oscillator with HCI on program time. To verify
improvement, three test dies were measured. As canbe seen,of the oscillator is reduced to 80 mV in
3 minutes and becomes as low as 70 mV in 10 minutes. The
maximum
improvement is 45% in our measured
chips. Comparing with AC stress in [5], the test time can be2560

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 11, NOVEMBER 2012

Fig. 15. Chip micrograph of dual-mode boost converter in 65-nm CMOS.

Fig. 18. Measured startup waveforms of proposed dual-mode boost converter.

Fig. 16. Measured dependence ofin Fig. 10 on program time for 3 dies.

of-tuned oscillator with HCI

Fig. 19. Measured dependence of conversion efficiency on load current.

TABLE ICOMPARISON WITH PUBLISHED LOW-STARTUP VOLTAGE STEP-UP
DC-DC CONVERTERS

Fig. 17. Measured dependence offinished.

change on time after program is

reduced by 1/20. Therefore, the test cost can be significantly
reduced.
Fig. 17 shows the measured dependences ofvariation over the time after the program is finished. The circuit isoperating under normal mode and the high reverse body bias isremoved.
change is less than 3 mV after 100 hours ofoperating and gets stable.
Fig. 18 shows measured startup waveforms of the proposeddual-mode boost converter with CPPG under 80 mV. By
applying dual-mode scheme with CPPG,
rises dramaticallyand reduces the startup time to 4.8 ms. The output voltage
is obtained after the boost converter is in operation
mode. Fig. 19 shows the measured dependence of conversion
efficiency on different load current. The proposed circuitachieves the maximum efficiency of 72% and 60% at 50 mV

and 80 mV, respectively. The conversion efficiency at 50mV
is higher because the power consumed by the drivercircuits is smaller than that of 80 mV.
The performance comparison with the state-of-the-art step-up
DC-DC converter with startup mechanism is shown in Table I.
The proposed startup mechanism achieves 4.8 ms startup timeand is shortest to date. Among the on-chip startup mechanisms,
the lowest startup voltage of 80 mV is achieved. Although theCHEN et al.: AN 80 mV STARTUP DUAL-MODE BOOST CONVERTER BY CHARGE-PUMPED PULSE GENERATOR

startup voltage of 35 mV is already implemented in [9], it requires a mechanical switch activated by vibration and is not an
on-chip startup mechanism. The proposed-tuned oscillator
by HCI (DC-stress) compensates for the die-to-die process variation reduces the program time to 3 minutes, which is 1/20 of
the conventional AC-stress.

2561[12] P. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and
T. Sakurai, “0.18-V input charge pump with forward body biasing instartup circuit using 65 nm CMOS,” in Proc. IEEE Custom Integrated
Circuits Conf. (CICC), 2010, pp. 239–242.
[13] J. F. Dickson, “On-chip high-voltage generation in MNOS integrated
circuits using an improved voltage multiplier technique,” IEEE J.
Solid-State Circuits, vol. SC-11, pp. 374–378, Jun. 1976.

VII. CONCLUSION
A dual-mode boost converter with CPPG is developedin 65-nm CMOS for energy harvesting applications. CPPG
generates a high-amplitude (0.5 V) high-duty clock signal
with low power consumption (1 nW) to kick start the system.
Therefore, an 80 mV startup voltage is achieved and is thelowest in on-chip startup mechanisms. A startup by the boost
converter instead of a charge pump reduces the startup-time
to 4.8 ms and is the shortest to date. We also proposeda-tuned oscillator with HCI to compensate for the
die-to-die process variation. It achieves 45% of
reduction in the program time of 10 minutes. In addition, theprogram time can be 20 times shorter than the conventional
AC stress, thereby reducing the test cost.

REFERENCES[1] C. Alippi and C. Galperti, “An adaptive system for optimal solar energy
harvesting in wireless sensor network nodes,” IEEE Trans. Circuits
Syst. I, vol. 55, pp. 1742–1750, Jul. 2008.
[2] Y. K. Tan and S. K. Panda, “Energy harvesting from hybrid indoor
ambient light and thermal energy sources for enhanced performanceof wireless sensor nodes,” IEEE Trans. Ind. Electron., vol. 58, pp.
4424–4435, Sep. 2011.
[3] D. Niyato, E. Hossain, M. M. Rashid, and V. K. Bhargava, “Wirelesssensor networks with energy harvesting technologies: A game-theoretic approach to optimal energy management,” IEEE WirelessCommun., vol. 14, pp. 90–96, Aug. 2007.
[4] P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and
T. Sakurai, “A 80-mV input, fast startup dual-mode boost converterwith charge-pumped pulse generator for energy harvesting,” in Proc.
IEEE Asia Solid-State Circuit Conf., Nov. 2011, pp. 33–36.
[5] P. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y.
Ryu, M. Takamiya, and T. Sakurai, “A 95-mV startup step-up converter-tuned oscillator by fixed-charge programming and capacitor
withpass-on scheme,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech.
Papers, 2011, pp. 216–217.
[6] Y. M. Sun and X. B. Wu, “Subthreshold voltage startup module forstepup DC-DC converter,” Electron. Lett., vol. 46, pp. 373–374, Mar.
2010.
[7] E. Carlson, K. Stunz, and B. Otis, “20 mV input boost converter forthermoelectric energy harvesting,” IEEE J. Solid-State Circuits, vol.
45, pp. 741–750, Apr. 2010.
[8] I. Doms, P. Merken, R. Mertens, and C. Van Hoof, “Integrated capacitive power-management circuit for thermal harvesters with output
power 10 to 1000 W,” in IEEE Int. Solid-State Circuits Conf. Dig.
Tech. Papers, 2009, pp. 300–301.
[9] Y. K. Ramadass and A. P. Chandrakasan, “A battery-less thermoelectric energy harvesting interface circuit with 35 mV startup voltage,”
IEEE J. Solid-State Circuits, vol. 46, pp. 333–341, Jan. 2011.
[10] Linear Technology LTC3108 Datasheet. [Online]. Available:
http://cds.linear.com/docs/Datasheet/3108fa.pdf[11] J. Damascheke, “Design of a low-input-voltage converter for thermoelectric generator,” IEEE Trans. Ind. Appl., vol. 33, no. 5, pp.
1203–1207, Sep. 1997.

Po-Hung Chen (S’10) received the B.S. degree inelectrical engineering from National Sun Yat-sen
University, Kaohsiung, Taiwan, in 2005 and the M.S.
degree in electronics engineering from National
Chiao Tung University, Hsinchu, Taiwan, in 2007.
In 2012, he received the Ph.D. degree in electricalengineering from the University of Tokyo.
He is currently a project researcher at the Instituteof Industrial Science (IIS), the University of Tokyo,
Tokyo, Japan. His research interests focus on low
voltage CMOS DC/DC converters, fully integrated
DC/DC converters, and low-voltage low-power CMOS analog circuits.

Xin Zhang (S’06–M’08) received the B.S. degree
in electronics engineering from Xi’an Jiaotong University, Xi’an, China, in 2003, and the Ph.D. degreein microelectronics from Peking University, Beijing,
China, in 2008.
Since 2008, he has been a project researcher
with the Institute of Industrial Science (IIS), theUniversity of Tokyo, Tokyo, Japan. His researchinterests include low-voltage low-power analog
and mixed-signal circuits, variation aware circuits, power management integrated circuits, andrenewable energy harvesting.

Koichi Ishida (S’00–M’06) received the B.S. degree
in electronics engineering from the University ofElectro-Communications, Tokyo, Japan, in 1998,
and received the M.S. and Ph.D. degrees in electronics engineering from the University of Tokyo,
Tokyo, Japan, in 2002 and 2005, respectively.
He joined Nippon Avionics Co., Ltd. Yokohama,Japan in 1989, where he developed high-reliability
hybrid microcircuits for aerospace programs. Since
July 2007, he has been working at Institute of Industrial Science, the University of Tokyo as a research
associate. His research interests include low-voltage low-power CMOS analog
circuits, on-chip power supply circuits, and large-area flexible electronics.
Dr. Ishida is a member of IEEE and IEICE.

Yasuyuki Okuma received the B.S. and M.S.
degrees in electrical engineering from the Tokyo
University of Science, Japan, in 1997 and 1999,
respectively.
In 1999, he joined Central Research Laboratory,
Hitachi, Ltd., Japan, where he was engaged in the
research and development of low-power analog
circuit techniques for HDD driver and RF-IC. From2003 through 2006, he was a visiting researcher
at YRP Ubiquitous Networking Laboratory, doing
research in the field of low-power circuits andsystems for ubiquitous computing. Currently, he is a visiting researcher at
the Extremely Low Power LSI Laboratory, Institute of Industrial Science,
University of Tokyo, since 2009. He is interested in power supply circuits for
extremely low-power LSI circuits and systems.

2562

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 11, NOVEMBER 2012

Yoshikatsu Ryu graduated from Kobe City College
of Technology in 1992.
In 1992, he joined Sharp Corporation, Nara,
Japan. From 1992 to 2001 he was involved in
the development of semiconductor processing
technology, and from 2001 to 2009 he was engaged
in the circuit design of analog LSIs. Currently, he
is a visiting researcher at the Extremely Low Power
LSI Laboratory, Institute of Industrial Science,
University of Tokyo, since 2009. His current
interests are low-voltage low-power CMOS charge
pump circuits.

Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995, 1997,
and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high speed
digital LSIs. In 2005, he joined the University ofTokyo, Japan, where he is an Associate Professor at
the VLSI Design and Education Center. His researchinterests include the circuit design of low-power
RF circuits, ultra-low-voltage digital circuits, andlarge-area electronics with organic transistors.
Dr. Takamiya is a member of the technical program committee for the IEEE
Symposium on VLSI Circuits and the IEEE Custom Integrated Circuits Conference (CICC).

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Japan, in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has worked
extensively on interconnect delay and capacitancemodeling known as the Sakurai model and the alphapower-law MOS model. From 1988 through 1990,
he was a visiting researcher at the University ofCalifornia Berkeley, where he conducted researchin the field of VLSI CAD. Since 1996, he has been a Professor at the University of Tokyo, working on low-power high-speed VLSI, memory design,interconnects, ubiquitous electronics, organic ICs and large-area electronics.
He has published more than 600 technical publications, including 100 invited
presentations and several books, and has filed more than 200 patents.
Prof. Sakurai will be an executive committee chair for VLSI Symposia anda steering committee chair for IEEE A-SSCC from 2010. He served as a conference chair for the Symposium on VLSI Circuits, and ICICDT, a vice chair
for ASPDAC, a TPC chair for the A-SSCC, and VLSI Symposium, an executive committee member for ISLPED and a program committee member for
ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He is a recipient of the 2010 IEEE Donald O. Pederson
Award in Solid-State Circuits, 2010 and 2011 IEEE Paul Rappaport award, 2010
IEICE Electronics Society award, 2009 achievement award of IEICE, 2005
IEEE ICICDT award, 2004 IEEE Takuo Sugano award and 2005 P&I patentof the year award and four product awards. He gave the keynote speech atmore than 50 conferences including ISSCC, ESSCIRC and ISLPED. He was anelected AdCom member for the IEEE Solid-State Circuits Society and an IEEE
CAS and SSCS distinguished lecturer. He is a STARC Fellow, IEICE Fellow
and IEEE Fellow.