10-4
93% Power Reduction by Automatic Self Power Gating (ASPG) and Multistage
Inverter for Negative Resistance (MINR) in 0.7V, 9.2W, 39MHz Crystal Oscillator
Shunta Iguchi1, Akira Saito2, Yunfei Zheng1, Kazunori Watanabe2, Takayasu Sakurai1, and Makoto Takamiya1
University of Tokyo, Tokyo, Japan, 2Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan

1

Abstract
In order to reduce the power consumption of a crystal
oscillator (XO), an automatic self power gating (ASPG) and amultistage inverter for a negative resistance (MINR) areproposed. By combining ASPG and MINR, the measured
power of a 39-MHz XO in 40-nm CMOS decreases by 93%
from 139W to 9.2W, which is the lowest power in thepublished XO’s at 0.7V.
Introduction
Fig. 1 shows a target application of a proposed crystal
oscillator (XO). XO must be always powered ON not only inan active mode but also in a stand-by mode. The power
reduction of XO is important, because XO dominates thepower in the stand-by mode. In the active mode, a low phasenoise of XO is required for RF blocks, while the low phasenoise is not required in the stand-by mode, because the RFblocks are powered OFF. Therefore, in this paper, a new low
power mode of XO with an automatic self power gating(ASPG) is proposed. A multistage inverter for a negative
resistance (MINR) is also proposed to reduce the power.
Multistage Inverter for Negative Resistance (MINR)
Figs. 2 (a) and (b) show schematics of a conventional Pierce
XO and a proposed XO with MINR. Comparing Figs. 2 (a) and(b), a one-stage CMOS inverter for the negative resistancenecessary for the oscillation of XO is replaced with three-stage
CMOS inverters in Fig. 2 (b). In the conventional Pierce XO,
short-circuit current in a CMOS inverter is large, because theinput signal is a sinusoidal wave as shown in Fig. 2 (a), thereby
increasing the power consumption of XO. In order to reduce
the short-circuit current, MINR is proposed. Fig. 3 shows
simulated waveforms of XO with MINR. The waveforms at X2
and X3 are rectangular waves, thereby reducing theshort-circuit current of Inv2 and Inv3. The power consumptionof Inv1 is much lower than that in Fig. 2 (a), because the gate
width of Inv1 is one-tenth of that in Fig. 2 (a).
Automatic Self Power Gating (ASPG)
XO can keep the oscillation for a while without the negative
resistance, because the quartz crystal has a very high Q (>10000). In order to investigate the duration of the oscillation
without the negative resistance, Fig. 4 shows measured
waveforms of Gating and X1 shown in Fig. 2 (c). Gating iscontrolled from an off-chip pulse generator to switch SW1,SW2, and SW3. The damping time is 2.5ms, whichcorresponds to 100k cycles of 39-MHz clock. By use of thelong damping time of XO, ASPG is proposed to reduce thepower of XO. Fig. 2 (c) shows a schematic of a proposed XO
with MINR and ASPG. Comparing Figs. 2 (b) and (c), threeswitches (SW1, SW2, and SW3) and a switch controller areadded in Fig. 2 (c). In ASPG, the negative resistance isintermittently powered OFF to save the power. After XO ispowered OFF, the amplitude of X1 attenuates as shown in Fig.
4. When the amplitude is less than a preset level, the switch
controller turns on the three switches. Fig. 5 shows a schematicof the switch controller. In order to detect the amplitude, instead of a conventional continuous time comparator which
consumes a lot of power, two inverter chains with different
threshold voltages are used to save the power. The simulated
power consumption of the switch controller is 1.3W. Fig. 6
shows a timing chart of the switch controller. When theamplitude of Out is less than a preset level (VREF), XHVT goes tolow and Gating goes to high. As a result, XO is powered ON.

C142 978-4-86348-348-4

Thus, the amplitude of Out is kept higher than VREF.
Experimental Results
The proposed XO with MINR and ASPG is fabricated in
40-nm CMOS process. Fig. 7 shows a die photo and layout.
Table I shows a performance summary. Fig. 8 shows ameasured power supply voltage (VDD) dependence of thepower consumption. The conventional Pierce XO [1], XO withMINR, and XO with MINR and ASPG are compared. Theminimum power of XO with MINR and ASPG is 9.2W at VDD= 0.7V, because the negative resistance is maximum at 0.7V.
At VDD = 0.7V, MINR reduces the power by 50%. ASPG
reduces the power by 87%, because the power ON duty is 6.7%.
Thus, MINR and ASPG reduce the power by 92% from139W to 9.2W.
Fig. 9 shows measured waveforms of Gating and Out in XO
with MINR and ASPG at 0.7V. The amplitude of Out is kept to0.2V by ASPG. The waveform of Out looks similar between
power OFF and power ON. The startup times with and without
ASPG are compared. Figs. 10 (a) and (b) show measuredstartup waveforms of Gating and X1 in XO with and withoutASPG, respectively. ASPG reduce the startup time by 20%
from 259s to 208s. Fig. 11 shows a measured amplitudedependence of the power consumption and the startup time in
XO with MINR and ASPG at 0.7V. With decreasing theamplitude, the power consumption is decreased and the startup
time is increased. Therefore, the power consumption and thestartup time are the trade-off in ASPG. Fig. 12 shows ameasured VDD dependence of the frequency accuracy with andwithout ASPG. The frequency accuracy across VDD from 0.6V
to 0.9V is -4 to +4 ppm without ASPG and -29 to +7 ppm withASPG. The degradation of the frequency accuracy due toASPG is acceptable.
Fig. 13 shows measured phase noise of XO with and without
ASPG at 0.7V. By introducing ASPG, the phase noise at
1-MHz frequency offset degrades by 38dB. The phase noisewith ASPG at 1-MHz frequency offset is -112dBc/Hz. The
phase noise is not acceptable for RF circuits, while it isacceptable for logic circuits.
Table II shows a comparison with previously reported crystal
oscillators [1-4]. 9.2W in this work is the lowest power at
0.7V in the published XO’s. Though 4.1W is reported in [1],the startup time dramatically increases as VDD is reduced asmodeled in [2]. In order to reduce the power, an analog-based
amplitude control is shown in [4], which fails to work below
1V. Therefore, the digital-based amplitude control shown inthis paper is important to reduce the power of sub-1V XO’s.
Conclusions
A new low power mode of XO enabled by ASPG is proposedand demonstrated for the first time. ASPG reduce the power
and the startup time by 87% and 20%, respectively, at the costof 38-dB phase noise degradation.
Acknowledgment
This work was carried out as a part of Extremely Low
Power (ELP) project supported by METI and NEDO.
References[1] A. Saito et al., ISLPED, pp. 33-38, 2012.
[2] E. Vittoz et al., JSSC, pp. 774-783, 1988.
[3] D. Aebischer et al., ISSCC, pp. 999-1005, 1997.
[4] R. van Langevelde et al., RFIC, pp. 113-116, 2009.

2013 Symposium on VLSI Circuits Digest of Technical Papers

VDD
Active mode
RF SoCStand-by mode
RF SoC

Always-on
circuits

RFOut

Always-on
circuits

RFX1

X1

X4Crystaloscillator

SW1

OutX2
Inv1

Crystaloscillator

VDD

VDD

VDD

MINR

Switchcontroller

Gating

Inv3

Inv2
RFRF

X4 Out

X3

X2

C3
X1

SW2
RFPower ON
Power OFFC1

New low power modewith ASPG is proposed.

Quartzcrystal

C2

C1

C2

Quartzcrystal

X4

X3

C1

SW3
C2

Quartzcrystal(a)(b)(c)
Fig. 1. Target application of proposed crystal oscillator (XO).
Fig. 2. (a) Conventional Pierce XO. (b) Proposed XO with MINR. (c) Proposed XO with MINR and ASPG.

Voltage [V]

1.0
0.5
0.0
1.0
0.5
0.0
1.00.50.0
1.00.50.039MHzX1OFFOFFONTransitiondetector

High VTH

X2Gating

XHVT

X3

X1
X4=OUTFig. 5. Schematic of switch controller.

Startup time=259s02040

Time [ns]8060Fig. 4. Measured waveforms of Gating and X1 in Fig. 2 (c).

OFFOFF ON

GatingOFFON

OFFOFFOFFFig. 3. Simulated waveforms of XO with MINR.

Startup time = 259sX1OutVREF

w/o ASPG

650m

39MHzON
Gating

ON1150m

Outclk

1/8 divider
XLVTLow VTH

Damping time=2.5ms

VREF is detected(a)XHVTOFF
220m

XLVTGating

Data

Out

XO coreSwitches

Switchcontroller

OFFGating

Gating

ON240ns

GatingStartup time = 208s
X1Out (39MHz)

275m

ON

w/ ASPG

Fig. 7. Die photo and layout.
(b)
Fig. 6. Timing chart of switch controller.
Fig. 9. Measured waveforms of Gating Fig. 10. Measured startup waveforms of Gating
and Out in XO with MINR and ASPG. and X1. (a) Without ASPG. (b) With ASPG.

-50%

100-87%

-93%

9.2W

100.6

0.70.8VDD [V]

0.9

1.0Frequency accuracy [ppm]Fig. 8. Measured VDD dependence of power
consumption in three XO’s.
1040w/o ASPG

-10-200.7

0.8

VDD [V]0.9

1.0

Fig. 12. Measured VDD dependence of frequency
accuracy with and without ASPG.

25020015030

10020105000800

0400
200600
Amplitude of Out [mV]Table I Performance summary.
CMOS technology

MINR
40nm

MINR+ASPG
Frequency (f)

39MHz



Supply voltage (VDD)

0.7V

Power69W

9.2W

Startup time259s

208s

Phase noise at 1MHz offset -150dBc/Hz -112dBc/Hz
60,500m2Core areaf accuracy
at VDD=0.6-0.9V

-4 / +4ppm -29 / +7ppm

Fig. 11. Measured amplitude dependence of power
consumption and startup time.

w/ ASPG

0-30
0.6

VDD=0.7V, w/ ASPG

Startup time [s]Power consumption [W]

50

1000

Phase noise [dBc/Hz]

Power consumption [W]

Time-50-60-70-80-90-100-110-120-130-140-150
100

VDD=0.7V

Table II Comparison with published crystal oscillators.

w/ ASPG

Ref.

w/o ASPG
38dB

1k

10k

100k

1M

Frequency offset [Hz][4]

Thiswork

[2]

[3]

[1]

Frequency MHz2.1

2.1

1939





CMOSprocess

m

3.0

2.0

0.1

0.04



VDD

V

1.5

1.8

1.2

0.35

0.7



Power

W

1.4

0.7

21.6

4.1

139

9.2

10M

Fig. 13. Measured phase noise of XO with and without
ASPG at 0.7V.

2013 Symposium on VLSI Circuits Digest of Technical Papers

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