12-2
An On-Chip Noise Canceller with High Voltage Supply Lines
for Nanosecond-Range Power Supply NoiseYasumi Nakamura, *Makoto Takamiya, and Takayasu Sakurai
Center for Collaborative Research, *VLSI Design and Education Center, University of Tokyo, Japan
Abstract
An on-chip noise canceller with high voltage supply lines
for the nanosecond-range power supply noise is proposed.
The canceller fabricated with 90-nm CMOS achieves 68%
noise reduction with 2.0% power increase. Under the same
noise reduction conditions, the area penalty for the canceller
is 1/77 and 1/45 of those for the additional on-chip decoupling capacitors and the power supply lines respectively.
Introduction
Recent low power VLSI design techniques such as power
gating, clock gating, and dynamic voltage and frequency
scaling (DVFS) generate rapid and large change of the power
supply current at the moment of the wake-up from the sleep
mode to the active mode. The large power supply noise
generated by such current change is a serious problem for low
power digital VLSIs [1-2]. The noise is nanosecond-range
or its frequency is usually from 100 MHz to 500 MHz [3],and is determined by the resonance of the package parasitic
inductance and the on-chip decoupling capacitor. The noise
suppression by decreasing the package inductance and increasing the on-chip decoupling capacitance leads to the large
area penalty. Conventional clock dithering [1] and powerswitch control [2] to slow the current change increase thewake-up time and are not useful for the frequent wake-up andpower-down. To solve these problems, an on-chip noise
canceller with small area penalty and the fast wake-up is proposed.
Noise Canceller
Fig. 1 shows the schematic of the proposed circuit. Ahigh voltage supply (VDDH), a switch between VDDH and thenormal power supply (VDD), and a level-shifter are added tothe normal power supply circuit. When the logic circuit
wakes up, the switch between VDDH and VDD is turned on by
the level-shifter and the current from VDDH substitutes thecurrent flowing through the bonding wire and the onboard
supply lines of VDD. The principle of this circuit is shown inFig. 2. Point A is the start of the wake-up. And the wake-up
current reaches the maximum at the point B. The current fromVDDH decreases at C, and reaches zero at D. Without VDDH
supply, current via the VDD line increases rapidly from A to B,
which induces large di/dt noise on VDD line. In contrast,with VDDH supply, VDD current remains small from A to C,
and increases slowly from C to D, suppressing the noise.
Since the noise on VDDH does not influence VDD, the impedance of VDDH supply line can be large compared to the main
VDD line as long as VDDH can substitute the current for VDD.
Fig. 3 shows the schematic of the test chip. It consists ofa 2nF capacitor emulating a 530k-gate logic circuit, M2 tomake the supply current increase. M1 is used to monitor
VDD via a 50: GSG probe. M3 is used as a switch between
VDDH and VDD, which is driven by a 0-1.0V to 1.0-2.0V levelshifter.
Level shifter circuit is shown in Fig. 4.
Diode-connected PMOSs are inserted between the current mir-124

978-4-900784-04-8

ror part and the input pair part to handle 2.0V supply with
1.0V-tolerant transistors.
Experimental Measurements
Fig. 5 shows the micrograph of the chip fabricated with
1V 90nm CMOS process. The circuit capacitor occupies
1450Pm x 140Pm and proposed canceller occupies 4.4% of
the capacitor. Since this capacitor emulates a 530k-gate
logic circuit, the area penalty of this canceller is equivalent to0.6%. Fig. 6 shows the measurement setup. Transient response with proposed canceller is measured and shown in Fig.
7. Without the canceller, the worst voltage in transient is71mV less than the steady state IR drop, while the cancellersuppresses this noise to 32%. The noise canceller consumes
2.0% power overhead of the load current for 25k transitions/sec.
As shown in Fig. 2, the timing setup of thr point C and D
is important for the canceller operation, the effect of the slopeof CD and timing of C was measured and shown in Figs. 8and 9. In Fig. 8, quick turnoff of the PMOS switch makes
2nd droop, which becomes larger than the reduced 1st droop.
Responses for slower turnoff with 20ns, 40ns and 80ns transition time is also shown, where turnoff slopes slower than40ns do not make larger droop than the reduced droop. Fig.
9 shows the dependence between turnoff start time and the 2nddroop. It is shown that 2nd droops are not affected by theturnoff start time when turnoff slope is not steep. Fig. 10shows the relation between the turnoff start time and the noisefor turnoff slope of 0ns, 20ns, 40ns, and 80ns, where 100%means the noise without canceller. It is shown that with steep
turnoff, the noise cancelling is not effective due to the 2nddroop.
From the results, point C was set to 40ns after the wakeup
and the time between point C and D was set to 80ns.
Discussions
The area penalty of the proposed noise canceller wascompared to conventional approaches, addition of the decoupling capacitors and additional pads for VDD. Fig. 11
shows the simulated transient responses of conventional approach. Simulated and measured waveform without noise
canceller are also shown in the Fig. 11. To obtain the same
noise cancelling effect, compared to the area and pad overhead of the proposed circuit, 45 times more pads or additional
decoupling capacitor with 77 times larger area is required.
Power consumption depends on the number of transitions
per second as shown in Fig. 12. For applications whose
sleep/wake-up frequency is below 10s of kHz, the power
overhead is less than 1.0%.
Conclusions
A noise canceller using higher voltage supply lines isfabricated and verified. The canceller reduced the power
supply noise to 32% with an additional power of 2.0%. With
conventional approaches, it is not feasible to achieve the reduction rate since very large area or pin overhead is required.

2007 Symposium on VLSI Circuits Digest of Technical Papers

IVDD

VDD
(1.0V)

References[1] C. Lichtenau et al., "Powertune: advanced frequency and power
scaling on 64b powerPC microprocessor," ISSCC Dig. of Tech.
Papers, pp. 356-357, 2004.
[2] Y. Kanno et al., "Hierarchical power distribution with 20 power
domains in 90-nm low power multi-CPU processor," ISSCC Dig.
of Tech. Papers, pp. 540-541, 2006.
[3] T. Rahal-Arabi et al., "Design & validation of the Pentium III
and Pentium 4 processors power delivery," Dig. of Symp. on
VLSI Circuits, pp. 220-223, June 2002Proposed

IVDDH

VDDH
(2.0V)

Level Shifter

Acknowledgement
This work is supported by Intel Corporation. The VLSI
chips were fabricated through the chip fabrication program of
VDEC with the collaboration by STARC.

CircuitCdecoupling

WakeupVSS(0.0V)
Off-chipOn-chip

Fig. 1: Configuration of the proposed circuit

Wake-upCap.

Withcanceller

VDD

1 pad

VDDH
(2.0V)

Cancelled

M3

5 padsBias

VDD(1.0V)VSS

B
Slower

IVDD
IVDDH

A

VSS
(0.0V)

IVDDH

C

M1
Wake-upD
IVDD

Noise source

6 padsTime

Ccircuit
2nF

M2

VDDHLevel Shifter

VDDH

Control

VDD

600Pm

Fig. 4: Schematic of the level
shifterFig. 3: Schematic of the test chip

1.00

Steady statevoltage

w/ canceller

0.90

0.90

2004060
Time[ns]80

2040100

OFF60
Time[ns]

AB

DC

B

AON

80

100

C

D

Fig. 8: Measured noise dependence withturnoff slope

Fig. 7: Measured effect of proposed noise canceller

1.05

w/o canceller

0.80

w/o canceller0

1st droop

0.85

100%

68%

0.85

Fig. 6: The photograph ofthe test setup

0.95

IR drop

0.95

2nd droop
affected by turnoff slope

VDD-VSS [V]VDD-VSS [V]

1.00

0.80

Fig. 5: Micrograph ofthe test chip

1.05

1.05

GSG probe

Cap.

REF

VBIAS

Oscilloscope

On-chip

Fig. 2: Principal of cancelling noise

VDD

50:Monitor

M3
ShifterNoisesourceOUT

0.90

1st droopAC D

w/o canceller
020

40

60
Time[ns]

ON80

OFF20ns

40%20%100

A

60%0%

B C D

Fig. 9: Measured noise dependence withturnoff start time

010
20
30
40
Turnoff time after wakeup [ns]45x padNormalized noise

0.95

w/ canceller(Measured)

0.90
77x area C

0.850204060
Time[ns]

0.6
0.4

0.32

0.2

Measured
w/o canceller
Simulated

0.80

0.8

80

0100

MPUs

Measuredted100

1k

10k

100k

1M

10M

Fig. 12: Measured noise dependence withturnoff start time
9080

0.90

Noc(M anea ce
su llinof Pa
sa d & red g)m ce aov pa
er cithe oad r(M Proea posu sere dd)

1.00

11050

1.2
11

lalcu
CaTransitions / sec

Fig. 10: Measured noise dependence withturnoff start time and slope

1.05VDD-VSS [V]80ns
2nd droop < 1st droop

40ns

Normalized area
or pad overhead

0.800ns(quick)

7060
504077453020
1001Dec
ca ou
pa plici ngtor
Additionpa ald(M Proea posu sere dd)

0.85

B

80%

100
10
1
0.1
0.01
0.001
0.00010.00001

Cellphones

0.95

100%
Noise

VDD-VSS [V]2nd droop
not so affected

Power overhead [%]

120%

1.00

(a)
(b)
(c)
Fig. 11: Simulated noise waveform and comparison with conventional approaches

2007 Symposium on VLSI Circuits Digest of Technical Papers

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