294IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO. 5, MAY 2011

Post-Silicon Clock Deskew Employing Hot-CarrierInjection Trimming With On-Chip Skew Monitoringand Auto-Stressing Scheme for Sub/NearThreshold Digital Circuits
Yu Pu, Member, IEEE, Xin Zhang, Member, IEEE, Katsuyuki Ikeuchi, Student Member, IEEE,Atsushi Muramatsu, Atsushi Kawasumi, Member, IEEE, Makoto Takamiya, Member, IEEE,Masahiro Nomura, Member, IEEE, Hirofumi Shinohara, and Takayasu Sakurai, Fellow, IEEE

Abstract—Clock skew is a major cause of severe timing yielddegradation for sub-/near-threshold digital circuits. We report for
the first time on employing hot-carrier injection (HCI) for postsilicon clock-deskew trimming. An HCI trimmed clock buffer,
which can be individually selected and stressed to adjust theclock edge, is proposed. In addition, it can be used in conjunction
with on-chip skew monitoring circuits to achieve auto-stressing.
Our approach is proven to be effective through a representative
1.1-mm × 0.8-mm clock tree in a 40-nm high-k complimentary
metal–oxide–semiconductor process. On average, it reduces theclock skew by eight times at 0.4 V Vdd . No significant recovery
is noticed two weeks after trimming.
Index Terms—Clock skew, hot-carrier injection (HCI), postsilicon tuning, sub-/near-threshold.

I. I NTRODUCTIONW

HILE ultra-low-Vdd digital circuits are becoming increasingly popular, they suffer from severe timing yielddegradation. A major cause of such a problem is clock skew. Although advanced electronic design automation (EDA) tools cansynthesize clock trees with balanced RLC networks, achievingskew-matched clock trees in the presence of process variations
is still difficult. To alleviate skew, prior art exploits clock bufferswith post-silicon programmable size. As an example, the Intel’s
Itanium-family processors insert clock vernier devices (CVDs)
at local clock buffers [1], as shown in Fig. 1(a). After comparing
clock phases, the CVDs can add delay to any fast clock,hence accommodating the latest clock. However, gate sizing
becomes neither effective nor efficient at an ultra-low-Vdd ,where the transistor’s driving strength is influenced exponentially by its threshold voltage Vth variation. When migrating

Manuscript received October 18, 2010; revised January 17, 2011; acceptedFebruary 26, 2011. Date of publication May 23, 2011; date of current version
June 8, 2011. This work was supported by the New Energy and Industrial
Technology Development Organization (NEDO), Japan, under the Extremely
Low Power (ELP) Project. This paper was recommended by Associate Editor
K. Chakrabarty.
Y. Pu, X. Zhang, K. Ikeuchi, M. Takamiya, and T. Sakurai are with theUniversity of Tokyo, Tokyo 153-8505, Japan (e-mail: ypu@iis.u-tokyo.ac.jp).
A. Muramatsu, A. Kawasumi, M. Nomura, and H. Shinohara are with theSemiconductor Technology Academic Research Center, Yokohama 222-0033,
Japan.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2011.2149050

Fig. 1. (a) Clock buffer with CVDs [1]. (b) Required number of CVDs in aclock buffer quickly increases as Vdd scales.

Intel’s approach to the ultra-low-Vdd regime, we see the following problems: 1) According to the simulated results, 3 σ/μof clock skew becomes tens of times worse compared with
the nominal Vdd . Such a wide spread implies an impracticallylarge number of CVDs embedded in a clock buffer, as shown in
Fig. 1(b). 2) The CVDs require firmware (e.g., electrical fuse) toedit programming bits, which also exacerbates area overhead.
Ideally, we want to find a low-cost post-silicon tuning methodthat can adjust the Vth of the fabricated transistors in each clock
buffer individually. Although body biasing can tune Vth , applying it to individual buffers is impossible due to an incrediblylarge overhead. In this brief, hot-carrier injection (HCI) deskew
trimming is proposed. To the best of our knowledge, we are
the first to apply HCI trimming to logics, whereas previous
work [2] had applied it to static random-access memory cells.
The remainder of this brief is organized as follows: Section II
introduces the concept of the proposed HCI trimmed clock
buffer (HTCB). Section III presents the experimental clock tree
diagram and circuit implementation. Section IV presents the1549-7747/$26.00 © 2011 IEEEPU et al.: POST-SILICON CLOCK DESKEW EMPLOYING HCI TRIMMING WITH ON-CHIP SKEW MONITORING295Fig. 4. Proposed HTCB.

Fig. 2.

HCI mechanism on nMOS transistor.

Fig. 5. Increased delay of CKLOCAL after HCI trimming.

the Vth of M1 is increased, consequently the HTCB delay
is also increased, which is especially prominent at the sub-/near-threshold region. Therefore, by controlling the switch, any
fast local clock CKLOCAL can be delayed to match the latest
reference clock CKREF , as illustrated in Fig. 5.
Fig. 3. Vth shift on nMOS transistor.

deskew trimming procedures. Measurement results in a 40-nm
high-k CMOS process are shown in Section V. Finally,
Section VI draws the conclusions of this brief.
II. C ONCEPT OF HTCBThe HCI mechanism is illustrated in Fig. 2. Typically, theHCI effect is much stronger on nMOS devices than on pMOSdevices. The necessary and sufficient conditions of HCI stressing are the following: 1) A large current flows through the channel. Some electrons are energized by the horizontal channel
electric field so they may become hot-carriers and are injected
into the gate oxide. 2) A high Vds exists, so the channel carriers
are accelerated by a high electric field of the drain. Ionization
collision and avalanche multiplication can occur and cause
electron–hole pairs. Some of these pairs are also injected into
the gate oxide. The net result of HCI stressing is an increase in
Vth . This Vth increase can be memorized because a significant
amount of carriers can be trapped for the device’s entire lifetime[3], as shown in Fig. 3.
The proposed HTCB is shown in Fig. 4. In the HTCB,
only the nMOS transistor M1 in the first inverter needs tobe stressed because the timing elements in our circuits are
triggered by positive clock edges and don’t care clock dutychanges. The second inverter can reshape the delayed clock
signal to improve its slew rate. During stressing, the switch ison, and a high Vdd is applied. Meanwhile, an AC signal (with0-Vdd amplitude) or a DC signal (at Vdd level) is applied tothe gate terminal. In this brief, we choose an AC signal as it
can be more effective compared with a DC signal [4]. After
stressing, Vdd goes back to normal, and the switch is off. Since

III. E XPERIMENTAL C LOCK T REE D IAGRAM
AND C IRCUIT I MPLEMENTATION
A grid-based H-type clock tree with balanced loadings is
implemented, as shown in Fig. 6. Conventional clock deskew
requires iterative pair-by-pair comparison and individual clockedge adjustment. After which, all the clocks can be synchronized with the latest clock. To reduce deskew effort andtime, we create the latest clock CKREF artificially. Thisis accomplished by using delay elements to generate theCKREF s, which are predetermined to be slightly later than any
CKLOCAL in the worst device mismatch case during designtime. When deskew, the phase information of a CKREF is
forwarded in its region, and the HTCBs are stressed to locktheir CKLOCAL s with the CKREF .
Please be aware that, although the deskew trimming scheme
is only applied to each region in our experimental clock tree,
just to prove the effectiveness of our concept, the proposed
scheme can be easily extended to other clock tree levels.
Inter-region clock deskew is also possible by using a hierarchical trimming method, that is, first deskew the CKREF sacross regions and then deskew CKLOCAL s according to theirCKREF s inside each region. This strategy helps reduce (semi-)
global metal wire utilization and save power consumption inoperational mode.
The key circuit components in our scheme include phasecomparators for skew monitoring, HTCBs, and a scan-chain.
They are shown in Fig. 7. Many kinds of phase comparatorsfor skew monitoring exist, such as the fully customized phasecomparator for ultra-high-speed clocks described in [1]. Toease the design, the adopted phase comparator consists ofonly standard cells and thus is synthesizable in EDA flow.

296IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO. 5, MAY 2011

Fig. 6. Diagram of the experimental H-type clock tree, with region-based, on-chip skew monitoring, and auto-stressing scheme. The scheme can be extended toother clock tree levels and inter-region deskew.

The CONFIG bits in the phase comparators are connected by
the scan-chain. During initialization, all the CONFIG bits areinitialized to “1” by scan operation. During evaluation, thecross-sampling D-flip-flops I1 and I2 compare the phases ofCKLOCAL and CKREF and reset the CONFIG bit to “0” if
any phase difference is detected. Note that the setup times of
I1 and I2 provide a guardband to avoid meta-stability, so theresolution of added delay to CKLOCAL should be confinedto this guardband. Once pulled down, the CONFIG bit cannot
restore back to “1” until the next initialization. The low-active
CONFIG bit indicates whether the connected HTCB should
be stressed. During stressing, the global signal STRESS isasserted to “0.” Vdd is raised to be significantly higher than
the nominal Vdd level. A “0” CONFIG bit remains at groundlevel, and a “1” CONFIG bit follows the Vdd level accordingly,thanks to the latch (essentially two cross-coupled inverters)in I3 . Therefore, a level-shifter is not needed. An AC signal
with 0-Vdd amplitude is applied to ROOT CLK and SEMIGLOBAL CLK. If CONFIG is “0,” then M1 and M2 in theHTCB are turned on simultaneously, so a large current goes into
the nMOS transistor M4 , and the HCI stressing conditions arefulfilled.
It is worth mentioning that the phase comparators, HTCBs,
and other logic gates share the same power grids in order tominimize the area overhead. Comparing our circuits with theprevious works, the overhead of phase comparators remains thesame. However, the clock buffer size is greatly reduced. A huge
number of programming bits are also avoided.

IV. P ROPOSED T RIMMING P ROCEDURES
Fig. 8 proposes the automated trimming procedures. Our
programming method takes “trial and error”-based iterations,so a maximum iteration number Nmax is set beforehand toavoid an exceedingly long trimming time. In addition, we areaware of a large current during stressing (refer to Fig. 10 in
Section V). The stressing current per HTCB exceeds 1 mA. For
large size circuits with hundreds or even more HTCBs, the total
stressing current may exceed the maximum current toleratedby power grids. To solve this issue, Steps III–V scan out theCONFIG bits of phase comparators, mask part of “0” (stressingenable) bits to “1” (stressing disable) bits, and scan in themagain, hence allowing stressing a chip sequentially. All the scan
operations, i.e., Steps I, III and V, are operated with the nominal
Vdd (e.g., 1.1 V) to guarantee correct scan functioning. Step II
is performed at the ultra-low-Vdd (e.g., 0.4 V) in operationalmode to capture correct skew information.
As indicated in Fig. 8, our method also contains a manualtrimming mode for selective stressing, which can be used in design rectification, such as hold-time debugging. In such mode,
Steps V and VI are used standalone to scan-in predetermined
bits, hence selecting targeted HTCBs for stressing.
V. M EASUREMENT R ESULTS
The clock tree regions 0, 1, and 2 in Fig. 6 are fabricatedin a 40-nm high-k CMOS process. The tree is distributed on a
1.1-mm × 0.8-mm die. Fig. 9 shows the die photo.

PU et al.: POST-SILICON CLOCK DESKEW EMPLOYING HCI TRIMMING WITH ON-CHIP SKEW MONITORING

Fig. 7.

Phase comparator for on-chip skew monitoring, HTCB implementation, and scan-chain.

Fig. 8.

Automated trimming procedures. Steps V and VI can also be used standalone for manual and selective stressing.

The appropriate stressing Vdd depends on individual process
technology. We use a 2.5-V Vdd , whereas our device cantolerate over 3.0-V Vdd according to measurement. A shorter
stressing period per iteration can provide a higher resolution ofadded delay and prevent over-stressing HTCBs. We choose 5 sas the stressing period per iteration. Raising the temperature canaccelerate the HCI, but stressing at a very high temperature fora long time (e.g., 103 s at 100 ◦ C) is not suggested. Otherwise,bias temperature instability (BTI) [5] may occur and degrade
other logic gates that share the same power grids since we do
not distribute separate power grids for the HTCBs. The maindifference between HCI and BTI is that HCI needs large current
injection, whereas BTI does not need current. Typically, the297

HCI effect happens much faster and more intensive than theBTI effect. However, BTI can become an important concernwhen 1) a high bias voltage is imposed on a transistor for a longtime, e.g., many hours/days, and 2) a high temperature exists.
To mitigate BTI on other gates, short-time AC stressing at
25 ◦ C room temperature is applied to HTCBs in the experiment.
Fig. 10 shows the measured stressing current per HTCB at
different stressing Vdd s.
The deskew results of 10 chips for 0.4-V operational Vdd areprovided in Fig. 11. On average, HCI trimming consumes 135 sof stressing time per die [Fig. 11(a)] and renders an over eighttimes skew reduction [Fig. 11(b)]. Note that we use a high-kprocess. For processes without high-k dielectric, the stressing

298IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO. 5, MAY 2011

Fig. 9. Die micrograph of the experimental clock tree in a 40-nm high-kCMOS.

Fig. 12. Measured clock waveforms at 0.5-V Vdd . (a) Before trimming.
(b) After trimming. (c) By superimposing CKREF of (a) on (b), the rise timeof CKREF is almost unaffected. (d) Delayed CKLOCAL .

Fig. 10. Stressing current at different stressing Vdd s.

and the shape of CKREF are almost unaffected (degradationis only less than 1%), as shown in Fig. 12(c). Since ultralow-Vdd s typically apply to medium-/low-speed applications,this slight degradation can easily be covered by design margin.
Meanwhile, CKLOCAL is delayed, as shown in Fig. 12(d).
Therefore, the effectiveness of selective stressing at HTCBs isconfirmed.
VI. C ONCLUSIONFig. 11. (a) Stressing time of 10 chips. (b) Normalized skew at 0.4-V Vdd
before and after HCI trimming.

time is expected to be significantly shorter. A very importantconcern is the retention property of the injected charge. In
Fig. 11(b), two weeks after trimming, no significant recovery
has been observed. By extrapolating the line in Fig. 11(b), theinjected carriers could be trapped for many years, which islong enough to cover the lifetime of many consumer electronicdevices.
Fig. 12(a) and (b) show the measured clock rise edges andskews at 0.5-V Vdd before and after trimming. Because theclock signals drive heavy probe pads, the absolute values of
the rise time and skews are magnified. To examine whether
other logic gates that share the same power grids are affected byimposing a high stressing Vdd in Fig. 12(c) and (d), Fig. 12(a) is
superimposed on Fig. 12(b). After HCI trimming, the rise time

We have reported for the first time on employing HCI for
post-silicon clock-deskew trimming. An HTCB, which can beindividually selected and stressed to adjust the clock edge, isproposed. In addition, it can be used in conjunction with onchip skew monitoring circuits to achieve auto-stressing. Ourapproach is proven to be effective through a representative
clock tree in a 40-nm high-k CMOS process.
The future CMOS technologies that scale into very deep submicrometer regions increase the electric fields in MOSFETs.
The chance for hot-carriers to get enough energy and be injected into gate oxide gets higher, yielding a more significant
HCI effect. Currently, we are exploring the optimum stressing conditions to reduce the trimming time while maintaining
device reliability. The reversibility of HCI mechanism is also
worth further investigation. Looking to the future, this trimming
method can possibly be incorporated in a wafer burn-in test.
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