IEEE ICICDT 2019, Suzhou, China

Session 5 - Digital IC

A 500-Mbps Digital Isolator Circuits using Counter-Pulse Immune
Receiver Scheme for Power Electronics
Tsukasa Kagaya, Koutaro Miyazaki, Makoto Takamiya, and Takayasu Sakurai
Institute of Industrial Science
The University of Tokyo
Tokyo, Japan{kagaya, koutaro, mtaka, tsakurai}@iis.u-tokyo.ac.jp
Abstract—A 500-Mbps digital isolator with the isolation
voltage more than 1kV is described, which is the fastest highvoltage isolator ever reported. The high-speed feature isachieved by a newly proposed Counter-Pulse Immune Receiver(CPIR) scheme based on a cross-coupled Schmitt-trigger
circuit. The isolator is manufactured in a widely-used highvoltage 0.18-µm CMOS technology and thus can be integrated
with smart digital driver circuits for power electronics.

DigitalIsolator

Resistor

PowerDevice

1bit

inductiveINTRODUCTION

Recently in power electronics, a digital gate driver has
been proposed to improve switching characteristics of powerdevices [1]. By driving the gate of the power device with an
optimized waveform, the digital gate driver is shown toreduce voltage/current overshoot noise while keeping thepower loss at the same level, compared with theconventional resistor driver. Although the digital gate driver
improves the system performance, more digital bits are to beprovided in the same amount of time than the conventional
resistor driver as shown in Fig.1. For example, in theimplementation in [1], 6-bit of digital data is to be provided
in every 25-ns period, and the digital data should go acrossthe high-voltage isolator at the rate of 240-Mbps. The higher
speed is needed for the higher resolution (ex. 8-bit) or for thefaster power devices (ex. SiC devices). Such high bandwidth of data may be transferred through multiple of digitalisolators in parallel but then the cost and module volumeincrease. Consequently, higher-speed digital isolators arelooked for in the next-generation power electronics.
In order to meet the requirement, this paper describes a500-Mbps digital isolator based on an inductive coupling
using two-chips configuration. A transmitter, TX, isimplemented on one chip and the receiver, RX, is on theother chip. Both chips are made with a 0.18-µm BCD highvoltage process with >0.5-µm channel length, which isinherently much slower than the standard low-voltage shortchannel CMOS and thus it is much more difficult to achieve
high speed. In order to achieve high speed, a new circuit
scheme is employed, namely, Counter-Pulse Immune
Receiver (CPIR) scheme, where a pair of Schmitt trigger
circuits are properly coupled to eliminate a counter-pulse
problem. To ensure the isolation voltage higher than 1kV, acareful design of coils is carried out considering technologycircuit interaction, which is discussed in section III.

6IN

1IN

B2T(b) Digital gate driver
63

B2T

electronics,

BufferIN

Serial-parallel
converterI.

powerINDigitalIsolator

Keywords-digital isolator,
coupling, high-speed(a) Conventional resistor driver

63

D Q

63

CK6CK

D Q

63

PowerDevice

6bit

25nsFig. 1. Two different driving schemes for power devices

II.

PREVIOUS ISOLATOR CIRCUITSThe fastest digital isolator for power electronics
previously reported is described in [2]. The isolator uses aninductive coupling principle and an edge-detection scheme
as opposed to a carrier-base on-off keying scheme. Thus, weadopt the inductive coupling and the edge detection concept,
but the signaling protocol and the associated circuits arecompletely different to realize the higher speed. The
conventional signaling protocol [2] is shown in Fig.2. Eachedge in input data, IN, is translated to a unique current wave
in TX-coil (ITX). Then, a signal pulse and a counter pulse
appear on the RX-coil (VRX) corresponding to the unique ITX
wave as shown in Fig.2. The TX needs to blunt the fallingedge of ITX so that the counter pulse at RX should nottranslated as a signal. This requirement of blunting the ITX
falling edge slows down the signaling process and hence
decreases the speed. On the other hand, the newly proposed
scheme excludes this requirement for blunting by
introducing novel RX circuits as described in Section III andthus achieves the higher speed.

70Paper 5.4

TX
circuitIN

IEEE ICICDT 2019, Suzhou, China

ITX

TX-coilVRX

RX
circuit250Φ TX-coil(thick M5)

Bonding wire(~1.5mm)

OUT

250Φ RX-coil(M1)

RX-coil
GNDRX

GNDTX

TX

ITX : Current in TX-coil
VRX : Voltage on RX-coilRX

TX ChipINRX Chip

Over pass (M2)
Under pass (M4)~5nsFig. 3. Overall implementation of proposed digital isolator

ITX
Counter pulse byblunted edge of ITX

TX Chip RX Chip

VTH,HVRX
VTH,LIN

OUT

Fig. 2. Conventional signaling protocol for high-speed data transmission

A similar transceiver based on an inductive coupling has
been reported for an inter-chip signaling among 3D stackedchips, which achieves very high-speed data transmission [3].
Although the concept of the data transmission using aninductive coupling is the same, the inter-chip signaling
circuit doesn’t need to integrate with a 15-V gate driver. Thatis, there is no need to use very long-channel BCD devices,which is orders of magnitude slower than the cutting-edge
short-channel device. Moreover, there is no need to consider
high-voltage isolation nor Common Mode Transition
Immunity (CMTI). Thus, there is no meaning to compare thehigh-voltage digital isolator circuits with the inductive
signaling circuits for inter-chip communication among 3D
stacked chips.
III.

ITX

TX circuit

SETRESETITXVRX

VRX

RX circuit

Signal pulse bysharp edge of ITXOUTGNDRXGNDTX
IN~2nsITX
Signal pulse by
sharp edge of ITX

Counter pulse by
sharp edge of ITX VTH,H

VRX

HL-wavesets OUT

COUNTER-PULSE IMMUNE RECEIVER SCHEME

VTH,L
LH-wave
resets OUT

OUT

A. Overall architecture
The overall architecture of the proposed digital isolator isshown in Fig.4. The isolator consists of two Si chips
ensuring the high-voltage isolation. Since the TX must use
low-resistance coil to increase current, ITX, for higher speed,
the top thick metal (metal layer 5: M5) is employed for theTX-coil. Then, the RX-coil must use the bottom metal (M1)to ensure the high-voltage isolation. Now that the RX-coil ismade with M1, the RX-coil must not be close to the TX chipsurface. Otherwise the high breakdown voltage cannot beachieved. As to the diameter of the coils, 250-µm isemployed. In order to increase the speed, the bigger coil ispreferable because it maximizes the received signal strength
but if more than 250-µm diameter is used, the dummy metal
should be laid out in the coil which negatively impact thesignal strength.
The counter pulse problem is taken care at the RX side,
being different from the previous scheme in Fig.2 where theproblem is taken care at the TX side. The proposed signaling
protocol is depicted in Fig.4. The detailed discussions are inChapter B and C.

Fig. 4. Proposed signaling protocol for high-speed data transmission

B. Transmitter
The circuit diagram of the TX is shown in Fig.5. Being
different from the previous scheme, there is no need tosuppress the counter pulse on the TX side, the TX generates
the fastest current pulse achievable by the slow BCDprocess. When input digital data (IN) comes in, the edges ofIN are detected by edge detectors. When a rising edge of IN
is detected, the coil driver DR1 outputs “H” (High) while
DR2 outputs “L” (Low). The current in TX-coil, ITX, starts
increasing. This phase continues about 1ns. Then, DR1outputs “L” and DR2 outputs “H”, which starts decreasing
ITX. This phase should end when ITX becomes zero. In orderto fulfill this condition, the timing of the rising edge of thedriver input, VC1, can be tuned by 4 levels using the
programmable fall-edge detector (P-FED). After all, a shortpositive current pulse of ITX is generated as shown in Fig.5.
On the other hand, when a falling edge of IN is detected,
similar circuit operation generates a negative current pulse of
ITX with a pulse width of about 2-ns.

71

IEEE ICICDT 2019, Suzhou, China

VA1

Fall-Edge
Detector
(FED)

DR1

VB1

ITX

ITX

TX-coil 2

Programable
Fall-Edge
Detector(P-FED)

Pulse-widthcontrol(4 levels)

IN

PU2 is activated, Schmitt trigger ST2 cannot output low,making ST2 dead for a while and neglect the positive pulse
part in “LH-wave” of VE2. This means that the RX neglects
the counter pulse realizing a counter-pulse immune receiver.
Similarly, when “HL-wave” is applied to the Schmitt
trigger, ST2, VF2 negative pulse is generated and it kills ST1
so that ST1 output pulse is suppressed. After all, the counterpulse immunity is achieved even though the counter pulse ishigh, being different from the previous system. This ensuresa fast digital signaling excluding intentionally blunted signal
in the previous scheme. In essence, two Schmitt trigger
circuits are cross-coupled so that a preceding signal pulse
kills the succeeding counter pulse to realize the fast CounterPulse Immune Receiver.

VC1

TX-coil 1

Rise-Edge
Detector(RED)

Session 5 - Digital IC

Driver
Programable
Fall-Edge
Detector(P-FED)

VA2

VB2

VC2

DR2IN
VA1

RED

Schmitt trigger
ST1

FED

VD1

P-FED

0V

VDD

PU1

VE1
R

VRX

VF1
5V

VSET
Fall-Edge
Detector
(FED)

VG1

ENABLE

RX-coil 2

VB1

P-FED

RX-coil 1

VA2C

4 levels controlVB2

VRX
VD2

VC1

RC0V
VG2

VE2

Schmitt trigger
ST2Fall-Edge
Detector(FED)
VF25V

OUT
VRESET

VDD PU2VC2VTH,H
VE1
(VD1)

ITX
~2nsFig. 5. Schematic and operation diagram of proposed TX circuit

HL-wave

LH-wave

LH-wave

HL-wave

VTH,L
VTH,H

VE2
(VD2)

C. Receiver: Counter-Pulse Immunity
The circuit diagram of the receiver is shown in Fig.6.
When the positive current pulse of ITX is transferred to theRX side, a voltage waveform like “HL-wave” in Fig.6 (b) isgenerated on RX-coil1 designated as VD1, while a voltage
waveform like “LH-wave” is generated at RX-coil2
designated as VD2. First, these waves go through high passfilters (HPF) consisting of C and R in Fig.6(a). C is designed
around 400-fF and R is chosen to be about 6.5-kΩ. This highpass filter eliminates slow voltage noise generated by
Common-Mode Transition of GNDTX and GNDRX describedin Chapter D to improve the CMT immunity.
The voltage waveform of VE1 is the same as VD1 while
the DC voltage is shifted so that VE1 stays about a half VDD
in a signal waiting phase. In the signal waiting phase,Schmitt trigger circuit does not change its state unless aninput noise goes beyond the range between VTH,H and VTH,L,
which does not happen. VTH,H – VTH,L is set around 2 x 0.33V. When “HL-wave” is applied to the Schmitt trigger, ST1, anegative pulse is generated at VF1. The pulse length isproperly enlengthened to result in VG2 pulse whose width isabout 1-ns and this activates PMOS pull-up, PU2. When

VF1VTH,L( VSET )VF2( VRESET )
VG1
VG2

FED

FED

Pull up

Pull up
Duration is pre-fixedby FEDOUTFig. 6. Schematic and operation diagram of proposed RX circuit

D. Receiver: Common-Mode Transition Immunity
Common-Mode Transition Immunity (CMTI) is anotherimportant consideration for a digital isolator. The signaling
should be carried out even when TX ground (GNDTX) andRX ground (GNDRX) is changing at the rate of dv/dt (kV/µs),
the maximum value of which without an error is called
CMTI. By inserting a proper high pass filter (HPF) at the72

Paper 5.4IEEE ICICDT 2019, Suzhou, China

front of the RX circuit, the CMT noise can be mitigated.
Fig.7 is the simulation results for the CMTI. The simulated
CMTI for the proposed circuit is 130 kV/µs.
GNDRX – GNDTX [kV]IN [V]

IN

130kV/µs

2ns
OUT

5ns

VD1 [V](before HPF)
697mV

Fig. 9. Measured 500Mbps operation
VE1 [V](after HPF)

Table 1. Comparison with prior publication
This work

286mV

OUT [V]time(ns)Fig. 7. Common-Mode Transition Immunity SimulationIV.

MEASUREMENT RESULTS AND DISCUSSIONSThe chip has been manufactured with the 0.18-µm BCD
process. The maximum gate voltage is 5V and thetechnology allows to implement 15-V output voltage driverneeded for power devices such as IGBT’s on the same chip.
The photo of the assembled digital isolator with the proposed
two-chips configuration is shown in Fig.8. 500-Mbps
operation is demonstrated in Fig.9.
Table I shows a comparison with the prior publications.
The proposed digital isolator circuit provides the fastest
digital isolator. As a conclusion, a high-speed operation isachieved by the proposed CPIR scheme. Added to the highspeed operation, the proposed scheme is can be integrated
with a smart digital driver needed in the next-generation
power electronics.

TX circuit
13275µm2

Ref. 4

Ref. 5

Edge detection

Edge detection

OOKOOK

Process

5V 0.18μm CMOS
(LP=0.5μm,LN=0.6μm)

5V standard
CMOS(L=0.54μm)

5V 0.18μm
CMOS-Max data rate

500Mbps

250Mbps-150Mbps

IDD@1Mbps, 5V

1.16mA

1.6mA

2.8mA

3.3mA

Energy per bit@100Mbps, 5V

1.52nJ/bit

5nJ/bit-335pJ/bit

Number oftransformers

2122Transformer Φ250μm

230μm-500μm(estimated)

Isolation rating>1kV (*)

2.5kV

20kV

2.5kV

Common-mode
transition
immunity

130kV/μs(simulation)

35kV/us200kV/us

100kV/us(*) Higher voltage experiments could not be conducted due to equipment limit.

ACKNOWLEDGMENT
Useful discussions with Dr. Kohei Onizuka and Mr.
Hiroaki Ishihara from Toshiba Corporation areacknowledged.
REFERENCES[1] K. Miyazaki, S. Abe, M. Tsukuda, I. Omura, K. Wada, M. Takamiya
and T. Sakurai, "General-Purpose Clocked Gate Driver (CGD) IC with
Programmable 63-Level Drivability to Reduce Ic Overshoot andSwitching Loss of Various Power," Applied Power Electronics
Conferenceand Exposition (APEC), pp. 1640- 1645, 2016.
[2] S. Kaeriyama, S. Uchida, M. Furumiya, M. Okada, T. Maeda and M.
Mizuno, "A 2.5 kV isolation 35 kV/usCMR 250 Mbps digital isolator
instandard CMOS witha small transformer driving technique," IEEEJournal of Solid-State Circuits, vol. 47, no. 2, pp. 435-4, February2012.
[3] Y. Take, N. Miura and T. Kuroda, "A 30 Gb/s/Link 2.2 Tb/s/mm2
Inductively-Coupled Injection-Locking CDR for High-Speed DRAM
Interface," IEEE Journal of Solid-State Circuits, vol. 46, no. 11,
November 2011.
[4] R. Yun, J. Sun, . E. Gaalaas and B. Chen, "A Transformer-based Digital
Isolator With 20kVPK Surge Capability and > 200kV/µS Common
Mode Transient Immunity," Symposium on VLSI Circuits Digest ofTechnical Papers, 2016.
[5] ADuM110N Data Sheet, Analog Devices, Available :https://www.analog.com/media/jp/technical-documentation/datasheets/ADuM110N_jp.pdf, 2015.

1mm
TX chip

Ref. 2ArchitectureRX chip
Inductors
250µm઴ ൈ2RX circuit3350µm2

Fig. 8. Chip photo of proposed digital isolator

73