IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 11, NOVEMBER 20092511

A 107-pJ/bit 100-kb/s 0.18-m
Capacitive-Coupling Transceiver With Data
Edge Signaling and DC Power-Free Pulse Detector
for Printable Communication Sheet
Lechang Liu, Makoto Takamiya, Member, IEEE, Tsuyoshi Sekitani, Yoshiaki Noguchi,
Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Fellow, IEEE, Takao Someya, Member, IEEE, andTakayasu Sakurai, Fellow, IEEE

Abstract—A novel communication system which simultaneously achieves the mobility of wireless communication and the
low-power performance of wireline communication is developedwith a printable sheet. By combining meter-scale wireline communication and micrometer-scale wireless capacitive-coupling
communication, the proposed communication system enables multiple electronic objects scattered over tables, walls, and ceilings tocommunicate contactlessly with each other by establishing communication paths without cumbersome physical connections. The
transceiver developed for the 20 cm 20 cm communication sheet
features a data-edge-signaling transmitter and a dc power-freepulse detector, thereby achieving the lowest energy of 107 pJ/bit
at 100 kb/s in wireless communications at a distance of 60 cm in
0.18- m CMOS.
Index Terms—Capacitive coupling, inductive coupling, lowpower, proximity communication, transceiver.

I. INTRODUCTIONU

BIQUITOUS electronics refers to electronic environments that are sensitive and responsive to the presenceof people. In a ubiquitous electronics world, devices work inconcert to support people to carry out their activities and tasks
in an easy natural way using information and intelligence thatis hidden in the network connecting these devices. The visionon the future of consumer electronics and telecommunications
is shown in Fig. 1(a). To protect safety and security, promote

Manuscript received October 15, 2008; revised December 10, 2008. First published February 18, 2009; current version published November 04, 2009. This
work is supported in part by CREST, by the Japan Science and Technology
Agency, and by the the Ministry of Education, Culture, Sports, Science andTechnology. This paper was recommended by Associate Editor Y. Massoud.
M. Takamiya is with the VLSI Design and Education Center, The Universityof Tokyo, Tokyo 153-8505, Japan.
T. Sekitani, Y. Noguchi, and K. Zaitsu are with the Quantum-Phase Electronics Center, School of Engineering, The University of Tokyo, Tokyo 1138656, Japan.
S. Nakano was with The University of Tokyo, Tokyo 113-8656, Japan. He is
now with Toshiba Corporation, Tokyo, 141-8664, Japan.
T. Kuroda is with the Department of Electronics and Electrical Engineering,
Keio University, Yokohama 223-8522, Japan.
T. Someya is with the Department of Applied Physics and the Quantum-Phase
Electronics Center, School of Engineering, The University of Tokyo, Tokyo 1138656, Japan.
L. Liu and T. Sakurai are with the Institute of Industrial Science, The University of Tokyo, Tokyo 153-8505, Japan (e-mail: llch@iis.u-tokyo.ac.jp).
Digital Object Identifier 10.1109/TCSI.2009.2015596

Fig. 1. (a) Ubiquitous electronics. (b) Proposed commutation system.

healthcare and welfare, and provide entertainment and convenience, 1000–10 000 electronic devices are distributed aroundthe user’s environment.
The future ubiquitous electronics requires a huge number ofchips, and thus, each of the chips should be implemented at aminimal power level. To capture the user’s environment, thebasic idea is to integrate sensor networks into wireless communication systems. However, singular wireless communication systems attain improved flexibility and mobility at the expense of increased circuit complexity and power consumption
over their wireline counterparts. In this paper, a novel communication method which simultaneously achieves the mobilityof wireless communication and the low-power performance of
wireline communication is implemented with a low-cost printable sheet [1], [2]. The proposed commutation system is shownin Fig. 1(b). By combining meter-scale wireline communicationand micrometer-scale wireless capacitive-coupling communication, the sheet enables multiple electronic objects scattered overtables, walls, and ceilings to communicate contactlessly with

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Compared with the capacitive-coupling system, an inductivecoupling system can transfer both power and signal information across an interface. A large size of inductors is required
to send both dc and ac signals, which negates the ability tohave high-density integration. However, if the inductive coupling is only used to transfer ac information, the size of inductors
can be reduced, and a simple current-mode driver is sufficient.
Fig. 2(b) shows the simplified schematic of the inductive-cou, the energy conpling system. For the given receiver voltage
sumption of the transmitter can be approximated by(2)

Fig. 2. Comparison of capacitive and inductive coupling. (a) Capacitive coupling. (b) Inductive coupling. (c) Energy–frequency characteristic.

each other by establishing communication paths without cumbersome physical connections. Together with the wireless powertransmission sheet [3], [4], the presented communication sheet
can build an infrastructure for ubiquitous electronics, wirelesssensor networks, and ambient intelligence.
The overview of the whole communication system is described in Section II. Sections III and VI present the proposed
data-edge-signaling transmitter (TX) and the dc power-freereceiver (RX), respectively. Experimental results are presented
in Section V, and Section VI concludes this paper.
II. PRINTABLE COMMUNICATION SHEETA. Capacitive versus Inductive Coupling
The communication between the transceiver and the sheet issimilar to the conventional proximity communication [5]–[11].
Proximity communication is based on the observation that fasterlower cost communication is possible over shorter distances. For
the communication sheet, this is achieved by placing two sheets
face-to-back in a manner that aligns the pads of the TX/RX
sheet with the pads of the routing sheet. Proximity communication can be implemented by capacitive and inductive coupling.
The option between capacitive and inductive coupling is complicated by various factors. If the received signal is large enoughso that the power consumption of the receiver can be ignored,
the power consumption of the whole system is only determinedby the transmitter.
For the capacitive-coupling system, the transmitter requirement is straightforward. A simple chain of inverters with adequate drive strength is usually sufficient. Fig. 2(a) shows thesimplified schematic of capacitive-coupling system. The capacand
represent the coupling and parasitic capaciitancesandform a capacitancetances of the sheet, respectively.
divider and reduce the received signal swing on the receiver pad.
The energy consumption of the capacitive-coupling system canbe approximated by(1)

In the communication sheet, the available maximum effective
inductance is 10 H, and the worst case parasitic capacitance is
100 pF. If the given receiver voltage
is 0.6 V, the required
coupling capacitance should be 50 pF. Fig. 2(c) shows the calculated frequency dependence of TX energy consumption. The
target data rate is limited to 100 kb/s by the bandwidth of theplastic microelectromechanical system (MEMS) switches. At
the target data rate, the energy of capacitive coupling is two orders of magnitude lower than that of inductive coupling. Therefore, the capacitive coupling is used in such a low-data-rate andlow-parasitic-capacitance system.
B. System Overview
The overview of the whole system is shown in Fig. 3(a).
The point-to-point communication is achieved by combining
the meter-scale wireline communication on the sheet and themicrometer-scale proximity communication between the sheet
and the transceiver. This work implements proximity communication by capacitively coupling the transmitter to the receiver.
The transmitter drives a plate of metal on the TX sheet that couples to a corresponding plate of routing line on the communication sheet, and the plate on the other end of the routing line, inturn, drives the receiver on the RX sheet. The typical pad distance for the capacitive coupling is 75 m, which corresponds
to 50-pF capacitance. In this application, differential signaling
is required because there is no common ground among the TX,
communication, and RX sheets. The 90 rotation of the TX/RX
sheet can be countered by the other two additional pads.
The communication route is dynamically formed using theplastic MEMS switches, and the routing information is stored
in the organic nonvolatile memories [2]. The “1”–“0” current
ratio of organic nonvolatile memory exceeds 10 , and the retention time is more than 15 days in air. In practical application, the routing on the communication sheet is similar to
the routing of a 2-D field-programmable gate array. With theincreased size of the communication sheet and the increased
number of electronic objects scattered over the sheet, speciallydesigned programmable switch blocks are required, and the interference between different TX/RX pairs due to crosstalk andmisalignment is inevitable [12]. To simplify the analysis of thewhole communication system, a routing model for nonoverlapped point-to-point communication is proposed in Fig. 3(b).
units, and every unit consists
The sheet is composed ofof four pads. The communication between each two units isachieved by turning on the adjacent two MEMS switches andAuthorized licensed use limited to: UNIVERSITY OF TOKYO. Downloaded on December 11, 2009 at 01:45 from IEEE Xplore. Restrictions apply.

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Fig. 4. Device structure of communication sheet.

measured result shows that the deterioration of position-detection sensitivity due to the four sheets above the coil array is only
7% and that this value can be ignored. The principle of the position-sensing sheet is similar to the power transmission sheet ofthe literature [4]. A voltage of 10 V at a resonance frequency(2.95 MHz) is applied to the position-sensing cells. When the
distance between the position-sensing coil and the receiver coil
reduces, the output voltage will be increased by 91%.
Fig. 3. (a) Overview of the communication system. (b) Model of thecommunication sheet.

III. DATA-EDGE-SIGNALING TRANSMITTER
A. DC Wander Effectthe top two routing switches. Thus, only four switches are required for the point-to-point communication. Since the information transmitted over the sheet is confined in a small spaceclose to ad hoc routed paths, the system is free from the issues
related with radio-frequency band allocation which has alreadybeen tight.
C. Device Structure
The device structure of the communication sheet is shown in
pad
Fig. 4(a). It consists of five low-cost printed sheets: aarray for capacitive coupling, two
MEMS switching maorganic nonvolatile
trices for differential signal routing, apomemory array for routing information storage, and an
capacitive-coupling padsition-detection coil array. The
arrays are fabricated on a polyimide film. The side length of
the square pad is 9.7 mm, and the distance between each pad
is 3.0 mm. Silver gate electrodes and polyimide gate dielectric
layers are patterned by using inkjet printing.
The MEMS switching matrix is formed by using inkjet
printing and screen printing. The electrodes for electrostatic
attraction are patterned on a 25- m-thick polyimide membrane. Compared with an organic FET switch, a MEMS switch
provides lower ON-resistance and lower parasitic capacitance,
which contributes to low energy/bit communication. When
9 V is applied to the control electrodes of the MEMS switch,
the resistance changes from 1 M to 20 . The maximum
frequency response of the MEMS switch is 1 kHz.
The position-sensing coil array is manufactured by screen
printing. The inner diameter of the copper coils is 10 mm. Boththe width and spacing of the copper lines are 100 m. The inductance and resistance are 20 H and 17 , respectively. The

For the capacitive coupling, a key constraint to consider isthat, when a long string of “1s” and “0s” is passed through thetransmitter, the signal experiences the dc wander effect. For thecapacitive-coupling system in Fig. 3(a), the series coupling capacitance yields a high-pass characteristic. In the time domain,
the high-pass filtering passes the time rate change of the voltage. The receiver will receive positive pulses for
signalrising edges and negative pulses for falling edges. This makes
the detection of the signal more difficult since the dc drift of thesignal causes a loss of noise margin.
B. Data Edge Signaling
Conventionally, quantized feedback is introduced to generate
a complementary signal to compensate the decaying signal[13]. In this paper, the input non-return-to-zero (NRZ) signal
signal pulse to avoid thisis converted into a return-toconstraint. As shown in Fig. 5(a), compared with the previous
synchronous circuits [14], the proposed asynchronous circuits
have no global clocks, and the operation is triggered by signaltransitions, potentially having the advantages of low power
dissipation.
Fig. 5(b) shows the schematics of the proposed transmitter.
The modulated data are achieved by switching the input data
generator [15]. The edge deand the output of the half
tector is used to generate the switching signal for the selector
by detecting both the rising and falling edges of the input
data. Fig. 5(c) shows the simulated dependence of the power
consumption on the data-transition probability at 100 kb/s. The
power consumption of the transceiver is proportional to thedata-transition probability. In the conventional synchronous
topology, the transmitted signal changes at every clock cycle,
and the consumed power is constant for different data rates. In

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Fig. 6. DC power-free pulse detector. (a) Circuit schematic. (b) Operation
principle.

Fig. 5. Data-edge-signaling transmitter. (a) DC wander effect. (b) Circuit
schematic. (c) Power dependence on data transition.

the proposed asynchronous topology, the power consumption of
the transceiver can be reduced by 48.3% at 50% data-transition
probability.
IV. DC POWER-FREE PULSE DETECTOR
A. DC Power Dissipation of Conventional Receiver
The receiver requirements depend upon the details of theinterconnecting medium and the expected signal degradationfrom driver to receiver. Capacitive coupling is implemented byforming one of the electrodes on the pad of the TX/RX sheet
and the other electrode on the pad of the communication sheet.
When the chip is brought into extremely close proximity, a capacitor is formed. In this implementation, no mechanism exists
to allow dc input voltage to pass through the same interface as
the ac coupled signals. In the conventional capacitive-couplingtransceiver, the dc level of the received signal is first biased toa reference voltage, and then, an amplifier and a comparator isused in the first stage of the receiver to amplify the signal for thefollowing demodulation [14], [16]. The major disadvantage of

Fig. 7. Simulated ratio dependence. (a) Voltage bias
consumption.

1V . (b) Power

this topology is the large dc power dissipation that occurs evenfor no ac input. In the transmitted signal of the communication
sheet, the circuit spends long periods of time with no ac signal.
Power dissipated in these periods is wasted.
B. DC Power-Free Pulse Detector
The design aims to minimize the dc power consumption byimplementing a dynamic threshold receiver and a pulse detection approach that maximize power efficiency. The proposed dc
power-free pulse detector is basically based on the CMOS inverter. As shown in Fig. 6(a), the gate of the inverter is biased toand capacitively coupled to the received data while thesource of the inverter is biased toand capacitively
coupled to the inverted received data. Fig. 6(b) shows the voltages on nodes A and B and the logical threshold of the inverter.
When the received voltage on node A and the logical thresholdof the inverter are overlapped, the pulse is detected, and thepower is only consumed on this period. Unbalanced inverters
with lower threshold voltages can be used to further reduce thepower consumption. As shown in Fig. 7, for the given received
and the power consumption can
voltage, the required bias

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Fig. 8. DC power-free receiver. (a) Circuit schematic. (b) Simulated
waveforms.

be decreased with the increase of the ratio between PMOS and
NMOS.
Fig. 8(a) shows the circuit schematic of the proposed pulse
detector. Two unbalanced inverters are used to detect the risingand falling edges, respectively, and the detection results are level. The simulated waveforms of the received signal
shifted toand power supply current of the two inverters are shown in
Fig. 8(b). The proposed pulse detector consumes essentiallyzero power dissipation for no ac input.

Fig. 9. (a) Chip micrographs. (b) Measurement setup.
TABLE IPERFORMANCE SUMMARY

V. MEASUREMENT RESULTS
A. Performance Summary
A test chip was designed and fabricated in 0.18- m 1P6M
CMOS process, and the microphotograph is shown in Fig. 9(a).
The core area for the TX and RX are 2475 and 975 m , respectively. Fig. 9(b) shows the measurement setup. The TX/RX
chips are bonded to the TX/RX pads on the TX/RX sheet, andthe pads are capacitively coupled to the communication sheet.
To simplify the measurement, the MEMS switching matrices,
the organic nonvolatile memory array, and the position-detection coil array are removed, and the communication route is laidout to 60 cm directly.
The measured performance is summarized in Table I. The developed data edge signaling and the dc power-free pulse detector
enable 107-pJ/bit energy consumption at 100 kb/s. Fig. 10(a)shows the measured waveforms at 100 kb/s. The transmitted
signal Txout, and the amdata are converted to return-toplitude of Txout is 1.8 V. The amplitude of the received signal
Rxin is 0.5 V, and Dataout is the demodulation output. Theeye diagram at the maximum data rate of 8 Mb/s is shown in
Fig. 10(b). The maximum data rate is determined by the drive
current of the transceiver and the parasitic capacitance of thecommunication sheet. For the given parameters of the communication sheet, a higher data rate can be achieved by increasing
the drive current of the transmitter and the receiver.
B. Misalignment Tolerance
For the capacitive-coupling system, a critical challenge inhigh-performance communication is correctly aligning the padson the sheets. In an aligned proximity communication system,
each TX/RX pad lines up perfectly with a routing pad, and the

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Fig. 10. Measurement results. (a) Measured waveforms at 100 kb/s. (b) Eye
diagram at 8 Mbits/s.

pads are pushed together such that their dielectric and passivation surfaces touch or nearly touch, thus maximizing the signal
coupled between the pads, reducing the parasitic capacitance,and saving the power. With misaligned pads, one transmitter
will be coupled to several other receivers, simultaneously reducing the intended signal and increasing crosstalk to the otherreceiver.
Fig. 11(a) shows the measured sensitivity requirement for
the horizontal misalignment and the vertical pad distance. The
to achieve thecontour represents the required minimum
capacitive-coupling communication. For the normal 75- m paddistance, which is equal to the sheet thickness, the sheet canoperate up to 3.75-mm displacement. The maximum tolerable
displacement is 7.5 mm, which corresponds to the 77% of thepad size.
The sensitivity of the receiver is tuned by the source bias
voltage of the inverter. The amplitude of the received voltage. Withcan be approximated by
the increased size of the communication sheet, the parasitic capacitance of the sheet will be increased, and therefore, the received voltage will be reduced. The tradeoff between the RX
sensitivity and the power consumption is shown in Fig. 11(b).
, the sensitivity of
By reducing the bias voltage
the receiver can be increased and communication distance canbe extended but the power consumption will be increased. The
power consumption of the receiver can be further reduced bylowering the supply voltage. Fig. 11(c) shows the measured
supply voltage dependence of power consumption. The voltages
andrepresent the gate and source biases,

1

Fig. 11. (a) V dependence of displacement. (b) Tradeoff between power andsensitivity. (c) Supply voltage dependence of power consumption.

Fig. 12. Comparison with the state-of-the-art wireless and wireline
communications.

respectively. Lower power consumption is achieved with lower.
supply voltage
Fig. 12 shows the comparison with the state-of-the-art
communication systems [17]–[20]. Wireline communicationrefers to the transmission of data over a wire-based communication technology. Examples include telephone networks,
cable television, and fiber-optic communication. Alternatively,
wireless communication is used to describe telecommunications in which electromagnetic waves carry the signal over

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LIU et al.: CAPACITIVE-COUPLING TRANSCEIVER WITH DATA EDGE SIGNALING AND DC POWER-FREE PULSE DETECTOR

the communication path. Examples of short-distance wirelesstechnology include wireless LAN and ultrawideband. Compared to wireless communication, the communication sheet
fills the space around it with a nonradiative electric field insteadof irradiating the whole environment with electromagnetic
waves. As shown in Fig. 12, the proposed communication
method achieves lower energy consumption than conventional
wireless communication, thus realizing a low-energy feature of
wireline communication with an easy-to-use feature of wirelesscommunication.
VI. CONCLUSION
cm
cm communicaA transceiver for the printabletion sheet combining the capacitive coupling and the point-topoint connection from TX to RX on the sheet has been developed. The transceiver with a data-edge-signaling transmitterand dc power-free pulse detector achieves the lowest energy of
107 pJ/bit at 100 kb/s in the wireless communications at a distance of 60 cm in 0.18- m CMOS. The proposed data-edge-signaling transmitter avoid the dc wander effect by converting thesignal. For the 50% datainput NRZ signal to return-totransition probability, the power consumption of the transceivercan be reduced by 48.3%. The proposed dc power-free detector
has essentially zero power dissipation for no ac input, and thefour-pad differential signaling scheme can tolerate 7.5-mm misalignment, which corresponds to 77% of the pad size.
ACKNOWLEDGMENT
The electronic-design-automation (EDA) tools are supportedby the VLSI Design and Education Center, The University ofTokyo, Tokyo, Japan, in collaboration with Cadence Design
Systems, Inc., Synopsys, Inc., and Mentor Graphics, Inc.

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[3] T. Sekitani, M. Takamiya, Y. Noguchi, S. Nakano, Y. Kato, K. Hizu, H.
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m

Lechang Liu received the B.S. degree from Shandong University, Jinan, China, in 2000, the M.S.
degree from Harbin Institute of Technology, Harbin,
China, in 2002, and the Ph.D. degree in electronicengineering from Shanghai Jiao Tong University,
Shanghai, China, in 2006.
From 2007 to 2009, he was with VLSI Design
and Education Center, The University of Tokyo,
Japan, where he conducted research on low-powerand high-performance impulse radio ultra-wideband(UWB) transceivers. Since 2009, he has been a
project researcher with the Institute of Industrial Science, The University ofTokyo, Japan. His current research interests include signal processing andmixed-signal circuit design for low-power wireless communications.

Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom The University of Tokyo, Tokyo, Japan, in
1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high-speed
digital large-scale integration. In 2005, he joined The
University of Tokyo, where he is an Associate Professor with the VLSI Design and Education Center.
His research interests include the circuit design of
low-power RF circuits, ultralow-voltage digital circuits, and large-area electronics with organic transistors.
Dr. Takamiya is a member of the technical program committees for theIEEE Symposium on VLSI Circuits and the IEEE Custom Integrated Circuits
Conference.

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Tsuyoshi Sekitani was born in Yamaguchi, Japan,
in 1977. He received the B.S. degree from Osaka
University, Osaka, Japan, in 1999, and the Ph.D.
degree in applied physics from The University ofTokyo, Tokyo, Japan, in 2003.
From 1999 to 2003, he was with the Institute for
Solid State Physics, The University of Tokyo, where
he developed measurement techniques in magnetic
fields up to 600 T and studied the solid-state physics
of condensed matter, particularly in high-Tc superconductors, and where he has been a Research Associate with the Quantum-Phase Electronics Center since 2003. His current objectof physics research is organic semiconductors and organic-FET devices.
Dr. Sekitani is a member of the Materials Research Society, the PhysicalSociety of Japan, and the Japanese Society of Applied Physics.

Yoshiaki Noguchi was born in Kanagawa, Japan,
in 1983. He received the M.S. degree in applied
physics from The University of Tokyo, Tokyo, Japan,
in 2007, where he is currently working toward the
Ph.D. degree in applied physics.
His research interests include organic transistors,
large-area electronics, and printed electrical devices.
Mr. Noguchi is a student member of the JapaneseSociety of Applied Physics. He is also a member of
the Japan Society for the Promotion of Science Research Fellowships.

Shintaro Nakano received the M.S. degree in applied physics from The University of Tokyo, Tokyo,
Japan, in 2008, where he developed large-area
printed microelectromechanical systems switches
for organic electronics.
He is currently with Toshiba Corporation, Tokyo,
Japan.
Mr. Nakano was the recipient of the Tanaka Shoji
Award for applied physics from The University ofTokyo in 2008.

Koichiro Zaitsu was born in Oita, Japan, in 1984. Hereceived the B.S. degree in applied physics from The
University of Tokyo, Tokyo, Japan, in 2007, where
he is currently working toward the M.S. degree in applied physics.
His research interests include ferroelectric polymers and new devices integrated with organic
transistors.
Mr. Zaitsu is a member of the Japanese Society ofApplied Physics.

Tadahiro Kuroda (M’88–SM’00–F’06) received the
Ph.D. degree in electrical engineering from The University of Tokyo, Tokyo, Japan, in 1999.
In 1982, he joined Toshiba Corporation, Tokyo,
Japan, where he designed CMOS SRAMs, gatearrays, and standard cells. From 1988 to 1990,
he was a Visiting Scholar with the University ofCalifornia, Berkeley, where he conducted researchin the field of VLSI computer-aided design. In
1990, he returned to Toshiba Corporation where he
was engaged in the research and development of
BiCMOS application-specified integrated circuits, emitter-coupled-logic gatearrays,ECL high-speed CMOS large-scale integrations (LSIs) for telecommunications, and low-power CMOS LSIs for multimedia and mobile applications.
He invented a variable threshold-voltage CMOS technology to control VTH
through substrate bias and applied it to a DCT core processor and a gate array in
1995. He also developed a variable supply-voltage scheme using an embedded
dc–dc converter and employed it to a microprocessor core and an MPEG-4
chip for the first time in the world in 1997. In 2000, he joined Keio University,
Yokohama, Japan, where he has been a Professor since 2002. He has been

a Visiting Professor with both Hiroshima University, Hiroshima, Japan, andUniversity of California, Berkeley. He has published more than 200 technicalpublications, including 50 invited papers and 20 books/chapters, and has filed
more than 100 patents. His research interests include low-power high-speed
CMOS design for wireless and wireline communications, human–computerinteractions, and ubiquitous electronics.
Dr. Kuroda is an elected AdCom member for the IEEE Solid-State Circuits
Society (SSCS) and an IEEE SSCS Distinguished Lecturer. He was the General
Chairman for the Symposium on VLSI Circuits, the Vice Chairman for the Asia
and South Pacific Design Automation Conference (ASP-DAC), the subcommittee chair for the Asian Solid-State Circuits Conference, the International
Conference on Computer-Aided Design, and the Structures, Structural Dynamics, and Materials Conference (SSDM), and a program committee member
for the Symposium on VLSI Circuits, Custom Integrated Circuits Conference,
DAC, ASP-DAC, International Symposium on Low-Power Electronics andDesign, SSDM, International Symposium on Quality Electronic Design, andother international conferences. He is a recipient of the 2005 IEEE System
LSI Award, the 2005 P&I Patent of the Year Award, the 2006 LSI IP DesignAward, the 2006 IP/SoC Best Design Paper Award, and the 2007 ASP-DACBest Design Award.

Takao Someya (M’03) received the Ph.D. degree inelectrical engineering from The University of Tokyo,
Tokyo, Japan, in 1997.
In 1997, he joined the Institute of Industrial
Science, The University of Tokyo, as a Research
Associate. He was appointed as a Lecturer with
the Research Center for Advanced Science andTechnology, The University of Tokyo, in 1998,
where he was an Associate Professor in 2002. From2001 to 2003, he was with the Nanoscale Scienceand Engineering Center, Columbia University, New
York, NY, and with Bell Labs, Lucent Technologies, as a Visiting Scholar.
Since 2003, he has been an Associate Professor with the Department of Applied
Physics and the Quantum-Phase Electronics Center, The University of Tokyo.
His current research interests include organic transistors, flexible electronics,
plastic integrated circuits, large-area sensors, and plastic actuators.
Prof. Someya is a member of the IEEE Electron Devices Society, the Materials Research Society, and the Japanese Society of Applied Physics. He is asubcommittee member for IEEE International Electron Devices Meeting and a
program cochair for the Third Organic Microelectronics Workshop.

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom The University of Tokyo, Japan, in 1981.
In 1981, he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and system-on-a-chip solutions. He has
worked extensively on interconnect delay and capacitance modeling known as the Sakurai model and thealpha power-law MOS model. From 1988 to 1990,
he was a Visiting Researcher with the University ofCalifornia, Berkeley, where he conducted research in
the field of VLSI computer-aided design. Since 1996, he has been a Professor
with The University of Tokyo, Tokyo, Japan, working on low-power high-speed
VLSI, memory design, interconnects, ubiquitous electronics, organic ICs, andlarge-area electronics. He has published more than 350 technical publications,
including 70 invited publications and several books, and filed more than 100
patents.
Dr. Sakurai is a Semiconductor Technology Academic Research Center(STARC) fellow, an elected AdCom member for the IEEE Solid-State Circuits(SSC) Society, and an IEEE Circuits and Systems Society Distinguished
Lecturer. He was a Conference Chair for the Symposium on VLSI Circuits
and the International Conference on IC Design and Technology (ICICDT), a
Vice Chair for the Asia and South Pacific Design Automation Conference, aTechnical Program Committee Chair for the first Asian Solid-State Circuits
Conference and the VLSI Symposia, and a program committee member for
the International Solid-State Circuits Conference (ISSCC), Custom Integrated
Circuits Conference, Design Automation Conference, European Solid-State
Circuits Conference, International Conference on Computer-Aided Design,
FPGA Workshop, International Symposium on Low-Power Electronics andDesign, TAU, and other international conferences. He is a plenary speaker forthe 2003 ISSCC. He is a recipient of the 2005 IEEE ICICDT Award, 2005 IEEE
ISSCC Takuo Sugano Award, and the 2005 P&I Patent of the Year Award.

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