Reduction of Minimum Operating Voltage (VDDmin)of CMOS Logic Circuits with Post-Fabrication
Automatically Selective Charge Injection
Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura*, Makoto Takamiya and Takayasu Sakurai
University of Tokyo, Tokyo, Japan*Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan
WL=0V

Abstract— In order to reduce minimum operating voltage(VDDmin) of CMOS logic circuits, a new method reducing thewithin-die random threshold (VTH) variation of transistors by apost-fabrication automatically selective charge injection using
substrate hot electrons (SHE) is proposed along with novel
circuitry to utilize this. In the new circuit, switches are added to
combinational logic circuits in order to turn them into latch loops.
In order to reduce VDDmin, design guides on the optimal (1) loop
topology, (2) number of stages in a loop, (3) VTH shift per charge
injection, and (4) number of charge injection trials are exploredthrough simulations. By applying the proposed scheme to 96stage inverter chain fabricated in 65-nm CMOS, the measured
reduction of VDDmin from 94mV to 74mV is successfully
demonstrated for the first time.

I.

VDD
INV1
INV2

BL

V1
VTH1

V2

M1

VTH2

M2

Vpwell(= -7V)
Initial : VTH1>VTH2(a)Selective charge injection

INTRODUCTION

Energy efficient operation of CMOS logic circuits enabled
by reducing the power supply voltage (VDD) is strongly
required and a lot of sub/near-threshold logic circuits arereported [1-5]. The VDD scaling, however, is hindered by theminimum operating voltage (VDDmin) [6] of CMOS logic gates.
VDDmin is the minimum power supply voltage when the circuits
operate without function errors. Timing errors are notconsidered in this paper. VDDmin increases with increasing
number of logic gates and CMOS technology down-scaling,
because VDDmin is determined by the random transistor
variations [6]. The trend of increasing VDDmin is a serious
problem in the design of future ultra low voltage (VDD < 0.4V)
logic circuits. A straightforward method to reduce the randomtransistor variations is to increase the size of transistors, which
is not practical. An alternative post-fabrication selfconvergence scheme for suppressing the random variability is
proposed in [7-8]. The threshold voltage (VTH) variation is
reduced by the substrate hot electron (SHE) stress [7] or BTI
stress [8] for SRAM cells and the drain avalanche hot carrier(DAHC) stress for logic transistors [7], respectively. SHE or
BTI stress is effective only for two inverter latch in the SRAM
cell and is not effective for logic circuits, because it is difficult
to form the two inverter latch in random logic circuits. DAHC
is not practical for logic circuits, because DAHC requires half
VDD DC biasing to the gate of all transistors in logic circuits
and DAHC has large DC current during the stress.

VTH1 is constant.
VTH2 is increased due to SHE.

Voltage
3.5V

V2

VDD

“VTH1>VTH2” is detected.

0V

V1
Time

0
Threshold voltage of nMOS(b)

In this paper, in order to reduce VDDmin of CMOS logic
circuits, a new method reducing the within-die random VTH
variation of transistors by a post-fabrication automaticallyselective charge injection using SHE is proposed along withnovel circuitry to utilize this.

978-1-61284-660-6/11/$26.00 © 2011 IEEE

BL

VTH1

VTH2

VSHIFT

Initial 1
2
3
4 5 6
7
Number of charge injection trials(c)Fig. 1 Automatically selective charge injection scheme in SRAM cell. (a)Schematic of SRAM cell. (b) Waveforms applied to SRAM cell for
automatically selective charge injection scheme. (c) Dependence of VTH1
and VTH2 on number of charge injection trials.

175

The remainder of this paper is organized as follows. Section
II presents the concept of the proposed post-fabrication
automatically selective charge injection scheme and the
proposed circuit. Section III presents design guides for the
proposed circuit on the optimal (1) loop topology, (2) numberof stages in a loop, (3) VTH shift per charge injection, and (4)number of charge injection trials. Section IV describes thedetails of the fabricated 96-stage inverter chain test chips in 65nm CMOS and the measured reduction of VDDmin. Finally,
Section V concludes this paper.
II.

Combinational logic
D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

PROPOSED POST-FABRICATION AUTOMATICALLYSELECTIVE CHARGE INJECTION SCHEME

Original concept of automatically selective charge injection
scheme in SRAM cell is explained. Then, the concept is
expanded to logic circuit applications.
A. Original Concept of Automatically Selective Charge
Injection Scheme for SRAM Cell
Fig. 1(a) shows a schematic of an SRAM cell and Fig. 1(b)shows waveforms applied to the SRAM cell for the
automatically selective charge injection scheme [7]. A negative(e.g. -7V) p-well bias (Vpwell) is applied to M1 and M2. Then,VDD is increased from 0V to a high voltage (e.g. 3.5V) and thehigh voltage is kept for a while (e.g. 1 min). When VTH of M2(VTH2) is lower than VTH of M1 (VTH1), V1 goes to 0V during
the ramp of VDD, thereby only VTH2 is increased due to the SHE
stress, because 3.5V is applied to V2 instead of V1. This is theconcept of automatically selective charge injection, because
either M1 or M2 with lower VTH is automatically selected andVTH of the transistor with the lower VTH is increased by the
charge injection due to the SHE stress. The VTH shift due to thecharge injection is nonvolatile. As shown in Fig. 1(c), by
repeating the charge injection process, the mismatch between
VTH1 and VTH2 is reduced [8].

(a)Combinational logic

B. Proposed Automatically Selective Charge Injection
Scheme for Logic Circuits
Fig. 2(a) shows a schematic of a normal logic circuit. In
order to apply the concept of automatically selective charge
injection scheme for SRAM cell into the logic circuit, latch
loops should be introduced in the logic circuit. Figs. 2(b) and(c) show schematics of the proposed logic circuit with theautomatically selective charge injection scheme, where
switches are added to combinational logic circuits in order toturn them into latch loops. Fig. 2(b) shows a normal logic
operation mode and Fig. 2(c) shows a latch mode for
automatically selective charge injection scheme. Ideally, alllogic gates should be included in the latch loops. The inputs ofeach latch loop should be adequately clamped to VDD or VSS inorder to achieve the latch operation. For example, the input of
2NAND is clamped to VDD and the input of 2NOR is clamped
to VSS. How to exhaustively add the switches to random
combinational logic circuits in order to form the latch loops isout of the scope of this paper. By repeating the charge injection
process as shown in Figs. 1(b) and (c), the within-die random
VTH variation is reduced, thereby reducing VDDmin of the logic
circuit. The charge injection could be performed at preshipment test, because the charge injection is nonvolatile.

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

(b)

Combinational logic

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

(c)
Fig. 2 Schematic of a logic circuit. (a) Normal logic circuit. (b) Proposed
logic circuit with automatically selective charge injection scheme innormal logic operation mode. (c) Proposed logic circuit in latch mode.

176




2n stages
2n stagesOut

2n stages

Fig. 3 Cascaded loop

1

In

1

2
n stages

1

1
2

n stagesOut2n stages

(a)
1

1

In

1

2
n stagesn stages

2

1

Out

2
n stages

1
1

1

1

2
n stages2n stages

m=40
=0.29INIT

n=1
Staggered loop
VSHIFT /INIT =40%

0.25
0.2

m=5
=0.62INIT

0.15

Initial=INIT

0.1
0.05
0

Thereshold voltage of nMOS(a.u.)

100

Out

2
n stages

Cascaded loop

80(c)Fig. 4 Staggered loop topology. (a) Normal logic operation mode. (b) Odd-loop
latch mode. (c) Even-loop latch mode.

Because the high voltages shown in Fig. 1(b) would be
supplied from a tester, high voltage generators are not required.
III.

0.3

Fig. 5 Simulated distributions of VTH of nMOS with different number ofcharge injection trials (m) in staggered loop with n=1 and VSHIFT/INIT
=40%.

(b)

In

Shift of mVSHIFT /2

Probability density function (PDF)/ INIT (%)



In

OPTIMAL IMPLEMENTATION OF AUTOMATICALLYSELECTIVE CHARGE INJECTION SCHEME

60
40

Staggered loop

20

n=1
VSHIFT/ INIT=40%

0

In this section, in order to effectively reduce VDDmin, design
guides on the optimal (1) loop topology, (2) number of stages
in a loop, (3) VTH shift per charge injection, and (4) number ofcharge injection trials are explored through simulations.

- 42%

0

10

20

30

40

50

60

Number of charge injection trials
Fig. 6 Simulated dependence of /INIT on number of charge injection
trials of the cascaded loop and the staggered loop at n=1 and VSHIFT/INIT=40%.

Two loop topologies for the charge injection scheme arecompared. Fig. 3 shows a cascaded loop topology and Fig. 4
shows a staggered loop topology. 2n-stage inverters areincluded in each latch loop. In Figs. 3 and 4, the combinational
logic circuit is simplified to an inverter chain. In Fig. 3, eachlatch loop is serially connected and the cascaded loop has only
one latch mode. In contrast, the staggered loop in Fig. 4 has
two latch modes. Fig. 4(a) shows a normal logic operationmode, Fig. 4(b) shows an odd-loop latch mode, and Fig. 4(c)shows an even-loop latch mode.

140

/ INIT (%)

120

In order to investigate the VDDmin reduction by the charge
injection scheme, VTH variation of nMOS is simulated with aMonte Carlo simulation using Matlab. Reducing VTH variationof either nMOS or pMOS is enough, because VDDmin of each
logic gate is determined by the balance between nMOS andpMOS transistors in each logic gate [9]. Therefore, theautomatically selective charge injection is applied to only
nMOS transistors. Fig. 5 shows simulated distributions of VTH
of nMOS with different number of charge injection trials (m) ina staggered loop with n=1. The normal distribution is assumed
for the initial distributions of VTH. The initial and current

n=6

100
n=2

80

n=3

Staggered loop
VSHIT/ NIT=40%

60
40

n=1

20
0

0

10

20

30

40

50

60

Number of charge injection trials
Fig. 7 Simulated dependence of /INIT on number of charge injection
trials with different n at VSHIFT/INIT =40%.

177

140

100

VSHIFT/ INIT=200%

120

100%

40% 20% 10% 4%

Minimum /INIT (%)

Minimum/ INIT (%)

100
80
40%

60
40

0

20%

Staggered loop
n=1

20
1

10%

10

100

80

VSHIFT/ INIT=200%

2%

n=2

1
3
100%

40
20
0

(a)

200%

60

1000

Number of charge injection trials

140

VSHIFT/ INIT=100%

Staggered
loop

40%
20%

n=1 10%

4% 2%

1
10
100
1000
Optimum number of charge injection trials

Fig. 9 Simulated dependence of minimum /INIT on optimum number of charge
injection trials with different VSHIFT/INIT at n=1 and n=2.

/INIT (%)

120
100
80
60
40

Staggered loop
n=2

20
0

1

Minimum

10

100

1000

Number of charge injection trials(b)Fig. 8 Simulated dependence of /INIT on number of charge injection
trials with different VSHIFT/INIT. (a) n=1. (b) n=2.

standard deviation of VTH is defined as INIT and , respectively.
As shown in Fig. 1(c), VTH shift per charge injection is definedas VSHIFT and VSHIFT/INIT =40% is assumed in Fig. 5. The
simulation steps to calculate the distributions of VTH using
Matlab are: (1) 10k random numbers are generated, (2) the
random numbers are divided into groups including 2n numbers,(3) the minimum number in the 2n numbers is selected in eachgroup, and (4) the minimum number and the every othernumbers are increased by VSHIFT. In Fig. 5,  is successfully
reduced by increasing m, while average VTH increases by
mVSHIFT/2. In the proposed charge injection scheme, theaverage VTH increase is compensated by the forward body bias
to nMOS.
Fig. 6 shows the simulated dependence of /INIT on
number of charge injection trials of the cascaded loop and thestaggered loop at n=1 and VSHIFT/INIT =40%. The /INIT ofthe staggered loop is reduced by 42% compared with that of thecascaded loop, because the cascaded loop can not compensate
for an inter-loop mismatch. Therefore, only the staggered loop
is used in the rest of this paper.

178

Fig. 7 shows the simulated dependence of /INIT on
number of charge injection trials with different n at
VSHIFT/INIT =40%. The minimum /INIT at n=1 is 29%, while
the minimum /INIT at n=2, 3, and 6 are 87%, 94%, and 99%,
respectively. The large difference between n=1 and 2 isinvestigated in details. Fig. 8 shows the simulated dependenceof /INIT on number of charge injection trials with different
VSHIFT/INIT at n=1 (Fig. 8(a)) and n=2 (Fig. 8(b)). In order toclarify the difference between n=1 and 2, the minimum /INIT
point is extracted from Fig. 8 and plotted in Fig. 9. Fig. 9shows the simulated dependence of minimum /INIT on
optimum number of charge injection trials with different
VSHIFT/INIT at n=1 and n=2. The minimum /INIT reduces
with decreasing VSHIFT at n=1. The minimum /INIT is 6.2% at
VSHIFT/INIT = 2%, while the optimum number of charge
injection trials is 3515, which is not practical because large
number of charge injection trials increases the pre-shipment
test cost. Therefore, The minimum /INIT of 52% at
VSHIFT/INIT = 100% and the number of trials of 9 or theminimum /INIT of 29% at VSHIFT/INIT = 40% and thenumber of trials of 40 will be a practical choice. In contrast, at
n=2, the minimum /INIT is more than 80% even if
VSHIFT/INIT is 2%, because the mismatch within each loop is
not completely compensated at n=2. Therefore, n=1 is used in
the rest of this paper.
IV.

MEASUREMENT RESULTS

The proposed automatically selective charge injection
scheme is verified with measurements. Fig. 10 shows measured
dependence of drain current on gate voltage of nMOS transistor
in 1.2V 65nm CMOS process before and after the charge
injection by SHE. VTH of 36mV was obtained at the charge
injection condition of VGS=3.5V, VDS=0V, Vpwell= -7V, and 5min.

Drain current

100A
10A

Charge injection condition

BeforeInjection

1A

After
5-min Injection

2

ΔVTH=36mV

In
0V

10nA

0.2

0.4

0.6

0.8

1.0

2

1

1

2

1

1

Vpwell=-7V

3.5V

1nA

1

2

2

2

1

Charge injection by SHE

100nA

100pA
0.0

2

2

2

VDD=3.2V
Vpwell= -7V
1min

2

2
2

1

1

1

Out

1

96-stage inverters
Fig. 11 Fabricated 96-stage inverter chain with the staggered loop. 191
CMOS transfer gates are added to original 96 inverters for the chain.

1.2

VGS(V)
Fig. 10 Measured dependence of drain current on gate voltage of nMOS
transistor of 1.2V 65nm CMOS process before and after the charge injection
by SHE.

670µm

Fig. 11 shows a schematic of a fabricated 96-stage inverter
chain with the staggered loop. When both 1 and 2 are “H”,
the circuit operates in the normal logic operation mode asshown in Fig. 4(a). When 1 is “H” and 2 is “L”, the circuit
operates in the odd-loop latch mode as shown in Fig. 4(b).
When 1 is “L” and 2 is “H”, the circuit operates in the evenloop latch mode as shown in Fig. 4(c). The charge injection isapplied at VDD=3.2V, Vpwell= -7V, and 1 min per injection. 191
CMOS transfer gates to make the staggered loop are added tooriginal 96 inverters for the chain. Area penalty due to the
proposed circuit for the automatically selective charge injection
scheme is discussed. The area of the proposed circuit is about
three times of that of the original 96-stage inverter chain,because the number of logic gates increase from 96 to 287.
According to the Pelgrom plot, /INIT is reduced to 1 3 (=0.58) by tripling the transistor area. Therefore, the proposedcharge injection scheme makes sense when /INIT is less than
1 3 . As shown in Fig. 9, /INIT less than 1 3 is achieved at
the optimum number of charge injection trials larger than 9.
Thus, the proposed charge injection scheme is more effective in
reducing  than simply increasing the transistor area.

280µm(Layout)

8µm

32µm
Fig. 12 The chip micrograph and core area layout of the 96-stage inverter
chain.

120

VDDmin (mV)100

The chip micrograph and core layout of the 96-stage
inverter chain shown in Fig. 11 are shown in Fig. 12. The test
chip was implemented in 1.2V 65-nm CMOS process. The sizeof core is 32m by 8m.
Fig. 13 shows measured dependence of VDDmin of theinverter chain shown in Fig. 11 on Vpwell. The number of charge
injection trials is varied. Charge injection trials of odd-loop
latch mode and even-loop latch mode are performed alternately.
VDDmin is defined as the minimum operating VDD whether 1-Hz
rectangular wave is observed or not from the output of theinverter chain. To compensate for the global variation between
pMOS and nMOS, Vpwell is tuned to find the minimum VDDmin.
Vpwell of the minimum VDDmin is increased as the numbers oftrials increases, because the average VTH of nMOS is increased.

179

80

Initial4times6times40

Number of charge
injection trials

20
0

-21%

Minimum VDDmin

60

Staggered loop
n=1

0

100

200
Vpwell (mV)

300

400

Fig. 13 Measured VDDmin of the inverter chain with various number of charge
injection trials.

Minimum VDDmin (mV)ACKNOWLEDGMENT

100
90
-21%
80
70
Best
60
50
40
30
Staggered loop
n=1
20
10
0
Initial 1
2
3
4
5
6
7
8
Number of charge injection trials

This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial
Technology Development Organization (NEDO).

REFERENCES

Fig. 14 Measured dependence of minimum VDDmin on number ofcharge injection trials. The minimum VDDmin points are extracted from
Fig. 13.

In order to clarify the trend of the minimum VDDmin, theminimum VDDmin point is extracted from Fig. 13 and plotted inFig. 14. In Fig. 13, all the measured points are not shown forsimplicity. Fig. 14 shows the measured dependence ofminimum VDDmin on number of charge injection trials. The
minimum VDDmin is the lowest at 6-time charge injection trials.
The initial minimum VDDmin is 94mV when Vpwell is 120mV.
After 6-time charge injection trials, the minimum VDDmin is
74mV when Vpwell is 250mV. Therefore, VDDmin is reduced by
21% from 94mV to 74mV.

V.

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CONCLUSION

In order to reduce minimum operating voltage (VDDmin) of
CMOS logic circuits, a new method to reducing the within-die
random threshold (VTH) variation of transistors by the postfabrication automatically selective charge injection using
substrate hot electrons (SHE) is proposed along with novel
circuitry to utilize this. The charge injection could be
performed at pre-shipment test. The circuit with the staggered
loop topology and n=1 is the best implementation for the
automatically selective charge injection scheme. The minimum
/INIT of 29% at VSHIFT/INIT = 40% and the number of trialsof 40 is one of a practical design choices. By applying the
proposed scheme to 96-stage inverter chain fabricated in 65-nm
CMOS, the measured VDDmin is successfully reduced by 21%
from 94mV to 74mV.

180