IEEE 2008 Custom Intergrated Circuits Conference (CICC)

Expected Vectorless Teacher-Student Swap (TSS)
Test Method with Dual Power Supply Voltages
for 0.3V Homogeneous Multi-core LSI’s
Taro Niiyama, Koichi Ishida, Makoto Takamiya, and Takayasu Sakurai
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
Abstract- A Teacher-Student Swap (TSS) test method with thedual supply voltage (VDD) for the ultra low VDD homogeneous
multi-core LSI’s is proposed and the test chips are fabricated in90 nm CMOS. In this method, two same cores with different
power supply voltages test each other by comparing their outputs,
which eliminates the need for the expected vector. When VDD isless than 0.3V, the die-to-die power reduction by the dual VDD in
the 5 chips was from 18% to 48%. In order to manage the large
die-to-die variations at low VDD, the fine grain dual VDD with TSS
test method is a promising approach without increasing the test
cost.

gates due to device variations, and VDDmin increases with thenumber of logic gates [7]. Therefore, the fine grain VDD tuning[7] is required to reduce VDD of the subthreshold logic circuits
and the tuning also raise the test cost.
This paper presents a new test method to reduce the test
cost in ultra low VDD homogeneous multi-core LSI’s. The
concept of the proposed Teacher-Student Swap (TSS) test
method is shown in Section II. Section III presents the chip
implementation of the dual VDD homogeneous multi-core
LSI’s with TTS test method. Measurement results from 90nm
CMOS test chips are described in Section IV.

I. INTRODUCTION
Both the low power supply voltage (VDD) and multi core
are the recent trend for power efficient processors. Manyworks have been carried out on the subthreshold logic circuits[1-4] and homogeneous multi-core LSI’s (e.g. 80 cores [5] and64 cores [6]). The subthreshold logic circuits are energy
efficient [1,4], while they are very slow. Therefore, an ultra
parallel processing with homogeneous subthreshold multicores may be a promising approach for the energy efficient
processors with the practical processing speed.
The increasing test cost proportional to the number ofcores, however, is among the most serious issues facing themulti-core LSI’s. Fig. 1 shows the conventional test method ofthe homogeneous multi-core LSI’s. The outputs from n cores
are compared with expected vectors, and pass or fail are
determined. The increasing quantity of the outputs with thenumber of cores raises the test cost.
Meanwhile, the minimum power supply voltage (VDDmin)of logic circuits is determined by the function errors of logic

II. PROPOSED TEACHER-STUDENT SWAP TEST METHOD
Fig. 2 shows a proposed TSS test method of thehomogeneous multi-core LSI’s. Every core is paired with theneighboring cores and the pair is called “teacher and studentpair” in this paper. A teacher core and a student core areswappable and they test each other. The teacher core is afunction guaranteed core and operates as an expected vector
generator for the student core, which eliminates the need forthe input of the expected vectors from the tester. The student
core is the circuits under test. The outputs from the student
core are compared with the expected vectors from the teacher
core, and only the pass or fail signals are reported to the tester.
Therefore, the quantity of the outputs from the chip is muchsmaller than that in Fig. 1, thus reducing the test cost for thePassorFailHomogeneous multi-core LSI
Testvectors

Core Core01

Homogeneous multi-core LSI
Testvectors

CoreCore Core01CoreCore Core
23
CoreCorenCore Core
23

Teacher and student pairCoreCoren

Teacher core
= Expectedvector
generator

Outputs=Pass or FailSwappable

Expected vectors

Fig. 2. proposed TSS test method of the homogeneous multi-core LSI’s.

Fig. 1. The conventional test method of the homogeneous multi-core LSI’s.

978-1-4244-2018-6/08/$25.00 ©2008 IEEE

Student core
= Circuits
Under
test

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Step1: Initial test

VDDH

VDDL

VDDL VDDH VDDL VDDH

VDDH

VDDL

Test0

Test1
LFSR

VDD
memoryVDD
memoryCore 0Core 0Teacher

Core 1Teacher

Core 1
D-FF

D-FF

32bit

32bit

16bit Full adder

Error
check
Pass

16bit Full adder

17bit

17bit

D-FF

Fail
Disable Core 0 &1

D-FF

17bit

17bit

Level Shifter

Level Shifter

XOR

Step2: Test of Core 0
VDDH V
VDDHV
DDL

DDL

Core 0Student

Core 1Teacher

Step3: Test of Core 1
VDDH VVDDHVDDL

Pass or FailDDLCore 0TeacherFig. 5. Schematic of the fabricated teacher and student pair with dual VDD.

operates with VDDH. Step3 is the swapped version of Step2 andconcludes the TSS test.

Core 1StudentError
check

Error
check

PassÎVDD(core0)=VDDLFail ÎVDD(core0)=VDDHPassÎVDD(core1)=VDDLFail ÎVDD(core1)=VDDH

III. CHIP IMPLEMENTATION OF HOMOGENEOUS MULTI-CORE
LSI WITH TEACHER-STUDENT SWAP TEST METHOD

FinishFig. 3. A flow chart of TSS test.

multi-core LSI’s.
Fig. 3 shows a flow chart of TSS test. In order to achieve
the fine grain VDD tuning for the ultra low VDD homogeneous
multi-core LSI’s, dual VDD (a high VDD (VDDH) and a low VDD(VDDL)) is adopted. VDDH is the minimum supply voltage
where all cores operate correctly and VDDL is the supply
voltage where some of the cores fail to operate. Thus the corewith VDDH is the teacher core and the core with VDDL is thestudent core. As shown in Fig. 3, in the initial test (Step1),
both core 0 and 1 are teacher-mode with VDDH to find theinitial failure of the cores. When the initial failure is found,both core 0 and 1 are disabled and can be replaced withredundant cores. In the test of core 0 (Step2), the core 0 with
VDDL is the student mode and the core 1 with VDDH is theteacher mode. When the test is passed, the core 0 operates
with VDDL. In contrast, when the test is failed, the core 0y

680µm

1mm
8x8 coresx(b)One pair (= 2 cores)(a)Fig. 4. (a) Layout and (b) micrograph of a homogeneous 64 core LSI withthe TSS test method in 90 nm CMOS.

In order to demonstrate the TSS test method with dual VDD
for the ultra low VDD homogeneous multi-core LSI’s, testchips has been designed and fabricated. Figs. 4 (a) and (b)show the layout and the micrograph of a homogeneous 64 core
LSI with the TSS test method in 90 nm CMOS respectively.
The core area is 1.0mm×0.68mm. The 64 core LSI has 32
teacher and student pairs. The two cores in a pair havesymmetrical layouts.
Fig. 5 shows the schematic of the fabricated teacher andstudent pair with dual VDD. Each core includes the 16 bit
ripple carry adder and D-flip-flops. In the cores, the primitive
cells provided by the foundry are used and are not optimized
for low VDD operations [1,8]. A 32 bit LFSR generates pseudo
random numbers, and the 17 bit adder outputs from core 0 and
1 are compared. The pass or fail signals are stored in a VDD
memory. VDDH or VDDL is selected by pMOSFET’s. The all
circuits except the cores and I/O’s use a separate VDD.
IV. MEASUREMENT RESULTS
VDDL distributions within 64 cores are measured by theTSS test method. The power reduction by the dual VDD is also
discussed.
A. VDDL Distributions
Fig. 6 shows the measured VDDL dependence of thenumber of error cores in 64 cores of a chip. The clock
frequency is varied from 10kHz to 30MHz. VDDH is defined as
VDD where the first error core is observed. The VDDL
distributions are divided into 2 modes (a delay error mode
(VDD > 0.3V) and a function error mode (VDD < 0.3V)). At30MHz and 15MHz, the VDDL distributions are narrow anddetermined by the classical timing error of the logic gates,
which is the delay error mode. In contrast, at 1MHz and10kHz, the VDDL distributions are broad and do not depend on
the clock frequency. The distributions are determined by thefunction error of the logic gates due to device variations[7],8-5-2138

24VDDH1680150

200

250

300

350

400

VDDL(mV)

B. Power Reduction by Dual VDD
Fig. 8 (a) shows the VDDL dependence of the power and thenumber of error cores in 64 cores of a chip at 4 different clock
frequencies. The power is simulated by SPICE based on themeasured number of error cores. The leakage power accounts
VDDL=370mV
370mV
372mV
374mV
374mV
376mV
378mV
378mV
380mV
382mV
382mV
384mV
386mV
386mV
388mV
390mV
390mV

8
76543

VDDH=388mV

21234567654

Power reduction by dual VDD (%)

VDDH=280mV

2678200

250

300

350

VDDL(mV)

400

00-515MHz30MHz

5MHz-10-15-20f=10kHz-25-30
150

200

250

300

350

VDDL(mV)

4008(b)Fig. 7. Measured VDDL distribution map on 64 cores (a) at 30MHz (delayerror mode) and (b) 10kHz (function error mode).

Chip1
Chip2
Chip3
Chip4
Chip556484032

f=30MHz(Delay error)

24
16810kHz(Functionerror)

0150

15166434

24

5Number of error cores

7332

108824015for 48% and 99.9% of the total power shown in Fig. 8 at30MHz and 10kHz respectively. By using the proposed TSS
test method, VDDH is assigned to the error cores and VDDL isassigned to the non-error cores automatically. When all the 64
cores have the errors, all cores operate at VDDH, which is equal
to the all VDDH approach. Therefore, the power is minimized
by optimizing VDDL. Fig. 8 (b) shows the VDDL dependence ofthe power reduction by the dual VDD at 4 different clock
frequencies. At 30MHz and 15MHz (delay error mode), thepower reduction is only 3%, because the VDDL distributions
are narrow. In contrast, at 10kHz (function error mode), thepower reduction is 27%, because the VDDL distribution isbroad.
Finally, the die-to-die variations of the measured VDDL
distribution are discussed. Fig. 9 shows the measured VDDL
dependence of the number of error cores in 64 cores of 5 chips

VDDL=170mV
170mV
180mV
190mV
190mV
200mV
210mV
210mV
220mV
230mV
230mV
240mV
250mV
250mV
260mV
270mV
270mV
280mV
290mV
290mV

1x48
20(b)
Fig. 8. VDDL dependence of (a) the power and the number of error cores in64 cores of a chip and (b) the power reduction by the dual VDD at 4 different
clock frequencies.

(a)y5625(a)which is the function error mode. At 5MHz and 2MHz, boththe delay error mode and the function error mode are mixed.
Figs. 7 (a) and (b) show the measured VDDL distribution
map on 64 cores at 30MHz (delay error mode) and 10kHz(function error mode) respectively. The x- and y-axis in Fig. 7corresponds to that in Fig. 4 (a). The maximum VDDL is388mV and the minimum VDDL is 370mV at 30MHz. Themaximum VDDL is 178mV and the minimum VDDL is 280mVat 10kHz. The VDDL distribution in Fig. 7 (a) has both therandom and the systematic (y-axis direction) component. Thesystematic component will derive from the on-chip IR-drop. Incontrast, the VDDL distribution in Fig. 7 (b) has only therandom component. The peak-to-peak variation of VDDL(=102mV) is larger than that (=18mV) in Fig. 7 (a), because
the low VDD exposes the effect of the device variations on thecircuit variations.

1x64

0150

Fig. 6. Measured VDDL dependence of the number of error cores in 64 coresof a chip. The clock frequency is varied from 10kHz to 30MHz.

y30MHzNumber of error cores

15MHz5MHzz
1 MH322MHzz
40

15MHz30

f=30MHz48

5MHz

f=10kHz

Simulated power (µW)

56

H
10k

Number of error cores

64

200

250

300

350

400

VDDL(mV)

Fig. 9. Measured VDDL dependence of the number of error cores in 64 coresof 5 chips at 10kHz and 30MHz clock.

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at 10kHz and 30MHz clock signals. Chip1 is the same as thatin Fig. 6. At both 10kHz and 30MHz, the die-to-die variationsof the VDDL distribution are observed. An interesting result isthat the delay error mode and the function error mode are notcorrelated, because their mechanisms are different. For
example, Chip2 has the highest VDDL at 30MHz, however,Chip3 or Chip5 has the highest VDDL at 10kHz.
Fig. 10 (a) shows the VDDL dependence of the simulated
power of 5 chips at 10kHz clock. Fig. 10 (b) shows the VDDL
dependence of the power reduction by the dual VDD. The
power reduction is from 18% to 48% among 5 chips, and thehigh VDDL chip (Chip3) achieves the largest power reduction.
Fig. 10 (c) shows the VDDL /VDDH dependence of the power
reduction by the dual VDD. In the conventional processors, theoptimum VDDL /VDDH to achieve the minimum power is 0.7[9].
In contrast, at 0.2 - 0.4V and 10kHz (function error mode), theoptimum VDDL /VDDH is from 66% to 82% among 5 chips. In
order to manage the large die-to-die variations at low VDD, thefine grain dual VDD with TSS test method is a promising
approach without increasing the test cost.

Simulated power (µW)

15ACKNOWLEDGMENTS
This work is partially supported by STARC. The VLSI
chips were fabricated through the chip fabrication program ofVLSI Design and Education Center (VDEC), the University ofTokyo, with the collaboration by STARC, Fujitsu Limited,
Matsushita Electric Industrial Company Limited., NECElectronics Corporation, Renesas Technology Corporation,and Toshiba Corporation.
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