3D Stacked Buck Converter with 15μm Thick SpiralInductor on Silicon Interposer for Fine-Grain
Power-Supply Voltage Control in SiP’s
Koichi Ishida 1, Koichi Takemura 2, Kazuhiro. Baba 2, Makoto Takamiya 1, and Takayasu Sakurai 1
12

University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, Japan

Association of Super-Advanced Electronics Technologies (ASET), Tokyo, Japan

Abstract-This paper proposes a 3D stacked buck converterwith a 15µm thick spiral inductor on a silicon Interposer, which
is suitable for fine-grain power-supply voltage control in SiP’s.
Our newly developed silicon interposer technology realizes afine-pitch design rule (Line/Space=20µm/20µm, via hole diameter=30um) at the metal thickness of 15µm as well as conventional
interposers with 5µm metal thickness. The measurement resultshows that the 15µm thick inductor improves the power
efficiency of the buck converter by 12% at the output current of
100mA compared with that by the conventional 5-µm thickinductor.

I. INTRODUCTIONSpace-domain fine-grain voltage engineering is a promising
method for low-power high-performance VLSI circuit designwith advanced CMOS technologies [1]. To realize fine-grain
VDD implementation, distributed power supplies with on-chipbuck converters are required as shown in Fig. 1.
Conventional buck converters employ either off-chip
discrete inductors or on-chip inductors. Off-chip inductors
have low parasitic resistance. However, interconnects between
LSI and the inductor tend to be long, and therefore, its
parasitic capacitance and resistance are issues for thefine-grain power supply voltage (VDD) implementation. On theother hand, on-chip inductors have high parasitic resistanceand occupy area of expensive LSI chip. A high-efficiency
buck converter using on-chip inductor has been proposed [2].
However, three metal layers from the top are used for theon-chip inductor to reduce its parasitic resistance. It is notreasonable to waste several metal layers for on-chip inductors
for the distributed power supplies.
Another candidate in which inductors are implemented is asilicon interposer technology. Its design rule is similar to thatof typical pad layouts on silicon VLSI chip. In addition,
recently developed SrTiO3 thin film decoupling capacitors insilicon interposer [3] can be used as an output filter of a buckconverter. Silicon interposer, therefore, has possibility to add
both inductors and capacitors to on-chip distributed buck

Fig. 1. Distributed power supply for the fine grain VDD in SiP’s.

converters with reasonable parasitic capacitance andresistance. Therefore, we propose a 3D stacked buck converter
using a 15μm thick spiral inductor on a newly developed
silicon interposer for fine-grain power-supply voltage control
in SiP’s as shown in Fig. 2.
We introduce the structure of the proposed 3D stacked buckconverter and details of the silicon interposer with 15μm thickmetal layers in Section II. Experimental results are describedand discussed In Section III. And finally the conclusions aregiven in Section IV.
II. PROPOSED 3D STACKED BUCK CONVERTER
A. Structure of the 3D Stacked Buck Converter
Fig. 2 shows the proposed 3D stacked buck converter witha spiral inductor on a silicon interposer. The buck converter
consists of a CMOS LSI circuit and a silicon interposer. The
CMOS LSI includes active components such as a PWM
controller, a CMOS switch, and a driver. Passive componentsof the buck converter, a spiral inductor and a
metal-insulator-metal (MIM) capacitor, are implemented on
the silicon interposer. The CMOS LSI circuit and the siliconinterposer are stacked and connected by metal bumps with asmall parasitic capacitance and resistance.
In order to improve power efficiency of buck converter,parasitic resistance of a spiral inductor, Ri in Fig. 2 should bereduced. Since the parasitic resistance is inversely
proportional to the thickness of the metal layers, 15μm thickmetal layers are adopted while conventional siliconinterposers typically employ around 5μm metal thickness. Theinductance, Li and parasitic resistance, Ri of a spiral inductor
as shown in Fig. 3 can be estimated analytically by following
formulas [4]Li |d avg

U{

P 0 n 2 d avg c1 ª § c 2 ·2º«ln¨¨ ¸¸  c3 U  c 4 U » ,2¬ ©U¹¼

d out  d in,
2d out  d in,
d out  d in

(1)

(2)

Fig. 2. Proposed 3D stacked buck converter with a spiral inductor on silicon

(3)

dout

Where C1=1.27, C2=2.07, C3=0.18, C4=0.13, n is number ofturns.
Power loss by inductor, PIND is given by
VIN D(1  D) § 2 I R2 · ,¨ I L  ¸¸
2 fLi / Ri I R ¨©
3 ¹(4)

where VIN is input voltage, D is duty ratio, f is switchingfrequency, IR is the ripple current, and IL is the load current [5].
The ratio of Li / Ri which is determined by the thickness anddesign rules of metal lyers, and is the most important metrics
to discuss inductor performance. Fig. 4 shows the ratio of Li /Ri dependence of power efficiency of buck converter at D=0.4,
VOUT=0.1V, POUT=0.4W calculated by using equations in [5].
As the ratio of Li / Ri increases, the power efficiency increase.
Therefore it is important that increasing metal thickness(t=15μm) and realizing fine pitch design rule (L/S=20/20μm)
at the same time to realize high Li / Ri ratio.
B. Silicon Interposer with 15µm Thick Metal Layers
To obtain higher inductance performance, our newly
developed silicon interposer technology realizes a fine-pitch
design rule (Line/Space=20μm/20μm, via hole diameter=30μm) at the metal thickness of15μm as well as conventional
interposers with 5μm metal thickness.
Fig. 5 shows the cross-section of the proposed siliconinterposer. MIM capacitors (Ru/SrTiO3/Ru thin film
capacitors) [3] are formed on the silicon substrate. The
capacitance density is around 12nF/mm2. 15μm thick metal
layers are formed with electroplated copper on the MIM

StL
Fig. 3. Planar spiral inductor and formulas to estimate Li and Ri.

100

Efficiency 㱓 [%]PIND

din9590

D=0.4
VOUT=1V
POUT=0.4WThis work
t=15µm
L/S=20/20µm

t=15µm858075

L/S=180/20µm

t=5µm

L/S=150/50µm

706510

L/S=100/100µm
1001000

Li / Ri [ nH/㱅]Fig. 4. The ratio of Li / Ri dependence of power efficiency of buck converter
at D=0.4, VOUT=0.1V, POUT=0.4W.

capacitors. Totally three metal layers including pad metal areavailable. By increasing metal thickness, photosensitive resin
thickness should be thicker. In this work, the thickness
between two metal layers is around 20μm The fact makes itdifficult to form cavities because of degradation of sensitivity
and under exposing at the bottom of the resin as shown in Fig.
6. To solve these problems in photolithography process, a
newly
developed
chemicallyamplified,positive
photosensitive resin is used for the proposed silicon interposer.
Fig. 7. shows photograph of the proposed interposer.

Electroplated-Cu(15µm)
Photo-sensitive resin(20µm)

III. MEASUREMENT RESULTS AND DISCUSSION
To demonstrate the effectiveness of the 15μm thick spiralinductor, a test CMOS LSI chip and interposers are fabricated.
Fig. 8 shows photographs of the CMOS LSI chip and thesilicon interposer. A CMOS switch, which is a main
component of the buck converter, is implemented in a
0.18-μm CMOS process. For the comparison of theperformance degradation by the parasitic resistance of thespiral inductor, Ri, we fabricated both 5 and 15μm metal
thickness interposers. We designed a 2000 × 2000-μm2, 6-turn,square spiral inductor. The calculated inductance and RS are
80nH and 0.6 with 15μm thickness, respectively. The MIM
capacitor is implemented underneath the spiral inductor. Themeasured Buck converter circuit is also shown in Fig.2.
36-MHz, non-overlap clocks are applied to the switch and
VOUT is monitored by an active current source, IOUT. VIN andVOUT are 1.8V and 1.0V, respectively.
Fig. 9 shows measured power efficiency vs. IOUT of thebuck converters. The peak power efficiency of the 15μm thickinductor achieves 77% at IOUT of 70mA, while that of the 5μm
thick inductor is only 66% at IOUT of 60mA. As the increase ofIOUT, the difference of the efficiency tends to increase because
the power consumption by Ri is dominant. As the result, thenewly developed 15μm thick inductor improves the power
efficiency by 12% at IOUT of 100mA compared with that of theconventional 5μm thick inductor.

Silicon substrate
MIM capacitor

p-TEOS(1µm)

Minimum pad pitch=150µm
Line/Space=20µm/20µm
Via hole diameter =30µm

SiO2(300nm)

Fig. 5. Cross-section of the proposed silicon interposer with 15-μm thickmetal layers.
Easy to form seed layer

Photo resist

Positive

Photo-sensitive resin
Soluble area

Negative

Photo-sensitive resin

Under exposing
Not curedFig. 6. Photolithography process issue with 20μm thick photo-sensitive resin.

A 3D stacked buck converter with a 15μm thick spiralinductor on a silicon Interposer has been proposed. Our newly
developed silicon interposer technology realizes a fine-pitch
design rule at the metal thickness of 15μm as well as
conventional interposers with 5μm metal thickness. The
measurement result shows that the 15μm thick inductor
improves the power efficiency of the buck converter by 12%
at the output current of 100mA compared with that by theconventional 5μm thick inductor. The buck converter realizes
fine-grain power-supply voltage control in SiP’s.

7mm

IV. Conclusions

7mm
Fig. 7. Photograph of the proposed silicon interposer with 15-μm thick metallayers.

0.18µm CMOS LSI

vol.34, no.10, pp.1419-1424, Oct. 1999.

Silicon interposer[5] G.Schrom, P.Hazucha, F.Paillet, D.S.Gardner, S.T.Moon, and T.Karnik,
Thickness:
5µm or 15µm

2000µm

560µm

370µm

Spiral inductor

2000µm

MIM capacitor

VIN=1.8V
80nH

Non-overlap
clock(36MHz)Ri

VOUT= 1V
0.1µF

IOUT

Fig. 8. Photographs of the CMOS LSI chip and the siliconinterposer and measurement circuit.

Power efficiency [%]100
VIN=1.8V, VOUT=1.0V, 36MHz90

t=15µm807060

t=5µm

5040

Improved by 12%@100mA

3020100020406080

100120

Output current [mA]Fig. 9. Measured power efficiency vs. IOUT of the buck converters.

ACKNOWLEDGMENT
This work is supported by NEDO (New Energy andIndustrial
TechnologyDevelopmentOrganization)
entrustment project.
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VLSI Packaging Workshop, pp.127-130, Dec. 2008.
[4] S. Mohan, M. Hershenson, S. Boyd, and T. Lee, "Simple Accurate
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