2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD) | 978-1-6654-2201-7/22/$31.00 ©2022 IEEE | DOI: 10.1109/ISPSD49238.2022.9813669

Large Current Output Digital Gate Driver Using
Half-Bridge Digital-to-Analog Converter IC andTwo Power MOSFETs
Kohei Horii1, Katsuhiro Hata1, Ruizhi Wang1, Wataru Saito2, and Makoto Takamiya1
1
The University of Tokyo, Tokyo, Japan
2
Kyushu University, Fukuoka, Japan

Abstract—An 8-bit digital gate driver (DGD) using a halfbridge digital-to-analog converter (HB DAC) IC and two powerMOSFETs is proposed to enable the output voltage swing of ± 15
V and the large gate current up to 58 A for a 6500 V, 1000 A IGBTmodule. In the turn-on measurements of IGBT at 3000 V and 1000
A, compared with the conventional single-step gate driving, theproposed active gate driving using DGD reduces the switching loss
from 6.9 J to 4.8 J by 30 % at the same current overshoot of 1.3
kA and reduces the current overshoot from 1560 A to 1330 A by
15 % at the same switching loss of 5 J, which clearly shows theadvantage of DGD for the 6500 V, 1000 A IGBT module. This
paper is the first to demonstrate the advantages of DGD in thehigh-voltage, large-current IGBT modules.
Keywords—gate driver, IGBT, switching loss, high voltage

I. INTRODUCTION
High-voltage, large-current IGBT modules (e.g. ratings of6500 V, 1000 A) are used in many social infrastructure fields
including high-voltage DC transmission systems and train
traction systems [1]. In addition to improving IGBTs themselves,gate driving technologies can be used to reduce the loss ofIGBTs. Recently, many papers have been published on thesimultaneous reduction of both switching loss (ELOSS) andswitching noise by active gate waveform control using digital
gate drivers (DGDs) [2-8]. Conventional DGDs, however, aredifficult to apply to the 6500 V, 1000 A IGBT modules, because
the modules require DGD with (1) the output voltage swing(VSWING) of ± 15 V to prevent a false turn-on and (2) the gate
current (IG) of up to around 20 A because of the large gate
capacitance. For example, VSWING is 3.3 V [3], 5 V [4–5, 7], 15V [2], 18 V [6] and 20 V [8], and the maximum IG is between 5
A [2, 4] and 42 A [5].
To solve the problems, in this paper, an 8-bit DGD using ahalf-bridge digital-to-analog converter (HB DAC) IC and twopower MOSFETs is proposed to enable VSWING of ± 15 V andlarge IG up to 58 A for the 6500 V, 1000 A IGBT modules. 30 %reduction of ELOSS and 15 % reduction of the current overshoot(IOVERSHOOT) compared with the conventional single-step gate
driving in the turn-on of the 6500 V, 1000 A IGBT module at
3000 V and 1000 A are experimentally shown. This paper is thefirst to demonstrate the advantages of DGD in the high-voltage,large-current IGBT modules.

978-1-6654-2201-7/22/$31.00 ©2022 IEEE

II. DESIGN OF DIGITAL GATE DRIVER USING HB DAC IC AND
TWO POWER MOSFETS
Figs. 1 to 3 show a circuit schematic of the proposed DGD
including HB DAC IC and two power MOSFETs (Q1 and Q2 :BSC094N06LS5, 60 V, 47 A), a block diagram of the proposed
HB DAC IC, and a timing chart of DGD, respectively. DGD isa current-source gate driver. The novelty of this work is thatpower MOSFETs are used as the output stage of the gate driverto achieve large IG, and DGD operation is achieved by digitallycontrolling the gate amplitude (VGSH and VGSL) of the power
MOSFETs operating in the saturation region instead of the linear
region using the proposed HB DAC IC to achieve the currentsource gate driver. As shown in Fig. 2, HB DAC IC includes twoDACs operating with different power supply rails, shift registers
for serial inputs to reduce the number of input pins, and an edge
detector to generate pulse signals from externally supplied“Timing” signal. HB DAC IC does not include the drivertransistors. If all the functions are integrated into a single IC, thechip size will be huge and the cost will be high. By controlling
the gate voltage of Q1 (VGSH) with a 16-bit input DAC (Fig. 2),
IG can be digitally varied four times at turn-on (Fig. 3). The four
periods from t1 to t4 are determined by “Timing” signal, and t1to t4 can be changed independently. The same is true for turnoff.
Digital gate driver (DGD)

IG Saturation
regionHalf-bridge digital-to-analog
converter (HB DAC) ICPowerMOSFETs
Q1
VDD3

VGSH
VDD1

VDS of Q1

IGBT

DAC

IG

VGSH

VGE
Q2
VDD4

VDD2

DAC
VGSL

Fig. 1. Circuit schematic of proposed digital gate driver (DGD) including HB
DAC IC and two power MOSFETs.

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Half-bridge digital-to-analog
converter (HB DAC) ICH_nPMOS [7:0]
H_nNMOS [7:0]

EnableSerial-in
parallel-out
shiftregister

Scan In
Scan CLK128

VDD3DAC
VGSH

8Parallel-inserial-out
shift registers
L_nPMOS [7:0]
L_nNMOS [7:0]

Edgedetector

TimingEdge detector

81 mm

IN

Shift registers

High-side
floating VSS
8DAC

VDD4DAC82.5 mm

VGSL

Fig. 5. Die micrograph of HB DAC IC.

Low-side VSS

Front

Back

Fig. 2. Block diagram of proposed half-bridge digital-to-analog converter (HBDAC) IC.

On

OffTiming
VGSH
VGSLIGHB DAC IC0V
VDD448 mm0V

Fig. 6. Photo of PCB of DGD.

0A

IN
H_nPMOSVGE 0 V

−VDD2

H_nNMOSt1 t2t3t4t5t6 t7 t8 t9t10

t1

H_nPMOS [7:0]

RP

H_nNMOS [7:0]

RN VGSH

VDD38WP

16WP

32WP

64WP

128WP

VGSH

WN

2WN

4WN

8WN

16WN

32WN

(a)

64WN

128WN

n0255

m0IN
H_nPMOS

Off255VDD3RNV
RP+RN DD30V

Time(b)Fig. 4. 16-bit input DAC for Q1. (a) Circuit schematic. (b) Equivalent circuit.

Figs. 4 (a) and (b) show a circuit schematic and an equivalentcircuit of the 16-bit input DAC for Q1, respectively. This DAC
has a similar circuit configuration to DGD with binary weighted
gate widths (WP, 2WP, 4WP, 8WP, 16WP, 32WP, 64WP, 128WP) in
the output stage [4], however, the method of operation isdifferent. VGSH can be digitally controlled by H_nPMOS [7:0] and
H_nNMOS [7:0] on the principle of a shunt regulator, where someof the eight pMOSFETs and some of the eight nMOSFETs inFig. 4 (a) are turned on. This DAC has 16-bit inputs, however,for simplicity, 8-bit digital signals H_nNMOS [7:0] are fixed and8-bit digital signals H_nPMOS [7:0] are varied in this paper. VGSH
can be varied in 256 levels depending on H_nPMOS [7:0], which
is defined as H_nPMOS, where H_nPMOS is an integer between 0and 255. Similarly, H_nNMOS is an integer between 0 and 255.
Fig. 5 shows a die micrograph of HB DAC IC fabricatedwith 180-nm BCD process. The die size is 2.5 mm by 1.0 mm.
Fig. 6 shows a photo of PCB of DGD. HB DAC IC is mounted
on the surface of the PCB, and Q1 and Q2 are mounted on theback of the PCB.

Onn10

H_nNMOS 255

0mV

VGSH DD3

VGSH DD3IG

IG0V

0A

0A

Q1(a)

Q1

VGSH

On0V

VDD34WP

Off255

VFig. 3. Timing chart of DGD.

2WP

Q2

VDD3VDD1WP

Q137 mm

IN

1040 ns 560 ns(b)Fig. 7. Timing charts for turn-on measurement. (a) Conventional single-step gatedriving (SGD). (b) Proposed active gate driving (AGD).

III. MEASURED RESULTS
In this paper, only IOVERSHOOT at turn-on discussed and thecollector-emitter voltage (VCE) overshoot at turn-off is notdiscussed, because IOVERSHOOT is large, while the voltage
overshoot is small, being less than 500 V.
Figs. 7 (a) and (b) show timing charts for the turn-on
measurement of the conventional single-step gate driving (SGD)
and the proposed active gate driving (AGD), respectively. AGD
is based on the stop-and-go gate driving [9]. In AGD, only twoperiods (t1 and t2) out of four periods (t1 to t4) in Fig. 3 are usedfor simplicity. n is varied in SGD and n1 is varied in AGD, wheren and n1 are integers between 0 and 255. m is common to SGDand AGD, where m is 60 or 100 in this paper.
Fig. 8 shows the measured n dependence VGSH in SGD todemonstrate the successful operation of 8-bit DAC at VDD3 =VDD4 = 3.5 V and 4 V and m = 60 and 100. VGSH is monotonicallyincreasing with n, although DAC is nonlinear. The maximum
output current of DAC is 100 mA. Fig. 9 shows the measured ndependence IG in SGD to demonstrate the successful operationof 8-bit DGD at VDD3 = VDD4 = 3.5 V and 4 V and m = 60 and100. To investigate the performance of DGD itself, a 100 F
capacitor is connected to the output of DGD and IG is measured.

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4m = 60

3.5

VGSH [V]32.5m = 100

21.5
10.50Digitalgate driver

VDD3 = VDD4 = 4 V
VDD3 = VDD4 = 3.5 V050100150n200250Fig. 8. Measured n dependence VGSH in SGD to demonstrate operation of 8-bit
DAC.

60

VDD3 = VDD4 = 4 V50

VDD3 = VDD4 = 3.5 V
VDD1 = VDD2 = 15 V40IG [A]Q430m = 60

2010m = 1000050

100150n200250Fig. 9. Measured n dependence IG in SGD to demonstrate operation of 8-bit
DGD.

IG is monotonically increasing with n, although it is nonlinear.
The maximum IG is 58 A.

Fig. 11. Measurement setup of double pulse test.

Fig. 13 shows corresponding measured waveforms in Fig. 12.
Fig. 13 (a) shows the measured waveforms of SGD at n = 175with the smallest IG, achieving the smallest IOVERSHOOT and thelargest ELOSS. In contrast, Fig. 13 (b) shows the measured
waveforms of SGD at n = 255 with the largest IG, achieving thesmallest ELOSS and the largest IOVERSHOOT. The maximum
measured IG is 14 A. Fig. 13 (d) shows the measured waveformsof the proposed AGD. Figs. 13 (c) and (e) show the measured
waveforms of SGD with the same IOVERSHOOT and ELOSS as AGD,respectively. In Fig. 13 (d), AGD achieves low ELOSS andIOVERSHOOT by setting IG to zero just before the timing ofIOVERSHOOT. In Fig. 13 (d), the maximum measured IG is 10 A.
Table I shows a comparison table of DGDs. The proposed
DGD using HB DAC IC and two power MOSFETs achieves thelargest VSWING of 30 V and the largest IG of 58 A in DGDs. Thispaper is the first to demonstrate the advantages of DGD in thehigh-voltage, large-current IGBT modules.

Figs. 10 and 11 show a circuit schematic and a measurement
setup of the double pulse test using DGD and two IGBT modules(Q3 and Q4 : CM1000HG-130XA, 6500 V, 1000 A) at 3000 V
and 1000 A, respectively. Fig. 12 shows the measured ELOSS vs.
IOVERSHOOT at VDD3 = VDD4 = 3.5 V and m = 100. The black line
shows the trade-off curve of the conventional SGD (Fig. 7 (a))
with varied n from 175 to 255. The red star shows the proposed
AGD (Fig. 7 (b)) at n1 = 223. Compared with SGD, the proposed
AGD reduces ELOSS from 6.9 J to 4.8 J by 30 % at the sameIOVERSHOOT of 1.3 kA and reduces IOVERSHOOT from 1560 A to1330 A by 15 % at the same ELOSS of 5 J, which clearly shows
the advantage of DGD for the 6500 V, 1000 A IGBT module.

12n = 175 (Fig. 13 (a))

10ELOSS [J]8n = 177 (Fig. 13 (c))

Digitalgatedriver

1000 A(Fig. 13 (d)) −15%IC
Q4

DGD

00500

1000

1500

2000

2500

3000

IOVERSHOOT [A]

VCE

VGE

n = 255(Fig. 13 (b))

m = 100
VDD1 = VDD2 = 15 V
VDD3 = VDD4 = 3.5 V

23000 V

IGn = 180 (Fig. 13 (e))

Proposed
4Q3Conventional−30%

6Fig. 12. Measured ELOSS vs. IOVERSHOOT of conventional SGD and proposed AGD.

Fig. 10. Circuit schematic of double pulse test.

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ELOSS : 10.4 J
2 μs/div

VCE: 500 V/div

2 μs/div
14 A(max)

IC: 500 A/div

IC: 500 A/div

VGSH: 2 V/div
IG: 4 A/div

VGSH: 2 V/div

0

VGE: 20 V/div IG: 4 A/div

VGE: 20 V/div
255

H_nPMOSH_nPMOS0175
0ACKNOWLEDGMENTTime(b)ELOSS : 6.9 J

ELOSS : 4.8 J

VCE: 500 V/div

VCE: 500 V/div2 μs/div

2 μs/div

IC: 500 A/div

1770Time(c)REFERENCES[1]

IG: 4 A/div

0

H_nPMOSH_nPMOSVGSH: 2 V/div

IG: 4 A/div

VGE: 20 V/div

The authors would like to thank Kenji Hatori, Kazuto
Mikami, and Koji Tanaka of Mitsubishi Electric Corporation for
the technical discussion and the support for measurements. Thiswork was partially supported by NEDO (JPNP21009).

IC: 500 A/div

10 A(max)

VGSH: 2 V/div

08-bit DGD using HB DAC IC and two power MOSFETs isproposed to enable VSWING of ± 15 V and large IG up to 58 A forthe 6500 V, 1000 A IGBT modules. In the turn-on
measurements of IGBT at 3000 V and 1000 A, compared withSGD, the proposed AGD reduces ELOSS from 6.9 J to 4.8 J by
30 % at the same IOVERSHOOT of 1.3 kA and reduces IOVERSHOOT
from 1560 A to 1330 A by 15 % at the same ELOSS of 5 J, whichclearly shows the advantage of DGD for the 6500 V, 1000 A
IGBT module.

0Time(a)IV. CONCLUSIONSELOSS : 3.1 J

VCE: 500 V/div

VGE: 20 V/div
255

[2]

223001040 ns 560 ns(d)

Time

[3]

ELOSS : 4.9 J
VCE: 500 V/div
2 μs/div[4]
IC: 500 A/div

VGSH: 2 V/div

H_nPMOS0

VGE: 20 V/div[5]

IG: 4 A/div[6]

1800Time(e)Fig. 13. Measured waveforms in Fig. 12. (a) Conventional SGD at n = 175. (b)Conventional SGD at n = 255. (c) Conventional SGD at n = 177. (d) Proposed
AGD. (e) Conventional SGD at n = 180.

[7]

Table I. Comparison table of DGDs.
TIA’17 [2]Target powerdeviceProcess

Chip area
Output voltage
swing

ISPSD’20[3]

ISPSD’21[4]TPEL’21 [5]Thiswork

Si IGBT &SiC MOSFET
180 nm
BCD
6.25 mm2GaN FETGaN FETGaN FET

Si IGBT180 nmBCD
1.97 mm2180 nm
BCD
4.32 mm2180 nm HVCMOS
5.0 mm2180 nm
BCD
2.5 mm2

15 V

3.3 V

5V

5V

30 V

Levels of IG

6 bit

7 bit

6 bit

Max. IG

5A

3.3 V / 0.5 Ω= 6.6 A

5A

Functions
integrated into IC

1 driver1 driver1 driver8 bit (coarse),
6 bit (fine)
5 V / 0.12 Ω= 42 A
1 driver[8][9]

V. Escrouzailles, E. Rabasse and J. Coiret, "Improved performances of6,5kV IGBT module by using current source gate driver," in Proc. 11th
International Conference on Integrated Power Electronics Systems, Mar.
2020, pp. 1-6.
K. Miyazaki, S. Abe, M. Tsukuda, I. Omura, K. Wada, M. Takamiya, andT. Sakurai, “General-purpose clocked gate driver IC with programmable63-level drivability to optimize overshoot and energy loss in switching bya simulated annealing algorithm,” IEEE Trans. Ind. Appl., vol.53, no.3,pp. 2350-2357, May/June 2017.
W. J. Zhang, J. Yu, Y. Leng, W. T. Cui, G. Q. Deng, and W. T. Ng, “Asegmented gate driver for E-mode GaN HEMTs with simple driving
strength pattern control,” in Proc. IEEE Int. Symp. Power Semicond.
Devices ICs, Sep. 2020, pp. 102-105.
R. Katada, K. Hata, Y. Yamauchi, T. -W. Wang, R. Morikawa, C. -H. Wu,
T. Sai, P. -H. Chen, and M. Takamiya, "5 V, 300 MSa/s, 6-bit digital gate
driver IC for GaN achieving 69 % reduction of switching loss and 60 %reduction of current overshoot," in Proc. IEEE Int. Symp. PowerSemicond. Devices ICs, May 2021, pp. 55-58.
D. Liu, H. C. P. Dymond, S. J. Hollis, J. Wang, N. McNeill, D. Pamunuwa,and B. H. Stark, “Full custom design of an arbitrary waveform gate driverwith 10-GHz waypoint rates for GaN FETs,” IEEE Trans. PowerElectron., vol. 36, no. 7, pp. 8267-8279, July 2021.
S. Kawai, T. Ueno, H. Ishihara, S. Takaya, K. Miyazaki and K. Onizuka,"A 1ns-resolution load adaptive digital gate driver IC with integrated
500ksps ADC for drive pattern selection and functional safety targeting
dependable SiC application," in Proc. IEEE Energy Conversion Congressand Exposition, Oct 2021, pp. 5417-5421.
W. J. Zhang, J. Yu, W. T. Cui, Y. Leng, J. Liang, Y.-T. Hsieh, H.-H. Tsai,
Y.-Z. Juang, W.-K. Yeh, and W. T. Ng"A smart gate driver IC for GaN
power HEMTs with dynamic ringing suppression," IEEE Trans. on
Power Electronics, vol. 36, no. 12, pp. 14119-14132, Dec 2021.
S. Fukunaga, H. Takayama and T. Hikihara, "A study on switching surge
voltage suppression of SiC MOSFET by digital active gate drive," in Proc.
IEEE 12th Energy Conversion Congress & Exposition - Asia (ECCEAsia), May 2021, pp. 1325-1330.
T. Sai, K. Miyazaki, H. Obara, T. Mannen, K. Wada, I. Omura, T. Sakurai,and M. Takamiya, "Stop-and-go gate drive minimizing test cost to findoptimum gate driving vectors in digital gate drivers," in Proc. IEEE Appl.
Power Electron, Conf. Expo., Mar. 2020, pp. 3096-3101.

8 bit

58 A
2 DACs296
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