General-Purpose Clocked Gate Driver (CGD) IC with
Programmable 63-Level Drivability to Reduce Ic
Overshoot and Switching Loss of Various PowerTransistors
Koutaro Miyazaki*, Seiya Abe†, Masanori Tsukuda†, Ichiro Omura†, Keiji Wada‡, Makoto Takamiya* andTakayasu Sakurai**
University of Tokyo, Tokyo, Japan
Kyushu Institute of Technology, Fukuoka, Japan‡Tokyo Metropolitan University, Tokyo, Japan
Email: koutaro@iis.u-tokyo.ac.jp†problems: (1) customized design to each power transistor (e.g.
Si-IGBT, SiC-MOSFET) increases the development cost andturnaround time (TAT), and (2) limited programmability (e.g. 2gate resistances [1-5], multi voltage levels [6-9], and 9 output
resistances of the segmented gate drivers [10]) prevents a
precise gate waveform optimization for the low noise and thelow loss of the power transistors. To solve the problems, ageneral-purpose clocked gate driver (CGD) IC is proposed toprovide a universal platform for fine-grained gate waveform
optimization handling various power transistors including SiIGBT and SiC-MOSFET, thereby reducing the development
cost and TAT for the gate drivers. The proposed CGD IC
enables a fine-grained programmability of 63-level drivability
and 40-ns step timing control, which reduces IC overshoot andturn-on energy loss for Si-IGBT and SiC-MOSFET in the 500V switching measurement. The programmability of CGD is thefinest compared with the previous gate drivers [1-10].

Abstract—A general-purpose clocked gate driver (CGD) IC togenerate an arbitrary gate waveform is proposed to provide a
universal platform for fine-grained gate waveform optimization
handling various power transistors. The fabricated IC with
0.18μm BCD process has 63 PMOS and 63 NMOS drivertransistors on a chip whose activation patterns are controlled by
6-bit digital signals and 25-MHz clock (= 40-ns time step control).
In the 500-V switching measurements, the proposed CGD
reduces the IC overshoot by 25% and 41% and the energy loss by
38% and 55% for Si-IGBT and SiC-MOSFET, respectively.
Keywords—Gate driver; IGBT; SiC; Clock; ProgrammableI.

INTRODUCTION

A gate driver is a key technology for the switching of powerdevices to minimize the switching loss and the current
overshoot. Conventional gate drivers, however, have two

Implemented on a chipLevel-shifters& Buffers B2T*
VDRIVE(10V-18V)
VDRIVE -VPD_PMOS
VPD_NMOS
BPMOS

6CK

1BNMOS

6GND

D-FF

663

BPMOS

NPMOS

1CK

663

BNMOS

NNMOS

1CK

DQ

63Predriver

63-Parallel
Drivers

63
GPMOS

IC
VC
VG

DQ

6363
GNMOS*) B2T: Binary to Thermometer-code decoder
Fig. 1 Schematic diagram of general-purpose clocked gate driver (CGD) IC.

978-1-4673-9550-2/16/$31.00 ©2016 IEEE

VDC =500V

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IG

II.

SYSTEM IMPLEMENTATIONThe schematic diagram of the implemented general-purpose
CGD IC is shown in Fig. 1. CGD IC is developed for theswitching of power devices at VDC = 500V. In order to realize
programmable 63-level drivability, 63 parallel drivers areconnected to the gate of the power device and a 6-bit binary
control signal, BPMOS (BNMOS), is applied to specify the numberof activated PMOS (NMOS) driver transistors, NPMOS (NNMOS).
A pair of 6-bit signals (BPMOS and BNMOS) are latched by theclock (CK) and activate the final 63 PMOS (NMOS)
transistors. CK frequency is 25MHz and 40-ns time step
control of the drivability is achieved. The power supply voltage(VDRIVE) of CGD IC is 10V–18V, and VDRIVE of 15V is used inthe following measurements. The voltage swing of input digital
signals (BPMOS, BNMOS, and CK) is 5V, and the swing isincreased to VDRIVE by level-shifters. By adjusting the predriver voltage swing, VPD_PMOS and VPD_NMOS, from 1.2V to 5V,
the output drivability of a single driver MOS transistor can betuned from 3mA to 80mA. The peak drivability is 63 times ofthe single driver, which corresponds to the maximum peakcurrent of the gate current (IG) from 0.19A (= 3mA x 63) to 5A(= 80mA x 63). VPD_PMOS and VPD_NMOS of 1.8V is used in thefollowing measurements.
The binary-coded input is indispensable since 63 x 2 input
pins are too many to handle. The binary signals, however, maycause glitch problems in the gate voltage (VG). The glitch will
break down the power transistors. For example, when thebinary input changes from 011111 (31) to 100000 (32), there isa possibility that the state goes from 011111 (31) to 111111(63) to 100000 (32) causing a few nano-seconds glitch at thepre-driver, if there are variability of devices andinterconnection designs which make the most significant bitchange faster than the other bits. This is the cause of the glitch
problems. To prevent this problem, a small-sized binary tothermometer-code decoder in Fig. 2 is employed.
Fig. 3 shows operation waveforms for 63 PMOS transistors
to pull up VG in CGD IC. The operation for 63 NMOS
transistors to pull down VG is similar. An arbitrary IG
waveform is generated by applying a control bit pattern (BPMOS(BNMOS)) in each clock cycle with 40-ns step and digitally
specifying time and current pairs of ti and IGi (i=1,2,3…n).
III.

MODELING OF GATE DRIVER

In this chapter, the modeling of the 63 parallel drivers in Fig.
1 is discussed. In the previous the segmented gate drivers [10],the transistors in the segmented gate drivers (Fig. 4(a)) weremodeled as a resistor (Fig. 4(b)). In this paper, it is proposedthat the transistors in the segmented gate drivers should bemodeled as current-source (Fig. 4(c)) instead of the resistor(Fig. 4(b)). Fig. 5 shows the SPICE simulated pull-up and pulldown waveforms of VG with two models in Fig. 4. The
capacitance in Fig. 4 is 22nF emulating the gate capacitance ofthe power devices. VPD_PMOS and VPD_NMOS are 5V and 1.8V inFigs. 5 (a) and (b), respectively. Compared with the resistor
model, the current-source model is in good agreement with thedriver with transistors. Therefore, the gate driver behaves likethe constant-current driver (Fig. 4(c)) rather than the resistor(Fig. 4(b)) because of the high output resistance of MOStransistors in a saturation region.

BX6BX5BX4BX3BX2BX10

NX63 00

NX62 00

NX61 0All 001

NX3 00

NX2 1All 1
NX1 1Fig. 2 Binary to thermometer-code decoder.

CKBPMOS1:6NPMOS06300N

N

63
IG1IG63NN

IG2

IG36363
IG4VG
if charging
pure capacitor
t140nst2

t3t4t5Fig. 3 Operation waveforms for 63 PMOS transistors to pull up VG in CGD
IC.

IV.

MEASUREMENT RESULTS

The proposed general-purpose CGD IC is fabricated with40V, 0.18μm BCD process. Fig. 6 shows a die photo of CGD
IC. The core size is 2300μm by 730μm. Fig. 7 shows photos ofPCB. The 2.5-mm square CGD IC is placed on the top side of
PCB. Si-IGBT and SiC diodes are placed on the reverse side ofPCB.
Turn-on characteristics are measured with a double-pulse
setup shown in Fig. 1 with SiC diodes (C4D10120D, 1200V,18A) at VDC = 500V. To demonstrate the versatility of theproposed general-purpose CGD IC, both Si-IGBT(IRG7PH46UPbF, 1200V, 75A) and SiC-MOSFET(SCH2080KE, 1200V, 40A) are driven by CGD IC. Althoughin Fig. 1, an IGBT symbol is used for a power device, theIGBT is replaced by SiC-MOSFET when SiC-MOSFET isunder test. Notations such as IC and VC are used even for theSiC-MOSFET device just for simplicity.

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Driver

To show the advantage of the proposed CGD IC withprogrammable 63-level drivability, three types of gate
waveforms shown in Fig. 8 are compared. Fig. 8 (a) shows aconventional “no active gate drive” [11]. To show the trade-off
between the turn-on energy loss and IC overshoot, IG to pull-up
VG is varied by NPMOS in the measurement. Fig. 8 (b) shows aconventional “9-level active gate drive” emulating the 9-levelsegmented gate drivers [10]. This waveform is based on [5, 7,9-10, 12]. At the turn-on, NPMOS changes from 0 to m andkeeps m for t1. Then, NPMOS changes from m to 9 level of i (i =2 to 58 with 7 increments in between) and keeps i for t2. Finally,NPMOS changes from i to m. Fig. 8 (c) shows the proposed “63level active gate drive”. Fig. 8 (c) is the same as Fig. 8 (b)except for i. In Fig. 8 (c), i is from 0 to 63 with 1 increment inVG

(a)

Resistor model
VG(b)Current-source modelVG

B2T+DFF+Predriver

730μm

(c)
Fig. 4 Modeling of gate drivers. (a) Original gate driver. (b) Conventional
resistor model. (c) Proposed current-source model.

NMOSdrivers

VPD_PMOS = VPD_NMOS = 5.0V

152300μm

Current-source
model

Fig. 6 Die photo of CGD IC.

VG [V]

10Resistor model

DriverTop side

500246Time [µs]810CGD IC(2.5mm x 2.5mm)(a)

VPD_PMOS = VPD_NMOS = 1.8V
15Current-source
model

Reverse side

VG [V]

10Si-IGBT

Resistor model

Driver500

102030Time [µs]40

SiC
diode50(b)Fig. 5 SPICE simulated pull-up and pull-down waveforms of VG with twomodels in Fig. 4. VPD_PMOS and VPD_NMOS are 5V and 1.8V in (a) and (b),respectively.

Fig. 7 Photos of PCB.

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PMOSdrivers

Table I Parameters used in measurements for Si-IGBT and SiC-MOSFETNPMOSSi-IGBT

SiC-MOSFETm3163t1160ns40nst2160ns80ns

6363 level
2Time

9-level active (Fig. 8(b))

Energy loss [mJ]0(a)NPMOS58m

9 level20

No active (Fig. 8(a))

t1

t2

63-level active (Fig. 8(c))

−38%

1

Fig. 11(b)0Fig. 11(a)−25%Si-IGBT05

10152530IC overshoot / Load current [%]Time

Fig. 9 Measured energy loss vs. IC overshoot in turn-on characteristics at 500V switching for Si-IGBT.

(b)2
No active (Fig. 8(a))

NPMOS

9-level active (Fig. 8(b))

Energy loss [mJ]

63m63 level020t1t2

Time63-level active (Fig. 8(c))

1Fig. 12(b)0(c)
Fig. 8 Three types of gate waveforms. (a) No active gate drive. (b) 9-level
active gate drive. (c) Proposed 63-level active gate drive.

between. Table I shows m, t1, and t2 in the measurements for
Si-IGBT and SiC-MOSFET, respectively.
Figs. 9 and 10 show measured energy loss versus IC
overshoot in turn-on characteristics at 500-V switching withthe three gate waveforms shown in Fig. 8 for Si-IGBT and SiCMOSFET, respectively. In the no active gate drive, the tradeoff between the turn-on energy loss and IC overshoot isobserved. By using 63-level active gate drive, however, theloss-overshoot trade-off can be optimized more compared withcases of 9-level active gate drive [10] and no active gate drive.
The proposed 63-level active gate drive reduces the measured
energy loss at the same IC overshoot by 38% (Fig. 9) and 55%

Fig. 12(a)

−55%

−41%

SiC-MOSFET
0510152025IC overshoot / Load current [%]30Fig. 10 Measured energy loss vs. IC overshoot in turn-on characteristics at 500V switching for SiC-MOSFET.

(Fig. 10) for Si-IGBT and SiC-MOSFET, respectively.
Similarly, the proposed 63-level active gate drive reduces themeasured IC overshoot at the same energy loss by 25% (Fig. 9)
and 41% (Fig. 10) for Si-IGBT and SiC-MOSFET,respectively. The corresponding measured waveforms of NPMOS,
VG, VC, and IC for Si-IGBT and SiC-MOSFET are shown inFigs. 11 and 12, respectively. The 25% and 41% reduction ofIC overshoot are clearly shown in Figs. 11 and 12, respectively.
Table II shows a comparison of the proposed CGD IC withprevious gate drivers. This work achieved the 40-ns step timing

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No active gate drive

No active gate drive

Overshoot=3.52A

Overshoot=3.36A

IC: 2.5A/div

IC: 2.5A/div
VC: 100V/div

VC: 100V/div
VG:5V/div

VG:5V/div

NPMOS 22=00100

200

300

400500600

Time [ns](a)NPMOS=00700

22100

50−25%

150

Time [ns](a)200−41%63-level active gate drive

63-level active gate drive

Overshoot=2.08A

Overshoot=2.51A

IC: 2.5A/divIC: 2.5A/div
VC: 100V/div

VC: 100V/div
VG:5V/div

100

VG:5V/div

6363

NPMOS 31=00300

250315200

300

400

500

600

0700

NPMOS=0750100

150200300

250Time [ns](b)Time [ns](b)Fig. 11 Measured waveforms for Si-IGBT corresponding to Fig. 9. (a) Noactive gate drive. (b) Proposed 63-level active gate drive.

Fig. 12 Measured waveforms for SiC-MOSFET corresponding to Fig. 10. (a)No active gate drive. (b) Proposed 63-level active gate drive.
Table II Comparison with previous gate drivers

control and 63-level drivability, thereby enabling the gate
waveform optimization for both Si-IGBT and SiC-MOSFET.
The time programmability is achieved for the first time and the63-level drivability is the largest number of the drivability
levels.
V.

CONCLUSIONS

The general-purpose CGD IC to generate an arbitrary gate
waveform is the universal platform for fine-grained gate
waveform optimization handling various power transistors.
The 40-ns step timing programmability is achieved for the firsttime and the 63-level drivability is the largest number of thedrivability levels in the previously published gate drivers. In
the 500-V switching measurements, the proposed CGD

[1]

[2]

[6]

[10]

This work

Implementation PCB

PCB

PCB

ICICTarget
power device

SiSiSiCSiIGBT IGBT MOSFET IGBT

Si-IGBT &SiC-MOSFET

Time
programmability

NA

NA

NA

NA

40-ns step

Number ofdrivability levels

224963

How to change
drivability

RG

RG

Gate current

NANA

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Drive Driver
NPMOS, NNMOS
voltage size VPD_PMOS, VPD_NMOS
NA

NA

3mA~5Areduces the IC overshoot by 25% and 41% and the energy lossby 38% and 55% for Si-IGBT and SiC-MOSFET, respectively.
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