Increasing Minimum Operating Voltage (VDDmin) with
Number of CMOS Logic Gates and Experimental
Verification with up to 1Mega-Stage Ring Oscillators
Taro Niiyama, Zhe Piao, Koichi Ishida, *Masami Murakata, Makoto Takamiya,
and Takayasu Sakurai
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, Japan, 153-8505*Semiconductor Technology Academic Research Center (STARC), Japan

VDDmin is the minimum power supply voltage when the circuits
operates without function errors. RO’s are useful VDDmin detectors[7], because RO’s stop oscillation when the first function error in
the logic circuits happens. Figure 1 shows simulated waveform of
5-stage CMOS inverter RO. VDD is varied from 0.2V to 0V. At
VDDmin of 50mV, RO stops oscillation. In order to emulate therecent SoC’s, the mega stage scale RO’s are required, because therecent SoC’s have 10M-100M logic gates. With the technology
scaling and the increased number of transistors on a chip, VDDmin
will increase, because the more gates there are, the more likely itis that the worst-case condition will occur, and thus a higher VDD
will be required. However, the systematic measurements of the
VDDmin of the subthreshold logic circuits made with scaled devices
have not been reported yet.

ABSTRACT
In order to explore the feasibility of the large scale subthresholdlogic circuits and to clarify the lower limit of supply voltage(VDD) for logic circuits, the dependence of minimum operating
voltage (VDDmin) of CMOS logic gates on the number of stages,
gate types and gate width is systematically measured with 90-nm
CMOS ring oscillators (RO’s). The measured average VDDmin of
inverter RO’s increased from 90 mV to 343 mV when the number
of RO stages increased from 11 to 1Mega, which indicates thedifficulty of the VDD scaling in the large scale subthreshold logic
circuits. The dependence of VDDmin on the number of stages iscalculated with the subthreshold current model with random
threshold voltage (VTH) variations and compared with themeasured results, which confirm the tendency of the measurement.

This paper reports the systematically measured dependence ofVDDmin of CMOS logic gates on the number of stages, gate types
and gate width with 90-nm CMOS RO’s for the first time in order
to explore the feasibility of the large scale subthreshold logic
circuits and to clarify the lower limit of VDD for logic circuits.

Categories and Subject Descriptors
B.7.0 [Integrated Circuits]: General

General Terms
Measurement, Performance, Design, Reliability, Experimentation.

Vout

Keywords
Minimum operating voltage, subthreshold, logic, variations(a)

1. INTRODUCTION
Very low voltage operation of VLSI's is effective in reducing bothdynamic and leakage power and the maximum energy efficiency
is achieved at low VDD (e.g. 320mV [1]). Thus many works havebeen carried out on the subthreshold operation of logic circuits [1,3-6] and SRAM’s [2], where VDD is less than VTH of transistors.
However, the number of transistors of the previously reported
subthreshold circuits is small (e.g. 70k transistor logic circuits at
VDD of 230mV [1], a 32kbit SRAM at VDD of 160mV [2], and a1000 stage inverter chain at VDD of 60mV [5]), and the possibilityof the mega gate scale subthreshold circuits is not clear.

Voltage (mV)

200

VDD

100

VDDmin500Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies are
not made or distributed for profit or commercial advantage and that
copies bear this notice and the full citation on the first page. To copy
otherwise, or republish, to post on servers or to redistribute to lists,requires prior specific permission and/or a fee.
ISLPED’08, August 11-13, 2008, Bangalore, India.
Copyright 2008 ACM 978-1-60558-109-5/08/08...$5.00.

Vout

150

0

20

40

60

80

100

Time ( μs)(b)Figure 1. Simulated waveform of 5-stage CMOS inverter
RO. Definition of VDDmin is shown.

117

VDD

Section 2 presents the design of CMOS RO’s for VDDminmeasurement and the measured VDDmin. Section 3 presents theanalysis of the origin of VDDmin with SPICE and MATLAB to
explain the measured results.

VDDIO
1V swing

Low swing

Ring
oscillator

2.2mm

1.3mm

VSSIO

VSS=0V

Output buffer

Figure 2. Proposed RO circuits to enable the VDDminmeasurement.

1M stageinverter RO
(a)

VDD
Wp

(b)

Wn

Figure 4. (a) Micrograph of a 1M-stage inverter RO. (b)Layout style of RO’s.

VSS

(a)
VDD
Wp

2. MEASURED VDDmin of 90-nm CMOS RO’s
2.1 Design of CMOS RO’s for VDDmin
Measurement

Wp

Wn

Figure 2 shows the schematic of the proposed RO circuits toenable the VDDmin measurement. The low swing output of RO is
amplified to 1-V swing by the output buffer, because both VDD
and VSS of RO are separated from the VDDIO and VSSIO of theoutput buffer by the triple well and VSS is manually tuned to the
optimum input level for the output buffer in the measurement.
VDDmin is defined as the supply voltage ( = VDD−VSS) when the
RO’s stop oscillation and no voltage transitions from the output
buffer are observed, which corresponds to the function errors inlogic LSI’s.

Wn
VSS

(b)
VDD
Wp

Wp

Wp

Wn
Wn

Figure 3 shows the schematic of fabricated RO circuits withvaried number of stages. RO’s include three different logic gates(inverter, 2NAND and 3NAND) and two inverters with different
gate width. The standard primitive cells are used for the logic
gates and the P/N ratio was not optimized for the minimum VDD
operation. The gate length is the minimum in 90 nm CMOS
process. The gate width of nMOS (Wn) and pMOS (Wp) are
0.54μm and 0.82μm respectively. RO’s were fabricated with 1 V
90 nm CMOS process in three different lots. The first lot includes
inverter RO’s from 11-stage to 1Mega-stage to investigate thedependence of VDDmin on the number of stages. The second lot
includes inverter RO’s, 2NAND RO’s and 3NAND RO’s toinvestigate the gate type dependence. The third lot includes
inverter RO’s and x4 inverter RO’s to investigate the gate width
dependence.

Wn
VSS

(c)
VDD
Wpx4

Wnx4
VSS

(d)
Figure 3. Fabricated RO circuits with varied number ofstages. (a) Inverter RO, (b) 2NAND RO, (c) 3NAND RO,(d) x4 inverter RO.

Figure 4(a) shows the micrograph of a 1Mega-stage inverter RO
in 90 nm CMOS. The core area is 2.2mm×1.3mm. Figure 4(b)shows the layout style of RO’s. In order to remove the effect of
the global variation on RO’s, the interconnect length between the

118

400
15

11-stage

350
Average VDDmin (mV)

10
5
0
15

0

50

100 150 200 250 300 350 400 450

101-stage

10

300
250
200
150
100
50

5

0
0
15

0

50

100 150 200 250 300 350 400 450

050

10k-stage

5

15

0

50 100 150 200 250 300 350 400 450

300
250
200
150

50
0
10

5

15

1M

100

100k-stage

10

0

100k

350

100 150 200 250 300 350 400 450

10

0

10k

400

VDDmin (mV)

Number of dies15

1k

Figure 6. Measured dependence of the average VDDmin of
inverter RO’s on the number of stages.

5
0

100

Number of stages

1k-stage

10

10

100

1k

10k

100k

1M

Number of stages
0

Figure 7. Measured dependence of VDDmin of inverter RO’s
on the number of stages for 15 dies.

50 100 150 200 250 300 350 400 450

1M-stage

10

logic circuits have high VDDmin. In order to analyze the die-to-die
VDDmin variations, Figure 7 shows the measured dependence ofVDDmin of inverter RO’s on the number of stages for 15 dies. The
die-to-die VDDmin variations are not systematic but random.

500

50 100 150 200 250 300 350 400 450

VDDmin (mV)

2.3 Dependence of VDDmin on Gate Types

Figure 5. Die-to-die distribution of VDDmin of inverter RO’s
with different number of stages from 11-stage to 1M-stage.

Figure 8 shows the measured dependence of the average VDDmin of
inverter, 2NAND and 3NAND RO’s on the number of stages
from 11-stage to 1k-stage. The three lines have the similar
gradient, but they have different offsets. The gradient isdetermined by the transistor variations and the offsets are
determined by the unbalance between nMOS and pMOS. In thiswork, 3NAND RO’s have the highest average VDDmin, because
both Wn and Wp are the same for the inverter, 2NAND and
3NAND RO’s as shown Figures 3(a)-(c) and the 3NAND RO’s
have the largest unbalance between nMOS and pMOS. The
unbalance, however, can be solved by tuning Wp /Wn ratio.

inverters is as short as possible and the maximum interconnect
length in the 1Mega-stage inverter RO is 3.5μm.

2.2 Dependence of VDDmin on Number ofStagesFigure 5 shows the measured die-to-die distribution of VDDmin of
inverter RO’s with different number of stages from 11-stage to
1M-stage. Figure 6 shows the measured dependence of theaverage VDDmin with ±1σ error bar of inverter RO’s on the numberof stages extracted from Figure 5. As the number of stages isincreased, the average VDDmin increase, because VDDmin isdetermined by the worst inverter(s) in each RO. For example, theaverage VDDmin increases from 90 mV to 343 mV when thenumber of RO stages increases from 11 to 1Mega. The 343 mVmeans above VTH operation. The results indicate that VDDmin for
logic circuits depends on the scale of the circuits and large scale

2.4 Dependence of VDDmin on Gate Width

Die-to-die distribution of VDDmin of inverter RO’s and x4 inverter
RO’s with different number of stages from 11-stage to 1Megastage is measured. The lowest VDDmin was 58 mV for the 11-stage
RO’s. Figure 9 shows the measured dependence of the average
VDDmin of inverter and x4 inverter RO’s on the number of stages.
The two lines have the similar offset, but they have different
gradients. In theory, the gradient of the x4 inverter RO’s is half of

119

VDD
O
ND R
3NA
D RO
N
A
2N
RO
rter
Inve

250
200
150

V2

2

50
100

1k

NumberstagesNumber ofof stages

200

85
80

150

rter
Inve

x4 in

100

RO

r
verte

V2

V6

V4

70

V10

11

V11

V11

VINV
V1~V11V7

50

VDD=85mV

40
30
20
10

V8
V1
1

V3
2

3

Fail

V10

VOUT_LOW_7 > VINV_8

V5
4

5

6

7

8

9 10 11

Inverter numberRO(b)
Figure 11. (a) Simulated 11-stage inverter chain where
each transistor has random VTH. (b) Node voltages(V1−V11) and inversion voltages (VINV’s) of the inverters.

50

0.40

100
Number ofof
stagesNumberstages

400

300

3N

ND

150

r
verte
x4 i nr t erFigure 12. Comparison of the inverter characteristic of
SPICE and Matlab.

RO

1k

VOUT

0.1V

VIN (V)RO

3. ANALYSIS OF VDDmin
3.1 Analysis of VDDmin with SPICE

50
100

VIN

0.15

0.00
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

RO
e
Inv

200

0.2V

0.20

0.05 0.05V

RO

2NA

250

SPICE
MATLAB

0.25

0.10

D
AN

0.3V

0.30

Figure 9. Measured dependence of the average VDDmin of
inverter and x4 inverter RO’s on the number of stages.
350

VDD=0.4V

0.35

1k

VOUT (V)

0
10

0
10

V9

60

0

100

10

(a)

Figure 8. Measured dependence of the average VDDmin of
inverter, 2NAND and 3NAND RO’s on the number ofstages.

Average V DDmin (mV)

V3

3

100

0
10

AverageVVDDmin (mV)
AverageDDmin (mV)V1

1

VINV of inverter, V1~V11 (mV)

Average
Average V
VDDmin
(mV)
(mV)
DDmin

300

10k

100k

1M

The origin of the VDDmin is analyzed with Monte Carlo SPICE
simulations. Figure 11(a) shows the schematic of the simulated
11-stage RO’s where each transistor has random VTH. The
inverter chain with the input of VDD is simulated. Figure 11(b)shows the node voltages (V1−V11) and the inversion voltages(VINV’s) of the inverters. Normally, the logical low of V1−V11 islower than VINV and the logical high of V1−V11 is higher than VIN.
The inverter chain, however, has a function error at #7 and #8
inverter, because #7 inverter has slow nMOS and fast pMOS,
VINV of #7 inverter is high, and the logical low of V7 (VOUT_LOW_7)
is higher than VINV of #8 inverter. The function error stops the RO
oscillation.

Number of stages
Figure 10. Summary the measured dependence of theaverage VDDmin of all RO’s lots on the number of stages.
that of the inverter RO’s, because the x4 gate width halves theVTH variations. The measured gradient of the x4 inverter RO’s,
however, is 70% of that of the inverter RO’s.

2.5 Summary of VDDmin Measurement

Figure 10 summarizes the measured dependence of the average
VDDmin of all RO’s lots on the number of stages extracted from
Figures 6, 8 and 9. The three lines of the inverter RO’s show themeasured average VDDmin in three different lots. While increasing
the number of stages and the number of stacked transistors
increases VDDmin, the wide gate width decreases VDDmin.

3.2 Comparison of Measured and Calculated
VDDminIn order to investigate the increasing average VDDmin with thenumber of stages, the simulations of VDDmin from 11-stage to
1Mega-stage RO’s are required. However, the simulations of120

I D = C1eC2 (VGS −VTH ) (1 − e −C3VDS )
1

2

3

n-1

n

ID is the drain current, VGS is the gate-to-source voltage and VDS isthe drain-to-source voltage. C1, C2 and C3 are constants. In the
CMOS inverter, the input-output characteristic of the inverter isderived by equating ID of nMOS and pMOS. Figure 12 shows thecomparison of the inverter characteristic of SPICE and thecalculation with Equation (1). MATLAB is used for the calculation.
VDD is varied from 50mV to 0.4V. The calculation is verified bycomparing with SPICE. Below VDD of 0.2V, the calculation error issmall. In contrast, Above VDD of 0.3V, the calculation error is large,
because the calculation includes only the diffusion current ( =subthreshold current) and neglects the drift current ( = strong
inversion current).

n = Odd number(a)
PDF of Vn-1 (%)

10

0V
n-1

1

Vn-1

5

0
0
Vn-1 (V)VDD

Figure 13 shows the calculation steps of VDDmin of a n-stage RO,
where n is an odd number. The transistors in the RO have random
VTH variations. First, the probability density function (PDF) of theoutput (Vn-1) of the (n−1)-stage inverter chain with the input of 0V is
calculated by cascading the (n−1)-stage inverters as shown in Figure13(b). Though the correct Vn-1 is low, Figure 13(b) shows someincorrect high Vn-1 due to the function error. Then, the PDF of thelogical low (=error) of Vn by integrating the VINV distribution is asshown in Figure 13(c). Figure 13(d) shows PDF of Vn error derived
by multiplying Figure 13(b) by Figure 13(c). Finally, Figure 13(e)shows the cumulative distribution function (CDF) of Vn error
derived by integrating Figure 13(d). Strictly speaking, CDF of Vnerror of the n-stage inverter chain with the input of VDD should also
be calculated and added to Figure 13(e). However, the inputs of 0V
or VDD are symmetry. Therefore, VDDmin is defined as VDD when
CDF of Vn error equals to 25% as shown in Figure 13(e).

(b)
PDF of logical
low of Vn (%)

100

Vn-1
50

0

Vn
n

0
Vn-1 (V)VDD

PDF of Vn error (%)

(c)
10

5

0
0
Vn-1 (V)

Table I shows the 4 sets of σVTH’s of nMOS and pMOS used in thecalculation. σVTH’s are originally determined by the Pelgrom plot,
however, σVTH’s are varied to fit the measured results. Figure 14
shows the comparison of measured and calculated dependence of
the average VDDmin of inverter RO’s on the number of stages. The
measured x4 inverter RO’s are also plotted. The calculation showsthe expected increasing gradients and offsets with increased σVTH,
which confirm the tendency of the measurement. The two reasonsfor the quantitative error between the measurement and MATLAB
are; (1) Only VTH variations are considered in the calculation and noother variations are not considered. (2) The inverter characteristic
error increases with the increased VDD as shown in Figure 12,
because the model includes only the subthreshold current andneglects the strong inversion current.

VDD

CDF of Vn error (%)

(d)
50

25

0
0

(1)

VDDminVDD (V)

Finally, the reason why the average VDDmin increases with thenumber of RO stages is discussed. Generally, the largest value
distributions fmax(x,n) of n samples which have Gaussian
distribution f(x) are shown in Figure 15.

(e)Figure 13. Calculation steps of VDDmin of n-stage RO. (a)Calculated n-stage inverters. (b) PDF of the output of the(n−1)-stage inverter chain with the input of 0V. (c) PDF of
the logical low (=error) of Vn. (d) PDF of Vn error. (e) CDF
of Vn error.

(x − x )2
1 − 2σ 2(2)
f (x ) =e
2σn⎧⎛( y − x )2 ⎞ ⎫
−
x
1
d ⎪
⎪
2
f max (x, n ) = ⎨⎜⎜ ∫e 2σ dy ⎟⎟ ⎬ (3)dx ⎪⎜ − ∞ 2σ
⎟ ⎪
⎠ ⎭
⎩⎝

VDDmin of up to 1Mega-stage RO’s with Monte Carlo SPICE take
too long time and are not practical. Therefore, VDDmin is
calculated with the subthreshold current model with random VTH
variations and compared with the measured results. Equation (1)shows the drain current model of MOSFET in the subthresholdregion.

121

Probability distribution function

Table I. Several sets of σVTH’s of nMOS and pMOS usedin the calculation.
σVTH (mV)
Name

nMOS

pMOS

Remarks

Sim075

25.8

22.5

x0.75

Sim100

34.4

30.0

x1

Sim125

43.0

37.5

x1.25

Sim150

51.6

45.0

x1.5

350
300

Measurement
MATLAB
e
Inv

r ter

RO

Sim075
r
verte

RO

50
0
10

100

1k

10k

100k

1M

104

105

106

109

1010

107

102

f (x)

n=101
n=0

0

x − 2σ

x−σ

x

x+σ

x + 2 σ x + 3 σ x + 4 σ x + 5 σ x + 6σ

x + 7σ

x

8
7
6
5
4
3
2
1
0

Exact
Approx.

100 102 104 106 108 1010 1012 1014nNumber of stages

Figure 16. Comparison of exact and approximated resultsin n dependence of xmax .

Figure 14. Comparison of measured and calculated
dependence of the average VDDmin of inverter RO’s on thenumber of stages.
x is the average of x and σ is the standard variation of x. The x
value ( xmax ) where fmax(x,n) has its peak is approximated as

xmax ≅ x + 2 log10 nσ1

Sim100

150
x4 in

103

Sim125

200

100

2

108

xmax at n=106
Figure 15. The largest value distributions fmax(x,n) of nsamples which have Gaussian distribution f(x).

Sim150250

f max (x, n )(xmax – x) / σ

Average VDDmin (mV)

400

3

6. REFERENCES[1] H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, R.

(4)

Figure 16 shows the n dependence of xmax , and compares the exact[2]and approximated results. Equation (4) intuitively explains thereason why the average VDDmin increases with the number of RO
stages. The calculated dependence in Figure 14 is also approximatedby Equation (4) and the error was negligible small.

[3]

4. CONCLUSIONS
The minimum operating voltage (VDDmin) of 90-nm CMOS logic
gates has been investigated with the ring oscillators. The measured
average VDDmin of inverter RO’s increased from 90 mV to 343 mV
when the number of RO stages increased from 11 to 1Mega, whichindicates the difficulty of the VDD scaling in the large scale
subthreshold logic circuits. While increasing the number of stages
and the number of stacked transistors increases VDDmin, the wide
gate width decreases VDDmin. The dependence of VDDmin on thenumber of stages is calculated with the subthreshold current modelwith random threshold voltage variations, which confirm thetendency of the measurement.

[4]

[5]

[6]

5. ACKNOWLEDGMENTS
This work is partially supported by STARC. The VLSI chips were
fabricated through the chip fabrication program of VLSI Design and
Education Center (VDEC), the University of Tokyo, with thecollaboration by STARC, Fujitsu Limited, Matsushita ElectricIndustrial Company Limited., NEC Electronics Corporation,
Renesas Technology Corporation, and Toshiba Corporation.

[7]

122

Krishnamurthy, and S. Borkar, "A 320mV 56µW 411GOPS/Wattultra-low voltage motion estimation accelerator in 65nm CMOS,"IEEE International Solid-State Circuits Conference, pp. 316-317,
Feb. 2008.
I. Chang, J. Kim, S. Park, and K. Roy, "A 32kb 10T Subthreshold
SRAM Array with Bit-Interleaving and Differential Read Schemein 90nm CMOS," IEEE International Solid-State Circuits
Conference, pp. 388-389, Feb. 2008.
B. Calhoun, and A. Chandrakasan, "Ultra-dynamic voltage scaling(UDVS) using sub-threshold operation and local voltage
dithering," IEEE Journal of Solid-State Circuits, Vol. 41, No. 1,
pp. 238-245, Jan. 2006.
S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M.
Minuth, J. Olson, L. Nazhan-dali, T. Austin, D. Sylvester, and D.
Blaauw, "Performance and variability optimization strategies in a
sub-200mV, 3.5pJ/inst, 11nW subthreshold processor," IEEE
Symposium on VLSI Circuits, pp. 152-153, June 2007.
M. Hwang, A. Raychowdhury, K. Kim, and K. Roy, "A 85mV
40nW process-tolerant subthreshold 8x8 FIR filter in 130nm
technology," IEEE Symposium on VLSI Circuits, pp. 154-155,
June 2007.
J. Kwong and A. Chandrakasan, "Variation-Driven Device Sizing
for Minimum Energy Sub-threshold Circuits," International
Symposium on Low Power Electronics and Design, pp. 8-13, Oct.
2006.
T. Niiyama, P. Zhe, K. Ishida, M. Murakata, M. Takamiya, and T.
Sakurai, "Dependence of Minimum Operating Voltage (VDDmin) on
Block Size of 90-nm CMOS Ring Oscillators and Its Implicationsin Low Power DFM," IEEE International Symposium on Quality
Electronic Design, pp. 133-136, March 2008.