Variation-aware Subthreshold Logic Circuit Design
Hiroshi Fuketa1*, Ryo Takahashi1, Makoto Takamiya1, Masahiro Nomura2,Hirofumi Shinohara2, and Takayasu Sakurai1
1Institute of Industrial Science, University of Tokyo, Japan
Semiconductor Technology Academic Research Center (STARC), Japan* Email: fuketa@iis.u-tokyo.ac.jp

10-1
10-2
10-3
10-4

10-5

1. Introduction

Subthreshold circuits are, however, extremely sensitive
to manufacturing and environmental (e.g. temperature)
variability, because I-V characteristics of MOSFET’s in
the subthreshold region have an exponential dependenceon VTH. In this paper, the following three challenges insubthreshold circuit design induced by such variability
are discussed; 1) rise in a minimum operating voltage(VDDmin), 2) signal integrity degradation due to crosstalknoise, and 3) large delay variations.

2. Minimum operating voltage (VDDmin)
Reducing VDD could cause functional errors. The supply
voltage at which the first functional error occurs isdefined as a minimum operating voltage (VDDmin). The

1.0

Power10-8
10-90.8

Delay

0.6

10-100.4

Energy10-11

10-120.1 0.2(PD product)

Vopt

0.4

0.6

0.8

0.201.0

Eopt

Fig. 1. Simulated dependence of power, delay, and energy of
CMOS logic circuit.

Slope:- Within-die VTH variation- Device parameter (h)VDDminSubthreshold logic circuits, which operate at lower
supply voltage than threshold voltage (VTH), are one ofpromising solutions to achieve ultra-low power operation[1]. Fig. 1 shows simulated delay, power, and energy(power delay product) of a CMOS logic circuit [2]. As
the supply voltage (VDD) is reduced, the delay increases,
whereas the power significantly decreases. Therefore,
subthreshold logic circuits are suitable for low-power
applications in which circuit speed is not a primaryconcern or can be compensated by parallelization. For
such applications, energy is a key metric. As shown inFig. 1, the energy has its optimum value (Eopt) at
VDD=Vopt. Thus, Vopt is the target supply voltage forultra-low-power applications. Vopt is around 0.3V for
typical logic circuits [2].

10-7Normalized energy

100

NAND2 FO1 Delay (s)Abstract
Subthreshold logic circuits are one of promisingsolutions to achieve ultra-low power operation. However,subthreshold circuits are significantly sensitive tomanufacturing and environmental variability. In thispaper, we will discuss design challenges in subthresholdlogic circuits, such as rise in a minimum operating
voltage, signal integrity degradation, and large delayvariations.

Normalized power

2()
Subthreshold swing parameter([mV/dec])()
DIBL coefficient
Thermal voltage
Within-die VTH variation

Intercept:- Balance between pMOS and nMOS
- Device parameter (n, h)- Temperature (UT)

Fig. 2. Closed-form expression of VDDmin of logic gates whenpMOS and nMOS are not perfectly balanced.

minimum operating voltage (VDDmin) is defined as the
supply voltage where the first functional error occurs. If
VDDmin is higher than Vopt, the minimum-energy
operation cannot be attained. Therefore, investigations
on VDDmin are essential for subthreshold circuits.
Fig. 2 shows a closed-form expression for estimating
VDDmin of logic gates [3]. VDDmin can be expressed as alinear function of square-root of logarithm of the numberof logic gates. This means that VDDmin rises as thenumber of logic gates increases. Fig. 3 illustrates
VDDmin’s of an inverter chain with various configurationsof the within-die VTH variation obtained by Monte Carlo
SPICE simulations and the closed-form expression in a

: Monte Carlo SPICE sim.
: Equation

2NAND chain

3NAND chain

4NAND chain

N stages

N stages

N stages

300
Inverter chain

250
N stages200200

pn=1.5 (a.u.)

VDDmin (mV)

VDDmin (mV)

250

150
pn=1.0 (a.u.)100pn=0.4 (a.u.)

50150100021ln  N / 2 101

321020103

10104

Number of stages (N)Fig. 3. Simulated VDDmin’s of inverter chain in 65nm process.
pn’s are normalized by nominal value of this process.

Fig. 4 shows simulated VDDmin’s of the inverter andNAND chains. VDDmin’s of logic gates, which contain thelarger number of stacked/paralleled transistors, are muchhigher. This is because stacking and parallelingtransistors contained in the NAND gate worsen thebalance of the strength of pMOS and nMOS, whichcorresponds to the increase in parameter |b| in theclosed-form expression (Fig. 2). Although VDDmin can be
reduced by adjusting the balance between the strength ofpMOS and nMOS, it is usually impractical, since thegate sizes of either pMOS or nMOS transistors must be
significantly enlarged for the adjustment, and hence it is
not acceptable due to the area constraint [4]. Therefore,
the logic gates with a lot of inputs should not be used in
the design of subthreshold logic circuits.

ln  N / 2 101

232102

103

104

Number of stages (N)Fig. 4. Simulated VDDmin’s of inverter and 2-, 3-, 4-input
NAND chains in 65nm process.

65nm CMOS process. VDDmin’s obtained by theexpression agree with the simulated results.
The slope of the expression of VDDmin (Fig. 2) is
proportional to the standard deviation of the within-die
variation in the VTH difference between pMOS andnMOS transistors (pn). In contrast, the intercept of theexpression depends on the balance between intrinsic
strengths of pMOS and nMOS transistors (). This
indicates that the slope depends on the within-die VTH
variation, while the intercept depends on the die-to-die
VTH variation. Although body-biasing can compensate
the die-to-die variation, that is, can reduce the intercept,
it has no effects on reducing the slope. Therefore, theVDDmin increase due to the within-die VTH variation could
be a critical problem in large-scale circuits.

: 2NAND: 4NAND: INV: 3NAND

500= VDD : For falling noiseVVIC= 0 V : For rising noise

VDD (= 0.3 ~ 1.1V)
1.5 mmDrivers
VAGR

Aggressor
VictimAggressor

Crosstalk noise
VPEAK

VPEAK

(Rising noise)(Falling noise)

Fig. 5. Crosstalk-noise on 1.5-mm coupled wire lines
discussed in this paper.

3. Increase of crosstalk noise due to VTH imbalance
In subthreshold circuits, the dependence of crosstalknoise on manufacturing variability should be also taken
into account. In this paper, crosstalk noise on a 1.5-mm
coupled wire line shown in Fig. 5 is investigated. The
approximation model of crosstalk noise in thesubthreshold region has been proposed in [5, 6]. The
peak voltage of crosstalk noise (VPEAK) in Fig. 5 in thesubthreshold region is approximated as
1.3c  r
VPEAK ,approx  VDD  , r  0.5 c  0.5 (1)where c=CC/CW (CW and CC are the wire capacitance andthe coupling capacitance, respectively.) and r is theequivalent resistance ratio. r is expressed as
VTH , N  VTH ,PrenU T,(2)

VPEAK / VDD, VPEAK,approx / VDD

0.8(Simulation)

VPEAK,approx(Eq. (1))

0.6

x1.1

SF
0.4

0.2

TT00for rising noise, andVPEAK

FS
0.2

0.4

0.6

0.8

1.01.2Supply voltage VDD (V)VTH ,P VTH , NrenU T(a) Rising noise,(3)Fig. 6 shows the simulated peak noise voltage under atypical process condition (TT) and the corner conditions(slow-nMOS/fast-pMOS (SF) and fast-nMOS/slowpMOS (FS)) for the rising noise and falling noise,respectively. VPEAK/VDD at 0.3V is 1.1 times larger thanVPEAK/VDD at 1.1V for the rising noise under the SFcorner condition and 1.4 times larger for the falling noise
under the FS corner condition. The approximated peaknoise (VPEAK,approx) calculated using (1) is also shown,and it agrees with the simulation results. Fig. 6 indicatesthat peak noise voltage in the subthreshold region issignificantly sensitive to the VTH balance, since peaknoise voltage depends on the equivalent resistance ratio(r), which has an exponential dependence on the VTH
difference between nMOS and pMOS, as indicated in (2)and (3). Therefore, designers must consider the process
corners, such as the SF and FS corner conditions, as theworst-case conditions for signal integrity in subthresholdcircuits.
In [5, 6], the peak voltage of crosstalk noise is measured
in a 40nm CMOS process, and the measurement results
agrees with the simulation results.

4. Gate delay variation in subthreshold region
In the subthreshold region, the gate delay is significantly

VPEAK / VDD, VPEAK,approx / VDD

0.8

for falling noise, where VTH,P and VTH,N are VTH’s ofpMOS and nMOS, respectively. These equations indicatethat the peak noise voltage is sensitive to the VTH balance
between pMOS and nMOS. Here, we focus on the VTHimbalance induced by the die-to-die VTH variation, since
within-die VTH variation can be reduced by employing
wider MOSFET’s.

FS
0.6

x1.4

TT0.4
VPEAK
(Simulation)

0.2

VPEAK,approx(Eq. (1))

SF
00

0.2

0.4

0.6

0.8

1.0

1.2

Supply voltage VDD (V)(b) Falling noise
Fig. 6. Peak voltage of crosstalk noise on 1.5-mm coupledwire line with two aggressors and one victim at TT, FS, andSF process corners in 40nm CMOS process.

sensitive to VTH, because the subthreshold current has anexponential dependence on VTH. Therefore, the gate
delay is fluctuated by environmental variability such astemperature. Fig. 7 shows the measured dependence of
the average gate delay (=) on temperature of NAND
and NOR gates with different VDD [7]. As temperature is
reduced from 80°C to -40°C, the average gate delayslightly decreases at VDD=1.1V, whereas it increases at
VDD=0.3V by a factor of more than 10. The worst-case(=largest)  is observed at -40°C.
In addition, the gate delay variation (=/) also depends
on temperature. Fig. 8 shows the measured dependenceof / on temperature [7]. The worst-case (=largest) /is also observed at -40°C. In the NAND gate at

104

NAND
NOR

Measured
VDD=0.3V

103
102
101

0.5V
0.7V

100
1.1V
10-1

100

3.0
3.5
4.0
1/Temperature [10-3/K]
500Temperature [ºC]-50

Normalized /µ of gate delay [a.u.]

Normalized µ of gate delay [a.u.]

105

NAND

NOR

Measured

10X1.8

X1.4
VDD=0.3V

50.5V
0.7V
1.1V

0100

3.03.5
4.0
1/Temperature [10-3/K]
500Temperature [ºC]-50Fig. 7. Measured dependence of average gated delay () ontemperature in 40nm CMOS process.

Fig. 8. Measured dependence of gated delay variation (/)on temperature in 40nm CMOS process.

VDD=0.3V, / at -40°C is 1.8 times larger than that at85°C. This indicates that the temperature dependence of
/ as well as  must be taken into account for
subthreshold logic circuits.

sensitive to manufacturing and environmental variability.
Due to VTH variation, VDDmin increases and signal
integrity is degraded in subthreshold region. In addition,
the gate delay is fluctuated by environmental variability
such as temperature, which requires the large timing
margins. Therefore, the adaptive performance control,
which can reduce the timing margins, is effective forsubthreshold logic circuits.

As shown in Figs 7 and 8, the gate delay variation in thesubthreshold region is much larger than that in thenominal supply voltage region. This indicates that large
timing margins are required in the worst case design.
Since such large timing margins spoil energy-efficient
operation achieved by the reduction of VDD, an adaptive
performance control, such as dynamic VDD control
and/or body-bias control, is indispensable forsubthreshold circuits.
In order to attain the adaptive performance control, aperformance monitor is required, and conventionally,
replica circuits have been used for monitoring [8].
However, the critical path replica is inadequate forsubthreshold circuits, because the delay mismatch
between the replica and the actual critical path isremarkably large due to the within-die variation. In orderto overcome this mismatch, in-situ techniques, such as
Canary FF [9] and PEPD [10], which can predict theoccurrence of timing errors, have been proposed. Thesetechniques reduce the large timing margins, andconsequently the energy-efficient operation can beachieved.

5. Conclusion
In this paper, design challenges in subthreshold logic
circuits were discussed. Subthreshold circuits are

Acknowledgments
This work was carried out as a part of the Extremely
Low Power (ELP) project supported by the Ministry ofEconomy, Trade and Industry (METI) and the New
Energy and Industrial Technology Development
Organization (NEDO).
References[1] D. Bol, et al., ISSCC, pp.490-491 (2012).
[2] H. Fuketa, et al., IEDM, pp. 559-562 (2011).
[3] H. Fuketa, et al., DAC, pp. 984-989 (2011).
[4] T. Yasufuku, et al., ISLPED, pp. 21-26 (2011).

[5] H. Fuketa, et al., CICC, 20-3 (2012).
[6] H. Fuketa, et al., JSSC, in press.
[7] R. Takahashi, et al., TCAS-II, 12, pp. 918-921(2012).
[8] J. Kao, et al., JSSC, 11, pp. 1545-1554 (2002).
[9] H. Fuketa, et al., TVLSI, 2, pp. 333-343 (2012).
[10] K. Hirairi, et al., ISSCC, pp. 486-487 (2012).