IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1, JANUARY 2011

285

User Customizable Logic Paper (UCLP) With Sea-Of
Transmission-Gates (SOTG) of 2-V Organic
CMOS and Ink-Jet Printed Interconnects
Koichi Ishida, Member, IEEE, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino,
Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Member, IEEE, Takao Someya, Member, IEEE, andTakayasu Sakurai, Fellow, IEEE

Abstract—In this paper we present User Customizable Logic
Paper (UCLP) with a Sea-of Transmission-Gates (SOTG) of 2-V
organic CMOS transistors. This can enable users to fabricate
custom integrated circuits, by printing 200 m wide interconnectswith at-home ink-jet printers for the prototyping of large-area
electronics and educational purposes. The SOTG reduces the areaof the circuits in UCLP by between 11% and 85% compared witha conventional gate array architecture.
Index Terms—Customizability, education, gate array, ink-jet
printer, large-area electronics, printed interconnects, prototyping,room-temperature sintering, transmission gate logic, 2-V organic
CMOS.

I. INTRODUCTIONT

HE recent and rapid progression of printable electronics
means that it is now becoming feasible for ordinary people
to fabricate macroscopic printed custom integrated circuits operating at visible speeds, using at-home ink-jet printers [1], [2].
Organic transistors can realize large-area electronics such as
smart flexible displays, power transmission sheets, and electronic skin for robots. As the system integration scale with organic transistors increases, prototyping of the organic circuits
becomes more important. A second benefit of prototyping withorganic transistors is that their slow operating speeds make iteasier for learners to intuitively understand and experience theoperations of integrated circuits. This is in contrast to silicon
integrated circuits, where nanometer-scale transistors operate at

Manuscript received April 20, 2010; revised July 05, 2010; accepted July 16,
2010. Date of publication October 14, 2010; date of current version December
27, 2010. This paper was approved by Guest Editor Alison Burdett. This study
was supported in part by CREST/JST and the Grant-in-Aid for Scientific Research (KAKENHI; WAKATE S), NEDO, the Special Coordination Funds for
Promoting and Technology.
K. Ishida, R. Takahashi, and T. Sakurai are with the Institute of Industrial
Science, University of Tokyo, Tokyo 153-8505, Japan (e-mail: ishida@iis.utokyo.ac.jp).
N. Masunaga was with the Institute of Industrial Science, University ofTokyo, Tokyo 153-8505, Japan. He is now with Terumo Corporation, Tokyo
100-0005, Japan.
T. Sekitani and T. Someya are with the Department of Electrical and Electronic Engineering, University of Tokyo, Tokyo 113-8654, Japan.
S. Shino is with Mitsubishi Paper Mills Ltd., Nagaokakyo 617-8666, Japan.
U. Zschieschang and H. Klauk are with the Max Planck Institute for Solid
State Research, Stuttgart 70569, Germany.
M. Takamiya is with the VLSI Design and Education Center, University ofTokyo, Tokyo 113-8654, Japan.
Digital Object Identifier 10.1109/JSSC.2010.2074330

the lightning speed of a GHz clock, well beyond the scope ofthe human sense of vision and time.
Therefore, this paper proposes the use of User Customizable Logic Paper (UCLP) for both prototyping of larger-area
electronics and educational applications. In particular, learners
can study and experience the operation of integrated circuits
by fabricating custom integrated circuits, using at-home ink-jet
printers to print conducting interconnects on paper that contains
prefabricated arrays of organic transistors. The feasibility of
UCLP is demonstrated with the newly proposed Sea-of Transmission-Gates (SOTG) of organic CMOS transistors, providing
field customizability through the use of the printable electronics
technology for the first time. UCLP is applicable to a wide rangeof products of printable electronics including flexible displays
and electronic paper, as well as for educational purposes. This
technology provides a new means to add programmability for
integrated circuits used in large-area electronics.
In this paper we describe UCLP and some key technologies
including ink-jet printed interconnects and organic SOTG architecture. In Section II, UCLP and ink-jet printed interconnects
are introduced, while in Section III, the SOTG architecture is introduced. In Section IV, experimental results are described anddiscussed. And finally the conclusions are given in Section V.
II. UCLP AND INK-JET PRINTED INTERCONNECTS
A. User Customizable Logic Paper
Fig. 1 shows a prototype of UCLP, which was proposed in[3]. In UCLP, paper that contains an array of vias and an organic SOTG film are stacked. Although it would be ideal to fabricate the whole UCLP including the organic transistors using
ink-jet printers, this proves to be very difficult since both hightemperature (130–150 C) and an organic solvent are required
to fabricate the organic transistors. Since high temperatures andorganic solvents cannot be handled by ink-jet printers, in UCLP
the organic transistors are prefabricated and the field customizability is provided by the printed interconnects. Conventional
printed interconnects, however, also require high temperatures(130–150 C), which damages the organic transistors. The technology that enables us to solve the problem is the newly developed room-temperature sintering, conductive Ag nanoparticle
ink, which is introduced in Section II-B.
Fig. 2(a) shows the cross section of the SOTG film which
is described in detail in Section III. The 2 V organic CMOS
transistors are fabricated on polyimide film [4], [5]. Organic

0018-9200/$26.00 © 2010 IEEE

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1, JANUARY 2011

Fig. 1. Photograph of User Customizable Logic Paper (UCLP).
Fig. 3. Materials of ink-jet printed interconnects.

Fig. 2. Device structure of UCLP. (a) Cross section of SOTG. (b) Cross sectionof UCLP. (c) UCLP with ink-jet printed interconnects.

semiconductors for nMOS and pMOS are F CuPc (hexa-decafluoro-copper-phthalo-cyanine) and pentacene, respectively [4].
Self-assembled mono-layers (SAM) realize 2-V organic transistors [5], which are covered with a protective layer of parylene. Connection pads to the paper are formed with gold on topof this protective layer. An organic-metallic hybrid passivation
layer, not indicated in Fig. 2(a), protects the organic CMOS andlengthens its lifetime to six months or more in air. Fig. 2(b)shows the cross section of UCLP. Organic CMOS SOTG anda rewiring layer on paper are stacked. Electrical connections areprovided by Ag conductive adhesive. Then the interconnects are
ink-jet printed onto the paper by users as shown in Fig. 2(c).
B. Ink-Jet Printed Interconnects
A number of ink-jet printed interconnects technologies havebeen developed to date. However, either a high temperature(130–150 C) sintering or chemical process with organic solvent is required after the printing process, which causes damage
to organic transistors. In contrast, our proposed ink-jet printing
technology does not require such processes. The technology
consists of pre-coated nanoconductive base and silver nanoparticle ink as shown in Fig. 3. The pre-coated nanoconductive
base is a type of micro-porous layer made of Polyethylene,
Polyvinyl alcohol, boracic acid, and other materials to absorb
the solvent in the silver nanoparticle ink. Its thickness is around40 um. The ink includes 15% silver particles, alcohol, surface
active agent, and dispersant. The diameter of silver nanoparticles in the ink is typically 20 nm.
The ink chemically reacts with the pre-coated nanoconductive base on the paper at room temperature, that is, a sinteringfree process, and does not cause damage to organic transistors.
When the printed interconnect is stored in a laminated bag, thelife time is five months or longer. In air, resistance of the interconnects increases by 10% after one month.
Fig. 4(a) shows a photograph of the printing process of theinterconnects on UCLP using an off-the-shelf ink-jet (piezo-jet)printer. Fig. 4(b) shows photographs of printed interconnects
and a via hole. The thickness of the Ag interconnect is 1 m(typ.) and the measured sheet resistance is 0.2 square (typ.).
The via holes of 200 m in diameter are prefabricated in UCLP
by punching, in order to form a connection to the SOTG. The
measured via resistance is 2.7 via.
In this study, a 3 mm pad and via pitch rule is adopted.
The reasons are as follows. Firstly, we have to consider misalignment in feeding the paper in the printer. To adopt an
off-the-shelf, family-use printer, a large misalignment shouldbe accepted. A 300 m misalignment error is assumed in thisstudy, and therefore, each via extension is 300 m as shown inmFig. 5. Secondly, the Line/Space design ruleof the printed interconnect is determined by both printing
resolution and sheet resistance. Typical printers realize 100 m
resolution with the silver nanoparticle ink. However, the minimum line width should be determined by the sheet resistanceof the ink. The sheet resistance depends on the room temperature and relative humidity during printing. A sheet resistance of
0.14 square can be achieved by family-use printers at a highroom temperature of 30 C and relative humidity of 80%Rh.

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287

Fig. 5. Pad/via layout rule on paper.

Fig. 4. (a) Photograph of the printing process of the interconnects on UCLP
using an off-the-shelf ink-jet printer. (b) Photographs of printed interconnects
and a via hole.
Fig. 6. Area issue on gate array architecture in UCLP.

However, we assume a sheet resistance of 0.2 square byconsidering a practical room temperature of 17 C and relative
humidity of 35%Rh. We adopt 200- m wide interconnects inthis study, and thus resistance between two pads can be estimated around 2.2 . The line space of 200 m is determined bycrosstalk. The crosstalk of the proposed printed interconnects
is caused by resistive coupling rather than capacitive coupling.
The sheet resistance of the pre-coated nanoconductive base issquare, but satellite ink drops by family-use
typically
printers lower the actual sheet resistance to around 10% of thisvalue. Thus, the isolation of 20-mm long interconnects with aspace of 200 m can be estimated at around 9 M . Thirdly, theminimum via-hole diameter should be larger than 200 m to
. Finally, in orderachieve an acceptable via resistance ofto implement practical circuits, the number of interconnects
between the pads should be around five. As the result, a 3-mm
pad and via pitch rule is determined.
III. SEA-OF TRANSMISSION-GATE ARCHITECTURE
A. Architecture
The large pad and via pitch of 3 mm mentioned in the previous section presents a design challenge for UCLP to increase
integration density. Gate array (G/A) architectures have been
widely used in silicon technologies. The G/A architecture includes two pMOS transistors, two nMOS transistors, and nine
via holes in a logic cell. In silicon technologies, a narrow via
spacing rule is available, and therefore the number of vias is notcritical for the cell area as shown in Fig. 6. On the other hand,since we adopt a 3-mm pad and via pitch in UCLP, pads andvias now dominate the cell area as shown in Fig. 6. The number

Fig. 7. Schematic and symbol definition of SOTG unit cell.

of vias becomes a critical issue in UCLP, and in order to solve
the problem, an area-efficient SOTG is proposed instead of theconventional G/A approach.
Fig. 7 shows the schematic of the SOTG unit cell. SOTG uses
a type of pass transistor logic and a single SOTG cell has six
transistors. Each unit cell has a pair of complementary transmission gates, n-switch (NSW) and p-switch (PSW), and fourandareterminals for ink-jet printed interconnects.
common to every SOTG cell. In SOTG, the output (OUT) is
connected to either PSW or NSW depending on the input (IN).
Fig. 8 shows several examples of logic gate implementation
with the proposed SOTG cells. Binary decision diagrams (BBD)[6] are also shown in Fig. 8. An inverter requires one logic cellthat consists of six transistors, as shown in Fig. 8(a). At firstglance, the SOTG architecture seems to require a large number

288IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1, JANUARY 2011

Fig. 11. D-flip flop (positive edge triggered) implementation with SOTG cells.

Fig. 8. Examples of logic gate implementation with SOTG cells. (a) Inverter.
(b) Buffer. (c) Two-input multiplexer.

Fig. 9. Two-input XOR gate implementation with SOTG cells.

Fig. 12. Comparison of unit logic cell between G/A and SOTG.

B. Area Comparison With G/A Architecture

Fig. 10. Truth table of two-input logic functions and their binary decision
diagram.

of transistors, however as will be shown this is not critical forthe proposed UCLP. In terms of saving on rewiring cost or area,
the SOTG architecture makes it easy to customize the UCLP.
In fact, either a buffer or a two-input multiplexer can be implemented with one logic cell, as shown in Figs. 8(b) and 8(c).
An XOR gate consists of the 2-input multiplexer, the inverter,and two additional interconnects, shown in Fig. 9. Thanks tothe complementary transmission gates, not only the XOR, butalso any two-input logical operation can be realized with two
logic cells as shown in Fig. 10. Furthermore, a D-flip flop can be
implemented with only four logic cells and six interconnects, inand,addition to the power supply connection to bothas shown in Fig. 11.

Fig. 12 shows logic cells of the conventional G/A architecture
and the proposed SOTG architecture. Numbers of transistors
in a typical G/A logic cell and a SOTG cell are four and six,
respectively. Transistor W/L are chosen to be 150 m wide and20 m long, determined by the driving capability and process
yield. Under the condition of a fixed via spacing rule of 3 mm, a
typical G/A logic cell occupies a layout area of 81 mm because
there are nine vias in each logic cell, as shown in Fig. 12. On
the other hand, the area of logic cell of SOTG is only 36 mm
although the SOTG cell contains more transistors than in G/A.
In UCLP, the logic cell area is determined by the number of vias;
in fact, the transistor area for a conventional G/A cell occupies
only 6% of the total cell area. Fig. 13(a) indicates the number oftransistors in various logic functions. The number of transistors
in the SOTG tends to be more than that in the G/A except in a
few functions such as a multiplexer and a latch. In contrast, thearea required for logic functions in SOTG are less than those in
G/A in each function shown in Fig. 13(b). The results indicatethat SOTG can reduce the area of logic cells by 11% (for INV
and NAND) and up to 85% (MUX) for the UCLP, comparedwith a typical G/A architecture.
Fig. 14 shows an area comparison for the ISCAS89 s27
benchmark circuit [7]. If no misalignment by an off-the-shelf
printer is accepted, (i.e., the via extensions in pads are 0 mm),
a 1.8-mm via and pad pitch can be achieved, and as a result theareas of G/A and SOTG are comparable. The area of SOTG
tends towards a constant with the pad pitch below 2.4 mm asshown in Fig. 14. However, as shown in Fig. 14 the SOTG has

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289

Fig. 15. Photograph of the 82 8 SOTG cell array.

Fig. 16. Measured static characteristics of the SOTG unit cell.

Fig. 13. Comparison on various logic functions. (a) Number of transistors.
(b) Area.

available. In practical use ESD protection must be considered.
However we make the observation that the SOTG requires
only one ESD protection device in each logic cell while theconventional G/A architecture requires three devices for their
inputs.
IV. EXPERIMENTAL RESULTS

Fig. 14. Area comparison of ISCAS89 s27 benchmark circuit implementation.

an advantage when the UCLP is constrained to accept larger
misalignments, since the area efficiency of SOTG improvescompared with G/A. In this work, the area of s27 can be reducedby 53% for a 3-mm pad/via pitch.
The ESD requirements for organic transistors are not addressed in this paper because this type of logic circuit was not

Fig. 15 shows a photograph of the 8 8 SOTG cell array anddetails of a single SOTG cell. The sizes of the 8 8 SOTG cellarray and the single SOTG cell are 73 mm square and 6 mm
square, respectively. The minimum design rule of the SOTG is
20 m.
Fig. 16 shows the measured SOTG cell static characteristics, which is a typical value of the supply voltage
at 2.5-V
for the organic CMOS. The single SOTG cell can operate asboth an inverter and a buffer. The inverter gain is 44 while theamplifier/buffer gain is 101. These results show sufficient gains
to be used for logic circuit implementation.
In order to evaluate signal attenuation due to the printed interconnects on the paper, the open drain pMOS LED driver withthree printed interconnects shown in Fig. 17(a) is measured at. Fig. 17(b) shows the measured waveform in the
2.5-V
case with conventional metallic interconnects for reference; in.
this case the output swing is around 2.0 V with 2.5-V
Fig. 17(c) shows the output waveform from the proposed printed
interconnects on the paper. Although the output swing is slightly

290IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1, JANUARY 2011

Fig. 17. Measured waveform of organic transistor through the printed interconnects. (a) Measurement circuit. (b) Output waveform with metallic interconnects.
(c) Output waveform with printed interconnects.

Fig. 19. Measurement result of SOTG-based ring oscillator. (a) Measurement
circuit. (b) Photograph of the ring oscillator. (c) Measured waveform.
Fig. 18. Measurement waveform of SOTG-based two-input multiplexer.
(a) Measurement circuit. (b) Measured waveforms.

degraded due to the printed interconnects, it is acceptable because the driver can drive low-power LEDs and logic gates of
the SOTG.
In order to demonstrate the functionality of the proposed
SOTG cell, Fig. 18(a) shows the measured schematic of a
two-input multiplexer using the SOTG logic cell. 3-V
is applied in the measurement. Square waves of 200 mHz are
applied to the select signal, S, and square waves of 800 mHz
are applied to input terminal A. Input terminal B is connected. Fig. 18(b) shows measured waveforms. The resulttoconfirm that the organic CMOS transmission gates successfully
conduct both high and low signals, and therefore, the feasibilityof the SOTG architecture is verified by measurement.
In order to measure the propagation delay of the SOTG logic
cell, a ring oscillator using three organic SOTG logic cells
was fabricated on a polyimide substrate. Fig. 19(a) shows theschematic and Fig. 19(b) shows the chip photograph. Since theoperating speed of organic circuits is slow, a three-stage ringoscillator gives a very low-frequency oscillation. Although the, the measurement
oscillator can operate from 2.0 to 3.0 V
of 2 V to measure the maximum propais carried out at
gation delay. The measured frequency is 3.1 Hz atof 2
V, that is, the propagation delay of each logic cell is 0.11 s asshown in Fig. 19(c). The speed is limited by the mobility andparasitic gate capacitance of the nMOS devices. With wider
transistors, the output driving capability will increase; however,the speed will not. The slow transistor speed is appropriate foreducational purposes, because the LED driven by the output
pulse flashes at visible (observable) speed.
From the measurements, the output swings of SOTG cells
are slightly degraded either because of the relatively high resistance of printed interconnects as shown in Fig. 17, or the limited
driving capability of the transmission gate as shown in Fig. 18.
This degradation limits the number of gate stages in practicalcircuits. In this study, the transistor area occupies only 19% ofISHIDA et al.: UCLP WITH SOTG OF 2-V ORGANIC CMOS AND INK-JET PRINTED INTERCONNECTS

TABLE IKEY FEATURES OF THE INK-JET PRINTED INTERCONNECTS,
2 V ORGANIC CMOS, AND SOTG

291

[4] H. Klauk, U. Zschieschang, J. Pflaum, and M. Halik, “Ultralow-powerorganic complementary circuits,” Nature, vol. 445, pp. 745–748, Feb.
2007.
[5] K. Ishida, N. Masunaga, Z. Zhou, T. Yasufuku, T. Sekitani, U.
Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai,“Stretchable EMI measurement sheet with 8
8 coil array, 2 Vorganic CMOS decoder, and 0.18 m silicon CMOS LSIs for electricand magnetic field detection,” IEEE J. Solid-State Circuits, vol. 45,
no. 1, pp. 249–259, Jan. 2010.
[6] S. Akers, “Binary decision diagrams,” IEEE Trans. Computers, vol.
C-27, no. 6, pp. 509–516, Jun. 1978.
[7] F. Brglez, D. Bryan, and K. Kozminski, “Combinational profilesof sequential benchmark circuits,” in Proc. ISCAS, May 1989, pp.
1929–1934.

2

the total SOTG cell area; this transistor area was chosen by considering the process yield. However to enhance the driving capability and increase the number of possible stages, wider transistors are recommended for use in a practical UCLP.
The total power consumption of an 8 8 SOTG cell arraycan be estimated as follows. Each transistor in the unit cell has
a parasitic capacitance of 21 pF. The total parasitic capacitancepF. When the 64 cells
in the unit cell is given by
operate at 10 Hz with 3 V, the total power consumption ofan 8 8 SOTG is given by

The key features of the ink-jet printed interconnects, 2-V organic CMOS, and SOTG are summarized in Table I.

Koichi Ishida (S’00–M’06) received the B.S. degree
in electronics engineering from the University ofElectro-Communications, Tokyo, Japan, in 1998,
and received the M.S. and Ph.D. degrees in electronics engineering from the University of Tokyo,
Tokyo, Japan, in 2002 and 2005, respectively.
He joined Nippon Avionics Co., Ltd. Yokohama,Japan, in 1989, where he developed high-reliability
hybrid microcircuits applied to aerospace programs.
Since July 2007, he has been working at the Instituteof Industrial Science, University of Tokyo, as a
research associate. His research interests include low-voltage low-power
CMOS analog circuits, RF wireless communication circuits, and on-chip power
supplies.
Dr. Ishida is a member of IEICE.

Naoki Masunaga received the B.S. and M.S. degrees
in electronic engineering from Sophia University,
Tokyo, Japan, and the University of Tokyo, Tokyo,
Japan, in 2008 and 2010, respectively.
He is now with Terumo Corporation. His researchinterests are in the field of integrated circuit design.

V. CONCLUSION
This paper has presented a UCLP with a SOTG of 2-V organic CMOS transistors, to enable users to fabricate custom integrated circuits by printing 200- m wide interconnects with
ink-jet printers. Applications include prototyping of large-area
electronics and educational purposes.
The proposed SOTG architecture reduces the area of the circuits in UCLP by between 11% and 85% compared to a conventional G/A architecture. This type of technology will provide ways to add programmability for integrated circuits used inlarge-area electronics, and is a step toward manufacturing ICs athome with an off-the-shelf printer.

Ryo Takahashi received the B.S. degree in electricaland electronic engineering from Tokyo Institute ofTechnology, Tokyo, Japan, in 2009. He is currently
studying in the graduate school of Electrical Engineering at the University of Tokyo.
His research interests are in the field of integrated
circuit design.

REFERENCES[1] M. Böhm, A. Ullmann, D. Zipperer, A. Knobloch, W. H. Glauert, and
W. Fix, “Printable electronics for polymer RFID applications,” in IEEE
ISSCC Dig. Tech. Papers, Feb. 2006, pp. 270–271.
[2] L. Liu, M. Takamiya, T. Sekitani, Y. Noguchi, S. Nakano, K. Zaitsu,
T. Kuroda, T. Someya, and T. Sakurai, “A 107 pJ/b 100 kb/s 0.18 m
capacitive-coupling transceiver for printable communication sheet,” inIEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 292–293.
[3] K. Ishida, N. Masunaga, R. Takahashi, T. Sekitani, S. Shino, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, “User
Customizable Logic Paper (UCLP) with organic Sea-of TransmissionGates (SOTG) architecture and ink-jet printed interconnects,” in IEEE
ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2010, pp. 138–139.

Tsuyoshi Sekitani was born in Yamaguchi, Japan,
in 1977. He received the B.S. degree from Osaka
University, Japan, and the Ph.D. degree in applied
physics from the University of Tokyo, Japan, in 1999
and 2003, respectively.
From 1999 to 2003, he was with the Institute for
Solid State Physics (ISSP), University of Tokyo.
From 2003 to 2009, he was a Research Associate of
the Quantum-Phase Electronics Center, Universityof Tokyo. Since 2010, he has been an Assistant Professor in the Department of Electrical and Electronic
Engineering, University of Tokyo.

292IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1, JANUARY 2011

Shigeki Shino received the B.S. and M.S. degrees infunctional polymer science from Shinshu University,
Japan, in 1989 and 1991, respectively.
In 1991, he joined Mitsubishi Paper Mills Ltd.
where he is currently working on the developmentof silver nanoparticle inks and micro-porous layers.
He is a deputy general manager of the imaging anddevelopment company.

Ute Zschieschang received the Dipl.-Ing. from
Oberflächentechnik, Fachhochschule Mittweida in
2000, and the Dr. rer. nat. from Technische Universität Bergakademie Freiberg, Germany, in 2006.
In 2005, she joined the Max Planck Institute for
Solid State Research, Stuttgart, Germany.

Hagen Klauk received the Diplom-Ingenieur degree
in electrical engineering from Chemnitz Universityof Technology, Germany, in 1995, and the Ph.D. degree in electrical engineering from the Pennsylvania
State University, University Park, in 1999.
From 2000 to 2005 he was with the Polymer Electronics group at Infineon Technologies, Erlangen,Germany. In 2005 he joined the Max Planck Institutefor Solid State Research, Stuttgart, Germany, to leadan Independent Junior Research Group in organic
electronics.

Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995, 1997,
and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high-speed
digital LSIs. In 2005, he joined the University ofTokyo, Japan, where he is an Associate Professor
of VLSI Design and Education Center. His researchinterests include the circuit design of the low-power
RF circuits, the ultra low-voltage digital circuits, andthe large area electronics with organic transistors.
Dr. Takamiya is a member of the technical program committee for IEEE
Symposium on VLSI Circuits and IEEE Custom Integrated Circuits Conference(CICC).

Takao Someya (M’03) received the Ph.D. degree inelectrical engineering from the University of Tokyo,
Tokyo, Japan, in 1997.
In 1997, he joined the Institute of Industrial Science (IIS), University of Tokyo, as a Research Associate and was appointed to be a Lecturer of the Research Center for Advanced Science and Technology(RCAST), University of Tokyo, in 1998, and an Associate Professor of RCAST in 2002. From 2001 to
2003, he worked for the Nanocenter (NSEC) of Columbia University and Bell Labs, Lucent Technologies, as a Visiting Scholar. From 2003 to 2009, he was an Associate Professor
in the Department of Applied Physics and Quantum-Phase Electronics Center,
University of Tokyo. Since 2009, he has been a Professor of Electrical and Electronic Engineering, University of Tokyo. His current research interests include
organic transistors, flexible electronics, plastic integrated circuits, large-area
sensors, and plastic actuators.
Prof. Someya is a member of the IEEE Electron Devices Society, the Materials Research Society (MRS), and the Japanese Society of Applied Physics. He
serves as a subcommittee member for IEEE/IEDM and a program co-chair forthe 3rd Organic Microelectronics Workshop.

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan, in 1981.
In 1981 he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and SoC Solutions. He has worked extensively
on interconnect delay and capacitance modelingknown as Sakurai model and alpha power-law MOS
model. From 1988 through 1990, he was a Visiting
Researcher at the University of California Berkeley,
where he conducted research in the field of VLSICAD. From 1996, he has been a professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic IC’s and large-area electronics. He has published morethan 400 technical publications including 100 invited presentations and several
books and filed more than 200 patents.
Dr. Sakurai will be an executive committee chair for VLSI Symposia and asteering committee chair for IEEE A-SSCC from 2010. He served as a conference chair for the Symposium on VLSI Circuits, and ICICDT, a vice chair
for ASPDAC, a TPC chair for the A-SSCC, and VLSI symp., an executive
committee member for ISLPED and a program committee member for ISSCC,
CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international
conferences. He is a recipient of 2010 IEEE Donald O. Pederson Award in
Solid-State Circuits, 2010 IEEE Paul Rappaport award, 2010 IEICE Electronics
Society Award, 2009 Achievement Award of IEICE, 2005 IEEE ICICDT award,
2004 IEEE Takuo Sugano Award and 2005 P&I patent of the year award andfour product awards. He gave keynote speech at more than 50 conferences including ISSCC, ESSCIRC and ISLPED. He was an elected AdCom member
for the IEEE Solid-State Circuits Society and an IEEE CAS and SSCS distinguished lecturer. He is a STARC Fellow and an IEICE Fellow.