Medium-term Management Plan (abridged version)
July 12, 2022
SEMICON West 2022 IR Meeting

SEMICON West 2022 IR Meeting / July 12, 2022

1

Forward Looking Statements
 Disclaimer regarding forward-looking statements
Forward-looking statements with respect to TEL’s business plan, prospects and other such information are based on
information available at the time of publication. Actual performance and results may differ significantly from thebusiness plan described here due to changes in various external and internal factors, including the economic
situation, semiconductor/FPD market conditions, intensification of sales competition, safety and product quality
management, intellectual property-related risks, and impacts from COVID-19.
 Processing of numbers
For the amount listed, because fractions are rounded down, there may be the cases where the total for certain
account titles does not correspond to the sum of the respective figures for account titles. Percentages are calculatedusing full amounts, before rounding.
 Exchange risk
In principle, export sales of Tokyo Electron’s mainstay semiconductor and FPD production equipment are
denominated in yen. Although some sales and expenses are denominated in foreign currencies, the impact of
exchange rate fluctuations on profits is negligible.

FPD: Flat panel display
SEMICON West 2022 IR Meeting / July 12, 20222

Medium-term Management Plan Briefing 2022 Program and Participants Presentation– The New Medium-term Management Plan
– Technology trends and TEL™’s business opportunities– SPE Business Strategy

Toshiki Kawai
Akihisa Sekiguchi
Yoshinobu Mitano Q&A Session

SEMICON West 2022 IR Meeting / July 12, 2022

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The New Medium-term Management Plan
July 12, 2022
Toshiki Kawai
Representative Director, President & CEO

SEMICON West 2022 IR Meeting / July 12, 2022

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FY’22 Financial Highlights
Net Sales andGross Profit Margin
Net sales
Sales (\B)
(¥B)
2,000

Gross profit margin

41.2%

2,003.8(\B)
Operating income (¥B)

50.0%

600

500
40.0%

24.3%

1,399.1

21.0%

1,278.2

40.0%

30.1%

22.9%

30.0%

26.5%
248.2

320.6

310.5

30.0%

437.0

37.2%

400

1,127.2

1,200

Net親会社株主に帰属する
income attributable to系列1ownersof parent
(¥B)
当期純利益
(億円)
ROE

29.9%

40.4%

1,600

599.2

Operating margin

45.5%
40.1%

Net Income Attributable to
Owners of Parent and ROE

Operating Income andOperating Margin

21.8%

242.9
20.0%

300

185.2

237.2

800
200
20.0%

10.0%

400
100

0

10.0%

FY'19

FY'20

FY'21

FY'22

0

0.0%

FY'19

FY'20

FY'21

FY'22

FY'19

FY'20

FY'21

FY'22

Net sales, gross profit margin, operating margin and ROE reached record high
SEMICON West 2022 IR Meeting / July 12, 20225

Performance of Growth Investments Made Over the Past Five Years
Miyagi logistics building(Began operation in 2018)

Iwate production building Yamanashi production building(Began operation in 2020)(Began operation in 2020)(Billion Yen)

200

100

0

R&D expenses
97.1

FY'18

113.9

120.2

FY'19

FY'20

136.6

FY'21

158.2

FY'22

Miyagi No.2 development bldg. TEL Digital Design Square(Billion Yen)

100

50

0

54.6

49.7
20.6

FY'18

(Began operation in 2018)

Depreciation

Capex
45.6

Production capacity doubled Production capacity doubled Production capacity 1.5 times

24.3

FY'19

FY'20

(Began operation in 2021)

57.2

53.8
29.1

(Began operation in 2020)

Miyagi Technology
Innovation Center

33.8

FY'21

36.7

FY'22

Invested on increases in production capacity, enhancement of development
capabilities, advancement of DX, and partnerships with suppliers
SEMICON West 2022 IR Meeting / July 12, 2022

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Progress on the Medium-term Management Plan
Announced on May 2019

Financial Model (by FY'24)

FY’22 Actual

Net sales

1.5T yen 1.7T yen 2T yen

2T 3.8B yen

OP margin

26.5%

ROE

28%
>30%

>30%

29.9%
37.2%

Reached our financial model 2 years ahead of schedule
SEMICON West 2022 IR Meeting / July 12, 2022

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Background of the Achievement of the Medium-termManagement Plan Two Years Ahead of Schedule Continued to invest in R&D even during the market adjustment period whensales declined Collaborated closely with many of technologically advanced suppliers locatedaround our plants, created differentiated technology, and worked together toovercome disruptions in procurement and logistics
 TEL employees with a spirit of challenge responded to the changing
environment amid the strict lockdown and travel restrictions imposed by
COVID-19
SEMICON West 2022 IR Meeting / July 12, 2022

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The New Medium-term Management Plan
- Business Environment- Overview of the New Medium-term Management Plan

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Annual average growth rate

Global Data Traffic

Data volume will increase26%

100x in 20 years
CAGR

Zetta byte*

Datacentric

35
30

CAGR 26%(2020-2040)(2020-2030)

25
20

Computercentric15

Bit-based

Mobilecentriccomputers

10

Quantum Brain-inspired

5

computers

computers

0

1990

2000

2010

2020

2030

2040

Source : Omdia

The digitization of society has only just begun.
Computing evolves into the true big data era
SEMICON West 2022 IR Meeting / July 12, 2022

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Outlook for the Semiconductor Market
US$ trillion>$1.35 trillion

1.2
1.0

Products × Value

Products(electronic devices)

0.8(services)

0.6$555.9 billion

Data centers

0.4(2021)

Smartphones

PC

0.2

Services for industry
Source:1990-2021 (WSTS)
2022-2030 (IBS, May 2022)

Services for consumers

0.0
1990

2000

2010

2020

2030

Growing to more than double by 2030
SEMICON West 2022 IR Meeting / July 12, 2022

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WFE* Market

ICT・DX・decarbonization,
electric vehicles, autonomous
driving, post-5G

Data center$50~65B

Mobile$30~40B

PC
$20B
$~10B
1985

1990

1995

2000

2005

2010

2015

2020

2025

2030

Source：TechInsights Manufacturing Analysis Inc. (VLSI) (1985-2021)

WFE Market will grow further with progress ofdigitalization and evolution of semiconductors
SEMICON West 2022 IR Meeting / July 12, 2022

*WFE (Wafer fab equipment): Wafer fab equipment refers to the production equipmentused in front-end production and in wafer-level packaging production.

12

The New Medium-term Management Plan : Financial Targets

Financial Targets (by FY’27)

Net sales≥ 3 trillion yen

OP margin

≥ 35%

ROE

≥ 30%

SEMICON West 2022 IR Meeting / July 12, 202213

Big Global Trends“In order to build a strong and resilient society
in which economic activities do not stop
under any circumstances”

Pushing firmly ahead with the implementation of ICT*Taking action to realize a carbon-free society

SEMICON West 2022 IR Meeting / July 12, 2022

* ICT : Information and Communication Technology

14Increasing Importance of Semiconductors

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Taking Advantage of TEL’s Strengths

Only
one
Deposition

Coater/developer

Etching

Cleaning

Have products in 4 sequential processes
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Taking Advantage of TEL’s Strengths

100%
Coater/developer

EUV lithography

100% share of coater/developer for EUV lithography
EUV: Extreme Ultraviolet
SEMICON West 2022 IR Meeting / July 12, 2022

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Taking Advantage of TEL’s Strengths

Major products and market position*

1#

Coater/developer#

2

Cleaning

2

1

1

1

2

1

#

#

#

#

#

#

Plasmaetch

Gaschemicaletch

Diffusion
furnaceBatchdeposition

Metal
deposition

Prober*TEL estimate

Products with the world's No.1 or No.2 market share
SEMICON West 2022 IR Meeting / July 12, 2022

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Taking Advantage of TEL’s Strengths
Industry’s largest install baseNo.1

82,000 units

Field Solution Sales

455.9B yen
400

300

Annual increase by about

6,000 units

362.3
288.2
251.0

304.8

200

100

0

FY’ 18 19 20 21 22

Equipment sold creates new business opportunities
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Every leading-edge semiconductorin the world passes through our equipment

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Profit is an important measure of value
in our products and services

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Further improving strengths

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Continue to Invest Aggressively on R&D

More than 1 trillion
yen planned for
5 years from FY’23

About 600 billion yen

FY’ 18

19

20

21

22

23

24

25

26

27

Continue active investment in growth tocreate high value-added next-generation products
SEMICON West 2022 IR Meeting / July 12, 2022

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FY60thSEMICON West 2022 IR Meeting / July 12, 2022

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New Vision
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New Vision
A company filled with dreams and vitality that contributes totechnological innovation in semiconductors
Tokyo Electron pursues technological innovation in semiconductors that supports the sustainable development of the world.
We aim for medium- to long-term profit expansion and continuous corporate value enhancement by utilizing our expertise tocontinuously create high value-added leading-edge equipment and technical services.
Our corporate growth is enabled by people, and our employees both create and fulfill company values. We work to realize
this vision through engagement with our stakeholders.

Corporate Message

SEMICON West 2022 IR Meeting / July 12, 2022

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TSV : TEL’s Shared Value
CSV (Creating Shared Value)
The concept is to create social and economic value by leveraging corporate expertise to solve
social issues, thereby enhancing corporate value and achieving sustainable growth.

TEL’s CSVTSV

TEL’s Shared ValueContributing to technological innovation in semiconductors
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Approaches to Sustainability

Environmental Co-Creation by Material, Process and Subcomponent Solutions

Semiconductors

Production equipment

Business activities

Pursuing higher device
performance and lower power
consumption

Achieving both high process
performance and environmental
performance of the equipment

Reduction of CO2 emissions inall business activities

Promoting technological innovation of semiconductors andreducing environmental impact throughout the supply chain
SEMICON West 2022 IR Meeting / July 12, 2022

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Aiming for Sustainable Development of the WorldNet Zero
Scope 1 & 2

To be achieved by 2040

Scope 3To be achieved by 2050

SEMICON West 2022 IR Meeting / July 12, 2022

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SEMICON West 2022 IR Meeting / July 12, 202230

Technology trends and TEL’s business opportunities
July 12, 2022
Akihisa Sekiguchi, Ph.D.
Fellow, Corporate Innovation Division

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Overview
 Development Trends for Key Devices Technology Trends and Business Opportunities– Logic– DRAM– NAND– CMOS Image Sensor

 Summary

SEMICON West 2022 IR Meeting / July 12, 202232

Development Trends for Key Devices

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Semiconductor Devices: Direction of Development
Logic

NAND

DRAM

CIS

Through miniaturization withstructural changes

Through high stacking

Through miniaturization

Through miniaturization

Through new structures

Through new structures,new materials

・Lowered cost per transistor
・Lower power consumption・Higher speed

・Lower cost per bit

・Lower cost per bit
・Lower power consumption・Higher speed

・Lower cost per bit
SEMICON West 2022 IR Meeting / July 12, 2022

・Increased number of pixels
・Higher speed

・Greater image quality

34

Logic Trends and Business Opportunities

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Advances in Smartphone CPUs
Product Year

2014

2020

Tech. Node

20nm

5nm

Transistor

Last Gen. Planar

4th Gen. FinFET

Adv. Litho

ArFi

EUV

Die Size

89mm2

88mm2

Transistor#

2B

CPU Cores#

2

GPU Cores#

4

NPU Cores#

N/A

L2/L3 Cache

5MB

×5.9

11.8B
6

New architecture
Many cores
New function

4
16

×5.6

28MB

Source: Wikipedia https://en.wikipedia.org/wiki/Apple_A14 https://en.wikipedia.org/wiki/Apple_A8
https://en.wikipedia.org/wiki/Ampere_(microarchitecture)

With advances in transistor fabrication, materials and lithography,
can improve integration by increasing transistor numbers, expanding functions, etc.
SEMICON West 2022 IR Meeting / July 12, 2022

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Advances in GPU (Operational Accelerator)
Product Year

2016

2020

Tech. Node

16nm

7nm

Transistor

1st Gen. FinFET+

3rd Gen. FinFET

Adv. Litho

ArFi

ArFi

Die Size

610mm2826mm2

Transistor#

15.3B

INT32/FP32
Mixed Cores#

3584

FP64 Cores#

1792

L1/L2 Cache

5.440MB

×3.5

54.2B
6912

New architecture
Many cores
New function

3456

×11.3

61.696MB

Source: Wikipedia https://en.wikipedia.org/wiki/Apple_A14 https://en.wikipedia.org/wiki/Apple_A8
https://en.wikipedia.org/wiki/Ampere_(microarchitecture)

Number of transistors increasing in HPC too, visible trend toward expansion of functions
Higher integration also sought
CORP IR / October 12, 2021

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Advances in Logic Integration Density
Pitch shrink
Key enablers

Shrink

EUV patterning
Small area gap fillingHigh selective etch
Pattern collapse free drying

Further advances in lithography, etch, thin film depositionand cleaning technologies needed for miniaturization
SEMICON West 2022 IR Meeting / July 12, 2022

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Advances in Logic Integration Density
Design Technology Co-optimization: DTCO
① Cell height scaling: Fin depopulation, Metal track# reduction

Key enablers






ShrinkNarrow, straight etch
Loading free recess etch
Fin capping to prevent oxidation
Low resistance silicide, metal② Cell width scaling: Single Diffusion Break, Contact Over Active Gate etc.
Contact PlugContact Over Active Gate
Standard Gate ContactKey enablers

Small hole, trench etch
Low stress gap fillingMulti-color films for etch
High selective etch

Further advances in process technology for DTCO sought
SEMICON West 2022 IR Meeting / July 12, 2022

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Logic Technology Roadmap: Generic
Source: TEL estimatesYear of HVM(20k/month)

2020

2022

2024

2026

2028

2030

2032

Node

N5

N3

N2

N1.4

N1

N0.7

N0.5

2 Fin

2~1 Fin

GAA NS

Forksheet

CFET

2nd Gen. CFET
IL/HK

DeviceIL/HK
2D material: TMDC
MoS2, WS2, MoSe2, WSe2 etc.

Poly pitch (PP)

51

45

42

39

36

33

30

Min. MP [nm]

28

22

20

18

16

12

12

Cell height (CH)

210 (2Fin)

162 (2Fin)

120 (NS)

90 (NS)

64 (CFET)

48 (CFET)

36 (CFET)

Density (a.u.)
PP x CH x DTCO*

1

1.69(vs. N5)

1.66(vs. N3)

1.65(vs. N2)

1.75(vs. N1.4)

1.67(vs. N1.0)

1.69(vs. N0.7)

EUVHigh m channel

Mix cell

4-Track cell

Hetero channel
New alloy

2D material

Scaling booster

Backside PDN High NA EUV
Subtractive Ru*Design Technology Co-Optimization:
Assume new knob will be created in each node for 1.15X

1.6-1.8x increase in logic density along with pitch scaling, DTCO and scaling booster
SEMICON West 2022 IR Meeting / July 12, 2022

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GAA Nanosheet Device (Gate All Around Nanosheet)Lay down

FinFET

Nanosheet

Patterning defined Fin width: 3s 1.1nm*

Si EPI thickness defined sheet thickness: 3s 0.4nm**Source: SC Song (Qualcomm) et al. VLSI 2019

Improved controllability of channel width by nanosheet structure, increased channel width
through stacking  Low leak, high on current
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GAA Device Process Flow
FinFETGAA FET

Source: TEL

TEL’s wafer fab equipment is essential for creating complex GAA structures
SEMICON West 2022 IR Meeting / July 12, 202242

2 nm GAA Technology

Cross section TEM of 2nm GAA device courtesy of IBM Research

TEL’s wafer fab equipment is essential for creating complex GAA structures
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GAA Related Process Modules
Mold stack & Etch

Inner spacer
Gate spacer

Nanosheet release

Replacement gate

Inner spacer

Si/SiGe

Sac film

STI Liner
・SiGe/Si: Defect free, Uniform EPI・Trench etch: Vertical profile
・STI Liner: Prevent oxidation
・STI OX: Low temp.
・STI recess: Loading less・Fin recess: Vertical profile
・Indent etch: Loading less・Inner spacer dep: Low-k (k<5)
・Inner spacer etch: High selective

・Full channel etch: High selective

・Reliability Si etch: High selective
・Advanced drying: Collapse free・Sac film: Conformal
・WFM/Dipole film: Conformal
・WFM/Dipole etch: High selective

Source: TEL

Offering new solutions for critical modules in nanosheet devices
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GAA Related Process Modules
Mold stack & Etch

Inner spacer

Nanosheet release

Replacement gate

R. Ritzenthaler (imec) et al., iedm 2018

N. Loubet (IBM) et al., iedm 2019

N. Loubet (IBM) et al., iedm 2019

Source: TEL・SiGe/Si: Defect free, Uniform EPI・Trench etch: Vertical profile
・STI Liner: Prevent oxidation
・STI OX: Low temp.
・STI recess: Loading less・Fin recess: Vertical profile
・Indent etch: Loading less・Inner spacer dep: Low-k (k<5)
・Inner spacer etch: High selective

・Full channel etch: High selective

・Reliability Si etch: High selective
・Advanced drying: Collapse free・Sac film: Conformal
・WFM/Dipole film: Conformal
・WFM/Dipole etch: High selective

Key points are preventing oxidation of Si/SiGe trench, high selectivity andprecisely controllable SiGe etch, and preventing pattern collapse
SEMICON West 2022 IR Meeting / July 12, 2022

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Miniaturization: EUV Lithography Technology Challenges
PerformanceLine : LER, Pinching, Bridge

Stochastic noise

Pinching

ArF

EUV

ArF

EUV

BridgeHole : L-CDU, Kissing, Missing• The number of EUV photons is only 1/14 compared to ArF at the same dose.
• Photon absorption of EUV resist is lower than that of ArF resist.
• These cause large edge roughness, resulting in one of the sources ofpattern defects.

Kissing

Missing

Source: S. Morikita, et al., Tokyo Electron Miyagi(DPS2018)

Resist stack and etching co-optimization necessary
for realizing high productivity, precise control and low defects
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Global Development Facilities

TEL Magnetic Solutions (Ireland)
Imec (Belgium)
CEA-Leti (France)(As of June 1, 2021)

TEL Manufacturing andEngineering of America

TEL Technology
Center, America

TEL Technology
Center Korea

CNSE
BRIDG
Tokyo Electron Technology Solutions
Tokyo Electron Kyushu
Tokyo Electron Miyagi
National Institute of Advanced Industrial
Science and Technology

IME(Singapore)

Tokyo Electron Development Sites
Consortiums

SEMICON West 2022 IR Meeting / July 12, 2022

TEL Technology
Center, Taiwan

47

15 nm Pitch L/S Fabrication Using EUV SADP
Demonstrated on TEL tools

Litho Pitch: 30nm
CDSEM CG6300
512*512/250k

Lithography

Trilayer + Plasma
Treatment

Tone Inversion

MandrelSEMP

CD: 14.7nm
LER: 2.25nm

LER: 2.0nm
CD: 16.1nm

CD: 15.6nm
LER: 1.89nm

CD: 10.6nm
LER: 1.71nm

CD: 7.7nm
LER: 1.57nm-11%Source: Eric Liu et al., TEL Technology Center,
America SPIE 2021 Advance Lithography

-24%

-30%
Achieve industry-leading 15 nm pitch line and space pattern
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Back End: Wafer Bonding and Thinning Technology for CFET
CFET
Upside down(Top tier wafer)

Wafer bonding Wafer thinning Top transistor
process

Low distortion wafer-to-wafer bonding technology and substrate film thinning technology
are necessary for scaling booster technology
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Back End: Wafer Bonding and Thinning Technology for BSPDN
Backside PDN
BEOL(Front side)

Wafer bonding

Upside down

BEOL
(Back side)

Wafer thinning

Low distortion wafer-to-wafer bonding technology and substrate film thinning technology
are necessary for scaling booster technology
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Wafer Bonding System

 Synapse™ Si– Integrate high high-productivity platform cultivatedin the front-end process with plasma, cleaning andhigh-accuracy bonding modules– high productivity (uptime ≧ 90%)
• alignment accuracy 3σ ≦ 50nm

High productivity and stable operation are realized at mass production fabs
Contribute to our customers to realize the future of "3D integration"
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Laser Trimming System Ulucus™ L (New release)– Edge trimming on bonded wafer– Latest platform utilizing super clean technology
from the front-end process, with the integration oflaser control technology

Laser technology realizes high accuracy and quality trimming processes, andenvironment-friendly capability through the reduction of DIW usage
SEMICON West 2022 IR Meeting / July 12, 2022

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DRAM Trends and Business Opportunities

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DRAM Structure and Process Flows

Source: TELHigh aspect ratio structure is fabricated with sophisticated patterning technology
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Advances in DRAM for Smartphones
Product Year

2014

2020

Tech. Node

25nm

1ynm

DDR

LPDDR3LPDDR4X

Data Rate

1.333Gbpps

4.266Gbpps

Capacity

1GB(4Gb ×2)

×4 or 6

4GB or 6GB(8Gb or 12Gb×4)

Source: Wikipedia https://en.wikipedia.org/wiki/Apple_A14 https://en.wikipedia.org/wiki/Apple_A8
https://en.wikipedia.org/wiki/Ampere_(microarchitecture)

DRAM

DRAM

Logic

Logic

Package substrate

Integrated Fan-Out

Flip Chip Package on Package

With the increase in data handling volumes, packaging has advancedwith expanded capacity, accelerated processing and further integration
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GPU (Operational Accelerator) and HBM DRAM
Product Year

2016

2020

Capacity

16GB HBM2

×5(HBM2×4)

80GB HBM2e(HBM2e×6)

Source: Wikipedia https://en.wikipedia.org/wiki/Apple_A14 https://en.wikipedia.org/wiki/Apple_A8
https://en.wikipedia.org/wiki/Ampere_(microarchitecture)

HBM

GPU

HBM
Si Interposer• RDL• Passive devices

Package substrate

Cu micro-bump

C4 bump

Data volumes are also increasing in HPC, driving packaging advanceswith increased integration, higher capacity and faster processing
SEMICON West 2022 IR Meeting / July 12, 2022

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DRAM Technology Roadmap
Source: TEL estimatesYear of HVM(20k/month)2020

F* [nm]

16

2021

2022
15~14

2023
13~12

2024

2025
12~11

2026

2027~28≦10<102029~30

6F2
3D

Cell / Peri.
layout*Feature size: STI hp along WL = STI hp / COS(21o)Patterning
Pillar cap. A.R.

Capacitor

193i SAQP, DP (+ EUV)
>40

>45

>50

>55

M. Popovici (imec) et al. IEDM 2018
Schematic by TEL>60

ZAZ CIP
Alternative: STO etc. TiN
Ru
STO
Ru
TiN

Poly SiON
Peri. CMOS

High-k Metal Gate
FinFET

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Key Modules in 3D DRAM
Stack formation

CMOS wafer bonding to enable CbA
CbA

Cell Transistor formation
Capacitor formation
Currently evaluating multiple options
SEMICON West 2022 IR Meeting / July 12, 2022

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NAND Trends and Business Opportunities

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Advances in 3D NAND Bit Density

Source: TEL

Reduced device footprint achieved by allocating logic under memory
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NAND Technology Roadmap
Source: TEL estimatesYear of HVM(20k/month)

2020

Stack

128L

16x~19xL(176)

22x~25xL(240)

28x~32xL(304)

35x~4xxL(368)

41x~45xL
(440)

5xxL
(512)

1 or 222

2

2 or 33

3 or 4

Vertical pitch 50~55nm

45~55nm40~50nm35~45nm35~45nm35~45nm35~40nm

7~8mm

8.5~10.5mm

10~12.5mm

11~14mm

13.5~17m
m

16~20.5mm

18.5~21m
m(~1.6x/3years)
Tier

Memoryheight#of memory
holes b/w slits
Peri. CMOS
(In general)

2022

2023

Poly Si grain CIP

ChannelWL metal

2021

2024

2025

2026

2027

2028

2029

2030

incl. MILC Si

W

W

W

Mo

Mo

Mo

Mo

9

9

9~24

14~24

19 or 24

19 or 24

19 or 24

Under arrayor Next array

Under array

Under arrayor Bonding

Under arrayor Bonding

Under arrayor Bonding

Under arrayor Bonding

Under arrayor Bonding

VerticalPitch#of memory holes b/w slits
SEMICON West 2022 IR Meeting / July 12, 2022

Tier

Vertical pitch61

3D NAND Technology Challenges and Solutions
HARC

Replacement gate: WL

Channel Si

Peri. CMOS bonding

Cell
Bonding
CMOS

Current

Potential

・HARC etch: Pluralization of each・SiN wet etch: High selective
process (multi-level contact/slit/channel, ・Advanced drying: Collapse freeetc.)
・Mo CVD: Low R WL metal

・CVD Si CIP: Large grain size

・Cu hybrid bonding EPI like

Source: TEL

Processing technology advances essential for enabling further high value-add in NAND devices
CORP IR / October 12, 2021

62

CIS Trends and Business Opportunities

SEMICON West 2022 IR Meeting / July 12, 2022

63

CIS Has Expanded Sensor Functions With Onboard AI
Image sensor

Applications

AI

×

=

Hybridization of devices is progressing and creating further added-value
SEMICON West 2022 IR Meeting / July 12, 2022

64

CIS Technology Challenges and Solutions
Wafer bonding:
3D stacked BSI

Deep Trench Isolation:
Pixel scaling

Capacitor:
Global Shutter

Cu Hybrid Bonding

H. Kim (Samsung) et al. ISSCC 2020 Data edit by TEL

・Wafer level Cu to Cu hybrid bonding

・Si deep trench etch: High A.R. etch

・Poly Si gap-fill: Depo-Etch-Depo for void free fill

Jae-kyu Lee (Samsung) et al. ISSCC 2020

Schematic by TEL・Capacitor etch

・Dielectric deposition
・Metal deposition

Increased importance of bonding technology, as well as etch and thin film deposition technology
SEMICON West 2022 IR Meeting / July 12, 2022

65

Summary

SEMICON West 2022 IR Meeting / July 12, 2022

66

Summary Market demands are becoming more complex
 To meet these needs, the evolution of devices is accelerating, including
multifunctional devices
 Most of the heterogeneity can be covered by existing process and systemtechnologies, but technological evolution is also essential
 Technology development must be undertaken in alignment with environmental
issues (SDGs)
 Development of advanced devices leads directly to the SDGs
 TEL's process development is conducted on a worldwide basis, and the company isstrongly promoting the development of leading-edge devices through global
collaboration both internally and externally And what else?
SEMICON West 2022 IR Meeting / July 12, 2022

67

Metaverse

WorkingmemoryAI & Data
processing

StoragememoryImage
sensing

Semiconductor devices enable Metaverse

SPE Business Strategy
July 12, 2022
Yoshinobu Mitano
Corporate Officer, Executive Vice President and General Manager
SPE Business Division

SEMICON West 2022 IR Meeting / July 12, 2022

71

Overview
 WFE Market and Technological Requirements by Application
 SPE Segment Sales Target and Business Opportunities
 Development Efforts– Strengthen R&D Capabilities– Increase in New Product Sales Composition Ratio– Increase Environmental Performance– Increase Efficiency of Equipment Start-up

 Hot Topics– EUV Patterning Technology– Backend Business Strategy

 Summary
SEMICON West 2022 IR Meeting / July 12, 2022

72

WFE Market and Technological Requirements by Application
Technological Requirements
WFE Market Growth (USB$) Logic/foundry：– Scaling along with structural changes
 Reduction in manufacturing cost per transistor
 Lowering power consumption
 Higher performance

92.3

 NAND– Increasing the layer counts
 Reduction in manufacturing cost per bit

 DRAM– Scaling to realize

CY2021DRAM

NVM

CY2026
Logic/foundry

SEMICON West 2022 IR Meeting / July 12, 2022

 Reduction in manufacturing cost per bit Lowering power consumption
 Higher performance

WLP/FA73

SPE Segment Sales Target and Business Opportunities
SPE New Equipment Sales Target ($B)

Business Opportunities
 Logic/foundry

Coarter/developer
Etch≥ 2,300.0

Deposition
Cleaning– Increase patterning complexity requires cooptimization between unit processes

Wafer prober– Adoption of High-NA EUV lithography

Others– Adoption of GAA and backside PDN
1,499.0

 NAND– 3D NAND layer counts reach more than 300 layers– High aspect ratio etch, high productivity sacrificial film
removal and atomic-level deposition on 3D structure DRAM– Technology to suppress RC delay in wiring
FY2022

FY2027

SEMICON West 2022 IR Meeting / July 12, 2022

– Capacitor formation technology for further scaling74

Development Efforts
Simultaneous 4-Generation Developments

 Align long-term technology roadmap with customers
 Simultaneously develop and evaluate technologies
up to 4 generations ahead

Demo evaluation (TEL)POR
N+1 Development
Evaluation system

Demo Evaluation(Customer
Environment)

HVM

introduction
Mass Production POR

 Demonstrate process performance on customer
structured wafers at customer’s environments atearly stage Create high value-added products and acquire
PORs

Demo evaluation (TEL)

N+2Development POR
Evaluation system
introduction

Demo Evaluation(Customer Environment)

HVM

Mass Production POR

Demo evaluation (TEL)

N+3Development POR
Evaluation system
introduction

Demo Evaluation(Customer Environment)

HVM

Mass Production POR

Demo evaluation (TEL)

N+4Development POR
Evaluation system
introduction

Demo Evaluation(Customer Environment)

HVM

Mass Production POR

SEMICON West 2022 IR Meeting / July 12, 2022

75

Strengthen R&D Capabilities
Yamanashi R&D building
Deposition system, gas chemical etch system,
corporate R&D

Kumamoto R&D building

Miyagi R&D building

Coater/Developers, surface preparation system

Etch system(Completion scheduled for fall 2024)(Completion scheduled for spring 2025)(Completion scheduled for spring 2023)

Miyagi Technology Innovation Center

TEL Digital Design Square

Etch system

DX, Software(Began operation in Oct. 2021)(Began operation in Nov. 2020)

SEMICON West 2022 IR Meeting / July 12, 2022

76

Increase in New Product Sales Composition Ratio
Deposition system sales
for advanced logic/foundry customers

New Products
Existing Products*New products: Products newly
adopted from N+1 generation

FY2023

FY2024FY2025

FY2026FY2027

The proportion of high value-added products will increase.
Contribute to enhancing sales, profits and market share
SEMICON West 2022 IR Meeting / July 12, 2022

77

Increase Environmental Performance
Cleaning system
Productivity

Tool footprint

DIW Consumption(WPH/system)(m2)(K ton)DIW supply & waste
Management Cost
(¥M)

×2.7

Exisiting
Product-52%

New
Product

Exisiting
Products

New
Products-30%

Exisiting
Products

New
Products

Power
Consumption perwafer (kWh/wafer)-30%

Exisiting
Products

New
Products-46%

Exisiting
Products

New
Products

Environmental performance = equipment performance
Further enhance environmental performance
SEMICON West 2022 IR Meeting / July 12, 2022

78

Increase Efficiency of Equipment Start-up
Equipment start-up time（hour）-50%
Conventional

 Measures：- Optimize inspection items and automate
inspection- Expand online support- DX network tool
- Automatic tool
DX network tool

Automatic tool

After increasing
effciency
EV

Conventional

After increasing effciency

Further enhance customer satisfaction and productivity
SEMICON West 2022 IR Meeting / July 12, 2022

79

Hot Topic 1 : EUV Patterning Technology

SEMICON West 2022 IR Meeting / July 12, 2022

80

CLEAN TRACK™ LITHIUS Pro™ Z EUV : Coater/Developer
LITHIUS Pro Z released in 2012 (Total shipment > 2000 systems)

Releasing new EUV CAR/MOR compatible features

High Reliability
100% market share in in-line coater/developer for EUV

High Productivity
Maximize EUV exposure tool performanceHigh Versatility
LITHIUS Pro Z EUV
Total shipment > 140 systems

Applicable to Metal Oxide Resists and underlayers in
addition to Chemically Amplified Resists

The LITHIUS Pro Z platform, which has a long track record of mass production for
exposure tools with a variety of light sources, has the above three strengths
SEMICON West 2022 IR Meeting / July 12, 2022

81

EUV Lithography Process: Roadmap and Challenges
Line pitch (nm)

34

32

30

28

26

24

22

20

Hole/pillar pitch (nm)

42

40

38

36

34

32

30

28

0.33 NA EUV (Single exposure or multi-patterning)
Roadmap of EUV
exposure equipment
and resist technology
RLS trade off
Sensitivity (S)Resolution (R)CD Variation(L: Line Edge
Roughness)

0.55 NA (High NA) EUV (Single exposure or multi-patterning)
Chemically Amplified Resist (CAR)
Metal Oxide Resist (MOR)
Defects induced by variationin EUV lithography
Bridging

Pinching

Missing

Kissing

P. De Bisschop, Proc. SPIE, 10957-10 (2019)

Issues of securing required resist film thickness

Post-etch
resist damage

Challenges for
Thinning
Resist Film

Resist line
collapse

Resist pillar
collapse

Residue inside hole

Challenges for
Thickening
Resist Film

TEL is providing patterning solutions for the EUV challenges
SEMICON West 2022 IR Meeting / July 12, 2022

82

New Development Method: ESPERT*™ for Pillar Metal Oxide Resist
36 nm pitch 18 nm pillar for DRAM
(after lithography)

Resist collapse with conventional
development technology

Enhanced pillar patterncollapse margin

Local CD
uniformity (3σ)= 1.52 nm

Conventionalwetdevelopment
technology

Newly
developed
development
technology;
ESPERT

CD 18.0 nm

15.1 nm

EUV exposure 99.5 mJ/cm2

86.0 mJ/cm2

Local CD
uniformity (3σ)= 1.47 nm

CD 18.0 nm

15.2 nm

EUV exposure 75.5 mJ/cm2

66.5 mJ/cm2

New wet development technology
prevents resist collapse

Total defects (Normalized)

2
Conventional
wet develop
many collapses
below 19 nm

1

ESPERT™
No collapse

Target CD
19 nm

0
12

Source: TEL, Resist film thickness: 22 nm

14

16 18 20 22
ADI CD (nm)24

ESPERT prevents resist collapse, reduces EUV exposure doseby 25% and decreases CD variations
SEMICON West 2022 IR Meeting / July 12, 2022

*Enhanced Sensitivity Developer Technology

83

New Development Method: ESPERT for L/S Metal Oxide Resist
Roughness and profile @ 30 nm-pitch(after development)
REFERENCE

ESPERT

14.3

Unb.
LER
(nm)
2.2

Unb.
LWR
(nm)
3.0

DCD
(nm)
14.5

Unb.
LER
(nm)
2.2

Open-shorttest patterns

ESPERT

100% yieldwith wide
process
window~30% dose
reduction

DCD
(nm)

Opens and shorts test @ 30 nm-pitch

Unb.
LWR
(nm)
2.9
Source: TEL

Target CD 14.5 nm

Source: TEL/IBM SPIE2022

EUV dose change
ESPERT can tune resist profile

Dose stripe e-test performance(CD 13.2 nm ~ 15.6 nm)

ESPERT on 30 nm pitch L/S shows ~30% dose reduction without roughness penalty.
100% yield data with wide process window were confirmed
SEMICON West 2022 IR Meeting / July 12, 2022

84

Benchmarking Wet MOR and Dry Resist in EUV Lithography#1 (All-in-One)

COT

Wet MOR

PEB
DEV

EUV

TEL/inpria#1

Dry Resist
TEL’s estimate

CVD
PAB

#2

CLEAN

#3

EUV

#4

#5

#6

PEB

2nd PEB/DRY DEV

CLEAN

Dry Resist:• Longer TAT/Q-time• Larger footprint (> 5x?)• Limitation for resist type

TEL’s MOR process provides higher economic/environmental values than Dry Resist
SEMICON West 2022 IR Meeting / July 12, 2022

85

TEL LITHIUS Pro Z for imec-ASML High NA EUV Joint Lab
High NA EUV for higher resolution
 TEL has shipped advanced modules on
TEL CLEAN TRACK LITHIUS Pro Z
for the high NA exposure tool

ASML
EXE:5000 First prototype high NA EUV exposure tool
is available in 2023 at the High NA lab
TEL CLEAN TRACK LITHIUS Pro Z

 A three-year program is planned for the Pre
HVM validation

Courtesy of imec

SEMICON West 2022 IR Meeting / July 12, 2022

86Hot Topic 2 : Backend Business Strategy

SEMICON West 2022 IR Meeting / July 12, 2022

87

Semiconductor Technology Node and Bump Pitch
1.0E+03

CSP

W.B.

X FCBGA

Pitch■● Solder Bump

1.0E+02TSV
1.0E+01

X Cu Pillar Bump

1.0E+00

1.0E-01●TSV Micro Bump

1.0E-02

1.0E-03
1970
[um]

1980

Technology Node
FBGA

1990

2000

Wire Bonding Memroy
Flip Chip SoC Organic

2010

2020

2030

CSP
micro Bump TSVIntroduction of wafer bonding technology accelerates further reduction of pitch
SEMICON West 2022 IR Meeting / July 12, 2022

88

Semiconductor Technology Node and Bump Pitch
1.0E+03

CSP

W.B.

X FCBGA

Pitch■● Solder Bump

1.0E+02
C2W Bonding
Core/SRAM
HBM

TSV

Active Interposer

1.0E+01

X Cu Pillar Bump

1.0E+00

W2W Bonding

1.0E-01●TSV Micro Bump

1.0E-02

Wafer Bonding●▲ Cu Hybrid Bonding
1.0E-03
1970
[um]

1980

Technology Node
FBGA

1990

2000

Wire Bonding Memroy
Flip Chip SoC Organic

2010

2020

CSP
micro Bump TSV

2030
Bonding surface
Dielectric layer

Introduction of wafer bonding technology accelerates further reduction of pitch
SEMICON West 2022 IR Meeting / July 12, 2022

89

Application of Wafer Bonding
DeviceNAND

BSI

3D NAND

(

HBM
DRAM

Sensor+
Memory
+
Logic

DRAM
…

Stacking
Device

CIS

Cell

)

+

DRAM

+

Peripheral

(
(

Logic

3D DRAM

Backside PDN

Cell

Logic

)
)

Sequential
CFET
Logic

+

+

+

Peripheral

Bare Si

Logic

Disaggregation/ Chiplets

Logic

Bonding

W-W
Cu Hybrid

W-W
Cu Hybrid

D-W
Cu Hybrid

W-W
Cu Hybrid

W-W
Ox Fusion

W-W
Ox Fusion

D-W / D-D
Cu Hybrid

3D I/O Pitch

3 μm
1 μm

1 μm
0.5 μm

40 μm
25 μm1 μm
0.5 μm

Sub μm(nTSV)Sub μm(nTSV)

10 μm
1 μm

Chip stacking
w/ µBump

Structure
Chip stacking
w/ Cu Hybrid

Source: TEL

Source: TEL
3D DRAM structure

StatusHVM

R&D~HVM

R&D

R&D

R&D

R&D

R&D

Expanding adoption of wafer bonding technology for next-generation devices
SEMICON West 2022 IR Meeting / July 12, 2022

90

Wafer Bonding Application for 3D NAND
Current structurePeripheral circuit performance deteriorates
due to exposure to high temperature during
memory cell manufacturing
Long interconnects wiring

New structure

Memory cell

Memory cell

Peripheral circuit

Peripheral circuitPeripheral circuit is manufactured on the separate wafer and bond tothe memory cell wafer•
higher peripheral circuit performance•
shorter TAT* process
Shorter interconnects wiring
SEMICON West 2022 IR Meeting / July 12, 2022

* TAT: Turnaround time91

Wafer Bonding Application for Logic Backside PDN
Backside PDN：Power Delivery Network

Current
structure

Signal BEOL
(Front side)

Bulk Si Wafer
bonding

Backside thinning

ReversePower
Signal &PowerPower BEOL
（Backside）

SignalPursue further scaling without
the power wiring bottleneck
SEMICON West 2022 IR Meeting / July 12, 2022

92

Our Proposal for Wafer Bonding Process
TEL Proposal for Wafer Bonding Process

Pre-Bond
CoaterDepo

Etch

SynapseTM Si

Cleaning

Wafer Process

UlucusTM L
Coater

CMP

Bonding

Trimming

Grinding

Synapse™ Si
Plasmaactivation

Post-Bond

DI watertreatment

Upper
Wafer

Cleaning

Ulucus™ L
Alignment andbonding

Thermalannealing

CMP

Depo

Etch

Cleaning

Wafer Process

Bonding Accuracy (Total Overlay)

Laser
Edge Trimming

Edge Trimming Quality
Before

After

Lower
Wafer

SEMICON West 2022 IR Meeting / July 12, 2022

93

Summary Business opportunities are expanding along with the technological innovationin both logic and memory

 Provide added value through co-optimization of our wide range of products
 Create high value-added equipment and acquire PORs through 4-generation
simultaneous developments and evaluations with our customers

 Enhance and strengthen development capabilities
 Enhance customer satisfaction and productivity by shortening equipment
start-up times using DX and AI

SEMICON West 2022 IR Meeting / July 12, 2022

94

Notice
You may not copy or disclose to any third party
without prior written consent with TEL.
Tokyo Electron

SEMICON West 2022 IR Meeting / July 12, 2022

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