Optimal Design to Maximize Efficiency of SingleInductor Multiple-Output Buck Converters inDiscontinuous Conduction Mode for IoT Applications
Yoshitaka Yamauchi, Yuki Yanagihara, Hiroshi Fuketa, Takayasu Sakurai, and Makoto Takamiya
University of Tokyo
Tokyo, Japan
Abstract—To clarify the design guide of single-inductor
multiple-output (SIMO) buck converters in discontinuous
conduction mode (DCM) targeted for small-size and low-power
IoT applications, equations of optimal design parameters(transistor size, inductance, and switching frequency) tomaximize the power conversion efficiency are derived for thefirst time. The analytical optimal designs are verified with SPICE
simulations. The maximum efficiency of SIMO DCM buckconverters is lower than that of conventional single-inductor
single-output (SISO) DCM buck converters, because the power
loss due to the energy distribution switches is added. Theefficiency degradation is analytically explained for the first time.

VINfSISO
MPfSISO
MNIL
WP L
SISO RIND

In the applications of Internet of Things (IoT), tiny andenergy efficient IoT nodes are required for physical datacollection. The requirements for power-management ICs are
the multiple output voltages, small output current (A – mA),and small size. Figs. 1 (a) and 2 show a conventional singleinductor single-output (SISO) buck converter and a singleinductor multiple-output (SIMO) buck converter, respectively.
Instead of the SISO buck converter in continuous conduction
mode (CCM), the SIMO buck converter in discontinuous
conduction mode (DCM) is an excellent candidate to meet therequirements for IoT, because the SIMO buck converter canprovide multiple output voltages using only one inductor and
DCM is better suited for the small output current. In DCM, theinductor current (IL) is intermittently zero within eachswitching cycle as shown in Fig. 1 (b). The design guide tomaximize the power conversion efficiency of SISO and SIMO
DCM buck converters, however, is not reported, though thatof the SISO CCM buck converter is reported in [1]. Inaddition, the efficiency degradation of the SIMO DCM buckconverter over the SISO DCM buck converter is nottheoretically clarified.
Therefore, in this paper, the optimal designs of transistor
size, inductance, and switching frequency to maximize thepower conversion efficiency of both SISO and SIMO DCM
buck converters are proposed, and the analytical optimal
designs are verified with SPICE simulations. Then, themaximum efficiency of SISO and SIMO DCM buckconverters are compared and analyzed.

ILOAD

T1 T2
Time

T=1/f

(a)

(b)

Fig. 1. Single-inductor single-output (SISO) buck converter. (a) Circuit.
(b) Inductor current waveform in DCM.

Keywords—buck converter; discontinuous conduction mode;
single-inductor multiple-output

I. INTRODUCTIONVOUTILWN

T1/(T1 +T2) = M

S1 fSIMO/N
VOUT1VINfSIMO
MPfSIMOMN

WS1WP LSIMO RINDWNIL

ILOAD1S2 fSIMO/N
VOUT2WS2ILOAD2SN fSIMO/N
VOUTN

WSN

ILOADN

Fig. 2. Single-inductor multiple-output (SIMO) buck converter.

II. OPTIMAL DESIGN OF SISO DCM BUCK CONVERTER
To obtain the optimal design of the SISO DCM buckconverter in Fig. 1 (a), the optimal design of the SISO CCM
buck converter in [1] is expanded. In the section, equations(12) - (18) are newly proposed in this paper, while equations(1) - (11) are similar to [1]. The effective ON resistance (REFF)
and effective switching capacitance (CEFF) of the powertransistors (MP and MN in Fig. 1 (a)) are as follows.
RNR
1  M   P M
WN
WP
CEFF  WNCN  WPCPREFF 

(1)(2)

where WN, WP, RN, RP, and CN, CP are the gate widths, ON
resistance per unit gate width, and the switched capacitance
per unit gate width of nMOS (MN) and pMOS (MP),respectively. M (= VOUT/VIN) is the conversion ratio, where VINand VOUT are input and output voltages, respectively. By
minimizing CEFF at constant REFF, the optimal gate width ratio(αOPT = WP/ WN) is determined as follows.

 OPT WPWNMRPCN1  M  RNCP

(3)

Here, the total gate width (WTOTAL = WN +WP) is defined. By
substituting (3) into (1) and (2), each of REFF and CEFF is afunction of WTOTAL as follows.
RREFF  AVE(4)
WTOTAL
MRP RAVE  1  OPT  1  M  RN OPT 
CEFF  WTOTALCAVEC   OPT CP
CAVE  N1   OPT(7)PLOSS,SISO  PCAP,SISO  PRES,SISO  PIND,SISO(8)

PCAP,SISO  fSISOCEFFVIN 2  fSISOWTOTALCAVEVIN 2(9)2VIN M 1  M  I LOAD
2I LOAD
3fSISO LSISO

(10)
(11)
(12)

As shown in Fig. 1 (a), fSISO, LSISO, RIND, ILOAD are theswitching frequency, the inductance, the parasitic resistance ofthe inductor, and the load current, respectively. τL is the figureof merit of an inductor technology [1-2] and IRMS,SISO is theeffective value of IL. The difference of this work from [1] isthe discontinuous IL shown in Fig. 1 (b) and (12).
In the design of the SISO DCM buck converter, threedesign parameters (WTOTAL, LSISO, fSISO) are available. Tomaximize the power conversion efficiency, PLOSS,SISO should
be minimized by setting the derivatives with respect to eachparameter to zero [1]. Then the optimal parameters are derived
as follows.
WTOTAL,OPT  WSISOLSISO,OPTfSISO,OPTLRSISO,MIN

SISO,MAX24 RAVECAVE M 1  M LPLOSS,SISO,MIN

3POUT24 RAVECAVE 1  M  LM 2(16)(17)

124 RAVE CAVE 1  M 1 3 LM 2(18)(6)

whereI RMS,SISO 2 

PLOSS,SISO,MIN  VIN I LOAD 3(5)The power loss (PLOSS,SISO) in a buck converter consists ofthree kinds of loss: the switching loss (PCAP,SISO), the resistiveloss (PRES,SISO) of MN and MP, and the resistive loss (PIND,SISO)
of the inductor [1].

RPRES,SISO  REFF I RMS,SISO 2  AVE I RMS,SISO 2WTOTAL
LPIND,SISO  RIND I RMS,SISO 2  SISO I RMS,SISO 2L

WSISO is an arbitrary parameter (total gate width). In theoptimal design, PCAP,SISO = PRES,SISO = PIND,SISO, and theminimum PLOSS,SISO (PLOSS,SISO,MIN), a newly defined loss ratio(LRSISO,MIN), and the maximum efficiency (SISO,MAX) areshown as follows.

(13)

RAVE L
WSISO

(14)

2 I LOAD M 1  M  RAVE
3WSISOVIN
9 LCAVE 2(15)III. OPTIMAL DESIGN OF SIMO DCM BUCK CONVERTERIn this section, the optimal design of the SIMO DCM buckconverter with N outputs in Fig. 2 is derived. Then, theanalytical optimal designs are verified with SPICE simulations.
In this paper, the time-multiplexing control [3-4] shown in Fig.
3 is used for the SIMO DCM buck converter, because thecross regulation between outputs is very small.
A. Analysis of Optimal Design
To simplify the analysis and to understand the essence ofthe SIMO DCM buck converter, N outputs in Fig. 2 areassumed to be equal. Specifically, VOUT1 = VOUT2 = … = VOUTN= VOUT, ILOAD1 = ILOAD2 = … = ILOADN = ILOAD, and WS1 = WS2= … = WSN = WS. In this assumption, the circuit in Fig. 2 canbe transformed to the circuit in Fig. 4. Compared to the circuitof the SISO DCM buck converter in Fig. 1 (a), an energy
distribution switch (S) is added and the load current increases
N times. The power loss (PLOSS,SIMO) is represented as follows.
IL1
S1

S2

N

2

12

ON

ON
OFFON

ONON

SNOFFT

2T

NT (N+1)TTimeFig. 3. Waveforms of SIMO DCM buck converter.

VINfSIMOMPfSIMOMN

WPfSIMO SLSIMO RINDWSWNILVOUTNILOAD

Fig. 4. Equivalent circuit of SIMO DCM buck converter with equaloutputs.

PLOSS,SIMO  PCAP,SIMO  PRES,SIMO  PIND,SIMO(19)

PCAP,SIMO  fSIMOWTOTALCAVEVIN 2  fSIMOWSCPVIN 2(20)(LRSIMO,MIN), and the maximum efficiency (SIMO,MAX) areshown as follows

whereRRPRES,SIMO  AVE I RMS,SIMO 2  S I RMS,SIMO 2WTOTALWSL
PIND,SIMO  RIND I RMS,SIMO 2  SIMO I RMS,SIMO 2
L
I RMS,SIMO 2 RS  RP

2V M 1  M  NI LOAD2 NI LOAD  IN
3fSIMO LSIMO

VIN  VTH
MVIN  VTH

PLOSS,SIMO,MIN  VIN  NI LOAD (21)(22)

LRSIMO,MIN(23)

3(24)SIMO,MAX

WS is the gate width of S, RS is ON resistance of S per unit
gate width, and VTH is the threshold voltage of S. RS instead of
RP is added, because the gate-source voltages of MP and S aredifferent in Fig. 4. In (20) and (21), the switching loss andresistive loss due to S are added. In the design of the SIMO
DCM buck converter, four design parameters (WTOTAL, WS,LSIMO, fSIMO) are available. Compared with the previous section,
WS is newly added. The optimal design parameters are derived
as follows.
WTOTAL,OPT  WSIMO(26)

LSIMO,OPT RAVE L 
RSCP 
1 WSIMO RAVECAVE (27)fSIMO,OPT2 NI LOAD M 1  M 
3VINWSIMO 9 LCAVE 2(28)RSCP 1 
R
AVECAVE 

24 RAVECAVE 1  M  
RSCP 1  LM 2RAVECAVE 
11 32(29)(30)

224 RAVECAVE 1  M  
RSCP 1 2 LMRAVECAVE 2(31)Table I summarizes the derived equations. Similar to the SISO
DCM buck converter, the optimal design for SISO DCM buckconverter has one degree of freedom (WSIMO). When RS = 0,(27) – (31) are equal to (14) – (18), respectively, which isreasonable.
B. Verification with SPICE Simulations
To check the validity of the derived equations in this paper,the optimal design of a SIMO DCM buck converter with twooutputs in Fig. 2 is performed using 1.8V, 180nm CMOS
process and the analytically derived PLOSS,SIMO is comparedwith SPICE simulations. Fig. 5 shows the calculated andSPICE simulated PLOSS,SIMO. In Figs. 5 (a) –(d), one of the four
design parameters (WTOTAL, WS, LSIMO, fSIMO) are varied,respectively, and all the other parameters are optimum values
shown in Table II. The calculated results are consistent with
the SPICE simulated results, which shows the validity of theequations in this paper. The minimum PLOSS,SIMO in each Figs.
5 (a) –(d) are identical, which is the evidence of the minimum
loss (= maximum efficiency) design.

(25)RSCAVEWSIMORAVECPWS,OPT24 RAVECAVE M 1  M  
RSCP 31 
L
RAVECAVE P LOSS,SIMO,MIN
POUT

WSIMO is an arbitrary parameter (total gate width). In the
optimal design, PCAP,SIMO = PRES,SIMO = PIND,SIMO, and theminimum PLOSS,SIMO (PLOSS,SIMO,MIN), the loss ratio

TABLE I SUMMARY OF EQUATIONS FOR BUCK CONVERTERS.

Operation mode

[1]This Work

CCM

DCM

Topology

SISO

SIMO

WTOTAL,OPTRAVE I LOAD
8 L
3VIN
3RAVE CAVE M 1  M 

WSISO(13)

LOPTVIN 33RAVE CAVE L 2 M 1  M 
2 I LOADRAVE LWSISO(14)M 2 1  M 

2 I LOAD M 1  M  RAVE
3WSISOVIN
9 LCAVE 2f OPT323RAVE CAVE L 2WSIMORAVE L 
RSCP 1  (27)
WSIMO RAVECAVE (15)2 NI LOAD M 1  M  RAVE
39 LCAVE 2
WSIMOVINPLOSS,MIN
POUT
MAX 1

1
PLOSS,MIN
POUT

RSCP 1  (28)RAVECAVE 

RSCAVEWSIMO
RAVECP

WS, OPTPLOSS, MIN(25)

VIN I LOAD 3324 RAVE CAVE M 1  M L24 RAVECAVE 1  M  LM

2VIN I LOAD 324 RAVE CAVE M 1  M 

L311 324 RAVECAVE 1  M 
 LM 224 RAVECAVE 1  M 

 LM 211 324 RAVE CAVE 1  M  LM 2(16)(17)

VIN  NI LOAD  3(26)24 RAVECAVE M 1  M  
RSCP 
1 L
RAVECAVE 


2(29)

2324 RAVECAVE 1  M  
RSCP 
1 
 LM 2RAVECAVE 

1 324 RAVECAVE 1  M  
RSCP 
1  R C LM 2AVE AVE 

(30)

1(18)

2(31)

PLOSS,SIMO [μW]2001000WTOTAL,OPT=4.1mm

0.1mm

300

PLOSS,SIMO [μW]300

Calculated
SPICE1mm10mm

WTOTAL(a)1001mm300

Calculated
SPICE

100fSIMO,OPT =270kHz
010kHz

WS,OPT =5.9mm

00.1mm100mm

200100kHz

1MHz

IV. COMPARISON OF MAXIMUM EFFICIENCY OF SISO ANDSIMO DCM BUCK CONVERTERS

Calculated
SPICE

200

PLOSS,SIMO [μW]

PLOSS,SIMO [μW]

300

WS
(b)

10mm

100mm

Calculated
SPICE

200100LSIMO,OPT =93μH
010μH

10MHz

100μH

1mH

LSIMO

fSIMO(c)(d)Fig. 5. Calculated and SPICE simulated PLOSS,SIMO. In (a) –(d), one offour design parameters (WTOTAL, WS, LSIMO, fSIMO) are varied,respectively.
TABLE II PARAMETERS USED IN FIG. 5
M

0.5

L

38 [μH/Ω]

VIN

1.8 [V]I LOAD

1.0 [mA]

VOUT

0.9 [V]

 OPT

1.9

RN

900 [Ωμm]

WTOTAL,OPT

4.1 [mm]

RP

3600 [Ωμm]

WS,OPT

5.9 [mm]CN

2.8 [fF/μm]fSIMO,OPT

270 [kHz]CP

3.2 [fF/um]

LSIMO,OPT

93 [μH]

RS

8600 [Ωμm]

RSCP
RAVE CAVE

RAVE

4000 [Ωμm]

CAVE

3.0 [fF/μm]

1.52
RSCP  31
RAVE CAVE 

1.8Fig. 6 shows the calculated WTOTAL dependence of theefficiency of SISO CCM, SISO DCM, and SIMO DCM buckconverters. Parameters except WTOTAL, L, and f are common asshown in Table II among the converters. In SISO CCM, theoptimal WTOTAL is uniquely determined, while the optimal
WTOTAL of SISO DCM and SIMO DCM has one degree offreedom. MAX of SISO CCM, however, is equal to MAX ofSISO DCM as shown in Table I. MAX of SIMO DCM islower than MAX of SISO DCM as shown in (18) and (31). Fig.
7 shows the calculated M dependence of MAX of SISO andSIMO DCM buck converters using (18) and (31). Parameters
except M are similar to Table II. When M is increased from0.3 to 0.9, the efficiency difference between SISO and SIMO
decreases from 4.5% to 0.6%. Direct comparison of (18) and(31) results in a complicated equation, while comparison of(17) and (30) results in a simple equation as follows.
2


LR
RSCP  3
RLR  SIMO,MIN  1 LRSISO,MINRAVECAVE 

The ratio of the loss ratio (RLR) is a function of M andtransistor-related parameters and does not depend on inductorrelated parameters. The efficiency degradation between SISO
and SIMO is universally explained by RLR. RLR is 2.4, 1.8,
and 1.6 at M = 0.3, 0.5, and 0.9, respectively in 1.8V, 180-nm
CMOS process. RLR decreases as M is increased, because S inFig. 4 is pMOS and RS decreases.

100

V. CONCLUSIONS

Efficiency [%]M = 0.5

98

SISO,CCM

SISO,DCM(3.8μH,19kHz)

ηMAX,SISO(L,f)=(210μH,1.1MHz)

96

ηMAX,SIMO(8.9μH,45kHz)

9492(22μH,66kHz)

0.1mm

1mm

SIMO,DCM(9.5μH,28kHz)

10mm

100mm

WTOTALThe design guides to maximize the power conversion
efficiency of both SISO and SIMO DCM buck converters areproposed as shown in Table I. In the conventional SISO CCM
buck converter, the optimal design parameters are uniquelydetermined, while the optimal design parameters in the SISOand SIMO DCM buck converters are not unique and havesome flexibility. The maximum efficiency of the SIMO DCM
buck converter is lower than that of the SISO DCM buckconverter. The efficiency degradation mechanism isuniversally explained by the proposed RLR in (32).

Fig. 6. Calculated WTOTAL dependence of efficiency of SISO CCM, SISO
DCM, and SIMO DCM buck converters.

REFERENCES[1]

Maximum efficiency (ηMAX) [%]

100

SISO
98

SIMO

[2]

96
94

[3]

180nm CMOS L =38[μH/Ω]

92
90
0.3

0.4

0.5

0.6

0.7

0.8(32)0.9

M = VOUT / VIN

Fig. 7. Calculated M dependence of MAX of SISO and SIMO DCM
buck converters.

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