一般社団法人 電子情報通信学会
THE INSTITUTE OF ELECTRONICS,INFORMATIONAND COMMUNICATION ENGINEERS
ࣾஂ๏ਓ ిࢠ৘ใ௨৴ֶձ

信学技報
IEICE Technical Report
VLD2020-75,HWS2020-50(2021-03)
৴ֶٕใTHE INSTITUTE OF ELECTRONICS,
INFORMATION AND COMMUNICATION ENGINEERSTECHNICAL REPORT OF IEICE.

RTOS ར༻γεςϜͷϑϧϋʔυ΢ΣΞԽʹ͓͚ΔαʔϏεॲཧ‫ػ‬ೳͷू໿࿡ं ҏ৫†ੴӜࡊ‫†ࠤذ‬҆ಊ ୓໵†෌ࢁ ޺೭††ਆ‫߂ ݪ‬೭†††† ؔ੢ֶӃେֶ ཧ޻ֶ෦ ˟ 669–1337 ฌ‫ֶࢢాࡾݝݿ‬Ԃ 2–1†† ໋ཱ‫ؗ‬େֶ ཧ޻ֶ෦ ˟ 525–8577 ࣎լ‫૲ݝ‬௡ࢢ໺࿏౦ 1 ஸ໨ 1–1††† ‫ٕ౓ߴ౎ژ‬ज़‫ ˟ ॴڀݚ‬600–8813 ‫ࢢ౎ژ‬Լ‫۠ژ‬தಊࣉೆொ 134 ൪஍͋Β·͠ ຊߘͰ͸, RTOS ར༻γεςϜΛϑϧϋʔυ΢ΣΞԽ͢Δख๏ʹ͓͍ͯ, ճ࿏‫ن‬໛࡟‫ߦ࣮ͱݮ‬ͷߴ଎ԽΛ໨తͱͨ͠ճ࿏ߏ੒๏ΛఏҊ͢Δ. େഭΒ͸, λεΫ/ϋϯυϥ౳ͷΧʔωϧΦϒδΣΫτͱ RTOS Χʔωϧͷ‫ػ‬ೳΛશͯ 1 ͭͷϋʔυ΢ΣΞʹ߹੒͢Δख๏ΛఏҊ͍ͯ͠Δ͕, RTOS ͷαʔϏε‫ػ‬ೳΛλεΫଆʹϦϯΫͯ͠ߴҐ߹੒͍ͯͨͨ͠Ί, ಉ͡αʔϏε‫ػ‬ೳΛ࣮ߦ͢Δϋʔυ΢ΣΞ͕ॏෳͯ͠ੜ੒͞Ε͍ͯͨ. ຊߘͰ͸, ΧʔωϧΦϒδΣΫτͷ࣮ߦΛ੍‫͢ޚ‬ΔϚωʔδϟϞδϡʔϧʹ RTOS ͷαʔϏε‫ػ‬ೳΛू໿͢Δ͜ͱʹΑΓ, ͜ͷॏෳΛ࡟আ͢Δ. ͜ΕΛ࣮‫͢ݱ‬ΔͨΊʹ, ΧʔωϧΦϒδΣΫτ͔ΒαʔϏεॲཧΛ‫ى‬ಈ͢Δํࣜͱ, ෳ਺ͷαʔϏεॲཧཁ‫ٻ‬Λௐఀ͢ΔํࣜΛ৽ͨʹఏҊ͢Δ. ͜ͷํࣜͰ͸, ؆୯ͳαʔϏεॲཧ͸ RTL Ͱઃ‫͖Ͱܭ‬ΔͨΊ, ॲཧͷߴ଎Խ΋࣮‫͖Ͱݱ‬Δ.

TOPPERS/ASP3 Χʔωϧ෇ଐͷαϯϓϧ “sample1” Λॖখͨ͠ϓϩάϥϜΛϑϧϋʔυ΢ΣΞ࣮૷ͨ݁͠Ռ, େഭΒͷख๏ʹൺ΂ͯճ࿏‫ن‬໛͸େ෯ʹ͸࡟‫͕͔ͨͬͳ͖Ͱݮ‬, ΄ͱΜͲͷαʔϏείʔϧͰॲཧʹཁ͢Δ࣮ߦ࣌ؒΛ 50%ҎԼʹ࡟‫͖ͨͰݮ‬.
ΩʔϫʔυϦΞϧλΠϜγεςϜ, RTOS, γεςϜ߹੒, ϋʔυ΢ΣΞΞΫηϥϨʔλ, TOPPERS/ASP3, ߴҐ߹੒Aggregating Service Functions in Full Hardware Implementationof RTOS-Based SystemsIori MUGURUMA† , Nagisa ISHIURA† , Takuya ANDO† ,Hiroyuki TOMIYAMA†† , and Hiroyuki KANBARA†††† Kwansei Gakuin University, Gakuen 2–1, Sanda, Hyogo, 669–1337, Japan†† Ritsumeikan University, 1–1–1 Noji–Higashi Kusatsu, Shiga, 525–8577, Japan††† ASTEM RI/KYOTO, 134 Chudoji Minamimachi, Shimogyo–ku, Kyoto, 600–8813, Japan
Abstract This article presents a revised architecture for full-hardware implementation of RTOS-based systems.
In the previous method by Oosako, where tasks and handlers along with kernel functions were all synthesized intoa single hardware, multiple copies of the same hardware modules were generated because the bodies of the same
service functions were linked with tasks and were synthesized into hardware. Our new architecture attempts toremove such duplication by migrating the bodies of the service functions from task modules to the manager module.
For this purpose, a new mechanism for activating service functions from tasks and arbitrating multiple requests isproposed. This scheme enables design of service modules in RT level, which contributes to reduce execution time ofthe service functions. An experimental hardware design of “sample1” bundled with TOPPERS/ASP3 kernel showsthat only small reduction in circuit size is achieved on this instance but the execution time is reduced by more than
50% for most of the service functions.
Key words Real-Time Systems, RTOS, System Synthesis, Hardware Accelerator, TOPPERS/ASP3, High-Level
Synthesis- 38 -—1—
This article is a technical report without peer review, and its polished and/or extended version may be published elsewhere.
Copyright ©2021 by IEICEIMEM1. ͸ ͡ Ί ʹ

TSK1 ... TSKnCYCiRTOSۙ೥ͷ৘ใ௨৴ٕज़ͷൃలʹΑΓ, ৽͍͠੡඼΍αʔϏε͕ALMi

INTi

ALMi

INTi

࣍ʑʹఏ‫͞ڙ‬ΕΔΑ͏ʹͳ͓ͬͯΓ, ͜ΕΒͷΩʔσόΠεͱͳΔ૊ࠐΈγεςϜʹ͸ӹʑߴ͍‫ػ‬ೳ͕ཁ‫͞ٻ‬ΕΔΑ͏ʹͳͬCPU͍ͯΔ. ಛʹ, ंࡌ‫ثػ‬, ແਓඈߦ‫ػ‬, ϩϘοτͷ੍‫ʹޚ‬͸, ߴDMEM͍‫ػ‬ೳͱಉ࣌ʹߴ͍Ԡ౴ੑ͕ཁ‫͞ٻ‬ΕΔ.
͜ͷΑ͏ͳϦΞϧλΠϜγεςϜͷ։ൃʹ͸, ϦΞϧλΠϜHW
TSK1 ... TSKn

OS (RTOS) ͕༻͍ΒΕΔ. RTOS ͸, λεΫ΍ϋϯυϥ੍͕໿࣌ؒ಺ʹ࣮ߦΛ‫ྃ͢׬‬ΔΑ͏ʹγεςϜΛ࣮૷͢ΔͨΊͷ‫ػ‬ೳCYCi
managerarbiterΛఏ‫͢ڙ‬Δ. ͔͠͠, γεςϜͷߴ‫ػ‬ೳԽ͕ਐΉʹͭΕ, RTOSΛར༻ͨ͠γεςϜͷϦΞϧλΠϜੑ֬อ͸೉͘͠ͳ͖ͬͯͯDMEM͍Δ.

ਤ 1: RTOS Λ༻͍ͨγεςϜͷϑϧϋʔυ΢ΣΞ࣮૷ [12]ೳͷҰ෦·ͨ͸શͯΛϋʔυ΢ΣΞ࣮૷͢Δํ๏͕͋Δ. จarbiter‫[ ݙ‬1], [2], [3] Ͱ͸, RTOS ͷεέδϡʔϥͷϋʔυ΢ΣΞԽʹmanagerpri

ΑΔߴ଎ԽΛߦ͍ͬͯΔ. ·ͨ, จ‫[ ݙ‬4], [5], [6] Ͱ͸ RTOS ͷlocalmem΄ͱΜͲͷ‫ػ‬ೳΛϋʔυ΢ΣΞ࣮૷͍ͯ͠Δ. ͔͜͠͠ΕΒͷख๏Ͱ͸, λεΫ΍ϋϯυϥ͸ιϑτ΢ΣΞͷ··Ͱ͋Γ, CPU

addr
data

addr
data
pri

଴ͪ΍ίϯςΩετεΠονʹΑΔ஗Ԇ͕ੜͣΔ.
Ұํ, ߴҐ߹੒ٕज़ [7] Λར༻ͯ͠λεΫ΍ϋϯυϥΛઐ༻localmemϋʔυ΢ΣΞʹ߹੒͢Δ͜ͱʹΑͬͯԠ౴ੑೳͷ޲্ΛਤΔख

addr
data

๏͕͋Δ. ࢦఆͨ͠λεΫΛϋʔυ΢ΣΞʹ߹੒͢ΔͨΊͷγ

addr
data
priεςϜϨϕϧઃ‫ܭ‬ख๏ [8], [9] ͕ఏҊ͞Ε͍ͯΔ͕, ͜ΕΒͷख
local
mem

๏Ͱ͸, RTOS ͓ΑͼҰ෦ͷλεΫ͸ιϑτ΢ΣΞͱ࣮ͯ͠ߦ͞ΕΔ. จ‫[ ݙ‬10], [11] ͸ׂࠐΈϋϯυϥΛ‫ؚ‬ΉγεςϜશମͷ

addr
data

addr
data

task
statustask
statuscyclicstatuspriϜʹ‫ݶ‬ΒΕΔ.
͜ͷ՝୊Λղܾ͢ΔҰख๏ͱͯ͠, จ‫[ ݙ‬12] ͸λεΫ͓Αͼ

local
mem

RTOS ͷαʔϏε‫ػ‬ೳશͯΛϋʔυ΢ΣΞԽ͢Δख๏ΛఏҊ

addr
data

addr
data

alarm
status͍ͯ͠Δ. ͜ͷख๏͸, RTOS ্Ͱಈ࡞͢ΔϓϩάϥϜΛೖྗpriΛࣗಈੜ੒͢Δ. λεΫ͸ͦΕͧΕಠཱʹಈ࡞͢Δϋʔυ΢Σ

local
mem

Ξʹ߹੒͞Ε, શͯͷλεΫ͸ฒྻʹ࣮ߦͰ͖ΔͨΊ, λεΫ

addr
data

addr
data

int
statusͷ੾Γସ͑Φʔόʔϔου͕ແ͍. TOPPERS/ASP3 ͓ΑͼԠ౴ੑೳΛ࣮‫͍ͯ͠ݱ‬Δ͕, ճ࿏‫ن‬໛͕େ͖͘ͳΔ͜ͱ͕՝୊

globalmemͱͳ͍ͬͯΔ.

addr
dataຊߘͰ͸, จ‫[ ݙ‬12] ͷϋʔυ΢ΣΞߏ੒ʹ͓͍ͯ, λεΫʹ

addr
data

TSKnstall, resetaddr
data

CYCi

stall, reset
addr
data

ALMi

stall, resetaddr
data

INTi

globalstatus

mutex
mutex

IRQ

෼ࢄ͍ͯ͠Δ RTOS ͷαʔϏεॲཧ‫ػ‬ೳΛλεΫ؅ཧϋʔυਤ 2: ϋʔυ΢ΣΞͷߏ੒ [12]΢ΣΞଆʹΑͬͯू໿͢Δ͜ͱʹΑͬͯ, ճ࿏‫ن‬໛Λ࡟‫͢ݮ‬Δ࣮૷͢Δ͜ͱʹΑΓॲཧͷߴ଎ԽΛਤΔ.

stall, reset

end

FreeRTOS Λର৅ͱͨ͠ϓϩτλΠϓ࣮૷ [13], [14] Ͱ͸, ߴ͍ํࣜΛ৽ͨʹఏҊ͢Δ. ·ͨ, ‫ج‬ຊతͳαʔϏεॲཧΛ RTL Ͱ

TSK1

end

ͱͯ͠, ͜ΕΛ࣮ߦ͢Δϓϩηοαͱ‫ػ‬ೳ౳Ձͳϋʔυ΢ΣΞ

͢Δํࣜ΍, ෳ਺ͷαʔϏεཁ‫͕ٻ‬ಉ࣌ʹൃੜͨ͠৔߹ͷௐఀaddr
data

endϋʔυ΢ΣΞԽΛߦ͍ͬͯΔ͕, ߹੒ର৅͸ϕΞϝλϧγεςख๏ΛఏҊ͢Δ. ͜ͷͨΊʹ, λεΫ͔ΒαʔϏεॲཧΛ‫ى‬ಈstall, reset...

RTOS Λ༻͍ͨγεςϜͷߴ଎Խख๏ͱͯ͠͸, RTOS ‫ػ‬υϥ, ΞϥʔϜϋϯυϥ, ׂࠐΈϋϯυϥ౳ͷΧʔωϧΦϒδΣΫτͰ͋Γ, RTOS ͷ؅ཧԼͰ࣮ߦ͞ΕΔ. ͜ͷख๏Ͱ͸, ֤λεΫ/ϋϯυϥ͸ߴҐ߹੒ʹΑͬͯಠཱͨ͠ϋʔυ΢ΣΞϞδϡʔϧʹ߹੒͞Ε, RTOS ‫ػ‬ೳ͸Ϛωʔδϟ (manager) ͱ͍

2. RTOS Λ༻͍ͨγεςϜͷϑϧϋʔυ΢ΣΞ࣮૷จ‫[ ݙ‬12] Ͱ͸, RTOS ͷαʔϏείʔϧΛ༻͍ͨϓϩάϥϜΛೖྗͱ͠, ͜ΕΛ࣮ߦ͢Δϓϩηοαͱ‫ػ‬ೳ౳Ձͳϋʔυ΢ΣΞΛ߹੒͢Δख๏ΛఏҊ͍ͯ͠Δ. ͦͷ֓೦Λਤ 1 ʹࣔ͢. ্ํͷ TSK, CYC, ALM, INT ͸ͦΕͧΕͷλεΫ, प‫ظ‬ϋϯ͏ϋʔυ΢ΣΞ͕࣮‫͢ݱ‬Δ.
λεΫ/ϋϯυϥ͸, ࣮ߦՄೳʹͳΕ͹શͯฒྻʹ࣮ߦ͞ΕΔ. ͜ͷ੍‫ޚ‬͸Ϛωʔδϟ͕֤λεΫ/ϋϯυϥͷঢ়ଶม਺ͷ஋͔ΒλεΫ/ϋϯυϥͷ࣮ߦ/ఀࢭΛ੍‫͢ޚ‬Δ৴߸Λੜ੒͢Δ͜ͱʹΑΓߦ͏. σʔλϝϞϦ (DMEM) ͷಉ͡όϯΫʹಉ࣌ʹΞΫηε͕͋ͬͨ৔߹ʹ͸, ༏ઌ౓ʹԠͯ͡ΞʔϏλ (arbiter)- 39 -—2—T1managerTF1

T2
TA1status[T1]

TF2

T3
TA2status[T2]

TF3

status[T3]TA3status[G](a) จ‫[ ݙ‬12]
RAXF
S1(b) ຊख๏XAS2XT
S3S4

ਤ 4: ߹੒͢Δϋʔυ΢ΣΞϞδϡʔϧͷৄࡉߏ੒ਤ 3: ఏҊ͢Δϋʔυ΢ΣΞߏ੒͍ͨ. ຊख๏Ͱ͸αʔϏεॲཧ͸͢΂ͯϚωʔδϟʹू໿͢Δ͕ௐఀΛߦ͏. ͜ͷख๏Ͱ͸, εέδϡʔϦϯά΍ίϯςΩε͜ͱʹΑͬͯ͜ͷॏෳΛഉআ͢Δ.

τεΠον, ͓Αͼ CPU ଴ͪͷΦʔόʔϔου͕ͳͤ͘Δ্,αʔϏεॲཧͷ‫ى‬ಈ͸, λεΫ͕Ϩδελ TFi, TAi ʹͦΕλεΫ/ϋϯυϥΛϋʔυ΢ΣΞԽͯ͠ߴ଎࣮ߦͰ͖ΔͨΊ, γͧΕ‫ى‬ಈ͍ͨ͠αʔϏεͷ൪߸ͱҾ਺Λॻ͖ࠐΉ͜ͱʹΑΓεςϜͷԠ౴ੑೳΛඈ༂తʹ޲্ͤ͞Δ͜ͱ͕Ͱ͖Δ.

ߦ͏. ෳ਺ͷαʔϏεͷ‫ى‬ಈཁ‫͕ٻ‬ಉ࣌ʹൃੜͨ͠৔߹ʹ͸Ϛ߹੒͞ΕΔϋʔυ΢ΣΞͷߏ੒Λਤ 2 ʹࣔ͢. ֤λεΫ/ϋωʔδϟ͕λεΫͷͦͷ࣌఺Ͱͷ༏ઌ౓ʹैͬͯ࠷ॳʹॲཧ͢ϯυϥͷঢ়ଶ΍༏ઌ౓౳ͷ৘ใ͸, ϚωʔδϟϞδϡʔϧ಺ͷΔαʔϏεΛܾఆ͠, ରԠ͢ΔαʔϏεϞδϡʔϧΛ‫ى‬ಈ͢Δ.

status Ϩδελʹ, Χʔωϧͷঢ়ଶ͸ global status ϨδελαʔϏεϞδϡʔϧͷ࣮ߦ͕‫ྃ͢׬‬Δͱ, Ϛωʔδϟ͸αʔϏʹ֨ೲ͞ΕΔ. ϚωʔδϟϞδϡʔϧ͸, status Ϩδελͷ஋εϞδϡʔϧ͕ग़ྗ͢ΔฦΓ஋Λ TAi ʹ֨ೲ͠, TFi ʹ‫ྃ׬‬ʹ‫͖ͮج‬, ͦͷλεΫ/ϋϯυϥ͕࣮ߦՄೳͳ৔߹ʹ͸ stall ৴஋Λॻ͖ࠐΜͰλεΫʹ‫ྃ׬‬Λ௨஌͢Δ.

߸Λ 0 ʹ, ࣮ߦΛఀࢭͤ͞Δ৔߹ʹ͸ stall ৴߸Λ 1 ʹ͢Δ͜

3. 2 ϚωʔδϟͱʹΑΓ, λεΫ/ϋϯυϥͷ࣮ߦΛ੍‫͢ޚ‬Δ. ϩοΫͷऔಘ/

3. 2. 1 ߏ੒ղ์ͳͲͷॲཧ͸, ϋʔυ΢ΣΞʹΑΓ࣮૷͞Ε͍ͯΔ. statusຊख๏Ͱ߹੒͢Δϋʔυ΢ΣΞϞδϡʔϧͷৄࡉߏ੒Λਤ 4Ϩδελͱ global status Ϩδελ͸, ϝϞϦۭؒʹϚοϓ͞Εʹࣔ͢. TFi ͓Αͼ TAi ͸λεΫ Ti ͱϚωʔδϟΛ஥հ͓ͯ͢Γ, λεΫ/ϋϯυϥ͔Β͸ϝϞϦΞΫηεʹΑͬͯࢀর/ΔϨδελͰ͋Δ. status[Ti] ͸λεΫ Ti ͷঢ়ଶม਺Λ֨ೲߋ৽Ͱ͖Δ. RTOS ͷαʔϏείʔϧ͸‫ج‬ຊతʹ status Ϩδ͢ΔϨδελ‫͋Ͱ܈‬Γ, status[G] ͸γεςϜͷঢ়ଶม਺Λ֨ελͱ global status Ϩδελ͓Αͼ‫ڞ‬༗ม਺Λࢀর/ߋ৽͢Δೲ͢ΔϨδελ‫͋Ͱ܈‬Δ. ϦΫΤετΞʔϏλ (RA) ͸ෳ਺ͷॲཧͱ࣮ͯ͠૷͞Ε͍ͯΔͷͰ, ֤λεΫͱϦϯΫ͢Δ֤λεαʔϏεॲཧཁ‫͕ͨͬ͋ٻ‬৔߹ͷௐఀΛߦ͏ճ࿏Ͱ͋Δ. Si ͸Ϋ಺ʹΠϯϥΠϯల։͢Δ͜ͱʹΑΓ, λεΫͷҰ෦ͱͯ͠ߴαʔϏεॲཧΛߦ͏ϋʔυ΢ΣΞ (αʔϏεϞδϡʔϧ) Ͱ͋Ґ߹੒͞ΕΔ.

Γ, XF, XA, XT ͸ϚωʔδϟͱαʔϏεϞδϡʔϧΛ஥հ͢ͳ͓, ͜ͷख๏Ͱ͸, ಉ࣌ʹ࣮ߦͰ͖ΔαʔϏείʔϧ͸Ұͭʹ੍‫͓ͯ͠ݶ‬Γ, αʔϏείʔϧͷೖ‫ͱޱ‬ग़‫Ͱޱ‬ϩοΫΛऔಘ/ΔϨδελͰ͋Δ. αʔϏεϞδϡʔϧ͸ॲཧͷ࣮ߦͷͨΊʹstatus Ϩδελ‫܈‬ͷಡΈॻ͖Λߦ͏.

ղ์͢Δ͜ͱʹΑΓ͜ΕΛ࣮‫͍ͯ͠ݱ‬Δ.

TFi ͱ XF ʹ͸, αʔϏεཁ‫ٻ‬ͷ༗ແ, αʔϏεΛॲཧ͢ΔαʔϏεϞδϡʔϧͷ൪߸, αʔϏε‫ػ‬ೳͷ൪߸౳͕ූ߸Խ͞

3. RTOS ͷαʔϏεॲཧ‫ػ‬ೳͷू໿
3. 1 ֓Ε͍ͯΔ. TAi ͱ XA ͸Ϩδελ഑ྻͰ͋Γ, ཁ‫ٻ‬ͷ͋ͬͨαʔϏεʹඞཁͳ‫͚ͩ਺ݸ‬Ҿ਺͕ॻ͖ࠐ·ΕΔ.

ཁ

3. 2. 2 ॲཧͷྲྀΕຊߘͰ͸จ‫[ ݙ‬12] ͷख๏ʹ͓͍ͯ, λεΫʹ෼ࢄ͍ͯ͠ΔϚωʔδϟͷ۩ମతͳಈ࡞ͷྲྀΕ͸࣍ͷ௨ΓͰ͋Δ.

RTOS ͷαʔϏεॲཧ‫ػ‬ೳΛϚωʔδϟଆʹू໿͢Δ͜ͱʹΑͬͯճ࿏‫ن‬໛ͷ࡟‫ݮ‬Λ໨ࢦ͢ͱͱ΋ʹ, ‫ج‬ຊతͳαʔϏεॲཧΛ RTL Ͱ࣮૷͢Δ͜ͱʹΑ࣮ͬͯߦͷߴ଎ԽΛਤΔ. ͜ͷ0) λεΫ Ti ͸Ҿ਺Λ TAi ʹ, αʔϏεͷ ID ౳Λ TFi ʹॻ͖ࠐΉ͜ͱʹΑͬͯϚωʔδϟʹαʔϏεΛཁ‫͢ٻ‬Δ.

ͨΊʹ, λεΫ͔ΒαʔϏεॲཧΛ‫ى‬ಈ͢Δํࣜ΍, ಉ࣌ʹෳ਺ͷαʔϏεཁ‫͕ͨͬ͋ٻ‬৔߹ͷௐఀํࣜΛ৽ͨʹఏҊ͢Δ.

1) Ϛωʔδϟ͸ TFi Λ‫͠ࢹ؂‬, λεΫ Ti ͔ΒαʔϏεͷཁจ‫[ ݙ‬12] ͷख๏ͱຊߘͷఏҊख๏Ͱੜ੒͞ΕΔϋʔυ΢ΣΞ‫͕͋ٻ‬Ε͹, XF, XA, XT ʹͦΕͧΕ TFi, TAi, i Λॻͷߏ੒ΛͦΕͧΕਤ 3 (a)(b) ʹࣔ͢. ਤத T1∼T3 ͸λεΫΛ͖ࠐΉ. ෳ਺ͷαʔϏεཁ‫͕ٻ‬ಉ࣌ʹ͋ͬͨ৔߹, ͋Δ͍࣮ߦ͢Δϋʔυ΢ΣΞΛ, S1∼S4 ͸αʔϏεॲཧΛߦ͏ϋʔυ͸, ͋ΔαʔϏεཁ‫ٻ‬ͷॲཧ଴ͪͷؒʹผͷαʔϏεཁ‫ٻ‬΢ΣΞΛද͢. จ‫[ ݙ‬12] ͷख๏Ͱ͸, OS ͷαʔϏεॲཧΛλ͕͋ͬͨ৔߹ʹ͸, λεΫͷ༏ઌ౓౳ʹԠͯͦ͡ͷ͏ͪͷεΫଆͷϓϩάϥϜͷҰ෦ͱͯ͠ߴҐ߹੒͍ͯͨͨ͠Ί, ಉ͡1 ͭΛબ୒ͯ͠ XF, XA, XT Λॻ͖ࠐΉ. ͦΕҎ֎ͷαʔαʔϏεॲཧ͕ෳ਺ͷλεΫϞδϡʔϧதʹॏෳͯ͠ଘࡏͯ͠Ϗεཁ‫ٻ‬͸, ࣮ߦதͷαʔϏεͷऴྃΛ଴ͭ. ·ͨ, ࣮ߦঢ়- 40 -—3—఺Ͱ࣮ߦதͰ͋Γ, ͔ͭͦͷ࣌఺Ͱͷ༏ઌ౓͕࠷΋ߴ͍λεΫS0 DONE <= 0if (XF.mod == this) {if(XF.func == ACT TSK) {tskid <= XA[0]STATE <= A1} else if(XF.func == WUP TSK) {tskid <= XA[0]STATE <= W1} else if(XF.func == SLP TSK) {...
}}
A1 lock <= status[G][CPU LOCK]STATE <= A2
A2 if (lock) {XA[0] <= E CTX
DONE <= 1
STATE <= S0} else {
actcnt <= status[tskid][ACTCNT]STATE <= A3}
A3 if (actcnt >= TMAX ACTCNT) {XA[0] <= E QOVRDONE <= 1
STATE <= S0} else {stat <= status[tskid][TSKSTAT]STATE <= A4}
A4 if (stat != TTS DMT) {status[tskid][ACTCNT] <= act + 1} else {status[tskid][TSKSTAT] <= TTS RDY}
XA[0] <= E OK
DONE <= 1
STATE <= S0ͷϦΫΤετΛબ୒͢Δ. ͜Ε͸, λεΫͷঢ়ଶ΍༏ઌ౓͸, Ϧਤ 6: αʔϏείʔϧ act tsk ͷ ॲཧͷྲྀΕਤ 5: ϦΫΤετΞʔϏλͷճ࿏ߏ੒ଶҎ֎ͷλεΫ͔Βͷཁ‫ٻ‬͸, ͦͷλεΫ͕࣮ߦঢ়ଶʹͳΔ·Ͱॲཧ͞Εͳ͍.

2) αʔϏεϞδϡʔϧ͸, XF, XA, XT ʹॻ͖ࠐΈ͕͋Δͱ,ͦΕΛಡΜͰཁ‫͞ٻ‬ΕͨαʔϏεͷॲཧΛ࣮ߦ͢Δ. ॲཧ͕‫ྃ͢׬‬Δͱ, XA ʹฦΓ஋Λॻ͖ࠐΜͰ‫ྃ׬‬৴߸Λग़͢.

3) Ϛωʔδϟ͸ XA ͷฦΓ஋Λཁ‫͕ͨͬ͋ٻ‬λεΫͷ TAiʹίϐʔ͠, λεΫ Ti ʹ‫ྃ׬‬Λ௨஌͢Δ.

3. 2. 3 αʔϏεཁ‫ٻ‬ͷௐఀϦΫΤετΞʔϏλ (RA) ͸, ෳ਺ͷαʔϏεཁ‫͕ٻ‬ಉ࣌ʹൃੜ͍ͯ͠Δ৔߹ʹ, ࣍ʹ࣮ߦ͢ΔαʔϏεΛܾఆ͠, XF, XA,XT ϨδελΛհͯ͠౰֘αʔϏεϞδϡʔϧΛ‫ى‬ಈ͢Δ. αʔϏεͷબ୒͸, ͦͷ࣌఺ͰͷλεΫͷঢ়ଶͱ༏ઌ౓ʹ‫͍ͯͮج‬ߦ͏. ͢ͳΘͪ, ϦΫΤετΛग़͍ͯ͠ΔλεΫͷ͏ͪ, ͦͷ࣌ΫΤετΛग़͔ͯ͠Βॲཧ͕։࢝͞ΕΔ·Ͱʹมಈ͢ΔՄೳੑ͕͋ΔͨΊͰ͋Δ.

(ঢ়ଶ S0) XF Λ‫͠ࢹ؂‬, ͦ͜ʹॻ͖ࠐ·ΕͨαʔϏεϞRA ͷճ࿏ߏ੒Λਤ 5 ʹࣔ͢. TFi ʹϦΫΤετ͕࣮͋ͬͯ

δϡʔϧͷ ID (XF.mod) ͕ࣗ෼ͷ΋ͷͰ͋Ε͹ॲཧΛ։࢝͢ߦ͕ετʔϧঢ়ଶͰͳ͍λεΫͷ༏ઌ౓Λൺֱ͠, ༏ઌ౓࠷େΔ. ཁ‫͞ٻ‬Ε͍ͯΔαʔϏεͷ ID (XF.func) ͕ ACT TSK ͰͷλεΫͷ ID Λ XT ʹ, ରԠ͢ΔϦΫΤετͱҾ਺Λ XF ͱ͋Ε͹, Ҿ਺ tskid Λ XA ͔ΒಡΈग़͠, ঢ়ଶ A1 ʹભҠ͢Δ.

XA ʹॻ͖ࠐΉ.

(ঢ়ଶ A1) CPU ϩοΫ͕͔͔͍ͬͯͳ͍͔Ͳ͏͔Λௐ΂Δ3. 3 αʔϏεϞδϡʔϧͷಈ࡞ͨΊʹγεςϜঢ়ଶม਺ status[G][CPU LOCK] ΛಡΈग़͢.

αʔϏεϞδϡʔϧ͸ XF Λ‫͠ࢹ؂‬, XF ʹࣗ෼͕୲౰͢Δ(ঢ়ଶ A2) CPU ϩοΫ͕͔͔͍ͬͯΕ͹Τϥʔίʔυ E CTXαʔϏεͷ൪߸͕ॻ͔ΕΔͱॲཧΛ։࢝͢Δ. αʔϏεϞδϡʔΛϨδελ XA[0] ʹॻ͖ࠐΜͰ, ‫ྃ׬‬৴߸ DONE Λૹग़͠,ϧ͸ඞཁʹԠͯ͡ঢ়ଶϨδελʹΞΫηε͠, λεΫ΍γες଴‫ػ‬ঢ়ଶ (S0) ʹ໭Δ. ͦ͏Ͱͳ͚Ε͹, ର৅λεΫͷ‫ى‬ಈཁ‫ٻ‬Ϝͷঢ়ଶม਺Λࢀর/ߋ৽͢Δ. ࣮ߦ͕‫ྃ͢׬‬Δͱ (࣮ߦதʹΤΩϡʔΠϯάճ਺Λද͢ঢ়ଶม਺ΛಡΈग़ͯ͠, ঢ়ଶ A3 ʹભϥʔ͕ൃੜͨ͠৔߹Λ‫ؚ‬Ή), αʔϏείʔϧͷฦΓ஋Λ XA ϨҠ͢Δ.

δελʹ֨ೲ͠, ‫ྃ׬‬৴߸ (DONE) Λૹग़ͯ͠Ϛωʔδϟʹ‫׬‬ྃΛ௨஌͢Δ.

(ঢ়ଶ A3) ର৅λεΫͷ‫ى‬ಈཁ‫ٻ‬ΩϡʔΠϯάճ਺্͕‫ݶ‬Λ௒͍͑ͯΕ͹, Τϥʔͱͯ͠ E QOVR Λ XA ʹॻ͖ࠐΜͰऴαʔϏείʔϧ act tsk (Ҿ਺Ͱࢦఆͨ͠ ID ͷλεΫΛ‫ࢭٳ‬

ྃ͢Δ. ͦ͏Ͱͳ͚Ε͹, ର৅λεΫͷঢ়ଶΛಡΈग़͢.

ঢ়ଶ͔Β࣮ߦՄೳঢ়ଶʹભҠͤ͞Δ) ͷॲཧΛߦ͏αʔϏεϞ(ঢ়ଶ A4) ର৅λεΫ͕‫ࢭٳ‬ঢ়ଶͰ͋Ε͹‫ى‬ಈཁ‫ٻ‬ΩϡʔΠδϡʔϧͷಈ࡞ྫΛਤ 6 ʹࣔ͢. ͜ͷαʔϏεϞδϡʔϧ͸,ϯάճ਺Λߋ৽͠, ࣮ߦՄೳঢ়ଶͰ͋Ε͹࣮ߦঢ়ଶʹมߋͯ͠

act tsk Ҏ֎ʹ΋ wup tsk ΍ slp tsk ౳, λεΫͷ࣮ߦঢ়ଶΛ؅ऴྃ͢Δ (଴‫ػ‬ঢ়ଶʹ໭Δ).

ཧ͢ΔαʔϏείʔϧͷॲཧ΋ߦ͏. STATE ͸͜ͷϞδϡʔϧͷঢ়ଶϨδελͰ͋Γ, ͦͷॳ‫ظ‬஋͸ S0 Ͱ͋Δ. act tsk ͷͳ͓, ͜ͷΑ͏ʹॲཧ͕؆୯ͳ৔߹͸ RTL ͷઃ‫͖Ͱ͕ܭ‬Δ͕, ॲཧ͕ෳࡶͳ৔߹ʹ͸ߴҐ߹੒Λ༻͍ͯ΋ྑ͍.

ຊ࣭తͳॲཧ͸, ࢦఆ͞ΕͨλεΫͷঢ়ଶΛද͢ঢ়ଶม਺Λॻ

3. 4 αʔϏε‫ͼݺ‬ग़͖͠‫͑׵‬Δ͚͕ͩͩ, ΤϥʔॲཧͷͨΊʹෳ਺ঢ়ଶΛཁ͍ͯ͠Δ.

Ϩδελ TFi ͱ TAi ͸λεΫͷϝϞϦۭؒʹϚοϓ͞Εͯ۩ମతͳಈ࡞ͷྲྀΕ͸࣍ͷ௨ΓͰ͋Δ.

- 41 -—4—ද 1: sample1 ͷ߹੒݁Ռ
12
3
4
5
67

ER act_tsk ( ID tskid ) {TA [ T O P P E R S _ H W _ S E L F _ I D ][0] = tskid ;TF [ T O P P E R S _ H W _ S E L F _ I D ] = F_ACT_TSK ;do {;} while ( T_EXEC ( TF [ T O P P E R S _ H W _ S E L F _ I D ] ) );(a) ճ࿏‫ن‬໛จ‫[ ݙ‬12]#LUT #FF

modulereturn TA [ T O P P E R S _ H W _ S E L F _ I D ][0];}ਤ 7: act tsk ͷ‫ͼݺ‬ग़͠ຊ‫ڀݚ‬#LUT #FF

top3685272

arbiter

383

5366

5
5

serv main

none

none

368

79

serv othernone

none

3,098

163

manager

4,079

2,672

5,452

3,871

͍ΔͷͰ, λεΫ͸ͦͷΞυϨεʹରͯ͠ಡΈॻ͖͢Δ͜ͱʹ

TASK1

5,520

929

5,219

929

ΑΓ, αʔϏεͷ‫ى‬ಈͱฦΓ஋ͷड͚औΓΛߦ͏. αʔϏείʔ

TASK2

7,567

925

5,912

925

TASK3

7,189

965

6,035

965

MAIN TASK

6,199

9435,593943

EXC TASK

8,008

939

6,095939

total

39,313

7,383

38,4108,824ϧͷຊମ͸ TFi ͱ TAi ͷಡΈॻ͖Λߦ͏ελϒʹม‫͢׵‬Δ.

act tsk ͷελϒͷྫΛਤ 7 ʹࣔ͢. 2–3 ߦ໨ͰҾ਺ (tskid)ͱαʔϏε ID (F ACT TSK) ΛࣗλεΫ༻ͷ TAi[0] ͱ TFi ʹॻ͖ࠐΜͰ͍Δ. 4 ߦ໨Ͱ‫ྃ׬‬Λ଴ͪ (T EXEC ͸ TF தͷ‫ྃ׬‬(b) ΫϦςΟΧϧύε஗Ԇ [ns]௨஌ΛಡΈग़͢ϚΫϩͰ͋Δ), TAi[0] ͔ΒಡΈͩͨ͠Ҿ਺ΛฦΓ஋ͱͯ͠ฦ͍ͯ͠Δ. ʢ஫ 1ʣจ‫[ ݙ‬12]ຊ‫ڀݚ‬

13.09813.935͜ͷελϒΛλεΫதʹϚΫϩల։͢Δ͜ͱʹΑΓ, αʔϏ(c) ࣮ߦαΠΫϧ਺ͱ஗ԆείʔϧΛ‫ؚ‬ΊͨλεΫΛߴҐ߹੒͢Δ͜ͱ͕Ͱ͖Δ.

4. ࣮૷ͱ࣮‫ݧ‬

service callจ‫[ ݙ‬12]#cycle latency [ns]act tsk
wup tsk
ext tskras terter tsk
slp tskຊख๏ʹ‫ ͖ͮج‬TOPPERS/ASP3 ෇ଐͷαϯϓϧϓϩάϥ
Ϝ “sample1” Λϋʔυ΢ΣΞԽͨ͠.
͜ͷϓϩάϥϜ͸, શମΛ੍‫͢ޚ‬ΔλεΫ MAIN TASK, ྫ֎Λॲཧ͢ΔλεΫ EXC TASK ͓Αͼ 3 ͭͷฒߦ࣮ߦλε

23
28
12
26
23
16

301.3
366.7
157.2
340.5
301.3
209.6

ຊ‫ڀݚ‬

#cyclelatency [ns]

999
10
8
14

125.4
125.4
125.4
139.3
111.5
195.1

Ϋ TASK1, TASK2, TASK3 ͔ΒͳΔ. MAIN TASK ͸γϦ
High-level synthesizer: ACAP [16]Logic synthesizer: Xilinx Vivado (2016.4)
Target: Xilinx Artix-7 (xc7a100tcsg324-3)

Ξϧ௨৴͔ΒͷϝοηʔδΛड͚ͱΓ, ҎԼͷαʔϏείʔϧΛ࣮ߦ͢Δ.

act tsk, can act, ter tsk, chg pri, get pri, wup tsk,can wup, rel wai, sus tsk, rsm tsk,

౴ੑೳΛද 1 (c) ʹࣔ͢. #cycle ͸, ֤αʔϏείʔϧ͕‫ݺ‬͹

loc cpu, unl cpuΕ͔ͯΒঢ়ଶ͕ߋ৽͞ΕΔ·Ͱͷ࣮ߦαΠΫϧ਺Λද͢. ྫ͑ͨͩ͠, ΞϥʔϜϋϯυϥ, αΠΫϧϋϯυϥͱׂΓࠐΈϋϯυϥ͸ະ࣮૷Ͱ͋Γ, ؔ࿈͢ΔαʔϏείʔϧͷ‫ͼݺ‬ग़͠͸࡟আ
͍ͯ͠Δ.
Ϛωʔδϟ͸ Verilog HDL Ͱઃ‫ͨ͠ܭ‬. αʔϏεϞδϡʔϧʹؔͯ͠͸ Verilog HDL Ͱ࣮૷, TOPPERS/ASP3 ͷαʔϏείʔϧ 178 ‫ݸ‬தλεΫૢ࡞ʹؔ͢Δ 28 ͷαʔϏείʔϧΛαϙʔτͨ͠. λεΫϞδϡʔϧ͸όΠφϦ߹੒γεςϜ͹, 1 ߦ໨ͷ act tsk ͸, λεΫΛ‫ࢭٳ‬ঢ়ଶ͔Β࣮ߦՄೳঢ়ଶʹભҠͤ͞Δ·ͰͷαΠΫϧ਺Ͱ͋Γ, จ‫[ ݙ‬12] ͷ൒෼ҎԼʹ࡟‫͍͖ͯͰݮ‬Δ. ॲཧͷ಺༰ࣗମ͸มΘ͍ͬͯͳ͍ͷͰ, RTL Ͱ௚઀ઃ‫ͨ͠ܭ‬Ө‫͑ߟͱڹ‬ΒΕΔ. latency ͸ຊख๏Ͱ͸࣮ߦαΠΫϧ਺ͱΫϦςΟΧϧύε஗ԆͷੵͰ͋Δ. ͍ͣΕͷαʔϏείʔϧ΋ 200 ns Ҏ಺ʹ࣮ߦ͢Δ͜ͱ͕Ͱ͖ͨ.

5. Ή ͢ ͼ

ACAP [16] ʹΑΓ߹੒ͨ͠.
͜ΕΒ ͷઃ‫ܭ‬͸, Xilinx Vivado 2016.4 Ͱ Xilinx FPGAArtix-7 (xc7a100tcsg324-3) Λλʔήοτʹ࿦ཧ߹੒ͨ͠.
߹੒֤ͨ͠Ϟδϡʔϧͷճ࿏‫ن‬໛Λද 1 (a) ʹࣔ͢. TASK1,TASK2, TASK3 ͷճ࿏‫ن‬໛͸จ‫[ ݙ‬12] ʹൺ΂ͯ࡟‫͍͖ͯͰݮ‬Δ. ͨͩ͠, ͦͷ෼αʔϏεϞδϡʔϧ (serv main, serv other)ͱϚωʔδϟͷϦΫΤετΞʔϏλ͕ඞཁʹͳͬͨͨΊ, શମͱͯ͠͸ճ࿏‫ن‬໛Λ͋·Γ࡟‫͔ͨͬͳ͖Ͱݮ‬. ͜Ε͸, ࠓճͷ

sample1 Ͱ࢖ΘΕ͍ͯΔαʔϏείʔϧͷॲཧࣗମ͕ܰྔͳͨΊ, ճ࿏‫ن‬໛࡟‫ݮ‬ͷޮՌ͕पลͷΦʔόϔουͷ૿ՃΛେ্͖͘ճΒͳ͔ͬͨͨΊͱߟ͑ΒΕΔ.
߹੒ͨ͠γεςϜͷΫϦςΟΧϧύε஗ԆΛද 1 (b) ʹ, ԠຊߘͰ͸, จ‫[ ݙ‬12] ͷ RTOS Λ༻͍ͨγεςϜͷϑϧϋʔυ΢ΣΞ߹੒ʹ͓͚Δճ࿏‫ن‬໛ͷ࡟‫ߴͱݮ‬଎ԽΛ໨తͱͨ͠ճ࿏ߏ੒๏ΛఏҊͨ͠. λεΫʹ෼ࢄ͍ͯ͠Δ RTOS ͷαʔϏεॲཧ‫ػ‬ೳΛϚωʔδϟଆʹू໿͠, ‫ج‬ຊతͳαʔϏεॲཧΛ

RTL Ͱ࣮૷ͨ͠. ·ͨ, ͜ΕΛ࣮૷͢ΔͨΊͷαʔϏεॲཧ‫ى‬ಈํࣜΛఏҊͨ͠.
࣮‫ݧ‬ͷ݁Ռ, ຊख๏ʹΑΓੜ੒͞Εͨϋʔυ΢ΣΞͷճ࿏‫ن‬໛͸, จ‫[ ݙ‬12] ͷγεςϜͱൺֱͯ͠େ͖͘࡟‫͢ݮ‬Δ͜ͱ͸Ͱ͖ͳ͔͕ͬͨ, ࣮ߦ଎౓͸޲্ͨ͠.
‫ࡏݱ‬, ຊߘͷఏҊํࣜʹ‫ ͍ͯͮج‬MUTEX, Πϕϯτϑϥά,Ωϡʔ౳ͷॲཧΛߦ͏ϋʔυ΢ΣΞͷઃ‫ܭ‬ΛਐΊ͓ͯΓ, ϋʔυ΢ΣΞԽՄೳͳ TOPPERS/ASP3 ͷαʔϏε‫ػ‬ೳΛ֦େ͠ʢ஫ 1ʣɿ4 ߦ໨ͷΑ͏ʹ‫ྃ׬‬௨஌ΛϙʔϦϯά͢ΔͷͰ͸ͳ͘, ฦΓ஋ͷಡΈग़͍ͯ͠Δͱ͜ΖͰ͋Δ. ·ͨ, ఏҊํࣜΛ FreeRTOS ʹ΋ద༻ͰͰλεΫΛετʔϧͤͯ͞΋ྑ͍.

- 42 -—5—͖ΔΑ͏ʹ͢Δ‫ܭ‬ըͰ͋Δ.
ճ࿏‫ن‬໛͕େ͖͍͜ͱ͕Ұͭͷ՝୊Ͱ͋Δ͕, όΠφϦ߹੒synthesizer based on MIPS object codes,” in Proc. ITCCSCC 2014, pp. 725–728 (July 2014).

γεςϜ ACAP ͷ߹੒ํࣜʹͦͷҰҼ͕͋Δͱߟ͑ΒΕΔͨ
Ί, Vivado HLS ౳ͷ൚༻ߴҐ߹੒γεςϜͰ߹੒Ͱ͖ΔΑ͏ʹΞʔΩςΫνϟΛௐ੔͢Δ͜ͱ΋ࠓ‫ޙ‬ͷ՝୊Ͱ͋Δ.
ँࣙຊ‫ͯؔ͠ʹڀݚ‬༗ӹͳ‫ݴॿޚ‬Λ௖͍ͨ‫໋ཱؗݩ‬େֶͷத୩ਹ೭ࢯ, ‫ݩ‬ؔ੢ֶӃେֶͷాଜਅฏࢯ, ͓Αͼ͝ࢧԉΛ௖͍ͨؔ੢ֶӃେֶੴӜ‫ݚ‬‫ࣨڀ‬ͷॾࢯʹ‫ँײ‬க͠·͢. ຊ‫ڀݚ‬͸Ұ෦ JSPS Պ‫ݚ‬අ 19H04081 ͓Αͼ 20H00590 ͷॿ੒ʹΑΔ.

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