Low Level RF Development ine‐/e+ Injector‐LINAC○Takako Miura, Hiroaki Katagiri, Shinichiro Michizono, Yoshiharu YanoContents
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Overview of LINAC RF System
EsOmaOon of LINAC RF Stability
Design of new RF DRIVER & RF MONITOR
PerformanceSchedule1

IntroducOon of LINAC RF System: klystron unit

Energy feedback

RF gunBAC

1 SecOon

LINAC has about 60 klystron‐units.
 RF is basically controlled by one RF driver in each sector .
means special place to be driven individually by each RF driver.
(RF‐Gun, Energy Feedback secOon, Positron Capture secOon etc.)
e+ Capture

2 Energy FB

e+ target
2m ACC x 4(160 MeV/Unit)

SLED40MWKlystron

SLED40MWKlystron

8 klystrons

IΦAIΦA
60kW SB
RF Drive unit

600W Amp
RF Drive unit

DR34Energy
5FB

40 MW klystron feeds RF to 4 acceleraOng
caviOes. AcceleraOon gain is ~160 MeV per unit.

60 kW sub‐booster klystron(SB) is installed ineach sector as a driver amp.
1 SB drives max. 8 high power klystrons.
In the place to need to change RF phaseindividually, 600W solid state amp(SSA) has
been installed per one unit.
2High Power RF Source
SLEDKlystronRF frequency

2856 MHzRF pulse width

4 µs

Typical output power

40 MWPerveance

2.1 µA/V3/2

Beam Voltage

300 kV

RepeOOon Rate

50 Hz

eﬃciency

45 %

400

60

300

50200

40

100

30020-100

10-2000-300-10-400-8-6-4-2Time(µs)

0-20
2 3RF Output Power(MW)Pulse Transformer Tank

Klystron SpeciﬁcaOons

Klystron Voltage(kV)
Klystron Current(A)Klystron Pulse Modulator

EsOmaOon of RF Stability< RF stability of Klystron>
K(Perveance) = I/V
Stability of Klystron High Voltage: ΔV/V (%)= 0.3 % p‐p
P= ηIV = η KV3/2V = η KV5/2.
(0.05% rms)
ΔP/P=5/2 ΔV/V.
RF variaOon due to high voltage jimer per klystron:
ΔE/E = 5/4 ΔV/V ←(𝐸∝√⁠𝑃 )Amplitude stability ΔA/A(%)= 5/4 ΔV/V(%)= 0.063% rms
Phase stability :Δθ= ‐4deg*Δ V/V(%)= ‐/+0.2deg rms (from ‐4deg/%)
ΔVacc/Vacc (%)=0.12 % rms at ‐10deg oﬀ‐crest​cos⁠(​𝜃↓0 ) −​(1+​∆𝑉/𝑉 )cos⁠(​𝜃↓0 +∆𝜃)0.15 % rms at ‐15deg oﬀ‐crest
3/2

Assuming there is no correlaOon to jimer between power supplies,
error of total energy is compressed to1/√⁠𝑁 . (N : number of klystrons)e.g. e‐: N=50 ‐> δ=0.15/√⁠50 =0.021% rms@ ‐15 deg oﬀ‐crest<RF error caused by Low Level RF> e+: N=30 ‐> δ=0.15 /√⁠30 =0.033% rms@ ‐15 deg oﬀ‐crest
Klystron Pout

RF saturaOon point of klystron is adopted as RF operaOon point.

Input RF amplitude ﬂuctuaOon becomes insensiOve .
Phase jimer Δθ of input RF ~ 0.1deg rms per RF Drive Unit.
Klystron Pine.g. e‐: N=8 ‐> δ=0.045/√⁠8 =0.016% rms@ ‐15 deg oﬀ‐crest
e+: N=4 ‐> δ=0.045 /√⁠4 =0.023% rms@ ‐15 deg oﬀ‐crest

EsOmaOon : Error caused by RF system:

0.026 % rms for e‐ @ ‐15deg oﬀ‐crest
0.040 % rms for e+ @ ‐15deg oﬀ‐crest

Requirement of beam energy spread for SuperKEKB: 0.08% rms.

4

Towards 4‐Ring Simultaneous InjecOon
Injector‐LINAC provides the beams to 4‐diﬀerent rings with diﬀerent energies.
HER: 7 GeV e‐Accelera;onee+ target
1.5 GeVCAccelera;one+
23Decelera;on PF: 2.5 GeV e‐

45RF phase change is necessary according to the “Beam Mode” in 50 Hz.
For high stability, RF modulaOon Oming should be synchronize the clockof “Timing System” (114.24 MHz).

KLYSLEDLER: 4 GeV e+Stand‐by

1RF Drive Unit

AR: 6.5 GeV e‐

Kly PfPbPf
Acc out

RF Monitor
Data taking and idenOﬁcaOon of “Beam Mode” in 50 Hz are necessary.

5Development of new RF Drive Unit & RF Monitor
IQ digital control
IQ Modulator /IQ Demodulator
ICommon design is adopted
Xilinx ML605 FPGA
evaluaOon board

IQ‐modulator or IQ‐demodulator
are mounted on rear side.
I+I‐

LO

RFQ+Q‐Q

Ethernet
ADC/DAC

Data are sent to EPICS IOC server

Digital processing
with “FPGA”
14bit ADC/DAC board
Touch panel

Parameter seung is possible
from front touch panel.

Clock : 114.24 MHz

SFP OpOcal Transceiver

Sampling clock synchronize
to “Event Timing System”

RecepOon of Event mode and phase
informaOon from event generator
6RecepOon Test of Event Data
ML605 Xilinx FPGA board
Input 50‐Hz Trigger

FPGA

114.24 MHz
reference clock ofEvent System

Mode : PFe‐ 2Hz50 Hz counter Event codeobtained

Phase datataking test
SD EV DB EV
00 00 01 00
00 BC 00 00
00 00 02 00
00 BC 00 00
00 00 03 00
00 BC 00 00
00 00 04 00
00 BC 00 00
00 00 05 00
00 BC 00 00
00 00 06 00

SFP(OpOcal Transceiver)
Serial signal of 2GHz
Event data are sent from Event‐
Generator via opOcal ﬁber

2345600 00 03 00
996
00 BC E4 00
00 00 03 00 997
00 BC E5 00
00 00 03 00
998
00 BC E6 00GbE
Data is sent to a serverusing GbE via SiTCP

Receive of beam mode and phase from“Event System” has been conﬁrmed.

152 : PF e‐
182: No InjecOon Mode

“2K Byte Data Buﬀer” isused for sending phasedata informaOon 7

SpeciﬁcaOon of RF Drive Unit
FuncOons :1. RF ModulaOon
2. VSWR measurement for Klystron output
3. Fast Interlock output for Klystron protecOon
4. RF‐monitor 1ch
5. Analog video out
Modulator speciﬁca9on

Photo of the front touch panel

Seung resoluOon: 0.1 %, 0.1deg
Reproducibility(Accuracy of phase): < 0.2% rms, <0.2 deg rms
AModulator out
180°Amplitude
θt0Phase

t1 t0+4µs

4 µs

ASLED OUT
8

SpeciﬁcaOon of RF Monitor
Previous RF Monitor for KEKBRF Monitor for SuperKEKB

ADC

8 bit, 1GHz, 2 RF

14 bit, 114MHz, 5 RFs

Measurement region< 40deg., 2µs360deg, ACC 9µs / STB 9µs

50Hz data acquisi;on

NG (Max 25Hz)

Iden;ﬁca;on of the events
Precision

OKNG

OK

0.15%rms, 0.2deg rms

0.1% rms, 0.1 deg rms

New RF‐Monitor can take whole RF waveform, and can idenOfy the event mode.
Trigger

4 µs

60µs

SLED_AMP
1024

ACC

1024

Stand‐byPulse is always output in either
the ACC or STB.

KlyPf_Phase
Analog video out

9Performance of ADC board
Monitor input : CW 2856 MHz
5706

Amplitude:
0.05 % rms
std=0.050651%rms

Phase: 0.03 deg. rms
std=0.02961deg.rms

169.05

0.1%

5704
5702

0.1deg169

5696

std=0.050651%rms

5705

5694

amp.

5692

5700

5690 5695
5688
5686

Phase [deg.]

5698

168.95168.9

168.85569005685

50105time [us]15168.82010time [us]015520101520time [us]@100MHz sampling

0FFT [dBc/50kHz]

Amplitude

5700

FFT-50No spurious-100-150

0102030freq [MHz]

4050

10

RF Monitor Data Taking Test
Event Code=182 (No injecOon mode)

SLED_AMP

NIM: no injecOon mode is selectedzoom

Data taking and event mode idenOﬁcaOon has been achieved.
Data correcOon will be performed in PC server(EPICS IOC).

11

Schedule of RF Drive Unit 8 RF Drive Units have been already installedand operaOon has been started:
KL_15, KL_16, KL_17, KL_18, KL_3T,SB_5, KL_51, KL_52
 End of June 2014, all “RF Drive Units” will bedelivered.
 From Sept. 2014, operaOon using “RF DriveUnits” will be started.

A2, A1‐B A1‐A,SB‐A

B‐6,B‐5,SB‐B

RF GUN

SB‐C

SB‐1

1‐5,1‐6,1‐7,1‐8

3T

SB‐2,2‐7,2‐8

SB‐3,3‐2,3‐3

SB‐5, 5‐1,5‐2
SB‐4,4‐4A,4‐4B

Already installed12Schedule of RF Monitor
Total=70 set
June 2014: 35 RF Monitors will be delivered.
RF Monitor will be installed per each 2‐Klystron Units, respecOvely.
(TentaOvely, whole area of LINAC will be covered.)
Sept. 2014: OperaOon of RF monitor system will be started.

Ref.
KLY
SLEDKLY

Sept.2014~

Kly PfPb
Pf
Acc out

RF Monitor
2ch

Data

GbE

1U rack server

2ch

SLED

Kly PfPb
Pf
Acc out

EPICS IOC

13Schedule of RF Monitor
Total=70 set
June 2014: 35 RF Monitors will be delivered.
RF Monitor will be installed per each 2‐Klystron Units, respecOvely.
(TentaOvely, whole area of LINAC will be covered.)
Sept. 2014: OperaOon of RF monitor system will be started.
Feb. 2015: Another 35 RF monitors will be delivered.
Dec. 2015:RF Monitor will be installed per each Klystron Unit.
Dec. 2015~RF Monitor
KLYSLEDSept.2014~

Kly PfPb
Pf
Acc out

4ch+Ref.

RF Monitor
DataGbE

1U rack server

4ch+Ref.

KLY
SLED

Kly PfPb
Pf
Acc out

EPICS IOC14

Summary
New RF Drive Unit & RF Monitor have been developed forSuperKEKB.
RecepOon of event code and phase data from Event Generator
have been tested.
Performance of ADC board was conﬁrmed.
Data taking of RF Monitor via EPICS IOC has already performed.
About long term stability and data correcOon, the study has
been conOnued.
15

Backup Slides

16

Klystron Phase VariaOon due to High Voltage Error
Phase changes depending on electron driy Ome from input cavity to output cavity of klystron.

​m↓0 𝛾​𝑐↑2 =​m↓0 ​𝑐↑2 +𝑒𝑉
𝛾=1+​𝑒𝑉/​m↓0 ​𝑐↑2
∆𝛾=​𝑒∆𝑉/​m↓0 ​𝑐↑2 =​𝑒𝑉/​m↓0 ​𝑐↑2 ​∆𝑉/𝑉
θ=​L/βc ∙𝑓∙360°∆θ=−360°∙𝑓​L/c ​∆𝛽/​β↑2 =−360°∙𝑓​L/c ​∆γ/​γ↑3 ​1/​𝛽↑3 =−360°∙𝑓​L/c ​∆γ/​(​γ↑2 −1)↑​3/2 =−360°∙​𝑓𝐿/𝑐 ​[​(1+​𝑒𝑉/​m↓0 ​𝑐↑2 )↑2 −1]↑−​3/2 ​𝑒𝑉/​m↓0 ​𝑐↑2 ​∆𝑉/𝑉

L=403mm, V=300 kV => Δθ= ‐3.99 deg/%
17SpeciﬁcaOon of RF Drive Unit
Seung resoluOon: 0.1 %, 0.1deg
Reproducibility: < 0.2% rms, <0.2 deg rms

AFuncOons : IQ ModulaOon / RF‐monitor 1ch/
VSWR meter/Interlock out / Analog video outLOθ

t0IQ
Detector

I180°

SLED INt1 t0+4µs

AQ

SLED OUT
114.24MHz (Reference Clock)

PfPbVideo outAmp.
PhaseAnalog out ‐> MulO‐meterPulse Trigger
0° /180° Trigger
ATT control
Phase control

ML605
FPGA
Vertex6

AD/DA
board
(12ch)
14bit

Log
AMP

Interlock Out

MO:2856 MHzPfLog
AMP

I
LO

VSWRPbQ

IQ
Modulator
Main Drive Line

20W
AMP

600W
AMP

Klystron18

Diagram of RF Monitor
14 bit, 114 MHz
Man-machineInterface

Monitor Out

DAC

Monitor Out

ADC/DAC board

DAC

Micro-processor

Xilinx ML605
Virtex6 FPGA

Event Signal
OpOcal ﬁber
PC server
EPICS IOC GbE

SFP
Tx/Rx

Event
receiverPHY SiTCPFMC Connector

50Hz Trigger

ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC

I

RF Ch.1

I

RF Ch.2

I/Q
Q demodulator
I/Q
Q demodulator
I
I/Q
Q demodulator

RF Ch.3

I

RF Ch.4

I

RF Ch.5

I/Q
Q demodulator
I/Q
Q demodulator

LO 2856 MHz

ANALOG DEVICES, AD9254 (14bit, max 150 MHz)
19