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PAPER

Special Section on Analog Circuits and Related SoC Integration Technologies

A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple
Sampling Correlators Eliminating Need for Phase Synchronizationin 65-nm CMOS
Lechang LIU†a) , Zhiwei ZHOU† , Nonmembers, Takayasu SAKURAI† , Fellow,
and Makoto TAKAMIYA†† , Member

SUMMARY
A low power impulse radio ultra-wideband (IR-UWB) receiver for DC-960 MHz band is proposed in this paper. The proposed receiver employs multiple DC power-free charge-domain sampling correlators to eliminate the need for phase synchronization. To alleviate BER
degradation due to an increased charge injection in a subtraction operationin the sampling correlator than that of an addition operation, a comparator
with variable threshold (=oﬀset) voltage is used, which enables an additiononly operation. The developed receiver fabricated in 1.2 V 65 nm CMOS
achieves the lowest energy consumption of 17.6 pJ/bit at 100 Mbps in stateof-the-art correlation-based UWB receivers.
key words: impulse radio ultra-wideband (IR-UWB), charge-domain sampling correlators, charge injection, variable threshold comparator, low
power

1.

Introduction

Impulse radio ultra-wideband (IR-UWB) has been investigated as a radio technology that can achieve lower power
than carrier-based UWB (e.g., OFDM-UWB [1]). IRUWB receiver can be classified as threshold detectionbased receiver [2], [3] and correlation-based receiver [4],[5]. Correlation-based UWB receiver attains superior noise
performance and robust narrowband interference suppression at the expense of increased power consumption andincreased circuit complexity over threshold detection-based
receivers. This work aims to minimize power dissipationof correlation-based receiver by employing multiple DC
power-free charge-domain sampling correlators to eliminate
the need for phase synchronization. The variable thresholdvoltage comparator can eliminate the subtraction operationfrom the conventional sampling correlator to alleviate the
BER degradation due to the increased charge injection in
the subtraction circuits.
Overview of the proposed receiver architecture is described in Sect. 2. Section 3 presents the circuit implementations of the sampling correlators and the variable threshold voltage comparator. Experimental results are presented
in Sect. 4 and Sect. 5 concludes the paper.
Manuscript received October 14, 2009.
Manuscript revised January 15, 2010.
†
The authors are with Institute of Industrial Science, The University of Tokyo, Tokyo, 153-8505 Japan.
††
The author is with VLSI Design and Education Center, The
University of Tokyo, Tokyo, 113-0032 Japan.
a) E-mail: llch@iis.u-tokyo.ac.jp
DOI: 10.1587/transele.E93.C.796

2.

Impulse Radio UWB Receiver Architecture

In the conventional IR-UWB receiver, correlation operation
is implemented in the continuous-time voltage domain [5]as shown in Fig. 1. Both the incoming signal (v s ) and thetemplate (vt ) of the correlator are represented by the voltage. To reduce the power consumption of the analog voltage multiplier, the correlator in the proposed receiver is designed in the discrete-time charge domain. In the discretetime charge domain, the incoming signal and the template
are represented by the voltage (v s ) and the capacitance (ct ),respectively. The multiplication of v s and ct is performed by
the charge of the sampling correlator and the analog voltage
multiplier is not required, thereby achieving the lower power
than the conventional continuous-time voltage correlator.
In Figs. 2(a) and (b), the conventional [4] and the proposed receiver architecture with the sampling correlator arecompared. The conventional receiver in Fig. 2(a) has single sampling correlator and a phase synchronization circuit.
The single sampling correlator has both addition and subtraction circuits as shown in Fig. 3, because the charge domain correlation is performed by both addition and subtraction of charges. φA and φE show sampling clocks with
diﬀerent phases. The new receiver architecture with multiple sampling correlators eliminating the need for phasesynchronization and the subtraction circuits is proposed andFig. 1 Conventional continuous-time voltage correlator and proposed
discrete-time charge domain correlator.

c 2010 The Institute of Electronics, Information and Communication Engineers
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Fig. 3

Addition and subtraction circuits in sampling correlator.

Figure 2(c) shows the correlator output waveforms of
the proposed receiver for data “1” and data “0.” Two 4input comparators in Fig. 2(b) are used to detect data “1”and data “0” respectively. When the upper correlator output (V1 − V2 ) is higher than the lower correlator output(V1b − V2b ) by the threshold (=oﬀset) voltage (VT H1 ) of thecomparator1, the output data is decided as “1” by the comparator1. On the contrary, when the lower correlator output(V1b −V2b ) is higher than the upper correlator output (V1 −V2 )by the threshold (VT H2 ) of the comparator2, the output data
is judged as “0” by the comparator2. VT H1 should be set tocorrectly detect the data “1,” and VT H2 should be set to correctly detect the data “0.” The VT H1 and VT H2 tuning circuit
was not implemented in this work.
3.

Circuit Implementation

3.1 DC Power-Free Pulse DiscriminatorFig. 2 (a) Conventional IR-UWB receiver architecture [4] with single
sampling correlator and phase synchronization circuit. (b) Proposed IRUWB receiver architecture with multiple sampling correlators eliminatingphase synchronization circuit. (c) Correlator output waveforms of the proposed receiver for data “1” and data “0.”shown in Fig. 2(b) (The front-end amplifier was not implemented in this work). The received single input is first converted to diﬀerential outputs by the front-end amplifier andthen correlated with the discrete templates in the multiple
sampling correlators. In the multiple sampling correlators,
4 sets of the sampling correlator always perform the correlation operation with 1-ns phase diﬀerence, thereby eliminating the power consuming phase synchronization circuit.
4-input comparators with built-in digitally tunable threshold voltages performs the subtraction function instead of thesampling correlator in the conventional architecture, thereby
eliminating the subtraction circuits in the sampling correlator and preventing the BER degradation.

Figures 4(a) and (b) show the circuits and the timing chartof the proposed multiple sampling correlators, respectively.
The multiple sampling correlators have 4 sets of single sampling correlator and each single sampling correlator is composed of four capacitors and eight switches. The proposed
multiple sampling correlators have only addition operationin order to alleviate BER degradation due to an increased
charge injection in the subtraction operation in the conventional sampling correlator than that of the addition operation. The received 100-Mbps Gaussian first-order derivative
pulse with 4-ns width is sampled at 1 GSa/s and correlatedwith the discrete templates in the multiple sampling correlators. The discrete templates are determined by the capacitance values of the sampling correlators. Sampling operation is implemented by turning on the switches controlled
by clocks φ1 , φ3 , φ5 , and φ7 sequentially and sampling results are stored in the corresponding capacitors respectively.
Summing and averaging results of the four sampling correlators are calculated and dumped to the following comparators by turning on the switches controlled by clocks φ2 ,φ4 , φ6 , and φ8 sequentially. In this way, 4 sets of the single sampling correlator always perform the correlation operation with 1-ns phase diﬀerence, thereby eliminating thepower consuming phase synchronization circuit.
In Fig. 5, the conventional [4] and the proposed implementation of the correlation calculation are compared in or-

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Fig. 5 Implementation of correlation calculation. (a) Conventional
implementation [4]. (b) Proposed implementation.

Fig. 4 Proposed multiple sampling correlators. (a) Circuit schematic. (b)Timing chart.

der to show how the variable threshold voltage comparator
removes the subtraction operation in the conventional sampling correlator. In Fig. 5, one comparator, a single samplingcorrelator, and single-ended signal are shown for simplicity,
though two comparators, two multiple sampling correlators,
and diﬀerential signal are used in the actual receiver shownin Fig. 2(b). φA , φB , φC , φD , φE , φ1 , φ3 , φ4 , φ5 and φ7 show
sampling clocks with diﬀerent phases. In the conventional
implementation shown in Fig. 5(a), both addition and subtraction calculations are performed by the sampling correlator, and the comparator compares the correlator output andVref 1 . In contrast, in the proposed implementation shown in
Fig. 5(b), only addition calculation is performed by the sampling correlator and the subtraction calculation is performedby the variable threshold voltage comparator by comparing
the two outputs of the sampling correlator with the threshold(=oﬀset) voltage (VT H ). As shown in the equations in Fig. 5,
the correlation calculations of Figs. 5(a) and (b) are equivalent. In this way, the variable threshold voltage comparator
removes the subtraction operation in the conventional sampling correlator and contributes to the BER improvement.
The design of the sampling rate of the proposed multiple sampling correlators is discussed. The sampling rate
determines the trade-oﬀ relationship between the BER andthe power consumption. Lower BER can be achieved withhigher sampling rate. However, the number of the capacitors is proportional to the square of the sampling rate andtherefore the power consumption of the correlator is proportional to the cubic of the sampling rate. For example,
1 GSa/s requires 4 correlators and 4 × 4 capacitors while
2 GSa/s requires 8 correlators and 8 × 8 capacitors. Figure 6(a) shows the simulated BER dependence on Eb /N0
with various sampling rates under the perfect phase synchronization condition (ΔT/T = 0%). The higher sampling rateachieves the lower BER at the cost of high power. BER
is also determined by the timing mismatch ΔT between theincoming signal and the templates of the sampling correlators. Figure 6(b) shows the simulated BER dependence on
ΔT/T with various Eb /N0 at 1 GSa/s. When Eb /N0 is higher
than 2.5 dB, BER is less than 3 × 10−3 . In this way, 1 GSa/s
can tolerate any ΔT and eliminate the need for phase synchronization. In this work, therefore, 1 GSa/s is adopted tominimize the power consumption of the multiple samplingcorrelators with a reasonable BER.
3.2 Variable Threshold Voltage Comparator
The developed transceiver is proposed for ad hoc and sensor
network where groups of wireless terminals are located in alimited area and communicate in an infrastructure-free fashion without any central coordinating unit or base-station.
The received signal strength can be aﬀected by path loss andmulti-path eﬀect, which are largely depending on the distance between the transmitter and receiver antennas. Variable gain amplifier (VGA) is required in the real application. However in this work VGA is not implemented andLIU et al.: A 1.76 MW 100 MBPS IMPULSE RADIO UWB RECEIVER

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therefore the variable threshold voltage comparator is used.
In this section, the circuit implementation of variable
threshold (=oﬀset) voltage comparator to eliminate the subtraction operation from the conventional sampling correlator is shown. Figure 7 shows the four-input comparator withbuilt-in digitally tunable thresholds based on variable resistance method. The comparator is based on [6], [7] and digital tunability is added to [7]. The four inputs are connected
to V1 , V2 , V1b , and V2b in Fig. 2(b). In Fig. 7, the lower set ofnMOSFET’s operate in the triode region and they are con-nected to the input and the reference voltages (VREFL and
VREFR ). The threshold voltage (VT H ) of the comparator isdetermined by Eq. (1) [7]:VT H = (VREFR − VREFL )Fig. 7Four-input variable threshold voltage comparator.

(1)

The Wtotal in Eq. (1) can be calculated as:
Wtotal = (a0 + 2 × a1 + 4 × a2 + 8 × a3 )W(2)where ai = 0 (i = 0, . . . , 3) when the corresponding switch
is turned to ground and ai = 0 when the switch is turned to
VREFL /VREFR .
Therefore, by changing Wtotal by changing the gate
voltage of the lower set of nMOSFET’s with the switches,
the threshold voltage of the comparator is varied digitallywith a good linearity. The comparator has 4 bits for the variable threshold voltage.
4.

Fig. 6 (a) Simulated BER dependence on Eb /N0 with various sampling
rate under the perfect phase synchronization condition (ΔT/T = 0%). (b)Simulated BER dependence on timing mismatch ΔT/T between input signal and template signal with various Eb /N0 at 1 GSa/s.

Wtotal /L
W1 /L1

Experimental Results

The proposed UWB receiver shown in Fig. 2(b) except LNA
was designed and fabricated in 1.2 V 65 nm CMOS process.
The chip micrograph is shown in Fig. 8. The die size is1050 × 670 μm2 and the core area is 110 × 30 μm2 .
Figure 9 shows the measured threshold (=oﬀset) voltage dependence on the 4-bit digital control of the proposedcomparator. Three dies are measured. The die-to-die variation could be compensated by the digital calibration using
the digital control bit. The deviation and the notch of themeasured comparator threshold voltage are due to the sizeof the lower set of transistors operating in the triode region.
In this work, small size is used to minimize the power consumption of the proposed comparator. The linearity of thecomparator threshold can be improved by increasing the sizeof the transistors. The impact of the nonlinearity for thesystem is compensated by oﬀ-chip calibration. The calibration must monitor the input noise signal and adaptively set
a threshold such that only a small percentage of false detections will occur.
Figure 10 shows the measured output of the receiverwith diﬀerent comparator thresholds (VT H1 and VT H2 ). Input BPSK signal was generated with an arbitrary waveformgenerator. As shown in Fig. 10(a), when VT H1 and VT H2 are

Fig. 8Chip micrograph of UWB receiver in 1.2 V 65 nm CMOS process.

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Table 1

Performance summary of fabricated receiver.

Fig. 9 Measured threshold (=oﬀset) voltage dependence on 4-bit digital
control of proposed variable threshold comparator.

Fig. 11 Energy and power comparison with state-of-the-art
correlation-based UWB receivers.

in this work.
The chip performance is summarized in Table 1.
The power consumption without amplifier is 0.96 mW at
100 Mbps. In the correlation-based UWB receiver, noise
figure (NF) can be traded-oﬀ for power consumption in thefront-end gain circuits without degrading performance [13].
The simulated power consumption of the front-end amplifier
is 0.8 mW and the estimated total power consumption of thereceiver is 1.76 mW, which corresponds to 17.6 pJ/bit. Figure 11 shows energy and power comparison with state-ofthe-art correlation-based UWB receivers. The proposed receiver with multiple sampling correlators eliminating phasesynchronization achieves the lowest energy consumption of
17.6 pJ/bit at 100 Mbps in the correlation-based UWB receivers.
Fig. 10 Measured output of the receiver with diﬀerent comparator
thresholds (VT H1 and VT H2 ). (a) Incorrect operation with inappropriate
VT H1 and VT H2 . (b). Correct operation with appropriate VT H1 and VT H2 .

too small, the output of the receiver is not correct, because
the auxiliary pulse of the correlation result is also detected
and the receiver output is corrupted by the auxiliary pulse.
In contrast, as shown in Fig. 10(b), when VT H1 and VT H2
are increased, the receiver returns to correct operation. The
VT H1 and VT H2 adaptive tuning circuit was not implemented

5.

Conclusions

A 1.2 V 100 Mbps IR-UWB receiver in 65 nm CMOS for
DC-960 MHz band is developed. The proposed receiverfeatures multiple DC power-free charge-domain samplingcorrelators to eliminate the need for phase synchronization,
thereby achieving the lowest energy of 17.6 pJ/bit in stateof-the-art correlation-based UWB receivers.

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Acknowledgments
This work is partially supported by CREST/JST. The fabrication of VLSI chips is supported by VLSI Design and
Education Center (VDEC), the University of Tokyo in collaboration with STARC, e-Shuttle, and Fujitsu.
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Lechang Liu
received the B.S. degreefrom Shandong University, China in 2000, theM.S. degree from Harbin Institute of Technology, China in 2002, and the Ph.D. degree
in electronic engineering from Shanghai Jiao
Tong University, China in 2006. From 2007
to 2009, he was with VLSI Design and Education Center, The University of Tokyo, Japan,
where he conducted research on low-power andhigh-performance impulse radio ultra-wideband(UWB) transceivers. Since 2009, he has been a
project researcher with the Institute of Industrial Science, The Universityof Tokyo, Japan. His current research interests include signal processing
and mixed-signal circuit design for low-power wireless communications.

Zhiwei Zhou
received the M.S. degrees
in electronic engineering from the University ofTokyo, Japan in 2008. His research interests include the circuit design of the low-power RF receiver circuits. He is now with Sony Corporation.

Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at
the University of California Berkeley, where heconducted research in the field of VLSI CAD.
From 1996, he has been a professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC’s and large-area electronics. He has publishedmore than 400 technical publications including 100 invited presentations
and several books and filed more than 200 patents. He served as a conference chair for the Symp. on VLSI Circuits, and ICICDT, a vice chair
for ASPDAC, a TPC chair for the first A-SSCC, and VLSI symp. and a
program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC,
ICCAD, ISLPED, and other international conferences. He will be an executive committee chair for VLSI Symposia and a steering committee chair
for A-SSCC from 2010. He is a recepient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, 2009 achievement award of IEICE,
2005 IEEE ICICDT award, 2004 IEEE Takuo Sugano award and 2005 P&I
patent of the year award and four product awards. He gave keynote speech
at more than 50 conferences including ISSCC, ESSCIRC and ISLPED. He
was an elected AdCom member for the IEEE Solid-State Circuits Society
and an IEEE CAS and SSCS distinguished lecturer. He is a STARC Fellow
and an IEEE Fellow.

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Makoto Takamiya
received the B.S., M.S.,
and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995,
1997, and 2000, respectively. In 2000, he joined
NEC Corporation, Japan, where he was engaged
in the circuit design of high speed digital LSIs.
In 2005, he joined University of Tokyo, Japan,
where he is an associate professor of VLSI Design and Education Center. His research interests include the circuit design of the low-power
RF circuits, the ultra low-voltage digital circuits,
and the large area electronics with organic transistors. He is a member of
the technical program committee for IEEE Symposium on VLSI Circuits
and IEEE Custom Integrated Circuits Conference (CICC).