Increase of Crosstalk Noise Due to Imbalanced
Threshold Voltage between NMOS and PMOS in
Sub-Threshold Logic Circuits
Hiroshi Fuketa1, Ryo Takahashi1, Makoto Takamiya1, Masahiro Nomura2, Hirofumi Shinohara2, Takayasu Sakurai1
1
University of Tokyo, Japan
2
Semiconductor Technology Academic Research Center (STARC), Japan
Abstract- Abnormal increase of the crosstalk noise in the subthreshold logic circuits is found for the first time. When thethreshold voltages (VTH) of nMOS and pMOS are imbalanced
and the on-resistance of the aggressor driver is much lower thanthat of the victim driver, the large crosstalk noise is observed,
because the on-resistance has an exponential dependence on VTH
in the sub-threshold circuits. In this paper, the large crosstalknoise due to the imbalanced VTH is measured. A new crosstalknoise model is also proposed and verified with SPICE simulations.
In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS
at the power supply voltage (VDD) of 0.3V, the measured noise
amplitude increases from 32% of VDD to 71% of VDD, when theimbalanced VTH is realized by tuning a body bias in pMOS. In
the worst case fast-nMOS/slow-pMOS corner simulations, thenoise amplitude increases from 47% of VDD to 68% of VDD, when
VDD is reduced from 1.1V to 0.3V, which is explained by the
proposed model.

I. INTRODUCTION
Sub-threshold circuits, which operate at a lower supply
voltage (VDD) than threshold voltage (VTH), are one ofpromising solutions to achieve ultra-low power operation [1].
Delay of sub-threshold circuits, however, has large variations
due to VTH variation, since the transistor current in the subthreshold region has an exponential dependence on VTH.
Therefore, many researchers have focused on investigating
circuit techniques to cope with such large delay variation [2,3].
In contrast, there are few reports on a crosstalk noise in subthreshold circuits [4], though a lot of paper is published on the
crosstalk noise in above-threshold circuits [5-7]. In theseprevious works, the dependence of the crosstalk noise on VDD
is not clear. If the crosstalk noise in sub-threshold circuits islarger than that of the crosstalk noise in above-thresholdcircuits, a new sign-off condition for the crosstalk checkshould be developed. Therefore, in this paper, the crosstalknoise in sub-threshold circuits is measured in a 40-nm CMOS
test chip. In addition, a new crosstalk noise model is proposedand verified with SPICE simulations. An abnormal increase of
the crosstalk noise in the sub-threshold operation is found forthe first time.
This paper is organized as follows. Section II describes
silicon measurements of the crosstalk noise and shows its
dependence on the balance of VTH. In order to investigate thedependence, a new crosstalk noise model for sub-thresholdcircuits is proposed in Section III. Finally, Section IV
concludes this paper.

978-1-4673-1556-2/12/$31.00@2012 IEEE

VDD(NTC)(= 0.3 ~ 1.1V)

Drivers

Noise test circuit (NTC)(VDD(NPD)-VSS(NPD)=1.1V)

Aggressor

VIN

VictimAggressor

VDD(NPD)VNOISE

Noise peakdetector (NPD)

1.5 mmDOUT

VSS(NPD)

Body-bias can be controlled.

(a) Circuit diagram of crosstalk noise measurement circuit.
Schmitt trigger buffer
VOUT

VDD(NPD)VNOISEVDD(NPD)VDETECT

VSS(NPD)

0VNOISE

VOUT

DOUT

Reset
VSS(NPD)(b) Schematic of noise peak detector (NPD) for falling noise.
VDD(NTC)

VIN

0
Time

VDD(NPD)VDD(NTC)

1.1V

VNOISEVDETECT

VPEAK
Sweep VDD(NPD) and VSS(NPD)
until DOUT goes high

VSS(NPD)Time

VDD(NPD)VSS(NPD)

VOUT

1.1V

DOUT
Time

(c) Timing chart of peak noise detection.
Fig. 1. Measurement circuit and mechanism to detect peak voltage offalling crosstalk noise. Rising noise can be also measured by the similar
mechanism.

II. MEASUREMENT OF CROSSTALK NOISE
A. Test Chip Design
In order to measure the dependence of the crosstalk noise
on VDD and VTH’s of nMOS and pMOS, a crosstalk noise test
chip is designed and fabricated in a 40-nm CMOS. Fig. 1(a)shows a circuit diagram to measure the peak noise voltage

1560μm

0.5

80μm
Drivers

Noise peak detector(10μm x 10μm)

1.5mm coupled wire line
(1 victim and 2 aggressor lines)

Fig. 2. Chip micrograph in 40-nm CMOS.

induced by crosstalk. The measurement circuit consists ofnoise test circuit (NTC), which includes 1.5mm coupled wirelines, and noise peak detector (NPD). The long (1.5mm) wireis used in the measurement, because the resistance of the wireis much smaller than that of the driver in the sub-thresholdregion and hence a lot of repeaters are not required. The
crosstalk noise is measured over a wide range of the supply
voltage of the NTC (VDD(NTC)). In addition, body-bias voltageof the wire line drivers can be controlled in order toinvestigate the dependence of the balance of VTH between
nMOS and pMOS on the crosstalk noise.
Fig. 1(b) shows a schematic of the NPD, which detects thepeak voltage of crosstalk noise induced by the fallingtransition on the aggressor lines. The Schmitt trigger buffer
converts a noise that exceeds the logical threshold voltage ofthe buffer (VDETECT) to a pulse, and then the pulse is capturedby the RS latch. The Schmitt trigger buffer is used to make thepulse wider. The voltage difference between the supply
voltage (VDD(NPD)) and the ground (VSS(NPD)) of the NPD is
fixed to 1.1V regardless of VDD(NTC). VDETECT is varied bychanging both VDD(NPD) and VSS(NPD). As shown in Fig. 1(c),the falling noise peak voltage (VPEAK) is measured by thefollowing procedure:
1.
2.
3.

VDD(NPD) and VSS(NPD) are set to low voltages.
A falling transition signal is given to the aggressor lines,
while the victim line is kept high.
If the output of the latch (DOUT) goes high, VDD(NTC)VDETECT is the peak noise voltage (VPEAK). On the other
hand, if DOUT remains low, VDD(NPD) and VSS(NPD) are
increased to raise VDETECT. Then, steps 2 and 3 arerepeated until the noise is detected.

In order to measure VPEAK, the calibration of VDETECT is
required, because VDETECT has die-to-die variations. During thecalibration, the crosstalk noise is not generated and VPEAK =0V. Therefore, the exact value of VDETECT is measured bysweeping both VDD(NPD) and VSS(NPD), because VDETECT is equal
to VDD(NTC) at the rising edge of DOUT.
The noises occurring in the sub-threshold region are slow,
and hence they can be easily measured with the noise peakdetector. However, it is difficult for the noise peak detector toaccurately measure the peak voltages of fast and sharp noises
which often occur at around nominal supply voltage region.
The relative error is estimated to be 10% at more than 0.8V.
It should be noted that the rising crosstalk noise can bemeasured by the similar mechanism (NOR RS latch is usedinstead of NAND RS latch in Fig. 1(b)). We also implemented

VPEAK / VDD(NTC)

0.4
0.3
0.2
0.1
0
0

: Measurement: Simulation
0.2

0.4

0.6

0.8

1.0

1.2

Supply voltage VDD(NTC) (V)
Fig. 3. Measured and simulated peak voltage (VPEAK) of the falling crosstalk noise as a function of the supply voltage of the NTC (VDD(NTC)).

the measurement circuit for the rising crosstalk noise andverified its functionality on silicon.
The chip micrograph is shown in Fig. 2. The measurement
circuit was fabricated in a 40-nm CMOS process with 7 metal
layers. M6 is used for the 1.5mm coupled wire lines.
B. Measurement Results
Fig. 3 shows the measured and simulated peak voltage ofthe falling crosstalk noise as a function of the supply voltage.
The SPICE simulations are conducted with the parasitic wire
resistance and capacitance extracted from the layout data. VTH
used in the simulations is based on the measured single
transistors provided by the foundry. The simulation results
agree with the measurement results. Fig. 3 shows that
VPEAK/VDD(NTC) decreases as VDD(NTC) is reduced. The detailsof this dependence will be discussed in Section III.
In order to examine how the balance of VTH between
nMOS and pMOS affects the peak noise voltage, thedependence of the peak noise voltage on the body-bias voltageof the victim driver is measured. The measurement results areillustrated in Fig. 4. The peak noise voltage at the nominal
supply voltage of 1.1V does not depend on the n-well bodybias voltage of the victim driver, whereas the reverse bodybias voltage significantly increases the peak noise voltage at
VDD(NTC) of 0.3V. The noise amplitude increases from 32% of
VDD to 71% of VDD, when the imbalanced VTH is realized bytuning a body bias in pMOS. This indicates that the peak noisevoltage is extremely sensitive to the balance of VTH between
nMOS and pMOS in sub-threshold circuits. The reason why
the balance of VTH significantly affects the peak noise voltage
is discussed in the next section.
III. MODELING OF CROSSTALK NOISE IN SUB-THRESHOLDREGIONAt first, the crosstalk noise by one aggressor line isinvestigated. Fig. 5 illustrates the equivalent circuit of thecoupled wire lines with one aggressor and one victim for thefalling noise. In this paper, R5N (R5P) and R3N (R3P) areequivalent resistances of nMOS (pMOS), and the definition

VDD(NTC)

VictimVPEAK / VDD(NTC)

0.8

0.6

Fig. 3

0.4

VDD(NTC)
z

1.1V

0.3V

Measurement
Simulation

0.2

0Drain-source current IDS (a.u.)

VNW -VDD(NTC)

0.25

0.75

1.0

1.25

Agressor-1

Body-bias voltage of n-well VNW-VDD(NTC) (V)

RW,0
CW,1 CW,2
CC,0 CC,1

Cc,2

VictimR3P CW,0RW,0CW,1 CW,2RW,1Subthreshold voltage region (This work)
Aggressor

R5N

VDD
0

R5N, R3P >> RW
CWÆ Wire resistance (Rw) can be ignored.

CC

VDD
VictimR3P CW

RW = RW,0 + RW,1 + RW,2 + …
CW = CW,0 + CW,1 + CW,2 + …
CC = CC,0 + CC,1 + CC,2 + …

Fig. 5. Equivalent circuit of the coupled wire lines with one aggressor and
one victim.

for nMOS is explained in Fig. 6. R5N and R5P are pentode
resistance (on-resistance) and are given by,

R5 N ( P ) =VDS,I DS , N ( P ) @ (VDS = VGS = VDD )(1)where IDS,N(P) is a drain-source current of nMOS (pMOS),
which is a function of the drain voltage (VDS) and the gate
voltage (VGS).
R3N and R3P are triode resistance and are defined as,

R3 N ( P ) =

1/R5N
1/R3N

2
1

VDS=VDD/4
0

0.1

0

VGS=VDD=0.3V
0.3

0.2

VDS
.
I DS , N ( P ) @ (VGS = VDD , VDS = VDD 4 )

R5N

R5N/2

Aggressor
VDD
0

2CWA

CC

2CC

VDD

R3P

R3P

VictimVictim

R5N

CWV

CWV

CC

CWA

Fig. 7. Equivalent circuit of the coupled wire lines with two aggressors
and one victim. This circuit can be converted to circuit with one
aggressor.

RW,1

CW,0

VDD

3

VDD

VDD
0

Wire resistance (Rw) must be considered.

VDD
0

4

CWA

Agressor-2

Nominal supply voltage region (Conventional)
R5N

IDS

VDD
0

Fig. 4. Measured and simulated dependence of the peak noise voltage(VPEAK) on the n-well body-bias voltage of the victim driver. The noise
peak voltage is significantly sensitive to the balance of VTH in subthreshold circuits.

Aggressor

R5N @ VDS=VDD
R3N @ VDS=VDD/4

5

Fig. 6. Definition of equivalent resistance of nMOS.

Imbalanced
0.5

VDD VDS

Drain-source voltage VDS (V)Balanced06(2)

In this paper, a critical peak noise voltage is assumed to half
VDD. Therefore, the resistance at VDS=VDD/4, which is anintermediate voltage between half VDD and the ground, is used.
In the nominal supply voltage region, the equivalent
resistances of the wire line drivers (R5N and R3P) are so smallthat the wire resistance (RW) must be taken into consideration
as shown in the upper figure of Fig. 5. On the other hand, RW
can be ignored in the sub-threshold region, since R5N and R3P
are much larger than RW. Therefore, the equivalent circuit in
the sub-threshold region can be easily analyzed as illustrated
in the lower figure of Fig. 5.
For the circuit of the wire lines with two aggressors asshown in Fig. 1(a), the equivalent circuit in the sub-thresholdregion is depicted in Fig. 7. When the wire capacitances of thevictim (CWV) and aggressors (CWA) are identical(CW=CWV=CWA), the peak noise on the victim line voltage(VPEAK) is derived using the wire capacitance (CW) and thecoupling capacitance between the aggressor and the victim(CC) as follows,αβ⎛⎞
2 rf c1 ⎜ ⎛ α ⎞α − β ⎛ α ⎞ α − β ⎟ (3)
VPEAK = VDD
−⎜ ⎟
,
⎜ ⎟
⎟⎟
rf ( 3c + 1) α − β ⎜⎜ ⎝ β ⎠⎝β ⎠⎝⎠where c=CC/CW and rf=R3P/R5N. Here, rf is the equivalent
resistance ratio for the falling noise. For the rising noise,
rr=R3N/R5P is used instead of rf. α and β are solutions of thefollowing quadratic equation,(4)
rf ( 3c + 1) x 2 + 2rf c + rf + c + 1 x + 1 = 0.

()

Equation (3) is too complicated to discuss the VPEAK
dependence on VTH, and hence the following simple
approximation model of VPEAK is introduced in this paper.
1.3

⎛ rf
c ⎞
VPEAK , approx = VDD ⎜⋅.
⎜ rf + 0.5 c + 0.5 ⎟⎟
⎝
⎠

(5)

VPEAK / VDD, VPEAK,approx / VDD

0.8

FS
0.6

x1.4

TT

0.4
VPEAK

(Simulation)

0.2

VPEAK,approxSF00(Equation (5))

0.2

0.4

0.6

0.8

1.0

1.2

Supply voltage VDD (V)Fig. 8. Peak voltage of falling noise on 1.5mm coupled wire line with two
aggressors and one victim at TT, FS, and SF process corners. VPEAK is
obtained by SPICE simulations and VPEAK,approx is calculated by the
proposed approximation model equation (5).

The relative error (|VPEAK-VPEAK,approx||/VDD) is less than 3.9%in the case of 0.5<rf<10 and 0.5<c<5.
If the wire capacitances of the victim and aggressors aredifferent, a slight modification of (5) is required. For example,
when the wire capacitance of the aggressor is two times larger
than that of the victim (CWA=2CWV), VPEAK can beapproximated by using 1.5th power instead of 1.3th power in(5). In this case, the relative error is less than 4.9% at thecondition of 0.5<rf<10 and 0.5<c<5.
In the sub-threshold region, IDS,N in (1) and (2) is given by[8],
VGS −VTH , N +ηVDS

I DS , N = I 0, N enU TV− DS ⎞⎛⎜ 1 − e UT ⎟ ,
⎜
⎟
⎝
⎠

(6)

where n is the sub-threshold slope parameter, η is the DIBL
coefficient, UT is the thermal voltage, VTH,N is VTH of nMOS,
and I0,N is the technology dependent parameter.
From (1), (2), and (6), rf can be expressed as,

rf =

R3 P
∝e
R5 N

VTH ,P −VTH , N
nU T

,

(7)

where VTH,P is VTH of pMOS. This equation indicates that rf
has an exponential dependence on the VTH difference between
nMOS and pMOS. According to (5), the peak noise voltage
depends on rf. Thus, the peak noise voltage is strongly affectedby the balance of VTH between nMOS and pMOS, whichmeans that it is especially crucial at the process corners, suchas FS(fast-nMOS/slow-pMOS) and SF(slow-nMOS/fastpMOS).
Fig. 8 shows the simulated peak noise voltage (fallingnoise) on the coupled wire line with one victim and two
aggressors at the typical process condition (TT) and the cornerconditions (SF and FS). The approximated peak noise(VPEAK,approx) calculated by (5) is also shown, and it agrees
with the simulated results. The measured VPEAK dependence
shown in Fig. 3 is different from the simulated one shown in

Fig. 8 because the VTH balance of the measured chip is
between TT and SF.
In the worst case FS corner simulations, VPEAK/VDD at
0.3V is 1.4 times larger than that at 1.1V. The reason why thecrosstalk noise at the nominal supply voltage region does notdepend on the balance of VTH is 1) the dependence of theequivalent resistances of the drivers on VTH is much smaller
than that in the sub-threshold region, and 2) the influence of
the wire resistances is not ignored. In contrast, the peak noisevoltage in the sub-threshold region is much more sensitive tothe balance of VTH. This is because the peak noise voltage
depends on the equivalent resistance ratio (rf and rr), which has
an exponential dependence on the VTH difference between
nMOS and pMOS as indicated in (7). Therefore designers
must take the process corner condition, such as SF and FS,
into consideration as the worst-case condition for signal
integrity in sub-threshold circuits.
IV. CONCLUSION
In this paper, the dependence of the peak noise voltage
induced by crosstalk on the VTH difference between nMOS
and pMOS in sub-threshold circuits was presented. The large
crosstalk noise due to the imbalanced VTH was measured in thetest chip with 1.5-mm coupled wires fabricated in a 40-nm
CMOS process. A new crosstalk noise model was proposedand verified with SPICE simulations. In the worst case FS
corner simulations, the noise amplitude increased by 1.4 times
when VDD was reduced from 1.1V to 0.3V, which was
explained by the proposed model.
ACKNOWLEDGMENTS
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial
Technology Development Organization (NEDO).
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