ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU
with Integrated Power Management Hardware
Reference

Revision 1.1, November 2018
Part Number
82-100132-01

Analog Devices, Inc.
One Technology Way
Norwood, MA 02062-9106

Notices
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Printed in the USA.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceiiContents
Introduction
ADuCM4050 MCU Features ........................................................................................................................ 1–1
ADuCM4050 Functional Description ........................................................................................................... 1–2
ADuCM4050 Block Diagram..................................................................................................................... 1–2
Memory Architecture.................................................................................................................................. 1–3
SRAM Region ............................................................................................................................................ 1–3
System Region ............................................................................................................................................ 1–4
Flash Controller.......................................................................................................................................... 1–5
Cache Controller ........................................................................................................................................ 1–5
ARM Cortex-M4F Memory Subsystem ...................................................................................................... 1–5
Booting ...................................................................................................................................................... 1–5
Security Features......................................................................................................................................... 1–6
Safety Features............................................................................................................................................ 1–6
Multi Parity Bit Protected SRAM............................................................................................................... 1–6
Programmable GPIOs ................................................................................................................................ 1–6
Timers ........................................................................................................................................................ 1–6
Power Management .................................................................................................................................... 1–7
Clocking ..................................................................................................................................................... 1–8
Real-Time Clock (RTC) ............................................................................................................................. 1–8
System Debug .......................................................................................................................................... 1–10
Beeper Driver ........................................................................................................................................... 1–10
Cryptographic Accelerator (Crypto) ......................................................................................................... 1–10
CRC Accelerator....................................................................................................................................... 1–11
True Random Number Generator (TRNG).............................................................................................. 1–11
Serial Ports (SPORTs) .............................................................................................................................. 1–11
Serial Peripheral Interface (SPI) Ports....................................................................................................... 1–12
UART Ports.............................................................................................................................................. 1–12
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Referenceiii

Inter-Integrated Circuit (I2C) ................................................................................................................... 1–12
Analog-to-Digital Converter (ADC) Subsystem........................................................................................ 1–12
Reference Designs..................................................................................................................................... 1–13
Development Tools................................................................................................................................... 1–13
ADuCM4050 Peripheral Memory Map ....................................................................................................... 1–13

Debug (DBG) and Trace Interfaces
Debug and Trace Features.............................................................................................................................. 2–1
DBG Functional Description......................................................................................................................... 2–1
Serial Wire Interface ................................................................................................................................... 2–1
DBG Operating Modes ................................................................................................................................. 2–2
Serial Wire Protocol.................................................................................................................................... 2–2
Debug Access Port (DAP).............................................................................................................................. 2–4
Debug Port .................................................................................................................................................... 2–5
ADuCM4050 SYS Register Descriptions ...................................................................................................... 2–5
ADI Identification ..................................................................................................................................... 2–6
Chip Identifier ........................................................................................................................................... 2–7
Serial Wire Debug Enable .......................................................................................................................... 2–8

Events (Interrupts and Exceptions)
Events Features .............................................................................................................................................. 3–1
Events Interrupts and Exceptions................................................................................................................... 3–1
Cortex Exceptions....................................................................................................................................... 3–1
Nested Vectored Interrupt Controller ......................................................................................................... 3–2
Handling Interrupt Registers...................................................................................................................... 3–4
External Interrupt Configuration................................................................................................................ 3–5
ADuCM4050 XINT Register Descriptions .................................................................................................. 3–5
External Interrupt Configuration ............................................................................................................... 3–7
External Interrupt Clear .......................................................................................................................... 3–10
External Wakeup Interrupt Status ............................................................................................................ 3–11
Non-maskable Interrupt Clear ................................................................................................................. 3–13
iv

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencePower Management (PMG)
Power Management Features ......................................................................................................................... 4–1
Power Management Functional Description .................................................................................................. 4–1
Power-up Sequence..................................................................................................................................... 4–1
Operating Modes ........................................................................................................................................... 4–2
Active Mode ............................................................................................................................................... 4–2
Flexi Mode.................................................................................................................................................. 4–3
Hibernate Mode ......................................................................................................................................... 4–4
Shutdown Mode ......................................................................................................................................... 4–5
Programming Sequence ................................................................................................................................. 4–6
Configuring Hibernate Mode ..................................................................................................................... 4–6
Configuring Shutdown Mode..................................................................................................................... 4–7
Wake-up Sequence ......................................................................................................................................... 4–7
Fast Wake-up from Shutdown Mode.............................................................................................................. 4–8
Monitor Voltage Control ............................................................................................................................... 4–8
Retention Register Details ........................................................................................................................... 4–10
ADuCM4050 PMG Register Descriptions ................................................................................................. 4–11
HPBUCK Control ................................................................................................................................... 4–13
Power Supply Monitor Interrupt Enable .................................................................................................. 4–14
Trimming Bits ......................................................................................................................................... 4–16
Power Supply Monitor Status .................................................................................................................. 4–17
Key Protection for PMG_PWRMOD and PMG_SRAMRET ................................................................ 4–20
Power Mode Register ............................................................................................................................... 4–21
Reset Status ............................................................................................................................................. 4–22
Shutdown Status Register ........................................................................................................................ 4–24
Control for Retention SRAM in Hibernate Mode ................................................................................... 4–25
ADuCM4050 PMG_TST Register Descriptions ........................................................................................ 4–25
Clear GPIO After Shutdown Mode ......................................................................................................... 4–27
Fast Shutdown Wake-up Enable .............................................................................................................. 4–28
Scratch Pad Saved in Battery Domain ...................................................................................................... 4–29
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencevScratch Pad Image ................................................................................................................................... 4–30
Control for SRAM Parity and Instruction SRAM .................................................................................... 4–31
Initialization Status Register .................................................................................................................... 4–33

General-Purpose I/O (GPIO)
GPIO Features............................................................................................................................................... 5–1
GPIO Functional Description........................................................................................................................ 5–1
GPIO Block Diagram................................................................................................................................. 5–1
ADuCM4050 GPIO Multiplexing ............................................................................................................. 5–3
GPIO Operating Modes ................................................................................................................................ 5–5
IO Pull-Up or Pull-Down Enable ............................................................................................................... 5–5
IO Data In ................................................................................................................................................. 5–5
IO Data Out............................................................................................................................................... 5–5
Bit Set......................................................................................................................................................... 5–5
Bit Clear ..................................................................................................................................................... 5–5
Bit Toggle ................................................................................................................................................... 5–5
IO Data Output Enable.............................................................................................................................. 5–5
Interrupts ................................................................................................................................................... 5–5
Interrupt Polarity........................................................................................................................................ 5–6
Interrupt A Enable...................................................................................................................................... 5–6
Interrupt B Enable...................................................................................................................................... 5–6
Interrupt Status .......................................................................................................................................... 5–6
GPIO Programming Model ........................................................................................................................... 5–7
ADuCM4050 GPIO Register Descriptions .................................................................................................. 5–7
Port Configuration .................................................................................................................................... 5–8
Port Data Out Clear ................................................................................................................................ 5–10
Port Drive Strength Select ....................................................................................................................... 5–11
Port Input Path Enable ............................................................................................................................ 5–14
Port Interrupt A Enable ........................................................................................................................... 5–15
Port Interrupt B Enable ........................................................................................................................... 5–16

vi

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencePort Registered Data Input ...................................................................................................................... 5–17
Port Interrupt Status ................................................................................................................................ 5–18
Port Output Enable ................................................................................................................................. 5–19
Port Data Output .................................................................................................................................... 5–20
Port Output Pull-up/Pull-down Enable ................................................................................................... 5–21
Port Interrupt Polarity ............................................................................................................................. 5–22
Port Data Out Set .................................................................................................................................... 5–23
Port Pin Toggle ........................................................................................................................................ 5–24

System Clocks
System Clock Features ................................................................................................................................... 6–1
System Clock Functional Description ............................................................................................................ 6–2
System Clock Block Diagram ..................................................................................................................... 6–2
Clock Muxes ........................................................................................................................................... 6–3
Clock Dividers ........................................................................................................................................ 6–4
Clock Gating........................................................................................................................................... 6–5
PLL Settings .................................................................................................................................................. 6–5
PLL Interrupts............................................................................................................................................ 6–6
PLL Programming Sequence ...................................................................................................................... 6–7
Crystal Programming..................................................................................................................................... 6–7
Oscillator Programming ................................................................................................................................ 6–8
Switching System Clock to Greater than 26 MHz ......................................................................................... 6–8
Oscillators...................................................................................................................................................... 6–9
System Clock Interrupts and Exceptions...................................................................................................... 6–13
Setting the System Clocks............................................................................................................................ 6–13
Set System Clock to PLL Input Source ..................................................................................................... 6–13
Set System Clock to XTAL ....................................................................................................................... 6–16
Changing System Clock Source ................................................................................................................ 6–18
ADuCM4050 CLKG_OSC Register Descriptions ...................................................................................... 6–19
Oscillator Control ................................................................................................................................... 6–20
Key Protection for OSCCTRL ................................................................................................................ 6–25
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Referencevii

ADuCM4050 CLKG_CLK Register Descriptions ...................................................................................... 6–25
Misc Clock Settings ................................................................................................................................. 6–26
Clock Dividers ......................................................................................................................................... 6–29
HF Oscillator Divided Clock Select ......................................................................................................... 6–31
System PLL ............................................................................................................................................. 6–33
User Clock Gating Control ...................................................................................................................... 6–35
Clocking Status ....................................................................................................................................... 6–38

Reset (RST)ADuCM4050 Reset Register Description ...................................................................................................... 7–2
Reset Status ............................................................................................................................................... 7–3

Flash Controller (FLASH)
Flash Features ................................................................................................................................................ 8–1
Supported Commands................................................................................................................................ 8–1
Protection and Integrity Features................................................................................................................ 8–2
Flash Functional Description ......................................................................................................................... 8–2
Organization .............................................................................................................................................. 8–2
Flash Access ................................................................................................................................................ 8–5
Reading Flash .......................................................................................................................................... 8–7
Erasing Flash ........................................................................................................................................... 8–7
Writing Flash........................................................................................................................................... 8–8
Protection and Integrity............................................................................................................................ 8–12
Integrity of Info Space........................................................................................................................... 8–12
User Space Protection............................................................................................................................ 8–12
Runtime Configuration ......................................................................................................................... 8–13
Meta Data Configuration ...................................................................................................................... 8–14
Signatures.............................................................................................................................................. 8–15
Key Register .......................................................................................................................................... 8–16
ECC ...................................................................................................................................................... 8–16
Clock and Timings................................................................................................................................ 8–17
Flash Operating Modes................................................................................................................................ 8–18
viii

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceClock Gating ............................................................................................................................................... 8–19
Flash Interrupts and Exceptions................................................................................................................... 8–19
Flash Programming Model........................................................................................................................... 8–19
Programming Guidelines.......................................................................................................................... 8–19
ADuCM4050 FLCC Register Descriptions ................................................................................................ 8–19
IRQ Abort Enable (Upper Bits) ............................................................................................................... 8–21
IRQ Abort Enable (Lower Bits) ............................................................................................................... 8–22
Flash Security .......................................................................................................................................... 8–23
Volatile Flash Configuration .................................................................................................................... 8–24
Command ............................................................................................................................................... 8–25
ECC Status (Address) .............................................................................................................................. 8–29
Interrupt Enable ...................................................................................................................................... 8–30
Key .......................................................................................................................................................... 8–32
Write Address .......................................................................................................................................... 8–33
Write Lower Data .................................................................................................................................... 8–34
Write Upper Data .................................................................................................................................... 8–35
Lower Page Address ................................................................................................................................. 8–36
Upper Page Address ................................................................................................................................. 8–37
Signature ................................................................................................................................................. 8–38
Status ....................................................................................................................................................... 8–39
Time Parameter 0 .................................................................................................................................... 8–46
Time Parameter 1 .................................................................................................................................... 8–49
User Configuration .................................................................................................................................. 8–51
Write Protection ...................................................................................................................................... 8–53
Write Abort Address ................................................................................................................................ 8–55

Static Random Access Memory (SRAM)
SRAM Features .............................................................................................................................................. 9–1
SRAM Configuration .................................................................................................................................... 9–1
Instruction SRAM vs Data SRAM.............................................................................................................. 9–1

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceixSRAM Retention in Hibernate Mode ......................................................................................................... 9–2
SRAM Programming Model .......................................................................................................................... 9–2
SRAM Parity ................................................................................................................................................. 9–2
SRAM Initialization....................................................................................................................................... 9–3
Initialization in Cache ................................................................................................................................ 9–4
ADuCM4050 SRAM Register Description.................................................................................................... 9–4
Initialization Status Register ...................................................................................................................... 9–5
Control for SRAM Parity and Instruction SRAM ...................................................................................... 9–7
Control for Retention SRAM in Hibernate Mode ..................................................................................... 9–9

Cache
Cache Programming Model ......................................................................................................................... 10–1
Programming Guidelines.......................................................................................................................... 10–1
ADuCM4050 FLCC_CACHE Register Descriptions ................................................................................. 10–1
Cache Key Register .................................................................................................................................. 10–2
Cache Setup Register ............................................................................................................................... 10–3
Cache Status Register .............................................................................................................................. 10–4

Direct Memory Access (DMA)DMA Features ............................................................................................................................................. 11–1
DMA Functional Description ...................................................................................................................... 11–2
DMA Architectural Concepts ................................................................................................................... 11–3
DMA Operating Modes............................................................................................................................... 11–3
Channel Control Data Structure............................................................................................................... 11–3
Source Data End Pointer .......................................................................................................................... 11–5
Destination Data End Pointer .................................................................................................................. 11–5
Control Data Configuration ..................................................................................................................... 11–5
DMA Priority ........................................................................................................................................... 11–7
DMA Transfer Types ................................................................................................................................ 11–7
Invalid ................................................................................................................................................... 11–8
Basic...................................................................................................................................................... 11–8
x

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceAuto-Request......................................................................................................................................... 11–8
Ping-Pong ............................................................................................................................................. 11–9
Memory Scatter-Gather....................................................................................................................... 11–11
Peripheral Scatter-Gather .................................................................................................................... 11–13
DMA Interrupts and Exceptions............................................................................................................. 11–15
Error Management .............................................................................................................................. 11–15
Address Calculation............................................................................................................................. 11–15
Address Decrement.............................................................................................................................. 11–16
Endian Operation................................................................................................................................... 11–17
DMA Channel Enable/Disable ............................................................................................................... 11–18
DMA Master Enable .............................................................................................................................. 11–19
Power-down Considerations ................................................................................................................... 11–19
DMA Programming Model........................................................................................................................ 11–19
Programming Guidelines........................................................................................................................ 11–19
ADuCM4050 DMA Register Descriptions ............................................................................................... 11–20
DMA Channel Alternate Control Database Pointer .............................................................................. 11–21
DMA Channel Primary Alternate Clear ................................................................................................ 11–22
DMA Channel Primary Alternate Set .................................................................................................... 11–23
DMA Channel Bytes Swap Enable Clear ............................................................................................... 11–24
DMA Channel Bytes Swap Enable Set ................................................................................................... 11–25
DMA Configuration .............................................................................................................................. 11–26
DMA Channel Destination Address Decrement Enable Clear ............................................................... 11–27
DMA Channel Destination Address Decrement Enable Set ................................................................... 11–28
DMA Channel Enable Clear .................................................................................................................. 11–29
DMA Channel Enable Set ..................................................................................................................... 11–30
DMA per Channel Error Clear .............................................................................................................. 11–31
DMA Bus Error Clear ........................................................................................................................... 11–32
DMA per Channel Invalid Descriptor Clear .......................................................................................... 11–33
DMA Channel Primary Control Database Pointer ................................................................................ 11–34
DMA Channel Priority Clear ................................................................................................................ 11–35

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Referencexi

DMA Channel Priority Set .................................................................................................................... 11–36
DMA Controller Revision ID ................................................................................................................ 11–37
DMA Channel Request Mask Clear ...................................................................................................... 11–38
DMA Channel Request Mask Set .......................................................................................................... 11–39
DMA Channel Source Address Decrement Enable Clear ....................................................................... 11–40
DMA Channel Source Address Decrement Enable Set ........................................................................... 11–41
DMA Status .......................................................................................................................................... 11–42
DMA Channel Software Request ........................................................................................................... 11–43

Cryptography (CRYPTO)
Crypto Features ........................................................................................................................................... 12–2
Crypto Functional Description .................................................................................................................... 12–2
Crypto Block Diagram ............................................................................................................................. 12–3
Crypto Operating Modes............................................................................................................................. 12–3
Crypto Data Transfer................................................................................................................................... 12–4
Crypto Data Rate ..................................................................................................................................... 12–4
Data Pipeline............................................................................................................................................ 12–5
DMA Capability....................................................................................................................................... 12–5
Core Transfer............................................................................................................................................ 12–5
Data Formatting .......................................................................................................................................... 12–5
Interrupts..................................................................................................................................................... 12–7
Crypto Error Conditions ............................................................................................................................. 12–8
Crypto Status Bits........................................................................................................................................ 12–8
Crypto Keys............................................................................................................................................... 12–10
Key Length ............................................................................................................................................. 12–10
Key Programming .................................................................................................................................. 12–10
Key Wrap-Unwrap Register .................................................................................................................... 12–11
Key Register Attributes........................................................................................................................... 12–11
Crypto Power Saver Mode ......................................................................................................................... 12–11
Registers with Mode Specific Roles............................................................................................................ 12–11

xii

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProtected Key Storage (PrKStor)................................................................................................................ 12–13
Operation ............................................................................................................................................... 12–14
Protected Key Storage Configuration...................................................................................................... 12–15
Command Fail Status ............................................................................................................................. 12–18
HMAC ...................................................................................................................................................... 12–19
HMAC Algorithm .................................................................................................................................. 12–19
Programming Model .............................................................................................................................. 12–20
CCM/CCM* Mode ................................................................................................................................... 12–21
Programming Flow for Block Modes of operation ..................................................................................... 12–23
Payload and Authenticated Data Formatting .......................................................................................... 12–25
Programming Flow for SHA-Only Operation............................................................................................ 12–25
Retention in Hibernate Mode .................................................................................................................... 12–26
ADuCM4050 CRYPT Register Descriptions ............................................................................................ 12–26
AES Key Bits [31:0] ............................................................................................................................... 12–29
AES Key Bits [63:32] ............................................................................................................................. 12–30
AES Key Bits [95:64] ............................................................................................................................. 12–31
AES Key Bits [127:96] ........................................................................................................................... 12–32
AES Key Bits [159:128] ......................................................................................................................... 12–33
AES Key Bits [191:160] ......................................................................................................................... 12–34
AES Key Bits [223:192] ......................................................................................................................... 12–35
AES Key Bits [255:224] ......................................................................................................................... 12–36
NUM_VALID_BYTES ......................................................................................................................... 12–37
Configuration Register .......................................................................................................................... 12–38
Counter Initialization Vector ................................................................................................................. 12–41
Payload Data Length ............................................................................................................................. 12–42
Input Buffer .......................................................................................................................................... 12–43
Interrupt Enable Register ...................................................................................................................... 12–44
Key Wrap Unwrap Register 0 ................................................................................................................ 12–45
Key Wrap Unwrap Register 1 ................................................................................................................ 12–46
Key Wrap Unwrap Register 10 .............................................................................................................. 12–47
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencexiiiKey Wrap Unwrap Register 11 .............................................................................................................. 12–48
Key Wrap Unwrap Register 12 .............................................................................................................. 12–49
Key Wrap Unwrap Register 13 .............................................................................................................. 12–50
Key Wrap Unwrap Register 14 .............................................................................................................. 12–51
Key Wrap Unwrap Register 15 .............................................................................................................. 12–52
Key Wrap Unwrap Register 2 ................................................................................................................ 12–53
Key Wrap Unwrap Register 3 ................................................................................................................ 12–54
Key Wrap Unwrap Register 4 ................................................................................................................ 12–55
Key Wrap Unwrap Register 5 ................................................................................................................ 12–56
Key Wrap Unwrap Register 6 ................................................................................................................ 12–57
Key Wrap Unwrap Register 7 ................................................................................................................ 12–58
Key Wrap Unwrap Register 8 ................................................................................................................ 12–59
Key Wrap Unwrap Register 9 ................................................................................................................ 12–60
Key Wrap Unwrap Validation String [63:32] ......................................................................................... 12–61
Key Wrap Unwrap Validation String [31:0] ........................................................................................... 12–62
Nonce Bits [31:0] .................................................................................................................................. 12–63
Nonce Bits [63:32] ................................................................................................................................ 12–64
Nonce Bits [95:64] ................................................................................................................................ 12–65
Nonce Bits [127:96] .............................................................................................................................. 12–66
Output Buffer ........................................................................................................................................ 12–67
Authentication Data Length .................................................................................................................. 12–68
PRKSTOR Configuration ..................................................................................................................... 12–69
SHA Bits [31:0] ..................................................................................................................................... 12–70
SHA Bits [63:32] ................................................................................................................................... 12–71
SHA Bits [95:64] ................................................................................................................................... 12–72
SHA Bits [127:96] ................................................................................................................................. 12–73
SHA Bits [159:128] ............................................................................................................................... 12–74
SHA Bits [191:160] ............................................................................................................................... 12–75
SHA Bits [223:192] ............................................................................................................................... 12–76
SHA Bits [255:224] ............................................................................................................................... 12–77
xiv

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSHA Last Word and Valid Bits Information ........................................................................................... 12–78
Status Register ....................................................................................................................................... 12–79

True Random Number Generator (TRNG)
TRNG Features ........................................................................................................................................... 13–1
TRNG Functional Description .................................................................................................................... 13–1
TRNG Block Diagram ............................................................................................................................. 13–1
TRNG Oscillator Counter ....................................................................................................................... 13–2
TRNG Entropy and Surprisal................................................................................................................... 13–4
Oscillator Count Difference ..................................................................................................................... 13–5
ADuCM4050 RNG Register Descriptions .................................................................................................. 13–5
RNG Control Register ............................................................................................................................. 13–7
RNG Data Register ................................................................................................................................. 13–8
RNG Sample Length Register .................................................................................................................. 13–9
Oscillator Count .................................................................................................................................... 13–10
Oscillator Difference .............................................................................................................................. 13–11
RNG Status Register ............................................................................................................................. 13–12

Cyclic Redundancy Check (CRC)CRC Features............................................................................................................................................... 14–1
CRC Functional Description ....................................................................................................................... 14–1
CRC Block Diagram................................................................................................................................. 14–1
CRC Operating Modes ................................................................................................................................ 14–2
Polynomial ............................................................................................................................................... 14–3
Reset and Hibernate Modes...................................................................................................................... 14–5
Input Data Length....................................................................................................................................... 14–5
CRC Data Transfer ...................................................................................................................................... 14–6
CRC Interrupts and Exceptions ................................................................................................................... 14–6
CRC Programming Model........................................................................................................................... 14–6
Mirroring Options.................................................................................................................................... 14–8
ADuCM4050 CRC Register Descriptions .................................................................................................. 14–9
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

xv

CRC Control ......................................................................................................................................... 14–10
Input Data Bits ...................................................................................................................................... 14–12
Input Data Byte ..................................................................................................................................... 14–13
Input Data Word ................................................................................................................................... 14–14
Programmable CRC Polynomial ............................................................................................................ 14–15
CRC Result ........................................................................................................................................... 14–16

Serial Peripheral Interface (SPI)SPI Features................................................................................................................................................. 15–1
SPI Functional Description.......................................................................................................................... 15–2
SPI Block Diagram................................................................................................................................... 15–2
MISO (Master In, Slave Out) Pin............................................................................................................. 15–3
MOSI (Master Out, Slave In) Pin............................................................................................................. 15–3
SCLK (Serial Clock I/O) Pin .................................................................................................................... 15–3
Chip Select (CS I/O) Pin.......................................................................................................................... 15–3
SPI Operating Modes .................................................................................................................................. 15–4
Wired-OR Mode (WOM) ........................................................................................................................ 15–4
General Instructions.............................................................................................................................. 15–4
Power-down Mode ................................................................................................................................... 15–4
Interfacing with SPI Slaves ....................................................................................................................... 15–5
Flow Control ............................................................................................................................................ 15–6
Three-Pin Mode ....................................................................................................................................... 15–7
SPI Data Transfer ........................................................................................................................................ 15–8
Transmit Initiated Transfer....................................................................................................................... 15–8
Receive Initiated Transfer ......................................................................................................................... 15–9
Transfers in Slave Mode.......................................................................................................................... 15–10
SPI Data Underflow and Overflow......................................................................................................... 15–11
SPI Interrupts and Exceptions ................................................................................................................... 15–11
Transmit Interrupt.................................................................................................................................. 15–11
Receive Interrupt .................................................................................................................................... 15–12

xvi

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceUnderflow/Overflow Interrupts.............................................................................................................. 15–12
SPI Programming Model ........................................................................................................................... 15–13
SPI DMA ............................................................................................................................................... 15–13
ADuCM4050 SPI Register Descriptions ................................................................................................... 15–16
Transfer Byte Count .............................................................................................................................. 15–17
Chip Select Control for Multi-slave Connections .................................................................................. 15–18
Chip Select Override ............................................................................................................................. 15–19
SPI Configuration ................................................................................................................................. 15–20
SPI Baud Rate Selection ........................................................................................................................ 15–23
SPI DMA Enable ................................................................................................................................... 15–24
FIFO Status ........................................................................................................................................... 15–25
Flow Control ......................................................................................................................................... 15–26
SPI Interrupts Enable ............................................................................................................................ 15–28
Read Control ......................................................................................................................................... 15–31
Receive .................................................................................................................................................. 15–33
Status ..................................................................................................................................................... 15–34
Transmit ................................................................................................................................................ 15–37
Wait Timer for Flow Control ................................................................................................................. 15–38

Serial Port (SPORT)
SPORT Features .......................................................................................................................................... 16–1
Signal Description ....................................................................................................................................... 16–2
SPORT Functional Description................................................................................................................... 16–3
SPORT Block Diagram ............................................................................................................................ 16–3
SPORT Transfer....................................................................................................................................... 16–4
Multiplexer Logic ..................................................................................................................................... 16–5
Serial Clock .............................................................................................................................................. 16–7
Frame Sync ............................................................................................................................................... 16–8
Frame Sync Options .............................................................................................................................. 16–9
Sampling Edge........................................................................................................................................ 16–11

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencexviiPremature Frame Sync Error Detection .................................................................................................. 16–12
Serial Word Length................................................................................................................................. 16–13
Number of Transfers............................................................................................................................... 16–13
SPORT Operating Modes ......................................................................................................................... 16–14
Mode Selection ....................................................................................................................................... 16–14
SPORT Data Transfer ............................................................................................................................... 16–16
Single Word (Core) Transfers.................................................................................................................. 16–16
DMA Transfers....................................................................................................................................... 16–16
SPORT Data Buffers ................................................................................................................................. 16–17
Data Buffer Status .................................................................................................................................. 16–17
Data Buffer Packing ............................................................................................................................... 16–17
SPORT Interrupts and Exceptions............................................................................................................. 16–18
Error Detection ...................................................................................................................................... 16–18
System Transfer Interrupts ..................................................................................................................... 16–19
Transfer Finish Interrupt (TFI)............................................................................................................... 16–19
SPORT Programming Model .................................................................................................................... 16–19
SPORT Power Management...................................................................................................................... 16–20
ADuCM4050 SPORT Register Descriptions ............................................................................................ 16–20
Half SPORT 'A' Control Register ......................................................................................................... 16–22
Half SPORT 'B' Control Register ......................................................................................................... 16–27
Half SPORT 'A' Divisor Register .......................................................................................................... 16–31
Half SPORT 'B' Divisor Register .......................................................................................................... 16–32
Half SPORT A's Interrupt Enable Register ........................................................................................... 16–33
Half SPORT B's Interrupt Enable Register ........................................................................................... 16–35
Half SPORT A Number of Transfers Register ....................................................................................... 16–37
Half SPORT B Number of Transfers Register ....................................................................................... 16–38
Half SPORT 'A' Rx Buffer Register ....................................................................................................... 16–39
Half SPORT 'B' Rx Buffer Register ....................................................................................................... 16–40
Half SPORT 'A' Status register ............................................................................................................. 16–41
Half SPORT 'B' Status register ............................................................................................................. 16–43
xviii

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceHalf SPORT 'A' CNV width ................................................................................................................. 16–45
Half SPORT 'B' CNV width register .................................................................................................... 16–46
Half SPORT 'A' Tx Buffer Register ...................................................................................................... 16–47
Half SPORT 'B' Tx Buffer Register ...................................................................................................... 16–48

Universal Asynchronous Receiver/Transmitter (UART)
UART Features ............................................................................................................................................ 17–1
UART Functional Description ..................................................................................................................... 17–1
UART Block Diagram .............................................................................................................................. 17–2
UART Operations........................................................................................................................................ 17–2
Serial Communications ............................................................................................................................ 17–2
UART Operating Modes.............................................................................................................................. 17–5
IO Mode .................................................................................................................................................. 17–5
DMA Mode.............................................................................................................................................. 17–5
FIFO Mode (16550) .................................................................................................................................... 17–5
UART Interrupts ......................................................................................................................................... 17–5
Auto Baud Rate Detection (ABD)................................................................................................................ 17–6
RS485 Half-Duplex Mode ........................................................................................................................... 17–8
Receive Line Inversion ................................................................................................................................. 17–9
Clock Gating ............................................................................................................................................... 17–9
UART and Power-Down Modes .................................................................................................................. 17–9
ADuCM4050 UART Register Descriptions .............................................................................................. 17–10
Auto Baud Control ................................................................................................................................ 17–11
Auto Baud Status (High) ....................................................................................................................... 17–13
Auto Baud Status (Low) ......................................................................................................................... 17–14
UART Control Register ......................................................................................................................... 17–15
Baud Rate Divider ................................................................................................................................. 17–16
Fractional Baud Rate ............................................................................................................................. 17–17
FIFO Control ........................................................................................................................................ 17–18
Interrupt Enable .................................................................................................................................... 17–20

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencexixInterrupt ID .......................................................................................................................................... 17–21
Line Control .......................................................................................................................................... 17–22
Second Line Control .............................................................................................................................. 17–24
Line Status ............................................................................................................................................. 17–25
RX FIFO Byte Count ............................................................................................................................ 17–27
RS485 Half-duplex Control ................................................................................................................... 17–28
Receive Buffer Register .......................................................................................................................... 17–29
Scratch Buffer ........................................................................................................................................ 17–30
TX FIFO Byte Count ............................................................................................................................ 17–31
Transmit Holding Register .................................................................................................................... 17–32

Inter-Integrated Circuit (I2C) Interface
I2C Features ................................................................................................................................................ 18–1
I2C Functional Description ......................................................................................................................... 18–1
I2C Block Diagram .................................................................................................................................. 18–1
I2C Operating Modes.................................................................................................................................. 18–2
Master Transfer Initiation......................................................................................................................... 18–2
Slave Transfer Initiation............................................................................................................................ 18–2
Rx/Tx Data FIFOs ................................................................................................................................... 18–3
No Acknowledge from Master .................................................................................................................. 18–4
No Acknowledge from Slave ..................................................................................................................... 18–5
General Call ............................................................................................................................................. 18–5
Generation of Repeated Starts by Master.................................................................................................. 18–5
DMA Requests ......................................................................................................................................... 18–6
I2C Reset Mode ....................................................................................................................................... 18–6
I2C Test Modes ........................................................................................................................................ 18–6
I2C Low-Power Mode .............................................................................................................................. 18–6
I2C Bus Clear Operation.......................................................................................................................... 18–6
Power-down Considerations ..................................................................................................................... 18–7
I2C Data Transfer........................................................................................................................................ 18–7

xx

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

I2C Interrupts and Exceptions..................................................................................................................... 18–8
ADuCM4050 I2C Register Descriptions .................................................................................................... 18–8
Master Address Byte 1 ............................................................................................................................. 18–9
Master Address Byte 2 ........................................................................................................................... 18–10
Hardware General Call ID ..................................................................................................................... 18–11
Automatic Stretch SCL .......................................................................................................................... 18–12
Start Byte ............................................................................................................................................... 18–14
Serial Clock Period Divisor .................................................................................................................... 18–15
First Slave Address Device ID ................................................................................................................ 18–16
Second Slave Address Device ID ............................................................................................................ 18–17
Third Slave Address Device ID .............................................................................................................. 18–18
Fourth Slave Address Device ID ............................................................................................................ 18–19
Master Control ...................................................................................................................................... 18–20
Master Current Receive Data Count ...................................................................................................... 18–22
Master Receive Data .............................................................................................................................. 18–23
Master Receive Data Count ................................................................................................................... 18–24
Master Status ......................................................................................................................................... 18–25
Master Transmit Data ............................................................................................................................ 18–28
Slave Control ......................................................................................................................................... 18–29
Shared Control ...................................................................................................................................... 18–31
Slave Receive .......................................................................................................................................... 18–32
Slave I2C Status/Error/IRQ ................................................................................................................... 18–33
Master and Slave FIFO Status ................................................................................................................ 18–36
Slave Transmit ....................................................................................................................................... 18–38
Timing Control Register ....................................................................................................................... 18–39

Beeper Driver (BEEP)
Beeper Features............................................................................................................................................ 19–1
Beeper Functional Description..................................................................................................................... 19–1
Beeper Block Diagram.............................................................................................................................. 19–1

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencexxiBeeper Operating Modes ............................................................................................................................. 19–2
Pulse Mode............................................................................................................................................... 19–3
Sequence Mode......................................................................................................................................... 19–3
Tones........................................................................................................................................................ 19–4
Clocking and Power.................................................................................................................................. 19–4
Power-down Considerations ..................................................................................................................... 19–5
Beeper Interrupts and Events ....................................................................................................................... 19–5
Beeper Programming Model ........................................................................................................................ 19–5
Timing Diagram....................................................................................................................................... 19–5
Programming Guidelines.......................................................................................................................... 19–6
ADuCM4050 BEEP Register Descriptions ................................................................................................. 19–7
Beeper Configuration .............................................................................................................................. 19–8
Beeper Status ......................................................................................................................................... 19–10
Tone A Data .......................................................................................................................................... 19–12
Tone B Data .......................................................................................................................................... 19–13

ADC Subsystem
ADC Features .............................................................................................................................................. 20–1
ADC Functional Description ....................................................................................................................... 20–2
ADC Subsystem Block Diagram............................................................................................................... 20–2
ADC Subsystem Components ..................................................................................................................... 20–2
ADC Voltage Reference Selection ............................................................................................................. 20–2
Digital Offset Calibration......................................................................................................................... 20–4
Powering the ADC ................................................................................................................................... 20–4
Hibernate ................................................................................................................................................. 20–5
Sampling and Conversion Time ............................................................................................................... 20–6
Operation ................................................................................................................................................. 20–8
Programming Flow................................................................................................................................. 20–10
Temperature Sensor ................................................................................................................................ 20–14
Battery Monitoring................................................................................................................................. 20–15

xxii

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceOversampling ......................................................................................................................................... 20–15
Averaging Function................................................................................................................................. 20–16
ADC Digital Comparator....................................................................................................................... 20–17
ADuCM4050 ADC Register Descriptions ................................................................................................ 20–20
Alert Indication ..................................................................................................................................... 20–22
Averaging Configuration ....................................................................................................................... 20–23
Battery Monitoring Result ..................................................................................................................... 20–24
Calibration Word ................................................................................................................................... 20–25
ADC Configuration ............................................................................................................................... 20–26
Reference Buffer Low Power Mode ........................................................................................................ 20–28
Conversion Result Channel 0 ................................................................................................................ 20–29
Conversion Result Channel 1 ................................................................................................................ 20–30
Conversion Result Channel 2 ................................................................................................................ 20–31
Conversion Result Channel 3 ................................................................................................................ 20–32
Conversion Result Channel 4 ................................................................................................................ 20–33
Conversion Result Channel 5 ................................................................................................................ 20–34
Conversion Result Channel 6 ................................................................................................................ 20–35
Conversion Result Channel 7 ................................................................................................................ 20–36
ADC Conversion Configuration ............................................................................................................ 20–37
ADC Conversion Time .......................................................................................................................... 20–38
DMA Output Register ........................................................................................................................... 20–39
Channel 0 Hysteresis ............................................................................................................................. 20–40
Channel 1 Hysteresis ............................................................................................................................. 20–41
Channel 2 Hysteresis ............................................................................................................................. 20–42
Channel 3 Hysteresis ............................................................................................................................. 20–43
Interrupt Enable .................................................................................................................................... 20–44
Channel 0 High Limit ........................................................................................................................... 20–45
Channel 0 Low Limit ............................................................................................................................ 20–46
Channel 1 High Limit ........................................................................................................................... 20–47
Channel 1 Low Limit ............................................................................................................................ 20–48
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencexxiiiChannel 2 High Limit ........................................................................................................................... 20–49
Channel 2 Low Limit ............................................................................................................................ 20–50
Channel 3 High Limit ........................................................................................................................... 20–51
Channel 3 Low Limit ............................................................................................................................ 20–52
Overflow of Output Registers ................................................................................................................ 20–53
ADC Power-up Time ............................................................................................................................. 20–55
ADC Status ........................................................................................................................................... 20–56
Temperature Result 2 ............................................................................................................................ 20–58
Temperature Result ............................................................................................................................... 20–59

Real-Time Clock (RTC)
RTC Features............................................................................................................................................... 21–1
RTC Functional Description........................................................................................................................ 21–2
RTC Block Diagram................................................................................................................................. 21–2
RTC Operating Modes ................................................................................................................................ 21–3
Initial RTC Power-Up .............................................................................................................................. 21–3
Persistent, Sticky RTC Wake-Up Events ................................................................................................... 21–4
RTC Capacity to Accommodate Posted Writes by CPU ........................................................................... 21–4
Realignment of RTC Count to Packet Defined Time Reference ............................................................... 21–4
RTC Recommendations: Clocks and Power................................................................................................. 21–4
RTC Interrupts and Exceptions ................................................................................................................... 21–5
RTC Digital Trimming ................................................................................................................................ 21–5
RTC Programming Model ........................................................................................................................... 21–6
Programming Guidelines.......................................................................................................................... 21–6
RTC SensorStrobe ....................................................................................................................................... 21–6
RTC Input Capture ................................................................................................................................... 21–15
RTC Power Modes Behavior...................................................................................................................... 21–19
ADuCM4050 RTC Register Descriptions ................................................................................................. 21–21
RTC Alarm 0 ......................................................................................................................................... 21–24
RTC Alarm 1 ......................................................................................................................................... 21–25

xxiv

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

RTC Alarm 2 ......................................................................................................................................... 21–26
RTC Count 0 ........................................................................................................................................ 21–27
RTC Count 1 ........................................................................................................................................ 21–28
RTC Count 2 ........................................................................................................................................ 21–29
RTC Control 0 ...................................................................................................................................... 21–30
RTC Control 1 ...................................................................................................................................... 21–34
RTC Control 2 for Configuring Input Capture Channels ...................................................................... 21–37
RTC Control 3 for Configuring SensorStrobe Channel ......................................................................... 21–42
RTC Control 4 for Configuring SensorStrobe Channel ......................................................................... 21–46
RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling ............................................... 21–50
RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge ...................................... 21–52
RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity .................................. 21–55
RTC Freeze Count ................................................................................................................................. 21–57
RTC GPIO Pin Mux Control Register 0 ............................................................................................... 21–58
RTC GPIO Pin Mux Control Register 1 ............................................................................................... 21–59
RTC Gateway ........................................................................................................................................ 21–60
RTC Input Capture Channel 2 .............................................................................................................. 21–61
RTC Input Capture Channel 3 .............................................................................................................. 21–62
RTC Input Capture Channel 4 .............................................................................................................. 21–63
RTC Modulo ......................................................................................................................................... 21–64
RTC SensorStrobe Channel 1 ................................................................................................................ 21–66
RTC Auto-Reload High Duration for SensorStrobe Channel 1 ............................................................. 21–67
RTC Auto-Reload Low Duration for SensorStrobe Channel 1 ............................................................... 21–68
RTC SensorStrobe Channel 1 Target ..................................................................................................... 21–69
RTC SensorStrobe Channel 2 ................................................................................................................ 21–70
RTC Auto-Reload High Duration for SensorStrobe Channel 2 ............................................................. 21–71
RTC Auto-Reload Low Duration for SensorStrobe Channel 2 ............................................................... 21–72
RTC SensorStrobe Channel 2 Target ..................................................................................................... 21–73
RTC SensorStrobe Channel 3 ................................................................................................................ 21–75
RTC Auto-Reload High Duration for SensorStrobe Channel 3 ............................................................. 21–76
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Referencexxv

RTC Auto-Reload Low Duration for SensorStrobe Channel 3 ............................................................... 21–77
RTC SensorStrobe Channel 3 Target ..................................................................................................... 21–78
RTC SensorStrobe Channel 4 ................................................................................................................ 21–80
RTC Mask for SensorStrobe Channel .................................................................................................... 21–81
RTC Masks for SensorStrobe Channels on Time Control ...................................................................... 21–83
RTC Snapshot 0 .................................................................................................................................... 21–84
RTC Snapshot 1 .................................................................................................................................... 21–85
RTC Snapshot 2 .................................................................................................................................... 21–86
RTC Status 0 ......................................................................................................................................... 21–87
RTC Status 1 ......................................................................................................................................... 21–92
RTC Status 2 ......................................................................................................................................... 21–95
RTC Status 3 ....................................................................................................................................... 21–100
RTC Status 4 ....................................................................................................................................... 21–105
RTC Status 5 ....................................................................................................................................... 21–109
RTC Status 6 ....................................................................................................................................... 21–114
RTC Status 7 ....................................................................................................................................... 21–117
RTC Status 8 ....................................................................................................................................... 21–119
RTC Status 9 ....................................................................................................................................... 21–124
RTC Trim ............................................................................................................................................ 21–128

Timer (TMR)
TMR Features.............................................................................................................................................. 22–1
TMR Functional Description ...................................................................................................................... 22–2
TMR Block Diagram................................................................................................................................ 22–2
TMR Operating Modes ............................................................................................................................... 22–3
Free Running Mode.................................................................................................................................. 22–3
Periodic Mode .......................................................................................................................................... 22–3
Toggle Mode............................................................................................................................................. 22–4
Match Mode............................................................................................................................................. 22–4
PWM Modulation ....................................................................................................................................... 22–6

xxvi

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencePWM Demodulation................................................................................................................................... 22–6
Clock Select ................................................................................................................................................. 22–7
Capture Events............................................................................................................................................. 22–7
TMR Interrupts and Exceptions .................................................................................................................. 22–9
ADuCM4050 TMR Register Descriptions ................................................................................................. 22–9
16-bit Load Value, Asynchronous .......................................................................................................... 22–10
16-bit Timer Value, Asynchronous ........................................................................................................ 22–11
Capture ................................................................................................................................................. 22–12
Clear Interrupt ...................................................................................................................................... 22–13
Control .................................................................................................................................................. 22–14
Timer Event Selection Register .............................................................................................................. 22–17
16-bit Load Value .................................................................................................................................. 22–18
PWM Control Register ......................................................................................................................... 22–19
PWM Match Value ................................................................................................................................ 22–20
Status ..................................................................................................................................................... 22–21
16-bit Timer Value ................................................................................................................................ 22–23

RGB Timer
RGB Timer Features .................................................................................................................................... 23–1
RGB Timer Functional Description............................................................................................................. 23–1
RGB Timer Block Diagram ......................................................................................................................... 23–1
RGB Timer Operation................................................................................................................................. 23–2
PWM Modulation.................................................................................................................................... 23–4
PWM Demodulation................................................................................................................................ 23–4
Clock Select .............................................................................................................................................. 23–5
Capture Events ......................................................................................................................................... 23–5
ADuCM4050 TMR_RGB Register Descriptions ........................................................................................ 23–7
16-bit Load Value, Asynchronous ............................................................................................................ 23–8
16-bit Timer Value, Asynchronous .......................................................................................................... 23–9
Capture ................................................................................................................................................. 23–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencexxviiClear Interrupt ...................................................................................................................................... 23–11
Control .................................................................................................................................................. 23–12
Timer Event selection Register .............................................................................................................. 23–15
16-bit Load Value .................................................................................................................................. 23–16
PWM0 Control Register ....................................................................................................................... 23–17
PWM0 Match Value .............................................................................................................................. 23–18
PWM1 Control Register ....................................................................................................................... 23–19
PWM1 Match Value .............................................................................................................................. 23–20
PWM2 Control Register ....................................................................................................................... 23–21
PWM2 Match Value .............................................................................................................................. 23–22
Status ..................................................................................................................................................... 23–23
16-bit Timer Value ................................................................................................................................ 23–25

Watchdog Timer (WDT)WDT Features ............................................................................................................................................. 24–1
WDT Functional Description...................................................................................................................... 24–1
WDT Block Diagram ............................................................................................................................... 24–1
WDT Operating Modes .............................................................................................................................. 24–2
Watchdog Synchronization ....................................................................................................................... 24–3
Watchdog Power Modes Behavior ............................................................................................................ 24–3
ADuCM4050 WDT Register Descriptions ................................................................................................. 24–3
Current Count Value ............................................................................................................................... 24–5
Control .................................................................................................................................................... 24–6
Load Value ............................................................................................................................................... 24–8
Clear Interrupt ........................................................................................................................................ 24–9
Status ..................................................................................................................................................... 24–10

ADuCM4050 Register List

xxviii

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencePreface
Thank you for purchasing and developing systems using an ADuCM4050 Micro Controller Unit (MCU) from Analog Devices, Inc.

Purpose of This Manual
The ADuCM4050 Ultra Low Power ARM® Cortex®-M4F MCU with Integrated Power Management Hardware Reference provides architectural information about the ADuCM4050 microcontrollers. This hardware reference provides
the main architectural information about the microcontroller.
For programming information, visit the ARM Information Center at: http://infocenter.arm.com/help/
The applicable documentation for programming the ARM Cortex-M4F processor include:• ARM Cortex-M4F Devices Generic User Guide• ARM Cortex-M4F Technical Reference Manual
For timing, electrical, and package specifications, refer to the ADuCM4050 Ultra Low Power ARM Cortex-M4F
MCU with Integrated Power Management Data Sheet.

Intended Audience
The primary audience for this manual is a programmer who is familiar with the Analog Devices processors. The
manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts, such as programming reference books and data sheets, that describe their target architecture.

What's New in This Manual?
This is Revision 1.1 of the ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference. This revision updates the Cryptography (CRYPTO), Real-Time Clock (RTC), Universal
Asynchronous Receiver/Transmitter (UART), Inter-Integrated Circuits (I2C) Interface, and Watchdog Timer(WDT) chapters.

Technical or Customer Support
You can reach customer and technical support for processors from Analog Devices in the following ways:• Post your questions in the analog microcontrollers support community at EngineerZone:
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Referencexxixhttp://ez.analog.com/community/analog-microcontrollers• Submit your questions to technical support at Connect with ADI Specialists:
http://www.analog.com/support• E-mail your questions about software/hardware development tools to:processor.tools.support@analog.com• E-mail your questions about processors to:iot_support@analog.com (world wide support)• Phone questions to 1-800-ANALOGD (USA only)• Contact your Analog Devices sales office or authorized distributor. Locate one at:
http://www.analog.com/adi-sales• Send questions by mail to:
Analog Devices, Inc.
Three Technology Way
P.O. Box 9106
Norwood, MA 02062-9106 USA

Product Information
Product information can be obtained from the Analog Devices Web site and the online help system.

Analog Devices Web Site
The Analog Devices Website (http://www.analog.com) provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.
To access a complete technical library for each processor family, go to http://www.analog.com/processors/technical_library. The manuals selection opens a list of current manuals related to the product as well as a link to theprevious revisions of the manuals. When locating your manual title, note a possible errata check mark next to thetitle that leads to the current correction report against the manual.
MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display
only the latest information about products you are interested in. You can choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests, including documentation errata against all manuals. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.
Visit MyAnalog.com to sign up. If you are a registered user, just log on. Your user name is your e-mail address.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Referencexxx

EngineerZone
EngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processingand DSP design questions.
Use EngineerZone to connect with other MCU developers who face similar design challenges. You can also use thisopen forum to share knowledge and collaborate with the ADI support team and your peers. Visit http://
ez.analog.com to sign up.

Notation Conventions
Text conventions used in this manual are identified and described as follows. Additional conventions, which apply
only to specific chapters, may appear throughout this document.
ExampleDescription

File > Close

Titles in reference sections indicate the location of an item within the CrossCore
Embedded Studio IDE's menu system (for example, the Close command appearson the File menu).

{this | that}

Alternative required items in syntax descriptions appear within curly brackets andseparated by vertical bars; read the example as this or that. One or the otheris required.

[this | that]

Optional items in syntax descriptions appear within brackets and separated byvertical bars; read the example as an optional this or that.

[this, …]

Optional item lists in syntax descriptions appear within brackets delimited bycommas and terminated with an ellipse; read the example as an optional commaseparated list of this.

.SECTION

Commands, directives, keywords, and feature names are in text with Letter
Gothic font.

filename

Non-keyword placeholders appear in text with italic style format.

NOTE:

NOTE: For correct operation, ...
A note provides supplementary information on a related topic. In the online version of this book, the word NOTE: appears instead of this symbol.

CAUTION:CAUTION: Incorrect device operation may result if ...
CAUTION: Device damage may result if ...
A caution identifies conditions or inappropriate usage of the product that could
lead to undesirable results or product damage. In the online version of this book,the word CAUTION appears instead of this symbol.

ATTENTION:ATTENTION: Injury to device users may result if ...
A warning identifies conditions or inappropriate usage of the product that could
lead to conditions that are potentially hazardous for devices users. In the online
version of this book, the word ATTENTION appears instead of this symbol.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Referencexxxi

Register Diagram Conventions
Register diagrams use the following conventions:• The descriptive name of the register appears at the top, followed by the short form of the name in parentheses.
• If the register is read-only (RO), write-1-to-set (W1S), or write-1-to-clear (W1C), this information appears under the name. Read/write is the default and is not noted. Additional descriptive text may follow.
• If any bits in the register do not follow the overall read/write convention, this is noted in the bit description
after the bit name.
• If a bit has a short name, the short name appears first in the bit description, followed by the long name inparentheses.
• The reset value appears in binary in the individual bits and in hexadecimal to the right of the register.
• Bits marked X have an unknown reset value. Consequently, the reset value of registers that contain such bits isundefined or dependent on pin values at reset.
• Shaded bits are reserved.
NOTE: To ensure upward compatibility with future implementations, write back the value that is read for reserved
bits in a register, unless specified.
Register description tables use the following conventions:• Each bit's or bit field's access type appears beneath the bit number in the table in the form (read-access/writeaccess). The access types include:• R = read, RC = read clear, RS = read set, R0 = read zero, R1 = read one, Rx = read undefined• W = write, NW = no write, W1C = write one to clear, W1S = write one to set, W0C = write zero to clear, W0S= write zero to set, WS = write to set, WC = write to clear, W1A = write one action.
• Several bits and bit field descriptions include enumerations, identifying bit values and related functionality. Unless indicated (with a prefix), these enumerations are decimal values.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Referencexxxii

Introduction

1 Introduction

The ADuCM4050 MCU is an ultra low power microcontroller system with integrated power management for processing, control, and connectivity. The MCU system is based on the ARM Cortex-M4F processor. The MCU also
has a collection of digital peripherals, embedded SRAM and flash memory, and an analog subsystem which provides
clocking, reset, and power management capability in addition to an analog-to-digital converter (ADC) subsystem.
The ADuCM4050 MCU provides a collection of power modes and features such as dynamic and software controlled clock gating and power gating to support extremely low dynamic and hibernate power.

ADuCM4050 MCU Features
The ADuCM4050 MCU supports the following features:• Up to 52 MHz ARM Cortex-M4F processor• 512 KB of embedded flash memory with ECC• 128 KB system SRAM with parity• 32 KB user configurable instruction/data SRAM with parity
4 KB of SRAM may be used as cache memory to reduce active power consumption by reducing access to flash
memory• Power Management Unit (PMU)• Power-on-Reset (POR) and Power Supply Monitor (PSM)• A buck converter for improved efficiency during active and Flexi™ states• A multilayer AMBA bus matrix• A multi-channel central direct memory access (DMA) controller• Programmable GPIOs• Two UART peripheral interfaces• One I2C interface• Three SPI interfaces capable of interfacing gluelessly with a range of sensors and converters
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

1–1

ADuCM4050 Functional Description• A serial port (SPORT) capable of interfacing with a wide range of radios and converters. Two single direction
half SPORT or one bidirectional full SPORT• A beeper driver to produce single and multi-tone playback options• A real-time clock (RTC) capable of maintaining accurate wall clock time
• A flexible real-time clock (FLEX_RTC) that supports a wide range of wake-up times• Three general-purpose timers and one watchdog timer• Crypto hardware supporting AES-128, AES-256 along with various modes (ECB, CBC, CTR, CBC-MAC,
CCM, CCM*) and SHA-256, and HMAC mode
• Protected key Storage with key wrap-unwrap• Keyed HMAC with key unwrap• True Random Number Generator (TRNG)• Hardware CRC with programmable generator polynomial• Multi parity-bit-protected SRAM
• A 12-bit, 1.8 MSPS, SAR ADC• RGB timer for driving RGB LED

ADuCM4050 Functional Description
This section provides information on the function of the ADuCM4050 MCU.

ADuCM4050 Block Diagram
The ARM Cortex-M4F core is a 32-bit reduced instruction set computer (RISC) offering up to 66 MIPS of peak
performance at 52 MHz. A central DMA controller is used to efficiently move data between peripherals and memory.

1–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Functional Description

Serial WireITM tracePLL
HFXTALLFXTAL
HFOSC
LFOSC

Ref Buffer
Temp
SensorADC

ADC Controller

CRYPTO(AES 128/256,
SHA 256)
Keyed HMAC
Key Wrap-unwrap
Protected
Key Storage

HP Buck

ARM
Cortex-M4F
NVIC

WIC

MPU

FPU

Multi
Layer
AMBA
Bus
Matrix

Data SRAM/Instruction SRAM/Cache (128 KB)

DMA

SPORT

UART0

Power
Management

Flash (512 KB)

UART1

TMR0

TMR1

RTC0

RTC1

TMR2

RGB
TMR

WDT

Beeper

AHB-APB
BridgeProgrammable
CRC Polynomial

SPI0

SPI1

SPIH

I2C

TRNG

GPIO

Figure 1-1: ADuCM4050 Block Diagram

Memory Architecture
The ADuCM4050 MCU incorporates 512 KB of embedded flash memory for program code and nonvolatile data
storage, 96 KB of data SRAM, 32 KB of SRAM (configured as instruction space or data space). For added robustness and reliability, ECC is enabled for the flash memory and multi bit parity can be used to detect random soft
errors in SRAM
0x4000_0C3C
0x4000_0C00
0x4000_082C
0x4000_0800
0x4000_042C

RESERVED

0x4000_70C4

RGB TIMER

0x4000_7000

RESERVED

0x4000_5C0F

GENERAL PURPOSE TIMER 2
RESERVEDGENERAL PURPOSE TIMER 1

0x4000_0400
0x4000_002C

RESERVEDGENERAL PURPOSE TIMER 00x4000_0000
0x2005_4000

RESERVEDSYSTEM SRAM BANK 6 (16kB)

0x2005_0000
0x2004_8000

0x4000_5C00
0x4000_544C
0x4000_5400
0x4000_504C
0x4000_5000
0x4000_4438
0x4000_4400
0x4000_4038

SYSTEM SRAM BANK 5 (32kB)

0x4000_4000
0x4000_305C

SYSTEM SRAM BANK 3 (16kB)

0x4000_3000
0x4000_2C1C

0x2004_4000

0x2000_4000

RESERVEDSYSTEM SRAM BANK 0 (16kB)

0x2000_0000
0x1000_8000

0x1000_0000

RESERVEDINSTRUCTION SRAM BANK 1
INSTRUCTION SRAM BANK 2,
INSTRUCTION SRAM BANK 7(32kB)RESERVED

0x0008 0000
0x0000_0000

ADC00x4000_2C00
0x4000_2040
0x4000_2000
0x4000_14E8
0x4000_1400
0x4000_10E80x4000_1000

RESERVED
0x4004_C814

RESERVEDBEEPER 0

POWER MANAGEMENT, EXTERNALINTERRUPTS, CLOCKING,MISCELLANEOUS REGISTERSRESERVEDUART 10x4004_C000

RESERVED

0x4004_40C8

UART 0RESERVEDSPI 1 MASTER/SLAVESYSTEM SRAM BANK 4 (16kB)
0x2004_0000

RESERVEDRESERVEDSPI 0 MASTER/SLAVERESERVED
I2C 0 MASTER/SLAVERESERVED
WATCHDOG TIMER

0x4004_4000
0x4004_0418
0x4004_0400
0x4004_0018

RESERVEDCRYPTOGRAPHIC ACCELERATORRESERVEDRANDOM NUMBER GENERATORRESERVEDPROGRAMMABLE CRC ENGINE

0x4004_0000
0x4003_806C

RESERVED

0x4003_8000
0x4002_4038

RESERVEDSPORT 0SPIH 0 MASTER/SLAVE

0x4002_4000
0x4002_00F8

RESERVEDRESERVED

0x4002_0000
0x4001_8064

RESERVEDREAL TIME CLOCK 1 (RTC1)0x4001_8000

RESERVEDSYSTEM ID AND DEBUG ENABLE

RESERVEDREAL TIME CLOCK 0 (RTC0)GPIOFLASH CONTROLLER
RESERVED

0x4001_0FE40x4001_0000

DMA 0

512kB FLASH MEMORY

Figure 1-2: ADuCM4050 Memory Map - SRAM Mode 0

SRAM Region
This memory space contains the application instructions and literal (constant) data which must be accessed in realtime. It supports read/write access by the ARM Cortex M4F core and read/write DMA access by system peripherals.
SRAM is divided into data SRAM of 96 KB and instruction SRAM of 32 KB. If instruction SRAM is not enabled,
then the associated 32 KB can be mapped as data SRAM, resulting in 128 KB of data SRAM.
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ADuCM4050 Functional Description

Internal SRAM Data Region
This space can contain read/write data. Internal SRAM can be partitioned between code and data (SRAM region in
M4F space) in 32 KB blocks. Access to this region occurs at core clock speed, with no wait states. It supports read/
write access by the Cortex-M4F core and read/write DMA access by system devices.
The figure shows the address map of the SRAM for various user selectable configurations. For information about theconfiguration, refer to Static Random Access Memory (SRAM).
MODE0
SRAM
BANK

MODE1

MODE2

MODE3

ISRAM Enabled
Cache OFF
32 KB ISRAM
96 KB DSRAM

ISRAM Enabled
4 KB Cache
28 KB ISRAM
96 KB DSRAM

ISRAM Disabled
Cache OFF0 KB ISRAM
128 KB DSRAM

ISRAM Disabled
4 KB Cache
0 KB ISRAM
124 KB DSRAM

512 KB Flash512 KB Flash512 KB Flash512 KB Flash

16 KB DSRAM

16 KB DSRAM

Bank1

12 KB DSRAM

12 KB DSRAM

0x2000_7FFF

Bank2

4 KB DSRAM

0x2004_0000

0x2004_3FFF

Bank3

16 KB DSRAM

0x2004_4000

0x2004_7FFF

Bank40x2004_8000

0x2004_FFFF

0x2005_0000

0x2005_3FFF

0x2005_4000

0x2005_7FFF

INI ADDR

END ADDR

0x0000_0000

0x0007_FFFF

0x1000_0000

0x1000_2FFF

Bank1

12 KB ISRAM

12 KB ISRAM

0x1000_3000

0x1000_6FFF

Bank7

16 KB ISRAM

16 KB ISRAM

0x1000_7000

0x1000_7FFF

Bank2

4 KB ISRAM

0x2000_0000

0x2000_3FFF

Bank0

16 KB DSRAM

0x2000_4000

0x2000_6FFF

0x2000_7000

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

Bank532 KB DSRAM

32 KB DSRAM

32 KB DSRAM

32 KB DSRAM

Bank6

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

16 KB DSRAM

Bank7Always Retained
Retained if SRAM_RET.RET1 is set
Retained if SRAM_RET.RET2 is set
Retained if SRAM_RET.RET3 is set
Retained if SRAM_RET.RET4 is set
Not Retained
Not Implemented

Figure 1-3: Selectable Configuration

System Region
The ARM Cortex-M4F processor accesses the system region on its SYS interface and is handled within the CortexM4F platform.
CoreSight™ ROM: The ROM table entries point to the debug components of the processor.
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ADuCM4050 Functional Description

ARM APB Peripherals: This space is defined by ARM and occupies the bottom 256 KB of the SYS region. The
space supports read/write access by the M4F core to the ARM core’s internal peripherals (SCS, NVIC, WIC) andthe CoreSight ROM. It is not accessible by system DMA.
Platform Control Registers: This space has registers within the Cortex-M4F platform component that control theARM core, its memory, and the code cache. It is accessible by the M4F core (but not accessible by system DMA).

Flash Controller
The ADuCM4050 MCU includes 512 KB of embedded flash memory, which is accessed using a flash controller.
The flash controller is coupled with a cache controller. A prefetch mechanism is implemented in the flash controller
to optimize code performance. Flash writes are supported by a key hole mechanism via APB writes to memory-mapped registers. The flash controller provides support for DMA-based key hole writes.
The flash controller supports:• A fixed user key required for running protected commands including mass erase and page erase.
• An optional and user definable user failure analysis key (FAA key). Analog Devices personnel needs this key
while performing failure analysis.
• An optional and user definable write protection for user accessible memory.
• 8-bit error correction code (ECC).

Cache Controller
The ADuCM4050 MCU has an optional 4 KB instruction cache. In certain applications, enabling the cache andexecuting the code can result in lower power consumption than operating directly from flash. When the cache controller is enabled, 4 KB of instruction SRAM is reserved as cache memory. In hibernate mode, the cache memory is
not retained.

ARM Cortex-M4F Memory Subsystem
The memory map of the ADuCM4050 MCU is based on the Cortex-M4F model from ARM. By retaining thestandardized memory mapping, it becomes easier to port applications across M4F platforms. ADuCM4050 application development is typically based on memory blocks across code/SRAM regions. Sufficient internal memory isavailable via internal SRAM and internal flash.

Booting
The MCU supports the following boot modes:• Booting from internal flash• Upgrading software through UART download
If the SYS_BMODE0 pin (GPIO17) is pulled low during power-up or a hard reset, the MCU enters into serial
download mode. In this mode, an on-chip loader routine is initiated in the kernel, which configures the UART port
and communicates with the host to manage the firmware upgrade via a specific serial download protocol.
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ADuCM4050 Functional Description

Table 1-1: Boot Modes
Boot Mode

Description

0

UART download mode.

1

Flash boot. Boot from integrated flash memory.

Security Features
The ADuCM4050 MCU provides a combination of hardware and software protection mechanisms that lock out
access to the part in secure mode, but grant access in open mode. These mechanisms include password-protectedslave boot modes (UART), as well as password-protected SWD debug interfaces. During boot, the system is clockedfrom an internal on-chip oscillator. Reset computes a hardware checksum of the information area and then permit
the CPU to execute the Analog Devices boot loader in the flash information area if the checksum passes. The Analog Devices boot loader inspects the GPIO boot pin (GPIO17) which determines if user code or a UART download
is executed.
There is a mechanism to protect the device contents (flash, SRAM, CPU registers, and peripheral registers) frombeing read through an external interface by an unauthorized user. This is referred to as read protection.
It is possible to protect the device from being reprogrammed in-circuit with unauthorized code. This is referred to as
in-circuit write protection.
The device can be configured with no protection, read protection, or read and in-circuit write protection. It is notnecessary to provide in-circuit write protection without read protection.

Safety Features
The ADuCM4050 MCU provides several features that help achieve certain levels of system safety and reliability.
While the level of safety is mainly dominated by system considerations, the following features are provided to enhance robustness.

Multi Parity Bit Protected SRAM
In the MCU's SRAM and cache memory space, each word is protected by multiple parity bits to allow detection of
random soft errors.

Programmable GPIOs
The ADuCM4050 MCU has 44/51 GPIO pins in the LFCSP/WLCSP packages, which have multiple, configurable
functions defined by the user code. They can be configured as I/O pins and have programmable pull-up resistors(SWD_CLK has a pull-down). All I/O pins are functional over the full supply range.
In deep sleep modes, GPIO pins retain state. On reset, they tristate.

TimersGeneral-Purpose Timers

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ADuCM4050 Functional Description

The ADuCM4050 MCU has three identical general-purpose timers, each with a 16-bit up/down counter. The up/
down counter can be clocked from one of four user-selectable clock sources. Any selected clock source can be scaled
down using a prescaler of 1, 16, 64, or 256.
Watchdog Timer (WDT)The watchdog timer is a 16-bit count-down timer with a programmable prescaler. The prescaler source is selectable
and can be scaled by a factor of 1, 16, or 256. The watchdog timer is clocked by the 32 kHz on-chip oscillator(LFOSC) and used to recover from an illegal software state. The WDT requires periodic servicing to prevent it fromforcing a reset or interrupt to the MCU.
RGB Timer
The ADuCM4050 MCU has one RGB Timer that supports common anode RGB LED. It has a timer counter andthree compare registers. It can generate three distinct PWM waveforms on three ports/pins simultaneously so thatdifferent colors can be realized on the common anode RGB LED.
When the RGB timer is in operation, the other three general-purpose timers are available for user software.
All timers support event capture feature, where they can take 40 different interrupts.

Power Management
The ADuCM4050 MCU includes power management and clocking features.
Power Modes
The PMU provides control of the ADuCM4050 MCU power modes and allows the ARM Cortex-M4F to control
the clocks and power gating to reduce the dynamic power and hibernate power.
Several power modes are available. Each mode provides an additional low power benefit with a corresponding reduction in functionality.
• Active Mode: All peripherals can be enabled. Active power is managed by optimized clock management.
• Flexi Mode: The core is clock-gated, but the remainder of the system is active. No instructions can be executedin this mode, but DMA transfers can continue between peripherals and memory.
• Hibernate Mode: This mode provides configurable SRAM and port pin retention, a limited number of wakeup interrupts, and (optionally) an active RTC.
• Shutdown Mode: This mode is the deepest sleep mode, in which all the digital and analog circuits are powered
down with an option to wake from four possible wake-up sources. The RTC can be (optionally) enabled in thismode, and the device can be periodically woken up by the RTC interrupt.
• Shutdown Mode - Fast wake-up: The functionality is same as that of the shutdown mode, but with a fasterwake-up time (at the expense of high power consumption).

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ADuCM4050 Functional Description

Clocking
The ADuCM4050 MCU has the following clocking options:
26 MHz• Internal oscillator: HFOSC (26 MHz)• External crystal oscillator : HFXTAL (26 MHz or 16 MHz)• GPIO clock in: SYS_CLK_IN
32 kHz• Internal oscillator: LFOSC• External crystal oscillator: LFXTALClock Fail Detection
The LFOSC clock continuously monitors LFXTAL in active, Flexi, and hibernate modes. If LFXTAL stops running, there is an option to detect and generate an interrupt and/or automatically switch to LFOSC without softwareintervention. The HFOSC clock monitors HFXTAL, GPIO CLK, and PLL CLK. If any of these clocks is used as
the system clock, and they fail to toggle, it can be detected through an interrupt. Also, there is an option to automatically switch to the HFOSC.

Real-Time Clock (RTC)
The ADuCM4050 MCU has two real-time clock blocks, RTC0 and RTC1 (also called FLEX_RTC).
The clock blocks share a low-power crystal oscillation circuit that operates in conjunction with a 32,768 Hz external
crystal or LFOSC.
The RTC has an alarm that interrupts the core when the programmed alarm value matches the RTC count. The
software enables and configures the RTC and correlates the count to the time of day.
The RTC also has a digital trim capability to allow a positive or negative adjustment to the RTC count at fixedintervals.
The FLEX_RTC supports SensorStrobe™ mechanism, via the SensorStrobe pins (SSx). Using this mechanism, the
ADuCM4050 MCU can be used as a programmable clock generator in all power modes except shutdown mode. In
this way, the external sensors can have their timing domains mastered by the ADuCM4050 MCU, as SensorStrobe
can output a programmable divider from the FLEX_RTC, which can operate up to a resolution of 30.7 μs. The
sensors and microcontroller are in sync, which removes the need for additional resampling of data to time align it.
In the absence of this mechanism,• The external sensor uses an RC oscillator. The MCU has to sample the data and resample it on the MCU’stime domain before using it.
Or
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Functional Description• The MCU remains in a higher power state and drives each data conversion on the sensor side.
This mechanism allows the ADuCM4050 MCU to be in hibernate mode for a long duration and also avoids unnecessary data processing which extends the battery life of the product.
The following table shows the key differences between RTC0 and RTC1.
Table 1-2: RTC Features
Features

RTC0

RTC1 (FLEX_RTC)

Resolution of time base(prescaling)

Counts time at 1 Hz in units of seconds. Operationally, always prescales to 1 Hz (for example, divide by 32,768) and always counts realtime in units of seconds.

Can prescale the clock by any power of two from 0 to 15. It
can count time in units of any of these 16 possible prescalesettings. For example, the clock can be prescaled by 1, 2, 4,
8, …, 16384, or 32768.

Wake-up time

Time is specified in units of seconds.

Supports alarm times down to a resolution of 30.7 μs, i.e.,
where the time is specified down to a specific 32 kHz clock
cycle.

Number of alarms

One alarm only. Uses an absolute, non-repeating alarm time, specified in units of one second.

Two alarms. One absolute alarm time and one periodic
alarm, repeating every 60 prescaled time units.

SensorStrobe mechanism

Not available

Four independent SensorStrobe channels with fine control
on duty cycle and frequency (0.5 Hz to 16 kHz). SensorStrobe is an alarm mechanism in the RTC which causes an
output pulse to be sent via SSx pins to an external device toinstruct that device to take a measurement or perform someaction at a specific time. SensorStrobe events are scheduled
at a specific target time relative to the real-time count of the
RTC. This feature can be enabled in active, Flexi, and hibernate modes.

Input capture

Not available

Input capture takes a snapshot of the RTC real-time countwhen an external device signals an event via a transition on
one of the GPIO inputs to the ADuCM4050 MCU. Typically, an input capture event is triggered by an autonomous
measurement or action on such a device, which then signals
to the ADuCM4050 MCU that the RTC must take a snapshot of time corresponding to the event. The taking of thissnapshot can wake up the ADuCM4050 MCU and cause
an interrupt to its CPU. The CPU can subsequently obtain
information from the RTC on the exact 32 kHz cycle onwhich the input capture event occurred.

Input sampling

Not available

Each SensorStrobe channel has up to 3 separate GPIO inputs from an external device, which can be sampled basedon the output pulse sent to the external device. Each SensorStrobe channel can be configured to interrupt the
ADuCM4050 MCU when any activity happens on these
GPIO inputs from the external device. These inputs canbroadcast sensor states such as FIFO full, switch open, andthreshold crossed. This feature allows the MCU to remain

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ADuCM4050 Functional Description

Table 1-2: RTC Features (Continued)
Features

RTC0

RTC1 (FLEX_RTC)
in hibernate mode and wakeup to process the data only
when a specific programmed sequence from an external device is detected.

System Debug
The ADuCM4050 MCU supports serial wire debug and trace via a single wire viewer port.

Beeper Driver
The ADuCM4050 MCU has an integrated audio driver for a beeper.
The beeper driver module in the ADuCM4050 MCU generates a differential square wave of programmable frequency. It drives an external piezoelectric sound component whose two terminals connect to the differential squarewave output. The beeper driver consists of a module that can deliver frequencies from 8 kHz to ~0.25 kHz. It operates on a fixed independent 32 kHz (32,768 Hz) clock source that is unaffected by changes in system clocks.
It allows for programmable tone durations from 4 ms to 1.02 s in 4 ms increments. Single-tone (pulse) and multitone (sequence) modes provide versatile playback options.
In sequence mode, the beeper can be programmed to play any number of tone pairs from 1 to 254 (2 to 508 tones)
or be programmed to play forever (until stopped by the user). Interrupts are available to indicate the start or end ofany beep, the end of a sequence, or that the sequence is nearing completion.

Cryptographic Accelerator (Crypto)
Crypto is a 32-bit APB DMA-capable peripheral. There are two 128-bit buffers provided for data I/O operations.
These buffers are read in or read out as 4 data accesses. Big-endian and little-endian data formats are supported, as
are the following modes:• Electronic Code Book (ECB) mode - Advanced Encryption Standard (AES) mode
• Counter (CTR) mode
• Cipher Block Chaining (CBC) mode
• Message Authentication Code (MAC) mode
• Cipher Block Chaining-Message Authentication Code (CCM/CCM*) mode
• SHA-256 mode
• Protected key storage with key wrap-unwrap• HMAC signature generation

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ADuCM4050 Functional Description

CRC Accelerator
The CRC accelerator can be used to compute the CRC for a block of memory locations. The exact memory location
can be in the SRAM, flash, or any combination of memory mapped registers. The CRC accelerator generates achecksum that can be used to compare it with an expected signature.
The following are the features of the CRC:
• Generate a CRC signature for a block of data
• Supports programmable polynomial length of up to 32 bits
• Operates on 32 bits of data at a time, and generates CRC for any data length• Supports MSB-first and LSB-first CRC implementations• Various data mirroring capabilities• Initial seed to be programmed by user
• DMA controller (memory to memory transfer) can be used for data transfer to offload the MCU

True Random Number Generator (TRNG)
The TRNG is used during operations where nondeterministic values are required. This may include generating challenges for secure communication or keys used for an encrypted communication channel. The generator can be run
multiple times to generate a sufficient number of bits for the strength of the intended operation. The TRNG can beused to seed a deterministic random bit generator.

Serial Ports (SPORTs)
The synchronous serial ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheraldevices such as Analog Devices' audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, aclock, and a frame sync. The data lines can be programmed to either transmit or receive, and each data line has adedicated DMA channel. Serial port data can be automatically transferred to and from on-chip memory/external
memory via dedicated DMA channels. The frame sync and clock are shared. Some of the ADCs/DACs require twocontrol signals for their conversion process. To interface with such devices, an extra signal (SPT_CNV) is provided.
To use this signal, enable the timer enable mode. In this mode, a PWM timer inside the module is used to generate
the programmable SPT_CNV signal.
SPORT can operate in three modes:• Standard DSP serial mode
• Timer enable mode
• Gated clock mode

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ADuCM4050 Functional Description

Serial Peripheral Interface (SPI) Ports
The ADuCM4050 MCU provides three SPIs. SPI is an industry standard, full-duplex, synchronous serial interface
that allows eight bits of data to be synchronously transmitted and simultaneously received. Each SPI incorporates
two DMA channels that interface with the DMA controller. One DMA channel is used for transmit and the other isused for receive. The SPI on the MCU eases interfacing to external serial flash devices.
The SPI features available include the following:• Serial clock phase mode and serial clock polarity mode
• Loopback mode
• Continuous transfer mode
• Wired-OR output mode
• Read-command mode for half-duplex operation (Tx followed by Rx)• Flow control support• Multiple CS line support• CS software override support• Support for 3-pin SPIUART Ports
The ADuCM4050 MCU provides two full-duplex UART ports, which are fully compatible with PC-standard
UARTs.
The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMAsupported, asynchronous transfers of serial data. The UART port includes support for five to eight data bits, andnone, even, or odd parity. A frame is terminated by one, one and a half, or two stop bits.

Inter-Integrated Circuit (I2C)
The ADuCM4050 MCU provides an I2C interface. The I2C bus peripheral has two pins for data transfer. SCL is a
serial clock pin, and SDA is a serial data pin. The pins are configured in a Wired-AND format that allows arbitration in a multi-master system. A master device can be configured to generate the serial clock.
The frequency is programmed by the user in the serial clock divisor register. The master channel can be set to operate in fast mode (400 kHz) or standard mode (100 kHz).

Analog-to-Digital Converter (ADC) Subsystem
The ADuCM4050 MCU integrates a 12-bit SAR ADC with up to eight external channels. Conversions can be performed in single or auto cycle mode. In single mode, the ADC can be configured to convert on a particular channel
by selecting one of the channels. Auto cycle mode is provided to convert over multiple channels with reduced MCU
overhead of sampling and reading individual channel registers. The ADC can also be used for temperature sensing
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ADuCM4050 Functional Description

and measuring battery voltage using dedicated channels. Temperature sensing and battery monitoring cannot be included in auto cycle mode.

Reference Designs
The Circuit from the Lab® provides information on the following:• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications• Links for components in each chain to selection guides and application information• Reference designs applying best practice design techniques

Development Tools
In addition to this Hardware reference document, the development support for the ADuCM4050 MCU includes
evaluation hardware and development software tools.
Hardware
The EV-COG-AD4050LZ (for 64-lead LFCSP) and EV-COG-AD4050WZ (for 72-ball WLCSP) are available toprototype sensor configuration with the ADuCM4050 MCU.
Software
The EV-COG-AD4050LZ (for 64-lead LFCSP) and EV-COG-AD4050WZ (for 72-ball WLCSP) include a complete development and debug environment for the ADuCM4050 MCU. The Board Support Package (BSP) for the
ADuCM4050 MCU is provided for the IAR Embedded Workbench for ARM, Keil™, and CrossCore® Embedded
Studio (CCES) environments.
The BSP also includes operating system (OS) aware drivers and example code for all the peripherals on the devices.

ADuCM4050 Peripheral Memory Map
Table 1-3: Instance Summary
Name

ModuleAddress

TMR0

General-Purpose Timer

0x40000000

TMR1

General-Purpose Timer

0x40000400

TMR2

General-Purpose Timer

0x40000800

TMR3

RGB Timer

0x40000C00

RTC0

Real-Time Clock0x40001000

RTC1

Real-Time Clock0x40001400

SYS

System0x40002000

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ADuCM4050 Peripheral Memory Map

Table 1-3: Instance Summary (Continued)
Name

ModuleAddress

WDT0

Watchdog Timer

0x40002C00

I2C0

I2C Interface

0x40003000

SPI0

SPI Interface

0x40004000

SPI1

SPI Interface

0x40004400

UART0

UART Interface

0x40005000

UART1

UART Interface

0x40005400

BEEP0

Beeper0x40005C00

ADC0

ADC

0x40007000

DMA0

DMA

0x40010000

FLCC0Flash/Cache Controller

0x40018000

GPIO0

GPIO

0x40020000

GPIO1

GPIO

0x40020040

GPIO2

GPIO

0x40020080

SPI2

SPI

0x40024000

SPORT0SPORT

0x40038000

CRC0

CRC Accelerator

0x40040000

RNG0

Random Number Generator

0x40040400

CRYPT0

Cryptographic Module0x40044000

PMG0

PMG

0x4004C000

XINT0

External Interrupt Module0x4004C080

CLKG0

Clocking Subsystem

0x4004C100

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDebug (DBG) and Trace Interfaces

2 Debug (DBG) and Trace Interfaces

The ADuCM4050 MCU supports the 2-wire serial wire debug (SWD) interface and trace feature via a single-wireviewer port

Debug and Trace Features
The ADuCM4050 MCU supports trace feature for Cortex-M4F via single wire viewer port. It contains several system debug components that facilitate low-cost debug, trace and profiling, breakpoints, watch-points, and code
patching.
This product is intended to be a lightweight implementation of the ARM Cortex-M4F processor.
The following are the supported system debug and trace components:• Flash Patch and Breakpoint (FPB) unit to implement two breakpoints. Flash patching is not supported.
• Data Watchpoint and Trace (DWT) unit to implement one watch-point, trigger resources, and system profiling. The DWT does not support data matching for watchpoint generation because it only has one comparator.
• Instruction Trace Macrocell (ITM) unit that supports printf style debugging to trace operating system and application events, and generates diagnostic system information. ITM generates trace packets that originate fromone of the four available sources.
• Trace Port Interface Unit (TPIU) that acts as a bridge between on-chip trace data from ITM to a data stream.

DBG Functional Description
This section provides information on the function of the SWD interface used by the ADuCM4050 MCU.

Serial Wire Interface
The serial wire interface consists of two pins:• SWCLK: SWCLK is driven by the debug probe.
• SWDIO: SWDIO is a bidirectional signal which may be driven by the debug probe or target depending on the
protocol phase. A non-driving idle turnaround cycle is inserted on the bus whenever data direction changes toavoid contention.
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DBG Operating Modes

SWD Pull-up
There must be a pull-up resistor on the SWDIO pin. The default state of this pin is pull-up.
The SWCLK pin must be pulled to a defined state (high or low). It is recommended to pull this pin low, which isthe default state of this pin.
SWD Timing
The target samples and drives SWDIO data on posedge SWCLK.
For optimum timing, the debug probe should drive SWDIO on negedge SWCLK and sample SWDIO on posedge
SWCLK.
Probe Driving
Target Sampling

Target Driving
Probe Sampling

SWCLK

SWCLK

SWDIO

SWDIO

Probe
TargetDrivesSamples
Neg Edge Pos Edge

TargetDrivesPos Edge

Probe
SamplesPos Edge

Target to Probe
Bus Turnaround

Probe to Target
Bus Turnaround

SWCLK

SWCLK

SWDIO

SWDIO

Probe
Target
Tristates
DrivesNeg Edge Pos Edge

delay

delay

Target
Tristates
Pos Edge

Probe
DrivesNeg Edge

Figure 2-1: SWD Timing

DBG Operating Modes
Serial Wire Protocol
The Serial Wire Protocol consists of three phases:• Packet Request• Acknowledge Response• Data Transfer
The debug probe always sends the packet request.
2–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDBG Operating Modes

The target always sends the acknowledge response.
The data transfer direction depends on the packet request and acknowledge response.
Packet Request
The packet request sent by the debug probe is 8 bits and is always followed by a turnaround bit.
Table 2-1: Packet Request
Bit

Description

Start

Always High: Logic 1

APnDP

Access Port: 1 or Data Port: 0

RnW

Read: 1 or Write: 0

A[2:3]

Address sent LSB first

ParityParity = APnDP + RnW + A[2] + A[3]Stop

Always Low: Logic 0

Park

Always High: Logic 1

Turn

High Impedance / Non-Driving

Acknowledge Response
The acknowledge response sent by the target is 3 bits. If the target sends data for a read (RnW=1), it is followed
directly by the data transfer, there is no turnaround bit. If the debug probe sends the data transfer for a write(RnW=0), acknowledge is followed by a turnaround bit.
Table 2-2: Acknowledge Response
Bit

Description

ACK[0:2]

Acknowledge Sent LSB first
100: Ok
010: Wait
001: Fault

Data Transfer
The data transfer phase consists of 32 bits of data sent LSB-first [0:31], followed by a single parity bit. If the numberof bits set in the data field is odd, the parity bit is set to 1.
For reads where data is sent by the target, the data transfer is followed by a turnaround bit. For writes where data issent by the debug probe, there is no turnaround bit.
The data transfer phase is omitted for Wait/Fault responses unless the CTRL/STAT ORUNDETECT bit is set. If
the ORUNDETECT bit is set, the data transfer phase is always sent and STICKYORUN is set if a Wait/Fault response occurs.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

2–3

Debug Access Port (DAP)

Protocol Format
The figure shows the protocol format.

Stop

Park

Turn

A[2:3]

Parity

Stop

Park

Turn

ACK[0:2]

A[2:3]

Parity

Stop

Park

Turn

ACK[0:2]

ParityTurn

ParityACK[0:2]

Turn

RnW

A[2:3]

RnW

Start

APnDP

Write

WDATA[0:31]

Turn

RDATA[0.31]

Parity

Start

APnDP

Read

Turn

RnW

Start

APnDP

Wait/Fault

Figure 2-2: Protocol Format

Debug Access Port (DAP)The DAP is split into two ports:• Debug Port (DP)• Access Port (AP)There is a single Debug Port. There may be multiple Access Ports.
The Debug Port has a 2-bit (4-word) address space which is separate from the system memory address space. These
registers can only be accessed through the serial wire debug interface, they cannot be accessed by the CPU.
Each Access-Port has a separate 6-bit address space allowing up to 64-word registers per access port. This address
space is separate from the debug port and system CPU address spaces. It can only be accessed by the serial wireinterface through the debug port.
On this device, there is an Access Port. The Memory Access Port is selected by setting APSEL= 00.
Table 2-3: Access Ports
APSEL [7:0]

Access Port

00

Memory Access Port

2–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDebug Port

Debug PortThe Debug Port has four 32-bit read write register locations. These are used to identify and configure the interface
and to select and communicate with a particular Access Port.
Table 2-4: Debug Port Registers
Address [3:2]

Read

Write

DPBANKSEL

00

DPIDR

ABORT

X

01

CTRL/STAT

0x0

DLCR

0x1

TARGET ID

0x2

DLPIDR

0x3

EVENTSTAT

0x4

10

RESEND

SELECTX

11

RDBUFF

TARGETSELX

ADuCM4050 SYS Register Descriptions
System Identification and Debug Enable (SYS) contains the following registers.
Table 2-5: ADuCM4050 SYS Register List
Name

Description

SYS_ADIIDADI Identification

SYS_CHIPID

Chip Identifier

SYS_SWDEN

Serial Wire Debug Enable

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

2–5

ADuCM4050 SYS Register Descriptions

ADI Identification
ADI Cortex device identification.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

0

1

0

0

0

1

0

0

1

0

0

0

0

0

VALUE (R)Reads a fixed value of 0x4144 to indicate
to debuggers that they are connected
to an Analog Devices implemented
Cortex based part

Figure 2-3: SYS_ADIID Register Diagram
Table 2-6: SYS_ADIID Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)

2–6

Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an
Analog Devices implemented Cortex based part.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SYS Register Descriptions

Chip Identifier
Chip identification.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

1

0

1

0

0

0

0

1

0

0

0

0

0

1

PARTID (R)Part identifier

REV (R)
Silicon revision

Figure 2-4: SYS_CHIPID Register Diagram
Table 2-7: SYS_CHIPID Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:4 PARTID

Part identifier.

(R/NW)
3:0 REV(R/NW)

Silicon revision.
0 Silicon revision

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SYS Register Descriptions

Serial Wire Debug Enable
The SYS_SWDEN register is used to enable the Serial Wire Debug (SWD) interface. This register is reset upon aninternal POR or external pin reset. It is not affected by a software reset.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

1

1

0

0

1

0

1

1

1

0

0

0

VALUE (W)To enable SWD interface

Figure 2-5: SYS_SWDEN Register Diagram
Table 2-8: SYS_SWDEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(RX/W)

2–8

To enable SWD interface.
Writing the SYS_SWDEN register with "en" (0x6E65) or "EN" (0x4E45) enables the
SWD interface. Writing the SYS_SWDEN register with "rp" (0x7072) or "RP"(0x5052) disables the SWD interface. Writes of any other value are ignored. The
SYS_SWDEN register cannot be modified once written with "EN" or "RP". This register is reset by a POR or PIN reset, but not software or WDT reset.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceEvents (Interrupts and Exceptions)

3 Events (Interrupts and Exceptions)

The ADuCM4050 MCU supports a number of system exceptions and peripheral interrupts.

Events Features
The ADuCM4050 Events have the following features:• 15 system exceptions with highest priority.
• 72 system interrupts with programmable priority.
• Four external interrupts which can be configured separately to wake up the core from low power modes.

Events Interrupts and Exceptions
Cortex Exceptions
Exceptions 1 to 15 are system exceptions.
Table 3-1: System Exceptions
Exception
Number

IRQ
NumberException TypePriority

Description

1

−

Reset

-3 (highest)

Any reset

2

-14

NMI

-2

Non-maskable interrupt connected to a combination of (logical OR) of VREG under or VBAT (under 1.8 V)

3-13

Hard fault-1

All fault conditions, if the corresponding fault handler is notenabled

4-12

MemManagement fault

Programmable

Memory management fault; access to illegal locations

5-11

Bus fault

Programmable

Prefetch fault, memory access fault, and other address/ memory related faults

6-10

Usage fault

Programmable

Exceptions such as undefined instruction executed or illegal
state transition attempt

7 to 10−

Reserved

Not applicable

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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Events Interrupts and Exceptions

Table 3-1: System Exceptions (Continued)
Exception
Number

IRQ
NumberException TypePriority

Description

11-5

SVCALL

Programmable

System service call with SVC instruction

12-4

Debug monitor

Programmable

Debug monitor (breakpoint, watchpoint, or external debug
requests)

13−

Reserved

Not applicable

14-2

PENDSV

Programmable

Pendable request for system service

15-1

SYSTICK

Programmable

System tick timer

Nested Vectored Interrupt Controller
Interrupts are controlled by the Nested Vectored Interrupt Controller (NVIC), and eight levels of priority are available. Only a limited number of interrupts can wake up the device from hibernate mode. When the device is woken
up from Flexi, hibernate, or shutdown modes, it always returns to active mode.
Table 3-2: Interrupt Sources
Exception
NumberIRQ
VectorNumberWake-up From
Flexi

Hibernate

Shutdown

160Real Time Clock 1/Wakeup Timer/Hibernate
RTC/ LFXTAL Clock Failure

Yes

Yes

No

17

1

External Interrupt 0

Yes

Yes

Yes

18

2

External Interrupt 1

Yes

Yes

Yes

19

3

External Interrupt 2

Yes

Yes

Yes

20

4

External Interrupt 3/ UART0_RX_Wakeup

Yes

Yes

No

21

5

Watchdog Timer

Yes

No

No

22

6

VREG Over

Yes

No

No

23

7

Battery Voltage Range

Yes

Yes

No

24

8

Real Time Clock 0

Yes

Yes

Yes

25

9

GPIO IntA

Yes

No

No

26

10

GPIO IntB

Yes

No

No

27

11

General Purpose Timer 0

Yes

No

No

28

12

General Purpose Timer 1

Yes

No

No

29

13

Flash Controller

Yes

No

No

30

14

UART0

Yes

No

No

31

15

SPI0

Yes*

No

No

3–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceEvents Interrupts and Exceptions

Table 3-2: Interrupt Sources (Continued)
Exception
NumberIRQ
VectorNumberWake-up From
Flexi

Hibernate

Shutdown

32

16

SPI2

Yes*

No

No

33

17

I2C0 Slave

Yes*

No

No

34

18

I2C0 Master

Yes*

No

No

35

19

DMA Error

Yes

No

No

36

20

DMA Channel 0 Done

Yes

No

No

37

21

DMA Channel 1 Done

Yes

No

No

38

22

DMA Channel 2 Done

Yes

No

No

39

23

DMA Channel 3 Done

Yes

No

No

40

24

DMA Channel 4 Done

Yes

No

No

41

25

DMA Channel 5 Done

Yes

No

No

42

26

DMA Channel 6 Done

Yes

No

No

43

27

DMA Channel 7 Done

Yes

No

No

44

28

DMA Channel 8 Done

Yes

No

No

45

29

DMA Channel 9 Done

Yes

No

No

46

30

DMA Channel 10 Done

Yes

No

No

47

31

DMA Channel 11 Done

Yes

No

No

48

32

DMA Channel 12 Done

Yes

No

No

49

33

DMA Channel 13 Done

Yes

No

No

50

34

DMA Channel 14 Done

Yes

No

No

51

35

DMA Channel 15 Done

Yes

No

No

52

36

SPORT0A

Yes

No

No

53

37

SPORT0B

Yes

No

No

54

38

Crypto

Yes

No

No

55

39

DMA Channel 24 Done

Yes

No

No

56

40

General Purpose Timer 2

Yes

No

No

57

41

Crystal Oscillator

Yes

No

No

58

42

SPI1

Yes

No

No

59

43

PLL

Yes

No

No

60

44

Random Number Generator

Yes

No

No

61

45

Beeper

Yes

No

No

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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Events Interrupts and Exceptions

Table 3-2: Interrupt Sources (Continued)
Exception
NumberIRQ
VectorNumberWake-up From
Flexi

Hibernate

Shutdown

62

46

ADC

Yes

No

No

63-71

47-55

Reserved

-

-

-

72

56

DMA Channel 16 Done

Yes

No

No

73

57

DMA Channel 17 Done

Yes

No

No

74

58

DMA Channel 18 Done

Yes

No

No

75

59

DMA Channel 19 Done

Yes

No

No

76

60

DMA Channel 20 Done

Yes

No

No

77

61

DMA Channel 21 Done

Yes

No

No

78

62

DMA Channel 22 Done

Yes

No

No

79

63

DMA Channel 23 Done

Yes

No

No

80

64

Reserved

Yes

No

No

81

65

Reserved

Yes

No

No

82

66

UART1

Yes

No

No

83

67

DMA Channel 25 Done

Yes

No

No

84

68

DMA Channel 26 Done

Yes

No

No

85

69

Timer RGB

Yes

No

No

86

70

Reserved

Yes

No

No

87

71

Root Clock Failure

Yes

No

No

* Corresponding PCLK is required to generate the interrupt.
Internally, the highest user-programmable priority (0) is treated as the fourth priority, after a reset, NMI, and a hardfault. Note that 0 is the default priority for all programmable priorities.
If the same priority level is assigned to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the MCU activates them. For example, if both SPI0 and SPI1 are Priority Level
1, SPI0 has higher priority.
For more information on the exceptions and interrupts, refer to Chapter 5 (Exceptions) and Chapter 8 (Nested Vectored Interrupt Controller) in the ARM Cortex-M4F Technical Reference Manual.

Handling Interrupt Registers
In the Interrupt Service Routine (ISR) for any interrupt source, the first action usually taken is clearing of the interrupt source. In case of write-1-to-clear interrupts, the interrupt status register should be written to clear the interrupt
source. Due to internal delays in the bus-matrix, this write may be delayed before it reaches the destination. Meanwhile, the ISR execution might have been completed and there is a possibility of mistaking the previous interrupt for
3–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceEvents Interrupts and Exceptions

a second one. Therefore, it is always recommended to ensure that the interrupt source has been cleared before exiting the ISR. This can be done by reading the interrupt status again at the end of the ISR.

External Interrupt Configuration
Four external interrupts are implemented, identified as SYS_WAKEx (x = 0, 1, 2, 3). These external interrupts canbe separately configured to detect any combination of the following types of events:• Rising edge: The logic detects a transition from low to high and generates a pulse. Only one pulse is sent to theCortex-M4F per rising edge.
• Falling edge: The logic detects a transition from high to low and generates a pulse. Only one pulse is sent to theCortex-M4F per falling edge.
• Rising or falling edge: The logic detects a transition from low to high or high to low and generates a pulse.
Only one pulse is sent to the Cortex-M4F per edge.
• High level: The logic detects a high level. The appropriate interrupt is asserted and sent to the Cortex-M4F.
The interrupt line is held asserted until the external source deasserts. The high level needs to be maintained for
one core clock cycle minimum to be detected.
• Low level: The logic detects a low level. The appropriate interrupt is asserted and sent to the Cortex-M4F. Theinterrupt line is held asserted until the external source deasserts. The low level needs to be maintained a minimum of one core clock cycle to be detected.
The external interrupt detection unit block is always on and allows external interrupt to wake up the device when inhibernate mode.
Apart from the four external interrupts, activity (any combination of events listed above) on the UART0_RX pin
can also be configured to wake up the device from Flexi or hibernate modes.
Interrupt No. 4 is assigned to both External Interrupt 3 and UART0_RX pin. Both pins can be configured to generate Interrupt No.4. The XINT_CFG0.UART_RX_EN bit must be set to enable UART0_RX pin based wake-up.
XINT_EXT_STAT.STAT_UART_RXWKUP bit is set whenever Interrupt No. 4 is asserted due to an event on the
UART0_RX pin.
NOTE: To use the external interrupt on the corresponding pads, the pads must be configured as GPIOs and thecorresponding GPIO input enable must be set high. For example, when using the pad P0_15 as external interrupt,
set GP0CON[31:30] to 2'b00 and GP0IE[15] to 1'b1.

ADuCM4050 XINT Register Descriptions
External interrupt configuration (XINT) contains the following registers.
Table 3-3: ADuCM4050 XINT Register List
Name

Description

XINT_CFG0

External Interrupt Configuration

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

3–5

ADuCM4050 XINT Register Descriptions

Table 3-3: ADuCM4050 XINT Register List (Continued)
Name

Description

XINT_CLR

External Interrupt Clear

XINT_EXT_STAT

External Wakeup Interrupt Status

XINT_NMICLR

Non-maskable Interrupt Clear

3–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 XINT Register Descriptions

External Interrupt Configuration
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IRQ3EN (R/W)
External Interrupt 3 Enable

IRQ0MDE (R/W)
External Interrupt 0 Mode Registers

IRQ3MDE (R/W)
External Interrupt 3 Mode Registers

IRQ0EN (R/W)
External Interrupt 0 Enable

IRQ2EN (R/W)
External Interrupt 2 Enable

IRQ1MDE (R/W)
External Interrupt 1 Mode Registers

IRQ2MDE (R/W)
External Interrupt 2 Mode Registers

IRQ1EN (R/W)
External Interrupt 1 Enable

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

UART_RX_MDE (R/W)
External Interrupt Using UART_RX Wakeup
Mode Registers

0

0

0

0

0

0

1

0

0

0

0

0
UART_RX_EN (R/W)
External Interrupt Using UART_RX Enable
Bit

Figure 3-1: XINT_CFG0 Register Diagram
Table 3-4: XINT_CFG0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
23:21 UART_RX_MDE(R/W)

External Interrupt Using UART_RX Wakeup Mode Registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)

20 UART_RX_EN(R/W)

External Interrupt Using UART_RX Enable Bit.
This bit enables 'UART_RX' pin to generate interrupt on interrupt (IRQ) number 4.
Refer to the Interrupt Sources table in Events (Interrupt and Exceptions) chapter.
Note: UART RX interrupt is ORed with external interrupt 3. Both interrupts can beseparately configured to generate interrupt on IRQ number 4. To distinguish the causeof the interrupt on IRQ number 4, use the XINT_EXT_STAT register
0 UART_RX wakeup interrupt is disabled
1 UART_RX wakeup interrupt is enabled

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 XINT Register Descriptions

Table 3-4: XINT_CFG0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
15 IRQ3EN(R/W)

External Interrupt 3 Enable.
0 External Interrupt 3 disabled
1 External Interrupt 3 enabled

14:12 IRQ3MDE(R/W)

External Interrupt 3 Mode Registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)

11 IRQ2EN(R/W)

External Interrupt 2 Enable.
0 External Interrupt 2 disabled
1 External Interrupt 2 enabled

10:8 IRQ2MDE(R/W)

External Interrupt 2 Mode Registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)

7 IRQ1EN(R/W)

External Interrupt 1 Enable.
0 External Interrupt 0 disabled
1 External Interrupt 0 enabled

6:4 IRQ1MDE(R/W)

External Interrupt 1 Mode Registers.
0 Rising edge
1 Falling edge

3–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 XINT Register Descriptions

Table 3-4: XINT_CFG0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
3 IRQ0EN(R/W)

External Interrupt 0 Enable.
0 External Interrupt 0 disabled
1 External Interrupt 0 enabled

2:0 IRQ0MDE(R/W)

External Interrupt 0 Mode Registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

3–9

ADuCM4050 XINT Register Descriptions

External Interrupt Clear
This register has W1C bits that are used to clear the corresponding EXT_STAT bits
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

UART_RX_CLR (R/W)
External Interrupt Clear for UART_RX
WAKEUP Interrupt

IRQ0 (R/W)
External Interrupt 0
IRQ1 (R/W)
External Interrupt 1

IRQ3 (R/W)
External Interrupt 3
IRQ2 (R/W)
External Interrupt 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 3-2: XINT_CLR Register Diagram
Table 3-5: XINT_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5 UART_RX_CLR(R/W)
3 IRQ3(R/W)
2 IRQ2(R/W)
1 IRQ1(R/W)
0 IRQ0(R/W)

3–10

External Interrupt Clear for UART_RX WAKEUP Interrupt.
Set to 1 to clear an interrupt STATUS flag. Cleared automatically by hardware.
External Interrupt 3.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External Interrupt 2.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External Interrupt 1.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External Interrupt 0.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 XINT Register Descriptions

External Wakeup Interrupt Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

STAT_UART_RXWKUP (R)Interrupt Status Bit for UART RX WAKEUP
Interrupt

STAT_EXTINT0 (R)Interrupt Status Bit for External Interrupt 0
STAT_EXTINT1 (R)Interrupt Status Bit for External Interrupt 1

STAT_EXTINT3 (R)Interrupt Status Bit for External Interrupt 3
STAT_EXTINT2 (R)Interrupt Status Bit for External Interrupt 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 3-3: XINT_EXT_STAT Register Diagram
Table 3-6: XINT_EXT_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5 STAT_UART_RXWKUP(R/NW)

3 STAT_EXTINT3(R/NW)

2 STAT_EXTINT2(R/NW)

1 STAT_EXTINT1(R/NW)

Interrupt Status Bit for UART RX WAKEUP Interrupt.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 4 as mentioned
in System Interrupts and exceptions chapter 0 - UART_RX Wakeup did not generate
the interrupt 1 - UART_RX Wakeup generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.UART_RX_CLR bit Note : Interrupt No. 4 is shared with External Interrupt 3, UART RX Wakeup.
Interrupt Status Bit for External Interrupt 3.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 4 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 3 did not generate
the interrupt 1 - External interrupt 3 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ3 bit
Interrupt Status Bit for External Interrupt 2.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 3 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 2 did not generate
the interrupt 1 - External interrupt 2 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ2 bit
Interrupt Status Bit for External Interrupt 1.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 2 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 1 did not generate
the interrupt 1 - External interrupt 1 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ1 bit

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

3–11

ADuCM4050 XINT Register Descriptions

Table 3-6: XINT_EXT_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 STAT_EXTINT0(R/NW)

3–12

Interrupt Status Bit for External Interrupt 0.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 1 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 0 did not generate
the interrupt 1 - External interrupt 0 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ0 bit

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 XINT Register Descriptions

Non-maskable Interrupt Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CLR (R/W)
NMI Clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 3-4: XINT_NMICLR Register Diagram
Table 3-7: XINT_NMICLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
0 CLR
(R/W)

NMI Clear.
Set to 1 to clear an interrupt status flag when the NMI interrupt is set. Cleared automatically by hardware.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

3–13Power Management (PMG)

4 Power Management (PMG)

This chapter provides an overview of the functional architecture and implementation of power management andpower modes used in the ADuCM4050 MCU.

Power Management Features
The features include:• High efficiency buck converter to reduce power in active and flexi modes.
• Customized clock gating for active modes.
• Power gating to reduce leakage in sleep modes.
• Voltage monitoring.
• Flexible sleep modes with smart peripherals.
• Deep sleep modes with and without retention.

Power Management Functional Description
This section provides information on the power management function of the ADuCM4050 MCU.
The system has two voltage domains:• VBAT: Input voltage with a range from 1.74 V - 3.6 V• VREG: Internally generated voltage with a range of 1.2 V ± 10%

Power-up Sequence
The system powers up when the battery voltage is more than 1.6 V. The buck converter is disabled during the power
up sequence, so the system starts in LDO mode. The user can switch to Buck mode if required. The buck provides
the lowest dynamic power at the expense of five extra pins, two flying capacitors and a load capacitor. User cantradeoff between external components and active power. The buck can be enabled by writing to bit 0 of the
PMG_CTL1 register.

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4–1

Operating Modes

Operating Modes
The ADuCM4050 MCU supports the following power modes:• Active Mode: Cortex-M4F executes from flash/SRAM.
• Flexi Mode: Cortex-M4F is disabled. User selects the peripherals to be enabled: DMA/SPI, DMA/I2C and soon.
• Hibernate Mode: System power gated. 16 KB of SRAM is always retained. In addition to this, up to 108 KB
SRAM can be selected and retained.
• Shutdown Mode: Non-retain state. Pins retain values.

Active ModeIn this mode, the device is up and running. The Cortex-M4F executes instructions from flash and/or SRAM.
The system is not only clock gated using automatic clock gating techniques, but also clock gates can be selectedusing the CLKG_CLK_CTL5 register. Most of the peripherals are automatically clock gated when disabled. The
clock runs only when the peripheral is enabled. Exceptions to this are I2C, UART, Timer_RGB, and general purpose
timer. These blocks must be manually clock gated using the CLKG_CLK_CTL5 register.
Writing 1 to the bit in the CLKG_CLK_CTL5 register stops the corresponding clock to the peripheral. After theclock stops, if the user/software accesses any register in that peripheral, the clock is auto enabled. Also, writing 0 to
the bit in the CLKG_CLK_CTL5 register enables the corresponding clock to the peripheral.
The CLKG_CLK_CTL5.PERCLKOFF bit can be used to disable all peripherals. This is useful when the CortexM4F processor is executing exclusively from SRAM or Flash, and no other peripherals are required.
When the CLKG_CLK_CTL5.PERCLKOFF bit is 1, the clock is gated. The clock is reenabled if the MCU or
DMA is accessing the register of any gated peripherals.
The part powers up with the LDO. Buck can be enabled to save power consumption, by writing to the PMG_CTL1
register.
HPBUCK Load Mode Selection
Set the PMG_CTL1.HPBUCK_LD_MODE bit as per the HPBUCK Load Mode Selection table. Set this bit at thestart of the software execution flow.
Table 4-1: HPBUCK Load Mode Selection
System Clock Frequency

HPBUCK Load Mode

≤ 26 MHz0> 26 MHz1

4–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceOperating Modes

Flexi ModeIn this mode, the Cortex-M4F is always disabled. The core can be switched to this mode by setting the
PMG_PWRMOD.MODE bit to 0 and executing WFI instruction.
Writing 1 to the bit in the CLKG_CLK_CTL5 register stops the corresponding clock to the peripheral.
If the user/software accesses any register in that peripheral after the clock stops, the clock is auto enabled. Also, writing 0 to the bit in CLKG_CLK_CTL5 register enables the corresponding clock to the peripheral.
The clock for all other blocks in the system runs if the peripheral is enabled.
This mode adds flexibility to the user to determine the blocks that are enabled while the Cortex is sleeping. For
example, the user can perform DMA transactions through SPI or I2C, or ADC conversions to DMA without MCU
interaction. This mode can be used to reduce active power when an activity is expected to complete (for example,
reading a certain number of bytes from a sensor, and so on) before the MCU can be woken up for processing thedata.
Low Power Mode in Flexi
If serial communication peripherals such as SPORT and UART are not required, the current consumption in flexi
can be reduced using a low power mode. This low power mode requires the system clock (Root Clk) to source fromthe HFOSC (clock setting).
The low power mode entry sequence is as follows:
1. Program the CLKG_CLK_CTL2.HFOSCDIVCLKSEL bits such that divided HFOSC frequency is less than
1.2 MHz.
2. Enable the PMG_CTL1.HPBUCK_LOWPWR_MODE bit.
If PMG_CTL1.HPBUCK_LOWPWR_MODE bit is set, the load current is minimal.
Therefore, only the following peripherals can be operational in this mode.
1. GPTs, where source for GPT blocks must be low frequency clocks
2. Beeper
3. GPIO
4. External interrupt sourceThis feature can be used in conjunction with fast wake-up from Flexi mode. In this case, the
CLKG_CLK_CTL2.HFOSCAUTODIV_EN bit can be set to 1 to enable the fast wake-up. On wake up from Flexi
mode, the HFOSC divided clock automatically reverts to 26 MHz. To resume normal operation after wake up from
Flexi mode, clear the PMG_CTL1.HPBUCK_LOWPWR_MODE bit.
Wake-up time from Flexi to active is one clock cycle of the divided HFOSC clock.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–3

Operating Modes

Hibernate ModeIn this mode, the Cortex-M4F and all digital peripherals are off. Up to 124KB of total 128KB SRAM can be retained in hibernate.
User can select:
1. The SRAM to be retained using the control bits. These control bits can be used to retain three 32 KB regions
and one 12 KB region. This is in addition to the 16 KB of SRAM always retained in hibernate mode.
The SRAM retention control bits are as follows:
PMG_SRAMRET.RET1: Enable retention of Bank1 (12 KB)
PMG_SRAMRET.RET2: Enable retention of Bank3 and Bank4 (32 KB)
PMG_SRAMRET.RET3: Enable retention of Bank5 (32 KB)
PMG_SRAMRET.RET4: Enable retention of Bank6 and Bank7 (32 KB)
2. The RTC with a 32 kHz crystal or internal 32 kHz oscillator. The crystal provides a higher accuracy clock.
However, the power consumption would be higher.
3. Enable and configure battery monitoring in hibernate mode.
4. The regulated 1.2 V supply is always monitored to guarantee data is not corrupted by the supply going below
the minimum retention voltage. If the regulated supply falls below a fixed threshold, the chip resets before any
data is corrupted. Though the regulated supply is always monitored, there is an option to also monitor thebattery in hibernate mode. This is done by using the PMG_PWRMOD register.
Memory Configuration
While entering into hibernate mode, user can retain 124 KB out of 128 KB. This is controlled by the
PMG_SRAMRET register.
The lowest 16 KB is always retained in hibernate mode irrespective of the configuration set in the PMG_SRAMRET
register.
For more information, refer to SRAM Region.
SRAM Hibernate Load Mode
Select the PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE and the
PMG_TRIM.HIBERNATE_LOAD_MODE bits as per the following table.
Wait for 3 ms after setting the PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE bit to 0, before entering into
hibernate mode.

4–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceOperating Modes

Table 4-2: SRAM Load Mode Selection
Size of SRAM Retained in Hibernate

HIBERNATE_SRAM_LOAD_MODE

HIBERNATE_LOAD_MODE

16 KB

1

7

28 KB

1

7

48 KB

1

7

60 KB

1

7

80 KB

0

0

92 KB

0

0

112 KB00

124 KB

00

Hibernate Mode Transitions with PLL as Source
The PMU monitors power-down and power-up requests and enables seamless switching of the Root clock mux.
This ensures a safe hibernate mode entry and exit.
The PMU automatically performs the following operations during hibernate mode transitions.
Hibernate Mode Entry:
1. Switches Root clock mux to HFOSC, when power-down request is detected.
2. Disables the PLL and enters into power down.
Hibernate Mode Exit:
1. Enables the PLL, when power-up request is detected.
If the PLL input is set to HFXTAL, PLL is enabled after HFXTAL lock is detected.
2. Waits for PLL lock.
3. Switches Root clock mux to PLL clock.
NOTE: On wake up from hibernate, core starts executing on HFOSC. Once PLL is locked, the PMU switches root
clock mux to PLL clock.

Shutdown Mode
This is the deepest sleep mode where all the digital and analog circuits are powered down except for a wake up controller and a fail safe. These circuits are powered from VBAT. The LDO is off, so the 1.2 V region is shutdown.
The state of the digital core is not retained and the SRAM memory content is not preserved. When the part wakes
up from shutdown mode, it follows the POR sequence and the code execution starts from the beginning. The user

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–5

Programming Sequence

can read the PMG_SHDN_STAT register to see the wake up source from this mode. There are four possible wake-up
sources:• External interrupts, limited to three external interrupts to save power.
• External reset.
• Battery falling below 1.6 V.
• RTC Timer (if the option is enabled). Only available with the crystal oscillator. The LF oscillator is off during
shutdown.
During this mode, the state of the pads and the wakeup interrupt configuration are preserved.
The configuration of the pads is preserved, but it is also locked after waking up from shutdown mode. The userneeds to unlock the state of the PADS by writing the value 0x58FA to register PMG_TST_CLR_LATCH_GPIOS.
It is recommended to perform the write inside the ISR routine.
The user can only go to shutdown with the HFOSC. It will not go to shutdown mode if running from PLL, external clock or HF XTAL. The user needs to switch to HFOSC before going to shutdown mode.
There is also a scratch pad available for the user during shutdown mode. The scratch pad consists of a 32-bit register.
The intention of the scratch pad is for the user to save some data on 3 V before all the information is lost in shutdown mode.
The user can write to the PMG_TST_SCRPAD_IMG register at any time. This is a read-write register. The information saved in this register is copied to an area in VBAT before going to shutdown mode. This information in VBAT
can be accessed through PMG_TST_SCRPAD_3V_RD register, which is a read-only register.
NOTE: Switch to HFOSC before going to shutdown mode if running from PLL, external clock, or HF XTAL.
For more information, refer to Configuring Shutdown Mode.

Programming Sequence
Configuring Hibernate Mode
This is the lowest power-down mode with state retention. Digital information and SRAM 0 are always retained, but
retaining SRAM 1, SRAM3 to SRAM7 is optional. Refer to SRAM Region.
It is also optional to monitor VBAT in hibernate mode. The PMG_CTL1 register provides information about the
VBAT state. Interrupts can be optionally generated using this control register.
The following steps describe the sequence to enter hibernate mode:
1. Select PMG_PWRMOD_MODE = 2.
2. Select SLEEPDEEP bit in the Cortex-M4F.
3. Enable the desired wake-up interrupt.

4–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProgramming Sequence

4. If battery monitor is required, set the PMG_PWRMOD.MONVBATN bit to 0.
5. Execute the WFI/WFE instruction.
Now, the chip is in hibernate mode.
When a wake-up interrupt arrives, the part exits hibernate mode and serves the interrupt routine.

Configuring Shutdown Mode
This is the deepest power-down mode. State information is not retained in this mode, and the chip restarts fromreset after waking up.
The wake-up sources available are external reset, external interrupts limited only to three and RTC0 with the crystal
oscillator if the application needs periodic wake-up. The internal low frequency oscillator is disabled during thismode. The only clock available in this mode is the low frequency crystal (optional).
The following steps describe the sequence to enter this mode:
1. Select PMG_PWRMOD_MODE = 3.
2. Set the SLEEPDEEP bit in the Cortex-M4F.
3. Enable the desired wake up interrupt.
4. If a wake up from RTC0 is required, enable LFXTAL.
5. Execute the WFI instruction.
Now, the chip is in shutdown mode.
NOTE: Switch to HFOSC before going to shutdown mode if running from PLL, external clock, or HFXTAL.
When a wake-up interrupt arrives, the device exits shutdown mode and wakes up to a POR scenario.
The sequence is as follows:
1. Read the PMG_SHDN_STAT register.
2. Enable the interrupt routine that caused the wake-up event.
3. The chip jumps to the enabled ISR and served the interrupt routine.
NOTE: Write PMG_PWRMOD back to 0 in the ISR after waking up from shutdown mode.

Wake-up Sequence
Wake-up is triggered by an interrupt or a reset. The sequence for the wake-up is different depending on the powermode.
If the wake-up is triggered by an interrupt, then the system first executes the interrupt routine.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–7

Fast Wake-up from Shutdown Mode

The wake-up sequence is different for shutdown mode. The information is not retained, and therefore the system
will always start from reset state after waking up. The interrupt triggering the wake-up sequence remains pending in
the Cortex-M4F until interrupt routine is enabled at the restart of the code. The status register can be read after
waking up from shutdown and the interrupt routine can be enabled.
For more information about interrupts and wake-up sources for power modes, refer to Table 3-2 Interrupt Sources.

Fast Wake-up from Shutdown ModeIn this mode, the device wakes up faster than the shutdown mode.
The wake-up time is period between the wake-up interrupt assertion and start of execution of first instruction in theuser code.
This feature is enabled by setting bit 0 of the PMG_FAST_SHT_WAKEUP register. This register field content isretained in all power modes. This register field is cleared when the PMG_RST_STAT.EXTRST or
PMG_RST_STAT.PORSRC bit is reset.

Monitor Voltage Control
Voltage supervisory circuits are enabled at all times to guarantee that the VBAT and the regulated supply are always
within operating levels. The circuit monitoring these supplies is called Power Supply Monitor (PSM).
The following are the main features of PSM in active mode:• Monitors VBAT voltage• Generates an alarm to the MCU if VBAT supply is below 1.83 V• Generates a reset to the chip if VBAT supply is below 1.6 V• Monitors the state of the VBAT source.
When the PMG_CTL1.HPBUCK_LD_MODE bit is low, it generates interrupts as per the following voltage ranges:
VBAT between 3.6 V - 2.8 V
VBAT between 2.8 V - 2.19 V. Generates interrupt BR1
VBAT between 2.19 V - 1.6 V. Generates interrupt BR2
When the PMG_CTL1.HPBUCK_LD_MODE bit is high, it generates interrupts as per the following voltage ranges:
VBAT between 3.6 V - 2.93 V
VBAT between 2.93 V - 2.39 V. Generates interrupt BR1
VBAT between 2.39 V - 1.6 V. Generates interrupt BR2
4–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceMonitor Voltage Control• Monitors regulated supply• Generates an interrupt if the regulated supply is above 1.32 V (over voltage)• Generates an interrupt if the regulated supply is below 1.1 V (under voltage)• Generates a reset if the regulated supply is below 1.08 V
The following are the main features of PSM in hibernate mode:• Monitors VBAT voltage• Generates an alarm to the MCU if supply is below 1.83 V (optional)• Generates a reset to the chip if supply is below 1.6 V (optional)• Monitors the state of the VBAT source (optional)
When the PMG_CTL1.HPBUCK_LD_MODE bit is low, it generates interrupts as per the following voltage ranges:
VBAT between 3.6 V - 2.8 V
VBAT between 2.8 V - 2.19 V. Generates interrupt BR1
VBAT between 2.19 V - 1.6 V. Generates interrupt BR2
When the PMG_CTL1.HPBUCK_LD_MODE bit is high, it generates interrupts as per the following voltage ranges:
VBAT between 3.6 V - 2.93 V
VBAT between 2.93 V - 2.39 V. Generates interrupt BR1
VBAT between 2.39 V - 1.6 V. Generates interrupt BR2• Monitors regulated supply• Generates a reset if the regulated supply is below 1.08 V
The VBAT and VREG supply monitors are shown below.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–9

Retention Register Details

2.93/2.8 V 2.39/2.19 V 1.8V

1.6V

Figure 4-1: VBAT Supply Monitor
VREG
1V

0V

1.1V

1.0V

1.0V 1.1V

VREG INT

VBAT RESET

Figure 4-2: VREG Supply Monitor

Retention Register Details
The PMG registers which are retained in hibernate mode and shutdown mode are mentioned in the following table.
Table 4-3: PMG Retention Register Details
Register Address

Register Name

Retention Status
Hibernate mode

Shutdown mode

0x4004C000

PMG_IEN

Yes

No

0x4004C004

PMG_PSM_STAT

Yes

No

0x4004C008

PMG_PWRMOD

Yes

No

0x4004C00C

PMG_PWRKEY

Yes

No

4–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG Register Descriptions

Table 4-3: PMG Retention Register Details (Continued)
Register Address

Register Name

Retention Status
Hibernate mode

Shutdown mode

0x4004C010

PMG_SHDN_STAT

Yes

No

0x4004C014

PMG_SRAMRET

Yes

No

0x4004C040

PMG_RST_STAT

Yes

No

0x4004C044

PMG_CTL1

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.INSTREN

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.PENBNK0

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.PENBNK1

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.PENBNK2

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.PENBNK3

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.PENBNK4

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.PENBNK5

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.PENBNK6

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.PENBNK7

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.AUTOINIT

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.BNK1EN

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.BNK2EN

Yes

No

0x4004C260

PMG_TST_SRAM_CTL.BNK7EN

Yes

No

0x4004C270

PMG_SCRPAD_3V_RD

Yes

Yes

0x4004C274

PMG_FAST_SHT_WAKEUP

Yes

Yes

ADuCM4050 PMG Register Descriptions
Power Management Registers (PMG) contains the following registers.
Table 4-4: ADuCM4050 PMG Register List
Name

Description

PMG_CTL1

HPBUCK Control

PMG_IENPower Supply Monitor Interrupt Enable

PMG_TRIM

Trimming Bits

PMG_PSM_STAT

Power Supply Monitor Status

PMG_PWRKEY

Key Protection for PMG_PWRMOD and PMG_SRAMRETPMG_PWRMOD

Power Mode Register

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–11

ADuCM4050 PMG Register Descriptions

Table 4-4: ADuCM4050 PMG Register List (Continued)
Name

Description

PMG_RST_STAT

Reset Status

PMG_SHDN_STAT

Shutdown Status Register

PMG_SRAMRET

Control for Retention SRAM in Hibernate Mode

4–12

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG Register Descriptions

HPBUCK Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

HPBUCK_LOWPWR_MODE (R/W)
HP Buck Low Power Mode

HPBUCKEN (R/W)
Enable HP Buck

HPBUCK_LD_MODE (R/W)
HP Buck Load Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

Figure 4-3: PMG_CTL1 Register Diagram
Table 4-5: PMG_CTL1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
2 HPBUCK_LOWPWR_M(R/W) ODEHP Buck Low Power Mode.
This bit can be used to choose Low power mode for the HPBUCK. The HPBUCKLow Power mode can be selected, when the chip is in Flexi power mode and low power
modules such as Timer, Beeper only are enabled.
0 HPBUCK Low power mode is disabled
1 HPBUCK Low power mode is enabled

1 HPBUCK_LD_MODE(R/W)

HP Buck Load Mode.
Used to choose the loading capability of the HPBUCK. User can select the HPBUCK
load mode for different use cases.
0 HPBUCK Low load mode is enabled This bit shall be
set to 0, if the maximum system clock (HCLK) frequency is 26 MHz.
1 HPBUCK High load mode is enabled This bit shall be
set to 1, if the system clock (HCLK) frequency is greaterthan 26 MHz.

0 HPBUCKEN

Enable HP Buck.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–13

ADuCM4050 PMG Register Descriptions

Power Supply Monitor Interrupt Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IENBAT (R/W)
Interrupt Enable for VBAT Range

VBAT (R/W)
Enable Interrupt for VBATRANGEBAT (R/W)
Battery Monitor Range

VREGUNDR (R/W)
Enable Interrupt When VREG Under
Voltage (Below 1V)

VREGOVR (R/W)
Enable Interrupt When VREG Over
Voltage (Above 1.32V)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4-4: PMG_IEN Register Diagram
Table 4-6: PMG_IEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
10 IENBAT(R/W)

Interrupt Enable for VBAT Range.
Set this bit if interrupt needs to be generated for appropriate PMG_IEN.RANGEBAT.
Configure the appropriate PMG_IEN.RANGEBAT for which interrupt to be generated and then set this bit. An Interrupt is generated if VBAT falls in the
PMG_IEN.RANGEBAT.
For example, if battery is good, to monitor the battery, configure in
PMG_PSM_STAT.RANGE2 or PMG_PSM_STAT.RANGE3, clear all
PMG_PSM_STAT flags and then enable this interrupt. Otherwise,
PMG_PSM_STAT.RANGE1 of battery will keep firing the interrupt.

4–14

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG Register Descriptions

Table 4-6: PMG_IEN Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9:8 RANGEBAT(R/W)

Battery Monitor Range.
Configure appropriate PMG_IEN.RANGEBAT for which interrupt has to be generated
0 Configure to generate interrupt if VBAT in Region1
VBAT Range1 varies with respect to the
PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT > 2.80 V, when
PMG_CTL1.HPBUCK_LD_MODE=0.
VBAT > 2.93 V, when
PMG_CTL1.HPBUCK_LD_MODE=1.
1 Configure to generate interrupt if VBAT in Region2
VBAT Range2 varies with respect to the
PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT is between 2.8 V and 2.19 V, when
PMG_CTL1.HPBUCK_LD_MODE=0.
VBAT is between 2.93 V and 2.39 V, when
PMG_CTL1.HPBUCK_LD_MODE=1.
2 Configure to generate interrupt if VBAT in Region3
VBAT Range3 varies with respect to the
PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT is between 2.19 V and 1.6 V, when
PMG_CTL1.HPBUCK_LD_MODE=0.
VBAT is between 2.39 V and 1.6 V, when
PMG_CTL1.HPBUCK_LD_MODE=1.
3 NA

2 VREGOVR

Enable Interrupt When VREG Over Voltage (Above 1.32V).

(R/W)
1 VREGUNDR(R/W)
0 VBAT(R/W)

Enable Interrupt When VREG Under Voltage (Below 1V).
If enabled, the irq connects to NMI (non-maskable interrupt)
Enable Interrupt for VBAT.
If enabled, the irq connects to NMI (non-maskable interrupt). if enabled, it generates
an interrupt if VBAT < 1.83 V

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–15

ADuCM4050 PMG Register Descriptions

Trimming Bits
Trimming bits for power management.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

0

0

1

0

0

1

0

0

0

1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

1

0

1

0

1

0

0

0

1

0

1

0

hibernate_load_mode (R/W)
Hibernate Mode Load Mode Control

Figure 4-5: PMG_TRIM Register Diagram
Table 4-7: PMG_TRIM Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:29 HIBER(R/W) NATE_LOAD_MODE

Hibernate Mode Load Mode Control.
Configured in conjunction with the
PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE.
It is not recommended to change this bitfield dynamically between two hibernates as
this would result on a reconfiguration delay. If there is a low hibernate load (SRAM
retained is 60 KB or less), set PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE
and use 3b111 for this bit field.
If there is a high hibernate load (i.e. the SRAM retained is higher than 60 KB), reset
PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE and use 3b000 for this bit
field.
0 High hibernate load
7 Low hibernate load

4–16

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG Register Descriptions

Power Supply Monitor Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RORANGE3 (R)VBAT Range3

VBATUNDR (R/W1C)
Status Bit Indicating an Alarm That
Battery is Below 1.8V

RORANGE2 (R)VBAT Range2

VREGUNDR (R/W1C)
Status Bit for Alarm Indicating VREG
is Below 1V

RORANGE1 (R)VBAT Range1
RANGE3 (R/W1C)
VBAT Range3

VREGOVR (R/W1C)
Status Bit for Alarm Indicating Over
Voltage for VREG

RANGE2 (R/W1C)
VBAT Range2

WICENACK (R)WIC Enable Acknowledge from Cortex
RANGE1 (R/W1C)
VBAT Range1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4-6: PMG_PSM_STAT Register Diagram
Table 4-8: PMG_PSM_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 RORANGE3(R/NW)VBAT Range3.
read-only status bit
0 VBAT NOT in the range specified
1 VBAT in the range specified

14 RORANGE2(R/NW)VBAT Range2.
read-only status bit
0 VBAT NOT in the range specified
1 VBAT in the range specified

13 RORANGE1(R/NW)VBAT Range1.
Read-only status bit.
0 VBAT NOT in the range specified
1 VBAT in the range specified

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–17

ADuCM4050 PMG Register Descriptions

Table 4-8: PMG_PSM_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10 RANGE3(R/W1C)VBAT Range3.
Indicates relevant VBAT range. Generates VBAT range interrupt if
PMG_IEN.IENBAT is set.
Note : The status bit will be set again even after '1' is written (to clear the flag) to theflag, if VBAT falls in the range specified.
VBAT Range3 varies with respect to the PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT Range3 Values:
Between 2.19 V and 1.6 V, when PMG_CTL1.HPBUCK_LD_MODE=0.
Between 2.39 V and 1.6 V, when PMG_CTL1.HPBUCK_LD_MODE=1.
0 VBAT NOT in the range specified
1 VBAT in the range specified

9 RANGE2(R/W1C)VBAT Range2.
Indicates relevant VBAT range. Generates VBAT range interrupt if
PMG_IEN.IENBAT is set.
Note : The status bit will be set again even after 1 is written (to clear the flag) to theflag, if VBAT falls in the range specified.
VBAT Range2 varies with respect to the PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT Range2 Values:
Between 2.80 V and 2.19 V, when PMG_CTL1.HPBUCK_LD_MODE=0.
Between 2.93 V and 2.39 V, when PMG_CTL1.HPBUCK_LD_MODE=1.
0 VBAT NOT in the range specified
1 VBAT in the range specified

8 RANGE1(R/W1C)VBAT Range1.
Indicates relevant VBAT range. Generates VBAT range interrupt if
PMG_IEN.IENBAT is set.
Note : The status bit will be set again even after '1' is written (to clear the flag) to theflag, if VBAT falls in the range specified.
VBAT Range1 varies with respect to the PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT Range1 Values:
VBAT > 2.80 V, when PMG_CTL1.HPBUCK_LD_MODE=0.
VBAT > 2.93 V, when PMG_CTL1.HPBUCK_LD_MODE=1.
0 VBAT NOT in the range specified
1 VBAT in the range specified

4–18

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG Register Descriptions

Table 4-8: PMG_PSM_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
7 WICENACKWIC Enable Acknowledge from Cortex.

(R/NW)
2 VREGOVR(R/W1C)

Status Bit for Alarm Indicating Over Voltage for VREG.
Set if VREG (LDO out) > 1.32 V Generates an interrupt if PMG_IEN.VREGOVR isset.
Note : The status bit will be set again even after '1' is written (to clear the flag) to theflag, if VREG > 1.32 V.

1 VREGUNDR(R/W1C)

Status Bit for Alarm Indicating VREG is Below 1V.
Generates an interrupt if PMG_IEN.VREGUNDR is set. This bit will be set if VREG <1 V.
Note : The status bit will be set again even after '1' is written (to clear the flag) to theflag, if VREG < 1 V.

0 VBATUNDR(R/W1C)

Status Bit Indicating an Alarm That Battery is Below 1.8V.
Generates an interrupt if PMG_IEN.VBAT is set. This bit will be set if VBAT < 1.83
V.
Note : The status bit will be set again even after '1' is written (to clear the flag) to theflag, if VBAT < 1.83 V.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–19

ADuCM4050 PMG Register Descriptions

Key Protection for PMG_PWRMOD and PMG_SRAMRET
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (W)Power Control Key
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4-7: PMG_PWRKEY Register Diagram
Table 4-9: PMG_PWRKEY Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(RX/W)

4–20

Power Control Key.
The PMG_PWRMOD and PMG_SRAMRET registers are key-protected. One write to thekey is necessary to change the value in the PMG_PWRMOD and PMG_SRAMRET registers. Key to be written is 0x4859. These registers should then be written. A write to
any other register on the APB bus before writing to PMG_PWRMOD or
PMG_SRAMRET will return the protection to the lock state.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG Register Descriptions

Power Mode Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

MONVBATN (R/W)
Monitor VBAT During Hibernate Mode

MODE (R/W)
Power Mode Bits

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4-8: PMG_PWRMOD Register Diagram
Table 4-10: PMG_PWRMOD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
3 MONVBATN(R/W)

Monitor VBAT During Hibernate Mode.
Monitors VBAT by Default. VDD Monitoring cannot be disabled.
0 VBAT monitor enabled in PMG block
1 VBAT monitor disabled in PMG block

1:0 MODE(R/W)

Power Mode Bits.
0 Flexi Mode
1 Reserved
2 Hibernate Mode3 Shutdown Mode

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–21

ADuCM4050 PMG Register Descriptions

Reset Status
This register is recommended to be read at the beginning of the user-code to determine the cause of the reset. Default values of this register is unspecified as the cause of reset can be any source.
15 14 13 12 11 10 9

8

7

6

5

0

0

0

0

X X X X X X

0

0

0

0

0

0

4

3

2

1

0

PORSRC (R)Power on Reset Source

POR (R/W)
Power-on Reset

SWRST (R/W)
Software Reset

EXTRST (R/W)
External Reset

WDRST (R/W)
Watchdog Timeout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4-9: PMG_RST_STAT Register Diagram
Table 4-11: PMG_RST_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5:4 PORSRC(R/NW)

Power on Reset Source.
This bit contains additional details after a power-on-reset occurs.
0 POR triggered because VBAT drops below Fail Safe
1 POR trigger because VBAT supply (VBAT < 1.7 V)
2 POR triggered because VDD supply (VDD < 1.08 V)
3 POR triggered because VREG drops below Fail Safe

3 SWRST(R/W)

2 WDRST(R/W)

1 EXTRST
(R/W)

4–22

Software Reset.
Software reset. Set automatically to 1 when the Cortex system reset is generated.
Cleared by writing 1 to any field of the PMG_RST_STAT register. This bit is also
cleared when power-on-reset is triggered
Watchdog Timeout.
Set automatically to 1 when a watchdog timeout occurs. Cleared by writing 1 to any
field of the PMG_RST_STAT register. This bit is also cleared when power-on-reset is
triggered
External Reset.
Set automatically to 1 when an external reset occurs. Cleared by writing 1 to any fieldof the PMG_RST_STAT register. This bit is also cleared when power-on-reset is triggered

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG Register Descriptions

Table 4-11: PMG_RST_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 POR
(R/W)

Power-on Reset.
Set automatically when a power-on reset occurs. Cleared by writing 1 to any field of
the PMG_RST_STAT register.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–23

ADuCM4050 PMG Register Descriptions

Shutdown Status Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RTC (R)Interrupt from RTC

EXTINT0 (R)Interrupt from External Interrupt 0

EXTINT2 (R)Interrupt from External Interrupt 2

EXTINT1 (R)Interrupt from External Interrupt 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4-10: PMG_SHDN_STAT Register Diagram
Table 4-12: PMG_SHDN_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
3 RTC

Interrupt from RTC.

(R/NW)
2 EXTINT2Interrupt from External Interrupt 2.

(R/NW)
1 EXTINT1

Interrupt from External Interrupt 1.

(R/NW)
0 EXTINT0

Interrupt from External Interrupt 0.

(R/NW)

4–24

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG Register Descriptions

Control for Retention SRAM in Hibernate Mode
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RET4 (R/W)
Enable Retention Bank 6 and Bank
7 (32 KB)

RET1 (R/W)
Enable Retention Bank 1 (12 KB)
RET2 (R/W)
Enable Retention Bank 3 and Bank
4 (32 KB)

RET3 (R/W)
Enable Retention Bank 5 (32 KB)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

HIBERNATE_SRAM_LOAD_MODE (R/W)
Hibernate Mode SRAM Load Mode Control

Figure 4-11: PMG_SRAMRET Register Diagram
Table 4-13: PMG_SRAMRET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
23 HIBER(R/W) NATE_SRAM_LOAD_M
ODE
9 RET4Hibernate Mode SRAM Load Mode Control.
Used to configure appropriate load current support in hibernate mode.
Enable Retention Bank 6 and Bank 7 (32 KB).

(R/W)
8 RET3

Enable Retention Bank 5 (32 KB).

(R/W)
1 RET2

Enable Retention Bank 3 and Bank 4 (32 KB).

(R/W)
0 RET1

Enable Retention Bank 1 (12 KB).

(R/W)

ADuCM4050 PMG_TST Register Descriptions
Power Management Registers (PMG_TST) contains the following registers.
Table 4-14: ADuCM4050 PMG_TST Register List
Name

Description

PMG_TST_CLR_LATCH_GPIOS

Clear GPIO After Shutdown Mode

PMG_TST_FAST_SHT_WAKEUP

Fast Shutdown Wake-up Enable

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–25

ADuCM4050 PMG_TST Register Descriptions

Table 4-14: ADuCM4050 PMG_TST Register List (Continued)
Name

Description

PMG_TST_SCRPAD_3V_RD

Scratch Pad Saved in Battery Domain

PMG_TST_SCRPAD_IMG

Scratch Pad ImagePMG_TST_SRAM_CTL

Control for SRAM Parity and Instruction SRAM

PMG_TST_SRAM_INITSTAT

Initialization Status Register

4–26

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG_TST Register Descriptions

Clear GPIO After Shutdown Mode
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (W)
Clear the Latches for GPIOs

Figure 4-12: PMG_TST_CLR_LATCH_GPIOS Register Diagram
Table 4-15: PMG_TST_CLR_LATCH_GPIOS Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(RX/W)

Clear the Latches for GPIOs.
when 0x58FA is written, the GPIO releases the latched values after shutdown mode.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–27

ADuCM4050 PMG_TST Register Descriptions

Fast Shutdown Wake-up Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FAST_SHT_WAKEUP (R/W)
Enables Fast Shutdown Wake-up
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4-13: PMG_TST_FAST_SHT_WAKEUP Register Diagram
Table 4-16: PMG_TST_FAST_SHT_WAKEUP Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
0 FAST_SHT_WAKEUP(R/W)

Enables Fast Shutdown Wake-up.
If enabled, the shut down wake-up time will be reduced to 1 ms from the normal shutdown wake-up time of 75 ms.
This register field content will be retained in all Power modes. This register field will
be cleared to 0 only during External reset or Fail Safe VBAT POR reset. The default
value is 0.
0 Fast shutdown wakeup is disabled
1 Fast shutdown wakeup is enabled

4–28

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG_TST Register Descriptions

Scratch Pad Saved in Battery Domain
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DATA[15:0] (R)Reading the Scratch Pad Stored in ShutdownMode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DATA[31:16] (R)Reading the Scratch Pad Stored in Shutdown
Mode

Figure 4-14: PMG_TST_SCRPAD_3V_RD Register Diagram
Table 4-17: PMG_TST_SCRPAD_3V_RD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 DATA(R/NW)

Reading the Scratch Pad Stored in Shutdown Mode.
Read Only register.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–29

ADuCM4050 PMG_TST Register Descriptions

Scratch Pad Image
Useful in Shutdown mode. The GPIO configuration, OUT registers lose its contents when in shutdown mode. 32bit scratch register can be used to store the GPIO configuration. Note that the bits are not wide enough to store all
GPIO related configuration and output values. User has only few combination of shutdown port configurations.
Therefore, these combination can be remembered by storing an equivalent encoded data in the scratch 32-bit registers. User after reading back the SCRATCHPAD_3V_READ register (wake up from shutdown) can determine the
GPIO configuration.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DATA[15:0] (R/W)
Scratch Image
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DATA[31:16] (R/W)
Scratch Image

Figure 4-15: PMG_TST_SCRPAD_IMG Register Diagram
Table 4-18: PMG_TST_SCRPAD_IMG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 DATA
(R/W)

4–30

Scratch Image.
Value written to this register is saved in 3 V when going to shutdown mode.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG_TST Register Descriptions

Control for SRAM Parity and Instruction SRAM
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ABTINIT (R/W)
Abort Current Initialization. Self-cleared

BNK1EN (R/W)
Enable Initialization

AUTOINIT (R/W)
Automatic Initialization on Wake up
from Hibernate Mode

BNK2EN (R/W)
Enable Initialization
BNK7EN (R/W)
Enable Initialization

STARTINIT (R/W)
Start Manual Initialization
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

INSTREN (R/W)
Enables 32kB Instruction SRAMPENBNK0 (R/W)
Enable Parity Check

PENBNK7 (R/W)
Enable Parity Check

PENBNK1 (R/W)
Enable Parity Check

PENBNK6 (R/W)
Enable Parity Check

PENBNK2 (R/W)
Enable Parity Check

PENBNK5 (R/W)
Enable Parity Check

PENBNK3 (R/W)
Enable Parity Check

PENBNK4 (R/W)
Enable Parity Check

Figure 4-16: PMG_TST_SRAM_CTL Register Diagram
Table 4-19: PMG_TST_SRAM_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31 INSTREN

Enables 32kB Instruction SRAM.

(R/W)
23 PENBNK7

Enable Parity Check.

(R/W)
22 PENBNK6

Enable Parity Check.

(R/W)
21 PENBNK5

Enable Parity Check.

(R/W)
20 PENBNK4

Enable Parity Check.

(R/W)
19 PENBNK3

Enable Parity Check.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–31

ADuCM4050 PMG_TST Register Descriptions

Table 4-19: PMG_TST_SRAM_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
18 PENBNK2

Enable Parity Check.

(R/W)
17 PENBNK1

Enable Parity Check.

(R/W)
16 PENBNK0

Enable Parity Check.

(R/W)
15 ABTINIT

Abort Current Initialization. Self-cleared.

(R/W)
14 AUTOINIT

Automatic Initialization on Wake up from Hibernate Mode.

(R/W)
13 STARTINIT(R/W)
7 BNK7EN

Start Manual Initialization.
Write one to trigger initialization. Self-cleared.
Enable Initialization.

(R/W)
2 BNK2EN

Enable Initialization.

(R/W)
1 BNK1EN

Enable Initialization.

(R/W)

4–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 PMG_TST Register Descriptions

Initialization Status Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BNK7DONE (R)Bank 7 Initialization Status

BNK0DONE (R)Bank 0 Initialization Status

BNK6DONE (R)Bank 6 Initialization Status

BNK1DONE (R)Bank 1 Initialization Status

BNK5DONE (R)Bank 5 Initialization Status

BNK2DONE (R)Bank 2 Initialization Status

BNK4DONE (R)Bank 4 Initialization Status

BNK3DONE (R)Bank 3 Initialization Status

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4-17: PMG_TST_SRAM_INITSTAT Register Diagram
Table 4-20: PMG_TST_SRAM_INITSTAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7 BNK7DONE(R/NW)

Bank 7 Initialization Status.
0 Bank 7 not initialized
1 Bank 7 initialized

6 BNK6DONE(R/NW)

Bank 6 Initialization Status.
0 Bank 6 not initialized
1 Bank 6 initialized

5 BNK5DONE(R/NW)

Bank 5 Initialization Status.
0 Bank 5 not initialized
1 Bank 5 initialized

4 BNK4DONE(R/NW)

Bank 4 Initialization Status.
0 Bank 4 not initialized
1 Bank 4 initialized

3 BNK3DONE(R/NW)

Bank 3 Initialization Status.
0 Bank 3 not initialized
1 Bank 3 initialized

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

4–33

ADuCM4050 PMG_TST Register Descriptions

Table 4-20: PMG_TST_SRAM_INITSTAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 BNK2DONE(R/NW)

Bank 2 Initialization Status.
0 Bank 2 not initialized
1 Bank 2 initialized

1 BNK1DONE(R/NW)

Bank 1 Initialization Status.
0 Bank 1 not initialized
1 Bank 1 initialized

0 BNK0DONE(R/NW)

Bank 0 Initialization Status.
0 Bank 0 not initialized
1 Bank 0 initialized

4–34

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceGeneral-Purpose I/O (GPIO)

5 General-Purpose I/O (GPIO)

This section describes the general-purpose input/output (GPIO) functionality.

GPIO Features
The GPIO ports include the following features:• Input and output modes of GPIO operation.
• Port multiplexing controlled by individual pin-per-pin base.
• All port pins provide interrupt functionality.
• Programmable pull-up/pull-down drive compatibility.

GPIO Functional Description
The ADuCM4050 MCU controls the GPIO pins through a set of Memory Mapped Registers (MMR). These
MMRs are implemented as part of an APB32 peripheral. Multiple functions are mapped on most of the GPIO pins.
These functions can be selected by appropriately configuring the corresponding ports of the GPIO_CFG registers.
The ADuCM4050 MCU has up to 51 GPIO bidirectional pins. Most of the GPIO pins have multiple functions,configurable by user code, when multiplexed at the top-level. The GPIOs are grouped into four ports: P0, P1, P2,
and P3. P0, P1, and P2 contain 16 GPIOs. P3 contains 4 GPIOs.

GPIO Block Diagram
The figures show the block diagrams of the GPIO pins with pull-up and pull-down resistors.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–1

GPIO Functional Description

Output Enable

IOVDD

Pull-up Enable
GPIO_PE

GPIO_OEN

Output Data
GPIO_OUT, GPIO_SET,GPIO_CLR, GPIO_TGL

GPIOInput Data
GPIO_IEN

Input Data
GPIO_IN

Figure 5-1: GPIO Pins with Pull-up Resistor
Output Enable
GPIO_OEN

Output Data

GPIO

GPIO_OUT, GPIO_SET,GPIO_CLR, GPIO_TGL

Pull-down Enable
GPIO_PE

Input Data
GPIO_IEN

Input DataIOGND

GPIO_IN

Figure 5-2: GPIO Pins with Pull-down Resistor

In applications where the input is not controlled by the system, the input voltage may exceed the maximum voltage
rating of the device. When the external overvoltage conditions are applied to the ADuCM4050 MCU, ESD diodes
must be used between the amplifier and electrical over stress.
All GPIOs have a diode clamping circuit to protect against overvoltage and ESD.
The following figure shows the equivalent circuit of diode clamping.

5–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceGPIO Functional Description

PAD

Figure 5-3: Diode Clamping Circuit

ADuCM4050 GPIO Multiplexing
The following tables show the pin functions that are multiplexed on the general-purpose I/O pins of the package
Table 5-1: Signal Muxing - Port 0
Signal Name

Multiplexed
Function 0

Multiplexed
Function 1

Multiplexed
Function 2

P0_00

P0_00

SPI0_CLK

SPT0_BCLK

P0_01

P0_01

SPI0_MOSISPT0_BFS

P0_02

P0_02

SPI0_MISO

SPT0_BD0

P0_03

P0_03

SPI0_CS0SPT0_BCNV

P0_04

P0_04

I2C0_SCL

P0_05

P0_05

I2C0_SDA

P0_06

SWD0_CLK

P0_06

P0_07

SWD0_DATA

P0_07

P0_08

P0_08

BEEP0_TONE

P0_09

P0_09

BEEP0_TONE

P0_10

P0_10

UART0_TX

P0_11

P0_11

UART0_RX

P0_12

P0_12

SPT0_AD0

P0_13/SYS_WAKE2

P0_13

P0_14

P0_14

P0_15/SYS_WAKE0

P0_15

Multiplexed
Function 3

SPI2_RDY

SPI2_CS1

UART_SOUT_EN

TMR0_OUT

SPI1_RDY

Multiplexed
Function 1

Multiplexed
Function 2

Table 5-2: Signal Muxing - Port 1
Signal Name

Multiplexed
Function 0

P1_00/SYS_WAKE1

P1_00

P1_01

SYS_BMODE0

P1_01

P1_02

P1_02

SPI2_CLK

Multiplexed
Function 3

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–3

GPIO Functional Description

Table 5-2: Signal Muxing - Port 1 (Continued)
Signal Name

Multiplexed
Function 0

Multiplexed
Function 1

Multiplexed
Function 2

P1_03

P1_03

SPI2_MOSI

P1_04

P1_04

SPI2_MISO

P1_05

P1_05

SPI2_CS0

P1_06

P1_06

SPI1_CLKRGB_TMR0_1

P1_07

P1_07

SPI1_MOSIRGB_TMR0_2

P1_08

P1_08

SPI1_MISORGB_TMR0_3

P1_09

P1_09

SPI1_CS0

SWV

P1_10

P1_10

SPI0_CS1

P1_11

P1_11

TMR1_OUT

P1_12

P1_12

RTC1_SS2

P1_13

P1_13

P1_14

P1_14

P1_15

P1_15

SYS_CLKIN

Multiplexed
Function 3

SPI1_CS3

TMR2_OUT
SPI0_RDY
SPT0_ACLKUART1_TX

Table 5-3: Signal Muxing - Port 2
Signal Name

Multiplexed
Function 0

Multiplexed
Function 1

Multiplexed
Function 2

P2_00

P2_00

SPT0_AFSUART1_RX

P2_01/SYS_WAKE3

P2_01

P2_02

P2_02

SPT0_ACNV

P2_03

P2_03

ADC0_VIN0

P2_04

P2_04

ADC0_VIN1

P2_05

P2_05

ADC0_VIN2

P2_06

P2_06

ADC0_VIN3

P2_07

P2_07

ADC0_VIN4SPI2_CS3

P2_08

P2_08

ADC0_VIN5

SPI0_CS2

P2_09

P2_09

ADC0_VIN6

SPI0_CS3

P2_10

P2_10

ADC0_VIN7

SPI2_CS2

P2_11

P2_11

SPI1_CS1

SYS_CLKOUT

5–4

Multiplexed
Function 3

TMR2_OUT
SPI1_CS2

RTC1_SS3

RTC1_SS1

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceGPIO Operating Modes

GPIO Operating ModesIO Pull-Up or Pull-Down Enable
All GPIO pins can be grouped into two categories: GPIO pins with a pull-up resistor and GPIO pins with a pulldown resistor. Each GPIO port has a corresponding GPIO_PE register. Using the GPIO_PE registers, it is possible
to enable/disable pull-up/pull-down registers on the pins when they are configured as inputs.

IO Data In
When configured as an input using the GPIO_IEN register, the GPIO input levels are available in the GPIO_IN
register.

IO Data Out
When the GPIOs are configured as outputs using the GPIO_OEN register, the values in the GPIO_OUT register arereflected on the GPIOs.

Bit SetEach GPIO port has a corresponding bit set register, GPIO_SET. Use the bit set register to set one or more GPIO
data outs without affecting others within the port. Only the GPIO corresponding with the write data bit equal to
one is set, the remaining GPIOs are unaffected.

Bit Clear
Each GPIO port has a corresponding bit clear register, GPIO_CLR. Use the bit clear register to clear one or more
GPIO data outs without affecting others within the port. Only the GPIO corresponding with the write data bit
equal to one is cleared, the remaining GPIOs are unaffected.

Bit Toggle
Each GPIO port has a corresponding bit toggle register, GPIO_TGL. Using the bit toggle register, it is possible toinvert one or more GPIO data outs without affecting others within the port. Only the GPIO corresponding withthe write data bit equal to one is toggled, the remaining GPIOs are unaffected.

IO Data Output Enable
Each GPIO port has a data output enable (GPIO_OEN) register, by which the data output path is enabled. Whenthe data output enable register bits are set, the values in GPIO_OUT are reflected on the corresponding GPIO pins.

Interrupts
Each GPIO pin can be associated with an interrupt. Interrupts can be independently enabled for each GPIO pin
and are always edge detect; only one interrupt will be generated with each GPIO pin transition. The polarity of thedetected edge can be positive (low-to-high) or negative (high-to-low). Each GPIO interrupt event can be mapped to
one of two interrupts (INTA or INTB). This allows the system more flexibility in terms of how GPIO interrupts are
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–5

GPIO Operating Modes

grouped for servicing, and how interrupt priorities are set. The interrupt status of each GPIO pin can be determined
and cleared by accessing the associated status registers.

Interrupt Polarity
The polarity of the interrupt determines if the interrupt is accepted on the rising or the falling edge. Each GPIO
port has a corresponding interrupt register (GPIO_POL) by which the interrupt polarity of each pin is configured.
When set to 0, an interrupt event will be latched on a high-to-low transition on the corresponding pin. When set to
1, an interrupt event will be latched on a low-to-high transition on the corresponding pin.

Interrupt A Enable
Each GPIO port has an Interrupt Enable A register (GPIO_IENA) that is enabled or masked for each pin in theport. These register bits determine if a latched edge event should be allowed to interrupt the core (Interrupt A) or bemasked. In either case, the occurrence of the event will be captured in the corresponding bit of the GPIO_INT
status register. When set to 0, Interrupt A is not enabled (masked). No interrupts to the core will be generated bythis GPIO pin. When set to 1, Interrupt A is enabled. On a valid detected edge, an interrupt source to the core will
be generated.

Interrupt B Enable
Each GPIO port has a corresponding Interrupt Enable B (GPIO_IENB) register that is enabled or masked for eachpin in the port. These register bits determine if a latched edge event should be allowed to interrupt the core (Interrupt B) or be masked. In either case, the occurrence of the event will be captured in the corresponding bit of the
GPIO_INT status register. When set to 0, Interrupt B is not enabled (masked). No interrupts to the core will be
generated by this GPIO pin. When set to 1, Interrupt B is enabled. On a valid detected edge, an interrupt source tothe core will be generated.

Interrupt Status
Each GPIO port has an interrupt status register (GPIO_INT) that captures the interrupts occurring on its pins.
These register bits indicate that the appropriately configured rising or falling edge has been detected on the corresponding GPIO pin.
Once an event is detected, GPIO_INT will remain set until cleared; this is true even if the GPIO pin transitions
back to a nonactive state. Out of reset, pull ups combined with falling edge detect can result in the GPIO_INT
status being cleared; however, this may not be the case based on pin activity. It is therefore recommended that thestatus of GPIO_INT be checked before enabling interrupts (GPIO_IENA and GPIO_IENB) initially as well as
anytime GPIO pins are configured.
Interrupt bits are cleared by writing a 1 to the appropriate bit location. Writing a 0 has no effect. If interrupts areenabled to the core (GPIO_IENA, GPIO_IENB), an interrupt (GPIO_INT) value of 1 will result in an interrupt
to the core. This bit should be cleared during servicing of the interrupt. When read as 0, a rising or falling edge was
not detected on the corresponding GPIO pin because this bit was last cleared. When read as 1, a rising or fallingedge (GPIO_POL selectable) was detected on the corresponding GPIO pin. This bit can be software cleared by

5–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceGPIO Programming Model

writing a 1 to this bit location. This bit can only be subsequently set again after the pin returns to its nonasserted
state and then returns to an asserted state.

GPIO Programming Model
Programming Sequence for output functionality:
1. Program the GPIO_OEN register for the appropriate GPIO pins.
2. The data on the selected pin is driven high or low by writing to the GPIO_SET/GPIO_CLR/GPIO_TGL
registers.
Programming Sequence for input functionality:
1. Program the GPIO_IEN register for the appropriate port pins.
2. The data latched by the input port pin is registered in the GPIO_IN register. Interrupts can be enabled bywriting to the GPIO_IENA or GPIO_IENB register.

ADuCM4050 GPIO Register Descriptions
General-Purpose Input/Output (GPIO) contains the following registers.
Table 5-4: ADuCM4050 GPIO Register List
Name

Description

GPIO_CFG

Port Configuration

GPIO_CLRPort Data Out Clear

GPIO_DSPort Drive Strength Select

GPIO_IEN

Port Input Path Enable

GPIO_IENAPort Interrupt A Enable

GPIO_IENBPort Interrupt B Enable

GPIO_IN

Port Registered Data Input

GPIO_INTPort Interrupt Status

GPIO_OEN

Port Output Enable

GPIO_OUTPort Data Output

GPIO_PE

Port Output Pull-up/Pull-down Enable

GPIO_POL

Port Interrupt Polarity

GPIO_SETPort Data Out Set

GPIO_TGLPort Pin Toggle

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–7

ADuCM4050 GPIO Register Descriptions

Port Configuration
The GPIO_CFG register is reserved for top-level pin muxing for the GPIO block.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PIN07 (R/W)
Pin 7 Configuration Bits

PIN00 (R/W)
Pin 0 Configuration Bits

PIN06 (R/W)
Pin 6 Configuration Bits

PIN01 (R/W)
Pin 1 Configuration Bits

PIN05 (R/W)
Pin 5 Configuration Bits

PIN02 (R/W)
Pin 2 Configuration Bits

PIN04 (R/W)
Pin 4 Configuration Bits

PIN03 (R/W)
Pin 3 Configuration Bits

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PIN15 (R/W)
Pin 15 Configuration Bits

PIN08 (R/W)
Pin 8 Configuration Bits

PIN14 (R/W)
Pin 14 Configuration Bits

PIN09 (R/W)
Pin 9 Configuration Bits

PIN13 (R/W)
Pin 13 Configuration Bits

PIN10 (R/W)
Pin 10 Configuration Bits

PIN12 (R/W)
Pin 12 Configuration Bits

PIN11 (R/W)
Pin 11 Configuration Bits

Figure 5-4: GPIO_CFG Register Diagram
Table 5-5: GPIO_CFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:30 PIN15

Pin 15 Configuration Bits.

(R/W)
29:28 PIN14

Pin 14 Configuration Bits.

(R/W)
27:26 PIN13

Pin 13 Configuration Bits.

(R/W)
25:24 PIN12

Pin 12 Configuration Bits.

(R/W)
23:22 PIN11

Pin 11 Configuration Bits.

(R/W)

5–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 GPIO Register Descriptions

Table 5-5: GPIO_CFG Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
21:20 PIN10

Pin 10 Configuration Bits.

(R/W)
19:18 PIN09

Pin 9 Configuration Bits.

(R/W)
17:16 PIN08

Pin 8 Configuration Bits.

(R/W)
15:14 PIN07

Pin 7 Configuration Bits.

(R/W)
13:12 PIN06

Pin 6 Configuration Bits.

(R/W)
11:10 PIN05

Pin 5 Configuration Bits.

(R/W)
9:8 PIN04

Pin 4 Configuration Bits.

(R/W)
7:6 PIN03

Pin 3 Configuration Bits.

(R/W)
5:4 PIN02

Pin 2 Configuration Bits.

(R/W)
3:2 PIN01

Pin 1 Configuration Bits.

(R/W)
1:0 PIN00

Pin 0 Configuration Bits.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–9

ADuCM4050 GPIO Register Descriptions

Port Data Out Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (W)
Set the Output Low for the Port Pin

Figure 5-5: GPIO_CLR Register Diagram
Table 5-6: GPIO_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(RX/W)

5–10

Set the Output Low for the Port Pin.
Each bit is set to drive the corresponding GPIO pin low. Clearing this bit has no effect.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 GPIO Register Descriptions

Port Drive Strength Select
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PIN15 (R/W)
Drive Strength Pin 15

PIN00 (R/W)
Drive Strength Pin 00

PIN14 (R/W)
Drive Strength Pin 14

PIN01 (R/W)
Drive Strength Pin 01

PIN13 (R/W)
Drive Strength Pin 13

PIN02 (R/W)
Drive Strength Pin 02

PIN12 (R/W)
Drive Strength Pin 12

PIN03 (R/W)
Drive Strength Pin 03

PIN11 (R/W)
Drive Strength Pin 11

PIN04 (R/W)
Drive Strength Pin 04

PIN10 (R/W)
Drive Strength Pin 10

PIN05 (R/W)
Drive Strength Pin 05

PIN09 (R/W)
Drive Strength Pin 09

PIN06 (R/W)
Drive Strength Pin 06

PIN08 (R/W)
Drive Strength Pin 08

PIN07 (R/W)
Drive Strength Pin 07

Figure 5-6: GPIO_DS Register Diagram
Table 5-7: GPIO_DS Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 PIN15

Drive Strength Pin 15.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

14 PIN14

Drive Strength Pin 14.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

13 PIN13

Drive Strength Pin 13.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

12 PIN12(R/W)

Drive Strength Pin 12.
0 Single Drive Strength
1 Double Drive Strength

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–11

ADuCM4050 GPIO Register Descriptions

Table 5-7: GPIO_DS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
11 PIN11

Drive Strength Pin 11.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

10 PIN10

Drive Strength Pin 10.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

9 PIN09

Drive Strength Pin 09.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

8 PIN08

Drive Strength Pin 08.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

7 PIN07

Drive Strength Pin 07.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

6 PIN06

Drive Strength Pin 06.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

5 PIN05

Drive Strength Pin 05.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

4 PIN04

Drive Strength Pin 04.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

3 PIN03

Drive Strength Pin 03.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

2 PIN02(R/W)

Drive Strength Pin 02.
0 Single Drive Strength
1 Double Drive Strength

5–12

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 GPIO Register Descriptions

Table 5-7: GPIO_DS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 PIN01

Drive Strength Pin 01.

(R/W)

0 Single Drive Strength
1 Double Drive Strength

0 PIN00(R/W)

Drive Strength Pin 00.
0 Single Drive Strength
1 Double Drive Strength

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–13

ADuCM4050 GPIO Register Descriptions

Port Input Path Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Input Path Enable

Figure 5-7: GPIO_IEN Register Diagram
Table 5-8: GPIO_IEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

5–14

Input Path Enable.
Each bit is set to enable the input path and cleared to disable the input path for the
GPIO pin.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 GPIO Register Descriptions

Port Interrupt A Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Interrupt A Enable

Figure 5-8: GPIO_IENA Register Diagram
Table 5-9: GPIO_IENA Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/W)

Interrupt A Enable.
Determines if a latched edge event should be allowed to interrupt the core (INTERRUPT A) or be masked. In either case the occurrence of the event will be captured in
the GPIO_INT status register. When cleared, Interrupt A is not enabled (masked).
When set Interrupt A is enabled.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–15

ADuCM4050 GPIO Register Descriptions

Port Interrupt B Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Interrupt B Enable

Figure 5-9: GPIO_IENB Register Diagram
Table 5-10: GPIO_IENB Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

5–16

Interrupt B Enable.
Determines if a latched edge event must be allowed to interrupt the core (INTERRUPT B) or be masked. In either case, the occurrence of the event is captured in the
GPIO_INT status register. When set to 0, Interrupt B is not enabled (masked). Whenset to 1, Interrupt A is enabled.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 GPIO Register Descriptions

Port Registered Data Input
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

X X X X X X X X X X X X X X X X
VALUE (R)Registered Data Input

Figure 5-10: GPIO_IN Register Diagram
Table 5-11: GPIO_IN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)

Registered Data Input.
Each bit reflects the state of the GPIO pin if the corresponding input buffer is enabled.
If the pin input buffer is disabled, the value seen is zero.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–17

ADuCM4050 GPIO Register Descriptions

Port Interrupt Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W1C)
Interrupt Status

Figure 5-11: GPIO_INT Register Diagram
Table 5-12: GPIO_INT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/W1C)

5–18

Interrupt Status.
Indicates that the appropriately configured rising or falling edge has been detected on
the corresponding GPIO pin. Once an event is detected, GPIO_INT.VALUE bit remains set until cleared. This is true even if the GPIO pin transitions back to a nonactive state. GPIO_INT.VALUE bits are cleared by writing 1 to the appropriate bit
location. Writing 0 has no effect.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 GPIO Register Descriptions

Port Output Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Pin Output Drive Enable

Figure 5-12: GPIO_OEN Register Diagram
Table 5-13: GPIO_OEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/W)

Pin Output Drive Enable.
Each bit is set to enable the output for that particular pin. It is cleared to disable theoutput for each pin.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–19

ADuCM4050 GPIO Register Descriptions

Port Data Output
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Data Out

Figure 5-13: GPIO_OUT Register Diagram
Table 5-14: GPIO_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

5–20

Data Out.
Set by user code to drive the corresponding GPIO high. Cleared by user to drive thecorresponding GPIO low.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 GPIO Register Descriptions

Port Output Pull-up/Pull-down Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Pin Pull Enable

Figure 5-14: GPIO_PE Register Diagram
Table 5-15: GPIO_PE Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/W)

Pin Pull Enable.
Each bit is set to enable the pull-up/pull-down for that particular pin. It is cleared todisable the pull-up/pull-down for each pin. The values shown in the Register Diagram
are for GPIO Port 0.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

5–21

ADuCM4050 GPIO Register Descriptions

Port Interrupt Polarity
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Interrupt Polarity

Figure 5-15: GPIO_POL Register Diagram
Table 5-16: GPIO_POL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

5–22

Interrupt Polarity.
Determines if the interrupts are generated on the rising or falling edge of the corresponding GPIO pin. When cleared, an interrupt event is latched on a high-to-lowtransition. When set, an interrupt event is latched on a low-to-high transition.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 GPIO Register Descriptions

Port Data Out Set
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (W)
Set the Output HIGH for the Pin

Figure 5-16: GPIO_SET Register Diagram
Table 5-17: GPIO_SET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(RX/W)

Set the Output HIGH for the Pin.
Set by user code to drive the corresponding GPIO high. Clearing this bit has no effect.

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ADuCM4050 GPIO Register Descriptions

Port Pin Toggle
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (W)Toggle the Output of the Port Pin

Figure 5-17: GPIO_TGL Register Diagram
Table 5-18: GPIO_TGL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(RX/W)

5–24

Toggle the Output of the Port Pin.
Each bit is set to invert the corresponding GPIO pin. Clearing this bit has not effect.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSystem Clocks

6 System Clocks

The ADuCM4050 MCU is integrated with two on-chip oscillators and the circuitry for two external crystals.

System Clock Features
The System Clock features include the following:• LFOSC is a 32 kHz internal oscillator.
• HFOSC is a 26 MHz internal oscillator.
• LFXTAL is a 32 kHz external crystal oscillator.
• HFXTAL is a 16 / 26 MHz external crystal oscillator.
• External clock input through SYS_CLKIN.
• An on-chip phase-locked loop (PLL) is available, system PLL (SPLL). PLL can use HFOSC, HFXTAL, or
SYS_CLKIN as an input clock.
• The high frequency oscillators (HFOSC and HFXTAL), SYS_CLKIN along with the output of the SPLL canbe used to generate the root clock.
• The 32 kHz clock (LF_CLK) is generated from either LFXTAL or LFOSC to drive certain blocks.
• The general purpose timers have their own multiplexers to select their clock source.
• The RTC1 works from LFXTAL or LFOSC in hibernate and active modes. The RTC0 always works fromLFXTAL in shutdown/hibernate/active modes.
• Watchdog timer always works on LFOSC oscillator. It cannot be run using LFXTAL to avoid reliability issues.
It does not work in hibernate or shutdown modes.
• LFXTAL clock failure detection in all modes other than shutdown mode.
• Automatic switching of LFMUX clock to LFOSC during LFXTAL clock failure.
• Root clock failure detection in active mode.
• Automatic switching of Root clock to HFOSC clock during root clock failure.
• The Root clock is divided into several internal clocks.
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System Clock Functional Description• RCLK (not to be confused with root clock) clocks the reference timer (counter) in flash controller. This is used
to time flash erase, write operations. By default, it is connected to 13 MHz clock source. This is generated by ½
divider connected to HFOSC by default (26 MHz). So, the default values of flash timer registers correspond to
13 MHz clock.
If CLKG_CLK_CTL0.RCLKMUX (RHP_CLK) = 11 (HFXTAL = 16 MHz), the ½ DIV (divider) is automatically bypassed and HFXTAL (16 MHz) is directly connected to the RCLK. Therefore, if HFXTAL (16 MHz)is used, flash timer registers need to be programmed to 16 MHz before any flash erase/write operations.
• HP_BUCK_CLK clocks the HP Buck module. The default HPBUCK clock frequency, if enabled, is 200 kHz.
There is another option available for HPBUCK clock frequency with 400 kHz frequency generation as highload mode.
• ACLK clocks the ADC.
• GPIOCLKOFF and PERCLKOFF are used to clock gate the GPIO input logics and peripherals respectively.
These bits are auto enabled if any corresponding read/write is issued. i.e., a write/read to the peripheral registers
will auto re-enable the PCLK and a write/read to the GPIOs will re-enable the GPIO CLK

System Clock Functional Description
This section provides information on the clocks and the clock gates required for power management.

System Clock Block Diagram
The clocking diagram is shown below.

6–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSystem Clock Block Diagram

SPLL mux
SYS_CLKIN

PLL

ACLK

ACLKDIV

52 MHzSPLL

PERCLKOFFADC

UCLKI2COFF
PCLK_I2C

I2C

PCLKDIV
PCLK
root_clock

HFXTAL
16/26 MHz
HFOSC
26 MHZGPIOCLKOFFPCLK self-gated peripherals
GPIO

HFOSC
DIV

AHB sub system clock

HCLKDIV
DIV /2or DIV/1

RCLK

Flash

RHP_CLK

400/200 kHz
clock

RTC0
LFCLK mux
LFXTAL32 kHzlf_clk

RTC1
Beeper

LFOSC
32 kHzHP_BUCK_CLK

HPBuckGPT_CLK Mux /Timer_RGB_CLK Mux
LFXTALLFOSC
PCLK
HFOSC divided

GPTCLKxOFF/
TMRRGBCLKOFF

RGB timer/
TMR

WDT

Figure 6-1: Clocking Diagram

Operation
On power-up, the core executes from a 6.5 MHz system clock. User can program a clocking scheme by setting approriate values in the clocking registers.
Clock Muxes
As shown in the Clocking Diagram, there are four clock source multiplexers:• Root clock selection Mux (Root clock Mux)
• Low frequency clock Mux (LFCLK Mux)
• SPLL input Mux (SPLL Mux)
• RCLK Mux controlled using MMRs
The multiplexer for general purpose timers are controlled through registers within the Timer block.
NOTE: Ensure that the desired clock input is available and stable for the clock selection made for the clock mux.
Else, the system can be locked out of a stable clock.
If RCLK Mux is configured as a non-SPLL clock, SPLL must be disabled by the user.

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System Clock Block Diagram

Table 6-1: Clock Muxes
ClocksRegisters

Selection

Root Clock Mux

CLKG_CLK_CTL0.CLKMUX

00: HFOSC
01: HFXTAL
10: SPLL
11: External clock through SYS_CLKIN GPIO

CLKG_CLK_CTL0.PLL_IPSELSPLL Mux

0: HFOSC
1: HFXTAL
2: External clock through SYS_CLKIN GPIO

CLKG_OSC_CTL.LFCLK_MUXLFCLK Mux

0: LFOSC
1: LFXTALCLKG_CLK_CTL0.RCLKMUXRCLK Mux

00: HFOSC
01: Reserved
10: HFXTAL 26 MHz
11: HFXTAL 16 MHz

GPT_CLK Mux

TMR_CTL.CLK

Controlled by Timer 0/Timer 1/Timer 2/Timer_RGB

Timer_RGB_Clk Mux

CLKG_CLK_CTL5.
TMRRGBCLKOFF

00: PCLK (Output from PDIV (PCLK Divider))01: HFOSC 26 MHz (Internal high frequency)
10: LFOSC 32 kHz (Internal low frequency oscillator)
11: LFXTAL 32 kHz

Clock Dividers
Three programmable clock dividers are available to generate the clocks in the system. A clock divider integer divides
the input clock down to a new clock. The division range is from 1 to 32 for HCLK and PCLK dividers, and 1 to
511 for ACLK divider. Division selection can be made on-the-fly. The output remains glitch free and stretches thehigh time, never creating a high time shorter than the pre or post value of the clock period.
Two clock dividers use the root clock as an input and generate the core and peripheral synchronized clocks. The
clock dividers are cascaded in such a way that each stage initially releases its divided clock in a sequence. The laststage informs all other stages that its divided clock is ready to be output. The effect of this cascading is that divided
clocks are released synchronously when new divider values are programmed. Initial edges of each clock are mutuallyaligned.
The Clock Dividers table summarizes the inputs and outputs of each clock divider along with the register bits toprogram them.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSystem Clock Block Diagram

Table 6-2: Clock Dividers
Divider

Input ClockOutput Clocks

Bit Field

Retained in Hibernate Mode0

Root clock

HCLK_CORE, HCLK_BUS,
FCLK

CLKG_CLK_CTL1.HCLKDIVCNT

Yes

1Root clock

PCLK, all peripheral clocks

CLKG_CLK_CTL1.PCLKDIVCNT

Yes

2

Root clock

ACLK (for ADC)

CLKG_CLK_CTL1.ACLKDIVCNTNo

As the ADC clock requires a clean start, the user must program the CLKG_CLK_CTL1.ACLKDIVCNT field after
waking from hibernate (CLKG_CLK_CTL1.ACLKDIVCNT is not retained in hibernate mode). Also, the user
must re-enable the ADC, as the ADC_CFG.EN bit is not retained in hibernate mode.
Only certain divider ratios are legal between PCLK and HCLK. The frequency of PCLK must be less than or equal
to the frequency of HCLK, and the ratio of the dividers must be an integer.
In general, clock division can be changed on the fly during normal operation.
Clock Gating
In the case of certain clocks, clocks can be individually gated depending on the power mode or register settings. For
more information about clock gating and power modes, refer to Power Management (PMG).
The clock gates of the peripheral clocks are user controllable in certain power modes. The CLKG_CLK_CTL5 register can be programmed to turn off certain clocks, depending on user application. To disable the clock, set the respective bits in the CLKG_CLK_CTL5 register to 1.

PLL Settings
The PLL Diagram shows the abstract PLL structure for SPLL. It has the multiplier coefficient N and divider coefficient M to decide the output clock ratio of N/M. There is an optional DIV2 built in the PLL to either divide down
the PLL output clock by 2 or directly output it. This is also an optional MUL2 built-in to PLL to multiply the clockout of PLL by 2 to increase the range of the PLL.
The PLL must always switch away from ROOT_CLK when changing any coefficients or clock sources.
When the reference clock for the phase frequency detector (PFD) has a 2 MHz input, the PLL has its best phasemargin. Therefore, it is recommended that for a 26 MHz crystal clock input, configure M as 13, and for a 16 MHz
crystal clock input, configure M as 8.
1/M

Phase Frequency
Detector

VCO

1/N

DIV2

Clock Out

1/MUL2

Figure 6-2: PLL Diagram

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PLL Settings

PLL Output Frequency = Clock in * (MUL2*N)/ (DIV2*M)
The PLL Settings table shows the recommend PLL settings for a variety of input and output clocks. The PLL settings can be programmed using the CLKG_CLK_CTL3 register.
To enable the SPLL, the CLKG_CLK_CTL3.SPLLEN bit must be set. The SPLL N multiplier can be set using the
CLKG_CLK_CTL3.SPLLNSEL bits.
The M divider can also be set using the CLKG_CLK_CTL3.SPLLMSEL bits. SPLL MUL2 is controlled by the
CLKG_CLK_CTL3.SPLLMUL2 bit. DIV2 is controlled by the CLKG_CLK_CTL3.SPLLDIV2 bit.
MUL2 = CLKG_CLK_CTL3.SPLLMUL2+1 and DIV2 = CLKG_CLK_CTL3.SPLLDIV2+ 1.
Table 6-3: PLL Settings for 26 MHz and 52 MHz
PLL

Input Clock (MHz)

M

MUL2

N

DIV2

Output Clock (MHz)

SPLL

26

13

1

26

2

26

SPLL

16

8

1

26

2

26

SPLL

26

13

1

26

1

52

SPLL

16

8

1

26

1

52

The minimum value of N is 8 (if MUL2=2) and maximum is 31. The recommended output frequency from 1/M
divider is 2 MHz and the minimum value of M = 2.
PLL Output Frequency = Clock in* ((MUL2*NSEL)/ (DIV2*MSEL))
Where,
MUL2 = CLKG_CLK_CTL3.SPLLMUL2+1
DIV2 = CLKG_CLK_CTL3.SPLLDIV2 + 1
DIV2 = CLKG_CLK_CTL3.SPLLNSELMSEL = CLKG_CLK_CTL3.SPLLMSELPLL Interrupts
The PLL can interrupt the core when it locks or when it loses its lock. To enable the SPLL interrupts, the
CLKG_CLK_CTL3.SPLLIE bit must be set. The CLKG_CLK_STAT0.SPLLUNLK bit indicates that the SPLL
unlock event has happened.
The CLKG_CLK_STAT0.SPLLLK bit indicates that a SPLL lock event has happened. Both the bits are used tointerrupt the core when PLL interrupts are enabled. Both bits are sticky and must write a 1 to be cleared. These bits
are different from the CLKG_CLK_STAT0.SPLL bit, which mirrors the value of the SPLL lock signal (1: Locked,
0: Unlocked).

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferencePLL Settings

PLL Programming Sequence
The following sequence shows how to configure a 26 MHz input clock from HFXTAL to 26 MHz SPLL output,
and use the PLL output as Root clock. The HCLK is set to 26 MHz and PCLK to 6.5 MHz.
1. Enable PLL interrupts by setting CLKG_CLK_CTL3.SPLLIE to 0x1.
2. Set HFXTAL as input to PLL by setting CLKG_CLK_CTL0.PLL_IPSEL to 0x1.
3. Enable HFXTAL by setting CLKG_OSC_CTL.HFXTALEN to 0x1.
4. Set the clock dividers consistent with the intended system clock rates by setting
CLKG_CLK_CTL1.PCLKDIVCNT to 0x04 and CLKG_CLK_CTL1.HCLKDIVCNT to 0x01.
5. Enable the PLL and configure the PLL M and N values by setting CLKG_CLK_CTL3.SPLLEN to 0x1,
CLKG_CLK_CTL3.SPLLMSEL to 0xD, and CLKG_CLK_CTL3.SPLLNSEL to 0x1A.
6. Wait for the PLL interrupt indicating that the PLL has locked. Optionally, also check that the crystal is stable
at this stage, even though the PLL should not lock if the crystal is not stable.
7. Clear the PLL interrupt and select PLL as the system clock source by setting CLKG_CLK_STAT0.SPLLLK
to 0x1 and CLKG_CLK_CTL0.CLKMUX to 0x2.
The following sequence shows how to configure a 26 MHz input clock from HFOSC to 16 MHz SPLL output, anduse the PLL output as Root clock. HCLKDIV and PCLKDIV are set to 0x1.
1. Enable PLL interrupts by setting CLKG_CLK_CTL3.SPLLIE to 0x1.
2. Set HFOSC as input to PLL by setting CLKG_CLK_CTL0.PLL_IPSEL to 0x0.
3. Disable the PLL by setting CLKG_CLK_CTL3.SPLLEN to 0x0.
4. Program appropriate MSEL, NSEL to get PLL clock out as 16 MHz by setting
CLKG_CLK_CTL3.SPLLMSEL to 0xD and CLKG_CLK_CTL3.SPLLNSEL to 0x10.
5. Enable the PLL by setting CLKG_CLK_CTL3.SPLLEN to 0x1.
6. Wait for the PLL interrupt indicating that the PLL has locked. Optionally, check if the crystal is stable at thisstage.
7. Clear the PLL interrupt and select PLL as the system clock source by setting CLKG_CLK_STAT0.SPLLLK
to 0x1 and CLKG_CLK_CTL0.CLKMUX to 0x2.

Crystal Programming
The crystals are disabled by default and can be programmed using the CLKG_OSC_CTL register. The crystals canbe enabled by setting the CLKG_OSC_CTL.HFX_EN or CLKG_OSC_CTL.LFX_EN bits. The stable signal status
bits are also mirrored in this register.

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Oscillator Programming

NOTE: The CLKG_OSC_CTL.HFOSC_EN bit must be set before issuing a SYSRESETREQ and allowing the
Cortex-M4F to assert a reset request signal to the systems reset generator. This ensures that all system components
are reset properly. This is independent of the Root clock mux and SPLL clock mux settings.
Interrupts
Each crystal can interrupt the core when its output clock becomes stable. The interrupts are enabled by setting the
CLKG_CLK_CTL0.HFXTALIE and CLKG_CLK_CTL0.LFXTALIE bits.
The CLKG_CLK_STAT0.HFXTAL and CLKG_CLK_STAT0.LFXTAL bits contain the current state of the stable signals of the crystals. The CLKG_CLK_STAT0.HFXTALOK or CLKG_CLK_STAT0.LFXTALOK bits are set
when an event is detected on the stable signals of the crystals.
The CLKG_CLK_STAT0.HFXTALOK/ CLKG_CLK_STAT0.HFXTALNOK and
CLKG_CLK_STAT0.LFXTALOK/ CLKG_CLK_STAT0.LFXTALNOK bits are sticky and must be cleared bywriting to 1.
NOTE: CLKG_CLK_STAT0.HFXTALNOK and CLKG_CLK_STAT0.LFXTALNOK bits are not continuous
XTAL monitors and are only set as a confirmation that the corresponding XTAL has been properly disabled.
PLL Clock Protection
In the event the clock source to the PLL is lost, the PLL will maintain operation at a reduced VCO output frequency of approximately 20 MHz, for approximately 3 to 5 ms, this clock will be active/running until PLL is disabled.
This behavior allows PLL interrupt sources such as CLKG_CLK_STAT0.SPLLUNLK to be serviced and enables
the appropriate action to be taken by the core. This feature protects the core from an indefinite stall due to broken
or short leads of the XTAL circuit.

Oscillator Programming
Both the internal oscillators are enabled by default.
Before issuing a SYSRESETREQ and allowing the Cortex-M4F to assert a reset request signal to the systems reset
generator, the CLKG_OSC_CTL.HFOSC_EN bit must be set. This ensures that all system components are reset
properly. This is independent of Root clock mux and SPLL clock mux settings.
HFOSC is enabled by using the CLKG_OSC_CTL.HFOSC_EN bit.
NOTE: Before stopping the HFOSC internal oscillator, the HFXTAL should be running the system. Otherwise, thepart locks because its clock has been stopped by the user without possibility of recovery. Peripherals driven with a 32
kHz clock should be switched over to the LFXTAL external crystal oscillator only after ensuring that LFXTAL is
stable and running. LFOSC internal oscillator cannot be disabled.

Switching System Clock to Greater than 26 MHz
The system frequency can be made 52 MHz only using the PLL clock output.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceOscillators

When changing the PLL output from 26 MHz to 52 MHz, the flash wait state has to be changed from 0 to 1. The
maximum ACLK frequency that can drive ADC is 26 MHz. If the Root clock is 52 MHz, change the ACLK frequency such that the frequency is limited to the maximum allowed frequency.
If the PCLK frequency is 52 MHz, the respective clock setting registers of SPI, UART, SPORT, and I2C modules
are also programmed with the appropriate values. Ensure that the ADC power-up wait count specified in ADC
PWRUP register is also programmed with respect to the PCLK frequency.
The PMG_CTL1.HPBUCK_LD_MODE bit has to be set to 1, when the system clock is greater than 26 MHz.
The following steps show how to change the PLL clock out frequency from 26 MHz to 52 MHz.
Assume that CLKG_CLK_CTL1.HCLKDIVCNT and CLKG_CLK_CTL1.PCLKDIVCNT are programmed to divide by 1. and PLL input source is HFXTAL (26 MHz):
1. Enable the PLL interrupts by setting the CLKG_CLK_CTL3.SPLLIE bit to 0x1.
2. Select HFOSC (26 MHz) as Root clock instead of PLL clock (CLKG_CLK_CTL0.CLKMUX = 0x0).
3. Disable PLL by setting the CLKG_CLK_CTL3.SPLLEN bit to 0x0.
4. To get PLL clock out as 52 MHz, set CLKG_CLK_CTL3.SPLLMSEL = 0xD, and
CLKG_CLK_CTL3.SPLLNSEL = 0x1A.
5. Set CLKG_CLK_CTL3.SPLLMUL2 = 0x0 and CLKG_CLK_CTL3.SPLLDIV2 = 0x0
6. Enable PLL by setting the CLKG_CLK_CTL3.SPLLEN bit to 0x1.
7. Wait for the PLL interrupt indicating that the PLL has locked. Optionally, check if the crystal is stable. The
PLL must not lock if the crystal is not stable.
8. Clear the PLL interrupt and select PLL as the system clock source by setting the
CLKG_CLK_STAT0.SPLLLK bit to 0x1 and the CLKG_CLK_CTL0.CLKMUX bit to 0x2.

Oscillators
HF Oscillator
The 26 MHz high frequency oscillator is enabled by the CLKG_OSC_CTL.HFOSC_EN bit. The divider values are
1, 2, 4, 8, 16, and 32. The HFOSC divider value can be selected using the CLKG_CLK_CTL2 register.
When the HFOSC divider value selected is 1 or 2, the RCLK divider is automatically selected to generate the 13
MHz clock. When the HFOSC divide value is above 2, the RCLK frequency is below 13 MHz, and during thisconditions. Flash erase and write operations are not possible. Read operation is possible.
The CLKG_CLK_CTL2.HFOSCAUTODIV_EN bit to enable the fast wake up from Flexi mode by automaticallyselecting the 26 MHz HFOSC clock during the wakeup.
The CLKG_CLK_CTL2 register must not be written for 3 μs after the CLKG_CLK_CTL2.HFOSCDIVCLKSEL
value is updated.
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Oscillators

Fast Wake-Up from Flexi Mode
During the Cortex wake up from Flexi mode, the HF oscillator divider can be automatically loaded with divided by
1 value to enable the fast wake-up, provided the CLKG_CLK_CTL2.HFOSCAUTODIV_EN bit is set to 1.
When divided by 1 clock is selected, the 26 MHz HFOSC clock itself will be used during the wakeup for enabling
the fast wake up. This updated divided by 1 select value remains the same until the new divider value is written to
the HFOSC divider select register.
If the CLKG_CLK_CTL2.HFOSCAUTODIV_EN bit is 0, this fast wake-up feature is disabled and HFOSC divider
register remains unchanged during the wake up.
LF Oscillator
The 32.768 kHz low frequency oscillator is enabled always, it cannot be disabled, and it is disabled automatically in
shutdown mode.
HFXTAL Oscillator
The high frequency oscillator is enabled by the CLKG_OSC_CTL.HFX_EN bit. Lock time is the time the XTAL
takes to give stable clock out after it is enabled. The locking of the oscillator to the correct frequency is signified by
the setting of CLKG_CLK_STAT0.HFXTALOK status bit.
LFXTAL Oscillator
The LFXTAL oscillator is the clock source for the RTC. It is used to keep the time of the system. It provides a
32.768 kHz output clock. This is enabled by setting the CLKG_OSC_CTL.LFX_EN bit.
Once the oscillator is enabled, it remains ON (in hibernate and shutdown modes).
LFXTAL Bypass Feature
LF crystal can be bypassed and external clock supplied on SYS_LFXTAL_IN and used as LFXTAL clock. This functionality is available in all modes other than shutdown mode. LFXTAL lock is automatically generated synchronous
to external clock provided. This feature has to be disabled before entering into shutdown.
Enable LFXTAL Bypass Mode
1. Disable LFXTAL by writing key to the CLKG_OSC_KEY.VALUE and then clearing the
CLKG_OSC_CTL.LFX_EN bit.
2. Wait for the CLKG_OSC_CTL.LFX_OK bit to be de-asserted.
3. Write key to the CLKG_OSC_KEY.VALUE and set the CLKG_OSC_CTL.LFX_BYP bit.
4. Wait for the CLKG_OSC_CTL.LFX_OK bit to be asserted. External clock is connected to LFXTAL at thisstage.
Disable LFXTAL Bypass Mode
1. Write key to the CLKG_OSC_KEY.VALUE and set the CLKG_OSC_CTL.LFX_BYP bit.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceOscillators

2. Wait for the CLKG_OSC_CTL.LFX_OK bit to be de-asserted. External clock is disconnected from LFXTAL
clock.
LFXTAL Clock Failure
Inactivity in LFXTAL clock can be monitored and interrupt/wakeup can be generated once clock failure is observed.
LFOSC clock (32 kHz) is used to monitor and report failure on LFXTAL clock. This feature is supported for
LFXTAL clock frequencies greater than or equal to 1 kHz. Interrupt/wakeup source is available with RTC1 interrupt source.
Clock failure is reported as active high status bit CLKG_OSC_CTL.LFX_FAIL_STA. This status bit has to becleared to de-assert the interrupt source.
Enable LFXTAL Clock Failure
1. Write proper key to the CLKG_OSC_KEY.VALUE.
2. Set the CLKG_OSC_CTL.LFX_MON_EN bit.
3. Enable interrupt source for RTC1.
Disable LFXTAL Clock Failure
1. Write proper key to CLKG_OSC_KEY.VALUE.
2. Clear the CLKG_OSC_CTL.LFX_MON_EN bit.
Clear Status Bit
1. Disable LFXTAL clock failure feature.
2. Write key to CLKG_OSC_KEY.VALUE.
3. Set the CLKG_OSC_CTL.LFX_FAIL_STA bit to clear the status.
4. Wait until the CLKG_OSC_CTL.LFX_FAIL_STA bit is cleared. This clears both status and interrupt.
LFMUX Auto Switch to LFOSC During LFXTAL FailureThis feature provides the automatic switching of the LFMUX output clock to LFOSC clock, during the LFXTAL
clock failure when the LFMUX is set to use the LFXTAL clock. The LFXTAL clock monitor feature must also beenabled.
Auto Switch Feature
1. Set CLKG_OSC_CTL.LFX_MON_EN = 1 and CLKG_OSC_CTL.LFX_AUTSW_STA =1. This enables boththe monitor and auto-switch features.
2. Monitor block tracks the LFXTAL and raises an error interrupt, in case of a failure.

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Oscillators

3. If CLKG_OSC_CTL.LFCLKMUX = LFXTAL and LFXTAL monitor error is raised, auto switching logic is
triggered and LFMUX switches to LFOSC clock.
4. Once the switch to LFOSC is complete, hardware sets the CLKG_OSC_CTL.LFX_AUTSW_STA bit.
5. Once original source of LFMUX is revived, to switch back, set CLKG_OSC_CTL.LFX_FAIL_STA to 1.
This clears the interrupt.
6. Once interrupt is cleared, write 1 to CLKG_OSC_CTL.LFX_AUTSW_STA to switch back to original clock
source.
Root Clock Failure
Inactivity in root clock can be monitored and interrupt can be generated once clock failure is observed. The
HFOSC clock is used to monitor and report failure on root clock. Clock failure is reported as active high sticky
status bit CLKG_OSC_CTL.ROOT_FAIL_STA. This status bit has to be cleared to de-assert the interrupt source.
Enable Root Clock Failure
1. Write proper key to CLKG_OSC_KEY.VALUE.
2. Set the CLKG_OSC_CTL.ROOT_MON_EN bit.
3. Enable Interrupt source IRQ71.
Disable LFXTAL Cock Failure
1. Write proper key to CLKG_OSC_KEY.VALUE.
2. Clear the CLKG_OSC_CTL.ROOT_MON_EN bit.
Clear Status Bit
1. Disable the Root clock failure feature.
2. Write key to CLKG_OSC_KEY.VALUE register.
3. Set the CLKG_OSC_CTL.ROOT_FAIL_STA bit to clear the status.
4. Wait until the CLKG_OSC_CTL.ROOT_FAIL_STA bit is cleared. This clears both status and interrupt.
Root CLKMUX Auto Switch to HFOSC during Root Clock FailureThis feature provides the automatic switching of the root clock to HFOSC clock, during the Root clock failure. The
Root clock monitor feature must also be enabled.
Auto Switch Feature
1. Set CLKG_OSC_CTL.ROOT_MON_EN =1 and CLKG_OSC_CTL.ROOT_AUTSW_EN =1. This enables
both monitor and auto-switch features.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSystem Clock Interrupts and Exceptions

2. Monitor block tracks the Root clock. In case of a failure, it raises an error interrupt on line 71.
3. If Root clock monitor error is raised, auto-switching logic is triggered and Root clock switches to HFOSC
clock.
4. Once the switch to HFOSC is complete, hardware sets the CLKG_OSC_CTL.ROOT_AUTSW_STA bit.
5. Once original source of Root clock is revived, to switch back, set the CLKG_OSC_CTL.ROOT_FAIL_STA
bit to 1. This clears the interrupt.
6. Once interrupt is cleared, write 1 to the CLKG_OSC_CTL.ROOT_AUTSW_STA bit to switch back to original clock source.

System Clock Interrupts and Exceptions
Refer to Events (Interrupts and Exceptions), for more information.

Setting the System Clocks
Set System Clock to PLL Input Source
The following timing diagrams describe the sequence of events to change system clock from internal oscillator to
PLL input source based. XTAL refers to HFXTAL (26 MHz or 16 MHz crystal oscillator). Timers (GPT) have following expiry periods.
HFXTAL lock timer expiry: 20 ms
LFXTAL lock timer expiry: 1.5 s
If the oscillators are not locked beyond the expiry period, it indicates that there are issues in the XTAL.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–13

Setting the System Clocks

1. Set System Clock tooscillator (default)

PLL input
source?

XTAL

2. Turn On XTAL

3. Setup Timer

4. Poll XTAL lock bit

NoOSC
5. Xtal Locked?
Timer ISR: Error, the
XTAL has not locked

6. Disable Timer

7. Select Xtal as PLL
source8. Setup Timer

9. Program PLL

10. Poll PLL lock bit

NoTimer ISR: Error, the
PLL has not locked

11. PLL Locked?

12. Disable Timer

13. Change System
Clock to PLL

Figure 6-3: Change System Clock to PLL (POLL)

6–14

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSetting the System Clocks

1. Set System Clock tooscillator (default)

PLL input source?

XTAL
2. Select XTAL as PLL
source3. Turn On XTAL

osc

4. Program PLL

5. Setup Timer

6. Poll XTAL lack bit

No

XTAL Locked?
Timer ISR: Error, the
XTAL has not locked

7. Poll PLL lack bit

No

PLL Locked?

Timer ISR: Error, the
PLL has not locked

8. Disable Timer

9. Change System
Clock to PLL

Figure 6-4: Change System Clock to PLL (POLL Alternative)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–15

Setting the System Clocks

1. Set System Clockto oscillator(default)

PLL input
source?

XTAL
2. Select XTALas PLL source

3. Turn On XTAL

osc

4. Program PLL
w/irq

5. Setup Timer

6. Go to Sleep

GPT ISR: The PLL
has not locked

7. PLL ISR.
The PLL has locked.
Clear interrupt

XTAL

PLL input
source?

8. XTAL Locked?
(sanity check)

Error, PLL is locked
but XTAL is not(unlikely)

osc
Yes

9. Change System
Clock to PLL

Figure 6-5: Change System Clock to PLL (IRQ Method)

Set System Clock to XTAL
The following figures show the sequence of events to change system clock from internal oscillator based to XTAL
based source.

6–16

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSetting the System Clocks

1. Set System Clockto oscillator(default)

2. Turn On XTAL

3. Setup Timer

4. Poll XTAL lock bit

No

5. XTAL Locked?
Timer ISR: Error, the
XTAL has not locked

6. Disable Timer

7. Change System
Clock to XTAL source

Figure 6-6: Change System Clock To XTAL (Poll Method)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–17

Setting the System Clocks

1. Set System Clockto oscillator(default)

2. Turn On XTAL withIRQ

3. Setup Timer

4. Go to Sleep

GPT ISR: The XTAL
has not locked

XTAL ISR. The XTAL
has locked

5. Change System
Clock to XTAL source

Figure 6-7: Change System Clock to XTAL (IRQ Method)

Changing System Clock Source
The figure shows the sequence to change the system clock source from oscillator to either XTAL input or PLL based
input source.

6–18

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_OSC Register Descriptions

1. Set System Clockto oscillator(default)

14. Turn On XTAL

XTAL

15. Setup Timer

16. Poll XTAL lock bit

Switch HF Clock?

PLL

PLL input
source?

XTAL

2. Turn On XTAL

3. Setup Timer

GPIO
13. Enable GPIO
clock input

4. Poll XTAL lock bit
No

No

OSC
5. XTAL Locked?

17. XTAL Locked?

Timer ISR: Error, the
XTAL has not locked

Timer ISR: Error, the
XTAL has not locked
6. Disable Timer

18. Disable Timer

7. Select XTAL as
PLL source

8. Program PLL

9. Setup Timer

10. Poll PLL lock bit
NoTimer ISR: Error, the
PLL has not locked

11. PLL Locked?

12. Disable Timer

19. Change System
Clock Source

Figure 6-8: Changing System Clock

ADuCM4050 CLKG_OSC Register Descriptions
Clocking registers (CLKG_OSC) contains the following registers.
Table 6-4: ADuCM4050 CLKG_OSC Register List
Name

Description

CLKG_OSC_CTL

Oscillator Control

CLKG_OSC_KEY

Key Protection for OSCCTRL

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 CLKG_OSC Register Descriptions

Oscillator Control
The CLKG_OSC_CTL register is key-protected. To unlock this protection, 0xCB14 should be written to
CLKG_OSC_KEY before writing to CLKG_OSC_CTL. A write to any other register on the APB bus before writing
to CLKG_OSC_CTL will return the protection to the lock state.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

RESERVED_16_15[0] (R/W)
Reserved Field

LFCLK_MUX (R/W)
32kHz Clock Select Mux

RESERVED_14 (R/W)
Reserved Field

HFOSC_EN (R/W)
High Frequency Internal Oscillator Enable

LFX_AUTSW_STA (R/W1C)
Status of Automatic Switching of the
LF Mux to LFOSC Upon Detection of
LFXTAL Failure

LFX_EN (R/W)
Low Frequency Crystal Oscillator Enable
HFX_EN (R/W)
High Frequency Crystal Oscillator Enable

LFX_AUTSW_EN (R/W)
Enables Automatic Switching of the
LF Mux to LFOSC on LFXTAL Failure

LFX_BYP (R/W)
Low Frequency Crystal Oscillator Bypass

HFX_OK (R)Status of HFXTAL Oscillator

LFX_MON_EN (R/W)
LFXTAL Clock Monitor and Clock FAIL
Interrupt Enable

LFX_OK (R)Status of LFXTAL Oscillator

LFOSC_OK (R)Status of LFOSC Oscillator

HFOSC_OK (R)Status of HFOSC Oscillator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

LFX_FAIL_STA (R/W)
LFXTAL (Crystal Clock) Not Stable

RESERVED_16_15[1] (R/W)
Reserved Field

ROOT_FAIL_STA (R/W)
Root Clock (Crystal Clock) Not Stable

ROOT_MON_EN (R/W)
Root Clock Monitor and Clock FAIL Interrupt
Enable

ROOT_AUTSW_STA (R/W1C)
Status of Automatic Switching of the
Root Clock to HFOSC Upon Detectionof Root Clock Failure

ROOT_AUTSW_EN (R/W)
Enables Automatic Switching of the
Root Clock to HFOSC on Root Clock
FailureFigure 6-9: CLKG_OSC_CTL Register Diagram

6–20

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_OSC Register Descriptions

Table 6-5: CLKG_OSC_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31 LFX_FAIL_STA(R/W)

LFXTAL (Crystal Clock) Not Stable.
This is a sticky bit. If set, it generates interrupt on the RTC1 IRQ line. It can generateinterrupt during Hibernate or Active modes. If the flag is set in Hibernate mode, thepart will wakeup from Hibernate mode by asserting interrupt on RTC1 IRQ line.
The interrupt and this bit can be cleared by writing 1 to this bit.
1 - LFXTAL (low frequency XTAL clock) is not running. The Crystal connection in
the board to the chip has possible snapped. Or the External clock driver has stopped
giving out clock.
0 - LFXTAL is running fine.

30 ROOT_FAIL_STA(R/W)

Root Clock (Crystal Clock) Not Stable.
This is a sticky bit. If set, it generates interrupt on the IRQ 71 line. It can generateinterrupt during Active mode. The interrupt and this bit can be cleared by writing 1 tothis bit.
1 - Root clock is not running.
0 - Root clock is running fine.

22 ROOT_AUTSW_STA(R/W1C)

Status of Automatic Switching of the Root Clock to HFOSC Upon Detection of RootClock Failure.
This is a sticky bit.This bit indicates whether HW automatically switched Root clockto HFOSC upon detection of Root clock failure. This bit can be cleared by writing 1
to this bit.
0 Indicates HW is not automatically switched to HFOSC
upon detection of Root clock failure
1 Indicates HW automatically switched to HFOSC upondetection of Root clock failure

21 ROOT_AUTSW_EN(R/W)

Enables Automatic Switching of the Root Clock to HFOSC on Root Clock Failure.
This bit is used to enable the Automatic Switching of the Root clock to HF OSC on
Root clock Failure. This feature is valid only when the ROOT clock monitor is enabled.The ROOTCLK_MON_EN bit of the OSCCTRL register should also be set to1, for the proper functionality of the automatic switching of Root clock to HF OSC
clock.
0 Disables Automatic Switching of the Root clock to HF
OSC on Root clock Failure
1 Enables Automatic Switching of the Root clock to HF
OSC on Root clock Failure

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 CLKG_OSC Register Descriptions

Table 6-5: CLKG_OSC_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration

20 ROOT_MON_EN

Root Clock Monitor and Clock FAIL Interrupt Enable.

(Access)(R/W)

If set, the Root clock will be monitored using the 26 MHz HF Oscillator This clock
will be monitored in Active mode. If the Root clock stops toggling for 2.5 us the
ROOTCLK_MON_FAIL flag is set and interrupt is generated on the Root Clock
Failure IRQ line.
If cleared, the Monitor circuit is reset and the Root clock FAIL interrupt is not generated.
0 Root clock Monitor and clock FAIL interrupt disabled
1 Root clock Monitor and clock FAIL interrupt enabled

16:15 RESERVED_16_15

Reserved Field.

(R/W)

Note: ADI kernel writes a value of 3 to these bit fields. These fields are reserved andshould not be modified.

14 RESERVED_14(R/W)
13 LFX_AUTSW_STA(R/W1C)

Reserved Field.
Note: ADI kernel writes a value of 1 to this bit. This field is reserved and should not
be modified.
Status of Automatic Switching of the LF Mux to LFOSC Upon Detection of LFXTAL
Failure.
This bit indicates if hardware is automatically switched to using LFOSC upon detection of LFXTAL failure.
0 Hardware is not automatically switched to LFOSC
upon detection of LFXTAL failure
1 Hardware automatically switched to LFOSC upon detection of LFXTAL failure

12 LFX_AUTSW_EN(R/W)

Enables Automatic Switching of the LF Mux to LFOSC on LFXTAL Failure.
This bit is used to enable the Automatic Switching of the LF Mux to LFOSC onLFXTAL Failure.
0 Disables Automatic Switching of the LF Mux to
LFOSC on LFXTAL Failure
1 Enables Automatic Switching of the LF Mux to LFOSC
on LFXTAL Failure

11 HFX_OK(R/NW)

Status of HFXTAL Oscillator.
This bit indicates when the crystal is stable after it is enabled. This bit is not a monitor
and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use

6–22

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_OSC Register Descriptions

Table 6-5: CLKG_OSC_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10 LFX_OK(R/NW)

Status of LFXTAL Oscillator.
This bit indicates when the crystal is stable after it is enabled. This bit is not a monitor
and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use

9 HFOSC_OK(R/NW)

Status of HFOSC Oscillator.
This bit indicates when the oscillator is stable after it is enabled. This bit is not a monitor and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use

8 LFOSC_OK(R/NW)

Status of LFOSC Oscillator.
This bit indicates when the oscillator is stable after it is enabled. This bit is not a monitor and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use

5 LFX_MON_EN(R/W)

LFXTAL Clock Monitor and Clock FAIL Interrupt Enable.
If set, the LFXTAL clock will be monitored using the on chip 32 kHz low frequency
OSCILLATOR. This clock will be monitored in both Hibernate and Active/Flexi
modes. If the LFXTAL clock stops toggling for 2 ms the LFXTAL_MON_FAIL flag is
set and interrupt is generated on the RTC1 IRQ line.
If cleared, the Monitor circuit is reset and the LFXTAL clock FAIL interrupt is not
generated.
0 LFXTAL Clock Monitor and clock FAIL interrupt disabled
1 LFXTAL Clock Monitor and clock FAIL interrupt enabled

4 LFX_BYP(R/W)

Low Frequency Crystal Oscillator Bypass.
This bit is used to bypass the low frequency crystal oscillator, and if a clock is suppliedexternally on one of the LFXTAL pin. The oscillator must be disabled before setting
this bit.
Disabling LFXTAL can take a while. Ensure that the oscillator is disabled by reading
the LFXTALEN bit and it reads 0.
0 LFXTAL oscillator is disabled and placed in a low powerstate
1 LFXTAL oscillator is enabled

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 CLKG_OSC Register Descriptions

Table 6-5: CLKG_OSC_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 HFX_EN(R/W)

High Frequency Crystal Oscillator Enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable beforeuse.
0 HFXTAL oscillator is disabled and placed in a low power state
1 HFXTAL oscillator is enabled

2 LFX_EN(R/W)

Low Frequency Crystal Oscillator Enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable beforeuse.
0 LFXTAL oscillator is disabled and placed in a low powerstate
1 LFXTAL oscillator is enabled

1 HFOSC_EN(R/W)

High Frequency Internal Oscillator Enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable before
use. This bit must be set before the SYSRESETREQ system reset can be initiated.
0 HFOSC oscillator is disabled and placed in a low powerstate
1 HFOSC oscillator is enabled

0 LFCLK_MUX(R/W)

32kHz Clock Select Mux.
This clock connects to beeper, RTC.
Note: This bit is not reset to default value when soft reset is asserted. Other bits will bereset. This bit will be reset during other reset such as Power-Up, external reset. Program appropriate value when software executes after a soft reset. Soft reset is generated
by setting the AIRCR.SYSRESETREQ bit in the Cortex register .
0 Internal 32 kHz oscillator is selected
1 External 32 kHz crystal is selected

6–24

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_OSC Register Descriptions

Key Protection for OSCCTRL
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (W)
Oscillator Key
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 6-10: CLKG_OSC_KEY Register Diagram
Table 6-6: CLKG_OSC_KEY Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(RX/W)

Oscillator Key.
The CLKG_OSC_CTL register is key-protected with value 0xCB14. The
CLKG_OSC_CTL register should be written after proper key value entered. A write to
any other register on the APB bus before writing to CLKG_OSC_CTL will return theprotection to the lock state.

ADuCM4050 CLKG_CLK Register Descriptions
Clocking registers (CLKG_CLK) contains the following registers.
Table 6-7: ADuCM4050 CLKG_CLK Register List
Name

Description

CLKG_CLK_CTL0

Misc Clock Settings

CLKG_CLK_CTL1

Clock Dividers

CLKG_CLK_CTL2

HF Oscillator Divided Clock Select

CLKG_CLK_CTL3

System PLL

CLKG_CLK_CTL5

User Clock Gating Control

CLKG_CLK_STAT0

Clocking Status

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 CLKG_CLK Register Descriptions

Misc Clock Settings
Clock Control 0 is used to configure clock sources used by various systems such as the core and memories and peripherals. All unused bits are read only returning a value of 0. Writing unused bits has no effect.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

HFXTALIE (R/W)
High Frequency Crystal Interrupt Enable

CLKMUX (R/W)
Clock Mux SelectLFXTALIE (R/W)
Low Frequency Crystal Interrupt Enable

CLKOUT (R/W)
GPIO Clock Out SelectPLL_IPSEL (R/W)
SPLL Source Select Mux

RCLKMUX (R/W)
Flash Reference Clock and HPBUCKClock Source Mux
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 6-11: CLKG_CLK_CTL0 Register Diagram
Table 6-8: CLKG_CLK_CTL0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 HFXTALIE(R/W)

High Frequency Crystal Interrupt Enable.
Controls if the core should be interrupted on a CLKG_CLK_STAT0.HFXTALOK or
CLKG_CLK_STAT0.HFXTALNOK status or if no interrupt should be generated.
This bit should not be cleared while a core interrupt is pending.
0 An interrupt to the core is not generated on a HFXTALOK or HFXTALNOK.
1 An interrupt to the core is generated on a HFXTALOK
or HFXTALNOK.

14 LFXTALIE(R/W)

Low Frequency Crystal Interrupt Enable.
Controls if the core should be interrupted on a CLKG_CLK_STAT0.LFXTALOK or
CLKG_CLK_STAT0.LFXTALNOK status or if no interrupt should be generated.
This bit should not be cleared while a core interrupt is pending.
0 An interrupt to the core is not generated on a LFXTALOK or LFXTALNOK.
1 An interrupt to the core is generated on a LFXTALOK
or LFXTALNOK.

6–26

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-8: CLKG_CLK_CTL0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
12:11 PLL_IPSELSPLL Source Select Mux.

(R/W)

CLKG_CLK_CTL0.PLL_IPSEL selects which source clock is feed to the SPLL.
The selection should be made before the SPLL is enabled. Selection should not bechanged after the SPLL is enabled.
0 Internal HF oscillator is selected
1 External HF XTAL oscillator is selected
2 GPIO_CLK input is selected
3 Reserved

9:8 RCLKMUX(R/W)

Flash Reference Clock and HPBUCK Clock Source Mux.
These bits are to be programmed, when both external crystal and HF oscillator are stable and running. The clock muxed output supplies Flash reference clock and HP buckclock (200 kHz).
If option 11 is programmed, the clock-out is 16 MHz instead of 26 MHz, the dividersof following clocks get auto-configured.
RCLK - divider is bypassed. RCLK = 16 MHz
HPBUCK clock - divider is auto-configured to generate 200 kHz clock
Note: If external XTAL clock is 16 MHz instead of 26 MHz. Then HP Buck nonoverlapping phases increases. This is not recommended if HP buck is enabled.
0 Sourcing from HFOSCCLK - 26 MHz.
Set CLKG_CLK_CTL0.RCLKMUX = 00 if HFOSC(26 MHz) to be the source for HPBUCK divider andflash-reference clock generators.
1 Reserved.
2 Sourcing from external HFXTAL (26 MHz).
Set CLKG_CLK_CTL0.RCLKMUX = 10 if HFXTAL
to be the source for HPBUCK divider and flash reference clock generators and HFXTAL frequency connected to chip is 26 MHz.
3 Sourcing from external HFXTAL (16 MHz).
Set CLKG_CLK_CTL0.RCLKMUX = 11 if HFXTAL
to be the source for HPBUCK divider and flash-reference clock generators and HFXTAL frequency connected to chip is 16 MHz.

6:3 CLKOUT(R/W)

GPIO Clock Out Select.
Selects the clock to be rooted to the GPIO clock out pin.
0 ROOT_CLK

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–27

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-8: CLKG_CLK_CTL0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 LF_CLK
2 ACLK
3 HCLK_BUS
4 HCLK_CORE
5 PCLK
6 RCLK (Ref clock for flash controller timer)
7 RHP_CLK (mux of HF OSC, HF XTAL clock)
8 GPT0_CLK
9 GPT1_CLK
10 HCLK_P (Connects to peripherals operating on
HCLK)
11 PLL out clock
12 RTC0 1 Hz generated clock
13 HPBUCK_CLK
14 HPBUCK_Non_overlap_clk
15 RTC1 1Hz generated clock
1:0 CLKMUX(R/W)

Clock Mux Select.
Determines which single shared clock source is used by the PCLK and HCLK dividers.
Ensure that an enabled active stable clock source is selected(AON_CORE_MUX_SEL).
0 High frequency internal oscillator is selected
1 High frequency external crystal oscillator is selected
2 System PLL is selected
3 External GPIO port is selected

6–28

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_CLK Register Descriptions

Clock Dividers
Clock Control 1 is used to set the divide rates for the HCLK, and PCLK and ACLK dividers. This register can be
written to at any time. All unused bits are read only, returning a value of 0. Writing to unused bits has no effect.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

PCLKDIVCNT (R/W)
PCLK Divide CountHCLKDIVCNT (R/W)
HCLK Divide Count31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

ACLKDIVCNT (R/W)
ACLK Divide Count.

Figure 6-12: CLKG_CLK_CTL1 Register Diagram
Table 6-9: CLKG_CLK_CTL1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
24:16 ACLKDIVCNTACLK Divide Count..

(R/W)

Determines the ACLK rate based on the following equation:
ACLK = ROOT_CLK/CLKG_CLK_CTL1.ACLKDIVCNT.
For example, if ROOT_CLK is 26 MHz and CLKG_CLK_CTL1.ACLKDIVCNT =0x1, ACLK operates at 26 MHz.
The value of CLKG_CLK_CTL1.ACLKDIVCNT takes effect after a write access tothis register and typically takes one ACLK cycle. This register can be read at any timeand can be written to at any time. The reset divider count is 0x10.
Value range is from 1 to 511. Values 0 and 1 have the same results as divide by 1.
Default value of this register is configured such that ACLK = 1.625MHz. The maximum configured ACLK frequency must be 26 MHz.

13:8 PCLKDIVCNT(R/W)

PCLK Divide Count.
Determines the PCLK rate based on the following equation:
PCLK = ROOT_CLK/CLKG_CLK_CTL1.PCLKDIVCNTFor example, if ROOT_CLK is 26 MHz and CLKG_CLK_CTL1.PCLKDIVCNT =0x2, PCLK operates at 13 MHz.
The value of CLKG_CLK_CTL1.PCLKDIVCNT takes effect after a write access tothis register and typically takes 2-to-4 PCLK cycles. This register can be read at any
time and can be written to at any time. The reset divider count is 0x4.
Value range is from 1 to 32. Values larger than 32 are saturated to 32. Values 0 and 1
have the same results as divide by 1.
The default value of this register is configured such that PCLK is 6.5 MHz.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–29

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-9: CLKG_CLK_CTL1 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
5:0 HCLKDIVCNT(R/W)

HCLK Divide Count.
Determines the HCLK rate based on the following equation:
HCLK = ROOT_CLK/CLKG_CLK_CTL1.HCLKDIVCNTFor example, if ROOT_CLK is 26 MHz and CLKG_CLK_CTL1.HCLKDIVCNT =0x1, HCLK operates at 26 MHz.
The value of CLKG_CLK_CTL1.HCLKDIVCNT takes effect after a write access tothis register and typically takes 2 to 4 PCLK cycles (not HCLK cycles). This registercan be read at any time and can be written to at any time. The reset divider count is
0x4.
Value range is from 1 to 32. Values larger than 32 are saturated to 32. Values 0 and 1
have the same results as divide by 1.
Default value of this register is configured such that HCLK is 6.5 MHz.

6–30

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_CLK Register Descriptions

HF Oscillator Divided Clock SelectClock Control 2 is used to select the clock from the frequency divided clocks derived from the hf oscillator clock. All
unused bits are read only, returning a value of 0. Writing to unused bits has no effect.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

HFOSCDIVCLKSEL (R/W)
HF Oscillator Divided Clock Select

HFOSCAUTODIV_EN (R/W)
HF Oscillator Auto Divide by One Clock
Selection During Wakeup from Flexi
Power Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 6-13: CLKG_CLK_CTL2 Register Diagram
Table 6-10: CLKG_CLK_CTL2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
3:1 HFOSCDIVCLKSEL(R/W)

HF Oscillator Divided Clock Select.
Used to select the clock from the frequency divided clocks derived from HFOSC
clock. All unused bits are read only, returning a value of 0. Writing to unused bits has
no effect.
Note: Setting the values for HFOSCDIVCLKSEL from 3'b010 to 3'b101 changes the
flash reference clock RCLK to be less than 13 MHz.
0 Selects the HFOSC/1 clock
1 Selects the HFOSC/2 clock
2 Selects the HFOSC/4 clock
3 Selects the HFOSC/8 clock
4 Selects the HFOSC/16 clock
5 Selects the HFOSC/32 clock
6 Reserved
7 Reserved

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–31

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-10: CLKG_CLK_CTL2 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 HFOSCAUTODIV_EN(R/W)

HF Oscillator Auto Divide by One Clock Selection During Wakeup from Flexi Power
Mode.
Used to enable the fast wakeup from Flexi power mode.
1: Fast wake-up from Flexi mode is enabled
0: Fast wake-up from Flexi mode is disabled
When the fast wakeup from Flexi mode is enabled, the frequency undivided 26 MHz
HFOSC clock itself will be used during the wake up.
The undivided HFOSC clock is selected automatically by clearing the HFOSCDIVCLKSEL bit, which selects the HFOSC/1 clock. This updated divided by 1 clock
selection remains same until the new divider value is written to this register.
If this bit is 0, fast wake-up feature will be disabled and the HFOSCDIVCLKSEL bit
remains unchanged during wake up.
0 Auto select HFOSC/1 clock during wakeup from Flexi
mode is disabled
1 Auto select HFOSC/1 clock during wakeup from Flexi
mode is enabled

6–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_CLK Register Descriptions

System PLL
Clock Control 3 is used to control the system PLL. This register should be written to only when the PLL is notselected as the clock source (ROOT_CLK). All unused bits are read only, returning a value of 0. Writing to unused
bits has no effect.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

1

1

0

1

0

1

1

0

1

0

0

SPLLMSEL (R/W)
System PLL M Divider

SPLLNSEL (R/W)
System PLL N Multiplier

SPLLIE (R/W)
System PLL Interrupt Enable

SPLLDIV2 (R/W)
System PLL Division by 2

SPLLEN (R/W)
System PLL Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SPLLMUL2 (R/W)
System PLL Multiply by 2

Figure 6-14: CLKG_CLK_CTL3 Register Diagram
Table 6-11: CLKG_CLK_CTL3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
16 SPLLMUL2(R/W)

System PLL Multiply by 2.
Used to configure if the VCO clock frequency is multiplied by 2 or 1.
0 PLL out frequency = SPLLNSEL * 1 / ((SPLLDIV2+1)* SPLLMSEL)
1 PLL out frequency = SPLLNSEL * 2 / ((SPLLDIV2+1)* SPLLMSEL)

14:11 SPLLMSEL

System PLL M Divider.

(R/W)

System PLL M Divider. Sets the M value used to obtain the multiplication factor N/Mof the PLL. if CLKG_CLK_CTL3.SPLLMSEL <= 2, Divider M value = 2
For example,
0000: M set to 2 (Div by 2)
0001: M set to 2 (Div by 2)0010: M set to 2 (Div by 2)
0011: M set to 3 (Div by 3)
0100: M set to 4 (Div by 4)1111: M set to 15 (Div by 15)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–33

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-11: CLKG_CLK_CTL3 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10 SPLLIE(R/W)

System PLL Interrupt Enable.
Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt
generated. This bit should not be cleared while a core interrupt is pending.
0 An interrupt to the core will not be generated on a PLL
lock or PLL unlock
1 An interrupt to the core will be generated on a PLL lockor PLL unlock

9 SPLLEN(R/W)

System PLL Enable.
Controls if the PLL should be enabled or placed in its low power state. This bit should
only be set while the System PLL is not selected as the system clock source(CLKG_CLK_CTL0.CLKMUX).
0 PLL is disabled and in power down state
1 PLL is enabled. Initially the PLL will not run at the selected frequency. After a stabilization period the PLL
will lock onto the selected frequency at which time it
can be selected as a system clock source (CLKMUX
bits)

8 SPLLDIV2(R/W)

System PLL Division by 2.
Controls if an optional divide by two is placed on the PLL output. This will guarantee
a balanced output duty cycle output at the cost of doubling the PLL frequency (power). This bit should not be modified after CLKG_CLK_CTL3.SPLLEN is set. Thisbit can be written at the same time CLKG_CLK_CTL3.SPLLEN is set.
This bit is set or reset based on the following constraints:
1. VCO output range is 32 MHz to 60 MHz
2. SPLL output range is 16 MHz to 60 MHz
It is set by default.
0 The System PLL is not divided. Its output frequency
equals that selected by the N/M ratio
1 The System PLL is divided by two. Its output frequency
equals that selected by the N/M ratio with an additional /2 divide

4:0 SPLLNSEL
(R/W)

6–34

System PLL N Multiplier.
Sets the N value used to obtain the multiplication factor N/M of the PLL. The default
value is 0b011010 (Mult by 26). Minimum valid value is 8 and writing any value lessthan 8 will force it to be 8. Maximum valid value is 31. Do not program the SPLL toan output clock lower than 16 MHz or higher than 60 MHz.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_CLK Register Descriptions

User Clock Gating Control
Clock Control 5 is used to control the gates of the peripheral UCLKs.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

0

1

1

1

1

1

0

0

0

0

0

0

TMRRGBCLKOFF (R/W)
Timer RGB User Control

GPTCLK0OFF (R/W)
GP Timer 0 User Control

PERCLKOFF (R/W)
This bit is used to disable all clocks
connected to all peripherals

GPTCLK1OFF (R/W)
GP Timer 1 User Control
GPTCLK2OFF (R/W)
GP Timer 2 User Control

GPIOCLKOFF (R/W)
GPIO Clock Control
UCLKI2COFF (R/W)
I2C Clock User Control
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 6-15: CLKG_CLK_CTL5 Register Diagram
Table 6-12: CLKG_CLK_CTL5 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
6 TMRRGBCLKOFF(R/W)

Timer RGB User Control.
This bit disables the Timer RGB (muxed version). It controls the gate on the Timer
RGB clock in Active and Flexi power modes. In Hibernate and Shutdown modes, theTimer RGB clock is always off, and this bit has no effect.
Note: Automatically clear this bit if Timer RGB is accessed via the APB bus.
0 TMRRGB clock is enabled
1 TMRRGB clock is disabled

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–35

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-12: CLKG_CLK_CTL5 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
5 PERCLKOFF(R/W)

This bit is used to disable all clocks connected to all peripherals.
This is useful to save power during following cases:(i) Processor is not working with any peripherals for a given time.
(ii) DMA transactions like SRAM to SRAM copy or FLASH to SRAM copy (or viceversa).
When this bit is set, following blocks are active:
GPIO, Flash, DMA, Cortex, and SRAM
System status registers for supply monitors, Clock source monitors:
0: Clocks to peripherals are active.
1: Clocks to following peripherals are gated off: SPI, SPORT, CRC, AES, SPI, I2C,
UART, Timers, APB16 bridges, PCLK divider, PM, and CLK register map.
After setting this bit, any read/write to any of the above module register will automatically reset the PERCLKOFF to 0, and that read/write transaction is honored.
Only exception is, after setting this bit to 1, user can read CLKG_CLK_CTL5 register.
This bit will not be automatically cleared in this case.
Recommended usage before setting PERCLKOFF bit:
1. Ensure that DMA transactions are done and no more transaction is expected fromDMA.
2. Ensure that this bit write is last write. And no write/read to any of above module
registers is done after setting this bit. Otherwise, this bit will be cleared.
0 Clocks to peripherals are active
1 Clocks to following peripherals are gated off: SPI,SPORT, CRC, AES, I2C, UART,Timers, APB16
bridges, PCLK divider, PM and CLK register map.

4 GPIOCLKOFF(R/W)

GPIO Clock Control.
This bit disables the Clock to the GPIO block. This control is applicable for Active
and Flexi modes. In Hibernate and Shutdown modes, the clock to GPIO is always off,
and this bit has no effect.
Note: If GPIO registers are accessed via the APB bus this bit will be auto-clear allowing clock to GPIO block.
0 GPIO Clock is enabled
1 GPIO Clock is disabled

6–36

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-12: CLKG_CLK_CTL5 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 UCLKI2COFF(R/W)

I2C Clock User Control.
This bit disables the I2C UCLK. It controls the gate on the I2C UCLK in Active andFlexi modes. In Hibernate and Shutdown modes the I2C UCLK is always off, and thisbit has no effect. Note: will automatically clear this bit if I2C is accessed via the APB
bus.
0 I2C Clock is enabled
1 I2C Clock is disabled

2 GPTCLK2OFF(R/W)

GP Timer 2 User Control.
This bit disables the gptclk2 (muxed version). It controls the gate on the GP Timer 2clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPTclock is always off, and this bit has no effect.
Note: Automatically this bit is cleared, if GPT2 is accessed via the APB bus.
0 TMR2 clock is enabled
1 TMR2 clock is disabled

1 GPTCLK1OFF(R/W)

GP Timer 1 User Control.
This bit disables the gptclk1 (muxed version). It controls the gate on the GP Timer 1
clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPTclock is always off, and this bit has no effect.
Note: Automatically this bit is cleared, if GPT1 is accessed via the APB bus.
0 TMR1 clock is enabled
1 TMR1 clock is disabled

0 GPTCLK0OFF(R/W)

GP Timer 0 User Control.
This bit disables the gptclk0 (muxed version). It controls the gate on the GP Timer 0
clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPTclock is always off, and this bit has no effect.
Note: Automatically this bit is cleared, if GPT0 is accessed via the APB bus.
0 TMR0 clock is enabled
1 TMR0 clock is disabled

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–37

ADuCM4050 CLKG_CLK Register Descriptions

Clocking Status
Clock Status is used to monitor PLL and Oscillator status. With interrupts enabled the user is free to continue torun initialization code or idle the core while clock components stabilize.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

HFXTALNOK (R/W1C)
HF Crystal Not Stable

SPLL (R)
System PLL Status

HFXTALOK (R/W1C)
HF Crystal Stable

SPLLLK (R/W1C)
System PLL LockHFXTAL (R)HF Crystal Status

SPLLUNLK (R/W1C)
System PLL Unlock

LFXTALNOK (R/W1C)
LF Crystal Not StableLFXTAL (R)
LF Crystal Status

LFXTALOK (R/W1C)
LF Crystal Stable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 6-16: CLKG_CLK_STAT0 Register Diagram
Table 6-13: CLKG_CLK_STAT0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14 HFXTALNOK(R/W1C)HF Crystal Not Stable.
This bit indicates the XTAL was successfully disabled. This bit is not associated with
continuous monitoring of the XTAL and will not be set in the event the XTAL becomes unstable. This bit is sticky. Write a 1 to this location to clear it. If enabled, aninterrupt can be associated with this bit.
0 HF crystal stable signal has not been de-asserted.
1 HF crystal stable signal has been de-asserted.

13 HFXTALOK(R/W1C)HF Crystal Stable.
This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1
to this location to clear it.
0 HF crystal stable signal has not been asserted.
1 HF crystal stable signal has been asserted.

6–38

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-13: CLKG_CLK_STAT0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
12 HFXTAL(R/NW)

HF Crystal Status.
This bit assists in determining when the XTAL is initially stable and ready to use. Thisbit does not perform a continuous monitoring function and will not clear in the event
an XTAL becomes unstable.
0 HF crystal is not stable or not enabled.
1 HF crystal is stable.

10 LFXTALNOK(R/W1C)LF Crystal Not Stable.
This bit indicates the XTAL was successfully disabled. This bit is not associated with
continuous monitoring of the XTAL and will not be set in the event the XTAL becomes unstable. This bit is sticky. Write a 1 to this location to clear it. If enabled, aninterrupt can be associated with this bit.
0 LF crystal stable signal has not been de-asserted.
1 LF crystal stable signal has been de-asserted.

9 LFXTALOK(R/W1C)LF Crystal Stable.
This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1
to this location to clear it.
0 LF crystal stable signal has not been asserted.
1 LF crystal stable signal has been asserted.

8 LFXTAL(R/NW)LF Crystal Status.
This bit assists in determining when the XTAL is initially stable and ready to use. Thisbit does not perform a continuous monitoring function and will not clear in the event
an XTAL becomes unstable.
0 LF crystal is not stable or not enabled.
1 LF crystal is stable

2 SPLLUNLK(R/W1C)

System PLL Unlock.
This bit is sticky. CLKG_CLK_STAT0.SPLLUNLK is set when the PLL looses its
lock. CLKG_CLK_STAT0.SPLLUNLK is used as the interrupt source to signal thecore that a lock was lost. Writing a one to this bit clears it.
CLKG_CLK_STAT0.SPLLUNLK will not set again unless the System PLL gains alock and subsequently loses again.
0 No loss of PLL lock is detected
1 A PLL loss of lock is detected

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

6–39

ADuCM4050 CLKG_CLK Register Descriptions

Table 6-13: CLKG_CLK_STAT0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 SPLLLK(R/W1C)

System PLL Lock.
This bit is sticky. CLKG_CLK_STAT0.SPLLLK is set when the PLL locks.
CLKG_CLK_STAT0.SPLLLK is used as the interrupt source to signal the core that alock is detected. Writing a one to this bit clears it. CLKG_CLK_STAT0.SPLLLK
will not set again unless the System PLL looses lock and subsequently locks again.
0 No PLL lock event is detected
1 A PLL lock event is detected

0 SPLL(R/NW)

System PLL Status.
Indicates the current status of the PLL. Initially the System PLL will be unlocked. After a stabilization period the PLL will lock and be ready for use as the system clock
source. This is a read only bit. A write has no effect.
0 PLL is not locked or not properly configured. The PLL
is not ready for use as the system clock source.
1 PLL is locked and is ready for use as the system clock
source.

6–40

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceReset (RST)

7 Reset (RST)The ADuCM4050 MCU has the following resets:• External• Power-on• Watchdog timeout• Software system
The software system reset is provided as part of the Cortex-M4F core.
To generate a system reset through software, the application interrupt/reset control register must be set to a value of
0x05FA0004. This register is part of the NVIC subsystem and is located at address 0xE000ED0C.
For more information about software reset, refer to the ARM Cortex-M4F Technical Reference Manual.
A hardware reset is performed by toggling the SYS_HWRST pin, which is active low.
The PMG_RST_STAT register indicates the source of the last reset. The register can be used during a reset exception service routine to identify the source of the reset.
Table 7-1: Reset Types
Reset

Reset External Pins
to Default
State

ExecuteKernelReset All MMRs Except
PMG_RST_STAT

Reset All Pe- Valid SRAM
ripherals

Software

Yes*1

Yes

Yes

Yes

Yes/no*2

PMG_RST_STAT.SWRST = 1

Watchdog

Yes

Yes

Yes

Yes

Yes/no*2

PMG_RST_STAT.WDRST = 1

External reset pin Yes

Yes

Yes

Yes

Yes/no*2

PMG_RST_STAT.EXTRST = 1

POR

Yes

Yes

Yes

No

PMG_RST_STAT.POR = 1

Yes

PMG_RST_STAT After Reset
Event

PMG_RST_STAT.PORSRC has
info on cause of POR reset*1

GPIOx returns to its default state, that is, same as a POR event.

*2

RAM is not valid in the case of a reset following a UART download.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

7–1

ADuCM4050 Reset Register Description

ADuCM4050 Reset Register Description
Table 7-2: ADuCM4050 Reset Register List
Name

Description

Reset

Access

PMG_RST_STAT

Reset Status

0x000000XX

R/W

7–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Reset Register Description

Reset Status
This register is recommended to be read at the beginning of the user code to determine the cause of the reset. Default values of this register is unspecified as the cause of reset can be any source.
15 14 13 12 11 10

9

8

7

6

5

0

0

0

0

0

X X X X X X

0

0

0

0

0

4

3

2

1

0

PORSRC (R)Power on reset Source

POR (R/W)
Power-on reset

SWRST (R/W)
Software reset

EXTRST (R/W)
External reset

WDRST (R/W)
Watchdog timeout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 7-1: PMG_RST_STAT Register Diagram
Table 7-3: PMG_RST_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5:4 PORSRC(R/NW)

Power-on-Reset Source.
This bit contains additional details after a Power-on-Reset occurs.
0 POR triggered because VBAT drops below Fail Safe
1 POR trigger because VBAT supply (VBAT < 1.7 V)
2 POR triggered because VDD supply (VDD < 1.08 V)
3 POR triggered because VREG drops below Fail Safe

3 SWRST(R/W)
2 WDRST(R/W)
1 EXTRST
(R/W)
0 POR
(R/W)

Software Reset.
Set automatically to 1 when the system reset is generated. Cleared by writing 1 to thebit. This bit is also cleared when power-on-reset is triggered.
Watchdog Time-out Reset.
Set automatically to 1 when a watchdog timeout occurs. Cleared by writing 1 to thebit. This bit is also cleared when power-on-reset is triggered
External Reset.
Set automatically to 1 when an external reset occurs. Cleared by writing 1 to the bit.
This bit is also cleared when power-on-reset is triggered
Power-on-Reset.
Set automatically when a Power-on-Reset occurs. Cleared by writing one to the bit.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

7–3

Flash Controller (FLASH)

8 Flash Controller (FLASH)

The ADuCM4050 MCU includes 512 KB of embedded flash memory available for access through the flash controller. The embedded flash has a 72-bit wide data bus providing two 32-bit words of data and one corresponding 8bit ECC byte per access.
The flash controller is coupled with a cache controller module, which provides two AHB ports:• DCode for reading data
• ICode for reading instructions
A prefetch mechanism is implemented in the flash controller to optimize ICode read performance.
Flash writes are supported by a key hole mechanism through APB writes to memory mapped registers. The flash
controller includes support for DMA based key hole writes.

Flash Features
The flash memory used by the ADuCM4050 MCU has the following features:• Prefetch buffer provides optimal performance when reading consecutive addresses on the ICode interface.
• Simultaneous ICode and DCode read accesses (DCode has priority on contention; simultaneous reads are possible if ICode returns buffered data from prefetch).
• DMA based key hole writes (including address auto-increment for sequential accesses).
• ECC for error correction and/or detection. Errors and corrections may be reported as Bus Errors (on the
ICode/DCode buses), interrupts, or ignored.

Supported Commands• Read: Supported through the ICode and DCode interfaces.
• Write: Provided by a key-hole mechanism through memory mapped registers.
• Mass erase: Clears all user data and program code.
• Page erase: Clears user data and/or program code from a 2 KB page in flash.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–1

Flash Features• Signature: Generate and verify signatures for any set of contiguous whole pages of user data and/or programcode.
• Abort: Terminate a command in progress.

Protection and Integrity Features• Fixed user key required for running protected commands including mass erase and page erase.
• Optional and user definable Write protection for user accessible memory.
• 8-bit Error Correction Code (ECC).

Flash Functional Description
This section provides information on the flash memory functions used by the ADuCM4050 MCU.

Organization
The flash IP provides a 64-bit data bus and 8 bits for ECC meta data corresponding to that data. The memory isorganized as a number of pages, each 2 KB in size plus 256 bytes reserved for ECC.
One Page

ECC
256B

Data
2KB

8 bits

64 bits

256

Figure 8-1: One Page of Flash Memory

These pages of memory are categorically divided into two sections: Info Space and User Space. Total device storageis generally described as the size of User Space.

8–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceFlash Functional Description

0x0008_0FFF

Info Space
4 KB

2 pages

User Space
512 KB

256 Pages

0x0008_0000
0x0007_FFFF

0x0000_0000

Figure 8-2: Flash Info and User Spaces

Info Space is reserved for use by Analog Devices and generally stores a boot loader (kernel), several trim and calibration values, and other device specific meta data. Most of info space is left readable by user code but attempted erasures and writes are denied.
User Space is the portion of flash memory intended for user data and program code. Several small address ranges inuser space are used by the flash controller as meta data to enable various protection and integrity features.
Info Space
User Accessible Data
While Info space is generally reserved for use only by Analog Devices, 32 bytes of data in addess space
0x0008_0EE0 to 0x0008_0EFF can be read by user code and the following table summarizes the information stored
therein.
Table 8-1: List of User Accessible Parameters in Device Information Space
Address Range

Size

Description

0x0008_0EF0 to 0x0008_0EFF

128 bits (16 bytes)

Unique ID

0x0008_0EE4 to 0x0008_0EEF

96 bits (12 bytes)

Manufacturer ID

0x0008_0EE0 to 0x0008_0EE3

32 bits (4 bytes)

Revision number of kernel

The 256 bytes of device information space in address space 0x0008_0F00 to 0x0008_0FFF are protected and cannot be read by user code (attempted reads return bus errors). None of info space may be programmed or erased by
the user (command is denied).
Bus errors are generated if user code attempts to read the protected range of info space. Writes and Erases targeting
info space are denied and appropriate bits are set in the FLCC_STAT register.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–3

Flash Functional Description

User code may perform a Mass Erase command on the part without affecting the content of the Info Space. This
provides a mechanism to upload new user firmware and data to a device without affecting ADIs secure boot loader.
User Space
User Space is the portion of flash memory intended for user data and program code. Several small address ranges inuser space are used by the flash controller as meta-data to enable various protection and integrity features.
Protected Key Storage
The top two pages of User Space are reserved for use as a Protected Key Storage region. These two pages exist inside
the physical User Space but are neither directly accessible to the user nor controlled by any of the user facing flash
controller features (such as Write Protection).
0x0007_FFFF

Protected Key Space
4 KB

2 pages

0x0007_F000
0x0007_EFFF

Available User Space508 KB

254 Pages

0x0000_0000

Figure 8-3: Dedicated Pages Reserved for Protected Key Storage (Parts with 512 KB User Space)

All user access and control functions for the Protected Key Storage region are provided by the Cryptographic module.
Any attempts to access this region, directly generates appropriate failures:• Commands: Command issued which targets this region will result in a command failure code in the status register and will have no effect on the flash memory.
• ICode: Any attempt to branch to this memory region as instruction code will result in bus faults and will otherwise not cause the flash controller to access the requested address.
• DCode: Any attempt to read this region as direct AHB memory reads will result in bus faults and will otherwise not cause the flash controller to access the requested address.
Meta Data
8–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceFlash Functional Description

ADI secure bootloader enforces various security features which are controlled by the user through writing metadata
into software defined locations of User Space.
There are two types of metadata that specifically affect the flash controller: CRC checksums and Write Protection
settings.
• Write Protection: Flash address 0x0000_019C
ADI secure bootloader defines a single address from which it will consume a value and store it into the
FLCC_WRPROT register of the flash controller prior to user code executing. User may populate this flash location with whatever default FLCC_WRPROT value is desired.
• CRC Checksums
The most significant word of each flash page may be used to store a CRC Checksum, also known as a Signature. The flash controller implements a sign checking feature such that software may request the signature forany contiguous set of whole pages to be verified; the expected signature must be stored by user code in the mostsignificant word of the region over which the signature is calculated.
ADI secure bootloader enforces signature checking from page zero through a user defined end-page prior to
executing user code. The bootloader consumes metadata from page zero of user space to determine the endpage used in signature verification. This value is known as User Code Length and is stored at address
0x0000_0194.
Store a value in the range 0 through 255 to the User Code Length address, indicating the end-page used forsignature generation. User must also populate the required signature value in the most significant word of theend-page indicated.
The signature address is calculated as:
SIG_ADR=[(PageID+1)*(0x800)-4]
where, PageID is the value stored to User Code Length.
For example, if PageID=0, SIG_ADR is 0x7FC.
Avoid corrupting the ECC byte associated with signature values by refraining from writing the adjacent flash
word at [SIG_ADR-4].

Flash AccessTwo pages of flash memory are reserved as a dedicated protected key storage region. All access to this region is performed indirectly through the cryptographic block. Access to all other regions of flash memory are performed directly through the flash controller through one of three interfaces: ICode, DCode, and APB.
These two access methods (direct and indirect) only affect the APB interface and are implemented in a mutually
exclusive manner to maintain coherency in software and provide required security features for the protected key storage region.

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Flash Functional Description

Table 8-2: Indirect Access Vs Direct Access
RegisterDirect Access

Indirect Access

Status Register

R/W

Read-only

Other Registers

R/W

No accessIn indirect access mode, user code may read the status register but register writes or reads of other registers are notenabled. Attempt to write to any register has no effect. Read to any register other than the status register returns astatic data not related to the flash controller.
ICode and DCode interfaces are not affected by active access mode. These interfaces are logically part of direct access mode but normally continue servicing direct access reads at all times.
When IDLE, the flash controller is effectively in direct access mode. Indirect accesses are requested by user code
through register writes in the Cryptographic block. The flash controller switches between direct and indirect accessmodes only. It is otherwise IDLE (at the completion of any pending command). Therefore, indirect access requests
are stalled when the flash controller is busy executing a direct access command.
User code must treat indirect accesses as a critical software region only to be executed when the flash controller is not
be expected to service any APB traffic (reads or writes of memory mapped registers including the command register
used to write, program, or erase flash memory). The most significant bit of the Status register indicates the current
access mode (0x0=Direct).
Indirect Access: Protected Key Storage
User Space includes a pair of pages reserved for use as a protected key storage region. User access to these pages isprovided only indirectly via the Cryptographic module. User code may perform any of the following operations inthis region:• WRITE: Store a key to the dedicated key storage region• DESTROY: Destroy a single key in the dedicated key storage region• READ: Retrieve a single key from the dedicated key storage region• ERASE: Perform a page erase operation on either page in this dedicated region
While the cryptographic module services any of the above requests, the flash controller continues to service ICodeand DCode requests, stalling as required while the flash memory is busy and therefore enabling user code to transparently execute from flash memory while interacting with the key storage region.
If indirect access is made to the protected key storage region while the flash controller is in sleep mode, the flash
controller automatically wakes up to process the request. User code has to return the flash controller to sleep mode,
if required.
While indirect protected key storage accesses are being serviced the flash controller ignores the ABORT_EN registersettings. Indirect flash accesses cannot be aborted by user code or interrupts. It is suggested that user code utilize

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceFlash Accesssemaphores or equivalents to treat indirect flash accesses as critical code segments during which no other flash accesses is attempted. ICode and DCode direct accesses are serviced during indirect accesses but performance may be
reduced.
The flash controller’s status register is automatically cleared while servicing indirect accesses.
Direct Access
Flash memory may be read, written, and erased by user code. Read access is provided through dedicated instruction
and data memory busses via the cache controller. Write access is provided through key hole writes via memory mapped registers including support for DMA based writes.
Read Path
AHB icode
AHB dcode

Cache
Controller

Custom Interface

Flash
Controller

APB

Write Path

Figure 8-4: Read and Write Data Paths

Bus errors are generated if user code reads from a protected or out of bounds address. Writes or Erasures of protected
addresses result in appropriate error flags set in the FLCC_STAT register. Address setup for writes and erasures is
automatically constrained to the flash address range.
Reading FlashThe flash controller provides two interfaces for reading non-volatile storage: ICode and DCode.
The ICode and DCode interfaces are accessed through the cache controller module through AHB. The flash controller includes a prefetch buffer for ICode. Due to this prefetch buffer, it is possible to return data on both ICodeand DCode interfaces in the same cycle.
Flash memory is available to be read only after an automatic initialization process. Attempts to read during the flash
controller initialization will stall. Reads also stall if the flash controller is already busy performing another command(for example, writing the flash) unless those reads are satisfied by the prefetch buffer.
Erasing FlashThe flash controller provides page-level granularity when erasing user space (ERASEPAGE command). Alternatively,
user code may erase the entirety of user space at once (MASSERASE command). The two commands have the same
execution time.
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Flash Access

Write protected pages cannot be erased; the command would be denied. If any pages are write protected, a masserase command is also be denied. Users wishing to write protect user space and planning to perform mass erases (forexample, for future firmware upgrades) must take this into consideration.
Writing FlashFlash memory operates by setting bits to 1 when erased, and clearing them to 0 when writing data. Any generalized
write accesses must be prefixed by an Erase operation.
Initial uploading of user content generally occurs immediately following a Mass Erase operation.
Subsequent modifications of already-written locations in the flash involve the following operations by the user code:• Copying a full page to SRAM
• Erasing the affected page
• Modifying the in-memory content• Writing the page back to flash
User Space protections may prevent a page erase operation. For more information about this, refer to Protection andIntegrity.
All User Space protections are cleared automatically after a successful Mass Erase or Blank Check (a blank checkpasses only if the entire user space is already erased). In these two cases, there is no user space content to protect.
Key Hole Writes
A key hole write is an indirect write operation where the user code programs the memory mapped registers withtarget Address and Data values, then commands the flash controller to perform a write operation in the background.
The flash controller supports Write access to the flash memory only through key hole writes. This constraint on
Write access enables the flash controller to guarantee that writes occur properly as atomic DWORD (64-bit) operations with an associated ECC byte.
Multiple writes to a single DWORD (64-bit) location cannot be performed without erasing the affected page between writes else ECC errors are reported.
A maximum of one write is permitted to a single flash location (64-bit DWORD) between erasures. Writing any
location more than once per erasure may result in ECC errors.
Key hole operations consist of writes to:• FLCC_KH_ADDR.VALUE: The target address in flash (for example, 0x104). The flash controller automatically trims the lower bits to make the address DWORD aligned.
• FLCC_KH_DATA0.VALUE: Bits [31:0] of the 64-bit DWORD to be written (for example, 0x7654_3210).
• FLCC_KH_DATA1.VALUE: Bits [63:32] of the 64-bit DWORD to be written (for example,
0xFEDC_BA98).
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceFlash Access• FLCC_CMD.VALUE: Assert the write command (0x4) in the flash.
After the write command is asserted, the flash controller initiates a 64-bit dual word write to the address provided in
FLCC_KH_ADDR.VALUE.
User code must not write to any of these key hole registers when DMA access is enabled (FLCC_UCFG.KHDMAEN
is set). Writing to these registers manually when DMA is enabled may result in spurious flash writes and can put the
DMA and flash controller out of sync, potentially hanging the DMA controller for long duration (~20 to 40 μs).
Burst Writes
Each 2 KB page of flash memory consists of eight rows, 256 bytes each. Design constraints for programming the
flash IP enable back-to-back writes within a single row to complete more quickly than the equivalent writes acrossrow boundaries. For optimizing writes, user code must attempt to write flash memory in (aligned) blocks of up to
256 bytes.
Table 8-3: Flash Addressing by Rows
0x7FFFC

0x7FFF8...

0x7FF04

0x7FF00

...

...

...

...

...

0xFC

0xF8

...

0x4

0x0

To benefit from this write-performance gain, the second (and subsequent) 64-bit write must be requested before theflash controller completes the first write. The flag FLCC_STAT.WRALCOMP is set when the first 64-bit write operation is nearing completion (~20 μs remaining in the write cycle). This provides user code with a manageable window of time in which to assert the next write request. This flag may be polled or an interrupt may optionally begenerated when it is asserted.
The following status flags are also available:• FLCC_STAT.CMDBUSY: High when the controller is processing a command from the FLCC_CMD register.
• FLCC_STAT.WRCLOSE: High during the first half of a write command, cleared when key hole registers arefree to be programmed for a subsequent write command.
• FLCC_STAT.CMDCOMP: Sticky flag, set when a command is completed (write, erase and so on). Write one
to clear.
• FLCC_STAT.WRALCOMP: Sticky flag, set when ~20-40 μs remains for an ongoing write command. Write
one to clear.
The following steps describe how to perform multiple writes with the potential to burst within a row:
• Wait for command busy flag to clear (to ensure on prior command is ongoing).
• Disable all interrupts so that sequenced writes to FLCC_KH_ADDR, FLCC_KH_DATA0, FLCC_KH_DATA1,
and FLCC_CMD registers are not interrupted by an ISR which might also have flash writes.
• Request first 64-bit write through the key hole access.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–9Flash Access• The flash controller starts the write process after the write command is written to the FLCC_CMD register.
• Check if the write command is accepted (read FLCC_STAT register to see if any error flags are set. If the command results in an error, the write is not performed).
• Set the FLCC_IEN.WRALCMPLT bit (to enable interrupt generation when WrAlComp is asserted) and reenable other interrupts.
• Continue the user program. WrAlComp interrupt will vector to an interrupt service routine to request the next
write at appropriate time.
• Burst Write ISR: Interrupt service routine (ISR) called when n interrupt is generated by WrAlComp.
• Disable all interrupts so that sequenced writes to FLCC_KH_ADDR, FLCC_KH_DATA0, FLCC_KH_DATA1,
and FLCC_CMD registers are not interrupted by another ISR which may also have flash writes.
• Read the FLCC_STAT register to verify the state of several status flags. Clear the flags by writing back thesame value:• FLCC_STAT.WRALCOMP: The flag must be set indicating that there is still time for the next write tooccur for a Burst Write.
• FLCC_STAT.CMDBUSY: The flag must be set indicating that the current write operation is still on-going.
• FLCC_STAT.CMDCOMP: The flag must not be set. This bit indicates that a command had already completed and therefore the command currently in progress is not the earlier write command (another function has initiated a new command).
• FLCC_STAT.WRCLOSE: The flag must not be set. If set, the key hole registers are closed and cannot be
written. This flag must clear when FLCC_STAT.WRALCOMP is asserted.
• If no further writes are required, wait for FLCC_STAT.CMDCOMP to be set, clear it, and then exit the subroutine.
• Request the next 64-bit dualword write through the key hole access (write FLCC_KH_ADDR,FLCC_KH_DATA0, FLCC_KH_DATA1, and FLCC_CMD registers).
• Check if the write command was accepted (read the FLCC_STAT register to see if any error flags are set).
• Re-enable interrupts.
• Exit the ISR.
If possible, user code with several write accesses to flash must be executed from SRAM to prevent thrashing the
flash. Write operations cause ICode reads to stall, resulting in degraded performance when ICode access is required
to fetch the next instruction (this may be partially alleviated by the cache controller).
Note that during a Burst Write, the flash controller overlaps the write operations and therefore any reported write
failures (for example, access denied due to write protection) may reflect the status of either of the two overlapped

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceFlash Accesswrites. User code must interpret a Burst Write failure as a failure for both writes being overlapped (that is, both thecurrent and the prior write requests).
DMA Writes
Key hole writes generally require writing four memory-mapped registers per flash write access. An optional address
auto-increment feature may reduce the APB traffic required per flash write transaction to three register writes(FLCC_KH_DATA0, FLCC_KH_DATA1, and FLCC_CMD) for all but the first in a series of sequential writes (firstwrite requires setting up the start address). DMA Writes reduces the number of APB transactions to two: every pairof FLCC_KH_DATA0 and FLCC_KH_DATA1 registers writes results in a single flash write command executing
and the address automatically incrementing to the next DWORD (regardless of the value of auto-increment, DMA
writes always increment in the address this manner).
To perform DMA based writes, user code must first configure the DMA controller (a separate peripheral module)
for basic access (this DMA mode supports transferring data to/from peripherals, including the flash controller).
Once the DMA controller module has been configured, it will sit IDLE until a DMA_REQ signal is asserted by the
flash controller.
The user code must manually write FLCC_KH_ADDR to setup the initial target address for DMA writes. The DMA
controller must be configured to write all output data to FLCC_KH_DATA1. Each pair of DMA writes to
FLCC_KH_DATA1 execute a single flash write command and wait for a corresponding delay before the next
DMA_REQ is made.
To start the flash controller process of requesting data from the DMA controller, the flash controller must be configured for DMA access. To enable DMA mode, user code must set the FLCC_UCFG.KHDMAEN bit.
Once the DMA mode is enabled (and flash controller is IDLE), the flash controller drives the DMA_REQ signal to
the DMA module. DMA_REQ is driven at the appropriate time to support Burst Writes (new requests are madeonce the current write operation is nearly complete).
For more information about DMA functionality, refer to Direct Memory Access (DMA).
Command Abort
Some flash commands result in long-duration processes. For example, erasures may take 20-40 ms (depends on the
FLCC_TIME_PARAM0 register). A critical or time-sensitive event, such as a low-voltage alarm, may occur while
the flash controller is busy processing such a long-duration command. In such scenarios, it may be necessary for theuser to abort an ongoing flash command to properly handle the critical event.
Command abort should be used sparingly and as a last resort to satisfy critical time-sensitive events. Aborting any
flash command results in prematurely ending the current flash access and may result in corrupted flash data or, inrare cases, damage to the flash array itself. The flash controller attempts to minimize the opportunity for data corruption of flash damage by aborting commands at opportune moments and such that internal high voltage is safely
drained prior to subsequent flash accesses. For this reason a command may complete successfully despite an attempt
to abort it.
Two mechanisms are provided to abort ongoing flash commands:
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Flash Functional Description• Command Register
An abort command may be issued by writing the command register in the same manner used to issue any otherflash command. Once the abort command has been issued any ongoing command will be aborted at the next
opportune moment.
• System Interrupt Abort
The flash controller is sensitive to the system interrupt bus. User code may write to the IRQ Abort Enableregisters to program the flash controller to automatically abort any ongoing command in the event of a matching interrupt. The IRQ Abort Enable registers enable selecting any system IRQ from 0 through 63.

Protection and Integrity
Integrity of Info Space
User Code does not have any control over the content of Info Space. If this integrity check fails on a Power-onReset, it will be attempted repeatedly until a preset number of attempts has occurred or the integrity check passes(this provides some recoverability from power faults occurring during device power-up). For all other resets (except
software reset which does not re-initialize the flash controller), the integrity check is attempted just once.
In the event of an info space integrity check failure, it is expected that the part has failed and will either be disposedof or returned to ADI for failure analysis. If the Info Space integrity check does not pass, the flash controller enters a
special purpose debugging mode. In this mode, User Space protection is automatically asserted and the flash controller's local JTAG protection is set to allow Serial Wire Debug (SWD) interface to interact with the ICode, DCodeand APB interfaces.
In this special purpose debugging mode:• All ICode reads return Bus Errors (code is not executed from the flash memory without passing the integrity
check).
• All DCode reads to User Space returns Bus Errors.
• All DCode reads to Info Space except the top 256 bytes are permitted. Reads of the top 256 bytes return Bus
Errors.
• All write commands are denied (write attempts set the appropriate error bits in the FLCC_STAT register).
• User Space protections may be bypassed only by satisfying the security requirements.
The status of the signature check after reset is read from the FLCC_STAT.SIGNERR bit. The status of ECC during signature check is available in the FLCC_STAT.ECCINFOSIGN bit. These values are read through a normal
SWD read if the SWD interface is enabled.
User Space Protection
Two layers of user space protections are provided:

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProtection and Integrity• Access Protection: Protects user space from all read or write operations. This protection mechanism may be
manually triggered but is typically automatically asserted in the event of system failure and/or the Serial Wire
Debug interface being enabled.
• Write Protection: User facing feature enabling blocks of user space pages to be protected against all write orerase commands. May be set by user at runtime or by ADIs secure bootloader (user would store the desired
value in flash for the boot loader to consume during boot).
Access Protection
Access Protection is meant to prevent third parties from reading or tampering user data and program code through
JTAG or Serial Wire. Access Protection applies to the entirety of User Space. Access Protection is enabled by one of
the following events:• Serial Wire Debug is enabled• Flash Initialization (info space sign check) fails
The first two enabling mechanisms are automatic features; user code does not have to configure or enable anything
for these mechanisms to enable/enforce Access Protection.
While Access Protection is enabled all User Space reads return Bus Errors, writes are denied, and erases are subject to
the FLCC_WRPROT.WORD bit.
Access Protection may be bypassed by successfully executing a MASSERASE or BLANKCHECK command. Notethat the MASSERASE command is disallowed in the event that the FLCC_WRPROT (Write Protection) register has
been modified from its reset value. BLANKCHECK command is always permitted to execute but will only passsuccessfully if all of User Space is already in an erased state.
Write Protection
User definable regions of User Space may be configured such that the flash controller will deny any attempts tomodify them (this affects both WRITE and ERASE commands). Write Protection may be configured at runtime or
may be stored in User Space meta-data to be loaded by the ADI secure bootloader during device boot.
NOTE: MASSERASE command is disallowed if any of the bits in the FLCC_WRPROT register have been modified
from the default value.
Runtime Configuration
Write Protection is configured by modifying the FLCC_WRPROT memory mapped register.
FLCC_WRPROT.WORD is a 32-bit wide bit field representing the Write Protection state for 32 similar size blocks ofUser Space pages. For 512 KB parts the flash memory is divided into 256 pages of User Space storage. For Write
Protection, these are logically divided into 32 blocks of 8 pages (16 KB) each. Write Protection is independently
controlled for each of these 32 blocks; each bit of FLCC_WRPROT.WORD controls the protection mechanism for aunique block of 8 pages of User Space. The least significant bits of FLCC_WRPROT.WORD correspond to the leastsignificant pages of User Space.

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Protection and Integrity

The bits in the FLCC_WRPROT register are active low. 0 represents active Write Protection and 1 represents noprotection for the corresponding block of pages. The FLCC_WRPROT register is sticky at 0. Once protection is enabled, it cannot be disabled without resetting the device.
User code may assert write protection for any block of pages by clearing the appropriate bit of
FLCC_WRPROT.WORD at any time. User must assert write protection as early as possible in user code. User mustalso write-protect block zero (that is, flash pages 0-3) and place user boot and integrity checking code in this block
to fully control the write protection scheme without relying on ADI bootloader to setup the FLCC_WRPROT register.
Meta Data Configuration
User Space contains a single 32-bit field representing a set of 1-bit Write Protect flags for each of these 32 logicalblocks (see User Space), matching the functionality of the FLCC_WRPROT register.
These Write Protection bits are read from the flash by ADIs secure bootloader and stored in the FLCC_WRPROT
register after a reset operation. The default (erased) state of flash memory is all 1s, therefore the default
FLCC_WRPROT register value is to disable protection for all pages in User Space. Each bit of
FLCC_WRPROT.WORD corresponds to the protection state for one block of four User Space pages.
User code may clear bits in the write protection word from the user flash address (address 0x0000019C), also known
as WrProt meta data word at run time, or this word may be included in the initial upload of user data and programcode. Writing the WrProt meta data word at run time does not immediately affect the Write Protection state; if
immediate protection is required, user code should also write the same values to the FLCC_WRPROT register. When
writing the WrProt meta data the user should consider including Write Protection of the most significant page (thusprotecting the meta data from a page erase or other modification).
Once protection has been enabled (corresponding bit has been cleared in FLCC_WRPROT.WORD) it cannot be disabled without resetting the device. For this reason, once Write Protection has been enabled for any block of pages
through the User Space meta data, it cannot be disabled without erasing the most significant page of User Space (thepage hosting the relevant meta-data) or otherwise affecting the flow of ADIs secure bootloader.
The following sequence outlines the process of programming the Write Protection meta data word in flash:• Ensure that the FLCC_WRPROT address of the user space has been erased since the last time the meta-data is
written.
• Write the desired value for the WrProt meta-data word directly to flash (write '0' to a particular bit to enable
protection for the corresponding block).
• Verify that the write completed successfully by polling the status register.
• If using CRC signature checking on the affected page, user code must program the signature• Reset the device. The WrProt bits will automatically be uploaded by the ADI secure bootloader from user space
to the FLCC_WRPROT register and used to enforce the protection scheme.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProtection and Integrity

Signatures
Signatures are used to check the integrity of the flash device contents. Signature calculations do not include the ECC
portion of the flash data bus nor the most significant word read from the set of pages being signed (this word isconsidered meta data and is meant to hold the expected signature value for the given set of pages).
The flash controller implements its own stand-alone CRC engine for generating and verifying signatures. Note however that this implementation matches the CRC Accelerator peripheral (with an initial value of 0xFFFF_FFFF). For
more information about the CRC algorithm used, refer to Cyclic Redundancy Check (CRC).
Signatures may be included in the initial upload of user data and program code (generated before being uploaded),or may be generated and stored to flash at runtime. Generation at runtime may utilize either the CRC Accelerator orcall the flash controller's signature generation logic.
ECC bytes correspond to 64-bit DWORDS in the flash memory, therefore the most significant 64 bits (including
the 32-bit signature word) must be written all at once (else the ECC byte gets corrupted by the second write). If
using the flash controller to generate the signature value, leave the unused 32 bits paired with the signature word intheir erased state (0xFFFF_FFFF). Else, it may result in spurious ECC errors after device reset (depending on
FLCC_WRPROT configuration) and the device may become unusable.
The Sign command generates a signature for all data from the start page to the end page (excluding the signature
meta-data word). User code must define the start and end pages by writing FLCC_PAGE_ADDR0.VALUE and
FLCC_PAGE_ADDR1.VALUE respectively.
The following procedure must be followed to generate or verify a signature:• Write to FLCC_PAGE_ADDR0.VALUE: Start address of a contiguous set of pages (if out of bounds, the command is denied).
• Write to FLCC_PAGE_ADDR1.VALUE: End address of a contiguous set of pages (if out of bounds, the command is denied).
• Write to FLCC_KEY.VALUE: Write the User Key value (0x676C7565) to the FLCC_KEY register.
• Write to FLCC_CMD.VALUE: Write the SIGN command (0x3) to the FLCC_CMD register.
• WAIT: When the command is completed, FLCC_STAT.CMDCOMP bit is set.
• If using the flash controller to generate a signature to write into the flash meta-data, the signature value
may be read from the FLCC_SIGNATURE register.
• The generated signature is automatically compared with the data stored in the most significant 32-bit
word of the region being signed. If the generated result does not match the stored value, a fail is reported
in the FLCC_STAT register by asserting verify error in the FLCC_STAT.CMDFAIL bit field (0x2).
While the signature is being computed all other accesses to the flash are stalled. Generating/verifying the signature
for a 512 KB block (full User Space) results in a stall duration of 64 KB flash reads (64 bits per read operation) orapproximately 128k HCLK periods.

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Protection and Integrity

NOTE: FLCC_PAGE_ADDR0.VALUE and FLCC_PAGE_ADDR1.VALUE addresses may be written as byte addresses but are consumed by the flash controller as page addresses (the lower 10 address bits are ignored). SIGN
command is denied if FLCC_PAGE_ADDR1.VALUE is less than FLCC_PAGE_ADDR0.VALUE. Signatures arealways performed at a page-level granularity over continuous address ranges.
Key Register
To prevent spurious and potentially damaging flash accesses, some commands and registers are key protected. The
User Key is not a security element and is not meant to be a secret. Instead, this key protects users from negative
consequences of software bugs (especially during early software development).
User KeyIt prevents accidental access to some flash features and addresses. The key value is 0x676C_7565. This key must beentered to run protected user commands (ERASEPAGE, SIGN, MASSERASE, and ABORT), or to enable write
access to the FLCC_UCFG or FLCC_TIME_PARAM0 and FLCC_TIME_PARAM1 registers. Once entered, thekey remains valid until an incorrect value is written to the key register, or a command is written to the FLCC_CMD
register when any command is requested this key is automatically cleared. If this key is entered to enable write accessto the FLCC_UCFG or FLCC_TIME_PARAM0 and FLCC_TIME_PARAM1 registers, clear the key immediately
after updating the register(s).
ECC
The flash controller provides ECC based error detection and correction for flash reads. ECC is enabled by default
for Info Space, and thus provides assurance that flash initialization functions work properly (info space signaturecheck unconditionally takes ECC into account).
The flash controller uses an 8-bit Hamming-modified code to correct 1-bit errors or detect 2-bit errors for any dualword (64-bit) flash data access.
The ECC engine is active during signature checks (refer to Signatures section). User code may request a signaturecheck of the entirety of User Space then check the FLCC_STAT.ECCERRCMD bit to determine if any single ordual bit data corruptions are present in User Space.
Defaults and Configuration
ECC errors may be optionally reported as bus errors for ICode or DCode reads, or may generate interrupts. Independent error reporting options are available for 1-bit corrections and 2-bit error detections by writing the
FLCC_IEN.ECC_ERROR and FLCC_IEN.ECC_CORRECT bits.
Error Handling
The impact of ECC errors during the information space signature check is described in Signatures. On any read
operation, if the ECC engine observes a 1 bit error it will be corrected automatically (the 1-bit error could be in the
ECC byte itself, or in the 64-bit dualword being read by the user). If a 2-bit error is observed the ECC engine canonly report the detection event (2-bit errors cannot be corrected).

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProtection and Integrity

Depending on when the read happens (for example, during an ICode or DCode read, or as part of a built-in command such as a signature check) appropriate flags are set in the status register (FLCC_STAT.ECCERRCMD,
FLCC_STAT.ECCRDERR, and so on).
If interrupt generation is enabled in the FLCC_IEN.ECC_ERROR/ FLCC_IEN.ECC_CORRECT bits, the source
address of the ECC error causing the interrupt are available in the FLCC_ECC_ADDR register for the interrupt
service routine to read.
ECC Errors during Sign Command Execution
ECC errors observed during signature checks generate the appropriate status register flags after completion but will
not populate the FLCC_ECC_ADDR register.
Concurrent Errors
If ECC errors occur on DCODE and ICODE simultaneously (for example, from an ICODE prefetch match and a
DCODE flash read), ECC error status information is prioritized as follows:• First Priority: 2-bit ECC errors are given priority over 1bit ECC errors/corrections.
For example, if a 2-bit ECC error is observed on a DCODE read in the same cycle as a 1-bit ECC error/correction on an ICODE read, the ECC error status is updated for DCODE only.
• Second Priority: ICODE is given priority over DCODE.
For example, if a 2-bit error is observed on an ICODE read and a DCODE read in the same cycle, the ECC
error status is updated for ICODE only.
Read of Erased Location
When erased, the flash memory holds a value of all 1s, including the ECC byte appended to every 64-bit DWORD.
The proper ECC meta-data for 64 ONES is not 0xFF, therefore in its erased state the flash memory holds data and
ECC meta-data representing some number of bit errors.
For this reason any flash reads of erased locations will automatically bypass the ECC engine. If user code reads alocation with all 1s in both 64-bit DWORD and ECC byte, the read returns the data without indicating any ECC
errors.
Clock and Timings
The flash controller is preconfigured to provide safe timing parameters for all flash operations for core clock frequencies of 26 MHz or less and reference clock frequency of 13 MHz.
If the core clock frequency is not within the limits of the frequency range specified for HFOSC in the datasheet,user code must adjust the timing parameters accordingly.
Flash accesses performed while core clock frequency is faster than 26 MHz (for example, 52 MHz) require user code
to first write to the FLCC_TIME_PARAM1 register to increase the WAITSTATES value from the default (0x0) to
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–17Flash Operating Modes

0x1 or greater. This adjustment inserts one (or more) wait states into the read path of the flash memory. Failure to
add at least one wait state to the read path results in undefined behavior of the flash memory during reads at coreclock frequencies above 26 MHz.

Flash Operating Modes
The flash memory used by the ADuCM4050 MCU supports the following power optimizing features:
Sleep Mode
The user code may put the flash IP into a low power sleep mode by writing the SLEEP command (0x2) to the
FLCC_CMD register. The flash controller wakes the flash IP from sleep automatically on the first flash access following a SLEEP command. The user code may observe the sleep state of flash by reading the
FLCC_STAT.SLEEPING bit.
NOTE: The cache controller, DMA reads, other peripheral, or user code may attempt to read flash memory at any
time, any of which will trigger a flash wakeup event; it is advisable that user code occasionally poll the
FLCC_STAT.SLEEPING bit to verify that the flash IP is still sleeping when the user expects it to be.
The flash controller does not honor new commands (WRITE, ERASE, and so on) while the flash IP is in sleep
mode; the only supported commands in this mode are IDLE and ABORT. DMA write requests will be stalled automatically by entering sleep mode.
System Interrupt based aborts (as configured through the FLCC_ABORT_EN_LO and FLCC_ABORT_EN_HI
registers) are generally used to abort any ongoing flash commands in the event of an enabled system interrupt. However, such an interrupt will not wake the flash from sleep mode. If the system interrupt can be serviced without
accessing flash, it remains in sleep mode; if servicing the interrupt requires accessing the flash then the flash accessitself will serve to wake the flash IP.
Waking from sleep incurs a ~5 μs latency before executing any reads or commands (this is a requirement of the flashIP). User code may wake the flash IP early by executing an IDLE command. This will wake the flash IP without anyother effect on the controller.
For consistency, the ABORT command can also be used to wake the flash IP. Waking with the ABORT command
differs from waking by the IDLE command only in that the status register will report FLCC_STAT.CMDFAIL bit(0x3) to match the expected user code checks for status register values.
Power-down Mode
The ADuCM4050 MCU automatically powers down the flash IP when the device hibernates. To support this feature, the flash controller interoperates with the power management unit and delays hibernation until any ongoing
flash accesses are completed. User code is responsible for reading and evaluating flash status registers prior to entering hibernate (status registers are not retained in hibernate). The abort command may be used to abruptly end an
ongoing flash command but must be used sparingly to avoid eventual damage to the flash array.

8–18

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceClock Gating

Clock Gating
A series of clock gates have been inserted into the flash controller to automatically gate off unused components ofthe module. User configuration or control is not required. Unused portions of the flash controller is automaticallygated off when appropriate (for example, while in sleep mode the majority of the flash controller is gated off to savepower).

Flash Interrupts and Exceptions
The flash controller may selectively generate interrupts for several events. The following table outlines the events
that may generate interrupts and bit fields of FLCC_IEN used to control interrupt generation for each event.
Table 8-4: Interrupts and Bit fields
Name (Bit field)

Description

CMDFAIL

IRQ generated when a command or write operation completes with an error status.

WRALCOMP

IRQ generated when an active flash write is nearly complete and the key-hole registers are open
for another write (if fulfilled on-time, a Burst write occurs).

CMDCMPLT

IRQ generated when a command or flash write operation completes.

ECC_ERROR

IRQ generated when 2-bit ECC errors are observed when this field is set to 2.

ECC_CORRECTIRQ generated when 1-bit ECC corrections are observed when this field is set to 2.

Flash Programming Model
The following section provides an example sequence to execute the Page erase command using the flash controller.
The same sequence can be used for other commands with some modifications.

Programming Guidelines
Here are the programming guidelines:
1. Program the FLCC_PAGE_ADDR0 or FLCC_PAGE_ADDR1 register with the address of the page whichneeds to be erased.
2. Write the Flash User Key (0x676C7565) to the FLCC_KEY.VALUE bits.
3. Write the command to be executed into the FLCC_CMD register.
4. Poll for the FLCC_STAT.CMDCOMP bit to be set.

ADuCM4050 FLCC Register Descriptions
Flash Controller (FLCC) contains the following registers.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–19

ADuCM4050 FLCC Register Descriptions

Table 8-5: ADuCM4050 FLCC Register List
Name

Description

FLCC_ABORT_EN_HI

IRQ Abort Enable (Upper Bits)

FLCC_ABORT_EN_LO

IRQ Abort Enable (Lower Bits)

FLCC_POR_SEC

Flash Security

FLCC_VOL_CFG

Volatile Flash Configuration

FLCC_CMD

Command

FLCC_ECC_ADDR

ECC Status (Address)

FLCC_IEN

Interrupt Enable

FLCC_KEY

Key

FLCC_KH_ADDR

Write Address

FLCC_KH_DATA0

Write Lower Data

FLCC_KH_DATA1

Write Upper Data

FLCC_PAGE_ADDR0

Lower Page Address

FLCC_PAGE_ADDR1Upper Page Address

FLCC_SIGNATURE

Signature

FLCC_STAT

Status

FLCC_TIME_PARAM0

Time Parameter 0

FLCC_TIME_PARAM1

Time Parameter 1

FLCC_UCFG

User Configuration

FLCC_WRPROT

Write Protection

FLCC_WR_ABORT_ADDR

Write Abort Address

8–20

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

IRQ Abort Enable (Upper Bits)
Upper bits of IRQ abort enable.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[47:32] (R/W)
Sys IRQ Abort Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[63:48] (R/W)
Sys IRQ Abort Enable

Figure 8-5: FLCC_ABORT_EN_HI Register Diagram
Table 8-6: FLCC_ABORT_EN_HI Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(R/W)

Sys IRQ Abort Enable.
To allow a system interrupt to abort an ongoing flash command (for example, Erase,
Write, Sign) write a 1 to the bit in this register corresponding with the desired system
IRQ number. Only the first 64 system IRQs are supported by this feature.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–21

ADuCM4050 FLCC Register Descriptions

IRQ Abort Enable (Lower Bits)
Lower bits of IRQ abort enable.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R/W)
Sys IRQ Abort Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R/W)
Sys IRQ Abort Enable

Figure 8-6: FLCC_ABORT_EN_LO Register Diagram
Table 8-7: FLCC_ABORT_EN_LO Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE
(R/W)

8–22

Sys IRQ Abort Enable.
To allow a system interrupt to abort an ongoing flash command (for example, Erase,
Write, Sign) write a 1 to the bit in this register corresponding with the desired system
IRQ number. Only the first 64 system IRQs are supported by this feature.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Flash Security
Controls the flash security features.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SECURE (R/W1S)
Set this bit to prevent read or write
access to User Space (sticky whenset)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 8-7: FLCC_POR_SEC Register Diagram
Table 8-8: FLCC_POR_SEC Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
0 SECURE(R/W1S)

Set this bit to prevent read or write access to User Space (sticky when set).
Requires User key.
Once set, it cannot be cleared without resetting the device (POR or PIN reset only) or
erasing/verifying erased state of User Space (Blank Check or Mass Erase running successfully to completion).
It plays a direct role in User Space security enforcement. Once set, this bit prevents
access to User Space:
DCode Reads: Returns bus faults with the data bus == 0
ICode Reads: Returns bus faults with the data bus == 0
APB Writes: command will be denied, flash content unchanged
When set, user code may still perform Mass Erase and Page Erase operations.
Note: FLCC_WRPROT register still applies. Only unprotected pages may be erased(Mass Erase is disallowed if any page is protected).

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–23

ADuCM4050 FLCC Register Descriptions

Volatile Flash Configuration
This register resets on any/all resets (POR/PIN/SW/WDT). The User Key must be written to the KEY Registerprior to writing this register.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

INFO_REMAP (R/W1C)
Alias the info space to the base addressof user space
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 8-8: FLCC_VOL_CFG Register Diagram
Table 8-9: FLCC_VOL_CFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
0 INFO_REMAP(R/W1C)

8–24

Alias the info space to the base address of user space.
When this bit is set, the boot loader is mirrored at address 0. This bit is automatically
cleared by the boot loader.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Command
Write this register to execute a specified command. The user key must first be written to the FLCC_KEY register for
most command requests to be honored.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Commands
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 8-9: FLCC_CMD Register Diagram
Table 8-10: FLCC_CMD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
3:0 VALUE(R/W)

Commands.
Write command values to this register to begin a specific operation. All commands but
write and idle require first writing the User Key to the FLCC_KEY register
0 IDLENo key is required.
No command executed. If flash IP is in the sleep state,
this command wakes the flash (returns command complete and no error codes).

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–25

ADuCM4050 FLCC Register Descriptions

Table 8-10: FLCC_CMD Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 ABORT[User Key] is required.
ABORT command must be used sparingly as a last resort mechanism to gain access to the flash IP during
time-sensitive events. For example a low voltage alarm
may be cause to abort an ongoing flash write or erasecommand to enable user code to shutdown the partgracefully. Note that the flash array may be damaged byover use of the ABORT command.
If this command is issued, any command currently inprogress will be abruptly stopped (if possible). The status will indicate command completed with an error of
ABORT.
ABORT is the only command that can be issued while
another command is already in progress (An exception isthat user code may stack one write command on top ofa single on-going write command. All other overlapping
command combinations are invalid unless the new command is an ABORT).
If a write or erase is aborted then some flash IP timing
requirements may be violated and it is not possible todetermine if the write or erase completed successfully.
User code should read the affected locations to determine the outcome of the aborted commands. Note that
an aborted command may result in a weakly programmed flash: it is always advisable to erase the affected region and reprogram it.
Depending on how far along the flash controller is in
the process of performing a command, an ABORT is
not always possible (some flash IP timing parametersmust not be violated). This is difficult (if not impossible) to predict in software, therefore, aborts must be
considered a request which may have no affect on actualcommand duration.

8–26

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Table 8-10: FLCC_CMD Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 Requests flash to enter Sleep mode
[User Key] is required.
Requests the flash controller to put the flash to sleep (alow power mode).
When in sleep, any ICode, DCode, or DMA transaction will wake the flash automatically.
Wake-up process takes ~5 us (configurable in
FLCC_TIME_PARAM1 register). If user code can predict ~5 us ahead of time that the flash will be required,user may write an IDLE command to the FLCC_CMD
register to manually wake the flash. An ABORT command is also respected for waking the part (and will return appropriate status indicating that the sleep command was aborted).
Once awoken, the part remains awake until user code
once again asserts a SLEEP command.
3 SIGN[User Key] is required.
Use this command to generate a signature for a block ofdata. Signatures may be generated for blocks of wholepages only. The address of the start page should be written to the FLCC_PAGE_ADDR0 register, the address ofthe end page written to the FLCC_PAGE_ADDR1 register, and then write this code to the FLCC_CMD register to start the signature generation. When the command has complete the signature will be readable fromthe FLCC_SIGNATURE register.
4 WRITE
No key is required.
This command takes the address and data from the
FLCC_KH_ADDR, FLCC_KH_DATA0, and
FLCC_KH_DATA1 registers and executes a single 64bit WRITE operation targeting the specified address.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–27

ADuCM4050 FLCC Register Descriptions

Table 8-10: FLCC_CMD Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
5 Checks all of User Space; fails if any bits in user space
are cleared[User Key] is required.
Performs a blank check on all of user space. If any bits
in user space are cleared the command will fail with a
READ VERIFY status. If all of user space is FFs thecommand will pass.
This command is intended to support early customer
software development. When an unprogrammed partboots with security features preventing reads and writes
of user space, this command may be used to verify thatthe user space contains no proprietary information. If
this command passes read and write protection of user
space will be cleared.
6 ERASEPAGE[User key] is required.
Write the address of the page to be erased to the
FLCC_PAGE_ADDR0 register, then write this code to
the FLCC_CMD register. When the erase has completed
the full page will be verified (read) automatically to ensure a complete erasure. If there is a read verify error thiswill be indicated in the FLCC_STAT register. To erase
multiple pages wait until a previous page erase has completed check the status then issue a command to start
the next page erase.
7 MASSERASE[User key] is required.
Erase all of flash user space. When the erase has completed the full user space will be verified (read) automatically to ensure a complete erasure. If there is a read verify error this will be indicated in the Status register.
8 Reserved
9 Reserved

8–28

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

ECC Status (Address)
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R)This register has the address for which
ECC error is detected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[19:16] (R)This register has the address for which
ECC error is detected

Figure 8-10: FLCC_ECC_ADDR Register Diagram
Table 8-11: FLCC_ECC_ADDR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
19:0 VALUE(R/NW)

This register has the address for which ECC error is detected.
This register is updated on ECC errors or corrections as selected to generate interrupts(IRQ) in the FLCC_IEN register. This register is not updated in the event of an ECC
error or correction which instead generates a bus fault. This register records the addressof the first ECC error or correction event to generate an interrupt since the last timethe ECC status bits were cleared (or since reset). If the status bits are cleared in thesame cycle as a new ECC event (selected to generate an IRQ), a new address will berecorded and the status bits will remain set. Errors have priority over corrections (2 ormore bits corrupt = ERROR; a correction results in proper data being returned after asingle bit is corrected). If an error and a correction occur in the same cycle, this register
will report the ERROR address. When two of the same priority ECC events occur(both ERROR or both CORRECTION) the ICODE bus has priority over DCODE.
Therefore, if both ICODE and DCODE buses generate the same type of ECC eventin the same cycle, the ICODE address will be stored in this register. The register cannot be cleared except by reset. It will always hold the address of the most recently reported ECC correction or error.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–29

ADuCM4050 FLCC Register Descriptions

Interrupt Enable
Used to specify when interrupts are generated.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

ECC_ERROR (R/W)
Control whether to generate bus errors,interrupts, or neither in response to
2-bit ECC Error events

CMDCMPLT (R/W)
Command Complete Interrupt Enable
WRALCMPLT (R/W)
Write Almost Complete Interrupt Enable

ECC_CORRECT (R/W)
Control whether to generate bus errors,interrupts, or neither in response to
1-bit ECC Correction events
CMDFAIL (R/W)
Command Fail Interrupt Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 8-11: FLCC_IEN Register Diagram
Table 8-12: FLCC_IEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:6 ECC_ERROR(R/W)

Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC
Error events.
0 Do not generate a response to ECC events
1 Generate Bus Errors in response to ECC events
2 Generate IRQs in response to ECC events

5:4 ECC_CORRECT(R/W)

Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC
Correction events.
Note: The hardware reset value is 2, but the kernel writes a value of 0 to these fields.
0 Do not generate a response to ECC events
1 Generate Bus Errors in response to ECC events
2 Generate IRQs in response to ECC events

2 CMDFAIL(R/W)
1 WRALCMPLT

Command Fail Interrupt Enable.
If this bit is set, an interrupt is generated when a command or flash write completeswith an error status.
Write Almost Complete Interrupt Enable.

(R/W)

8–30

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Table 8-12: FLCC_IEN Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 CMDCMPLT(R/W)

Command Complete Interrupt Enable.
If this bit is set, an interrupt is generated when a command or flash write completes.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–31

ADuCM4050 FLCC Register Descriptions

Key
When user code must write a key to access protected features, the key value must be written to this register.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key Register

Figure 8-12: FLCC_KEY Register Diagram
Table 8-13: FLCC_KEY Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(RX/W)Key Register.
Unlock protected features by writing the appropriate key value to this register1735161189 USERKEY
Write the User Key to enable certain registers to bemodified or to allow certain commands to be executed.
This key is used as a sanity check to prevent accidental
modification of settings or flash content. It is not a security component and is not intended to be secret information.

8–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Write Address
Write the byte address of any byte of a 64-bit dual-word flash location to be targeted by a WRITE command. All
writes target 64-bit dual-word elements in the flash array. Writing any address above the valid range of flash memory
will saturate the address to prevent aliasing; user code should take care to target valid flash address locations.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[12:0] (R/W)
Address to be written on a WRITE command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[16:13] (R/W)
Address to be written on a WRITE command

Figure 8-13: FLCC_KH_ADDR Register Diagram
Table 8-14: FLCC_KH_ADDR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
19:3 VALUE

Address to be written on a WRITE command.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–33

ADuCM4050 FLCC Register Descriptions

Write Lower Data
The lower half of 64-bit dual word data to be written to flash.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VALUE[15:0] (R/W)
Lower half of 64-bit dual word data
to be written on a Write command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VALUE[31:16] (R/W)
Lower half of 64-bit dual word data
to be written on a Write command

Figure 8-14: FLCC_KH_DATA0 Register Diagram
Table 8-15: FLCC_KH_DATA0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Lower half of 64-bit dual word data to be written on a Write command.

(R/W)

8–34

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Write Upper Data
The upper half of 64-bit dual word data to be written to flash.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VALUE[15:0] (R/W)
Upper half of 64-bit dual word data
to be written on a Write command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VALUE[31:16] (R/W)
Upper half of 64-bit dual word data
to be written on a Write command

Figure 8-15: FLCC_KH_DATA1 Register Diagram
Table 8-16: FLCC_KH_DATA1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(R/W)

Upper half of 64-bit dual word data to be written on a Write command.
If DMA is enabled, then this register acts as a FIFO. Writes to this register will push
the old data to lower 32 bit of 64 bit data (FLCC_KH_DATA0). When this register iswritten twice (in DMA mode) the FIFO becomes full and a flash write command willautomatically be executed.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–35

ADuCM4050 FLCC Register Descriptions

Lower Page Address
Write a byte address to this register to select the page in which that byte exists. The selected page may be used for a
ERASEPAGE command (selecting which page to erase) or for a SIGN command (selecting the start page for a blockon which a signature should be calculated) For commands using both FLCC_PAGE_ADDR0 and
FLCC_PAGE_ADDR1, user should ensure that FLCC_PAGE_ADDR0 is always less than or equal to
FLCC_PAGE_ADDR1, else the command will be denied. (Writing any address above the valid range of flash memory will saturate the address register to prevent aliasing in the flash memory space)
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[5:0] (R/W)
Lower Address Bits of the Page Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[9:6] (R/W)
Lower Address Bits of the Page Address

Figure 8-16: FLCC_PAGE_ADDR0 Register Diagram
Table 8-17: FLCC_PAGE_ADDR0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
19:10 VALUE

Lower Address Bits of the Page Address.

(R/W)

8–36

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Upper Page Address
Write a byte address to this register to select the page in which that byte exists. The selected page may be used for a
SIGN command (selecting the end page for a block on which a signature should be calculated) For commands using
both FLCC_PAGE_ADDR0 and FLCC_PAGE_ADDR1, user should ensure that FLCC_PAGE_ADDR0 is always
less than or equal to FLCC_PAGE_ADDR1, else the command will be denied.
Writing any address above the valid range of flash memory will saturate the address register to prevent aliasing in the
flash memory space.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[5:0] (R/W)
Upper Address Bits of the Page Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[9:6] (R/W)
Upper Address Bits of the Page Address

Figure 8-17: FLCC_PAGE_ADDR1 Register Diagram
Table 8-18: FLCC_PAGE_ADDR1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
19:10 VALUE

Upper Address Bits of the Page Address.

(R/W)

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ADuCM4050 FLCC Register Descriptions

Signature
Provides read access to the most recently generated signature.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

X X X X X X X X X X X X X X X X
VALUE[15:0] (R)Read Signature
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X X X X X X X X X
VALUE[31:16] (R)Read Signature

Figure 8-18: FLCC_SIGNATURE Register Diagram
Table 8-19: FLCC_SIGNATURE Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Read Signature.

(R/NW)

8–38

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ADuCM4050 FLCC Register Descriptions

StatusProvides information on current command states and error detection/correction.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ECCINFOSIGN[0] (R)ECC Status of Flash Initialization

CMDBUSY (R)Command Busy

INIT (R)
Flash Controller Initialization in Progress

WRCLOSE (R)WRITE Registers are Closed

SIGNERR (R)Signature Check Failure During Initialization

CMDCOMP (R/W1C)
Command Complete

OVERLAP (R/W1C)
Overlapping Command

WRALCOMP (R/W1C)
Write Almost Complete

ECCRDERR (R/W1C)
ECC IRQ Cause

CMDFAIL (R/W1C)
Provides Information on Command
Failures

ECCERRCMD (R/W1C)
ECC Errors Detected During User Issued
SIGN Command

SLEEPING (R)Flash Array is in Low Power (Sleep)Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ACCESS_MODE (R)
Access Mode

ECCINFOSIGN[1] (R)ECC Status of Flash Initialization

CACHESRAMPERR (R)SRAM Parity Errors in Cache Controller

ECCERRCNT (R/W1C)
ECC Correction Counter

ECCDCODE (R/W1C)
DCode AHB Bus Error ECC status

ECCICODE (R/W1C)
ICode AHB Bus Error ECC status

Figure 8-19: FLCC_STAT Register Diagram
Table 8-20: FLCC_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31 ACCESS_MODE(R/NW)

Access Mode.
Indicates whether the controller is in Direct Access (default) or Indirect Access (servicing crypto commands) mode of operation
0 Flash controller is currently in Direct Access mode; user
access to all registers is enabled
1 Flash Controller is currently in Indirect Access mode;
user access to registers is limited to read-only access ofthe status register. Full register access will be restored
when the Cryptographic module releases control of the
flash controller (crypto completes the ongoing operation
within the protected key storage region)

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ADuCM4050 FLCC Register Descriptions

Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
29 CACHESRAMPERR(R/NW)
28:27 ECCDCODE(R/W1C)SRAM Parity Errors in Cache Controller.
This register provides details for AHB Errors generated due to cache SRAM parity error on the ICODE bus.
DCode AHB Bus Error ECC status.
Provides details for AHB Bus Errors generated due to ECC errors and/or corrections
on the DCODE bus.
0 No Error
No errors or corrections reported since reset or the register was last cleared.
1 2-bit Error
2-bit ECC error has been detected and reported on
AHB read access.
2 1-bit Correction
1-bit ECC correction has been detected and reported on
AHB read access.

26:25 ECCICODE(R/W1C)

ICode AHB Bus Error ECC status.
Provides details for AHB Bus Errors generated due to ECC errors and/or corrections
on the ICODE bus.
0 No Error
No errors or corrections reported since reset or the register was last cleared.
1 2-bit Error
2-bit ECC error has been detected and reported on
AHB read access.
2 1-bit Correction
1-bit ECC correction has been detected and reported on
AHB read access.

19:17 ECCERRCNT(R/W1C)

8–40

ECC Correction Counter.
This counter keeps track of overlapping ECC 1-bit correction reports. When configured to generate IRQs or AHB Bus Errors in the event of an ECC correction event,
this field counts the number of ECC corrections that occur after the first reported correction. The counter remains at full scale when it overflows and clears automaticallywhen clearing either FLCC_STAT.ECCICODE or FLCC_STAT.ECCDCODE status
bits.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
16:15 ECCINFOSIGN(R/NW)ECC Status of Flash Initialization.
ECC status after the end of automatic signature check on Info space.
0 No Error
No errors reported.
1 2-bit error
1 or more 2-bit ECC Errors detected during signaturecheck (signature check has failed).
2 1-bit error
1 or more 1-bit ECC Corrections performed during signature check. (signature check will pass if checksum stillmatches).
3 1- and 2-bit error
At least one of each ECC event (1-bit Correction and 2bit Error) were detected during signature check (signature check will fail).

14 INIT(R/NW)
13 SIGNERR(R/NW)
11 OVERLAP(R/W1C)Flash Controller Initialization in Progress.
Flash controller initialization is in progress. Until this bit de-asserts, AHB accesses will
stall and APB commands are ignored.
Signature Check Failure During Initialization.
Indicates an automatic signature check has failed during flash controller initialization.
The register value is valid only after the signature check has completed.
Overlapping Command.
This bit is set when a command is requested while another command is busy (overlapping commands are ignored).

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ADuCM4050 FLCC Register Descriptions

Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10:9 ECCRDERR(R/W1C)ECC IRQ Cause.
This field reports the cause of recently generated interrupts. The controller may be
configured to generate interrupts for 1- or 2-bit ECC events by writing the appropriate
values to FLCC_IEN.ECC_ERROR and FLCC_IEN.ECC_ERROR. These bits are
sticky high until cleared by user code.
0 No Error
1 2-bit Error
ECC engine detected a non-correctable 2-bit error during AHB read access.
2 1-bit Correction
ECC engine corrected a 1-bit error during AHB readaccess.
3 1- and 2-bit Events
ECC engine detected both 1- and 2-bit data corruptions
which triggered IRQs (note that a single read can only
report one type of event. This status indicates that asubsequent AHB read access incurred the alternate ECC
error event).
By default, 1-bit ECC corrections are reported as IRQs
and 2-bit ECC errors are reported as bus faults. It is notrecommended to report both types as IRQs else the status bits become ambiguous when trying to diagnose
which fault came first.

8–42

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC Register Descriptions

Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
8:7 ECCERRCMD(R/W1C)ECC Errors Detected During User Issued SIGN Command.
ECC errors, if produced during signature commands, are reported by these bits. To
generate interrupts base on these bits user code should set the corresponding bits in
FLCC_IEN register.
0 SuccessNo error, successful flash read operation during signature check.
1 2-bit Error
During signature commands, 2 bit error is detected on
one or more flash locations, not corrected.
2 1-bit Error
1 bit error is corrected for one or more flash locations
while doing signature commands.
3 1 or 2 bit Error
During signature commands, 1 bit error and 2 bit errors
are detected on one or more flash locations.

6 SLEEPING(R/NW)

Flash Array is in Low Power (Sleep) Mode.
Indicates that the flash array is in a low power (sleep) mode. The flash controller automatically wakes the flash when required for another data transaction. User may wakethe flash at any time by writing the IDLE command to the FLCC_CMD register. Flashwake-up times vary but are typically ~5 us. User must wake the flash ~5 us before it isused as a performance optimization.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 FLCC Register Descriptions

Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
5:4 CMDFAIL(R/W1C)

Provides Information on Command Failures.
This field indicates the status of a command upon completion. If multiple commands
are executed without clearing these bits then only the first error encountered is stored.
0 Success.
Successful completion of a command (For example,
WRITE).
1 Ignored.
Attempted access of a protected or out of memory location (such a command is ignored).
2 Verify Error.
Read verify error occurred.
This status will be returned for either of 2 causes; Failed
erasures and/or failed signature checks.
Failed Erasure: After erasing flash page(s) the controller
reads the corresponding word(s) to verify that the erasure completed successfully. If data still persists, the erasure has failed and this field reports the failure.
Failed signature check: If the Sign command is executedand the resulting signature does not match the data stored in the most significant 32-bit word of the signchecked block, the sign check has failed and this fieldreports the failure.
3 Abort.
Indicates a command is aborted by user code (abortcommand issued) or system interrupt.

3 WRALCOMP(R/W1C)

Write Almost Complete.
WRITE data registers are re-opened for access as an ongoing write nears completion.
Requesting another write operation before FLCC_STAT.CMDCOMP asserts will resultin a burst write. Burst writes take advantage of low level protocols of the Flash memory
and result in significant performance gains (~15 us saved from each write operation).
Note: Performance gain of a Burst Write only applies to back-to-back writes within thesame row of the flash array.

8–44

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ADuCM4050 FLCC Register Descriptions

Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 CMDCOMP(R/W1C)

Command Complete.
This bit asserts when a command completes. (Automatically clears when a new command is requested).
Note: Following a power-on-reset, the flash controller performs a number of operations (for example, verifying the integrity of code in info space). At the conclusion ofthis process the controller sets the FLCC_STAT.CMDCOMP bit to indicate that theprocess has completed.

1 WRCLOSE(R/NW)

0 CMDBUSY(R/NW)WRITE Registers are Closed.
The WRITE data/address registers and the command register are closed for access.
This bit is asserted part of the time while a write is in progress. If this bit is high, therelated registers are in use by the flash controller and cannot be written. This bit clears
when FLCC_STAT.WRALCOMP flag goes high, indicating that the ongoing write
command has consumed the associated data and these registers may now be overwritten with new data.
Command Busy.
This bit is asserted when the flash block is actively executing any command entered via
the command register.
Note: There is a modest delay between requesting a command and having this bit assert; user code polling for command completion should watch for
FLCC_STAT.CMDCOMP bit rather than FLCC_STAT.CMDBUSY.

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ADuCM4050 FLCC Register Descriptions

Time Parameter 0[User Key] is required to write this register. This register should not be modified while a flash write or erase command is in progress. This register defines a set of parameters used to control the timing of signals driven to the Flash
Memory. The default values are appropriate for a system clock of 26MHz and a reference clock operating at
13MHz. The value of each timing parameter consists of a user programmable nibble (4 bits) as well as some numberof hard-coded bits. User programmable bits are the most significant bits for each parameter.
Time parameters describe the number of ref-clk periods to wait when meeting the associated timing constraint of
the flash memory itself. Note that clock-domain-crossings and the constraints of signals not described by these parameters will increase the effective delays by a small margin. When programming the time parameter registers theuser should select a value approaching the minimum time for each constraint.
Note: Improper programming of this register may result in damage to the flash memory during PROGRAM or
ERASE operations.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

0

1

0

1

0

0

0

0

1

0

0

1

0

0

TPROG (R/W)
Program Time

DIVREFCLK (R/W)
Divide Reference Clock (by 2)

TPGS (R/W)
NVSTR to Program Setup TimeTNVS (R/W)
PROG/ERASE to NVSTR Setup Time

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

0

1

1

1

0

0

0

1

0

0

1

0

1

0

1

TNVH1 (R/W)
NVSTR Hold Time During Mass Erase

TNVH (R/W)
NVSTR Hold TimeTERASE (R/W)
Erase Time

TRCV (R/W)
Recovery Time

Figure 8-20: FLCC_TIME_PARAM0 Register Diagram
Table 8-21: FLCC_TIME_PARAM0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:28 TNVH1

NVSTR Hold Time During Mass Erase.

(R/W)

Determines the upper 4 bits of an 11-bit value loaded into the timer. The lower bits
are hard-coded to 0x14.
With an ideal refclk at 13 MHz:Min [0x0] = 1.5 us
Default [0xB] = 110 us
Max [0xF] = 149 us

8–46

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ADuCM4050 FLCC Register Descriptions

Table 8-21: FLCC_TIME_PARAM0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
27:24 TERASE

Erase Time.

(R/W)

Determines the upper 4 bits of a 19-bit value loaded into the timer. The lower bits are
hard-coded to 0x2000.
With an ideal refclk at 13 MHz:Min [0x0] = 0.6 ms
Default [0x8] = 20.8 ms
Max [0xF] = 38.4 ms

23:20 TRCV

Recovery Time.

(R/W)

Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0x2.
With an ideal refclk at 13 MHz:Min [0x0] = 154 ns
Default [0x9] = 1.1 us
Max [0xF] = 18.6 us

19:16 TNVH

NVSTR Hold Time.

(R/W)

Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0x1.
With an ideal refclk at 13 MHz:Min [0x0] = 77 ns
Default [0x5] = 5.5 us
Max [0xF] = 18.5 us

15:12 TPROG

Program Time.

(R/W)

Determines the upper 4 bits of a 10-bit value loaded into the timer. The lower bits are
hard-coded to 0x0D.
With an ideal refclk at 13 MHz:Min [0x0] = 1 us
Default [0x4] = 20.7 us
Max [0xF] = 75.3 us

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ADuCM4050 FLCC Register Descriptions

Table 8-21: FLCC_TIME_PARAM0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
11:8 TPGS(R/W)

NVSTR to Program Setup Time.
Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0x2.
With an ideal refclk at 13 MHz:Min [0x0] = 154 ns
Default [0x9] = 1.1 us
Max [0xF] = 18.6 us

7:4 TNVS(R/W)

PROG/ERASE to NVSTR Setup Time.
Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0x1.
With an ideal refclk at 13 MHz:Min [0x0] = 77 ns
Default [0x5] = 5.5 us
Max [0xF] = 18.5 us

0 DIVREFCLK(R/W)

Divide Reference Clock (by 2).
If set to 1, the reference clock is divided by 2. All time parameters are relative to thereference clock; dividing the clock enables the selection of long time periods, if necessary.
Note: It is unlikely that user code should ever need to modify the time parameters.
Support is provided in the unlikely event that a user finds it necessary.

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ADuCM4050 FLCC Register Descriptions

Time Parameter 1[User Key] is required to write this register. This register should not be modified while a flash write or erase command is in progress. This register defines a set of parameters used to control the timing of signals driven to the Flash
Memory. The default values are appropriate for a system clock of 26MHz and a reference clock operating at
13MHz. The value of each timing parameter consists of a user programmable nibble (4 bits) as well as some numberof hard-coded bits. User programmable bits are the most significant bits for each parameter.
Time parameters describe the number of ref-clk periods to wait when meeting the associated timing constraint of
the flash memory itself. Note that clock-domain-crossings and the constraints of signals not described by these parameters will increase the effective delays by a small margin. When programming the time parameter registers theuser should select a value approaching the minimum time for each constraint.
Note: Improper programming of this register may result in damage to the flash memory during PROGRAM or
ERASE operations.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

CURWAITSTATES (R)Current Wait States [2:0]

TWK (R/W)
Wake up TimeWAITSTATES (R/W)
Number of Wait States to Access Flash31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 8-21: FLCC_TIME_PARAM1 Register Diagram
Table 8-22: FLCC_TIME_PARAM1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
10:8 CURWAITSTATES(R/NW)

Current Wait States [2:0].
When FLCC_TIME_PARAM1.WAITSTATES is modified, it may take a number ofclock ticks for the modification to take effect. The controller waits until all currently
active reads or writes or erases have completed before changing the number of waitstates. These bits can be used to verify that the change to
FLCC_TIME_PARAM1.WAITSTATES[2:0] has taken effect and it is safe to modify
the clock frequency.

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ADuCM4050 FLCC Register Descriptions

Table 8-22: FLCC_TIME_PARAM1 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
6:4 WAITSTATES(R/W)

Number of Wait States to Access Flash.
This field is read only until the ADI Key is provided.
This determines the number of wait states required on a read it depends on the flash
access time and the hclk frequency into the flash core. When WaitStates[2:0] is modified: poll FLCC_TIME_PARAM1.CURWAITSTATES until it is the same value, only
then it is safe to change the system clock frequency.
This can be programmed only till 3'b100, if any attempt is made to program morethan 3'b100 then this register will not be updated.

3:0 TWK(R/W)

Wake up Time.
Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0xB.
With an ideal refclk at 13 MHz:Min [0x0] = 847 ns
Default [0x4] = 5.7 us
Max [0xF] = 19.3 us.

8–50

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ADuCM4050 FLCC Register Descriptions

User Configuration
User key is required. Write to this register to enable user control of DMA and Auto-increment features. When user
code has finished accessing this register, garbage data should be written to the FLCC_KEY register to re-assert protection.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AUTOINCEN (R/W)
Auto Address Increment for Key Hole
AccessKHDMAEN (R/W)
Key Hole DMA Enable

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 8-22: FLCC_UCFG Register Diagram
Table 8-23: FLCC_UCFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 AUTOINCEN(R/W)

Auto Address Increment for Key Hole Access.
When this bit is set, FLCC_KH_ADDR automatically increments by 0x8 during eachwrite command or after each read command. This enables user code to write a series ofsequential flash locations without having to manually set the flash address for eachwrite.
The FLCC_KH_ADDR is incremented, and may be observed by user code, when
FLCC_STAT.WRALCOMP is asserted during a write command, or when
FLCC_STAT.WRALCOMP is asserted after a READ command.
When this bit is set, user code may not directly modify FLCC_KH_ADDR.

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ADuCM4050 FLCC Register Descriptions

Table 8-23: FLCC_UCFG Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 KHDMAEN(R/W)

Key Hole DMA Enable.
The flash controller interacts with the DMA controller, when this bit is set.
Prior to setting this bit, user code must:- Write the starting address to FLCC_KH_ADDR- Configure the DMA controller to write data to FLCC_KH_DATA1 (address must be
DWORD aligned)- Configure the DMA controller to always write pairs of 32 bit words (R Power = 1)
- Configure the DMA controller to write an integer number of data pairs (for an odd
number of words user code must write one word manually without the help of DMA)
Note: All DMA writes will automatically increment the target address (similar to the
behavior of FLCC_UCFG.AUTOINCEN). The DMA controller may only be used towrite sequential addresses starting from the value of FLCC_KH_ADDR
The flash controller automatically begins write operations each time the DMA controller provides a pair of words to write. Interaction with the DMA controller has been
designed to use burst writes which may significantly reduce overall programming time.

8–52

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ADuCM4050 FLCC Register Descriptions

Write Protection
User Key is required to modified this register. The FLCC_WRPROT register may be automatically configured during
device boot up. In this event, the boot loader reads data from user space and loads that data into this register.
User code may affect non-volatile write protection by writing to the appropriate location in the flash memory. Bydefault, the relevant location in flash is 0x3FFF0 (the 4th most significant word in user space), but may be relocatedby ADI's secure boot loader.
User code may alternatively assert protection at runtime for any unprotected blocks by directly writing this register.
Blocks may have protection added but cannot have protection removed; changes will be lost on reset. This approachis suggested especially during user code development.
All write protection is cleared on a power-on-reset but note that the ADI secure boot loader will reassert write protection as defined by the FLCC_WRPROT word in user space before enabling user access to the flash array. Therefore removing write protection can only be performed by an ERASEPAGE command of the most significant page inuser space (provided that page is not currently protected) or by a MASSERASE command. Following a successful
MASSERASE command all protection of pages in user space is immediately cleared (user may write to user space
immediately following such an erase without a device reset required).
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

WORD[15:0] (R/W0C)
Clear Bits to Write Protect RelatedGroups of User Space Pages
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

WORD[31:16] (R/W0C)
Clear Bits to Write Protect RelatedGroups of User Space Pages

Figure 8-23: FLCC_WRPROT Register Diagram

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

8–53

ADuCM4050 FLCC Register Descriptions

Table 8-24: FLCC_WRPROT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 WORD(R/W0C)

Clear Bits to Write Protect Related Groups of User Space Pages.
Once cleared, these bits can only be set again by resetting the part.
Each bit of this 32-bit word represents a 32nd of the total available user space.
For 512 KB parts consisting of 2 KB pages (256 pages) each bit represents the write
protection state of a group of 8 pages.
For 256 KB parts consisting of 2 KB pages (128 pages) each bit represents the write
protection state of a group of 4 pages.
for 128 KB parts consisting of 2 KB pages (64 pages) each bit represents the write protection state of a group of 2 pages.
The most significant bit of this register corresponds to the most significant group ofpages in user space.

8–54

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ADuCM4050 FLCC Register Descriptions

Write Abort Address
Address of recently aborted write command. This address is only populated if the aborted write command was started. If the command is aborted early enough to have no affect on the flash IP this address is not updated.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

X X X X X X X X X X X X X X X X
VALUE[15:0] (R)Address of Recently Aborted Write
Command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X X X X X X X X X
VALUE[31:16] (R)Address of Recently Aborted Write
CommandFigure 8-24: FLCC_WR_ABORT_ADDR Register Diagram
Table 8-25: FLCC_WR_ABORT_ADDR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(R/NW)

Address of Recently Aborted Write Command.
This register holds the address targeted by an ongoing write command and retains its
value after an abort event. User code may read this register to determine the flash location(s) affected a write abort.
The register value is not guaranteed to persist once a new flash command is requested,
therefore user code should read this value immediately following an aborted write.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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Static Random Access Memory (SRAM)

9 Static Random Access Memory (SRAM)

This chapter provides an overview of the SRAM functionality of the ADuCM4050 MCU.

SRAM Features
The SRAM used by the ADuCM4050 MCU supports the following features:• Low power controller for data SRAM, instruction SRAM and cache SRAM.
• Total available memory: 128 KB• Maximum retained memory in hibernate mode: 124 KB• Data SRAM is composed of 128 KB. 16 KB is always retained in hibernate mode. Maximum retained memory
in hibernate mode is 124 KB• If instruction SRAM is enabled, 32 KB of data SRAM is mapped to instruction SRAM, and data SRAM can
only access 96 KB. Instruction SRAM has option to retain 0 KB, 12 KB, 16 KB, or 28 KB in hibernate mode.
• When cache controller is enabled, 4 KB of the instruction SRAM is reserved for cache data. The 4 KB cachedata is not retained in hibernate mode.
• Parity bit error detection (optional) is available on all SRAM memories. Parity check can be configured to beenabled/disabled in different memory regions.
• Byte, Half-word, and Word accesses are supported.
For more information, refer to SRAM Region.

SRAM Configuration
Instruction SRAM vs Data SRAM
If the PMG_TST_SRAM_CTL.INSTREN bit is asserted, 32 KB of SRAM is mapped at start address 0x1000_0000
as Instruction SRAM (see MODE0 in memory map). 96 KB of data SRAM is mapped in two sections, the firststarting at 0x2000_0000 and second starting at 0x2004_0000. If cache memory feature is used, only 28 KB is available for instruction SRAM (see MODE1 in memory map).

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9–1

SRAM Configuration

If PMG_TST_SRAM_CTL.INSTREN bit is 0 and cache is disabled, the 128 KB of SRAM is mapped as data
SRAM. The memory is arranged in two sections, the first one (32 KB) is mapped at start address 0x2000_0000 andthe second one (96 KB) at 0x2004_0000 (see MODE2 in memory map). If cache memory feature is used, the firstsection only maps 28 KB, so the total data SRAM available is 124 KB (see MODE3 in memory map).
By default, at power up and hardware reset, the 32 KB of SRAM is made available as instruction SRAM. If the userneeds to exercise the option of using a total of 128 KB data SRAM, the PMG_TST_SRAM_CTL.INSTREN bit
must be programmed to zero at the start of the user code.
When cache controller is enabled, SRAM bank 2 is not accessible. A bus error (unmapped address) is generated if anaccess is attempted.
For more information, refer to the SRAM Region

SRAM Retention in Hibernate ModeIn terms of the amount of SRAM being retained in hibernate mode, different configurations are available to theuser.
The content of the first 16 KB (Bank0) of data SRAM mapped at 0x2000_0000 is always retained. The SRAM
bank 2 (4 KB) is not retained in hibernate mode. It may be mapped to data SRAM, instruction SRAM, or cache
based on the mode of operation.
When PMG_SRAMRET.RET1 bit is enabled, 12 KB of data SRAM mapped from 0x2000_4000 to 0x2000_6FFF(Bank1) is retained in hibernate mode. If instruction SRAM is enabled, this is mapped to 0x1000_0000 to
0x1000_2FFF.
When PMG_SRAMRET.RET2 bit is enabled, 32 KB of data SRAM mapped from 0x2004_0000 to 0x2004_7FFF(Bank3, Bank4) is retained.
When PMG_SRAMRET.RET3 bit is enabled, 32 KB of data SRAM mapped from 0x2004_8000 to 0x2004_FFFF(Bank5) is retained.
When PMG_SRAMRET.RET4 bit is enabled, 32 KB of data SRAM mapped from 0x2005_0000 to 0x2005_7FFF(Bank6, Bank7) is retained. If instruction SRAM is enabled, Bank7 is mapped 0x1000_3000 to 0x1000_6FFF.
The PMG_SRAMRET.RET1, PMG_SRAMRET.RET2, PMG_SRAMRET.RET3, and PMG_SRAMRET.RET4
bits are write protected with the PWRKEY.

SRAM Programming Model
The start address of the data SRAM and instruction SRAM are set to 0x2000_0000 and 0x1000_0000 respectively.

SRAM Parity
For robustness, parity check can be enabled on all or a user selected group of SRAM banks. Parity check can detect
up to two errors per word for banks Bank0, Bank1 and Bank2 and data read back is done before performing byte
and halfword data write. Parity check can detect up to four errors per word for banks Bank3 to Bank7, and the
9–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

SRAM Initialization

memories support byte wise write in one cycle. Therefore, read back is not done for these banks for byte and halfword writes.
Parity check feature can be enabled by asserting the PMG_TST_SRAM_CTL.PENBNK0 to
PMG_TST_SRAM_CTL.PENBNK5 bits for each SRAM bank. User must configure these bits at the beginning of
the program code.
Parity is checked when data is read. It is also checked when byte or halfword data is written to Bank0, Bank1, andBank2. Parity is not checked when word (32 bits) write is performed. If a parity error is detected, a bus error isgenerated. Even if parity error is detected when writing a byte or halfword, the write operation is completed andparity bits are updated according to the new data. User must manage the parity error in the bus fault interrupt routine.

SRAM Initialization
If parity check is enabled, SRAM contents have to be initialized to avoid false parity errors while performing byte or
halfword write for Bank0, Bank1 and Bank2. Other banks support byte and halfword write in single cycle. They
need not be initialized. If Bank7 is used as instruction SRAM, it must be initialization when parity check is enabledon the bank. A dedicated hardware can automatically initialize the selected SRAM banks and the process takes 2048
HCLK cycles to complete. This hardware is fully programmable by the user so initialization can be started automatically or manually.
As initialization overwrites the contents of the selected SRAM banks, this process must be performed before writing
to those SRAMs. During the initialization sequence, if a write or read access to a SRAM bank being initialized is
detected, bus error response is issued until the initialization sequence is completed. SRAMs banks that are not selected to be initialized can be accessed as usual during the initialization process of the rest of the banks.
The initialization for a particular SRAM bank can be monitored for its completion by polling the appropriate
PMG_TST_SRAM_INITSTAT.BNK0DONE to PMG_TST_SRAM_INITSTAT.BNK7DONE bits. Every time aparticular SRAM bank is initialized, the associated PMG_TST_SRAM_INITSTAT.BNK0DONE to
PMG_TST_SRAM_INITSTAT.BNK7DONE bits bits are cleared and remain low until initialization is completed.
After power-up, SRAM Bank0, Bank1, Bank2, and Bank7 are automatically initialized. SRAM Bank0 (16 KB) isalways retained and contains the stack pointer and critical information. The content is not overwritten as initialization is already been performed. User must avoid initializing the SRAM banks that are already initialized, as they may
already contain user information.
After hibernate, the content in the non-retained SRAM banks is lost. If Bank1 (if not retained), Bank2 and Bank7(if not retained and mapped to instruction SRAM) have parity enabled, initialization is required.
There are two options to initialize the required SRAM banks after hibernate mode:
1. Initialize by writing to PMG_TST_SRAM_CTL.STARTINIT register after coming out of hibernate mode.
SRAMs banks (PMG_TST_SRAM_CTL.BNK0EN to PMG_TST_SRAM_CTL.BNK7EN bits) that are set to
1 are initialized.

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9–3

SRAM Initialization

2. Automatic initialization after hibernate mode. No write to PMG_TST_SRAM_CTL is required each time wecome back from hibernate mode. To select this automatic mode, the user has to previously set the
PMG_TST_SRAM_CTL.AUTOINIT bit. SRAMs selected for initialization in this register are automaticallyinitialized after coming back from hibernate mode.
Initialization resets the contents of the selected memory banks. User must properly select the memory banks that are
initialized so that user information is not lost.
The initialization sequence can be aborted at any time by writing to the PMG_TST_SRAM_CTL.ABTINIT bit.
This bit is self-cleared after it has been written.

Initialization in Cache
When cache memory is used, parity can also be enabled on its associated SRAM bank (Bank 2). In this case, (whenSRAM Bank 2 is used as cache memory) initialization is not required. Initialization is required only when we perform byte or halfword accesses to SRAM with parity check enabled. When SRAM Bank 2 is used as cache memory,
all the accesses are word accesses.
As initialization is not required for the cache memory, the cache feature is available after coming back from hibernate mode (no initialization time penalty). To prevent undesired bus errors, the controller ignores any initializationof SRAM Bank 2 when cache is enabled.

ADuCM4050 SRAM Register Description
Table 9-1: ADuCM4050 SRAM Register List
Name

Description

Reset

AccessPMG_TST_SRAM_INITSTAT

Initialization Status Register

0x00000000

R/W

PMG_TST_SRAM_CTL

Control for SRAM Parity and Instruction
SRAM

0x80000000

R/W

PMG_SRAMRET

Control for Retention SRAM in Hibernate Mode

0x00000000

R/W

9–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SRAM Register Description

Initialization Status Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BNK7DONE (R)Bank 7 initialization status

BNK0DONE (R)Bank 0 initialization status

BNK6DONE (R)Bank 6 initialization status

BNK1DONE (R)Bank 1 initialization status

BNK5DONE (R)Bank 5 initialization status

BNK2DONE (R)Bank 2 initialization status

BNK4DONE (R)Bank 4 initialization status

BNK3DONE (R)Bank 3 initialization status

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 9-1: PMG_TST_SRAM_INITSTAT Register Diagram
Table 9-2: PMG_TST_SRAM_INITSTAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7 BNK7DONE

Bank 7 initialization status.

(R/NW)

0 Bank 7 not initialized
1 Bank 7 initialized

6 BNK6DONE

Bank 6 initialization status.

(R/NW)

0 Bank 6 not initialized
1 Bank 6 initialized

5 BNK5DONE

Bank 5 initialization status.

(R/NW)

0 Bank 5 not initialized
1 Bank 5 initialized

4 BNK4DONE

Bank 4 initialization status.

(R/NW)

0 Bank 4 not initialized
1 Bank 4 initialized

3 BNK3DONE(R/NW)

Bank 3 initialization status.
0 Bank 3 not initialized
1 Bank 3 initialized

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

9–5

ADuCM4050 SRAM Register Description

Table 9-2: PMG_TST_SRAM_INITSTAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 BNK2DONE

Bank 2 initialization status.

(R/NW)

0 Bank 2 not initialized
1 Bank 2 initialized

1 BNK1DONE

Bank 1 initialization status.

(R/NW)

0 Bank 1 not initialized
1 Bank 1 initialized

0 BNK0DONE(R/NW)

Bank 0 initialization status.
0 Bank 0 not initialized
1 Bank 0 initialized

9–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SRAM Register Description

Control for SRAM Parity and Instruction SRAM
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ABTINIT (R/W)
Abort current initialization. Self-cleared

BNK1EN (R/W)
Enable initialization

AUTOINIT (R/W)
Automatic initialization on wake up
from hibernate mode

BNK2EN (R/W)
Enable initialization
BNK7EN (R/W)
Enable initialization

STARTINIT (R/W)
Write one to trigger initialization. Self-cleared
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

INSTREN (R/W)
Enables 32 KB instruction SRAMPENBNK0 (R/W)
Enable parity check

PENBNK7 (R/W)
Enable parity check

PENBNK1 (R/W)
Enable parity check

PENBNK6 (R/W)
Enable parity check

PENBNK2 (R/W)
Enable parity check

PENBNK5 (R/W)
Enable parity check

PENBNK3 (R/W)
Enable parity check

PENBNK4 (R/W)
Enable parity check

Figure 9-2: PMG_TST_SRAM_CTL Register Diagram
Table 9-3: PMG_TST_SRAM_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31 INSTREN

Enables 32 KB instruction SRAM.

(R/W)
23 PENBNK7

Enable parity check.

(R/W)
22 PENBNK6

Enable parity check.

(R/W)
21 PENBNK5

Enable parity check.

(R/W)
20 PENBNK4

Enable parity check.

(R/W)
19 PENBNK3

Enable parity check.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SRAM Register Description

Table 9-3: PMG_TST_SRAM_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
18 PENBNK2

Enable parity check.

(R/W)
17 PENBNK1

Enable parity check.

(R/W)
16 PENBNK0

Enable parity check.

(R/W)
15 ABTINIT

Abort current initialization. Self-cleared.

(R/W)
14 AUTOINIT

Automatic initialization on wake up from hibernate mode.

(R/W)
13 STARTINIT

Write one to trigger initialization. Self-cleared.

(R/W)
7 BNK7EN

Enable initialization.

(R/W)
2 BNK2EN

Enable initialization.

(R/W)
1 BNK1EN

Enable initialization.

(R/W)

9–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SRAM Register Description

Control for Retention SRAM in Hibernate Mode
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RET4 (R/W)
Enable retention bank 6 and bank 7(32 KB)

RET1 (R/W)
Enable retention bank 1 (12 KB)
RET2 (R/W)
Enable retention bank 3 and bank 4(32 KB)

RET3 (R/W)
Enable retention bank 5 (32 KB)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

HIBERNATE_SRAM_LOAD_MODE (R/W)
Hibernate mode SRAM load mode control

Figure 9-3: PMG_SRAMRET Register Diagram
Table 9-4: PMG_SRAMRET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
23 HIBER(R/W) NATE_SRAM_LOAD_M
ODE
9 RET4Hibernate mode SRAM load mode control.
Used to configure appropriate load current support in hibernate mode.
Enable retention bank 6 and bank 7 (32 KB).

(R/W)
8 RET3

Enable retention bank 5 (32 KB).

(R/W)
1 RET2

Enable retention bank 3 and bank 4 (32 KB).

(R/W)
0 RET1

Enable retention bank 1 (12 KB).

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

9–9Cache10 Cache

Enabling Cache increases the performance of applications executing from flash. Cache memory coexists with
SRAM. When Cache is enabled, part of the SRAM is allocated to Cache. Therefore, Cache cannot be used for otherpurposes. Instruction Cache (I-Cache) is of size is 4 KB. On wake up from hibernate, I-Cache contents are not retained.

Cache Programming Model
Instruction Cache is disabled on power-up.

Programming Guidelines
The sequence to enable cache is as follows:
1. Read FLCC_CACHE_STAT.ICEN bit to make sure that Cache is disabled. Poll until this bit is cleared.
2. Write USER KEY (0xF123F456) to FLCC_CACHE_KEY register.
3. Set FLCC_CACHE_SETUP.ICEN bit to enable the cache.

ADuCM4050 FLCC_CACHE Register Descriptions
Cache Controller (FLCC_CACHE) contains the following registers.
Table 10-1: ADuCM4050 FLCC_CACHE Register List
Name

Description

FLCC_CACHE_KEY

Cache Key Register

FLCC_CACHE_SETUP

Cache Setup Register

FLCC_CACHE_STAT

Cache Status Register

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

10–1

ADuCM4050 FLCC_CACHE Register Descriptions

Cache Key Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Cache Key
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Cache Key

Figure 10-1: FLCC_CACHE_KEY Register Diagram
Table 10-2: FLCC_CACHE_KEY Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(RX/W)

10–2

Cache Key.
Enter 0xF123_F456 to set the UserKey. Returns 0x0 if read. The key is cleared automatically after writing to FLCC_CACHE_SETUP register.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 FLCC_CACHE Register Descriptions

Cache Setup Register
Cache User key is required to enable a write to this location. Key will be cleared after a write to this Register.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

LCKIC (R/W)
If this bit is set, I-Cache contents arelockedICEN (R/W)
If this bit set, I-Cache is enabled for
AHB accesses

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 10-2: FLCC_CACHE_SETUP Register Diagram
Table 10-3: FLCC_CACHE_SETUP Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 LCKIC(R/W)
0 ICEN(R/W)

If this bit is set, I-Cache contents are locked.
New misses are not replaced in I-Cache.
If this bit set, I-Cache is enabled for AHB accesses.
If 0, I-Cache is disabled, and all AHB accesses will be via Flash memory. This bit iscleared when Init bit is set.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

10–3

ADuCM4050 FLCC_CACHE Register Descriptions

Cache Status Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ICEN (R)
If this bit is set, I-Cache is enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 10-3: FLCC_CACHE_STAT Register Diagram
Table 10-4: FLCC_CACHE_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
0 ICEN(R/NW)

10–4

If this bit is set, I-Cache is enabled.
If this bit is cleared, I-Cache is disabled.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDirect Memory Access (DMA)

11 Direct Memory Access (DMA)

The direct memory access (DMA) controller is used to perform data transfer tasks and offload these from the
ADuCM4050 MCU. DMA is used to provide high speed data transfer between peripherals and memory. Data canbe quickly moved by the DMA without any CPU actions. This keeps the CPU resources free for other operations.

DMA Features
The DMA supports the following features:• 27 independent DMA channels• Two programmable priority levels for each DMA channel• Each priority level arbitrates using a fixed priority that is determined by the DMA channel number• Each DMA channel can access a primary, and/or alternate channel control data structure• Supports the following multiple transfer types:• Memory-to-memory• Memory-to-peripheral• Peripheral-to-memory• Supports the following multiple DMA cycle types:• Basic• Auto request• Ping-Pong• Scatter-Gather• Supports multiple DMA transfer data widths (8-bit, 16-bit, and 32-bit)• Each DMA channel can have independent source and destination increment/decrement controls

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–1

DMA Functional Description

DMA Functional Description
The DMA has 27 channels in total, each dedicated to managing memory access requests from peripherals. DMA
Channels shows the assignments.
Each DMA channel is connected to dedicated hardware DMA requests, and the software trigger is also supported oneach channel. This configuration is done by software. Each DMA channel has a programmable priority level default
or high. Each priority level arbitrates using a fixed priority that is determined by the DMA channel number.
The DMA controller supports multiple DMA transfer data widths. However, the source and destination transfer
sizes must be the same. Also, always align the source and destination addresses to the data transfer size. It has a single
output to indicate when an error condition occurs: DMA error interrupt. An error condition can occur when a bus
error happens while doing a DMA transfer, or when the DMA controller reads an invalid cycle control. The DMA
controller supports memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers and has accessto flash or SRAM as source and destination.
Table 11-1: DMA Channels
Channel Node

Peripheral

0

SPI2 Tx

1

SPI2 Rx

2

SPORT0A

3

SPORT0B

4

SPI0 Tx

5

SPI0 Rx

6

SPI1 Tx

7

SPI1 Rx

8

UART0 Tx

9

UART0 Rx

10

I2C Slave Tx

11

I2C Slave Rx

12

I2C Master

13

Crypto IN

14

Crypto OUT

15

Flash

16 to 23

Software DMA

24

ADC Rx25

UART1 Tx

26

UART1 Rx

11–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Functional Description

DMA Architectural Concepts
The DMA channel provides a means to transfer data between memory spaces or between memory and a peripheral
using the system interface. The DMA channel provides an efficient means of distributing data throughout the system, freeing up the core for other operations. Each peripheral that supports DMA transfers has a dedicated DMA
channel or channels with its register set that configures and controls the operating modes of the DMA transfers.

DMA Operating Modes
The DMA controller has two buses where one is connected to the system bus shared with the Cortex-M4F core andthe other bus is connected to 16-bit peripherals. The DMA request may stop the CPU access to the system bus forsome bus cycles, such as when the CPU and DMA target the same destination (memory or peripheral).
The DMA controller fetches channel control data structures located in the system memory to perform data transfers. The DMA-capable peripherals, when enabled to use DMA, can request the DMA controller for a transfer. At
the end of the programmed number of DMA transfers for a channel, the DMA controller generates a single cycle
dma_done interrupt corresponding to that channel. This interrupt indicates the completion of the DMA transfer.
Separate interrupt enable bits are available in the NVIC for each of the DMA channels.

Channel Control Data Structure
Every channel has two control data structures associated with it: a primary data structure and an alternate data structure. For simple transfer modes, the DMA controller uses either the primary or alternate data structure. For more
complex data transfer modes, such as Ping-Pong or Scatter-Gather, the DMA controller uses both the primary andalternate data structures. Each control data structure (primary or alternate) occupies four 32-bit locations in thememory as shown in the Channel Control Data Structure table.
Table 11-2: Channel Control Data Structure
OffsetName

Description

0x00

SRC_END_PTR

Source End Pointer

0x04

DST_END_PTR

Destination End Pointer0x08

CHNL_CFG

Control Data Configuration

0x0C

RESERVED

Reserved

Memory Map for Primary DMA Structure figure shows an example of the entire channel control data structure for
16 DMA channel case. It uses 256 bytes of system memory.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–3

DMA Operating Modes

0x07C

0x0FC

Control

0x078

Control

0x0F8

Destination End Pointer

0x074

Destination End Pointer

0x0F4

Source End Pointer

0x070

Source End Pointer

0x0F0

0x06C

0x0EC

Control

0x068

Control

0x0E8

Destination End Pointer

0x064
0x060

Destination End Pointer

0x0E4

Source End Pointer

0x0E0

Source End Pointer

0x0DC

0x05C
Control

0x058

Control

0x0D8

Destination End Pointer

0x054
0x050

Destination End Pointer

0x0D4

Source End Pointer

0x0D0

Source End Pointer

0x04C

0x0CC

Control

0x048

Control

0x0C8

Destination End Pointer

0x044

Destination End Pointer

0x0C4

Source End Pointer

0x040

Source End Pointer

0x0C0

0x03C

0x0BC

Control

0x038

Control

0x0B8

Destination End Pointer

0x034

Destination End Pointer

0x0B4

Source End Pointer

0x030

Source End Pointer

0x0B0

Control

0x028

Control

0x0A8

Destination End Pointer

0x024

Destination End Pointer

0x0A4

Source End Pointer

0x020
0x01C

Source End Pointer

0x0A0

Control

0x018

Control

0x098

Destination End Pointer

0x014
0x010

Destination End Pointer

0x094

Source End Pointer

0x090

0x0AC

0x02C

Source End Pointer

0x09C

0x00C

0x08C

Control

0x008

Control

0x088

Destination End Pointer

0x004

Destination End Pointer

0x084

Source End Pointer

0x000

Source End Pointer

0x080

Figure 11-1: Memory Map for Primary DMA Structure

Before the controller can perform a DMA transfer, the data structure related to the DMA channel needs to be written to the designated location in system memory. The Source End Pointer memory location contains the end address of the source data. The Destination End Pointer memory location contains the end address of the destination
data. The Control memory location contains the channel configuration control data. This determines the sourceand destination data size, number of transfers, and the number of data transfers for each arbitration.
When the DMA controller receives a request for a channel, it reads the corresponding data structure from the system memory into its internal cache. Any update to the descriptor in the system memory until dma_done interrupt
does not guarantee expected behavior. It is recommended that the user not update the descriptor before receiving
dma_done.

11–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Operating Modes

Source Data End PointerThe SRC_END_PTR memory location stores the address of the last location from where data will be read as part of
DMA transfer. This memory location must be programmed with the end address of the source data before the controller can perform a DMA transfer. The controller reads this memory location when it starts the first DMA datatransfer. DMA controller does not write to this memory location.
Table 11-3: Source Data End Pointer
Bit

Name

Description[31:0]

SRC_END_PTR

The end address of the source data.

Destination Data End Pointer
The DST_END_PTR memory location stores the address of the last location where data will be written to as part of
DMA transfer. This memory location must be programmed with the end address of the destination data before thecontroller can perform a DMA transfer. The controller writes this memory location when it starts the first DMA
data transfer. DMA controller does not read this memory location.
Table 11-4: Destination Data End Pointer
Bit

Name

Description[31:0]

DST_END_PTR

The end address of the destination data.

Control Data Configuration
For each DMA transfer, the control data configuration (CHNL_CFG) memory location provides the control information for the DMA transfer to the controller.
Table 11-5: Control Data Configuration
Bits

Name

Description

31:30

DST_INC

Destination address increment. The address increment depends on the source datawidth as follows:
SRC_SIZE:
00: byte
01: half-word
10: word
11: no increment. Address remains set to the value that the DST_END_PTR
memory location contains.

29:28

RESERVED

Undefined. Write as zero

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DMA Operating Modes

Table 11-5: Control Data Configuration (Continued)
Bits

Name

Description

27:26

SRC_INC

Source address increment. The address increment depends on the source data width
as follows:
SRC_SIZE:
00: byte
01: half-word
10: word
11: no increment. Address remains set to the value that the SRC_END_PTR memory location contains.

25:24

SRC_SIZE

Size of the source data.
00: byte
01: half-word
10: word
11: reserved

23:18

RESERVED

Undefined. Write as zero.

17:14

R_Power

R_Power arbitrates after x DMA transfers.
0000: x = 10001: x = 20010: x = 40011: x = 80100: x = 160101: x = 32
0110: x = 64
0111: x = 128
1000: x = 256
1001: x = 512
1010 to 1111: x = 1024
NOTE: Software DMA transfers can use any value from 0000 to 1111. DMA
transfers that involve peripherals should always use 0000 with the exception of theCrypto block, see Crypto chapter for further details. The operation of the DMA
will be indeterminate if a value other than 0000 is programmed for the DMA transfers involving peripherals.

13:4

N_minus_1

Total number of transfers in the current DMA cycle - 1.
This value indicates the total number of transfers in the DMA cycle and not the
total number of bytes.
The possible values are 0 - 1023.

11–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Operating Modes

Table 11-5: Control Data Configuration (Continued)
Bits

Name

Description

3

RESERVED

Undefined. Write as zero.

2:0

Cycle_ctrl

The operating mode of the DMA cycle.
000: Stop (Invalid)
001: Basic
010: Auto-Request
011: Ping-Pong
100: Memory Scatter-Gather Primary
101: Memory Scatter-Gather Alternate
110: Peripheral Scatter-Gather Primary111: Peripheral Scatter-Gather Alternate

During the DMA transfer process, if any error occurs during the data transfer, CHNL_CFG is written back to thesystem memory, with N_minus_1 field updated to reflect the number of transfers yet to be completed. When a full
DMA cycle is complete, cycle_ctrl bits are made invalid to indicate the completion of transfer.

DMA Priority
The priority of a channel is determined by its number and priority level. Each channel can have two priority levels:
default or high. All channels at the high priority level have higher priority than all channels at the default priority
level. At the same priority level, a channel with a lower channel number has a higher priority than a channel with ahigher channel number. The DMA channel priority levels can be changed by writing into the appropriate bit in the
DMA_PRI_SET register.

DMA Transfer Types
The DMA controller supports various types of DMA transfers based on the primary and alternate control data
structure and number of requests required to complete a DMA transfer. The DMA transfer type is configured byprogramming the appropriate values to the cycle_ctrl bits in the CHNL_CFG location of the control data
structure.
Based on the cycle_ctrl bits, the following DMA transfer types are supported:• Invalid• Basic• Auto request• Ping-Pong• Memory Scatter-Gather

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DMA Transfer Types• Peripheral Scatter-Gather
DMA Transfer Type Usage table shows the various DMA transfer types that should be used by the peripherals andsoftware DMA. Use of software DMA transfer types for peripherals and vice versa is not recommended.
Table 11-6: DMA Transfer Type Usage
Software

Peripheral

Auto Request

Basic

Ping-Pong

Ping-Pong*1

Memory Scatter-Gather

Peripheral Scatter-Gather*1

Software Ping-Pong DMA transfer operation is different from Peripheral Ping-Pong DMA transfer operation.

InvalidThis means that no DMA transfer is enabled for the channel. After the controller completes a DMA cycle, it sets thecycle type to invalid to prevent it from repeating the same DMA cycle. Reading an invalid descriptor for any channel
generates a DMA error interrupt and the corresponding bit in DMA_INVALIDDESC_CLR is set.
Basic
In this mode, the controller can be configured to use either primary or alternate data structure by programming
DMA_ALT_CLR register for the corresponding channel. This mode is used for peripheral DMA transfers. Whileusing this mode for peripherals, the R_Power in CHNL_CFG must be set to 0, which means the peripheral needs topresent a request for every data transfer.
Once the channel is enabled, when the controller receives a request, it performs the following operations:
1. The controller performs a transfer. If the number of transfers remaining is zero, the flow continues at Step 3.
2. The controller arbitrates:
a. If a higher priority channel is requesting service, the controller services that channel, orb. If the peripheral or software signals a request to the controller, it continues at Step 1.
3. At the end of the transfer, the controller interrupts the MCU using dma_done interrupt for the corresponding channel.
Auto-Request
In this mode, the controller must receive single request to enable the DMA controller to complete the entire DMA
cycle. This allows a large data transfer to occur, without significantly increasing the latency for servicing higher priority requests, or requiring multiple requests from the MCU or peripheral. This mode is useful for a memory-tomemory copy application using software DMA requests.
In this mode, the controller can be configured to use either primary or alternate data structure by programming the
DMA_ALT_CLR register for the corresponding channel.
11–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Transfer Types

After the channel is enabled, when the controller receives a request, it performs the following operations.
1. The controller performs, min (2R _ Power, N) transfers for the channel. If the number of transfers remaining iszero, the flow continues at Step 3.
2. A request for the channel is automatically generated. The controller arbitrates. If the channel has the highest
priority, the DMA cycle continues at Step 1.
3. At the end of the transfer, the controller interrupts the MCU using the dma_done interrupt for that channel.
Ping-Pong
In this mode, the controller performs a DMA cycle using one of the data structures and then performs a DMA cycle
using the other data structure. The controller continues to switch between primary and alternate, until it either reads
a data structure that is basic/auto-request, or the MCU disables the channel.
This mode is useful for transferring data using different buffers in the memory and it is best suited for continuous
data transmission/reception without any delay. In a typical application, the MCU is required to configure both primary and alternate data structure before starting the transfer. As the transfer progresses, the host can subsequently
configure primary or alternate control data structures in the interrupt service routine when corresponding transfer
ends.
The DMA controller interrupts the MCU using the dma_done interrupt after the completion of transfers associatedwith each control data structure. The individual transfers using either the primary or the alternate control data
structures work exactly the same as a basic DMA transfer.
Software Ping-Pong DMA Transfer
In this mode, if the DMA request is from software, request will be generated automatically after each arbitration
cycle until completion of primary or alternate descriptor tasks. This final descriptor must use an auto-request transfer type.

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DMA Transfer Types

Task A : Primary, cycle_ctrl = 011, 2 R = 4, N = 6
SW Request

Task Adma_done[C]Task B : Alternate, cycle_ctrl = 011, 2 R = 4, N = 12
Task BSW Request
AutoReqs

dma_done[C]Task C : Primary, cycle_ctrl = 011, 2 R = 2, N = 2
SW Request

Task C
dma_done[C]Task D : Alternate, cycle_ctrl = 011, 2 R = 4, N = 5
SW Request

Task D

AutoReq
dma_done[C]Task E : Primary, cycle_ctrl = 011, 2 R = 4, N = 7
SW Request

Task E

Auto Reqs
dma_done[C]End : Alternate, cycle_ctrl = 000
Auto Request

Figure 11-2: Software Ping-Pong DMA Transfer

Peripheral Ping-Pong DMA Transfer
In this mode, if the DMA request is from a peripheral, it needs to send DMA requests after every data transfer tocomplete primary or alternate descriptor tasks and the final descriptor must be programmed to use a basic transfer
type.

11–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Transfer Types

Task A : Primary, cycle_ctrl = 011, 2 R = 4, N = 6
Requests

Task Adma_done[C]Task B : Alternate, cycle_ctrl = 011, 2 R = 4, N = 12
Reqs

Task B

dma_done[C]Task C : Primary, cycle_ctrl = 011, 2 R = 2, N = 2
Req

Task C
dma_done[C]Task D : Alternate, cycle_ctrl = 011, 2 R = 4, N = 5
Reqs

Task D
dma_done[C]Task E : Primary, cycle_ctrl = 011, 2 R = 4, N = 7
Reqs

Task E

dma_done[C]End : Alternate, cycle_ctrl = 000
Invalid

Figure 11-3: Peripheral Ping-Pong DMA Transfer

Memory Scatter-Gather
In this mode, the DMA controller needs to be configured to use both primary and alternate data structures. It uses
the primary data structure to program the control configuration for alternate data structure. The alternate data
structure is used for data transfers using a transfer similar to an auto-request DMA transfer. The controller arbitrates
after every primary transfer. The controller only needs one request to complete the entire transfer. This mode is used
when performing multiple memory-to-memory copy tasks. The MCU can configure all of them together and is not
required to intervene. The DMA controller interrupts the MCU using the dma_done interrupt when the entire
Scatter-Gather transaction is completed using a basic cycle.
In this mode, the controller receives an initial request and then performs four DMA transfers using the primary data
structure to program the control structure of the alternate data structure. After this transfer is completed, it starts a

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11–11

DMA Transfer Types

DMA cycle using the alternate data structure. After the cycle is completed, the controller performs another four
DMA transfers using the primary data structure.
The controller continues to switch from primary to alternate to primary, until:• The MCU configures the alternate data structure for a basic cycle,
Or• The DMA reads an invalid data structure.
Table 11-7: CHNL_CFG for Primary Data Structure in Memory Scatter-Gather Mode
Bit

Name

Value

Description

31:30

DST_INC

10

Configures the controller to use word increments for the address.

29:28

RESERVED

00

Undefined. Write as zero.

27:26

SRC_INC

10

Configures the controller to use word increments for the address.

25:24

SRC_SIZE

10

Configures the controller to use word transfers.

23:18

RESERVED

00

Undefined. Write as zero.

17:14

R_power

0010

Indicates that the DMA controller performs four transfers.

13:4

N_minus_1

User

Configures the controller to perform N DMA transfers, where N is a multiple of 4.

3

RESERVED

00

Undefined. Write as zero.

2:0

Cycle_ctrl

100

Configures the controller to perform a memory Scatter-Gather DMA cycle.

11–12

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Transfer Types

Primary
RequestAlternate

Copy from A inmemory to
Alternate

Auto Req
Task A
Auto Req

N = 3, 2R = 4

Copy from B inmemory to
Alternate

Auto Req
Auto Reqs

Copy from C inmemory to
Alternate

Task BN = 8, 2R = 2

Auto Req

Auto Req
Task C
Auto Req

N = 5, 2R = 8

Copy from D inmemory to
Alternate

Auto Req
Task DN = 4, 2R = 4
dma_done[C]Figure 11-4: Memory Scatter-Gather Transfer Process

Peripheral Scatter-Gather
In this mode, the DMA controller should be configured to use both primary and alternate data structures. The controller uses the primary data structure to program the control structure of the alternate data structure. The alternate
data structure is used for actual data transfers and each transfer takes place using the alternate data structure with abasic DMA transfer. The controller does not arbitrate after every primary transfer. This mode is used when there are
multiple peripheral-to-memory DMA tasks to be performed. The MCU can configure all of them at the same timeand need not intervene in between.
This mode is similar to memory Scatter-Gather mode except for arbitration and request requirements. The DMA
controller interrupts the MCU using the dma_done interrupt when the entire Scatter-Gather transaction is completed using a basic cycle.
In peripheral Scatter-Gather mode, the controller receives an initial request from a peripheral and then performs
four DMA transfers using the primary data structure to program the alternate control data structure. It then immediately starts a DMA cycle using the al-ternate data structure, without re-arbitrating.

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DMA Transfer Types

After this cycle is completed, the controller re-arbitrates and if it receives a request from the peripheral and this has
the highest priority then it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the al-ternate data structure without re-arbitrating.
The controller continues to switch from primary to alternate to primary until:• The MCU configures the alternate data structure for a basic cycle,
Or• The DMA reads an invalid data structure
Table 11-8: CHNL_CFG for Primary Data Structure in Peripheral Scatter-Gather Mode
Bit

Name

Value

Description

31:30

DST_INC

10

Configures the controller to use word increments for the address.

29:28

RESERVED

00

Undefined. Write as zero.

27:26

SRC_INC

10

Configures the controller to use word increments for the address.

25:24

SRC_SIZE

10

Configures the controller to use word transfers.

23:18

RESERVED

00

Undefined. Write as zero.

17:14

R_power

0010

Indicates that the DMA controller performs four transfers.

13:4

N_minus_1

user

Configures the controller to perform N DMA transfers, where N is a multiple of four.

3

RESERVED

00

Undefined. Write as zero.

2:0

Cycle_ctrl

110

Configures the controller to perform a memory Scatter-Gather DMA cycle.

11–14

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Operating Modes

Primary
RequestAlternate

Copy from A inmemory to
Alternate

Req

Task AFor all primary to alternate transitions,the controller does not enter thearbitration process and immediately
perorms the DMA transfer that thealternate channel control data structure
specifies.

N = 3, 2R = 4

Copy from B inmemory to
Alternate

Reqs

Task BN = 8, 2R = 2

Copy from C inmemory to
Alternate

Task CN = 5, 2R = 8

Task DN = 4, 2R = 4

Req
Copy from D inmemory to
Alternate

dma_done[C]Figure 11-5: Peripheral Scatter-Gather Transfer Process

DMA Interrupts and Exceptions
Error Management
The DMA controller generates an error interrupt to the core when a DMA error occurs. A DMA error can occur
due to a bus error or an invalid descriptor fetch. A bus error occurs while fetching the descriptor or performing adata transfer. A bus error can occur when a read from or write to a reserved address location happens.
When a bus error occurs, the faulty channel is automatically disabled, and the corresponding status bit in the
DMA_ERRCHNL_CLR is set. If the DMA error is enabled in the NVIC, the error will also generate an interrupt. In
addition, the CHNL_CFG data structure for the corresponding channel will be updated with the latest n_count.
User can check this to know the number of successful data transfers before the bus error.
When the controller fetches an invalid descriptor, the faulty channel is automatically disabled, and the corresponding status bit in the DMA_INVALIDDESC_CLR register is set. If the DMA error is enabled in NVIC, the error also
generates an interrupt.
Address Calculation
The DMA controller calculates the source read address based on the SRC_END_PTR, the source address increment
setting in CHNL_CFG, and the current value of the N_Minus_1.
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DMA Interrupts and Exceptions

Similarly, the destination write address is calculated based on the DST_END_PTR, destination address increment
setting in CHNL_CFG, and the current value of the N_Minus_1.

N_minus_1 is the current count of transfers to be done.
Address Decrement
Address decrement can be enabled to source and destination addresses. Source address decrement can be enabled forchannels by setting appropriate bits in the DMA_SRCADDR_SET register. Similarly, destination address decrement
can be enabled for channels by setting the required bits in the DMA_DSTADDR_SET register. The values written
into the source data end pointer (SRC_END_PTR) and destination data end pointer (DST_END_PTR) are stillused as the addresses for the last transfer as part of the DMA cycle. However, the start address will be computed
differently to the address increment scheme for either source read or destination write.
If the source decrement bit is set in the DMA_SRCADDR_SET register for a channel, its source address is computed
as follows:

If the destination decrement bit is set in the DMA_DSTADDR_SET register for a channel, its source address is computed as follows:

NOTES:
N_minus_1 is the current count of transfers to be done.
Byte swap and address decrement should not be used together for any channel. If used together, DMA data transfer
operation is unpredictable.
Image Decrement figure shows all the combinations of source and destination decrement with their data movement
direction.

11–16

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Operating Modes

Figure 11-8: Image Decrement

Endian Operation
The DMA controller does the transfer by default using a little-endian approach; however, this default behavior canbe changed by setting the corresponding channel bit in the DMA_BS_SET register. The endian operation is referred
to as byte swap.
Byte Swap Disabled
Byte swap is disabled by default. In this case, the data transfer is considered to be little-endian. Data arriving from aperipheral is placed in sequence starting from the LSB of a 32-bit word.
For example, if 16 bytes of data arrive at the SPI as 0x01(start), 0x02, 0x03, 0x04 ... 0x0F, 0x10, it is stored by the
DMA in memory as follows:
1. 04_03_02_01
2. 08_07_06_05
3. 0C_0B_0A_09
4. 10_0F_0E_0D

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DMA Operating Modes

Byte Swap Enabled
Byte swap is enabled on any channel by setting the corresponding bit in the DMA_BS_SET register. By setting thebit, big-endian data transfers will occur. Data arriving from the peripheral will be placed in sequence starting from
the MSB of a 32-bit word.
For example, if 16 bytes of data arrive at the SPI as 0x01(start), 0x02, 0x03, 0x04 ... 0x0F, 0x10, it will be stored by
the DMA in memory as follows:
1. 01_02_03_04
2. 05_06_07_08
3. 09_0A_0B_0C
4. 0D_0E_0F_10
NOTES:
Byte swap happens on 32-bit data boundaries. The transfer size must be a multiple of 4.
Byte swap and address decrement should not be used together for any channel. If used together, DMA data transfer
operation is unpredictable.
When using byte swap, care must be taken to ensure that the source data address is constant for the full data transfer. For example, SPI where the data source is always from the same location (a FIFO).
Byte swap functionality is independent of DMA transfer size and can be 8-bit, 16-bit, or 32-bit.

DMA Channel Enable/Disable
Before issuing a DMA request, the DMA channel should be enabled, otherwise, the DMA request for the corresponding channel is driven as DONE interrupt. Any DMA channel can be enabled by writing the corresponding bit
in the DMA_EN_SET register. DMA controller disables the channel when the corresponding dma_done interrupt isgenerated. However, you can also disable any channel by writing to the corresponding bit in the DMA_EN_CLR
register.
Whenever a channel is disabled, based on the current state of the DMA controller, it does the following:• If the user disables the channel and there is no request pending for that channel, it is disabled immediately.
• If the user disables the channel that is not getting serviced, but its request is posted, its pending request will becleared, and the channel is disabled immediately.
• If the user disables a channel that has been selected after arbitration but yet to start transfers, the controller
completes the arbitration cycle and then disables channel.
• If the user disables the channel when it is getting serviced, controller completes the current arbitration cycle
and then disables the channel.

11–18

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceDMA Operating Modes

DMA Master Enable
The DMA_CFG.MEN bit acts as a soft reset to the DMA controller. Any activity in the DMA controller can be
performed only when this bit is set to 1. Clearing this bit to 0, clears all cached descriptors within the controller andresets the controller.

Power-down Considerations
Finish all the on-going DMA transfers before powering down the chip to hibernate. However, if the user decides tohibernate as early as possible (current data transfers are ignored), the DMA controller should be disabled by clearing
the DMA_CFG.MEN bit before going into hibernate.
NOTE: If hibernate mode is selected when a DMA transfer is in progress, the transfer discontinues on resumingfrom hibernate. The DMA returns to the disabled state.
After hibernate (or POR), the DMA must be enabled again by setting the DMA_CFG.MEN bit.
The following registers are retained in hibernate mode:• DMA_PDBPTR• DMA_ADBPTR• DMA_RMSK_SET• DMA_RMSK_CLR• DMA_PRI_SET• DMA_PRI_CLR• DMA_BS_SET• DMA_BS_CLR• DMA_SRCADDR_SET• DMA_SRCADDR_CLR• DMA_DSTADDR_SET• DMA_DSTADDR_CLR

DMA Programming Model
The following section describes the programming sequence to configure the DMA.

Programming Guidelines
1. Enable the DMA controller in the DMA_CFG register.
2. Enable the desired DMA channel.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 DMA Register Descriptions

3. Setup the DMA base pointer.
4. Setup the DMA descriptor for data transmission.
5. Generate the software DMA request in the DMA_SWREQ register or enable the peripheral which will generate
the interrupt to the DMA controller.

ADuCM4050 DMA Register Descriptions
DMA (DMA) contains the following registers.
Table 11-9: ADuCM4050 DMA Register List
Name

Description

DMA_ADBPTRDMA Channel Alternate Control Database PointerDMA_ALT_CLR

DMA Channel Primary Alternate Clear

DMA_ALT_SETDMA Channel Primary Alternate Set

DMA_BS_CLR

DMA Channel Bytes Swap Enable Clear

DMA_BS_SETDMA Channel Bytes Swap Enable Set

DMA_CFGDMA Configuration

DMA_DSTADDR_CLR

DMA Channel Destination Address Decrement Enable Clear

DMA_DSTADDR_SETDMA Channel Destination Address Decrement Enable Set

DMA_EN_CLR

DMA Channel Enable Clear

DMA_EN_SETDMA Channel Enable Set

DMA_ERRCHNL_CLR

DMA per Channel Error Clear

DMA_ERR_CLR

DMA Bus Error Clear

DMA_INVALIDDESC_CLR

DMA per Channel Invalid Descriptor Clear

DMA_PDBPTRDMA Channel Primary Control Database Pointer

DMA_PRI_CLRDMA Channel Priority Clear

DMA_PRI_SETDMA Channel Priority Set

DMA_REVIDDMA Controller Revision ID

DMA_RMSK_CLR

DMA Channel Request Mask Clear

DMA_RMSK_SETDMA Channel Request Mask Set

DMA_SRCADDR_CLR

DMA Channel Source Address Decrement Enable Clear

DMA_SRCADDR_SETDMA Channel Source Address Decrement Enable Set

DMA_STATDMA Status

DMA_SWREQDMA Channel Software Request

11–20

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Alternate Control Database Pointer
The DMA_ADBPTR read-only register returns the base address of the alternate channel control data structure. This
register removes the necessity for application software to calculate the base address of the alternate data structure.
This register cannot be read when the DMA controller is in the reset state.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

ADDR[15:0] (R)Base Address of the Alternate Data
Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ADDR[31:16] (R)Base Address of the Alternate Data
Structure

Figure 11-7: DMA_ADBPTR Register Diagram
Table 11-10: DMA_ADBPTR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 ADDR

Base Address of the Alternate Data Structure.

(R/NW)

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ADuCM4050 DMA Register Descriptions

DMA Channel Primary Alternate Clear
The DMA_ALT_CLR write-only register enables the user to configure the appropriate DMA channel to use the primary control data structure. Each bit of the register represents the corresponding channel number in the DMA controller.
Note: The DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather
and peripheral scatter-gather transfers.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (W)Select Primary Data Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (W)Select Primary Data Structure

Figure 11-8: DMA_ALT_CLR Register Diagram
Table 11-11: DMA_ALT_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(RX/W)

Select Primary Data Structure.
Set the appropriate bit to select the primary data structure for the corresponding DMA
channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_ALT_CLR.CHAN[C] = 0, No effect. Use the DMA_ALT_SET register to selectthe alternate data structure.
DMA_ALT_CLR.CHAN[C] = 1, Selects the primary data structure for channel C.

11–22

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Primary Alternate Set
The DMA_ALT_SET register enables the user to configure the appropriate DMA channel to use the alternate control data structure. Reading the register returns the status of which data structure is in use for the corresponding
DMA channel. Each bit of the register represents the corresponding channel number in the DMA controller.
Note: The DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather
and peripheral scatter-gather transfers.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W)
Control Structure Status / Select Alternate
Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W)
Control Structure Status / Select Alternate
Structure

Figure 11-9: DMA_ALT_SET Register Diagram
Table 11-12: DMA_ALT_SET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W)

Control Structure Status / Select Alternate Structure.
Returns the channel control data structure status, or selects the alternate data structure
for the corresponding DMA channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Read:
DMA_ALT_SET.CHAN[C] = 0, DMA channel C is using the primary data structure.
DMA_ALT_SET.CHAN[C] = 1, DMA channel C is using the alternate data structure.
When Written:
DMA_ALT_SET.CHAN[C] = 0, No effect. Use the DMA_ALT_CLR register to set bit[C] to 0.
DMA_ALT_SET.CHAN[C] = 1, Selects the alternate data structure for channel C.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–23

ADuCM4050 DMA Register Descriptions

DMA Channel Bytes Swap Enable Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (W)Disable Byte Swap
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (W)Disable Byte Swap

Figure 11-10: DMA_BS_CLR Register Diagram
Table 11-13: DMA_BS_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(RX/W)Disable Byte Swap.
The DMA_BS_CLR write-only register enables the user to configure a DMA channel
to not use byte swapping and use the default operation. Each bit of the register represents the corresponding channel number in the DMA controller. Bit 0 corresponds to
DMA channel and bit M-1 corresponds to DMA channel M-1.
When Written:
DMA_BS_CLR.CHAN[C] = 0, No effect. Use the DMA_BS_SET register to enablebyte swap on channel C.
DMA_BS_CLR.CHAN[C] = 1, Disables Byte Swap on channel C.

11–24

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Bytes Swap Enable Set
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W)
Byte Swap Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W)
Byte Swap Status

Figure 11-11: DMA_BS_SET Register Diagram
Table 11-14: DMA_BS_SET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W)

Byte Swap Status.
This register is used to configure a DMA channel to use byte swap. Each bit of theregister represents the corresponding channel number in the DMA controller. Bit 0
corresponds to DMA channel 0 and bit M-1 corresponds to DMA channel M-1 When
Read: DMA_BS_SET.CHAN[C] = 0, Channel C Byte Swap is disabled.
DMA_BS_SET.CHAN[C] = 1, Channel C Byte Swap is enabled. When Written:
DMA_BS_SET.CHAN[C] = 0, No effect. Use the DMA_BS_CLR register to disablebyte swap on channel C DMA_BS_SET.CHAN[C] = 1, Enables Byte Swap on channel
C.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–25

ADuCM4050 DMA Register Descriptions

DMA Configuration
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

MEN (W)
Controller Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 11-12: DMA_CFG Register Diagram
Table 11-15: DMA_CFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
0 MEN(RX/W)

Controller Enable.
0 Disable controller
1 Enable controller

11–26

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Destination Address Decrement Enable Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (W)Disable Destination Address Decrement
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (W)Disable Destination Address Decrement

Figure 11-13: DMA_DSTADDR_CLR Register Diagram
Table 11-16: DMA_DSTADDR_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(RX/W)Disable Destination Address Decrement.
The DMA_DSTADDR_CLR write-only register enables the user to configure a DMA
channel to use the default destination address in increment mode. Each bit of the register represents the corresponding channel number in the DMA controller.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_DSTADDR_CLR.CHAN[C] = 0, No effect. Use the DMA_DSTADDR_SET register to enable destination address decrement on channel C.
DMA_DSTADDR_CLR.CHAN[C] = 1, Disables destination address decrement onchannel C.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–27

ADuCM4050 DMA Register Descriptions

DMA Channel Destination Address Decrement Enable Set
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W)
Destination Address Decrement Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W)
Destination Address Decrement Status

Figure 11-14: DMA_DSTADDR_SET Register Diagram
Table 11-17: DMA_DSTADDR_SET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W)

Destination Address Decrement Status.
The DMA_DSTADDR_SET register is used to configure the destination address of a
DMA channel to decrement the address instead of incrementing the address after eachaccess. Each bit of the register represents the corresponding channel number in the
DMA controller. Bit 0 corresponds to DMA channel and bit M-1 corresponds to
DMA channel M-1.
When Read:
DMA_DSTADDR_SET.CHAN[C] = 0, Channel C destination address decrement isdisabled.
DMA_DSTADDR_SET.CHAN[C] = 1, Channel C destination address decrement isenabled.
When Written:
DMA_DSTADDR_SET.CHAN[C] = 0, No effect. Use the DMA_DSTADDR_CLR register to disable destination address decrement on channel C.
DMA_DSTADDR_SET.CHAN[C] = 1, Enables destination address decrement onchannel C.

11–28

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Enable Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (W)Disable DMA Channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (W)Disable DMA Channels

Figure 11-15: DMA_EN_CLR Register Diagram
Table 11-18: DMA_EN_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(RX/W)Disable DMA Channels.
This register allows for the disabling of DMA channels. This register is write only.
Each bit of the register represents the corresponding channel number in the DMA
controller. Note: The controller disables a channel automatically, by setting the appropriate bit, when it completes the DMA cycle. Set the appropriate bit to disable the corresponding channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_EN_CLR.CHAN[C] = 0, No effect. Use the DMA_EN_SET register to enable
the channel.
DMA_EN_CLR.CHAN[C] = 1, Disables channel C.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–29

ADuCM4050 DMA Register Descriptions

DMA Channel Enable Set
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W)
Enable DMA Channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W)
Enable DMA Channels

Figure 11-16: DMA_EN_SET Register Diagram
Table 11-19: DMA_EN_SET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W)

Enable DMA Channels.
This register allows for the enabling of DMA channels. Reading the register returns theenable status of the channels. Each bit of the register represents the corresponding
channel number in the DMA controller. Set the appropriate bit to enable the corresponding channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M -1
When Read:
DMA_EN_SET.CHAN[C] = 0, Channel C is disabled.
DMA_EN_SET.CHAN[C] = 1, Channel C is enabled.
When Written:
DMA_EN_SET.CHAN[C] = 0, No effect. Use the DMA_EN_CLR register to disable
the channel.
DMA_EN_SET.CHAN[C] = 1, Enables channel C.

11–30

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA per Channel Error Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W1C)
Per Channel Bus Error Status/Clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W1C)
Per Channel Bus Error Status/Clear

Figure 11-17: DMA_ERRCHNL_CLR Register Diagram
Table 11-20: DMA_ERRCHNL_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W1C)Per Channel Bus Error Status/Clear.
This register is used to read and clear the per channel DMA bus error status. The error
status is set if the controller encountered a bus error while performing a transfer. If a
bus error occurs on a channel, that channel is automatically disabled by the controller.
The other channels are unaffected. Write one to clear bits.
When Read:
0: No bus error occurred.
1: A bus error control is pending.
When Written:
0: No effect.
1: Bit is cleared.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–31

ADuCM4050 DMA Register Descriptions

DMA Bus Error Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W1C)
Bus Error Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W1C)
Bus Error Status

Figure 11-18: DMA_ERR_CLR Register Diagram
Table 11-21: DMA_ERR_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W1C)Bus Error Status.
This register is used to read and clear the DMA bus error status. The error status is set
if the controller encountered a bus error while performing a transfer or when it reads
an invalid descriptor (whose cycle control is 3'b000). If a bus error occurs or invalid
cycle control is read on a channel, that channel is automatically disabled by the controller. The other channels are unaffected. Write one to clear bits.
When Read:
0: No bus_error/invalid cycle control occurred.
1: A bus_error/invalid cycle control is pending.
When Written:
0: No effect.
1: Bit is cleared.

11–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA per Channel Invalid Descriptor Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W1C)
Per Channel Invalid Descriptor Status/Clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W1C)
Per Channel Invalid Descriptor Status/Clear

Figure 11-19: DMA_INVALIDDESC_CLR Register Diagram
Table 11-22: DMA_INVALIDDESC_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W1C)Per Channel Invalid Descriptor Status/Clear.
This register is used to read and clear the per channel DMA invalid descriptor status.
The per channel invalid descriptor status is set if the controller reads an invalid descriptor (cycle control is 3'b000). If it reads invalid cycle control for a channel, thatchannel is automatically disabled by the controller. The other channels are unaffected.
Write one to clear bits.
When Read:
0: No invalid cycle control occurred.
1: An invalid cycle control is pending.
When Written:
0 No effect.
1 Bit is cleared.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–33

ADuCM4050 DMA Register Descriptions

DMA Channel Primary Control Database Pointer
The DMA_PDBPTR register must be programmed to point to the primary channel control base pointer in the system memory. The amount of system memory that must be assigned to the DMA controller depends on the numberof DMA channels used and whether the alternate channel control data structure is used. This register cannot be readwhen the DMA controller is in the reset state.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ADDR[15:0] (R/W)
Pointer to the Base Address of thePrimary Data Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ADDR[31:16] (R/W)
Pointer to the Base Address of thePrimary Data Structure

Figure 11-20: DMA_PDBPTR Register Diagram
Table 11-23: DMA_PDBPTR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 ADDR
(R/W)

11–34

Pointer to the Base Address of the Primary Data Structure.
5 + log(2) M LSBs are reserved and must be written 0. M is number of channels.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Priority Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHPRICLR[15:0] (W)Configure Channel for Default Priority
Level
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHPRICLR[26:16] (W)Configure Channel for Default Priority
Level

Figure 11-21: DMA_PRI_CLR Register Diagram
Table 11-24: DMA_PRI_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHPRICLR(RX/W)

Configure Channel for Default Priority Level.
The DMA_PRI_CLR write-only register enables the user to configure a DMA channel
to use the default priority level. Each bit of the register represents the corresponding
channel number in the DMA controller. Set the appropriate bit to select the default
priority level for the specified DMA channel.
Bit 0 corresponds to DMA channel and bit M-1 corresponds to DMA channel M-1.
When Written:
DMA_PRI_CLR.CHPRICLR[C] = 0, No effect. Use the DMA_PRI_SET register to
set channel C to the high priority level.
DMA_PRI_CLR.CHPRICLR[C] = 1, Channel C uses the default priority level.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–35

ADuCM4050 DMA Register Descriptions

DMA Channel Priority Set
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (W)Configure Channel for High Priority
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (W)Configure Channel for High Priority

Figure 11-22: DMA_PRI_SET Register Diagram
Table 11-25: DMA_PRI_SET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(RX/W)

Configure Channel for High Priority.
This register enables the user to configure a DMA channel to use the high priority level. Reading the register returns the status of the channel priority mask. Each bit of theregister represents the corresponding channel number in the DMA controller. Returns
the channel priority mask status, or sets the channel priority to high.
Bit 0 corresponds to DMA channel 0, bit M-1 corresponds to DMA channel M-1.
When Read:
DMA_PRI_SET.CHAN[C] = 0, DMA channel C is using the default priority level.
DMA_PRI_SET.CHAN[C] = 1, DMA channel C is using a high priority level.
When Written:
DMA_PRI_SET.CHAN[C] = 0, No effect. Use the DMA_PRI_CLR register to set
channel C to the default priority level.
DMA_PRI_SET.CHAN[C] = 1, Channel C uses the high priority level.

11–36

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Controller Revision ID
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

VALUE (R)DMA Controller Revision ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 11-23: DMA_REVID Register Diagram
Table 11-26: DMA_REVID Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUEDMA Controller Revision ID.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–37

ADuCM4050 DMA Register Descriptions

DMA Channel Request Mask Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (W)Clear Request Mask Set Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (W)Clear Request Mask Set Bits

Figure 11-24: DMA_RMSK_CLR Register Diagram
Table 11-27: DMA_RMSK_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(RX/W)

Clear Request Mask Set Bits.
This register enables DMA requests from peripherals by clearing the mask set in
DMA_RMSK_SET register. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate bit to clear the corresponding
DMA_RMSK_SET.CHAN bit.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_RMSK_CLR.CHAN[C] = 0, No effect. Use the DMA_RMSK_SET register todisable DMA requests.
DMA_RMSK_CLR.CHAN[C] = 1, Enables peripheral associated with channel C togenerate DMA requests.

11–38

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Request Mask Set
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W)
Mask Requests from DMA Channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W)
Mask Requests from DMA Channels

Figure 11-25: DMA_RMSK_SET Register Diagram
Table 11-28: DMA_RMSK_SET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W)

Mask Requests from DMA Channels.
This register disables DMA requests from peripherals. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate
bit to mask the request from the corresponding DMA channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Read:
DMA_RMSK_SET.CHAN[C] = 0, Requests are enabled for channel C.
DMA_RMSK_SET.CHAN[C] = 1, Requests are disabled for channel C.
When Written:
DMA_RMSK_SET.CHAN[C] = 0, No effect. Use the DMA_RMSK_SET register to enable DMA requests.
DMA_RMSK_SET.CHAN[C] = 1, Disables peripheral associated with channel C fromgenerating DMA requests.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–39

ADuCM4050 DMA Register Descriptions

DMA Channel Source Address Decrement Enable Clear
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (W)Disable Source Address Decrement
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (W)Disable Source Address Decrement

Figure 11-26: DMA_SRCADDR_CLR Register Diagram
Table 11-29: DMA_SRCADDR_CLR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(RX/W)Disable Source Address Decrement.
The DMA_SRCADDR_CLR write-only register enables the user to configure a DMA
channel to use the default source address in increment mode. Each bit of the register
represents the corresponding channel number in the DMA controller.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_SRCADDR_CLR.CHAN[C] = 0, No effect. Use the DMA_SRCADDR_SET register to enable source address decrement on channel C.
DMA_SRCADDR_CLR.CHAN[C] = 1, Disables Address source decrement on channel
C.

11–40

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Source Address Decrement Enable Set
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (R/W)
Source Address Decrement Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (R/W)
Source Address Decrement Status

Figure 11-27: DMA_SRCADDR_SET Register Diagram
Table 11-30: DMA_SRCADDR_SET Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(R/W)

Source Address Decrement Status.
The DMA_SRCADDR_SET register is used to configure the source address of a DMA
channel to decrement the address instead of incrementing the address after each access.
Each bit of the register represents the corresponding channel number in the DMA
controller. Bit 0 corresponds to DMA channel and bit M-1 corresponds to DMA
channel M-1.
When Read:
DMA_SRCADDR_SET.CHAN[C] = 0, Channel C Source Address decrement is disabled.
DMA_SRCADDR_SET.CHAN[C] = 1, Channel C Source Address decrement is enabled.
When Written:
DMA_SRCADDR_SET.CHAN[C] = 0, No effect. Use the DMA_SRCADDR_CLR register to disable source address decrement on channel C.
DMA_SRCADDR_SET.CHAN[C] = 1, Enables source address decrement on channel
C.

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11–41

ADuCM4050 DMA Register Descriptions

DMA Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

MEN (R)
Enable Status of the Controller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

CHANM1 (R)Number of Available DMA Channels
Minus 1Figure 11-28: DMA_STAT Register Diagram
Table 11-31: DMA_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
20:16 CHANM1(R/NW)0 MEN(R/NW)

Number of Available DMA Channels Minus 1.
With 27 channels available, the register will read back 0x1A.
Enable Status of the Controller.
0 Controller is disabled
1 Controller is enabled

11–42

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 DMA Register Descriptions

DMA Channel Software Request
The DMA_SWREQ register enables the generation of software DMA request. Each bit of the register represents thecorresponding channel number in the DMA controller. M is the number of DMA channels
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[15:0] (W)Generate Software Request
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CHAN[26:16] (W)Generate Software Request

Figure 11-29: DMA_SWREQ Register Diagram
Table 11-32: DMA_SWREQ Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26:0 CHAN(RX/W)

Generate Software Request.
Set the appropriate bit to generate a software DMA request on the corresponding
DMA channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_SWREQ.CHAN[C] = 0, Does not create a DMA request for channel C.
DMA_SWREQ.CHAN[C] = 1, Generates a DMA request for channel C.
These bits are automatically cleared by the hardware after the corresponding software
request completes.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

11–43

Cryptography (CRYPTO)

12 Cryptography (CRYPTO)

Crypto is a hardware accelerator block that encloses the AES Cipher, NIST Block modes of operation, SHA-256
hash function generator, Keyed HMAC accelerator, Key wrap and unwrap module, and a protected key storage.
Advanced Encryption Standard (AES) is the specification for a symmetric key algorithm to encrypt electronic data
announced by the National Institute of Standards and Technology (NIST) in the year 2001 to replace the older
DES Standard. The AES algorithm operates on a fixed data block of 128 bits.
Block modes of operation are confidential and authentication modes of operation for use with a symmetric key
block cipher algorithm. In this block, the supported symmetric key cipher is AES.
Secure Hash Algorithm (SHA) is a hashing algorithm that works on messages parsed into 512-bit data blocks andgenerates a digest.
Keyed HMAC is a SHA-256 based algorithm to generate a Message Authentication Code (MAC) in combination
with a secret cryptographic key.
Key wrap and unwrap module is a NIST approved key encryption-decryption algorithm for secure storage andtransport of keys.
Protected key storage is a dedicated space accessible only by the crypto module for secure non-volatile storage of
cryptographic keys.
This document assumes familiarity with the operation of the AES standard, NIST block cipher modes of operation,
SHA-256 algorithm, SHA-256 based Keyed HMAC, and Key wrap-unwrap algorithms. For more information, referto the following publications.
Table 12-1: NIST Publication List
AES standard

Federal Information Processing Standard (FIPS) 197

NIST Block Modes of Operation

Special Publication-800-38A, B & C

SHA

FIPS 180-4

HMAC

FIPS 198-1 (Keyed HMAC)

Key Wrap

SP800-38F (Methods for Key Wrapping)

CCM*

Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–1

Crypto Features

Crypto Features
The ADuCM4050 MCU supports the following features:• 32-bit APB Slave• Two 128-bit buffers:• Input buffer• Output buffer• One 512-bit buffer to store input data for HMAC and SHA modes• Two DMA channels:• Input buffer• Output buffer• AES Cipher Key Lengths supported:• 128-bit• 256-bit• AES Cipher Key Source• Programmable through MMR• Not readable (read as zero in software)• Supported Modes:• AES Cipher Encryption and Decryption in ECB Mode
• AES Cipher Encryption and Decryption in CBC Mode
• AES Cipher Encryption and Decryption in CTR Mode
• AES Cipher MAC Generation Mode
• AES Cipher Encryption and Decryption in CCM Mode
• AES Cipher Encryption and Decryption in CCM* Mode
• SHA - 256 Mode
• Protected key storage with key wrap and unwrap• HMAC signature generation

Crypto Functional Description
This section provides information on the function of the Crypto block used by the ADuCM4050 MCU.
12–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCrypto Functional Description

Crypto Block Diagram
The figure shows the Crypto block used by the ADuCM4050 MCU.

Figure 12-1: Crypto Block

Crypto is a 32-bit APB DMA capable peripheral. There are two buffers provided for data I/O operations. Thesebuffers are 32-bit wide and will read in or read out 128-bits in four data accesses. Input data and output data byte
swapping is supported using CRYPT_CFG.AES_BYTESWAP and CRYPT_CFG.SHA_BYTESWAP configuration
bits. Additionally, the CRYPT_CFG.KEY_BYTESWAP bit allows software to byte swap key when programmingthem to MMR.
When enabled, the block takes the data from its input buffer and gives out the processed data through the output
buffer. DMA can be used for performing these data operations, which is critical to save power. Ensure that the configuration bits, keys and other relevant registers are set to the desired values before the block is enabled and datatransfer is initiated.

Crypto Operating Modes
The following block modes of operation are supported:• CTR mode: Counter mode
• CBC mode: Cipher Block Chaining mode
• MAC mode: Message Authentication Code
• CCM mode: Cipher Block Chaining-Message Authentication Code mode
• ECB mode: Electronic Code Book mode
• CCM* mode: Modified CCM for WPAN Standard

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12–3

Crypto Data Transfer

Crypto also supports the following modes of operation:• PrKStor Mode: Protected Key Storage with hardware accelerators for Key wrap and unwrap in a secure setting• SHA-256: Hash generating using SHA-256 algorithm• Keyed HMAC: SHA-256 based authentication mode
Mode enable bit fields in the CRYPT_CFG register must be set to enable the desired mode of operation. A particular block mode is enabled by setting the appropriate bit field to 1.
Enable only one block mode of operation at a given time.
The following are the bit fields to enable different modes of operation: CRYPT_CFG.ECBEN,CRYPT_CFG.CTREN, CRYPT_CFG.CBCEN, CRYPT_CFG.CCMEN, CRYPT_CFG.CMACEN,
CRYPT_CFG.SHA256EN, CRYPT_CFG.PRKSTOREN, and CRYPT_CFG.HMACEN.
Enabling multiple block modes causes unpredictable results. No error or warning is flagged. CCM* mode is enabled
by using the CRYPT_CFG.CCMEN bit.
Encryption/Decryption
The CRYPT_CFG.ENCR bit is used to select encryption/decryption operation for the different block modes involving the AES cipher. When decryption is enabled, the key schedule value for the final round is calculated andwritten back into the AESKEY register set by overwriting the original AESKEY values. Therefore, for a new encryption operation, the AESKEY values must be programmed again.

Crypto Data Transfer
The input buffer and the output buffer hold 128-bits of data. Being a peripheral on a 32-bit APB bus, the block isaccessed by a 32-bit data bus. Therefore, four reads/writes are required to empty/fill the output/input buffer.
In SHA256 mode, the results are updated in the CRYPT_SHAH0.SHAHASH0 to CRYPT_SHAH7.SHAHASH7
registers, and are not given out in the output buffer. Results for block modes of operation are streamed out of theoutput buffer.

Crypto Data Rate
Depending on the block mode and key length chosen for the AES Cipher, the rate at which data is processedchanges.
The following list shows the computation time involved in different block modes of operation. The numbers do notinclude the buffer read and write time which are controlled by the DMA or core data rates. The rates are written for
128/256 key length cases.
• ECB Mode: 40/56 clock cycles• CBC Mode: 40/56 clock cycles

12–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCrypto Data Transfer• CTR Mode: 40/56 clock cycles• MAC Mode: 40/56 clock cycles• CCM Mode: 80/102 clock cycles
If input buffer is provided with data at the rate of one word per clock cycle, SHA-256 computation takes 64 clock
cycles. Input data rate is less than one word per 2 clock cycles as Crypto input data buffer supports APB protocol.

Data Pipeline
In block mode of operation, as soon as 128 bits of data (say block B1) is written into the input buffer, the data is
copied internally for computation and the next 128 bits of data (say block B2) may be written into the input buffer.
By the time block B2 is written, if computation on the block B1 is not complete, the input buffer will remain fulland further writes will not be permitted. Appropriate interrupts and status registers are updated. As soon as block B1
processing is completed the results are moved to the output buffer and computation begins on the B2. If B1 is notread out of the output buffer by the time processing on B2 is completed, the block stalls. Appropriate interrupt andstatus registers are set.

DMA Capability
The block supports use of DMA to transfer data to or from the buffers. The DMA is expected to do four wordtransfers per DMA request on both the input and output buffers. The DMA requesting for the buffers can be enabled by setting the CRYPT_CFG.INDMAEN and CRYPT_CFG.OUTDMAEN bits. The block raises the input buffer DMA request line high till the input buffer is filled. Similarly, the DMA request on the output buffer is heldhigh till the output buffer is emptied.
The programmer must not change the configuration bits in the middle of a data transaction. Else, it may result inwrong output, and no error or warning is raised.

Core Transfer
If DMA is not used, then the software is expected to keep track of the number of words that are to be transferred tothe block and read back from the block. The bit-fields that indicate the status and error conditions are available in
the CRYPT_STAT register. The interrupts for different conditions can be enabled in the CRYPT_INTEN register.
DMA based data transfer is recommended as it is performance efficient and power efficient.

Data FormattingThis section explains how to map the input data and keys to the Crypto registers, and the format in which data canbe expected from the output buffer.
Consider the following key, input data, and output data. The key, plain text, and cipher text are taken from the data
mentioned in the NIST standard.
Key[0:15]: 2b7e151628aed2a6abf7158809cf4f3c
Plain text[0:15]: 6bc1bee22e409f96e93d7e117393172a

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–5Data Formatting

Cipher Text[0:15]: 3ad77bb40d7a3660a89ecaf32466ef97

This 128-bit key is mapped to the AESKEY registers as follows:
AESKEYi = Key[i*4+3:i*4];

For the above example,
AESKEY0[31:0] = 0x16157e2b;
AESKEY1[31:0] = 0xa6d2ae28;
AESKEY2[31:0] = 0x8815f7ab;
AESKEY3[31:0] = 0x3c4fcf09;

The plain text must be fed to the input buffer via APB writes using DMA/Core as follows:for (i=0; i<4; i++){
Input_buffer = plain_text[i*4+3:i*4];}

The example plain text can be mapped to input buffer writes as follows:
write(Input_buffer, 0xe2bec16b);
write(Input_buffer, 0x 969f402e);
write(Input_buffer, 0x117e3de9);
write(Input_buffer, 0x2a179373);

The ciphertext block can be read from the output buffer in four consecutive reads.
for (i=0; i<4; i++){cipher_text [i*4+3:i*4] = read(output_buffer);}

Byte-Swap Configuration
Three configuration bits have been provided for byte swapping the data written to the crypto buffers and key registers.
A byte swap operation is defined as:
Input String: 0xB3B2B1B0
Ouput String: 0xB0B1B2B3

AES_BYTESWAPThis bit when set, byte swaps the data written to input buffer for block modes of operation and also the expected
data out of the output buffer.
SHA_BYTESWAPThis bit when set, byte swaps the data written to input buffer for SHA and HMAC operations.

12–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceInterrupts

KEY_BYTESWAP
Additional flexibility has been provided to byte swap the data written to CRYPT_AESKEY0-CRYPT_AESKEY7 ,CRYPT_KUW0-CRYPT_KUW15, CRYPT_KEYValStr1, and CRYPT_KEYValStr2 registers.

Interrupts
INRDY
This interrupt indicates that the input buffer is not full. If enabled, this triggers interrupts as long as the input buffer
is not filled. As this interrupt is used when the data buffer is being written by the core, fill the input buffer from the
ISR.
This interrupt must be used to feed data to the Crypto accelerators for all AES based operations. This interrupt
must not be used for any SHA based operation or HMAC accelerator.
OUTRDYThis interrupt indicates that the output buffer holds data and is waiting to be read. This will remain set as long as
the output buffer is not empty. As this interrupt is used when the data buffer is being read by the core, read theentire 128-bits in the ISR.
This interrupt is to be used with AES block cipher modes only and not with SHA.
SHADONE
This interrupt indicates that the SHA computation is completed. New data may be written into the input buffer orthat the hash results may be read out of the CRYPT_SHAH0 to CRYPT_SHAH7 registers.
INOVR
This interrupt indicates that the input buffer overflow event has occurred. The causes for this may be:• The output buffer has not been read. This stalls the block.
• The input data rate is higher than the rate the Crypto block can process.
When the DMA or core program is programmed as recommended, this interrupt must not be raised.
Crypto operation is not reliable if input overflows.
HMACDONEThis interrupt indicates that the final step in the HMAC operation is complete. The result of the HMAC operation
can be read from the SHARES register set.
HMACMSGRDYThis status bit indicates that the HMAC block has finished hashing the KEY IPAD and is ready to take data input.
The corresponding status bit must be cleared in the interrupt routine. Once the HMAC controller has finished

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–7Crypto Error Conditions

hashing the current data block this interrupt will trigger again is enabled. For the last message data block, the software must indicate it using CRYPT_SHA_LAST_WORD.O_LAST_WORD and
CRYPT_SHA_LAST_WORD.O_BITS_VALID bits.
PRKSTOR_CMD_DONE
This bit indicates that the protected key store operation is done. Support for several operations including key wrapunwrap and storing the keys in a secure area in the flash is provided.

Crypto Error Conditions
If a read is attempted from the output buffer when the output data buffer is empty, there is an underflow error. The
block does not generate a DMA request on the Output buffer channel when the output buffer is empty.
If the Crypto block is disabled at any stage during the computation, the data output is no longer reliable. The statemachine is reset.
If a write is attempted to the input buffer when it is full, there will be an overflow error. The block does not generate
a DMA request on the Input buffer channel when the Input buffer is full.
The input and output buffers can be flushed by writing 1 to the corresponding flush bits in the CRYPT_CFG register.
Interrupts can be enabled by writing 1 into the corresponding bits in the CRYPT_INTEN register.
Clearing interrupts is to be done by writing 1 to the respective bits in the CRYPT_STAT register.
The protected key store mode (CRYPT_CFG.PRKSTOREN or CRYPTO_CFG.BLKEN bit) must not be disabledby the software if the CRYPT_STAT.PRKSTORBUSY bit is set.

Crypto Status Bits
INWORDS/OUTWORDS
These fields hold information about the number of words the input and output Buffers contain at that moment.
This information can be used in situations when the Input/output Buffers are not empty/full to know the number
words which need to be written or read.
SHADONE
This field indicates that the hash computation on the currently provided data is complete.
SHABUSY
This field indicates that hash computation is on-going. When this signal goes low, it is an indication that hash computation is complete and that the user can read out the hash result.

12–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCrypto Status Bits

INOVRThis field indicates that an overflow event has occurred on the input buffer. The status bit is sticky and can becleared by writing 1 into the bit field.
HMACDONEThis bit indicates that the HMAC operation on the current message input is complete and the result can be read outof the SHARES register set.
HMACBUSYThis bit indicates that HMAC accelerator is currently busy. If this bit is set, the result in the SHARES register set isan intermediate result and is read as zero.
HMACMSGRDYThis bit indicates that the HMAC block is ready to take message input from the user, that is, the first stage of
SHA256 computation with key xor ipad is done. This bit further goes low while SHA256 is processing the current
message input block.
PRKSTOR_CMD_DONE
This bit when set indicates that the current PrKStor command has finished and further commands can be issued to
PrKStor.
PRKSTOR_CMD_FAIL
This nit when set along with the CRYPT_STAT. PRKSTOR_CMD_DONE bit indicates that the current PrKStor
command has failed.
The following are the reasons for the failure:• Unwrap Command: It may fail when the validation string obtained after unwrap does not match any of thethree validation strings specified in the document.
• RETRIEVE_KEY: This command can fail due to no response from flash controller or the key being corrupted
due to ECC errors. In this case, the retrieved key is zeroed in the KUW registers.
• Erase and Destroy commands: They may fail due to no response from flash as flash may be busy in some operation when the commands were issued.
PRKSTOR_RET_STATUS
These status bits indicates the ECC status from flash reads which is similar to the ECC status in flash.
CMD_ISSUED
This retains the last command issued until the mode or block is disabled or a new command is issued.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–9Crypto Keys

PRKSTOR_BUSY
This status bit indicates that a command is in progress and PrKStor should not disabled during this stage. An ongoing PrKStor command must be allowed to complete before going to hibernate to maintain the integrity of the
PrKStor.

Crypto Keys
User must program the key used for the AES Cipher in the key registers from CRYPT_AESKEY0 to
CRYPT_AESKEY7.

Key Length
The AES Cipher can be used with two different ley lengths: 128 and 256 bits. It is selected by setting the
CRYPT_CFG.KEYLEN bit. The registers CRYPT_AESKEY0 to CRYPT_AESKEY7 hold the key to be used in
the AES Cipher.
CRYPT_CFG.KEYLEN when set to 0x2 indicates that a 256-bit key is used. When reset to 0x0, it indicates that a
128-bit key is used for Crypto operation.

Key Programming
The key registers can be programmed in any order. Registers that are used for key length 256 must not be programmed when the selected key length is 128 bits.
The following list shows how the key (K) used for the AES Cipher operations are constructed from the AESKEY
register set:
CRYPT_AESKEY0 = K[31:0]
CRYPT_AESKEY1 = K[63:32]
CRYPT_AESKEY2 = K[95:64]
CRYPT_AESKEY3 = K[127:96]
CRYPT_AESKEY4 = K[159:128]. Used only in case of Key Length 256.
CRYPT_AESKEY5 = K[191:160]. Used only in case of Key Length 256.
CRYPT_AESKEY6 = K[223:192]. Used only in case of Key Length 256.
CRYPT_AESKEY7 = K[255:224]. Used only in case of Key Length 256.
NOTE: Partial writes to the key registers are not allowed. To use a new key (same or different lengths), all the key
registers must be updated, even if the previous or new values for a given AESKEY register is same.

12–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCrypto Keys

Key Wrap-Unwrap Register
The CRYPT_KUW0 - CRYPT_KUW15 register set stores the wrapped/unwrapped key that is to be unwrapped/
wrapped, respectively.
The result of the wrap/unwrap operation is stored in the same register set. Additionally, CRYPT_KUWVALSTR1
and CRYPT_KUWVALSTR2 registers store the additional content that is generated by the virtue of the validation
string used to wrap the key. While wrapping a key, the validation string needed for the wrap operation is stored inthese registers.
The validation strings registers are readable only post an unwrap operation. A secure software may use this validation
string to implement a software based key validation.

Key Register Attributes
This field indicates that an overflow event has occurred on the input buffer. The status bit is sticky and can becleared by writing 1 into the bit field.
Key registers refer to the CRYPT_AESKEY0 - CRYPT_AESKEY7 register set, CRYPT_KUW0- CRYPT_KUW15
register set, CRYPT_KUWVALSTR1 and CRYPT_KUWVALSTR2 registers.
The following features are implemented to ensure secure usage of cryptographic key:
• The key registers are not readable by software.
• The validation string register used in a wrap-unwrap operation are only readable in a specific read window
which extends post an unwrap command to the issue of next PrKStor command or block disable, whichever isearlier. The read value can be used to associate key-usage validation metadata with a given key.
• The key registers except validation string registers are reset on partial writes. The software must program full
key when a new key is to be used with the hardware accelerator.
• Any changes in the key length, resets the key registers and key validation registers to default values.

Crypto Power Saver Mode
Enabling the power saver mode in the CRYPT_CFG.BLKEN register enables an automatic clock gating function.
This reduces the clocking activity in the block to the barest minimum possible. It is recommended to keep this on as
there is not performance hit by having this enabled.

Registers with Mode Specific RolesDATALENThe CRYPT_DATALEN register is used to specify the length of the payload data. This information is used in CCM
and MAC modes of operation.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–11Registers with Mode Specific Roles• CCM Mode: Program the number of 128-bit data blocks in the resulting aligned payload. CRYPT_DATALEN[15:0] is provided for this purpose. CCM supports data lengths which are not a multiples of 16 bytes. The
number of blocks must be rounded off to the next integer. For example, if the number of blocks in data is 4.5,
the data length must be programmed to 5.
• CMAC Mode: Pad the payload data to ensure that the total number of bits is an integral multiple of 128. Program the number of 128-bit blocks in the aligned payload data. CRYPT_DATALEN [19:0] is provided forthis purpose. For example, if the data length is 56 bytes, the data length must be programmed to 4.
PREFIXLENThe CRYPT_PREFIXLEN register is used to specify the length of the associated data that is only authenticated.
This information is used in CCM mode of operation.
CCM Mode: Pad the associated data enough zeroes with to ensure that the total number of bits is an integral multiple of 128. Then, program the number of 128-bit blocks in the resulting aligned payload data.
CRYPT_PREFIXLEN.VALUE bits are provided for this purpose.
NONCExThe CRYPT_NONCE0 to CRYPT_NONCE3 registers are used to program the nonce for CTR, CBC, and CCM
Modes of operation.
The Nonce is constructed in the following way:
Nonce[127:0] = {CRYPT_NONCE3[31:0], CRYPT_NONCE2[31:0], CRYPT_NONCE1[31:0],
CRYPT_NONCE0[31 :0]}
Different lengths of Nonce are used in different block modes of operation:• CTR Mode: This mode uses a 108-bit long Nonce. In this mode, the encryption operation is performed in thefollowing format:
Ciphertext_Block = Ciph ({Nonce[107:0], CRYPT_CNTRINIT[19:0] ) xor Payload_Block• CBC Mode: In this mode, 128 bits of the Nonce are used. The nonce is used as the initialization vector.
Initialization_Vector = Nonce[127:0]• CCM Mode: In this mode, 112 bits are used. The nonce is used in the Counter mode computation. The datais constructed in the following format:
Ciphertext_Block = Ciph ({Nonce[111:0], Counter[15:0]} ) xor Payload_BlockSHARESx
The results from the SHA hash operations are to be read out of the SHARES register set in the following format:
HASH[255:0] = {SHARES7[31:0], SHARES6[31:0], SHARES5[31:0], SHARES4[31:0],
SHARES3[31:0], SHARES2[31:0], SHARES1[31:0], SHARES0[31:0]}

12–12

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProtected Key Storage (PrKStor)

CNTRINIT
This value initializes the counter generating function. The counter generating function implemented in this block is
an incrementing function, i.e. this function counts up by 1 for every new data block. The initialization value for thecounters can be programmed in the CRYPT_CNTRINIT register.
Counter widths for CTR mode and CCM modes are:
• CTR Mode: 20-bit counter. If counter starts from zero, then 16 GB of data will be processed before the counter overflows. A 20-bit register for initializing the counter is provided.
• CCM Mode: 16-bit counter. If counter starts from zero, then 1 GB of data will be processed before the counter
overflows. A 16-bit counter initialization register is provided.
The fixed bit width of the counter implies that there is a limit to the maximum length of data that can beencrypted without repeating the same counter values. This is 16 MB of Payload data in CTR Mode and 1 MBof confidentiality data in CCM mode.
NOTE: When the counters reach the maximum value, the next data input causes them to rollover back to zero.
SHAINIT
This is an auto-clear register field. The control signal is to be used to initialize the SHA computation registers toreset value when a new computation is initiated
SHA_LAST_WORD
SHA-256 module is updated to include a length counter and padding mask. Software does not need to append the
padding and bit length at the end of a message.
SHA control register has the following fields:• last_word• bits_valid [4:0]Software loads the input data as a word (32 bits) to the crypto accelerator input buffer. The input data may or may
not be a multiple of 32 bits. User must set the last_word bit, bits_valid bit to number of bits valid in the last word
(0-31), and write the last word to the crypto accelerator. The LSBs of this word are ignored (replaced with padding)according to the SHA standard. If data length is a multiple of 32 bits, user must write a dummy word to complete
the final operation (all bits are replaced with padding).
NOTE: For the last word in the message, last_word must be asserted and bits_valid must reflect the number of valid
bits in last_word. If all the bits are valid, the word must be written first, and a dummy word (which is the last word)is written with no bits valid. Invalid bits are ignored.

Protected Key Storage (PrKStor)
This platform provides a secure nonvolatile location for the storage of cryptographic keys in the form of a Protected
Key Storage (PrKStor) region of flash memory. PrKStor consists of two 2 KB pages and provides protected storage
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Protected Key Storage (PrKStor)for up to 51 keys per page (102 keys in total). Each key record supports keys of size 320 bits and is identified by aPage and Index value. Software can store a 128-bit or 256-bit wrapped and unwrapped key into this 320-bit space.
All metadata for key usage policy has to be maintained by software. The module provides a command interface forvarious key related operations and a secure key-update policy can be designed using this module in conjunction with
the Key wrap-unwrap module.
The PrKStor module is implemented as a slave to the Crypto module. All interactions with the PrKStor are performed through register access within the register address space of the Crypto module. Flash memory reserved foruse by the PrKStor is not user configurable and cannot be accessed through the flash controller.
Key Wrap-Unwrap
This functionality is added to the PrKStor to support encryption/decryption of keys. This wrapped key along withthe validation prefix is stored in the KUW register set. CRYPT_KUW0 - CRYPT_KUW15 register set and
CRYPT_KUWVALSTR1 and CRYPT_KUWVALSTR2 registers. These registers are selectively readable via the software. This read window opens post unwrap operation and before the next PrKStor command is issued.
Key Validation
Given that a secure bootloader is inbuilt to prevent any unwarranted change in the software, a secure key validation
policy can be implemented in software. To enable this secure validation, the CRYPT_KUWVALSTR1 andCRYPT_KUWVALSTR2 registers are readable in a read window post the unwrap command and before any other
PrKStor command is issued or the block/mode is disabled. Software may read this register and store any metadata
related to key validation policy along with other metadata related to the key. The software may wipe the AESKEY
and KUW register sets if the validation key does not meet the current crypto operation requirement.
Protection and Integrity• Key Wrap: The keys stored in flash can be encrypted with any random key that should be programmed in the
AESKEY register set before any wrap or unwrap operation.
• Read protection: When targeting the PrKStor flash memory only the Crypto data path is enabled (flash controller data paths are pulled to FFs).
• Write/Erase protection: When targeting PrKStor flash memory only commands from the Crypto command interface are allowed (all other flash operations are stalled). Avoid mass erase operations (by write protecting any
set of pages in user space).
• Data integrity using ECC: 1-bit error corrections and multi-bit error detections are provided by the underlying
flash controller.

Operation
PrKStor physically resides in the two most significant pages of the user space in the flash memory. These two pages
are inaccessible via normal flash memory access methods and instead made accessed using a dedicated bus/protocol
to the Cryptographic module.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProtected Key Storage (PrKStor)

Figure 12-2: PrKStor Organization

Each of the two pages of PrKStor provides a storage up to 51 cryptographic keys. A single DWORD of slack space
exists in each PrKStor page and reserved. The Crypto module may index into any arbitrary dword of either PrKStor
page. For safety, the Crypto module provides a more abstract interface to the user. User code may atomically reference individual keys by page number and index (for example, [0.0] for the least significant key of page zero; [1.50]
for the most significant key of page one).
Metadata is not stored within the PrKStor region. User must maintain own metadata to track the location of thekeys stored and validity of the keys for a particular use.

Protected Key Storage Configuration
Configuration Bits
The configuration bit fields are available in the CRYPT_PRKSTORCFG and CRYPT_CFG registers.
• Device Key: The device key is a 256-bit fixed key in RTL. This key is provided to wrap/unwrap keys locally
before storing it to the PrKStor flash storage. The device key is not known to software but can be loaded to
AESKEY register set using a PrKStor command LD_DEVICE_KEY. The software may use any other for wrap
or unwrap operation by loading the same to the AESKEY register set.
• PRKSTOREN: This bit must be set before issuing any PrKStor command.
• KEY_INDEX [6:0]: Indicates the index of the key on which the operation suggested by the PrKStor command.
The MSB suggests the page id and the remaining bits suggest the key location in the corresponding page.
• CMD [3:0]: Indicates the command to be executed in the PrKStor. These bits are auto cleared once the command is executed. The last command issued can be viewed by reading the CRYPT_STAT.CMD_ISSUED
bits.

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Protected Key Storage (PrKStor)• KUW0 to KUW7, KUWValStr1 and KUWValStr2 registers: Write-only registers. They hold the key from user
on which wrap or unwrap operation needs to be performed. For example, if a 256 + 64 bit key needs to be
unwrapped, it must be loaded to the KUW0 to KUW7 register set and KUWValStr1 and KUWValStr2 registers.
• KUWKEYLEN [2:0]: Indicate the length of the wrapped key in terms of 64-bit blocks.
If KUWKEYLEN = 0x3, the key length is 512 bits. 512-bit key is only supported for HMAC calculation andcannot be stored in the PrKStor flash storage.
For a key length of 256 bits, KUWKEYLEN must be programmed to 0x2.
For a 128-bit key, KUWKEYLEN must be programmed to 0x1.
Status Bits
The status bits are available in the CRYPT_STAT register.
• PRKSTOR_BUSY: This bit when set indicates that the PrKStor is busy in executing a command and cannot
receive a new command.
• PRKSTOR_CMD_DONE: This bit when set indicates the PrKStor has finished executing the last issued command.
• PRKSTOR_CMD_FAIL: This bit when set indicates that the last issued command has failed. Some of thesecommands depend on flash operations. If they repeatedly fail, attempt a normal flash operation and debug theissues (if any) within the flash controller.
• PRKSTOR_RET_STATUS [1:0]: If the status is 0x2, it indicates that at least one 1-bit ECC error is observed
for a RETRIVE_KEY operation but corrected. If the status is 0x1, it indicates that at least one multi-bit ECC
error during read back in a RETRIEVE_KEY operation. The resultant key may be invalid.
• CMD_ISSUED [3:0]: This field records the last command issued to the PrKStor. As the CMD field is auto
cleared after the command completes, this is provided as an option to the software to read the last commandissued.
Interrupt Enable
PRKSTRCMDONEEN: This bit when set interrupts the core on completion of any PRKSTOR command.
Protected Key Storage Commands
The following commands are supported by the PrKStor module:• WRAP: CMD = 0x1. This command indicates that a wrap operation has to be performed for the key stored in
the CRYPT_KUW0 - CRYPT_KUW7 register set.
• UNWRAP: CMD = 0x2. This command indicates that an unwrap operation is required to be performed forthe wrapped key stored in the CRYPT_KUW0 - CRYPT_KUW15 register set and CRYPT_KUWVALSTR1 andCRYPT_KUWVALSTR2 registers. Post unwrap, the validation string is readable to software before any other
PrKStor command is issued or the mode/block is disabled.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProtected Key Storage (PrKStor)

The default value of the validation string is the NIST Standard validation string: 0xA6A6A6A6A6A6A6A6• RST_DECRYPTED_KEY: CMD = 0x3. The contents of the CRYPT_KUW0 - CRYPT_KUW15 register set
can be cleared by issuing this command. Once the usage of the decrypted/unwrapped key is complete. It is
recommended that this bit is set.
• USE_DECRYPTED_KEY: CMD = 0x4. The decrypted/unwrapped key can be used for further crypto operations by issuing this command. This command loads the content of the KUW registers to the AESKEY registers. The CRYPT_CFG.AESKEYLEN is updated with the value stored in CRYPT_CFG.KUWKEYLEN once
this command is executed. No partial modification to this key is allowed by the design. Software must not program a 512-bit key in the KUW before executing this command, as AES supports only 128-bit and 256-bit key
lengths.
• LD_DEV_KEY: CMD = 0x5. This command loads the device key to the CRYPT_AESKEY0 CRYPT_AESKEY7 register set. The CRYPT_CFG.AESKEYLEN bits must be set to a 256-bit option, as Device Key is a 256-bit key. This device key can be used to wrap-unwrap any key in the CRYPT_KUW0 CRYPT_KUW15 register set.
• RETRIEVE_KEY: CMD = 0x8. The location specified by the CRYPT_PRKSTORCFG.KEY_INDEX bits isread from flash and is loaded into the CRYPT_KUW0 - CRYPT_KUW15 register set and
CRYPT_KUWVALSTR1 and CRYPT_KUWVALSTR2 registers.
• STOR_KEY: CMD = 0x9. This command when issued stores the content of the CRYPT_KUW0 CRYPT_KUW15 register set and CRYPT_KUWVALSTR1 and CRYPT_KUWVALSTR2 registers at a location
specified by the CRYPT_PRKSTORCFG.KEY_INDEX bits in flash.
• DESTROY_KEY: CMD = 0xA. This command when issued, overwrites the key with zeroes at the index specified by the CRYPT_PRKSTORCFG.KEY_INDEX field.
• ERASE_PAGE: CMD = 0xB. This command when issued, does a page erase for the page specified by the
CRYPT_PRKSTORCFG.KEY_INDEX [6] field.
Programming Flow
PrKStor is recommended to be used in core mode.
• Programming a valid KUW key: For KUW key only complete key writes are allowed. Partially modifying theKUW key is not possible, as all the KUW key registers are reset to zero when any KUW key register is overwritten. Before programming the KUW key, theCRYPT_CFG.KUWKEYLEN field must be set to the appropriate value and all the relevant key registers must be progammed.
CRYPT_CFG.KUWKEYLEN = 3'b001: KUW key length is 512 and all the registers from CRYPT_KUW0 CRYPT_KUW15 must be progammed.
CRYPT_CFG.KUWKEYLEN = 3'b010: KUW key length is 256 and all the registers from CRYPT_KUW0 CRYPT_KUW7 must be progammed.
CRYPT_CFG.KUWKEYLEN = 3'b100: KUW key length is 128 and all the registers from CRYPT_KUW0 CRYPT_KUW3 must be progammed
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Protected Key Storage (PrKStor)

To implement wrap or unwrap command on a KUW key programmed via MMR the KUW validation strings
must be programmed. No partial changes to the validation string are supported and the complete 64-bit must
be programmed at once.
When executing the USE_DECRYPTED_KEY command, the CRYPT_CFG.KUWKEYLEN must be programmed correctly. Once the command is executed the CRYPT_CFG.AESKEYLEN bit field is updated withthe value stored in CRYPT_CFG.KUWKEYLEN.
• For executing any PrKStor command, the CRYPT_CFG.PRKSTOREN and CRYPT_CFG.BLKEN bits must
be set. The configuration register is programmed first and then the block is enabled before issuing any command to PrKStor.
• Once the PrKStor is enabled it can execute a series of commands.
• When using the USE_DECRYPTED_KEY and LD_DEV_KEY commands, the CRYPT_CFG.AESKEYLEN
bit field is internally modified by the design. The decrypted key can be of length 128-bit or 256-bit only for
the USE_DECRYPTED_KEY command. The Device Key is a fixed 256-bit key. When LD_DEV_KEY is executed, the CRYPT_CFG.AESKEYLEN field is modified to a 256-bit value.
• Before going to hibernate, all PrKStor commands must be allowed to complete. The integrity of PrKStor storage cannot be guranteed if a command is stopped midway. The CRYPT_STAT.PRKSTOR_BUSY bit whenset, indicates that a command is being executed.
• The status of a command can be retrieved using the CRYPT_STAT.PRKSTOR_CMD_DONE bit. The software must also verify the pass/fail status of a command using the CRYPT_STAT.PRKSTOR_CMD_FAIL bit.
If this bit is set along with CRYPT_STAT.PRKSTOR_CMD_DONE bit, it indicates that the PrKStor command has failed.
• For a RETRIEVE_KEY operation, if there is an ECC error (correctable or not) and the KEY_CORRUPT_INT_EN bit is set, interrupts the core. It is recommended that the key location be re-written with thecorrect key and reverified.
• If the commands continue to fail after multiple retries, flash debug must be initiated.

Command Fail Status
The CRYPT_STAT.PRKSTOR_CMD_FAIL bit when set along with the
CRYPT_STAT.PRKSTOR_CMD_DONE bit, it indicates that the last issued command has failed.
PrKStor Disabled
If PrKStor is disabled due to tampering with the PrKStor pages, the following commands fail:
RETRIEVE_KEY, STOR_KEY, DESTROY_KEY, and ERASE_PAGE
Non Zero ECC Status
If any of the data retrieved from flash when a RETRIEVE_KEY command is issued has a non-zero ECC status the
RETRIEVE command fails.
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HMAC

Flash Write Corrupted
When flash is not able to execute the write command properly, the STOR_KEY command fails.
Metadata Maintenance
Software must track which keys are stored at what indices and what they should be used for. This metadata must be
updated on Destory Key commands and Bad Key status (incorrectable ECC error). It is recommended that all commands should have their start and end reflected in the metadata. If some command cannot exit cleanly, this is reflected in the metadata indicating that the corresponding PrKStor index may not behave as expected, if reused.
Key Verification
Post any PrKStor operation, the key can be verified by encrypting/decrypting a known plain text-cipher text pairwith the key.

HMAC
HMAC generation mode is added as a more secure data authentication method. For additional security, a 512-bit
key/wrap unwrap mode is also added. This facilitates the encryption/decryption of HMAC secret key K using a key
encryption key.
This module supports any length of user key K. When using a wrapped HMAC key K, the key K0 must be processed and provided by software as the maximum key wrap length supported is 512.
K: Secret key shared between the originator and intended receiver.
K0: The key K after any necessary pre-processing to form a B byte key.

HMAC Algorithm
Input Specifications• HMAC key: 512-bit preprocessed key.
If key_len < 512, HMAC key = [Key, {512 - key_len}'b0]
If key_len > 512, HMAC key = [SHA256(KEY), {512 – 256}'b0}]• Message as plain text.
Output Specifications
HMAC authentication string. Same as SHA256 result.
o_key_pad = [0x5c * blocksize] ⊕ key // Blocksize = 256
i_key_pad = [0x36 * blocksize] ⊕ key // ⊕ represents XOR operation
HMAC_Output = SHA256(o_key_pad ∥SHA256 (i_key_pad ∥ message))// ∥ represents concatenation

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HMAC

Programming Model
Configuration Bits
• HMACEN: Enables HMAC mode in Crypto accelerator.
• KEY_BYTESWAP: Enables byte swapping the data that is being loaded in the key registers.
The HMAC key is assumed to be 512 bits long. This must be preprocessed as per NIST specification document. Padding of zeros is done by hardware automatically.
• SHA_BYTESWAP: If the message input needs to be byteswapped before feeding it to the HMAC accelerator.
SHA_BYTESWAP can be reused for the same.
Status Bits
• HMACMSGRDY: Indicates that Crypto is ready to take in the text that needs to be hashed.
• HMACDONE: Indicates that the current HMAC operation is done.
• HMACBUSY: Indicates that HMAC operation is in progress.
Operation
HMAC must be enabled in the configuration register by setting the CRYPT_CFG.HMACEN bit. As the design supports preprocessed HMAC key, if the length of HMAC key is greater than 512 bits, software must perform a hashing of the key to produce an output of 256 bits, which is appended with 256 zeroes to create the HMAC key K0.
Core Mode
1. Load a valid key Ko in the KUW registers.
2. Enable HMAC.
3. Software must wait for the CRYPT_STAT.HMACMSGRDY bit or CRYPT_INTEN.HMACMSGRDYEN (interrupt mode) before the message text is input to design.
4. Software must clear the CRYPT_STAT.HMACMSGRDY bit and input one block of data (512 bits to the
HMAC accelerator).
5. After providing a full block of message to the HMAC accelerator, the software has to wait for the next
CRYPT_INTEN.HMACMSGRDYEN to feed the next block of data to the HMAC accelerator.
6. For the last block of data, similar procedure as is done for SHA needs to be done. Once all data but last word isprovided to design, CRYPT_SHA_LAST_WORD must be set and
CRYPT_SHA_LAST_WORD.O_BITS_VALID must provide the information about number of valid bits inthe last word.
7. After data is fed to HMAC accelerator, software must wait for the HMACDONE interrupt, which indicates thatthe HMAC operation is complete.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCCM/CCM* ModeDMA Mode
1. Load key K0 in the KUW registers.
2. Configure DMA for the required data transfer (except last word).
3. Enable HMAC and DMA.
4. Enable Crypto.
5. Disable the CRYPT_INTEN.HMACMSGRDYEN. DMA transfers all requisite data without any interruption
from core.
6. For last word input to SHA, same procedure as described for core mode of operation has to be followed.
7. Software must wait for CRYPT_STAT.HMACDONE bit either through polling or interrtupt.
NOTE: Text data can be input in the same way as a normal SHA operation. Once the text data is input, softwaremust check for the CRYPT_STAT.HMACDONE bit, which indicates that the hash operation is done and the final
result can be read from the SHARES register set. For message lengths that are not a multiple of 512 bits, similar
operation with CRYPT_SHA_LAST_WORD and CRYPT_SHA_LAST_WORD.O_BITS_VALID is required asdone in SHA calculations, to enable the hardware to start processing the message input for the last block of data.

CCM/CCM* Mode
The diagrams use the following color code.
OutputInput

SoftwareOperation

Figure 12-3: Color Codes

The NIST Standard for CCM mode has the following description of the CCM operation.

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CCM/CCM* Mode

CCM Mode Standard (NIST SP800 - 38c) Description
Encrypt - Generate
Formatted
Plaintext

Cipher text

CCM

Enc(MAC)
Decrypt - Validate

Formatted
Cipher text

CCM

Plaintext
MAC

Enc(MAC)

Decryption

==

MAC

VALID/INVALID

Figure 12-4: CCM Mode Standard Description

The hardware implementation for the CCM mode is shown in the figure:
CCM Mode Hardware Implementation
Encrypt - Generate
Formatted
Plaintext

CCM

Cipher text
Enc(MAC)

Decrypt - Validate

Formatted
Cipher text
Enc(MAC)

CCM

Plaintext
Enc(MAC)==VALID/INVALID

Figure 12-5: CCM Mode Hardware Implementation

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProgramming Flow for Block Modes of operation

Hardware to Standard Equivalence

During Encrypt-Generate
Enc(MAC) = MAC xor AES (Counter 0)
During Decrypt-Validate
Enc(MAC’) = MAC ’ xor AES (Counter 0)
Validation of authenticity is specified in the standard to be thefollowing check:
VALID = (MAC = = MAC’)
The hardware implementaion flow generatesVALID by thecomparison:
VALID = (Enc(MAC) = = Enc(MAC’))
Clearly, both the comparisons are mathematically equivalent.

Figure 12-6: Hardware to Standard Equivalence

The following are the reasons for the difference in the implementation flow adopted for generation of VALID signal
in Decrypt-Validate phase:• CMAC mode provides the MAC results and does not check the result against the received reasonable to do thesame in CCM mode.
• This approach is faster. When the system receives data that needs decryption, it receives an encrypted MAC. In
out implementation it is not necessary to decrypt the received MAC.
• The length of the MAC is selectable. If the hardware has to compare internally, information regarding thelength of the MAC output has to be programmed. This adds an additional control parameter and also increases
the hardware complexity by having a variable length comparator.
• The comparison operation is simple and involves very few operations. It does not require a hardware accelerator.
• MAC is not expected as an output from CCM operation. Only a VALID or INVALID signal is necessary.

Programming Flow for Block Modes of operation
Block modes of operation require the software to perform the following operations:• Crypto Block Configuration• Input Data Preparation• Data Retrieval
Configuring the Crypto block
Crypto key configuration: The complete key must be programmed in the key registers before every operation. Partial key configuration is not allowed.
Crypto must be configured in following order:
1. Configure the parameters such as key length, encrypt/decrypt, mode and so on. Do not enable the block.
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Programming Flow for Block Modes of operation

2. Program the key into key registers. Ensure that only relevant key registers for a given key length are programmed.
3. Enable the block by doing a read-modfiy-write to the configuration register.
Encrypt or Decrypt
CRYPT_CFG.ENCR field
Data Transfer
1. Endianness in CRYPT_CFG.ENDIAN
2. CRYPT_CFG.INDMAEN/CRYPT_CFG.OUTDMAEN field
Block Mode of Operation
The Crypto block supports the following block modes of operation:• AES Cipher Encryption and Decryption in ECB Mode
• AES Cipher Encryption and Decryption in CBC Mode
• AES Cipher Encryption and Decryption in CTR Mode
• AES Cipher CMAC Generation Mode
• AES Cipher Encryption and Decryption in CCM Mode
• AES Cipher Encryption and Decryption in CCM* Mode
NOTE: Only one mode must be enabled at a time.
Mode Specific Parameters
CTR Mode• CRYPT_CNTRINIT• CRYPT_NONCE0 to CRYPT_NONCE3
CCM/CCM* Mode
• CRYPT_DATALEN• CRYPT_PREFIXLEN• CRYPT_CNTRINIT• CRYPT_NONCE0 to CRYPT_NONCE3
CBC Mode
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceProgramming Flow for Block Modes of operation

Initialization Vector in the CRYPT_NONCE0 to CRYPT_NONCE3 registers.
CMAC Mode
CRYPT_DATALEN: This information is used by the block to determine when the CMAC results must be provided
on the output buffer.
Enabling Crypto
CRYPT_CFG.BLKEN field.
Ensure that this bit is enabled only when the block is completely configured.

Payload and Authenticated Data Formatting
In every mode of operation (other than CMAC) it is necessary to pad the payload and/or authenticated data with
sufficient number of zeros so as to make the length a multiple of 128 bits. In the case of CMAC mode, user needs to
pad and XOR the last message block differently.
Mode Specific Data Format• CBC Mode: Initialize the CRYPT_NONCE0 to CRYPT_NONCE3 registers with the Initialization Vector.
• CMAC Mode: The block always gives out a 128-bit MAC result on the output buffer in the selected data format (Big_Endian or Little_Endian). The software needs to ensure that the desired number of bits is used.
Subkey Generation: The values of K1 and K2 are used to generate the final message DataBlock. Software handles the generation of K1 and K2, padding higher bits with 'b10....j (j = number of zeroes that on padding
make the final message data block 128-bit long), and XOR operation to generate last message data block.
• CCM/CCM* Mode: Refer to the CCM/CCM* Mode section.

Programming Flow for SHA-Only Operation
Core Mode
Configuration
1. Configure SHA.
2. Enable the CRYPT_CFG.SHA256EN bit.
3. Program the first block of data.
4. Wait for the CRYPT_STAT.SHADONE interrupt bit to be set.
5. Program any consecutive 512-bit data block to the input buffer.
6. For the last word in the data block, set the CRYPT_SHA_LAST_WORD.O_LAST_WORD bit and program
the number of valid bits in that word. For example, if 12 bits are valid, the
CRYPT_SHA_LAST_WORD.O_BITS_VALID bit must be loaded with 12.
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12–25Retention in Hibernate ModeIf all the bits are valid, the last write must be a dummy write.
7. For a fresh SHA calculation, initialize SHA using the CRYPT_CFG.SHAINIT bit.
Complete the ongoing SHA operation before starting another SHA operation.
DMA Mode
Configuration
The following parameters must be programmed:
1. DMA for input buffer (CRYPT_CFG.INDMAEN field).
2. Enable desired SHA mode (CRYPT_CFG.SHA256EN field).
3. Enable the Crypto block (CRYPT_CFG.BLKEN field).
4. Initialize SHA operation (CRYPT_CFG.SHAINIT field).
When a new data block is to be computed and a fresh start is needed, the data block needs to be initializedusing this auto-clear bit provided in the CRYPT_CFG register.
Data Preparation
SHA accelerator does not require any software padding of data to make it a multiple of block size.
Data Retrieval
When the data operation is complete, the message digest can be read out of the SHAH register set.
After the message digest for a particular block is complete, re-initialize the internal SHAH registers by writing 1 to
the CRYPT_CFG.SHAINIT bit.

Retention in Hibernate Mode
The CRYPT_CFG register except CRYPT_CFG.BLKEN are retained in hibernate mode. The AESKEY register set
are also retained. All other register fields including the KUW register set are reset.
If the part goes into hibernate mode in the middle of a transaction, it cannot be retrieved. All the internal registers
except CRYPT_CFG and AESKEY register set are reset.
If the PrKStor is busy, part must not be allowed to hibernate. The PrKStor command needs to be completed before
allowing the part to hibernate.

ADuCM4050 CRYPT Register Descriptions
Register Map for the Crypto Block (CRYPT) contains the following registers.

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ADuCM4050 CRYPT Register Descriptions

Table 12-2: ADuCM4050 CRYPT Register List
Name

Description

CRYPT_AESKEY0

AES Key Bits [31:0]

CRYPT_AESKEY1

AES Key Bits [63:32]

CRYPT_AESKEY2AES Key Bits [95:64]

CRYPT_AESKEY3AES Key Bits [127:96]

CRYPT_AESKEY4AES Key Bits [159:128]

CRYPT_AESKEY5AES Key Bits [191:160]

CRYPT_AESKEY6AES Key Bits [223:192]

CRYPT_AESKEY7AES Key Bits [255:224]

CRYPT_CCM_NUM_VALID_BYTES

NUM_VALID_BYTESCRYPT_CFG

Configuration Register

CRYPT_CNTRINIT

Counter Initialization Vector

CRYPT_DATALEN

Payload Data Length

CRYPT_INBUF

Input Buffer

CRYPT_INTENInterrupt Enable Register

CRYPT_KUW0

Key Wrap Unwrap Register 0

CRYPT_KUW1

Key Wrap Unwrap Register 1

CRYPT_KUW10Key Wrap Unwrap Register 10

CRYPT_KUW11

Key Wrap Unwrap Register 11

CRYPT_KUW12Key Wrap Unwrap Register 12

CRYPT_KUW13

Key Wrap Unwrap Register 13

CRYPT_KUW14

Key Wrap Unwrap Register 14

CRYPT_KUW15

Key Wrap Unwrap Register 15

CRYPT_KUW2

Key Wrap Unwrap Register 2

CRYPT_KUW3

Key Wrap Unwrap Register 3

CRYPT_KUW4

Key Wrap Unwrap Register 4

CRYPT_KUW5

Key Wrap Unwrap Register 5

CRYPT_KUW6

Key Wrap Unwrap Register 6

CRYPT_KUW7

Key Wrap Unwrap Register 7

CRYPT_KUW8

Key Wrap Unwrap Register 8

CRYPT_KUW9

Key Wrap Unwrap Register 9

CRYPT_KUWVALSTR1

Key Wrap Unwrap Validation String [63:32]

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–27

ADuCM4050 CRYPT Register Descriptions

Table 12-2: ADuCM4050 CRYPT Register List (Continued)
Name

Description

CRYPT_KUWVALSTR2

Key Wrap Unwrap Validation String [31:0]

CRYPT_NONCE0

Nonce Bits [31:0]

CRYPT_NONCE1

Nonce Bits [63:32]

CRYPT_NONCE2

Nonce Bits [95:64]

CRYPT_NONCE3

Nonce Bits [127:96]

CRYPT_OUTBUF

Output Buffer

CRYPT_PREFIXLEN

Authentication Data Length

CRYPT_PRKSTORCFGPRKSTOR Configuration

CRYPT_SHAH0SHA Bits [31:0]

CRYPT_SHAH1

SHA Bits [63:32]

CRYPT_SHAH2SHA Bits [95:64]

CRYPT_SHAH3

SHA Bits [127:96]

CRYPT_SHAH4SHA Bits [159:128]

CRYPT_SHAH5SHA Bits [191:160]

CRYPT_SHAH6SHA Bits [223:192]

CRYPT_SHAH7SHA Bits [255:224]

CRYPT_SHA_LAST_WORD

SHA Last Word and Valid Bits Information

CRYPT_STAT

Status Register

12–28

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

AES Key Bits [31:0]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key: Bytes [3:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key: Bytes [3:0]

Figure 12-7: CRYPT_AESKEY0 Register Diagram
Table 12-3: CRYPT_AESKEY0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Key: Bytes [3:0].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–29

ADuCM4050 CRYPT Register Descriptions

AES Key Bits [63:32]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key: Bytes [7:4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key: Bytes [7:4]

Figure 12-8: CRYPT_AESKEY1 Register Diagram
Table 12-4: CRYPT_AESKEY1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Key: Bytes [7:4].

(RX/W)

12–30

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

AES Key Bits [95:64]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key: Bytes [11:8]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key: Bytes [11:8]

Figure 12-9: CRYPT_AESKEY2 Register Diagram
Table 12-5: CRYPT_AESKEY2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Key: Bytes [11:8].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–31

ADuCM4050 CRYPT Register Descriptions

AES Key Bits [127:96]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key: Bytes [15:12]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key: Bytes [15:12]

Figure 12-10: CRYPT_AESKEY3 Register Diagram
Table 12-6: CRYPT_AESKEY3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Key: Bytes [15:12].

(RX/W)

12–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

AES Key Bits [159:128]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key: Bytes [19:16]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key: Bytes [19:16]

Figure 12-11: CRYPT_AESKEY4 Register Diagram
Table 12-7: CRYPT_AESKEY4 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Key: Bytes [19:16].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–33

ADuCM4050 CRYPT Register Descriptions

AES Key Bits [191:160]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key: Bytes [23:20]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key: Bytes [23:20]

Figure 12-12: CRYPT_AESKEY5 Register Diagram
Table 12-8: CRYPT_AESKEY5 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Key: Bytes [23:20].

(RX/W)

12–34

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

AES Key Bits [223:192]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key: Bytes [27:24]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key: Bytes [27:24]

Figure 12-13: CRYPT_AESKEY6 Register Diagram
Table 12-9: CRYPT_AESKEY6 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Key: Bytes [27:24].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 CRYPT Register Descriptions

AES Key Bits [255:224]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Key: Bytes [31:28]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Key: Bytes [31:28]

Figure 12-14: CRYPT_AESKEY7 Register Diagram
Table 12-10: CRYPT_AESKEY7 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Key: Bytes [31:28].

(RX/W)

12–36

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

NUM_VALID_BYTES
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

NUM_VALID_BYTES (R/W)
Number of Valid Bytes in CCM Last
Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 12-15: CRYPT_CCM_NUM_VALID_BYTES Register Diagram
Table 12-11: CRYPT_CCM_NUM_VALID_BYTES Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
3:0 NUM_VALID_BYTES

Number of Valid Bytes in CCM Last Data.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 CRYPT Register Descriptions

Configuration Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PRKSTOREN (R/W)
Enable PRKSTOR Commands

BLKEN (R/W)
Enable Bit for Crypto Block

KEY_BYTESWAP (R/W)
Use Key Unwrap Before HMAC

ENCR (R/W)
Encrypt or Decrypt

SHA_BYTESWAP (R/W)
Enable Key Wrap

INDMAEN (R/W)
Enable DMA Channel Request for Input
BufferAES_BYTESWAP (R/W)
Byteswap for AES Input

OUTDMAEN (R/W)
Enable DMA Channel Request for Output
BufferKUWKeyLen (R/W)
Key Length Key Wrap Unwrap

INFLUSH (W)Input Buffer FlushAESKEYLEN (R/W)
Select Key Length for AES Cipher

OUTFLUSH (W)Output Buffer Flush
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

RevID (R)
Rev ID for Crypto

ECBEN (R/W)
Enable ECB Mode Operation

SHAINIT (R0/W)
Restarts SHA Computation

CTREN (R/W)
Enable CTR Mode Operation

SHA256EN (R/W)
Enable SHA-256 Operation

CBCEN (R/W)
Enable CBC Mode Operation

HMACEN (R/W)
HMAC Enable

CCMEN (R/W)
Enable CCM/CCM* Mode Operation

CMACEN (R/W)
Enable CMAC Mode Operation

Figure 12-16: CRYPT_CFG Register Diagram
Table 12-12: CRYPT_CFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:28 REVID(R/NW)
26 SHAINIT(R0/W)

12–38

Rev ID for Crypto.
The revision id is set to 0x2 for this version.
Restarts SHA Computation.
Initialize SHA module for fresh SHA calculation on a new data block. This bit resets
the SHA result registers to their default state. This auto-clears after reseting the SHA
result registers.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Table 12-12: CRYPT_CFG Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
25 SHA256EN

Enable SHA-256 Operation.

(R/W)
21 HMACEN(R/W)
20 CMACEN

HMAC Enable.
Enable HMAC mode. At the end of HMAC calculation, this bit is auto-reset. To restart a fresh HMAC calculation this bit should be set again by software
Enable CMAC Mode Operation.

(R/W)
19 CCMEN

Enable CCM/CCM* Mode Operation.

(R/W)
18 CBCEN

Enable CBC Mode Operation.

(R/W)
17 CTREN

Enable CTR Mode Operation.

(R/W)
16 ECBEN

Enable ECB Mode Operation.

(R/W)
15 PRKSTOREN(R/W)
14 KEY_BYTESWAP(R/W)
13 SHA_BYTESWAP(R/W)
12 AES_BYTESWAP

Enable PRKSTOR Commands.
This bit should be enabled to execute any command in the Protected Key Storage.
Use Key Unwrap Before HMAC.
The input word to the AES Key, KUW Key, and KUW validating strings register isbyte-swapped once this bit is set.
Enable Key Wrap.
Enable byte-swap for each word input to the SHA module. Data that is input as {B3,
B2, B1, B0} will be recorded as {B1, B2, B3, B4}.
Byteswap for AES Input.

(R/W)

Enable byte-swap for each word input to the Input Buffer. Data that is input as {B3,
B2, B1, B0} will be recorded as {B1, B2, B3, B4}.

11:10 KUWKEYLEN

Key Length Key Wrap Unwrap.

(R/W)

Specify the length of the key in KUW registers in terms of 64 bit blocks. These are theregisters that hold the wrapped or unwrapped key in respective modes. They support amaximum key length of 512 bits. Any change in the key length will reset the KUWregisters.
1 The key size of KUW key is 128 bits
2 The key size of KUW key is 256 bits
3 The key size of KUW key is 512 bits

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–39

ADuCM4050 CRYPT Register Descriptions

Table 12-12: CRYPT_CFG Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9:8 AESKEYLEN(R/W)

Select Key Length for AES Cipher.
Specify the length of AES key. Supported key lengths are 128 and 256 bits. Anychange in the key length will reset the AES key.
0 Uses 128-bit long key
2 Uses 256-bit long key

5 OUTFLUSH

Output Buffer Flush.

(RX/W)
4 INFLUSH

Input Buffer Flush.

(RX/W)
3 OUTDMAEN

Enable DMA Channel Request for Output Buffer.

(R/W)

0 Disable DMA Requesting for Output Buffer
1 Enable DMA Requesting for Output Buffer

2 INDMAEN

Enable DMA Channel Request for Input Buffer.

(R/W)

0 Disable DMA Requesting for Input Buffer
1 Enable DMA Requesting for Input Buffer

1 ENCR(R/W)

Encrypt or Decrypt.
Select Encryption/Decryption for a given mode. This bit need not be set/reset for
Wrap/Unwrap operation in Protected Key Storage.
0 Decrypt
1 Encrypt

0 BLKEN(R/W)

Enable Bit for Crypto Block.
Enable Crypto hardware accelerator. This bit is intended to be used as a start of operation for all Crypto modes. Unless this bit is enabled, no Crypto mode shall function.
0 Disable Crypto Block
1 Enable Crypto Block

12–40

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Counter Initialization Vector
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R/W)
Counter Initialization Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[19:16] (R/W)
Counter Initialization Value

Figure 12-17: CRYPT_CNTRINIT Register Diagram
Table 12-13: CRYPT_CNTRINIT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
19:0 VALUE(R/W)

Counter Initialization Value.
This is the initialization value used in the internal counter generating functions thatare used in some modes of operation.
1. CCM/CCM* Mode: Only CRYPT_CNTRINIT.VALUE[15:0] are used in thismode for initializing the counter initialization vector. The higher bits are ignored.
2. CTR Mode: CRYPT_CNTRINIT.VALUE[19:0] are used in to initialize the counter initialization vector. When the block is reset, the counters are initialized to the value programmed in this register.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–41

ADuCM4050 CRYPT Register Descriptions

Payload Data Length
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R/W)
Length of Payload Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[19:16] (R/W)
Length of Payload Data

Figure 12-18: CRYPT_DATALEN Register Diagram
Table 12-14: CRYPT_DATALEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
19:0 VALUE(R/W)

Length of Payload Data.
Program the length of the Payload that needs to be encrypted with the following values:
1. MAC Mode: CRYPT_DATALEN.VALUE[19:0] should be used to program thenumber of 128-bit blocks in the Payload.
2. CCM/CCM* Mode: CRYPT_DATALEN.VALUE[15:0] should be used to program the number of 128-bit blocks in the Payload.

12–42

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Input Buffer
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Input Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Input Buffer

Figure 12-19: CRYPT_INBUF Register Diagram
Table 12-15: CRYPT_INBUF Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Input Buffer.

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–43

ADuCM4050 CRYPT Register Descriptions

Interrupt Enable Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PRKSTRCMDONEEN (R/W)
PRKSTOR CMD DONE INTENINRDYEN (R/W)
Enable Input Ready Interrupt

HMACMSGRDYEN (R/W)
Status Bit for HMAC Message Input
Ready

OUTRDYEN (R/W)
Enables the Output Ready Interrupt
INOVREN (R/W)
Enable Input Overflow Interrupt

HMACDONEEN (R/W)
Interrupt Enable for HMAC DoneSHADONEN (R/W)
Enable SHA_Done Interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 12-20: CRYPT_INTEN Register Diagram
Table 12-16: CRYPT_INTEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
8 PRKSTRCMDONEEN(R/W)
7 HMACMSGRDYEN(R/W)

6 HMACDONEEN(R/W)
5 SHADONEN(R/W)
2 INOVREN(R/W)
1 OUTRDYEN(R/W)
0 INRDYEN
(R/W)

12–44

PRKSTOR CMD DONE INTEN.
This bit when set interrupts the core on completion of any PRKSTOR command
Status Bit for HMAC Message Input Ready.
This bit when set interrupts the core when HMAC accelerator is ready to take in theuser data. For the last block of user input data, the SHA_LAST_WORD registershould be programmed as described in the SHA_LAST_WORD section below.
Interrupt Enable for HMAC Done.
This bit when set interrupts the core when HMAC computation is done
Enable SHA_Done Interrupt.
This bit when set interrupts the core when SHA has finished processing the current
data block.
Enable Input Overflow Interrupt.
This bit when set interrupts the core in case input buffer overflows.
Enables the Output Ready Interrupt.
This bit when set interrupts the core when output buffer is ready to provide more data.
Once the output buffer is empty, this bit resets.
Enable Input Ready Interrupt.
This bit when set interrupts the core when input buffer is ready for more data. Oncethe input buffer is full, this bit resets.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 0This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW0[15:0] (W)KUW [31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW0[31:16] (W)KUW [31:0]

Figure 12-21: CRYPT_KUW0 Register Diagram
Table 12-17: CRYPT_KUW0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW0KUW [31:0].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–45

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 1
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW1[15:0] (W)KUW [63:32]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW1[31:16] (W)KUW [63:32]

Figure 12-22: CRYPT_KUW1 Register Diagram
Table 12-18: CRYPT_KUW1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW1KUW [63:32].

(RX/W)

12–46

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 10
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW10[15:0] (W)KUW [351:320]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW10[31:16] (W)KUW [351:320]

Figure 12-23: CRYPT_KUW10 Register Diagram
Table 12-19: CRYPT_KUW10 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW10KUW [351:320].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–47

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 11
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW11[15:0] (W)KUW [383:352]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW11[31:16] (W)KUW [383:352]

Figure 12-24: CRYPT_KUW11 Register Diagram
Table 12-20: CRYPT_KUW11 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW11(RX/W)

12–48

KUW [383:352].
Reg 11 of KUW Registers

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 12
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW12[15:0] (W)KUW [415:384]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW12[31:16] (W)KUW [415:384]

Figure 12-25: CRYPT_KUW12 Register Diagram
Table 12-21: CRYPT_KUW12 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW12KUW [415:384].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–49

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 13
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW13[15:0] (W)KUW [447:416]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW13[31:16] (W)KUW [447:416]

Figure 12-26: CRYPT_KUW13 Register Diagram
Table 12-22: CRYPT_KUW13 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW13

KUW [447:416].

(RX/W)

12–50

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 14
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW14[15:0] (W)KUW [479:448]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW14[31:16] (W)KUW [479:448]

Figure 12-27: CRYPT_KUW14 Register Diagram
Table 12-23: CRYPT_KUW14 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW14KUW [479:448].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–51

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 15
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW15[15:0] (W)KUW [511:480]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW15[31:16] (W)KUW [511:480]

Figure 12-28: CRYPT_KUW15 Register Diagram
Table 12-24: CRYPT_KUW15 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW15KUW [511:480].

(RX/W)

12–52

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 2This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW2[15:0] (W)KUW [95:64]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW2[31:16] (W)KUW [95:64]

Figure 12-29: CRYPT_KUW2 Register Diagram
Table 12-25: CRYPT_KUW2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW2KUW [95:64].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–53

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 3This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW3[15:0] (W)KUW [127:96]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW3[31:16] (W)KUW [127:96]

Figure 12-30: CRYPT_KUW3 Register Diagram
Table 12-26: CRYPT_KUW3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW3

KUW [127:96].

(RX/W)

12–54

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 4This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW4[15:0] (W)KUW [159:128]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW4[31:16] (W)KUW [159:128]

Figure 12-31: CRYPT_KUW4 Register Diagram
Table 12-27: CRYPT_KUW4 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW4KUW [159:128].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–55

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 5This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW5[15:0] (W)KUW [191:160]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW5[31:16] (W)KUW [191:160]

Figure 12-32: CRYPT_KUW5 Register Diagram
Table 12-28: CRYPT_KUW5 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW5KUW [191:160].

(RX/W)

12–56

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 6
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW6[15:0] (W)KUW [223:192]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW6[31:16] (W)KUW [223:192]

Figure 12-33: CRYPT_KUW6 Register Diagram
Table 12-29: CRYPT_KUW6 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW6KUW [223:192].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–57

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 7This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW7[15:0] (W)KUW [255:224]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW7[31:16] (W)KUW [255:224]

Figure 12-34: CRYPT_KUW7 Register Diagram
Table 12-30: CRYPT_KUW7 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW7KUW [255:224].

(RX/W)

12–58

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 8This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW8[15:0] (W)KUW [287:256]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW8[31:16] (W)KUW [287:256]

Figure 12-35: CRYPT_KUW8 Register Diagram
Table 12-31: CRYPT_KUW8 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW8KUW [287:256].

(RX/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–59

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Register 9This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW9[15:0] (W)KUW [319:288]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

KUW9[31:16] (W)KUW [319:288]

Figure 12-36: CRYPT_KUW9 Register Diagram
Table 12-32: CRYPT_KUW9 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 KUW9KUW [319:288].

(RX/W)

12–60

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Validation String [63:32]
KUW Validation String [31:0]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

0

1

1

0

0

1

0

0

1

1

InitialValue0[15:0] (W)Initial Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

0

1

0

0

1

1

0

1

0

1

0

0

1

1

0

InitialValue0[31:16] (W)Initial Value

Figure 12-37: CRYPT_KUWVALSTR1 Register Diagram
Table 12-33: CRYPT_KUWVALSTR1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 INITIALVALUE0(RX/W)

Initial Value.
Key wrap/unwrap initial value string. In wrap mode this will be integrity check string
and can be used by software to attach integrity check to the key being wrapped. In
unwrap mode, the resulting string should be matched by the software to ensure theintegrity of key

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–61

ADuCM4050 CRYPT Register Descriptions

Key Wrap Unwrap Validation String [31:0]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

0

1

1

0

0

1

0

0

1

1

InitialValue1[15:0] (W)Initial Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

0

1

0

0

1

1

0

1

0

1

0

0

1

1

0

InitialValue1[31:16] (W)Initial Value

Figure 12-38: CRYPT_KUWVALSTR2 Register Diagram
Table 12-34: CRYPT_KUWVALSTR2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 INITIALVALUE1(RX/W)

12–62

Initial Value.
Key wrap/unwrap initial value string. In wrap mode this will be integrity check string
and can be used by software to attach integrity check to the key being wrapped. In
unwrap mode, the resulting string should be matched by the software to ensure theintegrity of key

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Nonce Bits [31:0]
Nonce is used in some modes of operations. Depending on the mode, different nonce lengths will be used.
1. CTR mode: This takes a 108-bit nonce. This nonce is formed as follows:{CRYPT_NONCE3[11:0], CRYPT_NONCE2, CRYPT_NONCE1, CRYPT_NONCE0}
2. CBC mode: This takes a 128-bit nonce. This nonce is formed as follows:{CRYPT_NONCE3, CRYPT_NONCE2, CRYPT_NONCE1, CRYPT_NONCE0}
3. CTR mode: This takes a 108-bit nonce. This nonce is formed as follows:{CRYPT_NONCE3[15:0], CRYPT_NONCE2, CRYPT_NONCE1, CRYPT_NONCE0}
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R/W)
Word 0: Nonce Bits [31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R/W)
Word 0: Nonce Bits [31:0]

Figure 12-39: CRYPT_NONCE0 Register Diagram
Table 12-35: CRYPT_NONCE0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Word 0: Nonce Bits [31:0].

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–63

ADuCM4050 CRYPT Register Descriptions

Nonce Bits [63:32]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R/W)
Word 1: Nonce Bits [63:32]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R/W)
Word 1: Nonce Bits [63:32]

Figure 12-40: CRYPT_NONCE1 Register Diagram
Table 12-36: CRYPT_NONCE1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Word 1: Nonce Bits [63:32].

(R/W)

12–64

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Nonce Bits [95:64]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R/W)
Word 2: Nonce Bits [95:64]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R/W)
Word 2: Nonce Bits [95:64]

Figure 12-41: CRYPT_NONCE2 Register Diagram
Table 12-37: CRYPT_NONCE2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Word 2: Nonce Bits [95:64].

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–65

ADuCM4050 CRYPT Register Descriptions

Nonce Bits [127:96]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R/W)
Word 3: Nonce Bits [127:96]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R/W)
Word 3: Nonce Bits [127:96]

Figure 12-42: CRYPT_NONCE3 Register Diagram
Table 12-38: CRYPT_NONCE3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Word 3: Nonce Bits [127:96].

(R/W)

12–66

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Output Buffer
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R)Output Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R)Output Buffer

Figure 12-43: CRYPT_OUTBUF Register Diagram
Table 12-39: CRYPT_OUTBUF Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Output Buffer.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–67

ADuCM4050 CRYPT Register Descriptions

Authentication Data Length
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Length of Associated Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 12-44: CRYPT_PREFIXLEN Register Diagram
Table 12-40: CRYPT_PREFIXLEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/W)

Length of Associated Data.
Program the length of the Associated that needs to be encrypted with the following
values:
CCM/CCM* Mode: 20 bits are provided to program the number of 128-bit blocks of
the associated data. The higher 4 bits are be ignored.

12–68

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

PRKSTOR Configuration
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CMD (R/W)
Command Input for PRKSTOR

KEY_INDEX (R/W)
Index of Key in PRKSTOR

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 12-45: CRYPT_PRKSTORCFG Register Diagram
Table 12-41: CRYPT_PRKSTORCFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
10:7 CMD

Command Input for PRKSTOR.

(R/W)
6:0 KEY_INDEX

Index of Key in PRKSTOR.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–69

ADuCM4050 CRYPT Register Descriptions

SHA Bits [31:0]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

1

1

0

0

1

1

1

1

1

0

0

1

1

SHAHASH0[15:0] (R)Word 0: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

1

1

0

1

0

1

0

0

0

0

0

1

0

0

1

SHAHASH0[31:16] (R)Word 0: SHA Hash

Figure 12-46: CRYPT_SHAH0 Register Diagram
Table 12-42: CRYPT_SHAH0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 SHAHASH0

Word 0: SHA Hash.

(R/NW)

12–70

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

SHA Bits [63:32]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

1

0

0

0

0

1

0

1

0

1

0

1

1

1

SHAHASH1[15:0] (R)Word 1: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

0

1

1

1

0

1

1

0

1

1

0

0

1

1

1

SHAHASH1[31:16] (R)Word 1: SHA Hash

Figure 12-47: CRYPT_SHAH1 Register Diagram
Table 12-43: CRYPT_SHAH1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 SHAHASH1

Word 1: SHA Hash.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–71

ADuCM4050 CRYPT Register Descriptions

SHA Bits [95:64]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

0

1

1

1

0

0

1

0

1

1

1

0

0

1

SHAHASH2[15:0] (R)Word 2: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

1

1

1

1

0

0

0

1

1

0

1

1

1

0

SHAHASH2[31:16] (R)Word 2: SHA Hash

Figure 12-48: CRYPT_SHAH2 Register Diagram
Table 12-44: CRYPT_SHAH2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 SHAHASH2

Word 2: SHA Hash.

(R/NW)

12–72

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

SHA Bits [127:96]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

0

0

1

1

1

0

1

0

1

1

1

0

1

0

SHAHASH3[15:0] (R)Word 3: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

0

1

0

0

1

0

1

0

1

0

0

1

1

1

1

SHAHASH3[31:16] (R)Word 3: SHA Hash

Figure 12-49: CRYPT_SHAH3 Register Diagram
Table 12-45: CRYPT_SHAH3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 SHAHASH3

Word 3: SHA Hash.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–73

ADuCM4050 CRYPT Register Descriptions

SHA Bits [159:128]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

1

1

1

1

1

1

1

0

1

0

0

1

SHAHASH4[15:0] (R)Word 4: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

1

0

1

0

0

0

1

0

0

0

0

1

1

1

0

SHAHASH4[31:16] (R)Word 4: SHA Hash

Figure 12-50: CRYPT_SHAH4 Register Diagram
Table 12-46: CRYPT_SHAH4 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 SHAHASH4

Word 4: SHA Hash.

(R/NW)

12–74

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

SHA Bits [191:160]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

1

0

0

0

1

1

0

0

1

1

0

1

0

0

SHAHASH5[15:0] (R)Word 5: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1

0

0

1

1

0

1

1

0

0

0

0

0

1

0

1

SHAHASH5[31:16] (R)Word 5: SHA Hash

Figure 12-51: CRYPT_SHAH5 Register Diagram
Table 12-47: CRYPT_SHAH5 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 SHAHASH5

Word 5: SHA Hash.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

12–75

ADuCM4050 CRYPT Register Descriptions

SHA Bits [223:192]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

1

0

1

0

1

0

1

1

1

0

1

1

0

0

SHAHASH6[15:0] (R)Word 6: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

1

1

1

1

1

1

0

0

0

0

0

1

1

SHAHASH6[31:16] (R)Word 6: SHA Hash

Figure 12-52: CRYPT_SHAH6 Register Diagram
Table 12-48: CRYPT_SHAH6 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 SHAHASH6

Word 6: SHA Hash.

(R/NW)

12–76

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

SHA Bits [255:224]
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

SHAHASH7[15:0] (R)Word 7: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

1

0

1

1

0

1

1

1

1

1

0

0

0

0

0

SHAHASH7[31:16] (R)Word 7: SHA Hash

Figure 12-53: CRYPT_SHAH7 Register Diagram
Table 12-49: CRYPT_SHAH7 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 SHAHASH7

Word 7: SHA Hash.

(R/NW)

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ADuCM4050 CRYPT Register Descriptions

SHA Last Word and Valid Bits Information
This register is to be written before writing the last word to SHA input register. This is to inform the SHA engine
that last word is about to be written by writing to the CRYPT_SHA_LAST_WORD.O_LAST_WORD. Also, thenumber of valid bits has to be programmed in the CRYPT_SHA_LAST_WORD.O_BITS_VALID.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

O_Bits_Valid (R/W)
Bits Valid in SHA Last Word Input

O_Last_Word (R/W)
Last SHA Input Word

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 12-54: CRYPT_SHA_LAST_WORD Register Diagram
Table 12-50: CRYPT_SHA_LAST_WORD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5:1 O_BITS_VALID(R/W)
0 O_LAST_WORD
(R/W)

12–78

Bits Valid in SHA Last Word Input.
Indicates the number of valid bits in the last input word to SHA. This should auto
clear when CRYPT_STAT.SHADONE is set
Last SHA Input Word.
This should be set to indicate that last word is about to be written to the SHA engine.
This should auto clear when CRYPT_STAT.SHADONE is set.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRYPT Register Descriptions

Status Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

HMACMSGRDY (R/W)
Status Bit Indicates HMAC is Message
Ready

INRDY (R)
Input Buffer Status
OUTRDY (R)Output Data Ready

HMACDONE (R/W)
Status Bit Indicates HMAC DoneINOVR (R/W1C)
Overflow in the Input Buffer

HMACBUSY (R)Status Bit Indicates HMAC BusySHADONE (R/W)
SHA Computation Complete

OUTWORDS (R)
Number of Words in the Output Buffer

SHABUSY (R)SHA Busy. in Computation

INWORDS (R)
Number of Words in the Input Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PRKSTOR_BUSY (R)
Indicates PrKSTOR is BusyPRKSTOR_CMD_DONE (R/W)
Indicates Command Done for PrKStor

CMD_ISSUED (R)Last Command Issued to PrKStor

PRKSTOR_CMD_FAIL (R/W)
Indicates Last Command Issued Failed

PRKSTOR_RET_STATUS (R)ECC Errors in the PRKSTOR_RETRIEVE
CommandFigure 12-55: CRYPT_STAT Register Diagram
Table 12-51: CRYPT_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31 PRKSTOR_BUSY(R/NW)

30:27 CMD_ISSUED(R/NW)

Indicates PrKSTOR is Busy.
This bit when set indicates that the protected key storage is busy executing a command. All the writes to the protected key store configuration register are ignored while
this bit is set
Last Command Issued to PrKStor.
This field records the last command issued to Protected Key Storage. It is cleared whenblock is disabled.

26:25 PRKSTOR_RET_STATUS ECC Errors in the PRKSTOR_RETRIEVE Command.
(R/NW)
24 PRKSTOR_CMD_FAIL

This field indicates whether there has been an ECC error
Indicates Last Command Issued Failed.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 CRYPT Register Descriptions

Table 12-51: CRYPT_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
23 PRKSTOR_CMD_DONE

Indicates Command Done for PrKStor.

(R/W)
15 HMACMSGRDY

Status Bit Indicates HMAC is Message Ready.

(R/W)
14 HMACDONE

Status Bit Indicates HMAC Done.

(R/W)
13 HMACBUSY

Status Bit Indicates HMAC Busy.

(R/NW)
12:10 OUTWORDS

Number of Words in the Output Buffer.

(R/NW)
9:7 INWORDS

Number of Words in the Input Buffer.

(R/NW)
6 SHABUSY(R/NW)
5 SHADONE(R/W)

2 INOVR

SHA Busy. in Computation.
Indicates that computation is ongoing for recent data. While this is set, values in the
CRYPT_SHAHx registers are invalid.
SHA Computation Complete.
Indicates that hash computation is complete for current data. When hash computationis complete, the current value of the hash may be read out or new data may be written
into the input buffer to proceed with further computation.
Overflow in the Input Buffer.

(R/W1C)
1 OUTRDY(R/NW)
0 INRDY(R/NW)

12–80

Output Data Ready.
Output Data ready to be readInput Buffer Status.
Input buffer requires more data before computation can begin. Remains set till thebuffer is filled.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceTrue Random Number Generator (TRNG)

13 True Random Number Generator (TRNG)

True Random Number Generator (TRNG) is used during operations where non-deterministic values are required.
This may include generating challenges for secure communication or keys used for an encrypted communication
channel. The generator can be run multiple times to generate a sufficient number of bits for the strength of theintended operation. The true random number generator can be used to seed a deterministic random bit generator
such as one described by NIST CRC SP-800-90A.

TRNG Features
The following are the features of TRNG:• Programmable length to obtain sufficient entropy.
• Includes an oscillator counter to characterize the sampling jitter.
• Cannot generate any interrupts.

TRNG Functional Description
This section provides information on the function of the TRNG used by the ADuCM4050 MCU.

TRNG Block Diagram
The figure shows the block diagram of the TRNG used by the ADuCM4050 MCU.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

13–1

TRNG Functional Description

Previous
Oscillator Count

Ring
Oscillator
TEST
EN

6-bit Oscillator
Ripple Counter

SampleOscillator
Count
Difference

22-bit Synchronous
Counter

8-bit CRC
Accumulator

22-bit Sample
Counter

32-bit Data
Buffer

TRNG DATA

Ready

Peripheral
Clock
TRNG LEN

Figure 13-1: TRNG Block Diagram

The TRNG is based on a sampled asynchronous clock (in this implementation a ring oscillator). A CRC is used as acompaction function to reduce a large amount of low entropy bits into a smaller amount of high entropy bits. The
CRC will accumulate a programmable number of samples determined by the sample length register.
The TRNG is enabled through the control register. The length register specifies the number of samples for which
the TRNG should run to accumulate sufficient entropy. One sample is obtained on each peripheral clock and compacted by the CRC. Once the TRNG has accumulated the programmed number of samples, the accumulated 8-bit
CRC result can be read. Software can poll a status bit (RNG_STAT.RNRDY) or be interrupted when the TRNG isready.
Any number of iterations can be run. For example, 112 bits of entropy can be obtained by reading the 8-bit TRNG
result at least 14 times.

TRNG Oscillator Counter
The TRNG peripheral includes an oscillator counter. This on-chip counter can be used to characterize the sampling
jitter which is difficult to measure off-chip. The sample jitter is the source of entropy for the random number generator.
By counting the number of ring oscillator clocks over a given sampling period, the frequency ratio of the ring oscillator to peripheral sampling clock can be determined (and the ring oscillator frequency can be determined if the peripheral clock frequency is known).

fOSCCLK = fPCLK X

OSCCNT
SAMPCNT

where,
13–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

TRNG Functional Description

OSCCNT is the oscillator count (RNG_OSCCNT.VALUE).
SAMPCNT (length of sampling time) used by the sample counter can be determined from the RNG_LEN register.
The sample jitter can be determined by calculating the standard deviation of multiple oscillator count values.
A pseudo-code for an efficient loop across N values to determine the average oscillator count and jitter is shown
below:
sum=0; sum_sqr=0;
for(i=0;i<N;i++){gen_rng();sum += osc_cnt;
sum_sqr += osc_cnt*osc_cnt;}
avg=sum/N;
std=sqrt((sum_sqr-avg*sum)/(N-1));
The code has been simplified for clarity. If implemented in C:• The sum and sum_sqr variables must be integer data types. Floating point variables could lose precision if thesums accumulate for a sufficient length to overflow the fractional portion of the variable truncating the result.
It is desirable to keep the entire fractional portion, so the exponent of a floating point data type can be excluded.
• The sum variable needs log2(osc_cnt) + log2(N) bits of storage.
• The sum_sqr variable needs 2 × log2(osc_cnt) + log2(N) bits of storage.
• The squaring operation (osc_cnt × osc_cnt and avg × avg) requires a cast to a type with size at least 2 ×log2(osc_cnt).
• The avg and std variables can take fractional values (real or fixed point data types).
• The division needs a cast to a fractional data type.
For accurate jitter measurements, the standard deviation of RNG_OSCCNT should be at least one. If it is less thanone, then SAMPCNT must be increased.
The jitter of the oscillator counter encapsulates both jitter of the ring oscillator and jitter of the peripheral clock.
This can be used to determine sample jitter. If the jitter of the peripheral clock is known, the jitter of the oscillator
clock can be determined using the following equation.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

13–3

TRNG Functional Description

OSCCNT

SAMPCNTSAMPCNTOSCCNT

1

f PCLK

2
PCLK

SAMPLEOSCCNT

2+ OSCCLKSAMPCNTTRNG Entropy and Surprisal
The jitter of the sampling clocks is the source of entropy for the random number generator. Noise in the transistorsof the oscillator contributes to jitter. Accumulated long-term jitter increases with the square root of time or thenumber of clocks.
TOTAL

N

CLK

The number of samples that need to be accumulated to achieve ideal entropy of 1.0/bit depends on the amount ofjitter in the system. Entropy is calculated as follows:
average entropy =p i lo g2(pi )minimum entropy = min(-log2(pi ) )The probability of each number occurring should be the same or uniform for all numbers for an ideal generator. A
deficient generator would output some numbers more frequently than others. This random number generator was
designed to retain no state such that entropy can be measured and quantified in this manner. For each random number generated, the CRC is reset and the ring oscillator starts up in the same phase. If there is insufficient entropy inthe system, then the generator will output the same number more frequently. This is by design and makes entropy
assessment possible. Insufficient entropy can be observed by setting SAMPCNT to a low value in which case somerandom numbers will appear more frequently than others. SAMPCNT should be increased until the probability ofseeing each number is uniform.
The minimum entropy of the TRNG can be computed by tallying a histogram of generated random numbers andcalculating the probability of the most frequent number occurring. The minimum entropy equation should be used
when determining how many true random numbers to seed to a deterministic random number generator.
The minimum value for SAMPCNT (set by RNG_LEN register) needed to obtain ideal minimum surprisal for the
8-bit accumulator can be determined using the following equation. A conservative design will set SAMPCNT atleast as large as this, if not greater (to account for variations in jitter across various operating conditions).
SAMPCNT min

1

f

2
2
SAMPLE OSC

If an attacker can physically tamper the system and has control of the peripheral clock, the jitter due to the peripheral clock must be removed from the sample jitter in the previous calculation. This assumes an attacker can replace thecrystal with a low jitter clock source. A physical attacker may also use better voltage supplies that can minimize theamount of noise in the system. If an attacker can remove or minimize the peripheral clock jitter, then the entropy
13–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

TRNG Functional Description

source of the random number generator is reduced. The system should rely solely on the jitter of the ring oscillator,and conservatively, assume the jitter of the peripheral clock to be zero.

Oscillator Count Difference
There is logic built into the random number generator to calculate the difference between subsequent oscillator
count values. This can be used to calculate the variance and quantify the amount of jitter and thus entropy in thesystem. This provides a measure of health of the random number generator entropy source.
The statistical sample variance is typically calculated as follows:

S

2

1

n-1

n

(xi — x)2
i=1

The on-chip circuit calculates the difference in oscillator count between the current and previous sample. Since thesamples are independent and identically generated, this removes the mean.
E[X] — E[X] = 0
E[(X — X)2] = 2 2

The variance can be computed by averaging half of the square of the difference between oscillator count values.

The average can be replaced with a low pass IIR filter to track changes in the variance over time.

ADuCM4050 RNG Register Descriptions
Random Number Generator (RNG) contains the following registers.
Table 13-1: ADuCM4050 RNG Register List
Name

Description

RNG_CTLRNG Control Register

RNG_DATARNG Data Register

RNG_LENRNG Sample Length Register

RNG_OSCCNT

Oscillator CountRNG_OSCDIFF[n]Oscillator Difference

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

13–5

ADuCM4050 RNG Register Descriptions

Table 13-1: ADuCM4050 RNG Register List (Continued)
Name

Description

RNG_STATRNG Status Register

13–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RNG Register Descriptions

RNG Control Register
The RNG_CTL register is used to enable the random number generator.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SINGLE (R/W)
Generate a Single Number

EN (R/W)RNG Enable

Figure 13-2: RNG_CTL Register Diagram
Table 13-2: RNG_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
3 SINGLE(R/W)

Generate a Single Number.
By default the RNG will generate and buffer four 8-bit values to provide a 32-bit random number. Setting this bit will cause the RNG to only generate a single 8-bit random number.
0 Buffer Word
1 Single Byte

0 EN
(R/W)

RNG Enable.
When RNG_CTL.EN is set and RNG_STAT.RNRDY is clear, the ring oscillator will
be powered up and the number of samples defined by RNG_LEN will be accumulated
in the RNG_DATA register.
0 Disable the RNG
1 Enable the RNG

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

13–7

ADuCM4050 RNG Register DescriptionsRNG Data Register
RNG_DATA register provides the CPU with read-only access of the entropy accumulator (8-bit CRC) and data buffer. When the data buffer is not enabled, an 8-bit result is provided. When the data buffer is enabled, 32-bits (four8-bit values) are provided. The contents of this register are valid when the RNG_STAT.RNRDY bit is set. This register is reset when the RNG_STAT.RNRDY bit is cleared. The RNG_STAT.RNRDY bit is automatically cleared
when this register is read and the CPU is not in debug halt. Reading this register by the CPU when RNG_CTL.EN
is set will cause a new random number to be generated.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BUFF[7:0] (RC)
Buffer for RNG Data

VALUE (RC)
Value of the CRC Accumulator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BUFF[23:8] (RC)
Buffer for RNG Data

Figure 13-3: RNG_DATA Register Diagram
Table 13-3: RNG_DATA Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:8 BUFF(RC/NW)
7:0 VALUE(RC/NW)

13–8

Buffer for RNG Data.
When configured to generate 32-bit values, RNG_DATA.BUFF stores the previous
three numbers generated.
Value of the CRC Accumulator.
This register provides data from the entropy compaction function (8-bit CRC accumulator).

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RNG Register Descriptions

RNG Sample Length Register
The RNG_LEN register defines the number of samples to accumulate in the CRC register when generating a random number. The number of samples accumulated is RNG_LEN.RELOAD scaled by 2^RNG_LEN.PRESCALE.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

PRESCALE (R/W)
Prescaler for the Sample Counter

RELOAD (R/W)
Reload Value for the Sample Counter

Figure 13-4: RNG_LEN Register Diagram
Table 13-4: RNG_LEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:12 PRESCALE

Prescaler for the Sample Counter.

(R/W)

The sample counter reload value RNG_LEN.RELOAD is scaled by
2^RNG_LEN.PRESCALE. The prescaler is a 10-bit counter. Valid values for the prescaler are 0 to 10. Values greater than 10 will saturate at the maximum prescaler value.

11:0 RELOAD(R/W)

Reload Value for the Sample Counter.
Defines the number of samples to accumulate in the CRC when generating a random
number.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

13–9

ADuCM4050 RNG Register Descriptions

Oscillator CountThe oscillator counter counts the number of ring oscillator cycles which occur during the generation of a random
number. The oscillator counter is 28-bits. The oscillator counter will saturate at the maximum value to prevent overflow.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R)Oscillator Count31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[27:16] (R)Oscillator Count

Figure 13-5: RNG_OSCCNT Register Diagram
Table 13-5: RNG_OSCCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
27:0 VALUE(R/NW)

13–10

Oscillator Count.
This register is only valid when RNG_STAT.RNRDY is set.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RNG Register Descriptions

Oscillator Difference
The oscillator difference register stores the difference in RNG_OSCCNT from the current value compared to the previous value (RNG_OSCCNT[n] - RNG_OSCCNT[n-1]). This difference is represented as a signed 8-bit value. It saturates at the maximum and minimum values. This can be used to reconstruct RNG_OSCCNT for the values currently
in the RNG_DATA buffer. This information can be used to compute the RNG_OSCCNT variance to check thehealth of the random number generator and ensure there is adequate entropy.
7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

DELTA (R)
Oscillator Count Difference

Figure 13-6: RNG_OSCDIFF[n] Register Diagram
Table 13-6: RNG_OSCDIFF[n] Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 DELTA

Oscillator Count Difference.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

13–11

ADuCM4050 RNG Register Descriptions

RNG Status Register
The RNG_STAT register indicates when the RNG has finished generating a random number.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

STUCK (R/W1C)
Sampled Data Stuck High or Low

RNRDY (R/W1C)
Random Number Ready

Figure 13-7: RNG_STAT Register Diagram
Table 13-7: RNG_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 STUCK(R/W1C)

0 RNRDY(R/W1C)

Sampled Data Stuck High or Low.
When a random number is generated, a circuit monitors the output of the sampled
ring oscillator. This circuit checks to ensure the ring oscillator output has been sampled both high and low and is not stuck at a constant value. This bit is sticky once set
and is write one to clear.
Random Number Ready.
This bit indicates when the value in RNG_DATA is ready to be read. An interrupt isgenerated when this bit is set. The ring oscillator is stopped when this bit is set to conserve power. This bit is automatically cleared when the RNG_DATA register is read andthe CPU is not stopped in Debug Halt. This bit can also be written with one to clear.
0 Data register not ready
1 Data register is ready to be read

13–12

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCyclic Redundancy Check (CRC)

14 Cyclic Redundancy Check (CRC)

The CRC accelerator is used to compute the CRC for a block of memory locations. The exact memory location canbe in the SRAM, flash, or any combination of memory mapped registers. The CRC accelerator generates a checksum that can be used to compare with an expected signature. The ADuCM4050 MCU is responsible for the final
CRC comparison.

CRC Features
The CRC used by the ADuCM4050 MCU supports the following features:• Generate a CRC signature for a block of data.
• Programmable polynomial length of up to 32 bits.
• Operates on 32 bits of data at a time and also supports data lengths from 1-8 bits.
• MSB-first and LSB-first CRC implementations.
• Various data mirroring capabilities.
• Initial seed to be programmed by user.
• DMA controller (using software DMA) can be used for data transfer to offload the MCU.

CRC Functional Description
This section provides information on the function of the CRC accelerator used by the ADuCM4050 MCU. Control for address decrement/increment options for computing the CRC on a block of memory is in the DMA controller.
For more information about these options, refer to Direct Memory Access (DMA).

CRC Block Diagram
The CRC block diagram is shown below.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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CRC Operating Modes

CRC Polynomial
CRC
Computation

Mirror Options

CRC Control

CRC Input Data

APB Interface

CRC Result

Figure 14-1: CRC Block Diagram

The CRC accelerator works on 32-bit data words which are fed to the block through the DMA channel dedicated to
the CRC accelerator or directly by the MCU and the CRC accelerator guarantees immediate availability of the CRC
output.

CRC Operating Modes
The accelerator calculates CRC on the data stream it receives, typically 32 bits at a time, which is written into theblock either using the DMA engine or the MCU directly.
This accelerator also supports data lengths from 1 to 8 bits, which implies that CRC can be calculated on any data
lengths. For example, to calculate CRC on 23 data bytes, the data must be fed to the CRC accelerator as 5 words
and 3 bytes. The data can also be fed as 23 separate byte writes, but, it requires more number of cycles and may not
be an efficient way to perform this operation. If the data length is 23 bits, it can be entered as 2 bytes and 7 bits.
The CRC accelerator provides flexibility to process any length data with all polynomial lengths from 1-32 bits,
MSB-first or LSB-first
Data mirroring on the input can be performed at bit-, byte-, and word level before the CRC engine uses it by setting
the CRC_CTL.BITMIRR, CRC_CTL.BYTMIRR, and CRC_CTL.W16SWP bits respectively. Mirroring option is
not applicable on any data that is less than a byte. Byte mirroring and word swap options do not work on byte data.
Only bit mirroring is applicable for byte data.
CRC algorithm runs on the incoming data stream written to the CRC_IPDATA register. For every new word ofdata received, the CRC is computed and the CRC_RESULT register is updated with the calculated CRC. The CRC

14–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCRC Operating Modes

Accelerator guarantees the immediate availability of CRC result up to the current data in the CRC Result registerand the same can be read by the MCU.
The CRC engine uses the current CRC_RESULT for generating the next CRC_RESULT when a new data-word isreceived. The CRC_RESULT register can be programmed with an initial seed. The bit-width of the seed value foran n-bit polynomial must be n. The seed must be justified in the CRC_RESULT register.

Polynomial
The CRC Accelerator supports the calculation of the CRC using any length polynomial. The polynomial has to be
written to the CRC_POLY register. For MSB first implementation the highest power is omitted while programming
the CRC polynomial register and the polynomial is left justified. For LSB, first implementation the polynomial isright justified and the LSB is omitted. The CRC_RESULT register contains n-bit MSBs as checksum for an n-bit
CRC polynomial.
The following examples illustrate the CRC polynomial.
16-bit Polynomial Programming for MSB First Calculation
Polynomial: CRC-16-CCITT, x16+x12+x5+1 = (1) 0001 0000 0010 0001 = 0x1021
The largest exponent (x16 term) is implied, so it is 0001 0000 0010 0001
When left justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
0001 0000

0010 0001

8b0

8b0

CRC Result Register (CRC_RESULT)
CRC

Result8b0

8b0

Initial seed programmed in CRC Result Register (CRC_RESULT)
CRC

SEED

8b0

8b0

16-bit Polynomial Programming for LSB First Calculation
Polynomial: CRC-16-CCITT, x16+x12+x5+1 = 1000 0100 0000 1000 (1) = 0x8408
The smallest exponent (x0 term) is implied, so it is 1000 0100 0000 1000
When right justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
8b0

8b0

1000 0100

0000 1000

CRC Result Register (CRC_RESULT)
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CRC Operating Modes

8b0

8b0

CRC

ResultInitial seed programmed in CRC Result Register (CRC_RESULT)
8b0

8b0

CRC

SEED

8-bit Polynomial Programming for MSB First Calculation
Polynomial: CRC-8-ATM, x8 + x2 + x + 1 = (1) 0000 0111= 0x07
The largest exponent (x8 term) is implied, so it is 0000 0111
When left justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
0000 0111

8b0

8b0

8b0

8b0

8b0

CRC Result Register (CRC_RESULT)CRC RESULT

8b0

Initial seed programmed in CRC Result Register (CRC_RESULT)CRC SEED

8b0

8b0

8b0

8-bit Polynomial Programming for LSB First Calculation
Polynomial: CRC-8-ATM, x8 + x2 + x + 1 = 1000 0011 (1) = 0x83
The smallest exponent (x0 term) is implied, so it is 1000 0011
When right justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
8b0

8b0

8b0

1000 0011

8b0

CRC RESULTCRC Result Register (CRC_RESULT)
8b0

8b0

Initial seed programmed in CRC Result Register (CRC_RESULT)
8b0

8b0

8b0

CRC SEEDThe CRC engine uses the following 32-bit CRC polynomial as default (IEEE 802.3):
g(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCRC Operating Modes

This is programmed for MSB First Calculation by default as shown below
0x04

0xC1

0x1D

0xB7

Reset and Hibernate Modes
1. The CRC configuration bits are retained except the block enable bit (CRC_CTL.EN). The block needs to beenabled again after coming out of the Hibernate mode.
2. The CRC polynomial and CRC result registers are retained after coming out of the Hibernate mode.
Table 14-1: Reset and Hibernate Modes
Register

Reset

Hibernate

CRC_CTL

0x0

Apart from BLKEN, all other bits retained

CRC_POLY

0x04C11DB7

Retained

CRC_IPDATA

0x0

Not retained (0x0)

0x0Retained

CRC_IPBYTE
CRC_IPBITS[n]CRC_RESULT

Input Data Length
The following examples show how to use the CRC accelerator for different data lengths and mirroring options.
1. Data length is a multiple of word(4 bytes)
Polynomial: Any length up to 32 bits, MSB-first or LSB-first CRC calculation
Data Length: 512 bits
The CRC_CTL register must be configured with appropriate options.
The polynomial must be programmed as described in the Polynomial section.
The data length is 16 words. The DMA can be setup to transfer these 16 words to the CRC_IPDATA register.
The result can be read by the core after the channel_done interrupt is received from the DMA.
2. Data Length is a multiple of byte but not a multiple of word
Polynomial: Any length up to 32 bits, MSB-first or LSB-first CRC calculation
Data Length: 496 bits
The CRC_CTL register must be configured with appropriate options.
The polynomial must be programmed as described in the Polynomial section.

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CRC Data Transfer

The data length is 15 words and 2 bytes. The DMA can be setup to transfer these 15 words to the
CRC_IPDATA register. The core can write the remaining two bytes to the CRC_IPBYTE register after receiving the dma_done interrupt. The result can be read immediately after core finishes writing the last two bytes.
To feed data to the CRC accelerator, the DMA can be configured in byte transfer mode, where it transfers data
to the CRC_IPBYTE register one byte at a time. This mode is not the recommended as the CRC accelerator
must be active for about four time when compared with the other method. Also, only bit mirroring option isapplicable for CRC calculation on byte data.
3. Data length is not a multiple of byte or word
Polynomial: Any length up to 32 bits, MSB-first or LSB-first CRC calculation
Data Length: 51 bits
The CRC_CTL register must be configured with appropriate options.
The polynomial must be programmed as described in the Polynomial section.
The data length is 1 word, 2 bytes and 3 bits. The data must be fed to the CRC accelerator in the following
order: One word write to the CRC_IPDATA register, followed by two byte writes to the CRC_IPBYTE register and then a write to the CRC_IPBIT3 register. If the residual data is n-bit (where n ɛ [1,7]), it must be
written to the CRC_IPBITS[n] register.
If the CRC calculation is MSB-first, the n-bit data must be aligned to the MSB of the input data and viceversa.
Consider an example where the residual data is 3-bit data (say 3'b101). For MSB-first calculation, the input
byte must be packed as 8’b101_00000. For LSB-first, it must be packed as 8'b00000_101. This byte must be
written to the CRC_IPBIT3 register. Mirroring options is not applicable for the residual data.

CRC Data Transfer
The data stream can be written to the block using DMA controller or by the MCU directly.

CRC Interrupts and Exceptions
DMA channel generates an interrupt upon completion of data transfer to the CRC block.

CRC Programming Model
This block is provided to calculate CRC signature over block of data in the background while the core can perform
other tasks.
The CRC block supports two modes of CRC calculation: Core access and DMA access.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceCRC Programming Model

Core Access1. Program the CRC_POLY register with the required polynomial justified as shown in the examples in the Polynomial section.
2. Program the CRC_RESULT register with initial seed. The seed must be justified and written to the
CRC_RESULT register, as described in Polynomial.
3. Kick in the CRC Accelerator block by writing into the CRC_CTL register:a. Set the CRC_CTL.EN bit high.
b. Modify the CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BITMIRR bits, which configure the application with different mirror options. For more information about this, refer to Mirroring
Options.
c. Set/Reset the CRC_CTL.LSBFIRST bit to indicate LSB/MSB first CRC calculation.
NOTE: The sub-steps in Step 3 require only a single write to the CRC_CTL register.
The core can now start sending data to the CRC block by writing into the CRC_IPDATA register. The
CRC accelerator continues to calculate the CRC as long as data is written to the CRC_IPDATA register.
It is the responsibility of the application to count the number of words written to the CRC block. Once
all the words are written, the application can read the CRC_RESULT register.
4. Read the CRC_RESULT register. It contains the n-bit result in n MSB bits for MSB first and in n LSB bits for
LSB first CRC calculation.
5. Calculate CRC on the next data block. To calculate the CRC on the next block of data, repeat Steps 1-4.
6. Disable the CRC accelerator block by clearing the CRC_CTL.EN bit. This ensure that the block is in the lowpower state.
DMA Access
The CRC accelerator block supports software DMA.
1. Program the CRC_POLY register with the required polynomial left justified as shown in the example in the
Polynomial section.
2. Program the CRC_RESULT register with initial seed value. The seed should be justified and written to the
CRC_RESULT register, as described in Polynomial.
3. Enable accelerator function by writing into CRC_CTL register.
a. Set the CRC_CTL.EN bit high.
b. Modify the CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BITMIRR bits, which configure the application with different mirror options. For more information about this, refer to Mirroring
Options.
c. Set/Reset the CRC_CTL.LSBFIRST bit to indicate LSB/MSB first CRC calculation.
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CRC Programming Model

NOTE: The sub-steps in Step 3 require only a single write to the CRC_CTL register.
The DMA starts sending the CRC data by writing into the CRC_IPDATA. The CRC Accelerator block
continues to calculate the CRC as long as the data is written to the CRC_IPDATA.
4. Setup the DMA channels as required. DST_END_PNTR value is CRC_IPDATA register address. Data size isword. Use the destination no increment option for the channel used. For more information about programming the DMA, refer to Programming Guidelines.
5. A dma_done interrupt signal of the DMA channel indicates the completion of data transfer to the CRC
block.
6. Repeat Steps 1-4 until all the data has been sent to the accelerator block.
7. Read the CRC_RESULT register. It contain the n-bit result in n MSB bits for MSB first and in n LSB bits for
LSB first CRC calculations.
8. Calculate CRC on the next data block. To calculate the CRC on the next block of data, repeat Steps 1-5.
9. Disable the CRC accelerator block by clearing the CRC_CTL.EN bit. This ensures that the block is in lowpower state.

Mirroring Options
The CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BYTMIRR bits determine the sequence of thebits in which the CRC is calculated.
Mirroring Options for 32-bit Input Data with 32-bit Polynomial table shows the details of all the mirroring options
used within this block for a 32-bit polynomial.
Assume that DIN[31:0] is the data being written to the CRC_IPDATA register, and CIN[31:0] is the data after the
mirroring of the data. The serial engine calculates CIN[31:0] starting with the MSB bit and ending with LSB bit insequence, that is, CIN[31], CIN[30], ... CIN[1], CIN[0] in order.
Table 14-2: Mirroring Options for 32-bit Input Data with 32-bit Polynomial
W16SWP BYTMIRRBITMIRR Input Data
DIN[31:0]

CRC Input Data (CIN[31:0])

0

0

0

DIN[31:0]

CIN[31:0] = DIN[31:0]

0

0

1

DIN[31:0]

CIN[31:0] = DIN[24:31], DIN[16:23], DIN[8:15], DIN[0:7]

0

1

0

DIN[31:0]

CIN[31:0] = DIN[23:16], DIN[31:24], DIN[7:0], DIN[15:8]

0

1

1

DIN[31:0]

CIN[31:0] = DIN[16:23], DIN[24:31], DIN[0:7], DIN[8:15]

1

0

0

DIN[31:0]

CIN[31:0] = DIN[15:0], DIN[31:16]

1

0

1

DIN[31:0]

CIN[31:0] = DIN[8:15], DIN[0:7], DIN[24:31], DIN[16:23]

1

1

0

DIN[31:0]

CIN[31:0] = DIN[7:0], DIN[15:8], DIN[23:16], DIN[31:24]

1

1

1

DIN[31:0]

CIN[31:0] = DIN[0:7], DIN[8:15], DIN[16:23], DIN[24:31]

14–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRC Register Descriptions

ADuCM4050 CRC Register Descriptions
CRC Accelerator (CRC) contains the following registers.
Table 14-3: ADuCM4050 CRC Register List
Name

Description

CRC_CTL

CRC Control

CRC_IPBITS[n]Input Data Bits

CRC_IPBYTE

Input Data Byte

CRC_IPDATA

Input Data Word

CRC_POLY

Programmable CRC Polynomial

CRC_RESULTCRC Result

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 CRC Register Descriptions

CRC Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

W16SWP (R/W)
Word16 Swap

EN (R/W)
CRC Peripheral Enable

BYTMIRR (R/W)
Byte Mirroring

LSBFIRST (R/W)
LSB First Calculation Order

BITMIRR (R/W)
Bit Mirroring
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

RevID (R)
Revision ID

Figure 14-2: CRC_CTL Register Diagram
Table 14-4: CRC_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:28 REVID

Revision ID.

(R/NW)
4 W16SWP(R/W)

Word16 Swap.
This bit will swap 16-bit half-words within a 32-bit word.
0 Word16 Swap disabled
1 Word16 Swap enabled

3 BYTMIRR(R/W)

Byte Mirroring.
This bit will swap 8-bit bytes within each 16-bit half-word.
0 Byte Mirroring is disabled
1 Byte Mirroring is enabled

2 BITMIRR(R/W)

Bit Mirroring.
This bit will swap bits within each byte.
0 Bit Mirroring is disabled
1 Bit Mirroring is enabled

1 LSBFIRST(R/W)

LSB First Calculation Order.
0 MSB First CRC calculation is done
1 LSB First CRC calculation is done

14–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRC Register Descriptions

Table 14-4: CRC_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 EN
(R/W)

CRC Peripheral Enable.
0 CRC peripheral is disabled
1 CRC peripheral is enabled

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ADuCM4050 CRC Register Descriptions

Input Data Bits
7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

DATA_BITS (W)Input Data Bits

Figure 14-3: CRC_IPBITS[n] Register Diagram
Table 14-5: CRC_IPBITS[n] Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 DATA_BITS(RX/W)

14–12

Input Data Bits.
These fields are used to calculate CRC on partial data byte from 1-7 bits of input data.
Computing CRC on n bits of input data can be achieved by writing byte to n bit of
CRC_IPBITS[n].DATA_BITS.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 CRC Register Descriptions

Input Data Byte
7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

DATA_BYTE (W)Input Data Byte

Figure 14-4: CRC_IPBYTE Register Diagram
Table 14-6: CRC_IPBYTE Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 DATA_BYTE(RX/W)

Input Data Byte.
Writing data to this field calculates CRC on a byte of data.

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ADuCM4050 CRC Register Descriptions

Input Data Word
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Data Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Data Input

Figure 14-5: CRC_IPDATA Register Diagram
Table 14-7: CRC_IPDATA Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE

Data Input.

(RX/W)

14–14

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ADuCM4050 CRC Register Descriptions

Programmable CRC Polynomial
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

0

1

1

0

1

1

1

0

0

1

1

1

0

VALUE[15:0] (R/W)
CRC Reduction Polynomial
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

1

0

0

1

1

0

0

0

0

0

1

VALUE[31:16] (R/W)
CRC Reduction Polynomial

Figure 14-6: CRC_POLY Register Diagram
Table 14-8: CRC_POLY Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUECRC Reduction Polynomial.

(R/W)

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ADuCM4050 CRC Register Descriptions

CRC Result
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R/W)
CRC Residue
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R/W)
CRC Residue

Figure 14-7: CRC_RESULT Register Diagram
Table 14-9: CRC_RESULT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUECRC Residue.

(R/W)

14–16

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSerial Peripheral Interface (SPI)

15 Serial Peripheral Interface (SPI)The Serial Peripheral Interface (SPI) is an industry-standard synchronous serial link that supports communication
with multiple SPI-compatible devices. The baseline SPI peripheral is a synchronous, four-wire interface consisting of
two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other
SPI-compatible devices. Enhanced modes of operation such as flow control, fast mode, and read-command mode
(half-duplex operation) are also supported. In addition, a DMA mode allows for transferring several words withminimal CPU interaction.
With a range of configurable options, the SPI ports provide a glueless hardware interface with other SPI-compatible
devices in master mode, slave mode, and multislave environments. The SPI peripheral includes programmable baudrates, clock phase, and clock polarity. The peripheral can operate in a multislave environment by interfacing withseveral other devices, acting as either a master device or a slave device. In a multislave environment, the SPI peripheral uses open-drain outputs to avoid data bus contention. The flow control features enable slow slave devices tointerface with fast master devices by providing an SPI ready pin which flexibly controls the transfers.

SPI Features
The SPI module supports the following features:• Serial clock phase mode and serial clock polarity mode
• Loopback mode
• Continuous transfer mode
• Wired-OR output mode
• Read-command mode for half-duplex operation• Flow control• Multiple CS line
• CS software override• Support for 3-pin SPI Master or Slave mode
• LSB-first transfer option

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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SPI Functional Description• Interrupt mode: interrupt after 1, 2, 3, 4, 5, 6, 7, or 8 bytes• 8 bytes/half word deep FIFOs for Tx and Rx

SPI Functional Description
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A
serial clock line synchronizes shifting and sampling of the information on the two serial data lines. During a datatransfer, one SPI system acts as the link master which controls the data flow, while the other system acts as the slave,
which has data shifted into and out of it by the master. Different devices can take turn being masters, and one master may simultaneously shift data into multiple slaves (broadcast mode).
However, only one slave may drive its output to write data back to the master at any given time. This must be enforced in the broadcast mode, where several slaves can be selected to receive data from the master, but only one slave
can be enabled to send data back to the master.
The SPI port can be configured for master or slave operation and consists of four pins: MISO, MOSI, SCLK, and
CS. Note that the GPIOs used for SPI communication must be configured in SPI mode before enabling the SPI
peripheral. The peripheral should be enabled by setting the SPI_CTL.SPIEN bit. If not used, the peripheral mustbe turned off by clearing this bit.

SPI Block Diagram
The figure shows the SPI block diagram.
SPI

Flow Control

APB
Registers

16-bitAPB

State Machine

SCLK
Generation

SPI(3 or 4 pins)
External
Interface

Tx/Rx FIFOIRQ,
DMA - Req

IRQ/DMA
Generation

Figure 15-1: SPI Block Diagram

15–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPI Functional Description

MISO (Master In, Slave Out) Pin
The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on
the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred asbyte wide (8-bit) serial data.

MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on
the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred asbyte wide (8-bit) serial data.

SCLK (Serial Clock I/O) Pin
The master serial clock (SCLK) synchronizes the data being transmitted and received during the MOSI SCLK period. Therefore, a byte is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output inmaster mode and as an input in slave mode.
In the master mode, the polarity and phase of the clock are controlled by the SPI_CTL register, and the bit rate isdefined in the SPI_DIV register as follows:
f serial clock = CLK / ( 2 (1 + SPIx_DIV))
CLK is PCLK for SPI0 and SPI1, and HCLK for SPIH
In the slave mode, the SPI_CTL register must be configured with the phase and polarity of the expected input
clock.
In both master and slave modes, data is transmitted on one edge of the SCLK signal and sampled on the other.
Therefore, the polarity and phase are configured the same for the master and slave devices.
NOTE: Refer to the Data Sheet for timing specifications.

Chip Select (CS I/O) Pin
In SPI slave mode, a transfer is initiated by the assertion of CS, which is an active low input signal. The SPI portthen transmits and receives 8-bit data until the transfer is concluded by deassertion of CS. In slave mode, CS isalways an input.
In SPI master mode, the CS is an active low output signal. It asserts itself automatically at the beginning of a transfer
and deasserts itself upon completion.
In a multi-slave environment, we would support up to 4 different slaves. The SPI master can be configured to drive
up to four CS lines (CS0, CS1, CS2, and CS3) using the SPI_CS_CTL register. Multiple CS lines can be driven
simultaneously for a broadcast access. There are also override fields to enable software driving of 0 or 1 on the active
CS line(s), which may be required for some special use cases. All other SPI pins are shared across by the slaves.

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SPI Operating ModesSPI Operating Modes
The SPI supports the following features.

Wired-OR Mode (WOM)To prevent contention when the SPI is used in multislave system, the data output pins, MOSI and MISO, can be
configured to behave as open-circuit drivers. An external pull-up resistor is required when this feature is selected.
The SPI_CTL.WOM bit in the control register controls the pad enable outputs for the data lines.
General Instructions
1. SPI module operates on PCLK. So, if PCLK is stopped, this block does not work.
2. Whenever SPI configuration needs to be changed, ensure that the CS is de-asserted. This avoids any abrupt
breaks in the SPI transfers. If the configuration changes while SPI transfer is actively going on, the behavior of
the peripheral is nondeterministic.
3. While changing configurations, program SPI_CNT register only after changing SPI_CTL and SPI_IEN
registers. Else, transfers may get started even before the configuration is changed.

Power-down Mode
In master mode, before entering power-down mode, the user should ensure that the transfers are completed bychecking the appropriate interrupts/status bits. The SPI block should then be disabled by clearing the
SPI_CTL.SPIEN bit. Only then, the power-down entry would be clean.
In slave mode, in either mode of operation (interrupt driven or DMA), the CS line level must be checked using the
SPI_STAT.CS bit to ensure that the SPI is not communicating. The SPI block must be disabled only when the
CS line is high.
While being powered down, the following fields are retained:• All the bit fields of SPI_CTL register except SPI_CTL.SPIEN. During power-up, the SPI_CTL.SPIEN
bit is reset. This allows a fresh start of the peripheral at wake up.
• SPI_IEN.IRQMODE bit• SPI_DIV.VALUE bit• SPI_RD_CTL.THREEPIN bit• SPI_FLOW_CTL.RDYPOL bit
All the other fields are not retained. They are reset on power-up. On exiting the power-down mode, the softwaremust reprogram all the non-retained registers as required. The SPI block must be re-enabled by setting the
SPI_CTL.SPIEN bit.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPI Operating Modes

Interfacing with SPI Slaves
Though the SPI transfers are usually full-duplex, in many cases, the slave works on a protocol which consists ofCommand, Address, and Data Read/Write. The write command is always unidirectional. However, the read command needs a transmit transfer followed by a receive transfer in a single CS frame. An example protocol is shown
below.

Figure 15-2: SPI Register Read

To support transfers like the above one, which resembles a half-duplex operation, SPI_RD_CTL.CMDEN bit must
be set. The number of bytes to be transmitted should be programmed in SPI_RD_CTL.TXBYTES field (which is
1 for the above example). The number of bytes to be received (after completing the transmit) would be specified by
the SPI_CNT.VALUE bits. In this case, SPI_CNT.VALUE must be 1.
The SPI_RD_CTL.OVERLAP bit specifices if the bytes received while transmitting the command and address
bytes must be stored or ignored. If this bit is set, the SPI_CNT.VALUE bit refers to the total number of bytes inthe entire frame i.e, SPI_CNT.VALUE = number of bytes to be transmitted + number of bytes to be received.
Some SPI read examples are given below.
Read Command with TXBYTES = 1, CNT = 4, OVERLAP = 0
CSn

MOSI

X/Z

MISO

X

Tx0

Tx1

X

X/Z

X

Rx0

Rx1

Rx2

Rx3

X

SCLK

Read Command with TXBYTES = 1, CNT = 6, OVERLAP = 1
CSn

MOSI

X/Z

Tx0

Tx1

MISO

X

Rx0

Rx1

X/Z

X

Rx2

Rx3

Rx4

Rx5

X

SCLK

Figure 15-3: SPI Read Examples

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SPI Operating Modes

Pseudo Code Example for Read Command Mode
SPI0_DIV = 0x0001
SPI0_CTL = 0x0883//SPI serial clk frequency = ¼ of PCLK freq//Enable SPI in master mode, ZEN=1,//Continuous mode, TIM=0
SPI0_CNT = 0x0040//64 bytes to be received
SPI0_DMA = 0x0005//Enable DMA mode and Rx-DMA request
SPI0_RD_CTL = 0x000D //TXBYTES=3, CMDEN=1, Write 4 Tx bytes//in two 16-bit writes (DMA mode)
SPI0_TX = 0xB6A5
SPI0_TX = 0xD8C7
read_data = SPI0_RX //Do a dummy read of the receive FIFO to//initiate SPI transfers

In this case, only 4 bytes are transmitted as TXBYTES is 3. However, zeroes are sent on MOSI for the next 64 bytes
that are being received. In total, 4 bytes are transmitted and 64 bytes are received in a non-overlapping mode.

Flow Control
Several converters use a flow-control mechanism to match the required data/sample rate. The SPI master supports
the following types of flow-control:• Using a 16-bit timer clocked at the serial clock rate to introduce wait-states while reading data. The masterwaits until the timer ends and then reads SPI_FLOW_CTL.RDBURSTSZ+1 number of bytes. It goes back to
wait state and restarts the timer. This continues until SPI_CNT.VALUE number of bytes are received.
• Using a separate RDY pin which is connected through one of the GPIOs. The master waits until it sees anactive level in this pin. Once it detects the transition, it reads SPI_FLOW_CTL.RDBURSTSZ+1 number ofbytes and then goes back to wait state until another active level is detected. This continues until
SPI_CNT.VALUE number of bytes are received.
• Using the MISO pin. In this mode, the master waits for an active level on the MISO pin. Once it detects thetransition, it reads SPI_FLOW_CTL.RDBURSTSZ+1 number of bytes and then goes back to wait state until
another active level is detected. This continues until SPI_CNT.VALUE number of bytes are received.
In all the above cases, SPI_CNT.VALUE must be an integer multiple of SPI_FLOW_CTL.RDBURSTSZ+1.
Some example flow-controlled transfers are shown below.
Read Command with TXBYTES = 1, CNT = 3, RDBURSTSZ = 0, RDY_POL = 1 (using MISO pin)
CSn

MOSI

X/Z

MISO

x

Tx1

Tx0

x

X/Z
Rx0

Rx1

Rx3

X

SCLK

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPI Operating Modes

Read Command with CPHA = 1, CPOL = 0, TXBYTES = 0, CNT = 4, RDBURSTSZ = 1, WAIT_TMR = 10 (using Timer)
CSn

MOSI

X/Z

MISO

X

Tx0

X/Z
Rx0

X

Rx1

X

Rx2

Rx3

X

SCLK
<- 10 SCLK Cycles -><- 10 SCLK Cycles ->Figure 15-4: Flow-controlled Transfer Examples

NOTE: While stalling the SCLK output for flow-control or FIFO data/space unavailability, the last SCLK edge isalways a sampling edge. This is to avoid a driving edge before the stall period. That way, the slave would have an
SCLK driving edge to proceed with, after the stall period.
Though the SCLK signal idles low for a SPI_CTL.CPOL =0 and idles high for a SPI_CTL.CPOL = 1, the
SPI_CTL.CPHA bit determines the sequence of sampling and driving edges. If SPI_CTL.CPHA = 1, the SCLK
signal is stalled at the same level as the idle level. If SPI_CTL.CPHA = 0, the SCLK is stalled at the opposite levelto the idle level. At the end of a transfer (when CS is deasserted), the SCLK is always idled as per SPI_CTL.CPOL.
The Flow Control table explains the same.
Table 15-1: Flow Control
CPHA

CPOL

SCLK Idle level

SCLK Stalled level

0

0

0

1

0

1

1

0

1

0

0

0

1

1

1

1

Read Command with CPHA = 0, CPOL = 0, TXBYTES = 0, CNT = 2, RDBURSTSZ = 0, WAIT_TMR = 10 (using Timer)

CSn

MOSI

X/Z

MISO

X

Tx0

X/Z

Rx0

X

X

Rx1

X

SCLK
(Inled LOW,
Stalled HIGH)<- 10 SCLK Cycles -><- 10 SCLK Cycles ->Figure 15-5: Sample Transfer

Three-Pin Mode
SPI can be used in a 3-pin mode where the data transmission/reception occurs over a single bi-directional line. The
SPI master supports this for read command mode, where the MOSI line is used for transmission of 'Command +address' bytes and the same line is used for receiving the read data. To enable this, SPI_RD_CTL.THREEPIN and
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SPI Data Transfer

SPI_RD_CTL.CMDEN fields of SPI_RD_CTL register should be set. Inherently, there is a half SCLK cycle between the last sampling edge of transmit phase and the first driving edge of receive phase. However, if the slave needsa larger turn-around time, then it should enable timer based flow-control and program the
SPI_WAIT_TMR.VALUE as required. An example 3-pin SPI transfer is shown below.
Read Command with 3-pin SPI, TXBYTES = 0, CNT = 2. RDBURSTSZ = 0, WAIT_TMR = 1 (using Timer)
CSn

MOSI

X/Z

Rx1 (driven by Slave)

Rx0 (driven by Slave)

Tx0 (driven by Master)

X/Z

SCLK
1 SCLK

1 SCLK

Figure 15-6: 3-Pin SPI Transfer

SPI Data Transfer
In master mode, the transfer and interrupt mode bit (SPI_CTL.TIM) determines the manner in which an SPI
serial transfer is initiated. If the SPI_CTL.TIM bit is set, a serial transfer is initiated after a write to the transmit
FIFO occurs. If the SPI_CTL.TIM bit is cleared, a serial transfer is initiated after a read of the receive FIFO. The
read must be done while the SPI interface is idle. A read done during an active transfer will not initiate anothertransfer.
For any setting of the master mode enable (SPI_CTL.MASEN) and SPI_CTL.TIM bits, the SPI simultaneously
receives and transmits data (if SPI_RD_CTL.CMDEN bit is 0). Therefore, during data transmission, the SPI is also
receiving data and filling up the receive FIFO. If the data is not read from the receive FIFO, the overflow interrupt
occurs once the FIFO starts to overflow. If the user does not want to read the receive data or receive overflow interrupts, the receive FIFO flush enable (SPI_CTL.RFLUSH) bit can be set, and the receive data will not be saved to
the receive FIFO. Else, if the user just wants to read the receive data (not concerned about the overflow condition),
this interrupt can be disabled by clearing the SPI_IEN.RXOVR bit. Similarly, when the user only wants to receive
data and does not want to write data to the transmit FIFO, the transmit FIFO flush enable (SPI_CTL.TFLUSH)
bit can be set to avoid getting underflow interrupts from the transmit FIFO. Alternatively, if the user wants to send
the FIFO data, but, does not want underflow interrupts, the SPI_IEN.TXUNDR bit must be cleared.

Transmit Initiated Transfer
For transfers initiated by a write to the transmit FIFO, the SPI transmits as soon as the first byte is written to the
FIFO. The SPI transfer of the first byte happens immediately.
If the continuous transfer enable bit (SPI_CTL.CON) is set, the transfer continues until it is complete. This completion is either the end of SPI_CNT.VALUE number of bytes (if SPI_CNT.VALUE > 0) or when no valid data
is available in the transmit FIFO (if SPI_CNT.VALUE = 0). Chip Select remains asserted for the duration of thecomplete transfer. If SPI_CNT.FRAMECONT is cleared and SPI_CNT.VALUE > 0, the transfer stops when all
the SPI_CNT.VALUE bytes have been transferred. If the SPI_CNT.FRAMECONT is set, a new frame starts after
every SPI_CNT.VALUE number of bytes. Therefore, multiples of the SPI_CNT.VALUE bytes are transferred. If
there is no data/space in FIFO, the transfer stalls until it is available. Conversely, the transfer continues when there isvalid data in the FIFO.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPI Data Transfer

If SPI_CTL.CON is cleared, each transfer consists of a single 8-bit serial transfer. If valid data exists in the transmit
FIFO, a new transfer is initiated after a stall period, where Chip Select is deasserted.

Receive Initiated Transfer
Transfers initiated by a read of the receive FIFO depend on the number of bytes to be received in the FIFO. If
SPI_IEN.IRQMODE is set to 7 and a read to the receive FIFO occurs, the SPI master initiates an 8-byte transfer.
If continuous mode is set (SPI_CTL.CON), the 8 bytes happen continuously with no deassertion of Chip Selectbetween bytes. If continuous mode is not set, the 8 bytes will happen with stall periods between transfers, where theChip Select is deasserted. However, in continuous mode, if SPI_CNT.VALUE > 0, CS is asserted for the entire
frame duration. SPI will introduce stall periods by not clocking SCL until FIFO space is available.
If SPI_IEN.IRQMODE is set to 6, then a read of the receive FIFO will initiate a 7-byte transfer similar to above. If
SPI_IEN.IRQMODE is set to 1, then a read of the receive FIFO will initiate a 2-byte transfer. Finally, a read of the
FIFO with SPI_IEN.IRQMODE set to 0 initiates a single byte transfer. A read of the receive FIFO while the SPI is
receiving data will not initiate another transfer after the present transfer is complete. In continuous mode, if
SPI_CNT.VALUE > 0 and SPI_CNT.FRAMECONT = 1, read of receive FIFO at the end of an SPI frame (to get
the last set of bytes received) will always initiate a new SPI frame. Therefore, to stop SPI transfers at any given frame,
SPI_CNT.FRAMECONT bit should be cleared before reading the final set of receive bytes.
Full-duplex transfer with CON = 0, CNT = 4
CSn

MOSI

X/Z

Tx0

X/Z

Tx1

X/Z

Tx2

X/Z

Tx3

X/Z

MISO

X

Rx0

X

Rx1

X

Rx2

X

Rx3

X

SCLK

Rx-only transfer with CON = 1, CNT = 6, FRAMECONT = 0
CSn

MOSI

X/Z

MISO

X

X
Rx0

Rx1

Rx2

X/Z
Rx3

Rx4

Rx5

X

SCLK

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SPI Data Transfer

Tx-only transfer with CON = 1, CNT = 3, FRAMECONT = 1
CSn

MOSI

X/Z

MISO

X

Tx2

Tx1

Tx0

Tx3

X/Z

Tx5

Tx4

X/Z

X

X

SCLK

Figure 15-7: SPI Transfers

Transfers in Slave ModeIn slave mode, a transfer is initiated by the assertion of the Chip Select of the device.
Though the master can support upto four CS output lines, only one CS input, CS0, is used in slave mode.
The device as a slave transmits and receives 8-bit data until the transfer is concluded by the deassertion of Chip
Select.
The following SPI transfer protocol figures show the data transfer protocol for SPI and the effects of
SPI_CTL.CPHA and SPI_CTL.CPOL bits in the control register on that protocol, as indicated by T1, T2, andT3 ( See Figures SPI Transfer Protocol CPHA = 0 and SPI Transfer Protocol CPHA = 1).
NOTE: Chip Select must not be tied to the ground.
Clock Cycle
Number

1

2

3

4

5

XX

msb

6

5

4

3

XX

msb

6

5

4

3

6

7

8

2

1

1sb

xx

2

1

1sb

xx

SPI Clock
SPI_CTL.CPOL=0
SPI Clock
SPI_CTL.CPOL=1
MOSI
(From
master)MISO(From Slave)
CS

T1

T2

T3

Figure 15-8: SPI Transfer Protocol CPHA = 0

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPI Data Transfer

Clock Cycle
Number

1

2

3

4

5

XX

msb

6

5

4

3

XX

msb

6

5

4

3

6

7

8

2

1

1sb

xx

2

1

1sb

xx

SPI Clock
SPI_CTL.CPOL=0
SPI Clock
SPI_CTL.CPOL=1
MOSI
(From
master)MISO(From Slave)
CS

T1

T2

T3

Figure 15-9: SPI Transfer Protocol CPHA = 1

SPI Data Underflow and Overflow
If the transmit zeroes underflow mode bit (SPI_CTL.ZEN) is cleared, the last stale byte is shifted out when atransfer is initiated with no valid data in the FIFO. If SPI_CTL.ZEN is set, zeros are transmitted when a transfer is
initiated with no valid data in the FIFO.
If the receive overflow overwrite enable bit (SPI_CTL.RXOF) is set, the valid data in the receive FIFO is overwritten by the new serial byte received when there is no space left in the FIFO. If SPI_CTL.RXOF is cleared, the newserial byte received is discarded when there is no space left in the FIFO.
When valid data is being overwritten in the receive FIFO, the oldest byte is overwritten first followed by the next
oldest byte and so on.

SPI Interrupts and Exceptions
There is one interrupt line per SPI and eleven sources of interrupts.
The SPI_STAT.IRQ bit reflects the state of the interrupt line.
The SPI_STAT[15:12] and SPI_STAT[7:1] bits reflect the state of the eleven sources.
The SPI generates either Transmit Interrupt Requests (TIRQ) or Receive Interrupt Request (RIRQ). Both interrupts
cannot be enabled at the same time. The appropriate interrupt is enabled using the SPI_CTL.TIM bit. If
SPI_CTL.TIM = 1, TIRQ is enabled. If SPI_CTL.TIM = 0, RIRQ is enabled.
All interrupts are sticky and are cleared only when the appropriate interrupt bits in SPI_STAT register are writtenwith a 1. The interrupt line from the device is cleared only after all the interrupt sources are cleared.

Transmit Interrupt
If the SPI_CTL.TIM bit is set, the transmit FIFO status causes the interrupt. The SPI_IEN.IRQMODE bit control when the interrupt occurs. When the SPI_IEN.IRQMODE bits are set to:
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SPI Interrupts and Exceptions

000: An interrupt is generated after each byte that is transmitted. The interrupt occurs when the byte is read fromthe FIFO and written to the shift register.
001: An interrupt is generated after every two bytes that are transmitted.
...
110: An interrupt occurs after every seven bytes that are transmitted.
111: An interrupt occurs after every eight bytes that are transmitted.
The interrupts are generated depending on the number of bytes transmitted and not on the number of bytes in the
FIFO. This is different from the receive interrupt, which depends on the number of bytes in the receive FIFO andnot the number of bytes received.
The status of this interrupt can be read by reading the TXIRQ status bit. The interrupt is disabled if transmit FIFO
flush enable (TFLUSH) is high.
NOTE: Write to the SPI_CTL register resets the transmitted byte counter back to zero. For example, when the
SPI_IEN.IRQMODE bit is set to 0x3 and after three bytes have been transmitted, the SPI_CTL register is reinitialized, the transmit interrupt does not occur until another 4 bytes have been transmitted.

Receive Interrupt
If the SPI_CTL.TIM is cleared, the receive FIFO status causes the interrupt. Again, SPI_IEN.IRQMODE controls when the interrupt will occur. The status of this interrupt can be read by reading the SPI_STAT.RXIRQ
status bit.
Interrupts are only generated when data is written to the FIFO. For example, if SPI_IEN.IRQMODE is set to 0x0,
an interrupt is generated after the first byte is received. If the interrupt was cleared by writing 1 and the data byte
was not read from the receive FIFO, the interrupt will not be regenerated. Another interrupt will only be generated
when another byte is received into the FIFO.
The interrupt depends on the number of valid bytes in FIFO when the SPI is receiving data. It does not depend on
the number of bytes received over the SPI.
The interrupt is disabled if SPI_CTL.RFLUSH is left high.

Underflow/Overflow Interrupts
When a transfer starts with no data in the transmit FIFO, the SPI_STAT.TXUNDR bit of the Status register getsset to indicate an underflow condition. This will cause an interrupt if SPI_STAT.TXUNDR is set. This interrupt
will occur irrespective of what SPI_CTL.TIM bit is set to. This interrupt is disabled if SPI_CTL.TFLUSH bit isset.
If data is received when the receive FIFO is already full, this will cause the SPI_STAT.RXOVR bit of the Status
register to go high indicating an overflow condition. This will cause an interrupt if SPI_IEN.RXOVR is set. This
interrupt occurs irrespective of the SPI_CTL.TIM bit setting. This interrupt is disabled if SPI_CTL.RFLUSH
bit is set.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPI Programming Model

The receive and transmit interrupts are cleared if the relevant flush bits are asserted or SPI is disabled. Else, the interrupts stay active even if the SPI is reconfigured.

SPI Programming Model
The following section provides the SPI DMA details.

SPI DMA
Two DMA channels are dedicated to SPI, transmit and receive. The two SPI DMA channels should be configuredin the DMA controller.
It is possible to enable DMA request on 1 or 2 channels at the same time, by setting the DMA request bits forreceive or transmit in the SPI_DMA register. If only the DMA transmit request (SPI_DMA.TXEN) is enabled, theRx FIFO overflows during the SPI transfer unless received data is read by user code, and an overflow interrupt isgenerated. To avoid generating overflow interrupts, the Rx FIFO flush bit (SPI_CTL.RFLUSH) should be set, or
the SPI_IEN.RXOVR bit should be cleared, or the SPI interrupt be disabled in the NVIC of the core. If only the
DMA receive request (SPI_DMA.RXEN) is enabled, the Tx FIFO underflows. Again, to avoid underflow interrupt,
the SPI_IEN.TXUNDR bit must be cleared or the SPI interrupt must be disabled in the NVIC.
NOTE: Check the status of Tx FIFO. It should not be empty before issuing a dummy read so that unintended Tx
underflow interrupt is not observed.
The SPI Tx and Rx interrupts are not generated when DMA is used. SPI_IEN.IRQMODE is not used in transmit
mode and must be set to 3'b000 in receive mode.
The DMA bit (SPI_DMA.TXEN) controls the start of a DMA transfer. DMA requests are only generated when
SPI_DMA.EN = 1. At the end of a DMA transfer, that is, when receiving a DMA SPI transfer interrupt, this bit
needs to be cleared to prevent extra DMA requests to the µDMA controller. The data still present in the Tx FIFO istransmitted if in Tx mode.
All DMA data transfers are 16-bit transfers, and the DMA should be programmed accordingly. For example, if 16
bytes of data are to be transferred over the SPI, the DMA should be programmed to perform eight half-word (16bit) transfers. If 17 bytes are to be transferred, nine half-word transfers are required, the additional byte is discarded.
Data errors occur if the DMA transfers are programmed as byte-wide transfers.
In DMA mode, the Tx/Rx FIFOs are 2 bytes wide. Bits[7:0] are first accessed by the SPI followed by the bits[15:8].
This is irrespective of count or SPI_CTL.LSB settings. For example, if SPI_CNT.VALUE = 3, the order oftransmission/reception is as follows (Byte-3 is ignored).
Byte-1

Byte-0Byte-3Byte-2

NOTE: The SPI_CTL.LSB bit does not affect the FIFO access order in the DMA mode. It only affects how eachbyte is transferred over SPI.
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SPI Programming Model

DMA Master Transmit Configuration
The DMA SPI Tx channel must be configured. The NVIC must be configured to enable DMA Tx master interrupt.
The SPI block must be configured as follows:
SPI_DIV = SPI_SERIAL_FREQ; //configures serial clock frequency.
SPI_CTL = 0x1043;//enables SPI in master mode and transmit mode, Rx FIFO//flush enabled.
SPI_CNT.VALUE = NUM_BYTES_TO transfer; //sets the number of bytes to transfer.
SPI_DMA = 0x1;//(optional) enables FIFO to accept 16-bit//core data writes.
SPI_TX = 0xXXXX;//(optional) up to four 16-bit core writes can be performed//to preload FIFO.
SPI_DMA = 0x3;//enable DMA mode, enable Tx DMA request.

All DMA transfers are expected to be 16-bit transfers. When all data present in the DMA buffer are transmitted, theDMA generates an interrupt. User code should disable DMA request. Data will still be in the Tx FIFO as the DMA
request is generated each time there is free space in the Tx FIFO, to keep the FIFO always full.
DMA Master Receive Configuration
The SPI_CNT register sets the number of receive bytes required by the SPI master. When the required number ofbytes has been received, no more transfers are initiated. To initiate a DMA master receive transfer, a dummy readshould be done by user code. This dummy read must not be added to the SPI_CNT number.
The counter counting the bytes as they are received is reset when SPI is disabled using the SPI_CTL.SPIEN bit in
SPI_CTL, or if the SPI_CNT register is modified by user code.
To perform SPI DMA master receive:
The DMA SPI Rx channel must be configured. The NVIC of the core must be configured to enable DMA Rx master interrupt.
The SPI block must be configured as follows:
SPI_DIV = SPI_SERIAL_FREQ; //configures serial clock frequency.
SPI_CTL = 0x2003;//enable SPI in master mode and//receive mode, 1 byte transfer.
SPI_DMA = 0x5;//enable DMA mode, enable Rx DMA request.
SPI_CNT.VALUE = XXX;//number of bytes to be received.
A = SPI_RX;//dummy read.

The DMA transfer stops when the appropriate number of clock cycles has been generated. All DMA data transfers
are 16-bit transfers, and the DMA should be programmed accordingly. For example, if 16 bytes of data are to be

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPI Programming Model

received over the SPI, the DMA should be programmed to perform eight 16-bit transfers. If 17 bytes are to be received, nine 16-bit transfers are required. The additional byte is padded for the final DMA transfer. Data errors
occur if the DMA transfers are programmed as byte wide transfers.
NOTE: DMA buffer must be of the same size as SPI_CNT.VALUE (or same size plus one if SPI_CNT.VALUE isodd) to generate a DMA interrupt when the transfer is complete.
DMA Slave Transmit Configuration
The DMA SPI Tx channel must be configured. The NVIC must be configured to enable DMA Tx interrupt.
The SPI block must be configured as follows:
SPI_CTL = 0x1241;
mit mode,//enables SPI in slave mode and trans-//Rx FIFO, flush enabled.
SPI_CNT.VALUE = NUM_BYTES_TO_TRANSFER;//set the number of bytes to transmit.
SPI_TX = 0xXXXX;//(optional) up to four 16-bit writes can be performed
to preload FIFO.
// This should also be considered while programming theN-1 of DMA.
SPI_DMA = 0x3;//enable DMA mode, enable Tx DMA request.

All SPI DMA transfers are expected to be 16-bit transfers. When all data present in the DMA buffer are transmitted,
the DMA generates an interrupt. User code should disable DMA request. Data will still be in the Tx FIFO as the
DMA request is generated each time there is free space in the Tx FIFO, to keep the FIFO always full.
DMA Slave Receive Configuration
The SPI_CNT register sets the number of receive bytes required.
The running counter counting the bytes as they are received is reset when SPI is disabled using the
SPI_CTL.SPIEN bit in SPI_CTL, or if the SPI_CNT register is modified by user code.
To perform SPI DMA master receive:
The DMA SPI Rx channel must be configured. The NVIC of the core must be configured to enable DMA Rx interrupt.
The SPI block must be configured as follows:
SPI_CTL = 0x2001;
transfer
SPI_DMA = 0x5;
SPI_CNT.VALUE = XXX;A = SPI_RX;//enables SPI in slave mode and receive mode, 1 byte//enable DMA mode, enable Rx DMA request.
//number of bytes to be received.
//dummy read.

The DMA transfer stops when the appropriate number of half words have been received. All DMA data transfers are
16-bit transfers, and the DMA should be programmed accordingly. For example, if 16 bytes of data are to be received over the SPI, the DMA should be programmed to perform eight 16-bit transfers. If 17 bytes are to be
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ADuCM4050 SPI Register Descriptions

received, nine 16-bit transfers are required. The additional byte is padded for the final DMA transfer. Data errors
occur if the DMA transfers are programmed as byte wide transfers.
NOTE: DMA buffer must be of the same size as SPI_CNT.VALUE (or same size plus one if SPI_CNT.VALUE isodd) to generate a DMA interrupt when the transfer is complete.

ADuCM4050 SPI Register Descriptions
Serial Peripheral Interface (SPI) contains the following registers.
Table 15-2: ADuCM4050 SPI Register List
Name

Description

SPI_CNT

Transfer Byte CountSPI_CS_CTL

Chip Select Control for Multi-slave Connections

SPI_CS_OVERRIDE

Chip Select Override

SPI_CTLSPI Configuration

SPI_DIV

SPI Baud Rate Selection

SPI_DMASPI DMA Enable

SPI_FIFO_STATFIFO Status

SPI_FLOW_CTL

Flow Control

SPI_IENSPI Interrupts Enable

SPI_RD_CTL

Read Control

SPI_RX

ReceiveSPI_STAT

StatusSPI_TX

Transmit

SPI_WAIT_TMR

Wait Timer for Flow Control

15–16

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ADuCM4050 SPI Register Descriptions

Transfer Byte Count
This register is only used in master mode.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FRAMECONT (R/W)
Continue Frame

VALUE (R/W)
Transfer Byte Count

Figure 15-10: SPI_CNT Register Diagram
Table 15-3: SPI_CNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 FRAMECONT(R/W)

Continue Frame.
This bit should be used in conjunction with SPI_CTL.CON and SPI_CNT.VALUE
fields. It is used to control SPI data framing. If this bit is cleared, the SPI master transfers only one frame of SPI_CNT.VALUE bytes. If set, the SPI master will transfer
data in frames of SPI_CNT.VALUE bytes each.
Note: If SPI_CNT.VALUE = 0, this field has no effect as the SPI master will continue with transfers as long as Tx/Rx FIFO is ready. If SPI_CTL.CON = 0, this field has
no effect as all SPI frames are single byte wide irrespective of other control fields.
0 If SPI_CNT.VALUE > 0, stop SPI transfers after
SPI_CNT.VALUE number of bytes.
1 Continue SPI transfers as long as Tx/Rx FIFO is ready.

13:0 VALUE(R/W)

Transfer Byte Count.
This field specifies the number of bytes to be transferred. It is used in both receive andtransmit transfer types. This value assures that a master mode transfer terminates at theproper time and that 16-bit SPI_DMA transfers are byte padded or discarded as required to match odd transfer counts.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPI Register Descriptions

Chip Select Control for Multi-slave Connections
This register is only used in master mode.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

SEL (R/W)
Chip Select Control

Figure 15-11: SPI_CS_CTL Register Diagram
Table 15-4: SPI_CS_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
3:0 SEL(R/W)

Chip Select Control.
This field specifies the CS line to be used for the current SPI transfer. It is useful in a
multi-slave setup where only the CS lines are unique across the various slaves. The SPI
master can support up to 4 different CS lines. By default, CS0 is used if none of thebits are set.
Note: If multiple bits are set, the respective CS lines are active simultaneously.

15–18

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPI Register Descriptions

Chip Select OverrideThis register is only used in master mode.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CTL (R/W)
CS Override Control

Figure 15-12: SPI_CS_OVERRIDE Register Diagram
Table 15-5: SPI_CS_OVERRIDE Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1:0 CTL(R/W)

CS Override Control.
This bit overrides the actual CS output from the master state machine. It may be needed for special SPI transfers. Note: Use it with precaution.
0 CS is not forced.
1 CS is forced to drive 1'b1.
2 CS is forced to drive 1'b0.
3 CS is not forced.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

15–19

ADuCM4050 SPI Register Descriptions

SPI Configuration
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CSRST (R/W)
Reset Mode for CS Error Bit

SPIEN (R/W)
SPI Enable

TFLUSH (R/W)
SPI Tx FIFO Flush Enable

MASEN (R/W)
Master Mode Enable

RFLUSH (R/W)
SPI Rx FIFO Flush Enable

CPHA (R/W)
Serial Clock Phase Mode

CON (R/W)
Continuous Transfer Enable

CPOL (R/W)
Serial Clock Polarity

LOOPBACK (R/W)
Loopback Enable

WOM (R/W)
SPI Wired-OR ModeOEN (R/W)
Slave MISO Output Enable

LSB (R/W)
LSB First Transfer Enable

RXOF (R/W)
Rx Overflow Overwrite Enable

TIM (R/W)
SPI Transfer and Interrupt ModeZEN (R/W)
Transmit Zeros Enable

Figure 15-13: SPI_CTL Register Diagram
Table 15-6: SPI_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14 CSRST(R/W)

13 TFLUSH(R/W)

Reset Mode for CS Error Bit.
If this bit is set, the bit counter will be reset after a CS error condition and the Cortex
is expected to clear the SPI_CTL.SPIEN. If this bit is clear, the bit counter will continue from where it stopped. SPI can receive the remaining bits when CS gets asserted
and Cortex has to ignore the SPI_STAT.CSERR interrupt. However, it is recommended to set this bit for recovery after a CS error.
SPI Tx FIFO Flush Enable.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if
a single flush is required. If this bit is left high, then either the last transmitted value or
0x00 is transmitted depending on the SPI_CTL.ZEN bit. Any writes to the Tx
FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.

15–20

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPI Register Descriptions

Table 15-6: SPI_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
12 RFLUSH(R/W)

SPI Rx FIFO Flush Enable.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if
a single flush is required. If this bit is set all incoming data is ignored and no interrupts
are generated. If set and SPI_CTL.TIM = 0, a read of the Rx FIFO will initiate atransfer.
Clear this bit to disable Rx FIFO flushing.

11 CON(R/W)

Continuous Transfer Enable.
Set by user to enable continuous transfer. In master mode, the transfer continues until
no valid data is available in the SPI_TX register (SPI_CTL.TIM=1) or until the Rx
FIFO is full (SPI_CTL.TIM=0). CS is asserted and remains asserted for the durationof each 8-bit serial transfer until Tx FIFO is empty or Rx FIFO is full.
Cleared by user to disable continuous transfer. Each SPI frame then consists of a single
8-bit serial transfer. If valid data exists in the SPI_TX register (SPI_CTL.TIM=1) or
Rx FIFO is not full (SPI_CTL.TIM=0), a new transfer is initiated after a stall periodof 1 serial clock cycle.

10 LOOPBACK
(R/W)
9 OEN
(R/W)
8 RXOF
(R/W)
7 ZEN
(R/W)
6 TIM
(R/W)

Loopback Enable.
Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Slave MISO Output Enable.
Set this bit for MISO to operate as normal. Clear this bit to disable the output driveron the MISO pin. The MISO pin will be Open-Circuit when this bit is clear.
Rx Overflow Overwrite Enable.
Set by user, the valid data in the SPI_RX register is overwritten by the new serial byte
received. Cleared by user, the new serial byte received is discarded.
Transmit Zeros Enable.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit
to transmit the last transmitted value when there is no valid data in the Tx FIFO.
SPI Transfer and Interrupt Mode.
Set by user to initiate transfer with a write to the SPI_TX register. Interrupt only occurs when SPI_IEN.IRQMODE+1 number of bytes have been transmitted.
Cleared by user to initiate transfer with a read of the SPI_RX register. Interrupt only
occurs when Rx-FIFO has SPI_IEN.IRQMODE+1 number of bytes or more.

5 LSB
(R/W)

LSB First Transfer Enable.
0 MSB transmitted first
1 LSB transmitted first

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPI Register Descriptions

Table 15-6: SPI_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
4 WOM

SPI Wired-OR Mode.

(R/W)

0 Normal output levels
1 Enables open circuit data output enable. External pullups required on data out pins

3 CPOL

Serial Clock Polarity.

(R/W)

0 Serial clock idles low
1 Serial clock idles high2 CPHA

Serial Clock Phase Mode.

(R/W)

0 Serial clock pulses at the end of each serial bit transfer
1 Serial clock pulses at the beginning of each serial bit
transfer

1 MASEN(R/W)

Master Mode Enable.
Note: Clearing this bit issues a synchronous reset to the design and most status bits,
while other MMRs are unaffected.
0 Enable slave mode
1 Enable master mode

0 SPIEN(R/W)

SPI Enable.
0 Disable the SPI
1 Enable the SPI

15–22

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPI Register Descriptions

SPI Baud Rate Selection
This register is only used in master mode.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
SPI Clock Divider

Figure 15-14: SPI_DIV Register Diagram
Table 15-7: SPI_DIV Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5:0 VALUE(R/W)

SPI Clock Divider.
SPI_DIV.VALUE is the factor used to divide PCLK to generate the serial clock.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

15–23

ADuCM4050 SPI Register Descriptions

SPI DMA Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RXEN (R/W)
Enable Receive DMA Request

EN (R/W)
Enable DMA for Data Transfer

TXEN (R/W)
Enable Transmit DMA Request

Figure 15-15: SPI_DMA Register Diagram
Table 15-8: SPI_DMA Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
2 RXEN(R/W)
1 TXEN(R/W)

Enable Receive DMA Request.
If this bit is set when DMA is enabled, then a Rx DMA request is raised as long there
is valid data in Rx FIFO.
Enable Transmit DMA Request.
If this bit is set and DMA is enabled, a Tx DMA request is raised as long there is spacein Tx FIFO.
Note: This bit needs to be cleared as soon as a Tx DMA DONE interrupt is received
to prevent extra Tx DMA requests to the DMA controller.

0 EN
(R/W)

15–24

Enable DMA for Data Transfer.
Set by user code to start a DMA transfer.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPI Register Descriptions

FIFO Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RX (R)SPI Rx FIFO Status

TX (R)SPI Tx FIFO Status

Figure 15-16: SPI_FIFO_STAT Register Diagram
Table 15-9: SPI_FIFO_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
11:8 RX(R/NW)SPI Rx FIFO Status.
This field specifies the number of bytes in Rx FIFO when DMA is disabled. In DMA
mode, it refers to the number of half-words in Rx FIFO.
0 Rx FIFO empty
1 1 valid byte/half-word in Rx FIFO
2 2 valid bytes/half-words in Rx FIFO
3 3 valid bytes/half-words in Rx FIFO
4 4 valid bytes/half-words in Rx FIFO
5 5 valid bytes/half-words in Rx FIFO
6 6 valid bytes/half-words in Rx FIFO
7 7 valid bytes/half-words in Rx FIFO
8 8 valid bytes/half-words in Rx FIFO (Rx FIFO full)

3:0 TX(R/NW)SPI Tx FIFO Status.
This field specifies the number of bytes in Tx FIFO when DMA is disabled. In DMA
mode, it refers to the number of half-words in Tx FIFO.
0 Tx FIFO empty
1 1 valid byte/half-word in Tx FIFO
2 2 valid bytes/half-words in Tx FIFO
3 3 valid bytes/half-words in Tx FIFO
4 4 valid bytes/half-words in Tx FIFO
5 5 valid bytes/half-words in Tx FIFO
6 6 valid bytes/half-words in Tx FIFO
7 7 valid bytes/half-words in Tx FIFO
8 8 valid bytes/half-words in Tx FIFO (Tx FIFO full)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

15–25

ADuCM4050 SPI Register Descriptions

Flow Control
This register is only used in master mode.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RDBURSTSZ (R/W)
Read Data Burst Size - 1

MODE (R/W)
Flow Control Mode

RDYPOL (R/W)
Polarity of RDY/MISO Line

Figure 15-17: SPI_FLOW_CTL Register Diagram
Table 15-10: SPI_FLOW_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:6 RDBURSTSZ(R/W)

Read Data Burst Size - 1.
Specifies number of bytes to be received - 1 in a single burst from a slave before waiting for flow-control.
This is not valid if SPI_FLOW_CTL.MODE is 2'b00. For all other values of
SPI_FLOW_CTL.MODE, this field is valid. It takes values from 0 to 1023 implying aread burst of 1 to 1024 bytes respectively.
Note: This mode is useful for reading fixed-width conversion results periodically.

4 RDYPOL(R/W)

Polarity of RDY/MISO Line.
Specifies the polarity of the RDY/MISO pin, which indicates that the slave's read data
is ready.
If SPI_FLOW_CTL.MODE= 2'b10, it refers to the polarity of RDY pin.
If SPI_FLOW_CTL.MODE=2'b11, it refers to the polarity of MISO (DOUT) line.
For all other values of SPI_FLOW_CTL.MODE, this bit is ignored.
0 Polarity is active high. SPI master waits until RDY/MISO becomes high.
1 Polarity is active low. SPI master waits until RDY/MISO becomes low.

15–26

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPI Register Descriptions

Table 15-10: SPI_FLOW_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1:0 MODE(R/W)

Flow Control Mode.
Flow control configuration for data reads.
Note: When RDY signal is used for flow-control, it could be any signal which is tied tothis RDY input of SPI module. For example, it can be an off-chip input, on-chip timer
output, or any other control signal.
0 Flow control is disabled.
1 Flow control is based on timer (WAIT_TMR).
2 Flow control is based on RDY signal.
3 Flow control is based on MISO pin.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

15–27

ADuCM4050 SPI Register Descriptions

SPI Interrupts Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

TXEMPTY (R/W)
Tx FIFO Empty Interrupt Enable

IRQMODE (R/W)
SPI IRQ Mode BitsXFRDONE (R/W)
SPI Transfer Completion Interrupt Enable

CS (R/W)
Enable Interrupt on Every CS Edge
in Slave CON ModeTXDONE (R/W)
SPI Transmit Done Interrupt Enable

TXUNDR (R/W)
Tx Underflow Interrupt Enable

RDY (R/W)
Ready Signal Edge Interrupt Enable

RXOVR (R/W)
Rx Overflow Interrupt Enable

Figure 15-18: SPI_IEN Register Diagram
Table 15-11: SPI_IEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14 TXEMPTY(R/W)

Tx FIFO Empty Interrupt Enable.
This bit enables the SPI_STAT.TXEMPTY interrupt whenever Tx FIFO gets emptied.
0 TXEMPTY interrupt is disabled.
1 TXEMPTY interrupt is enabled.

13 XFRDONE(R/W)

SPI Transfer Completion Interrupt Enable.
This bit enables the SPI_STAT.XFRDONE interrupt.
0 XFRDONE interrupt is disabled.
1 XFRDONE interrupt is enabled.

12 TXDONE(R/W)

SPI Transmit Done Interrupt Enable.
This bit enables the SPI_STAT.TXDONE interrupt in read command mode.
Note: This can be used to signal the change of SPI transfer direction in read commandmode.
0 TXDONE interrupt is disabled.
1 TXDONE interrupt is enabled.

15–28

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPI Register Descriptions

Table 15-11: SPI_IEN Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
11 RDY(R/W)

Ready Signal Edge Interrupt Enable.
Enables the SPI_STAT.RDY interrupt whenever an active edge occurs on RDY/MISO signals.
If SPI_FLOW_CTL.MODE = 2'b10, edge detection happens on RDY signal.
If SPI_FLOW_CTL.MODE = 2'b11, MISO signal is used instead of RDY.
For all other values of SPI_FLOW_CTL.MODE, this bit has no effect.
The active edge (rising/falling) is determined by the SPI_FLOW_CTL.RDYPOL bit.
0 RDY signal edge interrupt is disabled.
1 RDY signal edge interrupt is enabled.

10 RXOVR

Rx Overflow Interrupt Enable.

(R/W)

0 Rx overflow interrupt is disabled.
1 Rx overflow interrupt is enabled.

9 TXUNDR

Tx Underflow Interrupt Enable.

(R/W)

0 Tx underflow interrupt is disabled.
1 Tx underflow interrupt is enabled.

8 CS
(R/W)

Enable Interrupt on Every CS Edge in Slave CON Mode.
If this bit is set and the SPI module is configured as a slave in continuous mode, anyedge on CS will generate an interrupt and the corresponding status bits
(SPI_STAT.CSRISE, SPI_STAT.CSFALL) will be asserted.
If this bit is not set, then no interrupt will be generated and the status bits will not be
asserted.
This bit has no effect if the SPI is not in continuous mode or if it is a master.

2:0 IRQMODE(R/W)

SPI IRQ Mode Bits.
These bits configure when the Tx/Rx interrupts occur in a transfer. For DMA Rx
transfer, these bits must be 3'b000.
0 Tx interrupt occurs when 1 byte has been transferred.
Rx interrupt occurs when 1 or more bytes have been received into the FIFO.
1 Tx interrupt occurs when 2 bytes have been transferred.
Rx interrupt occurs when 2 or more bytes have been received into the FIFO.
2 Tx interrupt occurs when 3 bytes have been transferred.
Rx interrupt occurs when 3 or more bytes have been received into the FIFO.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

15–29

ADuCM4050 SPI Register Descriptions

Table 15-11: SPI_IEN Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 Tx interrupt occurs when 4 bytes have been transferred.
Rx interrupt occurs when 4 or more bytes have been received into the FIFO.
4 Tx interrupt occurs when 5 bytes have been transferred.
Rx interrupt occurs when 5 or more bytes have been received into the FIFO.
5 Tx interrupt occurs when 6 bytes have been transferred.
Rx interrupt occurs when 6 or more bytes have been received into the FIFO.
6 Tx interrupt occurs when 7 bytes have been transferred.
Rx interrupt occurs when 7 or more bytes have been received into the FIFO.
7 Tx interrupt occurs when 8 bytes have been transferred.
Rx interrupt occurs when the FIFO is full.

15–30

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPI Register Descriptions

Read Control
This register is only used in master mode.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

THREEPIN (R/W)
Three Pin SPI Mode

CMDEN (R/W)
Read Command Enable

TXBYTES (R/W)
Transmit Byte Count - 1 (Read Command)

OVERLAP (R/W)
Tx/Rx Overlap Mode

Figure 15-19: SPI_RD_CTL Register Diagram
Table 15-12: SPI_RD_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
8 THREEPIN(R/W)

Three Pin SPI Mode.
Specifies if the SPI interface has a bidirectional data pin (3-pin interface) or dedicatedunidirectional data pins for Tx and Rx (4-pin interface). This is only valid in Readcommand mode and when SPI_FLOW_CTL.MODE = 2'b01.
If 3-pin mode is selected, MOSI pin will be driven by master during transmit phaseand after a wait time of SPI_WAIT_TMR SCLK cycles, the slave is expected to drive
the same MOSI pin.
Note: SPI_FLOW_CTL.MODE should be programmed to 2'b01 to introduce waitstates for allowing turnaround time. Else, the slave only has a turn-around time of half
SCLK period (between sampling and driving edges of SCLK). If this mode is used, set
SPI_RD_CTL.OVERLAP = 0.
0 SPI is a 4-pin interface.
1 SPI is a 3-pin interface.

5:2 TXBYTES(R/W)

Transmit Byte Count - 1 (Read Command).
Specifies the number of bytes to be transmitted - 1 before reading data from a slave.
This field can take values from 0 to 15 corresponding to 1 to 16 Tx bytes . This includes all the bytes that need to be sent out to the slave viz., command and address (ifrequired). The design does not differentiate between these two. It just transmits the
specified number of bytes from the Tx FIFO.
Note: If there is a latency between the command transmission and data reception, then
the number of Tx bytes (mostly 0's) to be padded for that delay should also be accounted for in this count.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

15–31

ADuCM4050 SPI Register Descriptions

Table 15-12: SPI_RD_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 OVERLAP(R/W)

Tx/Rx Overlap Mode.
This bit specifies if the start of Tx and Rx overlap. In most of the slaves, the read data
starts only after the master completes the transmission of 'command+address'. This is a
non-overlapping transfer. In some slaves, there might be status bytes sent out while thecommand is being received. So, user may need to start receiving the bytes from the
beginning of the CS frame. This is overlapping mode.
Note: In case of overlapping mode, SPI_CNT.VALUE refers to the total number ofbytes to be received. So, the extra status bytes (which are in addition to the actual read
bytes) should be accounted for while programming SPI_CNT.VALUE.
0 Tx/Rx overlap is disabled.
1 Tx/Rx overlap is enabled.

0 CMDEN(R/W)

Read Command Enable.
SPI read command mode where a command + address is transmitted and read data is
expected in the same CS frame. If this bit is cleared, all other fields of SPI_RD_CTL,
SPI_FLOW_CTL and SPI_WAIT_TMR registers do not have any effect.
0 Read command mode is disabled.
1 Read command mode is enabled.

15–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPI Register Descriptions

Receive
This register allows access to the 8-deep receive FIFO.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BYTE2 (R)
8-bit Receive Buffer, Used Only in DMA
Modes

BYTE1 (R)
8-bit Receive Buffer

Figure 15-20: SPI_RX Register Diagram
Table 15-13: SPI_RX Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:8 BYTE2(R/NW)
7:0 BYTE1

8-bit Receive Buffer, Used Only in DMA Modes.
These 8-bits are used only in the SPI_DMA mode, where all FIFO accesses happen as
half-word access. They return zeros if SPI_DMA is disabled.
8-bit Receive Buffer.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

15–33

ADuCM4050 SPI Register Descriptions

Status15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

RDY (R/W1C)
Detected an Edge on Ready Indicatorfor Flow Control
CSFALL (R/W1C)
Detected a Falling Edge on CS, in Slave
CON Mode
CSRISE (R/W1C)
Detected a Rising Edge on CS, in Slave
CON Mode
CSERR (R/W1C)
Detected a CS Error Condition in SlaveMode
CS (R)CS Status

0

0

0

1

0

0

IRQ (R)
SPI Interrupt StatusXFRDONE (R)SPI Transfer Completion
TXEMPTY (R/W1C)
SPI Tx FIFO Empty Interrupt
TXDONE (R/W1C)
SPI Tx Done in Read Command Mode
TXUNDR (R/W1C)
SPI Tx FIFO Underflow
TXIRQ (R/W1C)
SPI Tx IRQ

RXOVR (R/W1C)
SPI Rx FIFO Overflow
RXIRQ (R/W1C)
SPI Rx IRQ

Figure 15-21: SPI_STAT Register Diagram
Table 15-14: SPI_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 RDY(R/W1C)

Detected an Edge on Ready Indicator for Flow Control.
This bit indicates that there was an active edge on the RDY/MISO line depending on
the flow control mode. If SPI_FLOW_CTL.MODE = 2'b10, this bit is set wheneveran active edge is detected on RDY signal.
If SPI_FLOW_CTL.MODE = 2'b11, this bit is set if an active edge is detected on MISO signal.
For all other values of MODE, this bit is always 0.
The active edge (rising/falling) is determined by the SPI_FLOW_CTL.RDYPOL.
When SPI_IEN.RDY is set, this bit will cause an interrupt, and it is cleared only
when 1 is written to this bit.
Note: This can be used for staggered flow-control on transmit side, along with a CS
override if required.

15–34

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ADuCM4050 SPI Register Descriptions

Table 15-14: SPI_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
14 CSFALL(R/W1C)

Detected a Falling Edge on CS, in Slave CON Mode.
This bit indicates that there was a falling edge in CS line, when the device was a slavein continuous mode and SPI_IEN.CS was asserted. This bit will cause an interrupt.
It is cleared when 1 is written to this bit or when SPI_CTL.SPIEN is cleared.
This can be used to identify the start of an SPI data frame.

13 CSRISE(R/W1C)

Detected a Rising Edge on CS, in Slave CON Mode.
This bit indicates that there was a rising edge in CS line, when the device was a slave incontinuous mode and SPI_IEN.CS was asserted. This bit will cause an interrupt. It
is cleared when 1 is written to this bit or when SPI_CTL.SPIEN is cleared.
This can be used to identify the end of an SPI data frame.

12 CSERR(R/W1C)

Detected a CS Error Condition in Slave Mode.
This bit indicates that the CS line was de-asserted abruptly by an external master, even
before the full-byte of data was transmitted completely.
This bit will cause an interrupt. It is cleared when 1 is written to this bit or when
SPI_CTL.SPIEN is cleared.

11 CS(R/NW)CS Status.
This bit reflects the actual CS status as seen by the SPI module.
Note: This uses SCLK-PCLK synchronization. So, there would be a slight delay when
CS changes state.
0 CS line is low.
1 CS line is high.

7 RXOVR(R/W1C)SPI Rx FIFO Overflow.
Set when the Rx FIFO was already full when new data was loaded to the FIFO. Thisbit generates an interrupt if SPI_IEN.RXOVR is set, except when
SPI_CTL.RFLUSH is set.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.

6 RXIRQ(R/W1C)SPI Rx IRQ.
Set when a receive interrupt occurs. Not available in DMA mode. This bit is set when
SPI_CTL.TIM is cleared and the required number of bytes have been received.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.

5 TXIRQ(R/W1C)SPI Tx IRQ.
SPI Tx IRQ Status Bit. Not available in DMA mode.
Set when a transmit interrupt occurs. This bit is set when SPI_CTL.TIM is set andthe required number of bytes have been transmitted.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.

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ADuCM4050 SPI Register Descriptions

Table 15-14: SPI_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
4 TXUNDR(R/W1C)SPI Tx FIFO Underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. Thisbit generates an interrupt if SPI_IEN.TXUNDR is set, except when
SPI_CTL.TFLUSH is set.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.

3 TXDONE(R/W1C)SPI Tx Done in Read Command Mode.
This bit is set when the entire transmit is completed in a read command. This bit generates an interrupt if SPI_IEN.TXDONE is set.
This bit is valid only if SPI_RD_CTL.CMDEN is set. It is cleared only when 1 is written to this bit.

2 TXEMPTY(R/W1C)SPI Tx FIFO Empty Interrupt.
This bit is set when the Tx-FIFO is empty and SPI_IEN.TXEMPTY is set, except
when SPI_CTL.TFLUSH is set. This bit generates an interrupt.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.

1 XFRDONE(R/NW)SPI Transfer Completion.
This bit indicates the status of SPI transfer completion in master mode. It is set when
the transfer of SPI_CNT.VALUE number of bytes have been finished. In slave mode
or if SPI_CNT.VALUE = 0, this bit is invalid.
If SPI_IEN.XFRDONE is set, this bit generates an interrupt. It uses the state of themaster state machine to determine the completion of a SPI transfer. Therefore, a CS
override does not affect this bit. It is cleared only when 1 is written to this bit.

0 IRQ
(R/NW)

15–36

SPI Interrupt Status.
Set to 1 when an SPI based interrupt occurs. Cleared when all the interrupt sources arecleared.

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ADuCM4050 SPI Register Descriptions

Transmit
This register allows access to the 8-deep transmit FIFO.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BYTE2 (W)
8-bit Transmit Buffer, Used Only in
DMA Modes

BYTE1 (W)
8-bit Transmit Buffer

Figure 15-22: SPI_TX Register Diagram
Table 15-15: SPI_TX Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:8 BYTE2(RX/W)
7:0 BYTE1

8-bit Transmit Buffer, Used Only in DMA Modes.
These 8-bits are used only in the SPI_DMA mode, where all FIFO accesses happen as
half-word access.
8-bit Transmit Buffer.

(RX/W)

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ADuCM4050 SPI Register Descriptions

Wait Timer for Flow Control
This register is only used in master mode.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Wait Timer

Figure 15-23: SPI_WAIT_TMR Register Diagram
Table 15-16: SPI_WAIT_TMR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/W)

Wait Timer.
This field specifies the number of SCLK cycles to wait before continuing the SPI read.
This field can take values of 0 to 65535.
This field is only valid if SPI_FLOW_CTL.MODE = 2'b01.
For all other values of SPI_FLOW_CTL.MODE, this field is ignored.
A value of 0 implies a wait time of 1 SCLK cycle.

15–38

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSerial Port (SPORT)

16 Serial Port (SPORT)The ADuCM4050 MCU has a serial port (SPORT) that support a variety of serial data communication protocols.
In addition, the SPORT provides a glueless hardware interface to several industry-standard data converters, codecs
and other processors, including DSPs. The SPORT top module comprises of two half SPORTs (HSPORT) withidentical functionality SPORT_A and SPORT_B. Each half SPORT can be independently configured as either atransmitter or receiver and can be coupled with the other HSPORT within the same SPORT. Each half SPORT has
the same capabilities and is programmed in the same way.

SPORT Features
Each HSPORT supports the following features:• One bidirectional data line, configurable as either transmitter or receiver. Further, two half SPORT can be
combined to enable full-duplex operation.
• Operation mode:• Standard DSP serial mode
• Timer-enabled mode
• Gated clock mode
• Serial data words between 4 and 32 bits in length.
• Granularity for internal clock generation, allowing even PCLK to SPT_CLK ratios. The SPORTs can also accept an input clock from an external source.
• Configurable rising or falling edge of the SPT_CLK for driving or sampling data and frame sync.
• Gated clock mode support for internal clock mode.
• Frame Sync options:• Unframed mode
• Internal/external frame sync options• Programmable polarity

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Signal Description• Early/Late Frame Sync
• External frame sync signal configured as level-sensitive signal.
• Status flagging and optional interrupt generation for prematurely received external frame syncs and transmit
underflow (or receive overflow).
• Optional 16-bit to 32-bit word or 8-bit to 32-bit packing when SPORT is configured as receiver and 32-bit to
16-bit or 32-bit to 8-bit word unpacking when configured as Transmitter.
• Interrupt driven transfer support.
• Interrupt control.
• Transfer Finish Interrupt (TFI): An interrupt is generated when the last bit of programmed number of transfers
is transmitted out.
• Programmable bit order - MSB/LSB first.
• Programmable transfer count of 1-4095 words.
• Both core transfers and DMA transfers are possible with dedicated DMA channel for each half SPORT.
• Ability to route and share the clocks and/or frame sync between the SPORT halves of the SPORT module.
• SPT_CNV signal generation in timer-enable mode.
• Each half SPORT has its own set of control registers and data buffers.

Signal Description
Each half SPORT module has four dedicated pins, as described in the following table.
Table 16-1: SPORT Pin Descriptions
Internal Node

Direction

Description

SPT_CLK

I/O

Transmit/Receive Serial Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated.

SPT_FS

I/O

Transmit/Receive Frame Sync. The frame sync pulse initiates shifting of serial data.
This signal is either generated internally or externally.

SPT_D0I/O

Transmit/receive Data channel. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data.

SPT_CNV

OutputThis is an additional control signal used only in the case of Timer enable mode for
peripherals which require two signals for control information.

• The clock and frame sync signals can be interconnected between the half SPORT pair.
• The SPT_CNV signal is used only in the timer enable mode (see Timer-Enable Mode).

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPORT Functional Description

SPORT Functional Description
The following section provides general information about functionality of the serial ports of MCU.

SPORT Block Diagram
The figure shows the top-level block diagram of the SPORT.
It shows the interfacing with the APB and DMA channel. It also shows the connection with the peripheral.
CORE IRQ

SPT_CNV A
SPT_FS A

HALF SPORT A

SPT_CLK ADMA Signals

SPT_D0 A
APB Bus

SPT_CNV B
SPT_FS B

HALF SPORT B

SPT_CLK B

DMA Signals

SPT_D0 B

CORE IRQ

Figure 16-1: Top-level Block Diagram of SPORTThe following figure shows the block diagram of a half SPORT.
Core IRQSPT_FS
MMR
Regis
ters

32

SPORT
transmit block
SPORT
receive block32

TX FIFO

Control
information

DMA signals

SPT_CLKSPT_CNVRX FIFOAPB signals

Control block

TX data

SPT_D0RX
data

Figure 16-2: Half SPORT Block Diagram

Each SPORT module consists of two separate blocks, known as half SPORT (HSPORT) A and B, with identical
functionality. These blocks can be independently configured as transmitter or receiver, as shown in the top-level
block diagram.
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SPORT Functional Description

Each HSPORT has its own set of control registers and data buffers. The Two HSPORTs must be combined to achieve full-duplex operation.

SPORT Transfer
The SPORT is configured in transmit mode, if SPORT_CTL_A.SPTRAN or SPORT_CTL_B.SPTRAN control
bit is set. If this bit is cleared, serial port is configured in receive mode. Once a path is activated, data is shifted in
response to a frame sync at the rate of serial clock. Receive data buffers are inactive when SPORT is operating intransmit mode and transmit data buffers when in receive mode. Inactive data buffers are not used and should not be
accessed. An application program must use the appropriate data buffers.
Transmit Path
The SPORT_CTL_A.SPTRAN or SPORT_CTL_B.SPTRAN control bit, when set, configures the SPORT in
transmit mode.
The SPORT_TX_A and SPORT_TX_B registers are used as the transmit data buffer (which is a three deep FIFO).
The data to be transmitted is written to the SPORT_TX_A and SPORT_TX_B registers. This data is then transferred to the transmit shift register. The shift register, clocked by SPT_CLK signal, then serially shifts out this data on
SPT_D0, synchronously. If framing signal is used, the SPT_FS signal indicates the start of the serial word transmission.
When SPORT is configured as transmitter, the enabled SPORT data pins SPT_ D0 are always driven.
NOTE: If next frame sync is assigned after a time duration greater than serial word length, then during inactive
serial clock cycles (clock cycles after data transmission in the current frame), the SPORT drives the first bit of next
word to be transmitted on the data pin. This does not cause any problem at the receiver end, as it starts sampling thedata pin only after detecting a valid frame sync. Note that this is not the case in gated clock mode as no clock ispresent during inactive frame sync.
The serial port provides status of transmit data buffers and error detection logic for transmit errors such as underrun. For more information, refer to Error Detection.
When a serial port is configured in transmit mode, the receive data path is deactivated and will not respond to serial
clock or frame sync signals. So, reading from an empty Receive Data Buffer is not recommended in Tx mode.
Receive Path
The SPORT_CTL_A.SPTRAN bit, when cleared, configures the SPORT in receive mode.
The SPORT_RX_A and SPORT_RX_B registers, which are the receive data buffers (three deep FIFO), are accessible over APB.
In Rx mode, the input shift register shifts in data bits on the SPT_D0, synchronous to the SPT_CLK. If framing
signal is used, the SPT_x.FS signal indicates the beginning of the serial word being received. When an entire word isshifted in on the channel, the data is available to be read from SPORT_RX_x.
The serial port provides the status of Receive Data buffers and error detection logic for receive errors such as overflow. For more information, refer to Error Detection.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPORT Functional Description

When a serial port is configured in receive mode, the transmit path is deactivated and does not respond to serial
clock or frame sync signals. Therefore, accessing the transmit data buffer is not recommended in Rx mode.

Multiplexer Logic
There is a multiplexing block integrated between the SPORT and the PinMux logic. It allows flexibility to route andshare the clock and frame sync signals between the two half SPORT pairs. This feature can be used to reduce thetotal number of pins for the interface and is efficient when the half SPORT pair is used for full-duplex operation.
SPORT_CTL_A.CKMUXSEL and SPORT_CTL_A.FSMUXSEL are used to configure this feature.
The figure below shows the operation of this multiplexer connected between half SPORTs clocks. Half SPORT A
can be programmed to obtain clock from the neighboring half SPORT B.
SPT_CLK A
HSCLK A_IN

0

HSPORT A

1

SPORT_CTL_A.CKMUXSELHSCLK B_OUT
SPT_CLK B

HSPORT B

Figure 16-3: Multiplexer Logic When HSPORT A Uses HSPORT B’s Internal Clock

If SPORT_CTL_A.CKMUXSEL is 1, it receives an internal clock of B when SPORT_CTL_B.ICLK value is 1.

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SPORT Functional Description

HSCLK A_IN

0

SPT_CLK A

1

SPT_CLK B

HSPORT A

SPORT_CTL_A.CKMUXSELHSCLK B_IN

HSPORT B

Figure 16-4: Multiplexer Logic When HSPORT A and HSPORT B Use Same External Clock

If SPORT_CTL_A.CKMUXSEL is 1 and SPORT_CTL_B.ICLK is 0, both half SPORTs get the same external
clock.
If SPORT_CTL_A.CKMUXSEL is 0, normal operation of clock is carried out for both the half SPORTs.
The figure below shows the operation of the multiplexer connected between half SPORTs frame sync. Half SPORT
A can be programmed to obtain frame sync from the neighboring half SPORT B
SPT_FSAHSFS A_IN

0

HSPORT A

1

SPORT_CTL_A.FSMUXSELHSCLK B_OUT

SPT_FS B

HSPORT B

Figure 16-5: Multiplexer Logic When HSPORT A Uses HSPORT B’s Internal Frame Sync

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPORT Functional Description

If SPORT_CTL_A.FSMUXSEL is 1, it gets internal frame sync of B when SPORT_CTL_B.IFS value is 1.

HSFS A_IN

0

SPT_FS A

1

SPT_FS B

HSPORT A

SPORT_CTL_A.FSMUXSELHSFS B_IN

HSPORT B

Figure 16-6: Multiplexer Logic When HSPORT A and HSPORT B Use Same External Frame Sync

If SPORT_CTL_A.FSMUXSEL is 1 and SPORT_CTL_B.IFS is 0, both half SPORTs get the same externalframe sync.
If SPORT_CTL_A.FSMUXSEL is 0, normal operation of frame sync is carried out for both the half SPORTs.
Polarity bits such as SPORT_CTL_A.CKRE,SPORT_CTL_B.CKRE, SPORT_CTL_A.LFS, and
SPORT_CTL_B.LFS must have identical settings when using muxing between two SPORT halves. The numberof transfers (NUMTRAN) value must also be programmed with the same number in both half SPORTs when sameinternal clock/frame sync is used in both halves.
NOTE: HSPORT A can import serial clock signal from HSPORT B, only when it is configured in external clock
mode. Similarly, it can import frame sync signal, only when it is configured in external frame sync mode.
SPORT_CTL_A register programming (for SPORT_CTL_A.CKMUXSEL and SPORT_CTL_A.FSMUXSEL) is
required only for HSPORT A (not for HSPORT B) to enable this sharing. HSPORTB cannot import serial clock
sgnal and framne sync signal from HSPORT A

Serial Clock
The serial clock (SPT_CLK) signal controls how the data bits are driven or sampled. The frame sync signal is also
driven (in internal frame sync mode) or sampled (in external frame sync mode) with respect to serial clock. The
serial clock can be internally generated from the MCU's system clock or externally provided, based on the
SPORT_CTL_x.ICLK (SPORT_CTL_A.ICLK or SPORT_CTL_B.ICLK) bit. If a SPORT is configured ininternal clock mode (SPORT_CTL_x.ICLK= 1), then the SPORT_DIV_x.CLKDIV(SPORT_DIV_A.CLKDIV or SPORT_DIV_B.CLKDIV) field specifies the divider to generate serial port clock
signal from its fundamental clock, HCLK. This divisor is a 16-bit value, allowing a wide range of serial clock rates.
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SPORT Functional Description

The following equation is used to calculate the serial clock frequency:
f SPT_CLK =HCLK
2x(1+SPORT_DIV_xCLKDIV)

In gated clock mode, the serial port can be configured to generate gated clock which is active only for the durationof valid data.
If a SPORT is configured in external clock mode (SPORT_CTL_x.ICLK = 0), then serial clock is an input signal
and the SPORT operates in slave mode. The SPORT_DIV_x.CLKDIV is ignored.
The externally supplied serial clock is always considered as an asynchronous clock with respect to the MCU system
clock. For exact AC timing specifications, refer to the ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with
Integrated Power Management Data Sheet.

Frame Sync
Frame sync is a control signal, used to determine the start of new word or frame. Upon detecting this signal, serial
port starts shifting in or out the data bits serially based on the direction selected. The frame sync signal can be internally generated from its serial clock (SPT_CLK x) or externally provided, based on the SPORT_CTL_x.IFS(SPORT_CTL_A.IFS or SPORT_CTL_B.IFS) bit setting.
If SPORT is configured for internal frame sync mode (SPORT_CTL_x.IFS = 1), then the
SPORT_DIV_x.FSDIV (SPORT_DIV_A.FSDIV or SPORT_DIV_B.FSDIV) field specifies the divider togenerate SPT_FS x signal from the serial clock. This divisor is a 8-bit value, allowing a wide range of frame sync
rates to initiate periodic transfers.
Number of serial clocks between frame syncs = (SPORT_DIV_x.FSDIV + 1).
FSDIV is used for the internally generated SPT_CNV signal when it is operating in timer enable mode. Therefore,
for timer enable mode, this field refers to the number of serial clock cycles between SPT_CNV pulses.
The value of SPORT_DIV_x.FSDIV must not be less than the value of the SPORT_CTL_x.SLEN(SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN) bit field (the serial word length minus one, as this may cause
an external device to abort the current operation or cause other unpredictable results.
NOTE: After enabling the SPORT, the first internal frame sync (or CNV in case of Timer enable mode) appears
after a delay of (SPORT_DIV_x. FSDIV + 1) serial clocks.
If a SPORT is configured in external frame sync mode (SPORT_CTL_x.IFS = 0), then SPT_FS x is an input
signal and the SPORT_DIV_x.FSDIV field of the SPORT_DIV_x (SPORT_DIV_A or SPORT_DIV_B) register is ignored. By default, this external signal is level-sensitive. The frame sync is expected to be synchronous withthe serial clock. If not, it must meet the timing requirements mentioned in the ADuCM4050 Ultra Low Power ARM
Cortex-M4F MCU with Integrated Power Management Data Sheet.
NOTE: When the SPORT is enabled with external frame sync, frame sync must be deasserted.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceFrame Sync

Frame Sync Options
The framing signals may be active high or low. The SPORT_CTL_x.LFS bit (SPORT_CTL_A.LFS or
SPORT_CTL_B.LFS) selects the logic level of the frame sync signals.
• When SPORT_CTL_x.LFS = 0, the corresponding frame sync signal is active high. Default polarity of frame
sync signal• When SPORT_CTL_x.LFS = 1, the corresponding frame sync signal is active low.
The following sections describe how frame sync signal is used by the serial port in an operating mode.
Data Dependent Frame Sync and Data Independent Frame Sync
When a SPORT is configured as a transmitter, that is, SPORT_CTL_x.SPTRAN bit (SPORT_CTL_A.SPTRAN
or SPORT_CTL_B.SPTRAN) is 1, and if data independent frame sync select, that is SPORT_CTL_x.DIFS bit(SPORT_CTL_A.DIFS or SPORT_CTL_B.DIFS) is 0, then an internally-generated transmit frame sync is only
driven when a new data word has been loaded into the transmit buffer of the SPORT. In other words, frame sync
signal generation and therefore data transmission is data-dependent. This mode of operation allows for wait states
when data is not ready.
When SPORT is configured as receiver (SPORT_CTL_x.SPTRAN = 0) and if SPORT_CTL_x.DIFS= 0, then areceive frame sync signal is generated only when receive data buffer status is not full.
The data-independent frame sync mode allows the continuous generation of the framing signal, regardless of thebuffer status. Setting SPORT_CTL_x.DIFS activates this mode. When SPORT_CTL_x.DIFS = 1, a transmit/
receive frame sync signal is generated regardless of the transmit/receive data buffer status respectively.
NOTE: The DMA typically keeps the transmit buffer full. The application is responsible for filling the transmit
buffers with data. Else, an underflow/overflow case would arise and it would be flagged.
Early Frame Sync and Late Frame Sync
The frame sync signals can be early or late. The SPORT_CTL_x.LAFS bit of the serial port control register configures this option.
By default, when SPORT_CTL_x.LAFS is cleared, the frame sync signal is configured as early framing signal. Thisis the normal mode of operation. In this mode, the first bit of the transmit data word is available (and the first bit of
the receive data word is latched) in the next serial clock cycle after the frame sync is asserted. The frame sync is notchecked again until the entire word has been transmitted (or received).
If data transmission is continuous in early framing mode (in other words, the last bit of each word is immediately
followed by the first bit of the next word), then frame sync signal occurs during the last bit of each word. Internallygenerated frame syncs are asserted for one clock cycle in early framing mode.
When SPORT_CTL_x.LAFS is set, late frame syncs are configured; this is the alternate mode of operation. In thismode, the first bit of the transmit data word is available (and the first bit of the receive data word is latched) in thesame serial clock cycle that the frame sync is asserted. Receive data bits are latched by serial clock edges. Internallygenerated frame syncs remain asserted for the entire length of the data word in late framing mode.
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Frame Sync

NOTE: In the case of late frame sync, externally generated frame syncs are expected to be asserted for the entire
word length of the data transfer. Else, unpredictable results can occur.
The figure shows the two modes of frame signal timing.

SPT_CLK

Early
Frame Sync

1 CLK

Late
Word Length

Frame Sync

Data

D3

D2

D1

D0

Figure 16-7: Normal Framing (Early Frame Sync) and Alternate Framing (Late Frame Sync)

Framed Sync and Unframed Frame Sync
The use of frame sync signal is optional in serial port communications. The SPORT_CTL_x.FSR bit(SPORT_CTL_A.FSR or SPORT_CTL_B.FSR) determines if framing signal is required.
When SPORT_CTL_x.FSR bit is set, a frame sync signal is required for every data word.
When SPORT_CTL_x.FSR is cleared, the corresponding frame sync signal is not required. A single frame sync isrequired to initiate communications but it is ignored after the first bit is transferred. Data words are then transferredcontinuously in what is referred to as an unframed mode. Unframed mode is appropriate for continuous reception/transmission.
The following figure shows the framed versus unframed mode of serial port operation.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPORT Functional Description

SPT_CLK

Framed Mode - Frame Sync

Data

B

B

B

B

B

B

B

B

3

2

1

0

3

2

1

0

B

B

B

B

B

B

B

B

B

B

B

3

2

1

0

3

2

1

0

3

2

1

Unframed Mode - Frame Sync

Data

Figure 16-8: Framed Data Stream and Unframed Data Stream

NOTE: In unframed mode of operation, the SPORT_CTL_x.DIFS bit must always be set to 1.
SPORT_CTL_x.DIFS=0 is not supported for unframed mode. Also, the SPORT_CTL_x.LAFS bit must always
be set as zero. Late frame sync is not supported for unframed mode.

Sampling Edge
The serial port uses two control signals to sample or drive the serial data:• Serial clock (SPT_CLK) applies the bit clock for each serial data.
• Frame sync (SPT_FS) divides the data stream into frames.
These control signals can be internally generated or externally provided, determined by the SPORT_CTL_x.ICLK(SPORT_CTL_A.ICLK or SPORT_CTL_B.ICLK) and SPORT_CTL_x.IFS (SPORT_CTL_A.IFS or
SPORT_CTL_B.IFS) bit settings.
Data and frame syncs can be sampled on the rising or falling edges of the serial port clock signals. The
SPORT_CTL_x.CKRE (SPORT_CTL_A.CKRE or SPORT_CTL_B.CKRE) bit controls the sampling edge. Bydefault, when SPORT_CTL_x.CKRE = 0, the MCU selects the falling edge of SPT_CLK signal for sampling receive data and external frame sync. The receive data and frame sync are sampled on the rising edge of SPT_CLK
when SPORT_CTL_x.CKRE = 1.
Transmit data and internal frame sync signals are driven (change their state) on the serial clock edge that is not selected. By default, (SPORT_CTL_x.CKRE = 0) the SPORTs drive data and frame sync signals on the rising edgeof the SPT_CLK signal and drives on falling edge when SPORT_CTL_x.CKRE= 1.
Therefore, transmit and receive functions of any two serial ports connected together should always select the samevalue for SPORT_CTL_x.CKRE so that internally generated signals are driven on one edge, and received signals
are sampled on the opposite edge.
The following figure shows the typical SPORT signals on two sides of serial communication for
SPORT_CTL_x.CKRE = 0.
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SPORT Functional Description

SPT_CLK
Frame Sync
drivenData driven

D6

D7

D5

D4

D3

D2

D1

D0

Frame Sync
sampledData sampled

D7

D6

D5

D4

D3

D2

D1

D0

Figure 16-9: Frame Sync and Data Driven on Rising Edge

When the slave samples the Frame Sync signal, the word counter is reloaded to the maximum setting. Each
SPT_CLK decrements this word counter until the full frame is received.
Therefore, if the transmitter drives the internal frame sync and data on the rising edge of serial clock, the falling edge
must be used by receiver to sample the external frame sync and data, and vice versa.

Premature Frame Sync Error Detection
A SPORT framing signal is used to synchronize transmit or receive data. In external FS mode, if a frame sync is
received when an active frame is in progress or the frame sync truncates during an on-going transfer when using lateframe sync, it is called premature frame sync and is invalid.
If premature frame sync is received, the SPORT_STAT_x.FSERR bit (SPORT_STAT_A.FSERR or
SPORT_STAT_B.FSERR) is flagged to indicate this framing error. An optional error interrupt can be generated
for this event by setting the SPORT_IEN_x.FSERRMSK bits (SPORT_IEN_A.FSERRMSK and
SPORT_IEN_B.FSERRMSK).
As shown in the figure, the frame sync error (which sets the error bit) is triggered when an early frame sync occurs
during data transfer (transmission or reception) or for late frame sync if the period of the frame sync is smaller than
the serial word length (SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN).
FSERR Interrupt

EARLY FS

SPT_CLK
Frame sync
drivenDatadriven

D6

D7

D5

D4

D3

D2

D1

D0

Frame sync
sampledSLENCounterDatasampled

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 16-10: Frame Sync Error Detection

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPORT Functional Description

When a frame sync error occurs, the SPORT_CTL_x_FSERMODE bit (SPORT_CTL_A.FSERRMODE or
SPORT_CTL_B.FSERRMODE) decides the way this error is handled only in case of receive operation. If this bit isset, the receive data is discarded. When the next frame sync comes, fresh receive transfer is carried out.
If this bit is zero, then the frame sync error is flagged and the transfer is continued. No action is taken with respect
to the transfer.

Serial Word Length
The SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field of serial port control register determines the word
length of serial data to transmit and receive. Each half SPORT can independently handle word lengths up to 32 bits.
Words smaller than 32 bits are right-justified during transmit or receive buffers to least significant bit (LSB) position. However, data can be shifted-in or out in MSB first or LSB first format based on SPORT_CTL_A.LSBF or
SPORT_CTL_B.LSBF bit setting.
The value of the SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field can be calculated as:
SLEN = Serial port word length - 1
The range of valid word length in Standard serial mode is 4-32.

Number of Transfers
The register SPORT_NUMTRAN_A or SPORT_NUMTRAN_B of the SPORT determines the number of word transfers. The word length is specified in the SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field. Each half
SPORT has this field and can be used for receive or transmit depending on the SPORT_CTL_A.SPTRAN or
SPORT_CTL_B.SPTRAN bit. This field can be programmed to the required number of word transfers to be transmitted/received. Once the programmed number of transfers are done, the SPORT disables all the operations. Thatis, clock is not generated if in internal clock mode and not latched if in external clock mode. The frame sync is not
generated and no operation is performed for received frame syncs.
For example, if 20 transfers are programmed and word length programmed is 20 bits, after 400 bits of transfer the
SPORT would disable all the operations.
This register has 12 programmable bits to decide the number of transfers.
To start the next set of transfers, the SPORT_NUMTRAN_A and SPORT_NUMTRAN_B registers must be reprogrammed with the desired number of transfers. If the same number of transfers need to be programmed, the samevalue must be reprogrammed.
Also, once the number of transfers are finished, in external clock mode, no extra frame syncs are expected to be sent
to the SPORT. For new transfers, the frame sync must be sent only once the NUMTRAN is reprogrammed.
NOTE: In unframed mode, the number of transfers cannot be reprogrammed to perform the next set of transfers.
SPORT must be disabled and re-enabled to perform the operation for the next set of transfers in case of unframed
mode.

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SPORT Operating Modes

SPORT Operating Modes
The ADuCM4050 MCU has SPORT that supports the following operating modes:• Standard serial mode
• Timer-enable mode
• Gated clock mode
The SPORT halves within a SPORT can be independently configured if they are not coupled using SPMUX logic.
NOTE:• These modes support either, cases where the clock and the frame sync are both internal or both are external.
Modes with external frame sync, internal clock and internal frame sync, external clock is not supported by the
SPORT. Only for the unframed mode, external clock (SPORT_CTL_x.ICLK = 0 (SPORT_CTL_A.ICLK
or SPORT_CTL_B.ICLK)) and internal frame sync pulse (SPORT_CTL_x.IFS = 1(SPORT_CTL_A.IFS or SPORT_CTL_B.IFS)), generated for the start of transfer is supported.
• To change the SPORT configuration (for example, changing SPORT_CTL_x.SLEN(SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN) or SPORT_CTL_x.LSBF (SPORT_CTL_A.LSBF
or SPORT_CTL_B.LSBF)), clear the SPORT_CTL_x.SPEN bit (SPORT_CTL_A.SPEN or
SPORT_CTL_B.SPEN) and re-enable again by setting this bit.
• When SPORT is operating in external clock mode, SPORT needs three serial clocks after the SPORT is enabled before the normal operation can begin.

Mode Selection
The operating mode is configured in the SPORT_CTL_x.OPMODE (SPORT_CTL_A.OPMODE or
SPORT_CTL_B.OPMODE).
Standard Serial Mode
The SPORT can be configured in standard DSP serial mode by clearing the SPORT_CTL_x.OPMODE. The standard serial mode lets programs configure serial ports to connect to a variety of serial devices such as serial data converters and audio codecs. In order to connect to these devices, a variety of clocking, framing, and data formatting
options are available. All these options are as discussed in the above section describing the signals and the various
features. All of these options can be used in the standard serial mode.
Timer-Enable Mode
Few ADCs/DACs require two control signals for their conversion process. To interface with such devices, an extra
signal (SPT_CNV) is required. The timer-enable mode must be enabled to use this signal by programming the
SPORT_CTL_x.OPMODE to 1. A PWM timer inside the module is used to generate the programmable CNV signal.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPORT Operating Modes

The width of the SPT_ONV signal is programmed in the SPORT_CNVT_x.WID (SPORT_CNVT_A.WID or
SPORT_CNVT_B.WID) field. The delay between SPT_CNV assertion and frame sync assertion is programmed in
the SPORT_CNVT_x.CNVT2FS (SPORT_CNVT_A.CNVT2FS or SPORT_CNVT_B.CNVT2FS). This programmability provides flexibility in the use of these signals. The following figure shows these values.
SPT_CLK
CNV

CNV_WIDTH

CNV_WIDTH
CNV_FS_DURTN
Word Length

Frame Sync
Data

D3

D2

D1

D0

FSDIV

Figure 16-11: Signals Interfaced in Timer-Enable Mode

The polarity of the SPT_CNV signal can be programmed in the SPORT_CNVT_x.POL (SPORT_CNVT_A.POL
or SPORT_CNVT_B.POL) bit field.
The number of serial clock cycles between CNV pulse is given by FSDIV value. All the other programmable options
defined for frame sync in the DSP serial mode can be used in this mode except the following options:• External frame sync and external clock cannot be used.
• Early frame sync cannot be used.
• Unframed mode cannot be used.
NOTE: SPT_CNV signal is not used when DSP serial mode is in use.
Gated Clock Mode
Some ADC/DACs support SPI compatible protocol for the interface. To communicate with such converters, theserial port supports gated clock mode of operation, in which the data valid information is embedded into the clock.
Therefore, in gated clock mode, the clock is active only when valid data is being transmitted or received.
The SPORT_CTL_x.GCLKEN (Gated clock mode select) control bit, is used to configure the serial port in gatedclock mode.
Gated clock mode has the following settings for other control bits. Program appropriately to set these bits to ensure
correct gated mode operation.
• Both serial clock and frame sync signals generated internally.
• Both serial clock and frame sync signals provided externally.
• Frame sync not required (mode SPORT_CTL_A.FSR = 0 not supported).

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SPORT Data Transfer

SPORT Data Transfer
The SPORT uses either a core driven or DMA driven data transfers. DMA transfers can be set up to transfer a configurable number of serial words between the serial port transmit or receive data buffers and internal memory automatically. Core-driven transfers use SPORT interrupts to signal the MCU core to perform single word transfers to/from the serial port data buffers.

Single Word (Core) Transfers
Individual data words may also be transmitted or received by the serial ports, with interrupts occurring as each data
word is transmitted or received. When a serial port is enabled and corresponding DMA is disabled, the SPORT
interrupts are generated whenever a complete word has been received in the receive data buffer, or whenever thetransmit data buffer is not full.
When serial port data packing is enabled, transmit and receive interrupts are generated for 32-bit packed words, notfor each 16-bit or 8-bit word. When performing core driven transfers, write to the buffer designated by the
SPORT_CTL_A.SPTRAN (where A is the half SPORT) bit setting. To avoid undetermined behavior, check thestatus of appropriate data buffers when the MCU core tries to read a word from a serial port's receive buffer orwrites a word to its transmit buffer. The full/empty status can be read using the SPORT_STAT_x.DXS(SPORT_STAT_A.DXS or SPORT_STAT_B.DXS) bits.

DMA Transfers
Direct memory access (DMA) provides a mechanism for receiving or transmitting an entire block of serial data before an interrupt is generated. When SPORT DMA is not enabled, the SPORT generates an interrupt every time it
receives or starts to transmit a data word. The MCU's on-chip DMA controller handles the DMA transfer, allowing
the MCU core to either go to sleep or continue running other tasks until the entire block of data is transmitted or
received. Service routines can then operate on the block of data rather than on single words, significantly reducing
overhead.
Therefore, set the direction bit, DMA enable bit, and serial port enable bit before initiating any operations on the
SPORT data buffers. Do not try to access data buffers when the associated DMA channel of serial port is enabled.
Each half SPORT has a dedicated DMA channel for Tx and Rx data paths. In transmit mode, the DMA controller
writes to the transmit data buffer. Similarly, in receive mode, the DMA controller reads from the receive data buffer.
The DMA controller generates an interrupt at the end of the completion of a DMA transfer.
The SPORTs can handle word sizes from 4 to 32 bits (as defined by SPORT_CTL_x.SLEN(SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN) field). If serial data length is 16 bits or smaller, two databytes can be packed into 32-bit words for each DMA transfer. If serial data length is 8 bits or smaller, four data canbe packed into 32-bit words for each DMA transfer. When serial port data packing is enabled, transmit and receive
DMA requests are generated for the 32-bit packed words, not for each 16-bit or 8-bit word.
Depending on whether packing is enabled, appropriate DMA transfer width needs to be selected in the DMA controller. If packing is enabled or greater than 16-bit transfers are desired, use word transfers in DMA. If packing is notenabled and transfer is less than 16 bits but greater than 8 bits, use half word transfers. If packing is not enabled andtransfer length is less than 8 bits, use byte transfers within the DMA controller.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPORT Data Buffers

NOTE: DMA requests may not be serviced frequently to guarantee continuous data flow in case of continuoustransmission/reception. Ensure that the DMA channel has the highest priority when performing such transfers.

SPORT Data Buffers
Data Buffer Status
The SPORT provides status information about data buffers. Depending on the SPORT_CTL_A.SPTRAN bit setting, these bits reflect the status of transmit data buffers or receive data buffers. The SPORT_STAT_x.DXS bits
indicate if the buffers are full, partially full, or empty.
To avoid undetermined conditions, always check the buffer status to determine if the access can be made. The status
bits in the SPORT_STAT_A.DXS field always reflect the FIFO status.
Three complete 32-bit words can be stored in the receive buffer while the fourth word is being shifted in. Therefore,
four complete words can be received without the receive buffer being read, before an overflow occurs. After receiving
the fourth word completely, the shift register contents overwrite the third word if the first word has not been readout (by the MCU core or DMA controller). When this happens, the receive overflow status is flagged through theerror status bits of the SPORT_STAT_A.DERR register. The overflow status is generated after the last bit of the
fourth word is received.

Data Buffer Packing
When the SPORT is configured as a receiver with a serial data word length of 16 or less or even 8 or less, thenreceived data words may be packed into a 32-bit word. Similarly, if the SPORT is configured as transmitter with aserial data word length of 16 or less, then 32-bit words being transmitted may be unpacked into two 16-bit words orfour 8-bit words. This feature is selected by the SPORT_CTL_x.PACK (SPORT_CTL_A.PACK or
SPORT_CTL_B.PACK) bit.
NOTE: If packing is not enabled for lower length transfers, bus bandwidth as well as FIFO buffers are not efficiently
used.
When SPORT_CTL_x.PACK= 01, four successive words received are packed into a single 32-bit word, or each 32bit word is unpacked and transmitted as four 8-bit words. The words with less than 16-bit are packed as [SLEN:0], [(SLEN+8):8], [(SLEN+16):16], and [(SLEN+24):24]. This applies to both receive (packing)and transmit (unpacking) operations.
The figure shows the 8-bit packing. The dark region corresponds to the packed bits.
32 SLEN+24

24

SLEN+16

16 SLEN+8

8

SLEN

0

Figure 16-12: Packed Data (8-bit Packing)

When SPORT_CTL_x.PACK is assigned 10, two successive words received are packed into a single 32-bit word,or each 32-bit word is unpacked and transmitted as two 16-bit words. The words with less than 16-bit are packed as
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SPORT Interrupts and Exceptions[SLEN: 0] and [(SLEN+16):16].This applies to both receive (packing) and transmit (unpacking) operations.
The figure shows the 16-bit packing.
32

SLEN+16

16

SLEN

0

Figure 16-13: Packed Data (16-bit Packing)In packing, transmit and receive interrupts are generated for the 32-bit packed words, not for each 16-bit word or 8
bit word. The packing feature enables efficient utilization of the system bandwidth.
NOTE: When packing is enabled, the word length must be programmed lesser than the programmed packing. For
example, if 8-bit packing is programmed, SLEN must be less than or equal to 7 and if 16-bit packing is programmed, SLEN must be less than or equal to 15.

SPORT Interrupts and Exceptions
Each half SPORT has an interrupt associated with it. To determine the source of an interrupt, applications should
check the interrupt status register. This section describes the various interrupt sources. In core mode, SPORT is able
to generate data interrupts for receive or transmit operations. Moreover, the SPORT modules generate error conditions which have a separate status bit for each interrupt source.
NOTE: To clear the interrupt signal, the corresponding status bit is written by 1. This clears the value of the status
bit, that is, the corresponding status bit becomes zero.

Error Detection
When the SPORT is configured as a transmitter, the SPORT_STAT_A.DERR or SPORT_STAT_B.DERR bit
provides transmit data buffer underflow status for the data path (it indicates that frame sync signal occurred when
the transmit data buffer was empty). The SPORT transmits data whenever it detects a framing signal.
Similarly, if the SPORT configured as a receiver, the SPORT_STAT_A.DERR or SPORT_STAT_B.DERR bit
provides receive overflow status of receive data buffer. In other words, the SPORT indicates that a channel has received new data when the receive buffer is full, so new data overwrites existing data. The SPORT receives data when
it detects a framing signal.
These error conditions occur in case of external frame sync or when the DIFS (Data independent frame sync) is set.
The SPORT_IEN_x.DERRMSK (SPORT_IEN_A.DERRMSK or SPORT_IEN_B.DERRMSK)(data error interrupt enable) bit can be used to unmask the status interrupt for data errors.
In addition to data underflow and data overflow errors, the status interrupt is also triggered optionally when frame
sync error is detected. The SPORT_IEN_x.FSERRMSK (SPORT_IEN_A.FSERRMSK or
SPORT_IEN_B.FSERRMSK)(frame sync error interrupt enable) bit unmasks the status interrupt for this frame

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceSPORT Interrupts and Exceptions

sync error. This frame sync error is generated due to premature frame sync. For more information about this, refer toPremature Frame Sync Error Detection.
NOTE: A frame sync error is not detected when there is no active data transmit/receive and the frame sync pulse
occurs due to noise in the input signal.

System Transfer Interrupts
When the SPORT is configured to transmit, an interrupt is generated when an attempt is made by the core to write
into a Transmit FIFO which is full. The SPORT_STAT_A.SYSDATERR or SPORT_STAT_B.SYSDATERR
status indicates this Transmit FIFO overflow error.
Similarly, when the SPORT is configured to receive, an interrupt is generated when an attempt is made by the core
to read from an empty Receive FIFO. The field SPORT_STAT_A.SYSDATERR or
SPORT_STAT_B.SYSDATERR status now indicates Receive FIFO underflow error.
NOTE: In DMA mode, SPORT does not produce a DMA request when Transmit FIFO is full or Receive FIFO isempty. Interrupt is not generated for DMA transfers.

Transfer Finish Interrupt (TFI)The Transmit Finish Interrupt feature is used to signal the end of the transmission/reception. This feature can be
enabled by setting SPORT_IEN_A or SPORT_IEN_B bit. When the number of transfers programmed in
SPORT_NUMTRAN_A or SPORT_NUMTRAN_B field are finished, SPORT waits until all the data in the FIFO istransmitted out (including the transmit shift register) or received completely in the receive registers and then generates the Transfer Finish Interrupt. This feature allows the user to determine that all data corresponding to understand that data corresponding to the programmed number of transfers have been transmitted out or received completely by the SPORT.
NOTE: Once the Transfer Finish Interrupt is obtained, the user can either reprogram the number of transfers or
disable the SPORT and re-enabled (if needed). To reprogram the number of transfers, see Number of Transfers.
To re-enable the SPORT, see SPORT Programming Model.

SPORT Programming Model
The following are the SPORT programming guidelines:• Write all the registers of SPORT with the desired values of configuration except the control register.
• After configuration, write the control register (SPORT_CTL_A or SPORT_CTL_B) with desired configuration for the transfer. SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN field must be programmed as 1.
• When the SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN fields are written to 1, normal operation of the
SPORT can start based on the programmed configuration values.
The SPORT registers that need to be written with configuration values are:• Write SPORT_DIV_A or SPORT_DIV_B to program the desired CLKDIV and FSDIV values.
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SPORT Power Management• The SPORT_CNVT_A or SPORT_CNVT_B register must only be written in timer-enable mode.
• EN register is written based on the interrupts. For example, if an interrupt is desired for an underflow/overflow
error, SPORT_IEN_A or SPORT_IEN_B must be set.
• Write SPORT_NUMTRAN_A or SPORT_NUMTRAN_B with the desired number of transfers. This must not
be programmed to zero.

SPORT Power Management
When the chip goes into hibernate mode, the configuration values are retained. The following registers are retained:• SPORT_CTL_A (except DMAEN and SPEN bit fields)• SPORT_DIV_A• SPORT_CNVT_A• SPORT_CTL_B (except DMAEN and SPEN bit fields)• SPORT_DIV_B• SPORT_CNVT_B
NOTE: If any transfer is going on before the chip goes into hibernate, that transfer does not resume after returningfrom hibernate. A fresh start must be made when SPORT comes back from hibernate for the new transfer. Program
the SPORT_NUMTRAN_A or SPORT_NUMTRAN_B register appropriately and then program the
SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN bit to enable the SPORT operation.

ADuCM4050 SPORT Register Descriptions
Serial Port (SPORT) contains the following registers.
Table 16-2: ADuCM4050 SPORT Register List
Name

Description

SPORT_CTL_A

Half SPORT 'A' Control Register

SPORT_CTL_B

Half SPORT 'B' Control Register

SPORT_DIV_A

Half SPORT 'A' Divisor Register

SPORT_DIV_B

Half SPORT 'B' Divisor Register

SPORT_IEN_A

Half SPORT A's Interrupt Enable Register

SPORT_IEN_B

Half SPORT B's Interrupt Enable Register

SPORT_NUMTRAN_A

Half SPORT A Number of Transfers Register

SPORT_NUMTRAN_B

Half SPORT B Number of Transfers Register

SPORT_RX_A

Half SPORT 'A' Rx Buffer Register

16–20

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ADuCM4050 SPORT Register Descriptions

Table 16-2: ADuCM4050 SPORT Register List (Continued)
Name

Description

SPORT_RX_B

Half SPORT 'B' Rx Buffer Register

SPORT_STAT_A

Half SPORT 'A' Status register

SPORT_STAT_B

Half SPORT 'B' Status register

SPORT_CNVT_A

Half SPORT 'A' CNV width

SPORT_CNVT_B

Half SPORT 'B' CNV width register

SPORT_TX_A

Half SPORT 'A' Tx Buffer Register

SPORT_TX_B

Half SPORT 'B' Tx Buffer Register

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ADuCM4050 SPORT Register Descriptions

Half SPORT 'A' Control Register
The SPORT_CTL_A contains transmit and receive control bits for SPORT half 'A', including serial port mode selection
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DIFS (R/W)
Data-Independent Frame Sync

SPEN (R/W)
Serial Port Enable

IFS (R/W)
Internal Frame Sync

FSMUXSEL (R/W)
Frame Sync Multiplexer SelectFSR (R/W)
Frame Sync Required

CKMUXSEL (R/W)
Clock Multiplexer Select

CKRE (R/W)
Clock Rising Edge

LSBF (R/W)
Least-Significant Bit FirstOPMODE (R/W)
Operation Mode

SLEN (R/W)
Serial Word Length

ICLK (R/W)
Internal Clock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DMAEN (R/W)
DMA Enable

LFS (R/W)
Active-Low Frame Sync

SPTRAN (R/W)
Serial Port Transfer Direction

LAFS (R/W)
Late Frame Sync

DATMUXSEL (R/W)
Data Multiplexer Select

PACK (R/W)
Packing Enable

GCLKEN (R/W)
Gated Clock Enable

FSERRMODE (R/W)
Frame Sync Error Operation

Figure 16-14: SPORT_CTL_A Register Diagram
Table 16-3: SPORT_CTL_A Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26 DMAEN(R/W)

DMA Enable.
This bit tells whether the half SPORT would send DMA request signals when theTransmit FIFO needs any data or Receive FIFO wants to send any data to DMA
0 DMA requests are diabled
1 DMA requests are enabled

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ADuCM4050 SPORT Register Descriptions

Table 16-3: SPORT_CTL_A Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
25 SPTRAN(R/W)

Serial Port Transfer Direction.
The SPORT_CTL_A.SPTRAN bit selects the transfer direction (receive or transmit)
for the half SPORT's channels.
0 Receive
1 Transmit

22 DATMUXSEL(R/W)

Data Multiplexer Select.
This bit is set to use the Data multiplexer to route the data from Half SPORT B toHalf SPORT A.
0 Data Multiplexer select disable
1 Data Multiplexer select enable

21 GCLKEN(R/W)

Gated Clock Enable.
The SPORT_CTL_A.GCLKEN bit enables gated clock operation for the half
SPORT.
When SPORT_CTL_A.GCLKEN is enabled, the SPORT clock is active when the
SPORT is transferring data or when the frame sync changes (transitions to active
state).
0 Disable
1 Enable

20 FSERRMODE(R/W)

Frame Sync Error Operation.
The SPORT_CTL_A.FSERRMODE bit decides the way the SPORT responds when aframe sync error occurs.
0 Flag the Frame Sync error and continue normal operation
1 When frame Sync error occurs, discard the receive data

19:18 PACK

Packing Enable.

(R/W)

The SPORT_CTL_A.PACK bit enables the half SPORT to perform 16- to 32-bit or
8- to 32- bit packing on received data and to perform 32- to 16-bit or 32- to 8- bit
unpacking on transmitted data.
0 Disable
1 8-bit packing enable
2 16-bit packing enable
3 Reserved

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ADuCM4050 SPORT Register Descriptions

Table 16-3: SPORT_CTL_A Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
17 LAFS(R/W)

Late Frame Sync.
The SPORT_CTL_A.LAFS bit selects whether the half SPORT generates a lateframe sync (SPORT_AFS during first data bit) or generates an early frame sync signal(SPORT_AFS during serial clock cycle before first data bit).
0 Early frame sync
1 Late frame sync

16 LFS(R/W)

Active-Low Frame Sync.
The SPORT_CTL_A.LFS bit selects whether the half SPORT uses active low or active high frame sync.
0 Active high frame sync
1 Active low frame sync

15 DIFS(R/W)

Data-Independent Frame Sync.
The SPORT_CTL_A.DIFS bit selects whether the half SPORT uses a data-independent or data-dependent frame sync. When using a data-independent frame sync,
the half SPORT generates the sync at the interval selected by
SPORT_DIV_A.FSDIV. When using a data-dependent frame sync, the half SPORT
generates the sync on the selected interval when the transmit buffer is not empty or
when the receive buffer is not full.
0 Data-dependent frame sync
1 Data-independent frame sync

14 IFS(R/W)

Internal Frame Sync.
The SPORT_CTL_A.IFS bit selects whether the half SPORT uses an internal frame
sync or uses an external frame sync.
Note that the externally-generated frame sync does not need to be synchronous withthe processor's system clock.
0 External frame sync
1 Internal frame sync

13 FSR(R/W)

Frame Sync Required.
The SPORT_CTL_A.FSR selects whether or not the half SPORT requires frame
sync for data transfer.
0 No frame sync required
1 Frame sync required

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ADuCM4050 SPORT Register Descriptions

Table 16-3: SPORT_CTL_A Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
12 CKRE(R/W)

Clock Rising Edge.
The SPORT_CTL_A.CKRE selects the rising or falling edge of the SPORT_ACLK
clock for the half SPORT to sample receive data and frame sync.
0 Clock falling edge
1 Clock rising edge

11 OPMODE(R/W)

Operation Mode.
The SPORT_CTL_A.OPMODE bit selects whether the half SPORT operates in DSP
standard mode or in Timer enable mode
0 DSP standard
1 Timer_enable mode

10 ICLK(R/W)

Internal Clock.
The SPORT_CTL_A.ICLK bit selects whether the half SPORT uses an internal orexternal clock.
0 External clock
1 Internal clock

8:4 SLEN(R/W)

Serial Word Length.
The SPORT_CTL_A.SLEN bits selects word length in bits for the half SPORT's datatransfers. Word may be from 4- to 32-bits in length. The formula for selecting theword length in bits is:
SPORT_CTL_A.SLEN = (serial word length in bits) - 1

3 LSBF(R/W)

Least-Significant Bit First.
The SPORT_CTL_A.LSBF bit selects whether the half SPORT transmits or receives
data LSB first or MSB first.
0 MSB first sent/received
1 LSB first sent/received

2 CKMUXSEL(R/W)

Clock Multiplexer Select.
The SPORT_CTL_A.CKMUXSEL bit enables multiplexing of the half SPORT' serial
clock. In this mode, the serial clock of the related half SPORT is used instead of thehalf SPORT's own serial clock. For example, if SPORT_CTL_A.CKMUXSEL is enabled, half SPORT 'A' uses SPORT_BCLK instead of SPORT_ACLK.
0 Disable serial clock multiplexing
1 Enable serial clock multiplexing

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPORT Register Descriptions

Table 16-3: SPORT_CTL_A Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 FSMUXSEL(R/W)

Frame Sync Multiplexer Select.
The SPORT_CTL_A.FSMUXSEL bit enables multiplexing of the half SPORT' frame
sync. In this mode, the frame sync of the related half SPORT is used instead of the half
SPORT's own frame sync. For example, if SPORT_CTL_A.FSMUXSEL is enabled,
half SPORT 'A' uses SPORT_BFS instead of SPORT_AFS.
0 Disable frame sync multiplexing
1 Enable frame sync multiplexing

0 SPEN(R/W)

Serial Port Enable.
The SPORT_CTL_A.SPEN bit enables the half SPORT's data channel. Note: When
this bit is cleared (changes from =1 to =0), the half SPORT automatically flushes thechannel's data buffers and disables the clock and frame sync and the counters inside
SPORT.
0 Disable
1 Enable

16–26

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT 'B' Control Register
The SPORT_CTL_B contains transmit and receive control bits for SPORT half 'B', including serial port mode selection for the channels. The function of some bits in SPORT_CTL_B vary, depending on the SPORT's operating
mode. For more information, see the SPORT operating modes description. If reading reserved bits, the read value isthe last written value to these bits or is the reset value of these bits.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DIFS (R/W)
Data-Independent Frame Sync

SPEN (R/W)
Serial Port Enable

IFS (R/W)
Internal Frame Sync

LSBF (R/W)
Least-Significant Bit FirstFSR (R/W)
Frame Sync Required

SLEN (R/W)
Serial Word Length

CKRE (R/W)
Clock Rising EdgeICLK (R/W)
Internal Clock

OPMODE (R/W)
Operation Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DMAEN (R/W)
DMA Enable

LFS (R/W)
Active-Low Frame Sync

SPTRAN (R/W)
Serial Port Transfer Direction

LAFS (R/W)
Late Frame Sync

GCLKEN (R/W)
Gated Clock Enable

PACK (R/W)
Packing Enable

FSERRMODE (R/W)
Frame Sync Error Operation

Figure 16-15: SPORT_CTL_B Register Diagram
Table 16-4: SPORT_CTL_B Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
26 DMAEN(R/W)

DMA Enable.
This bit tells whether the half SPORT would send DMA request signals when theTransmit FIFO needs any data or Receive FIFO wants to send any data to DMA
0 DMA requests are diabled
1 DMA requests are enabled

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPORT Register Descriptions

Table 16-4: SPORT_CTL_B Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
25 SPTRAN(R/W)

Serial Port Transfer Direction.
The SPORT_CTL_B.SPTRAN bit selects the transfer direction (receive or transmit)
for the half SPORT's channels.
0 Receive
1 Transmit

21 GCLKEN(R/W)

Gated Clock Enable.
The SPORT_CTL_B.GCLKEN bit enables gated clock operation for the half SPORT
when in DSP serial mode.
When SPORT_CTL_B.GCLKEN is enabled, the SPORT clock is active when the
SPORT is transferring data or when the frame sync changes (transitions to active
state).
0 Disable
1 Enable

20 FSERRMODE(R/W)

Frame Sync Error Operation.
The SPORT_CTL_B.FSERRMODE bit decides the way the SPORT responds when aframe sync error occurs.
0 Flag the Frame Sync error and continue normal operation
1 When frame Sync error occurs, discard the receive data

19:18 PACK

Packing Enable.

(R/W)

The SPORT_CTL_B.PACK bit enables the half SPORT to perform 16- to 32-bit or
8- to 32- bit packing on received data and to perform 32- to 16-bit or 32- to 8- bit
unpacking on transmitted data.
0 Disable
1 8-bit packing enable
2 16-bit packing enable
3 Reserved

17 LAFS(R/W)

Late Frame Sync.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0) ,the SPORT_CTL_B.LAFS bit selects whether the half SPORT generates a late frame
sync (SPORT_BFS during first data bit) or generates an early frame sync signal(SPORT_BFS during serial clock cycle before first data bit).
0 Early frame sync
1 Late frame sync

16–28

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Table 16-4: SPORT_CTL_B Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
16 LFS(R/W)

Active-Low Frame Sync.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0), the
SPORT_CTL_B.LFS bit selects whether the half SPORT uses active low or active
high frame sync.
0 Active high frame sync
1 Active low frame sync

15 DIFS(R/W)

Data-Independent Frame Sync.
The SPORT_CTL_B.DIFS bit selects whether the half SPORT uses a data-independent or data-dependent frame sync. When using a data-independent frame sync,
the half SPORT generates the sync at the interval selected by
SPORT_DIV_B.FSDIV. When using a data-dependent frame sync, the half SPORT
generates the sync on the selected interval when the transmit buffer is not empty or
when the receive buffer is not full.
0 Data-dependent frame sync
1 Data-independent frame sync

14 IFS(R/W)

Internal Frame Sync.
The SPORT_CTL_B.IFS bit selects whether the half SPORT uses an internal frame
sync or uses an external frame sync.
Note that the externally-generated frame sync does not need to be synchronous withthe processor's system clock.
0 External frame sync
1 Internal frame sync

13 FSR(R/W)

Frame Sync Required.
The SPORT_CTL_B.FSR selects whether or not the half SPORT requires frame
sync for data transfer.
0 No frame sync required
1 Frame sync required

12 CKRE(R/W)

Clock Rising Edge.
The SPORT_CTL_B.CKRE selects the rising or falling edge of the SPORT_BCLK
clock for the half SPORT to sample receive data and frame sync.
0 Clock falling edge
1 Clock rising edge

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPORT Register Descriptions

Table 16-4: SPORT_CTL_B Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
11 OPMODE(R/W)

Operation Mode.
The SPORT_CTL_B.OPMODE bit selects whether the half SPORT operates in DSP
standard mode or timer enable mode
0 DSP standard mode
1 Timer Enable mode

10 ICLK(R/W)

Internal Clock.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0), the
SPORT_CTL_B.ICLK bit selects whether the half SPORT uses an internal or external clock. For internal clock enabled, the half SPORT generates the SPORT_BCLK
clock signal, and the SPORT_BCLK is an output. The SPORT_DIV_B.CLKDIV
serial clock divisor value determines the clock frequency. For internal clock disabled,
the SPORT_BCLK clock signal is an input, and the serial clock divisor is ignored.
Note that the externally-generated serial clock does not need to be synchronous withthe processor's system clock.
0 External clock
1 Internal clock

8:4 SLEN(R/W)

Serial Word Length.
The SPORT_CTL_B.SLEN bits selects word length in bits for the half SPORT's datatransfers. Word may be from 4- to 32-bits in length. The formula for selecting theword length in bits is:
SPORT_CTL_B.SLEN = (serial word length in bits) - 1

3 LSBF(R/W)

Least-Significant Bit First.
The SPORT_CTL_B.LSBF bit selects whether the half SPORT transmits or receives
data LSB first or MSB first.
0 MSB first sent/received
1 LSB first sent/received

0 SPEN(R/W)

Serial Port Enable.
The SPORT_CTL_B.SPEN bit enables the half SPORT's data channel. Note: When
this bit is cleared (changes from =1 to =0), the half SPORT automatically flushes thechannel's data buffers and disables the clock and frame sync and the counters inside
SPORT.
0 Disable
1 Enable

16–30

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT 'A' Divisor Register
The SPORT_DIV_A contains divisor values that determine frequencies of internally-generated clocks and frame
syncs for half SPORT 'A'.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CLKDIV (R/W)
Clock Divisor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FSDIV (R/W)
Frame Sync Divisor

Figure 16-16: SPORT_DIV_A Register Diagram
Table 16-5: SPORT_DIV_A Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
23:16 FSDIV

Frame Sync Divisor.

(R/W)

The SPORT_DIV_A.FSDIV bits select the number of transmit or receive clock cycles that the half SPORT counts before generating a frame sync pulse. The half
SPORT counts serial clock cycles whether these are from an internally- or an externally-generated serial clock. This field is used to measure the number of serial clock cycles
before generating CNV signal in timer enable mode.

15:0 CLKDIV(R/W)

Clock Divisor.
The SPORT_DIV_A.CLKDIV bits select the divisor that the half SPORT uses tocalculate the serial clock (SPORT_ACLK) from the processor system clock (PCLK).

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

16–31

ADuCM4050 SPORT Register Descriptions

Half SPORT 'B' Divisor Register
The SPORT_DIV_B contains divisor values that determine frequencies of internally-generated clocks and frame
syncs for SPORT half 'B'.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CLKDIV (R/W)
Clock Divisor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FSDIV (R/W)
Frame Sync Divisor

Figure 16-17: SPORT_DIV_B Register Diagram
Table 16-6: SPORT_DIV_B Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
23:16 FSDIV

Frame Sync Divisor.

(R/W)

The SPORT_DIV_B.FSDIV bits select the number of transmit or receive clock cycles that the half SPORT counts before generating a frame sync pulse. The half
SPORT counts serial clock cycles whether these are from an internally- or an externally-generated serial clock. This field is used to measure the number of serial clock cycles
before generating CNV signal in timer enable mode.

15:0 CLKDIV
(R/W)

16–32

Clock Divisor.
The SPORT_DIV_B.CLKDIV bits select the divisor that the half SPORT uses tocalculate the serial clock (SPORT_BCLK) from the processor system clock (PCLK).

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT A's Interrupt Enable Register
This register contains all the fields related to the Enable given for the various interrupts related to errors and data
requests present in the half SPORT A.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SYSDATERR (R/W)
Data Error for System Writes or Reads

TF (R/W)
Transfer Finish Interrupt Enable

DATA (R/W)
Data Request Interrupt to the Core

DERRMSK (R/W)
Data Error (Interrupt) Mask

FSERRMSK (R/W)
Frame Sync Error (Interrupt) Mask
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 16-18: SPORT_IEN_A Register Diagram
Table 16-7: SPORT_IEN_A Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
4 SYSDATERR(R/W)

Data Error for System Writes or Reads.
This field enables the half SPORT to generate the data error interrupt for the systemwrite resulting in TX FIFO overflow or system read resulting in a RX FIFO underflow.
0 Disable System data error interrupt
1 Enable System data error interrupt

3 DATA(R/W)

Data Request Interrupt to the Core.
This bit enables interrupt given to the core for a data write into transmit FIFO fortransmit or data read from the Receive FIFO.
0 Data request interrupt disable
1 Data request interrupt enable

2 FSERRMSK(R/W)

Frame Sync Error (Interrupt) Mask.
The SPORT_IEN_A.FSERRMSK unmasks (enables) the half SPORT to generate theframe sync error interrupt.
0 Mask (disable)
1 Unmask (enable)

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ADuCM4050 SPORT Register Descriptions

Table 16-7: SPORT_IEN_A Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 DERRMSK(R/W)

Data Error (Interrupt) Mask.
The SPORT_IEN_A.DERRMSK unmasks (enables) the half SPORT to generate thedata error interrupt for the data channel.
0 Mask (disable)
1 Unmask (enable)

0 TF
(R/W)

Transfer Finish Interrupt Enable.
The SPORT_IEN_A.TF bit selects when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When enabled (SPORT_IEN_A.TF =1), when the last bit of last word of the programmed
number of transfers is shifted out or received completely, an interrupt is generated.
When disabled (SPORT_IEN_A.TF =0), no interrupt is generated by SPORT.
0 Transfer finish Interrupt is disabled
1 Transfer Finish Interrupt is Enabled

16–34

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ADuCM4050 SPORT Register Descriptions

Half SPORT B's Interrupt Enable Register
This register contains all the fields related to the Enable given for the various interrupts related to errors and data
requests present in the half SPORT B.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SYSDATERR (R/W)
Data Error for System Writes or Reads

TF (R/W)
Transmit Finish Interrupt Enable

DATA (R/W)
Data Request Interrupt to the Core

DERRMSK (R/W)
Data Error (Interrupt) Mask

FSERRMSK (R/W)
Frame Sync Error (Interrupt) Mask
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 16-19: SPORT_IEN_B Register Diagram
Table 16-8: SPORT_IEN_B Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
4 SYSDATERR(R/W)

Data Error for System Writes or Reads.
This field enables the half SPORT to generate the data error interrupt for the systemwrite resulting in TX FIFO overflow or system read resulting in a RX FIFO underflow.
0 Disable System data error interrupt
1 Enable System data error interrupt

3 DATA(R/W)

Data Request Interrupt to the Core.
This bit enables interrupt given to the core for a data write into transmit FIFO fortransmit or data read from the Receive FIFO.
0 Data request interrupt disable
1 Data request interrupt enable

2 FSERRMSK(R/W)

Frame Sync Error (Interrupt) Mask.
The SPORT_IEN_B.FSERRMSK unmasks (enables) the half SPORT to generate theframe sync error interrupt.
0 Mask (disable)
1 Unmask (enable)

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ADuCM4050 SPORT Register Descriptions

Table 16-8: SPORT_IEN_B Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 DERRMSK(R/W)

Data Error (Interrupt) Mask.
The SPORT_IEN_B.DERRMSK unmasks (enables) the half SPORT to generate thedata error interrupt for the data channel.
0 Mask (disable)
1 Unmask (enable)

0 TF
(R/W)

Transmit Finish Interrupt Enable.
The SPORT_IEN_B.TF bit selects when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When enabled (SPORT_IEN_B.TF =1), when the last bit of last word of the programmed
number of transfers is shifted out or received completely, an interrupt is generated.
When disabled (SPORT_IEN_B.TF =0), no interrupt is generated by SPORT
0 Transfer Finish Interrupt is disabled
1 Transfer Finish Interrupt is Enabled

16–36

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT A Number of Transfers Register
This register specifies the number of transfers of words to transfer or receive depending on
SPORT_CTL_A.SPTRAN.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Number of Transfers (Half SPORT A)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 16-20: SPORT_NUMTRAN_A Register Diagram
Table 16-9: SPORT_NUMTRAN_A Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
11:0 VALUE

Number of Transfers (Half SPORT A).

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPORT Register Descriptions

Half SPORT B Number of Transfers Register
This register specifies the number of transfers of the words to transfer or receive depending on
SPORT_CTL_B.SPTRAN.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Number of transfers (Half SPORT B)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 16-21: SPORT_NUMTRAN_B Register Diagram
Table 16-10: SPORT_NUMTRAN_B Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
11:0 VALUE

Number of transfers (Half SPORT B).

(R/W)

16–38

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT 'A' Rx Buffer Register
The SPORT_RX_A register buffers the half SPORT's receive data. This buffer becomes active when the half
SPORT is configured to receive data. After a complete word has been received in receive shifter, it is placed into the
SPORT_RX_A register. This data can be read in core mode (in interrupt-based or polling-based mechanism) or directly DMA'd into processor memory using DMA controller.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R)Receive Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R)Receive Buffer

Figure 16-22: SPORT_RX_A Register Diagram
Table 16-11: SPORT_RX_A Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(R/NW)

Receive Buffer.
The SPORT_RX_A.VALUE bits hold the half SPORT's channel receive data.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

16–39

ADuCM4050 SPORT Register Descriptions

Half SPORT 'B' Rx Buffer Register
The SPORT_RX_B register buffers the half SPORT's channel receive data. This buffer becomes active when thehalf SPORT is configured to receive data. After a complete word has been received in receive shifter, it is placed into
the SPORT_RX_B register. This data can be read in core mode or directly DMA'd into processor memory using
DMA controller.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (R)Receive Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (R)Receive Buffer

Figure 16-23: SPORT_RX_B Register Diagram
Table 16-12: SPORT_RX_B Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(R/NW)

16–40

Receive Buffer.
The SPORT_RX_B.VALUE bits hold the half SPORT's receive data.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT 'A' Status register
This register contains all the status fields in the half SPORT A. Detected errors are frame sync violations or buffer
over/underflow conditions.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DXS (R)
Data Transfer Buffer Status

TFI (R/W1C)
Transmit Finish Interrupt Status

SYSDATERR (R/W1C)
System Data Error Status

DERR (R/W1C)
Data Error Status

DATA (R)
Data Buffer Status

FSERR (R/W1C)
Frame Sync Error Status

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 16-24: SPORT_STAT_A Register Diagram
Table 16-13: SPORT_STAT_A Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
9:8 DXS(R/NW)

Data Transfer Buffer Status.
The SPORT_STAT_A.DXS indicates the status of the half SPORT A's data buffer.
0 Empty
1 Reserved
2 Partially full
3 Full4 SYSDATERR(R/W1C)

System Data Error Status.
This bit indicates the error status for the half SPORT's data buffers during systemtransfer of data. For transmit (SPORT_CTL_A.SPTRAN =1),
SPORT_STAT_A.SYSDATERR indicates transmit overflow status. For receive(SPORT_CTL_A.SPTRAN =0), SPORT_STAT_A.SYSDATERR indicates receive
underflow status.
0 No Error
1 System Transfer overflow for TXFIFO or System Transfer underflow for RXFIFO

3 DATA(R/NW)

Data Buffer Status.
This field indicates only the status of the data buffers in Half SPORT A.
0 Transmit FIFO is full or receive FIFO is empty
1 Transmit FIFO is not full or receive FIFO is not empty

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ADuCM4050 SPORT Register Descriptions

Table 16-13: SPORT_STAT_A Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 FSERR(R/W1C)

Frame Sync Error Status.
The SPORT_STAT_A.FSERR bit indicates that the half SPORT has detected aframe sync when the bit count (bits remaining in the frame) is non-zero or it has seen
frame sync active for less than the word length in case of late frame sync.
0 No error
1 Frame Sync Error occurred

1 DERR(R/W1C)

Data Error Status.
The SPORT_STAT_A.DERR bit indicates the error status for the half SPORT's data
buffers. During transmit (SPORT_CTL_A.SPTRAN =1), SPORT_STAT_A.DERR
indicates transmit underflow status. During receive (SPORT_CTL_A.SPTRAN =0),
SPORT_STAT_A.DERR indicates receive overflow status.
0 No error
1 Error (transmit underflow or receive overflow)

0 TFI(R/W1C)

Transmit Finish Interrupt Status.
The SPORT_STAT_A.TFI bit shows when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When it is1, the last bit of last word of the programmed number of transfers is shifted out or
received completely. When 0, the total number of transfers are not finished.
0 Last bit is not transmitted/received
1 Last bit Transmitted/received

16–42

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT 'B' Status register
This register contains all the status fields present in the half SPORT B. Detected errors are frame sync violations or
buffer over/underflow conditions.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DXS (R)
Data Transfer Buffer Status

TFI (R/W1C)
Transmit Finish Interrupt Status

SYSDATERR (R/W1C)
System Data Error Status

DERR (R/W1C)
Data Error Status

DATA (R/W1C)
Data Buffer Status

FSERR (R/W1C)
Frame Sync Error Status

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 16-25: SPORT_STAT_B Register Diagram
Table 16-14: SPORT_STAT_B Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
9:8 DXS(R/NW)

Data Transfer Buffer Status.
The SPORT_STAT_B.DXS indicates the status of the half SPORT B's data buffer.
0 Empty
1 Reserved
2 Partially full
3 Full4 SYSDATERR(R/W1C)

System Data Error Status.
This bit indicates the error status for the half SPORT's data buffers during systemtransfer of data. For transmit (SPORT_CTL_A.SPTRAN =1),
SPORT_STAT_B.SYSDATERR indicates transmit overflow status. For receive(SPORT_CTL_A.SPTRAN =0), SPORT_STAT_B.SYSDATERR indicates receive
underflow status.
0 No Error
1 System Transfer overflow for TXFIFO or System Transfer underflow for RXFIFO

3 DATA(R/W1C)

Data Buffer Status.
This field indicates only the status of the data buffers in Half SPORT B.
0 Transmit FIFO is full or receive FIFO is empty
1 Transmit FIFO is not full or receive FIFO is not empty

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPORT Register Descriptions

Table 16-14: SPORT_STAT_B Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 FSERR(R/W1C)

Frame Sync Error Status.
The SPORT_STAT_B.FSERR bit indicates that the half SPORT has detected aframe sync when the bit count (bits remaining in the frame) is non-zero or it has seen
frame sync active for less than the word length in case of late frame sync.
0 No error
1 Error (non-zero bit count at frame sync)

1 DERR(R/W1C)

Data Error Status.
The SPORT_STAT_B.DERR bit indicates the error status for the half SPORT B's
data buffers. During transmit (SPORT_CTL_B.SPTRAN =1),
SPORT_STAT_B.DERR indicates transmit underflow status. During receive(SPORT_CTL_B.SPTRAN =0), SPORT_STAT_B.DERR indicates receive overflow
status.
0 No error
1 Error (transmit underflow or receive overflow)

0 TFI(R/W1C)

Transmit Finish Interrupt Status.
The SPORT_STAT_B.TFI bit shows when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When it is1, the last bit of last word of the programmed number of transfers is shifted out or
received completely. When 0, the total number of transfers are not finished.
0 Last bit is not transmitted/received
1 Last bit Transmitted/received

16–44

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT 'A' CNV widthThis register contains the settings related to the CNV signal for Half SPORT A
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

POL (R/W)
Polarity of the CNV Signal

WID (R/W)
CNV Signal Width: Half SPORT A

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CNVT2FS (R/W)
CNV to FS Duration: Half SPORT A

Figure 16-26: SPORT_CNVT_A Register Diagram
Table 16-15: SPORT_CNVT_A Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
23:16 CNVT2FS

CNV to FS Duration: Half SPORT A.

(R/W)

This field contains the value of the number of clocks which would be programmed
corresponding to the desired time duration from assertion of CNV signal to Frame
sync signal for Half SPORT A

8 POL
(R/W)

Polarity of the CNV Signal.
This bit decides the polarity of the CNV signal
0 Active High Polarity
1 Active low Polarity

3:0 WID(R/W)

CNV Signal Width: Half SPORT A.
This field contains the value of the number of serial clocks for which CNV signal
should be active for Half SPORT A

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPORT Register Descriptions

Half SPORT 'B' CNV width register
This register contains the settings related to the CNV signal for Half SPORT B
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

POL (R/W)
Polarity of the CNV Signal

WID (R/W)
CNV Signal Width: Half SPORT B

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CNVT2FS (R/W)
CNV to FS Duration: Half SPORT B

Figure 16-27: SPORT_CNVT_B Register Diagram
Table 16-16: SPORT_CNVT_B Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
23:16 CNVT2FS

CNV to FS Duration: Half SPORT B.

(R/W)

This field contains the value of the number of clocks which would be programmed
corresponding to the desired time duration from assertion of CNV signal to Frame
sync signal for Half SPORT B

8 POL
(R/W)

Polarity of the CNV Signal.
This bit decides the polarity of the CNV signal
0 Active High Polarity
1 Active low Polarity

3:0 WID
(R/W)

16–46

CNV Signal Width: Half SPORT B.
This field contains the value of the number of clocks which would be programmed
corresponding to the desired width of the CNV signal for Half SPORT B

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 SPORT Register Descriptions

Half SPORT 'A' Tx Buffer Register
The SPORT_TX_A register buffers the half SPORT's transmit data. This register must be loaded with the data to
be transmitted if the half SPORT is configured to transmit. Either a program running on the processor core may
load the data into the buffer (word-by-word process) or the DMA controller may automatically load the data into
the buffer (DMA process).
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Transmit Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Transmit Buffer

Figure 16-28: SPORT_TX_A Register Diagram
Table 16-17: SPORT_TX_A Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(RX/W)

Transmit Buffer.
The SPORT_TX_A.VALUE bits hold the half SPORT's channel transmit data.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 SPORT Register Descriptions

Half SPORT 'B' Tx Buffer Register
The SPORT_TX_B register buffers the half SPORT's channel transmit data. This register must be loaded with thedata to be transmitted. Either a program running on the processor core may load the data into the buffer (word-byword process) or the DMA controller may automatically load the data into the buffer (DMA process).
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[15:0] (W)Transmit Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE[31:16] (W)Transmit Buffer

Figure 16-29: SPORT_TX_B Register Diagram
Table 16-18: SPORT_TX_B Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
31:0 VALUE(RX/W)

16–48

Transmit Buffer.
The SPORT_TX_B.VALUE bits hold the half SPORT's transmit data.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceUniversal Asynchronous Receiver/Transmitter (UART)

17 Universal Asynchronous Receiver/Transmitter (UART)The UART peripheral is a serial full duplex universal asynchronous receiver/ transmitter, compatible with the industry-standard 16450/16550. The serial communication follows an asynchronous protocol supporting various word
lengths, stop bits, and parity generation options. The ADuCM4050 MCU has two UART cores.

UART Features• Serial full duplex universal asynchronous receiver/transmitter.
• Compatible with the industry-standard 16450/16550.
• Contains interrupt handling hardware for number of unique events, such as data buffer full/empty, transfer error detection and break detection.
• Fractional divider that facilitates high accuracy baud rate generation.
• Word lengths from 7 to 12 bits.
• Two dedicated DMA channels for Receive and Transmit.
• 5 to 8 data bits.
• 1, 2 or 1 and 1/2 stop bits.
• None, or even or odd parity.
• Programmable over sample rate by 4, 8, 16, 32.

UART Functional Description
The UART peripheral supports industry standard asynchronous serial communication and can transfer data throughthe transmit and receive pins. It supports the word lengths from 7 to 12 bits. Transmit operation is initiated bywriting to the transmit holding register (UART_TX). Receive operation uses the same data format as the transmit
configuration, except for the number of stop bits, which is always one.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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UART Functional Description

UART Block Diagram
The UART block diagram is shown below.
PCLK domain

16550 UART CORE

RXFULL

Clock
GatingRX FIFO

PCLK

RX
PCLKg

RX LOGIC

RX FIFO
timeoutmonitorFractional
Baud Rate
Generate

Fractional
Baud Rate
Generate

Modulation

TX

REG
I/F

APB Slave IF

TX LOGIC

TX FIFOMODEM
CTLInterrupt
Encoding

Figure 17-1: UART Block Diagram

UART Operations
Serial Communications
The asynchronous serial communication protocol supports the following options:• 5 to 8 data bits
• 1, 2 or 1 and 1/2 stop bits
• None, or even or odd parity• Programmable over sample rate by 4, 8, 16, 32
17–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

UART Operations• Baud rate = PCLK / ((M + N/2048) × 2OSR+2 × DIV)
where,OSR (UART_LCR2.OSR) = 0 to 3
DIV (UART_DIV) = 1 to 65535
M (UART_FBR.DIVM) = 1 to 3
N (UART_FBR.DIVN) = 0 to 2047
All data words require a start bit and at least one stop bit. This creates a range from 7 bits to 12 bits for each word.
Transmit operation is initiated by writing to the transmit holding register (UART_TX). After a synchronization delay, the data is moved to the transmit shift register where it will be shifted out at a baud (bit) rate equal to PCLK /((M + N/2048) × 2OSR+2 × DIV) with start, stop, and parity bits appended as required. All data words begin with alow going start bit. The transfer of the transmit holding register to the transmit shift register causes the transmit
register empty status bit (UART_LSR.THRE) to be set.
Receive operation uses the same data format as the transmit configuration, except for the number of stop bits, whichis always one. After detecting the start bit, the received word is shifted to the receive shift register. After the appropriate number of bits (including stop bits) are received, the receive shift register is transferred to the receive buffer register, after the appropriate synchronization delay, and the receive buffer register full status flag (UART_IIR.STAT) is
updated.
A sampling clock equal to 2OSR+2 times the baud rate is used to sample the data as close to the midpoint of the bit
as possible. A receive filter is also present that removes spurious pulses less than the sampling clock period.
NOTE: Data is transmitted and received least significant bit first, that is, transmit shift register, bit 0.
Baud Rate Generator
The baud rate generator has a fractional divider to generate very accurate baud rates. The baud rate can be calculated
as follows.
To bypass the fractional divider, set UART_FBR.FBEN = 0.
This results in a baud rate = PCLK / (2OSR+2 × DIV).
To estimate the UART_FBR.DIVN and UART_FBR.DIVM values, the fractional baud rate generator fine tunes
the baud rate if the integer UART_DIV gives an unreasonable error to the rate.
NOTE: Setting UART_DIV to 0 disables the UART logic.
The following tables show example baud rates assuming a 52 MHz, 26 MHz and 16 MHz input clock.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–3

UART Operations

Table 17-1: Baud Rate Examples Based on 52 MHz PCLK
Baud Rate

OSR

DIV

DIVM

DIVN

ActualError

1,000,000

3

1

1

1280

1000000

0.0%

1,500,000

3

1

1

171

1499774-0.002%3,000,000

2

1

1

171

2999549-0.015%3,500,000

1

1

1

1755

35003940.0011%

Table 17-2: Baud Rate Examples Based on 26 MHz PCLK
Baud Rate

OSR

DIV

DIVM

DIVN

Actual

Error

9600

3

28

3

46

9600.74

0.0077%

19200

3

14

3

46

19201.48

0.0077%

38400

3

7

3

46

38402.95

0.0077%

57600

3

14

1

15

57613.74

0.0024%

115,200

3

3

2

719

115195.6-0.004%

230,400

3

3

1

359

2304390.0017%

460,800

3

1

1

1563

4608140.003%

921,600

2

1

1

1563

9216280.003%

1,000,000

2

1

1

1280

1000000

0.0%

1,500,000

2

1

1

171

1499774-0.002%

Table 17-3: Baud Rate Examples Based on a 16 MHz PCLK
Baud Rates

OSR

DIV

DIVM

DIVN

Actual% Error

9600

3

17

3

131

9599.25-0.0078%

19200

3

8

3

523

19199.04-0.0050%

38400

3

4

3

523

38398.08-0.0050%

57600

3

8

1

174

57605.76

0.0100%115,200

3

2

2

348

115211.5

0.0100%230,400

3

2

1

174

2304230.0100%460,800

3

1

1

174

460846.1

0.0100%921,600

2

1

1

174

921692.2

0.0100%1,000,000

2

1

1

0

1000000

0.0000%1,500,000

1

1

1

683

1499816.9-0.012%

17–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

UART Operating Modes

UART Operating Modes
The UART used by the ADuCM4050 MCU supports the following modes.

IO ModeIn this mode, the software moves the data to and from the UART. This is accomplished by interrupt service routinesthat respond to the transmit and receive interrupts by either reading or writing data as appropriate. In this mode, thesoftware must respond within a certain time to prevent overrun errors in the receive channel.
The IO mode also requires polling the status flags to determine when it is ok to move data.
This mode is core intensive and used only if the system can tolerate the overhead. Interrupts can be controlled using
the UART interrupt enable register (UART_IEN).
Writing to the transmit holding register when it is not empty, or reading from the receive buffer register when it is
not full produces an incorrect result. In the former case, the transmit holding register is overwritten by the new word
and the previous word is never transmitted, and in the latter case, the previously received word is read again. Theseerrors must be avoided in software by correctly using either interrupts or status register polling. These errors are notdetected in the hardware.

DMA ModeIn this mode, user code does not move data to and from the UART. The DMA request signals to the DMA blockare generated indicating that the UART is ready to transmit or receive data. These DMA request signals can be controlled in the UART_IEN register.

FIFO Mode (16550)
The 16-byte deep TX FIFO and RX FIFOs are implemented so that the UART is compatible with the industrystandard 16550.
By default, the FIFOs are disabled. They are enabled by setting the UART_FCR.FIFOEN bit. When enabled, theinternal FIFOs are activated, allowing 16 bytes (and 3 bits of error data per byte in the RX FIFO) to be stored inboth receive and transmit modes. This minimizes the system overhead and maximizes the system efficiency.
The interrupt and/or DMA trigger level of the RX FIFO are programmed by the UART_FCR.RFTRIG bit. Two
DMA modes are available. The required DMA mode can be programmed using the UART_FCR.FDMAMD bit.
DMA Mode 1 only works (in burst mode) when FIFO is enabled.
NOTE: Refer to the UART_FCR register for further information.

UART Interrupts
The UART peripheral has one output signal to the core interrupt controller representing all Rx and Tx interrupts.
The UART interrupt identification register (UART_IIR) must be read by the software to determine the cause of
the interrupt.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–5

Auto Baud Rate Detection (ABD)

In the IO mode, interrupts may be generated for the following cases:• Receive buffer register full
• Receive overrun error• Receive parity error• Receive framing error• Receive FIFO timeout if FIFO (16550) is enabled• Break interrupt (SIN held low)
• Transmit holding register empty

Auto Baud Rate Detection (ABD)The Auto baud detection block is used to match the baud rates of two UART devices automatically without preassumptions.
The UART_ACR.ABE bit enables the receiver to work in the Auto baud detection mode. A 20-bit counter logic
counts the number of cycles of PCLK between the programmed start and end edges (rising or falling). This 20-bit
counter is stored in the UART_ASRH.CNT (8 higher bits) and UART_ASRL.CNT (12 lower bits).

Figure 17-2: Auto Baud Rate Example

An interrupt is generated once the expected edges are reached. If the counter overflows while the timeout interrupt
is enabled (the UART_ACR.TOIEN set), the block generates a timeout interrupt due to long break(UART_ASRL.BRKTO), no valid start edge (UART_ASRL.NSETO), or no valid ending edge
(UART_ASRL.NEETO). Once the CNT is read back, the software must be aware of the effective number of bits
between active starting and ending edges (defined as CountedBits) to obtain the baud rate. CountedBits depends onthe character and the selected starting and ending edges used for Auto baud detection.
Auto baud must be disabled to clear the internal counter and re-enabled for another run (if required).
The following figures show how to configure the different parameters depending on the character and edges used.
For example, there are three rising and falling edges, if the data byte being received is 0x0D (0b'00001101, carriage
return), in 8-bit mode without parity bit, LSB first. To count from first to last edge of the carriage return, the
UART_ACR.SEC field must be written to 1 (second edge from the start bit), and the UART_ACR.EEC field must
17–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceAuto Baud Rate Detection (ABD)be written to 3 to count until the edge on the stop bit (fourth edge from the starting edge). In this case, the CountedBits between the starting edge and ending edge is 8 bits.
SEC = 1
Edge count

1

Data

START

2

EEC = 3
1

2

3

4
STOP

1

0

1

1

0

0

0

0 = 0x0D Carriage return

D0

D1

D2

D3

D4

D5

D6

D7

CountedBits = 8

Figure 17-3: Auto Baud Configuration Example

It is possible to count from the start bit to the stop bit. In this case, the UART_ACR.SEC field must be written to 0
(first edge from the start bit), the UART_ACR.EEC field to 4 (fifth edge from the start edge), and CountedBits
must be 9.
SEC = 0Edge count

1

Data

START

EEC = 4
1

2

3

4

5
STOP

1

0

1

1

0

0

0

0 = 0x0D Carriage return

D0

D1

D2

D3

D4

D5

D6

D7

CountedBits = 9

Figure 17-4: Auto Baud Configuration Example

Any other character can be used for auto baud rate detection. For example, the backspace 0x08 (0b'00010000), tomeasure between the first edge on the data and stop bit, the UART_ACR.SEC field is set to 1, the
UART_ACR.EEC field is set to 1, and CountedBits must be 5.
EEC = 1

SEC = 1
Edge count

1

Data

START

2

1

2
STOP

0

0

0

1

0

0

0

0 = 0x08 Backspace

D0

D1

D2

D3

D4

D5

D6

D7

CountedBits = 5

Figure 17-5: Auto Baud Configuration Example

The 20-bit counter uses the following equation:
CNT[19:0] = CountedBits × 2OSR+2 × UART_DIV × (UART_FBR.DIVM + UART_FBR.DIVN ÷ 2048)
Based on the UART baud rate configuration, the Auto Baud Detection result can be calculated in the following way:
NOTE: To reduce truncation error, the UART_FBR.DIVM field is set to 1.
if CNT < 8 × CountedBits, OSR = 0, UART_FBR.DIVN = 512 × CNT ÷ CountedBits - 2048,
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–7

RS485 Half-Duplex Modeelse if CNT < 16 × CountedBits, OSR = 1, UART_DIV = 1, UART_FBR.DIVN = 256 ×CNT ÷ CountedBits 2048,
else if CNT < 32 × CountedBits, OSR = 2, UART_DIV = 1, UART_FBR.DIVN = 128 ×CNT ÷ CountedBits 2048,
else if CNT > = 32 × CountedBits, OSR = 3,
if CNT exactly divided by (32 × CountedBits), UART_DIV = CNT ÷ 32 ÷ CountedBits,
else UART_DIV = 2log2(CNT ÷ 32 ÷ CountedBits) //The UART_DIV field is set to nearest power of 2 to reduce truncation error.
UART_FBR.DIVN = 64 × CNT ÷ UART_DIV ÷ CountedBits - 2048

RS485 Half-Duplex Mode
UART peripheral offers the ability to communicate to a RS485 transceiver at the expense of three GPIOs, two for
UART_TX (SOUT) and UART_RX (SIN), and one for UART_SOUT_EN. The UART_SOUT_EN controls thetransmit/receive direction of the RS485 transceiver. Whenever UART_SOUT_EN is asserted, the transceiver’s
transmit driver can be enabled (active high control) and receive driver can be disabled (active low control) simultaneously thereby facilitating data transmission to the RS485 bus. Whenever UART_SOUT_EN is deasserted, thetransceiver’s receive driver can be enabled and transmit driver can be disabled simultaneously. Set the
UART_RSC_DISTX bit to hold off Tx when receiving and set the UART_RSC_DISRX bit to disable Rx whentransmitting. An example interface diagram for RS485 Half Duplex Mode is shown below..

Figure 17-6: UART with RS485 Transceiver

17–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceReceive Line Inversion

Receive Line Inversion
For specific applications such as UART communication through optical link, the receive line may work at the opposite level (that is, idling at low level). The UART_CTL.RXINV register can invert the receive line for this purpose.
NOTE: Do not use Receive line inversion with RS485 applications.
Configure the UART_CTL.RXINV register before configuring the UART and enabling Auto Baud.

Clock Gating
The clock driving the UART logic is automatically gated off when idle, and not accessed. This automatic clock gating can be disabled by the UART_CTL.FORCECLKON field.

UART and Power-Down Modes
Complete the on-going UART transfers before powering down the chip into the Hibernate mode. Else, disable the
UART by clearing the UART_DIV register before going into hibernate.
NOTE: If hibernate mode is selected while a UART transfer is ongoing, the transfer does not continue on returningfrom hibernate. All the intermediate data, states, status logic in the UART are cleared. However, the TX pads
(SOUT and SOUT_EN, if pin mux is selected) may remain active in hibernate mode while transmitting.
After hibernate, the UART can be enabled by setting the UART_DIV register (if previously cleared). If DMA modeis needed, UART_IEN [5:4] must be configured.
For a clean wake-up,• Prior to hibernate: Disable the UART block by clearing the UART_DIV register.
Or• After waking from hibernate: Before any UART transaction, apply a break which is at least one frame period
longer than the system wake-up time (typically, 10 μs). This ensures that the UART identifies the transaction
start condition.
The wake-up time depends on the clock sources and memory used for instruction code.
The following registers are retained in the hibernate mode. Other registers and internal logic are cleared to hardware
default value.
• UART_IEN.ELSI, UART_IEN.ERBFI• UART_LCR.BRK, UART_LCR.SP, UART_LCR.EPS, UART_LCR.PEN, UART_LCR.STOP,UART_LCR.WLS• UART_FCR.RFTRIG, UART_FCR.FDMAMD, UART_FCR.FIFOEN• UART_FBR.FBEN, UART_FBR.DIVM, UART_FBR.DIVN
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–9

ADuCM4050 UART Register Descriptions• UART_DIV.DIV• UART_LCR2.OSR• UART_CTL.RXINV, UART_CTL.FORCECLK• UART_RSC.DISTX, UART_RSC.DISRX, UART_RSC.OENSP, UART_RSC.OENP

ADuCM4050 UART Register Descriptions
Universal Asynchronous Receiver/Transmitter (UART) contains the following registers.
Table 17-4: ADuCM4050 UART Register List
Name

Description

UART_ACR

Auto Baud Control

UART_ASRH

Auto Baud Status (High)UART_ASRL

Auto Baud Status (Low)

UART_CTL

UART Control Register

UART_DIV

Baud Rate Divider

UART_FBR

Fractional Baud Rate

UART_FCRFIFO Control

UART_IEN

Interrupt Enable

UART_IIR

Interrupt ID

UART_LCR

Line Control

UART_LCR2

Second Line Control

UART_LSR

Line Status

UART_RFC

RX FIFO Byte Count

UART_RSCRS485 Half-duplex Control

UART_RX

Receive Buffer Register

UART_SCR

Scratch Buffer

UART_TFC

TX FIFO Byte Count

UART_TX

Transmit Holding Register

17–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

Auto Baud Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EEC (R/W)
Ending Edge CountABE (R/W)
Auto Baud Enable

SEC (R/W)
Starting Edge CountDNIEN (R/W)
Enable Done Interrupt

TOIEN (R/W)
Enable Time-out Interrupt

Figure 17-7: UART_ACR Register Diagram
Table 17-5: UART_ACR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
11:8 EEC(R/W)

Ending Edge Count.
Counted from the start edge count configured by the UART_ACR.SEC bitfield.
0 First edge Corresponds to the first edge after the startingedge (configured in UART_ACR.SEC).
1 Second edge
2 Third edge
3 Fourth edge
4 Fifth edge
5 Sixth edge
6 Seventh edge
7 Eighth edge
8 Ninth edge

6:4 SEC(R/W)

Starting Edge Count.
Counted from the falling edge of START bit.
0 First edge Corresponds to the falling edge of the STARTbit.
1 Second edge
2 Third edge
3 Fourth edge
4 Fifth edge
5 Sixth edge

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–11

ADuCM4050 UART Register Descriptions

Table 17-5: UART_ACR Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
6 Seventh edge
7 Eighth edge
2 TOIEN

Enable Time-out Interrupt.

(R/W)

0 Disable timeout interrupt
1 Enable timeout interrupt

1 DNIEN

Enable Done Interrupt.

(R/W)

0 Disable done interrupt
1 Enable done interrupt

0 ABE
(R/W)

Auto Baud Enable.
0 Disable auto baudrate
1 Enable auto baudrate

17–12

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

Auto Baud Status (High)15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CNT[19:12] (R)Auto Baud Counter Value

Figure 17-8: UART_ASRH Register Diagram
Table 17-6: UART_ASRH Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 CNT

Auto Baud Counter Value.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–13

ADuCM4050 UART Register Descriptions

Auto Baud Status (Low)
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CNT[11:0] (R)Auto Baud Counter ValueDONE (RC)Auto Baud Done Successfully

NEETO (RC)Timed Out Due to No Valid Ending
Edge Found

BRKTO (RC)Timed Out Due to Long Time Break
Condition

NSETO (RC)Timed Out Due to No Valid Start Edge
Found

Figure 17-9: UART_ASRL Register Diagram
Table 17-7: UART_ASRL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:4 CNT

Auto Baud Counter Value.

(R/NW)
3 NEETO

Timed Out Due to No Valid Ending Edge Found.

(RC/NW)
2 NSETO

Timed Out Due to No Valid Start Edge Found.

(RC/NW)
1 BRKTO

Timed Out Due to Long Time Break Condition.

(RC/NW)
0 DONE

Auto Baud Done Successfully.

(RC/NW)

17–14

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

UART Control Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

REV (R)UART Revision ID

FORCECLK (R/W)
Force UCLK on

RXINV (R/W)
Invert Receiver Line

Figure 17-10: UART_CTL Register Diagram
Table 17-8: UART_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:8 REVUART Revision ID.

(R/NW)
4 RXINV

Invert Receiver Line.

(R/W)

0 Don't invert receiver line (idling high).
1 Invert receiver line (idling low).

1 FORCECLK(R/W)

Force UCLK on.
0 UCLK automatically gated
1 UCLK always working

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–15

ADuCM4050 UART Register Descriptions

Baud Rate Divider
Internal UART baud generation counters are restarted whenever UART_DIV register accessed by writing, regardlesssame or different value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DIV (R/W)
Baud Rate Divider

Figure 17-11: UART_DIV Register Diagram
Table 17-9: UART_DIV Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 DIV
(R/W)

17–16

Baud Rate Divider.
The UART_DIV register should not be 0, which is not specified. Allowed range is 1 to65535.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

Fractional Baud Rate
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FBEN (R/W)
Fractional Baud Rate Generator Enable

DIVN (R/W)
Fractional Baud Rate N Divide Bits 0
to 2047

DIVM (R/W)
Fractional Baud Rate M Divide Bits
1 to 3Figure 17-12: UART_FBR Register Diagram
Table 17-10: UART_FBR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 FBEN

Fractional Baud Rate Generator Enable.

(R/W)

The generating of fractional baud rate can be described by the following formula andthe final baud rate of UART operation is calculated as Baudrate = (UCLK / (2 *(UART_FBR.DIVM + UART_FBR.DIVN/2048) * 16 * UART_DIV) )12:11 DIVM

Fractional Baud Rate M Divide Bits 1 to 3.

(R/W)

This bit should not be 0 when Fractional Baud Rate enabled.

10:0 DIVN

Fractional Baud Rate N Divide Bits 0 to 2047.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–17ADuCM4050 UART Register Descriptions

FIFO Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RFTRIG (R/W)
Rx FIFO Trigger Level

FIFOEN (R/W)
FIFO Enable as to Work in 16550 Mode

FDMAMD (R/W)
FIFO DMA Mode

RFCLR (W)
Clear Rx FIFOTFCLR (W)
Clear Tx FIFO

Figure 17-13: UART_FCR Register Diagram
Table 17-11: UART_FCR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:6 RFTRIG(R/W)

Rx FIFO Trigger Level.
Writable only if FIFOEN=1.
0 1 byte to trigger RX interrupt
1 4 byte to trigger RX interrupt
2 8 byte to trigger RX interrupt
3 14 byte to trigger RX interrupt

3 FDMAMD(R/W)

FIFO DMA Mode.
Writable only if FIFOEN=1.
0 In DMA mode 0, RX DMA request will be asserted
whenever there's data in RBR or RX FIFO and de-assert
whenever RBR or RX FIFO is empty; TX DMA request
will be asserted whenever THR or TX FIFO is empty
and de-assert whenever data written to.
1 in DMA mode 1, RX DMA request will be asserted
whenever RX FIFO trig level or time out reached andde-assert thereafter when RX FIFO is empty; TX DMA
request will be asserted whenever TX FIFO is empty
and de-assert thereafter when TX FIFO is completely
filled up full.

2 TFCLR

Clear Tx FIFO.

(RX/W)
1 RFCLR

Clear Rx FIFO.

(RX/W)

17–18

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

Table 17-11: UART_FCR Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 FIFOENFIFO Enable as to Work in 16550 Mode.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–19

ADuCM4050 UART Register Descriptions

Interrupt Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EDMAR (R/W)
DMA Requests in Receive Mode

ERBFI (R/W)
Receive Buffer Full Interrupt

EDMAT (R/W)
DMA Requests in Transmit ModeETBEI (R/W)
Transmit Buffer Empty Interrupt

ELSI (R/W)
Line Status Interrupt

Figure 17-14: UART_IEN Register Diagram
Table 17-12: UART_IEN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5 EDMARDMA Requests in Receive Mode.

(R/W)

0 DMA requests disabled
1 DMA requests enabled

4 EDMATDMA Requests in Transmit Mode.

(R/W)

0 DMA requests are disabled
1 DMA requests are enabled

2 ELSI(R/W)

Line Status Interrupt.
0 Interrupt disabled
1 Interrupt enabled

1 ETBEI(R/W)

Transmit Buffer Empty Interrupt.
0 Interrupt disabled
1 Interrupt enabled

0 ERBFI(R/W)

Receive Buffer Full Interrupt.
0 Interrupt disabled
1 Interrupt enabled

17–20

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

Interrupt ID
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

FEND (R)FIFO Enabled

NIRQ (RS)Interrupt Flag

STAT (RC)Interrupt Status

Figure 17-15: UART_IIR Register Diagram
Table 17-13: UART_IIR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:6 FEND

FIFO Enabled.

(R/NW)

0 FIFO not enabled, 16450 mode
3 FIFO enabled, 16550 mode

3:1 STAT(RC/NW)

Interrupt Status.
When UART_IIR.NIRQ is low (active-low), this indicates an interrupt and the
UART_IIR.STAT bit decoding below is used.
0 Modem status interrupt (Read MSR register to clear)
1 Transmit buffer empty interrupt (Write to Tx register orread IIR register to clear)
2 Receive buffer full interrupt (Read Rx register to clear)
3 Receive line status interrupt (Read LSR register to clear)
6 Receive FIFO time-out interrupt (Read Rx register toclear)

0 NIRQInterrupt Flag.

(RS/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–21

ADuCM4050 UART Register Descriptions

Line Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BRK (R/W)
Set Break

WLS (R/W)
Word Length SelectSP (R/W)
Stick Parity

STOP (R/W)
Stop Bit

EPS (R/W)
Parity SelectPEN (R/W)
Parity Enable

Figure 17-16: UART_LCR Register Diagram
Table 17-14: UART_LCR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
6 BRK

Set Break.

(R/W)

0 Normal TxD operation
1 Force TxD to 0

5 SP
(R/W)

Stick Parity.
Used to force parity to defined values. When set, the parity will be based on the following bit settings : UART_LCR.EPS = 1 and UART_LCR.PEN = 1, parity will beforced to 0. UART_LCR.EPS = 0 and UART_LCR.PEN = 1, parity will be forced to
1. UART_LCR.EPS = X and UART_LCR.PEN = 0, no parity will be transmitted
0 Parity will not be forced based on Parity Select and Parity Enable bits.
1 Parity forced based on Parity Select and Parity Enable
bits.

4 EPS
(R/W)

Parity Select.
This bit only has meaning if parity is enabled (UART_LCR.PEN set).
0 Odd parity will be transmitted and checked.
1 Even parity will be transmitted and checked.

3 PEN
(R/W)

Parity Enable.
Used to control of the parity bit transmitted and checked. The value transmitted andthe value checked will be based on the settings of UART_LCR.EPS andUART_LCR.SP.
0 Parity will not be transmitted or checked.
1 Parity will be transmitted and checked.

17–22

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

Table 17-14: UART_LCR Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 STOP(R/W)

Stop Bit.
Used to control the number of stop bits transmitted. In all cases only the first stop bit
will be evaluated on data received.
0 Send 1 stop bit regardless of the Word Length Select bit
1 Send a number of stop bits based on the word length asfollows: WLS = 00, 1.5 stop bits transmitted (5-bit
word length) WLS = 01 or 10 or 11, 2 stop bits transmitted (6 or 7 or 8-bit word length)

1:0 WLS(R/W)

Word Length Select.
Selects the number of bits per transmission.
0 5 bits
1 6 bits
2 7 bits
3 8 bits

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–23

ADuCM4050 UART Register Descriptions

Second Line Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

OSR (R/W)
Over Sample Rate

Figure 17-17: UART_LCR2 Register Diagram
Table 17-15: UART_LCR2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1:0 OSR(R/W)

Over Sample Rate.
0 Over sample by 4.
1 Over sample by 8.
2 Over sample by 16.
3 Over sample by 32.

17–24

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

Line Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

FIFOERR (RC)Rx FIFO Parity Error/Frame Error/Break
Indication

DR (RC)
Data ReadyOE (RC)
Overrun Error

TEMT (R)
Transmit and Shift Register Empty
StatusPE (RC)
Parity Error

THRE (R)
Transmit Register Empty

FE (RC)
Framing Error

BI (RC)
Break Indicator

Figure 17-18: UART_LSR Register Diagram
Table 17-16: UART_LSR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7 FIFOERR(RC/NW)
6 TEMT

Rx FIFO Parity Error/Frame Error/Break Indication.
Data byte(s) in RX FIFO have either parity error, frame error or break indication. onlyused in 16550 mode. Read-clear if no more error in RX FIFO.
Transmit and Shift Register Empty Status.

(R/NW)

0 Tx register has been written to and contains data to betransmitted. Care should be taken not to overwrite its
value.
1 Tx register and the transmit shift register are empty and
it is safe to write new data to the Tx Register. Data has
been transmitted.

5 THRE(R/NW)

Transmit Register Empty.
THRE is cleared when UART_RX is read.
0 Tx register has been written to and contains data to betransmitted. Care should be taken not to overwrite its
value.
1 Tx register is empty and it is safe to write new data to
Tx register The previous data may not have been transmitted yet and can still be present in the shift register.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–25

ADuCM4050 UART Register Descriptions

Table 17-16: UART_LSR Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
4 BI(RC/NW)

Break Indicator.
If set, this bit will self clear after UART_LSR is read.
0 SIN was not detected to be longer than the maximum
word length.
1 SIN was held low for more than the maximum word
length.

3 FE(RC/NW)

Framing Error.
If set, this bit will self clear after UART_LSR is read.
0 No invalid Stop bit was detected.
1 An invalid Stop bit was detected on a received word.

2 PE(RC/NW)

Parity Error.
If set, this bit will self clear after UART_LSR is read.
0 No parity error was detected.
1 A parity error occurred on a received word.

1 OE(RC/NW)

Overrun Error.
If set, this bit will self clear after UART_LSR is read.
0 Receive data has not been overwritten.
1 Receive data was overwritten by new data before Rx register was read.

0 DR(RC/NW)

Data Ready.
This bit is cleared only by reading UART_RX. This bit will not self clear.
0 Rx register does not contain new receive data.
1 Rx register contains receive data that should be read.

17–26

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

RX FIFO Byte Count15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RFC (R)
Current Rx FIFO Data Bytes

Figure 17-19: UART_RFC Register Diagram
Table 17-17: UART_RFC Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
4:0 RFC

Current Rx FIFO Data Bytes.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–27

ADuCM4050 UART Register Descriptions

RS485 Half-duplex Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DISTX (R/W)
Hold off Tx When Receiving

OENP (R/W)
SOUT_EN Polarity

DISRX (R/W)
Disable Rx When Transmitting

OENSP (R/W)
SOUT_EN De-assert Before Full Stop
Bit(s)

Figure 17-20: UART_RSC Register Diagram
Table 17-18: UART_RSC Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
3 DISTX

Hold off Tx When Receiving.

(R/W)
2 DISRXDisable Rx When Transmitting.

(R/W)
1 OENSPSOUT_EN De-assert Before Full Stop Bit(s).

(R/W)

0 SOUT_EN de-assert same time as full stop bit(s)1 SOUT_EN de-assert half-bit earlier than full stop bit(s)0 OENP(R/W)

SOUT_EN Polarity.
0 High active.
1 Low active.

17–28

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

Receive Buffer Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RBR (R)
Receive Buffer Register

Figure 17-21: UART_RX Register Diagram
Table 17-19: UART_RX Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 RBR

Receive Buffer Register.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–29

ADuCM4050 UART Register Descriptions

Scratch Buffer
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SCR (R/W)
ScratchFigure 17-22: UART_SCR Register Diagram
Table 17-20: UART_SCR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 SCR
(R/W)

17–30

Scratch.
An 8-bit register used to store intermediate results. The value contained in
UART_SCR does not affect the UART functionality or performance. Only 8 bits ofthis register are implemented. Bits [15:8] are read only and always return 0x00 whenread. Writable with any value from 0 to 255. A read will return the last value written.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 UART Register Descriptions

TX FIFO Byte Count15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

TFC (R)
Current Tx FIFO Data Bytes

Figure 17-23: UART_TFC Register Diagram
Table 17-21: UART_TFC Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
4:0 TFC

Current Tx FIFO Data Bytes.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

17–31

ADuCM4050 UART Register Descriptions

Transmit Holding Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

THR (W)
Transmit Holding Register

Figure 17-24: UART_TX Register Diagram
Table 17-22: UART_TX Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 THR

Transmit Holding Register.

(RX/W)

17–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceInter-Integrated Circuit (I2C) Interface

18 Inter-Integrated Circuit (I2C) Interface

The ADuCM4050 MCU provides an Inter-Integrated Circuit (I2C) interface with both master and slave functionalities. The peripheral complies with the I2C Bus Specification, Version 2.1.

I2C Features
The I2C interface in the ADuCM4050 MCU supports the following features:• 2-byte transmit and receive FIFOs for the master and slave.
• Support for repeated starts.
• Support for 10-bit addressing.
• Master arbitration is supported.
• Continuous read mode for the master or up to 512 bytes fixed read.
• Clock stretching supported for the slave and the master.
• Slave address setting: support for four 7-bit addresses or one 10-bit address and two 7-bit adddresses.
• Support for internal and external loopback.
• Support for DMA.
• Support for bus clear.

I2C Functional Description
This section provides information on the function of the I2C used by the ADuCM4050 MCU.

I2C Block Diagram
The I2C block diagram is shown below.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

18–1

I2C Operating Modes

MasterStatus
MachineSCLAPB IF

APB
Interface

Datapath
ControlStatusBlock

Slave
Status
Machine

MIRPT
SIRPT
DMA IF

Datapath

External
Interface

SDA

Figure 18-1: I2C Block Diagram

The I2C bus peripheral has two pins used for data transfer. SCL is a serial clock, and SDA is a serial data pin. The
pins are configured in a wired-AND format that allows arbitration in a multimaster system.
A master device can be configured to generate the serial clock. The frequency is programmed by the user in the serial
clock divisor register. The master channel can be set to operate in fast mode (400 kHz) or standard mode (100kHz).
The I2C bus peripherals address in the I2C bus system is programmed by the user. This ID may be changed at any
time while a transfer is not in progress. The user can set up to four slave addresses that are recognized by the peripheral. The peripheral is implemented with a 2-byte FIFO for each transmit and receive shift register. IRQ pins andstatus bits in the control registers are available to signal to the MCU core when the FIFO's need to be serviced.

I2C Operating Modes
The GPIOs used for I2C communication must be configured in I2C mode before enabling the I2C peripheral.

Master Transfer Initiation
If the master enable bit (I2C_MCTL.MASEN) is set, a master transfer sequence is initiated by writing a valid value
to the I2C_ADDR1 and I2C_ADDR2 registers. If there is valid data in the I2C_MTX register, it will be the first
byte transferred in the sequence after the address byte during a write sequence.

Slave Transfer Initiation
If the slave enable bit (I2C_SCTL.SLVEN) is set, a slave transfer sequence is monitored for the device address in
the I2C_ID0, I2C_ID1, I2C_ID2, or I2C_ID3 registers. If the device address is recognized, the part participates in the slave transfer sequence.
A slave operation always starts with the assertion of one of three interrupt sources (I2C_MSTAT.MRXREQ/I2C_SSTAT.SRXREQ, I2C_MSTAT.MTXREQ/I2C_SSTAT.STXREQ, or I2C_SSTAT.GCINT). The
18–2

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I2C Operating Modes

software looks for a stop interrupt to ensure that the transaction has completed correctly and to deassert the stop
interrupt status bit.

Rx/Tx Data FIFOs
The transmit datapath for both master and slave consists of Tx FIFOs 2 bytes deep, MTX and STX, and a transmit
shifter. The transmit status bits, I2C_MSTAT.MTXF and I2C_SSTAT.STXFSEREQ indicate if there is valid data in the Tx FIFO. Data from the Tx FIFO is loaded into the Tx shifter when a serial byte begins transmission. If
the Tx FIFO is not full during an active transfer sequence, the transmit request bit (I2C_MSTAT.MTXREQ or
I2C_SSTAT.STXREQ) will assert.
In the slave, if there is no valid data to transmit when the Tx shifter is loaded, the transmit underflow status bit(I2C_SSTAT.STXUNDR) will assert.
The master generates a stop condition if there is no data in the transmit FIFO and the master is writing data.
The receive datapath consists of a master and slave Rx FIFO, each two bytes deep, I2C_MRX and I2C_SRX. The
receive request interrupt bits (I2C_MSTAT.MRXREQ or I2C_SSTAT.SRXREQ) indicate if there is valid data in
the Rx FIFO. Data is loaded into the Rx FIFO after each byte is received.
If valid data in the Rx FIFO is overwritten by the Rx shifter, the receive overflow status bit (I2C_MSTAT.MRXOVR
or I2C_SSTAT.SRXOVR) will assert.

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I2C Operating Modes

Prior to this, I2C_SCTL.SLVEN, I2C_SCTL.IENRX, I2C_SCTL.IENTX,
and I2C_SCTL.IENSTOP must be set. If necessary,set I2C_SCTL.ADR10EN and I2C_SCTL.EARLYTXR

Write Readto from Slave
Start

Wait for
IRQ

Read I2C_SSTATI2C_SSTAT.SRXREQ asserted?
N
Y
Read byte of theindirect addressfrom I2C_SRX
All of indirect address
received?

N

Y
I2C_SSTAT.STOP asserted?

Wait forIRQ

I2C_SSTAT.SRXREQ asserted?

N
Read I2C_SSTATY

I2C_SSTAT.SRXREQ asserted?
N

Verify which source
asserted IRQ andtake appropriate
actionN

Read a byte of datafrom I2C_SRXY

Go to ReadY
Using indirect address already received, read abyte from memory and write it to I2C_STX
Slave Write
FinishWait for
IRQ

Read I2C_SSTATI2C_SSTAT.STXREQ asserted?
N
Y
I2C_SSTAT.STOP asserted?

Write the next byte ofdata to I2C_STX

NY
Flush salve Tx FIFO
(Redundant data may be left)

Verify which source
caused the IRQ andtake action (for example,
2nd repeated startduring a read)

Slave Read
Complete

Figure 18-2: Slave Read/Write Flow

No Acknowledge from Master
When receiving data, the master responds with a NACK if its FIFO is full and an attempt is made to write anotherbyte to the FIFO. This last byte received is not written to the FIFO and is lost.

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I2C Operating Modes

No Acknowledge from Slave
If the slave does not want to acknowledge a read access, simply not writing data into the slave transmit FIFO results
in a NACK.
If the slave does not want to acknowledge a master write, assert the I2C_SCTL.NACK bit in the slave control register.
Normally, the slave will ACK all bytes written into the receive FIFO. If the receive FIFO fills up, the slave cannot
write further bytes to it, and it will not acknowledge the byte that it was not written to the FIFO. Then, the mastermust stop the transaction.
The slave does not acknowledge a matching device address if the direction bit is 1 (read) and the transmit FIFO isempty. Therefore, the microcontroller has less time to respond to a slave transmit request and the assertion of ACK.
It is recommended to assert the I2C_SCTL.EARLYTXR bit.

General Call
If the general call enable bit (I2C_SCTL.GCEN) and slave enable bit (I2C_SCTL.SLVEN) are set, the device
responds to a general call. If the second byte of the general call is 0x06, the I2C interface (master and slave) is reset.
The general call interrupt status bit (I2C_SSTAT.GCINT) is asserted and general call ID bits
(I2C_SSTAT.GCID) are set to 0x1. User code must reset the entire system or re-enable the I2C interface.
If the second byte is 0x04(write programmable part of slave address by hardware), the general call interrupt status bit(I2C_SSTAT.GCINT) is asserted and general call ID (I2C_SSTAT.GCID) is set to 0x2.
The general call interrupt status bit (I2C_SSTAT.GCINT) gets set on any general call after the second byte isreceived. User code must ensure correct actions such as reprogramming the device address and so on.
If I2C_SCTL.GCEN is asserted, the slave always acknowledges the first byte of a general call. It acknowledges thesecond byte of a general call if the second byte is 0x04 or 0x06, or if the second byte is a hardware general call, andI2C_SCTL.HGCEN is asserted.
The I2C_ALT register contains an alternate device ID for the hardware general call sequence. If the
I2C_SCTL.HGCEN, I2C_SCTL.GCEN, and I2C_SCTL.SLVEN bits are set, the device recognizes a hardware
general call. When a general call sequence is issued, and the second byte of the sequence is identical to ALT, thehardware call sequence is recognized for the device.

Generation of Repeated Starts by Master
The master generates a repeated start if the first master address byte register is written while the master is still busy
with a transaction. Once the state machine has started to transmit the device address, it is then safe to write to thefirst master address byte register.
For instance, if a write-repeated start-read/write transaction is required, write to the first master address byte register
after the state machine starts to transmit the device address, or after the first TXREQ interrupt is received. Whenthe transmit FIFO empties, a repeated start is generated.

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I2C Operating Modes

Similarly, if a read-repeated start-read/write transaction is required, write to the first master address byte register after
the state machine starts to transmit the device address, or after the first RXREQ interrupt is received. When therequested receive count is reached, a repeated start is generated.

DMA Requests
Four DMA channels (two for the master - MAS_DMA_RX_REQ and MAS_DMA_TX_REQ, and two for theslave - SLV_DMA_RX_REQ and SLV_DMA_TX_REQ) are available. The DMA enable bits are provided in the
I2C_SCTL.STXDMA, I2C_SCTL.SRXDMA, I2C_MCTL.MTXDMA, and I2C_MCTL.MRXDMA registers.

I2C Reset Mode
The slave state machine is reset when I2C_SCTL.SLVEN is written to 0, and the master state machine is reset
when I2C_MCTL.MASEN is written to 0.

I2C Test Modes
The device can be placed in an internal loopback mode by setting the I2C_MCTL.LOOPBACK bit. There are four
FIFOs (master Tx and Rx and slave Tx and Rx); therefore in effect, the I2C peripheral can be setup to talk to itself.
External loopback can be performed if the master is setup to address the address of the slave.

I2C Low-Power Mode
If the master and slave are both disabled (I2C_MCTL.MASEN = I2C_SCTL.SLVEN = 0), the device is in its
lowest power mode.
Auto Clock Stretching
Automatic clock stretching pauses a transaction by holding the SCL line low. The transaction cannot continue until
the line is high.
An I2C slave may receive data at a faster rate, but might need more time to store the received byte or prepare another byte for transmission. Slaves can then hold the SCL line low after reception and acknowledgment of a byte. This
forces the master into a wait state until the slave is ready for the next byte transfer.
In the case where the MCU runs at a low frequency or the I2C interrupt has low priority, the automatic clock
stretching feature can be used to hold the I2C bus until the I2C interrupt has been processed.

I2C Bus Clear Operation
In the scenario where the external slave holds SDA low to transmit a 0 (or ACK), it does not release SDA until itgets another falling edge on SCL. As a result, the bus hangs. If the I2C master initiates a new transfer, it hits anarbitration lost condition as SDA does not match the address sent.
If the master lost arbitration when the I2C_MCTL.BUSCLR bit is set, the master sends out extra nine SCL cycles
so that the slave holding the SDA line can release it anywhere before those nine SCL cycles. If the
I2C_MCTL.STOPBUSCLR bit is asserted, the master stops sending the SCL clocks once SDA is released.

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I2C Operating Modes

Power-down Considerations
Consider the following when the part is being powered down to hibernate mode. If the master/slave is IDLE (which
can be known from the respective status registers), it can be immediately disabled by clearing I2C_MCTL.MASEN/
I2C_SCTL.SLVEN bits in the master/slave control registers respectively.
If they are active, there are four cases:• I2C is a master and it does Rx:
In this case, the device receives data based on the count programmed in the I2C_MRXCNT register. It would
be in continuous read-mode if the I2C_MRXCNT.EXTEND bit is set. To stop the read transfer, clear the
I2C_MRXCNT.EXTEND bit and assign the I2C_MRXCNT register with I2C_MCRXCNT.VALUE + 1,
where I2C_MCRXCNT.VALUE gives the current read count.
"+1" signifies that there must be some room for the completion. If the newly programmed value is less than thecurrent count, it receives until the current count overflows and reaches the programmed count. This ends thetransfer after receiving the next byte. Once the transaction complete interrupt is received, the core must disable
the master by clearing the I2C_MCTL.MASEN bit.
• I2C is a master and it does Tx:
The software must flush the Tx-FIFO by setting the I2C_STAT.MFLUSH bit, and disable Tx-request byclearing the I2C_MCTL.IENMTX bit. This ends the current transfer after transmitting the byte in progress.
When the transaction complete interrupt is received, it must clear I2C_MCTL.MASEN bit.
NOTE: Disabling the master before completion can cause the bus to hang indefinitely.
• I2C is a slave and it does Rx:
The software must set the I2C_SCTL.NACK bit. This gives a NACK for the next communication, after
which, the external master has to STOP. On receiving the STOP interrupt, the core must disable the slave byclearing I2C_SCTL.SLVEN bit.
• I2C is a slave and it does Tx:
Once the Slave transmit starts, it cannot NACK any further transaction (ACK is driven only by the master).
So, it has to wait until the external master issues a STOP condition. After receiving the STOP interrupt, theslave can be disabled. This is a clean way to exit. However, if the slave has to be disabled immediately, then it
can be done only at the cost of wrong data getting transmitted (all FFs). This is because the SDA line is not
driven anymore and pulled up during the data phase. In this case, the bus does not hang.

I2C Data Transfer
The I2C peripheral can be programmed for data transfer through both core and DMA modes. There are dedicated
DMA channels for master and slave functionalities. Refer to the Direct Memory Access (DMA) for the DMA channel numbers.

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I2C Interrupts and Exceptions

I2C Interrupts and Exceptions
The I2C block can generate interrupts under various conditions in master and slave modes.

ADuCM4050 I2C Register Descriptions
I2C Master/Slave (I2C) contains the following registers.
Table 18-1: ADuCM4050 I2C Register List
Name

Description

I2C_ADDR1

Master Address Byte 1

I2C_ADDR2

Master Address Byte 2

I2C_ALT

Hardware General Call ID

I2C_ASTRETCH_SCL

Automatic Stretch SCL

I2C_BYT

Start Byte

I2C_DIV

Serial Clock Period Divisor

I2C_ID0

First Slave Address Device ID

I2C_ID1

Second Slave Address Device ID

I2C_ID2

Third Slave Address Device ID

I2C_ID3

Fourth Slave Address Device ID

I2C_MCTL

Master Control

I2C_MCRXCNT

Master Current Receive Data CountI2C_MRX

Master Receive Data

I2C_MRXCNT

Master Receive Data CountI2C_MSTAT

Master Status

I2C_MTX

Master Transmit Data

I2C_SCTL

Slave Control

I2C_SHCTL

Shared Control

I2C_SRX

Slave Receive

I2C_SSTAT

Slave I2C Status/Error/IRQ

I2C_STAT

Master and Slave FIFO Status

I2C_STX

Slave Transmit

I2C_TCTL

Timing Control Register

18–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Master Address Byte 1
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Address Byte 1

Figure 18-3: I2C_ADDR1 Register Diagram
Table 18-2: I2C_ADDR1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE(R/W)

Address Byte 1.
If a 7-bit address is required, Bit 7 to Bit 1 of I2C_ADDR1.VALUE are programmedwith the address, and Bit 0 of I2C_ADDR1.VALUE is programmed with the direction (read or write).
If a 10-bit address is required, Bit 7 to Bit 3 of I2C_ADDR1.VALUE are programmed with 11110, Bit 2 to Bit 1 of I2C_ADDR1.VALUE are programmed with the 2
MSBs of the address, and Bit 0 of I2C_ADDR1.VALUE is programmed to 0.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

18–9

ADuCM4050 I2C Register Descriptions

Master Address Byte 2
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Address Byte 2

Figure 18-4: I2C_ADDR2 Register Diagram
Table 18-3: I2C_ADDR2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE
(R/W)

18–10

Address Byte 2.
This register is only required when addressing a slave with a 10-bit address. Bit 7 to Bit
0 of I2C_ADDR2.VALUE are programmed with the lower 8 bits of the address.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Hardware General Call ID
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ID (R/W)
Slave Alt

Figure 18-5: I2C_ALT Register Diagram
Table 18-4: I2C_ALT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 ID(R/W)

Slave Alt.
This register is used in conjunction with I2C_SCTL.HGCEN to match a master generating a hardware general call. It is used when a master device cannot be programmedwith a slave address and the slave has to recognize the master address.

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ADuCM4050 I2C Register Descriptions

Automatic Stretch SCL
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SLVTMO (R)
Slave Automatic Stretch Timeout

MST (R/W)
Master Automatic Stretch ModeMSTTMO (R)
Master Automatic Stretch Timeout

SLV (R/W)
Slave Automatic Stretch Mode

Figure 18-6: I2C_ASTRETCH_SCL Register Diagram
Table 18-5: I2C_ASTRETCH_SCL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
9 SLVTMO(R/NW)
8 MSTTMO(R/NW)
7:4 SLV(R/W)

Slave Automatic Stretch Timeout.
Asserts when slave automatic stretch timeout occurs and gets cleared when the bit isread.
Master Automatic Stretch Timeout.
Asserts when master automatic stretch timeout occurs and gets cleared when the bit isread.
Slave Automatic Stretch Mode.
It defines the automatic stretch mode for slave. As a slave transmitter, SCL clock is automatically stretched start from the negative edge of SCL, when slave Tx FIFO is empty, before send ACK/NACK for address byte, or before send data for data byte.
Stretching stops when slave Tx FIFO is no longer empty or timeout occurs. As a slave
receiver, SCL clock is automatically stretched start from the negative edge of SCL,
when slave Rx FIFO is overflow, before send ACK/NACK. Stretching stops when slave
Rx FIFO is no longer overflow or timeout occurs.
Slave clock stretch mode is automatically disabled when I2C_SSTAT.STXREQ is asserted. Stretch mode will restore the previously configured value once
I2C_SSTAT.STXREQ is cleared.
Note: When this bit is 4b0000, I2C_SCTL.EARLYTXR must be set to 1. Otherwise, CPU has no time to service slave transmit interrupt when receive address andread request.

18–12

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ADuCM4050 I2C Register Descriptions

Table 18-5: I2C_ASTRETCH_SCL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3:0 MST(R/W)

Master Automatic Stretch Mode.
It defines the automatic stretch mode for master. Stretching means hold SCL line low,then theres more time to service the interrupt. And use a timeout to avoid bus lockup.
0000: no SCL clock stretching
0001: stretch SCL up to 2^1 = 2 bit-times
0010: stretch SCL up to 2^2 = 4 bit-times
1110: stretch SCL up to 2^14 bit-times
1111: stretch SCL up to infinity (no timeout)
Bit time is decided by I2C_DIV.HIGH + I2C_DIV.LOW, and count by PCLK.
Maximum timeout = 2^14/400 kHz = 40 ms. Compatible with SMBus, which has atimeout of 35 ms.
As a master transmitter, SCL clock is automatically stretched start from the negativeedge of SCL, when master Tx FIFO is empty, before send data. And stretching willstop when master Tx FIFO is no longer empty or timeout occurs.
As a master receiver, SCL clock is automatically stretched start from the negative edgeof SCL, when master Rx FIFO is overflow, before ACK/NACK. And stretching willstop when master Rx FIFO is no longer overflow or timeout occurs.
Master clock stretch mode will be automatically disabled when
I2C_MSTAT.MTXREQ is asserted or a new address is written. Stretch mode restoresthe previously configured value once I2C_MSTAT.MTXREQ is cleared or the address
is loaded (RESTART is sent).

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

18–13

ADuCM4050 I2C Register Descriptions

Start Byte
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SBYTE (R/W)
Start Byte

Figure 18-7: I2C_BYT Register Diagram
Table 18-6: I2C_BYT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 SBYTE
(R/W)

18–14

Start Byte.
Used to generate a start byte at the start of a transaction. To generate a start byte followed by a normal address, first write to I2C_BYT.SBYTE then write to the address
register (I2C_ADDR1). This will drive the byte written in I2C_BYT.SBYTE on to
the bus followed by a repeated start. This register can be used to drive any byte on to
the I2C bus followed by a repeated start (not just a start byte 00000001).

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Serial Clock Period Divisor
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

0

0

0

1

1

1

1

1

0

0

1

1

1

1

HIGH (R/W)
Serial Clock High Time

LOW (R/W)
Serial Clock Low Time

Figure 18-8: I2C_DIV Register Diagram
Table 18-7: I2C_DIV Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:8 HIGH(R/W)

Serial Clock High Time.
This register controls the clock high time. The timer is driven by the core clock(UCLK). Use the following equation to derive the required high time.
I2C_DIV.HIGH = ( REQD_HIGH_TIME/PCLK_PERIOD ) - 2
For example, to generate a 400 kHz SCL with a low time of 1300ns and a high time of
1200ns, with a core clock frequency 50 MHz:LOTIME = 1300 ns/20 ns - 1 = 0x40 (64 decimal)
I2C_DIV.HIGH = 1200 ns/20 ns - 2 = 0x3A (58 decimal).
This register is reset to 0x1F which gives an SCL high time of 33 PCLK ticks. tHD:
STA is also determined by the I2C_DIV.HIGH. tHD: STA = (HIGH-1) x pclk_period.
As tHD:STA must be 600 ns, with UCLK = 50 MHz the minimum value for
I2C_DIV.HIGH is 31. This gives an SCL high time of 660 ns.

7:0 LOW(R/W)

Serial Clock Low Time.
This register controls the clock low time. The timer is driven by the core clock(UCLK). Use the following equation to derive the required low time.
I2C_DIV.LOW = ( REQD_LOW_TIME/PCLK_PERIOD ) - 1
This register is reset to 0x1F, which gives an SCL low time of 32 PCLK ticks.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

18–15

ADuCM4050 I2C Register DescriptionsFirst Slave Address Device ID
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Slave Device ID 0

Figure 18-9: I2C_ID0 Register Diagram
Table 18-8: I2C_ID0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE
(R/W)

18–16

Slave Device ID 0.
I2C_ID0.VALUE[7:1] is programmed with the device ID. I2C_ID0.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmedwith a 10-bit address.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Second Slave Address Device ID
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Slave Device ID 1

Figure 18-10: I2C_ID1 Register Diagram
Table 18-9: I2C_ID1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE(R/W)

Slave Device ID 1.
I2C_ID1.VALUE[7:1] is programmed with the device ID. I2C_ID1.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmedwith a 10-bit address.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

18–17

ADuCM4050 I2C Register Descriptions

Third Slave Address Device ID
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Slave Device ID 2

Figure 18-11: I2C_ID2 Register Diagram
Table 18-10: I2C_ID2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE
(R/W)

18–18

Slave Device ID 2.
I2C_ID2.VALUE[7:1] is programmed with the device ID. I2C_ID2.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmedwith a 10-bit address.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Fourth Slave Address Device ID
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Slave Device ID 3

Figure 18-12: I2C_ID3 Register Diagram
Table 18-11: I2C_ID3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE(R/W)

Slave Device ID 3.
I2C_ID3.VALUE[7:1] is programmed with the device ID. I2C_ID3.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmedwith a 10-bit address.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Master Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

STOPBUSCLR (R/W)
Prestop Bus Clear

MASEN (R/W)
Master Enable

BUSCLR (R/W)
Bus-Clear Enable

COMPLETE (R/W)
Start Back-off Disable

MTXDMA (W)
Enable Master Tx DMA Request

LOOPBACK (R/W)
Internal Loopback Enable

MRXDMA (W)
Enable Master Rx DMA Request

STRETCHSCL (R/W)
Stretch SCL Enable

MXMITDEC (R/W)
Decrement Master Tx FIFO Status Whena Byte Txed

IENMRX (R/W)
Receive Request Interrupt Enable
IENMTX (R/W)
Transmit Request Interrupt Enable

IENCMP (R/W)
Transaction Completed (or Stop Detected)
Interrupt Enable

IENALOST (R/W)
Arbitration Lost Interrupt Enable

IENACK (R/W)
ACK Not Received Interrupt Enable

Figure 18-13: I2C_MCTL Register Diagram
Table 18-12: I2C_MCTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
13 STOPBUSCLR(R/W)

12 BUSCLR(R/W)

11 MTXDMA(RX/W)
10 MRXDMA(RX/W)

18–20

Prestop Bus Clear.
This bit should be used in conjunction with I2C_MCTL.BUSCLR. If this bit is set,the master will stop sending any more SCL clocks if SDA is released before 9 SCL cycles.
Bus-Clear Enable.
If this bit is set, the master will initiate a Bus-Clear operation by sending up to 9 extra
SCL cycles if the arbitration was lost. This bit is added to come out of a SDA-stuck
situation due to a misbehaving slave and hence it should be used with caution. Itshould be set only when there is no other active I2C master.
Enable Master Tx DMA Request.
Set to 1 by user code to enable I2C master DMA Tx requests. Cleared by user code todisable DMA mode.
Enable Master Rx DMA Request.
Set to 1 by user code to enable I2C master DMA Rx requests. Cleared by user code todisable DMA mode.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Table 18-12: I2C_MCTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9 MXMITDEC(R/W)

8 IENCMP(R/W)
7 IENACK

Decrement Master Tx FIFO Status When a Byte Txed.
Decrement master TX FIFO status when a byte has been transmitted. If set to 1, themaster transmit FIFO status is decremented when a byte has been transmitted. If set to0, the master transmit FIFO status is decremented when the byte is unloaded from the
FIFO into a shadow register at the start of byte transmission.
Transaction Completed (or Stop Detected) Interrupt Enable.
Transaction completed interrupt enable. When asserted an interrupt is generated whena STOP is detected.
ACK Not Received Interrupt Enable.

(R/W)
6 IENALOST

Arbitration Lost Interrupt Enable.

(R/W)
5 IENMTX

Transmit Request Interrupt Enable.

(R/W)
4 IENMRX

Receive Request Interrupt Enable.

(R/W)
3 STRETCHSCL(R/W)
2 LOOPBACK(R/W)

1 COMPLETE(R/W)
0 MASEN(R/W)

Stretch SCL Enable.
Setting this bit tells the device if SCL is 0 hold it at 0; or if SCL is 1 then when it next
goes to 0 hold it at 0.
Internal Loopback Enable.
When this bit is set, SCL and SDA lines are muxed onto their corresponding inputs.
Note that is also possible for the master to loop back a transfer to the slave as long as
the device address corresponds, i.e. external loopback.
Start Back-off Disable.
Setting this bit enables the device to compete for ownership even when another device
is driving a start condition.
Master Enable.
When the bit is 1 the master is enabled. When the bit is 0 all master state machine
flops are held in reset and the master is disabled. The master should be disabled when
not in use as this will gate the clock to the master and save power. This bit should not
be cleared until a transaction has completed, see the I2C_MSTAT.TCOMP. APB
writable register bits are not reset by this bit. Cleared by default.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Master Current Receive Data Count15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)
Current Receive Count

Figure 18-14: I2C_MCRXCNT Register Diagram
Table 18-13: I2C_MCRXCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE(R/NW)

18–22

Current Receive Count.
This register gives the total number of bytes received. If 256 bytes are requested, thisregister will read 0 when the transaction is completed.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Master Receive Data
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)
Master Receive Register

Figure 18-15: I2C_MRX Register Diagram
Table 18-14: I2C_MRX Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE(R/NW)

Master Receive Register.
This register allows access to the receive data FIFO. The FIFO can hold 2 bytes.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Master Receive Data Count15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EXTEND (R/W)
Extended Read

VALUE (R/W)
Receive Count

Figure 18-16: I2C_MRXCNT Register Diagram
Table 18-15: I2C_MRXCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
8 EXTEND(R/W)

7:0 VALUE
(R/W)

18–24

Extended Read.
Use this bit if greater than 256 bytes are required for a read. For example, to receive
412 bytes write 1 to I2C_MRXCNT.EXTEND. Wait for the first byte to be received,
then check the I2C_MCRXCNT register for every byte received. When
I2C_MRXCNT.VALUE returns to 0, 256 bytes have been received. Then write
0x09C to the I2C_MRXCNT register.
Receive Count.
Program the number of bytes required minus one to this register. If just 1 byte is required write 0 to this register. If greater than 256 bytes are required then use
I2C_MRXCNT.EXTEND.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Master Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

SCLFILT (R)State of SCL LineMTXF (R)
Master Transmit FIFO Status

SDAFILT (R)State of SDA LineMTXREQ (R/W)
Master Transmit Request/Clear MasterTransmit Interrupt

MTXUNDR (RC)
Master Transmit Underflow

MRXREQ (R)
Master Receive Request

MSTOP (RC)
STOP Driven by This I2C Master

NACKADDR (RC)ACK Not Received in Response to an
Address

LINEBUSY (R)Line is Busy

ALOST (RC)
Arbitration Lost

MRXOVR (RC)
Master Receive FIFO Overflow

MBUSY (R)
Master BusyTCOMP (RC)Transaction Complete or Stop Detected

NACKDATA (RC)ACK Not Received in Response to Data
Write

Figure 18-17: I2C_MSTAT Register Diagram
Table 18-16: I2C_MSTAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14 SCLFILT(R/NW)
13 SDAFILT(R/NW)
12 MTXUNDR(RC/NW)
11 MSTOP(RC/NW)

State of SCL Line.
This bit is the output of the glitch-filter on SCL. SCL is always pulled high when undriven.
State of SDA Line.
This bit is the output of the glitch-filter on SDA. SDA is always pulled high when undriven.
Master Transmit Underflow.
Asserts when the I2C master ends the transaction due to Tx FIFO empty condition.
This bit is asserted only when the I2C_MCTL.IENMTX bit is set.
STOP Driven by This I2C Master.
Asserts when this I2C master drives a STOP condition on the I2C bus. This bit, whenasserted, can indicate a Transaction completion, Tx-underflow, Rx-overflow or a
NACK by the slave. This is different from the I2C_MSTAT.TCOMP as this bit is notasserted when the STOP condition occurs due to any other I2C master. No interrupt
is generated for the assertion of this bit. However, if I2C_MCTL.IENCMP = 1, every
STOP condition will generate an interrupt and this bit can be read. When this bit isread, it will clear status.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Table 18-16: I2C_MSTAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10 LINEBUSY(R/NW)
9 MRXOVR(RC/NW)
8 TCOMP(RC/NW)

7 NACKDATA(RC/NW)

6 MBUSY(R/NW)
5 ALOST(RC/NW)

4 NACKADDR(RC/NW)

3 MRXREQ(R/NW)
2 MTXREQ
(R/W)

18–26

Line is Busy.
Asserts when a START is detected on the I2C bus. De-asserts when a STOP is detected on the I2C bus.
Master Receive FIFO Overflow.
Asserts when a byte is written to the receive FIFO when the FIFO is already full.
When the bit is read it will clear status.
Transaction Complete or Stop Detected.
Transaction complete. This bit will assert when a STOP condition is detected on the
I2C bus. If I2C_MCTL.IENCMP = 1, an interrupt will be generated when this bit
asserts. This bit will only assert if the master is enabled (I2C_MCTL.MASEN = 1).
This bit should be used to determine when it is safe to disable the master. It can also be
used to wait for another master transaction to complete on the I2C bus when this master looses arbitration. When this bit is read it will clear status. This bit can drive aninterrupt.
ACK Not Received in Response to Data Write.
This bit will assert when an ACK is not received in response to a data write transfer. If
I2C_MCTL.IENACK = 1, an interrupt will be generated when this bit asserts. Thisbit can drive an interrupt. This bit is cleared on a read of the I2C_MSTAT register.
Master Busy.
This bit indicates that the master state machine is servicing a transaction. It will beclear if the state machine is idle or another device has control of the I2C bus.
Arbitration Lost.
This bit will assert if the master loses arbitration. If I2C_MCTL.IENALOST = 1, aninterrupt will be generated when this bit asserts. This bit is cleared on a read of the
I2C_MSTAT register. This bit can drive an interrupt.
ACK Not Received in Response to an Address.
This bit will assert if an ACK is not received in response to an address. If
I2C_MCTL.IENACK = 1, an interrupt will be generated when this bit asserts. Thisbit is cleared on a read of the I2C_MSTAT register. This bit can drive an interrupt.
Master Receive Request.
This bit will assert when there is data in the receive FIFO. If I2C_MCTL.IENMRX =1, an interrupt will be generated when this bit asserts. This bit can drive an interrupt.
Master Transmit Request/Clear Master Transmit Interrupt.
When read is master transmit request; when write is clear master transmit interrupt
bit. This bit will assert when the direction bit is 0 and transmit FIFO is not full. If
I2C_MCTL.IENMTX = 1, an interrupt will be generated when this bit asserts. When
this bit is written to 1, master transmit interrupt and clock stretching will be cleared.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Table 18-16: I2C_MSTAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1:0 MTXF(R/NW)

Master Transmit FIFO Status.
These 2 bits show the master transmit FIFO status.
0 FIFO Empty.
2 1 byte in FIFO.
3 FIFO Full.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Master Transmit Data
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Master Transmit Register

Figure 18-18: I2C_MTX Register Diagram
Table 18-17: I2C_MTX Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE
(R/W)

18–28

Master Transmit Register.
For test and debug purposes, when read, this register returns the byte that is currently
being transmitted by the master. That is a byte written to the transmit register can beread back some time later when that byte is being transmitted on the line. This register
allows access to the transmit data FIFO. The FIFO can hold 2 bytes.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Slave Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

STXDMA (R/W)
Enable Slave Tx DMA Request

SLVEN (R/W)
Slave Enable

SRXDMA (R/W)
Enable Slave Rx DMA Request

ADR10EN (R/W)
Enabled 10-bit Addressing

IENREPST (R/W)
Repeated Start Interrupt Enable

GCEN (R/W)
General Call Enable

STXDEC (R/W)
Decrement Slave Tx FIFO Status Whena Byte is Txed

HGCEN (R/W)
Hardware General Call Enable
GCSBCLR (W)General Call Status Bit Clear

IENSTX (R/W)
Slave Transmit Request Interrupt Enable

EARLYTXR (R/W)
Early Transmit Request ModeIENSRX (R/W)
Slave Receive Request Interrupt Enable

NACK (R/W)
NACK Next Communication

IENSTOP (R/W)
Stop Condition Detected Interrupt Enable

Figure 18-19: I2C_SCTL Register Diagram
Table 18-18: I2C_SCTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14 STXDMA(R/W)
13 SRXDMA(R/W)
12 IENREPST(R/W)

11 STXDEC(R/W)

10 IENSTX

Enable Slave Tx DMA Request.
Set to 1 by user code to enable I2C slave DMA Rx requests. Cleared by user code todisable DMA mode.
Enable Slave Rx DMA Request.
Set to 1 by user code to enable I2C slave DMA Rx requests. Cleared by user code todisable DMA mode.
Repeated Start Interrupt Enable.
If 1 an interrupt will be generated when the I2C_SSTAT.REPSTART status bit asserts. If 0 an interrupt will not be generated when the I2C_SSTAT.REPSTART status bit asserts.
Decrement Slave Tx FIFO Status When a Byte is Txed.
Decrement Slave Tx FIFO status when a byte has been transmitted. If set to 1, thetransmit FIFO status is decremented when a byte has been transmitted. If set to 0, thetransmit FIFO status is decremented when the byte is unloaded from the FIFO into ashadow register at the start of byte transmission.
Slave Transmit Request Interrupt Enable.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Table 18-18: I2C_SCTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9 IENSRX

Slave Receive Request Interrupt Enable.

(R/W)
8 IENSTOP

Stop Condition Detected Interrupt Enable.

(R/W)
7 NACK(R/W)

5 EARLYTXR(R/W)
4 GCSBCLR(RX/W)

3 HGCEN(R/W)

2 GCEN(R/W)
1 ADR10EN(R/W)

0 SLVEN
(R/W)

18–30

NACK Next Communication.
If this bit is set the next communication will be NACK 'ed. This could be used forexample if during a 24xx style access, an attempt was made to write to a 'read only' ornonexisting location in system memory. That is the indirect address in a 24xx style
write pointed to an unwritable memory location.
Early Transmit Request Mode.
Setting this bit enables a transmit request just after the positive edge of the direction
bit SCL clock pulse.
General Call Status Bit Clear.
The I2C_SSTAT.GCINT and I2C_SSTAT.GCID bits are cleared when a '1' iswritten to this bit. The I2C_SSTAT.GCINT and I2C_SSTAT.GCID bits are notreset by anything other than a write to this bit or a full reset.
Hardware General Call Enable.
When this bit and the I2C_SCTL.GCEN bit are set the device after receiving a general call, address 00h and a data byte checks the contents of the I2C_ALT against thereceive shift register. If they match the device has received a 'hardware general call'.
This is used if a device needs urgent attention from a master device without knowing
which master it needs to turn to. This is a call "to whom it may concern". The device
that requires attention embeds its own address into the message. The LSB of the
I2C_ALT register should always be written to a 1, as per I2C January 2000 specification.
General Call Enable.
This bit enables the I2C slave to ACK an I2C general call, address 0x00 (Write).
Enabled 10-bit Addressing.
If this bit is clear, the slave can support four slave addresses, programmed in I2C_ID0
to I2C_ID0. When this bit is set, 10 bit addressing is enabled. One 10 bit address is
supported by the slave and is stored in I2C_ID0 and I2C_ID1, where I2C_ID0
contains the first byte of the address and the upper 5 bits must be programmed to11110. I2C_ID2 and I2C_ID3 can be programmed with 7 bit addresses at thesame time.
Slave Enable.
When '1' the slave is enabled. When '0' all slave state machine flops are held in reset
and the slave is disabled. Note that APB writable register bits are not reset.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Shared Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RST (W)
Reset START STOP Detect Circuit

Figure 18-20: I2C_SHCTL Register Diagram
Table 18-19: I2C_SHCTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
0 RST(RX/W)

Reset START STOP Detect Circuit.
Writing a 1 to this bit will reset the SCL and SDA synchronisers, the START and
STOP detect circuit and the LINEBUSY detect circuit. These circuits are not reset
when both the master and slave are disabled as LINEBUSY needs to assert even whenthe master is not enabled. It should only be necessary to reset these circuits after a
power on reset in case SCL/SDA do not power up cleanly. Reading this bit will always
read back '0'.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Slave Receive
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)
Slave Receive Register

Figure 18-21: I2C_SRX Register Diagram
Table 18-20: I2C_SRX Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE

Slave Receive Register.

(R/NW)

18–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Slave I2C Status/Error/IRQ
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

START (R)Start and Matching Address

STXFSEREQ (R/W)
Slave Tx FIFO Status or Early Request

REPSTART (RC)
Repeated Start and Matching Address

STXUNDR (RC)
Slave Transmit FIFO Underflow

IDMAT (R)
Device ID Matched

STXREQ (RC)
Slave Transmit Request/Slave Transmit
Interrupt

STOP (RC)
Stop After Start and Matching Address

SRXREQ (RC)
Slave Receive Request

GCID (R)General ID

SRXOVR (RC)
Slave Receive FIFO Overflow

GCINT (R)General Call Interrupt

NOACK (RC)ACK Not Generated by the Slave

SBUSY (R)
Slave Busy

Figure 18-22: I2C_SSTAT Register Diagram
Table 18-21: I2C_SSTAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14 START(R/NW)

13 REPSTART(RC/NW)

12:11 IDMAT(R/NW)Start and Matching Address.
This bit is asserted if a start is detected on SCL/SDA and the device address matched,or a general call(GC - 0000_0000) code is received and GC is enabled, or a High
Speed (HS - 0000_1XXX) code is received, or a start byte (0000_0001) is received. It
is cleared on receipt of either a stop or start condition.
Repeated Start and Matching Address.
This bit is asserted if I2C_SSTAT.START is already asserted and then a repeatedstart is detected. It is cleared when read or on receipt of a STOP condition. This bit
can drive an interrupt.
Device ID Matched.
0 Received address matched ID register 0
1 Received address matched ID register 1
2 Received address matched ID register 2
3 Received address matched ID register 3

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

18–33

ADuCM4050 I2C Register Descriptions

Table 18-21: I2C_SSTAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10 STOP(RC/NW)

9:8 GCID(R/NW)

Stop After Start and Matching Address.
Gets set by hardware if the slave device received a STOP condition after a previous
START condition and a matching address. Cleared by a read of the I2C_SSTAT register. If I2C_SCTL.IENSTOP in the slave control register is asserted, then the slaveinterrupt request will assert when this bit is set. This bit can drive an interrupt.
General ID.
I2C_SSTAT.GCID is cleared when the I2C_SCTL.GCSBCLR is written to 1.
These status bits will not be cleared by a General call reset.
0 No general call
1 General call reset and program address
2 General call program address
3 General call matching alternative ID

7 GCINT(R/NW)

6 SBUSY(R/NW)

5 NOACK(RC/NW)

4 SRXOVR(RC/NW)
3 SRXREQ(RC/NW)

18–34

General Call Interrupt.
This bit always drives an interrupt. The bit is asserted if the slave device receives a general call of any type. To clear, write 1 to the I2C_SCTL.GCSBCLR in the slave control register. If it was a general call reset, all registers will be at their default values. If it
was a hardware general call, the Rx FIFO holds the second byte of the general call, andthis can be compared with the I2C_ALT register.
Slave Busy.
Set by hardware if the slave device receives a I2C START condition. Cleared by hardware when the address does not match an ID register, the slave device receives a I2C
STOP condition, or if a repeated start address does not match.
ACK Not Generated by the Slave.
When asserted, it indicates that the slave responded to its device address with a
NOACK. It is asserted if there was no data to transmit and sequence was a slave reador if the I2C_SCTL.NACK bit was set and the device was addressed. This bit iscleared on a read of the I2C_SSTAT register.
Slave Receive FIFO Overflow.
Asserts when a byte is written to the slave receive FIFO when the FIFO is already full.
Slave Receive Request.
I2C_SSTAT.SRXREQ asserts whenever the slave receive FIFO is not empty. Read or
flush the slave receive FIFO to clear this bit. This bit will assert on the falling edge of
the SCL clock pulse that clocks in the last data bit of a byte. This bit can drive aninterrupt.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 I2C Register Descriptions

Table 18-21: I2C_SSTAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 STXREQ(RC/NW)

Slave Transmit Request/Slave Transmit Interrupt.
When read is slave transmit request; when write is clear slave transmit interrupt bit.
This bit is read only.
If I2C_SCTL.EARLYTXR = 0, this bit is set when the direction bit for a transfer isreceived high. There after, as long as the transmit FIFO is not full this bit will remain
asserted. Initially it is asserted on the negative edge of the SCL pulse that clocks in the
direction bit (if the device address matched also).
If I2C_SCTL.EARLYTXR = 1, this bit is set when the direction bit for a transfer isreceived high. There after, as long as the transmit FIFO is not full this bit will remain
asserted. Initially it is asserted after the positive edge of the SCL pulse that clocks inthe direction bit (if the device address matched also).
This bit is cleared on a read of the I2C_SSTAT register. slv_txint_clr, write only.
When this bit is 1, slave transmit interrupt and clock stretching will be cleared. And
this bit will be cleared, when STOP or (RE)START is received (transfer is done); TX
FIFO is written (software decided it now has more data to send); TX FIFO is empty
and an ACK is received instead of a NACK.

1 STXUNDR(RC/NW)
0 STXFSEREQ(R/W)

Slave Transmit FIFO Underflow.
Is set if a master requests data from the device, and the Tx FIFO is empty for the risingedge of SCL.
Slave Tx FIFO Status or Early Request.
If I2C_SCTL.EARLYTXR = 0, this bit is asserted whenever the slave Tx FIFO isempty.
If I2C_SCTL.EARLYTXR = 1, this bit is set when the direction bit for a transfer isreceived high. It asserts on the positive edge of the SCL clock pulse that clocks in the
direction bit (if the device address matched also). It only asserts once for a transfer. It iscleared when read if I2C_SCTL.EARLYTXR is asserted.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Master and Slave FIFO Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

MFLUSH (W)
Flush the Master Transmit FIFO

STXF (R)
Slave Transmit FIFO Status

SFLUSH (W)
Flush the Slave Transmit FIFOSRXF (R)
Slave Receive FIFO Status

MRXF (R)
Master Receive FIFO Status

MTXF (R)
Master Transmit FIFO Status

Figure 18-23: I2C_STAT Register Diagram
Table 18-22: I2C_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
9 MFLUSH(RX/W)
8 SFLUSH(RX/W)
7:6 MRXF(R/NW)

Flush the Master Transmit FIFO.
Writing a '1' to this bit flushes the master transmit FIFO. The master transmit FIFO
will have to flushed if arbitration is lost or a slave responds with a NACK.
Flush the Slave Transmit FIFO.
Writing a '1' to this bit flushes the slave transmit FIFO.
Master Receive FIFO Status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved

5:4 MTXF(R/NW)

Master Transmit FIFO Status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved

18–36

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ADuCM4050 I2C Register Descriptions

Table 18-22: I2C_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3:2 SRXF(R/NW)

Slave Receive FIFO Status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved

1:0 STXF(R/NW)

Slave Transmit FIFO Status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 I2C Register Descriptions

Slave Transmit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Slave Transmit Register

Figure 18-24: I2C_STX Register Diagram
Table 18-23: I2C_STX Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7:0 VALUE

Slave Transmit Register.

(R/W)

18–38

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ADuCM4050 I2C Register Descriptions

Timing Control Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

FILTEROFF (R/W)
Input Filter Control

THDATIN (R/W)
Data in Hold Start

Figure 18-25: I2C_TCTL Register Diagram
Table 18-24: I2C_TCTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
8 FILTEROFF(R/W)

Input Filter Control.
Input Filter Control. It may be desirable to disable the digital filter if PCLK rate becomes < 16MHz.
0 Digital filter is enabled and is equal to 1 PCLK
1 Digital filter is disabled. Filtering in the pad is unaffected

4:0 THDATIN(R/W)

Data in Hold Start.
I2C_TCTL.THDATIN determines the hold time requirement that must be met before a start or stop condition is recognized. The hold time observed between SDA and
SCL fall must exceed the programmed value to be recognized as a valid Start.
I2C_TCTL.THDATIN = ( tHD;STA) / (Clock Period). For example, at 16MHzPCLK (62.5ns) and setting a minimum tHD;STA limit of 300ns. (300ns)/(62.5ns) =5.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

18–39Beeper Driver (BEEP)

19 Beeper Driver (BEEP)

The beeper driver module generates a differential square wave of programmable frequency. It is used to drive an
external piezoelectric sound component whose two terminals connect to the differential square wave output. A
standard APB interface connects this module to the system bus.

Beeper Features
The beeper driver present in the MCU includes the following features:• A module that can deliver frequencies from 8 kHz to ~0.25 kHz.
• It operates on a fixed, independent 32 kHz clock source that is unaffected by changes in system clocks.
• It allows a programmable tone duration from 4 ms to 1.02 s in 4 ms increments.
• Single-tone (pulse) and multitone (sequence) modes provide versatile playback options.
• In sequence mode, the beeper may be programmed to play any number of tone pairs from 1 to 254 (2 to 508
tones) or be programmed to play forever (until stopped by the user).
• Interrupts are available to indicate the start or end of any beep, the end of a sequence, or that the sequence isnearing completion.

Beeper Functional Description
This section provides information on the function of the beeper driver used by the ADuCM4050 MCU.

Beeper Block Diagram
The figure shows the block diagram of the beeper driver used by the ADuCM4050 MCU.

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Beeper Operating Modes

BeeperBeeper Controller

IRQ

Sequence
Control
APB

MMR

Pulse Control

32 kHz clock

Clock Divider

Tone
Generator+-

Figure 19-1: Beeper Driver

The clock divider divides the 32 kHz input clock down to frequencies between 8 kHz and ~0.25 kHz for driving
the off-chip piezoelectric component. The beeper controller block controls the tone generator, enabling and disabling its operation, and selecting the appropriate frequency output from the clock divider.
The beeper controller also tracks the durations and repeating sequences of tones. The beeper module can interrupt
the micro with one interrupt line. Its off-chip output lines are held low when the module is disabled (no voltage
across the piezoelectric component), and drive a differential square wave while tones are being played.

Beeper Operating Modes
The basic operation of the beeper driver consists of writing tone data into one or both tone registers, followed byenabling the beeper by setting the BEEP_CFG.EN bit. Once enabled, the module plays one or more tones depending on the operating mode. During playback, the module outputs a differential square wave (VSS to VCC) withfrequency and duration based on the BEEP_TONEA or BEEP_TONEB register settings.
Beeper has two modes of operation. If the BEEP_CFG.SEQREPEAT bit fields have a non-zero value when the
beeper is enabled, the beeper operates in sequence mode. If the beeper is enabled with BEEP_CFG.SEQREPEAT
set to 0x0, the beeper operates in pulse mode.
Pulse mode operation completes after playing exactly one tone. Sequence mode operation plays a configurable number of tones before completion. While operating in pulse or sequence mode, the BEEP_STAT.BUSY bit is asserted. This bit is cleared on completion of the operation.
A currently playing tone may be prematurely terminated by writing 0x0 to the BEEP_TONEA.DUR and
BEEP_TONEB.DUR bits. When terminated, the BEEP_STAT.AENDED and BEEP_STAT.BENDED bits areset, and generates an interrupt if configured using the BEEP_CFG.AENDIRQ and BEEP_CFG.BENDIRQ bits.
Alternatively, all playback may be immediately terminated by disabling the beeper (clearing the BEEP_CFG.EN
bit). Disabling the beeper prevents any events from occurring and, therefore, prevents an interrupt from being generated.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceBeeper Operating Modes

An interrupt is generated when an event is requested. The BEEP_STAT register provides feedback on the six
tracked events that has occurred since the register was last cleared. Any of these six events may be used for generatinginterrupts by selecting them in the BEEP_CFG register.
The operating mode of the beeper is set when the beeper is enabled and cannot be changed until the beeper is again
disabled. The beeper may be disabled by writing 0x0 to the BEEP_CFG.EN bit or by waiting for the beeper todisable itself after the current pulse or sequence completes.

Pulse ModeIn pulse mode, the beeper plays back exactly one tone. Pulse mode operation begins by enabling the beeper with azero value in the BEEP_CFG.SEQREPEAT bit. Once enabled, the beeper plays back a single tone as described in
the BEEP_TONEA register. Once the playback of this tone has been completed, the BEEP_STAT.BUSY bit iscleared.
Interrupts are generated as requested in the BEEP_CFG register. Note that the only events that may occur in thismode (and used to generate meaningful interrupts) are for the start (BEEP_CFG.ASTARTIRQ) and end(BEEP_CFG.AENDIRQ) of BEEP_TONEA play back.

Sequence ModeIn sequence mode, the beeper plays back a programmable number of tones. Sequence mode operation begins byenabling the beeper with a non-zero value in the BEEP_CFG.SEQREPEAT field. Once enabled, the beeper plays
back a series of two-tone sequences as described in the BEEP_TONEA and BEEP_TONEB registers. Each two-tone
iteration starts by playing BEEP_TONEA and ends by playing BEEP_TONEB.
The sequence is repeated as configured in the BEEP_CFG.SEQREPEAT field. 0xFF is a special case used to run
the sequencer until terminated by the user code. Once all iterations have been completed, the BEEP_STAT.BUSY
bit is cleared.
The number of remaining sequence iterations may be read from the BEEP_STAT.SEQREMAIN bit. When running an infinite sequence, the BEEP_STAT.SEQREMAIN bit always returns 0xFF. Writing to
BEEP_CFG.SEQREPEAT while the beeper is running in sequence mode, restarts the iteration counter to that value and immediately updates the value of the BEEP_STAT.SEQREMAIN bit.
Sequence mode may be prematurely terminated by writing 0x0 to the BEEP_CFG.SEQREPEAT bit. Setting the
BEEP_CFG.SEQREPEAT bit to 0x0 causes the beeper to terminate playback and disable itself after the completion of the current two-tone sequence. When terminated, the BEEP_STAT.SEQENDED bit is set, and generates aninterrupt if configured using the BEEP_CFG.SEQATENDIRQ bit. Alternatively, all playback may be immediately
terminated by disabling the beeper (clearing the BEEP_CFG.EN bit); disabling the beeper prevents any events fromoccurring and, therefore, prevents an interrupt from being generated.
Interrupts are generated in sequence mode as requested in the BEEP_CFG register. All beeper events are valid forinterrupt generation in this mode.

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Beeper Operating Modes

Tones
The frequency and duration of tones played by the beeper depend on the values stored in the BEEP_TONEA and
BEEP_TONEB registers. Each of these registers describes a single independent tone. Pulse mode plays tones only
from register BEEP_TONEA, while sequence mode plays tones from both tone registers.
The tone registers are broken into three fields: a duration field (BEEP_TONEA.DUR, BEEP_TONEB.DUR), a frequency field (BEEP_TONEA.FREQ, BEEP_TONEB.FREQ), and a disable field (BEEP_TONEA.DIS,
BEEP_TONEB.DIS).
Tone registers may be written at any time. Writing 0x0 to the duration field (BEEP_TONEA.DUR,
BEEP_TONEB.DUR) or setting/clearing the disable bit (BEEP_TONEA.DIS, BEEP_TONEB.DIS) for a currently playing tone will take effect immediately. All other modifications to the BEEP_TONEA and BEEP_TONEB
registers take effect only the next time the tone is played; for most use cases, this allows the next tone data to be
written to while the current tone is being played.
The duration field is used to program how long a tone will play when selected for playback. Durations are measured
in units of 4 ms. Any value from 0 through 255 may be stored in the tone register. A duration of 0x0 will cause thetone playback to end immediately. A value of 255 (0xFF) is a special case value used to program a tone for infinite
duration; once started, the tone will play continuously until user code terminates the tone (writes 0x0 to
BEEP_TONEA.DUR, BEEP_TONEB.DUR) or disables the beeper (clears the BEEP_CFG.EN bit).
The frequency field is used to program the relative frequency of the tone with respect to the source clock (32.768
kHz). Writing values 0, 1, 2, or 3 into the frequency field all have the same effect: the output will not oscillate during playback (also known as rest tone). Any value from 4 through 127 (0x7F) may be used to divide the source clock
down to the desired tone frequency. This provides a playback range from 8 kHz down to ~0.25 kHz.
The disable field is used to provide further control over the output pins of the beeper during playback. When playing a tone with the BEEP_TONEA.DIS, BEEP_TONEB.DIS bit set, the output pins behave as though the beeper were disabled; both pins rest at logic 0 with no DC potential between them and no oscillations. This feature isintended for use when long periods of silence exist in a programmed sequence. It may be used to prevent damage tothe piezo electric component during these periods of silence.

Clocking and PowerThe frequency and duration timers of the beeper driver are based on a 32.768 kHz input clock. The clock source isconfigured system wide, selecting between an external crystal or an internal oscillator by writing to the appropriate
clock control module register (CLKG_OSC_CTL.LFCLKMUX). The selected clock only provides a stable reference
for the timers; the internal logic of the beeper is clocked by the peripheral clock (PCLK) of the system. For thisreason, the beeper cannot run while the system is in a low power mode that gates the peripheral clock (PCLK).
Timer start events are synchronized with the 32 kHz clock. When enabling the beeper, its output may therefore bedelayed by as much as one 32 kHz clock period (30,520 ns). For a 4 MHz PCLK, this results in up to 122 PCLK
periods between starting the beeper and actually producing audio output. Any changes to the BEEP_TONEA and

19–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceBeeper Operating Modes

BEEP_TONEB registers during this time will affect the pending audio. User code must ensure that the tone is playing before modifying the tone registers, either by polling the BEEP_STAT.ASTARTED and
BEEP_STAT.BSTARTED bits or by setting an interrupt for the same.
User code must disable the beeper prior to entering a low power state where the peripheral clock would be gated.
Damage to the piezo electric component may occur if the system enters a low power mode while the beeper is playing a tone due to constant, long term DC potential across the terminals of the piezo electric component.

Power-down Considerations
There is the possibility of irreversible damage to the external piezo beeper device if the beeper is enabled and driving
the Tone outputs under the following conditions:• Entering the Hibernate power mode
• Entering the Shutdown power mode
• Turning off PCLKThe pins do not disengage automatically from the beeper module in these modes.

Beeper Interrupts and Events
There are six tracked events that may occur while the beeper is running: Tone A may start or end, Tone B may startor end, and the sequencer may end or be one step away from ending. These six events are always monitored, andwhen they occur, a sticky bit is set in the BEEP_STAT register to be read by the user at some future time. These
bits remain set until cleared by user code.
Any of these six events may also be used to generate an interrupt. Selecting which events will generate interrupts isdone by setting the respective bits in the BEEP_CFG register. When an event triggers an interrupt, user code mustclear the event bit or disable the interrupt selection bit when servicing the interrupt.
When servicing a beeper interrupt, user code should check and eventually clear all event bits in the BEEP_STAT
register; multiple events may have triggered the interrupt (if enabled). Writing 0xFF to BEEP_STAT clears all
events.
All tracked events are independently selectable for interrupt generation.

Beeper Programming Model
The following sections provide general programming guidelines and procedures.

Timing Diagram
The figure shows the behavior of the beeper when programmed to generate a tone.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

19–5

Beeper Programming Model

PCLK

32 kHz CLK

TONE_A

BEEP_CFG

A

CON
Tdel

TONE_P

TONE_N
Tfreq

Figure 19-2: Timing Diagram

In this example, the tone is first written to the BEEP_TONEA register, followed by enabling the beeper by writing to
the BEEP_CFG register. Tdel illustrates the maximum one 32 kHz clock period delay between enabling the beeper
and the actual start of playback. Tfreq illustrates the output period of the two differential pins; for a 1 kHz (1024Hz) tone, Tfreq = 0.9766 ms.

Programming Guidelines
Programming Examples
The beeper driver is programmed for a single 1 kHz beep of 1 second length with an interrupt when the tone isdone playing.
1. Set Tone A duration to 1 s. BEEP_TONEA.DUR = 0xFA. // (250 × 4 ms).
2. Set Tone A frequency to 1 kHz. BEEP_TONEA.FREQ = 0x20 // (32 kHz/32).
3. Set interrupt at the end of Tone A. BEEP_CFG.AENDIRQ = 0x1.
4. Set the sequence repeat to zero. BEEP_CFG.SEQREPEAT = 0x0.
5. Enable the beeper. BEEP_CFG.EN = 0x1.
The register access sequence is BEEP_TONEA = 0x20FA and BEEP_CFG = 0x0900.
The beeper driver is programmed for a melody of 32 two-tone sequences of the note G# for 500 ms and F# for1000 ms with an interrupt at the end of the melody.
1. Set Tone A duration to 500 ms. BEEP_TONEA.DUR = 0x7D. // (125 × 4 ms).
2. Set Tone A frequency to G#. BEEP_TONEA.FREQ = 0x27. // (32 kHz/39 = 840 Hz).
3. Set Tone B duration to 1000 ms. BEEP_TONEB.DUR = 0xFA // (250 × 4 ms).
4. Set Tone B frequency to F#. BEEP_TONEB.FREQ = 0x2C. //(32 kHz/44 = 745 Hz).

19–6

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ADuCM4050 BEEP Register Descriptions

5. Set interrupt at end of sequence. BEEP_CFG.SEQATENDIRQ = 0x1.
6. Set sequence repeat to 32. BEEP_CFG.SEQREPEAT = 0x20.
7. Enable the beeper. BEEP_CFG.EN = 0x1.
The register access sequence is BEEP_TONEA = 0x277D, BEEP_TONEB = 0x2CFA, and BEEP_CFG = 0x8120.

ADuCM4050 BEEP Register Descriptions
Beeper Driver (BEEP) contains the following registers.
Table 19-1: ADuCM4050 BEEP Register List
Name

Description

BEEP_CFG

Beeper Configuration

BEEP_STAT

Beeper Status

BEEP_TONEA

Tone A Data

BEEP_TONEB

Tone B Data

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

19–7

ADuCM4050 BEEP Register Descriptions

Beeper Configuration
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SEQATENDIRQ (R/W)
Sequence End IRQ

SEQREPEAT (R/W)
Beeper Sequence Repeat ValueSEQNEARENDIRQ (R/W)
Sequence 1 Cycle from End IRQ

EN (W)
Beeper Enable

BENDIRQ (R/W)
Tone B End IRQ

ASTARTIRQ (R/W)
Tone A Start IRQ

BSTARTIRQ (R/W)
Tone B Start IRQ

AENDIRQ (R/W)
Tone A End IRQ

Figure 19-3: BEEP_CFG Register Diagram
Table 19-2: BEEP_CFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 SEQATENDIRQ(R/W)

Sequence End IRQ.
Set this bit to request an interrupt on the event the sequencer has stopped playing.
0 IRQ not generated at end of Sequence
1 IRQ generated at end of Sequence

14 SEQNEARENDIRQ(R/W)

Sequence 1 Cycle from End IRQ.
Set this bit to request an interrupt on the event the sequencer is currently running andhas just one repetition remaining before completion.
0 IRQ not generated 1 tone pair before Sequence ends
1 IRQ generated 1 tone pair before sequence ends

13 BENDIRQ(R/W)

Tone B End IRQ.
Set this bit to request an interrupt on the event BEEP_TONEB stops playing
0 IRQ not generated at end of Tone B
1 IRQ generated at end of Tone B

12 BSTARTIRQ(R/W)

Tone B Start IRQ.
Set this bit to request an interrupt on the event BEEP_TONEB starts playing
0 IRQ not generated at start of Tone B
1 IRQ generated at start of Tone B

19–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 BEEP Register Descriptions

Table 19-2: BEEP_CFG Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
11 AENDIRQ(R/W)

Tone A End IRQ.
Set this bit to request an interrupt on the event Tone A stops playing.
0 IRQ not generated at end of Tone A
1 IRQ generated at end of Tone A

10 ASTARTIRQ(R/W)

Tone A Start IRQ.
Set this bit to request an interrupt on the event Tone A starts playing.
0 IRQ not generated at start of Tone A
1 IRQ generated at start of Tone A

8 EN(RX/W)

Beeper Enable.
Write 0x1 to this bit to start playing Tone A. Plays a single tone if
BEEP_CFG.SEQREPEAT = 0, else plays a series of two-tone sequences. Write 0x0 to
this bit at any time to end audio playback. Reading this bit always returns 0x0, read
BEEP_STAT.BUSY to determine if the beeper is currently enabled.
0 Disable module
1 Enable module

7:0 SEQREPEAT(R/W)

Beeper Sequence Repeat Value.
When the beeper transitions to an enabled state, the value of this field selects whether
the beeper runs in Pulse mode or Sequence mode. If 0x0, the beeper runs in Pulse
mode and plays back only one tone (Tone A) before being disabled. If a non-zero value
is written to this field, the beeper runs in Sequence mode and plays the two-tone sequence (Tone A and Tone B) the requested number of times before being disabled.
Updates to this field have no affect while running in Pulse mode. Updates to this fieldtake immediate affect when running in Sequence mode.
0 Enabling will start in Pulse mode.
1-254 Enabling will start in Sequence mode and play a finite
number of notes.
255 Enabling will start in Sequence mode and play forever
until stopped by user code.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

19–9ADuCM4050 BEEP Register Descriptions

Beeper Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SEQENDED (R/W1C)
Sequencer Has Ended

SEQREMAIN (R)Remaining Tone-pair Iterations to Playin Sequence Mode

SEQNEAREND (R/W1C)
Sequencer Last Tone-pair Has Started

BUSY (R)
Beeper is Busy

BENDED (R/W1C)
Tone B Has Ended

ASTARTED (R/W1C)
Tone A Has Started

BSTARTED (R/W1C)
Tone B Has Started

AENDED (R/W1C)
Tone A Has Ended

Figure 19-4: BEEP_STAT Register Diagram
Table 19-3: BEEP_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 SEQENDED(R/W1C)
14 SEQNEAREND(R/W1C)

13 BENDED(R/W1C)
12 BSTARTED(R/W1C)
11 AENDED(R/W1C)
10 ASTARTED(R/W1C)

19–10

Sequencer Has Ended.
This bit is asserted whenever the beeper stops running in Sequence mode. It is cleared
only by user code writing 0x1 to this location.
Sequencer Last Tone-pair Has Started.
This bit is asserted whenever the beeper is running in Sequence mode and has only one
iteration of sequences left to play. It is cleared only by user code writing 0x1 to thislocation.
Tone B Has Ended.
This bit is asserted whenever the beeper stops playing Tone B. It is cleared only by user
code writing 0x1 to this location.
Tone B Has Started.
This bit is asserted whenever the beeper begins playing Tone B. It is cleared only byuser code writing 0x1 to this location.
Tone A Has Ended.
This bit is asserted whenever the beeper stops playing Tone A. It is cleared only by user
code writing 0x1 to this location.
Tone A Has Started.
This bit is asserted whenever the beeper begins playing Tone A. It is cleared only byuser code writing 0x1 to this location.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 BEEP Register Descriptions

Table 19-3: BEEP_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
8 BUSY(R/NW)

Beeper is Busy.
This bit is asserted after enabling the beeper module by writing 0x1 to
BEEP_CFG.EN. The bit is cleared when the module completes its operation or whenuser code writes 0x0 to BEEP_CFG.EN.
0 Beeper is currently disabled
1 Beeper is currently enabled

7:0 SEQREMAIN(R/NW)

Remaining Tone-pair Iterations to Play in Sequence Mode.
After a sequence has ended, this field resets to BEEP_CFG.SEQREPEAT. This field
is updated as the beeper plays back audio in Sequence mode. Each two-tone iteration
starts by playing Tone A and ends by playing Tone B. This field is updated at the conclusion of Tone B playback and therefore during the last iteration will return 0x1 during Tone A and Tone B playback. When playing an infinite sequence this field always
returns 0xFF.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 BEEP Register Descriptions

Tone A Data
Tone A is the first tone to play in Sequence Mode, and the only tone to play in Pulse Mode. Writing 0x0 to the
BEEP_TONEA.DUR field while Tone A is playing will immediately terminate the tone. All other writes to
BEEP_TONEA affect the next play back of the tone only and do not affect the currently playing tone.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

DIS (R/W)
Output Disable

DUR (R/W)
Tone Duration

FREQ (R/W)
Tone Frequency

Figure 19-5: BEEP_TONEA Register Diagram
Table 19-4: BEEP_TONEA Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 DIS(R/W)

Output Disable.
This bit is set to disable the beeper output while Tone A is playing. The beeper holds
both of its two output pins at logic 0 when disabled. Writes to this bit take effect immediately if Tone A is currently playing.
0 Output enabled
1 Output disabled, no DC potential across output pins

14:8 FREQ(R/W)

Tone Frequency.
This field defines the frequency for Tone A as integer divisions of the 32.768kHz
clock. The values 0 through 3 are interpreted as 'rest-tone' and will result in no oscillations of the beeper output pins. All other values are directly used to divide the 32kHz
input clock. Writes to this field immediately affect the output of Tone A if currently
playing.
0-3 Rest tone (duration but no oscillation)
4-127 Oscillation at 32kHz/(FREQ)

7:0 DUR(R/W)

Tone Duration.
This field defines the duration for Tone A in 4ms increments. Writing a value of 0x0
will immediately terminate Tone A if currently playing. Writing a value of 0xFF willcause Tone A to play forever once started, or until user code terminates the tone. Onlya write of 0x0 will affect a currently playing tone, all other values written will be used
only the next time Tone A is played.
0-254 Tone will play for (DUR)*4ms period
255 Tone will play for infinite duration

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ADuCM4050 BEEP Register Descriptions

Tone B Data
Tone B is the second tone to play in Sequence Mode, and is not played Pulse Mode. Writing 0x0 to the
BEEP_TONEB.DUR field while Tone B is playing will immediately terminate the tone. All other writes to
BEEP_TONEB affect the next play back of the tone only and do not affect the currently playing tone.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

DIS (R/W)
Output Disable

DUR (R/W)
Tone Duration

FREQ (R/W)
Tone Frequency

Figure 19-6: BEEP_TONEB Register Diagram
Table 19-5: BEEP_TONEB Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 DIS(R/W)

Output Disable.
This bit is set to disable the beeper output while Tone B is playing. The beeper holds
both of its two output pins at logic 0 when disabled. Writes to this bit take effect immediately if Tone B is currently playing.
0 Output enabled
1 Output disabled, no DC potential across output pins

14:8 FREQ(R/W)

Tone Frequency.
This field defines the frequency for Tone B as integer divisions of the 32.768kHz
clock. The values 0 through 3 are interpreted as 'rest-tone' and will result in no oscillations of the beeper output pins. All other values are directly used to divide the 32kHz
input clock. Writes to this field immediately affect the output of Tone B if currently
playing.
0-3 Rest tone (duration but no oscillation)
4-127 Oscillation at 32kHz/(FREQ)

7:0 DUR(R/W)

Tone Duration.
This field defines the duration for Tone B in 4ms increments. Writing a value of 0x0
will immediately terminate Tone B if currently playing. Writing a value of 0xFF willcause Tone B to play forever once started, or until user code terminates the tone. Onlya write of 0x0 will affect a currently playing tone, all other values written will be used
only the next time Tone B is played.
0-254 Tone will play for (DUR)*4ms period
255 Tone will play for infinite duration

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ADC Subsystem

20 ADC Subsystem

The ADuCM4050 MCU incorporates a fast, multichannel, 12-bit analog-to-digital converter (ADC) capable of operating up to a maximum of 1.8 MSPS. The ADC controller can be setup to perform a series of conversions andtransfer data to the system using a dedicated DMA channel. This allows the MCU to be in the Flexi mode (minimizing the overall device power consumption) or perform other tasks.

ADC Features
The ADC has the following features:• 12-bit resolution.
• Programmable ADC update rate up to 1.8 MSPS.
• Integrated input mux that supports up to eight channels.
• Supports temperature sensing.
• Supports battery monitoring.
• Software selectable on-chip reference voltage generation: 1.25 V, 2.5 V, and VBAT.
• Software selectable internal or external reference.
• Auto cycle mode: Ability to automatically select a sequence of input channels for conversion.
• Averaging function: Converted data on single or multiple channels can be averaged over up to 256 samples.
• Alert function: Internal digital comparator for ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3
channels. An interrupt can be generated if the digital comparator detects an ADC result above or below theuser-defined threshold.
• Supports dedicated DMA channel.
• Each channel, including temperature sensor and battery monitoring, has a dedicated data register for conversion result.

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ADC Functional Description

ADC Functional Description
This section provides information on the function of the ADC Subsystem used by the ADuCM4050 MCU.

ADC Subsystem Block Diagram
The figure shows the ADC subsystem.

Ref Buffer
Vref

ACLK

VREFVBAT/VREFP_ADC
VBAT_ADCAPBADCADC Controller

DMA

ADC0_VIN7 - ADC0_VIN0
CORE IRQTMP_OUT
Temperature
SensorFigure 20-1: ADC Subsystem

ADC Subsystem Components
The ADC subsystem consists of the following components:• ADC core
• ADC digital controller• Reference buffer• Temperature sensor

ADC Voltage Reference Selection
The ADC can use an internal voltage reference, battery voltage, or external voltage reference for its operation.
Internal Sources
The ADuCM4050 MCU integrates a reference buffer that can generate either 1.25 V or 2.5 V as reference using the
integrated bandgap reference. This internal reference buffer is enabled by setting the ADC_CFG.REFBUFEN bit.
When using internal reference buffer, a 4.7 μF capacitor in parallel to a 0.1 μF capacitor is recommended to beplaced as close as possible to the VREF_ADC pin.

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ADC Subsystem Components

Battery voltage (VBAT) can also be selected as internal reference by setting the ADC_CFG.VREFVBAT and
ADC_CFG.VREFVBAT_DEL bits.
The minimum VBAT voltage for selecting 2.5 V as internal reference is 2.75 V.
Low Power Mode
For conversion rate less than 100 KSPS, the reference buffer offers a capability where it consumes less current whencompared with the regular operation. This mode of operation can be enabled by setting the ADC_CFG1.RBUFLP
bit.
Sink Enable
If an external bias voltage is generated that requires an inverting configuration, the reference buffer can sink current,
as shown in ADC Subsystem Reference Buffer with an External Bias figure. A 50 μA sink current capability at 1.25
V reference, and 100 μA sink current capability at 2.5 V reference is provided in the ADC subsystem. This can be
enabled by setting the ADC_CFG.SINKEN bit.
The figure shows an example of the ADC reference buffer in current sink configuration from an external bias voltage.
10 KΩ

10 KΩ

VREFP_ADC

ISINK

VBIAS

MCU
2V

Figure 20-2: ADC Subsystem Reference Buffer with an External Bias

External Voltage Reference
To select an external reference voltage source as ADC reference, clear the ADC_CFG.REFBUFEN and
ADC_CFG.VREFVBAT bits, and connect the external voltage reference across VREFP_ADC and GND_VREFADC pins. VBAT_ADC can be connected externally to VREFP_ADC, to be used as a reference voltage. Ensurethat the external voltage reference is not greater than VBAT. If using external voltage reference, a 0.1 μF capacitor isrecommended to be placed as close as possible to the VREFP_ADC pin.
The Reference Voltage Selection table shows the programming of the various bit fields in the ADC_CFG register toperform reference voltage selection.
Table 20-1: Reference Voltage Selection
Voltage

REFBUFEN

VREFSEL

VREFVBAT

1.25 V

1

1

0

2.5 V

1

0

0

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ADC Subsystem Components

Table 20-1: Reference Voltage Selection (Continued)
Voltage

REFBUFEN

VREFSEL

VREFVBAT

External Voltage Reference

0

X

0

VBAT

0

X

1

NOTE: External Voltage Reference is connected to the ADC using VREFP_ADC pin. While using internal reference or VBAT as ADC reference, the VREFP_ADC pin must be left floating and it must not be connected to any
voltage source or ground.
If the ADC and Reference buffers are not used, VREFP_ADC pin can be left floating (without connecting it to an
external capacitor).

Digital Offset Calibration
An offset correction block is used to measure and correct the offset error of the reference voltage of the ADC. For
accuracy, calibration is required.
After the ADC is powered up, to start a new calibration cycle, the ADC_CFG.STARTCAL bit must be set after
ADC is ready. The ADC_STAT.CALDONE bit is set when calibration is done. Interrupt can be enabled by setting
the ADC_IRQ_EN.CALDONE bit. The ADC_CAL_WORD register is loaded with a new calibration word at the endof calibration. This register is retained in the Hibernate mode. The ADC_CAL_WORD register can also be programmed by the user.
NOTE: If the ADC_CAL_WORD register is programmed during conversion, the new calibration word is consideredfrom the next conversion cycle.

Powering the ADC
The ADC, reference buffer, and temperature sensor are powered down at reset. The user has to explicitly power up
each of these blocks. The power-up sequence depends on the internal or external reference used.
Using External Reference or VBAT as Reference
To use the external reference as the ADC reference, the following sequence must be employed at power-up:
1. Set the ADC_CFG.PWRUP bit to power up the ADC.
2. Set ADC_PWRUP.WAIT bits to generate at least 20 μs wait time with respect to the PCLK frequency set in the
CLKG_CLK_CTL1 register.
3. Set the ADC_CFG.VREFVBAT bit to use VBAT as reference voltage.
4. Wait for at least 700 μs and then set the ADC_CFG.VREFVBAT_DEL bit.
5. Assert the ADC_CFG.EN bit and enable the ADC.

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ADC Subsystem Components

6. Wait for interrupt and write 1 to clear the ADC_STAT.RDY bit. Interrupt must be enabled by setting the
ADC_IRQ_EN.RDY bit.
7. Set the ADC_CFG.STARTCAL bit to start the calibration cycle.
8. Wait for ADC_STAT.CALDONE bit to go high.
The ADC subsystem is ready for operation.
Using Internal Reference Buffer
To use the internal reference buffer, the following sequence must be employed at power-up:
1. Set the ADC_CFG.PWRUP bit to power up the ADC.
2. Set the ADC_PWRUP.WAIT field to generate at least 20 μs wait time with respect to the PCLK frequency set
in the CLKG_CLK_CTL1 register.
3. Select 1.25 V or 2.5 V as reference voltage using the ADC_CFG.VREFSEL bit.
4. Assert the ADC_CFG.REFBUFEN bit.
5. Assert the ADC_CFG.EN bit.
6. Wait for at least 3.5 ms.
One of the general-purpose timers can be used to wait for 3.5 ms. During this wait period, the device can be
put in Flexi mode to save system power, and woken up by genetal purpose timer interrupt.
7. Poll the ADC_STAT.RDY bit, once set, the ADC is ready to use. Write 1 to clear the ADC_STAT.RDY bit.
The interrupt for this bit must be enabled by setting the ADC_IRQ_EN.RDY bit.
8. Set the ADC_CFG.STARTCAL bit to start the calibration cycle.
9. Wait for ADC_STAT.CALDONE bit to go high.
The ADC is ready for conversion.

Hibernate
All components of the ADC subsystem are automatically powered down when the part goes to hibernate. This isdone to keep the power consumption minimum. After waking up from hibernate, all components must be explicitly
powered up and ready before a conversion can take place, as explained in Powering the ADC section.
However, while the ADC is in the Hibernate mode, the calibration coefficients are retained in the internal registersof the ADC. In this way, the ADC can wake up from hibernate, and a calibrated conversion cycle can be started
immediately after the wake-up time has elapsed. A new calibration cycle, if required, can be run by asserting the
ADC_CFG.STARTCAL bit.
A new calibration cycle is recommended at wake-up if the system is in hibernate mode for an extended period, andthe operating conditions of the ADC, temperature, and reference voltage may have changed since the last calibration
cycle.
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ADC Subsystem Components

The following register fields are retained when the chip goes into hibernate mode:• ADC_CFG.VREFSEL• ADC_CFG.SINKEN• ADC_PWRUP.WAIT• ADC_CAL_WORD.VALUE• ADC_CNV_TIME.SAMPTIME• ADC_AVG_CFG.FACTOR• ADC_AVG_CFG.OS• ADC_LIMx_LO.VALUE• ADC_LIMx_HI.VALUE• ADC_HYSx.VALUE• ADC_HYSx.MONCYC• ADC_CFG1.RBUFLPNOTE: If a conversion is ongoing prior to the part going to hibernate mode, that conversion does not resume after
the part wakes up.
The ADC must be disabled before going to the Hibernate or Shutdown mode by clearing the ADC_CFG.EN bit.

Sampling and Conversion TimeThe ADC can be in one of the following phases:• Acquisition Phase: During the acquisition phase, the capacitor arrays are connected directly to the inputs to getfully charged. The minimum required acquisition time depends on the output impedance. The timing for thisphase is programmed in the ADC_CNV_TIME.SAMPTIME bit in terms of number of clock cycles.
Acquisition phase is (SAMPTIME + 1) ACLK cycles.
The time depends on the SAMPTIME value and selected clock frequency (ACLK).
ACLK frequency = System clock frequency / ACLKDIVACLKDIV can be programmed in the CLKG_CLK_CTL1.ACLKDIVCNT register (9 bits).
• Conversion Phase: At the end of the acquisition phase, the conversion phase is initiated. The conversion iscompleted by successive approximation and takes 13 ACLK cycles.
NOTE: The time between two conversions must not exceed 100 μs or in other words, the minimum sampling
rate of the ADC is 10 KSPS.

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ADC Subsystem Components

If ADC needs to be operated at a sampling rate less than 10KSPS (sampling time more than 100 μs), dummy
conversion must be performed in between the samples. To match the required throughput, discard the dummy
samples.
Acquisition

Conversion

SAMPTIME+1

13

Acquisition

Sample period = SAMPTIME + 14
Where:SAMPTIME is the sampling time (ADC_CNV_TIME.SAMPTIME)
Time units in ACLK cycles

Figure 20-3: Oversampling Disabled and Zero Delay

Acquisition 1

Conversion 1

SAMPTIME+1

13

Acquisition 2

Acquisition N

Conversion N

Acquisition 1

Delay

Acquisition 1

Sample period = N * (SAMPTIME + 14)
Where:SAMPTIME is the sampling time (ADC_CNV_TIME.SAMPTIME)
N is the oversampling rate (ADC_AVG_CFG.FACTOR)
Time units in ACLK cycles

Figure 20-4: Oversampling Enabled and Zero Delay

Acquisition

Conversion

Delay

SAMPTIME+1

13

DLY+2

Acquisition

Sample period = SAMPTIME + DLY +16
Where:SAMPTIME is the sampling time (ADC_CNV_TIME.SAMPTIME)DLY is the delay - 2 * (ADC_CNV_TIME.DLY)
Time units in ACLK cycles

Figure 20-5: Oversampling Disabled and Delay > 0
Acquisition 1

Conversion 1

SAMPTIME+1

13

Acquisition 2

Acquisition N

Conversion N

DLY+2
Sample period = (N * (SAMPTIME + 14)) + (DLY +2)

Where:SAMPTIME is the sampling time (ADC_CNV_TIME.SAMPTIME)
N is the oversampling rate (ADC_AVG_CFG.FACTOR)DLY is the delay - 2 * (ADC_CNV_TIME.DLY)
Time units in ACLK cycles

Figure 20-6: Oversampling Enabled and Delay > 0

For a single channel:• If ADC_CNV_TIME.DLY = 0,
ADC Sampling Rate =(Root_clock / ACLKDIV)(14 + SAMPTIME) x (Oversampling Rate)

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ADC Subsystem Components

Where,
Root_clock is the system clock at which the MCU operates
Oversampling Rate is the numbers of ADC samples to be oversampled and averaged to obtain a required resolution. It can take values from 1 to 256 in steps of power of 2.
• If ADC_CNV_TIME.DLY > 0,
ADC Sampling Rate =(Root_clock / ACLKDIV)((14 + SAMPTIME) x (Oversampling Rate))+ (DLY + 2)

For example, with a 26 MHz Root_clock, ACLKDIV of 10, SAMPTIME of 6 ACLK cycles, DLY of 4 ACLK cycle,
and an Oversampling Rate of 1, the ADC Sampling Rate is 100 KSPS
For a required resolution of 14 bits in the above example, the Oversampling Rate is 16 that gives an ADC Sampling
Rate of 7.975 KSPS.
For mutiple channels:• If ADC_CNV_TIME.DLY = 0,
ADC Sampling Rate =(Root_clock / ACLKDIV)(14 + SAMPTIME) x (Oversampling Rate) x (No of Channels)• If ADC_CNV_TIME.DLY > 0,
ADC Sampling Rate =(Root_clock / ACLKDIV)((14 + SAMPTIME) x (Oversampling Rate) x (No of Channels)) + (DLY + 3)

Operation
The ADC controller supports several use cases.
Single Channel Mode
The ADC can be configured to convert on a particular channel by selecting one of the channels using the
ADC_CNV_CFG.SEL bits. The ADC converts analog input, provides the CNV_DONE interrupt, and stores theresult in the corresponding CHx_OUT register. A channel can be enabled by writing to the specific bit in the
ADC_CNV_CFG.SEL bits. For example, to enable channel 2, set the ADC_CNV_CFG.SEL[2] bit. Ensure that
only one bit (out of SEL[7:0], BAT, TMP, TMP2) is set for conversion on single channel(ADC_CNV_CFG.AUTOMODE = 0).
To perform multiple conversions on a selected channel, set the ADC_CNV_CFG.MULTI bit. An interrupt is generated if enabled, and the corresponding bit in the ADC_STAT register is set after each conversion. The conversion
output is stored in the CHx_OUT register.

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ADC Subsystem Components

If the result is not read from the output register and the status bit is not cleared before the next conversion ends, theconversion output overflows and new result is stored in the CHx_OUT register, resulting in data loss.
It is recommended to use DMA for multiple conversions. Delay can also be introduced between successive conversions.
NOTE: After the desired number of conversions are complete, the ADC_CNV_CFG.MULTI bit must be cleared tostop the ADC subsystem from converting.
Auto Cycle Mode
Auto cycle mode reduces the MCU overhead of sampling and reading individual channel registers. It allows the user
to select a sequence of ADC input channels and provides a single interrupt when conversions on all channels end.
Temperature sensing and battery monitoring cannot be included in the auto cycle mode. Auto cycle mode is enabled
by setting the ADC_CNV_CFG.AUTOMODE bit.
Conversions are performed starting from the lowest numbered channel to the highest numbered channel of thechannels enabled. Output for each channel is stored in the respective CHx_OUT register, and the orresponding bitsin the ADC_STAT register are set after conversion on all channels (one sequence) is completed.
To initiate multiple conversions on selected channels, enable the ADC_CNV_CFG.MULTI bit. An interrupt is generated after each sequence completes. Delay can be introduced between successive sequences. It is recommended touse DMA for multiple conversions due to the amount of data that can be generated.
NOTE: After the desired number of conversions are complete, the ADC_CNV_CFG.MULTI bit must be cleared tostop the ADC subsystem from converting. ADC_CNV_CFG.MULTI must be low for a minimum of one ACLK
cycle. Status bits for conversion done, alert, and overflow must be cleared before starting a next conversion.
Delay Between Conversions
The ADC_CNV_TIME.DLY bits can be programmed to set the delay between completing one sequence of channels and starting another sequence, or multiple conversions on a single channel. This delay is in terms of number of
ACLK cycles.
MULTI
CNV
ACQ1

CONV1
SAMP1

Delay

ACQ2

CONV2

Delay

SAMP2

ACQ3

CONV3
SAMP3

Figure 20-7: Delay Between Conversions on Single Channel in Multiple Conversions Mode

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ADC Subsystem Components

MULTI

AUTO MODE

CNV
ACQ

CONV
CH0

CONV

ACQ

CH1

Delay

ACQ

CONV
CH0

ACQ

CONV
CH1

Figure 20-8: Delay Between Sequences in Auto Cycle ModeDMAA DMA channel can be used to reduce the MCU overhead by moving the ADC results directly into SRAM with asingle interrupt asserted after the required number of ADC conversions are completed. DMA can be enabled using
the ADC_CNV_CFG.DMAEN bit. The conversion result must be read from the ADC_DMA_OUT.RESULT bits.
The DMA channel can be programmed for a given number of conversions. The MCU can be in Flexi mode during
this period, until the programmed number of conversions is completed and the DMA done interrupt is received. For
more information, refer to the Programming Flow section.
Interrupts
The ADC controller has an interrupt associated with it. The interrupt status register indicates the source of an interrupt. When DMA is not used, the ADC controller generates data interrupts after a conversion.
NOTE: All interrupts are Write One to Clear.
Conversion
An interrupt can be generated after each conversion is complete by setting the ADC_IRQ_EN.CNVDONE bit. Corresponding DONE bit is set in the ADC_STAT register after the completion of a conversion.
Overflow
If output data is not read from the output register by the user or DMA before the next conversion is performed on
the channel, it is overwritten. The overflow bit is set for the respective channel in the ADC_OVF register and interrupt is generated. It remains set until it is cleared by the user. This interrupt must be enabled by the user by setting
the ADC_IRQ_EN.OVF bit.
NOTE: The ADC_CNV_CFG.SEL bits must remain unchanged when a conversion is being done.

Programming Flow
After powering up and calibrating (if required), the ADC is ready for conversion.

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ADC Subsystem Components

Single Conversion on Single Channel
This mode is used to perform a single conversion on a selected channel. The ADC_CNV_CFG.SINGLE bit must
set to 1 to perform the conversion. This bit works as a write one to action bit and reads as zero. DMA is not recommended for this mode, as only a single data needs to be read. The conversion result can be read from the RESULT
bits in the corresponding Channel Output register.
The following steps describe how to program the ADC for a single conversion on a single channel (say AIN2):
1. Set ADC_CNV_CFG.SEL = 0x2 and select channel 2 for conversion.
2. Set ADC_IRQ_EN.CNVDONE = 0x1 to enable interrupt when conversion is done.
3. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
4. Interrupt is generated and STAT[2] is set when conversion is done.
5. Set cnv_result = ADC_CH0_OUT.RESULT to read the conversion result.
6. Set ADC_STAT.DONE2 = 0x1 to clear the interrupt.
CLK

SINGLE
DONE2

CH2_OUT[11:0]

Figure 20-9: Single Conversion on Single Channel

Multiple Conversion on Single Channel
The ADC_CNV_CFG.MULTI bit is used to perform multiple conversions on the selected channel. The conversions
continue until this bit is deasserted. Use DMA for this mode. This mode is similar to performing multiple back-toback single conversions on the channel with the added overhead of reading the data (else, it is overwritten) and restarting the conversion. When using DMA, the number of conversions to be done must be programmed in the
count descriptor of the DMA.
The following steps describe how to program the ADC for a multiple conversion on a single channel (say
ADC0_VIN2):
1. Set ADC_CNV_CFG.SEL = 0x2 and select channel 2 for conversion.
2. Set the following DMA configurations:a. DMA count = 2 for three conversions (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT register
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ADC Subsystem Components

c. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result.
e. Program the required increment (half-word) in the DMA channel control data structure.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA.
4. Set ADC_CNV_TIME.DLY = 0x14 and set the delay between two conversions.
5. Set ADC_CNV_CFG.MULTI = 0x1 to start the conversion.
dma_done interrupt is generated after three conversions (count = 2).
6. Set ADC_CNV_CFG.MULTI = 0 to clear MULTI and disable further conversions in ISR.
The conversion results can be read from the SRAM.
MULTI
CNV
ACQ1

CONV1

Delay

ACQ2

SAMP1

CONV2

Delay

SAMP2

ACQ3

CONV3
SAMP3

dma_done

Figure 20-10: Multiple Conversion on Single Channel

Single Conversion in Auto Cycle Mode
Set the appropriate ADC_CNV_CFG.SEL channel bits to enable the channels included in the sequence.
The following steps describe how to program the ADC for a single conversion on a series of channels in auto cycle
mode (say ADC0_VIN2, ADC0_VIN4, and ADC0_VIN7):
1. Set ADC_CNV_CFG.SEL = 0x94.
2. Set the following DMA configurations:a. DMA count = 2, for three conversions (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT registerc. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result
e. Program the required increment (half-word) in the DMA channel control data structure.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA (if used).
4. Set ADC_CNV_CFG.AUTOMODE = 0x1.

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ADC Subsystem Components

5. Set ADC_CNV_TIME.DLY = 0x0.
6. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
dma_done is generated after conversion.
The conversion results can be read from the SRAM or respective Channel Out registers.
SINGLE

AUTO MODE
CNV
ACQ

CONV

ACQ

CH0

CONV
CH1

ACQ

CONV
CH7

dma_done

Figure 20-11: Single Conversion in Auto Cycle Mode

Multiple Conversions in Auto Cycle Mode
Program the number of sequences multiplied by number of channels selected to be run in the count descriptor of
the DMA.
The following steps describe how to program the ADC for a multiple conversion on a series of channels in auto
cycle mode (say ADC0_VIN0, ADC0_VIN2, and ADC0_VIN3):
1. Set ADC_CNV_CFG.SEL = 0x0D.
2. Set ADC_CNV_TIME.DLY = 0x7E.
3. Set the following DMA configurations:a. Source Address = Address of ADC_DMA_OUT registerb. Source Size = Halfword
c. Destination address of DMA as SRAM memory location address to store the conversion resultd. Program the required increment (half-word) in the DMA channel control data structure.
e. count = 5, for two sequences
4. Set ADC_CNV_CFG.DMAEN = 0x1.
5. Set ADC_CNV_CFG.MULTI = 0x1 to start the conversion.
dma_done is generated after conversion.
6. Set ADC_CNV_CFG.MULTI = 0 to disable further conversions in ISR.
The conversion results can be read from the SRAM.
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ADC Subsystem Components

MULTI
AUTO MODE
CNV
ACQ

CONV
CH0

ACQ

CONV

Delay

ACQ

CH3

CONV
CH0

ACQ

CONV
CH3

dma_done

Figure 20-12: Multiple Conversions in Auto Cycle Mode

Temperature Sensor
The ADC subsystem provides a temperature sensor that measures die temperature. To enable the temperature sensing, set the ADC_CFG.TMPEN bit. Wait for 300 μs before starting the conversion. The temperature sensor can be
enabled along with the ADC or the reference buffer to save time.
This temperature sensor is not designed for use as an absolute ambient temperature calculator. It is used as an approximate indicator of temperature of the ADuCM4050 MCU die.
Program the ADC_CNV_TIME.SAMPTIME bit to provide an acquisition time of at least 65 μs.
The following steps describe how to measure temperature:
1. Set the ADC_CNV_CFG.TMP bit to 1.
2. Set the ADC_CNV_CFG.SINGLE bit.
3. The ADC_STAT.TMPDONE bit is set after conversion.
Interrupt is given if the ADC_IRQ_EN.CNVDONE bit is set.
4. Read the result from the ADC_TMP_OUT register.
5. Set the ADC_CNV_CFG.TMP2 bit to 1.
6. Set the ADC_CNV_CFG.SINGLE bit to 1.
7. The ADC_STAT.TMP2DONE bit is set after conversion.
Interrupt is given if the ADC_IRQ_EN.CNVDONE bit is set.
8. Read the result from ADC_TMP2_OUT register after conversion.
Auto mode can also be used.
Set the ADC_CNV_CFG.TMP and ADC_CNV_CFG.TMP2 bits.
Start the conversion by setting the ADC_CNV_CFG.SINGLE bit or ADC_CNV_CFG.MULTI bit (for multiple
conversions).

20–14

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ADC Subsystem Components

Temperature can be calculated as:
T (⁰C) = [[[ADC_TMP_OUT - (Offsetcode * 1.25 / Vref )] / (ADC_TMP2_OUT + (RG * ADC_TMP_OUT)] * [Rvirtualreference / idealsensitivity]] - 273.15
where,• RG = 1.1829• Rvirtualreference = 1.2256• idealsensitivity = 0.0012411• Offsetcode = 161
For example, if ADC_TMP_OUT is 1620 and ADC_TMP2_OUT is 2102, the temperature is 85⁰C.

Battery Monitoring
To enable battery monitoring, the ADC_CNV_CFG.BAT bit must be set. The ADC_CNV_TIME.SAMPTIME bit
must be set to obtain an acquisition time of 500 ns. Set the ADC_CNV_CFG.SINGLE bit to start conversion. The
ADC converted output can be read from the ADC_BAT_OUT register, depending on the conversion mode.
Conversion done interrupt can be enabled for getting an interrupt after conversion is done. Clear the
ADC_CNV_CFG.BAT bit after conversion is done to reduce power consumption.
To convert ADC result to battery voltage:
VBAT = 4 * ADC_BAT_OUT * Vref / (212 – 1)
where,• VBAT is battery voltage• Vref is reference voltage selected (preferred, 1.25 V)• ADC_BAT_OUT is ADC converted output

Oversampling
Resolution greater than 12-bit can be achieved by oversampling. Oversampling can be enabled by writing the
ADC_AVG_CFG.OS and ADC_AVG_CFG.EN bits to 1. When oversampling is enabled, the ADC samples multiple times and averages the result to provide an output with required resolution in the CHx_OUT register. The value
to be programmed in the ADC_AVG_CFG.FACTOR field for a required resolution is given in the Factor for Enhanced Resolution table.

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ADC Subsystem Components

Table 20-2: Factor for Enhanced Resolution
Resolution Required

AVG_CFG_FACTOR to be programmed

Number of Samples Used

13-bith02

414-bith08

1615-bith20

64

16-bith80

256

Averaging Function
When performing multiple conversions, averaging can be enabled on all selected channels. Averaging can be performed over a maximum of 256 samples, in the steps of power of 2 (that is, 2, 4, 8, 16…256). The accumulated
value is truncated to result in a 12-bit average output in the CHx_OUT register. Averaging can be enabled by writing
the ADC_AVG_CFG.OS bit to 0 and the ADC_AVG_CFG.EN bit to 1.
Averaging factor is to be programmed as factor/2 in the ADC_AVG_CFG.FACTOR bits.
For example, to average 64 samples, program ADC_AVG_CFG.FACTOR as 32 (0x20). An interrupt is generated
after averaging is complete.
In case of auto cycle mode, DMA can be enabled.
For example, to average over 16 samples, 16 values are converted, added, and then divided by 16.
If averaging is enabled in auto mode (for multiple channels), programmed number of conversions are done on one
channel (and averaged) before moving to the next channel.
Averaging for Multiple Conversions on Single Channel
The following steps describe how to perform averaging over multiple conversions on a single channel (say
ADC0_VIN2):
1. Set ADC_CNV_CFG.SEL = 0x2 and select Channel 2 for conversion.
2. Set ADC_IRQ_EN.CNVDONE = 0x1 to enable interrupt when conversion is done.
3. Set ADC_AVG_CFG.OS = 0.
4. Set ADC_AVG_CFG.EN = 0x1 to enable averaging.
5. Set ADC_AVG_CFG.FACTOR = 0x20 to average 64 samples.
6. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
7. Interrupt is generated and ADC_STAT.DONE2 is set when conversion is done.
8. Set cnv_result = ADC_CH2_OUT.RESULT to read the conversion output.
9. Set ADC_STAT.DONE2 = 0x1 to clear the interrupt.

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ADC Subsystem Components

Averaging for Multiple Conversions in Auto Cycle Mode
The following steps describe how to perform averaging over multiple conversion on a series of channels in auto cyclemode:
1. Set ADC_CNV_CFG.SEL = 0x30 and select Channel 5 and Channel 4 for conversion.
2. Set the following DMA configurations:a. DMA count = 1, for averaging ones over two channels (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT registerc. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result
e. Program the required increment in the destination address.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA (if used).
4. Set ADC_CNV_CFG.AUTOMODE = 0x1 to start the conversion.
5. Set ADC_AVG_CFG.OS = 0.
6. Set ADC_AVG_CFG.EN = 0x1.
7. Set ADC_AVG_CFG.FACTOR = 0x08 to average 16 samples.
8. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
dma_done is generated after conversion.
The conversion result can be read from the SRAM or respective Channel Out registers.
NOTE: Averaging/Over sampling and monitoring cannot be enabled together. They are mutually exclusive.

ADC Digital Comparator
A digital comparator is provided to allow an interrupt to be triggered if the ADC input is above or below a programmable threshold. Input channels ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3 can be used withthe digital comparator. This can be used to continuously monitor if any (or a set) of these channels stay within normal range of values. Comparators can be enabled only in multiple conversion mode, either on single channel or in
auto cycle mode. Overflow indication is disabled, as the user is not expected to read the results during monitoring.
To set up the ADC digital comparator:• Lower threshold value must be written to 12-bit ADC_LIMx_LO.VALUE field. To enable comparison withlower limit, the EN bit of the corresponding register must be set.
• Higher threshold value must be written to 12-bit ADC_LIMx_HI.VALUE field. To enable comparison, theEN bit of the corresponding register must be set.

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20–17

ADC Subsystem Components• Hysteresis value can also be given for each of these channels in the ADC_HYSx.VALUE bit . It must be enabled by setting the ADC_HYSx.EN bit.
• An alert is indicated if the ADC result crosses the threshold (ADC_LIMx_LO.VALUE or
ADC_LIMx_HI.VALUE) and does not return to its normal value within number of clock cycles programmedin the ADC_HYSx.MONCYC bit.
The Normal value is defined as:• For lower threshold: Above ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE• For higher threshold: Below ADC_LIMx_HI.VALUE – ADC_HYSx.VALUE
If the converted result is above ADC_LIMx_HI.VALUE, it is monitored for the next MONCYC conversions.
If the converted results during monitoring remain above ADC_LIMx_HI.VALUE - ADC_HYSx.VALUE, an alert
is indicated.
If the converted result during monitoring is below ADC_LIMx_HI.VALUE – ADC_HYSx.VALUE, alert is notindicated and monitoring stops.
Similarly, if the converted result is below ADC_LIMx_LO.VALUE, it is monitored for the next MONCYC conversions.
If the converted results during monitoring remain below ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE, an alert
is indicated.
If the converted result during monitoring is above ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE, alert is notindicated and monitoring stops.
The ADC_ALERT register can be read to determine the source of alert. An interrupt is generated if the
ADC_IRQ_EN.ALERT bit is set.

ADC_LIMx_HI.VALUE
ADC_LIMx_HI.VALUE - ADC_HYSx.VALUE

HYS

ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE
HYS
ADC_LIMx_LO.VALUE

Figure 20-13: Low-High Limits and Hysteresis

20–18

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ADC Subsystem Components

ADC_LIM0_HI

12’h2FF

ADC_HYS0.VALUE

9’h010ADC_HYS0.MONCYC

3’h4

CNV
ADC_CH0_OUT

CONV1

ACQ1

12’h301

CONV2

ACQ2

12’h315

CONV3

ACQ3

12’h2F0

ACQ4

CONV4

12’h2FD

CONV5

ACQ5

12’h300

Monitor
ADC_ALERT.HI0

Figure 20-14: Alert Functionality
ADC_LIM2_L0

12’h01E

ADC_HYS2.VALUE

9’h00E

ADC_HYS2.MONCYC

3’h6

CNV
ADC_CH2_OUT

ACQ1

CONV1

12’h010

ACQ2

CONV2

12’h00D

ACQ3

CONV3

12’h012

ACQ4

CONV4

12’h022

ACQ5

CONV5

12’h02F

Monitor
ADC_ALERT.Hi1

Figure 20-15: Alert Not Indicated when Conversion Result Returns to Normal Value within MONCYC Cycles

In auto cycle mode, channels are converted sequentially. If any channel crosses the threshold, it is monitored before
moving to the next channel in sequence. Monitoring stops if the channel input returns to a normal value within
MONCYC cycles or an alert is raised after MONCYC cycles.
NOTE: Hysteresis is not supported with DMA enabled.
The flowchart explains the flow of conversion when comparison is enabled on three channels in auto cycle mode.

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20–19ADuCM4050 ADC Register Descriptions

CNV onFirst Channel

Yes

CrossedThreshold?

MonitorFirst Channel

No
Monitoring Stops

CNV onSecond Channel

Yes

CrossedThreshold?

Monitor
Second Channel

No
Monitoring Stops

CNV onThird Channel

No

CrossedThreshold?

Yes

MonitorThird Channel

Monitoring Stops

Figure 20-16: Conversion Flow for Comparison Enabled on Three Channels in Auto Cycle Mode

ADuCM4050 ADC Register Descriptions
Digital Controller for ADC (ADC) contains the following registers.
Table 20-3: ADuCM4050 ADC Register List
Name

Description

ADC_ALERT

Alert Indication

ADC_AVG_CFG

Averaging Configuration

ADC_BAT_OUT

Battery Monitoring Result

ADC_CAL_WORD

Calibration Word

ADC_CFGADC Configuration

20–20

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ADuCM4050 ADC Register Descriptions

Table 20-3: ADuCM4050 ADC Register List (Continued)
Name

Description

ADC_CFG1

Reference Buffer Low Power Mode

ADC_CH0_OUT

Conversion Result Channel 0

ADC_CH1_OUT

Conversion Result Channel 1

ADC_CH2_OUT

Conversion Result Channel 2

ADC_CH3_OUT

Conversion Result Channel 3

ADC_CH4_OUT

Conversion Result Channel 4

ADC_CH5_OUT

Conversion Result Channel 5

ADC_CH6_OUT

Conversion Result Channel 6

ADC_CH7_OUT

Conversion Result Channel 7

ADC_CNV_CFG

ADC Conversion Configuration

ADC_CNV_TIMEADC Conversion Time

ADC_DMA_OUTDMA Output Register

ADC_HYS0

Channel 0 Hysteresis

ADC_HYS1

Channel 1 Hysteresis

ADC_HYS2

Channel 2 Hysteresis

ADC_HYS3

Channel 3 Hysteresis

ADC_IRQ_EN

Interrupt Enable

ADC_LIM0_HI

Channel 0 High Limit

ADC_LIM0_LO

Channel 0 Low Limit

ADC_LIM1_HI

Channel 1 High Limit

ADC_LIM1_LO

Channel 1 Low Limit

ADC_LIM2_HI

Channel 2 High Limit

ADC_LIM2_LO

Channel 2 Low Limit

ADC_LIM3_HI

Channel 3 High Limit

ADC_LIM3_LO

Channel 3 Low Limit

ADC_OVF

Overflow of Output Registers

ADC_PWRUP

ADC Power-up Time

ADC_STATADC Status

ADC_TMP2_OUT

Temperature Result 2

ADC_TMP_OUT

Temperature Result

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ADuCM4050 ADC Register Descriptions

Alert Indication
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

LO3 (R/W1C)
Channel 3 Low Alert Status

HI0 (R/W1C)
Channel 0 High Alert Status

HI3 (R/W1C)
Channel 3 High Alert Status

LO0 (R/W1C)
Channel 0 Low Alert Status

LO2 (R/W1C)
Channel 2 Low Alert Status

HI1 (R/W1C)
Channel 1 High Alert Status

HI2 (R/W1C)
Channel 2 High Alert Status

LO1 (R/W1C)
Channel 1 Low Alert Status

Figure 20-17: ADC_ALERT Register Diagram
Table 20-4: ADC_ALERT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7 LO3

Channel 3 Low Alert Status.

(R/W1C)
6 HI3Channel 3 High Alert Status.

(R/W1C)
5 LO2

Channel 2 Low Alert Status.

(R/W1C)
4 HI2Channel 2 High Alert Status.

(R/W1C)
3 LO1Channel 1 Low Alert Status.

(R/W1C)
2 HI1Channel 1 High Alert Status.

(R/W1C)
1 LO0

Channel 0 Low Alert Status.

(R/W1C)
0 HI0Channel 0 High Alert Status.

(R/W1C)

20–22

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Averaging Configuration
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

EN (R/W)To enable averaging on Channels enabled
in enable register

FACTOR (R/W)
Program averaging factor for averaging
enabled channels (1-256)

OS (R/W)
Enable oversampling

Figure 20-18: ADC_AVG_CFG Register Diagram
Table 20-5: ADC_AVG_CFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable averaging on Channels enabled in enable register.

(R/W)
14 OS

Enable oversampling.

(R/W)
7:0 FACTOR

Program averaging factor for averaging enabled channels (1-256).

(R/W)

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ADuCM4050 ADC Register Descriptions

Battery Monitoring Result
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of battery monitoringis stored here

Figure 20-19: ADC_BAT_OUT Register Diagram
Table 20-6: ADC_BAT_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of battery monitoring is stored here.

(R/NW)

20–24

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Calibration Word
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Offset Calibration Word

Figure 20-20: ADC_CAL_WORD Register Diagram
Table 20-7: ADC_CAL_WORD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
6:0 VALUE

Offset Calibration Word.

(R/W)

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ADuCM4050 ADC Register Descriptions

ADC Configuration
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VREFVBAT_DEL (R/W)
VRef VBAT delayed

PWRUP (R/W)
Powering up ADC

FAST_DISCH (R/W)
For fast switchover of Vref from 2.5
V to 1.25 V

VREFSEL (R/W)
To select Vref as 1.25 V or 2.5 V
REFBUFEN (R/W)
To enable internal reference buffer

TMPEN (R/W)
To power up temperature sensor

VREFVBAT (R/W)
VRef VBATSINKEN (R/W)
To enable additional 50 uA sink current
capability @1.25 V, 100 uA current
capability @2.5 V

EN (R/W)To enable ADC subsystem

RST (R/W)
Resets internal buffers and registers
when highSTARTCAL (R/W)
To start a new offset calibration cycle

Figure 20-21: ADC_CFG Register Diagram
Table 20-8: ADC_CFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
10 VREFVBAT_DEL(R/W)

9 FAST_DISCH

VRef VBAT delayed.
Set to 1 after minimum delay of 700 us from ADC_CFG.VREFVBAT field being set
to 1. NOTE: ADC_CFG.VREFVBAT_DEL and ADC_CFG.VREFVBAT must be reset to 0 together.
For fast switchover of Vref from 2.5 V to 1.25 V.

(R/W)
8 TMPEN

To power up temperature sensor.

(R/W)
7 SINKEN
(R/W)
6 RST

To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability@2.5 V.
Resets internal buffers and registers when high.

(R/W)
5 STARTCAL

To start a new offset calibration cycle.

(R/W)
4 EN

To enable ADC subsystem.

(R/W)

20–26

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ADuCM4050 ADC Register Descriptions

Table 20-8: ADC_CFG Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 VREFVBAT(R/W)

VRef VBAT.
Set to 1 to select VBAT as Vref. After a minimum delay of 700 us from setting thisfield, ADC_CFG.VREFVBAT_DEL field must be set to 1.
Note: ADC_CFG.VREFVBAT_DEL and ADC_CFG.VREFVBAT must be reset to 0
together.

2 REFBUFENTo enable internal reference buffer.

(R/W)

0 External reference is used
1 Reference buffer is enabled

1 VREFSEL

To select Vref as 1.25 V or 2.5 V.

(R/W)

0 Vref = 2.5 V
1 Vref = 1.25 V

0 PWRUPPowering up ADC.

(R/W)

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ADuCM4050 ADC Register Descriptions

Reference Buffer Low Power Mode
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

RBUFLP (R/W)
Enable low power mode for reference
bufferFigure 20-22: ADC_CFG1 Register Diagram
Table 20-9: ADC_CFG1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
0 RBUFLP

Enable low power mode for reference buffer.

(R/W)

20–28

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ADuCM4050 ADC Register Descriptions

Conversion Result Channel 0
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of channel 0 is stored
here

Figure 20-23: ADC_CH0_OUT Register Diagram
Table 20-10: ADC_CH0_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of channel 0 is stored here.

(R/NW)

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ADuCM4050 ADC Register Descriptions

Conversion Result Channel 1
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of channel 1 is stored
here

Figure 20-24: ADC_CH1_OUT Register Diagram
Table 20-11: ADC_CH1_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of channel 1 is stored here.

(R/NW)

20–30

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Conversion Result Channel 2
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of channel 2 is stored
here

Figure 20-25: ADC_CH2_OUT Register Diagram
Table 20-12: ADC_CH2_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of channel 2 is stored here.

(R/NW)

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ADuCM4050 ADC Register Descriptions

Conversion Result Channel 3
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of channel 3 is stored
here

Figure 20-26: ADC_CH3_OUT Register Diagram
Table 20-13: ADC_CH3_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of channel 3 is stored here.

(R/NW)

20–32

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Conversion Result Channel 4
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of channel 4 is stored
here

Figure 20-27: ADC_CH4_OUT Register Diagram
Table 20-14: ADC_CH4_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of channel 4 is stored here.

(R/NW)

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ADuCM4050 ADC Register Descriptions

Conversion Result Channel 5
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of channel 5 is stored
here

Figure 20-28: ADC_CH5_OUT Register Diagram
Table 20-15: ADC_CH5_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of channel 5 is stored here.

(R/NW)

20–34

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Conversion Result Channel 6
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of channel 6 is stored
here

Figure 20-29: ADC_CH6_OUT Register Diagram
Table 20-16: ADC_CH6_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of channel 6 is stored here.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 ADC Register Descriptions

Conversion Result Channel 7
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of channel 7 is stored
here

Figure 20-30: ADC_CH7_OUT Register Diagram
Table 20-17: ADC_CH7_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of channel 7 is stored here.

(R/NW)

20–36

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

ADC Conversion Configuration
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

MULTI (R/W)
Set to start multiple conversions

SEL (R/W)
To select channel(s) to convert

SINGLE (R/W)
Set to start single conversion

BAT (R/W)
Enable Battery Monitoring

DMAEN (R/W)
Enable DMA Channel

TMP (R/W)
To select temperature measurement 1

AUTOMODE (R/W)
Enable Auto Mode

TMP2 (R/W)
To select temperature measurement 2

Figure 20-31: ADC_CNV_CFG Register Diagram
Table 20-18: ADC_CNV_CFG Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 MULTI

Set to start multiple conversions.

(R/W)
14 SINGLE

Set to start single conversion.

(R/W)
13 DMAEN

Enable DMA Channel.

(R/W)
12 AUTOMODE

Enable Auto Mode.

(R/W)
10 TMP2

To select temperature measurement 2.

(R/W)
9 TMP

To select temperature measurement 1.

(R/W)
8 BAT

Enable Battery Monitoring.

(R/W)
7:0 SELTo select channel(s) to convert.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–37

ADuCM4050 ADC Register Descriptions

ADC Conversion Time15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DLY (R/W)
Delay between two consecutive conversionsin terms of number of ACLK cycles

SAMPTIME (R/W)
Number of clock cycles (ACLK) required
for sampling

Figure 20-32: ADC_CNV_TIME Register Diagram
Table 20-19: ADC_CNV_TIME Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:8 DLY

Delay between two consecutive conversions in terms of number of ACLK cycles.

(R/W)
7:0 SAMPTIME

Number of clock cycles (ACLK) required for sampling.

(R/W)

20–38

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

DMA Output Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)Register to store conversion result
for DMA

Figure 20-33: ADC_DMA_OUT Register Diagram
Table 20-20: ADC_DMA_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Register to store conversion result for DMA.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–39

ADuCM4050 ADC Register Descriptions

Channel 0 Hysteresis
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN (R/W)To enable hysteresis for comparisonon Channel 0

VALUE (R/W)
Hysteresis Value for Channel 0

MONCYC (R/W)
Program number of conversion cycles
to monitor channel 0 before raising
alert

Figure 20-34: ADC_HYS0 Register Diagram
Table 20-21: ADC_HYS0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable hysteresis for comparison on Channel 0.

(R/W)
14:12 MONCYC

Program number of conversion cycles to monitor channel 0 before raising alert.

(R/W)
8:0 VALUE

Hysteresis Value for Channel 0.

(R/W)

20–40

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Channel 1 Hysteresis
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN (R/W)To enable hysteresis for comparisonon Channel 1

VALUE (R/W)
Hysteresis Value for Channel 1

MONCYC (R/W)
Program number of conversion cycles
to monitor channel 1 before raising
alert

Figure 20-35: ADC_HYS1 Register Diagram
Table 20-22: ADC_HYS1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable hysteresis for comparison on Channel 1.

(R/W)
14:12 MONCYC

Program number of conversion cycles to monitor channel 1 before raising alert.

(R/W)
8:0 VALUE

Hysteresis Value for Channel 1.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–41

ADuCM4050 ADC Register Descriptions

Channel 2 Hysteresis
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN (R/W)To enable hysteresis for comparisonon Channel 2

VALUE (R/W)
Hysteresis Value for Channel 2

MONCYC (R/W)
Program number of conversion cycles
to monitor channel 2 before raising
alert

Figure 20-36: ADC_HYS2 Register Diagram
Table 20-23: ADC_HYS2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable hysteresis for comparison on Channel 2.

(R/W)
14:12 MONCYC

Program number of conversion cycles to monitor channel 2 before raising alert.

(R/W)
8:0 VALUE

Hysteresis Value for Channel 2.

(R/W)

20–42

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Channel 3 Hysteresis
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN (R/W)To enable hysteresis for comparisonon Channel 3

VALUE (R/W)
Hysteresis Value for Channel 3

MONCYC (R/W)
Program number of conversion cycles
to monitor channel 3 before raising
alert

Figure 20-37: ADC_HYS3 Register Diagram
Table 20-24: ADC_HYS3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable hysteresis for comparison on Channel 3.

(R/W)
14:12 MONCYC

Program number of conversion cycles to monitor channel 3 before raising alert.

(R/W)
8:0 VALUE

Hysteresis Value for Channel 3.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–43

ADuCM4050 ADC Register Descriptions

Interrupt Enable
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RDY (R/W)
Set to enable interrupt when ADC isready to convert

CNVDONE (R/W)
Set it to enable interrupt after conversion
is done

ALERT (R/W)
Enable Interrupt on Crossing Lower
or Higher Limit

CALDONE (R/W)
Set it to enable interrupt for calibration
done

OVF (R/W)
Set to enable interrupt in case of overflow

Figure 20-38: ADC_IRQ_EN Register Diagram
Table 20-25: ADC_IRQ_EN Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
13 RDYSet to enable interrupt when ADC is ready to convert.

(R/W)
12 ALERT

Enable Interrupt on Crossing Lower or Higher Limit.

(R/W)
11 OVF

Set to enable interrupt in case of overflow.

(R/W)
10 CALDONE

Set it to enable interrupt for calibration done.

(R/W)
0 CNVDONE

Set it to enable interrupt after conversion is done.

(R/W)

20–44

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Channel 0 High Limit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

EN (R/W)To enable high limit comparison on
Channel 0

VALUE (R/W)
High Limit Value for Channel 0

Figure 20-39: ADC_LIM0_HI Register Diagram
Table 20-26: ADC_LIM0_HI Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable high limit comparison on Channel 0.

(R/W)
11:0 VALUEHigh Limit Value for Channel 0.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–45

ADuCM4050 ADC Register Descriptions

Channel 0 Low Limit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN (R/W)To enable low limit comparison on
Channel 0

VALUE (R/W)
Low Limit Value for Channel 0

Figure 20-40: ADC_LIM0_LO Register Diagram
Table 20-27: ADC_LIM0_LO Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable low limit comparison on Channel 0.

(R/W)
11:0 VALUE

Low Limit Value for Channel 0.

(R/W)

20–46

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Channel 1 High Limit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

EN (R/W)To enable high limit comparison on
Channel 1

VALUE (R/W)
High Limit Value for Channel 1

Figure 20-41: ADC_LIM1_HI Register Diagram
Table 20-28: ADC_LIM1_HI Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable high limit comparison on Channel 1.

(R/W)
11:0 VALUEHigh Limit Value for Channel 1.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–47

ADuCM4050 ADC Register Descriptions

Channel 1 Low Limit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN (R/W)To enable low limit comparison on
Channel 1

VALUE (R/W)
Low Limit Value for Channel 1

Figure 20-42: ADC_LIM1_LO Register Diagram
Table 20-29: ADC_LIM1_LO Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable low limit comparison on Channel 1.

(R/W)
11:0 VALUE

Low Limit Value for Channel 1.

(R/W)

20–48

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Channel 2 High Limit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

EN (R/W)To enable high limit comparison on
Channel 2

VALUE (R/W)
High Limit Value for Channel 2

Figure 20-43: ADC_LIM2_HI Register Diagram
Table 20-30: ADC_LIM2_HI Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable high limit comparison on Channel 2.

(R/W)
11:0 VALUEHigh Limit Value for Channel 2.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–49

ADuCM4050 ADC Register Descriptions

Channel 2 Low Limit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN (R/W)To enable low limit comparison on
Channel 2

VALUE (R/W)
Low Limit Value for Channel 2

Figure 20-44: ADC_LIM2_LO Register Diagram
Table 20-31: ADC_LIM2_LO Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable low limit comparison on Channel 2.

(R/W)
11:0 VALUE

Low Limit Value for Channel 2.

(R/W)

20–50

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Channel 3 High Limit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

EN (R/W)To enable high limit comparison on
Channel 3

VALUE (R/W)
High Limit Value for Channel 3

Figure 20-45: ADC_LIM3_HI Register Diagram
Table 20-32: ADC_LIM3_HI Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable high limit comparison on Channel 3.

(R/W)
11:0 VALUEHigh Limit Value for Channel 3.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–51

ADuCM4050 ADC Register Descriptions

Channel 3 Low Limit
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN (R/W)To enable low limit comparison on
Channel 3

VALUE (R/W)
Low Limit Value for Channel 3

Figure 20-46: ADC_LIM3_LO Register Diagram
Table 20-33: ADC_LIM3_LO Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 EN

To enable low limit comparison on Channel 3.

(R/W)
11:0 VALUE

Low Limit Value for Channel 3.

(R/W)

20–52

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Overflow of Output Registers
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

TMP2 (R/W1C)
Indicates overflow in temperature 2
output register

CH0 (R/W1C)
Indicates overflow in channel 0 output
register

TMP (R/W1C)
Indicates overflow in temperature output
register

CH1 (R/W1C)
Indicates overflow in channel 1 output
register

BAT (R/W1C)
Indicates overflow in battery monitoring
output register

CH2 (R/W1C)
Indicates overflow in channel 2 output
register

CH7 (R/W1C)
Indicates overflow in channel 7 output
register

CH3 (R/W1C)
Indicates overflow in channel 3 output
register

CH6 (R/W1C)
Indicates overflow in channel 6 output
register

CH4 (R/W1C)
Indicates overflow in channel 4 output
register

CH5 (R/W1C)
Indicates overflow in channel 5 output
registerFigure 20-47: ADC_OVF Register Diagram
Table 20-34: ADC_OVF Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
10 TMP2

Indicates overflow in temperature 2 output register.

(R/W1C)
9 TMP

Indicates overflow in temperature output register.

(R/W1C)
8 BAT

Indicates overflow in battery monitoring output register.

(R/W1C)
7 CH7

Indicates overflow in channel 7 output register.

(R/W1C)
6 CH6

Indicates overflow in channel 6 output register.

(R/W1C)
5 CH5

Indicates overflow in channel 5 output register.

(R/W1C)
4 CH4

Indicates overflow in channel 4 output register.

(R/W1C)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–53

ADuCM4050 ADC Register Descriptions

Table 20-34: ADC_OVF Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 CH3

Indicates overflow in channel 3 output register.

(R/W1C)
2 CH2

Indicates overflow in channel 2 output register.

(R/W1C)
1 CH1

Indicates overflow in channel 1 output register.

(R/W1C)
0 CH0

Indicates overflow in channel 0 output register.

(R/W1C)

20–54

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

ADC Power-up Time15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

1

1

1

0

0

0

0

0

0

1

0

WAIT (R/W)
Program this count to generate 20us
wait time with respect to the PCLK
frequency

Figure 20-48: ADC_PWRUP Register Diagram
Table 20-35: ADC_PWRUP Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
10:0 WAIT

Program this count to generate 20us wait time with respect to the PCLK frequency.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–55

ADuCM4050 ADC Register Descriptions

ADC Status
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RDY (R/W1C)
Indicates ADC is ready to start converting,when using external reference buffer

DONE0 (R/W1C)
Indicates conversion done on Channel 0
DONE1 (R/W1C)
Indicates conversion done on Channel 1

CALDONE (R/W1C)
Indicates calibration is done

DONE2 (R/W1C)
Indicates conversion done on Channel 2

TMP2DONE (R/W1C)
Indicates conversion is done for temperaturesensing 2

DONE3 (R/W1C)
Indicates conversion done on Channel 3

TMPDONE (R/W1C)
Indicates conversion is done for temperaturesensing

DONE4 (R/W1C)
Indicates conversion done on Channel 4
DONE5 (R/W1C)
Indicates conversion done on Channel 5

BATDONE (R/W1C)
Indicates conversion done for battery
monitoring
DONE7 (R/W1C)
Indicates conversion done on Channel 7
DONE6 (R/W1C)
Indicates conversion done on Channel 6

Figure 20-49: ADC_STAT Register Diagram
Table 20-36: ADC_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 RDY

Indicates ADC is ready to start converting, when using external reference buffer.

(R/W1C)
14 CALDONE

Indicates calibration is done.

(R/W1C)
10 TMP2DONE

Indicates conversion is done for temperature sensing 2.

(R/W1C)
9 TMPDONE

Indicates conversion is done for temperature sensing.

(R/W1C)
8 BATDONE

Indicates conversion done for battery monitoring.

(R/W1C)
7 DONE7

Indicates conversion done on Channel 7.

(R/W1C)
6 DONE6

Indicates conversion done on Channel 6.

(R/W1C)

20–56

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Table 20-36: ADC_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
5 DONE5

Indicates conversion done on Channel 5.

(R/W1C)
4 DONE4

Indicates conversion done on Channel 4.

(R/W1C)
3 DONE3

Indicates conversion done on Channel 3.

(R/W1C)
2 DONE2

Indicates conversion done on Channel 2.

(R/W1C)
1 DONE1

Indicates conversion done on Channel 1.

(R/W1C)
0 DONE0

Indicates conversion done on Channel 0.

(R/W1C)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–57

ADuCM4050 ADC Register Descriptions

Temperature Result 2
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of Temperature measurement
2 is stored here

Figure 20-50: ADC_TMP2_OUT Register Diagram
Table 20-37: ADC_TMP2_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of Temperature measurement 2 is stored here.

(R/NW)

20–58

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 ADC Register Descriptions

Temperature Result
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RESULT (R)
Conversion result of Temperature measurement
1 is stored here

Figure 20-51: ADC_TMP_OUT Register Diagram
Table 20-38: ADC_TMP_OUT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 RESULT

Conversion result of Temperature measurement 1 is stored here.

(R/NW)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

20–59Real-Time Clock (RTC)

21 Real-Time Clock (RTC)

The ADuCM4050 MCU uses the real-time clock (RTC) that keeps track of elapsed time, in configurable timeunits, using an externally attached 32,768 Hz crystal to generate a time base. When enabled, the RTC maintains acumulative count of elapsed time from the counts most recent redefinition (re-initialization) by the CPU or powerup value as applicable. The RTC can count from any configured initial value and roll-overs of the RTC count aresupported. The RTC is a 16-bit peripheral, but contains triple registers for any 47-bit quantities such as the elapsed
time count and alarm values.
The ADuCM4050 MCU has two real-time clock blocks, RTC0 and RTC1 (also called FLEX_RTC).
Each RTC has two configurable alarm features which permit the generation of absolute (exact time match) or periodic (every 60 increments of the RTC count) alarms.
Software is responsible for enabling and configuring the RTC and for interpreting its count value to turn this into
the time of day. The RTC logic also has a digital trim capability that is calibrated to achieve higher PPM accuracy intracking time.

RTC Features
The ADuCM4050 MCU supports the following features:• An RTC count register with 32 integer bits and 15 fractional bits of elapsed time in configurable time units
from a programmable reference point (initial value). This register is programmed under software control.
• The RTC can count time in units of a divided-down period of the RTC base clock (nominally 32,768
Hz), where the division can be any power of two from zero to fifteen. The range of RTC time units is thus
30.52 μs to 1s.
When programming (initializing) or re-enabling the RTC count, or when changing the prescale division
ratio, the prescaler is automatically zeroed. This is so that the RTC count value is positioned on exact,
coincident boundaries of both the start of the prescale sequence and the modulo-60 count roll-over.
In practical terms, a CPU redefinition of the RTC count (elapsed time) can be deposited on coincident 1second and 1-minute boundaries, when using a time base of 1 second. The same capability is supportedby the RTC for any prescaled time base.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–1

RTC Functional Description• Two optionally enabled, independent alarm features (one at absolute time and the other at modulo-60, periodic time) that cause a processor interrupt when the RTC count equals the alarm values. Note that such an interrupt wakes up the processor if the latter is in a sleep state.
• A digital trim capability whereby a positive or negative adjustment (in units of configured RTC time units) canbe added to the RTC count at a fixed interval to keep the RTC PPM time accuracy within target. The values
for both the adjustment and interval are calculated by running a calibration algorithm on the CPU.
• The RTC can take and preserve a snapshot of its elapsed real-time count when prompted to do so by the CPU.
This allows the CPU to associate a time stamp with an event such as incoming data packet. The RTC preserves
the snapshot for read-back by the CPU. The snapshot is persistent and is only overwritten when the CPU issues a request to capture a new value.
• RTC has four independent SensorStrobe channels with an alarm function. Each channel sends an output pulse
to an external device via GPIO, and instructs the device to measure or perform some action at a specific time.
The SensorStrobe events are scheduled by the CPU on the ADuCM4050 MCU by instructing the RTC to
activate the SensorStrobe events at a specific target time relative to the RTC real-time count. Duty-cycle andfrequency (0.5 Hz to 16384 Hz) of the output pulse can be configured.
• Each SensorStrobe channel can have up to three GPIO inputs from the external device, which can be sampled
based on the output pulse sent to the external device. Each SensorStrobe channel can be configured to interrupt the ADuCM4050 MCU when a specific activity is detected on these GPIO inputs from the external device. These inputs can broadcast sensor states like FIFO full, switch open, threshold crossed. This feature allows
the MCU to remain in a low power state and wake up to process the data only on specific activity.
• Input sampling is an optional feature of the RTC where dedicated GPIOs can be configured to be sampled on
the rising/falling edges of the SensorStrobe events.
• RTC has an input capture feature. Input capture is the process of taking a snapshot of the RTC real-time countwhen an external device signals an event via a transition on one of the GPIO inputs to the ADuCM4050
MCU.

RTC Functional Description
This section provides information on the RTC functionalities of the ADuCM4050 MCU.

RTC Block Diagram
A high-level block diagram of the RTC is shown below. All functionality for counting, alarm, trim, snapshot andwake-up interrupts is located in a dedicated 32 kHz timed, always ON RTC power domain. The APB interface with
the CPU, which comprises queuing and dispatch logic for posted register writes, along with interrupts to the Cortex
NVIC are all located in a PCLK/FCLK-timed (synchronous clocks) section of the main power-gated core domain.

21–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

RTC Operating Modes

RTC
Clock Domain,
32 kHzCrystalOscillator
Circuit(Analog)

GPIOs

GPIOs

Processor
Clock Domain,
FCLK and PCLK

DigitalTrim
Prescaler
32 kHzBase Clock
Prescaled, gated
32 kHz RTC time baseSnapshots /Input
Capture

RTC
Count

Interrupt
Control& Status
Clock
DomainCrossing
Control

PostedWrite
Transaction
Engine32 kHz FCLKPCLK

Alarms /SensorStrobe

GPIOs

FCLK-timed
IRQ to NVIC

FCLK

APB
Slave
Port

APB

PCLK
Interrupt
Control
32 kHz timed
wake-up IRQ to PMU

Figure 21-1: RTC High-level Block Diagram

The key use of the RTC is to provide time keeping functionality and maintain the time and date in an accurate andreliable manner with minimal power consumption. In addition to time keeping, it also provides stopwatch andalarm features. The RTC uses internal counters to keep the time of the day in terms of seconds, minutes, hours, anddays. This data is enough for the user application to extract the date and time information from RTC. Interrupts
can be issued periodically.
The prescaler allows the RTC to count in time units less than 1 second (applies only to RTC1). For a configured
prescale (RTC_CR1.PRESCALE2EXP), the integer count registers RTC_CNT0 and RTC_CNT1 count the time
unit at the rate of base clock (32768 Hz) divided by RTC_CR1.PRESCALE2EXP power of two and the fractionalcount register RTC_CNT2 gets RTC_CR1.PRESCALE2EXP number of fractional bits. The RTC_CNT2 registercounts a sequence from 0 to RTC_CR1.PRESCALE2EXP power of two at the base clock frequency of 32768 Hz
in order to increment a count in RTC_CNT0. Thus the RTC count is denominated in prescaled time units and isgiven by: {RTC_CNT1, RTC_CNT0} POINT {RTC_CNT2}. The overall resolution of the real-time count, including the fractional bits in RTC_CNT2, is therefore one 32kHz clock period.

RTC Operating Modes
The RTC used by the ADuCM4050 MCU supports the following operations.

Initial RTC Power-Up
The RTC operates in a dedicated voltage domain which, under normal (configurable) conditions, is always powered.
However, when a battery is attached for the first time or replaced, a power-on reset occurs which resets all RTC
registers.
Upon detecting an RTC failure, the CPU will typically reprogram the RTCs count and digital trim registers andclear the fail flag in the RTC control register. The CPU can optionally program the alarm registers of the RTC to
generate an interrupt when the alarm and count values match.
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RTC Operating Modes

Persistent, Sticky RTC Wake-Up Events
There is no loss of any RTC alarm event that happens when the part is in a power down mode. The resulting interrupt due to the alarm, assuming it is enabled, is maintained in an asserted state by the RTC so that the NVIC willsubsequently see it (FCLK timed version of the interrupt) when power is restored to the processor. To facilitate this,the RTC sends a 32 kHz-timed version of the same interrupt to the wake-up controller in the PMU which causes
the digital core to be repowered. Once the CPU is woken up, it can inspect both the PMU and RTC to understandthe cause of the interrupt event for the wake-up.

RTC Capacity to Accommodate Posted Writes by CPU
If a posted write by the CPU to a 32 kHz-sourced MMR in the RTC is pending dispatch (in the RTC) due to aqueue of other, similar register writes to the 32 kHz domain, a second or subsequent write by the CPU to the same
RTC register cannot be stacked up or overwrite the pending transaction. Any such attempts will be rejected by the
RTC. These result in RTC_SR0.WPNDERRINT interrupt events in the RTC (see the MMR details of RTC_SR0).

Realignment of RTC Count to Packet Defined Time Reference
The CPU can instruct the RTC to take a snapshot of its elapsed time count by writing a software key of 0x7627 to
the RTC_GWY MMR. This causes the combined three snap registers (RTC_SNAP2, RTC_SNAP1, and
RTC_SNAP0) to update to the current value of the three count registers (RTC_CNT2, RTC_CNT1, and
RTC_CNT0) and to maintain this snapshot until subsequently told by the CPU to overwrite it.

RTC Recommendations: Clocks and PowerThe following recommendations apply for using the RTC.
PCLK Frequency
When RTC writes are in progress, PCLK frequency must not drop below 1 MHz. RTC clock must be at least 30
times slower than PCLK.
Stopping PCLK
Before entering any mode which causes PCLK to stop, the CPU must first wait until there is confirmation from the
RTC that no previously posted writes are yet to complete. The CPU can check this by reading both the RTC_SR0
and RTC_SR2 registers.
Ensuring No Communication across RTC Power Boundary when Powering Down
When the CPU has advance knowledge about a power down, it must take the following action to ensure the integrity of always-on part of the RTC.
• Either :The CPU must verify that there are no posted writes in the RTC awaiting execution.
• Or :
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RTC Interrupts and Exceptions

Cancel all queued and executing posted writes in the RTC. This is achieved by writing a cancellation key of
0xA2C5 to the RTC_GWY register which takes immediate effect.
• And :Do not post any further register writes to the RTC until power is lost by the core.
These steps ensure that no communication between the CPU and the RTC is ongoing and thus liable to corruption
when the RTC power domains isolation barrier is subsequently activated.

RTC Interrupts and Exceptions
The RTC block can generate interrupts from multiple sources which can be unmasked by programming the control
register. The source of the interrupt is reflected in the Status register.

RTC Digital Trimming
The RTC block allows to compute the LF crystal trim values to compensate the RTC. This can come from a static
measure (a frequency counter), a real-time drift measure based external reference.
Commercial crystals typically run between 20-100 ppm. As an example, trimming a particular crystal and board
configuration in which it measures an untrimmed error of about +58.6 ppm (0.00586%) is given. This corresponds
to a faster clock of about 35.5 seconds/week (30 minutes/year).
Table 21-1: Trim Correction
Trim Value

Trim Interval (second)(second)

16384

32768

65536

131072

0

0.00

0.00

0.00

0.00

1

61.04

30.52

15.26

7.63

2

122.07

61.04

30.52

15.26

3

183.11

91.55

45.78

22.89

4

244.14122.07

61.04

30.52

5

305.18152.59

76.29

38.15

6

366.21

183.11

91.55

45.78

7

427.25

213.62106.81

53.41

Trim
Correction(ppm)

Based on the Trim Correction table, the closest matching ppm correction for the given example is 61.04. In casethere are different combinations yielding the same desired correction, prefer the shortest trim interval (and smallest
trim value) so as to minimize instantaneous drift.

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RTC Programming Model

A trim interval of 2^14 seconds with a negative trim value of 1 second is chosen for this example, subtracting 1
second every 4.5 hours to "slow" the fast crystal down to a more reasonable rate. This particular trim leaves a residual error of negative 2.44 ppm (0.000244%), making the trimmed clock a tad slow (less than 1.5 seconds/week orabout 1.3 minutes/year), but much better than the untrimmed accuracy of 30 minutes/year.

RTC Programming Model
The following section shows the programming sequence to configure RTC for an alarm event.

Programming Guidelines
The following are the programming guidelines:
1. Reset the RTC_CNT registers to 0.
2. Configure the prescaler to divide the RTC base clock in the RTC_CR1 register.
3. Poll for the RTC synchronization bit to be set in the RTC_SR1 register, as the MMR write happens in theslower RTC domain.
4. Program the RTC_ALM0, RTC_ALM1, RTC_ALM2 registers with the intended alarm time.
5. Enable the interrupt for alarm by setting the RTC_CR0.ALMINTEN bit.
6. Set the RTC_CR0.ALMEN and RTC_CR0.CNTEN bits.
7. Wait for the RTC alarm interrupt which is triggered when the RTC_CNT matches with the RTC_ALM value.

RTC SensorStrobe
SensorStrobe is an alarm mechanism in the RTC. It sends an output pulse to an external device via GPIO, and instructs the device to measure or perform some action at a specific time. The SensorStrobe events are scheduled by
the CPU on the ADuCM4050 MCU by instructing the RTC to activate the SensorStrobe events at a specific target
time relative to the RTC real-time count.
The alarm time is programmed in the RTC by the CPU, typically before going into hibernate. When a SensorStrobe
event occurs, the RTC can optionally cause the CPU to be woken up and interrupted to examine the results of thesensor obtained via the GPIO.
The input sampling feature is used to monitor the external device at specific time intervals. This period is controlled
by the SensorStrobe channel output. At a defined rate, inputs from the external device are sampled through dedicated GPIO inputs. When a specific programmed sequence from the external device is detected via these GPIO inputs,
the RTC can optionally cause the CPU to be woken up and interrupted to process the incoming data.
The RTC1 on the ADuCM4050 MCU has five SensorStrobe channels—SS0 (alarm only), SS1, SS2, SS3, and SS4(alarm only). These channels act as alarms scheduled in the RTC by the CPU. When a SensorStrobe event (alarm)
occurs, the channel toggles an output control line. This output is routed through a fixed GPIO pin for the channel
concerned and exported off chip.
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RTC SensorStrobe

Currently, the ADuCM4050 MCU has GPIO support for SS1, SS2 and SS3. SS0 is the 47-bit alarm feature andSS4 is a 16 bit alarm feature of the RTC without GPIO connectivity.
Table 21-2: SensorStrobe Output GPIO
SensorStrobe Channel

MCU GPIO Pin

SS1

P2_11 (GPIO43)

SS2

P1_12 (GPIO28)

SS3

P2_08 (GPIO40)

RTC0 has no SensorStrobe functionality.
The figure shows the SensorStrobe channels and how they align to the main RTC count.
15

RTC_CNT1

015

RTC_CNT00

15 14

RTC_CNT2032-bit integer and 15-bit
fractional RTC countConfigurable

CompareUnmasked for
SensorStrobeMatch
Maskedfor Sensor
Strobe Match

RTC_ALM1

46

14

SS1
RTCSS1TGT

0

16 bit SensorStobe Alarm
SS1 (1 channel), whenprescaling by 215 to 1 Hz

M

14

SS1
RTC_SS1TGT0

Bit 15 of SS1 target
time optionally masked out

M

M 13

0

Contiguous bits [15:14]
optionally masked outM

M M 12 RTC_SS1TGT 0

Contiguous bits [15:13]
optionally masked out

M

SS1
M
M 0
RTC_SS1TGTContiguous bits [15:1]
optionally masked out

M

M

SS1
RTC_SS1TGT

M

All bits
optionally masked out

0

16-bit SensorStrobe Alarm
SS1 (1 channel), whenprescaling by 22 to 8 kHz

SS1
RTC_SS1TGT
SS1...and so on, down to...

For all prescaledalignments of the 16-bit
SS1 channel,
contiguous bit positions at
the MSB end of theSensorStrobe Target
time can optionally bemasked out of a matchcomparison against
corresponding bits in the
RTC Count Integer register
RTC_CNT0 and fractional
register RTC_CNT2

15

15

15

SS1
RTC_SS1TGT

2

1Alignment of 16-bit
SensorStrobe Channel, SS1
tracks prescaling of RTC timebase by any power of 2

15

SS1
RTC_SS1TGT

0

0

15

RTC_ALM0

0

15 14

31

30

SS0

15

14

RTC_ALM20016-bit SensorStrobe Alarm
SS1 (1 channel), whenprescaling by 20 to 32 kHz
SS0 is a 47 -bit SensorStorbe
Channel, which reuses
the RTC_ALM1/0/2 Alarm registers

Figure 21-2: RTC SensorStrobe Channels

The 47-bit SensorStrobe channel (SS0) is a synonym of the 47-bit alarm feature in the RTC defined by the
RTC_ALM1, RTC_ALM0, and RTC_ALM2 registers. This is an absolute-time alarm, unmaskable in any of its bit
positions and whose time span before the alarm repeats is equal to the length of the RTC count.
To use SS0 for frequent SensorStrobe activations, the CPU must reprogram the alarm time in the RTC_ALM1/
RTC_ALM0/RTC_ALM2 registers each time it is woken up and interrupted by the RTC upon an SS0 event. SS0
does not have GPIO activation associated with it.
The 16-bit SensorStrobe channels—SS1, SS2, SS3, and SS4 have a shorter time span, but more versatile than SS0.
They align the 16 usable bits for prescaling the RTC integer count time base.

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RTC SensorStrobe

The RTC_SSMSK register masks the contiguous MSB bits of its target time to reduce the periodicity of repeating
alarms (as shown in the RTC SensorStrobe Channels figure). The RTC_SSMSKOT register also masks the contiguous LSB bits of its target time to control high duration of the pulse. The 16-bit SensorStrobe channels—SS1, SS2,
SS3, and SS4 support optional auto-reloading for alarm periods which are not powers of 2 with respect to 32 kHz
clock period. Each SensorStrobe channel has a fixed GPIO associated with it to export a one-cycle activation of its
SensorStrobe line.
RTC SensorStrobe Channels figure shows three example degrees of prescaling (215, 22, and 20) of the RTC timebase. It shows how the 16 bits of the alarm time for SS1, SS2, SS3, and SS4 align with the degree of prescaling of
the 32 kHz clock.
All the fractional bits in the RTC_CNT2 register consistent with the configurable prescaling are compared with thecorresponding bit positions of the alarm time specified by SS1, SS2, SS3, and SS4 when checking for a SensorStrobe
match. The remaining bits are compared with the LSB end of the RTC_CNT0 register. This self-aligning of SS1,
SS2, SS3, and SS4 with the RTC_CNT2 and RTC_CNT0 registers based on prescaling is supported for all prescale
powers of 2 between 0 and 15.
SensorStrobe for two types of periodicity of alarms (SensorStrobe events):• Periods which are a power of 2 with respect to the 32 kHz clock: Comparisons are made repeatedly between thevalue in the SSx bits (x = 1, 2, 3, 4) in the RTC count, suitably aligned for prescaling.
Period = ((RTC_CR4SS.SSxMSKEN ?2RTC_SSMSK.SSxMSK: 216)) / 32768 seconds
On Time = 2SSMSKOT.SSxMSKOT / 32768 seconds• Periods which are not a power of 2: Comparison is done by auto-reloading (cumulatively adding to the existing
content in the SSx) an offset value in the RTC_SSxHIGHDUR and RTC_SSxLOWDUR (x = 1, 2, 3) into
SSx (x = 1, 2, 3, 4) every time an SensorStrobe event occurs.
Period = (RTC_SSxLOWDUR + RTC_SSxHIGHDUR) / 32768 seconds
On Time = RTC_SSxHIGHDUR / 32768 seconds
The target time for an upcoming event on the SensorStrobe channel can be read by the CPU via the RTC_SSxTGT
register. For SensorStrobe that does not use auto reloading, the live value in the RTC_SSxTGT register is same as
the value of SSx (x = 1, 2, 3, 4) , as the step size between events is defined by the SSx. When auto-reloading isused, the live value in the RTC_SSxTGT register reflects the repeated, cumulative, modulo-16 addition of the
RTC_SSxHIGHDUR and RTC_SSxLOWDUR to a starting value of the SSx. RTC_SSxTGT always allows the
CPU to know when a SensorStrobe event is due, in terms of a match between RTC_SSxTGT and RTC count.
All SensorStrobe channels can be partially masked on both MSB and LSB end of target. Masking allows shorteningof the period of recurrence of SensorStrobe events by considering the bit positions of the target time and RTC countas Don’t Cares and contiguous matching in case of LSB masking. When a 16-bit SensorStrobe match check is carried out for SSx against the RTC count, contiguous bits at the MSB end of SSx and RTC_SSxTGT can
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RTC SensorStrobe

optionally be masked, thereby becoming Don’t Cares (shown as M-bit positions in the figure). The number of contiguous bits masked out in the SSx and RTC_SS1TGT are specified by RTC_SSMSK and RTC_SSMSKOT.
Each SensorStrobe channel has a dedicated GPIO output via which output pulses are exported outside the chip.
RTC SensorStrobe Programming Model
1. Configure GPIO for SensorStrobe as per the SensorStrobe Output GPIO table.
2. Reset RTC1_CNT register to 0.
3. Set the value in RTC1_SSxHIGHDUR and RTC1_SSxLOWDUR register with the high and low duration of
the SensorStrobe pulse. Writing to these registers will also set the duty cycle of the SensorStrobe output pulse,
where x is the SensorStrobe Channel number.
4. Enable Auto Reload by writing to RTC1_CR4SS.SSxARLEN = 1, where x is the SensorStrobe Channel
number.
5. Enable SensorStrobe Channel by writing to RTC1_CR3SS.SSxEN = 1, where x is the SensorStrobe Channel
number.
6. Enable RTC by writing to RTC1_CR0.CNTEN = 1. This will enable the RTC count as well as SensorStrobe
output on the selected channel.
RTC Input Sampling
It is an optional feature associated with the SensorStrobe channel. Each SensorStrobe channel (SSx, where x = 1, 2,3) has up to 3 GPIO inputs (SSxGPINy, y = 0, 1, 2). These inputs are sampled based on the output capture
events.
The falling edge, rising edge, or both SensorStrobe events can be used to sample the inputs. Sampled input for eachchannel is available as a non-sticky read back status in the RTC_SR7.SSxSMP field (updated when next sample isused). This allows periodic and controlled sampling of external activity generated by the sensor. Six sampling edges
are available for each output pulse.

RTC_SSx

Falling Edge

Rising Edge

32.768 kHz
RTC Clock
Before Falling Edge

Falling Edge

After Falling Edge

Before Rising Edge

Rising Edge

After Rising Edge

Figure 21-3: Sampling Edges

Sensor activity monitoring is achieved by generating an optional interrupt when the current sample matches withcertain behavior. One of the following sequence can be selected for this:
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RTC SensorStrobe• Current sample (SMPnt) is different from a previously sampled value(SMPnt-1) or• Current sample (SMPnt) is same as the previously sampled value(SMPnt-1) or• Current sample (SMPnt) matches the expected sample value (EXP_SMPn) or• Current sample (SMPnt) does not match the expected sample value (EXP_SMPn)

RTC_SSx

32.768 kHz
RTC Clock
SMPnt

SMPnt-1
SSxGPINy

Figure 21-4: RTC Input Sampling

The sticky status bit is available in the RTC_SR7 register denotes that the programmed sequence has occurred in
the sensor interface. This status bit can be optionally exported as interrupt to CPU. It allows the CPU to stay in low
power mode and wake up only when the programmed sequence occurs the sensor interface.
Each SensorStrobe channel (SS1, SS2, SS3, and SS4) can select up to 3 GPIO inputs from available 8 dedicated
GPIOs by configuring the RTC_GPMUX0 and RTC_GPMUX1 registers. Selected GPIOs must be configured as an
input to monitor external activity.
GPMUX0/1.SSxGPINySEL

3'b000

3'b0013'b010

3'b0113'b100

3'b101

3'b110

3'b111SSxGPINy

P0_12

P2_00

P0_09

P0_08

P1_13

P1_02

P2_07

P2_09

The following are the SensorStrobe capabilities of hibernate real time clock (RTC1) on the ADuCM4050 MCU:
• Supports four SensorStrobe channels (SS1, SS2, SS3, and SS4) with GPIO activation:• 16-bit channels. The target time for the 16-bit channel is specified as:{least_significant_integer_bits_to_bring_total_to_16,
fractional_bits_due_to_prescaling}
The total number of bits in this concatenated capture time is 16.
The number of fractional bits in the target depends on the degree of prescaling configured for the 32 kHzbase clock. The number of fractional bits used in the input capture function tracks with the prescaling.
The remaining bits in the 16-bit target time consist of integers from the LSB end of the integer count of
the RTC. The number of integer bits combined with the fractional bits (due to prescaling) must be 16.
• There is a 47-bit alarm feature in the RTC. However, there is no GPIO associated with it to act as a SensorStrobe channel. The target time for this 47-bit alarm is specified as:
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RTC SensorStrobe{32_integer_bits, 15_fractional_bits}• For SensorStrobe channel, the target time is always specified down to an individual 32 kHz clock cycle as all
relevant fractional bits are included in the target time.
• For the 16-bit SensorStrobe channels—SS1, SS2, SS3, and SS4, contiguous bits in the 16-bit target time canbe thermometer-code masked out, on a per-channel basis, from the MSB end of the target.
As a result of this optional masking, the contiguous bits at the MSB end of the target time are treated as Don’t
Cares, which results in dividing the periodicity of the repeating SensorStrobe event by 2 for every bit maskedout.
In other words, if more bits are masked out from the MSB end of the target time, the modular sequence ofrepeating SensorStrobe events is shortened by a factor of 2 for that channel.
• For a 16-bit sensorstrobe channel, contiguous bits in the 16-bit target time can be thermometer code masked
out, on a per channel basis, from the LSB end of the target. As a result of this optional masking, the contiguous
bits at the LSB end of the target time are treated as Don’t Cares, which results in continuous match and hence
controlling the high duration of the output pulse. High duration of SensorStrobe channel scales by 2 for every
bit masked out in LSB.
In other words, if more bits are masked out from the LSB end of the target time, the high duration of senstrobe
events is increased by a factor of 2 for that channel.
• Auto Reload: Each time an event triggers, a configurable 16-bit delta (reload value) is added to its target time
to calculate the revised target for the next event. The reloaded value is derived from the low and high duration
registers. When the output pulse goes low due to a falling/rising edge event, the low/high duration value is used
as reload value and the next target is set for rising/falling edge event. This allows the periodicity and high duration of repeating events to be created on this channel which is not a power of two with respect to the 32 kHz
clock.
The reloaded target time can be read by the CPU to confirm the accumulation due to reloading with each
event on that SensorStrobe channel. The reloaded target can also be contiguously masked from the MSB end.
• The SensorStrobe channel has a readable, sticky interrupt source bit, which activates (sticks high) whenever a
SensorStrobe event occurs. Separate bits are available for falling edge and rising edge events. This interrupt
source bit can optionally be enabled to fan into the interrupt and wake-up lines from the RTC.
• The SS1, SS2, SS3, and SS4 output pulses are exported by the RTC via the GPIOs, to an external device,prompting the device to act.
The exported pulses are on a dedicated-channel basis from the RTC to external device connected to the channel. A pulse on one SensorStrobe channel has no effect on other SensorStrobe channels. A non-inverted or an
inverted version of output pulse can be exported on a per-channel basis. Optionally, inverted version of SSx (x= 1, 3) can be exported via GPIO of SSy (y = 2, 4) respectively. These channel pairs can be used for differential pairing. There is no broadcast function, where a SensorStrobe event on one channel can be routed to all
SensorStrobe channels and external devices.

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RTC SensorStrobe• Each SensorStrobe channel can select up to 3 GPIO inputs from the available 8 GPIOs. These inputs are sampled with respect to the output pulse event as configured. The latest sampled value is available as a non-sticky
readback status. Optionally, an interrupt can be sent to the CPU when a specified sequence occurs on the sampled value.
• The SensorStrobe channel can be reconfigured and enabled/disabled on the fly, with no interruption to channels that are not part of the reconfiguration.
• A SensorStrobe channel is independent of input capture channels in the RTC.
RTC SensorStrobe Channel Waveforms show how the SensorStrobe for the SS1 channel works in the RTC.
32 kHzClock
RTC_CNT2[1:0]
Fractional
RTC count

0100

RTC_CNT1,
RTC_CNT0

10

11
11

01

00

32'h0000_0000

10

11

00

32'h0000_0001

01

10

11

32'h0000_0002

PRESCALE2EXP = 4'b0010 : Prescale the RTC base 32 kHz clock by 2 2 = 4 for integer RTC count time base : Defines roll-over and significant bits of RTC_CNT2

RTC_SSMSK [3:0] = 4'b0010 : Mask out contiguous bits of SS1 and RTC_SS1TGT from the MSB end down to and including bit 2 when comparing against the RTC count
RTC_SS1 = 16'bxxxx_xxxx_xxxx_xx11 : Starting compare time, where “x” indicates a “don’t-care” bit value because of the RTC_SSMSK setting

RTC_SS1TGT = 16'bxxxx_xxxx_xxxx_xx11 : Target compare time (no auto-reloading), where “x” indicates a “don’t-care” bit value because of the RTC_SSMSK setting

GPIO (no auto-reloading)

SS1IRQ (no auto-reloading)

IRQ reasserted

IRQ reasserted

SS1ARLEN = 1'b1 : Enable auto-reloading (cumulative, additive target time) for SS1
RTCSS1_HIGHDUR = 16’d1, RTC_SS1LOWDUR = 16’d6 : Auto Reload Values
RTC_SS1TGT(with auto-reloading)3(3 + 1) Mod 4(0 + 6) Mod 402(2 + 1) Mod 4 (3 + 6) Mod 4
31(1 + 1) Mod 4(2 + 6) Mod 4

20

GPIO (with auto-reloading)

SS1IRQ (with auto-reloading)

IRQ reasserted

IRQ reasserted

Figure 21-5: RTC SensorStrobe Channel Waveforms

The figure shows the occurrence of the SensorStrobe events when the RTC prescales the base 32 kHz clock by 22(giving two meaningful, fractional bits in the RTC_CNT2 register). SensorStrobe is supported for all prescaling powers of 2 between 0 and 15, selected via RTC_CR1.PRESCALE2EXP.
The settings in red show a SensorStrobe event occurring on the SS1 channel for every four cycles of the 32 kHz
clock. The event has a period which is a power of two cycles due to the absence of auto-reloading, disabled via
RTC_CR4SS.SS1ARLEN. The value in the SS1 register defines the target time. Only two least significant bits of
SS1 are compared with the RTC count due to the mask setting in the RTC_SSMSK register. The number of unmasked bits (2) defines the periodicity of the compare events, as the unmasked target time 2'b11 at the LSB end of
SS1 is matched with every four increments of the RTC_CNT2 register.
The settings in blue show an equivalent sequence of SensorStrobe events with auto-reloading enabled. The effects ofthe cumulative addition on the target time can be seen in the RTC_SS1TGT register. When auto-reloading is
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RTC SensorStrobe

enabled, the initial target time is the value of SS1, but on activation of each event, the value of the
RTC_SS1HIGHDUR and RTC_SS1LOWDUR are added to the content existing in the RTC_SS1TGT register, allowing roll-overs in the addition. As the SensorStrobe match considers the masking specified in the RTC_SSMSK
register, cumulative addition when auto-reloading undergoes modulo operation (modular addition). Modulo operation is 2 Number of unmasked bits in the comparison.
The figure shows two unmasked LSBs of the auto-reload value (2'b11) being added cumulatively to the unmasked
bits of the RTC_SS1TGT. The result is subjected to a modulo-4 operation. The period of the compare events is
specified by the unmasked bits of the auto-reload value.
Masking and auto-reloading are optional features of the RTC.
There is an automatic alignment to the LSB end of the RTC count by the 16 bits (considering prescaling) in thefollowing:• Initial target time in RTC_SS1• Cumulative target time in the RTC_SS1TGT• Any possible mask decoded from the RTC_SSMSKWhen a SensorStrobe event occurs, a GPIO output is activated for one 32 kHz cycle along with the assertion of a
sticky interrupt source (RTC_CR3SS.SS1IRQEN), to record the occurrence of a new compare event since theCPU last cleared this interrupt source bit. The CPU can optionally enable RTC_CR3SS.SS1IRQEN to contributeto the activation of the RTC interrupt lines to the wake-up controller and NVIC. This is used to wake up the CPU
from hibernate and examine the results from an external sensor device prompted by an RTC SensorStrobe event toperform an action.
32 Hz
Clock

RTC_SS1HIGHDUR = 4, RTC_SS1LOWDUR = 6

GPIO
SS1 output pulse

RTC_CR6SSS.SS1SMPONFE = 2'b10 : Sample input on falling edge of SS1.
RTC_CR6SSS.SS1SMPONRE = 2'b00 : No sample taken on rising edge of SS1.
GPIO
Input to be sampledx

RTC_SR7.SS1SMP
read back value

RTC_SR7.SS1SMPMTCHIRQ

5x

RTC_CR7SSS.SS1SMPPTRN = 2'b00 : Interrupt if sampled value changed from previous.
RTC_CR5SSS.SS1SMPEN = 3'b011 : Only lower two inputs are valid on sampled data, Any change in MSB is ignored as it is not enabled

x

7

5

x

3

7

IRQ Asserted (5 to 7 transition
has lower two bits changing)x

3

No new IRQ Asserted (7 to 3 transition
has lower two bits constant)Figure 21-6: RTC Input Sampling

The figure shows the SensorStrobe sampling mechanism. The RTC_CR6SSS.SSxSMPONFE and
RTC_CR6SSS.SSxSMPONRE fields enable the sampling of input GPIOs around the falling and rising edge of
output pulse sent. In this example, inputs are sampled/recorded only on the falling edge of output pulse as per the
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–13

RTC SensorStrobe

configuration. The sampling point and sampled value are marked in blue. At the first sampling point, the inputs
have value 5. At the next sampling points, it has values 7 and 3. These values are available as readback to user in the
RTC_SR7.SS1SMP field.
The core is configured to be interrupted only when inputs change (RTC_CR7SSS.SS1SMPPTRN is 2'b00). Only
two out of available 3 inputs are enabled. The RTC_CR5SSS.SS1SMPEN has a value of 3'b011. It denotes that
only 2 LSBs are considered and MSB is a Don’t Care.
For the first sample 5 (3'b101), interrupt is not generated as there is no reference to the previous sample.
For the next sample 7 (3'b111), lower second bit changed and interrupt is sent to the core.
For the third sample 3 (3'b011), both LSBs are same as the previous and new interrupt is not generated.
The following table shows the summary of the Sensorstrobe channels.
Table 21-3: SensorStrobe Mechanism
SensorStrobe
ChannelPolarity Control

SS1

On/Off Time

On/Off Time

Mask Control

Interrupt Edge
Selection

Input Sampling

Differential Output Pairs

Yes

Yes

Yes

Yes

Yes

Yes

SS2

Yes

Yes

Yes

Yes

Yes

Yes

SS3

Yes

Yes

Yes

Yes

Yes

Yes

SS4

Yes

Yes

Yes

No

No

Yes

Fine control

Table 21-4: SensorStrobe Lookup Table
RTC_SSx
SensorStrobe Parameters

On Time (RTC Clocks)

RTC_CR4SS.
SSxMSKEN = 0

RTC_CR4SS.
SSxMSKEN = 1

RTC_CR4SS.
SSxMSKEN = 0

RTC_CR4SS.
SSxMSKEN = 1

RTC_CR4SS.
SSxARLEN = 0

RTC_CR4SS.
SSxARLEN = 0

RTC_CR4SS.
SSxARLEN = 1

RTC_CR4SS.
SSxARLEN = 1(x = 1, 2, 3, 4)(x = 1, 2, 3, 4)(x = 1, 2, 3)(x = 1, 2, 3)

RTC_SSxHIGHDUR.
SSxHIGHDUR(RTC_SSxHIGHDUR.
SSxHIGHDUR)

2RTC_SSMSKOT.SSxMSKOT% 2 SSxMSKPeriod (RTC Clocks)

RTC_CR4SS.RTC_SSxMSKEN?
(2RTC_SSMSK.SSxMSK) : 216

RTC_SSxHIGHDUR.
SSxHIGHDUR +RTC_SSxLOWDUR.
SSxLOWDUR(RTC_SSxHIGHDUR.
SSxHIGHDUR +RTC_SSxLOWDUR.
SSxLOWDUR)% 2 SSxMSKIllegal Case

21–14

NA

RTC_SSMSK.SSxMSK≤RTC_SSMSKOT.
SSxMSKOT

On Time = 0 Or Period = RTC_SSMSKOT.
SSxMSKOT != 0 Or On
0Time = 0 Or Period = 0

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

RTC Input Capture

RTC Input Sampling Programming Model
1. Configure GPIO for SensorStrobe as per the SensorStrobe Output GPIO table.
2. Reset RTC1_CNT register to 0.
3. Set the value in RTC1_SSxHIGHDUR and RTC1_SSxLOWDUR register with the high and low duration of
the SensorStrobe pulse. Writing to these registers will also set the duty cycle of the SensorStrobe output pulse,
where x is the SensorStrobe Channel number.
4. Enable Auto Reload by writing to RTC1_CR4SS.SSxARLEN = 1, where x is the SensorStrobe Channel
number.
5. Configure GPIOs as Input used for Input Sampling.
6. Configure the GPIO pin mux for selecting a GPIO as data to be sampled by SensorStrobe Channel by writing
to RTC1_GPMUX0 and RTC1_GPMUX1.
7. Configure the sampling edge as rising or falling or both for selected SS channel by writing to RTC1_CR6SSS
register.
8. Configure GPIO sampling pattern matching condition for the selected SensorStrobe channel by writing to
RTC1_CR7SSS register.
9. Enable GPIO Input Sampling and Activity Interrupt for the selected SensorStrobe Channel by writing to
RTC1_CR5SSS.
10. Enable SensorStrobe Channel by writing to RTC1_CR3SS.SSxEN = 1, where x is the SensorStrobe Channel
number.
11. Enable RTC by writing to RTC1_CR0.CNTEN = 1. This will enable the RTC count as well as SensorStrobe
output on the selected channel.

RTC Input Capture
Input capture is the process of taking a snapshot of the RTC real-time count when an external device signals an
event via a transition on one of the GPIO inputs to the ADuCM4050 MCU. An input capture event is triggered byan autonomous measurement or action on a device, which then signals to the ADuCM4050 MCU that the RTC
must take a snapshot of time corresponding to the event. Taking a snapshot can wake up the ADuCM4050 MCU
and interrupt the CPU. The CPU can subsequently obtain information from the RTC on the exact 32 kHz cycleand exact time of the input capture event.
The RTC1 on the ADuCM4050 MCU has four input capture channels—RTCIC0, RTCIC2, RTCIC3, and
RTCIC4. RTCIC2, RTCIC3 and RTCIC4 are 16-bit input capture channels. RTCIC0 is a 47-bit wide channel.
Table 21-5: RTC Input Capture GPIO
RTC Input Capture Channel

MCU GPIO Pin
P0_15 (GPIO15)

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21–15

RTC Input Capture

Table 21-5: RTC Input Capture GPIO (Continued)
RTC Input Capture Channel

MCU GPIO Pin

RTCIC0
RTCIC2

P1_00 (GPIO16)

RTCIC3

P0_13 (GPIO13)

RTCIC4

P2_01 (GPIO33)

Each of these independent channels can take a snapshot of the RTC count when a rising edge or falling edge event(one of these edge types is selected per channel) occurs on a GPIO associated with that channel. The snapshots areused to time stamp the inputs from external sensors devices for subsequent examination and processing by the CPU(once woken up).
Input capture snapshots are accurate down to a single 32 kHz clock period for all prescaling by the RTC of thisclock. Prescaling is the process of dividing the 32 kHz clock by any power of 2 (between 0 and 15), to create aslower time base and count the integer time in the RTC_CNT1 and RTC_CNT0 registers. Fractional time for thistime base is simultaneously counted in the RTC_CNT2 register in the units of 32 kHz clock periods. Each input
capture channel has a fixed GPIO pin to prompt the snapshot of RTC time to be taken when an edge (rising or
falling) occurs on the GPIO.
The RTCIC0 channel, unlike its counterparts, can also take a software-initiated snapshot when the CPU writes a
special key to the RTC.
The 16-bit input capture channels takes snapshots based on the degree of prescaling in the RTC for the integer
count time base, and align themselves accordingly. The 16-bit snapshots contain fractional bits in RTC_CNT2 register that are relevant for prescaling, and additional bits from the LSB end of the RTC_CNT0 register.
RTCIC0 snapshots all the bits from the RTC_CNT1, RTC_CNT0, and RTC_CNT2 registers. This gives a full, absolute-time snapshot for an event on the RTCIC0 channel. Other 16-bit input capture channels only have a timespan (uniqueness of the snapshot) equivalent to 216 periods of the 32 kHz clock.
The alignment of snapshots with the main RTC count is shown in the Input Capture Channels: 16-bit and 47-bit
Snapshots of RTC Count figure. It contains three example degrees of prescaling (215, 22, and 20) of the RTC timebase. All powers of 2 between 0 and 15 used in prescaling are supported for the 16-bit input capture channels.

21–16

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

RTC Input Capture

15

RTC_CNT1

015

RTC_CNT 0

0

15 14

15

14

RTC_CNT2032-bit integer and 15-bit
fractional RTC count

RTC_IC2/3/4

016-bit Input Capture
snapshots (3 channels) whenprescaling by 215 to 1 Hz

016-bit Input Capture
snapshots (3 channels) whenprescaling by 22 to 8 kHZ

Capture15

RTC_SNAP1

46

15 RTC_IC2/3/4

2

1

15

RTC_IC2/3/4

0

0

15

RTC_SNAP 0

0

15 14

31

30

RTC_IC015

14

Alignment of 16-bit
16-bit Input Capture
Input Capture Channels
snapshots (3 channels) when
RTC_IC2/3/4, tracks
prescaling by 20 to 32 kHZ
prescaling of RTC timebase by any power of 2
RTC_IC0 is a 47-bit Input
0
RTC_SNAP2
Capture Channel, which reuses
RTC_SNAP 1/0/2 registers.
0

Figure 21-7: RTC Input Capture Channels: 16-bit and 47-bit Snapshots of RTC Count

Each input capture channel has an independent control of the following features and can be changed on-the-fly
without affecting the other channels:• Enable/disable channel• Polarity of the active-going edge, rising or falling, of the GPIO to prompt snapshots• Enable to interrupt upon a capture event• Sticky interrupt source for a capture event• Read/unread status of a capture snapshot by the CPU
A common configurable setting RTC_CR2IC.RTCICOWUSEN is applied to all input capture channels. It is used
to select between allowing new snapshots overwrite unread previous ones on a per-channel basis, and having the
input capture snapshots stick until read by the CPU. While the same policy on overwriting snapshots applies to allchannels, each channel enforces it independently.
The following are the input capture capabilities of the hibernate real-time clock (RTC1) on the ADuCM4050
MCU:• Supports four independent input capture channels (three 16-bit channels and one 47-bit channel):• The three 16-bit channels snapshot the RTC elapsed count using 16 bits as follows:{least_significant_integer_bits_to_bring_total_to_16,
fractional_bits_due_to_prescaling}
The total number of bits in this concatenated capture time is 16.
The number of fractional bits in the target depends on the degree of prescaling configured for the 32 kHzbase clock. The number of fractional bits used in the input capture function tracks with the prescaling.
The remaining bits in the 16-bit target time consist of integers from the LSB end of the integer count of
the RTC. The number of integer bits combined with the fractional bits (due to prescaling) must be 16.

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21–17

RTC Input Capture• The 47-bit channel captures the absolute time for that input capture channel, where the capture time isgiven as {32_integer_bits, 15_fractional_bits}.
• For each of the four input capture channels, the snapshot always has a resolution down to an individual 32 kHz
clock cycle as all relevant fractional bits are included in the capture time.
• When an input capture event is detected by the RTC, the accuracy of the snapshot time for the event is asfollows:• For the three 16-bit input capture channels, each channel captures a snapshot which is exact in time down
to the 32 kHz cycle in which the event occurred.
• For the one 47-bit input capture channel, there is a fixed latency (delay) of one 32 kHz cycle of fractionaltime in the snapshot value captured for that event.
This latency of one LSB of the fractional count can be subtracted later by the software.
• An input capture event can be configured as a low-to-high or high-to-low transition on the GPIO input forthat channel. The polarity of this transition can be configured on a per-channel basis. The input capture channels can individually specify the type of transition that must cause an event for it.
• Each of the four input capture channels has a readable, sticky interrupt source bit, which activates (sticks high)whenever an input capture event occurs. This interrupt source bit can optionally be enabled to fan into (be acontributory term to) the interrupt and wake-up lines from the RTC.
• User can configure one of the following global overwrite policy for all the input capture channels in the RTC:
• When a new input capture event occurs on a given channel, the new snapshot value overwrites the previously captured value for that individual channel.
• For a given channel, snapshot can be overwritten by a new event only if the CPU has already read theexisting snapshot value for that channel.
NOTE: In addition to the readable interrupt sources, which stick active upon reception of new input capture events, the RTC also provides flags to the CPU confirming the read/unread status of the input capture snapshots. This aids the CPU if it is uses a policy of not allowing the unread snapshots to be overwritten by new events on the input capture channels.
• The input capture channels can be reconfigured and enabled/disabled on-the-fly, with no interruption to thechannels not part of the reconfiguration.
• The input capture channels operate independently of each other and independently of SensorStrobe channel in
the RTC.
RTC Input Capture Channels Waveforms show the input capture operation in the RTC. It shows the occurrence ofthe capture events while the RTC prescales the 32 kHz base clock by 22 (giving two meaningful, fractional bits in
RTC_CNT2), but the input capture is supported for all prescaling powers of two between 0 and 15 (selected via
RTC_CR1.PRESCALE2EXP).

21–18

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

RTC Power Modes Behavior

32 kHzClock

GPIO

PRESCALE2EXP = 4'b0010 : Prescale the RTC base 32 kHz clock by 22 = 4 for integer RTC count time base : Defines roll-over and significant bits of RTC_CNT2
RTC_CNT2[1:0]
Fractional
RTC count
RTC_CNT1,
RTC_CNT0
Integer RTC count

00

01

10

11

00

32'h0000_0000

01

10

11

00

32'h0000_0001

01

10

11

32'h0000_0002

RTCIC0/2/3/4LH = 1'b1 : Take input -capture snapshots of the RTC count at the rising edge of the GPIO

RTCIC0/2/3/4 : Snapshots of RTC count

RTCIC2/3/4 = 16'b0000_0000_0000_0001
RTCIC0= {32'h0000_0000, 15'b000_0000_0000_0001}

RTCIC0/2/3/4IRQ :Interrupt due to input capture on rising edge of GPIO

RTCIC0/2/3/4LH = 1'b0 : Take input -capture snapshots of the RTC count at the falling edge of the GPIO

RTCIC0/2/3/4 : Snapshots of RTC count

RTCIC2/3/4 = 16'b0000_0000_0000_0110
RTCIC0= {32'h0000_0001, 15'b000_0000_0000_0010}

RTCIC0/2/3/4IRQ :Interrupt due to input capture on falling edge of GPIO

Figure 21-8: RTC Input Capture Channels Waveforms

For a given input capture channel, the RTC_CR2IC.RTCIC2LH/RTC_CR2IC.RTCIC3LH/
RTC_CR2IC.RTCIC4LH fields allow the user to take the snapshot of the RTC time on the rising edge or fallingedge of the GPIO (not both edges). When an input capture event occurs, a 16-bit input capture channel stores thecurrent value of the 16 meaningful LSBs (accounting for prescaling) from the RTC_CNT2 and RTC_CNT0 registers
necessary to identify the individual 32 kHz cycle in which the GPIO edge has occurred. The 47-bit input capturechannel (RTCIC0) stores all the bits from the RTC_CNT1, RTC_CNT0, and RTC_CNT2 registers, giving its snapshot a longer span of uniquely identifying a 32 kHz cycle.
If RTC_CR2IC.RTCICOWUSEN does not allows overwriting of unread snapshots due to new GPIO edges, thesnapshots of the RTC time are sticky (not overwritten) until read by the CPU. When a snapshot is taken, a sticky
interrupt source (RTC_SR3.RTCIC0IRQ/RTC_SR3.RTCIC2IRQ/RTC_SR3.RTCOC3IRQ/
RTC_SR3.RTCIC4IRQ) goes high to record the occurrence of a new input capture event since the CPU lastcleared the interrupt source bit. Optionally, the CPU can enable such sources to contribute to the interrupt lines
from the RTC to the wake-up controller and NVIC.
Any number of channels, ranging from 0 to 8, of the four input capture channels and four SensorStrobe channel canoperate simultaneously.

RTC Power Modes Behavior
The table shows the MMR retention in hibernate and shutdown mode.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–19

RTC Power Modes Behavior

Table 21-6: RTC Registers Summary
Register

RTC0 Retention Status

RTC1 Retention Status

Hibernate Mode

Shutdown Mode

Hibernate Mode

Shutdown Mode

RTC_CR0

Yes

Yes

Yes

No

RTC_SR0

Yes

Yes

Yes

No

RTC_SR1

Yes

Yes

Yes

No

RTC_CNT0

Yes

Yes

Yes

No

RTC_CNT1

Yes

Yes

Yes

No

RTC_ALM0

Yes

Yes

Yes

No

RTC_ALM1

Yes

Yes

Yes

No

RTC_TRM

Yes

Yes

Yes

No

RTC_GWY

No

No

No

No

RTC_CR1

Yes

Yes

Yes

No

RTC_SR2

Yes

Yes

Yes

No

RTC_SNAP0

Yes

Yes

Yes

No

RTC_SNAP1

Yes

Yes

Yes

No

RTC_SNAP2

Yes

Yes

Yes

No

RTC_MOD

Yes

Yes

Yes

No

RTC_CNT2

Yes

Yes

Yes

No

RTC_ALM2

Yes

Yes

Yes

No

RTC_SR3

NA

NA

Yes

No

RTC_CR2IC

NA

NA

Yes

No

RTC_CR3SS

NA

NA

Yes

No

RTC_CR4SS

NA

NA

Yes

No

RTC_SSMSK

NA

NA

Yes

No

RTC_IC2

NA

NA

Yes

No

RTC_IC3

NA

NA

Yes

No

RTC_IC4

NA

NA

Yes

No

RTC_SS1

NA

NA

Yes

No

RTC_SS2

NA

NA

Yes

No

RTC_SS3

NA

NA

Yes

No

RTC_SS4

NA

NA

Yes

No

RTC_SR4

NA

NA

Yes

No

21–20

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-6: RTC Registers Summary (Continued)
Register

RTC0 Retention Status

RTC1 Retention Status

Hibernate Mode

Shutdown Mode

Hibernate Mode

Shutdown Mode

RTC_SR5

NA

NA

Yes

No

RTC_SR6

NA

NA

Yes

No

RTC_SS1TGT

NA

NA

Yes

No

RTC_FRZCNT

NA

NA

No

No

RTC_SS2TGT

NA

NA

Yes

No

RTC_SS3TGT

NA

NA

Yes

No

RTC_SS1LOWDUR

NA

NA

Yes

No

RTC_SS2LOWDUR

NA

NA

Yes

No

RTC_SS3LOWDUR

NA

NA

Yes

No

RTC_SS1HIGHDUR

NA

NA

Yes

No

RTC_SS2HIGHDUR

NA

NA

Yes

No

RTC_SS3HIGHDUR

NA

NA

Yes

No

RTC_SSMSKOT

NA

NA

Yes

No

RTC_CR5SSS

NA

NA

Yes

No

RTC_CR6SSS

NA

NA

Yes

No

RTC_CR7SSS

NA

NA

Yes

No

RTC_SR7

NA

NA

Yes

No

RTC_SR8

NA

NA

Yes

No

RTC_SR9

NA

NA

Yes

No

RTC_GPMUX0

NA

NA

Yes

No

RTC_GPMUX1

NA

NA

Yes

No

ADuCM4050 RTC Register Descriptions
Real-Time Clock (RTC) contains the following registers.
Table 21-7: ADuCM4050 RTC Register List
Name

Description

RTC_ALM0

RTC Alarm 0

RTC_ALM1

RTC Alarm 1

RTC_ALM2

RTC Alarm 2

RTC_CNT0

RTC Count 0

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–21

ADuCM4050 RTC Register Descriptions

Table 21-7: ADuCM4050 RTC Register List (Continued)
Name

Description

RTC_CNT1

RTC Count 1

RTC_CNT2

RTC Count 2

RTC_CR0

RTC Control 0

RTC_CR1

RTC Control 1

RTC_CR2IC

RTC Control 2 for Configuring Input Capture Channels

RTC_CR3SS

RTC Control 3 for Configuring SensorStrobe Channel

RTC_CR4SS

RTC Control 4 for Configuring SensorStrobe Channel

RTC_CR5SSS

RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling

RTC_CR6SSS

RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge

RTC_CR7SSS

RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity

RTC_FRZCNTRTC Freeze CountRTC_GPMUX0

RTC GPIO Pin Mux Control Register 0

RTC_GPMUX1

RTC GPIO Pin Mux Control Register 1

RTC_GWY

RTC Gateway

RTC_IC2

RTC Input Capture Channel 2

RTC_IC3

RTC Input Capture Channel 3

RTC_IC4

RTC Input Capture Channel 4

RTC_MOD

RTC Modulo

RTC_SS1

RTC SensorStrobe Channel 1

RTC_SS1HIGHDUR

RTC Auto-Reload High Duration for SensorStrobe Channel 1

RTC_SS1LOWDUR

RTC Auto-Reload Low Duration for SensorStrobe Channel 1

RTC_SS1TGTRTC SensorStrobe Channel 1 Target

RTC_SS2

RTC SensorStrobe Channel 2

RTC_SS2HIGHDUR

RTC Auto-Reload High Duration for SensorStrobe Channel 2

RTC_SS2LOWDUR

RTC Auto-Reload Low Duration for SensorStrobe Channel 2

RTC_SS2TGTRTC SensorStrobe Channel 2 Target

RTC_SS3

RTC SensorStrobe Channel 3

RTC_SS3HIGHDUR

RTC Auto-Reload High Duration for SensorStrobe Channel 3

RTC_SS3LOWDUR

RTC Auto-Reload Low Duration for SensorStrobe Channel 3

RTC_SS3TGTRTC SensorStrobe Channel 3 Target

RTC_SS4

RTC SensorStrobe Channel 4

21–22

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-7: ADuCM4050 RTC Register List (Continued)
Name

Description

RTC_SSMSKRTC Mask for SensorStrobe Channel

RTC_SSMSKOT

RTC Masks for SensorStrobe Channels on Time Control

RTC_SNAP0

RTC Snapshot 0

RTC_SNAP1

RTC Snapshot 1

RTC_SNAP2

RTC Snapshot 2

RTC_SR0

RTC Status 0

RTC_SR1

RTC Status 1

RTC_SR2

RTC Status 2

RTC_SR3

RTC Status 3

RTC_SR4

RTC Status 4

RTC_SR5

RTC Status 5

RTC_SR6

RTC Status 6

RTC_SR7

RTC Status 7

RTC_SR8

RTC Status 8

RTC_SR9

RTC Status 9

RTC_TRM

RTC Trim

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–23

ADuCM4050 RTC Register Descriptions

RTC Alarm 0
RTC_ALM0 contains the lower 16 bits of the non-fractional (prescaled) RTC alarm target time value .
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VALUE (R/W)
Lower 16 Prescaled (i.e. Non-Fractional)
Bits of the RTC Alarm Target Time

Figure 21-9: RTC_ALM0 Register Diagram
Table 21-8: RTC_ALM0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

21–24

Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time.
Note that the alarm register has a different reset value to the RTC count to avoid spurious alarms.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Alarm 1
RTC_ALM1 contains the upper 16 bits of the non-fractional (prescaled) RTC alarm target time value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VALUE (R/W)
Upper 16 Prescaled (Non-Fractional)
Bits of the RTC Alarm Target Time

Figure 21-10: RTC_ALM1 Register Diagram
Table 21-9: RTC_ALM1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/W)

Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time.
Note that the alarm register has a different reset value to the RTC count to avoid spurious alarms.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–25

ADuCM4050 RTC Register Descriptions

RTC Alarm 2
RTC_ALM2 specifies the fractional (non-prescaled) bits of the RTC alarm target time value, down to an individual
32 kHz clock cycle.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Fractional Bits of the Alarm Target Time

Figure 21-11: RTC_ALM2 Register Diagram
Table 21-10: RTC_ALM2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14:0 VALUE
(R/W)

21–26

Fractional Bits of the Alarm Target Time.
Fractional (non-prescaled) bits of the RTC alarm target time.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Count 0
RTC_CNT0 contains the lower 16 bits of the RTC counter which maintains a real-time count in elapsed prescaled
RTC time units.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Lower 16 Prescaled (Non-Fractional)
Bits of the RTC Real-Time Count

Figure 21-12: RTC_CNT0 Register Diagram
Table 21-11: RTC_CNT0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE

Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count.

(R/W)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–27

ADuCM4050 RTC Register Descriptions

RTC Count 1
RTC_CNT1 contains the upper 16 bits of the RTC counter, which maintains a real-time count in elapsed prescaled
RTC time units.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Upper 16 Prescaled (Non-Fractional)
Bits of the RTC Real-Time Count

Figure 21-13: RTC_CNT1 Register Diagram
Table 21-12: RTC_CNT1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE

Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count.

(R/W)

21–28

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ADuCM4050 RTC Register Descriptions

RTC Count 2
RTC_CNT2 contains the fractional part of the RTC count, where the count is denominated in prescaled time units
and is given by: {RTC_CNT1, RTC_CNT0} . {RTC_CNT2}. The overall resolution of the real-time count, including
the fractional bits in RTC_CNT2, is one 32 kHz clock period.
Note that the RTC_CNT2 register only exists in RTC1. In RTC0, the fractional part of the RTC count cannot beread by the CPU.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)Fractional Bits of the RTC Real-TimeCount

Figure 21-14: RTC_CNT2 Register Diagram
Table 21-13: RTC_CNT2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14:0 VALUE(R/NW)

Fractional Bits of the RTC Real-Time Count.
RTC_CNT2 is zeroed when one of the following events occurs:(i) The CPU writes a new pair of values to the RTC_CNT1 and RTC_CNT0 registers
to redefine the elapsed time units count while the RTC is enabled and the posted twin
write is executed.
(ii) The CPU enables the RTC from a disabled state using the RTC_CR0.CNTEN
field.
(iii) When the RTC is enabled, the degree of prescaling in the RTC is changed via the
RTC_CR1.PRESCALE2EXP field.

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ADuCM4050 RTC Register Descriptions

RTC Control 0
RTC_CR0 is the primary of two control registers for the RTC, the other being RTC_CR1.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

1

0

0

0

1

0

0

0

WPNDINTEN (R/W)
Enable Write Pending Sourced Interrupts
to the CPU
WSYNCINTEN (R/W)
Enable Write Synchronization SourcedInterrupts to the CPU

0

0

0

0

1

CNTEN (R/W)
Global Enable for the RTC
ALMEN (R/W)
Enable the RTC Alarm (Absolute) Operation
ALMINTEN (R/W)
Enable ALMINT Sourced Alarm Interrupts
to the CPU

WPNDERRINTEN (R/W)
Enable Write Pending Error SourcedInterrupts to the CPU When an RTC
Register-write Pending Error Occurs

TRMEN (R/W)
Enable RTC Digital Trimming

ISOINTEN (R/W)
Enable ISOINT Sourced Interrupts to
the CPU When Isolation of the RTC
Power Domain is Activated and Subsequently
De-activated

MOD60ALMEN (R/W)
Enable RTC Modulo-60 Counting ofTime Past a Modulo-60 Boundary

MOD60ALMINTEN (R/W)
Enable Periodic Modulo-60 RTC Alarm
Sourced Interrupts to the CPU
MOD60ALM (R/W)
Periodic, Modulo-60 Alarm Time in Prescaled
RTC Time Units Beyond a Modulo-60
Boundary

Figure 21-15: RTC_CR0 Register Diagram
Table 21-14: RTC_CR0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 WPNDINTEN(R/W)

Enable Write Pending Sourced Interrupts to the CPU.
This field is an enable for RTC interrupts to the CPU based on the
RTC_SR0.WPNDINT sticky interrupt source field.
0 Disable RTC_SR0.WPNDINT-sourced interrupts to
the CPU.
1 Enable RTC_SR0.WPNDINT-sourced interrupts to the
CPU.

21–30

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ADuCM4050 RTC Register Descriptions

Table 21-14: RTC_CR0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
14 WSYNCINTEN(R/W)

Enable Write Synchronization Sourced Interrupts to the CPU.
This field is an enable for RTC interrupts to the CPU based on the
RTC_SR0.WSYNCINT sticky interrupt source field.
0 Disable RTC_SR0.WSYNCINT-sourced interrupts to
the CPU.
1 Enable RTC_SR0.WSYNCINT-sourced interrupts to
the CPU.

13 WPNDERRINTEN(R/W)

Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Registerwrite Pending Error Occurs.
This field is an enable for RTC interrupts to the CPU based on the
RTC_SR0.WPNDINT sticky interrupt source field.
0 Disable interrupts if write pending errors occur in the
RTC.
1 Enable interrupts for write pending errors in the RTC.

12 ISOINTEN(R/W)

Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power
Domain is Activated and Subsequently De-activated.
This field enables interrupts to the CPU based on the RTC_SR0.ISOINT sticky interrupt source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR0.ISOINT-sourced interrupts to theCPU.
1 Enable RTC_SR0.ISOINT-sourced interrupts to theCPU.

11 MOD60ALMINTEN(R/W)

Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU.
This field enables interrupts to the CPU based on the RTC_SR0.MOD60ALMINT
sticky interrupt source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable periodic interrupts due to modulo-60 RTC
elapsed time.
1 Enable periodic interrupts due to modulo-60 RTC
elapsed time.

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ADuCM4050 RTC Register Descriptions

Table 21-14: RTC_CR0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10:5 MOD60ALM(R/W)

Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60
Boundary.
This field allows the CPU to position a periodic (repeating) alarm interrupt from the
RTC at any integer number of prescaled RTC time units from a modulo-60 boundary(roll-over event) of the RTC integer count in RTC_CNT1 and RTC_CNT0.
Values of 0 to 59 are allowed. If a greater value is configured, it is treated as zero prescaled RTC time units.
Boundaries are defined whenever any of the following events occurs :(i) the CPU writes a new pair of values to the RTC_CNT1and RTC_CNT0 registers.
(ii) the CPU enables the RTC from a disabled state using the RTC_CR0.CNTEN
field.
(iii) when the RTC is enabled by RTC_CR0.CNTEN, the degree of prescaling in the
RTC is changed via the RTC_CR1.PRESCALE2EXP field.
This bit field only exists in RTC1. In RTC0, the field is reserved and reads back as all
zeros.

4 MOD60ALMEN(R/W)

Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary.
RTC_CR0.MOD60ALMEN enables the RTC to detect and record until cleared by the
CPU the periodic interrupt condition of RTC_CNT1 and RTC_CNT0 having reached
RTC_CR0.MOD60ALM number of prescaled RTC time units past a modulo-60
boundary.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable determination of modulo-60 RTC elapsed time.
1 Enable determination of modulo-60 RTC elapsed time.

3 TRMEN(R/W)

Enable RTC Digital Trimming.
Trimming of the RTC allows the real-time count in prescaled RTC time units to be
adjusted on a periodic basis to track time with better accuracy. RTC_CR0.TRMEN
enables this adjustment, provided the RTC is enabled via RTC_CR0.CNTEN.
Note that if RTC_CR0.TRMEN is activated from a disabled state while
RTC_CR0.CNTEN is also active, this will cause a trim interval boundary to occur anda new trim interval will begin. No trim adjustment of the RTC count occurs on such
RTC_CR0.TRMEN activation. A whole, enabled trim interval must have elapsed before any adjustment is made.
0 Digital trimming of the RTC count value is disabled.
1 Trim is enabled.

21–32

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ADuCM4050 RTC Register Descriptions

Table 21-14: RTC_CR0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 ALMINTEN(R/W)

Enable ALMINT Sourced Alarm Interrupts to the CPU.
RTC_CR0.ALMINTEN enables interrupts to the CPU based on the
RTC_SR0.ALMINT sticky interrupt source.
0 Disable alarm interrupts.
1 Enable an interrupt if RTC alarm and count values
match.

1 ALMEN(R/W)

Enable the RTC Alarm (Absolute) Operation.
RTC_CR0.ALMEN must be set active for the alarm logic to function and for any
alarm event to be detected. Such an event is defined as a match between the values of
the RTC count and alarm registers, namely RTC_CNT1, RTC_CNT0, RTC_CNT2,
RTC_ALM1, RTC_ALM0, and RTC_ALM2.
0 Disable detection of alarm events.
1 Enable detection of alarm events.

0 CNTEN(R/W)

Global Enable for the RTC.
RTC_CR0.CNTEN enables counting of elapsed real time and acts as a master enable
for the RTC.
All interrupt sources can be cleared by the CPU irrespective of the value of CNTEN.
If the RTC is enabled by activating RTC_CR0.CNTEN , this event causes a realignment of the prescaler, the trim interval and the modulo-60 counter used by the RTC
to generate RTC_SR0.MOD60ALMINT-sourced interrupts.
0 Disable the RTC.
1 Enable the RTC.

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ADuCM4050 RTC Register Descriptions

RTC Control 1
RTC_CR1 register expands the granularity of RTC control which is already available via RTC_CR0.
Note that RTC_CR1 is only configurable in RTC1, whereas in RTC0 it is a read-only register with fixed (reset)
settings.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

PRESCALE2EXP (R/W)
Prescale Power of 2 Division Factor
for the RTC Base Clock

CNTINTEN (R/W)
Enable for the RTC Count Interrupt
SourceCNTMOD60ROLLINTEN (R/W)
Enable for the RTC Modulo-60 Count
Roll-Over Interrupt Source

PSINTEN (R/W)
Enable for the Prescaled, Modulo-1
Interrupt Source

CNTROLLINTEN (R/W)
Enable for the RTC Count Roll-OverInterrupt Source

TRMINTEN (R/W)
Enable for the RTC Trim Interrupt Source

Figure 21-16: RTC_CR1 Register Diagram
Table 21-15: RTC_CR1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
8:5 PRESCALE2EXP(R/W)

Prescale Power of 2 Division Factor for the RTC Base Clock.
RTC_CR1.PRESCALE2EXP defines the power of two by which the RTC base clock(32 kHz) is prescaled (divided in frequency) before being used to count time by advancing the contents of the RTC_CNT1 and RTC_CNT0 registers. It also defines thenumber of fractional bits of the count in RTC_CNT2 register.
For example, if RTC_CR1.PRESCALE2EXP is 0xF, RTC_CNT1 and RTC_CNT2
increment at 1Hz rate (32768/2^15) and RTC_CNT2 counts a sequence from 0 to
2^15 time units at a base clock frequency of 32768 Hz in order to advance
RTC_CNT0 value by one.
Note that this bit field is only configurable in RTC1. In RTC0, the field is read-only
and contains a value of 0xF, signifying a fixed prescaling of 2 to the power of 15. Thisis because RTC0 always counts real time at 1Hz. In contrast, RTC1 can prescale theclock by any power of two in the interval [15,0] to use as its time base.
0 Prescale the RTC base clock by 2^0 = 1.
1 Prescale the RTC base clock by 2^1 = 2.
2 Prescale the RTC base clock by 2^2 = 4.
3 Prescale the RTC base clock by 2^3 = 8.
4 Prescale the RTC base clock by 2^4 = 16.
5 Prescale the RTC base clock by 2^5 = 32.

21–34

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-15: RTC_CR1 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
6 Prescale the RTC base clock by 2^6 = 64.
7 Prescale the RTC base clock by 2^7 = 128.
8 Prescale the RTC base clock by 2^8 = 256.
9 Prescale the RTC base clock by 2^9 = 512.
10 Prescale the RTC base clock by 2^10 = 1024.
11 Prescale the RTC base clock by 2^11 = 2048.
12 Prescale the RTC base clock by 2^12 = 4096.
13 Prescale the RTC base clock by 2^13 = 8192.
14 Prescale the RTC base clock by 2^14 = 16384.
15 Prescale the RTC base clock by 2^15 = 32768.
4 CNTMOD60ROLLINT(R/W) EN

Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source.
Interrupt source is in RTC_SR2.CNTMOD60ROLLINT bitfield. This bit field only
exists in RTC1. In RTC0, the field is reserved and reads back as zero.
0 Disable RTC_SR2.CNTMOD60ROLLINT as a fan-interm of the RTC peripheral interrupt.
1 Enable RTC_SR2.CNTMOD60ROLLINT as a fan-interm of the RTC peripheral interrupt.

3 CNTROLLINTEN(R/W)

Enable for the RTC Count Roll-Over Interrupt Source.
This bit field only exists in RTC1. In RTC0, the field is reserved and reads back as
zero.
0 Disable RTC_SR2.CNTROLLINT as a fan-in term of
the RTC peripheral interrupt.
1 Enable RTC_SR2.CNTROLLINT as a fan-in term of
the RTC peripheral interrupt.

2 TRMINTEN(R/W)

Enable for the RTC Trim Interrupt Source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR2.TRMINT as a fan-in term of the
RTC peripheral interrupt.
1 Enable RTC_SR2.TRMINT as a fan-in term of the
RTC peripheral interrupt.

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ADuCM4050 RTC Register Descriptions

Table 21-15: RTC_CR1 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 PSINTEN(R/W)

Enable for the Prescaled, Modulo-1 Interrupt Source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR2.PSINT as a fan-in term of the
RTC peripheral interrupt.
1 Enable RTC_SR2.PSINT as a fan-in term of the RTC
peripheral interrupt.

0 CNTINTEN(R/W)

Enable for the RTC Count Interrupt Source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR2.CNTINT as a fan-in term of the
RTC peripheral interrupt.
1 Enable RTC_SR2.CNTINT as a fan-in term of the
RTC peripheral interrupt.

21–36

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ADuCM4050 RTC Register Descriptions

RTC Control 2 for Configuring Input Capture Channels
RTC_CR2IC is a control register for configuring enables related to input-capture channels. RTC_CR2IC contains
enables for both the input-capture function itself for each channel, as well as enables for whether an event on a channel should contribute to the interrupt lines from the RTC to both the CPU and the wake-up controller.
RTC input capture channels and GPIO pads: Input Capture channel [0,2,3,4] are connected to the External Interrupt pins [0,1,2,3] respectively.
Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

1

0

1

0

0

0

0

0

0

0

ICOWUSEN (R/W)
Enable Overwrite of Unread Snapshots
for All Input Capture Channels
IC4IRQEN (R/W)
Interrupt Enable for the RTC Input Capture
Channel 4

0

0

0

1

IC0EN (R/W)
Enable for the RTC Input Capture Channel 0
IC2EN (R/W)
Enable for the RTC Input Capture Channel 2
IC3EN (R/W)
Enable for the RTC Input Capture Channel 3

IC3IRQEN (R/W)
Interrupt Enable for the RTC Input Capture
Channel 3

IC4EN (R/W)
Enable for the RTC Input Capture Channel 4

IC2IRQEN (R/W)
Interrupt Enable for the RTC Input Capture
Channel 2

IC0LH (R/W)
Polarity of the Active-Going Capture
Edge for the RTC Input Capture Channel 0

IC0IRQEN (R/W)
Interrupt Enable for the RTC Input Capture
Channel 0

IC2LH (R/W)
Polarity of the Active-going Capture
Edge for the Input Capture Channel 2

IC4LH (R/W)
Polarity of the Active-going Capture
Edge for the Input Capture Channel 4
IC3LH (R/W)
Polarity of the Active-going Capture
Edge for the Input Capture Channel 3

Figure 21-17: RTC_CR2IC Register Diagram

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ADuCM4050 RTC Register Descriptions

Table 21-16: RTC_CR2IC Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 ICOWUSEN(R/W)

Enable Overwrite of Unread Snapshots for All Input Capture Channels.
This field controls whether snapshots for input capture channels are automaticallyoverwritten whenever a new capture event occurs, even if a previously-captured snapshot has not yet been read by the CPU.
0 Snapshots persist until first read and then subject to acapture event. Overwrites of unread snapshots are notenabled.
1 Snapshots persist until new capture events occur. Overwrites of unread snapshots are enabled.

14 IC4IRQEN(R/W)

Interrupt Enable for the RTC Input Capture Channel 4.
This field, active high, determines whether the sticky interrupt source
RTC_SR3.IC4IRQ is enabled to fan in as a contributory term to the RTC IRQ interrupt line to the CPU.
0 Disable RTC_SR3.IC4IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.IC4IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

13 IC3IRQEN(R/W)

Interrupt Enable for the RTC Input Capture Channel 3.
This field, active high, determines whether the sticky interrupt source
RTC_SR3.IC3IRQ is enabled to fan in as a contributory term to the RTC IRQ interrupt line to the CPU.
0 Disable RTC_SR3.IC3IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up-controller
1 Enable RTC_SR3.IC3IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller

21–38

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ADuCM4050 RTC Register Descriptions

Table 21-16: RTC_CR2IC Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
12 IC2IRQEN(R/W)

Interrupt Enable for the RTC Input Capture Channel 2.
This field, active high, determines whether the sticky interrupt source
RTC_SR3.IC2IRQ is enabled to fan in as a contributory term to the RTC IRQ interrupt line to the CPU.
0 Disable RTC_SR3.IC2IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.IC2IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

10 IC0IRQEN(R/W)

Interrupt Enable for the RTC Input Capture Channel 0.
This field, active high, determines whether the sticky interrupt source
RTC_SR3.IC0IRQ enabled to fan in as a contributory term to the RTC IRQ interrupt line to the CPU.
0 Disable RTC_SR3.IC0IRQ from contributing to the
RTC interrupt.
1 Enable RTC_SR3.IC0IRQ as a contributory fan-interm to the RTC interrupt.

9 IC4LH(R/W)

Polarity of the Active-going Capture Edge for the Input Capture Channel 4.
This field selects whether an input capture event on the RTC_IC4 channel is defined
as a low-to-high (LH) or high-to-low transition of the GPIO input for that channel.
0 The RTC_IC4 channel uses a high-to-low transition on
its GPIO pin to signal an input capture event.
1 The RTC_IC4 channel uses a low-to-high transition on
its GPIO pin to signal an input capture event.

8 IC3LH(R/W)

Polarity of the Active-going Capture Edge for the Input Capture Channel 3.
This field selects whether an input capture event on the RTC_IC3 channel is defined
as a low-to-high (LH) or high-to-low transition of the GPIO input for that channel.
0 The RTC_IC3 channel uses a high-to-low transition on
its GPIO pin to signal an input capture event.
1 The RTC_IC3 channel uses a low-to-high transition on
its GPIO pin to signal an input capture event.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

Table 21-16: RTC_CR2IC Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
7 IC2LH(R/W)

Polarity of the Active-going Capture Edge for the Input Capture Channel 2.
This field selects whether an input capture event on the RTC_IC2 channel is defined
as a low-to-high (LH) or high-to-low transition of the GPIO input for that channel.
0 The RTC_IC2 channel uses a high-to-low transition on
its GPIO pin to signal an input capture event.
1 The RTC_IC2 channel uses a low-to-high transition on
its GPIO pin to signal an input capture event.

5 IC0LH(R/W)

Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0.
This field selects whether an input capture event on the IC0 channel is defined as a
low-to-high (LH) or high-to-low transition of the GPIO input for that channel.
0 The IC0 channel uses a high-to-low transition on its
GPIO pin to signal an input capture event.
1 The IC0 channel uses a low-to-high transition on its
GPIO pin to signal an input capture event.

4 IC4EN(R/W)

Enable for the RTC Input Capture Channel 4.
This field, active high, is a global enable for the Input Capture 4 channel RTC_IC4.
0 Disable the 16-bit input-capture channel RTC_IC4.
1 Enable the 16-bit input-capture channel RTC_IC4.

3 IC3EN(R/W)

Enable for the RTC Input Capture Channel 3.
This field, active high, is a global enable for the Input Capture 3 channel RTC_IC3.
0 Disable the 16-bit input-capture channel RTC_IC3.
1 Enable the 16-bit Input-capture channel RTC_IC3.

2 IC2EN(R/W)

Enable for the RTC Input Capture Channel 2.
This field, active high, is a global enable for the Input Capture 2 channel RTC_IC2.
0 Disable the 16-bit input-capture channel RTC_IC2.
1 Enable the 16-bit input-capture channel RTC_IC2.

21–40

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-16: RTC_CR2IC Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 IC0EN(R/W)

Enable for the RTC Input Capture Channel 0.
Active high, global enable for the IC0 functionality related only to GPIO promptingof input capture into the 47-bit snapshot registers, RTC_SNAP1, RTC_SNAP0 and
RTC_SNAP2. Note that RTC_CR2IC.IC0EN has no effect on CPU-originatedsnapshots, which are prompted by a write of the specific key value of 0x7627 to the
RTC_GWY register.
0 Disable externally-requested (GPIO, non-CPU) snapshots for the 47-bit input-capture channel IC0.
1 Enable externally-requested (GPIO, non-CPU) snapshots for the 47-bit input-capture channel IC0.

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ADuCM4050 RTC Register Descriptions

RTC Control 3 for Configuring SensorStrobe Channel
RTC_CR3SS is a control register for configuring enables related to 16-bit SensorStrobe channels. The 47-bit SensorStrobe channel 0 is not controlled by RTC_CR3SS. This is because SensorStrobe channel 0 is a synonym for themain 47-bit RTC alarm (whose interrupt source is RTC_SR0.ALMINT), which is controlled by
RTC_CR0.ALMEN and RTC_CR0.ALMINTEN. Note that RTC_CR3SS only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS4IRQEN (R/W)
Rising Edge Interrupt Enable for SensorStrobe
Channel 4
SS3IRQEN (R/W)
Rising Edge Interrupt Enable for SensorStrobe
Channel 3000SS1EN (R/W)
Enable for SensorStrobe Channel 1
SS2EN (R/W)
Enable for SensorStrobe Channel 2
SS3EN (R/W)
Enable for SensorStrobe Channel 3

SS2IRQEN (R/W)
Rising Edge Interrupt Enable for SensorStrobe
Channel 2

SS4EN (R/W)
Enable for SensorStrobe Channel 4

SS1IRQEN (R/W)
Rising Edge Interrupt Enable for SensorStrobe
Channel 1

SS1FEIRQEN (R/W)
Falling Edge Interrupt Enable for SensorStrobe
Channel 1

SS4FEIRQEN (R/W)
Falling Edge Interrupt Enable for SensorStrobe
Channel 4

SS2FEIRQEN (R/W)
Falling Edge Interrupt Enable for SensorStrobe
Channel 2

SS3FEIRQEN (R/W)
Falling Edge Interrupt Enable for SensorStrobe
Channel 3

Figure 21-18: RTC_CR3SS Register Diagram
Table 21-17: RTC_CR3SS Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
12 SS4IRQEN(R/W)

Rising Edge Interrupt Enable for SensorStrobe Channel 4.
Active high, determines whether the sticky interrupt source RTC_SR3.SS4IRQ is
enabled to fan in as a contributory term to the RTC IRQ interrupt lines to both the
CPU and the wake-up controller.
0 Disable RTC_SR3.SS4IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.SS4IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

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ADuCM4050 RTC Register Descriptions

Table 21-17: RTC_CR3SS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
11 SS3IRQEN(R/W)

Rising Edge Interrupt Enable for SensorStrobe Channel 3.
Active high, determines whether the sticky interrupt source RTC_SR3.SS3IRQ is
enabled to fan in as a contributory term to the RTC IRQ interrupt lines to both the
CPU and the wake-up controller.
0 Disable RTC_SR3.SS3IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.SS3IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

10 SS2IRQEN(R/W)

Rising Edge Interrupt Enable for SensorStrobe Channel 2.
Active high, determines whether the sticky interrupt source RTC_SR3.SS2IRQ is
enabled to fan in as a contributory term to the RTC IRQ interrupt lines to both the
CPU and the wake-up controller.
0 Disable RTC_SR3.SS2IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.SS2IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

9 SS1IRQEN(R/W)

Rising Edge Interrupt Enable for SensorStrobe Channel 1.
Active high, determines whether the sticky interrupt source RTC_SR3.SS1IRQ is
enabled to fan in as a contributory term to the RTC IRQ interrupt lines to both the
CPU and the wake-up controller.
0 Disable RTC_SR3.SS1IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.SS1IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–43

ADuCM4050 RTC Register Descriptions

Table 21-17: RTC_CR3SS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
8 SS4FEIRQEN(R/W)

Falling Edge Interrupt Enable for SensorStrobe Channel 4.
Active high, determines whether the sticky interrupt source RTC_SR3.SS4IRQ is
enabled to fan in as a contributory term to the RTC IRQ interrupt lines to both the
CPU and the wake-up controller.
0 Disable RTC_SR3.SS4IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.SS4IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

7 SS3FEIRQEN(R/W)

Falling Edge Interrupt Enable for SensorStrobe Channel 3.
Active high, determines whether the sticky interrupt source RTC_SR3.SS3IRQ is
enabled to fan in as a contributory term to the RTC IRQ interrupt lines to both the
CPU and the wake-up controller.
0 Disable RTC_SR3.SS3IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.SS3IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

6 SS2FEIRQEN(R/W)

Falling Edge Interrupt Enable for SensorStrobe Channel 2.
Active high, determines whether the sticky interrupt source RTC_SR3.SS2IRQ is
enabled to fan in as a contributory term to the RTC IRQ interrupt lines to both the
CPU and the wake-up controller.
0 Disable RTC_SR3.SS2IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.SS2IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

21–44

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-17: RTC_CR3SS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
5 SS1FEIRQEN(R/W)

Falling Edge Interrupt Enable for SensorStrobe Channel 1.
Active high, determines whether the sticky interrupt source RTC_SR3.SS1IRQ is
enabled to fan in as a contributory term to the RTC IRQ interrupt lines to both the
CPU and the wake-up controller.
0 Disable RTC_SR3.SS1IRQ from contributing to the
RTC interrupts to both the CPU and the wake-up controller.
1 Enable RTC_SR3.SS1IRQ as a contributory fan-interm to the RTC interrupts to both the CPU and thewake-up controller.

4 SS4EN(R/W)

Enable for SensorStrobe Channel 4.
Active high, global enable for the SensorStrobe channel 4 (scheduled alarm),
RTC_SS4.
0 Disable the 16-bit SensorStrobe channel 4.
1 Enable the 16-bit SensorStrobe channel 4

3 SS3EN(R/W)

Enable for SensorStrobe Channel 3.
Active high, global enable for the SensorStrobe channel 3 (scheduled alarm),
RTC_SS3.
0 Disable the 16-bit SensorStrobe channel 3.
1 Enable the 16-bit SensorStrobe channel 3.

2 SS2EN(R/W)

Enable for SensorStrobe Channel 2.
Active high, global enable for the SensorStrobe channel 2 (scheduled alarm),
RTC_SS2.
0 Disable the 16-bit SensorStrobe channel 2
1 Enable the 16-bit SensorStrobe channel 2.

1 SS1EN(R/W)

Enable for SensorStrobe Channel 1.
Active high, global enable for the SensorStrobe channel 1 (scheduled alarm),
RTC_SS1.
0 Disable the 16-bit SensorStrobe channel 1
1 Enable the 16-bit SensorStrobe channel 1

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC Control 4 for Configuring SensorStrobe Channel
RTC_CR4SS is a control register for configuring enables related to masking and auto-reloading of the 16-bit SensorStrobe channel RTC_SS1. Note that this register only exists in RTC1. In RTC0, the register address is reserved
and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS3ARLEN (R/W)
Enable for Fine Control on SensorStrobe
Channel 3 Period and Duty Cycle

SS1MSKEN (R/W)
Enable for Thermometer-Code Maskingof the SensorStrobe Channel 1

SS2ARLEN (R/W)
Enable for Fine Control on SensorStrobe
Channel 2 Period and Duty Cycle

SS2MSKEN (R/W)
Enable for Thermometer-Code Maskingof the SensorStrobe Channel 2

SS1ARLEN (R/W)
Enable for Fine Control on SensorStrobe
Channel 1 Period and Duty Cycle

SS3MSKEN (R/W)
Enable for Thermometer-Code Maskingof the SensorStrobe Channel 3

SS4POL (R/W)
SensorStrobe Channel 4 Polarity Control

SS4MSKEN (R/W)
Enable for Thermometer-Code Maskingof the SensorStrobe Channel 4

SS3POL (R/W)
SensorStrobe Channel 3 Polarity Control
SS2POL (R/W)
SensorStrobe Channel 2 Polarity Control

SS1POL (R/W)
SensorSTrobe Channel 1 Polarity Control

Figure 21-19: RTC_CR4SS Register Diagram
Table 21-18: RTC_CR4SS Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
11 SS3ARLEN(R/W)

Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle.
Set this bit to enable fine control on high and low duration of RTC_SS3 SensorStrobe
channel by configuring RTC_SS3HIGHDUR and RTC_SS3LOWDUR.
0 Disable auto-reloading of RTC_SS1 and instead maintain its target value whenever an enabled SensorStrobe
event occurs on that channel.
1 Enable auto-reloading of RTC_SS3 from
RTC_SS3LOWDUR and RTC_SS3HIGHDUR whenever an enabled SensorStrobe event occurs on that channel.

21–46

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-18: RTC_CR4SS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10 SS2ARLEN(R/W)

Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle.
Set this bit to enable fine control on high and low duration of SensorStrobe channel 2
by configuring RTC_SS2HIGHDUR and RTC_SS2LOWDUR.
0 Disable auto-reloading of RTC_SS1 and instead maintain its target value whenever an enabled SensorStrobe
event occurs on that channel.
1 Enable auto-reloading of RTC_SS2 from
RTC_SS2LOWDUR and RTC_SS2HIGHDUR whenever an enabled SensorStrobe event occurs on that channel.

9 SS1ARLEN(R/W)

Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle.
Set this bit to enable fine control on high and low duration of SensorStrobe channel 1
by configuring RTC_SS1HIGHDUR and RTC_SS1LOWDUR.
0 Disable auto-reloading of RTC_SS1 and instead maintain its target value whenever an enabled SensorStrobe
event occurs on that channel.
1 Enable Auto-Reloading of RTC_SS1 from
RTC_SS1LOWDUR and RTC_SS1HIGHDUR whenever an enabled SensorStrobe event occurs on that channel.

8 SS4POL(R/W)

SensorStrobe Channel 4 Polarity Control.
Set this bit to initialize the polarity of RTC_SS4.
0 Polarity of SensorStrobe channel 4 starts with low.
1 Polarity of SensorStrobe channel 4 starts with high.

7 SS3POL(R/W)

SensorStrobe Channel 3 Polarity Control.
Set this bit to initialize the polarity of RTC_SS3.
0 Polarity of SensorStrobe channel 3 starts with low.
1 Polarity of SensorStrobe channel 3 starts with high.

6 SS2POL(R/W)

SensorStrobe Channel 2 Polarity Control.
Set this bit to initialize the polarity of RTC_SS2.
0 Polarity of SensorStrobe channel 2 starts with low.
1 Polarity of SensorStrobe channel 2 starts with high.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

Table 21-18: RTC_CR4SS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
5 SS1POL(R/W)

SensorSTrobe Channel 1 Polarity Control.
Set this bit to initialize the polarity of RTC_SS1.
0 Polarity of SensorStrobe channel 1 starts with low.
1 Polarity of SensorStrobe channel 1 starts with high.

4 SS4MSKEN(R/W)

Enable for Thermometer-Code Masking of the SensorStrobe Channel 4.
It is used to optionally enable masking of matches between RTC_SS4 and the RTC
count, when determining whether a scheduled alarm should be activated for SensorStrobe channel 4.
When enabled via this field, a four-bit code, embedded in RTC_SSMSK, is decodedout to a 16-bit thermometer-code mask and applied to bit positions in both
RTC_SS4 and 16 least significant integer and fractional bits in the lower end of the
RTC count given by RTC_CNT0 and RTC_CNT2.
0 Do not apply a mask to the 16-bit SensorStrobe channel
4
1 Apply a thermometer-decoded mask to the 16-bit SensorStrobe channel 4 provided that channel is enabled via
RTC_CR3SS.SS4EN

3 SS3MSKEN(R/W)

Enable for Thermometer-Code Masking of the SensorStrobe Channel 3.
It is used to optionally enable masking of matches between RTC_SS3 and the RTC
count, when determining whether a scheduled alarm should be activated for SensorStrobe channel 3.
When enabled via this field, a four-bit code, embedded in RTC_SSMSK, is decodedout to a 16-bit thermometer-code mask and applied to bit positions in both
RTC_SS3 and 16 least significant integer and fractional} bits in the lower end of the
RTC count given by RTC_CNT0 and RTC_CNT2.
0 Do not apply a mask to the 16-bit SensorStrobe channel
3
1 Apply a thermometer-decoded mask to the 16-bit SensorStrobe channel 3 provided that channel is enabled via
RTC_CR3SS.SS3EN

21–48

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-18: RTC_CR4SS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 SS2MSKEN(R/W)

Enable for Thermometer-Code Masking of the SensorStrobe Channel 2.
It is used to optionally enable masking of matches between RTC_SS2 and the RTC
count, when determining whether a scheduled alarm should be activated for SensorStrobe channel 2.
When enabled via this field, a four-bit code, embedded in RTC_SSMSK, is decodedout to a 16-bit thermometer-code mask and applied to bit positions in both
RTC_SS2 and 16 least significant integer and fractional bits in the lower end of the
RTC count given by RTC_CNT0 and RTC_CNT2.
0 Do not apply a mask to the 16-bit SensorStrobe channel
2
1 Apply a thermometer-decoded mask to the 16-bit SensorStrobe channel 2 provided that channel is enabled via
RTC_CR3SS.SS2EN

1 SS1MSKEN(R/W)

Enable for Thermometer-Code Masking of the SensorStrobe Channel 1.
This field is used to optionally enable masking of matches between RTC_SS1 and the
RTC count, when determining if a scheduled alarm should be activated for SensorStrobe channel 1.
When enabled via this field, a four-bit code, embedded in RTC_SSMSK, is decodedout to a 16-bit thermometer-code mask and applied to bit positions in both
RTC_SS1 and 16 least significant integer and fractional bits in the lower end of the
RTC count given by RTC_CNT0 and RTC_CNT2.
0 Do not apply a mask to SensorStrobe Channel 1 Register
1 Apply thermometer decoded mask Apply a thermometer-decoded mask to RTC_SS1, provided the channel isenabled via RTC_CR3SS.SS1EN.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–49

ADuCM4050 RTC Register Descriptions

RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling
RTC_CR5SSS is a control register for configuring enables related to sampling of GPIO for every 16-bit SensorStrobe channels. RTC_CR5SSS contains enables for both the gpio sampling for each channel, as well as enables forwhether an event on a channel should contribute to the interrupt lines from the RTC to both the CPU and thewake-up controller.
Note that the 47-bit SensorStrobe channel 0 is not controlled by RTC_CR5SSS. This is because SensorStrobe
channel 0 is a synonym for the main 47-bit RTC alarm (whose interrupt source is ALMINT), which is controlled
by the RTC_CR0.ALMEN and RTC_CR0.ALMINTEN fields.
Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS3SMPMTCHIRQEN (R/W)
Sample Activity Interrupt Enable for
SensorStrobe Channel 3

SS1SMPEN (R/W)
GPIO Input Sample Enable for SensorStrobe
Channel 1

SS3SMPEN (R/W)
GPIO Input Sample Enable for SensorStrobe
Channel 3

SS1SMPMTCHIRQEN (R/W)
Sample Activity Interrupt Enable for
SensorStrobe Channel 1

SS2SMPMTCHIRQEN (R/W)
Sample Activity Interrupt Enable for
SensorStrobe Channel 2

SS2SMPEN (R/W)
GPIO Input Sample Enable for SensorStrobe
Channel 2

Figure 21-20: RTC_CR5SSS Register Diagram
Table 21-19: RTC_CR5SSS Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
11 SS3SMPMTCHIRQEN(R/W)
10:8 SS3SMPEN(R/W)

7 SS2SMPMTCHIRQEN
(R/W)

21–50

Sample Activity Interrupt Enable for SensorStrobe Channel 3.
Setting this bit sends an interrupt to core when RTC_SR7.SS3SMPMTCHIRQ is set.
Sticky interrupt is sent to the core.
GPIO Input Sample Enable for SensorStrobe Channel 3.
Each SensorStrobe Channel has dedicated 3 GPIO inputs to be sampled. User can ignore one or many of these GPIO's by configuring this register. This three bit value isused to mask the respective GPIO. Setting a bit low masks that corresponding input
from sampling and comparison.
Sample Activity Interrupt Enable for SensorStrobe Channel 2.
Setting this bit sends an interrupt to core when RTC_SR7.SS2SMPMTCHIRQ is set.
Sticky interrupt is sent to the core.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-19: RTC_CR5SSS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
6:4 SS2SMPEN(R/W)

3 SS1SMPMTCHIRQEN(R/W)
2:0 SS1SMPEN(R/W)

GPIO Input Sample Enable for SensorStrobe Channel 2.
Each SensorStrobe Channel has dedicated 3 GPIO inputs to be sampled. User can ignore one or many of these GPIO's by configuring this register. This three bit value isused to mask the respective GPIO. Setting a bit low masks that corresponding input
from sampling and comparison.
Sample Activity Interrupt Enable for SensorStrobe Channel 1.
Setting this bit sends an interrupt to core when RTC_SR7.SS1SMPMTCHIRQ is set.
Sticky interrupt is sent to the core.
GPIO Input Sample Enable for SensorStrobe Channel 1.
Each SensorStrobe Channel has dedicated 3 GPIO inputs to be sampled. User can ignore one or many of these GPIO's by configuring this register. This three bit value isused to mask the respective GPIO. Setting a bit low masks that corresponding input
from sampling and comparison.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–51

ADuCM4050 RTC Register Descriptions

RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge
RTC_CR6SSS is a control register for configuring GPIO sampling edges with respective to every 16-bit SensorStrobe channel activity. RTC_CR6SSS contains enables to configure sampling around rising edge or falling edge orboth for every SensorStrobe channel. Note that this register only exists in RTC1. In RTC0, the register address isreserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS3SMPONRE (R/W)
GPIO Sample Around Rising Edge of
SensorStrobe Channel 3

SS1SMPONFE (R/W)
GPIO Sample Around Falling Edge of
SensorStrobe Channel 1

SS3SMPONFE (R/W)
GPIO Sample Around Falling Edge of
SensorStrobe Channel 3

SS1SMPONRE (R/W)
GPIO Sample Around Rising Edge of
SensorStrobe Channel 1

SS2SMPONRE (R/W)
GPIO Sample Around Rising Edge of
SensorStrobe Channel 2

SS2SMPONFE (R/W)
GPIO Sample Around Falling Edge of
SensorStrobe Channel 2

Figure 21-21: RTC_CR6SSS Register Diagram
Table 21-20: RTC_CR6SSS Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
11:10 SS3SMPONRE

GPIO Sample Around Rising Edge of SensorStrobe Channel 3.

(R/W)

Enables sampling of SensorStrobe GPIO inputs around rising edge of SensorStrobe
channel 3 pulse. Sampled data is available in RTC_SR7.SS3SMP register as readback. This data gets over-written when new sample is available.
0 No sampling of input around rising edge
1 Input sampled one clock cycle before rising edge of theSensorStrobe channel 3
2 Input sampled at rising edge of the SensorStrobe channel 3
3 Input sampled one clock cycle after rising edge of theSensorStrobe channel 3

21–52

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-20: RTC_CR6SSS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9:8 SS3SMPONFE(R/W)

GPIO Sample Around Falling Edge of SensorStrobe Channel 3.
Enables sampling of SensorStrobe GPIO inputs around falling edge of SensorStrobe
channel 3 pulse. Sampled data is available in RTC_SR7.SS3SMP register as readback. This data gets over-written when new sample is available.
0 No sampling of input around falling edge
1 Input sampled one clock cycle before falling edge of theSensorStrobe channel 3
2 Input sampled at falling edge of the SensorStrobe channel 3
3 Input sampled one clock cycle after falling edge of theSensorStrobe channel 3

7:6 SS2SMPONRE(R/W)

GPIO Sample Around Rising Edge of SensorStrobe Channel 2.
Enables sampling of SensorStrobe GPIO inputs around rising edge of SensorStrobe
channel 2 pulse. Sampled data is available in RTC_SR7.SS2SMP register as readback. This data gets over-written when new sample is available.
0 No sampling of input around rising edge
1 Input sampled one clock cycle before rising edge of theSensorStrobe channel 2
2 Input sampled at rising edge of the SensorStrobe channel 2
3 Input sampled one clock cycle after rising edge of theSensorStrobe channel 2

5:4 SS2SMPONFE(R/W)

GPIO Sample Around Falling Edge of SensorStrobe Channel 2.
Enables sampling of SensorStrobe GPIO inputs around falling edge of SensorStrobe
channel 2 pulse. Sampled data is available in RTC_SR7.SS2SMP register as readback. This data gets over-written when new sample is available.
0 No sampling of input around falling edge
1 Input sampled one clock cycle before falling edge of theSensorStrobe channel 2
2 Input sampled at falling edge of the SensorStrobe channel 2
3 Input sampled one clock cycle after falling edge of theSensorStrobe channel 2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–53

ADuCM4050 RTC Register Descriptions

Table 21-20: RTC_CR6SSS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3:2 SS1SMPONRE(R/W)

GPIO Sample Around Rising Edge of SensorStrobe Channel 1.
Enables sampling of SensorStrobe GPIO inputs around rising edge of SensorStrobe
pulse. Sampled data is available in RTC_SR7.SS1SMP register as readback. This data
gets over-written when new sample is available.
0 No sampling of input around rising edge
1 Input sampled one clock cycle before rising edge of theSensorStrobe channel 1
2 Input sampled at rising edge of the SensorStrobe channel 1
3 Input sampled one clock cycle after rising edge of theSensorStrobe channel 1

1:0 SS1SMPONFE(R/W)

GPIO Sample Around Falling Edge of SensorStrobe Channel 1.
Enables sampling of SensorStrobe GPIO inputs around falling edge of SensorStrobe
pulse. Sampled data is available in RTC_SR7.SS1SMP register as readback. This data
gets over-written when new sample is available.
0 No sampling of input around falling edge
1 Input sampled one clock cycle before falling edge of theSensorStrobe channel 1
2 Input sampled at falling edge of the SensorStrobe channel 1
3 Input sampled one clock cycle after falling edge of theSensorStrobe channel 1

21–54

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity
RTC_CR7SSS is a control register for configuring GPIO activity at which interrupt to core is sent. GPIO activity
can be denoted as inputs changing or inputs not changing or input matching expected value or input not matching
int he expected value. This activity is recorded in RTC_SR7 register and can be optionally sent as interrupt to core.
Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS3SMPPTRN (R/W)
Sample Activity Selection for SensorStrobe
Channel 3

SS1SMPEXP (R/W)
Expected GPIO Sample for SensorStrobe
Channel 1

SS3SMPEXP (R/W)
Expected GPIO Sample for SensorStrobe
Channel 3

SS1SMPPTRN (R/W)
Sample Activity Selection for SensorStrobe
Channel 1

SS2SMPPTRN (R/W)
Sample Activity Selection for SensorStrobe
Channel 2

SS2SMPEXP (R/W)
Expected GPIO Sample for SensorStrobe
Channel 2

Figure 21-22: RTC_CR7SSS Register Diagram
Table 21-21: RTC_CR7SSS Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14:13 SS3SMPPTRN

Sample Activity Selection for SensorStrobe Channel 3.

(R/W)

This field is used to set the status bit RTC_SR7.SS3SMPMTCHIRQ based on expected pattern RTC_CR7SSS.SS3SMPEXP or change in the sampled value.
0 Current GPIO sample is not same as previous sample
1 Current GPIO sample is same as previous sample
2 Current GPIO sample is same as expected sample
3 Current GPIO sample is not same as expected sample

12:10 SS3SMPEXP

Expected GPIO Sample for SensorStrobe Channel 3.

(R/W)

RTC_SR7.SS3SMPMTCHIRQ is set if RTC_SR7.SS3SMP matches
RTC_CR7SSS.SS3SMPEXP as per RTC_CR7SSS.SS3SMPPTRN. This register
provides the expected GPIO sample value for pattern matching.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

Table 21-21: RTC_CR7SSS Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9:8 SS2SMPPTRN(R/W)

Sample Activity Selection for SensorStrobe Channel 2.
This field is used to set the status bit RTC_SR7.SS2SMPMTCHIRQ based on expected pattern RTC_CR7SSS.SS2SMPEXP or change in the sampled value.
0 Current GPIO sample is not same as previous sample
1 Current GPIO sample is same as previous sample
2 Current GPIO sample is same as expected sample
3 Current GPIO sample is not same as expected sample

7:5 SS2SMPEXP(R/W)

4:3 SS1SMPPTRN(R/W)

Expected GPIO Sample for SensorStrobe Channel 2.
RTC_SR7.SS2SMPMTCHIRQ is set if RTC_SR7.SS2SMP matches
RTC_CR7SSS.SS2SMPEXP as per RTC_CR7SSS.SS2SMPPTRN. This register
provides the expected GPIO sample value for pattern matching.
Sample Activity Selection for SensorStrobe Channel 1.
This field is used to set the status bit RTC_SR7.SS1SMPMTCHIRQ based on expected pattern RTC_CR7SSS.SS1SMPEXP or change in the sampled value.
0 Current GPIO sample is not same as previous sample
1 Current GPIO sample is same as previous sample
2 Current GPIO sample is same as expected sample
3 Current GPIO sample is not same as expected sample

2:0 SS1SMPEXP
(R/W)

21–56

Expected GPIO Sample for SensorStrobe Channel 1.
RTC_SR7.SS1SMPMTCHIRQ is set if RTC_SR7.SS1SMP matches
RTC_CR7SSS.SS1SMPEXP as per RTC_CR7SSS.SS1SMPPTRN. This register
provides the expected GPIO sample value for pattern matching.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Freeze CountRTC Freeze Count MMR allows a coherent, triple 16-bit read of the 47-bit RTC count contained in RTC_CNT2,
RTC_CNT1 and RTC_CNT0.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FRZCNT (R)RTC Freeze Count. Coherent, Triple
16-Bit Read of the 47-Bit RTC Count

Figure 21-23: RTC_FRZCNT Register Diagram
Table 21-22: RTC_FRZCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 FRZCNT(R/NW)RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count.
This field is always read in sequences of three reads, such that the first read in the sequence returns the current value of RTC_CNT0.
Simultaneously, with this first read, a snapshot is taken and frozen of the value of
RTC_CNT1 and RTC_CNT2 so that in the second and third reads in the sequence of
RTC_FRZCNT.FRZCNT, the snapshot values of RTC_CNT1 and RTC_CNT2 are returned respectively. The sequence number for such a triplet of reads is visible via
RTC_SR6.FRZCNTPTR.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC GPIO Pin Mux Control Register 0
RTC_GPMUX0is a control register for selecting a GPIO (pin) as data to be sampled by a SensorStrobe channel. This
register has to be updated only when appropriate SensorStrobe channel is disabled. Note that this register only exists
in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

1

SS2GPIN1SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 2 Input 1

SS1GPIN0SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 1 Input0

SS2GPIN0SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 2 Input 0

SS1GPIN1SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 1 Input 1

SS1GPIN2SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 1 Input 2

Figure 21-24: RTC_GPMUX0 Register Diagram
Table 21-23: RTC_GPMUX0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14:12 SS2GPIN1SELGPIO Mux Selection for SensorStrobe Channel 2 Input 1.

(R/W)

SensorStrobe channel 2 gpio input to be sampled is GPIO
[RTC_GPMUX0.SS2GPIN1SEL].

11:9 SS2GPIN0SEL(R/W)
8:6 SS1GPIN2SEL(R/W)
5:3 SS1GPIN1SEL(R/W)
2:0 SS1GPIN0SEL
(R/W)

21–58

GPIO Mux Selection for SensorStrobe Channel 2 Input 0.
SensorStrobe channel 2 gpio input to be sampled is GPIO
[RTC_GPMUX0.SS2GPIN0SEL].
GPIO Mux Selection for SensorStrobe Channel 1 Input 2.
SensorStrobe channel 1 gpio input to be sampled is GPIO
[RTC_GPMUX0.SS1GPIN2SEL].
GPIO Mux Selection for SensorStrobe Channel 1 Input 1.
SensorStrobe channel 1 gpio input to be sampled is GPIO
[RTC_GPMUX0.SS1GPIN1SEL].
GPIO Mux Selection for SensorStrobe Channel 1 Input0.
SensorStrobe channel 1 gpio input to be sampled is GPIO
[RTC_GPMUX0.SS1GPIN0SEL].

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC GPIO Pin Mux Control Register 1
RTC_GPMUX1 is a control register for selecting a GPIO (pin) as data to be sampled by a SensorStrobe channel.
This register has to be updated only when appropriate SensorStrobe channel is disabled. Note that this register only
exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

1

1

1

0

1

0

1

0

0

0

0

0

0

SS3DIFFOUT (R/W)
Differential SensorStrobe Out Option
for SensorStrobe Channel 3

SS2GPIN2SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 2 Input 2

SS1DIFFOUT (R/W)
Differential SensorStrobe Out Option
for SensorStrobe Channel 1

SS3GPIN0SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 3 Input 0

SS3GPIN2SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 3 Input 2

SS3GPIN1SEL (R/W)
GPIO Mux Selection for SensorStrobe
Channel 3 Input 1

Figure 21-25: RTC_GPMUX1 Register Diagram
Table 21-24: RTC_GPMUX1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 SS3DIFFOUT(R/W)

14 SS1DIFFOUT(R/W)

11:9 SS3GPIN2SEL(R/W)
8:6 SS3GPIN1SEL(R/W)
5:3 SS3GPIN0SEL(R/W)
2:0 SS2GPIN2SEL(R/W)

Differential SensorStrobe Out Option for SensorStrobe Channel 3.
SensorStrobe channel 3 is used as differential signal, actual RTC_SS3 out for thischannel is available in corresponding GPIO. RTC_SS4 is used to provided inverted
signal of RTC_SS3.
Differential SensorStrobe Out Option for SensorStrobe Channel 1.
SensorStrobe channel 1 is used as differential signal, actual RTC_SS1 out for thischannel is available in corresponding GPIO. RTC_SS2 of SensorStrobe channel 2 isused to provided inverted signal of RTC_SS1.
GPIO Mux Selection for SensorStrobe Channel 3 Input 2.
SensorStrobe channel 3 gpio input to be sampled is GPIO
[RTC_GPMUX1.SS3GPIN2SEL].
GPIO Mux Selection for SensorStrobe Channel 3 Input 1.
SensorStrobe channel 3 gpio input to be sampled is GPIO
[RTC_GPMUX1.SS3GPIN1SEL].
GPIO Mux Selection for SensorStrobe Channel 3 Input 0.
SensorStrobe channel 3 gpio input to be sampled is GPIO
[RTC_GPMUX1.SS3GPIN0SEL].
GPIO Mux Selection for SensorStrobe Channel 2 Input 2.
SensorStrobe channel 2 gpio input to be sampled is GPIO
[RTC_GPMUX1.SS2GPIN2SEL].

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ADuCM4050 RTC Register Descriptions

RTC Gateway
RTC_GWY is a gateway MMR address through which the CPU can order actions to be taken within the RTC. The
CPU does this by writing specific keys to RTC_GWY. Note that RTC_GWY reads back as all zeros.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SWKEY (W)
Software-keyed Command Issued by
the CPU

Figure 21-26: RTC_GWY Register Diagram
Table 21-25: RTC_GWY Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SWKEY(RX/W)

Software-keyed Command Issued by the CPU.
The RTC_GWY register is the write target for activating software-keyed commands issued by the CPU to the RTC. The supported keys are as follows:(i) A FLUSH_RTC software key (delivered via a register write to RTC_GWY) of value
0xa2c5 causes the RTC to flush (discard) all posted write transactions and to immediately stop any transaction that is currently executing.
(ii) A SNAPSHOT_RTC key of value 0x7627 (delivered via a register write to
RTC_GWY) causes the RTC to take a sticky snapshot of the value of RTC_CNT1,
RTC_CNT0 and RTC_CNT2 and store it in RTC_SNAP1, RTC_SNAP0 and
RTC_SNAP2.
(iii) A key of value 0x9376, when written to RTC_GWY, zeroes the
RTC_SR6.FRZCNTPTR pointer and thus re-initialises the 0-1-2 sequence for readsof RTC_FRZCNT.

21–60

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Input Capture Channel 2
RTC_IC2 is a read-only snapshot of the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit
RTC count at the most recent event on input capture channel 2. Note that this register only exists in RTC1. In
RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IC2 (R)
RTC Input Capture Channel 2

Figure 21-27: RTC_IC2 Register Diagram
Table 21-26: RTC_IC2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 IC2(R/NW)

RTC Input Capture Channel 2.
A snaphot of RTC time is placed with an alignment determined by prescaling into
RTC_IC2.IC2 when prompted to do so by an external requesting input into the
RTC on input capture channel 2. Such an event overwrites (if allowed by
RTC_CR2IC.ICOWUSEN) any value captured previously in RTC_IC2.IC2.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC Input Capture Channel 3
RTC_IC3 is a read-only snapshot of the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit
RTC count at the most recent event on input capture channel 3. Note that this register only exists in RTC1. In
RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IC3 (R)
RTC Input Capture Channel 3

Figure 21-28: RTC_IC3 Register Diagram
Table 21-27: RTC_IC3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 IC3(R/NW)

21–62

RTC Input Capture Channel 3.
A snaphot of RTC time is placed with an alignment determined by prescaling into
RTC_IC3.IC3 when prompted to do so by an external requesting input into the
RTC on input capture channel 3. Such an event overwrites (if allowed by
RTC_CR2IC.ICOWUSEN) any value captured previously in RTC_IC3.IC3.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Input Capture Channel 4
RTC_IC4 is a read-only snapshot of the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit
RTC count at the most recent event on input capture channel 4. Note that this register only exists in RTC1. In
RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IC4 (R)
RTC Input Capture Channel 4

Figure 21-29: RTC_IC4 Register Diagram
Table 21-28: RTC_IC4 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 IC4(R/NW)

RTC Input Capture Channel 4.
A snaphot of RTC time is placed with an alignment determined by prescaling into
RTC_IC4.IC4 when prompted to do so by an external requesting input into the
RTC on input capture channel 4. Such an event overwrites (if allowed by
RTC_CR2IC.ICOWUSEN) any value captured previously in RTC_IC4.IC4.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC Modulo
RTC_MOD is a read-only register which makes available RTC_MOD.CNTMOD60, which is the modulo-60 equivalent of the count value in RTC_CNT1 and RTC_CNT0. This modulo-60 value is equal to the displacement in prescaled RTC time units past the most recent modulo-60 roll-over event. A roll-over is a synonym for a modulo-60
boundary.
Boundaries are defined in the following way. The RTC realigns itself to create coincident modulo-60 and modulo-1
boundaries whenever any of the following events occurs :(i) the CPU writes a new pair of values to the RTC_CNT1 and RTC_CNT0 registers to redefine the elapsed timeunits count while the RTC is enabled and this posted twin write is subsequently executed.
(ii) the CPU enables the RTC from a disabled state using the RTC_CR0.CNTEN field.
(iii) while the RTC is enabled by RTC_CR0.CNTEN, the degree of prescaling in the RTC is changed via the
RTC_CR1.PRESCALE2EXP field.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

CNT0_4TOZERO (R)
Mirror of RTC_CNT0[4:0]

CNTMOD60 (R)Modulo-60 Value of the RTC Count:
RTC_CNT1 and RTC_CNT0

TRMBDY (R)
Trim Boundary Indicator

INCR (R)Most Recent Increment Value Added
to the RTC Count in RTC_CNT1 and
RTC_CNT0

Figure 21-30: RTC_MOD Register Diagram
Table 21-29: RTC_MOD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:11 CNT0_4TOZERO(R/NW)

Mirror of RTC_CNT0[4:0].
RTC_MOD.CNT0_4TOZERO is a mirror of RTC_CNT0[4:0], available for simultaneous read-back along with the RTC_MOD.CNTMOD60 field.
Having this mirror available at the same time allows the relationship between the modulo-60 and absolute versions of the RTC count to be better understood and debugged.

21–64

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-29: RTC_MOD Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10 TRMBDY(R/NW)

Trim Boundary Indicator.
Trim boundary indicator that the most recent RTC count increment has coincidedwith trimming of the count value.
0 Trimming has not occurred at the most recent increment of the RTC count.
1 Trimming has occurred at the most recent increment of
the RTC count

9:6 INCR(R/NW)

Most Recent Increment Value Added to the RTC Count in RTC_CNT1 and
RTC_CNT0.
RTC_MOD.INCR is a read-only value by which the RTC count has most recently
been incremented. Under normal circumstances, when the RTC is enabled, this value
will be one. However, when trimming occurs, RTC_MOD.INCR can be any integer
value between zero and eight, depending on the trim configuration in the RTC_TRM
register.

5:0 CNTMOD60(R/NW)

Modulo-60 Value of the RTC Count: RTC_CNT1 and RTC_CNT0.
RTC_MOD.CNTMOD60 counts from 0 to 59, and then rolls over to 0 again. It advances (and is trimmed) in tandem with the main RTC count in RTC_CNT1,
RTC_CNT0 and RTC_CNT2.
RTC_MOD.CNTMOD60 is zeroed whenever any of the following events occurs:(i) A normal roll-over from a value of 59 when advancing at a prescaled time unit.
(ii) whenever the CPU writes a new pair of values to the RTC_CNT1 and RTC_CNT0
registers to redefine the elapsed time count while the RTC is enabled and this posted
twin write is executed.
(iii) the CPU enables the RTC from a disabled state using the RTC_CR0.CNTEN
field.
(iv) while the RTC is enabled via RTC_CR0.CNTEN, the degree of prescaling in the
RTC is changed via the RTC_CR1.PRESCALE2EXP field.
This bit field only exists in RTC1. In RTC0, the field is reserved and reads back as all
zeros.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC SensorStrobe Channel 1
RTC_SS1 is the scheduled alarm time for SensorStrobe channel 1 with respect to the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit RTC count. The upper bits of the main RTC count, beyond these 16
bit positions, are don't cares for the purposes of the 16-bit RTC_SS1 SensorStrobe channel.
Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS1 (R/W)
SensorStrobe Channel 1

Figure 21-31: RTC_SS1 Register Diagram
Table 21-30: RTC_SS1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS1(R/W)

SensorStrobe Channel 1.
Scheduled alarm target time for SensorStrobe channel 1, with optional auto-reloading
and masking.
When an SensorStrobe match with the RTC count occurs, the value in
RTC_SS1.SS1 is either maintained or auto-reloaded from a separate 16-bit register.
This update is given by:
RTC_SS1.SS1 = RTC_CR4SS.SS1ARLEN ? RTC_SS1.SS1 + ((RTC_SS1 ?
RTC_SS1HIGHDUR : RTC_SS1LOWDUR) : RTC_SS1.SS1.

21–66

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Auto-Reload High Duration for SensorStrobe Channel 1
RTC_SS1HIGHDUR contains the 16-bit reload value which is optionally (enabled by RTC_CR4SS.SS1ARLEN)
added to the cumulative value of RTC_SS1, visible in the RTC_SS1TGT register, whenever a enabled SensorStrobe
event occurs on that channel. The use of RTC_SS1HIGHDUR allows a repeating alarm whose periodicity either is
or is not a power of 2 to be put into effect for RTC_SS1. If reloading is not enabled, the read-back values of
RTC_SS1 and RTC_SS1TGT are the same, namely the starting (and not reloaded because not enabled) SensorStrobe value in RTC_SS1. Note that this register only exists in RTC1. In RTC0, the register address is reserved andreads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS1HIGHDUR (R/W)
High Duration for SensorStrobe Channel 1

Figure 21-32: RTC_SS1HIGHDUR Register Diagram
Table 21-31: RTC_SS1HIGHDUR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS1HIGHDUR(R/W)

High Duration for SensorStrobe Channel 1.
If auto-reloading of RTC_SS1 is enabled via RTC_CR4SS.SS1ARLEN, the contents of RTC_SS1HIGHDUR controls the high duration of SensorStrobe channel 1.
RTC_SS1TGT initial value is RTC_SS1.
This is expressed as:
RTC_SS1TGT = RTC_CR4SS.SS1ARLEN ? (RTC_SS1TGT + (SensorStrobe
channel 1 output level ? RTC_SS1LOWDUR : RTC_SS1HIGHDUR)) :RTC_SS1.SS1.
SensorStrobe channel 1 toggles when RTC timer value reaches RTC_SS1TGT andnew value for RTC_SS1TGT is updated as mentioned above.
In such circumstances, RTC_SS1TGT acts as a repeating alarm with alternate load
values RTC_SS1LOWDUR and RTC_SS1HIGHDUR, whereby those bits which are
not masked in the reload value effectively define the step size (offset) from the current
time to the next SensorStrobe alarm.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC Auto-Reload Low Duration for SensorStrobe Channel 1
RTC_SS1LOWDUR contains the 16-bit reload value which is optionally (enabled by RTC_CR4SS.SS1ARLEN)
added to the cumulative value of RTC_SS1, visible in the RTC_SS1TGT register, whenever a enabled SensorStrobe
event occurs on that channel.
The use of RTC_SS1LOWDUR allows a repeating alarm whose periodicity either is or is not a power of 2 to be put
into effect for RTC_SS1.
If reloading is not enabled, the read-back values of RTC_SS1 and RTC_SS1TGT are the same, namely the starting(and not reloaded because not enabled) SensorStrobe value in RTC_SS1. Note that this register only exists in
RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS1LOWDUR (R/W)
Low Duration for SensorStrobe Channel 1

Figure 21-33: RTC_SS1LOWDUR Register Diagram
Table 21-32: RTC_SS1LOWDUR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS1LOWDUR(R/W)

Low Duration for SensorStrobe Channel 1.
If auto-reloading of RTC_SS1 is enabled via RTC_CR4SS.SS1ARLEN, the contents of RTC_SS1LOWDUR controls the low duration of RTC_SS1 SensorStrobe
channel. RTC_SS1TGT initial value is RTC_SS1.
This is expressed as:
RTC_SS1TGT = RTC_CR4SS.SS1ARLEN ? (RTC_SS1TGT + (SensorStrobe
channel 1 level ? RTC_SS1LOWDUR : RTC_SS1HIGHDUR)) : RTC_SS1.SS1.
SensorStrobe channel 1 output toggles when RTC timer value reaches RTC_SS1TGTand new value for RTC_SS1TGT is updated as mentioned above.
In such circumstances, RTC_SS1TGT acts as a repeating alarm with alternate load
values RTC_SS1LOWDUR and RTC_SS1HIGHDUR, whereby those bits which are
not masked in the reload value effectively define the step size (offset) from the current
time to the next SensorStrobe alarm.

21–68

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC SensorStrobe Channel 1 Target
Reflects the current, cumulative target alarm time for the SensorStrobe channel 1. This register only exists in RTC1.
In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS1TGT (R)Current Target Value for the SensorStrobe
Channel 1

Figure 21-34: RTC_SS1TGT Register Diagram
Table 21-33: RTC_SS1TGT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS1TGT(R/NW)

Current Target Value for the SensorStrobe Channel 1.
Provides visibility to the CPU of the current target value for the SensorStrobe Channel
1, taking account of any possible auto-reloading.
If auto-reloading is disabled by RTC_CR4SS.SS1ARLEN, the value returned by thisfield is identical to the starting value of the RTC_SS1 register.
If auto-reloading is enabled, a read-back of this field returns the current, cumulative
target value for the SensorStrobe channel 1, having started the SensorStrobe sequence
from the value contained in the RTC_SS1 register and then reloaded, i.e. additively
accumulated a new target time (offset by the value in RTC_SS1LOWDUR and
RTC_SS1HIGHDUR) every time an SensorStrobe event occurs.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC SensorStrobe Channel 2This register is the scheduled alarm time for SensorStrobe channel 2 with respect to the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit RTC count. The upper bits of the main RTC count, beyond these 16
bit positions, are don't cares for the purposes of the 16-bit SensorStrobe channel 2. Note that this register only exists
in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS2 (R/W)
SensorStrobe Channel 2

Figure 21-35: RTC_SS2 Register Diagram
Table 21-34: RTC_SS2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS2(R/W)

SensorStrobe Channel 2.
It contains a 16-bit target value which causes an SensorStrobe alarm activation whenever there is a masked match between {RTC_CNT0[(15 - PRESCALE2EXP):0],
RTC_CNT2[15:0]} and {RTC_SS2[(15 - PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b0}}, RTC_SS2[(PRESCALE2EXP - 1):0]}.
The active high mask for the match, i.e. don't care bit positions for the comparison, isdefined as {TCODEMSK2[(15 - PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b1}}, TCODEMSK2[(PRESCALE2EXP - 1):0]}, where TCODEMSK2[15:0] is athermometer-decoded mask defined by RTC_CR4SS.SS2MSKEN ? (16'hFFFF <<RTC_SSMSK[7:4]) : 16'h0000.
When an SensorStrobe match occurs, the value in RTC_SS2.SS2 is either maintained or auto-reloaded from a separate 16-bit register. This update is given by
RTC_SS2.SS2 = RTC_CR4SS.SS2ARLEN ? RTC_SS2.SS2 + (RTC_SS2 ?
RTC_SS2HIGHDUR : RTC_SS2LOWDUR) : RTC_SS2.SS2.
RTC_SS2 gives the user the ability to schedule repeating alarms whose target time ischecked against the 16 least significant {integer_bits, fractional_bits} of the RTC countdefined by RTC_CNT1, RTC_CNT0, and RTC_CNT2 (fractional bits in
RTC_CNT2) which have meaning, considering the degree of prescaling of the base 32
kHz clock.

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ADuCM4050 RTC Register Descriptions

RTC Auto-Reload High Duration for SensorStrobe Channel 2
RTC_SS2HIGHDUR contains the 16-bit reload value which is optionally (enabled by RTC_CR4SS.SS2ARLEN)
added to the cumulative value of RTC_SS2, visible in the RTC_SS2TGT register, whenever a enabled SensorStrobe
event occurs on that channel.
The use of RTC_SS2HIGHDUR allows a repeating alarm whose periodicity either is or is not a power of 2 to be put
into effect for RTC_SS2.
If reloading is not enabled, the read-back values of RTC_SS2 and RTC_SS2TGT are the same, namely the starting(and not reloaded because not enabled) SensorStrobe value in RTC_SS2. Note that this register only exists in
RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS2HIGHDUR (R/W)
High Duration for SensorStrobe Channel 2

Figure 21-36: RTC_SS2HIGHDUR Register Diagram
Table 21-35: RTC_SS2HIGHDUR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS2HIGHDUR(R/W)

High Duration for SensorStrobe Channel 2.
If auto-reloading of RTC_SS2 is enabled via RTC_CR4SS.SS2ARLEN, the contents of RTC_SS2HIGHDUR controls the high duration of SensorStrobe channel 2.
RTC_SS2TGT initial value is RTC_SS2.
This is expressed as:
RTC_SS2TGT = RTC_CR4SS.SS2ARLEN ? (RTC_SS2TGT + (SensorStrobe
channel 2 level ? RTC_SS2LOWDUR : RTC_SS2HIGHDUR)) : RTC_SS2.SS2.
SensorStrobe channel 2 toggles when RTC timer value reaches RTC_SS2TGT andnew value for RTC_SS2TGT is updated as mentioned above.
In such circumstances, RTC_SS2TGT acts as a repeating alarm with alternate load
values RTC_SS2LOWDUR and RTC_SS2HIGHDUR, whereby those bits which are
not masked in the reload value effectively define the step size (offset) from the current
time to the next SensorStrobe alarm.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC Auto-Reload Low Duration for SensorStrobe Channel 2
RTC_SS2LOWDUR contains the 16-bit reload value which is optionally (enabled by RTC_CR4SS.SS2ARLEN)
added to the cumulative value of RTC_SS2, visible in the RTC_SS2TGT register, whenever a enabled SensorStrobe
event occurs on that channel.
The use of RTC_SS2LOWDUR allows a repeating alarm whose periodicity either is or is not a power of 2 to be put
into effect for RTC_SS2.
If reloading is not enabled, the read-back values of RTC_SS2 and RTC_SS2TGT are the same, namely the starting(and not reloaded because not enabled) SensorStrobe value in RTC_SS2.
Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS2LOWDUR (R/W)
Low Duration for SensorStrobe Channel 2

Figure 21-37: RTC_SS2LOWDUR Register Diagram
Table 21-36: RTC_SS2LOWDUR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS2LOWDUR(R/W)

Low Duration for SensorStrobe Channel 2.
If auto-reloading of RTC_SS2 is enabled via RTC_CR4SS.SS2ARLEN, the contents of RTC_SS2LOWDUR controls the low duration of RTC_SS2 SensorStrobe
channel. RTC_SS2TGT initial value is RTC_SS2.
This is expressed as:
RTC_SS2TGT = RTC_CR4SS.SS2ARLEN ? (RTC_SS2TGT + (SensorStrobe
channel 2 level ? RTC_SS2LOWDUR : RTC_SS2HIGHDUR)) : RTC_SS2.SS2.
SensorStrobe channel 2 output toggles when RTC timer value reaches RTC_SS2TGTand new value for RTC_SS2TGT is updated as mentioned above.
In such circumstances, RTC_SS2TGT acts as a repeating alarm with alternate load
values RTC_SS2LOWDUR and RTC_SS2HIGHDUR, whereby those bits which are
not masked in the reload value effectively define the step size (offset) from the current
time to the next SensorStrobe alarm.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC SensorStrobe Channel 2 Target
Read-only register which reflects the current, cumulative target alarm time for the SensorStrobe channel 2, taking
account of any auto-reloading upon SensorStrobe events. This register only exists in RTC1. In RTC0, the register
address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS2TGT (R)Current, Cumulative Target Time for
SensorStrobe Channel 2, Taking Accountof Any Auto-reloading

Figure 21-38: RTC_SS2TGT Register Diagram

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

Table 21-37: RTC_SS2TGT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS2TGT(R/NW)

Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any
Auto-reloading.
RTC_SS2TGT.SS2TGT is a read-only register which gives visibility to the CPU ofthe current target value for the SensorStrobe channel RTC_SS2, taking account of any
possible auto-reloading.
If auto-reloading is not enabled by RTC_CR4SS.SS2ARLEN, the value returned by
RTC_SS2TGT.SS2TGT is identical to that of the RTC_SS2 register, i.e. the starting value for the SensorStrobe channel 2.
If auto-reloading is enabled, a read-back of RTC_SS2TGT.SS2TGT returns the current, cumulative target value for the RTC_SS2 channel, having started the SensorStrobe sequence from the value contained in the RTC_SS2 register and then reloaded,
i.e. additively accumulated a new target time (offset by the value in
RTC_SS2LOWDUR and RTC_SS2HIGHDUR) every time a SensorStrobe event occurs.
Note that any of the following configuration changes, when synchronized to the 32
kHz domain, causes a re-initialization of the cumulative RTC_SS2TGT.SS2TGT
target time, such that it is set back again to the starting value in the RTC_SS2 register
for any subsequent auto-reload sequence. In other words, any of the following willcause a new reload sequence to be begun, with RTC_SS2TGT.SS2TGT re-initialized
to the value in RTC_SS2:[1] A redefinition occurs of the starting value itself due to a write to the RTC_SS2
MMR.
[2] Whenever RTC_CR3SS.SS2EN transitions from 0 to 1, thus enabling the
RTC_SS2 SensorStrobe channel.
[3] Whenever RTC_CR4SS.SS2ARLEN transitions from 1 to 0, thus disabling autoreloading for RTC_SS2.
Note that RTC_SS2TGT.SS2TGT is sourced in the 32 kHz domain and WSYNC
flags for any related MMR redefinitions should be checked to be 1'b1 (effects
synchronized to the PCLK domain) if such redefinitions affect the target time for the
RTC_SS2 channel, reflected in RTC_SS2TGT.SS2TGT.

21–74

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC SensorStrobe Channel 3This register is the scheduled alarm time for SensorStrobe channel 3 with respect to the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit RTC count. The upper bits of the main RTC count, beyond these 16
bit positions, are don't cares for the purposes of the 16-bit SensorStrobe channel 3. Note that this register only exists
in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS3 (R/W)
SensorStrobe Channel 3

Figure 21-39: RTC_SS3 Register Diagram
Table 21-38: RTC_SS3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS3(R/W)

SensorStrobe Channel 3.
It contains a 16-bit target value which causes an SensorStrobe alarm activation whenever there is a masked match between {RTC_CNT0[(15 - PRESCALE2EXP):0],
RTC_CNT2[15:0]} and {RTC_SS3[(15 - PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b0}}, RTC_SS3[(PRESCALE2EXP - 1):0]}.
The active-high mask for the match, i.e. don't care bit positions for the comparison, isdefined as {TCODEMSK3[(15 - PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b1}}, TCODEMSK3[(PRESCALE2EXP - 1):0]}, where TCODEMSK3[15:0] is athermometer-decoded mask defined by RTC_CR4SS.SS3MSKEN ? (16'hFFFF <<RTC_SSMSK[11:8]) : 16'h0000.
When an SensorStrobe match occurs, the value in RTC_SS3.SS3 is either maintained or auto-reloaded from a separate 16-bit register. This update is given by
RTC_SS3.SS3 = RTC_CR4SS.SS3ARLEN ? RTC_SS3.SS3 + ((RTC_SS3) ?
RTC_SS3HIGHDUR : RTC_SS3LOWDUR) : RTC_SS3.SS3.
RTC_SS3 gives the user the ability to schedule repeating alarms whose target time ischecked against the 16 least significant {integer_bits, fractional_bits} of the RTC countdefined by RTC_CNT1, RTC_CNT0, and RTC_CNT2 (fractional bits in
RTC_CNT2) which have meaning, considering the degree of prescaling of the base 32
kHz clock.

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ADuCM4050 RTC Register Descriptions

RTC Auto-Reload High Duration for SensorStrobe Channel 3
RTC_SS3HIGHDUR contains the 16-bit reload value which is optionally (enabled by RTC_CR4SS.SS3ARLEN)
added to the cumulative value of RTC_SS3, visible in the RTC_SS3TGT register, whenever a enabled SensorStrobe
event occurs on that channel. The use of RTC_SS3HIGHDUR allows a repeating alarm whose periodicity either is
or is not a power of 2 to be put into effect for RTC_SS3. If reloading is not enabled, the read-back values of
RTC_SS3 and RTC_SS3TGT are the same, namely the starting (and not reloaded because not enabled) SensorStrobe value in RTC_SS3. Note that this register only exists in RTC1. In RTC0, the register address is reserved andreads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS3HIGHDUR (R/W)
High Duration for SensorStrobe Channel 3

Figure 21-40: RTC_SS3HIGHDUR Register Diagram
Table 21-39: RTC_SS3HIGHDUR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS3HIGHDUR(R/W)

High Duration for SensorStrobe Channel 3.
If auto-reloading of RTC_SS3 is enabled via RTC_CR4SS.SS3ARLEN, the contents of RTC_SS3HIGHDUR controls the high duration of SensorStrobe channel 3.
RTC_SS3TGT initial value is RTC_SS3.
This is expressed as:
RTC_SS3TGT = RTC_CR4SS.SS3ARLEN ? (RTC_SS3TGT + (SensorStrobe
channel 3 level ? RTC_SS3LOWDUR : RTC_SS3HIGHDUR)) : RTC_SS3.SS3.
SensorStrobe channel 3toggles when RTC timer value reaches RTC_SS3TGT and newvalue for RTC_SS3TGT is updated as mentioned above.
In such circumstances, RTC_SS3TGT acts as a repeating alarm with alternate load
values RTC_SS3LOWDUR and RTC_SS3HIGHDUR, whereby those bits which are
not masked in the reload value effectively define the step size (offset) from the current
time to the next SensorStrobe alarm.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Auto-Reload Low Duration for SensorStrobe Channel 3
RTC_SS3LOWDUR contains the 16-bit reload value which is optionally (enabled by RTC_CR4SS.SS3ARLEN)
added to the cumulative value of RTC_SS3, visible in the RTC_SS3TGT register, whenever a enabled SensorStrobe
event occurs on that channel. The use of RTC_SS3LOWDUR allows a repeating alarm whose periodicity either is or
is not a power of 2 to be put into effect for RTC_SS3. If reloading is not enabled, the read-back values of
RTC_SS3 and RTC_SS3TGT are the same, namely the starting (and not reloaded because not enabled) SensorStrobe value in RTC_SS3. Note that this register only exists in RTC1. In RTC0, the register address is reserved andreads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS3LOWDUR (R/W)
Low Duration for SensorStrobe Channel 3

Figure 21-41: RTC_SS3LOWDUR Register Diagram
Table 21-40: RTC_SS3LOWDUR Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS3LOWDUR(R/W)

Low Duration for SensorStrobe Channel 3.
If auto-reloading of RTC_SS3 is enabled via RTC_CR4SS.SS3ARLEN, the contents of RTC_SS3LOWDUR controls the low duration of RTC_SS3 SensorStrobe
channel. RTC_SS3TGT initial value is RTC_SS3.
This is expressed as:
RTC_SS3TGT = RTC_CR4SS.SS3ARLEN ? (RTC_SS3TGT + (SensorStrobe
channel 3 level ? RTC_SS3LOWDUR : RTC_SS3HIGHDUR)) : RTC_SS3.SS3.
SensorStrobe channel 3 output toggles when RTC timer value reaches RTC_SS3TGT
and new value for RTC_SS3TGT is updated as mentioned above.
In such circumstances, RTC_SS3TGT acts as a repeating alarm with alternate load
values RTC_SS3LOWDUR and RTC_SS3HIGHDUR, whereby those bits which are
not masked in the reload value effectively define the step size (offset) from the current
time to the next SensorStrobe alarm.

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ADuCM4050 RTC Register Descriptions

RTC SensorStrobe Channel 3 Target
Read-only register which reflects the current, cumulative target alarm time for the SensorStrobe channel 3, taking
account of any auto-reloading upon SensorStrobe events. This register only exists in RTC1. In RTC0, the register
address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS3TGT (R)Current, Cumulative Target Time for
SensorStrobe Channel 3, Taking Accountof Any Auto-reloading

Figure 21-42: RTC_SS3TGT Register Diagram

21–78

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-41: RTC_SS3TGT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS3TGT(R/NW)

Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any
Auto-reloading.
RTC_SS3TGT.SS3TGT is a read-only register which gives visibility to the CPU ofthe current target value for the SensorStrobe channel RTC_SS3, taking account of any
possible auto-reloading.
Note that if auto-reloading is not enabled by RTC_CR4SS.SS3ARLEN, the value returned by RTC_SS3TGT.SS3TGT is identical to that of the RTC_SS3 register, i.e.
the starting value for the SensorStrobe channel 3.
However, if auto-reloading is enabled, a read-back of RTC_SS3TGT.SS3TGT returns the current, cumulative target value for the RTC_SS3 channel, having started
the SensorStrobe sequence from the value contained in the RTC_SS3 register andthen reloaded, i.e. additively accumulated a new target time (offset by the value in
RTC_SS3LOWDUR and RTC_SS3HIGHDUR) every time an SensorStrobe event occurs.
Note that any of the following configuration changes, when synchronized to the 32
kHz domain, causes a re-initialization of the cumulative RTC_SS3TGT.SS3TGT
target time, such that it is set back again to the starting value in the RTC_SS3 register
for any subsequent auto-reload sequence. In other words, any of the following willcause a new reload sequence to be begun, with RTC_SS3TGT.SS3TGT re-initialized
to the value in RTC_SS3:[1] A redefinition occurs of the starting value itself due to a write to the RTC_SS3
MMR.
[2] Whenever RTC_CR3SS.SS3EN transitions from 0 to 1, thus enabling the
RTC_SS3 SensorStrobe channel.
[3] Whenever RTC_CR4SS.SS3ARLEN transitions from 1 to 0, thus disabling autoreloading for RTC_SS3.
Note that RTC_SS3TGT.SS3TGT is sourced in the 32 kHz domain and WSYNC
flags for any related MMR redefinitions should be checked to be 1'b1 (i.e. effects
synchronized to the PCLK domain) if such redefinitions affect the target time for the
RTC_SS3 channel, reflected in RTC_SS3TGT.SS3TGT.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

RTC SensorStrobe Channel 4This register is the scheduled alarm time for SensorStrobe channel 4 with respect to the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit RTC count. The upper bits of the main RTC count, beyond these 16
bit positions, are don't cares for the purposes of the 16-bit SensorStrobe channel 4. Note that this register only exists
in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS4 (R/W)
SensorStrobe Channel 4

Figure 21-43: RTC_SS4 Register Diagram
Table 21-42: RTC_SS4 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 SS4(R/W)

SensorStrobe Channel 4.
It contains a 16-bit target value which causes an SensorStrobe alarm activation whenever there is a masked match between {RTC_CNT0[(15 - PRESCALE2EXP):0],
RTC_CNT2[15:0]} and {RTC_SS4[(15 - PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b0}}, RTC_SS4[(PRESCALE2EXP - 1):0]}.
The active-high mask for the match, i.e. don't care bit positions for the comparison, isdefined as {TCODEMSK4[(15 - PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b1}}, TCODEMSK4[(PRESCALE2EXP - 1):0]}, where TCODEMSK4[15:0] is athermometer-decoded mask defined by RTC_CR4SS.SS4MSKEN ? (16'hFFFF <<RTC_SSMSK[15:12]) : 16'h0000.
Unlike RTC_SS1, auto-reloading upon an SensorStrobe event is not available on
RTC_SS2, RTC_SS3 or RTC_SS4. Instead, when an SensorStrobe match occurs,
the value in RTC_SS4 is maintained. SensorStrobe channel 4 therefore acts as a repeating alarm whose periodicity is a power of 2, given by the unmasked bits in
RTC_SS4.
RTC_SS4 gives the user the ability to schedule repeating alarms whose target time ischecked against the 16 least significant {integer_bits, fractional_bits} of the RTC countdefined by RTC_CNT1, RTC_CNT0, and RTC_CNT2 (fractional bits in
RTC_CNT2) which have meaning, considering the degree of prescaling of the base 32
kHz clock.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Mask for SensorStrobe Channel
RTC_SSMSK contains a 4-bit encoded mask, which is decoded out to a 16-bit thermometer-code mask to define
contiguous don't care bit positions for target alarm times in the 16-bit SensorStrobe channel 1. Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS4MSK (R/W)
SensorStrobe Channel 4 Period Control
SS3MSK (R/W)
SensorStrobe Channel 3 Period Control

00SS1MSK (R/W)
Concatenation of Thermometer-Encoded
Masks for the 16-bit SensorStrobe Channels
SS2MSK (R/W)
SensorStrobe Channel 2 Period Control

Figure 21-44: RTC_SSMSK Register Diagram
Table 21-43: RTC_SSMSK Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:12 SS4MSK

SensorStrobe Channel 4 Period Control.

(R/W)

SensorStrobe Channel 4 period is 2 * RTC_SSMSK.SS4MSK RTC clock period. In asimilar fashion to RTC_SSMSK[3:0] for SensorStrobe Channel 1, RTC_SSMSK[7:4]
is decoded out as an optional mask for SensorStrobe Channel 2, RTC_SSMSK[11:8]
for SensorStrobe Channel 3 and RTC_SSMSK[15:12] for SensorStrobe Channel 4.

11:8 SS3MSK(R/W)

7:4 SS2MSK(R/W)

SensorStrobe Channel 3 Period Control.
SensorStrobe Channel 3 period is 2 * RTC_SSMSK.SS3MSK RTC clock period. In asimilar fashion to RTC_SSMSK[3:0] for SensorStrobe Channel 1, RTC_SSMSK[7:4]
is decoded out as an optional mask for SensorStrobe Channel 2, RTC_SSMSK[11:8]
for SensorStrobe Channel 3 and RTC_SSMSK[15:12] for SensorStrobe Channel 4.
SensorStrobe Channel 2 Period Control.
SensorStrobe channel 2 period is 2 * RTC_SSMSK.SS2MSK RTC clock period. In asimilar fashion to RTC_SSMSK[3:0] for SensorStrobe Channel 1, RTC_SSMSK[7:4]
is decoded out as an optional mask for SensorStrobe Channel 2, RTC_SSMSK[11:8]
for SensorStrobe Channel 3 and RTC_SSMSK[15:12] for SensorStrobe Channel 4.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

Table 21-43: RTC_SSMSK Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3:0 SS1MSK(R/W)

Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels.
SensorStrobe channel 1 period is 2 * RTC_SSMSK.SS1MSK RTC clock period.
RTC_SSMSK.SS1MSK contains four 4-bit thermometer-encoded masks, concatenated into a 16-bit register. Bits [3:0] when thermometer-decoded out to 16-bit values,
act as an optional mask, enabled by RTC_CR4SS.SS1MSKEN, used in the determination of matches with the RTC count for c channel RTC_SS1.
For SensorStrobe channel<n>, an active-high mask for matches with the RTC count,i.e. don't-care bit positions for the comparison, is defined as {TCODEMSK<n>[(15 PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b1}}, TCODEMSK<n>[(PRESCALE2EXP - 1):0]}, where TCODEMSK<n>[15:0] is a thermometer-decoded mask
defined by RTC_SS<n>MSKEN ? (16'hFFFF << RTC_SSMSK[(nx4)+:4]) :16'h0000, where the index, n, lies in the range 0 to 3.
Thermometer masks, independently decoded for each of the four 16-bit SensorStrobe
channels, thus take on a value from the following series : 16'h0000 (no bits masked),
16'8000 (MSBit masked), 16'hC000 (2 MSBits masked), 16'hE000, 16'hF000, ...,
16'hFFF0, 16'hFFF8, 16'hFFFC (only the 2 LSBits unmasked), 16'hFFFE (only the
LSBit unmasked), 16'hFFFF (all bits masked, implying continuous SensorStrobe
matches).

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Masks for SensorStrobe Channels on Time Control
It contains four 4-bit encoded masks, which are decoded out to four 16-bit thermometer-code masks to define contiguous don't care bit positions for target alarm times in the 16-bit SensorStrobe channel. Note that this register
only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS4MSKOT (R/W)
SensorStrobe Channel 4 on Time Control
SS3MSKOT (R/W)
SensorStrobe Channel 3 on Time Control

0

SS1MSKOT (R/W)
Concatenation of Thermometer-encoded
Masks for the 16-bit SensorStrobe Channels
SS2MSKOT (R/W)
SensorStrobe Channel 2 on Time Control

Figure 21-45: RTC_SSMSKOT Register Diagram
Table 21-44: RTC_SSMSKOT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:12 SS4MSKOT

SensorStrobe Channel 4 on Time Control.

(R/W)

This field defines the on time of the SensorStrobe channel 4 output by default. SensorStrobe channel 4 on time is 2 * RTC_SSMSKOT.SS4MSKOT RTC clock period.
If RTC_CR4SS.SS4POL is set, this register defines the off time of SensorStrobe
channel 4.

11:8 SS3MSKOT(R/W)

7:4 SS2MSKOT(R/W)

3:0 SS1MSKOT(R/W)

SensorStrobe Channel 3 on Time Control.
This field defines the on time of the SensorStrobe channel 3 output by default. SensorStrobe channel 3 on/off time is 2 * RTC_SSMSKOT.SS3MSKOT RTC clock period. If RTC_CR4SS.SS3POL is set, this register defines the off time of SensorStrobe
channel 3. This field should be 0 when RTC_CR4SS.SS3ARLEN is set.
SensorStrobe Channel 2 on Time Control.
This field defines the on time of the SensorStrobe channel 2 output by default. SensorStrobe channel 2 on/off time is 2 * RTC_SSMSKOT.SS2MSKOT RTC clock period. If RTC_CR4SS.SS2POL is set, this register defines the off time of SensorStrobe
channel 2. This field must be 0 when RTC_CR4SS.SS2ARLEN is set.
Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels.
This field defines the on time of the SensorStrobe channel 1 output by default. SensorStrobe channel 1 on/off time is 2 * RTC_SSMSKOT.SS1MSKOT RTC clock period. If RTC_CR4SS.SS1POL is set, this register defines the off time of SensorStrobe
channel 1. This field must be 0 when RTC_CR4SS.SS1ARLEN is set.

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ADuCM4050 RTC Register Descriptions

RTC Snapshot 0
RTC_SNAP0 is a sticky snapshot of the value of RTC_CNT0. It is updated, along with its counterparts
RTC_SNAP1 and RTC_SNAP2, thereby overwriting any previous value, whenever either of the following two
events occurs:(i) the CPU writes a snapshot request key of 16'h7627 to the RTC_GWY MMR.
(ii) an input capture event occurs on the Input Capture channel 0 when enabled, provided the setting
RTC_CR2IC.ICOWUSEN allows such overwriting.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)Constituent Part of the 47-bit Input
Capture Channel 0, Containing a Sticky
Snapshot of RTC_CNT0

Figure 21-46: RTC_SNAP0 Register Diagram
Table 21-45: RTC_SNAP0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)

Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of RTC_CNT0.
RTC_SNAP0.VALUE is part of the 47-bit Input Capture channel 0.

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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Snapshot 1
RTC_SNAP1 is a sticky snapshot of the value of RTC_CNT1. It is updated, along with its counterparts
RTC_SNAP0 and RTC_SNAP2, thereby overwriting any previous value, whenever either of the following two
events occurs:(i) the CPU writes a snapshot request key of 16'h7627 to the RTC_GWY MMR.
(ii) an input capture event occurs on the Input Capture channel 0 when enabled, provided the setting of
RTC_CR2IC.ICOWUSEN allows such overwriting.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)Part of the 47-bit Input Capture Channel
0 Containing a Sticky Snapshot of
RTC_CNT1

Figure 21-47: RTC_SNAP1 Register Diagram
Table 21-46: RTC_SNAP1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of
RTC_CNT1.
RTC_SNAP1.VALUE is part of the 47-bit Input Capture channel 0.

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ADuCM4050 RTC Register Descriptions

RTC Snapshot 2
RTC_SNAP2 is a sticky snapshot of the value of RTC_CNT2. It is updated, along with its counterparts
RTC_SNAP0 and RTC_SNAP1, thereby overwriting any previous value, whenever either of the following two
events occurs:(i) the CPU writes a snapshot request key of 16'h7627 to the RTC_GWY MMR.
(ii) an input capture event occurs on the Input Capture channel 0 when enabled, provided the setting of
RTC_CR2IC.ICOWUSEN allows such overwriting.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)Part of the 47-bit Input Capture Channel
0 Containing a Sticky Snapshot of RTC_CNT2

Figure 21-48: RTC_SNAP2 Register Diagram
Table 21-47: RTC_SNAP2 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14:0 VALUE(R/NW)Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of
RTC_CNT2.
RTC_SNAP2.VALUE is part of the 47-bit Input Capture channel 0.

21–86

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ADuCM4050 RTC Register Descriptions

RTC Status 0
Information on RTC operation is made available to the CPU via three status registers RTC_SR0, RTC_SR1, and
RTC_SR2. These registers include all flags related to CPU interrupt sources and error conditions within the RTC.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

ISOENB (R)
Visibility of 32kHz Sourced Registers

ALMINT (R/W1C)
Alarm Interrupt Source

WSYNCTRM (R)Synchronisation Status of Posted Writes
to RTC_TRM

MOD60ALMINT (R/W1C)
Modulo-60 RTC Alarm Interrupt Source
ISOINT (R/W1C)
RTC Power-Domain Isolation Interrupt
SourceWSYNCALM1 (R)Synchronisation Status of Posted Writes
to RTC_ALM1

WPNDERRINT (R/W1C)
Write Pending Error Interrupt Source

WSYNCALM0 (R)Synchronisation Status of Posted Writes
to RTC_ALM0

WSYNCINT (R/W1C)
Write Synchronisation Interrupt

WSYNCCNT1 (R)Synchronisation Status of Posted Writes
to RTC_CNT1

WPNDINT (R/W1C)
Write Pending Interrupt

WSYNCCNT0 (R)Synchronisation Status of Posted Writes
to RTC_CNT0

WSYNCCR0 (R)Synchronisation Status of Posted Writes
to RTC_CR0

WSYNCSR0 (R)Synchronisation Status of Posted Writes
to RTC_SR0

Figure 21-49: RTC_SR0 Register Diagram
Table 21-48: RTC_SR0 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
14 ISOENB(R/NW)

Visibility of 32kHz Sourced Registers.
Visibility status of 32 kHz sourced registers, taking account of power-domain isolation.
0 32 kHz-sourced MMRs in the always-on half of the
RTC are not visible to the CPU due to isolation.
1 32 kHz-sourced MMRs in the always-on half of the
RTC are visible to the CPU.

13 WSYNCTRM(R/NW)

Synchronisation Status of Posted Writes to RTC_TRM.
This field indicates if the effects of a posted write to RTC_TRM are visible to the CPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.

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ADuCM4050 RTC Register Descriptions

Table 21-48: RTC_SR0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
12 WSYNCALM1(R/NW)

Synchronisation Status of Posted Writes to RTC_ALM1.
This field indicates if the effects of a posted write to RTC_ALM1 are visible to theCPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.

11 WSYNCALM0(R/NW)

Synchronisation Status of Posted Writes to RTC_ALM0.
This field indicates if the effects of a posted write to RTC_ALM0 are visible to theCPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.

10 WSYNCCNT1(R/NW)

Synchronisation Status of Posted Writes to RTC_CNT1.
This field indicates if the effects of a posted write to RTC_CNT1 are visible to theCPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.

9 WSYNCCNT0(R/NW)

Synchronisation Status of Posted Writes to RTC_CNT0.
This field indicates if the effects of a posted write to RTC_CNT0 are visible to theCPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.

8 WSYNCSR0(R/NW)

Synchronisation Status of Posted Writes to RTC_SR0.
This field indicates if the effects of a posted write to RTC_SR0 are visible to the CPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.

7 WSYNCCR0(R/NW)

Synchronisation Status of Posted Writes to RTC_CR0.
This field indicates if the effects of a posted write to RTC_CR0 are visible to the CPU.
0 Results of a posted write are not yet visible by the CPU.
1 Results of a posted write are visible by the CPU.

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ADuCM4050 RTC Register Descriptions

Table 21-48: RTC_SR0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
6 WPNDINT(R/W1C)

Write Pending Interrupt.
Sticky interrupt source which is activated whenever room frees up for the CPU to posta new write transaction to a 32 kHz sourced MMR or MMR bit field in the RTC.
To enable a RTC_SR0.WPNDINT interrupt, set RTC_CR0.WPNDINTEN to 1.
RTC_SR0.WPNDINT is cleared by writing 1 to it.
0 There has been no change in the pending status of any
posted write transaction in the RTC since WPENDINT
was last cleared.
1 A posted write transaction has been dispatched since
WPENDINT was last cleared, thus freeing up a slot for
a new posted write by the CPU to the same MMR.

5 WSYNCINT(R/W1C)

Write Synchronisation Interrupt.
Sticky interrupt source which is activated whenever a posted write transaction to a 32
kHz sourced MMR or MMR bit field completes and whose effects are then visible to
the CPU.
To enable a RTC_SR0.WSYNCINT interrupt, set RTC_CR0.WSYNCINTEN to one.
RTC_SR0.WSYNCINT is cleared by writing one to it.
0 Since the CPU last cleared RTC_SR0.WSYNCINT,
there has been no occurrence of the effects of a posted
write transaction to a 32 kHz-sourced MMR or MMR
bit field have becoming newly visible to the CPU's clock
domain.
1 Since the CPU last cleared RTC_SR0.WSYNCINT, theeffects of a posted write transaction to a 32 kHz-sourced
MMR or MMR bit field have becoming newly visible to
the CPU's clock domain.

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ADuCM4050 RTC Register Descriptions

Table 21-48: RTC_SR0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
4 WPNDERRINT(R/W1C)

Write Pending Error Interrupt Source.
Sticky interrupt source which indicates that an error has occurred because the CPU attempted to write to an RTC register while a previous write to the same register was
pending execution.
A maximum of one pending write transaction per MMR is supported by the RTC
when such writes are to MMRs which are sourced in the 32 kHz domain. Note that if
multiple write pending errors (i.e. rejected posted writes) occur,
RTC_SR0.WPNDERRINT sticks active at the first occurrence.
RTC_SR0.WPNDERRINT is cleared by writing one to it.
0 No posted write has been rejected by the RTC since
RTC_SR0.WPNDERRINT is last cleared by the CPU.
1 Write Rejected A posted write has been rejected by the
RTC due to a previously-posted write to the same
MMR which is still awaiting execution. Such a rejection
has occurred since the CPU last cleared
RTC_SR0.WPNDERRINT.

3 ISOINT(R/W1C)

RTC Power-Domain Isolation Interrupt Source.
Sticky interrupt source which indicates whether the RTC has had to activate its powerdomain isolation barrier due to a power loss in the core. When the core regains power,
the CPU can read ISOINT to inform itself of such a power event.
RTC_SR0.ISOINT is cleared by the CPU by writing one to it.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 The always-on RTC power domain has not activated its
isolation from the core since the RTC_SR0.ISOINT
interrupt source was last cleared by the CPU.
1 The always-on RTC power domain has activated andsubsequently de-activated its isolation from the core due
to a power event. This event occurred since
RTC_SR0.ISOINT was last cleared by the CPU.

21–90

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ADuCM4050 RTC Register Descriptions

Table 21-48: RTC_SR0 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 MOD60ALMINT(R/W1C)

Modulo-60 RTC Alarm Interrupt Source.
Sticky flag which is the source of an optionally-enabled interrupt to the CPU. This interrupt is activated once every 60 increments of the integer count in RTC_CNT1 and
RTC_CNT0, at a displacement of RTC_CR0.MOD60ALM increments past a modulo-60 boundary.
It is enabled and its target time is configured using the
RTC_CR0.MOD60ALMINTEN and RTC_CR0.MOD60ALM respectively. It is clearedby writing a value of one to its bit position.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 RTC_SR0.MOD60ALMINT interrupt event has notoccurred since this bit was last cleared by the CPU.
1 RTC_SR0.MOD60ALMINT interrupt event has occurred since this bit was last cleared by the CPU.

1 ALMINT(R/W1C)

Alarm Interrupt Source.
Sticky flag which is the source of an optionally-enabled interrupt to the CPU. It indicates that an alarm event has occurred due to a match between the RTC count andalarm register values. A match is defined as the value in RTC_CNT1, RTC_CNT0 and
RTC_CNT2 equating to the alarm time given by RTC_ALM1, RTC_ALM0 and
RTC_ALM2. The detection of such an event is enabled by RTC_CR0.ALMEN in
RTC_CR0, assuming that RTC_CR0.CNTEN is also enabled.
RTC_SR0.ALMINT is cleared by writing a value of one to it.
0 RTC_SR0.ALMINT interrupt event has not occurredsince this bit was last cleared by the CPU.
1 RTC_SR0.ALMINT interrupt event has occurred since
this bit was last cleared by the CPU.

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ADuCM4050 RTC Register Descriptions

RTC Status 1
Information on RTC operation is made available to the CPU via three status registers RTC_SR0, RTC_SR1 and
RTC_SR2. These registers include all flags related to CPU interrupt sources and error conditions within the RTC.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

WPNDTRM (R)Pending Status of Posted Writes to
RTC_TRMWPNDCR0 (R)Pending Status of Posted Writes to
RTC_CR0WPNDALM1 (R)Pending Status of Posted Writes to
RTC_ALM1WPNDSR0 (R)Pending Status of Posted Clearancesof Interrupt Sources in RTC_SR0

WPNDALM0 (R)Pending Status of Posted Writes to
RTC_ALM0WPNDCNT0 (R)Pending Status of Posted Writes to
RTC_CNT0WPNDCNT1 (R)Pending Status of Posted Writes to
RTC_CNT1

Figure 21-50: RTC_SR1 Register Diagram
Table 21-49: RTC_SR1 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
13 WPNDTRM(R/NW)

Pending Status of Posted Writes to RTC_TRM.
Indicates if a posted register write to RTC_TRM is currently pending (buffered and enqueued) and awaiting execution and therefore no further write to the same MMR canbe accepted at this time.
0 The RTC can accept a new posted write to the
RTC_TRM MMR.
1 A previously-posted write to RTC_TRM is still awaiting
execution, so no new posting to this MMR can be accepted.

12 WPNDALM1(R/NW)

Pending Status of Posted Writes to RTC_ALM1.
Indicates if a posted register write to RTC_ALM1 is currently pending (buffered andenqueued) and awaiting execution and therefore no further write to the same MMR
can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_ALM1 MMR.
1 A previously-posted write to RTC_ALM1 is still awaiting execution, so no new posting to this MMR can be
accepted.

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ADuCM4050 RTC Register Descriptions

Table 21-49: RTC_SR1 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
11 WPNDALM0(R/NW)

Pending Status of Posted Writes to RTC_ALM0.
Indicates if a posted register write to RTC_ALM0 is currently pending (buffered andenqueued) and awaiting execution and therefore no further write to the same MMR
can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_ALM0 MMR.
1 A previously-posted write to RTC_ALM0 is still awaiting execution, so no new posting to this MMR can be
accepted.

10 WPNDCNT1(R/NW)

Pending Status of Posted Writes to RTC_CNT1.
Indicates if a posted register write to RTC_CNT1 is currently pending (buffered andenqueued) and awaiting execution and therefore no further write to the same MMR
can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_CNT1 MMR.
1 A previously-posted write to RTC_CNT1 is still awaiting execution, so no new posting to this MMR can be
accepted.

9 WPNDCNT0(R/NW)

Pending Status of Posted Writes to RTC_CNT0.
Indicates if a posted register write to RTC_CNT0 is currently pending (buffered andenqueued) and awaiting execution and therefore no further write to the same MMR
can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_CNT0 MMR.
1 A previously-posted write to RTC_CNT0 is still awaiting execution, so no new posting to this MMR can be
accepted.

8 WPNDSR0(R/NW)

Pending Status of Posted Clearances of Interrupt Sources in RTC_SR0.
Indicates if posted clearances of interrupt sources in RTC_SR0 are currently pending(buffered and enqueued) and awaiting execution.
0 The RTC can accept new posted clearances of interrupt
sources in RTC_SR0 located in the 32 kHz domain.
1 A previously-posted clearance of interrupt sources in
RTC_SR0 maintained in the 32 kHz domain is still
awaiting execution. Additional clearances can still be aggregated into the existing, pending transaction.

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ADuCM4050 RTC Register Descriptions

Table 21-49: RTC_SR1 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
7 WPNDCR0(R/NW)

Pending Status of Posted Writes to RTC_CR0.
Indicates if a posted register write to RTC_CR0 is currently pending (buffered and enqueued) and awaiting execution and therefore no further write to the same MMR canbe accepted at this time.
0 The RTC can accept a new posted write to RTC_CR0.
1 A previously-posted write to RTC_CR0 is still awaiting
execution, so no new posting to this MMR can be accepted.

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ADuCM4050 RTC Register Descriptions

RTC Status 2
RTC_SR2 is a status register which further complements the status information provided by RTC_SR0 and
RTC_SR1. Note that RTC1 has full RTC_SR2 functionality, whereas RTC0 has reduced features.
All interrupt sources in RTC_SR2 are sticky, active high, level signals. Each source can be cleared by writing one toit.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

0

0

0

0

0

0

0

0

0

WSYNCALM2MIR (R)Synchronization Status of Posted Writes
to RTC_ALM2
WSYNCCR1MIR (R)Synchronization Status of Posted Writes
to RTC_CR1
WPNDALM2MIR (R)Pending Status of Posted Writes to
RTC_ALM2

1

0

0

0

0

0

CNTINT (R/W1C)
RTC Count Interrupt Source
PSINT (R/W1C)
RTC Prescaled, Modulo-1 Boundary
Interrupt Source
TRMINT (R/W1C)
RTC Trim Interrupt Source
CNTROLLINT (R/W1C)
RTC Count Roll-Over Interrupt Source

WPNDCR1MIR (R)Pending Status of Posted Writes to
RTC_CR1

CNTMOD60ROLLINT (R/W1C)
RTC Modulo-60 Count Roll-Over Interrupt
Source

TRMBDYMIR (R)Mirror of RTC_MOD.TRMBDYCNTROLL (R)RTC Count Roll-Over

CNTMOD60ROLL (R)RTC Count Modulo-60 Roll-Over

Figure 21-51: RTC_SR2 Register Diagram
Table 21-50: RTC_SR2 Register Fields
Bit No.

Bit Name

Description/Enumeration

15 WSYNCALM2MIR

Synchronization Status of Posted Writes to RTC_ALM2.

(Access)(R/NW)

Indicates if the effects of a posted write to RTC_ALM2 are visible to the CPU.
0 Results of a posted write are not yet visible.
1 Results of a posted write are visible.

14 WSYNCCR1MIR(R/NW)

Synchronization Status of Posted Writes to RTC_CR1.
Indicates if the effects of a posted write to RTC_CR1 are visible to the CPU.
0 Results of a posted write are not yet visible.
1 Results of a posted write are visible.

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ADuCM4050 RTC Register Descriptions

Table 21-50: RTC_SR2 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
13 WPNDALM2MIR(R/NW)

Pending Status of Posted Writes to RTC_ALM2.
Indicates if a posted register write to RTC_ALM2 is currently pending (i.e. bufferedand enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to RTC_ALM2.
1 A previously-posted write is still awaiting execution, so
no new posting to this MMR can be accepted.

12 WPNDCR1MIR(R/NW)

Pending Status of Posted Writes to RTC_CR1.
Indicates if a posted register write to RTC_CR1 is currently pending (i.e. buffered andenqueued) and awaiting execution and therefore no further write to the same MMR
can be accepted at this time.
0 The RTC can accept a new posted write to RTC_CR1.
1 A previously-posted write is still awaiting execution, so
no new posting to this MMR can be accepted.

7 TRMBDYMIR(R/NW)

6 CNTMOD60ROLL(R/NW)

Mirror of RTC_MOD.TRMBDY.
This bitfield is a read-only mirror of the value of RTC_MOD.TRMBDY MMR. It is
included here so that when RTC_SR2 is read, the influence will be indicated of any
trimming on a roll-over of the main RTC count or its modulo-60 equivalent.
RTC Count Modulo-60 Roll-Over.
RTC_SR2.CNTMOD60ROLL indicates whether the current modulo-60 value of the
RTC count given by RTC_MOD.CNTMOD60 MMR has come about due to a roll-overfrom/through its maximum possible value to/through its minimum possible value
when incremented at the most recent, prescaled time unit.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 The modulo-60 value of the RTC count in
RTC_MOD.CNTMOD60 has not arisen due to a rollover.
1 The modulo-60 value of the RTC count currently in
RTC_MOD.CNTMOD60 has rolled over from a value ator within trimming distance of its maximum to a value
at or within trimming distance of its minimum.

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ADuCM4050 RTC Register Descriptions

Table 21-50: RTC_SR2 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
5 CNTROLL(R/NW)

RTC Count Roll-Over.
RTC_SR2.CNTROLL indicates whether the current value of the RTC real-time countgiven by RTC_CNT1, RTC_CNT0 and RTC_CNT2 has come about due to a roll-overfrom/through its maximum possible value to/through its minimum possible value
when incremented at the most recent, prescaled time unit.
0 The current value of the RTC real-time count has notarisen due to a roll-over.
1 The current value of the RTC real-time count has rolled
over from a value at or within trimming distance of its
maximum to a value at or within trimming distance ofits minimum.

4 CNTMOD60ROLLINT(R/W1C)

RTC Modulo-60 Count Roll-Over Interrupt Source.
This source sticks active high when the modulo-60 equivalent of the integer count value in RTC_CNT1 and RTC_CNT0 rolls over from 59 to zero or is trimmed such thatthese values are spanned. Such a roll-over event happens every 60 prescaled incrementsof the RTC count, or fewer if positive (additive) trimming is active.
Note that for RTC_SR2.CNTMOD60ROLLINT to cause an interrupt from the RTC,
the corresponding enable bit for this interrupt fan-in term,
RTC_CR1.CNTMOD60ROLLINTEN must be active high.
This interrupt source is cleared by writing one to it.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 The modulo-60 value of RTC_CNT1 and RTC_CNT0
in RTC_MOD.CNTMOD60 has not rolled over since
RTC_SR2.CNTMOD60ROLLINT was last cleared.
1 The modulo-60 value of of RTC_CNT1 and
RTC_CNT0 in RTC_MOD.CNTMOD60 has rolled oversince RTC_SR2.CNTMOD60ROLLINT was lastcleared.

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ADuCM4050 RTC Register Descriptions

Table 21-50: RTC_SR2 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 CNTROLLINT(R/W1C)RTC Count Roll-Over Interrupt Source.
This source sticks active high when the integer count value in RTC_CNT1 and
RTC_CNT0 rolls over from (2^32-1) to zero or is trimmed such that the trim increment causes the RTC to pass through (potentially spanning) these maximum and minimum values.
Note that for RTC_SR2.CNTROLLINT to cause an interrupt from the RTC, thecorresponding enable bit for this interrupt fan-in term, RTC_CR1.CNTROLLINTEN
must be active high.
This interrupt source is cleared by writing one to it.
Note that in RTC0, the CPU can only obtain information about
RTC_SR2.CNTROLLINT by reading it. RTC_SR2.CNTROLLINT cannot be enabled as an interrupt fan-in term for RTC0 because of the absence of the
RTC_CR1.CNTROLLINTEN. In contrast, full interrupt capability is available for
RTC1.
0 The integer count in RTC_CNT1 and RTC_CNT0 has
not rolled over since RTC_SR2.CNTROLLINT waslast cleared.
1 The integer count in RTC_CNT1 and RTC_CNT0 has
rolled over since RTC_SR2.CNTROLLINT was lastcleared.

2 TRMINT(R/W1C)RTC Trim Interrupt Source.
This source sticks active high when a trim boundary occurs at the end of an enabledtrim interval and the integer value of RTC_CNT1 and RTC_CNT0 is adjusted according to the settings of RTC_TRM.
Note that for RTC_SR2.TRMINT to cause an interrupt from the RTC, the corresponding enable bit for this interrupt fan-in term, RTC_CR1.TRMINTEN, must be
active high.
This interrupt source is cleared by writing one to it.
Note that in RTC0, the CPU can only obtain information about
RTC_SR2.TRMINT by reading it. RTC_SR2.TRMINT cannot be enabled as an interrupt fan-in term for RTC0 because of the absence of the RTC_CR1.TRMINTEN
In contrast, full interrupt capability is available for RTC1.
0 An RTC trim interval boundary has not occurred since
RTC_SR2.TRMINT was last cleared.
1 An RTC trim interval boundary has occurred since
RTC_SR2.TRMINT was last cleared.

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ADuCM4050 RTC Register Descriptions

Table 21-50: RTC_SR2 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 PSINT(R/W1C)

RTC Prescaled, Modulo-1 Boundary Interrupt Source.
This source sticks active high whenever a prescaled RTC time unit elapses and the
RTC integer count is incremented or trimmed.
Note that for RTC_SR2.PSINT to cause an interrupt from the RTC, the corresponding enable bit for this interrupt fan-in term, RTC_CR1.PSINTEN, must be active high.
This interrupt source is cleared by writing one to its bit position in RTC_SR2.
Note that in RTC0, the CPU can only obtain information about RTC_SR2.PSINT
by reading it. RTC_SR2.PSINT cannot be enabled as an interrupt fan-in term for
RTC0 because of the absence of the RTC_CR1.PSINTEN In contrast, full interrupt
capability is available for RTC1.
0 Count not Incremented or Trimmed The RTC integer
count has not been incremented or trimmed since
RTC_SR2.PSINT was last cleared.
1 The RTC integer count has been incremented or trimmed since RTC_SR2.PSINT was last cleared.

0 CNTINT(R/W1C)RTC Count Interrupt Source.
This source sticks active high whenever the integer count value in RTC_CNT1 and
RTC_CNT0 changes. Note that such an event is not the same as the occurrence of aprescaled RTC time unit (RTC_SR2.PSINT), since the RTC count can either be redefined or trimmed which may or may not lead to value changes.
This interrupt source is cleared by writing one to it.
Note that in RTC0, the CPU can only obtain information about
RTC_SR2.CNTINT by reading it. RTC_SR2.CNTINT cannot be enabled as an interrupt fan-in term for RTC0 because of the absence of the RTC_CR1.CNTINTEN.
In contrast, full interrupt capability is available for RTC1.
0 The value of the RTC integer count has not changed
since RTC_SR2.CNTINT was last cleared.
1 The value of the RTC integer count has changed since
RTC_SR2.CNTINT was last cleared.

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ADuCM4050 RTC Register Descriptions

RTC Status 3
RTC_SR3 is a status register containing write-one-to-clear, interrupt sources which stick active high whenever
events occur for enabled input capture or SensorStrobe channels.
Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ALMINTMIR (R)Read-only Mirror of the RTC_SR0.ALMINT
Interrupt Source

IC0IRQ (R/W1C)
Sticky Interrupt Source for the RTC
Input Capture Channel 0

SS4IRQ (R/W1C)
Sticky Interrupt Source for the SensorStrobe
Channel 4

IC2IRQ (R/W1C)
Sticky Interrupt Source for the RTC
Input Capture Channel 2

SS3IRQ (R/W1C)
Sticky Interrupt Source for the SensorStrobe
Channel 3

IC3IRQ (R/W1C)
Sticky Interrupt Source for the RTC
Input Capture Channel 3

SS2IRQ (R/W1C)
Sticky Interrupt Source for the SensorStrobe
Channel 2

IC4IRQ (R/W1C)
Sticky Interrupt Source for the RTC
Input Capture Channel 4

SS1IRQ (R/W1C)
Sticky Interrupt Source for SensorStrobe
Channel 1

SS1FEIRQ (R/W1C)
Sticky Interrupt Source for the SensorStrobe
Channel 1 Falling Edge

SS4FEIRQ (R/W1C)
Sticky Interrupt Source for the SensorStrobe
Channel 4 Falling Edge

SS2FEIRQ (R/W1C)
Sticky Interrupt Source for the SensorStrobe
Channel 2 Falling Edge

SS3FEIRQ (R/W1C)
Sticky Interrupt Source for the SensorStrobe
Channel 3 Falling Edge

Figure 21-52: RTC_SR3 Register Diagram
Table 21-51: RTC_SR3 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
13 ALMINTMIR(R/NW)

Read-only Mirror of the RTC_SR0.ALMINT Interrupt Source.
Note that the 47-bit absolute-time alarm function in the RTC which causes
RTC_SR0.ALMINT to activate doubles up as the SensorStrobe channel 0.
0 An ALMINT interrupt event has not occurred since the
RTC_SR0.ALMINT interrupt source bit was lastcleared by the CPU.
1 An ALMINT interrupt event has occurred since the
RTC_SR0.ALMINT interrupt source bit was lastcleared by the CPU.

21–100

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-51: RTC_SR3 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
12 SS4IRQ(R/W1C)

Sticky Interrupt Source for the SensorStrobe Channel 4.
This interrupt source sticks high whenever a scheduled alarm event causing rising edge
for the enabled (via RTC_CR3SS.SS4EN) SensorStrobe channel 4.
RTC_SR3.SS4IRQ is cleared by writing a value of 1'b1 to its bit position. If enabled
via RTC_CR3SS.SS4IRQEN, the RTC_SR3.SS4IRQ source is included as a contributory term to the RTC interrupt lines sent to the CPU and the wake-up controller.
0 No enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the SensorStrobe
channel 4 since the CPU last cleared this bit.
1 An enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the SensorStrobe
channel 4 since the CPU last cleared this bit.

11 SS3IRQ(R/W1C)

Sticky Interrupt Source for the SensorStrobe Channel 3.
This interrupt source sticks high whenever a scheduled alarm event causing rising edge
for the enabled (via RTC_CR3SS.SS3EN) SensorStrobe channel 3.
RTC_SR3.SS3IRQ is cleared by writing a value of 1'b1 to its bit position. If enabled
via RTC_CR3SS.SS3IRQEN, the RTC_SR3.SS3IRQ source is included as a contributory term to the RTC interrupt lines sent to the CPU and the wake-up controller.
0 No enabled SensorStrobe event (rising edge in SensorStrobe output) has occurred on the SensorStrobe channel
3 since the CPU last cleared this bit.
1 An enabled SensorStrobe event (rising edge in SensorStrobe output) has occurred on the SensorStrobe channel
3 since the CPU last cleared this bit.

10 SS2IRQ(R/W1C)

Sticky Interrupt Source for the SensorStrobe Channel 2.
This interrupt source sticks high whenever a scheduled alarm event causing rising edge
for the enabled (via RTC_CR3SS.SS2EN) SensorStrobe channel 2.
RTC_SR3.SS2IRQ is cleared by writing a value of 1'b1 to its bit position. If enabled
via RTC_CR3SS.SS2IRQEN, the RTC_SR3.SS2IRQ source is included as a contributory term to the RTC interrupt lines sent to the CPU and the wake-up controller.
0 No enabled SensorStrobe event (rising edge in SensorStrobe output) has occurred on the SensorStrobe channel
2 since the CPU last cleared this bit.
1 An enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the SensorStrobe
channel 2 since the CPU last cleared this bit.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

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ADuCM4050 RTC Register Descriptions

Table 21-51: RTC_SR3 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9 SS1IRQ(R/W1C)

Sticky Interrupt Source for SensorStrobe Channel 1.
This interrupt source sticks high whenever a scheduled alarm event causing rising edge
for the enabled (via RTC_CR3SS.SS1EN) SensorStrobe channel 1.
RTC_SR3.SS1IRQ is cleared by writing one to it. If enabled via
RTC_CR3SS.SS1IRQEN, the RTC_SR3.SS1IRQ source is included as a contributory term to the RTC interrupt lines sent to the CPU and the wake-up controller.
0 No enabled SensorStrobe event (rising edge in SensorStrobe output) has occurred on the RTC_SS1 channel
since the CPU last cleared this bit.
1 An enabled SensorStrobe event (rising edge in SensorStrobe output) has occurred on the RTC_SS1 channel
since the CPU last cleared this bit.

8 SS4FEIRQ(R/W1C)

Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge.
This interrupt source sticks high whenever a scheduled alarm event causing fallingedge for the enabled (via RTC_CR3SS.SS4EN) SensorStrobe channel 4.
RTC_SR3.SS4IRQ is cleared by writing a value of 1'b1 to its bit position. If enabled
via RTC_CR3SS.SS4IRQEN, the RTC_SR3.SS4FEIRQsource is included as acontributory term to the RTC interrupt lines sent to the CPU and the wake-up controller.
0 No enabled SensorStrobe event (rising edge in SensorStrobe output) has occurred on the SensorStrobe channel
4 since the CPU last cleared this bit.
1 An enabled SensorStrobe event (rising edge in SensorStrobe output) has occurred on the SensorStrobe channel
4 since the CPU last cleared this bit.

7 SS3FEIRQ(R/W1C)

Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge.
This interrupt source sticks high whenever a scheduled alarm event causing fallingedge for the enabled (via RTC_CR3SS.SS3EN) SensorStrobe channel 3.
RTC_SR3.SS3IRQ is cleared by writing a value of 1'b1 to its bit position. If enabled
via RTC_CR3SS.SS3IRQEN, the RTC_SR3.SS3FEIRQsource is included as acontributory term to the RTC interrupt lines sent to the CPU and the wake-up controller.
0 No enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the SensorStrobe
channel 3 since the CPU last cleared this bit.
1 An enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the SensorStrobe
channel 3 since the CPU last cleared this bit.

21–102

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-51: RTC_SR3 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
6 SS2FEIRQ(R/W1C)

Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge.
This interrupt source sticks high whenever a scheduled alarm event causing fallingedge for the enabled (via RTC_CR3SS.SS2EN) SensorStrobe channel 2.
RTC_SR3.SS2IRQ is cleared by writing a value of 1'b1 to its bit position. If enabled
via RTC_CR3SS.SS2IRQEN, the RTC_SR3.SS2FEIRQsource is included as acontributory term to the RTC interrupt lines sent to the CPU and the wake-up controller.
0 No enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the SensorStrobe
channel 2 since the CPU last cleared this bit.
1 An enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the SensorStrobe
channel 2 since the CPU last cleared this bit.

5 SS1FEIRQ(R/W1C)

Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge.
This interrupt source sticks high whenever a scheduled alarm event causing fallingedge for the enabled (via RTC_CR3SS.SS1EN) SensorStrobe channel 1.
RTC_SR3.SS1IRQ is cleared by writing a value of 1'b1 to its bit position. If enabled
via RTC_CR3SS.SS1IRQEN, the RTC_SR3.SS1FEIRQ source is included as acontributory term to the RTC interrupt lines sent to the CPU and the wake-up controller.
0 No enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the RTC_SS1 channel since the CPU last cleared this bit.
1 An enabled SensorStrobe event (falling edge in SensorStrobe output) has occurred on the RTC_SS1 channel since the CPU last cleared this bit.

4 IC4IRQ(R/W1C)

Sticky Interrupt Source for the RTC Input Capture Channel 4.
This interrupt source in RTC_SR3 sticks high whenever an enabled (via
RTC_CR2IC.IC4EN) input requester to the RTC asks for a snapshot of the RTC
count to be taken for the RTC_IC4 input capture channel. It is cleared by writing avalue of 1'b1 to its bit position.
0 No enabled input capture event has occurred on the
RTC_IC4 channel since the CPU last cleared this bit.
1 An enabled input capture event has occurred on the
RTC_IC4 channel since the CPU last cleared this bit.

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ADuCM4050 RTC Register Descriptions

Table 21-51: RTC_SR3 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 IC3IRQ(R/W1C)

Sticky Interrupt Source for the RTC Input Capture Channel 3.
This interrupt source in RTC_IC3 sticks high whenever an enabled (via
RTC_CR2IC.IC3EN) input requester to the RTC asks for a snapshot of the RTC
count to be taken for the RTC_IC3 input capture channel. It is cleared by writing avalue of 1'b1 to its bit position.
0 No enabled input capture event has occurred on the
RTC_IC3 channel since the CPU last cleared this bit.
1 An enabled input capture event has occurred on the
RTC_IC3 channel since the CPU last cleared this bit.

2 IC2IRQ(R/W1C)

Sticky Interrupt Source for the RTC Input Capture Channel 2.
This interrupt source in RTC_SR3 sticks high whenever an enabled (via
RTC_CR2IC.IC2EN) input requester to the RTC asks for a snapshot of the RTC
count to be taken for the RTC_IC2 input capture channel. It is cleared by writing avalue of 1'b1 to its bit position.
0 No enabled input capture event has occurred on the
RTC_IC2 channel since the CPU last cleared this bit.
1 An enabled input capture event has occurred on the
RTC_IC2 channel since the CPU last cleared this bit.

0 IC0IRQ(R/W1C)

Sticky Interrupt Source for the RTC Input Capture Channel 0.
This interrupt source in RTC_SR3 sticks high whenever an enabled (via
RTC_CR2IC.IC0EN) input requester (non-CPU) to the RTC asks for a snapshot of
the RTC count to be taken for the IC0 input capture channel. It is cleared by writing avalue of 1'b1 to its bit position. Note that this field is unaffected by CPU-promptedsnapshots, requested by writing a specific key value of 0x7627 to the GWY register.
0 No enabled, non-CPU input capture event has occurredon the IC0 channel since the CPU last cleared this bit.
1 An enabled, non-CPU input capture event has occurredon the IC0 channel since the CPU last cleared this bit.

21–104

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Status 4
RTC_SR4 is a status register which provides the synchronization status of posted writes and posted reads to thoseregisters related to input capture and output control which are sourced in the 32 kHz always-on half of the RTC.
Note that RTC_SR4 only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

1

1

1

1

0

1

1

1

1

1

1

WSYNCSSMSKOT (R)Synchronization Status of Posted Reads
Writes to Mask for SensorStrobe Channels
on Time Control Register
RSYNCIC4 (R)Synchronization Status of Posted Reads
of RTC Input Channel 4
RSYNCIC3 (R)Synchronization Status of Posted Reads
of RTC Input Channel 3
RSYNCIC2 (R)Synchronization Status of Posted Reads
of RTC Input Channel 2
RSYNCIC0 (R)Synchronization Status of Posted Reads
of RTC Input Channel 0
WSYNCSS4 (R)Synchronization Status of Posted Writes
to SensorStrobe Channel 4
WSYNCSS3 (R)Synchronization Status of Posted Writes
to SensorStrobe Channel 3

1

1

0

1

1

WSYNCSR3 (R)Synchronisation Status of Posted Writes
to RTC_SR3
WSYNCCR2IC (R)Synchronization Status of Posted Writes
to RTC Control 2 for Configuring Input
Capture Channels Register
WSYNCCR3SS (R)Synchronization Status of Posted Writes
to RTC Control 3 for Configuring SensorStrobe
Channel Register
WSYNCCR4SS (R)Synchronization Status of Posted Writes
to RTC Control 4 for Configuring SensorStrobe
Channel Register
WSYNCSSMSK (R)Synchronization Status of Posted Writes
to Masks for SensorStrobe Channel
Register
WSYNCSS1 (R)Synchronization Status of Posted Writes
to SensorStrobe Channel 1
WSYNCSS2 (R)Synchronization Status of Posted Writes
to SensorStrobe Channel 2

Figure 21-53: RTC_SR4 Register Diagram

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–105ADuCM4050 RTC Register Descriptions

Table 21-52: RTC_SR4 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 WSYNCSSMSKOT(R/NW)

Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on
Time Control Register.
This field indicates if the effects of a posted write to RTC_SSMSKOT are visible to theCPU.
0 The results of a posted write to RTC_SSMSKOT are notyet visible to the CPU.
1 The results of a posted write to RTC_SSMSKOT are
now visible to the CPU.

14 RSYNCIC4(R/NW)

Synchronization Status of Posted Reads of RTC Input Channel 4.
This field indicates if the effects of a read of RTC_IC4 are visible to the CPU, namely
if RTC_SR6.IC4UNR has been updated to reflect the unread status of that inputcapture channel.
0 Results of a read of IC4 are not yet visible to the CPU.
1 Results of a read of IC4 are now visible to the CPU.

13 RSYNCIC3(R/NW)

Synchronization Status of Posted Reads of RTC Input Channel 3.
This field indicates if the effects of a read of RTC_IC3 are visible to the CPU, namely
if RTC_SR6.IC3UNR has been updated to reflect the unread status of that inputcapture channel.
0 Results of a read of IC3 are not yet visible to the CPU.
1 Results of a read of IC3 are now visible to the CPU.

12 RSYNCIC2(R/NW)

Synchronization Status of Posted Reads of RTC Input Channel 2.
This field indicates if the effects of a read of RTC_IC2 are visible to the CPU, namely
if RTC_SR6.IC2UNR has been updated to reflect the unread status of that inputcapture channel.
0 Results of a read of IC2 are not yet visible to the CPU.
1 Results of a read of IC2 are now visible to the CPU.

10 RSYNCIC0(R/NW)

Synchronization Status of Posted Reads of RTC Input Channel 0.
This field indicates if the effects of a read of all 47 bits of RTC_IC0 are visible to theCPU, namely whether RTC_SR6.IC0UNR has been updated to reflect the unread
status of that input capture channel.
0 Results of a read of IC0 are not yet visible to the CPU.
1 Results of a read of IC0 are now visible to the CPU.

21–106

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-52: RTC_SR4 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9 WSYNCSS4(R/NW)

Synchronization Status of Posted Writes to SensorStrobe Channel 4.
RTC_SR4.WSYNCSS4 indicates if the effects of a posted write to RTC_SS4 are visible to the CPU.
0 The results of a posted write to RTC_SS4 are not yet
visible to the CPU.
1 The results of a posted write to RTC_SS4 are now visible to the CPU.

8 WSYNCSS3(R/NW)

Synchronization Status of Posted Writes to SensorStrobe Channel 3.
This field indicates if the effects of a posted write to RTC_SS3 are visible to the CPU.
0 The results of a posted write to RTC_SS3 are not yet
visible to the CPU.
1 The results of a posted write to RTC_SS3 are now visible to the CPU.

7 WSYNCSS2(R/NW)

Synchronization Status of Posted Writes to SensorStrobe Channel 2.
This field indicates if the effects of a posted write to RTC_SS2 are visible to the CPU.
0 The results of a posted write to RTC_SS2 are not yet
visible to the CPU.
1 The results of a posted write to RTC_SS2 are now visible to the CPU.

6 WSYNCSS1(R/NW)

Synchronization Status of Posted Writes to SensorStrobe Channel 1.
This field indicates if the effects of a posted write to RTC_SS1 are visible to the CPU.
0 Results of a posted write to RTC_SS1 are not yet visible to the CPU.
1 Results of a posted write to RTC_SS1 are now visible
to the CPU.

4 WSYNCSSMSK(R/NW)

Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register.
This field indicates if the effects of a posted write to RTC_SSMSK are visible to theCPU.
0 Results of a posted write to RTC_SSMSK are not yet
visible to the CPU.
1 Results of a posted write to RTC_SSMSK are now visible to the CPU.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–107

ADuCM4050 RTC Register Descriptions

Table 21-52: RTC_SR4 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 WSYNCCR4SS(R/NW)

Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register.
This field indicates if the effects of a posted write to RTC_CR4SS are visible to theCPU.
0 Results of a posted write to RTC_CR4SS are not yet
visible to the CPU.
1 Results of a posted write to RTC_CR4SS are now visible to the CPU.

2 WSYNCCR3SS(R/NW)

Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register.
This field indicates if the effects of a posted write to RTC_CR3SS are visible to theCPU.
0 Results of a posted write to RTC_CR3SS are not yet
visible to the CPU.
1 Results of a posted write to RTC_CR3SS are now visible to the CPU.

1 WSYNCCR2IC(R/NW)

Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input
Capture Channels Register.
This field indicates if the effects of a posted write to RTC_CR2IC are visible to theCPU.
0 Results of a posted write to RTC_CR2IC are not yet
visible to the CPU.
1 Results of a posted write to RTC_CR2IC are now visible to the CPU.

0 WSYNCSR3(R/NW)

Synchronisation Status of Posted Writes to RTC_SR3.
This field indicates if the effects of a posted write to RTC_SR3 are visible to the CPU.
0 Results of a posted interrupt clearance to RTC_SR3 arenot yet visible to the CPU.
1 Results of a posted interrupt clearance to RTC_SR3 arevisible to the CPU.

21–108

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Status 5
RTC_SR5 is a status register which provides the pending (buffered and enqueued) status of posted writes to thoseregisters related to input capture and output control which are sourced in the 32 kHz always-on half of the RTC.
Note that RTC_SR5 only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

WPENDSSMSKOT (R)Pending Status of Posted Writes to
RTC Masks for SensorStrobe Channel
Register

WPENDSR3 (R)Pending Status of Posted Clearancesof Interrupt Sources in RTC Status 3
Register

RPENDIC4 (R)Pending Status of Posted Reads of
Input Capture Channel 4

WPENDCR2IC (R)Pending Status of Posted Writes to
RTC Control 2 for Configuring Input
Capture Channels Register

RPENDIC3 (R)Pending Status of Posted Reads of
Input Capture Channel 3
RPENDIC2 (R)Pending Status of Posted Reads of
Input Capture Channel 2
RPENDIC0 (R)Pending Status of Posted Reads of
Input Capture Channel 0

WPENDCR3SS (R)Pending Status of Posted Writes to
RTC Control 3 for Configuring SensorStrobe
Channel Register
WPENDCR4SS (R)Pending Status of Posted Writes to
RTC Control 4 for Configuring SensorStrobe
Channel Register

WPENDSS4 (R)Pending Status of Posted Writes to
SensorStrobe Channel 4

WPENDSSMSK (R)Pending Status of Posted Writes to
RTC Masks for SensorStrobe Channel
Register

WPENDSS3 (R)Pending Status of Posted Writes to
SensorStrobe Channel 3

WPENDSS1 (R)Pending Status of Posted Writes to
SensorStrobe Channel 1
WPENDSS2 (R)Pending Status of Posted Writes to
SensorStrobe Channel 2

Figure 21-54: RTC_SR5 Register Diagram

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–109ADuCM4050 RTC Register Descriptions

Table 21-53: RTC_SR5 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 WPENDSSMSKOT(R/NW)

Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register.
RTC_SR5.WPENDSSMSKOT indicates if a posted register write to RTC_SSMSKOT
is currently pending (i.e. buffered and enqueued) and awaiting execution and therefore
no further write to the same MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_SSMSKOT.
1 A previously-posted write to RTC_SSMSKOT is still
awaiting execution, so no new posting to this MMR canbe accepted.

14 RPENDIC4(R/NW)

Pending Status of Posted Reads of Input Capture Channel 4.
This field indicates if posted reads of RTC_IC4 are currently pending (buffered andenqueued) and still awaiting execution, in order to update the value of
RTC_SR6.IC4UNR, sourced in the 32 kHz domain.
0 The RTC can accept new reads of RTC_IC4 and post
this change in the unread status (to read) to the 32 kHzsourced RTC_SR6.IC4UNR bit field.
1 A previously-posted change (to read) in the unread status of RTC_IC4, maintained at RTC_SR6.IC4UNR
in the 32kHz domain, is still awaiting execution.

13 RPENDIC3(R/NW)

Pending Status of Posted Reads of Input Capture Channel 3.
This field indicates if posted reads of RTC_IC3 are currently pending (buffered andenqueued) and still awaiting execution, in order to update the value of
RTC_SR6.IC3UNR, sourced in the 32 kHz domain.
0 The RTC can accept new reads of RTC_IC3 and post
this change in the unread status (to read) to the 32kHzsourced RTC_SR6.IC3UNR bit field.
1 A previously-posted change (to read) in the unread status of RTC_IC3, maintained at RTC_SR6.IC3UNR
in the 32kHz domain, is still awaiting execution.

21–110

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-53: RTC_SR5 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
12 RPENDIC2(R/NW)

Pending Status of Posted Reads of Input Capture Channel 2.
This field indicates if posted reads of RTC_IC2 are currently pending (buffered andenqueued) and still awaiting execution, in order to update the value of
RTC_SR6.IC2UNR, sourced in the 32kHz domain.
0 The RTC can accept new reads of RTC_IC2 and post
this change in the unread status (to read) to the 32 kHzsourced RTC_SR6.IC2UNR bit field.
1 A previously-posted change (to read) in the unread status of RTC_IC2, maintained at RTC_SR6.IC2UNR
in the 32 kHz domain, is still awaiting execution.

10 RPENDIC0(R/NW)

Pending Status of Posted Reads of Input Capture Channel 0.
This field indicates if posted reads of Input Capture channel 0 are currently pending(buffered and enqueued) and still awaiting execution, in order to update the value of
RTC_SR6.IC0UNR, sourced in the 32 kHz domain.
0 The RTC can accept new reads of IC0 and post thischange in the unread status (to read) to the 32 kHzsourced RTC_SR6.IC0UNR bit field.
1 A previously-posted change (to read) in the unread status of IC0, maintained at RTC_SR6.IC0UNR in the
32 kHz domain, is still awaiting execution.

9 WPENDSS4(R/NW)

Pending Status of Posted Writes to SensorStrobe Channel 4.
This field indicates if a posted register write to RTC_SS4 is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to RTC_SS4
1 A previously-posted write to RTC_SS4 is still awaiting
execution, so no new posting to this MMR can be accepted.

8 WPENDSS3(R/NW)

Pending Status of Posted Writes to SensorStrobe Channel 3.
This field indicates if a posted register write to RTC_SS3 is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to RTC_SS3.
1 A previously-posted write to RTC_SS3 is still awaiting
execution, so no new posting to this MMR can be accepted.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–111

ADuCM4050 RTC Register Descriptions

Table 21-53: RTC_SR5 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
7 WPENDSS2(R/NW)

Pending Status of Posted Writes to SensorStrobe Channel 2.
This field indicates if a posted register write to RTC_SS2 is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to RTC_SS2.
1 A previously-posted write to RTC_SS2 is still awaiting
execution, so no new posting to this MMR can be accepted.

6 WPENDSS1(R/NW)

Pending Status of Posted Writes to SensorStrobe Channel 1.
This field indicates if a posted register write to RTC_SS1 is currently pending (buffered and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to RTC_SS1.
1 A previously-posted write to RTC_SS1 is still awaiting
execution, so no new posting to this MMR can be accepted.

4 WPENDSSMSK(R/NW)

Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register.
This field indicates if a posted register write to RTC_SSMSK is currently pending(buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_SSMSK.
1 A previously-posted write to RTC_SSMSK is still awaiting execution, so no new posting to this MMR can be
accepted.

3 WPENDCR4SS(R/NW)

Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe
Channel Register.
This field indicates if a posted register write to RTC_CR4SS is currently pending(buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR4SS.
1 Write to RTC_CR4SS Pending A previously-posted
write to RTC_CR4SS is still awaiting execution, so no
new posting to this MMR can be accepted.

21–112

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-53: RTC_SR5 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 WPENDCR3SS(R/NW)

Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe
Channel Register.
This field indicates if a posted register write to RTC_CR3SS is currently pending(buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR3SS.
1 A previously-posted write to RTC_CR3SS is still awaiting execution, so no new posting to this MMR can be
accepted.

1 WPENDCR2IC(R/NW)

Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture
Channels Register.
This field indicates if a posted register write to RTC_CR2IC is currently pending(buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR2IC.
1 A previously-posted write to RTC_CR2IC is still awaiting execution, so no new posting to this MMR can be
accepted.

0 WPENDSR3(R/NW)

Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register.
This field indicates if posted clearances of interrupt sources in RTC_SR3 are currently
pending (buffered and enqueued) and awaiting execution.
0 The RTC can accept new posted clearances of interrupt
sources in RTC_SR3 located in the 32kHz domain.
1 A previously-posted clearance of interrupt sources in
RTC_SR3 maintained in the 32kHz domain is still
awaiting execution. Additional clearances can still be aggregated into the existing, pending transaction.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–113

ADuCM4050 RTC Register Descriptions

RTC Status 6
SR6 is a status register which provides the unread status of snapshots of input-capture channels, IC0, IC2, IC3 andIC4. Note that RTC_SR6 only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

FRZCNTPTR (R)Pointer for the Triple-Read Sequenceof RTC_FRZCNTIC0UNR (R)Sticky Unread Status of the Input Capture
Channel 0

IC0SNAP (R)Confirmation That RTC Snapshot 0,
1, 2 Registers Reflect the Value of
Input-Capture Channel RTC Input Capture
Channel 0

IC2UNR (R)Sticky Unread Status of the Input Capture
Channel 2

IC4UNR (R)Sticky Unread Status of the Input Capture
Channel 4

IC3UNR (R)Sticky Unread Status of the Input Capture
Channel 3

Figure 21-55: RTC_SR6 Register Diagram
Table 21-54: RTC_SR6 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
10:9 FRZCNTPTR(R/NW)

Pointer for the Triple-Read Sequence of RTC_FRZCNT.
This field indicates the sequence number for the next read in triple-read sequences of
the RTC_FRZCNT register.
Note that this field can be zeroed by writing a software key of value 0x9376 to
RTC_GWY.
0 The next read of RTC_FRZCNT will cause both of thefollowing to happen: (i) The read data of
RTC_FRZCNT will be the current value of RTC_CNT0
and(ii) A coherent snapshot of the current value of
RTC_CNT2 and RTC_CNT1 will be taken for return
during the subsequent two reads of RTC_FRZCNT.
1 The next read of RTC_FRZCNT will be the second in a
triple-read sequence and will return the snapshot of
RTC_CNT1 which was taken when the first read of
RTC_FRZCNT in the sequence occurred.
2 The next read of RTC_FRZCNT will be the third in a
triple-read sequence and will return the snapshot of
RTC_CNT2 which was taken when the first read of
RTC_FRZCNT in the sequence occurred.

21–114

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-54: RTC_SR6 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
8 IC0SNAP(R/NW)

Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture
Channel RTC Input Capture Channel 0.
This flag indicates if RTC_SNAP0, RTC_SNAP1, and RTC_SNAP2 registers reflect
the value of the 47-bit IC0 channel or the value of a software-initiated snapshot of the
RTC count.
0 Software Initiated Snapshot The value which can beread in RTC_SNAP0, RTC_SNAP1 and RTC_SNAP2
is due to a software-initiated snapshot.
1 Snapshot Initiated by IC0 Input Capture Event. The
value which can be read in RTC_SNAP0,
RTC_SNAP1, and RTC_SNAP2 is due to an IC0 input-capture event.

4 IC4UNR(R/NW)

Sticky Unread Status of the Input Capture Channel 4.
This field is a sticky, 32 kHz sourced flag which indicates if a new, unread snapshot
exists for input capture channel IC4.
0 No new, unread snapshot is contained in RTC_IC4 forthat input-capture channel.
1 An unread snapshot is contained in RTC_IC4 for that
input-capture channel.

3 IC3UNR(R/NW)

Sticky Unread Status of the Input Capture Channel 3.
This field is a sticky, 32 kHz sourced flag which indicates if a new, unread snapshot
exists for input capture channel IC3.
0 No new, unread snapshot is contained in RTC_IC3 forthat input-capture channel.
1 An unread snapshot is contained in RTC_IC3 for that
input-capture channel.

2 IC2UNR(R/NW)

Sticky Unread Status of the Input Capture Channel 2.
This field is a sticky, 32 kHz sourced flag which indicates if a new, unread snapshot
exists for input capture channel IC2.
0 No new, unread snapshot is contained in RTC_IC2 forthat input-capture channel.
1 An unread snapshot is contained in RTC_IC2 for that
input-capture channel.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–115ADuCM4050 RTC Register Descriptions

Table 21-54: RTC_SR6 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 IC0UNR(R/NW)

Sticky Unread Status of the Input Capture Channel 0.
This field is a sticky, 32 kHz sourced flag which indicates if a new, unread snapshot
exists for input capture channel IC0.
0 No new, unread snapshot is contained in IC0 for that
input-capture channel.
1 An unread snapshot is contained in IC0 for that inputcapture channel.

21–116

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Status 7
It is a status register which provides the sampled GPIO data for every SensorStrobe channel. And the status of pattern match in these values. Note that RTC_SR7 only exists in RTC1. In RTC0, the register address is reserved andreads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS4OUT (R)Output Value for SensorStrobe Channel 4

SS1SMP (R)
Latest GPIO Sample for SensorStrobe
Channel 1

SS3OUT (R)Output Value for SensorStrobe Channel 3

SS1SMPMTCHIRQ (R/W)
Sticky Status of GPIO Sample Pattern
Match for SensorStrobe Channel 1

SS2OUT (R)Output Value for SensorStrobe Channel 2
SS1OUT (R)Output Value for SensorStrobe Channel 1

SS2SMP (R)
Latest GPIO Sample for SensorStrobe
Channel 2

SS3SMPMTCHIRQ (R/W)
Sticky Status of GPIO Sample Pattern
Match for SensorStrobe Channel 3

SS2SMPMTCHIRQ (R/W)
Sticky Status of GPIO Sample Pattern
Match for SensorStrobe Channel 2
SS3SMP (R)
Latest GPIO Sample for SensorStrobe
Channel 3

Figure 21-56: RTC_SR7 Register Diagram
Table 21-55: RTC_SR7 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 SS4OUT(R/NW)
14 SS3OUT(R/NW)
13 SS2OUT(R/NW)
12 SS1OUT(R/NW)
11 SS3SMPMTCHIRQ(R/W)

Output Value for SensorStrobe Channel 4.
Output state of SensorStrobe channel 4.
Output Value for SensorStrobe Channel 3.
Output state of SensorStrobe channel 3.
Output Value for SensorStrobe Channel 2.
Output state of SensorStrobe channel 2.
Output Value for SensorStrobe Channel 1.
Output state of SensorStrobe channel 1.
Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3.
Sticky status of pattern match for SensorStrobe Channel 3. When a new sample
matches the expected pattern based on
RTC_CR7SSS.SS3SMPPTRN ,RTC_CR7SSS.SS3SMPEXP and previous
RTC_SR7.SS3SMP. Write 1 to clear this status bit.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–117

ADuCM4050 RTC Register Descriptions

Table 21-55: RTC_SR7 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10:8 SS3SMP(R/NW)
7 SS2SMPMTCHIRQ(R/W)

6:4 SS2SMP(R/NW)
3 SS1SMPMTCHIRQ(R/W)

2:0 SS1SMP(R/NW)

21–118

Latest GPIO Sample for SensorStrobe Channel 3.
This field provides the latest sample of GPIO data for SensorStrobe Channel 3. Gets
over-written when new sample is available.
Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2.
Sticky status of pattern match for SensorStrobe Channel 2. When a new sample
matches the expected pattern based on
RTC_CR7SSS.SS2SMPPTRN ,RTC_CR7SSS.SS2SMPEXP and previous
RTC_SR7.SS2SMP. Write 1 to clear this status bit.
Latest GPIO Sample for SensorStrobe Channel 2.
This field provides the latest sample of GPIO data for SensorStrobe Channel 2. Gets
over-written when new sample is available.
Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1.
Sticky status of pattern match for SensorStrobe Channel 1. When a new sample
matches the expected pattern based on
RTC_CR7SSS.SS1SMPPTRN ,RTC_CR7SSS.SS1SMPEXP and previous
RTC_SR7.SS1SMP. Write 1 to clear this status bit.
Latest GPIO Sample for SensorStrobe Channel 1.
This field provides the latest sample of GPIO data for SensorStrobe channel 1. Gets
over-written when new sample is available.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

RTC Status 8
It is a status register which provides the synchronization status of posted writes and posted reads to those registers
related to input capture and output control which are sourced in the 32 kHz always-on half of the RTC.
A WSYNC value of zero for a given register means the results of a previously-posted write to that register are not yet
visible to the CPU. A WSYNC value of one for a register means no posted write to that register has yet to complete
execution.
An RSYNC value of zero for a given register means the results of a previously-posted read of that register are not yet
visible to the CPU. An RSYNC value of one for a register means no posted read of that register has yet to complete
execution.
Note that RTC_SR8 only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

0

1

1

1

0

1

1

1

0

1

WSYNCGPMUX1 (R)Synchronisation Status of Posted Writes
to GPIO Pin Mux Control Register 1
WSYNCGPMUX0 (R)Synchronisation Status of Posted Writes
to GPIO Pin Mux Control Register 0
WSYNCSR7 (R)Synchronisation Status of Posted Writes
to Status 7 Register
WSYNCCR7SSS (R)Synchronisation Status of Posted Writes
to Control 7 for Configuring SensorStrobe
Channel Register
WSYNCCR6SSS (R)Synchronisation Status of Posted Writes
to Control 6 for Configuring SensorStrobe
Channel Register
WSYNCCR5SSS (R)Synchronisation Status of Posted Writes
to Control 5 for Configuring SensorStrobe
Channel Register

1

1

1

1

WSYNCSS1LOWDUR (R)Synchronisation Status of Posted Writes
to SensorStrobe Channel 1 Low Duration
Register
WSYNCSS2LOWDUR (R)Synchronisation Status of Posted Writes
to SensorStrobe Channel 2 Low Duration
Register
WSYNCSS3LOWDUR (R)Synchronisation Status of Posted Writes
to SensorStrobe Channel 3 Low Duration
Register
WSYNCSS1HIGHDUR (R)Synchronisation Status of Posted Writes
to SensorStrobe Channel 1 High Duration
Register
WSYNCSS2HIGHDUR (R)Synchronisation Status of Posted Writes
to SensorStrobe Channel 2 High Duration
Register
WSYNCSS3HIGHDUR (R)Synchronisation Status of Posted Writes
to SensorStrobe Channel 3 High Duration
RegisterFigure 21-57: RTC_SR8 Register Diagram

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–119ADuCM4050 RTC Register Descriptions

Table 21-56: RTC_SR8 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
13 WSYNCGPMUX1(R/NW)

Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1.
It indicates if the effects of a posted write to RTC_GPMUX1 are visible to the CPU.
If RTC_SR8.WSYNCGPMUX1 is low, a posted write to RTC_GPMUX1 is currently
queued up or in the process of being executed, but the results of this transaction are
not yet visible to the CPU. When RTC_SR8.WSYNCGPMUX1 goes high and thereby
activates the WSYNCINT sticky interrupt source, the effects of a write to
RTC_GPMUX1 are then available to the processor.
0 The results of a posted write to RTC_GPMUX1 are notyet visible to the CPU.
1 The results of a posted write to RTC_GPMUX1 are now
visible to the CPU.

12 WSYNCGPMUX0(R/NW)

Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0.
It indicates if the effects of a posted write to RTC_GPMUX0 are visible to the CPU.
If RTC_SR8.WSYNCGPMUX0 is low, a posted write to RTC_GPMUX0 is currently
queued up or in the process of being executed, but the results of this transaction are
not yet visible to the CPU. When RTC_SR8.WSYNCGPMUX0 goes high and thereby
activates the WSYNCINT sticky interrupt source, the effects of a write to
RTC_GPMUX0 are then available to the processor.
0 The results of a posted write to RTC_GPMUX0 are notyet visible to the CPU.
1 The results of a posted write to RTC_GPMUX0 are now
visible to the CPU.

11 WSYNCSR7(R/NW)

Synchronisation Status of Posted Writes to Status 7 Register.
It indicates if the effects of a posted write to RTC_SR7 are visible to the CPU.
If RTC_SR8.WSYNCSR7 is low, a posted write to RTC_SR7 is currently queued up
or in the process of being executed, but the results of this transaction are not yet visible
to the CPU. When RTC_SR8.WSYNCSR7 goes high and thereby activates the
WSYNCINT sticky interrupt source, the effects of a write to RTC_CR7SSS are thenavailable to the processor.
0 The results of a posted write to RTC_SR7 are not yet
visible to the CPU.
1 The results of a posted write to RTC_SR7 are now visible to the CPU.

21–120

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-56: RTC_SR8 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
10 WSYNCCR7SSS(R/NW)

Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe
Channel Register.
It indicates if the effects of a posted write to RTC_CR7SSS are visible to the CPU.
If RTC_SR8.WSYNCCR7SSS is low, a posted write to RTC_CR7SSS is currently
queued up or in the process of being executed, but the results of this transaction are
not yet visible to the CPU. When RTC_SR8.WSYNCCR7SSS goes high and thereby
activates the WSYNCINT sticky interrupt source, the effects of a write to
RTC_CR7SSS are then available to the processor.
0 The results of a posted write to RTC_CR7SSS are notyet visible to the CPU.
1 The results of a posted write to RTC_CR7SSS are now
visible to the CPU.

9 WSYNCCR6SSS(R/NW)

Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe
Channel Register.
It indicates if the effects of a posted write to RTC_CR6SSS are visible to the CPU.
If RTC_SR8.WSYNCCR6SSS is low, a posted write to RTC_CR6SSS is currently
queued up or in the process of being executed, but the results of this transaction are
not yet visible to the CPU. When RTC_SR8.WSYNCCR6SSS goes high and thereby
activates the WSYNCINT sticky interrupt source, the effects of a write to
RTC_CR6SSS are then available to the processor.
0 The results of a posted write to RTC_CR6SSS are notyet visible to the CPU.
1 The results of a posted write to RTC_CR6SSS are now
visible to the CPU.

8 WSYNCCR5SSS(R/NW)

Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe
Channel Register.
It indicates if the effects of a posted write to RTC_CR5SSS are visible to the CPU.
If RTC_SR8.WSYNCCR5SSS is low, a posted write to RTC_CR5SSS is currently
queued up or in the process of being executed, but the results of this transaction are
not yet visible to the CPU. When RTC_SR8.WSYNCCR5SSS goes high and thereby
activates the WSYNCINT sticky interrupt source, the effects of a write to
RTC_CR5SSS are then available to the processor.
0 The results of a posted write to RTC_CR5SSS are notyet visible to the CPU.
1 The results of a posted write to RTC_CR5SSS are now
visible to the CPU.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–121

ADuCM4050 RTC Register Descriptions

Table 21-56: RTC_SR8 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
6 WSYNCSS3HIGHDUR(R/NW)

Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration
Register.
It indicates if the effects of a posted write to RTC_SS3HIGHDUR are visible to theCPU.
If RTC_SR8.WSYNCSS3HIGHDUR is low, a posted write to RTC_SS3HIGHDUR iscurrently queued up or in the process of being executed, but the results of this transaction are not yet visible to the CPU. When RTC_SR8.WSYNCSS3HIGHDUR goeshigh and thereby activates the WSYNCINT sticky interrupt source, the effects of awrite to RTC_SS3HIGHDUR are then available to the processor.
0 The results of a posted write to RTC_SS3HIGHDUR
are not yet visible to the CPU.
1 The results of a posted write to RTC_SS3HIGHDUR
are now visible to the CPU.

5 WSYNCSS2HIGHDUR(R/NW)

Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration
Register.
It indicates if the effects of a posted write to RTC_SS2HIGHDUR are visible to theCPU.
If RTC_SR8.WSYNCSS2HIGHDUR is low, a posted write to RTC_SS2HIGHDUR iscurrently queued up or in the process of being executed, but the results of this transaction are not yet visible to the CPU. When RTC_SR8.WSYNCSS2HIGHDUR goeshigh and thereby activates the WSYNCINT sticky interrupt source, the effects of awrite to RTC_SS2HIGHDUR are then available to the processor.
0 The results of a posted write to RTC_SS2HIGHDUR
are not yet visible to the CPU.
1 The results of a posted write to RTC_SS2HIGHDUR
are now visible to the CPU.

4 WSYNCSS1HIGHDUR(R/NW)

Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration
Register.
It indicates if the effects of a posted write to RTC_SS1HIGHDUR are visible to theCPU.
If RTC_SR8.WSYNCSS1HIGHDUR is low, a posted write to RTC_SS1HIGHDUR iscurrently queued up or in the process of being executed, but the results of this transaction are not yet visible to the CPU. When RTC_SR8.WSYNCSS1HIGHDUR goeshigh and thereby activates the WSYNCINT sticky interrupt source, the effects of awrite to RTC_SS1HIGHDUR are then available to the processor.
0 The results of a posted write to RTC_SS1HIGHDUR
are not yet visible to the CPU.
1 The results of a posted write to RTC_SS1HIGHDUR
are now visible to the CPU.

21–122

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-56: RTC_SR8 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 WSYNCSS3LOWDUR(R/NW)

Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration
Register.
It indicates if the effects of a posted write to RTC_SS3LOWDUR are visible to theCPU.
If RTC_SR8.WSYNCSS3LOWDUR is low, a posted write to RTC_SS3LOWDUR iscurrently queued up or in the process of being executed, but the results of this transaction are not yet visible to the CPU. When RTC_SR8.WSYNCSS3LOWDUR goes highand thereby activates the WSYNCINT sticky interrupt source, the effects of a write to
RTC_SS3LOWDUR are then available to the processor.
0 The results of a posted write to RTC_SS3LOWDUR are
not yet visible to the CPU.
1 The results of a posted write to RTC_SS3LOWDUR are
now visible to the CPU.

1 WSYNCSS2LOWDUR(R/NW)

Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration
Register.
It indicates if the effects of a posted write to RTC_SS2LOWDUR are visible to theCPU.
If RTC_SR8.WSYNCSS2LOWDUR is low, a posted write to RTC_SS2LOWDUR iscurrently queued up or in the process of being executed, but the results of this transaction are not yet visible to the CPU. When RTC_SR8.WSYNCSS2LOWDUR goes highand thereby activates the WSYNCINT sticky interrupt source, the effects of a write to
RTC_SS2LOWDUR are then available to the processor.
0 The results of a posted write to RTC_SS2LOWDUR are
not yet visible to the CPU.
1 The results of a posted write to RTC_SS2LOWDUR are
now visible to the CPU.

0 WSYNCSS1LOWDUR(R/NW)

Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration
Register.
It indicates if the effects of a posted write to RTC_SS1LOWDUR are visible to theCPU.
If RTC_SR8.WSYNCSS1LOWDUR is low, a posted write to RTC_SS1LOWDUR iscurrently queued up or in the process of being executed, but the results of this transaction are not yet visible to the CPU. When RTC_SR8.WSYNCSS1LOWDUR goes highand thereby activates the WSYNCINT sticky interrupt source, the effects of a write to
RTC_SS1LOWDUR are then available to the processor.
0 The results of a posted write to RTC_SS1LOWDUR are
not yet visible to the CPU.
1 The results of a posted write to RTC_SS1LOWDUR are
now visible to the CPU.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–123

ADuCM4050 RTC Register Descriptions

RTC Status 9
It is a status register which provides the pending (i.e. buffered and enqueued) status of posted writes to those registers related to input capture and output control which are sourced in the 32 kHz always-on half of the RTC. A
WPEND value of one for a given register means a previously-posted write to that register is currently queued up in a
one-deep buffer and has yet to begin execution. When WPEND is therefore one, no further write to the register inquestion can be accommodated by the RTC until the existing write begins execution and vacates the buffer. When
WPEND is zero for a register, there is room in the RTC to accept a new posted write to that register. Note that
RTC_SR9 only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

WPENDGPMUX1 (R)Pending Status of Posted Writes to
RTC_GPMUX1WPENDGPMUX0 (R)Pending Status of Posted Writes to
RTC_GPMUX0WPENDSR7 (R)Pending Status of Posted Writes to
RTC_SR7
WPENDCR7SSS (R)Pending Status of Posted Writes toControl 7 for Configuring SensorStrobe
Channel Register
WPENDCR6SSS (R)Pending Status of Posted Writes toControl 6 for Configuring SensorStrobe
Channel Register
WPENDCR5SSS (R)Pending Status of Posted Writes toControl 5 for Configuring SensorStrobe
Channel Register

0

0

0

0

WPENDSS1LOWDUR (R)Pending Status of Posted Writes to
SensortStrobe Channel 1 Low Duration
Register
WPENDSS2LOWDUR (R)Pending Status of Posted Writes to
SensortStrobe Channel 2 Low Duration
Register
WPENDSS3LOWDUR (R)Pending Status of Posted Writes to
SensortStrobe Channel 3 Low Duration
Register
WPENDSS1HIGHDUR (R)Pending Status of Posted Writes to
SensortStrobe Channel 1 High Duration
Register
WPENDSS2HIGHDUR (R)Pending Status of Posted Writes to
SensortStrobe Channel 2 High Duration
Register
WPENDSS3HIGHDUR (R)Pending Status of Posted Writes to
SensortStrobe Channel 3 High Duration
RegisterFigure 21-58: RTC_SR9 Register Diagram

21–124

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-57: RTC_SR9 Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
13 WPENDGPMUX1(R/NW)

Pending Status of Posted Writes to RTC_GPMUX1.
It indicates if a posted register write to RTC_GPMUX1 is currently pending (i.e. buffered and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_GPMUX1.
1 A previously-posted write to RTC_GPMUX1 is still
awaiting execution, so no new posting to this MMR canbe accepted.

12 WPENDGPMUX0(R/NW)

Pending Status of Posted Writes to RTC_GPMUX0.
It indicates if a posted register write to RTC_GPMUX0 is currently pending (i.e. buffered and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_GPMUX0.
1 A previously-posted write to RTC_GPMUX0 is still
awaiting execution, so no new posting to this MMR canbe accepted.

11 WPENDSR7(R/NW)

Pending Status of Posted Writes to RTC_SR7.
It indicates if a posted register write to RTC_SR7 is currently pending (i.e. bufferedand enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to RTC_SR7.
1 A previously-posted write to RTC_SR7 is still awaiting
execution, so no new posting to this MMR can be accepted.

10 WPENDCR7SSS(R/NW)

Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel
Register.
It indicates if a posted register write to RTC_CR7SSS is currently pending (i.e. buffered and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR7SSS.
1 A previously-posted write to RTC_CR7SSS is still
awaiting execution, so no new posting to this MMR canbe accepted.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

21–125ADuCM4050 RTC Register Descriptions

Table 21-57: RTC_SR9 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
9 WPENDCR6SSS(R/NW)

Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel
Register.
It indicates if a posted register write to RTC_CR6SSS is currently pending (i.e. buffered and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR6SSS.
1 A previously-posted write to RTC_CR6SSS is still
awaiting execution, so no new posting to this MMR canbe accepted.

8 WPENDCR5SSS(R/NW)

Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel
Register.
It indicates if a posted register write to RTC_CR5SSS is currently pending (i.e. buffered and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR5SSS.
1 A previously-posted write to RTC_CR5SSS is still
awaiting execution, so no new posting to this MMR canbe accepted.

6 WPENDSS3HIGHDUR(R/NW)

Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register.
It indicates if a posted register write to RTC_SS3HIGHDUR is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_SS3HIGHDUR.
1 A previously-posted write to RTC_SS3HIGHDUR isstill awaiting execution, so no new posting to this MMR
can be accepted.

5 WPENDSS2HIGHDUR(R/NW)

Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register.
It indicates if a posted register write to RTC_SS2HIGHDUR is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_SS2HIGHDUR.
1 A previously-posted write to RTC_SS2HIGHDUR isstill awaiting execution, so no new posting to this MMR
can be accepted.

21–126

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 RTC Register Descriptions

Table 21-57: RTC_SR9 Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
4 WPENDSS1HIGHDUR(R/NW)

Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register.
It indicates if a posted register write to RTC_SS1HIGHDUR is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_SS1HIGHDUR.
1 A previously-posted write to RTC_SS1HIGHDUR isstill awaiting execution, so no new posting to this MMR
can be accepted.

2 WPENDSS3LOWDUR(R/NW)

Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register.
It indicates if a posted register write to RTC_SS3LOWDUR is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_SS3LOWDUR.
1 A previously-posted write to RTC_SS3LOWDUR is still
awaiting execution, so no new posting to this MMR canbe accepted.

1 WPENDSS2LOWDUR(R/NW)

Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register.
It indicates if a posted register write to RTC_SS2LOWDUR is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_SS2LOWDUR.
1 A previously-posted write to RTC_SS2LOWDUR is still
awaiting execution, so no new posting to this MMR canbe accepted.

0 WPENDSS1LOWDUR(R/NW)

Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register.
It indicates if a posted register write to RTC_SS1LOWDUR is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to thesame MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_SS1LOWDUR.
1 A previously-posted write to RTC_SS1LOWDUR is still
awaiting execution, so no new posting to this MMR canbe accepted.

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ADuCM4050 RTC Register Descriptions

RTC Trim
RTC_TRM contains the trim value and interval for a periodic adjustment of the RTC count value to track time withthe required accuracy. Trimming is enabled and disabled via the RTC_CR0.TRMEN bit. For trimming to occur, theglobal enable for the RTC, RTC_CR0.CNTEN, must also be active.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

IVL2EXPMIN (R/W)
Minimum Power-of-two Interval of Prescaled
RTC Time Units Which RTC_TRM.IVL
Can SelectIVL (R/W)
Trim Interval in Prescaled RTC Time
Units

0

1

VALUE (R/W)
Trim Value in Prescaled RTC Time Units
to Be Added or Subtracted from the
RTC Count at the End of a Periodic
Interval Selected by RTC_TRM.IVL
ADD (R/W)
Trim Polarity

Figure 21-59: RTC_TRM Register Diagram
Table 21-58: RTC_TRM Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
9:6 IVL2EXPMIN(R/W)

Minimum Power-of-two Interval of Prescaled RTC Time Units Which
RTC_TRM.IVL Can Select.
RTC_TRM.IVL2EXPMIN configures the range of trim intervals which are available
to the RTC at any one time. The range is 2 to the power of(RTC_TRM.IVL2EXPMIN + 0, 1, 2 or 3), selectable by RTC_TRM.IVL.
The minimum supported value of RTC_TRM.IVL2EXPMIN is 2. The maximum
supported value (and default) is 14. If a user configures the RTC with a value outside
the range [2,14], the default value of 14 will be used.

5:4 IVL(R/W)

Trim Interval in Prescaled RTC Time Units.
RTC_TRM.IVL specifies the interval at the end of which a periodic adjustment of
RTC_TRM.VALUE prescaled RTC time units is made to the RTC count.
0 Trim interval is 2^RTC_TRM.IVL2EXPMIN prescaled
RTC time units. Equivalent to 4 hours 33 minutes 04
seconds if prescaling to count time at 1Hz.
1 Trim interval is 2^(RTC_TRM.IVL2EXPMIN + 1)
prescaled RTC time units. Equivalent to 9 hours 06 minutes 08 seconds if prescaling to count time at 1 Hz.
2 Trim interval is 2^(RTC_TRM.IVL2EXPMIN + 2)
prescaled RTC time units. Equivalent to 18 hours 12
minutes 16 seconds if prescaling to count time at 1Hz.
3 Trim interval is 2^(RTC_TRM.IVL2EXPMIN + 3)
prescaled RTC time units. Equivalent to 36 hours 24
minutes 32 seconds if prescaling to count time at 1Hz.

21–128

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ADuCM4050 RTC Register Descriptions

Table 21-58: RTC_TRM Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
3 ADD
(R/W)

Trim Polarity.
RTC_TRM.ADD specifies whether RTC_TRM.VALUE is a positive (additive) or negative (subtractive) adjustment of the RTC count.
0 Subtract (by means of a stall) RTC_TRM.VALUE prescaled RTC time units from the RTC count at a period
defined by RTC_TRM.IVL.
1 Add Trim Value to RTC Count Add
RTC_TRM.VALUE prescaled RTC time units to the
RTC count at a period defined by RTC_TRM.IVL.

2:0 VALUE(R/W)

Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC
Count at the End of a Periodic Interval Selected by RTC_TRM.IVL.
A trim adjustment of +/- 0,1,2,3,4,5,6,7 prescaled RTC time units in the RTC count(at a period defined by RTC_TRM.IVL) can be specified using RTC_TRM.VALUE.
Note that if an RTC interrupt event is configured to occur at a time which is coincidentally trimmed, the interrupt behavior is as follows. If the interrupt time is trimmedout (skipped) because of a positive trim, the interrupt issues at the end of the trim. For
negative trims which coincidentally stall the RTC count at the target time for the interrupt event, the interrupt issues at the first occurrence of the target time.
0 Make no adjustment to the RTC count at the end of atrim interval.
1 Add or subtract 1 prescaled RTC time unit to the RTC
count.
2 Add or subtract 2 prescaled RTC time units to the RTC
count.
3 Add or subtract 3 prescaled RTC time units to the RTC
count.
4 Add or subtract 4 prescaled RTC time units to the RTC
count.
5 Add or subtract 5 prescaled RTC time units to the RTC
count.
6 Add or subtract 6 prescaled RTC time units to the RTC
count.
7 Add or subtract 7 prescaled RTC time units to the RTC
count.

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Timer (TMR)

22 Timer (TMR)

The ADuCM4050 MCU has three general purpose timers (GP Timers); each with a 16-bit up/down counter and aclock prescaler of up to 8 bits, specifically with prescale options of 1, 4, 16, 64, or 256. Up to four clock sources canbe selected for the timer in a separate clocking block.
The timers have a maximum timeout range of (2 Counter_width/Clock Frequency).
For a timer clock frequency of 26 MHz, the maximum timeout range is 2 (16+8) /26 MHz = 0.6 s.
For a timer clock frequency of 32 kHz, the maximum timeout range is 2 (16+8) /32 kHz = 512 s.
Some sample use cases of these timers are as follows:• As a 1 μs clock• As a SysTick timer to provide a reference time base of 50 to 60 μs for firmware• As a data rate counter
The data rate can range between 100 bps and 400 Kbps, depending on the wireless protocol.
• PWM generation• PWM demodulation

TMR Features
The general purpose timers used by the ADuCM4050 MCU supports the following features:• Supports two modes of operation: free running and periodic• The PWM generation function can be configured to be idle in logic 0 or logic 1• The PWM output is generated in toggle mode or match mode
• Selectable IRQ source assertions can be used to reset the timers• Allows PWM demodulation to be performed on all three timers using the reset and capture features
The timers have two modes of operation, free running and periodic. In free running mode, the counter decrements/
increments from the maximum/minimum value until zero/full scale and starts again at the maximum/minimum
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TMR Functional Description

value. In periodic mode, the counter decrements/increments from the value in the load register, TMR_LOAD until
zero/full scale and starts again at the value stored in the load register.
The value of a counter can be read at any time by accessing its value register (TMR_ACURCNT.VALUE). This assumes a synchronized clock and avoids synchronization delay by returning the asynchronous (not synchronized)
timer value directly . The alternative is to read TMR_CURCNT.VALUE which returns a slightly delayed timer value.
Reading TMR_ACURCNT.VALUE when the timer and core operate on different clocks is unsupported, and the return value is undefined in this case.
Writing 1 to the TMR_CTL.EN bit initiates the up/down counter. An IRQ is generated each time the value of thecounter reaches zero when counting down, or each time the counter value reaches full scale when counting up. An
IRQ can be cleared by writing 1 to the TMR_CLRINT.TIMEOUT bit . The IRQ is also set when a selected event
occurs on the event inputs.
The PWM generation function may be configured to be idle in logic 0 or logic 1 by writing to the
TMR_PWMCTL.IDLESTATE bit. An optional match value may be written to the TMR_PWMMATCH.VALUE bit
and enabled by writing to the TMR_PWMCTL.MATCH bit.
The PWM output is generated in one of two modes: toggle or match. In toggle mode, the PWM output toggles ontimer zero/full scale which provides a 50% duty cycle with a configurable period. Match mode provides a configurable duty cycle and a configurable period PWM output. In match mode, the PWM output starts in the idle state asconfigured in the TMR_CTL register, is then asserted when the timer and match values are equal, and is deasserted
to the idle state again when the timer reaches zero/full scale.
Selectable IRQ source assertions can be used to reset the timers if the TMR_CTL.RSTEN bit is set. It can select one
from 40 different events as trigger source as input to the block. This interrupt source can also be used as part of acapture feature. This capture feature is also triggered by a selected IRQ source assertion. When triggered, the current
timer value is copied to the TMR_CAPTURE.VALUE bit, and the timer continues to run. This feature can be used
to determine the assertion of an event with increased accuracy.

TMR Functional Description
This section provides information on the function of the general-purpose timers used by the ADuCM4050 MCU.

TMR Block Diagram
The figure shows the general-purpose timers used by the ADuCM4050 MCU.

22–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceTMR Operating Modes

16-bit LOAD
Clock
Sources
8-bit PRESCALE(1, 4, 16, 64, 256)

16-bit Up/Down COUNTER

IRQ
GEN
Reset

TIMER VALUEIRQ

CAPTURE

40 IRQ Events
CaptureMATCH VALUE

PWM LOGIC
PWM
OutputFigure 22-1: Timer 1 Block Diagram

TMR Operating Modes
The general-purpose timers used by the ADuCM4050 MCU supports the following modes of operation:

Free Running ModeIn free running mode, the timer is started by writing to the TMR_CTL.EN bit. The timer increments from zero /full scale to full scale/zero if counting up/down (configured by TMR_CTL.UP bit). Full scale is 216 − 1 or 0xFFFF
in hexadecimal format. On reaching full scale (or zero), a time out interrupt occurs, and TMR_STAT.TIMEOUT
bit is set. To clear the TMR_STAT.TIMEOUT bit, user code must write 1 to the TMR_CLRINT.TIMEOUT bit.
The timer is reloaded with the maximum/minimum value when the time out interrupt occurs. If the
TMR_CTL.RLD bit is set, the timer also reloads when the TMR_CLRINT.TIMEOUT bit is written 1.

Periodic Mode
In periodic mode, the initial TMR_LOAD.VALUE value must be loaded before enabling the timer. The timer isstarted by writing TMR_CTL.EN bit. The counter value increments from the value stored in the
TMR_LOAD.VALUE register to full scale or decrements from the value stored in the TMR_LOAD.VALUE registerto zero, depending on the TMR_CTL.UP settings (count up/down). When the counter reaches full scale or zero, thetimer generates an interrupt. The TMR_LOAD.VALUE is reloaded into the counter, and it continues counting up/
down. The timer should be disabled prior to changing the or TMR_LOAD.VALUE register. By default, the counteris reloaded automatically when generating the IRQ. If TMR_CTL.RLD bit is set to 1, the counter is also reloaded
when user code writes TMR_CLRINT.TIMEOUT bit. To enable timing critical modifications to the load value, anonsynchronized write address is provided at TMR_ALOAD. Writing TMR_ALOAD bypasses synchronization logic,
providing finer grained control over the load value. If the TMR_ALOAD register is changed while the timer is enabled and running on a different clock than the core, undefined results may occur.

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TMR Operating Modes

TMR_STAT should be read prior to writing to any timer registers following the set or clear of enable. Once
TMR_STAT.PDOKbit returns zero, registers can be modified. This assures the timer is done synchronizing timer
control between the core and timer clock domains. The typical synchronization time is two timer clock periods. Any
modification to TMR_CTL.UP or TMR_CTL.MODE bits must be performed while the timer is disabled.
At any time, TMR_CURCNT.VALUE contains a valid value to be read, synchronized to the core clock. The
TMR_CTL register enables the counter, selects the mode, selects the prescale value, and controls the event capture
function.

Toggle Mode
In toggle mode, the PWM provides a 50% duty cycle output with configurable period. The PWM output is inverted when a timeout interrupt is generated by the timer. The period is therefore defined by the selected clock andprescaler. If the timer is running in the periodic mode, the PWM output also depends on the TMR_LOAD.VALUE
value. Timeout events are evaluated at the end of a timer period (larger than a core clock period).
The following figures show the PWM output in toggle mode when the timer is set to count up/down.
Count Max

Count MinPWM Output

Figure 22-2: PWM Output in Toggle Mode When Timer is Set to Count Up

Count Max

Count MinPWM Output

Figure 22-3: PWM Output in Toggle Mode When Timer is Set to Count Down

Match Mode
Match mode provides a configurable duty cycle and configurable period PWM output. Like toggle mode, the period
is defined by the selected clock and the prescaler, as well as TMR_LOAD.VALUE (when the timer is run in periodic
22–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceTMR Operating Modes

mode). The duty cycle is defined by the TMR_PWMMATCH.VALUE value. When the timer's counter value is equal
to the value stored in TMR_PWMMATCH.VALUE, the PWM output is asserted. It remains asserted until the timer
reaches zero/full scale and is then deasserted. Match and timeout events are evaluated at the end of a timer period(longer than a core clock period).
Match events take priority over timeout events when triggered on the same cycle, therefore a 100% duty cycle PWM
may be configured by setting TMR_PWMMATCH.VALUE equal to TMR_LOAD.VALUE when running in periodic
mode, or zero/full scale when set to free running mode. A 0% duty cycle is only possible when running in periodic
mode and may be configured by setting TMR_PWMMATCH.VALUE outside of the range of the timers counter(TMR_LOAD.VALUE + 1 when counting down, TMR_LOAD.VALUE − 1 when counting up).
The following figures show the PWM output in Match mode when the timer is set to count up/down and PWM
idle state set to 0.
Count MaxPWM Match
Count MinPWM Output

Figure 22-4: PWM Output in Match Mode When Timer is Set to Count Up and PWM Idle State is 0

Count MaxPWM Match
Count MinPWM Output

Figure 22-5: PWM Output in Match Mode When Timer is Set to Count Down and PWM Idle State is 0

For a given clock source, prescaler, and TMR_LOAD.VALUE value, the PWM period in toggle mode is twice that ofthe period in match mode, due to toggle mode inverting just once each timer counter period, while match modeboth asserts and de-asserts the PWM output. Writes to the TMR_CTL and TMR_PWMMATCH.VALUE registers
while the timer is running are supported. Note however that the PWM output will not reflect changes to TMR_CTL

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22–5

PWM Modulation

until the next match or timeout event. This enables modifying the PWM behavior while maintaining a deterministic PWM duty cycle. It is possible to force the PWM output to match newly written settings by writing to
TMR_CLRINT or by disabling/enabling the timer.
NOTE: The PWM may be configured to operate in either toggle mode or match mode. In either mode, using thePWM output requires selecting the appropriate mux settings in the GPIO control module.

PWM Modulation
The PWM generation function may be configured to idle in logic 0 or logic 1 by writing the corresponding bit inrespective PWM control register. An optional match value may be written to the respective PWM match registerand enabled by writing another bit in PWM control register. The PWM output is generated in one of two modes:
toggle or match. In toggle mode, the PWM output toggles on timer zero/full scale which provides a 50% duty cyclewith a configurable period. Match mode provides a configurable duty cycle and a configurable period PWM output.
In match mode, the PWM output starts in the idle state as configured in the PWM control register, is then asserted
when the timer and match values are equal, and is deasserted to the idle state again when the timer reaches zero/fullscale.
The sequence is as follows:
1. Set the PWM registers.
2. Enable the Timer.

PWM Demodulation
PWM demodulation can be implemented by enabling both the timer reset and capture features with the event logic,
which allows separate count values to be read for the high and low levels of the PWM input. In practice, the MCU
selects the appropriate PWM (GPIO) interrupt source and triggers an interrupt on the rising edge of the PWM
pulse. This resets the counters and interrupts the MCU when a capture is detected. The MCU modifies the interrupt to trigger on the falling edge of the PWM pulse (before the edge occurs). This interrupt captures the high levelcount in TMR_CAPTURE.VALUE and resets the counter and interrupts the MCU again with the updated capture.
The MCU reads this captured count and modifies the interrupt to operate off the positive edge again (before theedge occurs). This interrupt captures the low level count in TMR_CAPTURE.VALUE and resets the counter andinterrupts the MCU again. The MCU can read this captured count. Comparing both read values indicates thePWM values. The PWM pulse widths must be wide enough to allow for the overhead of synchronization delays,
IRQ delays, and software setup that is required between the various input edges.

22–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceClock Select

GPIO
GPIO_IRQ
Selected EVENT Input
RESET/EVENT Rising EDGE
GPT_IRQPRESCALE/VALUE
CAPTURE01

Don’t Care

0x350

0x300

01

0x348

01

High Count(0x350)

Low Count(0x300)01

High Count(0x348)Figure 22-6: PWM Demodulation Waveforms

Clock SelectFour clocks are available for each of the four timers. The selected clock is used, along with a prescaler, to control thefrequency of the timers counter logic. The available clocks are selected using the TMR_CTL.CLK bits. Only synchronous clocks are used. When 32 kHz clock is selected, it is synchronized to the system clock first. Clock configuration settings are part of the clock control module. For more information, refer to System Clocks.
Table 22-1: Clock Source
Clock SelectGPT Clock Source

00

PCLK

01

HFOSC

10

LFOSC

11

LFXTAL

Capture Events
40 interrupt events can be captured by the general-purpose timers. Any one of the 40 events associated with a general-purpose timer can cause a capture of the 40-bit TMR_CURCNT register into the 16-bit TMR_CAPTURE register.
TMR_CTL.EVTRANGE has a 6-bit field selecting which of the 40 events to capture.
When the selected IRQ occurs, the TMR_CURCNT register is copied into the TMR_CAPTURE.VALUE register.
The TMR_STAT.CAPTURE bit is set. The IRQ is cleared by writing 1 to the TMR_CLRINT.EVTCAPT bit. The
TMR_CAPTURE.VALUE bit also holds its value and cannot be overwritten until the TMR_CLRINT.EVTCAPT
bit is written to 1.
Table 22-2: Capture and Reset Event Function
Event Select Bits (EVTSEL)

GPT0 Capture Source

GPT1 Capture Source

GPT2 Capture Source

0

RTC1/lfxtal_err

External Interrupt 0

External Interrupt 1

1

External Interrupt 3

RTC0

UART0

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–7Capture Events

Table 22-2: Capture and Reset Event Function (Continued)
Event Select Bits (EVTSEL)

GPT0 Capture Source

GPT1 Capture Source

GPT2 Capture Source

2

SPI0

SPI1

SPI2

3

SPORT0B

GPIO-IntA

GPIO-IntB

4

I2C0 Slave

P0_8 Input

Reserved

5

Reserved

DMA Error

DMA Channel 0 Done

6

DMA Channel 2 DoneDMA Channel 3 DoneDMA Channel 4 Done

7

DMA Channel 6 DoneDMA Channel 7 DoneDMA Channel 8 Done

8

DMA Channel 10 DoneDMA Channel 11 DoneDMA Channel 12 Done

9

DMA Channel 14 DoneDMA Channel 15 DoneDMA Channel 16 Done10

DMA Channel 18 DoneDMA Channel 19 DoneDMA Channel 20 Done11

DMA Channel 22 DoneDMA Channel 23 DoneDMA Channel 24 Done

12

DMA Channel 26 Done

Flash Controller

PLL

13

VREG Over

Battery Voltage Range

Crypto14

Reserved

Reserved

Reserved

15

Reserved

Reserved

Reserved

16

BeeperTimer0Timer1

17

TimerRGB

WDT

RTC1

18

External Interrupt 0

RTC1

External Interrupt 0

19

External Interrupt 1

External Interrupt 1

External Interrupt 2

20

External Interrupt 2External Interrupt 2External Interrupt 3

21

RTC

External Interrupt 3

RTC

22

UART0

UART0

UART1

23

UART1

UART1

SPI0

24

SPI1

SPI0

SPI1

25

SPI2

SPI2

SPORT0A

26

SPORT0A

SPORT0A

SPORT0B

27

GPIO-IntASPORT0B

GPIO-IntA

28

GPIO-IntB

GPIO-IntB

I2C0 Master29

I2C0 Master

I2C0 Master

I2C0 Slave30

P0_8 Input

I2C0 Slave

P0_8 Input

31

Reserved

Reserved

Reserved

32

Reserved

Reserved

Reserved

22–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceTMR Interrupts and Exceptions

Table 22-2: Capture and Reset Event Function (Continued)
Event Select Bits (EVTSEL)

GPT0 Capture Source

GPT1 Capture Source

GPT2 Capture Source

33

DMA Error

Reserved

DMA Error

34

DMA Channel 0 DoneDMA Channel 0 DoneDMA Channel 1 Done35

DMA Channel 1 DoneDMA Channel 1 DoneDMA Channel 2 Done36

DMA Channel 3 DoneDMA Channel 2 DoneDMA Channel 3 Done37

DMA Channel 4 DoneDMA Channel 4 DoneDMA Channel 5 Done38

DMA Channel 5 DoneDMA Channel 5 DoneDMA Channel 6 Done39

DMA Channel 7 DoneDMA Channel 6 DoneDMA Channel 7 DoneTMR Interrupts and Exceptions
Refer to Events (Interrupts and Exceptions), for more information.
TMR Power Modes Behavior
All the registers in the three general purpose timers are retained in hibernate mode.

ADuCM4050 TMR Register Descriptions
General Purpose Timer (TMR) contains the following registers.
Table 22-3: ADuCM4050 TMR Register List
Name

Description

TMR_ALOAD

16-bit Load Value, Asynchronous

TMR_ACURCNT

16-bit Timer Value, Asynchronous

TMR_CAPTURE

CaptureTMR_CLRINT

Clear Interrupt

TMR_CTL

Control

TMR_EVENTSELECT

Timer Event Selection Register

TMR_LOAD

16-bit Load Value

TMR_PWMCTL

PWM Control Register

TMR_PWMMATCH

PWM Match Value

TMR_STAT

Status

TMR_CURCNT

16-bit Timer Value

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–9ADuCM4050 TMR Register Descriptions

16-bit Load Value, Asynchronous
Only use when a synchronous clock source is selected (TMR_CTL.CLK=00).
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Load Value, Asynchronous

Figure 22-7: TMR_ALOAD Register Diagram
Table 22-4: TMR_ALOAD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

22–10

Load Value, Asynchronous.
The up/down counter is periodically loaded with this value if periodic mode is selected(TMR_CTL.MODE=1). Writing this bitfield takes advantage of having the timer run
on PCLK by bypassing clock synchronization logic otherwise required.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR Register Descriptions

16-bit Timer Value, Asynchronous
Only use when a synchronous clock source is selected (TMR_CTL.CLK=00).
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)Counter Value

Figure 22-8: TMR_ACURCNT Register Diagram
Table 22-5: TMR_ACURCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)Counter Value.
Reflects the current up/down counter value. Reading this bitfield takes advantage of
having the timer run on PCLK by bypassing clock synchronization logic otherwise required.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–11

ADuCM4050 TMR Register Descriptions

Capture15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)16-bit Captured Value

Figure 22-9: TMR_CAPTURE Register Diagram
Table 22-6: TMR_CAPTURE Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)

22–12

16-bit Captured Value.
This bitfield will hold its value until TMR_CLRINT.EVTCAPT is set by user code.
This bitfield will not be over written even if another event occurs without writing to
the TMR_CLRINT.EVTCAPT.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR Register Descriptions

Clear Interrupt
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EVTCAPT (W1C)
Clear Captured Event Interrupt

TIMEOUT (W1C)
Clear Timeout Interrupt

Figure 22-10: TMR_CLRINT Register Diagram
Table 22-7: TMR_CLRINT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 EVTCAPT(RX/W1C)

Clear Captured Event Interrupt.
This bit is used to clear a capture event interrupt
0 No effect
1 Clear the capture event interrupt

0 TIMEOUT(RX/W1C)

Clear Timeout Interrupt.
This bit is used to clear a timeout interrupt.
0 No effect
1 Clears the timeout interrupt

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–13

ADuCM4050 TMR Register Descriptions

Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

SYNCBYP (R/W)
Synchronization Bypass

PRE (R/W)
Prescaler

RSTEN (R/W)
Counter and Prescale Reset Enable

UP (R/W)
Count up

EVTEN (R/W)
Event SelectMODE (R/W)
Timer ModeRLD (R/W)
Reload Control

EN (R/W)
Timer Enable

CLK (R/W)
Clock SelectFigure 22-11: TMR_CTL Register Diagram
Table 22-8: TMR_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 SYNCBYP(R/W)

Synchronization Bypass.
Used to bypass the synchronization logic within the block. Use only with synchronous
clocks, i.e, when the core clock (PCLK) is selected as the source for Timer clock. Thisbit also changes TMR_CTL.PRE prescaler count from 3 to 0 when this bit is set 1'b1
and TMR_CTL.PRE is selected to Source_Clock/1.
The value of this bit will affect the prescaler count value when TMR_CTL.PRE is selected to Source_Clock/1.
When this bit is set, Source_Clock/1 is selected and prescale count of zero will be usedby the prescaler.
When this bit is cleared, Source_Clock/4 is selected and prescale count of three will be
used by the prescaler.
0 Synchronization bypass is disabled
1 Synchronization bypass is enabled

14 RSTEN
(R/W)

22–14

Counter and Prescale Reset Enable.
Used to enable and disable the reset feature. Used in conjunction with
TMR_CTL.EVTEN and TMR_EVENTSELECT.EVTRANGE. When a selected event
occurs the 16 bit counter and 8 bit prescale are reset. This is required in PWM demodulation mode.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR Register Descriptions

Table 22-8: TMR_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
13 EVTEN(R/W)

Event Select.
Used to enable and disable the capture of events. Used in conjunction with the
TMR_EVENTSELECT.EVTRANGE: when a selected event occurs the current valueof the Up/Down counter is captured in TMR_CAPTURE.
0 Events will not be captured
1 Events will be captured

7 RLD
(R/W)

Reload Control.
This bit is only used for periodic mode. It allows the user to select whether the up/
down counter should be reset only on a timeout event or also when
TMR_CLRINT.TIMEOUT is set.
0 Up/Down counter is only reset on a timeout event
1 Resets the up/down counter when the Clear Timeout
Interrupt bit is set

6:5 CLK(R/W)

Clock Select.
Used to select a timer clock from the four available clock sources.
0 Select CLK Source 0 (default)
1 Select CLK Source 1
2 Select CLK Source 2
3 Select CLK Source 3

4 EN
(R/W)

Timer Enable.
Used to enable and disable the timer. Clearing this bit resets the timer, including the
TMR_CURCNT register.
0 Timer is disabled (default)
1 Timer is enabled

3 MODE(R/W)

Timer Mode.
This bit is used to control whether the timer runs in periodic or free running mode. In
periodic mode the up/down counter starts at the defined TMR_LOAD.VALUE; in freerunning mode the up/down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down.
0 Timer runs in free running mode
1 Timer runs in periodic mode (default)

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–15

ADuCM4050 TMR Register Descriptions

Table 22-8: TMR_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
2 UP
(R/W)

Count up.
Used to control whether the timer increments (counts up) or decrements (counts
down) the Up/Down counter.
0 Timer is set to count down (default)
1 Timer is set to count up

1:0 PRE(R/W)

Prescaler.
Controls the prescaler division factor applied to the timer's selected clock.
0 source_clock / 1 or source_clock/4 When
TMR_CTL.SYNCBYP is set Source_Clock/1, andwhen cleared Source_Clock/4
1 Source_clock / 16
2 Source_clock / 64
3 Source_clock / 256

22–16

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR Register Descriptions

Timer Event Selection Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EVTRANGE (R/W)
Event Select Range

Figure 22-12: TMR_EVENTSELECT Register Diagram
Table 22-9: TMR_EVENTSELECT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5:0 EVTRANGE(R/W)

Event Select Range.
Timer event select range (0 - 39).The register value selects one of the 40 event inputs
connected to the module.The event select range is 0 to 39 only. If any value above 39
is written, the register content will be cleared to zero.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–17

ADuCM4050 TMR Register Descriptions

16-bit Load Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Load Value

Figure 22-13: TMR_LOAD Register Diagram
Table 22-10: TMR_LOAD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

22–18

Load Value.
The up/down counter is periodically loaded with this value if periodic mode is selected(TMR_CTL.MODE=1). TMR_LOAD.VALUE writes during up/down counter timeout
events are delayed until the event has passed.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR Register Descriptions

PWM Control Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IDLESTATE (R/W)
PWM Idle State

MATCH (R/W)
PWM Match Enabled

Figure 22-14: TMR_PWMCTL Register Diagram
Table 22-11: TMR_PWMCTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 IDLESTATE(R/W)

PWM Idle State.
This bit is used to set the PWM idle state
0 PWM idles low
1 PWM idles high0 MATCH(R/W)

PWM Match Enabled.
This bit is used to control PWM operational mode
0 PWM in toggle mode
1 PWM in match mode

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–19

ADuCM4050 TMR Register Descriptions

PWM Match Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
PWM Match Value

Figure 22-15: TMR_PWMMATCH Register Diagram
Table 22-12: TMR_PWMMATCH Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

22–20

PWM Match Value.
The value is used when the PWM is operating in match mode. The PWM output isasserted when the up/down counter is equal to this match value. PWM output is deasserted again when a timeout event occurs. If the match value is never reached, or occurs simultaneous to a timeout event, the PWM output remains idle.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR Register Descriptions

Status15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CNTRST (R)Counter Reset Occurring

TIMEOUT (R)Timeout Event Occurred

PDOK (R)
Clear Interrupt Register Synchronization

CAPTURE (R)Capture Event Pending

BUSY (R)Timer Busy

Figure 22-16: TMR_STAT Register Diagram
Table 22-13: TMR_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
8 CNTRST(R/NW)
7 PDOK(R/NW)Counter Reset Occurring.
Indicates that the counter is currently being reset due to an event detection. For this towork, TMR_CTL.RSTEN needs to be set
Clear Interrupt Register Synchronization.
This bit is set automatically when the user sets TMR_CLRINT.TIMEOUT=1. It iscleared automatically when the clear interrupt request has crossed clock domains andtaken effect in the timer clock domain
0 The interrupt is cleared in the timer clock domain
1 Clear Timeout Interrupt bit is being updated in the timer clock domain

6 BUSY(R/NW)

Timer Busy.
This bit informs the user that a write to TMR_CTL is still crossing into the timer clock
domain. This bit should be checked after writing TMR_CTL and further writes should
be suppressed until this bit is cleared.
0 Timer ready to receive commands to Control Register
1 Timer not ready to receive commands to Control Register

1 CAPTURE(R/NW)

Capture Event Pending.
A capture of the current timer value has occurred.
0 No capture event is pending
1 A capture event is pending

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–21

ADuCM4050 TMR Register Descriptions

Table 22-13: TMR_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 TIMEOUT(R/NW)

Timeout Event Occurred.
This bit set automatically when the value of the counter reaches zero while counting
down or reaches full scale when counting up. This bit is cleared when
TMR_CLRINT.TIMEOUT is set by the user.
0 No timeout event has occurred
1 A timeout event has occurred

22–22

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR Register Descriptions

16-bit Timer Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)
Current Count

Figure 22-17: TMR_CURCNT Register Diagram
Table 22-14: TMR_CURCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)

Current Count.
Reflects the current up/down counter value. Value delayed two PCLK cycles due toclock synchronizers.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

22–23

RGB Timer

23 RGB Timer

This section describes the RGB Timer functionality of the ADuCM4050 MCU.

RGB Timer Features
The RGB Timer supports the following features:• A 16-bit up/down counter and a clock prescaler of up to 8 bits with prescale options of 1, 16, 64, or 256.
• Up to 4 clocks can be selected for the timer in a separate clocking block.
• Three PWM outputs with independent control and match registers.
• Maximum timeout duration depends on the clock selected.
Timeout = (2Counter_width)/Clock Frequency
For example, Timeout with 26 MHz clock = (2 16+8) /26 MHz = 0.6 s
Timeout with 32 kHz clock = (2 16+8) /32 kHz = 512 s• Supports two modes of operation: free running and periodic.
• Reset and capture features allows PWM demodulation to be performed on the timer.
• Facilitates clocks asynchronous to the processor clock to be used as the source for the timers.

RGB Timer Functional Description
This section provides information on the function of the RGB Timer used by the ADuCM4050 MCU.

RGB Timer Block Diagram
The figure shows the block diagram of RGB Timer.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–1

RGB Timer Operation

Figure 23-1: RGB Timer Block Diagram

RGB Timer Operation
The RGB Timer supports two modes of operation: free running and periodic.
In free running mode, the timer is started by writing to the TMR_RGB_CTL.EN bit. The timer increments fromzero /full scale to full scale/zero when counting up/down. Full scale is 216 − 1 or 0xFFFF. On reaching full scale (orzero scale), a time out interrupt occurs, and the TMR_RGB_STAT.TIMEOUT bit is set. To clear this bit, user code
must write to the TMR_RGB_CLRINT.TIMEOUT bit. The timer interrupt generated is always a level and remains
high until this clear occurs. The timer is reloaded with the maximum/minimum value when the time out interrupt
occurs. If the TMR_RGB_CTL.RLD bit is set, the timer is also reload when the TMR_RGB_CLRINT.TIMEOUT
bit is written to 1.
In periodic mode, the initial value must be loaded in the TMR_RGB_LOAD.VALUE bit before enabling the timer.
The timer is started by writing to the TMR_RGB_CTL.EN bit. The counter value increments to full scale from thevalue stored in the TMR_RGB_LOAD register or decrements to zero scale from the value stored in the
TMR_RGB_LOAD register, depending on the TMR_RGB_CTL.UP bit. When the counter reaches full scale/zero,
the timer generates an interrupt. The TMR_RGB_LOAD.VALUE bit is reloaded into the counter, and it continues
counting up/down. The timer must be disabled prior to changing the TMR_RGB_CTL or TMR_RGB_LOAD register. By default, the counter is reloaded automatically when generating the IRQ. If the TMR_RGB_CTL.RLD bit isset, the counter is also reloaded when user code writes to the TMR_RGB_CLRINT register. To enable timing criticalmodifications to the load value, a nonsynchronized write address is provided at the TMR_RGB_ALOAD register.
23–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceRGB Timer Operation

Writing to the TMR_RGB_ALOAD register bypasses synchronization logic, providing finer grained control over theload value. If the TMR_RGB_ALOAD register is changed while the timer is enabled and running on a different clock
than the core, undefined results may occur.
Following a set or clear of the TMR_RGB_CTL.EN bit, the TMR_RGB_STAT register must be read prior to writing
to any timer registers. Once the TMR_RGB_STAT.PDOK bit returns zero, the registers can be modified. This ensures that the timer has completed synchronizing timer control between the core and timer clock domains. The typical synchronization time is two timer clock periods. Any modification to the TMR_RGB_CTL.UP and
TMR_RGB_CL.MODE bits must be performed while the timer is disabled.
At any time, the TMR_RGB_CURCNT register contains a valid value to be read, synchronized to the core clock. The
TMR_RGB_CTL register enables the counter, selects the mode, selects the prescale value, and controls the event capture function.
The PWM may be configured to operate in toggle mode or match mode. For both modes, using the PWM output
requires selecting the appropriate mux settings in the GPIO control module.
In toggle mode, the PWMs provides a 50% duty cycle output with configurable period. The PWMs output is inverted when a timeout interrupt is generated by the timer. The period is therefore defined by the selected clock andprescaler. If the timer is run in periodic mode, the PWM outputs also depends on the TMR_RGB_LOAD.VALUE
bit. Timeout events are evaluated at the end of a timer period (longer than a core clock period).
Match mode provides a configurable duty cycle and configurable period PWM outputs. As in the case of toggle
mode, the period is defined by the selected clock, prescaler, and TMR_RGB_LOAD.VALUE bit (when the timer is
run in periodic mode). The duty cycle is defined by the respective PWM match register values of each PWM output. When the timer counter value is equal to the value stored in the match register, the PWM outputs are asserted.
The PWM outputs remains asserted until the timer reaches zero/full scale and then deasserted. Match and timeout
events are evaluated at the end of a timer period (potentially much longer than a core clock period). Match eventstake priority over timeout events when triggered on the same cycle. Therefore, a 100% duty cycle PWM may be
configured by setting the Match register value equal to TMR_RGB_LOAD.VALUE when running in periodic mode,or zero/full scale when set to free running mode. A 0% duty cycle is only possible when running in periodic modeand may be configured by setting the Match register outside the timer counter range (TMR_RGB_LOAD.VALUE +1 when counting down and TMR_RGB_LOAD.VALUE − 1 when counting up).
For a given clock source, prescaler, and TMR_RGB_LOAD.VALUE, the PWM period in toggle mode is twice thatof the match mode. Toggle mode inverts only once for the timer counter period. Match mode asserts and de-asserts
the PWM output. Writes to the PWM control and match registers while the timer is running are supported.
NOTE: PWM outputs do not reflect changes to the control register until the next match or timeout event. This
enables modifying the PWM behavior while maintaining a deterministic PWM duty cycle. It is possible to force thePWM output to match newly written settings by writing to the TMR_RGB_CLRINT register or by disabling/enabling the timer.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–3

RGB Timer Operation

PWM Modulation
The PWM generation function may be configured to idle in logic 0 or logic 1 by writing the corresponding bit inrespective PWM control register. An optional match value may be written to the respective PWM match registerand enabled by writing another bit in PWM control register. The PWM output is generated in one of two modes:
toggle or match. In toggle mode, the PWM output toggles on timer zero/full scale which provides a 50% duty cyclewith a configurable period. Match mode provides a configurable duty cycle and a configurable period PWM output.
In match mode, the PWM output starts in the idle state as configured in the PWM control register, is then asserted
when the timer and match values are equal, and is deasserted to the idle state again when the timer reaches zero/fullscale.
The corresponding PWM control registers for the PWM outputs PWM0, PWM1, and PWM2 are
TMR_RGB_PWM0CTL, TMR_RGB_PWM1CTL, and TMR_RGB_PWM2CTL respectively.
The PWM match registers for the PWM outputs PWM0, PWM1, and PWM2 are TMR_RGB_PWM0MATCH,
TMR_RGB_PWM1MATCH, and TMR_RGB_PWM2MATCH respectively.
Set the PWM register with appropriate values prior to enabling the timer to avoid unknown starting point.
The sequence is as follows:
1. Set the PWM registers.
2. Enable the Timer.
The figure shows the waveform for all the three PWM outputs programmed with different duty cycle and the risingedge of all the PWM outputs occur simultaneously.

Figure 23-2: PWM Output Waveforms

PWM Demodulation
PWM demodulation can be implemented by enabling both the timer reset and capture features with events logic
that allows separate count values to be read for the high and low levels of the PWM input. In practice, the MCU
selects the appropriate PWM (GPIO) interrupt source and triggers an interrupt on the rising edge of the PWM
pulse. This resets the counters and interrupts the MCU when a capture is detected. The MCU modifies the
23–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware ReferenceRGB Timer Operationinterrupt to trigger on the falling edge of the PWM pulse (before the edge occurs). This interrupt captures the highlevel count in the TMR_RGB_CAPTURE register and resets the counter and interrupts the MCU again with theupdated capture. The MCU reads this captured count and modified the interrupt to operate off the positive edge
again (before the edge occurs). This interrupt captures the low level count in the TMR_RGB_CAPTURE register andresets the counter and interrupts the MCU again. The MCU can read this captured count. Comparing both readvalues indicates the PWM values. The PWM pulse widths must be wide enough to allow for the overhead of synchronization delays, IRQ delays and software setup that is required between the various input edges.
The figure shows PWM demodulation waveforms.
GPIO
GPIO_IRQ
Selected EVENT Input
RESET/EVENT Rising EDGE
GPT_IRQ
01

PRESCALE/
VALUE

0x350

Don’t CareCAPTURE

0x300

01

High Count(0x350)

0x348

01

Low Count(0x300)01

High Count(0x348)Figure 23-3: PWM Demodulation Waveforms

Clock Select
There are four clocks available for each of the timers. The selected clock is used, along with a prescaler, to control
the frequency of the timer’s counter logic. Thecclocks are selected by setting the TMR_RGB_CTL.CLK bits. Only
synchronous clocks are used. When the 32 kHz clock is selected, it is synchronized to the system clock first external,
which is to this block.

Capture Events
There are 40 interrupt events that can be captured by the timer. Any one of the 40 events associated with the timer
can cause a capture of the 16-bit TMR_RGB_CURCNT register into the 16-bit TMR_RGB_CAPTURE register. The
TMR_RGB_EVENTSELECT register has 6 bit fields to select one of the 40 events. When any event triggers an output enable, event_out, is asserted. The interrupt events are connected to the 32 sources of the Cortex NVIC interrupt bus and these are all synchronous to the main system clock.
When the selected IRQ occurs, the TMR_RGB_CURCNT register is copied into the TMR_RGB_CAPTURE register.
The TMR_RGB_STAT.CAPTURE bit is set. The IRQ is cleared by writing 1 to the
TMR_RGB_CLRINT.EVTCAPT bit. The TMR_RGB_CAPTURE register also holds its value and cannot be overwritten until TMR_RGB_CLRINT.EVTCAPT is written to 1.
Table 23-1: Event Lists
Event Select Bits (EVTSEL)

Timer_RGB Capture Source

0

External Interrupt 2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–5

RGB Timer Operation

Table 23-1: Event Lists (Continued)
Event Select Bits (EVTSEL)

Timer_RGB Capture Source

1

UART1

2

SPORT0A

3

I2C0 Master4

Reserved

5

DMA Channel 1 Done

6

DMA Channel 5 Done

7

DMA Channel 9 Done

8

DMA Channel 13 Done

9

DMA Channel 17 Done10

DMA Channel 21 Done11

DMA Channel 25 Done

12

XTAL OSC

13

RNG

14

Reserved

15

Reserved

16

Timer2

17

RTC1

18

External Interrupt 0

19

External Interrupt 1

20

External Interrupt 3

21

RTC0

22

UART0

23

SPI0

24

SPI1

25

SPI2

26

SPORT0B

27

GPIO-IntA

28

GPIO-IntB

29

I2C0 Slave30

P0_8 Input

31

Reserved

23–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

Table 23-1: Event Lists (Continued)
Event Select Bits (EVTSEL)

Timer_RGB Capture Source

32

Reserved

33

DMA Error

34

DMA Channel 0 Done35

DMA Channel 2 Done36

DMA Channel 3 Done37

DMA Channel 4 Done38

DMA Channel 6 Done39

DMA Channel 7 Done

ADuCM4050 TMR_RGB Register Descriptions
Timer_RGB with 3 PWM outputs (TMR_RGB) contains the following registers.
Table 23-2: ADuCM4050 TMR_RGB Register List
Name

Description

TMR_RGB_ALOAD

16-bit Load Value, Asynchronous

TMR_RGB_ACURCNT

16-bit Timer Value, Asynchronous

TMR_RGB_CAPTURE

CaptureTMR_RGB_CLRINT

Clear Interrupt

TMR_RGB_CTL

Control

TMR_RGB_EVENTSELECT

Timer Event selection Register

TMR_RGB_LOAD

16-bit Load Value

TMR_RGB_PWM0CTL

PWM0 Control Register

TMR_RGB_PWM0MATCH

PWM0 Match Value

TMR_RGB_PWM1CTL

PWM1 Control Register

TMR_RGB_PWM1MATCH

PWM1 Match Value

TMR_RGB_PWM2CTL

PWM2 Control Register

TMR_RGB_PWM2MATCH

PWM2 Match Value

TMR_RGB_STAT

Status

TMR_RGB_CURCNT

16-bit Timer Value

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–7

ADuCM4050 TMR_RGB Register Descriptions

16-bit Load Value, Asynchronous
Only use when a synchronous clock source is selected (TMR_RGB_CTL.CLK=00)
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Load Value, Asynchronous

Figure 23-4: TMR_RGB_ALOAD Register Diagram
Table 23-3: TMR_RGB_ALOAD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

23–8

Load Value, Asynchronous.
The Up/Down counter is periodically loaded with this value if periodic mode is selected (TMR_RGB_CTL.MODE=1). Writing TMR_RGB_ALOAD.VALUE takes advantage of having the timer run on PCLK by bypassing clock synchronization logic otherwise required.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

16-bit Timer Value, Asynchronous
Only use when a synchronous clock source is selected (TMR_RGB_CTL.CLK=00)
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)Counter Value

Figure 23-5: TMR_RGB_ACURCNT Register Diagram
Table 23-4: TMR_RGB_ACURCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)Counter Value.
Reflects the current Up/Down counter value. Reading TMR_RGB_ACURCNT takes
advantage of having the timer run on PCLK by bypassing clock synchronization logic
otherwise required.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–9

ADuCM4050 TMR_RGB Register Descriptions

Capture15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)16-bit Captured Value

Figure 23-6: TMR_RGB_CAPTURE Register Diagram
Table 23-5: TMR_RGB_CAPTURE Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)

23–10

16-bit Captured Value.
TMR_RGB_CAPTURE will hold its value until TMR_RGB_CLRINT.EVTCAPT is
set by user code. TMR_RGB_CAPTURE will not be over written even if another event
occurs without writing to the TMR_RGB_CLRINT.EVTCAPT.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

Clear Interrupt
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EVTCAPT (W1C)
Clear Captured Event Interrupt

TIMEOUT (W1C)
Clear Timeout Interrupt

Figure 23-7: TMR_RGB_CLRINT Register Diagram
Table 23-6: TMR_RGB_CLRINT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 EVTCAPT(RX/W1C)

Clear Captured Event Interrupt.
This bit is used to clear a capture event interrupt
0 No effect
1 Clear the capture event interrupt

0 TIMEOUT(RX/W1C)

Clear Timeout Interrupt.
This bit is used to clear a timeout interrupt.
0 No effect
1 Clears the timeout interrupt

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–11

ADuCM4050 TMR_RGB Register Descriptions

Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

SYNCBYP (R/W)
Synchronization Bypass

PRE (R/W)
Prescaler

RSTEN (R/W)
Counter and Prescale Reset Enable

UP (R/W)
Count up

EVTEN (R/W)
Event SelectMODE (R/W)
Timer ModeRLD (R/W)
Reload Control

EN (R/W)
Timer Enable

CLK (R/W)
Clock SelectFigure 23-8: TMR_RGB_CTL Register Diagram
Table 23-7: TMR_RGB_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15 SYNCBYP(R/W)

14 RSTEN(R/W)

13 EVTEN(R/W)

Synchronization Bypass.
Used to bypass the synchronization logic within the block. Use only with synchronous
clocks. This bit field also changes TMR_RGB_CTL.PRE max prescaler count from 3
to 0.
Counter and Prescale Reset Enable.
Used to enable and disable the reset feature. Used in conjunction with
TMR_RGB_CTL.EVTEN and TMR_RGB_EVENTSELECT.EVTRANGE: when a selected event occurs the 16 bit counter and 8 bit prescale are reset. This is required in
PWM demodulation mode.
Event Select.
Used to enable and disable the capture of events. Used in conjunction with the
TMR_RGB_EVENTSELECT.EVTRANGE: when a selected event occurs the current
value of the Up/Down counter is captured in TMR_RGB_CAPTURE.
0 Events will not be captured
1 Events will be captured

23–12

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

Table 23-7: TMR_RGB_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
7 RLD
(R/W)

Reload Control.
TMR_RGB_CTL.RLD is only used for periodic mode; this bit allows the user to selectwhether the Up/Down counter should be reset only on a timeout event or also when
TMR_RGB_CLRINT.TIMEOUT is set
0 Up/Down counter is only reset on a timeout event
1 Resets the up/down counter when the Clear Timeout
Interrupt bit is set

6:5 CLK(R/W)

Clock Select.
Used to select a timer clock from the four available clock sources. Refer to the ClockSource table for further details on the available clock sources
0 Select CLK Source 0(default)
1 Select CLK Source 1
2 Select CLK Source 2
3 Select CLK Source 3

4 EN
(R/W)

Timer Enable.
Used to enable and disable the timer. Clearing this bit resets the timer, including the
TMR_RGB_CURCNT register.
0 Timer is disabled (default)
1 Timer is enabled

3 MODE(R/W)

Timer Mode.
This bit is used to control whether the timer runs in periodic or free running mode. In
periodic mode the up/down counter starts at the defined TMR_RGB_LOAD.VALUE;
in free running mode the up/down counter starts at 0x0000 or 0xFFFF depending onwhether the timer is counting up or down.
0 Timer runs in free running mode
1 Timer runs in periodic mode (default)

2 UP
(R/W)

Count up.
Used to control whether the timer increments (counts up) or decrements (counts
down) the Up/Down counter.
0 Timer is set to count down (default)
1 Timer is set to count up

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–13

ADuCM4050 TMR_RGB Register Descriptions

Table 23-7: TMR_RGB_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1:0 PRE(R/W)

Prescaler.
Controls the prescaler division factor applied to the timer's selected clock.
0 source_clock / 1 or source_clock/4 When
TMR_RGB_CTL.SYNCBYP is Set Source_Clock/1 andwhen cleared Source_Clock/4
1 source_clock / 16
2 source_clock / 64
3 source_clock / 256

23–14

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

Timer Event selection Register
The register value selects one of the 40 event inputs connected to the module.The event select range is 0 to 39 only.
If any value above 39 is written, the register content will be cleared to zero.
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EVTRANGE (R/W)
Event select range

Figure 23-9: TMR_RGB_EVENTSELECT Register Diagram
Table 23-8: TMR_RGB_EVENTSELECT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
5:0 EVTRANGE(R/W)

Event select range.
Timer event select range (0 - 39).The register value selects one of the 40 event inputs
connected to the module.The event select range is 0 to 39 only. If any value above 39
is written, the register content will be cleared to zero.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–15

ADuCM4050 TMR_RGB Register Descriptions

16-bit Load Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
Load Value

Figure 23-10: TMR_RGB_LOAD Register Diagram
Table 23-9: TMR_RGB_LOAD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

23–16

Load Value.
The Up/Down counter is periodically loaded with this value if periodic mode is selected (TMR_RGB_CTL.MODE=1). TMR_RGB_LOAD.VALUE writes during Up/Down
counter timeout events are delayed until the event has passed.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

PWM0 Control Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IDLESTATE (R/W)
PWM Idle State

MATCH (R/W)
PWM Match Enabled

Figure 23-11: TMR_RGB_PWM0CTL Register Diagram
Table 23-10: TMR_RGB_PWM0CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 IDLESTATE(R/W)
0 MATCH(R/W)

PWM Idle State.
This bit is used to set the PWM Idle state 0: PWM idles low 1: PWM idles high
PWM Match Enabled.
This bit is used to control PWM operational mode 0: PWM in toggle mode 1: PWM
in match mode

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–17

ADuCM4050 TMR_RGB Register Descriptions

PWM0 Match Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
PWM Match Value

Figure 23-12: TMR_RGB_PWM0MATCH Register Diagram
Table 23-11: TMR_RGB_PWM0MATCH Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

23–18

PWM Match Value.
The value is used when the PWM is operating in match mode. The PWM output isasserted when the Up/Down counter is equal to this match value. PWM output isdeasserted again when a timeout event occurs. If the match value is never reached, or
occurs simultaneous to a timeout event, the PWM output remains idle.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

PWM1 Control Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IDLESTATE (R/W)
PWM Idle State

MATCH (R/W)
PWM Match Enabled

Figure 23-13: TMR_RGB_PWM1CTL Register Diagram
Table 23-12: TMR_RGB_PWM1CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 IDLESTATE(R/W)
0 MATCH(R/W)

PWM Idle State.
This bit is used to set the PWM Idle state 0: PWM idles low 1: PWM idles high
PWM Match Enabled.
This bit is used to control PWM operational mode 0: PWM in toggle mode 1: PWM
in match mode

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–19

ADuCM4050 TMR_RGB Register Descriptions

PWM1 Match Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
PWM Match Value

Figure 23-14: TMR_RGB_PWM1MATCH Register Diagram
Table 23-13: TMR_RGB_PWM1MATCH Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

23–20

PWM Match Value.
The value is used when the PWM is operating in match mode. The PWM output isasserted when the Up/Down counter is equal to this match value. PWM output isdeasserted again when a timeout event occurs. If the match value is never reached, or
occurs simultaneous to a timeout event, the PWM output remains idle.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

PWM2 Control Register
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IDLESTATE (R/W)
PWM Idle State

MATCH (R/W)
PWM Match Enabled

Figure 23-15: TMR_RGB_PWM2CTL Register Diagram
Table 23-14: TMR_RGB_PWM2CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
1 IDLESTATE(R/W)
0 MATCH(R/W)

PWM Idle State.
This bit is used to set the PWM Idle state 0: PWM idles low 1: PWM idles high
PWM Match Enabled.
This bit is used to control PWM operational mode 0: PWM in toggle mode 1: PWM
in match mode

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–21

ADuCM4050 TMR_RGB Register Descriptions

PWM2 Match Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R/W)
PWM Match Value

Figure 23-16: TMR_RGB_PWM2MATCH Register Diagram
Table 23-15: TMR_RGB_PWM2MATCH Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE
(R/W)

23–22

PWM Match Value.
The value is used when the PWM is operating in match mode. The PWM output isasserted when the Up/Down counter is equal to this match value. PWM output isdeasserted again when a timeout event occurs. If the match value is never reached, or
occurs simultaneous to a timeout event, the PWM output remains idle.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

Status15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CNTRST (R)Counter Reset Occurring

TIMEOUT (R)Timeout Event Occurred

PDOK (R)
Clear Interrupt Register Synchronization

CAPTURE (R)Capture Event Pending

BUSY (R)Timer Busy

Figure 23-17: TMR_RGB_STAT Register Diagram
Table 23-16: TMR_RGB_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
8 CNTRST(R/NW)
7 PDOK(R/NW)Counter Reset Occurring.
Indicates that the counter is currently being reset due to an event detection. For this towork, TMR_RGB_CTL.RSTEN needs to be set
Clear Interrupt Register Synchronization.
This bit is set automatically when the user sets TMR_RGB_CLRINT.TIMEOUT=1. It
is cleared automatically when the clear interrupt request has crossed clock domains andtaken effect in the timer clock domain
0 The interrupt is cleared in the timer clock domain
1 Clear Timeout Interrupt bit is being updated in the timer clock domain

6 BUSY(R/NW)

Timer Busy.
This bit informs the user that a write to TMR_RGB_CTL is still crossing into the timer
clock domain. This bit should be checked after writing TMR_RGB_CTL and further
writes should be suppressed until this bit is cleared.
0 Timer ready to receive commands to Control Register
1 Timer not ready to receive commands to Control Register

1 CAPTURE(R/NW)

Capture Event Pending.
A capture of the current timer value has occurred.
0 No capture event is pending
1 A capture event is pending

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–23

ADuCM4050 TMR_RGB Register Descriptions

Table 23-16: TMR_RGB_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
0 TIMEOUT(R/NW)

Timeout Event Occurred.
This bit set automatically when the value of the counter reaches zero while counting
down or reaches full scale when counting up. This bit is cleared when
TMR_RGB_CLRINT.TIMEOUT is set by the user.
0 No timeout event has occurred
1 A timeout event has occurred

23–24

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 TMR_RGB Register Descriptions

16-bit Timer Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE (R)
Current Count

Figure 23-18: TMR_RGB_CURCNT Register Diagram
Table 23-17: TMR_RGB_CURCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)

Current Count.
Reflects the current Up/Down counter value. Value delayed two PCLK cycles due toclock synchronizers.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

23–25

Watchdog Timer (WDT)

24 Watchdog Timer (WDT)The watchdog timer is used to recover from an illegal software state. Once enabled by the user code, it requires
periodic servicing to prevent it from forcing a reset or an interrupt to the MCU.

WDT Features
The watchdog timer is clocked by 32 kHz on-chip oscillator (LFOSC). The watchdog is clocked at all times except
during reset, hibernate, shutdown and debug mode. The timer is a 16-bit down counter with a programmable prescaler. The prescaler source is selectable and can be scaled by factors of 1, 16, or 256. A WDT timeout can generatea reset or an interrupt. The WDT_CTL.IRQ bit selects an interrupt instead of a reset; this is intended to be a debug
feature. The interrupt can be cleared by writing 0xCCCC to the WDT_RESTART write-only register.

WDT Functional Description
This section provides information on the function of the WDT used by the ADuCM4050 MCU.

WDT Block Diagram
The figure shows the block diagram of the WDT used by the ADuCM4050 MCU.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

24–1

WDT Operating Modes

timer_wd

16 Bit Load

32 KHzclock

Watchdog Reset
Prescale(1,16, 256)

16 Bit Down
Counter
IRQ

16 BitDown
MMR
ReadableCounter
Count
Value

Figure 24-1: Watchdog Timer Block Diagram

WDT Operating Modes
After a valid reset, the watchdog timer is reset in the hardware as follows:
1. Set WDT_CTL = 0x00E9
2. Set WDT_LOAD = 0x1000
3. Set WDT_CCNT = 0x1000
This configuration enables the watchdog timer with a timeout value of 32 s. However ADI kernel disables thewatchdog timer to allow the user to configure the timer. So while accessing the registers, the user would observe thefollowing values:
1. WDT_CTL = 0x0
2. WDT_LOAD = 0x1000
3. WDT_CCNT = 0x1000
Disabling the timer in the kernel enables the user to utilize the advantage of the write protection feature of thewatchdog timer. When the WDT_CTL.EN bit is set by the user code, the WDT_STAT.LOCKED bit is also set
thereby write-protects WDT_CTL and WDT_LOAD.VALUE (the load value). Only a reset will clear the write protection and WDT_STAT.LOCKED bit to allow reconfiguration of the timer.
If the WDT_CTL register is not modified, the user code can change WDT_LOAD.VALUE at any time. If the
WDT_CTL.EN bit is cleared (prior to any write of the WDT_CTL register), the timer is disabled. Doing so allows
the timer settings to be modified, and the timer can be re-enabled. As soon as the timer is re-enabled by a write to
the WDT_CTL register, the watchdog configuration is locked to prevent any inadvertent modification to the registervalues.
24–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

WDT Operating Modes

If the watchdog timer is set to free-running mode (WDT_CTL.MODE = 0), the watchdog timer value will decrementfrom 0x1000 to zero, wrap around to 0x1000 and continue to decrement.
To achieve a timeout value greater or less than 0x1000 (~32 s with default prescale = 2), periodic mode should be
used (WDT_CTL.MODE = 1), and WDT_LOAD.VALUE and WDT_CTL.PRE written with the values corresponding to the desired timeout period. The maximum timeout is ~8 min (WDT_LOAD.VALUE = 0xFFFF,
WDT_CTL.PRE = 2). When periodic mode is chosen, the timer value will decrement from the
WDT_LOAD.VALUE value to zero, wrap around to WDT_LOAD.VALUE again and continue to decrement.
At any time, WDT_CCNT.VALUE will contain a valid value to be read, synchronized to the APB clock.
When the watchdog timer decrements to 0, a reset or an interrupt is generated. This reset can be prevented by writing the value 0xCCCC to the WDT_RESTART register before the expiration period. A write to WDT_RESTART
causes the watchdog timer to reload with the WDT_LOAD.VALUE value (or 0x1000 if in free-running mode) immediately to begin a new timeout period and start to count again. If any value other than 0xCCCC is written, areset or interrupt is generated.
When the timer is disabled by clearing the WDT_CTL.EN bit, both the internal prescaler and counter will becleared. The counter will be reloaded with the value corresponding to the WDT_CTL.MODE bit setting once reenabled.
The WDT setup is re-initialized/reset only after a POR or system reset.
The watchdog reset assertion duration will be one PCLK period when generated by a wrong WDT_RESTART access; the reset due to timeout will be a full 32 kHz clock period.

Watchdog Synchronization
The watchdog timer has three status bits, WDT_STAT.COUNTING, WDT_STAT.LOADING, and
WDT_STAT.CLRIRQ , which indicate that synchronization between fast clock and slow clock domains is in progress for the WDT_CTL, WDT_LOAD.VALUE and WDT_RESTART registers respectively.
Writes to the WDT_CTL or WDT_LOAD.VALUE register must not occur while the corresponding synchronization
bit is set. However, consecutive access to the WDT_RESTART register with 0xCCCC value is permitted. The
WDT_RESTART access with value 0xCCCC that occurs during the synchronization of previous access is ignored.

Watchdog Power Modes Behavior
The watchdog timer is automatically disabled in Hibernate and Shutdown modes. None of the watchdog timer registers are retained in hibernate mode. The user needs to reprogram the WDT counter after exiting from hibernate
and shutdown modes. Otherwise, the WDT timeout value used will be the default value of around 32 s.

ADuCM4050 WDT Register Descriptions
Watchdog Timer (WDT) contains the following registers.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

24–3

ADuCM4050 WDT Register Descriptions

Table 24-1: ADuCM4050 WDT Register List
Name

Description

WDT_CCNT

Current Count Value

WDT_CTL

Control

WDT_LOAD

Load Value

WDT_RESTART

Clear Interrupt

WDT_STAT

Status

24–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 WDT Register Descriptions

Current Count Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

VALUE (R)
Current Count Value

Figure 24-2: WDT_CCNT Register Diagram
Table 24-2: WDT_CCNT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE(R/NW)

Current Count Value.
This register is synchronized to the APB clock.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

24–5

ADuCM4050 WDT Register Descriptions

Control
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

1

1

1

0

1

0

0

1

0

0

0

0

0

0

SPARE (R/W)
Unused Spare Bit

IRQ (R/W)
Timer Interrupt

MODE (R/W)
Timer Mode

PRE (R/W)
Prescaler

EN (R/W)
Timer Enable

Figure 24-3: WDT_CTL Register Diagram
Table 24-3: WDT_CTL Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
7 SPARE(R/W)
6 MODE(R/W)

Unused Spare Bit.
Note: ADI kernel writes '0x0' to this bit field.
Timer Mode.
Set by user to operate in periodic mode. Cleared by user to operate in free running
mode. In free running mode, it wraps around at 0x1000.
Note: ADI kernel writes '0x0' to this bit field (default).
0 Free running mode
1 Periodic mode

5 EN
(R/W)

Timer Enable.
Set by user to enable the timer. Cleared by user to disable the timer. Once set, thewatchdog cannot be disabled without a system reset. This prevents software inadvertently disabling the watchdog.
Note: ADI kernel writes '0x0' to this bit field (default).
0 WDT not enabled
1 WDT enabled

3:2 PRE(R/W)

Prescaler.
Note: ADI kernel writes '0x0' to these bit fields (default).
0 Source clock/1
1 Source clock/16
2 Source clock/256
3 Reserved

24–6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 WDT Register Descriptions

Table 24-3: WDT_CTL Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 IRQ
(R/W)

Timer Interrupt.
Set by user to generate an interrupt when the timer times out. This feature is provided
for debug purposes and is only available when PCLK is active.
Cleared by user to generate a reset on a time out (default).
0 WDT asserts reset when timed out
1 WDT generates interrupt when timed out

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

24–7

ADuCM4050 WDT Register Descriptions

Load Value
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

VALUE (R/W)
Load Value

Figure 24-4: WDT_LOAD Register Diagram
Table 24-4: WDT_LOAD Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 VALUE

Load Value.

(R/W)

24–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 WDT Register Descriptions

Clear Interrupt
15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CLRWORD (W)Clear Watchdog

Figure 24-5: WDT_RESTART Register Diagram
Table 24-5: WDT_RESTART Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
15:0 CLRWORD(RX/W)

Clear Watchdog.
User writes 0xCCCC to reset, reload, restart WDT or clear IRQ. A write of any othervalue causes a watchdog reset/IRQ. Write only, reads 0.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

24–9

ADuCM4050 WDT Register Descriptions

Status15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

LOCKED (R)Lock Status Bit

IRQ (R)
WDT Interrupt

COUNTING (R)Control Register Write Sync in Progress

CLRIRQ (R)
Clear Interrupt Register Write Sync
in Progress

LOADING (R)
Load Register Write Sync in Progress

Figure 24-6: WDT_STAT Register Diagram
Table 24-6: WDT_STAT Register Fields
Bit No.

Bit Name

Description/Enumeration(Access)
4 LOCKED(R/NW)

Lock Status Bit.
Set automatically in hardware if WDT_CTL.EN has been set by user code. Cleared bydefault and until user code sets WDT_CTL.EN.
0 Enable bit is not set by software
1 Enable bit is set by software. WDT is locked

3 COUNTING(R/NW)

Control Register Write Sync in Progress.
Software should not write to the WDT_CTL register when this bit is set to avoid synchronization issues.
0 APB and WDT clock domain WDT_CTL values match
1 APB WDT_CTL register values are being synchronized
to WDT clock domain.

2 LOADING(R/NW)

Load Register Write Sync in Progress.
Software should not write to the WDT_LOAD register when this bit is set to avoid synchronization issues.
0 APB and WDT clock domains WDT_LOAD values
match.
1 APB WDT_LOAD value is being synchronized to WDT
clock domain.

24–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 WDT Register Descriptions

Table 24-6: WDT_STAT Register Fields (Continued)
Bit No.

Bit Name

Description/Enumeration(Access)
1 CLRIRQ(R/NW)

Clear Interrupt Register Write Sync in Progress.
Software should not write to the RESTART register when this bit is set to avoid synchronisation issues.
0 APB WDT_RESTART write sync not done
1 APB WDT_RESTART write is being synced to WDT
clock domain. WDT will be restarted (if 0xCCCC waswritten) once sync is complete.

0 IRQ(R/NW)WDT Interrupt.
Write WDT_RESTART register with value 0xCCCC to clear this bit.
0 WDT interrupt not pending.
1 WDT interrupt pending.

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

24–11

ADuCM4050 Register List

25 ADuCM4050 Register List

This appendix lists Memory-Mapped Register address and register names. The modules are presented in alphabeticalorder.
Table 25-1: ADuCM4050 ADC0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40007000

ADC0_CFG

ADC0 ADC Configuration

0x00000000

0x40007004

ADC0_PWRUP

ADC0 ADC Power-up Time

0x0000041C

0x40007008

ADC0_CAL_WORD

ADC0 Calibration Word

0x00000040

0x4000700C

ADC0_CNV_CFG

ADC0 ADC Conversion Configuration

0x00000000

0x40007010

ADC0_CNV_TIME

ADC0 ADC Conversion Time

0x00000000

0x40007014

ADC0_AVG_CFG

ADC0 Averaging Configuration

0x00004008

0x40007020

ADC0_IRQ_EN

ADC0 Interrupt Enable

0x00000000

0x40007024

ADC0_STAT

ADC0 ADC Status

0x00000000

0x40007028

ADC0_OVF

ADC0 Overflow of Output Registers

0x00000000

0x4000702C

ADC0_ALERTADC0 Alert Indication

0x00000000

0x40007030

ADC0_CH0_OUT

ADC0 Conversion Result Channel 00x00000000

0x40007034

ADC0_CH1_OUT

ADC0 Conversion Result Channel 10x00000000

0x40007038

ADC0_CH2_OUT

ADC0 Conversion Result Channel 20x00000000

0x4000703C

ADC0_CH3_OUT

ADC0 Conversion Result Channel 30x00000000

0x40007040

ADC0_CH4_OUT

ADC0 Conversion Result Channel 40x00000000

0x40007044

ADC0_CH5_OUT

ADC0 Conversion Result Channel 50x00000000

0x40007048

ADC0_CH6_OUT

ADC0 Conversion Result Channel 60x00000000

0x4000704C

ADC0_CH7_OUT

ADC0 Conversion Result Channel 70x00000000

0x40007050

ADC0_BAT_OUT

ADC0 Battery Monitoring Result

0x00000000

0x40007054

ADC0_TMP_OUT

ADC0 Temperature Result

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–1

ADuCM4050 Register List

Table 25-1: ADuCM4050 ADC0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40007058

ADC0_TMP2_OUT

ADC0 Temperature Result 20x00000000

0x4000705C

ADC0_DMA_OUT

ADC0 DMA Output Register

0x00000000

0x40007060

ADC0_LIM0_LO

ADC0 Channel 0 Low Limit

0x00000000

0x40007064

ADC0_LIM0_HI

ADC0 Channel 0 High Limit

0x00000FFF

0x40007068

ADC0_HYS0

ADC0 Channel 0 Hysteresis

0x00000000

0x40007070

ADC0_LIM1_LO

ADC0 Channel 1 Low Limit

0x00000000

0x40007074

ADC0_LIM1_HI

ADC0 Channel 1 High Limit

0x00000FFF

0x40007078

ADC0_HYS1

ADC0 Channel 1 Hysteresis

0x00000000

0x40007080

ADC0_LIM2_LO

ADC0 Channel 2 Low Limit

0x00000000

0x40007084

ADC0_LIM2_HI

ADC0 Channel 2 High Limit

0x00000FFF

0x40007088

ADC0_HYS2

ADC0 Channel 2 Hysteresis

0x00000000

0x40007090

ADC0_LIM3_LO

ADC0 Channel 3 Low Limit

0x00000000

0x40007094

ADC0_LIM3_HI

ADC0 Channel 3 High Limit

0x00000FFF

0x40007098

ADC0_HYS3

ADC0 Channel 3 Hysteresis

0x00000000

0x400070C0

ADC0_CFG1

ADC0 Reference Buffer Low Power Mode

0x00000400

Table 25-2: ADuCM4050 BEEP0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40005C00

BEEP0_CFG

BEEP0 Beeper Configuration

0x00000000

0x40005C04

BEEP0_STAT

BEEP0 Beeper Status

0x00000000

0x40005C08

BEEP0_TONEABEEP0 Tone A Data

0x00000001

0x40005C0C

BEEP0_TONEBBEEP0 Tone B Data

0x00000001

Table 25-3: ADuCM4050 BUSM0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x4004C800

BUSM0_ARBIT0

BUSM0 Arbitration Priority Configuration for FLASHand SRAM00x00240024

0x4004C804

BUSM0_ARBIT1

BUSM0 Arbitration Priority Configuration for SRAM1

0x00240024

0x4004C808

BUSM0_ARBIT2

BUSM0 Arbitration Priority Configuration for APB32
and APB16

0x00240024

25–2

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-3: ADuCM4050 BUSM0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x4004C80C

BUSM0_ARBIT3

BUSM0 Arbitration Priority Configuration for APB16
priority for core and for DMA1

0x00010002

0x4004C814

BUSM0_ARBIT4

BUSM0 Arbitration Priority Configuration for SRAM1
and SIP

0x00000024

Table 25-4: ADuCM4050 CLKG0_OSC MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x4004C10C

CLKG0_OSC_KEY

CLKG0_OSC Key Protection for OSCCTRL

0x00000000

0x4004C110

CLKG0_OSC_CTL

CLKG0_OSC Oscillator Control

0x00060002

Table 25-5: ADuCM4050 CLKG0_CLK MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x4004C300

CLKG0_CLK_CTL0

CLKG0_CLK Misc Clock Settings

0x00000078

0x4004C304

CLKG0_CLK_CTL1

CLKG0_CLK Clock Dividers

0x00100404

0x4004C308

CLKG0_CLK_CTL2

CLKG0_CLK HF Oscillator Divided Clock Select

0x00000000

0x4004C30C

CLKG0_CLK_CTL3

CLKG0_CLK System PLL

0x0000681A

0x4004C314

CLKG0_CLK_CTL5

CLKG0_CLK User Clock Gating Control

0x0000005F

0x4004C318

CLKG0_CLK_STAT0

CLKG0_CLK Clocking Status

0x00000000

Table 25-6: ADuCM4050 CRC0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40040000

CRC0_CTL

CRC0 CRC Control

0x10000000

0x40040004

CRC0_IPDATA

CRC0 Input Data Word

0x00000000

0x40040008

CRC0_RESULT

CRC0 CRC Result

0x00000000

0x4004000C

CRC0_POLY

CRC0 Programmable CRC Polynomial

0x04C11DB7

0x40040010

CRC0_IPBITS[n]CRC0 Input Data Bits

0x00000000

0x40040010

CRC0_IPBYTE

CRC0 Input Data Byte

0x00000000

0x40040011

CRC0_IPBITS[n]CRC0 Input Data Bits

0x00000000

0x40040012

CRC0_IPBITS[n]CRC0 Input Data Bits

0x00000000

0x40040013

CRC0_IPBITS[n]CRC0 Input Data Bits

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–3

ADuCM4050 Register List

Table 25-6: ADuCM4050 CRC0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40040014

CRC0_IPBITS[n]CRC0 Input Data Bits

0x00000000

0x40040015

CRC0_IPBITS[n]CRC0 Input Data Bits

0x00000000

0x40040016

CRC0_IPBITS[n]CRC0 Input Data Bits

0x00000000

0x40040017

CRC0_IPBITS[n]CRC0 Input Data Bits

0x00000000

Table 25-7: ADuCM4050 CRYPT0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40044000

CRYPT0_CFG

CRYPT0 Configuration Register

0x20000000

0x40044004

CRYPT0_DATALENCRYPT0 Payload Data Length

0x00000000

0x40044008

CRYPT0_PREFIXLENCRYPT0 Authentication Data Length

0x00000000

0x4004400C

CRYPT0_INTENCRYPT0 Interrupt Enable Register

0x00000000

0x40044010

CRYPT0_STAT

CRYPT0 Status Register

0x00000001

0x40044014

CRYPT0_INBUFCRYPT0 Input Buffer

0x00000000

0x40044018

CRYPT0_OUTBUF

CRYPT0 Output Buffer

0x00000000

0x4004401C

CRYPT0_NONCE0

CRYPT0 Nonce Bits [31:0]

0x00000000

0x40044020

CRYPT0_NONCE1

CRYPT0 Nonce Bits [63:32]

0x00000000

0x40044024

CRYPT0_NONCE2

CRYPT0 Nonce Bits [95:64]

0x00000000

0x40044028

CRYPT0_NONCE3

CRYPT0 Nonce Bits [127:96]

0x00000000

0x4004402C

CRYPT0_AESKEY0

CRYPT0 AES Key Bits [31:0]

0x00000000

0x40044030

CRYPT0_AESKEY1

CRYPT0 AES Key Bits [63:32]

0x00000000

0x40044034

CRYPT0_AESKEY2CRYPT0 AES Key Bits [95:64]

0x00000000

0x40044038

CRYPT0_AESKEY3CRYPT0 AES Key Bits [127:96]

0x00000000

0x4004403C

CRYPT0_AESKEY4CRYPT0 AES Key Bits [159:128]

0x00000000

0x40044040

CRYPT0_AESKEY5CRYPT0 AES Key Bits [191:160]

0x00000000

0x40044044

CRYPT0_AESKEY6CRYPT0 AES Key Bits [223:192]

0x00000000

0x40044048

CRYPT0_AESKEY7CRYPT0 AES Key Bits [255:224]

0x00000000

0x4004404C

CRYPT0_CNTRINIT

CRYPT0 Counter Initialization Vector

0x00000000

0x40044050

CRYPT0_SHAH0CRYPT0 SHA Bits [31:0]

0x6A09E667

0x40044054

CRYPT0_SHAH1CRYPT0 SHA Bits [63:32]

0xBB67AE85

0x40044058

CRYPT0_SHAH2CRYPT0 SHA Bits [95:64]

0x3C6EF372

25–4

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-7: ADuCM4050 CRYPT0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x4004405C

CRYPT0_SHAH3CRYPT0 SHA Bits [127:96]

0xA54FF53A

0x40044060

CRYPT0_SHAH4CRYPT0 SHA Bits [159:128]

0x510E527F

0x40044064

CRYPT0_SHAH5CRYPT0 SHA Bits [191:160]

0x9B05688C

0x40044068

CRYPT0_SHAH6CRYPT0 SHA Bits [223:192]

0x1F83D9AB

0x4004406C

CRYPT0_SHAH7CRYPT0 SHA Bits [255:224]

0x5BE0CD19

0x40044070

CRYPT0_SHA_LAST_WOR CRYPT0 SHA Last Word and Valid Bits Information
D

0x00000000

0x40044074

CRYPT0_CCM_NUM_VAL- CRYPT0 NUM_VALID_BYTES
ID_BYTES

0x00000000

0x40044078

CRYPT0_PRKSTORCFG

CRYPT0 PRKSTOR Configuration

0x00000000

0x40044080

CRYPT0_KUW0CRYPT0 Key Wrap Unwrap Register 00x00000000

0x40044084

CRYPT0_KUW1CRYPT0 Key Wrap Unwrap Register 10x00000000

0x40044088

CRYPT0_KUW2CRYPT0 Key Wrap Unwrap Register 20x00000000

0x4004408C

CRYPT0_KUW3

CRYPT0 Key Wrap Unwrap Register 30x00000000

0x40044090

CRYPT0_KUW4CRYPT0 Key Wrap Unwrap Register 40x00000000

0x40044094

CRYPT0_KUW5

CRYPT0 Key Wrap Unwrap Register 50x00000000

0x40044098

CRYPT0_KUW6

CRYPT0 Key Wrap Unwrap Register 60x00000000

0x4004409C

CRYPT0_KUW7

CRYPT0 Key Wrap Unwrap Register 70x00000000

0x400440A0

CRYPT0_KUW8CRYPT0 Key Wrap Unwrap Register 80x00000000

0x400440A4CRYPT0_KUW9CRYPT0 Key Wrap Unwrap Register 90x00000000

0x400440A8CRYPT0_KUW10CRYPT0 Key Wrap Unwrap Register 100x00000000

0x400440AC

CRYPT0_KUW11CRYPT0 Key Wrap Unwrap Register 110x00000000

0x400440B0

CRYPT0_KUW12CRYPT0 Key Wrap Unwrap Register 120x00000000

0x400440B4

CRYPT0_KUW13CRYPT0 Key Wrap Unwrap Register 130x00000000

0x400440B8CRYPT0_KUW14CRYPT0 Key Wrap Unwrap Register 140x00000000

0x400440BC

CRYPT0_KUW15CRYPT0 Key Wrap Unwrap Register 150x00000000

0x400440C0

CRYPT0_KUWVALSTR1

CRYPT0 Key Wrap Unwrap Validation String [63:32]

0xA6A6A6A60x400440C4CRYPT0_KUWVALSTR2

CRYPT0 Key Wrap Unwrap Validation String [31:0]

0xA6A6A6A6

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–5

ADuCM4050 Register List

Table 25-8: ADuCM4050 DMA0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40010000

DMA0_STATDMA0 DMA Status

0x001A0000

0x40010004

DMA0_CFG

DMA0 DMA Configuration

0x00000000

0x40010008

DMA0_PDBPTR

DMA0 DMA Channel Primary Control Database Pointer 0x00000000

0x4001000C

DMA0_ADBPTR

DMA0 DMA Channel Alternate Control Database Point- 0x00000200
er

0x40010014

DMA0_SWREQDMA0 DMA Channel Software Request

0x00000000

0x40010020

DMA0_RMSK_SET

DMA0 DMA Channel Request Mask Set

0x00000000

0x40010024

DMA0_RMSK_CLR

DMA0 DMA Channel Request Mask Clear

0x00000000

0x40010028

DMA0_EN_SET

DMA0 DMA Channel Enable Set

0x00000000

0x4001002C

DMA0_EN_CLR

DMA0 DMA Channel Enable Clear

0x00000000

0x40010030

DMA0_ALT_SET

DMA0 DMA Channel Primary Alternate Set

0x00000000

0x40010034

DMA0_ALT_CLR

DMA0 DMA Channel Primary Alternate Clear

0x00000000

0x40010038

DMA0_PRI_SETDMA0 DMA Channel Priority Set

0x00000000

0x4001003C

DMA0_PRI_CLR

DMA0 DMA Channel Priority Clear

0x00000000

0x40010048

DMA0_ERRCHNL_CLR

DMA0 DMA per Channel Error Clear

0x00000000

0x4001004C

DMA0_ERR_CLR

DMA0 DMA Bus Error Clear

0x00000000

0x40010050

DMA0_INVALIDDESC_CLR

DMA0 DMA per Channel Invalid Descriptor Clear

0x00000000

0x40010800

DMA0_BS_SET

DMA0 DMA Channel Bytes Swap Enable Set

0x00000000

0x40010804

DMA0_BS_CLR

DMA0 DMA Channel Bytes Swap Enable Clear

0x00000000

0x40010810

DMA0_SRCADDR_SET

DMA0 DMA Channel Source Address Decrement Enable 0x00000000
Set

0x40010814

DMA0_SRCADDR_CLR

DMA0 DMA Channel Source Address Decrement Enable 0x00000000
Clear

0x40010818

DMA0_DSTADDR_SET

DMA0 DMA Channel Destination Address Decrement
Enable Set

0x00000000

0x4001081C

DMA0_DSTADDR_CLR

DMA0 DMA Channel Destination Address Decrement
Enable Clear

0x00000000

0x40010FE0

DMA0_REVID

DMA0 DMA Controller Revision ID

0x00000002

Table 25-9: ADuCM4050 XINT0 MMR Register Addresses
Memory Mapped Address

25–6

Register Name

Description

Reset ValueXINT0_CFG0

XINT0 External Interrupt Configuration

0x00200000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-9: ADuCM4050 XINT0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x4004C084

XINT0_EXT_STAT

XINT0 External Wakeup Interrupt Status

0x00000000

0x4004C090

XINT0_CLR

XINT0 External Interrupt Clear

0x00000000

0x4004C094

XINT0_NMICLR

XINT0 Non-maskable Interrupt Clear

0x00000000

0x4004C080

Table 25-10: ADuCM4050 FLCC0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40018000

FLCC0_STAT

FLCC0 Status

0x00000000

0x40018004

FLCC0_IEN

FLCC0 Interrupt Enable

0x00000060

0x40018008

FLCC0_CMD

FLCC0 Command

0x00000000

0x4001800C

FLCC0_KH_ADDR

FLCC0 Write Address

0x00000000

0x40018010

FLCC0_KH_DATA0

FLCC0 Write Lower Data

0xFFFFFFFF

0x40018014

FLCC0_KH_DATA1

FLCC0 Write Upper Data

0xFFFFFFFF

0x40018018

FLCC0_PAGE_ADDR0

FLCC0 Lower Page Address

0x00000000

0x4001801C

FLCC0_PAGE_ADDR1

FLCC0 Upper Page Address

0x00000000

0x40018020

FLCC0_KEY

FLCC0 Key

0x00000000

0x40018024

FLCC0_WR_ABORT_ADD
R

FLCC0 Write Abort Address

0x00000000

0x40018028

FLCC0_WRPROTFLCC0 Write Protection

0xFFFFFFFF

0x4001802C

FLCC0_SIGNATURE

FLCC0 Signature

0x00000000

0x40018030

FLCC0_UCFG

FLCC0 User Configuration

0x00000000

0x40018034

FLCC0_TIME_PARAM0

FLCC0 Time Parameter 0

0xB8954950

0x40018038

FLCC0_TIME_PARAM1

FLCC0 Time Parameter 10x00000004

0x4001803C

FLCC0_ABORT_EN_LO

FLCC0 IRQ Abort Enable (Lower Bits)

0x00000000

0x40018040

FLCC0_ABORT_EN_HI

FLCC0 IRQ Abort Enable (Upper Bits)

0x00000000

0x40018048

FLCC0_ECC_ADDR

FLCC0 ECC Status (Address)

0x00000000

0x40018050

FLCC0_POR_SEC

FLCC0 Flash Security

0x00000000

0x40018054

FLCC0_VOL_CFG

FLCC0 Volatile Flash Configuration

0x00000001

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–7

ADuCM4050 Register List

Table 25-11: ADuCM4050 FLCC0_CACHE MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40018058

FLCC0_CACHE_STAT

FLCC0_CACHE Cache Status Register

0x00000000

0x4001805C

FLCC0_CACHE_SETUP

FLCC0_CACHE Cache Setup Register

0x00000000

0x40018060

FLCC0_CACHE_KEY

FLCC0_CACHE Cache Key Register

0x00000000

Table 25-12: ADuCM4050 GPIO0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40020000

GPIO0_CFG

GPIO0 Port Configuration

0x00000000

0x40020004

GPIO0_OEN

GPIO0 Port Output Enable

0x00000000

0x40020008

GPIO0_PE

GPIO0 Port Output Pull-up/Pull-down Enable

0x000000C00x4002000C

GPIO0_IEN

GPIO0 Port Input Path Enable

0x00000000

0x40020010

GPIO0_IN

GPIO0 Port Registered Data Input

0x00000000

0x40020014

GPIO0_OUT

GPIO0 Port Data Output

0x00000000

0x40020018

GPIO0_SETGPIO0 Port Data Out Set

0x00000000

0x4002001C

GPIO0_CLR

GPIO0 Port Data Out Clear

0x00000000

0x40020020

GPIO0_TGLGPIO0 Port Pin Toggle

0x00000000

0x40020024

GPIO0_POL

GPIO0 Port Interrupt Polarity

0x00000000

0x40020028

GPIO0_IENA

GPIO0 Port Interrupt A Enable

0x00000000

0x4002002C

GPIO0_IENB

GPIO0 Port Interrupt B Enable

0x00000000

0x40020030

GPIO0_INTGPIO0 Port Interrupt Status

0x00000000

0x40020034

GPIO0_DS

GPIO0 Port Drive Strength Select

0x00000000

Table 25-13: ADuCM4050 GPIO1 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40020040

GPIO1_CFG

GPIO1 Port Configuration

0x00000000

0x40020044

GPIO1_OEN

GPIO1 Port Output Enable

0x00000000

0x40020048

GPIO1_PE

GPIO1 Port Output Pull-up/Pull-down Enable

0x00000002

0x4002004C

GPIO1_IEN

GPIO1 Port Input Path Enable

0x00000000

0x40020050

GPIO1_IN

GPIO1 Port Registered Data Input

0x00000000

0x40020054

GPIO1_OUTGPIO1 Port Data Output

0x00000000

0x40020058

GPIO1_SETGPIO1 Port Data Out Set

0x00000000

25–8

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-13: ADuCM4050 GPIO1 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x4002005C

GPIO1_CLR

GPIO1 Port Data Out Clear

0x00000000

0x40020060

GPIO1_TGLGPIO1 Port Pin Toggle

0x00000000

0x40020064

GPIO1_POLGPIO1 Port Interrupt Polarity

0x00000000

0x40020068

GPIO1_IENA

GPIO1 Port Interrupt A Enable

0x00000000

0x4002006C

GPIO1_IENB

GPIO1 Port Interrupt B Enable

0x00000000

0x40020070

GPIO1_INTGPIO1 Port Interrupt Status

0x00000000

0x40020074

GPIO1_DS

GPIO1 Port Drive Strength Select

0x00000000

Table 25-14: ADuCM4050 GPIO2 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40020080

GPIO2_CFG

GPIO2 Port Configuration

0x00000000

0x40020084

GPIO2_OEN

GPIO2 Port Output Enable

0x00000000

0x40020088

GPIO2_PE

GPIO2 Port Output Pull-up/Pull-down Enable

0x00000000

0x4002008C

GPIO2_IEN

GPIO2 Port Input Path Enable

0x00000000

0x40020090

GPIO2_IN

GPIO2 Port Registered Data Input

0x00000000

0x40020094

GPIO2_OUTGPIO2 Port Data Output

0x00000000

0x40020098

GPIO2_SETGPIO2 Port Data Out Set

0x00000000

0x4002009C

GPIO2_CLR

GPIO2 Port Data Out Clear

0x00000000

0x400200A0

GPIO2_TGLGPIO2 Port Pin Toggle

0x00000000

0x400200A4

GPIO2_POLGPIO2 Port Interrupt Polarity

0x00000000

0x400200A8

GPIO2_IENA

GPIO2 Port Interrupt A Enable

0x00000000

0x400200AC

GPIO2_IENB

GPIO2 Port Interrupt B Enable

0x00000000

0x400200B0

GPIO2_INTGPIO2 Port Interrupt Status

0x00000000

0x400200B4

GPIO2_DS

GPIO2 Port Drive Strength Select

0x00000000

Table 25-15: ADuCM4050 GPIO3 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x400200C0

GPIO3_CFG

GPIO3 Port Configuration

0x00000000

0x400200C4

GPIO3_OEN

GPIO3 Port Output Enable

0x00000000

0x400200C8

GPIO3_PE

GPIO3 Port Output Pull-up/Pull-down Enable

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–9ADuCM4050 Register List

Table 25-15: ADuCM4050 GPIO3 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x400200CC

GPIO3_IEN

GPIO3 Port Input Path Enable

0x00000000

0x400200D0

GPIO3_IN

GPIO3 Port Registered Data Input

0x00000000

0x400200D4

GPIO3_OUTGPIO3 Port Data Output

0x00000000

0x400200D8

GPIO3_SETGPIO3 Port Data Out Set

0x00000000

0x400200DC

GPIO3_CLR

GPIO3 Port Data Out Clear

0x00000000

0x400200E0

GPIO3_TGLGPIO3 Port Pin Toggle

0x00000000

0x400200E4

GPIO3_POLGPIO3 Port Interrupt Polarity

0x00000000

0x400200E8

GPIO3_IENA

GPIO3 Port Interrupt A Enable

0x00000000

0x400200EC

GPIO3_IENB

GPIO3 Port Interrupt B Enable

0x00000000

0x400200F0

GPIO3_INTGPIO3 Port Interrupt Status

0x00000000

0x400200F4

GPIO3_DS

GPIO3 Port Drive Strength Select

0x00000000

Table 25-16: ADuCM4050 TMR0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40000000

TMR0_LOAD

TMR0 16-bit Load Value

0x00000000

0x40000004

TMR0_CURCNT

TMR0 16-bit Timer Value

0x00000000

0x40000008

TMR0_CTL

TMR0 Control

0x0000000A

0x4000000C

TMR0_CLRINT

TMR0 Clear Interrupt

0x00000000

0x40000010

TMR0_CAPTURE

TMR0 Capture

0x00000000

0x40000014

TMR0_ALOAD

TMR0 16-bit Load Value, Asynchronous

0x00000000

0x40000018

TMR0_ACURCNT

TMR0 16-bit Timer Value, Asynchronous

0x00000000

0x4000001C

TMR0_STAT

TMR0 Status

0x00000000

0x40000020

TMR0_PWMCTL

TMR0 PWM Control Register

0x00000000

0x40000024

TMR0_PWMMATCH

TMR0 PWM Match Value

0x00000000

0x40000028

TMR0_EVENTSELECT

TMR0 Timer Event Selection Register

0x00000000

Table 25-17: ADuCM4050 TMR1 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40000400

TMR1_LOAD

TMR1 16-bit Load Value

0x00000000

0x40000404

TMR1_CURCNT

TMR1 16-bit Timer Value

0x00000000

25–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-17: ADuCM4050 TMR1 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40000408

TMR1_CTL

TMR1 Control

0x0000000A

0x4000040C

TMR1_CLRINT

TMR1 Clear Interrupt

0x00000000

0x40000410

TMR1_CAPTURE

TMR1 Capture

0x00000000

0x40000414

TMR1_ALOAD

TMR1 16-bit Load Value, Asynchronous

0x00000000

0x40000418

TMR1_ACURCNT

TMR1 16-bit Timer Value, Asynchronous

0x00000000

0x4000041C

TMR1_STAT

TMR1 Status

0x00000000

0x40000420

TMR1_PWMCTL

TMR1 PWM Control Register

0x00000000

0x40000424

TMR1_PWMMATCH

TMR1 PWM Match Value

0x00000000

0x40000428

TMR1_EVENTSELECT

TMR1 Timer Event Selection Register

0x00000000

Table 25-18: ADuCM4050 TMR2 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40000800

TMR2_LOAD

TMR2 16-bit Load Value

0x00000000

0x40000804

TMR2_CURCNTTMR2 16-bit Timer Value

0x00000000

0x40000808

TMR2_CTL

TMR2 Control

0x0000000A

0x4000080C

TMR2_CLRINT

TMR2 Clear Interrupt

0x00000000

0x40000810

TMR2_CAPTURE

TMR2 Capture

0x00000000

0x40000814

TMR2_ALOAD

TMR2 16-bit Load Value, Asynchronous

0x00000000

0x40000818

TMR2_ACURCNTTMR2 16-bit Timer Value, Asynchronous

0x00000000

0x4000081C

TMR2_STAT

TMR2 Status

0x00000000

0x40000820

TMR2_PWMCTL

TMR2 PWM Control Register

0x00000000

0x40000824

TMR2_PWMMATCH

TMR2 PWM Match Value

0x00000000

0x40000828

TMR2_EVENTSELECT

TMR2 Timer Event Selection Register

0x00000000

Table 25-19: ADuCM4050 I2C0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40003000

I2C0_MCTL

I2C0 Master Control

0x00000000

0x40003004

I2C0_MSTAT

I2C0 Master Status

0x00006000

0x40003008

I2C0_MRX

I2C0 Master Receive Data

0x00000000

0x4000300C

I2C0_MTX

I2C0 Master Transmit Data

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–11

ADuCM4050 Register List

Table 25-19: ADuCM4050 I2C0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40003010

I2C0_MRXCNT

I2C0 Master Receive Data Count

0x00000000

0x40003014

I2C0_MCRXCNT

I2C0 Master Current Receive Data Count

0x00000000

0x40003018

I2C0_ADDR1

I2C0 Master Address Byte 10x00000000

0x4000301C

I2C0_ADDR2

I2C0 Master Address Byte 20x00000000

0x40003020

I2C0_BYT

I2C0 Start Byte

0x00000000

0x40003024

I2C0_DIV

I2C0 Serial Clock Period Divisor

0x00001F1F

0x40003028

I2C0_SCTL

I2C0 Slave Control

0x00000000

0x4000302C

I2C0_SSTAT

I2C0 Slave I2C Status/Error/IRQ

0x00000001

0x40003030

I2C0_SRX

I2C0 Slave Receive

0x00000000

0x40003034

I2C0_STX

I2C0 Slave Transmit

0x00000000

0x40003038

I2C0_ALTI2C0 Hardware General Call ID

0x00000000

0x4000303C

I2C0_ID0

I2C0 First Slave Address Device ID

0x00000000

0x40003040

I2C0_ID1

I2C0 Second Slave Address Device ID

0x00000000

0x40003044

I2C0_ID2

I2C0 Third Slave Address Device ID

0x00000000

0x40003048

I2C0_ID3

I2C0 Fourth Slave Address Device ID

0x00000000

0x4000304C

I2C0_STAT

I2C0 Master and Slave FIFO Status

0x00000000

0x40003050

I2C0_SHCTL

I2C0 Shared Control

0x00000000

0x40003054

I2C0_TCTL

I2C0 Timing Control Register

0x00000005

0x40003058

I2C0_ASTRETCH_SCL

I2C0 Automatic Stretch SCL

0x00000000

Table 25-20: ADuCM4050 NVIC0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0xE000E004

NVIC0_INTNUM

NVIC0 Interrupt Control Type

0x00000000

0xE000E010

NVIC0_STKSTA

NVIC0 Systick Control and Status

0x00000000

0xE000E014

NVIC0_STKLD

NVIC0 Systick Reload Value

0x00000000

0xE000E018

NVIC0_STKVAL

NVIC0 Systick Current Value

0x00000000

0xE000E01C

NVIC0_STKCAL

NVIC0 Systick Calibration Value

0x00000000

0xE000E100

NVIC0_INTSETE0

NVIC0 IRQ0..31 Set_Enable

0x00000000

0xE000E104

NVIC0_INTSETE1

NVIC0 IRQ32..63 Set_Enable

0x00000000

0xE000E108

NVIC0_INTSETE2

NVIC0 IRQ64..95 Set_Enable

0x00000000

25–12

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-20: ADuCM4050 NVIC0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0xE000E180

NVIC0_INTCLRE0

NVIC0 IRQ0..31 Clear_Enable

0x00000000

0xE000E184

NVIC0_INTCLRE1

NVIC0 IRQ32..63 Clear_Enable

0x00000000

0xE000E188

NVIC0_INTCLRE2

NVIC0 IRQ64..95 Clear_Enable

0x00000000

0xE000E200

NVIC0_INTSETP0

NVIC0 IRQ0..31 Set_Pending

0x00000000

0xE000E204

NVIC0_INTSETP1

NVIC0 IRQ32..63 Set_Pending

0x00000000

0xE000E208

NVIC0_INTSETP2

NVIC0 IRQ64..95 Set_Pending

0x00000000

0xE000E280

NVIC0_INTCLRP0

NVIC0 IRQ0..31 Clear_Pending

0x00000000

0xE000E284

NVIC0_INTCLRP1

NVIC0 IRQ32..63 Clear_Pending

0x00000000

0xE000E288

NVIC0_INTCLRP2

NVIC0 IRQ64..95 Clear_Pending

0x00000000

0xE000E300

NVIC0_INTACT0

NVIC0 IRQ0..31 Active Bit

0x00000000

0xE000E304

NVIC0_INTACT1

NVIC0 IRQ32..63 Active Bit

0x00000000

0xE000E308

NVIC0_INTACT2

NVIC0 IRQ64..95 Active Bit

0x00000000

0xE000E400

NVIC0_INTPRI0

NVIC0 IRQ0..3 Priority

0x00000000

0xE000E404

NVIC0_INTPRI1

NVIC0 IRQ4..7 Priority

0x00000000

0xE000E408

NVIC0_INTPRI2

NVIC0 IRQ8..11 Priority

0x00000000

0xE000E40C

NVIC0_INTPRI3

NVIC0 IRQ12..15 Priority

0x00000000

0xE000E410

NVIC0_INTPRI4

NVIC0 IRQ16..19 Priority

0x00000000

0xE000E414

NVIC0_INTPRI5

NVIC0 IRQ20..23 Priority

0x00000000

0xE000E418

NVIC0_INTPRI6

NVIC0 IRQ24..27 Priority

0x00000000

0xE000E41C

NVIC0_INTPRI7

NVIC0 IRQ28..31 Priority

0x00000000

0xE000E420

NVIC0_INTPRI8

NVIC0 IRQ32..35 Priority

0x00000000

0xE000E424

NVIC0_INTPRI9

NVIC0 IRQ36..39 Priority

0x00000000

0xE000E428

NVIC0_INTPRI10

NVIC0 IRQ40..43 Priority

0x00000000

0xE000E42C

NVIC0_INTPRI11

NVIC0 IRQ44..47 Priority

0x00000000

0xE000E430

NVIC0_INTPRI12

NVIC0 IRQ48..51 Priority

0x00000000

0xE000E434

NVIC0_INTPRI13

NVIC0 IRQ52..55 Priority

0x00000000

0xE000E438

NVIC0_INTPRI14

NVIC0 IRQ56..59 Priority

0x00000000

0xE000E43C

NVIC0_INTPRI15

NVIC0 IRQ60..63 Priority

0x00000000

0xE000E440

NVIC0_INTPRI16

NVIC0 IRQ64..67 Priority

0x00000000

0xE000E444

NVIC0_INTPRI17

NVIC0 IRQ68..71 Priority

0x00000000

0xE000ED00

NVIC0_INTCPID

NVIC0 CPUID Base

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–13

ADuCM4050 Register List

Table 25-20: ADuCM4050 NVIC0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0xE000ED04

NVIC0_INTSTA

NVIC0 Interrupt Control State

0x00000000

0xE000ED08

NVIC0_INTVEC

NVIC0 Vector Table Offset

0x00000000

0xE000ED0C

NVIC0_INTAIRC

NVIC0 Application Interrupt/Reset Control

0x00000000

0xE000ED10

NVIC0_INTCON0

NVIC0 System Control

0x00000000

0xE000ED14

NVIC0_INTCON1

NVIC0 Configuration Control

0x00000000

0xE000ED18

NVIC0_INTSHPRIO0

NVIC0 System Handlers 4-7 Priority

0x00000000

0xE000ED1C

NVIC0_INTSHPRIO1

NVIC0 System Handlers 8-11 Priority

0x00000000

0xE000ED20

NVIC0_INTSHPRIO3

NVIC0 System Handlers 12-15 Priority

0x00000000

0xE000ED24

NVIC0_INTSHCSR

NVIC0 System Handler Control and State

0x00000000

0xE000ED28

NVIC0_INTCFSR

NVIC0 Configurable Fault Status

0x00000000

0xE000ED2C

NVIC0_INTHFSR

NVIC0 Hard Fault Status

0x00000000

0xE000ED30

NVIC0_INTDFSR

NVIC0 Debug Fault Status

0x00000000

0xE000ED34

NVIC0_INTMMAR

NVIC0 Mem Manage Address

0x00000000

0xE000ED38

NVIC0_INTBFAR

NVIC0 Bus Fault Address

0x00000000

0xE000ED3C

NVIC0_INTAFSR

NVIC0 Auxiliary Fault Status

0x00000000

0xE000ED40

NVIC0_INTPFR0

NVIC0 Processor Feature Register 00x00000000

0xE000ED44

NVIC0_INTPFR1

NVIC0 Processor Feature Register 10x00000000

0xE000ED48

NVIC0_INTDFR0

NVIC0 Debug Feature Register 00x00000000

0xE000ED4C

NVIC0_INTAFR0

NVIC0 Auxiliary Feature Register 00x00000000

0xE000ED50

NVIC0_INTMMFR0

NVIC0 Memory Model Feature Register 00x00000000

0xE000ED54

NVIC0_INTMMFR1

NVIC0 Memory Model Feature Register 10x00000000

0xE000ED58

NVIC0_INTMMFR2

NVIC0 Memory Model Feature Register 20x00000000

0xE000ED5C

NVIC0_INTMMFR3

NVIC0 Memory Model Feature Register 30x00000000

0xE000ED60

NVIC0_INTISAR0

NVIC0 ISA Feature Register 00x00000000

0xE000ED64

NVIC0_INTISAR1

NVIC0 ISA Feature Register 10x00000000

0xE000ED68

NVIC0_INTISAR2

NVIC0 ISA Feature Register 20x00000000

0xE000ED6C

NVIC0_INTISAR3

NVIC0 ISA Feature Register 30x00000000

0xE000ED70

NVIC0_INTISAR4

NVIC0 ISA Feature Register 40x00000000

0xE000EF00

NVIC0_INTTRGI

NVIC0 Software Trigger Interrupt Register

0x00000000

0xE000EFD0

NVIC0_INTPID4

NVIC0 Peripheral Identification Register 40x00000000

0xE000EFD4

NVIC0_INTPID5

NVIC0 Peripheral Identification Register 50x00000000

25–14

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-20: ADuCM4050 NVIC0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0xE000EFD8

NVIC0_INTPID6

NVIC0 Peripheral Identification Register 60x00000000

0xE000EFDC

NVIC0_INTPID7

NVIC0 Peripheral Identification Register 70x00000000

0xE000EFE0

NVIC0_INTPID0

NVIC0 Peripheral Identification Bits7:0

0x00000000

0xE000EFE4

NVIC0_INTPID1

NVIC0 Peripheral Identification Bits15:8

0x00000000

0xE000EFE8

NVIC0_INTPID2

NVIC0 Peripheral Identification Bits16:23

0x00000000

0xE000EFEC

NVIC0_INTPID3

NVIC0 Peripheral Identification Bits24:31

0x00000000

0xE000EFF0

NVIC0_INTCID0

NVIC0 Component Identification Bits7:0

0x00000000

0xE000EFF4

NVIC0_INTCID1

NVIC0 Component Identification Bits15:8

0x00000000

0xE000EFF8

NVIC0_INTCID2

NVIC0 Component Identification Bits16:23

0x00000000

0xE000EFFC

NVIC0_INTCID3

NVIC0 Component Identification Bits24:31

0x00000000

Table 25-21: ADuCM4050 PMG0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x4004C000

PMG0_IEN

PMG0 Power Supply Monitor Interrupt Enable

0x00000000

0x4004C004

PMG0_PSM_STAT

PMG0 Power Supply Monitor Status

0x00000000

0x4004C008

PMG0_PWRMOD

PMG0 Power Mode Register

0x00000000

0x4004C00C

PMG0_PWRKEY

PMG0 Key Protection for PMG_PWRMOD and
PMG_SRAMRET

0x00000000

0x4004C010

PMG0_SHDN_STAT

PMG0 Shutdown Status Register

0x00000000

0x4004C014

PMG0_SRAMRET

PMG0 Control for Retention SRAM in Hibernate Mode

0xFF000000

0x4004C038

PMG0_TRIM

PMG0 Trimming Bits

0x0A8AA2A2

0x4004C040

PMG0_RST_STAT

PMG0 Reset Status

0x00000000

0x4004C044

PMG0_CTL1

PMG0 HPBUCK Control

0x00A00000

Table 25-22: ADuCM4050 PMG0_TST MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x4004C260

PMG0_TST_SRAM_CTL

PMG0_TST Control for SRAM Parity and Instruction
SRAM

0x80000000

0x4004C264

PMG0_TST_SRAM_INITSTAT

PMG0_TST Initialization Status Register

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–15

ADuCM4050 Register List

Table 25-22: ADuCM4050 PMG0_TST MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

0x4004C268

PMG0_TST_CLR_LATCH_ PMG0_TST Clear GPIO After Shutdown Mode
GPIOS

0x00000000

0x4004C26C

PMG0_TST_SCRPAD_IMG PMG0_TST Scratch Pad Image

0x00000000

0x4004C270

PMG0_TST_SCRPAD_3V_
RD

0x00000000

0x4004C274

PMG0_TST_FAST_SHT_W PMG0_TST Fast Shutdown Wake-up Enable
AKEUP

PMG0_TST Scratch Pad Saved in Battery Domain

Reset Value

0x00000000

Table 25-23: ADuCM4050 RNG0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40040400

RNG0_CTL

RNG0 RNG Control Register

0x00000000

0x40040404

RNG0_LEN

RNG0 RNG Sample Length Register

0x00003400

0x40040408

RNG0_STAT

RNG0 RNG Status Register

0x00000000

0x4004040C

RNG0_DATARNG0 RNG Data Register

0x00000000

0x40040410

RNG0_OSCCNT

RNG0 Oscillator Count

0x00000000

0x40040414

RNG0_OSCDIFF[n]RNG0 Oscillator Difference

0x00000000

0x40040415

RNG0_OSCDIFF[n]RNG0 Oscillator Difference

0x00000000

0x40040416

RNG0_OSCDIFF[n]RNG0 Oscillator Difference

0x00000000

0x40040417

RNG0_OSCDIFF[n]RNG0 Oscillator Difference

0x00000000

Table 25-24: ADuCM4050 RTC0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40001000

RTC0_CR0

RTC0 RTC Control 00x000003C40x40001004

RTC0_SR0

RTC0 RTC Status 00x00003F80

0x40001008

RTC0_SR1

RTC0 RTC Status 10x00000078

0x4000100C

RTC0_CNT0

RTC0 RTC Count 00x00000000

0x40001010

RTC0_CNT1

RTC0 RTC Count 10x00000000

0x40001014

RTC0_ALM0

RTC0 RTC Alarm 00x0000FFFF

0x40001018

RTC0_ALM1

RTC0 RTC Alarm 10x0000FFFF

0x4000101C

RTC0_TRM

RTC0 RTC Trim

0x00000398

0x40001020

RTC0_GWY

RTC0 RTC Gateway

0x00000000

25–16

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-24: ADuCM4050 RTC0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40001028

RTC0_CR1

RTC0 RTC Control 1

0x000001E00x4000102C

RTC0_SR2

RTC0 RTC Status 20x0000C000

0x40001030

RTC0_SNAP0

RTC0 RTC Snapshot 00x00000000

0x40001034

RTC0_SNAP1

RTC0 RTC Snapshot 1

0x00000000

0x40001038

RTC0_SNAP2

RTC0 RTC Snapshot 2

0x00000000

0x4000103C

RTC0_MOD

RTC0 RTC Modulo

0x00000040

0x40001040

RTC0_CNT2

RTC0 RTC Count 20x00000000

0x40001044

RTC0_ALM2

RTC0 RTC Alarm 20x00000000

0x40001048

RTC0_SR3

RTC0 RTC Status 30x00000000

0x4000104C

RTC0_CR2IC

RTC0 RTC Control 2 for Configuring Input Capture
Channels

0x000083A00x40001050

RTC0_CR3SS

RTC0 RTC Control 3 for Configuring SensorStrobe
Channel

0x00000000

0x40001054

RTC0_CR4SS

RTC0 RTC Control 4 for Configuring SensorStrobe
Channel

0x00000000

0x40001058

RTC0_SSMSK

RTC0 RTC Mask for SensorStrobe Channel

0x00000000

0x40001064

RTC0_IC2

RTC0 RTC Input Capture Channel 20x00000000

0x40001068

RTC0_IC3

RTC0 RTC Input Capture Channel 30x00000000

0x4000106C

RTC0_IC4

RTC0 RTC Input Capture Channel 40x00000000

0x40001070

RTC0_SS1

RTC0 RTC SensorStrobe Channel 10x00008000

0x40001074

RTC0_SS2

RTC0 RTC SensorStrobe Channel 20x00008000

0x40001078

RTC0_SS3

RTC0 RTC SensorStrobe Channel 30x00008000

0x4000107C

RTC0_SS4

RTC0 RTC SensorStrobe Channel 40x00008000

0x40001080

RTC0_SR4

RTC0 RTC Status 40x0000F7DF

0x40001084

RTC0_SR5

RTC0 RTC Status 50x00000000

0x40001088

RTC0_SR6

RTC0 RTC Status 60x00007900

0x4000108C

RTC0_SS1TGT

RTC0 RTC SensorStrobe Channel 1 Target

0x00008000

0x40001090

RTC0_FRZCNT

RTC0 RTC Freeze Count

0x00000000

0x40001094

RTC0_SS2TGT

RTC0 RTC SensorStrobe Channel 2 Target

0x00008000

0x40001098

RTC0_SS3TGT

RTC0 RTC SensorStrobe Channel 3 Target

0x00008000

0x400010A0

RTC0_SS1LOWDUR

RTC0 RTC Auto-Reload Low Duration for SensorStrobe
Channel 10x00008000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–17

ADuCM4050 Register List

Table 25-24: ADuCM4050 RTC0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x400010A4

RTC0_SS2LOWDUR

RTC0 RTC Auto-Reload Low Duration for SensorStrobe
Channel 20x00008000

0x400010A8

RTC0_SS3LOWDUR

RTC0 RTC Auto-Reload Low Duration for SensorStrobe
Channel 30x00008000

0x400010B0

RTC0_SS1HIGHDUR

RTC0 RTC Auto-Reload High Duration for SensorStrobe 0x00008000
Channel 10x400010B4

RTC0_SS2HIGHDUR

RTC0 RTC Auto-Reload High Duration for SensorStrobe 0x00008000
Channel 20x400010B8

RTC0_SS3HIGHDUR

RTC0 RTC Auto-Reload High Duration for SensorStrobe 0x00008000
Channel 30x400010C0

RTC0_SSMSKOT

RTC0 RTC Masks for SensorStrobe Channels on Time
Control

0x00000000

0x400010C4

RTC0_CR5SSS

RTC0 RTC Control 5 for Configuring SensorStrobe
Channel GPIO Sampling

0x00000000

0x400010C8

RTC0_CR6SSS

RTC0 RTC Control 6 for Configuring SensorStrobe
Channel GPIO Sampling Edge

0x00000000

0x400010CC

RTC0_CR7SSS

RTC0 RTC Control 7 for Configuring SensorStrobe
Channel GPIO Sampling Activity

0x00000000

0x400010D0

RTC0_SR7

RTC0 RTC Status 70x00000000

0x400010D4

RTC0_SR8

RTC0 RTC Status 80x00003F77

0x400010D8

RTC0_SR9

RTC0 RTC Status 90x00000000

0x400010E0

RTC0_GPMUX0

RTC0 RTC GPIO Pin Mux Control Register 00x00004688

0x400010E4

RTC0_GPMUX1

RTC0 RTC GPIO Pin Mux Control Register 10x000001F5

Table 25-25: ADuCM4050 RTC1 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40001400

RTC1_CR0

RTC1 RTC Control 00x000003C40x40001404

RTC1_SR0

RTC1 RTC Status 00x00003F80

0x40001408

RTC1_SR1

RTC1 RTC Status 10x00000078

0x4000140C

RTC1_CNT0

RTC1 RTC Count 00x00000000

0x40001410

RTC1_CNT1

RTC1 RTC Count 10x00000000

0x40001414

RTC1_ALM0

RTC1 RTC Alarm 00x0000FFFF

0x40001418

RTC1_ALM1

RTC1 RTC Alarm 10x0000FFFF

25–18

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-25: ADuCM4050 RTC1 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x4000141C

RTC1_TRM

RTC1 RTC Trim

0x00000398

0x40001420

RTC1_GWY

RTC1 RTC Gateway

0x00000000

0x40001428

RTC1_CR1

RTC1 RTC Control 1

0x000001E00x4000142C

RTC1_SR2

RTC1 RTC Status 20x0000C000

0x40001430

RTC1_SNAP0

RTC1 RTC Snapshot 00x00000000

0x40001434

RTC1_SNAP1

RTC1 RTC Snapshot 1

0x00000000

0x40001438

RTC1_SNAP2

RTC1 RTC Snapshot 2

0x00000000

0x4000143C

RTC1_MOD

RTC1 RTC Modulo

0x00000040

0x40001440

RTC1_CNT2

RTC1 RTC Count 20x00000000

0x40001444

RTC1_ALM2

RTC1 RTC Alarm 20x00000000

0x40001448

RTC1_SR3

RTC1 RTC Status 30x00000000

0x4000144C

RTC1_CR2IC

RTC1 RTC Control 2 for Configuring Input Capture
Channels

0x000083A00x40001450

RTC1_CR3SS

RTC1 RTC Control 3 for Configuring SensorStrobe
Channel

0x00000000

0x40001454

RTC1_CR4SS

RTC1 RTC Control 4 for Configuring SensorStrobe
Channel

0x00000000

0x40001458

RTC1_SSMSK

RTC1 RTC Mask for SensorStrobe Channel

0x00000000

0x40001464

RTC1_IC2

RTC1 RTC Input Capture Channel 20x00000000

0x40001468

RTC1_IC3

RTC1 RTC Input Capture Channel 30x00000000

0x4000146C

RTC1_IC4

RTC1 RTC Input Capture Channel 40x00000000

0x40001470

RTC1_SS1

RTC1 RTC SensorStrobe Channel 10x00008000

0x40001474

RTC1_SS2

RTC1 RTC SensorStrobe Channel 20x00008000

0x40001478

RTC1_SS3

RTC1 RTC SensorStrobe Channel 30x00008000

0x4000147C

RTC1_SS4

RTC1 RTC SensorStrobe Channel 40x00008000

0x40001480

RTC1_SR4

RTC1 RTC Status 40x0000F7DF

0x40001484

RTC1_SR5

RTC1 RTC Status 50x00000000

0x40001488

RTC1_SR6

RTC1 RTC Status 60x00007900

0x4000148C

RTC1_SS1TGT

RTC1 RTC SensorStrobe Channel 1 Target

0x00008000

0x40001490

RTC1_FRZCNT

RTC1 RTC Freeze Count

0x00000000

0x40001494

RTC1_SS2TGT

RTC1 RTC SensorStrobe Channel 2 Target

0x00008000

0x40001498

RTC1_SS3TGT

RTC1 RTC SensorStrobe Channel 3 Target

0x00008000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–19

ADuCM4050 Register List

Table 25-25: ADuCM4050 RTC1 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x400014A0

RTC1_SS1LOWDUR

RTC1 RTC Auto-Reload Low Duration for SensorStrobe
Channel 10x00008000

0x400014A4

RTC1_SS2LOWDUR

RTC1 RTC Auto-Reload Low Duration for SensorStrobe
Channel 20x00008000

0x400014A8

RTC1_SS3LOWDUR

RTC1 RTC Auto-Reload Low Duration for SensorStrobe
Channel 30x00008000

0x400014B0

RTC1_SS1HIGHDUR

RTC1 RTC Auto-Reload High Duration for SensorStrobe 0x00008000
Channel 10x400014B4

RTC1_SS2HIGHDUR

RTC1 RTC Auto-Reload High Duration for SensorStrobe 0x00008000
Channel 20x400014B8

RTC1_SS3HIGHDUR

RTC1 RTC Auto-Reload High Duration for SensorStrobe 0x00008000
Channel 30x400014C0

RTC1_SSMSKOT

RTC1 RTC Masks for SensorStrobe Channels on Time
Control

0x00000000

0x400014C4

RTC1_CR5SSS

RTC1 RTC Control 5 for Configuring SensorStrobe
Channel GPIO Sampling

0x00000000

0x400014C8

RTC1_CR6SSS

RTC1 RTC Control 6 for Configuring SensorStrobe
Channel GPIO Sampling Edge

0x00000000

0x400014CC

RTC1_CR7SSS

RTC1 RTC Control 7 for Configuring SensorStrobe
Channel GPIO Sampling Activity

0x00000000

0x400014D0

RTC1_SR7

RTC1 RTC Status 70x00000000

0x400014D4

RTC1_SR8

RTC1 RTC Status 80x00003F77

0x400014D8

RTC1_SR9

RTC1 RTC Status 90x00000000

0x400014E0

RTC1_GPMUX0

RTC1 RTC GPIO Pin Mux Control Register 00x00004688

0x400014E4

RTC1_GPMUX1

RTC1 RTC GPIO Pin Mux Control Register 10x000001F5

Table 25-26: ADuCM4050 SPI0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40004000

SPI0_STATSPI0 Status

0x00000800

0x40004004

SPI0_RXSPI0 Receive

0x00000000

0x40004008

SPI0_TX

SPI0 Transmit

0x00000000

0x4000400C

SPI0_DIVSPI0 SPI Baud Rate Selection

0x00000000

0x40004010

SPI0_CTL

SPI0 SPI Configuration

0x00000000

0x40004014

SPI0_IEN

SPI0 SPI Interrupts Enable

0x00000000

25–20

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-26: ADuCM4050 SPI0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40004018

SPI0_CNT

SPI0 Transfer Byte Count

0x00000000

0x4000401C

SPI0_DMASPI0 SPI DMA Enable

0x00000000

0x40004020

SPI0_FIFO_STATSPI0 FIFO Status

0x00000000

0x40004024

SPI0_RD_CTL

SPI0 Read Control

0x00000000

0x40004028

SPI0_FLOW_CTL

SPI0 Flow Control

0x00000000

0x4000402C

SPI0_WAIT_TMR

SPI0 Wait Timer for Flow Control

0x00000000

0x40004030

SPI0_CS_CTL

SPI0 Chip Select Control for Multi-slave Connections

0x00000001

0x40004034

SPI0_CS_OVERRIDESPI0 Chip Select Override

0x00000000

Table 25-27: ADuCM4050 SPI1 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40004400

SPI1_STATSPI1 Status

0x00000800

0x40004404

SPI1_RXSPI1 Receive

0x00000000

0x40004408

SPI1_TXSPI1 Transmit

0x00000000

0x4000440C

SPI1_DIVSPI1 SPI Baud Rate Selection

0x00000000

0x40004410

SPI1_CTL

SPI1 SPI Configuration

0x00000000

0x40004414

SPI1_IEN

SPI1 SPI Interrupts Enable

0x00000000

0x40004418

SPI1_CNT

SPI1 Transfer Byte Count

0x00000000

0x4000441C

SPI1_DMASPI1 SPI DMA Enable

0x00000000

0x40004420

SPI1_FIFO_STATSPI1 FIFO Status

0x00000000

0x40004424

SPI1_RD_CTL

SPI1 Read Control

0x00000000

0x40004428

SPI1_FLOW_CTL

SPI1 Flow Control

0x00000000

0x4000442C

SPI1_WAIT_TMR

SPI1 Wait Timer for Flow Control

0x00000000

0x40004430

SPI1_CS_CTL

SPI1 Chip Select Control for Multi-slave Connections

0x00000001

0x40004434

SPI1_CS_OVERRIDESPI1 Chip Select Override

0x00000000

Table 25-28: ADuCM4050 SPI2 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40024000

SPI2_STATSPI2 Status

0x00000800

0x40024004

SPI2_RXSPI2 Receive

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–21

ADuCM4050 Register List

Table 25-28: ADuCM4050 SPI2 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40024008

SPI2_TXSPI2 Transmit

0x00000000

0x4002400C

SPI2_DIVSPI2 SPI Baud Rate Selection

0x00000000

0x40024010

SPI2_CTLSPI2 SPI Configuration

0x00000000

0x40024014

SPI2_IEN

SPI2 SPI Interrupts Enable

0x00000000

0x40024018

SPI2_CNT

SPI2 Transfer Byte Count

0x00000000

0x4002401C

SPI2_DMASPI2 SPI DMA Enable

0x00000000

0x40024020

SPI2_FIFO_STATSPI2 FIFO Status

0x00000000

0x40024024

SPI2_RD_CTL

SPI2 Read Control

0x00000000

0x40024028

SPI2_FLOW_CTL

SPI2 Flow Control

0x00000000

0x4002402C

SPI2_WAIT_TMR

SPI2 Wait Timer for Flow Control

0x00000000

0x40024030

SPI2_CS_CTL

SPI2 Chip Select Control for Multi-slave Connections

0x00000001

0x40024034

SPI2_CS_OVERRIDESPI2 Chip Select Override

0x00000000

Table 25-29: ADuCM4050 SPORT0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40038000

SPORT0_CTL_A

SPORT0 Half SPORT 'A' Control Register

0x00000000

0x40038004

SPORT0_DIV_A

SPORT0 Half SPORT 'A' Divisor Register

0x00000000

0x40038008

SPORT0_IEN_A

SPORT0 Half SPORT A's Interrupt Enable Register

0x00000000

0x4003800C

SPORT0_STAT_A

SPORT0 Half SPORT 'A' Status register

0x00000000

0x40038010

SPORT0_NUMTRAN_A

SPORT0 Half SPORT A Number of Transfers Register

0x00000000

0x40038014

SPORT0_CNVT_A

SPORT0 Half SPORT 'A' CNV width

0x00000000

0x40038020

SPORT0_TX_A

SPORT0 Half SPORT 'A' Tx Buffer Register

0x00000000

0x40038028

SPORT0_RX_A

SPORT0 Half SPORT 'A' Rx Buffer Register

0x00000000

0x40038040

SPORT0_CTL_B

SPORT0 Half SPORT 'B' Control Register

0x00000000

0x40038044

SPORT0_DIV_B

SPORT0 Half SPORT 'B' Divisor Register

0x00000000

0x40038048

SPORT0_IEN_B

SPORT0 Half SPORT B's Interrupt Enable Register

0x00000000

0x4003804C

SPORT0_STAT_B

SPORT0 Half SPORT 'B' Status register

0x00000000

0x40038050

SPORT0_NUMTRAN_B

SPORT0 Half SPORT B Number of Transfers Register

0x00000000

0x40038054

SPORT0_CNVT_B

SPORT0 Half SPORT 'B' CNV width register

0x00000000

0x40038060

SPORT0_TX_B

SPORT0 Half SPORT 'B' Tx Buffer Register

0x00000000

25–22

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-29: ADuCM4050 SPORT0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40038068

SPORT0_RX_B

SPORT0 Half SPORT 'B' Rx Buffer Register

0x00000000

Table 25-30: ADuCM4050 SYS MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40002020

SYS_ADIIDSYS ADI Identification

0x00004144

0x40002024

SYS_CHIPIDSYS Chip Identifier

0x000002A1

0x40002040

SYS_SWDEN

SYS Serial Wire Debug Enable

0x00007072

Table 25-31: ADuCM4050 TMR_RGB MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40000C00

TMR_RGB_LOAD

TMR_RGB 16-bit Load Value

0x00000000

0x40000C04

TMR_RGB_CURCNTTMR_RGB 16-bit Timer Value

0x00000000

0x40000C08

TMR_RGB_CTL

TMR_RGB Control

0x0000000A

0x40000C0C

TMR_RGB_CLRINT

TMR_RGB Clear Interrupt

0x00000000

0x40000C10

TMR_RGB_CAPTURE

TMR_RGB Capture

0x00000000

0x40000C14

TMR_RGB_ALOAD

TMR_RGB 16-bit Load Value, Asynchronous

0x00000000

0x40000C18

TMR_RGB_ACURCNTTMR_RGB 16-bit Timer Value, Asynchronous

0x00000000

0x40000C1C

TMR_RGB_STAT

TMR_RGB Status

0x00000000

0x40000C20

TMR_RGB_PWM0CTL

TMR_RGB PWM0 Control Register

0x00000000

0x40000C24

TMR_RGB_PWM0MATCH TMR_RGB PWM0 Match Value

0x00000000

0x40000C28

TMR_RGB_EVENTSELECT

TMR_RGB Timer Event selection Register

0x00000000

0x40000C2C

TMR_RGB_PWM1CTL

TMR_RGB PWM1 Control Register

0x00000000

0x40000C30

TMR_RGB_PWM1MATCH TMR_RGB PWM1 Match Value

0x00000000

0x40000C34

TMR_RGB_PWM2CTL

0x00000000

0x40000C38

TMR_RGB_PWM2MATCH TMR_RGB PWM2 Match Value

TMR_RGB PWM2 Control Register

0x00000000

Table 25-32: ADuCM4050 UART0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40005000

UART0_TX

UART0 Transmit Holding Register

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–23

ADuCM4050 Register List

Table 25-32: ADuCM4050 UART0 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x40005000

UART0_RX

UART0 Receive Buffer Register

0x00000000

0x40005004

UART0_IEN

UART0 Interrupt Enable

0x00000000

0x40005008

UART0_IIR

UART0 Interrupt ID

0x00000001

0x4000500C

UART0_LCR

UART0 Line Control

0x00000000

0x40005014

UART0_LSR

UART0 Line Status

0x00000060

0x4000501C

UART0_SCR

UART0 Scratch Buffer

0x00000000

0x40005020

UART0_FCR

UART0 FIFO Control

0x00000000

0x40005024

UART0_FBRUART0 Fractional Baud Rate

0x00000000

0x40005028

UART0_DIVUART0 Baud Rate Divider

0x00000000

0x4000502C

UART0_LCR2

UART0 Second Line Control

0x00000002

0x40005030

UART0_CTL

UART0 UART Control Register

0x00000100

0x40005034

UART0_RFC

UART0 RX FIFO Byte Count

0x00000000

0x40005038

UART0_TFC

UART0 TX FIFO Byte Count

0x00000000

0x4000503C

UART0_RSC

UART0 RS485 Half-duplex Control

0x00000000

0x40005040

UART0_ACR

UART0 Auto Baud Control

0x00000000

0x40005044

UART0_ASRLUART0 Auto Baud Status (Low)

0x00000000

0x40005048

UART0_ASRH

UART0 Auto Baud Status (High)

0x00000000

Table 25-33: ADuCM4050 UART1 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40005400

UART1_TX

UART1 Transmit Holding Register

0x00000000

0x40005400

UART1_RX

UART1 Receive Buffer Register

0x00000000

0x40005404

UART1_IEN

UART1 Interrupt Enable

0x00000000

0x40005408

UART1_IIR

UART1 Interrupt ID

0x00000001

0x4000540C

UART1_LCR

UART1 Line Control

0x00000000

0x40005414

UART1_LSR

UART1 Line Status

0x00000060

0x4000541C

UART1_SCR

UART1 Scratch Buffer

0x00000000

0x40005420

UART1_FCR

UART1 FIFO Control

0x00000000

0x40005424

UART1_FBRUART1 Fractional Baud Rate

0x00000000

0x40005428

UART1_DIVUART1 Baud Rate Divider

0x00000000

25–24

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

ADuCM4050 Register List

Table 25-33: ADuCM4050 UART1 MMR Register Addresses (Continued)
Memory Mapped Address

Register Name

Description

Reset Value

0x4000542C

UART1_LCR2

UART1 Second Line Control

0x00000002

0x40005430

UART1_CTL

UART1 UART Control Register

0x00000100

0x40005434

UART1_RFC

UART1 RX FIFO Byte Count

0x00000000

0x40005438

UART1_TFC

UART1 TX FIFO Byte Count

0x00000000

0x4000543C

UART1_RSC

UART1 RS485 Half-duplex Control

0x00000000

0x40005440

UART1_ACR

UART1 Auto Baud Control

0x00000000

0x40005444

UART1_ASRLUART1 Auto Baud Status (Low)

0x00000000

0x40005448

UART1_ASRH

UART1 Auto Baud Status (High)

0x00000000

Table 25-34: ADuCM4050 WDT0 MMR Register Addresses
Memory Mapped Address

Register Name

Description

Reset Value

0x40002C00

WDT0_LOAD

WDT0 Load Value

0x00001000

0x40002C04

WDT0_CCNT

WDT0 Current Count Value

0x00001000

0x40002C08

WDT0_CTL

WDT0 Control

0x000000E9

0x40002C0C

WDT0_RESTART

WDT0 Clear Interrupt

0x00000000

0x40002C18

WDT0_STAT

WDT0 Status

0x00000000

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

25–25IndexSymbols
16-bitLoad
Value,
Asynchronous,
TMR_RGB(TMR_RGB_ALOAD).......................................... 23–8
16-bit Load Value, Asynchronous, TMR (TMR_ALOAD)....
.............................................................................22–10
16-bit Load Value, TMR_RGB (TMR_RGB_LOAD) 23–16
16-bit Load Value, TMR (TMR_LOAD).................... 22–18
16-bitTimer
Value,
Asynchronous,
TMR_RGB(TMR_RGB_ACURCNT).................................... 23–9
16-bitTimer
Value,
Asynchronous,
TMR(TMR_ACURCNT)............................................ 22–11
16-bit Timer Value, TMR_RGB (TMR_RGB_CURCNT)...
.............................................................................23–25
16-bit Timer Value, TMR (TMR_CURCNT)............ 22–23

A
ADC_ALERT (Alert Indication, ADC)....................... 20–22
ADC_AVG_CFG (Averaging Configuration, ADC)....20–23
ADC_BAT_OUT (Battery Monitoring Result, ADC).20–24
ADC_CAL_WORD (Calibration Word, ADC).......... 20–25
ADC_CFG (ADC Configuration, ADC).................... 20–26
ADC_CFG1 (Reference Buffer Low Power Mode, ADC)......
.............................................................................20–28
ADC_CH0_OUT (Conversion Result Channel 0, ADC).....
.............................................................................20–29
ADC_CH1_OUT (Conversion Result Channel 1, ADC).....
.............................................................................20–30
ADC_CH2_OUT (Conversion Result Channel 2, ADC).....
.............................................................................20–31
ADC_CH3_OUT (Conversion Result Channel 3, ADC).....
.............................................................................20–32
ADC_CH4_OUT (Conversion Result Channel 4, ADC).....
.............................................................................20–33
ADC_CH5_OUT (Conversion Result Channel 5, ADC).....
.............................................................................20–34
ADC_CH6_OUT (Conversion Result Channel 6, ADC).....
.............................................................................20–35
ADC_CH7_OUT (Conversion Result Channel 7, ADC).....
.............................................................................20–36
ADC_CNV_CFG (ADC Conversion Configuration, ADC).
.............................................................................20–37

ADC_CNV_TIME (ADC Conversion Time, ADC)...20–38
ADC_DMA_OUT (DMA Output Register, ADC).....20–39
ADC_HYS0 (Channel 0 Hysteresis, ADC)..................20–40
ADC_HYS1 (Channel 1 Hysteresis, ADC)..................20–41
ADC_HYS2 (Channel 2 Hysteresis, ADC)..................20–42
ADC_HYS3 (Channel 3 Hysteresis, ADC)..................20–43
ADC_IRQ_EN (Interrupt Enable, ADC)................... 20–44
ADC_LIM0_HI (Channel 0 High Limit, ADC)......... 20–45
ADC_LIM0_LO (Channel 0 Low Limit, ADC)..........20–46
ADC_LIM1_HI (Channel 1 High Limit, ADC)......... 20–47
ADC_LIM1_LO (Channel 1 Low Limit, ADC)..........20–48
ADC_LIM2_HI (Channel 2 High Limit, ADC)......... 20–49
ADC_LIM2_LO (Channel 2 Low Limit, ADC)..........20–50
ADC_LIM3_HI (Channel 3 High Limit, ADC)......... 20–51
ADC_LIM3_LO (Channel 3 Low Limit, ADC)..........20–52
ADC_OVF (Overflow of Output Registers, ADC)......20–53
ADC_PWRUP (ADC Power-up Time, ADC).............20–55
ADC_STAT (ADC Status, ADC)................................20–56
ADC_TMP_OUT (Temperature Result, ADC).......... 20–59
ADC_TMP2_OUT (Temperature Result 2, ADC)..... 20–58
ADC Configuration, ADC (ADC_CFG).................... 20–26
ADC Conversion Configuration, ADC (ADC_CNV_CFG).
.............................................................................20–37
ADC Conversion Time, ADC (ADC_CNV_TIME)...20–38
ADC Power-up Time, ADC (ADC_PWRUP).............20–55
ADC Status, ADC (ADC_STAT)................................20–56
ADI Identification, SYS (SYS_ADIID)............................2–6
AES Key Bits [127:96], CRYPT (CRYPT_AESKEY3).12–32
AES Key Bits [159:128], CRYPT (CRYPT_AESKEY4).........
.............................................................................12–33
AES Key Bits [191:160], CRYPT (CRYPT_AESKEY5).........
.............................................................................12–34
AES Key Bits [223:192], CRYPT (CRYPT_AESKEY6).........
.............................................................................12–35
AES Key Bits [255:224], CRYPT (CRYPT_AESKEY7).........
.............................................................................12–36
AES Key Bits [31:0], CRYPT (CRYPT_AESKEY0).....12–29
AES Key Bits [63:32], CRYPT (CRYPT_AESKEY1)...12–30
AES Key Bits [95:64], CRYPT (CRYPT_AESKEY2)...12–31
Alert Indication, ADC (ADC_ALERT)....................... 20–22
Authentication Data Length, CRYPT (CRYPT_PREFIXLEN)....................................................................12–68

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference26Auto Baud Control, UART (UART_ACR)..................17–11
Auto Baud Status (High), UART (UART_ASRH).......17–13
Auto Baud Status (Low), UART (UART_ASRL)......... 17–14
Automatic Stretch SCL, I2C (I2C_ASTRETCH_SCL).........
.............................................................................18–12
Averaging Configuration, ADC (ADC_AVG_CFG)....20–23

B
Battery Monitoring Result, ADC (ADC_BAT_OUT).20–24
Baud Rate Divider, UART (UART_DIV)....................17–16
BEEP_CFG (Beeper Configuration, BEEP).................. 19–8
BEEP_STAT (Beeper Status, BEEP)............................ 19–10
BEEP_TONEA (Tone A Data, BEEP)........................ 19–12
BEEP_TONEB (Tone B Data, BEEP).........................19–13
Beeper Configuration, BEEP (BEEP_CFG).................. 19–8
Beeper Status, BEEP (BEEP_STAT)............................ 19–10

C
Cache
Key
Register,
FLCC_CACHE(FLCC_CACHE_KEY)..........................................10–2
Cache
Setup
Register,
FLCC_CACHE(FLCC_CACHE_SETUP).....................................10–3
Cache
StatusRegister,
FLCC_CACHE(FLCC_CACHE_STAT)........................................10–4
Calibration Word, ADC (ADC_CAL_WORD).......... 20–25
Capture, TMR_RGB (TMR_RGB_CAPTURE)........ 23–10
Capture, TMR (TMR_CAPTURE)............................ 22–12
Channel 0 High Limit, ADC (ADC_LIM0_HI)......... 20–45
Channel 0 Hysteresis, ADC (ADC_HYS0)..................20–40
Channel 0 Low Limit, ADC (ADC_LIM0_LO)..........20–46
Channel 1 High Limit, ADC (ADC_LIM1_HI)......... 20–47
Channel 1 Hysteresis, ADC (ADC_HYS1)..................20–41
Channel 1 Low Limit, ADC (ADC_LIM1_LO)..........20–48
Channel 2 High Limit, ADC (ADC_LIM2_HI)......... 20–49
Channel 2 Hysteresis, ADC (ADC_HYS2)..................20–42
Channel 2 Low Limit, ADC (ADC_LIM2_LO)..........20–50
Channel 3 High Limit, ADC (ADC_LIM3_HI)......... 20–51
Channel 3 Hysteresis, ADC (ADC_HYS3)..................20–43
Channel 3 Low Limit, ADC (ADC_LIM3_LO)..........20–52
Chip Identifier, SYS (SYS_CHIPID)............................... 2–7
Chip Select Control for Multi-slave Connections, SPI(SPI_CS_CTL).................................................... 15–18
Chip Select Override, SPI (SPI_CS_OVERRIDE)...... 15–19
Clear GPIO After Shutdown Mode, PMG_TST(PMG_TST_CLR_LATCH_GPIOS).................... 4–27
Clear Interrupt, TMR_RGB (TMR_RGB_CLRINT).23–11

Clear Interrupt, TMR (TMR_CLRINT).................... 22–13
Clear Interrupt, WDT (WDT_RESTART)................... 24–9
CLKG_CLK_CTL0 (Misc Clock Settings, CLKG_CLK).....
...............................................................................6–26
CLKG_CLK_CTL1 (Clock Dividers, CLKG_CLK)..... 6–29
CLKG_CLK_CTL2 (HF Oscillator Divided Clock Select,
CLKG_CLK)......................................................... 6–31
CLKG_CLK_CTL3 (System PLL, CLKG_CLK)..........6–33
CLKG_CLK_CTL5 (User Clock Gating Control,
CLKG_CLK)......................................................... 6–35
CLKG_CLK_STAT0 (Clocking Status, CLKG_CLK).. 6–38
CLKG_OSC_CTL (Oscillator Control, CLKG_OSC). 6–20
CLKG_OSC_KEY (Key Protection for OSCCTRL,
CLKG_OSC)......................................................... 6–25
Clock Dividers, CLKG_CLK (CLKG_CLK_CTL1)..... 6–29
Clocking Status, CLKG_CLK (CLKG_CLK_STAT0).. 6–38
Command, FLCC (FLCC_CMD)................................ 8–25
Configuration Register, CRYPT (CRYPT_CFG).........12–38
Control, TMR_RGB (TMR_RGB_CTL)................... 23–12
Control, TMR (TMR_CTL).......................................22–14
Control, WDT (WDT_CTL)....................................... 24–6
Control for Retention SRAM in Hibernate Mode, PMG(PMG_SRAMRET)........................................ 4–25,9–9
Control for SRAM Parity and Instruction SRAM,
PMG_TST (PMG_TST_SRAM_CTL).......... 4–31,9–7
Conversion Result Channel 0, ADC (ADC_CH0_OUT).....
.............................................................................20–29
Conversion Result Channel 1, ADC (ADC_CH1_OUT).....
.............................................................................20–30
Conversion Result Channel 2, ADC (ADC_CH2_OUT).....
.............................................................................20–31
Conversion Result Channel 3, ADC (ADC_CH3_OUT).....
.............................................................................20–32
Conversion Result Channel 4, ADC (ADC_CH4_OUT).....
.............................................................................20–33
Conversion Result Channel 5, ADC (ADC_CH5_OUT).....
.............................................................................20–34
Conversion Result Channel 6, ADC (ADC_CH6_OUT).....
.............................................................................20–35
Conversion Result Channel 7, ADC (ADC_CH7_OUT).....
.............................................................................20–36
Counter Initialization Vector, CRYPT (CRYPT_CNTRINIT).................................................................... 12–41
CRC_CTL (CRC Control, CRC)................................14–10
CRC_IPBITS[n] (Input Data Bits, CRC)....................14–12
CRC_IPBYTE (Input Data Byte, CRC)...................... 14–13

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference27

CRC_IPDATA (Input Data Word, CRC)....................14–14
CRC_POLY (Programmable CRC Polynomial, CRC).14–15
CRC_RESULT (CRC Result, CRC)............................14–16
CRC Control, CRC (CRC_CTL)................................14–10
CRC Result, CRC (CRC_RESULT)........................... 14–16
CRYPT_AESKEY0 (AES Key Bits [31:0], CRYPT).... 12–29
CRYPT_AESKEY1 (AES Key Bits [63:32], CRYPT).. 12–30
CRYPT_AESKEY2 (AES Key Bits [95:64], CRYPT).. 12–31
CRYPT_AESKEY3 (AES Key Bits [127:96], CRYPT) 12–32
CRYPT_AESKEY4 (AES Key Bits [159:128], CRYPT)........
.............................................................................12–33
CRYPT_AESKEY5 (AES Key Bits [191:160], CRYPT)........
.............................................................................12–34
CRYPT_AESKEY6 (AES Key Bits [223:192], CRYPT)........
.............................................................................12–35
CRYPT_AESKEY7 (AES Key Bits [255:224], CRYPT)........
.............................................................................12–36
CRYPT_CCM_NUM_VALID_BYTES(NUM_VALID_BYTES, CRYPT)........................................... 12–37
CRYPT_CFG (Configuration Register, CRYPT).........12–38
CRYPT_CNTRINIT (Counter Initialization Vector,
CRYPT)............................................................... 12–41
CRYPT_DATALEN (Payload Data Length, CRYPT). 12–42
CRYPT_INBUF (Input Buffer, CRYPT).....................12–43
CRYPT_INTEN (Interrupt Enable Register, CRYPT) 12–44
CRYPT_KUW0 (Key Wrap Unwrap Register 0, CRYPT).....
.............................................................................12–45
CRYPT_KUW1 (Key Wrap Unwrap Register 1, CRYPT).....
.............................................................................12–46
CRYPT_KUW10 (Key Wrap Unwrap Register 10, CRYPT).
.............................................................................12–47
CRYPT_KUW11 (Key Wrap Unwrap Register 11, CRYPT).
.............................................................................12–48
CRYPT_KUW12 (Key Wrap Unwrap Register 12, CRYPT).
.............................................................................12–49
CRYPT_KUW13 (Key Wrap Unwrap Register 13, CRYPT).
.............................................................................12–50
CRYPT_KUW14 (Key Wrap Unwrap Register 14, CRYPT).
.............................................................................12–51
CRYPT_KUW15 (Key Wrap Unwrap Register 15, CRYPT).
.............................................................................12–52
CRYPT_KUW2 (Key Wrap Unwrap Register 2, CRYPT).....
.............................................................................12–53
CRYPT_KUW3 (Key Wrap Unwrap Register 3, CRYPT).....
.............................................................................12–54

CRYPT_KUW4 (Key Wrap Unwrap Register 4, CRYPT).....
.............................................................................12–55
CRYPT_KUW5 (Key Wrap Unwrap Register 5, CRYPT).....
.............................................................................12–56
CRYPT_KUW6 (Key Wrap Unwrap Register 6, CRYPT).....
.............................................................................12–57
CRYPT_KUW7 (Key Wrap Unwrap Register 7, CRYPT).....
.............................................................................12–58
CRYPT_KUW8 (Key Wrap Unwrap Register 8, CRYPT).....
.............................................................................12–59
CRYPT_KUW9 (Key Wrap Unwrap Register 9, CRYPT).....
.............................................................................12–60
CRYPT_KUWVALSTR1 (Key Wrap Unwrap Validation
String [63:32], CRYPT)....................................... 12–61
CRYPT_KUWVALSTR2 (Key Wrap Unwrap Validation
String [31:0], CRYPT)......................................... 12–62
CRYPT_NONCE0 (Nonce Bits [31:0], CRYPT)........12–63
CRYPT_NONCE1 (Nonce Bits [63:32], CRYPT)......12–64
CRYPT_NONCE2 (Nonce Bits [95:64], CRYPT)......12–65
CRYPT_NONCE3 (Nonce Bits [127:96], CRYPT)....12–66
CRYPT_OUTBUF (Output Buffer, CRYPT)............. 12–67
CRYPT_PREFIXLEN (Authentication Data Length,
CRYPT)............................................................... 12–68
CRYPT_PRKSTORCFG(PRKSTOR
Configuration,
CRYPT)............................................................... 12–69
CRYPT_SHA_LAST_WORD (SHA Last Word and Valid
Bits Information, CRYPT)................................... 12–78
CRYPT_SHAH0 (SHA Bits [31:0], CRYPT)..............12–70
CRYPT_SHAH1 (SHA Bits [63:32], CRYPT)............12–71
CRYPT_SHAH2 (SHA Bits [95:64], CRYPT)............12–72
CRYPT_SHAH3 (SHA Bits [127:96], CRYPT)..........12–73
CRYPT_SHAH4 (SHA Bits [159:128], CRYPT)........12–74
CRYPT_SHAH5 (SHA Bits [191:160], CRYPT)........12–75
CRYPT_SHAH6 (SHA Bits [223:192], CRYPT)........12–76
CRYPT_SHAH7 (SHA Bits [255:224], CRYPT)........12–77
CRYPT_STAT (Status Register, CRYPT).................... 12–79
Current Count Value, WDT (WDT_CCNT)............... 24–5

D
DMA_ADBPTR (DMA Channel Alternate Control Database Pointer, DMA)..............................................11–21
DMA_ALT_CLR (DMA Channel Primary Alternate Clear,
DMA).................................................................. 11–22
DMA_ALT_SET (DMA Channel Primary Alternate Set,
DMA).................................................................. 11–23

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference28

DMA_BS_CLR (DMA Channel Bytes Swap Enable Clear,
DMA).................................................................. 11–24
DMA_BS_SET (DMA Channel Bytes Swap Enable Set,
DMA).................................................................. 11–25
DMA_CFG (DMA Configuration, DMA)..................11–26
DMA_DSTADDR_CLR (DMA Channel Destination Address Decrement Enable Clear, DMA).................. 11–27
DMA_DSTADDR_SET (DMA Channel Destination Address Decrement Enable Set, DMA)..................... 11–28
DMA_EN_CLR (DMA Channel Enable Clear, DMA).........
.............................................................................11–29
DMA_EN_SET (DMA Channel Enable Set, DMA)...11–30
DMA_ERR_CLR (DMA Bus Error Clear, DMA).......11–32
DMA_ERRCHNL_CLR (DMA per Channel Error Clear,
DMA).................................................................. 11–31
DMA_INVALIDDESC_CLR (DMA per Channel Invalid
Descriptor Clear, DMA).......................................11–33
DMA_PDBPTR (DMA Channel Primary Control Database
Pointer, DMA)..................................................... 11–34
DMA_PRI_CLR (DMA Channel Priority Clear, DMA).......
.............................................................................11–35
DMA_PRI_SET (DMA Channel Priority Set, DMA). 11–36
DMA_REVID (DMA Controller Revision ID, DMA)11–37
DMA_RMSK_CLR (DMA Channel Request Mask Clear,
DMA).................................................................. 11–38
DMA_RMSK_SET (DMA Channel Request Mask Set,
DMA).................................................................. 11–39
DMA_SRCADDR_CLR (DMA Channel Source Address
Decrement Enable Clear, DMA).......................... 11–40
DMA_SRCADDR_SET (DMA Channel Source Address
Decrement Enable Set, DMA)..............................11–41
DMA_STAT (DMA Status, DMA)............................. 11–42
DMA_SWREQ (DMA Channel Software Request, DMA)...
.............................................................................11–43
DMA Bus Error Clear, DMA (DMA_ERR_CLR).......11–32
DMA Channel Alternate Control Database Pointer, DMA(DMA_ADBPTR)................................................11–21
DMA Channel Bytes Swap Enable Clear, DMA(DMA_BS_CLR)................................................. 11–24
DMA Channel Bytes Swap Enable Set, DMA(DMA_BS_SET)..................................................11–25
DMA Channel Destination Address Decrement Enable
Clear, DMA (DMA_DSTADDR_CLR).............. 11–27
DMA Channel Destination Address Decrement Enable Set,
DMA (DMA_DSTADDR_SET)......................... 11–28

DMA Channel Enable Clear, DMA (DMA_EN_CLR).........
.............................................................................11–29
DMA Channel Enable Set, DMA (DMA_EN_SET)...11–30
DMA Channel Primary Alternate Clear, DMA(DMA_ALT_CLR)...............................................11–22
DMA
ChannelPrimary
Alternate
Set,
DMA(DMA_ALT_SET)............................................... 11–23
DMA Channel Primary Control Database Pointer, DMA(DMA_PDBPTR)................................................11–34
DMA Channel Priority Clear, DMA (DMA_PRI_CLR).......
.............................................................................11–35
DMA Channel Priority Set, DMA (DMA_PRI_SET). 11–36
DMA
ChannelRequest
Mask
Clear,DMA(DMA_RMSK_CLR)...........................................11–38
DMA
ChannelRequest
Mask
Set,
DMA
(DMA_RMSK_SET)........................................... 11–39
DMA Channel Software Request, DMA (DMA_SWREQ)...
.............................................................................11–43
DMA Channel Source Address Decrement Enable Clear,
DMA (DMA_SRCADDR_CLR).........................11–40
DMA Channel Source Address Decrement Enable Set,
DMA (DMA_SRCADDR_SET)......................... 11–41
DMA Configuration, DMA (DMA_CFG)..................11–26
DMA Controller Revision ID, DMA (DMA_REVID)11–37
DMA Output Register, ADC (ADC_DMA_OUT).... 20–39
DMA
perChannelError
Clear,DMA(DMA_ERRCHNL_CLR)...................................11–31
DMA per Channel Invalid Descriptor Clear, DMA(DMA_INVALIDDESC_CLR)........................... 11–33
DMA Status, DMA (DMA_STAT)............................. 11–42

E
ECC Status (Address), FLCC (FLCC_ECC_ADDR)....8–29
External Interrupt Clear, XINT (XINT_CLR).............. 3–10
External Interrupt Configuration, XINT (XINT_CFG0) 3–7
External
WakeupInterrupt
Status,XINT(XINT_EXT_STAT)..............................................3–11

F
Fast

Shutdown
Wake-up
Enable,PMG_TST(PMG_TST_FAST_SHT_WAKEUP)................... 4–28
FIFO Control, UART (UART_FCR).......................... 17–18
FIFO Status, SPI (SPI_FIFO_STAT).......................... 15–25
First Slave Address Device ID, I2C (I2C_ID0)............ 18–16
Flash Security, FLCC (FLCC_POR_SEC).....................8–23

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference29

FLCC_ABORT_EN_HI (IRQ Abort Enable (Upper Bits),
FLCC)....................................................................8–21
FLCC_ABORT_EN_LO (IRQ Abort Enable (Lower Bits),
FLCC)....................................................................8–22
FLCC_CACHE_KEY(CacheKey
Register,
FLCC_CACHE).................................................... 10–2
FLCC_CACHE_SETUP(Cache
Setup
Register,
FLCC_CACHE).................................................... 10–3
FLCC_CACHE_STAT(CacheStatusRegister,
FLCC_CACHE).................................................... 10–4
FLCC_CMD (Command, FLCC)................................ 8–25
FLCC_ECC_ADDR (ECC Status (Address), FLCC)....8–29
FLCC_IEN (Interrupt Enable, FLCC).......................... 8–30
FLCC_KEY (Key, FLCC)..............................................8–32
FLCC_KH_ADDR (Write Address, FLCC)..................8–33
FLCC_KH_DATA0 (Write Lower Data, FLCC)...........8–34
FLCC_KH_DATA1 (Write Upper Data, FLCC)...........8–35
FLCC_PAGE_ADDR0 (Lower Page Address, FLCC)... 8–36
FLCC_PAGE_ADDR1 (Upper Page Address, FLCC)...8–37
FLCC_POR_SEC (Flash Security, FLCC).....................8–23
FLCC_SIGNATURE (Signature, FLCC)...................... 8–38
FLCC_STAT (Status, FLCC)........................................ 8–39
FLCC_TIME_PARAM0 (Time Parameter 0, FLCC)....8–46
FLCC_TIME_PARAM1 (Time Parameter 1, FLCC)....8–49
FLCC_UCFG (User Configuration, FLCC)..................8–51
FLCC_VOL_CFG (Volatile Flash Configuration, FLCC).....
...............................................................................8–24
FLCC_WR_ABORT_ADDR (Write Abort Address, FLCC)...............................................................................8–55
FLCC_WRPROT (Write Protection, FLCC)................ 8–53
Flow Control, SPI (SPI_FLOW_CTL)........................ 15–26
Fourth Slave Address Device ID, I2C (I2C_ID3)........ 18–19
Fractional Baud Rate, UART (UART_FBR)................17–17

G
GPIO_CFG (Port Configuration, GPIO)........................5–8
GPIO_CLR (Port Data Out Clear, GPIO).................... 5–10
GPIO_DS (Port Drive Strength Select, GPIO)..............5–11
GPIO_IEN (Port Input Path Enable, GPIO).................5–14
GPIO_IENA (Port Interrupt A Enable, GPIO)............. 5–15
GPIO_IENB (Port Interrupt B Enable, GPIO)............. 5–16
GPIO_IN (Port Registered Data Input, GPIO)............. 5–17
GPIO_INT (Port Interrupt Status, GPIO).................... 5–18
GPIO_OEN (Port Output Enable, GPIO)....................5–19
GPIO_OUT (Port Data Output, GPIO).......................5–20

GPIO_PE (Port Output Pull-up/Pull-down Enable, GPIO)..
...............................................................................5–21
GPIO_POL (Port Interrupt Polarity, GPIO)................. 5–22
GPIO_SET (Port Data Out Set, GPIO)........................ 5–23
GPIO_TGL (Port Pin Toggle, GPIO)........................... 5–24

H
Half SPORT 'A' CNV width, SPORT (SPORT_CNVT_A).
.............................................................................16–45
Half
SPORT
'A'
Control
Register,
SPORT(SPORT_CTL_A)................................................16–22
Half
SPORT
'A'
DivisorRegister,
SPORT(SPORT_DIV_A)................................................ 16–31
Half SPORT 'A' Rx Buffer Register, SPORT(SPORT_RX_A).................................................. 16–39
Half SPORT 'A' Status register, SPORT (SPORT_STAT_A).............................................................................16–41
Half SPORT 'A' Tx Buffer Register, SPORT(SPORT_TX_A).................................................. 16–47
Half SPORT 'B' CNV width register, SPORT(SPORT_CNVT_B)............................................ 16–46
Half
SPORT
'B'
Control
Register,
SPORT(SPORT_CTL_B)................................................16–27
Half
SPORT
'B'
DivisorRegister,
SPORT(SPORT_DIV_B)................................................ 16–32
Half SPORT 'B' Rx Buffer Register, SPORT(SPORT_RX_B).................................................. 16–40
Half SPORT 'B' Status register, SPORT (SPORT_STAT_B).............................................................................16–43
Half SPORT 'B' Tx Buffer Register, SPORT(SPORT_TX_B).................................................. 16–48
Half SPORT A's Interrupt Enable Register, SPORT(SPORT_IEN_A).................................................16–33
Half SPORT A Number of Transfers Register, SPORT(SPORT_NUMTRAN_A)...................................16–37
Half SPORT B's Interrupt Enable Register, SPORT(SPORT_IEN_B).................................................16–35
Half SPORT B Number of Transfers Register, SPORT(SPORT_NUMTRAN_B)...................................16–38
Hardware General Call ID, I2C (I2C_ALT)................ 18–11
HF Oscillator Divided Clock Select, CLKG_CLK(CLKG_CLK_CTL2)............................................ 6–31
HPBUCK Control, PMG (PMG_CTL1)......................4–13

I
I2C_ADDR1 (Master Address Byte 1, I2C).................. 18–9

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference30

I2C_ADDR2 (Master Address Byte 2, I2C)................ 18–10
I2C_ALT (Hardware General Call ID, I2C)................ 18–11
I2C_ASTRETCH_SCL (Automatic Stretch SCL, I2C).........
.............................................................................18–12
I2C_BYT (Start Byte, I2C)..........................................18–14
I2C_DIV (Serial Clock Period Divisor, I2C)............... 18–15
I2C_ID0 (First Slave Address Device ID, I2C)............ 18–16
I2C_ID1 (Second Slave Address Device ID, I2C)........18–17
I2C_ID2 (Third Slave Address Device ID, I2C)..........18–18
I2C_ID3 (Fourth Slave Address Device ID, I2C)........ 18–19
I2C_MCRXCNT (Master Current Receive Data Count,
I2C)..................................................................... 18–22
I2C_MCTL (Master Control, I2C)............................. 18–20
I2C_MRX (Master Receive Data, I2C)........................18–23
I2C_MRXCNT (Master Receive Data Count, I2C).... 18–24
I2C_MSTAT (Master Status, I2C).............................. 18–25
I2C_MTX (Master Transmit Data, I2C)..................... 18–28
I2C_SCTL (Slave Control, I2C)..................................18–29
I2C_SHCTL (Shared Control, I2C)............................18–31
I2C_SRX (Slave Receive, I2C).....................................18–32
I2C_SSTAT (Slave I2C Status/Error/IRQ, I2C).......... 18–33
I2C_STAT (Master and Slave FIFO Status, I2C).........18–36
I2C_STX (Slave Transmit, I2C).................................. 18–38
I2C_TCTL (Timing Control Register, I2C)................ 18–39
Initialization
StatusRegister,
PMG_TST(PMG_TST_SRAM_INITSTAT)................... 4–33,9–5
Input Buffer, CRYPT (CRYPT_INBUF).....................12–43
Input Data Bits, CRC (CRC_IPBITS[n])....................14–12
Input Data Byte, CRC (CRC_IPBYTE)...................... 14–13
Input Data Word, CRC (CRC_IPDATA)....................14–14
Interrupt Enable, ADC (ADC_IRQ_EN)................... 20–44
Interrupt Enable, FLCC (FLCC_IEN).......................... 8–30
Interrupt Enable, UART (UART_IEN)....................... 17–20
Interrupt Enable Register, CRYPT (CRYPT_INTEN) 12–44
Interrupt ID, UART (UART_IIR)...............................17–21
IRQ
Abort
Enable(LowerBits),FLCC(FLCC_ABORT_EN_LO).................................... 8–22
IRQ
Abort
Enable(UpperBits),FLCC(FLCC_ABORT_EN_HI)..................................... 8–21

KKey, FLCC (FLCC_KEY)..............................................8–32
KeyProtectionfor
OSCCTRL,
CLKG_OSC(CLKG_OSC_KEY)...............................................6–25
Key Protection for PMG_PWRMOD and PMG_SRAMRET, PMG (PMG_PWRKEY)...............................4–20

Key Wrap Unwrap Register 0, CRYPT (CRYPT_KUW0).....
.............................................................................12–45
Key Wrap Unwrap Register 1, CRYPT (CRYPT_KUW1).....
.............................................................................12–46
Key Wrap Unwrap Register 10, CRYPT (CRYPT_KUW10).
.............................................................................12–47
Key Wrap Unwrap Register 11, CRYPT (CRYPT_KUW11).
.............................................................................12–48
Key Wrap Unwrap Register 12, CRYPT (CRYPT_KUW12).
.............................................................................12–49
Key Wrap Unwrap Register 13, CRYPT (CRYPT_KUW13).
.............................................................................12–50
Key Wrap Unwrap Register 14, CRYPT (CRYPT_KUW14).
.............................................................................12–51
Key Wrap Unwrap Register 15, CRYPT (CRYPT_KUW15).
.............................................................................12–52
Key Wrap Unwrap Register 2, CRYPT (CRYPT_KUW2).....
.............................................................................12–53
Key Wrap Unwrap Register 3, CRYPT (CRYPT_KUW3).....
.............................................................................12–54
Key Wrap Unwrap Register 4, CRYPT (CRYPT_KUW4).....
.............................................................................12–55
Key Wrap Unwrap Register 5, CRYPT (CRYPT_KUW5).....
.............................................................................12–56
Key Wrap Unwrap Register 6, CRYPT (CRYPT_KUW6).....
.............................................................................12–57
Key Wrap Unwrap Register 7, CRYPT (CRYPT_KUW7).....
.............................................................................12–58
Key Wrap Unwrap Register 8, CRYPT (CRYPT_KUW8).....
.............................................................................12–59
Key Wrap Unwrap Register 9, CRYPT (CRYPT_KUW9).....
.............................................................................12–60
Key Wrap Unwrap Validation String [31:0], CRYPT(CRYPT_KUWVALSTR2).................................. 12–62
Key Wrap Unwrap Validation String [63:32], CRYPT(CRYPT_KUWVALSTR1).................................. 12–61

LLine Control, UART (UART_LCR)............................17–22
Line Status, UART (UART_LSR)................................17–25
Load Value, WDT (WDT_LOAD)............................... 24–8
Lower Page Address, FLCC (FLCC_PAGE_ADDR0)... 8–36

M
Master Address Byte 1, I2C (I2C_ADDR1).................. 18–9
Master Address Byte 2, I2C (I2C_ADDR2)................ 18–10

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference31Master and Slave FIFO Status, I2C (I2C_STAT).........18–36
Master Control, I2C (I2C_MCTL)............................. 18–20
MasterCurrent
Receive
Data
Count,
I2C(I2C_MCRXCNT).............................................. 18–22
Master Receive Data, I2C (I2C_MRX)........................18–23
Master Receive Data Count, I2C (I2C_MRXCNT).... 18–24
Master Status, I2C (I2C_MSTAT).............................. 18–25
Master Transmit Data, I2C (I2C_MTX)..................... 18–28
Misc Clock Settings, CLKG_CLK (CLKG_CLK_CTL0).....
...............................................................................6–26

N
Nonce Bits [127:96], CRYPT (CRYPT_NONCE3)....12–66
Nonce Bits [31:0], CRYPT (CRYPT_NONCE0)........12–63
Nonce Bits [63:32], CRYPT (CRYPT_NONCE1)......12–64
Nonce Bits [95:64], CRYPT (CRYPT_NONCE2)......12–65
Non-maskable Interrupt Clear, XINT (XINT_NMICLR).....
...............................................................................3–13
NUM_VALID_BYTES,CRYPT(CRYPT_CCM_NUM_VALID_BYTES)............12–37

O
Oscillator Control, CLKG_OSC (CLKG_OSC_CTL). 6–20
Oscillator Count, RNG (RNG_OSCCNT)................ 13–10
Oscillator Difference, RNG (RNG_OSCDIFF[n])..... 13–11
Output Buffer, CRYPT (CRYPT_OUTBUF)............. 12–67
Overflow of Output Registers, ADC (ADC_OVF)......20–53

P
Payload Data Length, CRYPT (CRYPT_DATALEN). 12–42
PMG_CTL1 (HPBUCK Control, PMG)......................4–13
PMG_IEN (Power Supply Monitor Interrupt Enable, PMG)...............................................................................4–14
PMG_PSM_STAT (Power Supply Monitor Status, PMG)....
...............................................................................4–17
PMG_PWRKEY (Key Protection for PMG_PWRMOD
and PMG_SRAMRET, PMG)............................... 4–20
PMG_PWRMOD (Power Mode Register, PMG)..........4–21
PMG_RST_STAT (Reset Status, PMG)................. 4–22,7–3
PMG_SHDN_STAT (Shutdown Status Register, PMG).......
...............................................................................4–24
PMG_SRAMRET (Control for Retention SRAM in Hibernate Mode, PMG)........................................... 4–25,9–9
PMG_TRIM (Trimming Bits, PMG)............................ 4–16

PMG_TST_CLR_LATCH_GPIOS (Clear GPIO After
Shutdown Mode, PMG_TST)............................... 4–27
PMG_TST_FAST_SHT_WAKEUP (Fast Shutdown Wakeup Enable, PMG_TST)..........................................4–28
PMG_TST_SCRPAD_3V_RD (Scratch Pad Saved in Battery Domain, PMG_TST)......................................4–29
PMG_TST_SCRPAD_IMG(Scratch
Pad
Image,
PMG_TST)............................................................4–30
PMG_TST_SRAM_CTL (Control for SRAM Parity and Instruction SRAM, PMG_TST)......................... 4–31,9–7
PMG_TST_SRAM_INITSTAT (Initialization Status Register, PMG_TST)...............................................4–33,9–5
Port Configuration, GPIO (GPIO_CFG)........................5–8
Port Data Out Clear, GPIO (GPIO_CLR).................... 5–10
Port Data Output, GPIO (GPIO_OUT).......................5–20
Port Data Out Set, GPIO (GPIO_SET)........................ 5–23
Port Drive Strength Select, GPIO (GPIO_DS)..............5–11
Port Input Path Enable, GPIO (GPIO_IEN).................5–14
Port Interrupt A Enable, GPIO (GPIO_IENA)............. 5–15
Port Interrupt B Enable, GPIO (GPIO_IENB)............. 5–16
Port Interrupt Polarity, GPIO (GPIO_POL)................. 5–22
Port Interrupt Status, GPIO (GPIO_INT).................... 5–18
Port Output Enable, GPIO (GPIO_OEN)....................5–19
Port Output Pull-up/Pull-down Enable, GPIO (GPIO_PE)..
...............................................................................5–21
Port Pin Toggle, GPIO (GPIO_TGL)........................... 5–24
Port Registered Data Input, GPIO (GPIO_IN)............. 5–17
Power Mode Register, PMG (PMG_PWRMOD)..........4–21
Power Supply Monitor Interrupt Enable, PMG (PMG_IEN)...............................................................................4–14
Power Supply Monitor Status, PMG (PMG_PSM_STAT)....
...............................................................................4–17
PRKSTOR
Configuration,
CRYPT(CRYPT_PRKSTORCFG).................................. 12–69
Programmable CRC Polynomial, CRC (CRC_POLY).14–15
PWM0
Control
Register,
TMR_RGB(TMR_RGB_PWM0CTL).................................. 23–17
PWM0
Match
Value,
TMR_RGB(TMR_RGB_PWM0MATCH)........................... 23–18
PWM1
Control
Register,
TMR_RGB(TMR_RGB_PWM1CTL).................................. 23–19
PWM1
Match
Value,
TMR_RGB(TMR_RGB_PWM1MATCH)........................... 23–20
PWM2
Control
Register,
TMR_RGB(TMR_RGB_PWM2CTL).................................. 23–21

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

32

PWM2
Match
Value,
TMR_RGB(TMR_RGB_PWM2MATCH)........................... 23–22
PWM Control Register, TMR (TMR_PWMCTL)..... 22–19
PWM Match Value, TMR (TMR_PWMMATCH).... 22–20

R
Read Control, SPI (SPI_RD_CTL)............................. 15–31
Receive, SPI (SPI_RX).................................................15–33
Receive Buffer Register, UART (UART_RX)............... 17–29
Reference Buffer Low Power Mode, ADC (ADC_CFG1)......
.............................................................................20–28
Reset Status, PMG (PMG_RST_STAT)................. 4–22,7–3
RNG_CTL (RNG Control Register, RNG).................. 13–7
RNG_DATA (RNG Data Register, RNG).....................13–8
RNG_LEN (RNG Sample Length Register, RNG)....... 13–9
RNG_OSCCNT (Oscillator Count, RNG)................ 13–10
RNG_OSCDIFF[n] (Oscillator Difference, RNG)..... 13–11
RNG_STAT (RNG Status Register, RNG)..................13–12
RNG Control Register, RNG (RNG_CTL).................. 13–7
RNG Data Register, RNG (RNG_DATA).....................13–8
RNG Sample Length Register, RNG (RNG_LEN)....... 13–9
RNG Status Register, RNG (RNG_STAT)..................13–12
RS485 Half-duplex Control, UART (UART_RSC).....17–28
RTC_ALM0 (RTC Alarm 0, RTC)............................. 21–24
RTC_ALM1 (RTC Alarm 1, RTC)............................. 21–25
RTC_ALM2 (RTC Alarm 2, RTC)............................. 21–26
RTC_CNT0 (RTC Count 0, RTC).............................21–27
RTC_CNT1 (RTC Count 1, RTC).............................21–28
RTC_CNT2 (RTC Count 2, RTC).............................21–29
RTC_CR0 (RTC Control 0, RTC)..............................21–30
RTC_CR1 (RTC Control 1, RTC)..............................21–34
RTC_CR2IC (RTC Control 2 for Configuring Input Capture Channels, RTC)............................................ 21–37
RTC_CR3SS (RTC Control 3 for Configuring SensorStrobe
Channel, RTC).....................................................21–42
RTC_CR4SS (RTC Control 4 for Configuring SensorStrobe
Channel, RTC).....................................................21–46
RTC_CR5SSS (RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling, RTC)...................21–50
RTC_CR6SSS (RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge, RTC)..........21–52
RTC_CR7SSS (RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity, RTC)......21–55
RTC_FRZCNT (RTC Freeze Count, RTC)................ 21–57
RTC_GPMUX0 (RTC GPIO Pin Mux Control Register 0,
RTC)....................................................................21–58

RTC_GPMUX1 (RTC GPIO Pin Mux Control Register 1,
RTC)....................................................................21–59
RTC_GWY (RTC Gateway, RTC).............................. 21–60
RTC_IC2 (RTC Input Capture Channel 2, RTC).......21–61
RTC_IC3 (RTC Input Capture Channel 3, RTC).......21–62
RTC_IC4 (RTC Input Capture Channel 4, RTC).......21–63
RTC_MOD (RTC Modulo, RTC)..............................21–64
RTC_SNAP0 (RTC Snapshot 0, RTC)....................... 21–84
RTC_SNAP1 (RTC Snapshot 1, RTC)....................... 21–85
RTC_SNAP2 (RTC Snapshot 2, RTC)....................... 21–86
RTC_SR0 (RTC Status 0, RTC)..................................21–87
RTC_SR1 (RTC Status 1, RTC)..................................21–92
RTC_SR2 (RTC Status 2, RTC)..................................21–95
RTC_SR3 (RTC Status 3, RTC)................................21–100
RTC_SR4 (RTC Status 4, RTC)................................21–105
RTC_SR5 (RTC Status 5, RTC)................................21–109
RTC_SR6 (RTC Status 6, RTC)................................21–114
RTC_SR7 (RTC Status 7, RTC)................................21–117
RTC_SR8 (RTC Status 8, RTC)................................21–119
RTC_SR9 (RTC Status 9, RTC)................................21–124
RTC_SS1 (RTC SensorStrobe Channel 1, RTC)......... 21–66
RTC_SS1HIGHDUR (RTC Auto-Reload High Durationfor SensorStrobe Channel 1, RTC)....................... 21–67
RTC_SS1LOWDUR (RTC Auto-Reload Low Duration for
SensorStrobe Channel 1, RTC).............................21–68
RTC_SS1TGT (RTC SensorStrobe Channel 1 Target, RTC).............................................................................21–69
RTC_SS2 (RTC SensorStrobe Channel 2, RTC)......... 21–70
RTC_SS2HIGHDUR (RTC Auto-Reload High Durationfor SensorStrobe Channel 2, RTC)....................... 21–71
RTC_SS2LOWDUR (RTC Auto-Reload Low Duration for
SensorStrobe Channel 2, RTC).............................21–72
RTC_SS2TGT (RTC SensorStrobe Channel 2 Target, RTC).............................................................................21–73
RTC_SS3 (RTC SensorStrobe Channel 3, RTC)......... 21–75
RTC_SS3HIGHDUR (RTC Auto-Reload High Durationfor SensorStrobe Channel 3, RTC)....................... 21–76
RTC_SS3LOWDUR (RTC Auto-Reload Low Duration for
SensorStrobe Channel 3, RTC).............................21–77
RTC_SS3TGT (RTC SensorStrobe Channel 3 Target, RTC).............................................................................21–78
RTC_SS4 (RTC SensorStrobe Channel 4, RTC)......... 21–80
RTC_SSMSK (RTC Mask for SensorStrobe Channel, RTC).
.............................................................................21–81
RTC_SSMSKOT (RTC Masks for SensorStrobe Channels
on Time Control, RTC)....................................... 21–83

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference33

RTC_TRM (RTC Trim, RTC)..................................21–128
RTC Alarm 0, RTC (RTC_ALM0)............................. 21–24
RTC Alarm 1, RTC (RTC_ALM1)............................. 21–25
RTC Alarm 2, RTC (RTC_ALM2)............................. 21–26
RTC Auto-Reload High Duration for SensorStrobe Channel
1, RTC (RTC_SS1HIGHDUR).......................... 21–67
RTC Auto-Reload High Duration for SensorStrobe Channel
2, RTC (RTC_SS2HIGHDUR).......................... 21–71
RTC Auto-Reload High Duration for SensorStrobe Channel
3, RTC (RTC_SS3HIGHDUR).......................... 21–76
RTC Auto-Reload Low Duration for SensorStrobe Channel
1, RTC (RTC_SS1LOWDUR)............................ 21–68
RTC Auto-Reload Low Duration for SensorStrobe Channel
2, RTC (RTC_SS2LOWDUR)............................ 21–72
RTC Auto-Reload Low Duration for SensorStrobe Channel
3, RTC (RTC_SS3LOWDUR)............................ 21–77
RTC Control 0, RTC (RTC_CR0)..............................21–30
RTC Control 1, RTC (RTC_CR1)..............................21–34
RTC Control 2 for Configuring Input Capture Channels,
RTC (RTC_CR2IC)............................................ 21–37
RTC Control 3 for Configuring SensorStrobe Channel,
RTC (RTC_CR3SS).............................................21–42
RTC Control 4 for Configuring SensorStrobe Channel,
RTC (RTC_CR4SS).............................................21–46
RTC Control 5 for Configuring SensorStrobe Channel
GPIO Sampling, RTC (RTC_CR5SSS)............... 21–50
RTC Control 6 for Configuring SensorStrobe Channel
GPIO Sampling Edge, RTC (RTC_CR6SSS).......21–52
RTC Control 7 for Configuring SensorStrobe Channel
GPIO Sampling Activity, RTC (RTC_CR7SSS)...21–55
RTC Count 0, RTC (RTC_CNT0).............................21–27
RTC Count 1, RTC (RTC_CNT1).............................21–28
RTC Count 2, RTC (RTC_CNT2).............................21–29
RTC Freeze Count, RTC (RTC_FRZCNT)................21–57
RTC Gateway, RTC (RTC_GWY).............................. 21–60
RTC GPIO Pin Mux Control Register 0, RTC(RTC_GPMUX0)................................................ 21–58
RTC GPIO Pin Mux Control Register 1, RTC(RTC_GPMUX1)................................................ 21–59
RTC Input Capture Channel 2, RTC (RTC_IC2).......21–61
RTC Input Capture Channel 3, RTC (RTC_IC3).......21–62
RTC Input Capture Channel 4, RTC (RTC_IC4).......21–63
RTC Mask for SensorStrobe Channel, RTC (RTC_SSMSK).
.............................................................................21–81
RTC Masks for SensorStrobe Channels on Time Control,
RTC (RTC_SSMSKOT)...................................... 21–83

RTC Modulo, RTC (RTC_MOD)..............................21–64
RTC SensorStrobe Channel 1, RTC (RTC_SS1)......... 21–66
RTC SensorStrobe Channel 1 Target, RTC (RTC_SS1TGT).............................................................................21–69
RTC SensorStrobe Channel 2, RTC (RTC_SS2)......... 21–70
RTC SensorStrobe Channel 2 Target, RTC (RTC_SS2TGT).............................................................................21–73
RTC SensorStrobe Channel 3, RTC (RTC_SS3)......... 21–75
RTC SensorStrobe Channel 3 Target, RTC (RTC_SS3TGT).............................................................................21–78
RTC SensorStrobe Channel 4, RTC (RTC_SS4)......... 21–80
RTC Snapshot 0, RTC (RTC_SNAP0)....................... 21–84
RTC Snapshot 1, RTC (RTC_SNAP1)....................... 21–85
RTC Snapshot 2, RTC (RTC_SNAP2)....................... 21–86
RTC Status 0, RTC (RTC_SR0)..................................21–87
RTC Status 1, RTC (RTC_SR1)..................................21–92
RTC Status 2, RTC (RTC_SR2)..................................21–95
RTC Status 3, RTC (RTC_SR3)................................21–100
RTC Status 4, RTC (RTC_SR4)................................21–105
RTC Status 5, RTC (RTC_SR5)................................21–109
RTC Status 6, RTC (RTC_SR6)................................21–114
RTC Status 7, RTC (RTC_SR7)................................21–117
RTC Status 8, RTC (RTC_SR8)................................21–119
RTC Status 9, RTC (RTC_SR9)................................21–124
RTC Trim, RTC (RTC_TRM)..................................21–128
RX FIFO Byte Count, UART (UART_RFC).............. 17–27

S
Scratch Buffer, UART (UART_SCR).......................... 17–30
Scratch
Pad
Image,
PMG_TST(PMG_TST_SCRPAD_IMG)............................... 4–30
Scratch Pad Saved in Battery Domain, PMG_TST(PMG_TST_SCRPAD_3V_RD)........................... 4–29
Second Line Control, UART (UART_LCR2)..............17–24
Second Slave Address Device ID, I2C (I2C_ID1)........18–17
Serial Clock Period Divisor, I2C (I2C_DIV)............... 18–15
Serial Wire Debug Enable, SYS (SYS_SWDEN)............. 2–8
SHA Bits [127:96], CRYPT (CRYPT_SHAH3)..........12–73
SHA Bits [159:128], CRYPT (CRYPT_SHAH4)........12–74
SHA Bits [191:160], CRYPT (CRYPT_SHAH5)........12–75
SHA Bits [223:192], CRYPT (CRYPT_SHAH6)........12–76
SHA Bits [255:224], CRYPT (CRYPT_SHAH7)........12–77
SHA Bits [31:0], CRYPT (CRYPT_SHAH0)..............12–70
SHA Bits [63:32], CRYPT (CRYPT_SHAH1)............12–71
SHA Bits [95:64], CRYPT (CRYPT_SHAH2)............12–72

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference

34

SHA Last Word and Valid Bits Information, CRYPT(CRYPT_SHA_LAST_WORD).......................... 12–78
Shared Control, I2C (I2C_SHCTL)............................18–31
Shutdown Status Register, PMG (PMG_SHDN_STAT).......
...............................................................................4–24
Signature, FLCC (FLCC_SIGNATURE)...................... 8–38
Slave Control, I2C (I2C_SCTL)..................................18–29
Slave I2C Status/Error/IRQ, I2C (I2C_SSTAT).......... 18–33
Slave Receive, I2C (I2C_SRX).....................................18–32
Slave Transmit, I2C (I2C_STX).................................. 18–38
SPI_CNT (Transfer Byte Count, SPI)......................... 15–17
SPI_CS_CTL (Chip Select Control for Multi-slave Connections, SPI).............................................................15–18
SPI_CS_OVERRIDE (Chip Select Override, SPI)...... 15–19
SPI_CTL (SPI Configuration, SPI)............................. 15–20
SPI_DIV (SPI Baud Rate Selection, SPI)..................... 15–23
SPI_DMA (SPI DMA Enable, SPI)............................. 15–24
SPI_FIFO_STAT (FIFO Status, SPI).......................... 15–25
SPI_FLOW_CTL (Flow Control, SPI)........................ 15–26
SPI_IEN (SPI Interrupts Enable, SPI)......................... 15–28
SPI_RD_CTL (Read Control, SPI)............................. 15–31
SPI_RX (Receive, SPI).................................................15–33
SPI_STAT (Status, SPI)............................................... 15–34
SPI_TX (Transmit, SPI).............................................. 15–37
SPI_WAIT_TMR (Wait Timer for Flow Control, SPI).........
.............................................................................15–38
SPI Baud Rate Selection, SPI (SPI_DIV).....................15–23
SPI Configuration, SPI (SPI_CTL)............................. 15–20
SPI DMA Enable, SPI (SPI_DMA)............................. 15–24
SPI Interrupts Enable, SPI (SPI_IEN)......................... 15–28
SPORT_CNVT_A (Half SPORT 'A' CNV width, SPORT).
.............................................................................16–45
SPORT_CNVT_B (Half SPORT 'B' CNV width register,
SPORT)............................................................... 16–46
SPORT_CTL_A (Half SPORT 'A' Control Register,
SPORT)............................................................... 16–22
SPORT_CTL_B (Half SPORT 'B' Control Register,
SPORT)............................................................... 16–27
SPORT_DIV_A (Half SPORT 'A' Divisor Register,
SPORT)............................................................... 16–31
SPORT_DIV_B (Half SPORT 'B' Divisor Register,
SPORT)............................................................... 16–32
SPORT_IEN_A (Half SPORT A's Interrupt Enable Register, SPORT)......................................................... 16–33
SPORT_IEN_B (Half SPORT B's Interrupt Enable Register, SPORT)......................................................... 16–35

SPORT_NUMTRAN_A (Half SPORT A Number of Transfers Register, SPORT)...........................................16–37
SPORT_NUMTRAN_B (Half SPORT B Number of Transfers Register, SPORT)...........................................16–38
SPORT_RX_A (Half SPORT 'A' Rx Buffer Register,
SPORT)............................................................... 16–39
SPORT_RX_B (Half SPORT 'B' Rx Buffer Register,
SPORT)............................................................... 16–40
SPORT_STAT_A (Half SPORT 'A' Status register, SPORT).............................................................................16–41
SPORT_STAT_B (Half SPORT 'B' Status register, SPORT).............................................................................16–43
SPORT_TX_A (Half SPORT 'A' Tx Buffer Register,
SPORT)............................................................... 16–47
SPORT_TX_B (Half SPORT 'B' Tx Buffer Register,
SPORT)............................................................... 16–48
Start Byte, I2C (I2C_BYT)..........................................18–14
Status, FLCC (FLCC_STAT)........................................ 8–39
Status, SPI (SPI_STAT)............................................... 15–34
Status, TMR_RGB (TMR_RGB_STAT).....................23–23
Status, TMR (TMR_STAT)........................................ 22–21
Status, WDT (WDT_STAT).......................................24–10
Status Register, CRYPT (CRYPT_STAT).................... 12–79
SYS_ADIID (ADI Identification, SYS)............................2–6
SYS_CHIPID (Chip Identifier, SYS)............................... 2–7
SYS_SWDEN (Serial Wire Debug Enable, SYS)............. 2–8
System PLL, CLKG_CLK (CLKG_CLK_CTL3)..........6–33

T
Temperature Result, ADC (ADC_TMP_OUT).......... 20–59
Temperature Result 2, ADC (ADC_TMP2_OUT)..... 20–58
Third Slave Address Device ID, I2C (I2C_ID2)..........18–18
Time Parameter 0, FLCC (FLCC_TIME_PARAM0)....8–46
Time Parameter 1, FLCC (FLCC_TIME_PARAM1)....8–49
Timer
Event
selection
Register,
TMR_RGB(TMR_RGB_EVENTSELECT).......................... 23–15
Timer Event Selection Register, TMR (TMR_EVENTSELECT)..................................................................22–17
Timing Control Register, I2C (I2C_TCTL)................ 18–39
TMR_ACURCNT (16-bit Timer Value, Asynchronous,
TMR)...................................................................22–11
TMR_ALOAD (16-bit Load Value, Asynchronous, TMR)....
.............................................................................22–10
TMR_CAPTURE (Capture, TMR)............................ 22–12
TMR_CLRINT (Clear Interrupt, TMR).....................22–13
TMR_CTL (Control, TMR).......................................22–14

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference35

TMR_CURCNT (16-bit Timer Value, TMR)............ 22–23
TMR_EVENTSELECT (Timer Event Selection Register,
TMR)...................................................................22–17
TMR_LOAD (16-bit Load Value, TMR).................... 22–18
TMR_PWMCTL (PWM Control Register, TMR)..... 22–19
TMR_PWMMATCH (PWM Match Value, TMR).... 22–20
TMR_RGB_ACURCNT (16-bit Timer Value, Asynchronous, TMR_RGB)................................................. 23–9
TMR_RGB_ALOAD (16-bit Load Value, Asynchronous,
TMR_RGB)...........................................................23–8
TMR_RGB_CAPTURE (Capture, TMR_RGB).........23–10
TMR_RGB_CLRINT (Clear Interrupt, TMR_RGB).23–11
TMR_RGB_CTL (Control, TMR_RGB)................... 23–12
TMR_RGB_CURCNT (16-bit Timer Value, TMR_RGB)...
.............................................................................23–25
TMR_RGB_EVENTSELECT (Timer Event selection Register, TMR_RGB).................................................23–15
TMR_RGB_LOAD (16-bit Load Value, TMR_RGB) 23–16
TMR_RGB_PWM0CTL (PWM0 Control Register,
TMR_RGB).........................................................23–17
TMR_RGB_PWM0MATCH (PWM0 Match Value,
TMR_RGB).........................................................23–18
TMR_RGB_PWM1CTL (PWM1 Control Register,
TMR_RGB).........................................................23–19
TMR_RGB_PWM1MATCH (PWM1 Match Value,
TMR_RGB).........................................................23–20
TMR_RGB_PWM2CTL (PWM2 Control Register,
TMR_RGB).........................................................23–21
TMR_RGB_PWM2MATCH (PWM2 Match Value,
TMR_RGB).........................................................23–22
TMR_RGB_STAT (Status, TMR_RGB).....................23–23
TMR_STAT (Status, TMR)........................................ 22–21
Tone A Data, BEEP (BEEP_TONEA)........................ 19–12
Tone B Data, BEEP (BEEP_TONEB).........................19–13
Transfer Byte Count, SPI (SPI_CNT)......................... 15–17
Transmit, SPI (SPI_TX).............................................. 15–37
Transmit Holding Register, UART (UART_TX)......... 17–32
Trimming Bits, PMG (PMG_TRIM)............................ 4–16
TX FIFO Byte Count, UART (UART_TFC)..............17–31

UART_FBR (Fractional Baud Rate, UART)................17–17
UART_FCR (FIFO Control, UART)..........................17–18
UART_IEN (Interrupt Enable, UART)....................... 17–20
UART_IIR (Interrupt ID, UART)...............................17–21
UART_LCR (Line Control, UART)............................17–22
UART_LCR2 (Second Line Control, UART)..............17–24
UART_LSR (Line Status, UART)................................17–25
UART_RFC (RX FIFO Byte Count, UART).............. 17–27
UART_RSC (RS485 Half-duplex Control, UART).....17–28
UART_RX (Receive Buffer Register, UART)............... 17–29
UART_SCR (Scratch Buffer, UART).......................... 17–30
UART_TFC (TX FIFO Byte Count, UART)..............17–31
UART_TX (Transmit Holding Register, UART)......... 17–32
UART Control Register, UART (UART_CTL)........... 17–15
Upper Page Address, FLCC (FLCC_PAGE_ADDR1)...8–37
User
Clock
GatingControl,
CLKG_CLK(CLKG_CLK_CTL5)............................................ 6–35
User Configuration, FLCC (FLCC_UCFG)..................8–51

U

XINT_CFG0 (External Interrupt Configuration, XINT) 3–7
XINT_CLR (External Interrupt Clear, XINT).............. 3–10
XINT_EXT_STAT (External Wakeup Interrupt Status,
XINT)....................................................................3–11
XINT_NMICLR (Non-maskable Interrupt Clear, XINT).....
...............................................................................3–13

UART_ACR (Auto Baud Control, UART)..................17–11
UART_ASRH (Auto Baud Status (High), UART).......17–13
UART_ASRL (Auto Baud Status (Low), UART)......... 17–14
UART_CTL (UART Control Register, UART)........... 17–15
UART_DIV (Baud Rate Divider, UART)....................17–16

V
Volatile Flash Configuration, FLCC (FLCC_VOL_CFG).....
...............................................................................8–24

W
Wait Timer for Flow Control, SPI (SPI_WAIT_TMR).........
.............................................................................15–38
WDT_CCNT (Current Count Value, WDT)............... 24–5
WDT_CTL (Control, WDT)....................................... 24–6
WDT_LOAD (Load Value, WDT)............................... 24–8
WDT_RESTART (Clear Interrupt, WDT)................... 24–9
WDT_STAT (Status, WDT).......................................24–10
Write Abort Address, FLCC (FLCC_WR_ABORT_ADDR)...............................................................................8–55
Write Address, FLCC (FLCC_KH_ADDR)..................8–33
Write Lower Data, FLCC (FLCC_KH_DATA0)...........8–34
Write Protection, FLCC (FLCC_WRPROT)................ 8–53
Write Upper Data, FLCC (FLCC_KH_DATA1)...........8–35

X

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference36