9th International Symposium on Quality Electronic Design

Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm
CMOS Ring Oscillators and Its Implications in Low Power DFM
Taro Niiyama, Piao Zhe, Koichi Ishida, *Masami Murakata, Makoto Takamiya, andTakayasu Sakurai
University of Tokyo, Japan, *STARC, Japan
Abstract

VDD2
L/W=0.1/0.82

The minimum operating voltage (VDDmin) of 90-nm
CMOS ring oscillators (RO’s) is investigated in order toclarify the lower limit of supply voltage (VDD) for logiccircuits. The measured VDDmin is determined by theintra-die threshold voltage random variations andincreased from 91 mV to 224 mV when the number ofRO stages increased from 11 to 1001, which hinders theVDD scaling. Lowering VDDmin is difficult, since it would
require an impractical inverter-by-inverter adaptive
body bias control. Therefore, the fine-grain adaptive
VDD control will be more effective for the ultra low
voltage logic circuits to reduce the power consumption.

L/W=0.1/0.54
VSS2
VDD2

1V swing

VSS0VVSS2
Ring Oscillator

1. Introduction

Output Buffer(a)

400μm

1mm

Very low voltage operation of VLSI's is effective in
reducing both dynamic and leakage power. Thus manyworks have been carried out on the subthresholdoperation of circuits [1-3], where the supply voltage(VDD) is less than the threshold voltage (VTH) oftransistors. The subthreshold operation of logic circuits
is strongly affected by the variation of VTH. However,systematic measurements of the VDDmin of CMOS logic
circuits made with scaled devices have not beenreported yet.
This paper reports the measured VDDmin variations in
CMOS ring oscillators (RO’s) in 90 nm technology forthe first time. It is shown that VDDmin depends on thenumber of devices in a circuit block. The measurement
results give new insight to the subthreshold logic design
especially from the low power DFM point of view,
because the design margin of VDD is the critical issue.
They also provide a basis for a new approach incharacterizing CMOS logic for the very low voltage
operation and a guideline to determine the circuit blocks
size in fine-grain adaptive body bias and VDD designs.

11-stage
101-stage
1001-stage
Layout(b)Micrograph

Figure 1. CMOS ring oscillators (RO’s). (a)Schematic of the proposed circuits to enable
the VDDmin measurement. (b) Layout andmicrograph.
separated from the VDD and VSS of the output buffer by
the triple well process and VSS2 is manually tuned to theoptimum input level for the output buffer in themeasurement. The inverters in RO have the body bias
terminals. Figure 1(b) shows the layout and themicrograph of the chip fabricated with 1 V 90 nm
CMOS process.

2. Measured VDDmin of 90-nm CMOS RO’s
Figure 1(a) shows the schematic of the proposed RO
circuits to enable the VDDmin measurement. The lowswing output of RO is amplified to 1-V swing by theoutput buffer, because both VDD2 and VSS2 of RO are

0-7695-3117-2/08 $25.00 © 2008 IEEE
DOI 10.1109/ISQED.2008.59

VDD
1VLow swing

133

15

Frequency Variations(= σ / average) (%)

Oscillation frequency (Hz)The chip has three RO’s (11-stage, 101-stage and1001-stage) and its area is 1000μm×400μm. The
smallest size inverter in the primitive cell libraries isused.
10G1G

11-stage

100M
10M

11-stagering oscillators
1010k0.01001-stage

Figure 3. VDD dependence of the inter-die
oscillation frequency variations extracted
from Figure 2.

13 dies
0.2

VDDmin0.4

0.6

VDD (V)0.8

500.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VDD (V)

1M
100k

13 dies

1.0

Number of dies

Figure 2. Measured VDD dependence of theoscillation frequency of 11-stage and1001-stage RO’s.
Figure 2 shows the measured VDD dependence of theoscillation frequency of 11-stage and 1001-stage RO’sfor 13 dies. VDDmin is defined as the supply voltage ( =VDD2−VSS2) when the RO’s stop oscillation and novoltage transitions from the output buffer are observed,
which corresponds to the function errors in logic LSI’s.
It should be noted that VDDmin of 11-stage RO’s is lower
than that of 1001-stage RO’s.
Figure 3 shows the VDD dependence of the inter-die
oscillation frequency variations of 11-stage RO’s
extracted from Figure 2. When VDD is reduced, therelative frequency variations increase [4] because therelative on-current variations of transistors due to thethreshold voltage variations increase. The frequency
variations, for example, increase from 3% to 14%, asVDD is reduced from 1 V to 0.2 V. The large variations
are one of the most serious issues in the subthresholdlogic circuits.
Figure 4 shows the measured distribution of VDDmin ofRO’s with different number of stages. The lowest VDDmin
was 50 mV for the 11-stage RO’s. Average VDDmin of11-stage, 101-stage and 1001-stage RO’s were 91mV,158mV and 224mV, respectively. As the number ofstages is increased, VDDmin increase, because VDDmin isdetermined by the worst inverter(s) in each RO. Theresults indicate that VDDmin for logic circuits depends on
the scale of the circuits and large scale logic circuits
have high VDDmin.

864200864
20086420011-stage

50

100

150200250300350

101-stage

50

100

150200

250

300

350

1001-stage

50

100150200

250300350

VDDmin (mV)
Figure 4. Measured distribution of VDDmin ofRO’s with different number of stages.

3. Analysis of VDDmin with Monte Carlo
Simulations
The VDDmin variations are mainly caused by theintra-die VTH variations. Figure 5(a) shows the measured
position dependence of the intra-die VTH of a 4-mm
4000×1 transistor array [5] with the same 90 nm
technology. Fourier transform of the Figure 5(a) gives
the spatial spectrum shown in Figure 5(b). It doesn’tshow distinctive peaks at particular spatial frequencies,
which indicates that the intra-die VTH variations are notsystematic but purely random across 4 mm [5].
The origin of the VDDmin variations is analyzed with
Monte Carlo SPICE simulations. Figure 6(b) shows thesimulated VDDmin distribution of the 11-stageRO’s(Figure 6(a)) where each transistor has random VTH
determined from the Pelgrom plot provided by thefoundry. Figure 6(c) shows and VTH’s of 22 transistors
in the RO with the highest VDDmin in Figure 6(b). Thehighest VDDmin is caused by a pair of a FS (fast nMOS

134

1

Number of samples

1.2
1.0
0.8
0.6

0.0

4000 transistors
Zero body bias
with 1-μm pitch01000

2000

3000Transistor location(μm)

561001011E-3891011151050050

VDDmin (mV)

1003020100-10 1 2 3 4 5 6 7 8 9 1011
-20-30-40pMOS nMOS-50Inverter number(c)Zero body bias
07(b)4000(a)Power(a.u.)

4(a)

1.4

0.2

3Random VTH

1.6

0.4

2

ΔVTH (mV)
Slow
Fast

Normalized Threshold Voltage

and slow pMOS) inverter and a SF (slow nMOS andfast pMOS) inverter as shown in Figure 6(d). When the#10 inverter has the low input, the high output voltage
level of the #10 inverter is reduced and the #11 inverter
outputs the incorrect high, which stops the RO
oscillation.

0.01#100.1

Spatial frequency(1/μm)(b)Figure 5. Measured intra-die VTH of a 4000×1transistor array [5]. (a) Position dependence. (b)Spatial spectrum.

4. Fine-Grain Adaptive Body Bias Control
to Reduce VDDmin

L#11

Slow HFastFHS (Error)(d)Figure 6. (a) Schematic of the circuit of the11-stage
RO.
(b)
Simulated
VDDmindistribution of the 11-stage RO’s where
each transistor has random VTH. (c) VTH’s of
22 transistors in the RO with the highest
VDDmin. (d) A pair of a FS inverter and a SF
inverter that stops the RO operation.

A higher VDDmin as the number of stages increases isnot acceptable. The fine-grain adaptive body bias
control is an effective technique to compensate for theintra-die systematic VTH variations [6]. Theeffectiveness for the intra-die random VTH variations,however, is not clear. The required circuit block size forthe fine-grain control is also unclear. Therefore, VDDminhas been extracted by simulations for different grain
sizes. Figure 7 shows the initial and compensated VDDminfor the 11-stage RO that demonstrates the highest VDDmin
in Figure 6(b). The body bias of pMOS is adaptively
controlled to minimize VDDmin and the body bias ofnMOS is fixed. When a common body bias is applied to
the 11 inverters(Figure 7(b)), VDDmin is improved from
89 mV to 87 mV. The VDDmin reduction by common
body bias control is also verified by the measurement.

Figure 8 shows the measured VDDmin dependence on
the body bias of both nMOS and pMOS for an 11-stage
RO. When VTH of nMOS and that of pMOS arebalanced, VDDmin is low.
In contrast, when they are unbalanced, VDDmin is high[2-3]. The initial VDDmin is 91mV when both body biases
are 0V. Common body bias control allows to reduce
VDDmin to 87mV, i.e. by 4mV only. This is coherent withthe simulation results and shows that the coarse-grain
body bias control is not effective to significantly reduce
VDDmin. When independent body bias is applied forevery 2 inverters, VDDmin lowers to 85mV as shown inFigure 7(c). In contrast, when inverter-by-inverter body13512345678910011

VDDmin (mV)

VDDmin=89 mV(Initial)(a)

Vb control
1234567891011

VDDmin=87 mV
(b)

Vb1

1

Vb2

234Vb3

5Vb4

67

Vb5

8910Vb6

11

require impractical inverter-by-inverter adaptive bodybias control. Instead, the fine-grain adaptive VDD control
will be more effective for the ultra low voltage logic
circuits.

(c)

Vb3
Vb2

12

Vb5

Vb4
34Vb7
Vb656Vb87

Vb11

Vb98Vb109102.
1. 0 )
1.0 5as (V0.5 0.00.
i
0.0 5 y B
nMOS -0.5 -1.0 -1.5
Body B.0 -0.5 Bod-2ias (V)OSpM

Figure 8. Measured VDDmin dependence of thebody bias of both nMOS and pMOS for a11-stage RO.

VDDmin=85 mV
Vb1

400
350
300
250
200
150
100
50040
40.08080.0120160
200240280320360Acknowledgement
This work is partially supported by STARC. The
VLSI chips were fabricated through the chip fabrication
program of VDEC with the collaboration by STARC.

11VDDmin=43 mV(d)References

Figure 7. Initial and compensated VDDmin by
the various fine-grain adaptive body bias
controls for the 11-stage RO. (a) No bodybias. (b) Common body bias. (c) Body bias
for every 2 inverters. (d) Inverter-by-inverter
body bias.

[1] B. Calhoun, and A. Chandrakasan, "Ultra-dynamic voltage
scaling (UDVS) using sub-threshold operation and local
voltage dithering," IEEE Journal of Solid-State Circuits,Vol. 41, No. 1, pp. 238-245, Jan. 2006.
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[5] D. Levacq, T. Minakawa, M. Takamiya, and T. Sakurai, "Awide range spatial frequency analysis of intra-die
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CMOS," IEEE Custom Integrated Circuits Conference, pp.
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bias is applied, VDDmin is drastically reduced to 43mV as
shown in Figure 7(d). Despite the significant
improvement, the inverter-by-inverter body bias control
is impractical due to large area penalty. Therefore,fine-grain adaptive body bias control is not effective tocompensate the intra-die random VTH variations in ultra
low-voltage logic circuits. Instead, fine-grain adaptive
VDD control should be preferred.

5. Conclusions
Subthreshold behavior of RO’s in 90-nm CMOS has
been investigated. The lowest measured VDDmin was 50
mV for an 11-stage RO. The measured average VDDmin
increased from 91mV to 224mV when the number ofRO stages increased from 11 to 1001, which hinders theVDD scaling. Lowering VDDmin is difficult, because thecompensation of purely random VTH variations would136