Rev: 080317 Prelim

CCVPX66-16AISS8AO4C
12-Channel 16-Bit PMC Analog Input/Output
Conduction-Cooled 3U VPX Module
With Eight Simultaneously-Sampled Inputs at 2.0 MSPS per Channel,
Four Analog Outputs at 1.0 MSPS per Channel,
And 16-Bit Digital I/O Port___________REFERENCE MANUAL**** PRELIMINARY ****____________________________________________________________________________________________
General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com

MAN-CCVPX-16AISS8AO4C

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MAN-CCVPX-16AISS8AO4C

CCVPX-16AISS8AO4C

TABLE OF CONTENTSSECTION

TITLE

PAGE

1.0

INTRODUCTION

1-1

2.0

INSTALLATION AND MAINTENANCE

2-1

2.1

Board Configuration

2-1

2.2

Installation

2-1

2.2.1

Physical Installation

2-1

2.2.2

Input/Output Cable Connections

2-2

2.3
2.3.1

System Configuration

2-3

Analog Inputs

2-3

2.3.1.1

Differential Inputs

2-3

2.3.1.2

Single-Ended Inputs

2-4

2.3.2

Analog Outputs

2-4

2.3.2.1

Output Configurations

2-4

2.3.2.2

Loading Considerations

2-5

2.3.3

External Sync I/O

2-5

2.3.4

Multiboard Synchronization

2-6

2.4

Maintenance

2-7

2.5

Reference Verification

2-7

2.5.1

Equipment Required

2-7

2.5.2

Verification and Adjustment

2-7

3.0

CONTROL SOFTWARE

3-1

3.1

Introduction

3-1

3.2

Board Control Register (BCR)

3-2

3.3

Configuration and Initialization

3-2

3.3.1

Board Configuration

3-2

3.3.2

Initialization

3-2

3.4

Analog Inputs

3-4

3.4.1

Input Modes

3-4

3.4.1.1

System Inputs

3-4

3.4.1.2

Test Modes

3-5____________________________________________________________________________________________
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SECTION

TITLE

PAGE

3.4.2

Active Channel Selection

3-5

3.4.3

Input Ranges

3-5

3.4.4

Sampling Modes

3-6

3.4.4.1

Continuous

3-6

3.4.4.2

Burst Sampling

3-6

3.4.5

Input Data Buffer

3-7

3.4.5.1

Organization

3-7

3.4.5.2

Buffer Size and Threshold Registers

3-8

3.5

Analog Input Buffer DMA Operation

3-8

3.6

Data Coding Formats

3-9

3.7

Rate-A/B Generators

3-9

3.8

Multiboard Synchronization

3-10

3.9

Digital I/O Port

3-11

3.10

Autocalibration

3-11

3.11

Primary Status Register

3-12

3.12

Registered Analog Outputs

3-13

3.12.1

Output Ranges

3-14

3.12.2Clocking Modes

3-14

3.12.2.1

Immediate

3-14

3.12.2.2

Simultaneous

3-14

3.13
3.13.1

Buffered Analog Output Control

3-15

Data Organization

3-16

3.13.1.1

Active Channels

3-16

3.13.1.1.1

Selection

3-16

3.13.1.1.2

Loading

3-16

3.13.1.2

Data Frame

3-18

3.13.1.3

Voltage Range Selection

3-18

3.13.2

Output Buffer

3-18

3.13.2.1

Output Data Format

3-18

3.13.2.2

Output Data Coding

3-19

3.13.2.3

Output Buffer Control

3-19

3.13.2.4

Open Buffer

3-20

3.13.2.5

Circular Buffer

3-20____________________________________________________________________________________________
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CCVPX-16AISS8AO4C`TABLE OF CONTENTS (Continued)
SECTION

TITLE

PAGE

3.13.33.13.3.1
3.13.3.2
3.13.3.3
3.13.43.13.4.1
3.13.4.1.1
3.13.4.1.2
3.13.4.2
3.13.4.3
3.13.53.13.5.1
3.13.5.2
3.13.63.13.6.1
3.13.6.2
3.14
3.14.1
3.14.2
3.14.33.14.43.14.53.14.6
3.15
3.16

Function Generation
Periodic and One-Shot Functions
Multiple Functions
Function Sequencing (Concatenation)
Output Clocking
Clock Source
External Clock
Internal Output Rate Generator
Simultaneous Clocking
Sequential Operation
Sampling Mode
Continuous Sampling
Data Bursts
Multiboard Synchronization
Synchronous Bursts
Synchronous Clocking
Buffered Analog Output Application Examples
Sequential Direct Outputs
Simultaneous Direct (Single Group) Outputs
Continuous Function
Periodic Function
Function Burst
Function Sequencing
Analog Output Buffer DMA Operation
Assembly Configuration Register

3-21
3-21
3-21
3-21
3-23
3-23
3-23
3-23
3-24
3-24
3-24
3-24
3-24
3-25
3-25
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-33
3-34
3-34

3.17

Synchronizing Analog Input Bursts to Analog Outputs

3-35

3.18

Isolating the System Bidirectional Control I/O Pins

3-36

3.19

Analog Input Warp Mode (1.5-2.0MSPS)

3-36

4.0
4.1
4.2
4.3
4.4
4.5
4.6

PRINCIPLES OF OPERATION
General Description
Analog Inputs
Input Data Buffer
Analog Outputs
Autocalibration
Power Control

4-1
4-1
4-2
4-2
4-2
4-2
4-3

App A
App B

Local Register Quick Reference
Migration from PMC66-16AISS8AO4C

A-1
B-1

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LIST OF ILLUSTRATIONSFIGURE

TITLE

PAGE

1.1-1

Functional Organization

1-1

2.2-1

System I/O Connector

2-2

2.3-1

Analog Input Configurations

2-3

2.3-2

Output Configurations

2-4

2.3-3

Line Loss versus Load Current

2-5

2.3-4

Multiboard Synchronization

2-6

2.5-1

Reference Adjustment Access

2-8

3.6-1

Analog Data Coding Formats; 16-Bit Data

3-9

3.13-1

Typical Buffer Loading Sequence

3-16

3.13-2

Open Buffer Data Flow

3-20

3.13-3Circular Buffer Data Flow

3-21

3.13-4

Function Sequencing

3-22

4.1-1

Functional Block Diagram

4-1____________________________________________________________________________________________
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CCVPX-16AISS8AO4C

LIST OF TABLES
TABLE

TITLE

PAGE

2.2-1

System I/O Connector Pin Functions

2-2

2.5-1

Reference Verification Equipment

2-7

3.1-1

Control and Status Registers

3-1

3.2-1

Board Control Register (BCR)

3-3

3.3-1

Configuration Operations

3-4

3.4-1

Input Configuration Register

3-5

3.4-2

Input Data Buffer

3-7

3.4-3

Input Buffer Threshold Register

3-8

3.7-1

Analog Input and Trigger Rate Generator Registers (A, B)

3-9

3.7-2

Input Rate Generator Frequency Selection

3-10

3.9-1

Digital I/O Port Register

3-11

3.11-1Primary Status Register

3-13

3.12-1

Analog Output Channel Data Register

3-13

3.12-2

Simultaneous Output Clock Source Selection

3-14

3.13-1

Summary of Output Control Parameters

3-15

3.13-2

Buffered Output Operations Register

3-17

3.13-3

Analog Output Buffer

3-18

3.13-4

Output Buffer Size Register

3-19

3.13-5

Output Buffer Threshold Register

3-19

3.13-6

Output Sample Rate Control Register (Rate-C)

3-23

3.13-7

Output Sample Rate Selection

3-24

3.14-1

Summary of Operation Examples

3-26

3.14-2

Initial Operations

3-26

3.14-3

Sequential Direct Outputs Example

3-27

3.14-4

Simultaneous Direct Outputs Example

3-28

3.14-5

Continuous Function Example

3-29

3.14-6

Periodic Function Example

3-30

3.14-7

Function Burst Example

3-31

3.14-8Function Sequencing Example

3-33

3.16-1

Assembly Configuration Register

3-34

3.18-1

Ancillary Control Register3-36____________________________________________________________________________________________
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CCVPX-16AISS8AO4C

SECTION 1.0
INTRODUCTION
The 3U VPX module CCVPX-16AISS8AO4C provides 16-bit analog input and output capability
for PMC applications. Eight analog input channels (Figure 1.1-1) are digitized simultaneously at
rates up to 2,000,000 conversions per second per channel, with software-controlled voltage
ranges of ±10V, ±5V or ±2.5V. Digitized input data is buffered through a 256K-sample FIFO.
Four 16-bit analog output channels provide software-selected output ranges of ±10V, ±5V or±2.5V, and are accessed either directly through dedicated control registers, or through a
256K-sample FIFO buffer. The analog output buffer can be clocked at rates up to 1,000,000
output samples per second per channel.
A 16-Bit bidirectional digital port is configurable as two independent byte-wide ports.
The board is designed for minimum off-line maintenance. All functional parameters are undersoftware control, thereby eliminating field-configuration jumpers. A selftest switching networkroutes output channels or calibration reference signals to the analog inputs, and permits board
integrity to be verified by the host.

SystemI/O Conn
Analog Outputs (4)±10V, 5V, 2.5V
Chan-00 of 8 Identical Input Channels
Analog Inputs

Selftest
Switching±10V, 5V, 2.5V

Inputs 01-07

Diff
Amp

16-Bit
ADC

Channels 01 to 07

Voltage
Reference

Input
Data

Input Control

External Clock and Sync I/O
16-BitDAC (4)

Sample-Rate
Generators (3)+5VDC+12VDCPower
Conversion

Local
Controller

Regulated
Power Voltages

PCI Express
Interface
Adapter

Local Bus

Host Conn(PCI Express)

Figure 1.1-1. Functional Organization
This product conforms to the VPX baseline standard ANSI/VITA 46.0-2007 (R2013).
System connections are made at the front panel through a high-density front-panel I/O
connector. Power requirements consist of +12VDC and +5VDC in compliance with the VPX
specification, and operation over the specified temperature range is achieved with standard
conduction cooling.

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1-1

CCVPX-16AISS8AO4C

SECTION 2.0
INSTALLATION AND MAINTENANCE
2.1 Board Configuration
This product has no field-alterable configuration features, and is completely configured at
the factory for field use.
2.2 Installation
2.2.1 Physical Installation
To minimize the opportunity for accidental damage before installation, the board should be
stored in the original protective shipping envelope. System power must be turned OFF
before proceeding with the installation.
CAUTION:

This product is susceptible to damage from electrostatic discharge (ESD).
Before removing the board from the conductive shipping envelope, ensurethat the work surface, the installer and the host board have been properly
discharged to ground.

Before removing the board from the protective shipping envelope, select an empty 6U
expansion slot in the host computer and, if a blank panel is located in the slot position,
remove the panel. Then remove the board from the shipping envelope and insert the board
into the allocated expansion slot, carefully pressing the board firmly to seat the rear-panel
connectors. Secure the panel latches to complete the installation.
2.2.2 Input/Output Cable Connections
System I/O connections are made through the 85-Pin front-panel system I/O connector(Figure 2.2-1), with the pin assignments listed in Table 2.2-1. An acceptable mating cableis Omnetics # MNPO-85-DD-N-EJS-C. Contact Sales for custom cables.

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CCVPX-16AISS8AO4C

Table 2.2-1. System I/O Connector Pin Functions *Pin

SignalPin

43

OUTPUT RTN

---

---

42

OUTPUT RTN

85

ANA OUT 00

41

OUTPUT RTN

84

ANA OUT 01

40

OUTPUT RTN

83

ANA OUT 02

39

OUTPUT RTN

82

ANA OUT 03

38

INPUT RTN

81

INPUT RTN

37

INP00_LO

180

INP00_HI36

INPUT RTN

79

INPUT RTN

35

INP01_LO

1

78

INP01_HI34

INPUT RTN

77

INPUT RTN

33

INP02_LO

2

76

INP02_HI32

INPUT RTN

75

INPUT RTN

31

INP03_LO

2

74

INP03_HI30

INPUT RTN

73

INPUT RTN

29

INP04_LO

1

72

INP04_HI28

INPUT RTN

71

INPUT RTN

27

INP05_LO

1

70

INP05_HI26

INPUT RTN

69

INPUT RTN

25

INP06_LO2

68

INP06_HI2

24

INPUT RTN

67

INPUT RTN

23

INP07_LO

2

66

INP07_HI22

INPUT RTN

65

INPUT RTN

1
2

Signal
PIN 1

PIN 44

PIN 43PWB

PIN 85

1

1

2

2

1

Panel Pin-view
1

2

21

VTEST RTN

64

VTEST

20

INPUT RTN

63

INPUT RTN

19

DIGITAL RTN

62

DIO 0018

DIGITAL RTN

61

DIO 01

17

DIGITAL RTN

60

DIO 02

16

DIGITAL RTN

59

DIO 03

15

DIGITAL RTN

58

DIO 04

14

DIGITAL RTN

57

DIO 05

13

DIGITAL RTN

56

DIO 06

12

DIGITAL RTN

55

DIO 07

11

DIGITAL RTN

54

DIO 08

10

DIGITAL RTN

53

DIO 09

9

DIGITAL RTN

52

DIO 108

DIGITAL RTN

51

DIO 11

7

DIGITAL RTN

50

DIO 12

6

DIGITAL RTN

49

DIO 13

5

DIGITAL RTN

48

DIO 14

4

DIGITAL RTN

47

DIO 15

3

DIGITAL RTN

46

OUTPUT CLK I/O

2

DIGITAL RTN

45

INPUT CLK I/O

1

DIGITAL RTN

44

TRIGGER I/O

Figure 2.2-1. System I/O Connector

System I/O Mating Connector:
System
I/O #Mating
Connector:
Omnetics
MNPO-85-DD-N-EJS-C,
Omnetics# MNPO-85-DD-N-EJS-C,
dual-row,
straight
tail.
dual-row, straighttail.
(Assembled
cables available)(Assembled cables available)

Input Group-A.
Input Group-B.
(4 input-channel modules contain input Channels 00-03).

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2-2

CCVPX-16AISS8AO4C

2.3 System Configuration
2.3.1 Analog Inputs
The eight analog input channels can be configured for either differential or single-ended
operation. The hardware input configuration must be acknowledged by the control
software.
2.3.1.1 Differential Inputs
Differential input operation usually provides the best performance, and is essential when
the input signal sources are not isolated from each other or have returns that are atsignificantly different potentials. A potential difference between grounds is significant if it islarger than the maximum tolerable measurement error.
Differential operation also offers the highest rejection of the common mode noise, which isa characteristic of long cables in typical instrumentation environments. When operating in
the differential mode, shown in Figure 2.3-1a, the wire pair from each signal source isconnected between the HI(+) and LO(-) inputs of a single input channel. The input return(INPUT RTN in Table 2.2-1) is connected to a ground point which ensures that the sum of
the signal level (Vsig) and the common mode voltage (Vcm) remains within the range
specified for the board. Ground current through the INPUT RTN pins must be limited inorder to avoid damage to the cable or the input board.

a. Differential Analog Input

b. Single-ended Analog Input

Figure 2.3-1. Analog Input Configurations____________________________________________________________________________________________
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CCVPX-16AISS8AO4C

2.3.1.2 Single-Ended Inputs
Single-ended operation (Figure 2.3-1b) generally provides acceptable performance only
when the input signal sources either are isolated from each other, or are common to asingle isolated signal return. A single-ended configuration usually is more susceptible tosystem interference than a differential configuration.
Single-ended inputs share a common input return that provides a return path for all inputs,
making isolation from other system grounds a critical issue. If the signal sources are
returned externally to system ground when operating in this mode, a potential difference
between the system ground and input return can cause erroneous measurements, or could
generate potentially destructive ground current.
For applications in which multiple signal sources share a single ground, the differential
configuration is recommended, with all "LO" inputs connected together at the common
remote return.
2.3.2 Analog Outputs
2.3.2.1 Output Configurations
The four analog output channels are single-ended and have a common signal return that isreferred to in Table 2.2-1 as OUTPUT RTN. Single-ended outputs should drive only loads
that have high impedances to system ground. The best results are obtained when theloads are isolated also from each other.
Figure 2.3-2 shows the primary sources of error in both isolated and nonisolated system
configurations. For loads that are isolated from each other (Figure 2.3-2a), the total lineloss error is twice the loss produced in a single line, assuming equal wire size and lengthfor output and return lines. For loads with a common return that is isolated from system
ground, line loss in the common return appears as crosstalk between channels.

OUTPUT BUFFER

Vline
Vdac
Vdac

Rline
Vline
Rline

Rload

Vload = Vdac - 2Vline

Iload

a. Isolated Analog Output

OUTPUT BUFFER

Vline

Vdac

Iload
Rline
Vdac
Vgnd

Ignd

Rgnd

Rload

Vload = Vdac - Vline - Vgnd

REMOTEGROUNDb. Grounded Analog Output (Not recommended)lcaio12app4

Figure 2.3-2. Output Configurations____________________________________________________________________________________________
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CCVPX-16AISS8AO4C

If the load return is connected to a remote system ground (Figure 2.3-2b), the potential
difference Vgnd between the remote ground and the internal signal return will introduce anerror into the signal delivered to the load. The ground current Ignd developed in the returnline is limited essentially only by Rgnd, and can damage the cable or the board if notcontrolled.
2.3.2.2 Loading Considerations
The voltage drop in the system I/O cable can be a significant source of error, especiallywith relatively long cables driving moderate or heavy loads. Figure 2.3-3 shows the effectof load current on the voltage drop in copper wire of various sizes. A 4.0 milliamp load forexample, inserts a voltage drop of more than 0.25 millivolt per foot in #28 AWG ribbon
cable; twice that if the return line also is considered. Several feet of ribbon cable therefore
can produce significant errors, especially in a 16-bit system, in which 1 LSB can represent
only 76 microvolts on a ±2.5 Volt range. High impedance loads generally do not produce
significant DC errors.

Figure 2.3-3. Line Loss versus Load Current
2.3.3 External Sync I/O
The INPUT CLK I/O and OUTPUT CLK I/O pins in the system connector are bidirectional
TTL synchronization signals that provide external control of analog input sampling andanalog output clocking, respectively. The TRIGGER I/O pin also is bidirectional, and isshared by the analog inputs and outputs. Specific input/output configurations are
determined by individual system requirements, and must be acknowledged by the control
software.

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CCVPX-16AISS8AO4C

When a board is software-configured as an Initiator, these I/O signals are outputs that canbe used to control multiple Target boards. Each clock or trigger event output consists ofan 80-130 nanosecond TTL pulse, asserted LOW.
Output loading in the Initiator
configuration should be limited to 10 milliamps or less. The analog inputs, analog outputs
and triggering all can be configured independently as either initiators or targets.
For Target boards, the I/O signals become inputs and can synchronize input and output
operations to an Initiator board. Clock and trigger inputs are edge-detected on the negative(falling) edge, and must be asserted for at least 60 nanoseconds in order to beacknowledged. All three inputs are asserted LOW, and are pulled up internally to +5V
through approximately 33 KOhms.
NOTE: The OUTPUT CLK I/O, INPUT CLK I/O and TRIGGER I/O pins in the I/O
connector should either be left open or pulled to a digital HIGH level if notused. If used, the pins should be pulled HIGH normally, and asserted LOW
when active.

2.3.4 Multiboard Synchronization
If multiple boards are to be synchronized together, the INPUT CLK I/O, TRIGGER I/O andOUTPUT CLK I/O pins from one board, the initiator, are connected to the corresponding
pins of as many as four target boards in the same backplane (Figure 2.3-4).
The
controlling software determines specific synchronization functions.

Target Board #1

Input
Clk I/O

Trigger
I/O

OutputClk I/O

Target Board #2
TriggerInput
I/O
Clk I/O

OutputClk I/O

Initiator Board
Input Clk I/O
To Additional
Target Boards

Trigger I/O
Output Clk I/O(DAC Control)

Figure 2.3-4. Multiboard Synchronization____________________________________________________________________________________________
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CCVPX-16AISS8AO4C

2.4 MaintenanceThis product requires no scheduled maintenance other than periodic verification andpossible adjustment of the internal voltage reference. The optimum verification interval willvary with upon the specific application, but in most instances an interval of one year should
be sufficient.
In the event of a suspected malfunction, all associated system parameters, such as power
voltages, control bus integrity, and system interface signal levels, should be evaluatedbefore troubleshooting of the board itself is attempted. A board that has been determined
to be defective should be returned to the factory for detailed problem analysis and repair.

2.5 Reference Verification
All analog channels are software-calibrated to a single internal voltage reference by anembedded autocalibration utility. The procedure presented here describes the verification
and adjustment of the reference.

2.5.1 Equipment Required
Table 2.5-1 lists the equipment required for verifying or adjusting the internal reference.
Alternative equivalent equipment may be used.
Table 2.5-1. Reference Verification Equipment
Equipment Description

Manufacturer

Model

Digital Multimeter, 5-1/2 digit, 0.005%
accuracy for DC voltage measurements at±10 Volts. Input impedance 10 Megohms
or greater.

Hewlett Packard

34401A

3U VPX Host assembly(Existing host)

---

---

---

Test cable; suitable for connecting thedigital multimeter to the system I/O
connector.

2.5.2 Verification and Adjustment
The following procedure describes the verification of the internal voltage reference.
Adjustment of the internal reference, if necessary, is performed with an internal trimmer thatis accessible as shown in Figure 2.5-1.

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2-7

CCVPX-16AISS8AO4C

P3

System I/OPowerConversion

P0

P1

Analog Components

Digital Control
Ref Adj
AccessRepresentive illustration; Details may vary.

Figure 2.5-1. Reference Adjustment AccessThis procedure assumes that the PMC is installed on a host board, and that the host is
installed in a system.
1.

Connect the digital multimeter between the VTEST pin (+), and the VTEST RTN
pin (-) in the System I/O connector.

2.

If power has been removed from the board, apply power now. Wait at least 10
minutes after power is applied before proceeding..

3.

Verify that the digital multimeter indication is +9.9000 VDC ±0.0015 VDC. If theindication is not within this range, adjust the internal reference trimmer for an
in-range digital multimeter indication.

4.

Verification and adjustment is completed. Remove all test connections.

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2-8

CCVPX-16AISS8AO4C____________________________________________________________________________________________
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2-9

CCVPX-16AISS8AO4C

SECTION 3.0
CONTROL SOFTWARE
3.1 Introduction
The CCVPX-16AISS8AO4C board is compatible with the PCI Express Local Bus specification
Revision 1.0a, and a PLX PEX-8311 adapter controls the bus interface. Configuration-spaceregisters are initialized internally to support the location of the board on any 32-longword
boundary in memory space. After initialization is completed, communication between the PCI
Express bus and the local bus takes place through the control and data registers listed in Table
3.1-1. All data transfers are long-word D32. DMA access is supported for data transfers fromthe analog input buffer and to the analog output data buffers. To ensure compatibility withsubsequent controller revisions, reserved control bits should be written LOW (zero), andmaintenance registers should not be modified.
Table 3.1-1. Control and Status Registers
Offset(Hex)

Register

Mode1

Default

Primary Function

Ref

0000

BOARD CONTROL

RW

2202 00A0h

Board Control Register (BCR).

3.2

0004

DIGITAL I/O PORT

RW

00XX 00XXh

16-Bit Digital I/O port data.

3.9

0008

ANALOG OUTPUT CHAN 00

RW0000 8000h

Output Channel 00 data.

3.12

000C

ANALOG OUTPUT CHAN 01

RW

0000 8000h

Output Channel 01 data.

3.12

0010

ANALOG OUTPUT CHAN 02

RW

0000 8000h

Output Channel 02 data.

3.12

0014

ANALOG OUTPUT CHAN 03

RW0000 8000h

Output Channel 03 data.

3.12

0018

ANALOG INPUT BUFFER

RO

00XX XXXXh

Analog input buffer data.

3.4.5

001C

RATE GENERATOR A

RW

0000 00C8h

Rate-A generator divider; 24 bits.

3.7

0020

RATE GENERATOR B

RW

0000 3E80h

Rate-B generator divider; 24 bits.

3.7

0024

INPUT CONFIGURATION

RW

FF00 0400h

Analog inputs channel-mask andburst-size.

3.4.2

0028

INPUT BUFFER SIZE

RO

0000 0000h`

Number of data values in the input
buffer.

3.4.5.2

002C

INPUT BUFFER THRESHOLD

RW

0003 FFFEh

Input buffer status flag threshold.

3.4.5.20030

PRIMARY STATUS

RW

0000 0X00h

Principal status-flag register

3.11

0034

ASSEMBLY CONFIGURATION

RO

000X XXXXh

Options and firmware revision.

3.16

RW

0000 XXXXh

Autocal value readback.

---

2

0038

Autocal Values

003C

BUFFERED OUTPUT OPERATIONS

RW

0000 104Fh

Buffered Analog Outputs Control

3.13.2.30040

OUTPUT BUFFER THRESHOLD

RW

0003 FFFEh

Output buffer status flag threshold.

3.13.2.30000 0000h

Number of data values in the output
buffer.

3.13.2.3

0044

OUTPUT BUFFER SIZE

RO

0048

ANALOG OUTPUT BUFFER

WO

0000 0000h

Analog Output Data Buffer.

004C

RATE GENERATOR C

RW

0000 00C8h

Rate-C generator divider; 24 bits.

3.13.4.1.20050005C(Auxiliary Registers)

RW

0000 0000h

Four auxiliary 32-Bit user registers.

---

0060

ANCILLARY CONTROL

R/W

0000 0000h

I/O Isolation and ADC Warp mode

3.18, 3.190064007C(Reserved)

---

---

Notes:

3

3.13.2---

1. RW = Read/Write, RO = Read-Only, WO = Write-Only.
2. Maintenance register; Shown for reference only.
3. Firmware Revisions 0102 and higher. These auxiliary registers have no internal functions.

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CCVPX-16AISS8AO4C

3.2 Board Control Register (BCR)
Basic board functions such as initialization, autocalibration and input/output range selection arecontrolled through the board control register (BCR) shown in Table 3.2-1. Specific control bits
are cleared automatically after the associated operations have been completed. Read-only
status flags indicate the states of specific operational functions.
3.3 Configuration and Initialization
3.3.1 Board Configuration
During board configuration, initial values for both the PCI configuration registers and the internal
control logic are extracted from internal nonvolatile read-only memory. This process is initiatedby a PCI Express bus reset, and should be required only once after the initial application of
power. While the PCI configuration registers are being loaded, the response to PCI target
accesses is RETRY's.
Configuration operations are executed in the sequence shown in
Table 3.3-1.
Loading of the PCI Express configuration registers is completed within 3 milliseconds after theassertion of a PCI Express bus reset.
3.3.2 Initialization
Internal control logic can be initialized without invoking a full reconfiguration by setting the
INITIALIZE control bit HIGH in the BCR. This action initializes the internal logic, but does notaffect the configuration registers and does not reconfigure the internal control logic. Initialization
requires 3 milliseconds or less for completion, and produces the following default conditions: The BCR is initialized; all register defaults are invoked. (Paragraph 3.3).
 Analog input and output data coding is offset binary. (3.6).
 All analog input and output channels are active. (3.4.2, 3.13.1.1.1).
 Analog input and output ranges are ±10V. (3.4.3, 3.13.1.3).
 External clock and trigger signals are in the target (Input) mode. (3.8, 3.13.6).
 The input and output buffers are reset to empty. (3.4.5.1, 3.13.2.3).
 Analog Inputs:
 Input channels are differential. (3.4.1.1).
 Sample clocking is from the Rate-A generator; Bursting is disabled. (3.4.4.2, 3.7).
 The ADC (Rate-A) generator is adjusted to 320 kHz, and is disabled. (3.7),
 The analog input buffer is reset to empty; buffer threshold is 3FFFEh. (3.4.5).
 Burst block size is 1024 (0400h). (3.4.4.2).
 Analog Outputs:
 Analog outputs are at midrange (zero). (3.13.1.1).
 Direct-Register access is selected. (3.12).
 The DAC (Rate-C) generator is adjusted to 320 kHz, and is disabled. (3.13.4.1.2).
 The burst-trigger (Rate-B) generator is adjusted to 4 kHz, and is disabled. (3.7)
 The digital I/O port is configured as two input bytes. (3.9).

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CCVPX-16AISS8AO4C

Table 3.2-1. Board Control Register (BCR)
Offset: 0000h

Default: 2202 00A0h

Mode 1

Bit

DesignationDef

D00-D02RW

ANALOG INPUT MODE

D03

RW

ANALOG INPUTS AUTOCAL

0

2

0

D04-D05RW

INPUT RANGE A

2

D06-D07

RW

INPUT RANGE B

2

D08

RW

INPUT S/W CLOCK

D09
D10

RW
RO

ENABLE INPUT BURSTINPUT BURST BUSY

0
0

D11

RW

INPUT S/W TRIGGER

2

0

D12
D13

RW
RW

ENABLE INPUT BUFFER
2
CLEAR INPUT BUFFER

D14

RO

INPUT BUFFER THRESHOLD FLAG

D15

RW

INPUT BUFFER OVERFLOW

0

D16-D17RW

OUTPUT RANGE

2

D18

RW

SIMULTANEOUS OUTPUTS

0

D19

RW

ENABLE BUFFERED OUTPUTS

0

D20

RW

OUTPUT S/W CLOCK

D21

RW

TRIGGER INITIATOR

0

D22

R/W

ENABLE RATE-C GENERATOR

0

D23

R/W

INPUT BUFFER UNDERFLOW

0

D24

RW

ANALOG INPUT CLK INITIATOR

0

D25

RW

OFFSET BINARY

1

D26
D27

RW
RW

ENABLE RATE-A GENERATORENABLE RATE-B GENERATOR

0
0

D28

RW

AUTOCAL

D29

RO

AUTOCAL PASS

1

D30

R/W

SWAP DEMAND MODE CHANNELS

0

D31

RW

INITIALIZE

2

0
0

2,3

0

2

2

Notes: 1. RW = Read/Write, RO = Read-Only.

0

0

0

Initiates an analog-inputs autocalibration operation.

3.10

2. Clears automatically.

3. Duplicated elsewhere____________________________________________________________________________________________
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3-3

Ref

3.4.1

Analog input Range-A; Channels 00, 01, 04, 05:
0 => ±2.5V
2 => ±10V
1 => ±5V
3 => (Reserved)
Analog input Range-B; Channels 02, 03, 06, 07:
0 => ±2.5V
2 => ±10V
1 => ±5V
3 => (Reserved)
Initiates a single sample of active input channels.
Overrides existing input clocking source.
Enables triggered burst input acquisition.
HIGH when a triggered input burst is in progress.
Initiates a single input data burst. Overrides
existing burst triggering source.
Enables the analog input buffer for accepting data.
Clears (empties) the analog input data buffer.
HIGH when the number of values in the input buffer
exceeds the selected buffer threshold.
Set HIGH if the input buffer overflows. Stays HIGH
until cleared from the bus or by a board reset.
Analog Output Voltage Range:
0 => ±2.5V
2 => ±10V
1 => ±5V
3 => (Reserved)
When HIGH, all outputs update simultaneously inresponse to an output clock. When LOW, each
output is updated immediately when new data isreceived.
When HIGH, enables the analog output FIFO
buffer, and disables the analog output registers
ANALOG OUTPUT CHAN xx.
Produces a single analog output clock. Overrides
existing output clocking source.
Configures the shared analog input/output
hardware trigger pin as an output if HIGH, or as an
input if LOW.
Enables the Rate-C generator for analog outputs.
Set HIGH if the input buffer underflows. Stays
HIGH until cleared from the bus or by a board
reset.
Configures the analog input I/O clock as an output
if HIGH, or as an input if LOW.
Selects offset-binary analog I/O data format when
HIGH, or two's complement when LOW.
Enables the Rate-A generator for analog inputs.
Enables the Rate-B generator for triggered bursts.
Initiates an autocalibration operation whenasserted. Clears automatically upon completion,
Set HIGH at reset or autocal initialization. A HIGH
state after autocal confirms a successful
calibration.
Reverses the default demand-mode DMA channels
for analog inputs and outputs
Initializes the board. Sets all register defaults.

03

Description
Analog input mode:
0 => Differential system inputs
1 => Single-ended system inputs
2 => Zero selftest
3 => VREF selftest
4 => Output Channel 00
5 => Output Channel 01
6 => Output Channel 02
7 => Output Channel 03

3.4.3

3.4.3
3.4.4
3.4.4.2
3.4.4.2
3.4.4.2
3.4.5.1
3.4.5.1
3.4.5.2
3.4.5.1
3.12.1
3.13.1.3
3.12.2.2
3.13.4.2
3.12
3.13
3.12.2.2
3.13.4.1
3.4.4.2
3.13.4.1.2
3.4.5.1
3.4.4
3.6
3.7
3.7
3.10
3.10
3.5
3.15
3.3.2

CCVPX-16AISS8AO4C

Table 3.3-1. Configuration Operations
Operation

Maximum Duration

PCI Express configuration registers are loaded from internal ROM
Internal control logic is configured from internal ROM
Internal control logic is initialized

3 ms
300 ms
3 ms

3.4 Analog Inputs
Each of eight analog input channels can be digitized simultaneously with 16-bit resolution at
rates from DC to 2 Megasamples per second. Data from any combination of inputs can beacquired in a 256 Ksample buffer, and a tag-bit is attached to the first (lowest-numbered) active
channel data values. Three voltage ranges are available, and any two of these ranges can beused simultaneously on different channels. Each input channel contains a dedicated 16-Bit
ADC.
All active inputs are sampled simultaneously, and the sample clock can be derived: (a) from aninternal rate generator, (b) from an external hardware clock input, or (c) directly from the bus.
To illustrate the requirements for initiating analog input acquisition directly after board
initialization, setting the following control bits HIGH simultaneously in the BCR would starteight-channel acquisition using the Rate-A generator at the default sample rate: ANALOG INPUT CLK INITIATOR; Selects the analog input clock initiator mode, ENABLE INPUT BUFFER; Enables the analog input buffer,
 ENABLE RATE-A GENERATOR: Enables the Rate-A generator.
3.4.1 Input Modes
An input switching network routes either the system input signals or internal test signals throughthe input channels, and is controlled by the ANALOG INPUT MODE control field in the BCR.
The system inputs are disconnected when internal signals are monitored, and have no effect on
test results.
3.4.1.1 System Inputs
Of the eight possible input modes available through the ANALOG INPUT MODE field, two are
dedicated to system inputs. In the differential configuration, the signal present between the HI
and LO inputs in each channel is acquired. For a single-ended input, the input signal ismeasured between the HI input and the input return, and the LO input is ignored. The selected
system input configuration must agree with the system wiring configuration (Paragraph 2.3).

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3.4.1.2 Test Modes
Internal analog nodes can be monitored to verify the functional integrity of the board. The
selected input ranges apply in all input modes, including test modes. The following signals arepresent in all input channels when the indicated test modes are selected:
Zero Selftest:

Midscale value, ideally equal to 0.000 VDC,

VREF Selftest:

Internal voltage reference, ideally equal to +99.00 percent of theselected analog output range *,Output Channels:

Any of the four analog output channels.

* The VREF Selftest source and the Output DAC's share a common reference.
3.4.2 Active Channel Selection
Input channels are designated as active by setting the corresponding ENABLE CHANNEL XX
control bit HIGH in the Input Configuration register (Table 3.4-1), or as inactive by clearing the
bit LOW. All active inputs are sampled simultaneously when a sample clock occurs. Inactive
channels produce no data in the input buffer.
Table 3.4-1. Input Configuration Register
Offset: 0024h

Default: FF00 0400h

Bit

Mode

DesignationDef

D00-D23RW

BURST BLOCK SIZE

0400h

D24

RW

ENABLE INPUT 00

1

D25

RW

ENABLE INPUT 01

1

D26

RW

ENABLE INPUT 02

1

D27

RW

ENABLE INPUT 03

1

D28

RW

ENABLE INPUT 04

1

D29

RW

ENABLE INPUT 05

1

D30

RW

ENABLE INPUT 06

1

D31

RW

ENABLE INPUT 07

1

Description
Number of active channel sets acquired during a
triggered burst.
Analog input channel selection mask.

3.4.3 Input Ranges
Input voltage ranges of ±10V, ±5V and ±2.5V are assigned independently to two groups of input
channels by the INPUT RANGE A and INPUT RANGE B control fields in the BCR:
Range A:

Input channels 00, 01, 04, 05,

Range B:

Input channels 02, 03, 06, 07.

Note: Voltage levels outside the selected ranges will produce saturation codes of plus orminus fullscale, but will not damage the inputs if they are within the range indicatedin the product specification for overvoltage protection.

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3.4.4 Sampling Modes
All active channels are sampled at each occurrence of the analog input sample clock. If the
ANALOG INPUT CLK INITIATOR control bit is HIGH in the BCR, input sample clocks aresupplied by either the Rate-A generator or by the INPUT S/W CLOCK control bit in the BCR.
The INPUT S/W CLOCK control bit always produces an input clock, regardless of the state of
the Rate-A generator or the INITIATOR control bit. In the Initiator mode, each sample clock
produces a 100 nanosecond LOW output pulse at the bidirectional INPUT CLK I/O pin in thesystem I/O connector.
If the INITIATOR control bit is LOW, designating the board as a Target, the INPUT CLK I/O pin
becomes an input, and a sample clock is generated for each HIGH-to-LOW transition received
at the pin. The Rate-A generator is ignored in the target clocking mode.
To avoid contention among multiple boards that are interconnected for multiboard synchronous
operation, the INITIATOR control but defaults LOW to target mode.
3.4.4.1 Continuous
During continuous sampling, all active input channels are sampled continuously as long as aclock source is present. Continuous sampling is selected when the ENABLE INPUT BURST
control bit is LOW in the BCR.
3.4.4.2 Burst SamplingIf burst sampling is enabled by setting the ENABLE INPUT BURST control bit HIGH in the BCR,
an input trigger initiates the acquisition of a specific number of samples for each active channel.
During a burst, sampling proceeds at the selected input sample rate until the specified numberof samples has been acquired, and then terminates until a subsequent trigger occurs. The
number of samples acquired during a triggered burst is specified by the
24-Bit BURST BLOCK SIZE control field in the Input Configuration register (Table 3.4-1). The
value in this field is the number of samples acquired for each active channel, and the total
number of samples acquired equals this value times the number of active channels.
Note: If a BURST BLOCK SIZE of zero is selected while bursting is enabled, a burst
trigger initiates a nonterminating burst that continues until (a) the sample clock isdisabled, (b) input bursting is disabled, or (c) BURST BLOCK SIZE becomes
nonzero.
The END OF BURST status bit in the input buffer (Paragraph 3.4.5) is set HIGH for the last
input value acquired in a burst. The INPUT BURST BUSY status flag in the BCR is HIGH
during each triggered burst, and is LOW otherwise. Input triggering cannot occur when
INPUT BURST READY is LOW.
If the TRIGGER INITIATOR control bit in the BCR is HIGH, the board is a trigger initiator, and aburst trigger is provided either by the Rate-B generator or by the INPUT S/W TRIGGER control
bit in the BCR. The INPUT S/W TRIGGER bit always produces a burst trigger, regardless of thestate of the Rate-B generator or the INITIATOR control bit. In the Initiator mode, each burst
trigger produces a 100 nanosecond LOW output pulse at the bidirectional TRIGGER I/O pin in
the system I/O connector.
If the TRIGGER INITIATOR control bit is LOW (default), indicating Target Mode, the
TRIGGER I/O pin becomes an input, and a trigger is generated for each HIGH-to-LOWtransition received at the pin. The Rate-B generator is ignored in the target clocking mode, but
the INPUT S/W TRIGGER control bit remains active.
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CCVPX-16AISS8AO4C
NOTE: If TRIGGER INITIATOR is HIGH (initiator mode), the TRIGGER I/O pin is an output andproduces a trigger pulse in response to either an input trigger or an output trigger(3.13.5.2). If the control bit is LOW (target mode), an input HIGH-to-LOW transition at the
TRIGGER I/O pin produces either an input or output trigger if either is enabledindividually, or inputs and outputs simultaneously if both are enabled.

3.4.5 Input Data Buffer
3.4.5.1 Organization
Analog input data accumulates in the input data FIFO buffer until extracted by the PCI Express
bus. The buffer has a capacity of 256K total samples, and contains a 16-bit data field, a 1-bit
tag field, and an END OF BURST status bit (Table 3.4-2). Analog input data is right-justified to
the LSB, and occupies bit positions D00 through D15.
NOTE: The input buffer capacity of 256 K-Samples is distributed among all active input
channels. The capacity in samples-per-channel is:
Sample Capacity per Channel = 256K / Number of active channels.
The channel tag identifies the first (lowest-numbered) active channel in each active channel-set.
Reserved bits are always returned as zeros. The END OF BURST (EOB) status bit identifies
the last data value in an input burst or function.
Table 3.4-2. Input Data Buffer
Offset: 0018h
Data Bit
D00

Default: 00XX XXXXhDesignation

Description

DATA00

Data value least significant bit (LSB)

DATA01 - DATA14

Data value intermediate bits

D15

DATA15

Data value most significant bit (MSB)

D16

FIRST-CHANNEL TAG

Tag assigned to first (lowest-numbered) active channel.

D17

END OF BURST (EOB)

Identifies the last input value in a burst.

(Reserved)

Always zero.

D01-D14

D18-D31

In order for the input buffer to acquire input data, the ENABLE INPUT BUFFER control bit must
be set HIGH in the BCR. The buffer can be cleared, or emptied, by writing a "one" to the
CLEAR INPUT BUFFER control bit in the BCR. The CLEAR INPUT BUFFER bit clears
automatically. An empty buffer returns an indeterminate value.
The INPUT BUFFER OVERFLOW status bit in the BCR is set HIGH if the buffer overflows,
thereby indicating data loss. The INPUT BUFFER UNDERFLOW bit is set HIGH if the buffer
underflows (underruns), indicating that indeterminate data was acquired from an empty buffer.
Each status bit remains HIGH until cleared, either directly from the bus, by the
CLEAR INPUT BUFFER control bit, or by a board reset.

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3.4.5.2 Buffer Size and Threshold Registers
The Input Buffer Size control register listed in Table 3.1-1 contains the total number of data
values present in the input buffer. The Input Buffer Threshold register (Table 3.4-3) specifies
the buffer size value above which the INPUT BUFFER THRESHOLD FLAG is asserted HIGH.
The threshold flag is duplicated in the BCR.
Table 3.4-3. Input Buffer Threshold Register
Offset: 002Ch
Data Bit

Default: 0003 FFFEh

Mode

DesignationDef

Description
Specifies the number of values in the
input buffer, above which the threshold
flag is asserted HIGH.

D00-D18RW

INPUT BUFFER THRESHOLD

3 FFFEh

D19

RO

INPUT BUFFER THRESHOLD FLAG 10

HIGH when the number of values in the
input buffer exceeds the specified buffer
threshold.

D20-D31

RO

Reserved

0---

1. Duplicated in the BCR.

3.5 Analog Input Buffer DMA Operation
DMA transfers from the analog input FIFO buffer are supported in either block-mode or
demand mode, with the board operating as bus master. Demand mode operation requires theslow terminate mode. Refer to the PEX-8311 reference manual for a detailed description of theassociated DMA configuration registers.
NOTE: The PEX-8311 adapter extracts data from the 32-Bit (Lword) local bus in 64-Bit(quad-word) increments. Consequently, if the buffer runs empty or nearly empty,
the situation can arise in which the last one or two samples in an active channelgroup are retained until subsequent data is acquired by the host. If this occurs,
the next sample set flushes the retained data through the PEX-8311 adapter tothe PCI Express bus, and no samples are lost.
NOTE: The default analog input DMA channel for demand-mode operation is Channel 00.
To operate in DMA Channel 01, set the SWAP DEMAND MODE CHANNELS control
bit HIGH in the BCR and use the Channel 01 PCI express registers.

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3.6 Data Coding Formats
Analog input and output data is arranged as 16 active right-justified data bits with the coding
conventions shown in Figure 3.6-1. The default format is offset binary. Two's complement
format is selected by clearing the OFFSET BINARY control bit LOW in the BCR. Unlessindicated otherwise, offset binary coding is assumed throughout this document.

Input / Output CodeDATA CODE:
OFF BIN 2'S COMPPOS Fullscale

te
er
v
n
Co

0xFFFF
0xFFFE

0x7FFF
0x7FFE0x80010x80000x7FFF

0x00010x0000
0xFFFF

0x00010x00000x80010x8000

e
ns
po
s
e
rR

Input / Output Voltage

MID Scale

NEG Fullscale

Figure 3.6-1. Analog Data Coding Formats; 16 Bit Data
3.7 Rate-A/B Generators
Two rate generators supply independent clock frequencies from 3 Hz to 2.000 MHz. The Rate-A
Generator shown in Table 3.7-1 generates an internal sample clock for the analog inputs. The RateB generator output can be used as a trigger source for input burst acquisition.
NOTE: For sample rates above 1.5MSPS, the ADC WARP MODE control bit in the Ancillary
Control register must be set HIGH (Paragraph 3.19).
Each generator is enabled by the associated ENABLE RATE-A/B GENERATOR control bit in the
BCR. The generators are disabled when these bits are LOW.

Table 3.7-1. Analog Input and Trigger Rate Generator Registers (Rate-A,B)
Offset: 001Ch (Rate-A), 0020h (Rate-B)

Default: 0000 00C8 (Rate-A), 0000 3E80h (Rate-B)

Data Bit

Mode

DesignationDef

D00-D23

R/W

Ndiv

---

Rate generator frequency control

D24-D31

RO(Inactive)0---

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The frequency Fgen (Table 3.7-2) of each generator is calculated as:Fgen = Fclk / Ndiv,
where Fclk is the master clock frequency for the board, and Ndiv is the value written to theRate-A/B Generator register. Fgen and Fclk are both expressed in the same frequency units. For
simplicity, Fclk is assumed here to be 64.000MHz, but is an ordering option and can have any value
close to this frequency. The actual value for Fclk is identified in the Assembly Configuration register
shown in Section 3.16.

Table 3.7-2. Input Rate Generator Frequency Selection
Ndiv

FREQUENCY Fgen
(64 MHz Master Clock)*

(Dec)

(Hex)

(kHz)

32

20

2000.00

33

21

1939.39---

Fgen (Hz) = Fclk (Hz) / Ndiv--* ±0.003 percent.

3.8 Multiboard Synchronization
Analog input and output clocking and triggering can be synchronized among multiple boards bydesignating one of the boards as an initiator, and the remaining boards as targets. In order toimplement this function, the boards must be connected together as described in Paragraph 2.3.4.
When multiple boards are configured as an initiator and multiple targets, the analog input clock, theanalog input trigger, and the analog output clock generated in the initiator board are duplicated in thetarget boards with delays of less than 100 nanoseconds.

All boards default to the target mode, with the ANALOG INPUT CLK INITIATOR and
TRIGGER INITIATOR control bits cleared LOW in the BCR. To designate a board as a clock or
trigger initiator, set the associated control bit HIGH.
NOTE: To avoid contention among boards that are wired in an initiator/target
configuration, ensure that all target boards have been designated before
initiating clocking operations.

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3.9 Digital I/O PortThe 16-Bit bidirectional digital I/O port consists of two independent data bytes, as shown in
Table 3.9-1. Data fields DIO BYTE 00 and DIO BYTE 01 represent the 16 digital I/O pins in thesystem I/O connector. Logic polarities are retained, with a HIGH level at a connector pin
associated with a HIGH level for the corresponding bit in the Digital I/O Port register.
Each data byte is an input field from the system I/O connector if the corresponding
BYTE XX OUTPUT control bit is LOW, or is an output field to the connector if the control bit is
HIGH. Both byte fields default to inputs.
Table 3.9-1. Digital I/O Port Register
Offset: 0004h
Data Bit

Mode

D00-D07

RW

D08

Default: 00XX 00XXh
DesignationDef

Description

DIO BYTE 00

XXh

System connector pins DIO 00 through DIO 07.

RW

BYTE 00 OUTPUT

0

Direction control for DIO BYTE 00. When LOW,DIO BYTE 00 is an input field. When HIGH,DIO BYTE 00 is an output field.

D09-D15

RO(Reserved)

0h

Read back as all-zero.

D16-D23RW

DIO BYTE 01

XXh

System connector pins DIO 08 through DIO 15.

D24

RW

BYTE 01 OUTPUT

0

Direction control for DIO BYTE 01. When LOW,DIO BYTE 01 is an input field. When HIGH,DIO BYTE 01 is an output field.

D25-D31

RO(Reserved)

0h

Read back as all-zero.

3.10 Autocalibration
To obtain maximum measurement accuracy, autocalibration should be performed after: Power warmup,
 PCI Express bus reset, Analog input or output range change.
The analog inputs are always calibrated on all input ranges during autocal, but to prevent
damage to possibly low-voltage loads, the analog outputs are calibrated only on the selected
output range.
Note: Analog outputs are active during standard autocalibration,
Autocalibration is invoked by setting the AUTOCAL control bit HIGH in the BCR. The control bit
returns LOW automatically at the end of autocalibration. Autocalibration can be invoked at any
time, and has a duration of less than 5 seconds. Completion of the operation can be detected
either by monitoring the "Autocal Busy" status flag in the primary status register (Table 3.11-1),
or by simply waiting a sufficient amount of time to ensure that autocalibration has been
completed.

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To compensate for component aging and to minimize the effects of temperature on accuracy,
the autocalibration function determines the optimum calibration values for current conditions,and stores the necessary correction values in internal volatile memory. If a board is defective,
the autocalibration process may be unable to successfully calibrate the inputs. If this situation
occurs, the AUTOCAL PASS status bit in the BCR is cleared LOW at the end of the
autocalibration interval, and remains LOW until a subsequent initialization or autocalibration
occurs. AUTOCAL PASS is initialized HIGH, and remains HIGH unless an autocalibration
failure occurs.
Inputs-Only Autocalibration:
The ANALOG INPUTS AUTOCAL control bit in the BCR initiates an autocal sequence thatcalibrates only the analog inputs. This control bit remains HIGH during the autocal sequence,and clears automatically at autocal completion. The analog outputs are forced to midrange(zero) during the calibration sequence, and retain this value after autocalibration.

3.11 Primary Status Register
Critical status flags are consolidated into a single Primary Status register (Table 3.11-1), which
is organized into a selection field and a response field. A response status bit is asserted if theselected event occurs after it has been selected. The response bit remains high until it iscleared from the PCI Express bus, either by clearing the response bit, or by clearing theassociated selection bit.
NOTE: Response status bits can only be cleared LOW from the PCI Express bus. A"one" written to a response bit is ignored.
A selected event is edge-detected on a transition of the event from false to true. Onceasserted, a response bit remains in that state until cleared from the bus, regardless ofsubsequent changes in the associated event state.
NOTE: Any PSR event will generate a local interrupt (LINT#), which can in turn can
generate an interrupt (INT-A) on the PCI Express bus. Refer to the PLX PEX8311 adapter reference manual for a description of interrupts.

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CCVPX-16AISS8AO4C

Offset 0x0030
Selection Bit

Table 3.11-1 Primary Status Register
Default 0x0000 0000

1

Response2
Bit

Critical Event

Reference
Paragraph

D00

Autocal completed

D16

3.10

D01

Input Buffer threshold flag HIGH-to-LOW transition

D17

3.4.5.2

D02

Input Buffer threshold flag LOW-to-HIGH transition

D18

D03

Input Buffer Overflow or Underflow

D19

3.4.5.1

D04

Analog Input Burst initiated (BURST BUSY LO-HI)

D20

3.4.4.2

D05

Analog Input Burst Completed (BURST BUSY HI-LO)

D21

D06

Analog Input Clock

D22

3.4.4

D07

Analog Output ClockD23

3.13.4

D08

Digital I/O Port DIO 00 LOW-to-HIGH transition

D24

3.9

D09

Output Buffer threshold flag HIGH-to-LOW transitionD25

3.13.2.3

D10

Output Buffer threshold flag LOW-to-HIGH transition

D26

D11

Output Load-Ready Flag HIGH-to-LOW transition

D27

D12

Output Load-Ready Flag LOW-to-HIGH transition

D28

D13

Analog Output Burst ReadyD29

3.13.5.2

D14

Output Buffer Overflow or Frame Overflow

D30

3.13.2.3

3.13.3.3

3.13.3.3
D15(Reserved)

D31

---

1. Event selection. Enables assertion of the corresponding response bit when the selected event occurs.
2. Event response. Asserted HIGH when a selected event occurs. Remains HIGH until cleared LOW.

3.12 Registered Analog Outputs
If the ENABLE BUFFERED OUTPUTS control bit is LOW in the BCR, the analog outputs arecontrolled in Direct-Register mode through the four ANALOG OUTPUT CHAN xx registers listed
in Table 3.1-1. If the control bit is HIGH, then the outputs are controlled in the Buffered Outputs
mode through the output buffer described in Section 3.13.
Each analog output channel is controlled directly through the associated
ANALOG OUTPUT CHAN xx register. The outputs are double-buffered, and can be clocked
either independently or simultaneously. Output data is written to a 16-bit field that is rightjustified in the data registers (Table 3.12-1).
Table 3.12-1. Analog Output Channel Data Register
Offset: 0008h - 0014h
Data Bit/Field

Default: 0000 8000h
Designation

Description

D00
D01-D14
D15

DATA00
DATA01 - DATA14DATA15

Data value least significant data bit
Data value intermediate data bits
Data value most significant data bit

D16-D31(Reserved)

Data in this field is ignored.

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CCVPX-16AISS8AO4C

3.12.1 Output Ranges
An output voltage range of ±10V, ±5V or ±2.5V is assigned by the OUTPUT RANGE control
field in the BCR. The default output range is ±10V.
3.12.2 Clocking Modes
3.12.2.1 Immediate
When the SIMULTANEOUS OUTPUTS control bit is LOW in the BCR, each analog output
channel is updated immediately when the associated data register receives a new value.
3.12.2.2 Simultaneous
When the SIMULTANEOUS OUTPUTS control bit is HIGH in the BCR, all analog outputs retain
their existing values until an output clock occurs. An output clock updates all output channels
simultaneously with the most recent data received by the data registers.
When operating in the simultaneous output clocking mode, an output clock is generated by:
 The OUTPUT S/W CLOCK control bit in the BCR, or: The internal Rate-C generator, or:An external clock input from the I/O connecter,as shown in Table 3.12-2
Table 3.12-2 Simultaneous Output Clock Source Selection
Register
BCR

BOR *

Control Bit

S/W Clock(BCR)

Rate-C Gen

External
Input

HIGH

HIGH

HIGH

ENABLE RATE-C GENERATOR

X

HIGH

X

ANALOG OUTPUT CLK INITIATOR

X

HIGH

LOW

SIMULTANEOUS OUTPUTS* Buffered Outputs Operations register (Table 3.13-2).

To select the output clock Initiator mode, set ANALOG OUTPUT CLK INITIATOR HIGH in the
Buffered Outputs Operations control register (Table 3.13-2). In this mode, the bidirectional
OUTPUT CLK I/O pin in the system I/O connector is an output, and each output clock produces
a 100 nanosecond LOW output pulse.
If ANALOG OUTPUT CLK INITIATOR is LOW, designating the board as an output clock
Target, the OUTPUT CLK I/O pin becomes an input, and an output clock is generated for each
HIGH-to-LOW transition received at the pin. The Rate-C generator is ignored in the target
clocking mode.

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3.13 Buffered Analog Output Control
If the ENABLE BUFFERED OUTPUTS control bit is set HIGH in the BCR, the analog outputs
are controlled through the output buffer in the Buffered Outputs mode described in thissection (3.13).
This section describes those operations that control the movement of data from the PCI Express
bus through the analog output buffer. These functions include the selection of active channels,
the organization of data within the buffer, and the clocking of data from the buffer to the analog
outputs. The principal parameters associated with controlling the analog output channels are
summarized below in Table 3.13-1.
Table 3.13-1. Summary of Output Control Parameters
Parameter
Data Control

BufferConfiguration

Clock Source

Clocking Mode

Sampling Mode

Mode

Description

Active Channels;
Channel GroupA single set of all active output channels constitutes an Active
Channel Group. Active channels are selected under a channel
mask.

Data Frame

All data values in the buffer comprise a Data Frame.

Data Coding

Output data can be coded either in offset-binary format or in two's
complement format.

Open

Data read from the buffer is used and then discarded, until thebuffer is empty.

Circular (closed)

Data within the buffer is recirculated. Each value read from theoutput of the buffer FIFO is written back to the input of the FIFO.
An end-of-frame (EOF) flag tracks the movement of data throughthe buffer.

External

External hardware provides the sample clock.

Internal

The sample clock is provided by an internal rate generator, at a
rate determined by the sample rate control register.

Simultaneous

At each clock occurrence, the next channel group (i.e.: a single
group of all active channel values) in the output buffer istransferred to the respective analog output channels. All outputs
are updated simultaneously.

Sequential

At each clock occurrence, the next active channel value in the
output buffer is transferred to the associated analog output
channel, which is updated immediately.

Continuous

The contents of the output buffer are sampled continuously at the
selected clock rate.

Triggered Burst

A single data frame in the buffer is clocked to the outputs.

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3.13.1 Data Organization
3.13.1.1 Active Channels
Analog output data is loaded into the output buffer in discrete groups or frames of channel data.
An active channel group consists of a single set of output values for all active channels.
Only active output channels receive data from the output buffer. A channel that is deselected tothe inactive state retains the last value that was received while the channel was still active.
During initialization, all channels are designated as active and are set to midrange (zero output
level).
3.13.1.1.1 Selection
An output channel is selected as active by setting the corresponding AO CHANNEL-xx-ACTIVE
selection bit HIGH in the Buffered Output Operations register shown in Table 3.13-2. A channel
is deselected to the inactive state by clearing the corresponding selection bit.
3.13.1.1.2 Loading
Channel data values are loaded into the output buffer in ascending order of active channels.
The channel groups are loaded contiguously, beginning with the first group to be transferred tothe outputs, and proceeding sequentially to the last group. Figure 3.13-1 illustrates a loading
example that represents three active channels, with 100 values per channel. Each channelgroup consists of active channels 0, 1 and 3.
NOTE: Data can be loaded from the PCI Express bus to the output buffer only if thebuffer is open… That is, not circular or closed (3.13.2.4).

Channels 0, 1 and 3 Enabled;
100 Values per Channel

LOADINGSEQUENCE

VALUE LOADED

0 (First)

Chan-0, 1st value

1

Chan-1, 1st value

2

Chan-3, 1st value

3

Chan-0, 2nd value

4

Chan-1, 2nd value

5

Chan-3, 2nd value

1st Channel Group

2nd Group(Intermediate Values)
297

Chan-0, Last value

298

Chan-1, Last value299

Chan-3, Last value

Last Group

Figure 3.13-1. Typical Buffer Loading Sequence____________________________________________________________________________________________
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CCVPX-16AISS8AO4C

Table 3.13-2. Buffered Output Operations Register
Offset: 003Ch

Default: 0000_104Fh

Bit
D00
D01
D02
D03

Mode
R/W
R/W
R/W
R/W

Designation
AO CHAN 00 ACTIVEAO CHAN 01 ACTIVEAO CHAN 02 ACTIVEAO CHAN 03 ACTIVE

Def
1
1
1
1

D04

R/W

ANALOG OUTPUT CLK INITIATOR

0

D05

R/W

ENABLE OUTPUT CLOCKING

0

D06

RO

OUTPUT CLOCK READY

1

D07

R/W

OUTPUT SW CLOCK *

0

D08

R/W

CIRCULAR BUFFER

0

D09

R/W

LOAD REQUEST *

0

D10

RO

LOAD READY

0

D11
D12

R/W
RO

CLEAR OUTPUT BUFFER *AO BUFFER EMPTY

0
1

D13

RO

AO BUFFER THRESHOLD

0

D14
D15
D16
D17

RO
RO
R/W
R/W

(Reserved)
AO BUFFER FULLAO BUFFER OVERFLOW
FRAME OVERFLOW

0
0
0
0

D18

RO

BURST READY

0

D19

R/W

ENABLE OUTPUT BURST

0

D20

R/W

OUTPUT SW TRIGGER *

0

D21

R/W

TRIG AI BURST ON AO

0

D22D31

RO(Reserved)

0

Description
Active-channel mask for analog output
channels. HIGH => Active; LOW => Inactive.

Selects the internal Rate-C generator for output
clocking if HIGH, or the Output Clock I/O hardware
input if LOW.
Enables output clocking when HIGH. Disables
clocking when LOW. Default is LOW (clocking
disabled).
Indicates when HIGH that an output clock will be
accepted. If LOW, indicates that the output will not
respond to a clock.
Produces a single output clock event whenasserted.
Independent of clocking mode.
Duplicated in the BCR.
Selects circular buffer configuration if HIGH, or open
self-flushing buffer configuration if LOW. Access forloading new data into the circular buffer must be
requested by asserting LOAD REQUEST. Default is
LOW; i.e. open buffer.
When set HIGH, requests loading access to thecircular buffer. Initializes LOW.
Set HIGH when the frame index passes throughzero, if both CIRCULAR BUFFER and LOAD
REQUEST are HIGH. When HIGH, indicates thatthe circular buffer is ready to accept new data.
Available also in the PSR. Defaults HIGH.
Resets the output buffer to empty.
Indicates the analog output buffer is empty.
Analog output buffer threshold flag.
Duplicated in the AO Buffer Threshold register.
Inactive; Returns zero.
Indicates the output buffer is full.
Set HIGH when data is written to a full buffer. **Set HIGH when data is written to a closed buffer. **If HIGH, indicates that a burst trigger will be
accepted. If LOW, indicates that the output will not
respond to a trigger.
Enables analog output burst operation.
Produces a single output trigger event whenasserted. Clears LOW automatically when the clock
event is completed.
Independent of triggering
mode.
Synchronizes triggering of analog input bursts toanalog output bursts.
Inactive. Returns all-zero.

* Clears LOW automatically when operation is completed.
** Remains HIGH until cleared by a direct write as LOW, or by initialization.

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3-17

Ref
3.4.1.1

3.13.4.1

3.13.43.13.43.13.4.1

3.13.2.5

3.13.3.3

3.13.3.3

3.13.2.3
3.13.2.3
3.13.2.3--3.13.2.3
3.13.2.3
3.13.2.3
3.13.53.13.5.2
3.13.5.2

3.17---

CCVPX-16AISS8AO4C

3.13.1.2 Data Frame
A data frame consists of an integral number of channel groups.
For triggered bursts, or for function concatenation, the last active channel in the last channelgroup is designated as the end-of-frame (EOF). The EOF designation is applied by setting the
EOF flag (D16) HIGH when loading the last channel value into the buffer. Thereafter, the EOF
flag follows the last channel value through the buffer.
3.13.1.3 Voltage Range Selection
An output voltage range of ±10V, ±5V or ±2.5V is assigned by the OUTPUT RANGE control
field in the BCR. The default output range is ±10V.
For maximum accuracy, autocalibration should be performed after a new input or output range
is selected.
3.13.2 Output Buffer
Analog output data from the PCI Express bus is first corrected for offset and gain errors, andthen flows directly into the 256K-sample analog output FIFO data buffer (Table 3.13.1). Fromthe buffer, the corrected data is routed to the analog output DAC channels.
NOTE: The output buffer capacity of 256 K-Samples is distributed among all active output
channels. The capacity in samples-per-channel is:
Sample Capacity per Channel = 256K / Number of active channels.
3.13.2.1 Output Data Format
Analog output data values are written in Lword-serial sequence from the PCI Express bus to theAnalog Output Buffer register shown in Table 3.13-3. Bits D15..0 represent the output data
value. Bit D16 is set HIGH to indicate the last value in a data frame, and is the end-of-frame(EOF) flag. Bits D31..17 are inactive. Access to the output buffer is supported for both singlelongword transfers and single-address multiple-longword DMA transfers. The output buffer
appears to the PCI Express bus as a single register, and a read-access to this register returns
an all-zero value.

Offset: 0048h

Table 3.13-3. Analog Output Buffer
Default: N/A (Write-Only)

Bit

Mode *

Designation

Description

D00

WO

DATA 00

Least significant data bit

D01-D14WO

DATA 01 - DATA 14

Intermediate data bits

D15

WO

DATA 15

Most significant data bit

D16

WO

EOF FLAG

End-of-frame (EOF) flag.

D17-D31

WO---(Inactive)* WO indicates write-only access. Read-access returns all-zero value.

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CCVPX-16AISS8AO4C

3.13.2.2 Output Data Coding
Analog output data coding is described in Paragraph 3.6.
3.13.2.3 Output Buffer Control
The Buffered Output Operations register in Table 3.13-2 controls and monitors the flow of data
through the analog output data buffer. Asserting the CLEAR OUTPUT BUFFER control bit
HIGH clears, or empties, the buffer.
The AO BUFFER OVERFLOW flag is set HIGH if data is written to a full buffer, and the
FRAME OVERFLOW flag indicates that an attempt was made to write data to a closed buffer.
Both flags indicate data loss. Once set, each of these flags remains HIGH until written LOW
directly from the bus, or by initialization .
The AO BUFFER EMPTY flag indicates that the buffer contains no output data. The
AO BUFFER FULL flag is asserted when the buffer is full. Data written to a full output buffer isdiscarded.
The Output Buffer Size register shown in Table 3.13-4 contains the number of output data
values present in the buffer, and is updated continuously.
Table 3.13-4. Output Buffer Size Register
Offset: 0044h

Default: 0000 0000h

Bit Field

Mode

Designation

D00-D18RO

BUFFER SIZE

D19-D31

RO(Inactive)

Default

Description

0 0000h

Number of values in the output buffer

0---

The Output Buffer Threshold register in Table 3.13-5 specifies the buffer size value above which
the OUTPUT BUFFER THRESHOLD FLAG is asserted HIGH.

Table 3.13-5. Output Buffer Threshold Register
Offset: 0040h

Default: 0003 FFFEh

Bit Field

Mode

Designation

Default

Description

D00-D18RW

OUTPUT BUFFER THRESHOLD

3 FFFEh

Specifies the number of values in the output
buffer, above which the threshold flag isasserted HIGH.

D19

RO

OUTPUT BUFFER THRESHOLD FLAG0HIGH when the number of values in the
output buffer exceeds the specified buffer
threshold.

D20-D31

RO

Reserved0---____________________________________________________________________________________________
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CCVPX-16AISS8AO4C

3.13.2.4 Open Buffer
If the CIRCULAR BUFFER control bit is LOW in the buffer operations register (Table 3.13-2),
the output buffer operates in the open mode. Data in an open buffer is discarded as it is used.
Consequently, the buffer is self-flushing, and will empty itself unless it is replenished from thePCI Express bus. This mode of operation permits the continuous flow of data from the PCI
Express bus to the analog outputs.
The open-buffer configuration also can be used to produce a one-shot waveform, provided theparticular waveform is to be used only once. Figure 3.13-2 illustrates the movement of a single
data frame through an open buffer.

Active Buffer
From Busa. Buffer Loading

Input

Outputb. Frame Loaded

c. Clock Enabled;
Buffer Emptying

To DAC’s

Figure 3.13-2. Open Buffer Data Flow

3.13.2.5 Circular Buffer
Data in a circular (closed) buffer is retained indefinitely. This configuration generally is
implemented to produce either periodic waveforms of constant frequency, or one-shot transient
waveforms that will be used repeatedly but not necessarily periodically. While closed, the buffer
is not accessible from the PCI Express bus.
In Figure 3.13-3 a single data frame is loaded into the buffer. The buffer is then closed(CIRCULAR BUFFER set HIGH) and clocking is enabled. The data frame subsequently
circulates in the buffer while passing data values to the output channels.
An end-of-frame (EOF) flag accompanies the end-point, or last value in a data frame. The EOF
flag is D16 in the buffer, and is set HIGH when the last value in a data frame is loaded. This
flag is used at the end of a function or triggered burst to define the last value.
Multiple
contiguous burst functions, or frames, can reside in the buffer simultaneously.
NOTE: Disable output clocking before loading the output buffer for circular operation.

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CCVPX-16AISS8AO4C

Active Buffer
EOF Flaga. Frame Loaded
Circulating Datab. Clock enabled;
Data Recirculating

To DAC’s

Figure 3.13-3. Circular Buffer Data Flow

3.13.3 Function Generation
3.13.3.1 Periodic and One-Shot Functions
Periodic waveforms are produced when the buffer is configured for continuous sampling andcircular operation. In this mode, the contents of the buffer are scanned continuously as long as
clocking is enabled and a clock is present. The data frame is recirculated through the buffer
repeatedly. Clocking is enabled when the ENABLE OUTPUT CLOCKING control bit in thebuffer operations register is HIGH.
If triggered-burst sampling is used in conjunction with a circular buffer, a one-shot waveform is
produced that contains all values within a single data frame. The triggered burst is initiated by asoftware or hardware trigger, and terminates automatically when the end-of-frame (EOF) flag is
encountered. Because the buffer is circular, the waveform is retained in the buffer and can be
reproduced repeatedly by subsequent triggers.
3.13.3.2 Multiple Functions
When multiple functions are loaded into the buffer as contiguous data frames, and if triggeredburst sampling is selected, the functions will be generated sequentially in response to a seriesof burst triggers. If the buffer is open, the functions are flushed from the buffer as they areclocked to the analog outputs. However, if the buffer is closed (circular), the functions are
retained in the buffer, and the series of functions is repeated indefinitely. .
3.13.3.3 Function Sequencing (Concatenation)
A new function can be concatenated to the end of an existing function in a circular buffer, while
the existing function is being flushed from the buffer. During this operation, the existing function
is flushed from the buffer as it is clocked to the outputs, and is replaced by the new function.
When the last value of the existing function is clocked out of the buffer, the buffer closes and the
new function seamlessly begins circulating in the buffer and producing an output.

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CCVPX-16AISS8AO4C

Introduction of a new function commences by setting the LOAD REQUEST flag HIGH in thebuffered output operations register (Table 3.13-2), and by then waiting for the LOAD READY
flag to be asserted. (In effect, LOAD REQUEST is an "interrupt request" to the buffer). The
LOAD READY flag indicates that the buffer has opened, and that the existing function is being
flushed from the buffer, beginning with the first value in the function's data frame.
After LOAD READY goes HIGH, the new function is written to the buffer and is terminated with
an EOF flag (output data bit D16 set HIGH). The EOF flag of the existing function causes thebuffer to close, and clears both the LOAD READY flag and the LOAD REQUEST control bit.
Notice that the loading of the new function into the buffer must be completed before the existing
function terminates.
In Figure 3.13-4, an existing function is replaced by a new function while the existing ('old')
function is flushed from the buffer.
NOTE: If the loading of a new function extends beyond the LOAD-READY interval, the
FRAME OVERFLOW flag is set HIGH in the Buffer Operations register, indicating data
loss. Once set, this flag remains HIGH until written LOW directly from the bus, or byinitialization

Circulating Data
EOF Flaga. Old Function Recirculating(Set LOAD REQUEST
for Buffer Access)
Input

OutputTo DAC’s

Active Buffer

b. Buffer Opened(LOAD READY goes HIGH)
From Busc. New Function Loading;
Old Function Flushing
New EOF Flag

Old EOF Flag

d. New Function Loaded
e. Old Function Flushed.
Buffer Closed.
(LOAD READY clears LOW)

f. New Function Recirculating

To DAC’s

Figure 3.13-4. Function Sequencing____________________________________________________________________________________________
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CCVPX-16AISS8AO4C

3.13.4 Output Clocking
If the ENABLE OUTPUT CLOCKING control bit in the buffer operations register is asserted
HIGH, clocking is enabled and the active analog outputs are updated at each occurrence of thesample clock. The sample clock can be generated internally by the rate generator, or can besupplied externally through the I/O connector.
Output clocking is disabled when the
ENABLE OUTPUT CLOCKING control bit is LOW. The OUTPUT CLOCK READY flag indicatesthat data is available to be clocked to the output channels .
Hardware output signal OUTPUT CLK I/O (Table 2.2-1) goes LOW momentarily each time asample clock occurs, Connecting this signal to the OUTPUT CLK I/O pins of other boards
permits synchronous clocking of multiple boards.
3.13.4.1 Clock Source
When buffer operations register bit ANALOG OUTPUT CLK INITIATOR is LOW, the output
clock is supplied externally through the I/O connector as OUTPUT CLK I/O. If the control bit is
HIGH, the output clock is derived from the internal Rate-C generator. An output clock can also
be supplied at any time by asserting the OUTPUT SW CLOCK control bit, which clears
automatically.
3.13.4.1.1 External Clock
The external clock source can have any frequency up to the maximum value specified for the
sampling rate. When the external clock source is selected, sampling occurs on a HIGH-to-LOWtransition of the OUTPUT CLK I/O pin in the I/O connector.
3.13.4.1.2 Internal Output Rate Generator
The internal Rate-C generator provides a sample clock that is adjustable by the RATE[23..0]
control bits in the Output Sample Rate control register shown in Table 3.13-6. The Rate-C
generator is enabled by setting the ENABLE RATE-C GENERATOR control bit HIGH in the
BCR.
Table 3.13-6. Output Sample Rate Control Register (Rate-C)
Offset: 004Ch

Default: 0000_007Eh

Data Bit

Mode

Designation

Description

D00

R/W

RATE 00

Least significant rate bit

D01-D22R/W

RATE 01 - RATE 22

Intermediate rate bits

D23

R/W

RATE 23

Most significant rate bit

D24-D31

RO---

Inactive. Returns all-zero.

The output clocking rate Fclock is calculated from the relationship:
Fclock (Hz) = Fclk / Nrate ,where Nrate is the decimal equivalent of the value in the RATE value in the Sample Rate
control register, and Fclk is the master clock frequency for the board. For simplicity, Fclk is
assumed here to be 64.000 MHz, but is an ordering option and can have any value close to thisfrequency. The actual value for Fclk is identified in the Assembly Configuration register shownin Section 3.16.

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Table 3.13-7 illustrates the effect of Nrate on the sample rate. Clocking rates above
1000 KSPS can produce unpredictable results and are not recommended. Nrate should not be
modified during function generation.
Table 3.13-7. Output Sample Rate Selection
Ndiv

FREQUENCY Fgen
(64 MHz Master Clock)*

(Dec)

(Hex)

(kHz)

32

20

2000.00

33

21

1939.39---

Fgen (Hz) = Fclk (Hz) / Ndiv--* ±0.003 percent.

3.13.4.2 Simultaneous Clocking
Simultaneous sampling is selected by setting the SIMULTANEOUS OUTPUTS control bit in theboard control register HIGH. If simultaneous sampling is selected, the analog values in eachsuccessive channel group appear simultaneously at the outputs, with minimum time-skew
between channels. Upon each occurrence of the sampling clock, an entire active channelgroup is transferred from the output buffer, and all outputs are updated simultaneously. In thismode, the effective sample rate for each channel equals the output clocking rate Fclock.
3.13.4.3 Sequential Operation
Sequential sampling is selected when the SIMULTANEOUS OUTPUTS control bit in the board
control register is LOW. At each clock occurrence in sequential operation, a single channel
value is transferred from the buffer to the associated output channel, and the channel is
updated immediately. Channel values are read from the buffer beginning with the lowestnumbered active channel in a channel group, and proceeding upward through the highestnumbered active channel.
When operating in this mode, the effective sample rate for eachchannel equals the output clocking rate Fclock divided by the number of active channels.
3.13.5 Sampling Mode
3.13.5.1 Continuous Sampling
If the ENABLE OUTPUT BURST control bit in the Buffered Output Operations register is LOW(default), the continuous sampling mode is selected and data is transferred continuously fromthe buffer to the analog outputs, assuming that the buffer is not empty and that an output clockis present.
3.13.5.2 Data Bursts
If the ENABLE OUTPUT BURST control bit in the Buffered Output Operations register is HIGH,
burst operation is selected. During a triggered output burst, data is transferred continuously
from the output buffer to the analog outputs until either the buffer goes empty, or the end-offrame (EOF) flag is encountered. In the triggered-burst sampling mode, an internal orexternal output trigger initiates the transfer of data from the output buffer to the output channels.
If the TRIGGER INITIATOR control bit in the BCR is HIGH, internal triggering is selected, andeither a software or hardware trigger will initiate a burst. A software trigger is generated by
setting the OUTPUT S/W TRIGGER control bit HIGH, and a hardware trigger is provided by the____________________________________________________________________________________________
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Rate-B generator, if enabled. These trigger sources are independent of each other, and theoccurrence of either or both will initiate a burst. The OUTPUT SW TRIGGER bit remains HIGH
during the burst, and clears automatically when the burst is completed.
In the initiator mode, hardware output pin TRIGGER I/O produces a LOW pulse at the beginningof each burst. Connecting this signal to the TRIGGER I/O pins of other boards permits
synchronous burst triggering of multiple boards.
If the TRIGGER INITIATOR control bit is LOW in the BCR, indicating Target Mode or External
triggering, a hardware burst trigger occurs upon a HIGH-to-LOW transition of the TRIGGER I/O
pin in the I/O connector, if the ENABLE OUTPUT BURST control bit in the operations register is
HIGH, and if the BURST READY flag also is HIGH. The BURST READY flag is LOW during aburst, and is HIGH if no burst is in progress. The OUTPUT S/W TRIGGER control bit also isactive in the target mode.
Multiple burst functions can exist simultaneously within the buffer if the end-of-frame (EOF) flagis used (Paragraph 3.13.2.1). The EOF flag defines the last output value in each data burst.
After a burst is triggered, data values from the buffer are clocked to the analog outputs at the
selected sample rate until the EOF flag is encountered. The burst then terminates, and clockingof the buffer ceases until a subsequent trigger occurs.
Refer also to the Trigger Initiator note in 3.4.4.2.
3.13.6 Multiboard Synchronization
Boards that are configured for synchronous clocking update their outputs simultaneously inresponse to a common clock signal. Boards that are configured for synchronous burst
triggering initiate data bursts simultaneously in response to a common trigger signal. Multiple
boards can be arranged to operate with:a. Independent clocking and burst triggeringb. Synchronous burst triggering (Common burst trigger)
c. Synchronous clocking (Common DAC clock)d. Synchronous clocking and burst triggering (Common trigger and DAC clock).
As many as four boards can be synchronized together. External clock and trigger I/O signalinguses standard TTL levels.
3.13.6.1 Synchronous Bursts
To burst-synchronize a group of boards, the TRIGGER I/O signal from one board, the burstinitiator, is connected to the TRIGGER I/O pins of a group of burst-target boards. Each bursttarget, when operated in the triggered-burst mode, initiates a single burst from its buffer eachtime the burst-initiator initiates a burst.
3.13.6.2 Synchronous Clocking
To clock-synchronize multiple boards together, the OUTPUT CLK I/O from one board,
designated the clock-initiator, is connected to the OUTPUT CLK I/O pin of one or more clocktarget boards.
In this case, the clock-targets are configured for external clocking(ANALOG OUTPUT CLK INITIATOR cleared LOW in the operations control register), and theinitiator is configured for internal clocking.

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3.14 Buffered Analog Output Application Examples
NOTE: This section provides examples of operation in the Buffered Outputs mode, andassumes that the ENABLE BUFFERED OUTPUTS control bit is set HIGH in the BCR.
Specific operating modes and procedures vary widely according to the unique requirements ofeach application. The examples presented in this section (Table 3.14-1) illustrate several basic
operating modes, and can be modified or combined for more complex operations.
References to functions in these examples generally apply to a single output channel for
simplicity of explanation. However, each active channel represents an independent set offunction values, and all channels share a common output clock.
Table 3.14-1. Summary of Operation Examples
Operation Example

Description

Sequential Direct Outputs

Each value written to the output data buffer updates the associated analog output
channel when clocked, independently of the other channels.

Simultaneous Direct Outputs

Data values accumulate in the output data buffer until an entire channel group has
been loaded. When the last channel is loaded, all active output channels update
simultaneously when clocked.
An extension of Simultaneous Direct Outputs, in which the buffer is not allowed to
become either empty or full.

Continuous Function
Periodic Function

A single function is generated repeatedly in each active channel.

Function Burst

One or more functions are generated as discrete data bursts. The burst cycle isrepeated indefinitely if the circular-buffer mode is selected.

Function Sequencing

An existing active function is replaced seamlessly by a new function.

Each of the examples in this section assumes that the initial operations listed in Table 3.14-2
have already been performed.
Table 3.14-2. Initial Operations
Operation

Default Value

Applicable
Paragraph

The board has been reset or initialized.

---

3.3.2

The active channel group has been defined .

All channels active

3.13.1.1

The required output coding has been selected.

Offset binary

3.6

The remaining operational parameters are assumed to be in the following default states initially:
Parameter
Buffer mode:
Buffer status:
Clock source:
Clock status:

Default
Open
Empty
External (Buffer Operations register)
Disabled (Buffer Operations register)

Parameter

Default

Sample rate:
Sampling mode:

320KSPS
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3.14.1 Sequential Direct Outputs
Table 3.14-3. Sequential Direct Outputs Example
Operation

PCI Express Bus Action

Board Response

Select Internal Clocking

Set the ANALOG OUTPUT CLK
INITIATOR control bit HIGH in thebuffer operations register.

The internal Rate-C generator is selected
as the output clocking source.

Enable clocking

Set the ENABLE OUTPUT
CLOCKING control bit HIGH in thebuffer operations register.

Clocking is enabled at the default rate.

Set the ENABLE RATE-C
GENERATOR control bit HIGH in
the BCR.
Load the output value for the
first active channel.

Write the first value to the output
data buffer.

Output value appears immediately (whenclocked) at the analog output.

Load the output values for theremaining active channels.

Write the remaining active channel
values to the output data buffer.

Remaining active analog outputs are
updated in ascending sequence.

Repeat the above operationsforsubsequentchannelgroups.

Continue to write output values tothe output data buffer.

Each value written to the buffer istransferred immediately to the associatedanalog output when clocked

Notes:

1. End-of-frame (EOF) flags are ignored when operating in the open-buffer mode.
Only D15..0 are active in the output buffer.
2. Data written to the buffer at rates above 1000KSPS will accumulate in the buffer.
3. Access to an individual output channel is accomplished by first selecting (enabling) only the
specific channel, and by then writing the output value to the buffer.

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3.14.2 Simultaneous Direct Outputs

Table 3.14-4. Simultaneous Direct (Single Group) Outputs Example
Operation

PCI Express Bus Action

Board Response

Select simultaneous clocking.

Set SIMULTANEOUS OUTPUTS in
the BCR.

Simultaneous clocking is selected.

Select Internal Clocking

Set the ANALOG OUTPUT CLK
INITIATOR control bit HIGH in thebuffer operations register.

The internal Rate-C generator is selected
as the output clocking source.

Enable clocking

Set
the
ENABLEOUTPUT
CLOCKING control bit HIGH in thebuffer operations register.

Clocking is enabled at the default rate.

Set
the
ENABLE RATE-C
GENERATOR control bit HIGH in
the BCR.
Clear the output buffer.

Set the CLEAR OUT BUFFER bit
in the output operations register.

The output buffer clears to empty.

Load the output value for the
first active channel.

Write the first value to the output
data buffer.

First value is retained in the buffer.

Load the output values for theremaining active channels.

Write the remaining active channel
values to the output data buffer.

Remaining values are accumulated in thebuffer. When the last value is loaded, allvalues are extracted from the buffer andappear simultaneously at the associatedoutput channels.

Repeat the above operationsforsubsequentchannelgroups.

Continue to write output values tothe output data buffer.

Allactivechannelsareupdatedsimultaneously when the last value ineach group is written to the buffer.

Notes:

1. Data written to the buffer at rates above 1000KSPS will accumulate in the buffer.

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3.14.3 Continuous Function

Table 3.14-5. Continuous Function Example
Operation
Select simultaneous clocking.

PCI Express Bus Action
Set SIMULTANEOUS OUTPUTS
in the board control register.
Write 1/4 block size to thethreshold register (Table 3.13-5).
Write
the
requiredsampleclocking rate to the Rate-C
generator control register.

Board Response
Simultaneous clocking is selected.

To select internal clocking, set the
ANALOG OUTPUT CLK
INITIATOR bit HIGH in the buffer
operations register.
Set the ENABLE OUTPUT
CLOCKING control bit HIGH in
the buffer operations register.

Internal clocking is selected, if required.

Set
the
ENABLE RATE-C
GENERATOR control bit HIGH in
the BCR.

The internal rate generator is enabled, if
internal clocking is required.

Clear the output buffer.

Set the CLEAR OUT BUFFER bit
in the output operations register.

The output buffer clears to empty.

Write a block of values to all
active channels.

Write function values for all active
channels to the output data buffer.

All active channels produce
respective output functions.

To avoid discontinuities in the
output functions, the effective
loading rate for channel groups
must be greater than thesample (clocking) rate times thenumber of active channels.
Maximum loading rate is
40MSPS during DMA transfers.
Wait for the buffer threshold flag
to go LOW. (See Note 1).

Monitor the analog output buffer
threshold flag until LOW.

The output buffer empties to less than 1/4full status.

Set the buffer threshold flag to
1/4 of the expected block size.
If the internal rate generator is
to be used, select the sample
rate. (Skip this step if external
clocking will be used).
If internal clocking is required,select internal clocking.

Enable clocking

Repeat the previous two steps
to sustain function generation.

The threshold flag will go LOW when thebuffer contents drop below the threshold.
The frequency of the internal rate
generator is selected, if internal clocking isrequired.

Clocking is enabled at the selected rate.

their

All output functions proceed continuously.

Notes:
1. Response to the flag must be fast enough to prevent the buffer from going empty.

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3.14.4 Periodic Function
Table 3.14-6. Periodic Function Example
Operation

PCI Express Bus Action

Select simultaneous clocking.

Set SIMULTANEOUS OUTPUTS in
the board control register.

Simultaneous clocking is selected.

Clear the output buffer.

Set the CLEAR OUTPUT BUFFER
bit in the output operations register.

The output buffer clears to empty.

Load the first function value foreach active channel.

Write the values for the first active
group to the output data buffer.

Initial values for all active channels
accumulate in the buffer.

Load the remaining function
values for all active channels.
(Note 1)

Write all remaining function values
for all active channels to the output
buffer.

Remaining function values for all active
channels accumulate in the buffer.

Set the end-of-frame (EOF)
flag.

Set the EOF flag (D16 in the output
buffer) HIGH when writing the data
value for the last channel in the lastgroup.
Write the required sample clocking
rate to the Rate-C generator control
register.

The EOF flag is set HIGH in the buffer
location that contains the last channel
value in the last channel group.

Note:
The
remaining
operations may be performed
simultaneously with a single
write-transaction to the buffer
operations register:

---

---

Selectmode.

Set CIRCULAR BUFFER in thebuffer operations register.
To select internal clocking, set the
ANALOG OUTPUT CLK
INITIATOR bit HIGH in the buffer
operations register.

The output buffer is closed (circular).

Set ENABLE OUTPUT CLOCKING
in the buffer operations register.

Clocking is enabled. All active channels
producetheirrespectivefunctions
repeatedly until the clock is disabled or theoperating mode is changed. All outputs
update simultaneously at the sample clockrate.

If the internal rate generator is
to be used, select the sample
rate. (Skip this step if external
clocking will be used).

thecircularbuffer

If the internal rate generator is
to be used, select internal
clocking.
Enable the sample clock.

Set the ENABLE RATE-C
GENERATOR control bit HIGH in
the BCR.

Board Response

The frequency of the internal rate
generator is selected, if internal clocking isrequired.

The internal Rate-C generator is selected,
if required.

Notes:
1. To generate periodic functions simultaneously in multiple channels, all functions must be commensurate. That is,
the functions in all channels must have frequencies that are exact integer multiples of the frequency of the lowestfrequency channel. Conversely, the period of the lowest-frequency channel must be an exact integer multiple ofthe period of each of the other channels.

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3.14.5 Function Burst
Table 3.14-7. Function Burst Example
Operation
Select simultaneous clocking.
Clear the output buffer.
Load the first function value foreach active channel.
Load the remaining function
values for all active channels.
Set the end-of-frame (EOF)
flag.

If more than one burst-functionisrequired,
repeattheprevious operations for each
additional function.
Select the trigger source.

If the internal rate generator is
to be used for clocking, selectthe clocking rate.
If the internal rate generator is
to be used for triggering,
select the triggering rate.
Select triggered-burst mode.
Prepare the buffer operations
register for burst mode:
If the burst functions will be
used repeatedly, select thecircular buffer mode.
If internal clocking isrequired, select internal
clocking.
Enable the sample clock.
Enable the internal
generators, if required.

rate

PCI Express Bus Action
Set SIMULTANEOUS OUTPUTS
in the board control register.
Set the CLEAR OUT BUFFER bit
in the output operations register.
Write the values for the first active
group to the output data buffer.
Write all remaining function values
for all active channels to the output
buffer.
Set the EOF flag (D16 in the output
buffer) HIGH when writing the data
value for the last channel in the lastgroup.
---

Board Response
Simultaneous clocking is selected.
The output buffer clears to empty.
Initial values for all active channels
accumulate in the buffer.
All function values for all active channels
accumulate in the buffer.
The EOF flag is set HIGH in the buffer
location that contains the last channel
value in the last channel group.
If required, additional burst functions
accumulate in the output buffer.

For internal triggering, set the
TRIGGER INITIATOR bit HIGH in
the BCR. For external triggering,clear the bit LOW (default).
Write the required clocking rate to
the Rate-C generator control
register.
Write the required triggering rate to
the Rate-B generator control
register.
Set ENABLE OUTPUT BURST in
the buffer operations register.

The frequency of the internal rate
generator is selected, if internal clocking
is required.

Write to the buffer operations
register:
To select the circular buffer
mode,
set
CIRCULARBUFFER.
To select internal clocking, set
ANALOG OUTPUT CLK
INITIATOR.
Set
ENABLEOUTPUT
CLOCKING.
Set the ENABLE RATE-B andRATE-C GENERATOR control bitsin the BCR.

---

The frequency of the internal rate
generator is selected, if internal clocking
is required.
The frequency of the internal rate
generator is selected, if internal triggering
is required.
The triggered-burst operating mode isselected.

If required, the output buffer is closed(circular), and all functions will be
retained in the buffer indefinitely.
Internal clocking is selected, if
required.
Output clocking is enabled.
Required internal rate generators areenabled.

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3.14.5 Function Burst (Continued)

Table 3.14-7. Function Burst Example (Continued)
Operation

PCI Express Bus Action

Board Response

For software burst triggering,
generate a software trigger toproduce a single burst on all
active output channels.

Set OUTPUT SW TRIGGER in thebuffer operations register..

All active output channels produce asingle burst in response to each software
trigger, if software triggering is used.

For external burst triggering, orinternal rate-generator
triggering, no further bus
activity is required.

---

All active output channels produce asingle burst in response to each internal orexternal trigger.

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3.14.6 Function Sequencing (Concatenation)

Table 3.14-8. Function Sequencing Example
Operation

PCI Express Bus Action

Board Response---

Each active output is producing a specificoutput function or waveform. The output
buffer is circular (closed), and is notaccessible from the bus.

Request buffer access

Set LOAD REQUEST in the buffer
operations register.

The board will assert the LOAD READY
flag when the EOF flag in the originalfunction occurs.

Wait for the buffer to open.

Monitor the LOAD READY statusflag. The buffer is open when thisflag goes HIGH.

The EOF flag in the existing function set
causes the LOAD READY bit in the buffer
operations register to be asserted.

Establish a periodic function as
described in Paragraph 3.14.4.
The following operations will
replace the original ('old')
function in each channel with a
new function.

The buffer is now open, and the originalfunctions are being flushed from thebuffer.
Load the new function for eachactive channel into the buffer.
Set the end-of-frame (EOF)
flag.

Write the function values for all
active channels to the output
buffer. Set the EOF flag (D16 in
the output buffer) HIGH whenwriting the data value for the lastchannel in the last group.

New function values for all active channels
reside in the buffer. The EOF flag is set
HIGH in the buffer location that contains
the last channel value in the last channelgroup.
The original functions are still active, andthe remaining values are flushed from thebuffer as they are sent to the output
channels.

(None required)No further attention is required fromthe PCI Express bus.

The buffer returns to circular (closed)mode after the last data value in theoriginal function set leaves the buffer.
The new function then commences
seamlessly and circulates within thebuffer.
Both the Load Request control bit and theLoad Ready flag are cleared automaticallywhen the buffer closes.

3.15 Analog Outputs DMA Operation
DMA transfers to the analog output FIFO buffer are supported in either block-mode or demandmode, with the board operating as bus master. Refer to the reference manual for the PLXtm
PEX-8311 PCI Express adapter for details involving DMA operations.

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3.16 Assembly Configuration Register
The read-only Assembly Configuration register (Table 3.16-1) contains the existing firmware
revision and a status field that indicates the availability of optional features.
Table 3.16-1. Assembly Configuration Register
Offset: 0000 0034h
Default: 00XX XXXXhBIT FIELDDESCRIPTION

D00-D11

Firmware Revision

D12-D15(Reserved bit field; all-zero)

D16

Number of analog input channels:
0 => 8 Analog input channels.
1 => 4 Analog input channels.

D17

Number of analog output channels:
0 => 4 analog output channels.
1 => No analog outputs.

D18-D19

Master clock frequency:
0 => 64.000MHz
1 => (Reserved)
2 => (Reserved)
3 => (Reserved)

D20-D31(Reserved bit field; returns all-zero).

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3.17 Synchronizing Analog Input Bursts to Analog Outputs
Analog input and output bursts can be triggered simultaneously either from the Rate-B
generator or externally through the Trigger IO pin in the system I/O connector (Paragraphs
3.4.4.2 and 3.13.5.2). However, while both input and output bursts can be triggered
simultaneously, the first input sample generally will not occur simultaneously with the first output
clock. The skew of the first input sample from the first output clock can be as large as the input
sample period or the output clocking period, whichever is larger.
The first input sample can be synchronized to the first output clock in simultaneous bursts bysetting the TRIG AI BURST ON AO control bit HIGH in the BOR. This synchronous modeensures that the first input sample will occur within 100-125 nanoseconds of the first output
clock.
The following setup sequence represents one baseline approach to triggering input and output
bursts simultaneously and synchronously, either externally or from the internal Rate-B
generator. It is provided as a general guide only, and is not intended to be a definitive set of
requirements. Input and output burst sizes are independent, and can have any valid values.
('Overlays' are OR'd into the indicated registers' existing contents):
1. Initialize the following control registers to required values:
Rate Generator-A,B,C: (A=> input sample rate; B=> Internal burst triggering rate; C => Output clocking rate).
Input Configuration.
2. BCR @00: Assert: (Net overlay = 010C_1000h):
D12: Enable Input Buffer.
D18: Simultaneous Outputs.
D19: Enable Buffered Outputs.
D24: Analog Input Clk Initiator.
3. BOR @3C: Assert: (Net overlay = 0000_0800):
D11: Clear Output Buffer.
4. Load the required function into the output buffer.
5. BOR @3C: Assert: (Net overlay = 0028_0130h for AO-synchronized bursts):(Net overlay = 0008_0130h for nonsynchronous simultaneous bursts):
D04: Analog Output Clk Initiator.
D05: Enable Output Clocking.
D08: Circular Buffer (If periodic function is required).
D19: Enable Output Burst.
D21: Trigger AI Burst On AO (For AI/AO burst synchronization).
(BOR D21 has no effect with firmware Revision 202)
6. BCR @00: Assert: (Net overlay = 0D6C_1200):
D09: Enable Input Burst.
D21: Trigger Initiator (For Rate-B generator triggering; Omit for external triggering)
D22: Enable Rate-C Generator.
D26: Enable Rate-A Generator.
D27: Enable Rate-B Generator (Omit for external triggering).

Simultaneous triggering should commence at this point. Details of the setup will vary,depending upon the requirements of specific applications.

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3.18 Isolating the System Bidirectional Control I/O Pins:
To eliminate activity on the bidirectional Input Clk I/O, Output Clk I/O, and Trigger I/O pins when
they are not required for system control functions, the Ancillary Control register (Table 3.18-1)
can be used to configure these pins as passive grounded outputs.
When each control bit is asserted HIGH, the corresponding I/O pin becomes a logic LOW
output, but the associated internal functions otherwise associated with that pin are unaffected.
If all three bits are asserted, the board is completely isolated from front-panel external system
control functions and operates autonomously.
Table 3.18-1. Ancillary Control Register
Offset: 0060h
Data Bit

Access
Mode

D00

R/W

D01

Default: 0000 0000
Designation

Default

Function

ISOLATE INPUT CLK IO PIN

0When HIGH, configures the INPUT CLK
I/O pin as a logic LOW output.

RO

ISOLATE TRIGGER IO PIN

0When HIGH, configures the TRIGGER
I/O pin as a logic LOW output.

D02

RO

ISOLATE OUTPUT CLK IO PIN

0When HIGH, configures the OUTPUT
CLK I/O pin as a logic LOW output..

D03

R/W

ADC WARP MODE

0

When HIGH, selects the ADC Warp
mode.

D03-D31

RO(Reserved)

0h

---

3.19 Analog Input Warp Mode; 1.5-2.0MSPS
For input sampling rates above 1500KSPS, the ADC WARP MODE control bit in the Ancillary
control register (Table 3.18-1) must be set HIGH.
NOTE: In warp mode, the minimum sample rate is 1 KSPS, and the first sample acquired
from all active channels after a lapse of 1 millisecond or longer should bediscarded.

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SECTION 4.0
PRINCIPLES OF OPERATION

4.1 General Description
Each of eight analog input channels contains a selftest input switching network, a differential
amplifier, a scaling network and a 16-Bit ADC (Figure 4.1-1), and provides input ranges of ±10V,±5V and ±2.5V. A 256 Ksample FIFO buffer accumulates analog input data for subsequent
retrieval through the PCI Express bus. Four 16-bit analog output channels provide softwareselected output ranges of ±2.5V, ±5V or ±10V, and are accessed either directly throughdedicated control registers, or through a 256 Ksample FIFO buffer. A 16-Bit bidirectional digital
port can be configured as two independent byte-wide ports.
A PCI Express interface adapter provides the interface between the controlling PCI Express bus
and an internal local controller, and supports universal signaling. +5 VDC and +12VDC powerfrom the Express bus is converted into regulated power voltages for the internal analog
networks.

SystemI/O Conn
Analog Outputs (4)±10V, 5V, 2.5V
Chan-00 of 8 Identical Input Channels
Analog Inputs

Selftest
Switching±10V, 5V, 2.5V

Inputs 01-07

Diff
Amp

16-Bit
ADC

Channels 01 to 07

Voltage
Reference

Input
Data

Input Control

External Clock and Sync I/O
16-BitDAC (4)

Sample-Rate
Generators (3)+5VDC+12VDCPower
Conversion

Local
Controller

Regulated
Power Voltages

PCI Express
Interface
Adapter

Local Bus

Host Conn(PCI Express)

Figure 4.1-1. Functional Block Diagram
Selftest switches at the inputs provide test signals for autocalibration of all input and output
channels, and can be configured to accept either differential or single-ended system inputs.
Analog input sampling and output clocking on multiple target boards can be synchronized to asingle software-designated initiator board.

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4.2 Analog Inputs
Analog-to-digital conversions can be performed on signals from any of several sources, which
are selected by the selftest switches shown in Figure 4.1-1. During normal operation, the 16-bit
ADC's receive system analog input signals from the system I/O connector. For integrity testing
and autocalibration operations, the internal voltage reference and the analog outputs can berouted through the selftest switches to the ADC's. An attenuator in each channel provides thenecessary scaling for software-controlled input ranging.
Parallel data from each ADC is multiplexed into a continuous data stream within the local
controller. The output of the data multiplexer passes through a digital processor that applies
gain and offset correction values obtained during autocalibration. The corrected data isformatted, and the final processed and formatted data is loaded into the analog input data
buffer.
ADC clocking can be supplied either from an internal 24-Bit rate generator, or from an externalsource. Triggered bursts can be acquired by using a second internal rate generator, or an
external input as a trigger source. The burst block-size can be controlled by a 24-Bit counter, or
sampling can be configured to operate continuously after a trigger. The ADC external clock andtrigger pins can be configured independently as inputs or outputs.
4.3 Input Data Buffer
A 256K-sample FIFO buffer accumulates analog input data for subsequent retrieval through the
PCIbus. The buffer is supported by a 'size' register that tracks the number of values in thebuffer, and by an adjustable threshold flag that generates a status flag in response to thenumber of samples contained within the buffer.
4.4 Analog Outputs
Four independent 16-bit DAC's are controlled either directly through dedicated control registers,or through a 256 Ksample FIFO buffer. The buffer can be operated either open for data
streaming, or closed (circular) for periodic function generation. Function concatenation from thePCI Express bus is supported.
Output clocking can be supplied either from a third internal 24-Bit rate generator, or from anexternal source. Triggered bursts are supported, and share the triggering function with theanalog inputs (4.2). The output burst size is controlled by a tag-bit attached to the last output
value in a sequence. If the tag-bit is not attached, a burst will operate continuously after a
trigger, or until the buffer goes empty.
4.5 Autocalibration
Autocalibration is an embedded firmware utility that calibrates all analog input and output
channels to a single internal voltage reference. The utility can be invoked at any time by thecontrol software.
The internal voltage reference is used to calibrate the span of each channel, and azero-reference is used to calibrate the offset value. Correction values determined during
autocalibration are applied to each digitized sample acquired during acquisition, and to each
output value written to the DAC channels.
Correction values are retained until the
autocalibration sequence is repeated, or until power is removed.

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4.6 Power Control
Regulated supply voltages of ±5 VDC and ±15 VDC are required for the analog networks, andare derived from the +5VDC and +12VDC inputs provided by the PCI Express bus, both byswitching preregulators and by linear postregulators.

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APPENDIX A
Local Register Quick Reference____________________________________________________________________________________________
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APPENDIX A
LOCAL REGISTER QUICK REFERENCE
This appendix summarizes the local registers and principal control-bit fields described in Section 3.

Table 3.1-1. Control and Status Registers
Offset(Hex)

Register

Mode1

Default

Primary Function

Ref

0000

BOARD CONTROL

RW

2202 00A0h

Board Control Register (BCR).

3.2

0004

DIGITAL I/O PORT

RW

00XX 00XXh

16-Bit Digital I/O port data.

3.9

0008

ANALOG OUTPUT CHAN 00

RW0000 8000h

Output Channel 00 data.

3.12

000C

ANALOG OUTPUT CHAN 01

RW

0000 8000h

Output Channel 01 data.

3.12

0010

ANALOG OUTPUT CHAN 02

RW

0000 8000h

Output Channel 02 data.

3.12

0014

ANALOG OUTPUT CHAN 03

RW0000 8000h

Output Channel 03 data.

3.12

0018

ANALOG INPUT BUFFER

RO

00XX XXXXh

Analog input buffer data.

3.4.5
3.7

001C

RATE GENERATOR A

RW

0000 00C8h

Rate-A generator divider; 24 bits.

0020

RATE GENERATOR B

RW

0000 3E80h

Rate-B generator divider; 24 bits.

3.7

0024

INPUT CONFIGURATION

RW

FF00 0400h

Analog inputs channel-mask andburst-size.

3.4.2

0028

INPUT BUFFER SIZE

RO

0000 0000h`

Number of data values in the input
buffer.

3.4.5.2

002C

INPUT BUFFER THRESHOLD

RW

0003 FFFEh

Input buffer status flag threshold.

3.4.5.20030

PRIMARY STATUS

RW

0000 0X00h

Principal status-flag register

3.11

0034

ASSEMBLY CONFIGURATION

RO

000X XXXXh

Options and firmware revision.

3.16

0038

Autocal Values

RW

0000 XXXXh

Autocal value readback.

---

2

003C

BUFFERED OUTPUT OPERATIONS

RW

0000 104Fh

Buffered Analog Outputs Control

3.13.2.30040

OUTPUT BUFFER THRESHOLD

RW

0003 FFFEh

Output buffer status flag threshold.

3.13.2.3

0044

OUTPUT BUFFER SIZE

RO

0000 0000h

Number of data values in the output
buffer.

3.13.2.3

0048

ANALOG OUTPUT BUFFER

WO

0000 0000h

Analog Output Data Buffer.

004C

RATE GENERATOR C

RW

0000 00C8h

Rate-C generator divider; 24 bits.

3.13.4.1.20050005C(Auxiliary Registers)

RW

0000 0000h

Four auxiliary 32-Bit user registers.

---

0060

ANCILLARY CONTROL

R/W

0000 0000h

I/O Isolation and ADC Warp mode

3.18, 3.190064007C(Reserved)

---

---

Notes:

3

3.13.2---

1. RW = Read/Write, RO = Read-Only, WO = Write-Only.
2. Maintenance register; Shown for reference only.
3. Firmware Revisions 0102 and higher. These auxiliary registers have no internal functions.

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CCVPX-16AISS8AO4C

Table 3.2-1. Board Control Register (BCR)
Offset: 0000h
Bit

Default: 2202 00A0h

Mode 1

DesignationDef

D00-D02RW

ANALOG INPUT MODE

D03

RW

ANALOG INPUTS AUTOCAL

0

2

0

D04-D05RW

INPUT RANGE A

2

D06-D07

RW

INPUT RANGE B

2

D08

RW

INPUT S/W CLOCK

D09
D10

RW
RO

ENABLE INPUT BURSTINPUT BURST BUSY

0
0

D11

RW

INPUT S/W TRIGGER

2

0

D12
D13

RW
RW

ENABLE INPUT BUFFER
2
CLEAR INPUT BUFFER

D14

RO

INPUT BUFFER THRESHOLD FLAG

D15

RW

INPUT BUFFER OVERFLOW

0

D16-D17RW

OUTPUT RANGE

2

D18

RW

SIMULTANEOUS OUTPUTS

0

D19

RW

ENABLE BUFFERED OUTPUTS

0

D20

RW

OUTPUT S/W CLOCK

D21

RW

TRIGGER INITIATOR

0

D22

R/W

ENABLE RATE-C GENERATOR

0

D23

R/W

INPUT BUFFER UNDERFLOW

0

D24

RW

ANALOG INPUT CLK INITIATOR

0

D25

RW

OFFSET BINARY

1

D26
D27

RW
RW

ENABLE RATE-A GENERATORENABLE RATE-B GENERATOR

0
0

D28

RW

AUTOCAL

D29

RO

AUTOCAL PASS

1

D30

R/W

SWAP DEMAND MODE CHANNELS

0

D31

RW

INITIALIZE

2

0

0
0
3

2,3

0

2

2

Notes: 1. RW = Read/Write, RO = Read-Only.

0

0

0

Description

Ref

Analog input mode:
0 => Differential system inputs
1 => Single-ended system inputs
2 => Zero selftest
3 => VREF selftest
4 => Output Channel 00
5 => Output Channel 01
6 => Output Channel 02
7 => Output Channel 03

3.4.1

Initiates an analog-inputs autocalibration operation.

3.10

Analog input Range-A; Channels 00, 01, 04, 05:
0 => ±2.5V
2 => ±10V
1 => ±5V
3 => (Reserved)
Analog input Range-B; Channels 02, 03, 06, 07:
0 => ±2.5V
2 => ±10V
1 => ±5V
3 => (Reserved)
Initiates a single sample of active input channels.
Overrides existing input clocking source.
Enables triggered burst input acquisition.
HIGH when a triggered input burst is in progress.
Initiates a single input data burst. Overrides
existing burst triggering source.
Enables the analog input buffer for accepting data.
Clears (empties) the analog input data buffer.
HIGH when the number of values in the input buffer
exceeds the selected buffer threshold.
Set HIGH if the input buffer overflows. Stays HIGH
until cleared from the bus or by a board reset.
Analog Output Voltage Range:
0 => ±2.5V
2 => ±10V
1 => ±5V
3 => (Reserved)
When HIGH, all outputs update simultaneously inresponse to an output clock. When LOW, each
output is updated immediately when new data isreceived.
When HIGH, enables the analog output FIFO
buffer, and disables the analog output registers
ANALOG OUTPUT CHAN xx.
Produces a single analog output clock. Overrides
existing output clocking source.
Configures the shared analog input/output
hardware trigger pin as an output if HIGH, or as an
input if LOW.
Enables the Rate-C generator for analog outputs.
Set HIGH if the input buffer underflows. Stays
HIGH until cleared from the bus or by a board
reset.
Configures the analog input I/O clock as an output
if HIGH, or as an input if LOW.
Selects offset-binary analog I/O data format when
HIGH, or two's complement when LOW.
Enables the Rate-A generator for analog inputs.
Enables the Rate-B generator for triggered bursts.
Initiates an autocalibration operation whenasserted. Clears automatically upon completion,
Set HIGH at reset or autocal initialization. A HIGH
state after autocal confirms a successful
calibration.
Reverses the default demand-mode DMA channels
for analog inputs and outputs
Initializes the board. Sets all register defaults.

2. Clears automatically.

3.4.3

3.4.3
3.4.4
3.4.4.2
3.4.4.2
3.4.4.2
3.4.5.1
3.4.5.1
3.4.5.2
3.4.5.1
3.12.1
3.13.1.3
3.12.2.2
3.13.4.2
3.12
3.13
3.12.2.2
3.13.4.1
3.4.4.2
3.13.4.1.2
3.4.5.1
3.4.4
3.6
3.7
3.7
3.10
3.10
3.5
3.15
3.3.2

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Table 3.3-1. Configuration Operations
Operation

Maximum Duration

PCI configuration registers are loaded from internal ROM

3 ms

Internal control logic is configured from internal ROM

300 msInternal control logic is initialized

3 ms

Table 3.4-1. Input Configuration Register
Offset: 0024h

Default: FF00 0400h

Mode

Designation

D00-D23RW

BURST BLOCK SIZE

0400h

D24

RW

ENABLE INPUT 00

1

D25

RW

ENABLE INPUT 01

1

D26

RW

ENABLE INPUT 02

1

D27

RW

ENABLE INPUT 03

1

D28

RW

ENABLE INPUT 04

1

D29

RW

ENABLE INPUT 05

1

D30

RW

ENABLE INPUT 06

1

D31

RW

ENABLE INPUT 07

1

Bit

Def

Description
Number of active channel sets acquired during a
triggered burst.
Analog input channel selection mask.

Table 3.4-2. Input Data Buffer
Offset: 0018h
Data Bit
D00

Default: 00XX XXXXhDesignation

Description

DATA00

Data value least significant bit (LSB)

DATA01 - DATA14

Data value intermediate bits

D15

DATA15

Data value most significant bit (MSB)

D16

FIRST-CHANNEL TAG

Tag assigned to first (lowest-numbered) active channel.

D17

END OF BURST (EOB)

Identifies the last input value in a burst.

(Reserved)

Always zero.

D01-D14

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Table 3.4-3. Input Buffer Threshold Register
Offset: 002Ch

Default: 0003 FFFEh

Data Bit

Mode

DesignationDef

D00-D18RW

INPUT BUFFER THRESHOLD

3 FFFEh

D19

RO

INPUT BUFFER THRESHOLD FLAG 10

HIGH when the number of values in the
input buffer exceeds the specified buffer
threshold.

D20-D31

RO

Reserved

0---

Description
Specifies the number of values in the
input buffer, above which the threshold
flag is asserted HIGH.

1. Duplicated in the BCR.

Table 3.7-1. Analog Input and Trigger Rate Generator Registers (Rate-A,B)
Offset: 001Ch (Rate-A), 0020h (Rate-B)

Default: 0000 00C8 (Rate-A), 0000 3E80h (Rate-B)

Data Bit

Mode

DesignationDef

D00-D23

R/W

Ndiv

---

Rate generator frequency control

D24-D31

RO(Inactive)0---

Description

Table 3.7-2. Input Rate Generator Frequency Selection
Ndiv

FREQUENCY Fgen
(64 MHz Master Clock)*

(Dec)

(Hex)

(kHz)

32

20

2000.00

33

21

1939.39---

Fgen (Hz) = Fclk (Hz) / Ndiv--* ±0.003 percent.

Table 3.9-1. Digital I/O Port Register
Offset: 0004h
Data Bit

Mode

D00-D07

RW

D08

Default: 00XX 00XXh
DesignationDef

Description

DIO BYTE 00

XXh

System connector pins DIO 00 through DIO 07.

RW

BYTE 00 OUTPUT

0

Direction control for DIO BYTE 00. When LOW,DIO BYTE 00 is an input field. When HIGH,DIO BYTE 00 is an output field.

D09-D15

RO(Reserved)

0h

Read back as all-zero.

D16-D23RW

DIO BYTE 01

XXh

System connector pins DIO 08 through DIO 15.

D24

RW

BYTE 01 OUTPUT

0

Direction control for DIO BYTE 01. When LOW,DIO BYTE 01 is an input field. When HIGH,DIO BYTE 01 is an output field.

D25-D31

RO(Reserved)

0h

Read back as all-zero.

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Table 3.11-1 Primary Status Register
Default 0x0000 0X00

Offset 0x0030
Selection Bit

1Critical Event

Response2
Bit

Reference
Paragraph

D16

3.10
3.4.5.2

D00

Autocal completed

D01

Input Buffer threshold flag HIGH-to-LOW transition

D17

D02

Input Buffer threshold flag LOW-to-HIGH transition

D18

D03

Input Buffer Overflow or Underflow

D19

3.4.5.1

D04

Analog Input Burst initiated (BURST BUSY LO-HI)

D20

3.4.4.2

D05

Analog Input Burst Completed (BURST BUSY HI-LO)

D21

D06

Analog Input Clock

D22

3.4.4

D07

Analog Output ClockD23

3.13.4

D08

Digital I/O Port DIO 00 LOW-to-HIGH transition

D24

3.9

D09

Output Buffer threshold flag HIGH-to-LOW transitionD25

3.13.2.3

D10

Output Buffer threshold flag LOW-to-HIGH transition

D26

D11

Output Load-Ready Flag HIGH-to-LOW transition

D27

D12

Output Load-Ready Flag LOW-to-HIGH transition

D28

D13

Analog Output Burst ReadyD29

3.13.5.2

D14

Output Buffer Overflow or Frame Overflow

D30

3.13.2.3

3.13.3.3

3.13.3.3
D15(Reserved)

D31

---

1. Event selection. Enables assertion of the corresponding response bit when the selected event occurs.
2. Event response. Asserted HIGH when a selected event occurs. Remains HIGH until cleared LOW.

Table 3.12-1. Analog Output Channel Data Register
Offset: 0008h - 0014h
Data Bit/Field

Default: 0000 8000h
Designation

Description

D00
D01-D14
D15

DATA00
DATA01 - DATA14DATA15

Data value least significant data bit
Data value intermediate data bits
Data value most significant data bit

D16-D31(Reserved)

Data in this field is ignored.

Table 3.12-2 Simultaneous Output Clock Source Selection
Register
BCR

BOR *

Control Bit

S/W Clock(BCR)

Rate-C Gen

External
Input

HIGH

HIGH

HIGH

ENABLE RATE-C GENERATOR

X

HIGH

X

ANALOG OUTPUT CLK INITIATOR

X

HIGH

LOW

SIMULTANEOUS OUTPUTS* Buffered Outputs Operations register (Table 3.14-2).

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Table 3.13-1. Summary of Output Control Parameters
Parameter
Data Control

Mode
Active Channels;
Channel Group

BufferConfiguration

Clock Source

Clocking Mode

Sampling Mode

Description
A single set of all active output channels constitutes an Active
Channel Group. Active channels are selected under a channel
mask.

Data Frame

All data values in the buffer comprise a Data Frame.

Data Coding

Output data can be coded either in offset-binary format or in two's
complement format.

Open

Data read from the buffer is used and then discarded, until thebuffer is empty.

Circular (closed)

Data within the buffer is recirculated. Each value read from theoutput of the buffer FIFO is written back to the input of the FIFO.
An end-of-frame (EOF) flag tracks the movement of data throughthe buffer.

External

External hardware provides the sample clock.

Internal

The sample clock is provided by an internal rate generator, at a
rate determined by the sample rate control register.

Simultaneous

At each clock occurrence, the next channel group (i.e.: a single
group of all active channel values) in the output buffer is transferredto the respective analog output channels. All outputs are updated
simultaneously.

Sequential

At each clock occurrence, the next active channel value in the
output buffer is transferred to the associated analog output
channel, which is updated immediately.

Continuous

The contents of the output buffer are sampled continuously at the
selected clock rate.

Triggered Burst

A single data frame in the buffer is clocked to the outputs.

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Table 3.13-2. Buffered Output Operations Register
Offset: 003Ch

Default: 0000_104Fh

Bit
D00
D01
D02
D03

Mode
R/W
R/W
R/W
R/W

Designation
AO CHAN 00 ACTIVEAO CHAN 01 ACTIVEAO CHAN 02 ACTIVEAO CHAN 03 ACTIVE

Def
1
1
1
1

D04

R/W

ANALOG OUTPUT CLK INITIATOR

0

D05

R/W

ENABLE OUTPUT CLOCKING

0

D06

RO

OUTPUT CLOCK READY

1

D07

R/W

OUTPUT SW CLOCK *

0

D08

R/W

CIRCULAR BUFFER

0

D09

R/W

LOAD REQUEST *

0

D10

RO

LOAD READY

0

D11
D12

R/W
RO

CLEAR OUTPUT BUFFER *AO BUFFER EMPTY

0
1

D13

RO

AO BUFFER THRESHOLD

0

D14
D15
D16
D17

RO
RO
R/W
R/W

(Reserved)
AO BUFFER FULLAO BUFFER OVERFLOW
FRAME OVERFLOW

0
0
0
0

D18

RO

BURST READY

0

D19

R/W

ENABLE OUTPUT BURST

0

D20

R/W

OUTPUT SW TRIGGER *

0

D21

R/W

TRIG AI BURST ON AO

0

D22D31

RO(Reserved)

0

Description
Active-channel mask for analog output
channels. HIGH => Active; LOW => Inactive.

Selects the internal Rate-C generator for output
clocking if HIGH, or the Output Clock I/O hardware
input if LOW.
Enables output clocking when HIGH. Disables
clocking when LOW. Default is LOW (clocking
disabled).
Indicates when HIGH that an output clock will be
accepted. If LOW, indicates that the output will not
respond to a clock.
Produces a single output clock event whenasserted.
Independent of clocking mode.
Duplicated in the BCR.
Selects circular buffer configuration if HIGH, or open
self-flushing buffer configuration if LOW. Access forloading new data into the circular buffer must be
requested by asserting LOAD REQUEST. Default is
LOW; i.e. open buffer.
When set HIGH, requests loading access to thecircular buffer. Initializes LOW.
Set HIGH when the frame index passes throughzero, if both CIRCULAR BUFFER and LOAD
REQUEST are HIGH. When HIGH, indicates thatthe circular buffer is ready to accept new data.
Available also in the PSR. Defaults HIGH.
Resets the output buffer to empty.
Indicates the analog output buffer is empty.
Analog output buffer threshold flag.
Duplicated in the AO Buffer Threshold register.
Inactive; Returns zero.
Indicates the output buffer is full.
Set HIGH when data is written to a full buffer. **Set HIGH when data is written to a closed buffer. **If HIGH, indicates that a burst trigger will be
accepted. If LOW, indicates that the output will not
respond to a trigger.
Enables analog output burst operation.
Produces a single output trigger event whenasserted. Clears LOW automatically when the clock
event is completed.
Independent of triggering
mode.
Synchronizes triggering of analog input bursts toanalog output bursts.
Inactive. Returns all-zero.

* Clears LOW automatically when operation is completed.
** Remains HIGH until cleared by a direct write as LOW, or by initialization.

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A-9

Ref
3.4.1.1

3.13.4.1

3.13.43.13.43.13.4.1

3.13.2.5

3.13.3.3

3.13.3.3

3.13.2.3
3.13.2.3
3.13.2.3--3.13.2.3
3.13.2.3
3.13.2.3
3.13.53.13.5.2
3.13.5.2

3.17---

CCVPX-16AISS8AO4C

Table 3.13-3. Analog Output Buffer
Default: N/A (Write-Only)

Offset: 0048h
Bit

Mode*

Designation

Description

D00

WO

DATA 00

Least significant data bit

D01-D14WO

DATA 01 - DATA 14

Intermediate data bits

D15

WO

DATA 15

Most significant data bit

D16

WO

EOF FLAG

End-of-frame (EOF) flag.

D17-D31

WO---(Inactive)* WO indicates write-only access. Read-access returns all-zero value.

Table 3.13-4. Output Buffer Size Register
Offset: 0044h

Default: 0000 0000h

Bit Field

Mode

Designation

D00-D18RO

BUFFER SIZE

D19-D31

RO(Inactive)

Default

Description

0 0000h

Number of values in the output buffer0---

Table 3.13-5. Output Buffer Threshold Register
Offset: 0040h

Default: 0003 FFFEh

Bit Field

Mode

Designation

Default

Description

D00-D18RW

OUTPUT BUFFER THRESHOLD

3 FFFEh

Specifies the number of values in the output
buffer, above which the threshold flag isasserted HIGH.

D19

RO

OUTPUT BUFFER THRESHOLD FLAG0HIGH when the number of values in the
output buffer exceeds the specified buffer
threshold.

D20-D31

RO

Reserved

0---

Table 3.13-6. Output Sample Rate Control Register (Rate-C)
Offset: 004Ch

Default: 0000_0038h

DATA BIT

MODE

D00

R/W

DESIGNATIONRATE 00

DESCRIPTION
Least significant rate bit

D01-D22R/W

RATE 01 - RATE 22

Intermediate rate bits

D23

R/W

RATE 23

Most significant rate bit

D24-D31

RO---

Inactive. Returns all-zero.

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Table 3.13-7. Output Sample Rate Selection
Ndiv

FREQUENCY Fgen
(64 MHz Master Clock)*

(Dec)

(Hex)

(kHz)

32

20

2000.00

33

21

1939.39---

Fgen (Hz) = Fclk (Hz) / Ndiv--* ±0.003 percent.

Table 3.16-1. Assembly Configuration Register
Offset: 0000 0034h
Default: 00XX XXXXhBIT FIELDDESCRIPTION

D00-D11

Firmware Revision

D12-D15(Reserved bit field; all-zero)

D16

Number of analog input channels:
0 => 8 Analog input channels.
1 => 4 Analog input channels.

D17

Number of analog output channels:
0 => 4 analog output channels.
1 => No analog outputs.

D18-D19

Master clock frequency:
0 => 64.000MHz
1 => (Reserved)
2 => (Reserved)
3 => (Reserved)

D20-D31(Reserved bit field; returns all-zero).

Table 3.18-1. Ancillary Control Register
Offset: 0060h
Data Bit

Access
Mode

D00

R/W

D01

Default: 0000 0000
Designation

Default

Function

ISOLATE INPUT CLK IO PIN

0When HIGH, configures the INPUT CLK
I/O pin as a logic LOW output.

R/W

ISOLATE TRIGGER IO PIN

0When HIGH, configures the TRIGGER
I/O pin as a logic LOW output.

D02

R/W

ISOLATE OUTPUT CLK IO PIN

0When HIGH, configures the OUTPUT
CLK I/O pin as a logic LOW output.

D03

R/W

ADC WARP MODE

0

When HIGH, selects the ADC Warp
mode.

D04-D31

RO(Reserved)

0h

---

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CCVPX-16AISS8AO4C

Appendix-B
Migration from PMC66-16AISS8AO4____________________________________________________________________________
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CCVPX-16AISS8AO4C

Appendix B
Migration from PMC66-16AISS8AO4Operation of the CCVPX-16AISS8AO4C is very similar to that of the PMC66-16AISS8AO4. Thisappendix summarizes the principal similarities and differences between the two products, and isprovided as a general guide rather than a definitive list of requirements.
B.1. Comparison of Features
Table B.1 provides a brief comparison of PMC66-16AI32SSC and CCVPX-16AI32SSC1M features.
Table B.1. PMC66-16AISS8AO4, CCVPX-16AISS8AO4C Features Comparison
FeaturePMC66-16AISS8AO4CCVPX-16AISS8AO4C

Input Channels

8 Differential

Output Channels

4 Single-ended

Conversion Resolution

16 Bits

Input/Output Ranges±10V, ±5V, ±2.5V

Maximum Clocking Rates

2MSPS inputs, 1MSPS outputs

Host Interface *PCI 2.3; D32; 33MHz/66MHzPCI Express, Single lane

Master Clock

40MHz

64MHz

* The host adapter (PEX-8311) provides the same local interface for both the CCVPX-16AISS8AO4C and
PMC66-16AISS8AO4 products, thereby assuring a transparent software-control transition from PMC66-16AISS8AO4 to
CCVPX-16AISS8AO4C.

B.2. Migration Issues
General:1. The system I.O connector has changed.
2. The host bus has changed from PCI to PCI Express.
3. The master clock frequency has changed from 40MHz to 64MHz.
Section 2.0. Installation and Maintenance:
Paragraph 2.2.2:
The system I/O connector pin-count has changed from 80 Pins to 85 Pins..
Section 3.0. Control Software:
Paragraphs 3.7, 3.13.4.1.2, 3.16:
The standard master clock frequency has changed from 40MHz to 64MHz.

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Revision History:
04-03-2017: Origination as Preliminary Draft.
08-03-2017: Para 3.3.2: Revised reference pertaining to AO default.

Copyright (C) 2017 General Standards Corp.
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FAX:(256) 880-8788
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General Standards Corp. makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for aparticular purpose. Although extensive editing and reviews are performed before release to ECO control, General Standards Corp. assumes no responsibility for any errorsthat may exist in this document. No commitment is made to update or keep current the information contained in this document.
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General Standards Corp. reserves the right to make any changes, without notice, to this product to improve reliability, performance, function, or design.
All rights reserved.
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