Cycle Identification
Yizhou Li (Huawei)

Jeong-dong Ryoo (ETRI)

Guanhua Zhuang (Huawei)

Li Dong (Shenyang Institute of Automation)

Jiang Li (Huawei)

Wenbin Dai (Shanghai Jiao Tong University)

Sept, 2022

1

Introduction• 802.1Qdv proposes to
1. Store received frames into multiple cyclic bins based on the time ofreception of the frame
2. Bins are drained in rotation manner at a fixed interval (i.e. cycle/cycle timein the slides)• Goal of the slides• Show the goal to improve the bandwidth utilization in small cycle• Discuss the cycle ambiguity problem when making dead time (DT) minimum
to improve the utilization• Propose to use cycle id based determination in addition to time based one in802.1Qdv• Provide three options to carry cycle id2

DT (dead time) is the key to absorb the time variation/Cycle time T

Node A(transmitter)

T1

T2
DT

Node B(receiving &processing)

T3
DTDT

T1

T2

Label 1

Label 2• DT (Dead time)：time imposed in a cycle toTime window for sending orensure that the last byte sent in node A’s cycle
receiving frames (not a single frame)
x is fully received and ready to be sent at thestart of node B’ cycle y, where cycle y is usually
the earliest available cycle to meet such aT4
T5
DTDT
requirement
Dead time imposed at each cycle

DTT3• DT (*) = output delay at node A + link delay +preemption delay + processing delay at node B

T4• Link delay will not contribute to DT if node B’s
receiving side offsets the cycle start time by link delay• DT << T, so DT is negligible conventionally

Link delay• cycle time T is normally ~100x μs• DT is ~10x μs• DT/T < 5% generallyCycle time T

Node B(transmitter)

T1

T2
DT

T3
DTT4
DTDTtime• Frame reception time at node B determines towhich bin the frame should be put(*): draft-ietf-detnet-bounded-latency

3

Utilization unacceptably low in small cycle• E2e latency and jitter is proportional to cycle time T and #of hops h• E2e delay ≈ h * T; jitter = 2T

• Desire to use smaller T for better latency and jitter• To achieve e2e latency (e.g. < 1ms) or large # of hops (e.g. 10+)
• A known app cycle 31.25 μs; cycle T < 31.25 would be desired• Should support T in the order of ~10x μs• DT is in the order of ~10x μs as well
• DT and T are in the same order then

• Utilization decreases when cycle time T decreases• DT eats T, e.g. ≈50% when T=40 μs & DT=20 μs
Cycle T1 = 100x μs

T2 = 10x μs
DTDT

Unacceptably low utilization
4

Hardware and Software frame reception time used foroutput bin determination
DTDead time imposed at each cycle/Time window for sending or receiving
frames (not a single frame)

Cycle time T

Node A(transmitter)

Node B(receiver, i.e.
hardwarereception time)
Node B(processing,i.e. software
reception time)

Hardware reception time

T1

T2
DT

T3
DTDT

DT

T1

T2

Label 1

Label 2

• Timestamp every data frame with the 1st bit reception time atphy layer• Output delay at node A contributes to time variation• Each frame offset by link delay at minimum• Not always available in practice

T4

T3

T4

Software reception time• Time at the moment that the frame starts the processing• Generally available in implementations, e.g. high mac layer inprogrammable NP• Frames in a cycle experience the variable delay in Node B.

Link delay

T1

T2

Label 1

Label 2

T3

T4Why?
• Store the variable frame size
• Variable residence time before frame started being
processed, e.g. by PBA (packet bus arbiter) or buffering

Cycle time T

Node B(transmitter)

T1

T2
DT

T3
DT

T4DTDT• The following slides uses the software reception
time to determine to which bin the frame shouldbe put at node Btime
5

Goal - Improve the utilization in small cycle T
T1

Node A(transmitter)
Node B(software
receptiontime)
Node B(transmitter)

T2
DT

T1 rcvwindow

T3

T4

Low utilization
with large DT

DT

T2 rcvwindow

Node B(software
receptiontime)
DT

DT

T1

Node A(transmitter)

T2

T3

T4

Node B(transmitter)

T1

T2
DT

T3

High utilization
with small DT

T4DT

T2 rcv window
T1 rcv window

Cycle
ambiguity time

DT

T1

T2

DT

T3

T4timetime• Why low utilization? DT is relatively too large.
• A straightforward way to improve utilization: make DT minimum• Absorb only the preemption delay instead of the full time variation, i.e. curve out output delay and processing delay• A remaining problem: cycle ambiguity in reception time based bin determination
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Propose to use the explicit cycle identification

Node A(transmitter)

T1

T2
DT

1

DT

Dead time imposed at each cycle/

Time window for sending or receiving
frames (not a single frame)

T3

T4

DT

2

Cycle ambiguity time

Node B(softwarereception time)

Node B(transmitter)

1

11 22

D
T

T1T2

• Carry cycle id and change per hop• Use cycle id based output bin
determination instead of time
based
• Remove the ambiguity• Achieve the good utilization in small
cycles by making DT minimum

DT

T3

T4time7

How to carry a cycle id
1. R-tag (defined in 802.1CB)
Ethertype (F1-C1)

Reserved (16-bit)

Sequence number (16-bit)

Define a subtype flag and use the last 4-bit in Reserved field for cycle id.
Ethertype (F1-C1)

Reserved (16-bit)
Sequence number (16-bit)flag(1) Rsvd (11) Cycle id (4)8How to carry a cycle id (cont’d)
2. Define a new cycle-tag
Ethertype(cycle-tag)

Subtype Reserved Cycle ID(4-bit)(4-bit)(8-bit)9

How to carry a cycle id (cont’d)
3. Use vlan stacking + vlan mapping function• Inner vlan is used for cycle id, use ACL to map from ingress cycle id toegress cycle id• Outer vlan is used as normal vlan based mac learning and forwarding• Used in a controlled domain, may not be compatible with some existing svlan + c-vlan usage
Ethertype (s-vlan)

vlan-tag (16-bit)

Ethertype (c-vlan)

Cycle id (16-bit)

ACL example: if-match cvlan-id cycle-id-in
remark cvlan-id cycle-id-out

10

backup11

Cycle id used in the extension to traditional 2-buffer CQF
T1

Node A(transmitter)

T2

T3

T4

DTDT

Traditional 2buffer CQF

Link delay

Link delay

Node B(software
receptiontime)

Node B(receiver)

Node B(transmitter)

T1’

Node A
1 DT(transmitter)

T1

T2

T3

T3’ T4’
DT

2

DT

3

T5’

T6’

T7’ T8’

DT1Cycle ambiguities
223Use 3-buffer
CQF carrying
cycle id withthe smaller
cycle T

Check cycle id

1 DT 2 DT 3 DT 1 DT
Node B(transmitter) T1’ T2’ T3’ T4’ T5’ T6’ T7’ T8’DTDT

T2’T4time•

Demand to have the restricted extension to traditional 2-buffer CQF usage•

Re-use traditional CQF as much as possible•Nodes sync their cycles as usual, gate open/close controlled by sync’ed time

•Utilization gets worse as DT can not curve out the link delaytime

Restricted extension:•Use 3 buffer rotation with the smaller buffer space each•

Set cycle T smaller, e.g. half of the original in pic above•

Cycle id based determination works well to solve the ambiguity in this case and improve the utilization effectively
12Procedures when using frame 1st bit hardware
timestamping
Node A(transmitter)

T1

T2
DTDT

Dead time imposed at each cycle/Time window for sending or receiving
frames (not a single frame)

T3

T4

DT

T1

T2

timestampDD
timestamp
TT

Node B(receiver,Hardware
timestamping)t0

Node B(processing,With hardware
timestamp info)

t0

T3

T4

t1

t2

t3

t1

t2

t3

Cycle ambiguity time, but withtimestamp on each framettCheck timestamp ts
t1<ts<t2

Node B(transmitter)

DT

T1

T2

DT

T3

T4

• Time variation before hardware
timestamping has to be put into DT,e.g. output delay, clock/timestamp
accuracy• Time variation after hardware
timestamping has no more impact• Check timestamp for each frame atprocessing phase to determine theoutput bin in order to remove cycle
ambiguity• Requires:• Native hardware support. Can not bedone in programmable NP.
• Time variation before timestamping has
to be negligible since it contributes to DT.
• DT here is always larger than the value
used in cycle-id case since it can not curveout this part of variation.
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