Switching Loss Reduction of MOSFET
Using Switching Assist Circuit
Toshihiko Noguchi

Munehiro Murata

Department of Electrical and Electronic Engineering,
Graduate School of Engineering,
Shizuoka University
3-5-1 Johoku, Naka-Ku, Hamamatsu,
Shizuoka 432-8561, Japan
ttnogut@ipc.shizuoka.ac.jp

Department of Electrical and Electronic Engineering,
Graduate School of Engineering,
Shizuoka University
3-5-1 Johoku, Naka-Ku, Hamamatsu,
Shizuoka 432-8561, Japanf0330137@ipc.shizuoka.ac.jp

Abstract—This paper describes a new high-efficiency andhigh-speed switching method of a MOSFET using a switchingassist circuit fed by the gate drive power supply. By applying the
proposed circuit to a chopper and an inverter, a turn-off time of
the MOSFET can be effectively reduced, which allows a higherfrequency operation and reduction of the turn-on loss. In thecase of the application to the inverter, the total efficiency can be
improved by 14.8 points in the low-load range owing to the
reduction of the turn-on loss of the MOSFET.

capacitance is one of the great concerns, which may fade away
the above excellent features.

Keywords— MOSFET, high-speed switching, parametric
design, turn-on ,turn-off, switching loss, auxiliary circuit, chopper,
inverterI.

INTRODUCTION

In recent years, great attention has been paid to nextgeneration semiconductor devices such as SiC (Silicon
Carbide) based MOSFETs and diodes because they are very
promising and attractive as power switching devices forvarieties of near-future power converters [1]-[5]. The SiC
based devices have the following significant features, which
completely surpasses conventional Si (Silicon) based
semiconductor devices:(1) approximately ten times higher voltage ratings than Si
based devices;(2) 105 V/μs-class switching speed;(3) as low on-resistance as 1/200 to 1/500 of conventional
MOSFETs; and(4) over 300 °C junction temperature.
These are very attractive features to improve the power
density as well as the efficiency of the power converters
dramatically. However, there still remain many problems tobe solved from the viewpoint of practical implementation ofsuch SiC based MOSFETs. One of the problems is anextremely high-speed operation without sacrificing the power
converter efficiency. In general, the parasitic capacitor of the
MOSFET disturbs the high-speed switching operation because
the turn-on and the turn-off times become longer due to theparasitic capacitor. To make matters worse, as the onresistance becomes lower and the drain current becomes
higher, the MOSFET tends to increase its parasitic capacitance.
Similarly in the case of the SiC power devices, the parasitic

978-1-4799-7799-4/15/$31.00 ©2015 IEEE

1198

It is necessary to reduce both of the turn-on time and theturn-off time to achieve high-speed switching of the MOSFET.
Particularly the turn-on time can be adjusted by controllingelectrical charge to the input parasitic capacitance.
Conventional approaches have been taking some simple
techniques to speed up the turn-on time, e.g., reducing the gate
resistance of the MOSFET, and connecting a speed-up
capacitor in parallel with the gate resistor. Recently anothernew gate drive circuit is proposed, which introduces an
inductive impulse superposition technique to drive the highspeed MOSFET [6]-[9]. The superposed impulse gate current
allows extremely fast charge to the parasitic input capacitor of
the MOSFET, resulting in speed-up of the turn-on. On theother hand, it is difficult to speed up the turn-off behaviour bytuning the gate drive circuit because the turn-off time ismainly determined by the charging time of the output parasitic
capacitor across the source and the drain. The authors haveproposed a new switching method of the MOSFET using aswitching assist circuit which makes a short circuit across theload [10]. The proposed method can reduce the turn-off timeby connecting the auxiliary circuit in parallel with the load.
However, the method has a drawback because it requires
modification of the main circuit.
The percentage of the switching loss to the whole power
loss becomes large in the high-frequency operation of thepower converter. The output parasitic capacitor of the
MOSFET used in the power converter such as the inverter
cannot be discharged perfectly in the low-load range during
the dead time period. Otherwise, the body diode of the
MOSFET turns on during the dead time period. As a result,the short circuit current flows through the switching device tocharge up the output parasitic capacitor when thecorresponding counterpart switching device turns on. In
addition, a large reverse recovery current is superimposed tothe short circuit current when the body diode is turned off.
The short circuit current causes the large turn-on loss which is
the major part of the switching loss in the case of the lightload operation. The turn-on loss caused by the recovery
current of the body diode can be reduced by using therecovery assist circuit, but the charging current of the output
parasitic capacitor cannot be suppressed [11].
In general, there are two manners to operate the powerswitching devices, i.e., one is a soft switching technique andthe other is a hard switching technique. The former technique
is basically employed to reduce the switching loss as well as
the radiation and the conduction noises [12]-[17]. However,
the technique can inherently reduce the switching loss bylowering dv/dt and di/dt, so it is rather difficult to achieve ahigh-frequency operation of MHz-class because the lowered
dv/dt and di/dt increase the switching transient time.
Therefore, this paper proposes a new alternative approachto achieve the high-speed switching operation of the MOSFET
with a large output parasitic capacitor. By using the proposed
switching assist circuit fed by the gate drive power supply, theswitching loss of the MOSFET can be effectively reduced
without any modification of the main circuit [18]. The
purpose of this auxiliary circuit is not a soft-switching but ahard-switching operation, and it makes not only the highspeed switching but also the high-efficiency operation possible
by enhancing the dv/dt. The proposed method is applied to achopper and a half-bridge inverter as well in this paper, and it
has been confirmed that the switching assist circuit is effective
to enchance the performance of the MOSFET.
II. MOSFET SWITCHING ASSIST CIRCUITFED BY GATE DRIVE POWER SUPPLY
A. Configuration and Operation Principle of Proposed
Auxiliary Circuit
Figure 1 shows the MOSFET switching assist circuit fed
by the gate drive power supply, which is an application of thesimple voltage boost converter. C1 is not a snubber circuit but
an output parasitic capacitor of the main switching device S1.
The gate drive power supply Ed1 and the power source of theauxiliary device Sc1 and S1 are connected on a common
potential. Therefore, S1 and Sc1 can be driven by only asingle gate drive power supply. The zener diode ZD1 isrequired to prevent the auxiliary circuit from circulating thecurrent through S1 while S1 is turned on. Because the current
rating of the zener diode is low, three devices are actuallyconnected in parallel to enlarge the current rating.
In the conventional circuit of the power converter such as
the buck chopper and the half-bridge inverter, if the main
circuit current flows in the direction which charges C1, inother words, if the drain current of the MOSFET id1 is positive,
C1 is charged as soon as S1 is turned off. Therefore, the turnoff time is determined by id1 and C1; thus, if id1 is low enough,the turn-off time becomes longer. On the other hand, in thecase of id1 is negative, the body diode D1 turns on when themain switching device is turned off; hence C1 cannot becharged entirely. In the proposed circuit, Sc1 is turned onprior to turning off S1 to store the energy in the inductor Lc1.
Sc1 is turned off as soon as S1 is turned off to transfer theenergy from Lc1 to C1. It makes the high-speed switchingpossible regardless of the load power. Figure 2 shows theswitching pattern of the auxiliary circuit. In the mode 1, the1199

Fig. 1. Switching assist circuit fed by gate drive power supply.

Fig. 2. Switching pattern of switching assist circuit.

energy is charged in Lc1 through the path
Ed1→Dc1→Lc1→Sc1→Ed1 by turning on Sc1. In the mode
2, the current commutates to the path Ed1→Dc1→Lc1→Dc2→ZD1→C1→Ed1 by turning off Sc1, so C1 is charged
rapidly. When id1 is positive, the energy of Lc1 can betransferred to the main circuit without consideration of thevalue of id1. However, if id1 is negative, the current of Lc1
keeps flowing as a constant value which is determined by id1even if Sc1 is turned off. Therefore, the limited energy of thedifference between ilc1 and id1 is transferred. The charging timeof C1 is basically determined by the resonance frequency of
Lc1 and C1.
B.

Parameter Design of Switching Assist Circuit
The parameters of the auxiliary circuit are designed,
assuming that id1 is zero. To achieve the high-speed switchingby using the proposed circuit, the energy balance condition
must be satisfied as expressed by

1
1
C1vds12 = Lc1ilc12 ,
2
2

(1)

where vds1 is the voltage applied across S1 and ilc1 is the peakcurrent flowing through Lc1. ilc1 is determined by Ed1, Lc1,
and t, where t is on-time duration of Sc1. Consequently, ilc1 isgiven asilc1 =

Ed1
t.
Lc1

(2)

By substituting (2) into (1), (1) can be rewritten as thefollowing expression:
C1vds12 =Ed12 2
t .
Lc1

(3)

Therefore, there still remain the undetermined parameters
Lc1 and t in the auxiliary circuit, where other parameters vds1,
Ed1, and C1 are already given. Hence, if either parameter ofDetermine xu and tu
Calculate xc from (7)and tc from (5)xu > xc andtc > tuNoYest = tuCalculate Lc1 from (6)Fig. 4. Proposed buck chopper with auxiliary circuit.

t = tcCalculate Lc1 from (4)Calculate ilc1 from (2)Fig. 3. Flow chart to determine parameters of switching assist circuit.

Lc1 or t is determined, the other parameter can be resultantly
derived. The first method to determine the parameters is a
way to design t after determination of Lc1. The charging timeof C1 is determined by quarter of the resonance period
governed by Lc1 and C1. Therefore, Lc1 can be simply
expressed by

Lc1 =4 x 2T 2

π 2C1

,

(4)

where T is the switching operation period of S1 and x is the
charging time in percentage with respect to the operation
period T. As a result, t can be calculated as follows:t=

vds1 2 xT
.
Ed1 π

(5)

t must be within T, so it is difficult to make switching Sc1
possible if t is too long. Due to this restriction, when t reaches
a certain prefixed time, this method is no longer applicable.
Then any value x is defined as xu (upper limit), and calculated
t is defined as tc (calculated value). The other method todesign the auxiliary circuit parameters is a way to derive Lc1
under the condition of the given value of t. When on-time of
Sc1 is t, Lc1 can be derived as2⎛ Ed1 ⎞ t 2⎟
Lc1 = ⎜⎜.
⎟
⎝ vds1 ⎠ C1

(6)

In consequence, x is obtained as
x=

π Ed1
t.
2T vds1(7)

When x is too large, the auxiliary circuit is not effective to
make the high-speed switching possible. Accordingly, if x
reaches a constant predetermined percentage, this condition is
no longer used. Then any value t is defined as tu (upper limit),

1200

and calculated x is defined as xc (calculated value). The
parameters of the auxiliary circuit are determined under theconditions that both calculated values xc and tc does not exceed
the upper limits xu and tu, respectively. Figure 3 shows a flow
chart to design the auxiliary circuit parameters. At the
beginning of the flowchart, xu and tu are determined. xc and tc
are calculated from (5) and (7). If xu > xc and tc > tu, Lc1 isderived from (6) as t = tu. On the other hand, if xc > xu and tu >tc, Lc1 is determined from (4) as t = tc. ilc1 is computed from
(2) to select the appropriate switching device of the auxiliary
circuit in terms of the current rating.
III. APPLICATIONS OF PROPOSED AUXILIARY CIRCUITAND THEIR OPERATION CHARACTERISTICS
A. Buck Chopper with Proposed Auxiliary Circuit
This section describes that the output parasitic capacitor of
the MOSFET can be quickly charged by applying the auxiliary
circuit to a buck chopper. Figure 4 shows the buck chopperwith the proposed auxiliary circuit. The turn-off time toff ofthe conventional circuit is determined by id1 and C1.
Accordingly, toff is given ast off =

EC1
.
iL

(8)

Thus, if the load resistance is high, toff becomes longer.
Particularly it is difficult to speed up the switching time in the
low-load range. In the proposed circuit, Sc1 is turned on prior
to turning off S1 to store the energy in the inductor Lc1. Sc1
is turned off as soon as S1 is turned off to transfer the energy
from Lc1 to C1. The proposed auxiliary circuit makes thehigh-speed switching possible regardless of the load condition.
In this application, it is not necessary to care the relationshipbetween iL and the current charging C1 because id1 is always
positive.
The parameters of the auxiliary circuit are designed asfollows: the main power supply voltage E is 140 V; S1 is
STY60NM60 (Coss = 2000 pF); Ed1 is 12 V; and the switchingfrequency is 100 kHz. When xu is 2.5 % and tu is 4 μs, tc= 1.8
μs and xc = 5.3 % are calculated from (5) and (7), respectively.
As a result, t is tc and Lc1 is derived to be 13 μH from (4)because xc > xu and tu > tc. This derivation of the parameters is
conducted in the ideal state, but there is a power consuming
factor such as a forward voltage drop of the auxiliary diodes.

id1
E1

Auxiliarycircuit

S1

D1

vL
Load
E2

Auxiliarycircuit(a) Conventional circuit.
(b) Proposed circuit.
Fig. 5. Experimental waveforms of buck chopper.

Actual duty cycle (%)

vds1

vgs1

iL
S2

C2
D2

vds2

vgs2

Fig. 7. Proposed inverter with auxiliary circuit.

80
70
Conventional circuit
Proposed circuit

60
50
40

.

C1

Fig. 8. Switching sequence of proposed inverter with auxiliary circuit.

0

30

60

90

120 150 180 210

Load power (W)Fig. 6. Load power-actual on-duty cycle characteristic.

Therefore, t must be modified from 1.8 μs to 3 μs to satisfy(1), for example. ilc1 is calculated to be 2.8 A from (2) in thiscase. For this reason, STP12NM60 as Sc1, D06S60 as Dc1
and Dc2, and 1N5349BG as ZD1 are employed in the test
circuit.
Figure 5 shows the output waveforms of the conventional
and the proposed circuits for 13-W output power. In order to
conduct the experiments in this operating condition, a 800-Ω
and 0.8-mH RL load, a 100-kHz switching frequency, and a
50 % duty cycle are adopted to the test circuit. It is confirmed
from the figures that toff of the proposed circuit is much shorter
than that of the conventional circuit. Since C1 is quickly
charged by using the auxiliary circuit, the turn-off dv/dts of
vds1 are 0.16 kV/μs and 1.49 kV/μs, respectively, so the turnoff dv/dt of the proposed circuit is approximately 9 times
higher than that of the conventional circuit. Figure 6 shows acharacteristic between the load power and the actual duty
cycle. It can be seen in the figure that the proposed circuit
operates around 50 % regardless of the load power even in the
low-load range, while the conventional circuit can no longer
operate at 50 % duty cycle as the load power is reduced. Thisis because C1 cannot be charged due to the low-load current in
the low-load range. It has been confirmed through the above
experimental tests that the high-speed switching operation ispossible by using the proposed technique.
B. 50 % Duty Cycle Rectangular Waveform Operation of
Half-Bridge Inverter with Proposed Auxiliary Circuit
This section explains the turn-on loss reduction by meansof reducing the short circuit current when the auxiliary circuit
is applied to 50 % duty cycle rectangular waveform operation

1201(a) Polarity of id1 is positive(b) Polarity of id1 is negative
Fig. 9. Short-circuit current path of conventional circuit.

of the half-bridge inverter. Figure 7 shows another applicationof the proposed auxiliary circuit to the half-bridge inverter,and Figure 8 shows the switching sequence of the proposed
inverter. During the dead time period tdead to avoid a shortcircuit across the DC bus, the charging time and thedischarging time of C1 and C2 are determined by iL and thetotal capacitance of C1 and C2. iL required to charge theoutput parasitic capacitor perfectly during tdead is obtained as
(9)
iL =

( E1 + E 2)(C1 + C 2)
.
tdead

(9)

If tdead is considerably short, the energy stored in C2 isdissipated by turning on S2, and the short circuit current flows
through S2 in the path E1→C1→S2→E2→E1 as shown in
Fig. 9(a); hence the total efficiency is detrimentally affected
due to increase of the turn-on loss of S2. The on-resistance ofmain devices are high in the right moment of turning on themain devices, so the short circuit current becomes a key factorof the large turn-on loss. In the proposed circuit, however, C1

100

Efficiency (%)

80
Conventional circuit
Proposed circuit

60
40
20

(a) Conventional circuit.
(b) Proposed circuit.
Fig. 10. Experimental waveforms of 50 % duty cycle operation of
inverter at 14-W output.

0

Turn-on loss of main devices (W)

30

60

90

120

150

Load power (W)Fig. 12. Load power-efficiency characteristic

12

TABLE I. OPERATION MODES OF AUXILIARY CIRCUIT

10

Polarityof iL

8

Positive

6
4

Negative

2
0

0

0

30

60

90

120

150

Load power (W)Fig. 11. Load power-turn-on loss of conventional circuit characteristic.

and C2 are quickly charged by using the auxiliary circuit justlike the proposed chopper does. Therefore, the short circuitcurrent through the two of the main devices can be effectively
reduced, compared with the conventional circuit. It is notnecessary to consider the load current polarity because id1
always flows in the direction of charging the output parasitic
capacitor in the moment of turning off the main devices.
The parameters of the auxiliary circuit are designed asfollows: the main power supply voltage E1 and E2 are 70 V;
S1 and S2 are STY60NM60 (Coss = 2000 pF); Ed1 is 12 V; theswitching frequency is 100 kHz; and tdead is 250 ns. When xu
and tu are determined to be 2.1 % and 4 μs, (5) and (7) give thevalues tc and xc of 5.4 % and 1.6 μs, respectively. t is tc and
Lc1 is calculated from (4) to be 4.5 μH because xc > xu and tu >tc. This derivation of the parameters are conducted in the ideal
state similarly to the buck chopper case. Therefore, t must be
adjusted from 1.6 μs to 2 μs. ilc1 is reckoned to be 5.3 A from(2). Thus, Sc1 is STP12NM60, Dc1 is IDH12S60C, Dc2 is
D06S60, and ZD1 are 1N5349BG.
Figure 10 shows the output waveforms of the conventional
and the proposed circuits for 14-W output power. A 200-Ω
and 0.2-mH RL load, a 100-kHz switching frequency, and a
50 % duty cycle are applied to the circuits. It is confirmed inFig. 10(a) that the short circuit current flows because theoutput parasitic capacitor cannot be discharged during tdead.
Figure 11 shows the turn-on loss of the conventional circuit.
It can be seen in the figure that the large turn-on loss is causedby this short circuit current in the low-load range. On theother hand, the short circuit current can be remarkably reducedby the proposed circuit as shown in Fig. 10(b). C1 and C2 arecharged quickly during tdead by using the proposed auxiliary

1202

Thresholdcurrent of Sc1( E1 + E 2)(C1 + C 2)
I th1 =
tdead
I th 2 =

Ed1
t
Lc1

Thresholdcurrent of Sc2
I th 2I th1circuit regardless of iL. In addition, the turn-off times of S1
with and without the proposed auxiliary circuit are 450 ns and390 ns, respectively. Figure 12 shows a load power to total
efficiency characteristic including the power consumption of
the auxiliary circuit. It is confirmed from the figure that the
total efficiency of the proposed circuit is higher than that of
the conventional circuit in the low-load range. The proposed
circuit can charge and discharge the output parasitic capacitor
quickly even in the low-load range, so the turn-on loss of themain devices caused by the short circuit current isdramatically reduced. As a result, the total efficiency can be
improved from 62.7 % to 71.7 % for 26-W output power. By
disabling the auxiliary circuit in the heavy-load range, it ispossible to operate the inverter at higher efficiency without
power dissipation of the auxiliary circuit. Because the highefficiency range can be expanded by the auxiliary circuit, theproposed technique is effective for the applications that need avery wide load range.
C. PWM Half-Bridge Inverter with Proposed Auxiliary
CircuitThis section describes the reduction of the large turn-on
loss caused by the charging current of the output parasitic
capacitors and the recovery current of the body diodes, andexplicates the control scheme of the auxiliary circuit in theapplication to the PWM half-bridge inverter. When one of themain switching devices turns off, the direction of the id1 can bepositive or negative because the carrier frequency is muchhigher than the load current fundamental frequency. If thepolarity of id1 is positive and the instantaneous amplitude of id1
is high, it is not necessary to operate the auxiliary circuit asindicated by (9). The load current value which charges theoutput parasitic capacitor perfectly during tdead is defined as
Ith1, and the operation of the auxiliary circuit is disabled when
id1 is over Ith1. On the other hand, under the condition that thepolarity of id1 is negative, C1 is not charged at all even though
the S1 turns off. Thus, the charging current of C1 flows to the(a) Conventional circuit.
(b) Proposed circuit.
Fig. 13. Experimental waveforms of PWM inverter at MI = 0.2.

(a) Conventional circuit.
(b) Proposed circuit.
Fig. 15. Experimental waveforms of PWM inverter at MI = 0.9.

120

Utilization Ratio (%)

100
80
60
40
20
0

0

30

60

90

120

150

Load Power (W)(a) Conventional circuit.
(b) Proposed circuit.
Fig. 14. Expanded views of experimental waveforms of PWM inverter
at MI = 0.2.

Fig. 16. Load power-utilization ratio characteristic.

The load current value is defined as Ith2 when Pt is zero. The
auxiliary circuit is no longer operated if id1 is over Ith2. As
described above, it is necessary to divide the operation modes
by the value and the polarity of id1 which is determined by iL
and the mode classification of the auxiliary circuit as shown in
TABLE I.
The all parameters of the experimental setup other thanthe load resistance are the same as those described in theprevious section, and the fundamental operation frequency is
identical to that of the 50 % duty cycle operation of the halfbridge inverter. Ith1 = 2.2 A and Ith2 = 5.3 A are calculated
from TABLE I. These threshold currents are calculated in the

1203

100
80
Efficiency (%)

path E1→C1→S2→E2→E1, and the recovery current of D1
commutates to the path E1→D1→S2→E2→E1 through S2 inthe moment of turning on S2 as shown in Fig. 9(b). This shortcircuit current causes the large turn-on loss, so the efficiency
is detrimentally deteriorated. In the proposed circuit, however,C1 is rapidly charged and D1 is turned off at the same time byusing the auxiliary circuit. The recovery current of D1 flows
to the path C1→D1→C1, so the turn-on loss of S2 is notcaused since the DC bus is not short-circuited. However, theenergy of Lc1 is not transferred perfectly to C1 because ilc1
still flows as the constant value which is determined by id1
after Sc1 is turned off. The energy which can be transferred tothe output parasitic capacitor Pt is determined by the energy
difference between ilc1 and id1. Pt is simply expressed by
1(10)
Pt = Lc1(ilc12 − id12 ) .
2

60
40

Conventional circuit
Proposed circuit

20
0

0

30

60

90

120

150

Load power (W)Fig. 17. Load power-efficiency characteristic.

ideal state, but C1 and C2 have voltage dependence and there
are power consuming factors such as a forward voltage dropof the auxiliary diode. Hence, Ith1 and Ith2 must be slightly
modified from 2.2 A to 3.0 A and 5.3 A to 4.0 A, respectively.
Figures 13 and 14 show the output waveforms of theconventional and the proposed circuits for 14-W output power.
An 8-Ω and 1-mH RL load, a 100-kHz switching frequency, a
1-kHz operating frequency, and a 0.2 modulation index (MI)are applied to the circuits. It is confirmed in Figs. 13(a) and14(a) that the DC bus is short-circuited by the charging currentof the output parasitic capacitors and the recovery current of
the body diodes. In addition, the gate voltage vgs1 oscillates
just after S1 is turned off due to the high di/dt of the shortcircuit current flowing through the parasitic inductance along
the current path. However, it is clear that this short circuitcurrent do not flow across the DC bus by using the auxiliary
circuit as demonstrated in Figs. 13(b) and 14(b). Furthermore
the oscillation of vgs1 is effectively suppressed by the low dv/dt
determined by the resonance frequency of Lc1 and the output
parasitic capacitors. The reduction of the short circuit current
and the noise mean that the output parasitic capacitor ischarged and the body diode turns off before the othercounterpart main device turns on. The auxiliary circuit isalways operated because the iL is lower than the thresholdcurrent owing to the low MI. Figure 15 shows the output
waveforms of the conventional and the proposed circuits in theheavy-load range. It is confirmed from this figure, the modeswitching of the auxiliary circuit is properly performed when
the load current is over the threshold current. In addition, it isobserved that the short circuit current is effectively reduced aswell as the low-load case. Figure 16 shows a load power toutilization ratio characteristic. In the heavy-load range, theutilization ratio of the auxiliary circuit decreases because theamplitude of iL is high. Figure 17 shows a load to total
efficiency characteristic including the power consumption of
the auxiliary circuit. The efficiency of the proposed circuit ishigher than that of the conventional circuit because the turn-on
loss of the main devices is improved; thus, the efficiency ofthe proposed circuit is improved by 14.8 pt, compared with theconventional circuit at 14-W output power.
In general, the dead-time period should be less than 5 % of
the switching operation period. In the case of the highfrequency drive such as 100-kHz, the output parasitic
capacitors cannot be fully charged and discharged during thedead time period, so the proposed method is very effective to
make the high-speed and high-frequency operation possible.
Since the conduction loss and the switching loss are dominantfactors among the power conversion losses, and the
conduction loss is at almost the same level between theconventional and the proposed circuits, the efficiency
improvement of the proposed method mainly owes reductionof the switching loss. The proposed technique is considered tobe effective and efficient for the MHz-class power converters.
The size of the power converters becomes compact in the caseof the high-frequency operation because the filter inductor andthe filter capacitor can be miniaturized.
IV. CONCLUSION
This paper has described a high-efficiency and high-speed
switching operation technique of the MOSFETs using theswitching assist circuit fed by the gate drive power supply.
The designed auxiliary circuit has been applied to a chopperand a half-bridge inverter, and their operation characteristics
have been confirmed through several experimental tests.
In the case of the chopper, it was confirmed that the turnoff dv/dt of the proposed circuit was 9 times higher than thatof the conventional circuit.
On the other hand, in the case of the half-bridge inverter,
the total efficiency was improved from 33.5 % to 48.3 % at
14-W output owing to the reduction of the switching loss of
the MOSFET.
The proposed method is very effective to drive the
MOSFET with a large parasitic capacitance. Particularly, if

1204

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multiple MOSFETs are connected in parallel to enhance thecurrent rating, the method is more suitable to such higher
power applications.
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CONFERENCE -ECCE ASIA- IPEC-Hiroshima, 20D1-4 (2014)