Engineer-to-Engineer Notea

EE-234

Technical notes on using Analog Devices DSPs, processors and development tools
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Interfacing T1/E1 Transceivers/Framers to Blackfin® Processors via theSerial Port
Contributed by K. Unterkofler and T. Lukasiak

Introduction
This EE-Note describes how to interface
Blackfin® processors to standard T1 or E1
encoded signals. The proposed template assumes
that a Blackfin processor is functionally locatedbetween two T1/E1 streams to perform therequired processing, such as line echo canceling.
However, the Blackfin processor can be adapted
easily to other functional architectures. As shownin this EE-Note, most standard backplane PCM
data streams interface directly to the processor’s
serial port(s), without any external hardware.
This document provides schematics, layout
suggestions, and a software framework forreceiving, processing, and transmitting PCM
streams between two T1/E1 transceivers/
framers.
The chosen framing device is the PMC-Sierra
PM4351 COMET. The PCM streams areconnected to one of the processor’s synchronous
serial ports (SPORTs), which can handle two
input streams and two output streams. The
COMET is configured via the processor’s
asynchronous memory interface in the external
bus interface unit (EBIU).
The schematics are intended to be for a daughterboard that plugs into an EZ-KIT Lite™
evaluation system available from Analog
Devices, Inc.
The application was implemented on and is
described herein for the ADSP-BF533 processor

Rev 1 – May 11, 2004

[1], [2]. Though it is possible to apply this sameboard to the ADSP-BF561 EZ-KIT Liteevaluation system with only minor changes,
considering that this device incorporates twocores and two SPORTs, it makes more sense toextend the board to four COMET devices and toallow it to handle twice the number of processedchannels [3].

!

The board was also designed to interface
also to a ADSP-BF535 processor,
although it requires more substantial
hardware changes, such as using two
SPORTs instead of the one needed for the
ADSP-BF533. The schematics refer to thethe required changes. This entails
significant software which are beyond thescope of this EE-Note.

The software framework is written in C entirely.
All references to execution times are taken fromthis code example.

System Architecture
Figure 1 shows a block diagram of a typicalapplication. The board is designed to plug into an
existing T1/E1 connection via two RJ48C
connectors. This leads to two streams (stream 1
and stream 2), both carrying incoming andoutgoing data (RIN, ROUT, SIN, and SOUT). In themost basic mode of operation (pass-through),
RIN and SIN are copied unaltered to ROUT and
SOUT, respectively, such that the whole resembles
the original single T1/E1 connection.

Copyright 2004, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application ofcustomers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are propertyof their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however
no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.

aT1/E1 Interface Board

T1/E1 Stream 1

T1/E1 Stream 2
Rout

Rin
Framing andprocessing

Sout

Sin
RS232 to Host

Figure 1. System overview

The software also provides a parser-based UART
interface to a generic host processor for setting
operating modes and parameters and controlling
the Blackfin processor and the COMET framing
device.
Figure 2 provides a detailed view of the interface.
The signals from the two RJ48C connectors areconditioned and isolated from the digital domain
by transformers. Also provided are over-voltage
protection diodes. The COMET framers(PM4351) are configured to generate serial inputs
in a format compliant with the SPORT’s multichannel mode from the RIN and SIN streams, andto generate the ROUT and SOUT streams from the
SPORT’s serial output data. The two COMET
framer chips are connected to the Blackfin
processor via the External Bus Interface Unit
(EBIU) and are configured via this interface.

T1/E1 Data Formats
T1/E1 connections are a well-known and widelyadopted standard. For the purpose of this EENote, it is sufficient to say that T1 lines encode 24channels of 8-bit data plus one framing bit(totaling 193 bits) into a 1.544 MHz carrier wave.
Similarly, E1 lines encode 32 channels of 8-bit
data (totaling 256 bits) into a 2.048 MHz carrier.
In both cases, this corresponds to a new sample ofeach channel every 125 µs. The 8-bit data is
obtained from linear, 14- or 13-bit data samples
by compression according to a-law or µ-law,respectively.
In addition to the data (sometimes referred to as
the payload), T1/E1 streams contain signaling bits
according to a variety of communication
standards. This EE-Note does not go into thedetails of these standards, since the COMET
devices’ functionality is to extract the payload
from the incoming T1/E1 streams and to encode avalid T1/E1 outgoing stream from the payload
from the DSP, according to the selected standard.
Thus, if the COMET devices are set up correctly,
the processor will “see” the payload only andnever have to handle the signaling bits. If errors
occur, the COMET can be set up to generate aninterrupt for the DSP as well. For more details,
refer to [4], [5] and [7].

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a

Sout

CLK
2.048MHz

RS232

Protection

Line Interface
Protection

&

&
UART
DSP

Isolation

Isolation

EZ-KIT Lite
via
Expansion
Connectors
COMET1

RJ48C

Line Interface
RJ48C

Rin

Rout

Sin

COMET2EBIU

SPORT

PM4351

PM4351
PCM data streams

Figure 2. T1/E1 Interface Card Block Diagram

The incoming streams (RIN and SIN) are thus
converted (mapped) into a PCM data stream,sometimes referred to as “backplane”. Again,
there are a variety of standards, but they consist ofa signal containing the data bits for each channel
and, for T1 lines, the framing bit, synchronous to a
1.544 (T1) or 2.048 MHz (E1) clock. This blockof data is called a frame. The beginning of a frame
is signaled by a separate signal called a “framesync”. For T1, the COMET also provides theoption of mapping the 24 channels into a
2.048 MHz backplane, such that channels 24-31
contain dummy data, which the processor can thenignore. This offers the advantage that both T1 andE1 settings use the same clock, thus switching
between the two formats requires only a simple
software change, rather than switching between
two clock sources.
For the outgoing streams (ROUT and SOUT), similar
considerations apply. The backplane signals
consist of 32 channels of 8-bit data for an E1 line.
Similarly, for a T1 line, the COMET simply
ignores channels 24-31.

Figure 3 graphically shows the backplane formats.
Since each SPORT has two transmit lines and two
receive lines, the ADSP-BF561 can be used tohandle all four PCM streams. The clock and frame
sync are shared so that the data flows aresynchronized at all times. With its ability to
independently select driving and sampling edges
for the receiver and the transmitter, clock andframe sync, and delay between frame sync andfirst bit of the data streams, the ADSP-BF561 canbe adapted to virtually all common backplane
formats. Figure 3 shows the format used in thisapplication.
For the PCM data to be available for processing, it
must be transferred into the processor’s memory.
Similarly, outgoing data has to be transferred frommemory to the SPORT. This is done via direct
memory access (DMA) channels. The so called
2D-DMA capabilities allow for rearranging
samples in flexible ways, as is shown in
Figure 4. Incoming samples are stored in themanner depicted in the figure as they arrive, that is
RIN[0],
SIN[0],
RIN[1],
SIN[1],…

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a
RIN[Number_of_channels-1], SIN[Number_of_channels-1]
for frame 0, and similarly for the other frames.
Note that the two receive lines (RIN and SIN) are
re-organized as they come in to the SPORT
without any intervention of the core. The attachedcode
exampleacquiresablockofNumber_of_Samples frames, set by default to 40,
such
that
an
interrupt
occursevery(Number_of_Samples * 125) µs (5 ms for theprovided example). The interrupt signals that theacquired frames are available for processing, but
the DMA continues to acquire new frames in adifferent memory area. When this second block is
acquired, another interrupt is generated and the
DMA places new frames into the first memoryarea, overwriting the ones already there. Thismechanism is sometimes referred to as double
buffering and allows the Blackfin processor toprocess half the incoming data (the first

Number_of_Samples frames) while the other half isacquired. This is done in hardware, without any
code intervention, by using the descriptor chain
mechanism provided by the DMA engines.
Similar considerations apply for the transmitted
streams, ROUT and SOUT. For details on DMA
functionality, refer to [2].
The last step before processing the incoming datais to convert the PCM data into linear values. As
previously mentioned, the incoming data iscompressed and has to be expanded using a-law orµ-law. Once processed, the resulting output data
must be compressed to fit into the outgoing PCM
data streams.
The SPORT does the expanding and compressing(companding) in hardware, which eliminates
processing time needed by the processor.

Figure 3. Backplane signal formats

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aOrdering represents
increasing 16-bit
word addresses

Frame
[0]

Frame
[1]

Rin[0]

Sin[0]

Rin[0]

Sin[0]

Rin[1]

Sin[1]

Rin[1]

Sin[1]

...

...

...

...

Rin[Number_of_channels-1]

Sin[Number_of_channels-1]

Rin[Number_of_channels-1]

Sin[Number_of_channels-1]

Rin[0]

Sin[0]

Rin[0]

Sin[0]

Rin[1]

Sin[1]

Rin[1]

Sin[1]

...

...

...

...

Rin[Number_of_channels-1]

Sin[Number_of_channels-1]

Rin[Number_of_channels-1]

Sin[Number_of_channels-1]

...

...

...

...

...

...

...

...

...

...

...

...

Rin[0]

Sin[0]

Rin[0]

Sin[0]

Sin[1]

Rin[1]

Sin[1]

...

...

...

...

Rin[Number_of_channels-1]

Sin[Number_of_channels-1]

Rin[Number_of_channels-1]

Sin[Number_of_channels-1]

Frame
Rin[1][Number_of_Samples-1]

Repeat frombeginning

1st Half

2nd Half

Figure 4. PCM samples allocation in L1 Data Memory – see text on how 2D-DMA fills the buffers

Note that the hardware companding does notguarantee bit accuracy; thus, if an incoming
sample is expanded and then compressed again,
the result may differ from the original by one bit.
This may not be acceptable, depending on theapplication. By default, the provided examples use
software companding, which provides bit
accuracy, but requires about 75 µs or 65 µs ofprocessing time, each way, for a-law or µ-law,respectively, measured for 40 frames at a coreclock speed of 600 MHz. To put this inperspective, this is about 3.0% (or 2.6%) of theoverall available computation time of 5 ms.
The
described
double-buffer
mechanism
introduces an intrinsic delay. For instance,
considering a single data word that enters RIN, it
will be copied to ROUT in the next block offrames, and then transmitted with the block after
that. Thus, the delay from RIN to ROUT is (2 *Number_of_Samples * 125) µs (10 ms for theprovided example, but 250 µs in the best case).

Similarly, samples going into SIN will reappear(unaltered or in processed form) on SOUT with thesame delay. The minimum amount of delay isclearly dependent on how many frames the
adopted processing algorithm requires at each
iteration to produce the desired results.

Reference Board Design
The design closely follows the reference design
described in great detail in [6]. In particular, theline interface with its signal conditioning, overvoltage protection, and isolation has not been
modified. The analog side of the COMET devices
is connected to the line interface in accordancewith the reference design as well. The 2.048 MHz
clock is derived from an external oscillator device,
which also feeds the processor’s SPORT clock.
The frame sync is generated from the Blackfin
processor. Since both COMET devices have thesame external clocks and frame syncs, they areInterfacing T1/E1 Transceivers/Framers to Blackfin® Processors via the Serial Port (EE-234)

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aforced to synchronize all four PCM streams. They
come from, and go to, the SPORT’s primary andsecondary transmitter, and primary and secondary
receiver, respectively.

1. Check whether a message has been received
from the UART host, and take the appropriate
action.

The COMET devices are configured via a 9-bit
address bus and an 8-bit data bus. These buses are
mapped onto the EBIU’s external buses. The
devices are selected by the /AMS3 and /AMS1
memory bank select signals.

2. Check whether a new block of received data isready for processing and a new block ofoutgoing data is “empty” to hold new results(via two semaphores set by the DMA interrupt
service routines). If it is not, repeat the cycle
above, otherwise go to step 3.

!

3. Process the data according to the content of
globalandper-channel
configuration
variables. Three modes are available:!

The address decoding scheme adopted inthis design is very simple. It can be
improved by using one memory bankselect signal only, and decoding more
address lines. This requires one or two
logic gates.
Be careful when laying out the EBIU
connection to the COMET devices.
Although the interface is that of a slow
asynchronous memory device, the
EBIU’s buses are shared with SDRAM
devices, which can operate at up to
133 MHz. If SDRAM accesses are
required (for example, when complex
algorithms must be executed), layout ofthese buses becomes critical.

The reference design, which is configured as adaughter-board to the EZ-KIT Lite board, buffers
the EBIU buses and uses a flag pin (PF4) tooptionally disable the buffers’ outputs whenaccess to the COMET devices is not needed.

Software Framework
Figure 5 shows a high-level flowchart of theprovided framework. Because the code is modular
and well commented, this EE-Note provides onlya brief outline. More importantly, this section
gives an overview on the possible operating
modes and options that are implemented.
After the initialization of the hardware (Blackfin
processor’s PLL, SDRAM, asynchronous memory
controllers, SPORT, DMA and exception handler;
COMET devices; and the UART interface), themain loop performs three basic tasks:a. Global pass-through: for initial debugging,
all data is passed through unaltered, and, incase of software companding, not evenexpanded and re-compressed.
b. Global Enable, Per-channel Enable forcurrent channel is OFF: data for thatparticular channel is passed throughunaltered; however, unlike the previous
case, the incoming data is expanded,copied to the output buffer, and then recompressed. Since it works on a perchannel basis, this mode is intended to be
used for individual pure-data channels, as
opposed to voice channels.
c. Global Enable, Per-channel Enable forcurrent channel is ON: data for thatparticular channel (RIN and SIN) is fed as
input to the desired algorithm (such as aline echo canceller) and the algorithm
places its results into SOUT. In addition,
each channel can also be scaled
individually before entering the algorithm(separate scaling factors for RIN and SIN)
In all cases, ROUT is a copy of RIN. You canswitch between these three modes at run-timeby setting the corresponding variables fromthe UART host. The scaling factors and thecompanding law can be changed at runtime
via this interface as well.
Although the above modes and settings are
dynamic, many settings must be determined at

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acompile time. All of them are controlled by(un)commenting or assigning values to #defineclauses in one file system.h. The most importantones are:!

CLKIN, CORECLK, SYSCLK, and SPORT0CLK:
set system frequencies (in Hz)!

Number_of_Samples: number of frames acquired!

Settings for backplane clock source, frame
sync source, and driving and sampling edge
relationships for COMET and SPORT. Only
needed if adapting to a different backplanetiming standard than what is shown in Figure
3.

!

Assignments of General-Purpose Flags forvarious functions. Flag 0 and Flag 2 are used
to reset the COMET devices and generateinterrupt requests, respectively.

!

DEVICE1, DEVICE2: Base addresses in external

for each block!

Number_of_Channels: Set to 32 for a 2.048 MHz

backplane; set to 24 for a true T1 (1.544 MHz)
backplane!

asynchronous memory of the two COMET
devices. By default, they are located at thestart of bank 3 and bank 1, respectively

SOFTWARE_COMPANDING: if defined, enabledcompanding in software, otherwise the
SPORT’s hardware companding feature isenabled!

COMPANDING_LAW!

T1_map: defines settings for T1 (mapping 24(available
only
if
hardware companding is selected): sets the
SPORT’s companding law!

STANDALONE: if this label is commented, theapplication writes diagnostic and status
information to the VisualDSP++® Output
window.

!

DUMP_VARIABLES: sends a message withaddresses of important mode variables over
the UART terminal, used to control operating
modes at runtime.

T1 channels onto a 2.048 MHz backplane)!

E1, T1: define settings for an E1 backplane @2.048 MHz or a T1 line @ 1.544 MHz,
respectively!

E1 and T1 COMET configuration
settings are not implemented at thistime. If these configurations are
required, modify the
initializeCOMET_T1_Short_Haul()!

DEBUG_COMET: verifies every write to the
COMET registers and displays a warning if
the read value does not match the originallyintended value. Used for debugging.

!

DEBUG_ALGORITHM: uses flag pins to show

execution time of the algorithm, etc. Used fordebugging, see “Flag Settings” in system.horinitializeCOMET_E1_75()

functions in COMET_init.c according to
the procedures in [4] and [7].

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aMain()

ProcessData()

Set Exception Handler
Set System Frequencies
SDRAM controller
ASYNC memory controller
Flag IO
Reset COMET devices
Initialize variables

Calculate which half of
databuffers can beprocessed

Detect UART terminaland set up connection

Press (or send)@ on Terminal
for AutoBaud
detection

Copy Rin to Rout
(Number_of_Samples *Number_of_channels)
words

Initialize COMET devices
PASS
through?
Initialize SPORT and DMA
Initialize Interrupts

No
Copy SIN to SOUT
(Number_of_Samples *Number_of_channels)
words

Expand Rin and Sin
with a-law or u-law

Start Transfers

Loop: For EACH channel(Number_of_Channel times) :Process Loop
(Infinite)

Voice
Channel?

Message from
Host?

Yes

Yes

Input Scaling Rin and Sin
Process themessage

Semaphore:
new Block ofSamples?

Semaphore is set by
DMA interrupt every
Number_of_samples * 125usec

Sout() =Algorithm(Rin,Sin)

Copy expanded
Sin to Sout
(Number_of_Samples *Number_of_channels)
words

Output Scaling Sout

Yes
Clear Semaphore

ProcessData()

Compress Sout
with a-law or u-law

End Channel Loop

returnEnd Process Loop

Figure 5. Flow Diagram of Main() routine and Processing of PCM samples

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aMemory Allocation – Data Cache
The software framework has been structured
knowing that most algorithms will work withrelatively small amounts of code but operate onlarge amounts of data. Therefore, the code isassumed to be small enough to fit into L1
instruction memory – thus, executing at theprocessor’s core clock frequency. The software
framework enables data caching for eventual large
data buffers in external SDRAM. This is simply
done by the initial definition of the int __cplb_ctrl
control variable in main.c. The data cacheorganization is done in the cplbtab533.s file andexcludes external asynchronous memory frombeing cached (such that there are no cachingeffects on the COMETs’ configuration and status
registers).
The data buffers for the incoming and outgoing
PCM data streams are placed into (non-cached)
L1 memory since they are modified by DMA
transfers, which are independent of the cachesystem.
In conclusion, the framework places instructions
and all necessary data into non-cacheable L1
memory and sets up the upper half of L1 Data
Bank A as cache buffer for data placed in
SDRAM. This approach has been tested on a line

Command Syntax

echo canceller algorithm, where caching reduced
the execution time for each channel from roughly
1 ms to 100 µsec.

Using the UART Host Port
The UART port is used to interface with a hostprocessor using easy-to-read string commands.
This allows the host to be an embedded
microcontroller or a PC with a human operator.
An interrupt-driven system is used to receive datafrom the UART. Each received character is stored
in a temporary array and echoed back to the
UART as an acknowledge signal. The host must
prevent buffer overruns based on thisacknowledgment. As soon as the CR character(carriage return) is received, the temporary chararray is placed on a queue of strings to be parsed.
Table 1 lists a few of the general commands
implemented in the prototype system. The
READ_MEM and WRITE_MEM commands modify
the processor’s memory in general, and the control
and status variables in particular.
To create a system where new commands caneasily be added, two tools (Lex and Yacc) wereused to make sense of the incoming string queue.

PurposeCOMET_READ_REG <base addr> <reg addr>

Read a register from the COMET framer

COMET_READ_REG <base addr> ALL

Read all registers from the COMET framer

COMET_WRITE_REG <base addr> <reg addr> <val>Write a register to the COMET framer

READ_MEM_8 <addr>

Read an 8-bit value from a location in Blackfin memory

READ_MEM_16 <addr>

Read a 16-bit value from a location in Blackfin memory

READ_MEM_32 <addr>

Read a 32-bit value from a location in Blackfin memory

WRITE_MEM_8 <addr> <val>Write an 8-bit value to a location in Blackfin memory

WRITE_MEM_16 <addr> <val>Write a 16-bit value to a location in Blackfin memory

WRITE_MEM_32 <addr> <val>Write a 32-bit value to a location in Blackfin memory

Table 1. COMET and DSP memory commands

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aBoth tools take a configuration file as input andproduce C code. Lex produces a scanner thattokenizes incoming strings, and Yacc produces a
program that parses lists of tokens to identify
meaningful patterns (i.e., valid commands). The
Lex/Yacc suite allows for automatic filtering ofincoming strings that do not have commands
associated with them. For general information on
Lex and Yacc, refer to [8].

Yacc Configuration File[yacc_gmr.txt]...
%token INTEGER%token COMET_READ_REG...
COMET_READ_REG INTEGER INTEGER{

Lex and Yacc each have a distinct configuration

unsigned char temp;

file. Below are excerpts of each file that show how
to configure the command to read a memorymapped register in one of the COMET framer
chips. The syntax of this command is:size = sprintf(str,"COMET_READ_REG 0x%x 0x%x;\n\r", $2, $3);
YY_OUTPUT(str, size);// echo the command to acknowledge
temp = COMET_readReg($2, $3);// pass the parameters to a function that// actually does the COMET access

COMET_READ_REG <base addr> <reg addr>

where<base addr> is the base address of the COMET

size = sprintf(str,"COMET_READ_REG (0x%x, 0x%x) -> 0x%x;\n\r",$2, $3, temp);

chip in the Blackfin

YY_OUTPUT(str, size);// echo the output

and<reg addr> is the address of the MMR in the
COMET memory space
Lex Configuration File[lex_spec.txt]...
COMET_READ_REG {return COMET_READ_REG;// string COMET_READ_REG
returns a distinct token}{integer}{yylval = atoi(yytext);}

The GNU version of Lex and Yacc were used inthis system. Both Flex, the Lex alternative, andBison, the Yacc alternative, are part of the Cygwin
distribution (www.cygwin.com).
The following command line creates the Lex
scanner and Yacc parser.
flex lex_spec.txt [creates lex.yy.c]bison –y –d yacc_gmr.txt [creates y.tab.c and y.tab.h]

The resulting C source and header files areincorporated into the Blackfin VisualDSP++
project.

// yylval is passed to Yacc
return INTEGER;// any integer returns with this token}...

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aFigure 6. Hyperterminal session

Results
Figure 6 shows a screenshot of the implemented
UART interface protocol. Shown are the initial
status message with the addresses of control
variables and two write_mem commands.
Figure 7 shows a graphical visualization of theoutput data in “pass-through” mode. Inputs are
generated externally (1 kHz sine waves) on asubset of the 24 T1 channels. ROUT is looped backexternally to SIN, such that all four streams containthe same data, only delayed in time.
Figure 8 shows an example of how the debugging
flag pins (PF1 and PF3) can be used to show, forinstance, the execution time for the processing of
all channels, or any other useful time in a
relatively straightforward way. The example wastaken from an application where the algorithm
was a line echo canceller (128 ms tail length).
Each of the 32 channels is processed, althoughchannels 24-31 are not used by a T1 connection.

This was solely intended to demonstrate that theprocessing power of the Blackfin processor issufficient to do significant amounts of calculations
on all 32 channels, and leaving about 27% of thetotal time for other tasks, such as the UART
interface.

Conclusions
This EE-Note, along with schematic drawings andsoftware framework provides design ideas for avariety of T1/E1 communication lines.
The main focus is to interface the Blackfin
processors’ serial ports to standard backplane
formats and to show how to process the PCM
data. This is demonstrated on PCM streams from aframer device such as the PM4351.

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aFigure 7. ROUT and SOUT (channel 0) in “pass-through” mode (RIN is a 1kHz sine-wave for channels 0,1 and 2),
SIN is looped back externally from ROUT.

Figure 8. Execution time (signal PF1, trace 1) and individual channel convergence indicator (signal PF3, trace 4)in the case of a line echo canceller algorithm. See RESULTS section for more details

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aReferences[1] ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin Embedded Processor Data Sheet. Rev 0, March 2004.
Analog Devices, Inc.
[2] ADSP-BF533 Blackfin Processor Hardware Reference Manual. Revision 1.0, December 2003.
Analog Devices, Inc.
[3] ADSP-BF561 Blackfin Processor Hardware Reference Manual. Preliminary Revision 0.2, November 2003.
Analog Devices, Inc.
[4] PM4351 COMET Combined E1/T1 Transceiver Datasheet. Issue10, November 2000. PMC-Sierra, Inc.
[5] PM4351 COMET Combined E1/T1/J1 Transceiver/Framer Device Errata. Issue6, April 2002.
PMC-Sierra, Inc.
[6] PM4351 COMET Reference Design. Rev. 2.0, Issue1, November 1998. PMC-Sierra, Inc.
[7] PM4351 COMET Programmer’s Guide. Issue2, September 2000. PMC-Sierra, Inc.
[8] Lex and Yacc for Embedded Programmers. Embedded Systems Programming.
http://www.embedded.com/story/OEG20030220S0036

Document History
Revision

Description

Rev 1 – May 11, 2004
by K. Unterkofler

Initial Release

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