Engineer-to-Engineer Notea

EE-261

Technical notes on using Analog Devices DSPs, processors and development tools
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Understanding Jitter Requirements of PLL-Based Processors
Contributed by Boris Lerner and Aaron Lowenberger

Introduction
With the advance of faster processors that
require faster lines of communication,
understanding and characterizing clock jitter has
become more important.
Jitter occurs in many different parts of digitalapplications. Jitter of data with respect to clockin synchronous protocols is one example; jitter ofthe signal itself in CDR (clock data recovery)
applications is another.
This EE-Note describes jitter issues of the clockfrom which PLL-based processors derive timing.
This document analyzes the given clock's jitterwith respect to an ideal clock, only as far as aprocessor’s tolerance requires. This document isintended for hardware design engineers
responsible for choosing the components tosatisfy a processor’s jitter requirements.
The specific processor being analyzed in this EENote is the ADSP-TS201S TigerSHARC®
processor. Some portions of this EE-Note apply
to jitter in general; other portions apply
specifically to our case in question.
Unfortunately, unlike more traditional data sheet
parameters like setup and hold, analyzing
acceptable system jitter is not as simple as
merely ensuring that specification numbers are
met. There are many ways to measure jitter; on
top of that, there are infinitely many different
kinds of jitter and the system may behave
differently depending on the jitter type. Thus,
before doing any analysis whatsoever, it is

Rev 1 – January 20, 2005

important to supply all of the jitter terms anddefinitions, first intuitively what they mean andthen the correct mathematical definition.

Terminology
We consider an ideal clock that is being jittered(i.e., the clock’s edges experience movementwith respect to ideal locations).
The jitter of a particular waveform can bemeasured/characterized as period, cycle-to-cycle,
or time interval error (TIE).
Period jitter. This measures the maximum
deviation of each single period of the jitteredclock from that of the ideal clock. In Figure 1, if
C 0 = Period of Ideal clock, then(1)

Period Jitter = max {Pk − C 0 }.
k =0 ,1, 2 , 3,...

Cycle-to-cycle jitter. This measures the
maximum deviation of each single period of thejittered clock from the previous period of thesame clock. In Figure 1,(2)

Cycle - to - Cycle Jitter = max {Pk +1 − Pk }.
k =0 ,1, 2 , 3,...

Time interval jitter. This measures the maximum
deviation of the edge (Figure 1 shows thisrelating to the rising edge; it can also relate to thefalling edge) of the jittered clock from thecorresponding edge of the ideal clock. In
Figure 1,(3)

TIE Jitter = max {Tk }k =0 ,1, 2 , 3,..

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aHere we presume that at time t=0 of themeasurement, the edge of the jittered clockaligns with the edge of the ideal clock. Note that
this is not just a simple aberration of the edge ofthe jittered clock from the nearest edge of theideal clock, because the edge of the jittered clock
may have “wandered” away from the edge of theideal clock by more than a full cycle period.

Figure 1. Jitter Definitions

It is time to put clock and jitter under a more
precise mathematical definition. We define theideal clock of period T and constant amplitude A
as the following function of time t:⎧
1⎞⎛
if nT ≤ t < ⎜ n + ⎟T
⎪⎪ A
2⎠
⎝
(4) C A,T (t ) = ⎨1⎪ 0 if ⎛⎜ n + ⎞⎟T ≤ t < (n + 1)T⎪⎩2⎠⎝
Here, T is measured in units of time (usuallyseconds) and A is measured in volts. Amplitudeof the ideal clock is irrelevant to the discussion
about jitter, so in all that follows we presume thatthe clocks have unit amplitude and we consider
them as parameterized by T, (i.e., their period):

(5)

⎧
⎪⎪ 1
CT (t ) = ⎨
⎪ 0
⎪⎩

1⎞
⎛
if nT ≤ t < ⎜ n + ⎟T
2⎠
⎝
1
⎛
⎞
if ⎜ n + ⎟T ≤ t < (n + 1)T2⎝⎠

We also define C J ,T (t ) , the clock of period T

with jitter J(t), as the ideal clock delayed by afunction of time J(t) (delay can be positive or
negative), mathematically:(6)

C J ,T (t ) = CT (t − J (t ))There are several intuitive reasons for defining
jitter this way. The most compelling reason isthat jitter is usually generated in a laboratory by
applying a function generator signal to a delay
input of a pulse generator. This is the way
processor manufacturers test susceptibility tojitter.
For simplicity we define(7) G (t ) := t − J (t ) , so that C J ,T (t ) = CT (G (t )) .

Note that G(t) matters only at points

1⎞⎛
t = rk or f k where G(rk ) = kT andG( f k ) = ⎜ k + ⎟T.
2⎠⎝
These points are precisely where the clockchanges from low to high or high to low (thus“r” for rising and “f” for falling edges). Since
what G does outside of these discrete points iscompletely immaterial, we can presume that G(and, thus J) are infinitely differentiable at all
points.
Since these definitions are mathematical innature and we must maintain real-lifeplausibility, it is safe to assume that G must be aUnderstanding Jitter Requirements of PLL-Based Processors (EE-261)

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auniformly increasing function (that is,
t1 < t 2 ⇒ G (t1 ) < G (t2 ) , since G cannot change
the order of the edges, only their locations.

In fact, its period is Pk =Going back to Figure 1, we see that Tk = J (kT ) .

Period Jitter =Thus, these definitions naturally lend themselvesto specifying jitter as TIE (simply because themaximum amplitude of J(t) is the TIE jitter, as
defined in equation (3)). Unfortunately, clock
driver manufacturers do not typically specify
jitter as TIE. Thus, it becomes important to relatedifferent types of jitter with mathematicalformulas. This is the main reason for thisapplication note.

Cycle - to - Cycle Jitter = 0,

Jitter Examples
Let’s hesitate from this mild mathematicalonslaught and examine different examples ofjitter as consequences of our definitions.

J (t ) = ε ,ε is a small real number. ThenC J ,T (t ) = C T (t − ε ) , whichshift of the original

εT
T
−T =
,
1− ε
1− ε

TIE Jitter = ∞.
Intuitively, function J(t) is slowly increasing (ordecreasing, depending on the sign of epsilon),
and the edges shift uniformly. Note that infinite
TIE jitter implies that this jitter cannot be
generated by laboratory setup described above; itwould require the function generator to output asignal of infinite amplitude. For the same reason,
this type of jitter does not occur in real-lifesystems, so we will restrict our attention to jitterof finite amplitude.
Example 3

J (t ) = A sin( 2π f 0 t )Example 1

whereT, the same for all k.
1− εis a phase

ideal clock.

Period Jitter = 0
Cycle-to-Cycle Jitter = 0
TIE Jitter = ε
Example 2This type of jitter is appropriately called thesinusoidal jitter of frequency f 0 . In this case, TIE
jitter (which, as noted before, is the maximum
amplitude of J) is A. Deriving period and cycleto-cycle jitter is not as trivial as in Example 1,
and derivation of period jitter will be done in afollowing section.
Example 4

J (t ) = C A,T0 (t ) , another ideal clock of period T0
and amplitude A. It is easy to see that J(t) delays
the original clock by A or does not delay it at all.
Thus, provided that T0 is reasonably smaller thanT,

J (t ) = εt ,Period Jitter = A

where ε is a small real number. Then

Cycle-to-Cycle Jitter = A

C J ,T (t ) = CT ((1 − ε )t ) , which is another ideal clock of

TIE Jitter = A

lower (if ε > 0) or higher (if ε < 0) frequency.

Understanding Jitter Requirements of PLL-Based Processors (EE-261)

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aExample 5

J(t) = White Gaussian noise. The implications of
this jitter type on period, cycle-to-cycle, and TIE
jitter are postponed to a latter section of thisapplications note, when we discuss general casejitter.

Statement of the Problem
All of the above is not intended to hopelessly
confuse this topic. It is, however, intended toshow the reader how confusing the subject canbe - there are infinitely many types of jitter andseveral ways of measuring it. Let us state theproblem for a designer of a clock to a processor
specifically.
1. Processor manufacturers care about how
short a clock pulse may become due to jitter
before it violates the processor’s guardbanded frequency spec. (Note that theprocessor’s PLL usually has a jitter
frequency transfer function which needs to betaken into account. It is the clock that comesout of the PLL that must abide by thefrequency spec). Looking at the definitions of
the jitter measurements, it is clear that theprocessor is concerned about the period jitter.
2. When characterizing the jitter frequency
transfer function of the processor’s PLL,
processor manufacturers often use the lab
setup described above (i.e., they reallymeasure TIE jitter).
3. Clock driver and oscillator manufacturers do
not artificially generate, but rather measure
jitter and usually specify it as cycle-to-cycle.
The hardware design engineer, who is faced withthree seemingly incompatible definitions, throws
in a towel, goes back to school, gets an MBA andjoins the marketing department instead. Or (andthis happens at least as often), the engineer

simply designs the board without checking thejitter specs and hopes that it works.

Jitter Frequency Domain Transfer
Function Through a PLL
Without a detailed discussion of PLLs (which, in
itself, has little to do with the subject at hand),we can just state that a PLL, being a phaselocked loop, is linear in phase and, thus, is linear
in jitter. Although this statement is not as simple
as it looks, it is correct and we’ll leave it at that.
This is good news, because linear systems can beanalyzed in terms of their frequency domaintransfer function (i.e., frequency response). Notethat this transfer function is linear in jitter only; a
PLL itself is certainly not linear as output withrespect to input. Thus, the linear system
discussion that follows looks at the transfer ofjitter through the PLL only.
Generally, a PLL will have a fairly flat unity gain
response up to a certain frequency (because a
low-frequency jitter appears as a slowly varying
phase that the PLL has enough time to adjustfor). Also, as is the case with all real-lifesystems, frequency response rolls off at the highend. The locations of these cut-off points and the
response between these cut-off points varies
among PLLs. The jitter transfer function for
ADSP-TS201S processors with a base clock of
125 MHz and PLL multiplier set to 4 is shown in
Figure 2.
Another important factor to this analysis is:given a clock at the processor maximum allowed
frequency, by how much can a clock period
shrink before failure. In case of ADSP-TS201S
TigerSHARC processors, this value is 40 ps (i.e.,
2% of the 2 ns period of a 500 MHz clock).
Armed with this data, it is time to analyze jitter
tolerance. We begin with sinusoidal jitter.

Understanding Jitter Requirements of PLL-Based Processors (EE-261)

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ADSP-TS201S PLL Jitter Transfer Function
CLOCK MULTIPLIER = 4
SCLK = 125 MHz
10transfer function (dB)

5

0

-5

-10

-15

-20
0.1

1

10

100

jitter frequency (MHz)Figure 2. Jitter Transfer Function

Sinusoidal Jitter
The sinusoidal jitter of amplitude A (measured intime units, say seconds) and frequency
f (in Hz) is given by J (t ) = A sin (2πft ) .
From
the previous discussion, we know that A is the
TIE jitter.
This jitter inputs into the PLL of ADSP-TS201S
and outputs J f (t ) = A( f )sin(2πft ) , where A( f )is taken from the graph in Figure 2. According toformula (1), period jitter (which, stated above,
must be less than 40 ps), is given by:
max {Pk − C0 } . Since G of equation (7) is

k = 0 ,1, 2 , 3,...

monotonically increasing, it is also invertible.
The edges of CT (t ) are at points kT , so theedges ofC J ,T (t ) = CT (G (t ))are at points

G −1 (kT ). Thus,

Pk = G −1 ((k + 1)T ) − G −1 (kT ) .
We now invoke the Intermediate Value Theorem
from beginner calculus, which states that, given a
continuously differentiable function, thedifference of this function’s values at the end
points of an interval equals the length of thatinterval times the derivative of the function atsome point inside the interval. We thus obtain:
Pk =

( )

( )

−1
d G −1(t0 )((k + 1)T − kT ) = d G (t0 )T
dt
dt

for some t0 ∈ [kT , (k + 1)T ].

Understanding Jitter Requirements of PLL-Based Processors (EE-261)

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aAgain, using beginner calculus, if

T − Pk ≤ 79 ⋅10 ⋅ A ⋅ 2 ⋅10 ≤ 158 ⋅10 −3 A ,y = G −1 (t ) , then t = G ( y ) andwhich must be ≤ 40ps = 40 ⋅10 −12 sec .

( )

dy
1
, i.e.
=
dt dt
dyd G −1(t ) = dG1 = dG 1.
dt(y)
G −1 (t )
dt
dt

(

)

Substituting this into the above (with t = t0 )gives:
Pk =

T
.
dG −1
G (t0 )
dt()

Since G (t ) = t − A( f )sin (2πft ) ,
Pk =

(8)

T
T
≥
1 − A( f )2πf cos 2πfG −1 (t 0 ) 1 + A( f )2πf()

We now use Figure 2 to find the worst (i.e.,
maximal) value of A( f ) f . Note that the curve in
Figure 2 rolls off at the high end at the rate of
12 dB/oct. This means that every time we double
the frequency, amplitude is divided by 4. Thus,A( f ) f is maximized at the beginning of the rolloff curve (i.e., at approximately 7 MHz) where
the PLL actually boosts the jitter amplitude by
about 5 dB. Thus,
5
6

max{A( f ) f } ≤ 2 A ⋅ 7 ⋅106 = 12.46 ⋅106 ⋅ A.
f

Substituting this back into equation (8) gives:
Pk ≥

T
T
≥
, so
6
1 + 2π ⋅ 12 . 46 ⋅ 10 ⋅ A 1 + 79 ⋅ 10 6 ⋅ A

T − Pk ≤ T −T
1 + 79 ⋅ 10 6 ⋅ A

79 ⋅ 10 6 ⋅ A ⋅ T=≤ 79 ⋅ 10 6 ⋅ A ⋅ T
1 + 79 ⋅ 10 6 ⋅ A

The ideal clock input in this case is 500 MHz(125 MHz input multiplied by PLL by a factorof 4; see Figure 2), so T = 2ns = 2 ⋅10 −9 sec , so

6

−9Solving this inequality for A yields
A ≤ 0.253 ⋅10−9 sec = 253 ps .
Thus, in the case of sinusoidal jitter, to satisfy
the 40 ps of period jitter required by ADSPTS201S processors, we must ensure that the TIEof that jitter is no more than 253 ps.
Unfortunately, one usually cannot assume thatthe jitter will be sinusoidal in nature, in whichcase the above analysis does not apply
completely. But it does show how estimating theabsolute value of the derivative of the jitter
relates TIE to period jitter. Note that the above
analysis can be performed more simply, without
referring to the derivative. The reason that we
did it in the more complicated way is because
most of this argument will apply when weanalyze general case jitter. We now turn ourattention to this more difficult case.

General Case JitterAs shown in the analysis above, it is very
important to try to estimate the absolute value ofthe derivative of the jitter function on the outputof the PLL.
Given jitter J(t) input to the PLL, its output is
J h (t ) = J ∗ h(t ) , where the magnitude Laplacetransform of h evaluated on the unit circle
H (2πif ) = L(h )(2πif )is given by the graph of Figure 2 (as a function of
f, of course).
It follows thatJ h ' (t ) = J ∗ h' (t )i.e., Jh' is the output of a filter whose impulse
response is h’ and input J. Since,
L(h')(s ) = sL(h )(s ) ,Understanding Jitter Requirements of PLL-Based Processors (EE-261)

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athe magnitude response of the filter h’, using thenotation of the previous section is given by

Solving this inequality for J ∞ gives(9) L(h')(2πif ) = 2πf H (2πif ) = 2πfA( f )J ∞ ≤ 253 ⋅10 −12 = 253ps

which is maximum at f = 7 MHz, because thehigh-frequency roll-off is at 12 dB/octave (this isexactly as in the previous section).

Thus, we end up deriving the same conclusion as
was the case with sinusoidal jitter (i.e., less than
253 ps of TIE jitter ensures that the pulse jitter
requirement of the processor is met).

Using
standard
mathematicalnotationg (t ) ∞ to denote the smallest upper bound ofg (t ) (i.e. pointwise amplitude of g ), we now have()

J h ' ∞ ≤ 2π ⋅ 7 ⋅106 ⋅ A 7 ⋅106 ⋅ J ∞56≤ 2π ⋅ 7 ⋅10 ⋅ 2 ⋅ J ∞ ≤ 79 ⋅106 ⋅ J ∞6Now, just like in the previous section,
Pk = G −1 ((k + 1)T ) − G −1 (kT ) =

( )

( )

d G −1d G −1(t0 )((k + 1)T − kT ) =(t0 )T =
dt
dt
T

(

)

dG −1
G (t0 )
dt

for some t0 ∈ [kT , (k + 1)T ].

Substituting G (t ) = t − J h (t ) gives

Pk =

T
.
1 − J h ' G −1 (t0 )()

Since T = 2 ns,
T − Pk ≤ T −

=

T
T
≤T −
1+ Jh ' ∞1 + 79 ⋅106 ⋅ J ∞2 ⋅10 −9 ⋅ 79 ⋅106 ⋅ J ∞1 + 79 ⋅106 ⋅ J ∞≤ 158 ⋅10 −3 ⋅ J ∞To ensure that T − Pk ≤ 40 ps, we must ensurethat
158 ⋅10 −3 ⋅ J ∞ ≤ 40 ⋅10 −12

Guidelines
Jitterfor

Measuring

TIE

Now that we know that the TIE jittermeasurement is ultimately what we want, someguidelines are necessary to convert the definition
of TIE jitter as given by the equation (3) into ameasurement that makes sense in the real worldthat we live in. The problem, of course, is thatthe definition in (3) is theoretical in nature; themaximum is taken over an infinite number ofindexes, in other words, over an infinitely long
period of time. This would be rather difficult toreproduce in laboratory conditions. A greater
length of time is needed to analyze a lower
frequency content of jitter and, as shown by theequation (9), our TIE jitter tolerance is inversely
proportional to the jitter’s frequency. So, let us
analyze the example at hand. Our clock
frequency is 125 MHz (i.e., each cycle is 8 nslong). It is highly unlikely that this clock has
more than 100 ns of TIE jitter (it would have tojitter by more than 12 periods of the clock!), if it
does, there is something fundamentally wrong
with the board’s design. We know from theprevious section that a 7 MHz jitter frequency
allows about 250 ps of TIE jitter. By the inverse
proportionality mentioned above, a 17.5 KHz
jitter frequency should allow about 100 ns of TIE
jitter (it is actually even better than that due tothe jitter boost at 7 MHz). Thus, if we presume
that the total TIE jitter is limited by 100 ns, alljitter content below 17.5 KHz can be ignored.
Frequency of 17.5 KHz corresponds to a periodof less than 60 µs (i.e., measuring TIE over a
period of 60 µs should do the trick).

.

Understanding Jitter Requirements of PLL-Based Processors (EE-261)

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aCycle-to-Cycle Jitter
The previous sections relate TIE and pulse jitter.
A few words need to be said in the relevance tocycle-to-cycle jitter.
The problem with cycle-to-cycle jitter is thatgiven cycle-to-cycle jitter, no matter how small,
TIE and pulse jitter can be as large as desired. A
simple sinusoidal jitter of very low frequency
and large amplitude will change very little fromcycle to cycle (since its frequency is low), but theaccumulated total change from ideal period canbe very large. Thus, a board designer could notuse a clock driver whose jitter is specified as
cycle-to-cycle
without
some
additional
information about the nature of that jitter. In
these cases, if such a driver must be used, it may
be necessary to obtain a driver evaluation board
and measure the TIE jitter. Then one must be
careful not to assume that the jitter will measure
the same on another board with a physicallydifferent driver chip. It may be necessary tocontact the driver manufacturer to understandboard issues that contribute to jitter (such as thepower supply noise on the driver), deviation ofjitter numbers across the chips, and then guardband the measured number appropriately toensure that the final result has no more than
250 ps of TIE jitter.
Thus, having reached this point in the applicationnote and having survived bombardment oftheoretical and practical calculations, the reader
still has not been given a way to select a clock
driver for our example processor! Fully realizing
that, simply leaving the issue “as is”, would,
most likely, also leave the unfortunate reader
more than just a little peeved at the authors, we
decided to contact a clock buffer manufacturer tosee if they can help us resolve this dilemma. We
sent the above portion of this EE-Note to theapplications folks at IDT, who were more thanhelpful. They agreed that the cycle-to-cycle jitter
specification cannot be used in processor clock
designs and were happy to characterize theirrecommended parts jitter as TIE. For our
processor example, they recommended their
IDT5T9070 driver. It turns out that the jitter that
this part produces depends almost entirely on thequality of its power supply. The TIE jitter on
their clean evaluation board’s output measured
52 ps. At this point they were actually limited by
the quality of the input clock that measured TIE
jitter of 50 ps. Following this, they modulated thepower supply with a 400 mV peak-to-peak wave
and bypass capacitors removed (to ensure thatthe supply is truly modulated this much). The
TIE jitter depended on the modulation frequency
as shown in Table 1. Keep in mind that thefrequency in Table 1. corresponds to the power
supply modulation frequency. The resulting jitter
frequency may be quite different.

1MHz

2MHz

3MHz

4MHz

5MHz

6MHz

7MHz

8MHz

9MHz

10MHz

314.5ps200.2ps

163.2ps

143.6ps

140ps

127.8ps

136.1ps

148.1ps

122.6ps

125.1ps

Table 1. TIE Jitter of IDT5T9070 with Power Supply Modulated by 400mV Wave.

Note that 315 ps of jitter at 1 MHz will violate
the processor’s minimum spec derived above if
the jitter frequency is around 7 MHz — this isunlikely to be caused by a 1 MHz modulation of
the power supply. Thus, even in the worst case of
the supply modulated by 400 mV and all of thedecoupling removed, the jitter spec is still met,

except possibly, if the supply modulation is at
1 MHz (and even then, it is, most likely, met!).
The designer is encouraged to use the
IDT5T9070 that has already been specified tomeet the requirements, or, if another driver isdesired, to contact the driver manufacturer
directly for their TIE jitter specs.

Understanding Jitter Requirements of PLL-Based Processors (EE-261)

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References[1] ADSP-TS201 TigerSHARC Processor Data Sheet. Rev 0, November 2004. Analog Devices, Inc.

Document History
Revision

Description

Rev 1 – January 20, 2005
by Boris Lerner and
Aaron Lowenberger

Initial Release

Understanding Jitter Requirements of PLL-Based Processors (EE-261)

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