23 Providence Rd
Westford, MA 01886(978) 692-4828
bjrosen@polybus.com

Polybus Systems
Corporation
InfiniBand Cores from Polybus Systems

Polybus offers a family of InfiniBand Cores ranging from Single Data Rate 4X (10Gb/Second) toQuad Data Rate 4X (32Gb/Sec in FPGAs). All Link Layer cores and Target Channel Adapter cores
are available for Altera FPGAs.
Link Layer Cores are fully compliant with the IBTA 1.2.1 standard, providing auto-negotiation, link
layer flow control, CRC generation and checking and link layer format checking. Link Layer Cores
are designed for very low latency operation and wire speed bandwidth.
Target Channel Adapters combine a Link Layer Core with a UC Transport Layer core. TCAs support
UC SEND and UC RDMA and UD SEND services. TCAs provide 32 to 1024 Queue Pairs and one
to eight Virtual Lanes (depending on application requirements and FPGA resources). The high speed
data connections are simple FIFO interfaces that are easily connected to the streaming interfaces
supported by Altera.
Polybus InfiniBand cores are interoperable with all Mellanox and QLogic switches and HCAs.

Applications
Typical FPGA System
ClientLogic

Target Channel Adapter
Streaming TXTransport
LayerLinkLayerPCS
Layer•Target Channel Adapters and Bridges,••PCI-> InfiniBand
Polybus
InfiniBand Cores aredevelopedin partnershipwith1G, 10G Ethernet-> InfiniBand
Tenesix, Inc. 20 Taylor St. Littleton,
HyperTransport
MA 01460. -> InfiniBand
SPI4 -> InfiniBand•

FibreChannel -> InfiniBand•

High speed data acquisition (Video,Radar ...)

•Routers and Switches•SerDesTo QSFP•Streaming RXCPU

Custom Application Support
Polybus Systems and Tenesix Inc, will provide
custom core development, integration support,and system verification support.

Polybus Systems Corporation

23 Providence Rd, Westford Ma, 01886 (978) 692-4828, bjrosen@polybus.com

Target Channel
Adapters

DDR 4X InfiniBand
Link Layer Core

•20GBit/second (DDR),40GBit/second (QDR)•Unreliable Connect SEND

and RDMA Write•Unreliable Datagram SEND

(in QDR TCA only)•QDR TCA supports bothcutthrough and store andforward modes.

QDR 4X/8X Link
Layer Core

•20 Gbit/second•

80 Gbit/second in ASICs•64 bit parallel interfaces•

40 Gbits/second in FPGA

•1X, 4X operation•

128 bit parallel interfaces•Link initialization and•

1X, 4X, 8X operation•

Link initialization andtraining•

Link layer flow control•

CRC generation andchecking•

Protocol error and packet
length checking•

Programmable FlowControl Period•

Dynamic Flow ControlMechanism•

Available for 1,4 & 8
Virtual lanes.

•Very low latency•

Very low latency• IBA Rev 1.2.1 compliant•

IBA Rev 1.2.1 compliant•Supports Altera Stratix 5,•

Supports Altera Stratix 5•Proven design, running in•

Proven design, running in
ASICs and FPGAs•

270MHz (FPGA),>500MHz ASICs

training•Link layer flow control•CRC generation andchecking•Protocol error and packet•1024 Queue Pairs

length checking•Unlimited 2 Gbyte

Unreliable Requests•Single or multiple data lanes•64 bit Transmit and Receive

DMA Interface for DDR,
128 bit interfaces for
QDR.

•Programmable Flow ControlPeriod•Dynamic Flow Control

Mechanism•Available for 1, 2 & 4 VirtualLanes•Supports Stratix5GX•IBA Version 1.2.1

compatible•Supports Altera Stratix 5•270MHz clock

FPGAS and ASICs•250MHz clock

UC DDR TCA QDRQDR Link Layer 8VLs

UC QDR TCA

FPGA

S5GX

S5GXS5GXVLANES

282

MHz

250

300

300

LEs

18,83227,44736,658Flip22546
23273
39,912
Flops
Polybus Systems Corporation
23 Providence Rd, Westford Ma, 01886 (978) 692-4828, bjrosen@polybus.com
BRAMS
1,233,472
48,039 Bits
1,536,807
Bits
Bits