２００７年度第５回知的財産翻訳検定＜英文和訳＞【電気・電子工学分野】※解答作成前に必ず下記の注意事項に目を通してください。
【解答にあたっての注意事項】
１．問題は 3 題あります。それぞれの問題の指示に従い、3 題すべて解答してください。
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問１．次のクレーム１と２をそれぞれ日本特許明細書の請求項１と請求項２として、＜スタート＞から＜エンド＞までを翻訳しなさい。参考資料として FIG. 1 とその説明を添付していますが、これらは翻訳対象ではありません。
＜スタート＞

1.

An active matrix display device, comprising:sets of row and column address conductors;
a row and column array of electro-optic display elements operableto produce a display, each of which is connected in series with a twoterminal non-linear switching device between a row conductor and acolumn conductor; anda drive circuit connected to the sets of row and column address
conductors for applying selection signals to the row address conductors
to select the rows of display elements and data signals to the column
address conductors to drive the selected display elements to produce
a required display effect,
wherein the data signals comprise pulse width modulated signals
whose width determines a desired grey scale output from a display element,
andwherein the drive circuit is adapted to provide selection signals
which comprise voltage pulse signals whose magnitude increases to amaximum voltage amplitude such that the current flowing through a
non-linear switching device during the application of a selection signal
tends towards a substantially constant value.

1

2.
An active matrix display device according to claim 1,
characterized in that the duration of a selection signal applied toa row address conductor is predetermined and defines an address period
for a display element and in that a data signal applied to a column
address conductor determines the end of an interval within the display
element address period in which current flows through the non-linear
switching device to drive the display element.
＜エンド＞

＊参考資料

Referring to FIG. 1, the display device, which is intended for
datagraphic display purposes, comprises an active matrix addressedliquid crystal display panel 10 of conventional construction andconsisting of m rows (1 to m) with n display elements 12 (1 to n) ineach row. Each display element 12, here represented as a capacitor,
comprises a liquid crystal display element consisting of two spaced
electrodes with twisted nematic liquid crystal material disposed
therebetween, and is connected electrically in series with abidirectional non-linear resistance switching device 15 between a row
address conductor 16 and a column address conductor 17. The non-linear
device 15 exhibits a substantially symmetrical threshold characteristic
and functions in operation as a switching element. The display elements
12 are addressed via the sets of row and column conductors 16 and 17
which are carried on respective opposing faces of two, spaced, glass
supporting plates (not shown) also carrying the opposing electrodesof the liquid crystal display elements. The devices 15 are provided
on the same plate as the set of row conductors 16 but could instead
be provided on the other plate and connected between the column
conductors and the display elements.

2【問１・課題図表（電気・電子工学）】

問２．次の米国特許明細書中の背景技術にかかわる記載内容について翻訳しなさい。
＜スタート＞As might be expected, the very small components on MEMS devices are
sometimes very fragile and subject to being easily damaged or degradedeven in normal operation. For this reason, a protective cover is often
employed even when the device is ultimately to be disposed in a
relatively isolated location. This cover is designed to protect the3components of the MEMS device from moisture and from deleterious
materials, as well as from impact by other objects during assembly oroperation. In the case of an optical MEMS device, the cover will normallybe transparent, or at least clear enough to allow passage of therequisite amount of light. The cover is almost always a separate
component, and must be securely mounted in such a manner so as tofacilitate the function of the cover and of the device itself. As
background for the present invention, an exemplary MEMS device will
now be described in greater detail.
＜エンド＞

問３．次の米国特許明細書中の実施例の説明にかかわる記載内容について翻訳しなさい。参考資料として FIG. 2 を添付します。

＜スタート＞

This embodiment also comprises a bidirectional shift register whichcontains a plurality of one bit shift registers. The number of one bit
shift registers is equal to the number of bottom stack registers, S2
through S9 located below the S register. Each one bit shift register
is connected to its corresponding S2 through S9 stack register as shownin FIG. 2. The one bit shift registers are electrically interconnectedin an alternating pattern, such that the S2 through S9 registers ofthe stack function in the sequential circular interconnect pattern given
by S2→S4→S6→S8→S9→S7→S5→S3→S2 as shown in FIG. 2. This sequential
selection of bottom stack registers operates in a circular repeatingpattern. The interconnecting wires of the one bit shift registers neverspan more than three adjacent shift registers, which avoids the needfor a long wire connecting the bottom shift register to the top shift
register. These shorter wires require a smaller driver, and bufferingis also minimized. The embodiment given uses eight additional stackregisters for the circular register array. However, other combinationsof bottom registers used in multiples of four can also be utilized.
＜エンド＞

4

【問 3・課題図表（電気・電子工学）】5