SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23D • 12277 Berlin • Germany
Phone +49 30 772051-0 • Fax ++49 30 7531078
E-Mail: sales@shf.de • Web: http://www.shf.deDatasheet
SHF 12124 A
Compact Dual-Channel 32 Gbps
Bit Pattern Generator

SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 1/14

Description
The SHF 12124 A is a dual-channel 32 Gbps bit pattern generator. It features two differential data outputs
with individual 4-Tap pre-emphasis capabilities, 2 UI skew control and duty cycle adjustment. Digital bit
sequences such as standard pseudo-random bit sequences (PRBS) or short user defined bit patterns aregenerated by the unit at the data outputs. Many applications in research, product development as well as
production tests require these data streams for testing electrical/optical components or testing signal
integrity in high speed digital data communication. A wide range of operating bit rates from 5 to 32 Gbps iscovered.
The operating bit rate is determined by a clock signal from an external clock source which is not part of thepattern generator. The generator operates at full clock, i.e. a 32 GHz clock signal is required for 32 Gbps
operation.
For trigger purposes two clock output signals (clock/2 and clock/16) are provided on the rear panel of theinstrument.
Its compact size allows placement very close to the probe tips for on-wafer measurements.

Features
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Two differential output channels
5 to 32 Gbps operation, ‘gap-free’
Output amplitude control (maximum 400 mV single ended)
4-Tap-FIR pre-emphasis individually adjustable for both channels
Skew control over two UI with 1/32 UI resolution for each output
711152331
PRBS 2 -1, 2 -1, 2 -1, 2 -1, 2 -1
16 Bit user programmable pattern
Two clock outputs (input clock divided-by-2 and 16) for trigger purposes
Built-in frequency counter for input clock
USB port to control the generator
Low power consumption: < 4 W
Compact size: 91 mm (W) x 54 mm (H) x 124 mm (D)Applications
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Research, Development, Production Tests
On-Wafer Testing
CEI-28G
100G Ethernet
Infiniband
Fibre Channel ®
High Speed Serial
Backplane Applications

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Specifications – SHF 12124 A
Parameter

Symbol

Unit

Min.

Typ.

Max.

Comment

Data Outputs
Minimum Bit Rate

Gbps

Maximum Bit Rate

Gbps

532

33430

500

adjustable by up to -6 dB,
AC coupled, no preemphasis applied

fs

450

600

measured at 32 Gbps
1
on scope display

ps

2.7

4

measured at 32 Gbps
2
on scope display

Maximum Output Level(Eye Amplitude)

VoutmV

Jitter (RMS)

JRMS

Jitter (PP)

JPP350

Crossing%

4750

53

Duty Cycle%

4750

53

of two consecutive eyes,
can be adjusted using BCC

Skew Control

UI-1

+1

adjustable in 1/32UI-steps

Connector TypeΩ

50ps

14

Rise/Fall Time

tr/tf

2.92 mm (K) female

1520%...80%
on scope display

1

Measured with Agilent 86100A with 70 GHz sampling head and precision time base triggered by Clk or Clk/2 output, using PRBS 231-1

2Measured with Agilent 86100A with 70 GHz sampling head and precision time base triggered by Clk or Clk/2 output, using PRBS 231-1

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ClockConnector TypeClock Input

2.92 mm (K) female

Clock/2 Output

Ω50

2.92 mm (K) female

Clock/16 Output

2.92 mm (K) female

Clock Input Frequency

fin_clock

GHz

532

Input Level

Vin_clock

mVpp

600

1000

AC coupled

Output Level
Clock/2
Clock/16

Vout_clock

mVpp

350
550

600
750

AC coupled
AC coupled

Output Frequency
Clock/2
Clock/16

fout_clock

GHzGHz2.50.3125

162

half of input frequency
input frequency/16

400600PatternITU-T (CCITT) conform
PRBS patterns at a length of71115
2331
2 -1, 2 -1, 2 -1, 2 -1 & 2 1 plus user defined pattern

Output Pattern

User Pattern Memory
Size for Data Outputs

bit16Clock Output Pattern

Output can be set to transmit
a clock pattern clock/2,clock/4, clock/8, clock/16

GeneralSupply Voltage

VeeV

4.75

55.25

Power Consumption

Ptot

W

HeightHmm

54

WidthWmm

91

DepthDmm

124

Weightmg

500

Case Temperature

Tcase°C

45+5V switching power supplyis included

4SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 4/14

Pre-Emphasis Terms and Definitions
Pre-emphasis based on a finite impulse response (FIR) filter is a way to compensate for high frequency
losses in a transmission path. It helps to reduce the inter-symbol interference when the filter coefficientscan be set adequately to compensate the imperfections of the channel’s impulse response. The basic idea
is to boost the high-frequency components while leaving the low frequency components in their originalstate.
The SHF12124A features a 4-Tap FIR filter structure for each channel as depicted in the following picture.

Pre-Cursor

Main

1st Post-Cursor 2nd Post-Cursor

+

X

Input

C(-1)

+

X

C(0)

1UI
Delay+

X

C(1)

1UI
Delay

X

Output

C(2)

1UI
Delay

The structure can be used very flexible. Up to four taps can be used and each one is individuallycontrollable. Polarity inversion allows to add or substract the tap from the main signal. Depending on theweight of the taps different configurations as pre- and post-cursors are possible. The most common
configuration is probably the use of one pre- and two post-cursors. As depicted in the following picture.

1st Post-Cursor Vpst1

2nd Post-Cursor Vpst2

1. Post-Cursor

Vpst1
Vpst2
Vamp
Main Vamp

2. Post-Cursor

Eye Amplitude

0Vpre

Pre-Cursor

Pre-Cursor Vpre

The ratio of the individual taps to the final eye amplitude is given by the following equations:

[]

()

[]

()

[]

()

SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 5/14

The following pictures show how pre- and post-cursor appear in the waveform or eye diagram of thesignal.

10 Gbps – One Pre- & Two Post-Cursors

10 Gbps – One Pre- & Two Post-Cursors

GraphicalPreview

Individual
Tap Settings

PreEmphasis
Channel 1
PreEmphasis
Channel 2

Main Tap
Selection
Pre-Emphasis Software Representation

SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 6/14

Skew Control Function
The skew control function allows adjusting the channel timing relative to each other. As a result, timing
delays between the two output channels can be compensated. The skew can be controlled in steps of1/32 UI. The maximum skew range is 2 UI, i.e. two eye lengths. Since the built-in phase rotator isoptimized for operation between 25 Gbps and 30 Gbps step accuracy might degrade at lower and higher
bitrates.

+5.5 ps
Skew
Control
Channel 1Skew
Control
Channel 2-5.5 ps

Skew Control Software Representation

0 ps

Skew Control Eye Diagram Representation

SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 7/14User Pattern Function
Besides the five pseudo-random bit sequences and the clock patterns a 16-Bit user pattern can betransmitted from each output. The user pattern can be set using a graphical representation in the userinterface.

Toggle User
Pattern Bits
Channel 1

Toggle User
Pattern Bits
Channel 2User Pattern Software Representation

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Duty Cycle Control Function
The duty cycle control function allows adjusting the length of consecutive eyes with a range ofapproximately +/-5% and with a 0.33% resolution.

DutyCycle
Channel 1

DutyCycle
Channel 2

Duty Cycle Control Software Representation

Duty Cycle Control Set to 50%

Duty Cycle Control Set to less than 50%

Duty Cycle Control Set to more than 50%

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Typical Output Waveforms
Data Output Signals (Pre-Emphasis completely deactivated)

32 Gbps output eye at maximum output level

30 Gbps output eye at maximum output level28 Gbps output eye at maximum output level

25 Gbps output eye at maximum output level

20 Gbps output eye at maximum output level

16 Gbps output eye at maximum output level

SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 10/14

14 Gbps output eye at maximum output level

10 Gbps output eye at maximum output level

5 Gbps output eye at maximum output level

SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 11/14

Clock/2 Output Signals

Clock/2 output signal @ 32 Gbps data rate

Clock/2 output signal @ 28 Gbps data rate

Clock/2 output signal @ 25 Gbps data rate

Clock/2 output signal @ 20 Gbps data rate

Clock/2 output signal @ 10 Gbps data rate

Clock/2 output signal @ 5 Gbps data rate

SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 12/14

Clock/16 Output Signals

Clock/16 output signal @ 32 Gbps data rate

Clock/16 output signal @ 28 Gbps data rate

Clock/16 output signal @ 25 Gbps data rate

Clock/16 output signal @ 20 Gbps data rate

Clock/16 output signal @ 10 Gbps data rate

Clock/16 output signal @ 5 Gbps data rate

SHF reserves the right to change specifications and design without notice – SHF 12124 A - V004 – August 26, 2014 Page 13/14

Outline Drawing+-SHF 12124 A Bit Pattern Generator

53.5

Channel 1Data

5V / 1A

Clock In

Data

Data

Data

50

50

1648
9150

50

USB

16.950

32.1

19.150

50

Clock/2 Out Clock/16 Out

Channel 2

22.6
39.554.5
69.5

113.7
123.4

All dimensions are specified in millimeters (mm).

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