Data Sheet SHF 19120 C
SHF Communication Technologies AG

Data SheetSHF 19120 C

2.85 GSa/s Arbitrary Waveform
Generator with
4x 12.5 Gbps BPG Outputs

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 1

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Description
The SHF 19120 C is a 2.85 GSa/s, 14-bit Arbitrary Waveform Generator (AWG) with four NRZ bit pattern
outputs. Its high AWG bandwidth (>1.4 GHz), high output amplitude (1.2 V on DC output, +10 dBm on the
AC output) and large sample memory size (1 Giga Sample) make it a versatile arbitrary generator.
Three outputs (Direct, DC and AC) cover a wide range of test scenarios (jitter, glitched signal, modulationand modulated signal generation, etc.)
Two markers with a 2-sample resolution can be used to trigger external equipment. Two edge/level trigger
inputs with adjustable thresholds start, pause or restart the signal generation.
Two or more SHF 19120 C instruments can be synchronized together via their 10 MHz references.
In addition to the three analog outputs, the SHF 19120 C can generate up to four 12.5 Gbps PRBS signals
with emphasis on the rear panel, driven by the DAC clock, or by an external clock.
The SHF Control Center software allows a complete control of the SHF 19120 C, including a waveform
editor with a waveform library and a Python equation editor.

SHF 19120 C: actual waveform and GUI

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 2

Data Sheet SHF 19120 C
SHF Communication Technologies AG

FeaturesArbitrary Waveform Generator
•
•
•
•
•
•
•
•
•

Sampling frequency fDAC up to 2.85 GHz
1 GSa - sample memory
Three types of outputs: Direct, DC coupled (1.2 Vpp) and AC coupled (+10 dBm max, in 0.1 dB
steps)High output bandwidth: DC to 1.4 GHz for the direct and DC outputs, 20 MHz to 500 MHz for the AC
outputUp-sampling: in Double Interpolation Mode, the signal spectrum is shifted to f DAC, doubling theeffective DAC update rate
Two sample-synchronous marker outputs
Two trigger (edge/level) inputs with adjustable thresholds
Output skew control in combination with trigger and marker delays help the synchronization ofseveral SHF 19120 C AWGs
Outputs and inputs for the DAC and BPG clock, and the 10 MHz reference

Bit Pattern Generator
•
•
•
•
•

Four PRBS differential outputs with lane bitrates from 0.372 Gbps to 10.3125 Gbps using the internal
clock and to 12.5 Gbps using an external clock.
Nine PRBS patterns (from PRBS 27-1 to PRBS 231-1), plus two square wave patterns of half-line rate
(SQUARE2) and line rate ÷ 32 (SQUARE32) and user-defined patterns (4 Gb per channel)
Frame trigger output
Bit skew adjustment
Pre and post cursor emphasis

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 3

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Applications
Jitter modulation source
•
•
•
•
•

random noise with a Crest factor up to 17 dB
Sinusoidal
PRBS
Multi-frequency and multi-tone
Custom shapes

Telecommunication
•
•
•
•
•
•
•
•
•

Generation of real-world waveforms
Ultrawide band signals
Development of long-haul data transmission schemes
Compliance testing
Step response and bandwidth measurements
Wireless communications
Backplane characterization
High speed serial link testing
Clock source

Optics••Shaped pulses
Photonics research

Medicine••

Simulating complex ECG patterns
Living cell stimulation

Radar / Lidar••

Chirp generation
Shaped signal generation

Physics••••

Reflectometry
Nuclear magnetic resonance research
Study of materials
Mass spectrometry experiments

Miscellaneous•••

Quantum Computing and quantum measurements
Development of Test and Measure Equipment
Radar signals

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 4

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Block Diagram

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V002 - February 20, 2024 - Page 5

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Specifications
Absolute Maximum Ratings
Parameter

Unit

Power Supply Voltage

V

Trigger Inputs

V

Clock Input
10 MHz Input

Symbol

Min.

Typ.

Max.

Comment

13
0

5CMOS, DC coupleddBm

3

AC coupledV

3.3

Peak-to-Peak, AC coupled

General Characteristics
Parameter

Unit

Symbol

Min.

Typ.

Max.

Power Supply Voltage

V

11.6

12

12.4

Power Supply Current

A

2

2.5

3

Power Consumption

W

Operating Temperature°C

Comment+12 V switching power supply is
included

30
10

35

General Characteristics AWG
Parameter

Unit

Resolution

bits

Sample Rate

GSa/sSymbolMin.

Output Adjustable Delay Step

Max.

fDAC

1.4

Comment
Markers do not decrease
resolution or memory size.

14

RF Connectors
Output Adjustable Delay

Typ.

the

2.85
SMA

Sample Clock0

Periods
Sample Clock254

2

periods

General Characteristics BPG
Parameter

Unit

SymbolMin.

Channels

Typ.

Max.

Comment4

Bit Rate Minimum

Gbps

0.500

Bit Rate Maximum (int. clock)Gbps

10.3125

See Ranges for the Bit Rate, p 15

Bit Rate Maximum (ext. clock)

Gpbs

12.5

See Ranges for the Bit Rate, p 15

RF Connectors

SMA

External Clock Input
Multiplier Factor
Adjustable Delay Lengthbit

Differential

18-Pattern
Length+Pattern
LengthThe BPG bitrate will be the external
clock frequency multiplied by thisfactorWith a 1 bit step

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V002 - February 20, 2024 - Page 6

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Direct Output AWG
Parameter

Unit

Symbol

Min.

Typ.

Max.

Comment

Impedance

Ohm

50

Voltage Window Minimum

mV

205

215

Single-ended. Includes the output
offset from internal biasing

Voltage Window Maximum

mV

740

790

Single-ended. Includes the output
offset from internal biasing

Adjustable Full-Scale
Amplitude Minimum

mV

210

Single-ended, Peak-to-Peak

Adjustable Full-Scale
Amplitude Maximum

mV

750

Single-ended, Peak-to-Peak

Full-Scale Amplitude StepmV

5±(50mV

Full-Scale Amplitude Accuracy±10%)

Random Jitter RMS

ps

JRMS

4

Measured with PRBS 7, sample clock
for trigger.

Rise/Fall Time

ps

tr/tf

110

0.7 V, 1.425 GHz square signal, from20 % to 80 %3 dB BandwidthMHz

Calculated Bandwidth

MHz

2000

0.223
𝑡𝑟

dBc

-81

32 Samples sine wave (89.0625 MHz),
0.63 Vpp signal. Harmonics excluded;
40 dB interpolation filter enabled.

dBc

-56

f1= 19.9 MHz f2= 20.1 MHz; 630 mVpp;
2f2-f1

%

0.7

SFDR
Spurious Free Dynamic Range
Two-Tone IMD
Inter Modulation Distortion
Harmonic Distortion

Not compensated for the sin(x)/x DAC
response.

1400

101.7857 MHz Output, 630 mVpp;
5 first harmonics.

Direct output: Differential or Single-ended output (Unused output must be terminated with a 50 Ω load), DC-coupled.
All the SHF 19120 C AWG outputs are unfiltered, to give the user the most versatile bandwidth. Depending on the application, an external low orhigh pass filter is recommended.

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V002 - February 20, 2024 - Page 7

Data Sheet SHF 19120 C
SHF Communication Technologies AG

DC Output AWG
Parameter

Unit

Symbol

Min.

Typ.

Max.

Comment

Impedance

Ohm

50

Voltage Window MinimummV

Voltage Window MaximummV

Adjustable Full-Scale
Amplitude Minimum

mV

330

Single-ended, Peak-to-Peak

Adjustable Full-Scale
Amplitude Maximum

mV

1300

Single-ended, Peak-to-Peak

Full-Scale Amplitude StepmV

5

The signal will be clipped outside thevoltage window

-200
1200

The signal will be clipped outside thevoltage window±(50mV

Full-Scale Amplitude Accuracy±10%)

Adjustable Offset

mV

Offset StepmV

5

Offset Accuracy

mV

±50

Random Jitter RMS

ps

JRMS

6

Rise/Fall Time

ps

tr/tf

120

3 dB Bandwidth (from DC)

MHz

Calculated Bandwidth

MHz

1850

dB

1

dBc

-71

32 Samples sine wave (89.0625 MHz);
1 Vpp with 0.6 V offset signal;
harmonics and fDAC excluded, 40 dB
interpolation filter enabled.

dBc

-56

f1= 19.9 MHz f2= 20.1 MHz; 700 mVpp;
2f2-f1%

0.2

Bandwidth Ripple(0 – 1400 MHz)SFDR
Spurious Free Dynamic Range
Two-Tone IMD
Inter Modulation Distortion
Harmonic Distortion

150

650

Limited by the output voltage window

Measured with PRBS 7, 0.7 Vpp,sample clock for trigger.
Measured with PRBS 7, 1 Vpp, sample
clock for trigger, from 20 % to 80 %Not compensated for the sin(x)/x DAC
response.

1400

0.223
𝑡𝑟

101.7857 MHz Output, 630 mVpp;
5 first harmonics.

DC output: Differential or Single-ended output (Unused output must be terminated with a 50 Ω load), DC-coupled
All the SHF 19120 C AWG outputs are unfiltered, to give the user the most versatile bandwidth. Depending on the application, an external low orhigh pass filter is recommended.

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 8

Data Sheet SHF 19120 C
SHF Communication Technologies AG

AC Output AWG
Parameter

Unit

SymbolMin.

Typ.

Impedance

Ohm

Adjustable Full Scale
Amplitude Minimum

dBm

Adjustable Full Scale
Amplitude MaximumdBm

Adjustable Amplitude Step

dB

0.1

AccuracydBm

0.2

Adjustable Bias

V

Adjustable Bias StepmV

50

Offset Accuracy

mV

±50

Bias Output Current

mA

3 dB Bandwidth(Starting at 20 MHz)
6 dB Bandwidth(Starting at 20 MHz)SFDR
Spurious Free Dynamic Range
Two-Tone IMD
Inter Modulation Distortion
Harmonic distortionMax.

Comment

50
-27
10

14

0

0.4
4.5

Integrated bias tee

±100
150

MHz

500

Not compensated for the sin(x)/x DAC
response.

MHz

1400

Not compensated for the sin(x)/x DAC
response.

dBc

-71

32 Samples sine wave (89.0625 MHz) 0
dB Output, harmonics and fDAC
excluded, 40 dB interpolation filter
enabled. DC to fDAC.

dBc

-55

f1= 99.45 MHz f2= 100.45 MHz; 0 dBm
output; fDAC= 2.12 GHz; 2f2-f1

%

0.4

dBc

-55

30 Sample sine wave, -10 dBm Output,
harmonics excluded DC to fDAC.

dBc

-63

f1= 2.28001 GHz f2= 2.2857 GHz; 0 dBm
output; fDAC= 2.85 GHz; 2f2-f1

101.7857 MHz Output, 0 dBm output
5 first harmonics.

Double Interpolation mode
SFDR
Spurious Free Dynamic Range
Two-Tone IMD
Inter Modulation Distortion

AC output: Single-ended output, AC coupled, with adjustable offset.
All the SHF 19120 C AWG outputs are unfiltered, to give the user the most versatile bandwidth. Depending on the application, an external low orhigh pass filter is recommended.

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 9

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Markers – Two Marker Outputs- Front Panel
Parameter

Unit

Symbol

Min.

Typ.

Max.

2

2.5

3

Comment

Amplitude

V

Impedance

Ohm

50

Match to 50 Ohms for best signal.

Resolution

Sample2*

Sample synchronous.

Width

Sample1

1G

LVCMOS25, DC coupled

A single marker will be automaticallyextended to a width of 1 ns by the
SHF Control Center.
Each marker must have a dead timeof 3 samples before the next marker.

Maximum Repeatability

Sa

3

Maximum Frequency

MHz

700

With fDAC =2.85 GSa/s.

Jitter peak-peak

ps

100

Direct output, 32-sample Dirac signal
for trigger. 3-sample marker, output
1.

Adjustable Delay

Sample Clockperiods

Adjustable Delay Step

Sample Clockperiods

0254
2*2 samples position uncertainty when generating a repeating signal with an odd sample count period and a marker on each period. The SHF Control
Center will issue a warning when this situation happens.

Triggers – Two Trigger Inputs – Front Panel
Parameter
Type

Unit

Symbol

Min.

Typ.

Max.

Comment

Rising edge, falling edge, gated high, gated low.

Adjustable Threshold Low

V

VIL

1.2

Measured on a 50 Ω system.

Adjustable Threshold High

V

VIH

4

Measured on a 50 Ω system.

Adjustable Threshold Step

mV

100

Measured on a 50 Ω system.

Adjustable Threshold
AccuracymV

100

Measured on a 50 Ω system.

Delay

ns

250 +
200*SaPulse Widthns

Pulse Frequency inStart/Pause Mode

MHz

Dwell time in Restart Modeµs

Trigger Jitter peak-peaknsAdjustable Delay

Sample Clockperiods

Adjustable Delay Step

Sample Clockperiods

From Trigger in to Signal present on
output.
X ns + Y*Sample Period

250
2
4

5
15+10*Sa0

X ns + Y*Sample Period510
2

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 10

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Internal Reference
Parameter

Unit

FrequencyMHz

Accuracyppm

Stabilityppb

Output Level

V

Output Impedance

Symbol

Min.

Typ.

Max.

Comment

10
-1

1
280

0.5

Ohms

0.6

Over the operational range.
Over the operational range.

1

External, back panel.

50

External Reference Input
Parameter

Unit

Frequency

MHz

Level

V

Impedance

Symbol

Min.

Typ.

Max.

Comment

10
0.5

Ohms

3.3

Peak-to-Peak.

50

Sample Clock
Parameter

Unit

SymbolMin.

Typ.

Frequency

GHz

1.4

Output LeveldBm

0

Output Impedance

Ohms

50

Max.

Comment

2.85
Rear panel, Peak-to-Peak.

Sample Sequencer
Parameter

Unit

Sample Granularity

SampleSample Length

Symbol

Min.

1G

1024

1G

1

Loops

1
GSa

Max.

1024

Segments

Sample Memory

Typ.

1

Comment

1 Sample = 14 bits + 2 Markers.

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 11

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Plots of Phase NoiseDAC Clock SMA Output, fDAC=1.4 GHz, 10 dB attenuator.

DAC Clock SMA Output, fDAC=2.85 GHz, 10 dB attenuator.

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 12

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Direct non inverting output. 28–sample sine wave (101.79 MHz), 0 dB output, 10 dB attenuator.

DC non inverting output. 28–sample sine wave (101.79 MHz), 0 dB output, 10 dB attenuator.

AC output. 28–sample sine wave (101.79 MHz), 0 dB output, 10 dB attenuator.

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 13

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Bit Pattern Generator Outputs
Parameter

Unit

ImpedanceΩOutput Amplitude MinimummV

Output Amplitude Maximum

mV

Symbol

Min.

Typ.

Max.

50

500

Output Level Steps

580

Comment
AC coupled

270

Single Ended, Peak-to-Peak, at 5 Gbps

750

Single Ended, Peak-to-Peak, at 5 Gbps

15Pre-emphasis: Precursor

dB

0

6.02

20 steps

Pre-emphasis: Postcursor

dB

0

12.96

31 steps

Jitter RMS

ps3

Rise/Fall Time

ps55

Crossing%

Duty Cycle%50

At 10.3125 Gbps.

Inter-Channel Skew

ps40

At 10.3125 Gbps.

45

50

4

At 10.3125 Gbps, PRBS 31, SQUARE32
for trigger.
At 10.3125 Gbps, PRBS 31, SQUARE32
for trigger, from 20 % to 80 %.

55

At 10.3125 Gbps.

ITU-T (CCITT) conform PRBS patterns at a length of:
Output pattern

27-1, 29-1, 210-1, 211-1, 213-1, 215-1, 220-1, 223-1, 231-1
Additional SQUARE2 and SQUARE32 0-1 patterns: line rate divided by 2 and32. 4 Gb of user pattern per channel.

Bit Rate Ranges

Gbps

Bitrate resolution

Kbps

See Ranges for the Bit Rate, p 15

100

Wordframe Trigger Division

231-1

32

Of internal clock cycles. 32 means 32
x (pattern length).
Uses the AWG Marker output.

Wordframe Trigger Level

V

2.1

2.5

LVCMOS25, DC coupled

Wordframe Jitter

ps

500

Peak-to-Peak

PRBS Ext. Clock Input Level

dBm

-5

10

PRBS Ext. Clock Input
Frequency

MHz

60

2800

Using the internal multiplierMax.

Comment

50 Ω, AC coupled

BPG User Pattern
Parameter

Unit

Symbol

Min.

Typ.
11

Bit Rate Maximum

Gbps

10.3125

Granularity

bits

64

Length64

Segments

1

Loops

1

MemoryGb

Per channel. The channels must havethe same pattern length.

4G

Per channel. The channels must havethe same pattern length.

4

Per channel*Enabling the BPG user pattern disables the AWG function.

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 14

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Ranges for the Bit Rate

Range 1
Range 2Range 3Range 4
Range 5
Range 6 (internal clock)Range 6 (external clock)1

From [Gbps]
0.372
0.613
1.225
2.45
4.9
9.8
9.8

To [Gbps]
0.5
1
2
4
8
10.3125
12.5

Pattern Types for the Pseudo Random Binary Sequence

1

Name
PRBS27-1
PRBS29-1
PRBS210-1
PRBS211-1
PRBS213-1

Polynomial
1 + X6 + X7
1 + X9 + X5
1 + X10 + X7
1 + X11 + X9
1 + X2 + X12 + X13

Length27 – 1 bit
29 – 1 bit
210 – 1 bit
211 – 1 bit
213 – 1 bit

PRBS215-1
PRBS220-1
PRBS223-1
PRBS231-1

1 + X14 + X15
1 + X17 + X20
1 + X18 + X23
1 + X28 + X31

215 – 1 bit
220 – 1 bit
223 – 1 bit
231 – 1 bit

Above 10.3125 Gbps user pattern will not be available

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 15

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Typical Output Waveforms (AWG)

2.85 GSa/s PAM-4 signal, DC Output

Frequency and phase synchronization of three SHF 19120 C(200 mV/div; 100 ps/div)

Edge-triggered signal generation.

Level-gated trigger signal generation.

“SHF” writing

Burst mode of three synchronized SHF 19120 C

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 16

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Signal with markers: marker output 1 for each risingpart of signal, marker output 2 for the signal start.

Screenshot from the SHF Control Center preview of thesignal shown on the left.

Multiple-Carrier Signal Noise-Power Ratio, AC Output,
0 dBm, 10 dB ext. att.

Multiple Carriers in Double Interpolation Mode, AC
Output, 0 dBm, 10 dB ext. att.

Original (yellow) and AWG waveform (green) after
import. Inductor voltage of a Ćuk converter.

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 17

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Typical Output Waveforms (BPG)

1 Gbps PRBS 231-1

5 Gbps PRBS 231-1

10.3125 Gbps PRBS 231-1

12.5 Gbps PRBS 231-1

12.5 Gbps PRBS 231-1 with a 3 meter cable12.5 Gbps PRBS 231-1 with a 3 meter cable andemphasis enabled

POST cursor = 0 dB PRE cursor = 0 dB

POST cursor = 1.94 dB PRE cursor = 2.5 dB

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 18

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Pre-emphasis: precursor, max. val. (1 Gbps, PRBS 27-1)

12.5 Gbps SQUARE 2 pattern

Pre-emphasis: postcursor, max. val. (1 Gbps, PRBS 27-1)

1 bit pattern shift (1 Gbps, PRBS 27-1 ; ch1 and ch2)

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 19

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Software
The SHF 19120 C is operated via an Ethernet connection with the SHF Control Center software.

SHF Control Center Software

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 20

Data Sheet SHF 19120 C
SHF Communication Technologies AG

SHF Control Center Software: Trigger Settings and Waveform Library pop-up

SHF Control Center Software: Waveform Editor

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 21

Data Sheet SHF 19120 C
SHF Communication Technologies AG

SHF Control Center Software: Python Equation Editor

SHF Control Center Software: Detail of the Bit Pattern Generator Controls

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 22

Data Sheet SHF 19120 C
SHF Communication Technologies AG

Mechanical Drawing
SHF 19120 C Arbitrary Waveform Generator - 4 Ch. Bit Pattern Generator

50.8

Triggers

Marker 1

Marker 2/
W-FrameDirect Output

DC Output

PWR

AC Output

OUT

On
Off

ERR

Input 1

Input 2

OutputOutputOutOut

DC OutDC OutAC Out5 Vpp Max

5 Vpp Max

2.5 Vpp Max

2.5 Vpp Max

1 Vpp Max

1 Vpp Max

1.5 Vpp Max

1.5 Vpp Max

4 Vpp Max8950  / 1.85 mm Female

1 2

3 4

5

1

6 7
221.5

7x 15

177

10

15

32.2
24.7
17.2

10

23.7
38.7
58.7
73.7
93.7
113.7
133.7
153.7
173.7

30.2

Pos
1
2
3

Designation
Trigger Input 1
Trigger Input 2
Marker Output 1

4

Marker Output 2 /Word Frame Out

SMA

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

Direct Output Out

SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA

Pos
1
2
3
4
5
6
7

Direct Output Out
DC Output DC Out
DC Output DC Out
AC Output AC Out
PRBS 1
PRBS 1
PRBS 2
PRBS 2
PRBS 3
PRBS 3
PRBS 4
PRBS 4Clock OutClock In
10MHz In
10MHz Out

Connector
SMA
SMA
SMA

Designation
GND
Service
HDMI
GND
Ethernet
USB
Power In18 16 14 12 101

250  / SMA Female

3

Ref. Clock
5 Vpp Max

12 V / 4 A

1 Vpp Max

10 MHz In 10 MHz Out
ServiceUSB

4

2 1 Vpp Max 3

Clock Out

PRBS Out1+10 dBm Max

4

2 1 Vpp Max 31+5 dBm Max

Ethernet
HDMI

PRBS OutClock In

21 20 19 17 15 13 11

2 3 4

5

6

7

All dimensions are specified in millimeters (mm).

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 23

Data Sheet SHF 19120 C
SHF Communication Technologies AG

SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23 D | 12277 Berlin | Germany+49 30 772 051 0
sales@shf-communication.com
www.shf-communication.com

SHF reserves the right to change specifications and design without notice
V002 - February 20, 2024 - Page 24