SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23D • 12277 Berlin • Germany
Phone +49 30 772051-0 • Fax ++49 30 7531078
E-Mail: sales@shf.de • Web: http://www.shf.de

Application Note
Jitter Injection using the MultiChannel BPG SHF 12103/12104

SHF reserves the right to change specifications and design without notice – V006 – October 23, 2014

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Introduction
The characterization of jitter tolerance and jitter transfer on high-speed communication components isessential to ensure low bit error rate transmission and compliance with telecommunication industry
standards. A jitter tolerance test specifies the limits of timing jitter a network device is required to tolerate
without performance degradation. A typical test as detailed by several standards comprises the generationof a jittered data signal with a sinusoidal jitter component of a certain frequency and amplitude. Figure 1
shows four examples of jitter frequency masks as defined in the IEEE 802.3ba Ethernet standard for 40
and 100 Gbit/s, and the ITU-T G.8251 OUT-3 standard for 10 and 40 Gbit/s [1], [2]. The jittered data signal
is applied to a device under test (DUT) to analyze if the performance is maintained under certain jitterstress limits given in the standard.
This application note presents the experimental setups that allow the injection of deterministic sinusoidal
jitter with a pre-defined peak-to-peak jitter amplitude and jitter frequency using either the SHF 12103 A or
the 12104 A bit pattern generator (BPG) and a minimal number of external components. The first sectionsof this note concentrate on sinusoidal jitter, whereas other jitter types are briefly covered in the lastsection. An overview of the various jitter types may be found in several textbooks on this topic, e.g. [3].
100Peak-to-Peak Jitter Amplitude [UI]IEEE 802.3ba 40G Ethernet
IEEE 802.3ba 100G Ethernet
ITU-T G.8251 OTU-2 (10 Gb/s)
ITU-T G.8251 OTU-3 (40 Gb/s)

10

1

0.1

0.01
1k

10k

100k

1M

10M

100M

1000M

Jitter Frequency [Hz]Figure 1: Sinusoidal jitter tolerance masks as defined in relevant
communication industry standards [1], [2].

Principle of Jitter Generation
Deterministic sinusoidal jitter can be interpreted as a harmonic frequency modulation (FM) of the signal
with a sine wave of a certain frequency and amplitude. The principle of jitter generation by frequency
modulation is illustrated in Figure 2. An ideal clock signal as shown in Figure 2(a) is frequency modulatedusing the sine wave shown in Figure 2(b) which results in the jittered clock signal shown in Figure 2(c).
The frequency and the amplitude of the FM input signal will determine the properties of the jittered clock.
The jitter frequency fjitter is set by the frequency of the FM input signal.

SHF reserves the right to change specifications and design without notice – V006 – October 23, 2014

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(a) Clock Source

TCLK = 1/fCLKTime(b) FM Input Signal
Deviation Vpp
1/fjitter(c) Jittered Clock Signal

Figure 2: Generation of a jittered clock signal by sinusoidal frequency modulation.

The peak-to-peak jitter amplitude App is commonly measured in unit intervals (UI) where 1 UI corresponds
to the bit duration TB of the data signal. Given a jitter amplitude value in seconds, App is obtained in UI
using

A pp T
TB(1)

where TB is the inverse of the bit rate. For example, a peak-to-peak jitter amplitude of 0.5 UI is equivalent
to 20 ps for a 25 Gbit/s data signal (TB = 40 ps).
The jitter amplitude is controlled by the amplitude Vpp of the FM input signal. The FM frequency deviation
F is proportional to Vpp as shown in Figure 2.
Theoretically, the jittered clock signal c(t) of Figure 2(c) may be described by

c(t )  Cˆ sin 2 f CLK t   cos 2 f jitter t

 ,

(2)

where fCLK is the clock frequency in Hz,  is the modulation index and fjitter is the jitter frequency in Hz. The
modulation index is related to the FM frequency deviation F by



F
.
f jitter(3)

The jitter peak-to-peak amplitude App is related to the modulation index by

App 


,


(4)

where App is measured in UI.

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Jittered Clock Signal
Jittered Clock Source
Signal Generator #1
fCLK

Jittered Data
SignalRF OutFM ModeDevice Under Test
Data
In

Error Analyzer

Data
Out

Data InClock
Out

Clock In

FM In
Signal Generator #2
fjitterVrms

RF OutFM
SignalFigure 3: Jitter tolerance setup using the SHF 12104 A BPG.

Jitter Injection Measurement Setup
In practice, a jittered clock signal may be generated using a signal generator with an FM input. The setup
is shown in Figure 3. Two signal generators are required to form a jittered clock source. The first generator
produces a high-frequency clock signal at fCLK, whereas the second may be a lower speed signal
generator that modulates the frequency of the clock signal at fjitter.
The jittered clock signal is connected to the clock input of the SHF 12103 A or 12104 A BPG. The clock
jitter is transferred to all the data outputs of the BPG (as will be confirmed below). The jittered data signals
may be applied to the DUT to determine the jitter tolerance. Depending on the specific jitter tolerance test
requirement, the output of the DUT is evaluated using the adequate test equipment such as an error
analyzer.
Using this setup, a jittered data signal with specified jitter frequency and amplitude may be generated byvarying the signal frequency fjitter and the amplitude level Vrms at signal generator #2. Practical limitations
arise due to the finite modulation bandwidth and linearity. Therefore, the calibration and verification of theclock source are mandatory.

Calibration and Verification of the Injected Jitter
In order to create an accurate jitter signal for a specific task, the parameters of the setup presented in
Figure 3 need to be calibrated and verified. We will describe how to determine the settings of generator #2
for the generation of jitter with a desired frequency and amplitude. Also, the limitations of this jitter
generation technique are discussed. The accuracy and the characteristics of the jittered data signal may
be verified using an oscilloscope in the time domain. Additional verification can be achieved by analyzing
the spectrum of the jittered clock signal.
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Jittered Clock Source
Signal Generator #1
fCLK

JitteredClock
SignalRF OutFM ModeJittered Data
SignalPower
Divider

10 MHz Ref Out FM In
Ch1 Ch2 Trigger

Signal Generator #2
fjitter
Vrms

Oscilloscope
RF OutFM
SignalSignal Generator #3
fCLK / 2

RF Out10 MHz Ref In

Jitter-Free
Clock

Figure 4: Jitter calibration and verification setup for the time-domain analysis of jittered signals.

Time-Domain Jitter Measurement
For the time-domain analysis of the jittered output waveform, a modified setup is used as shown in
Figure 4. The procedure for setting up the jittered clock source depends on the signal generator models to
be used. Here, an Anritsu 68197C is used as signal generator #1. The FM function of the 68197C isenabled using the following parameters:Mode: Locked Low Noise
Impedance: 50 Ω
Source: Front.
Sensitivity: up to 20 MHz/V

The FM input signal is provided by the lower speed signal generator #2. Remember that, typically, the jitter
frequency ranges from a few kHz to several hundreds of MHz. Here, a HAMEG HM8135 is used. The jitter
frequency and amplitude are programmed on the HM8135 by varying the signal frequency and RMS level.
The jittered clock and data output signals are visualized and characterized on an Agilent 86100A sampling
oscilloscope. In order to derive a jitter-free trigger signal, a third signal generator is synchronized to signal
generator #1 using the 10 MHz reference port. The trigger signal is connected to the time base input of thesampling oscilloscope.
As an example, the setup was adjusted to generate sinusoidal jitter with an amplitude of App = 0.47 UI anda frequency of fjitter = 1 MHz at a clock frequency of fCLK = 28 GHz and a bit rate of 28 Gbit/s. The jitter
amplitude is verified using the time markers on the oscilloscope. The time difference T is measured as
the maximum deviation at a defined instant of the waveform. The jitter amplitude App is calculated using
Equation (1).

SHF reserves the right to change specifications and design without notice – V006 – October 23, 2014

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Figure 5: Jittered clock eye diagram with 0.47 UI jitter amplitude at 28 GHz clock frequency(bottom) and jittered PRBS data eye at 28 Gbit/s with the same amount of jitter transferred fromthe clock (top).

Figure 5 shows the eye diagrams of the jittered clock and data waveforms measured using the presented
setup. The jitter on the clock is transferred to the jitter on the data signals. Clearly, a deterministic jitter of
16.9 ps is measured on the data signal which corresponds to 0.47 UI according to Equation (1). The shapeof the histogram shown in Figure 5 is typical of sine-wave jitter [4].

Jitter Transfer from the Clock Signal to the BPG Data Output
Due to its clock distribution circuitry, the SHF 12103 A and SHF 12104 A pattern generators transfers thejitter correctly from the clock signal to the PRBS data signal over the relevant range of jitter frequencies
and amplitudes. The setup shown in Figure 4 was used to measure the clock jitter amplitude App,clk andthe data jitter amplitude App,data for seven different jitter frequencies (8 kHz, 100 kHz, 500 kHz, 1 MHz,
4 MHz, 10 MHz, and 16 MHz) at 28 Gbit/s using a 28 GHz clock. At each frequency, up to five jitter
amplitude value pairs were measured. The results showed that the jitter properties (jitter type, frequency
and amplitude) of the clock signal are transferred unaltered to the data output signal. It will be discussed
below that for the presented lab setup the largest achievable jitter amplitude and frequency are limited bysignal generator #1.

Frequency-Domain Jitter Measurement
The jitter amplitude measurement on the oscilloscope is limited to 2 UI since the signal or clock edges
cannot be identified in the eye above 2 UI. For larger amplitudes, spectrum based techniques can beused. For the spectral analysis of the jittered clock, a setup according to Figure 6 is used. The jitteredclock is connected to a spectrum analyzer for the analysis of the FM spectrum.
Jitter frequency and amplitude can be verified on the spectrum analyzer in the frequency domain using theso called Bessel “nulls” method which is detailed in [5]. An important property of the frequency-modulated
clock signal spectrum is that the amplitude of the carrier becomes zero at defined jitter amplitudes. FromFM theory it can be shown that a carrier zero occurs whenever the modulation index  is equal to the rootsof the Bessel function J0. The first four roots are at  = 2.40, 5.52, 8.65, 11.79. Note that the modulationindex is related to the jitter amplitude by Equation (4). For example, at a jitter frequency of fjitter = 1 MHz,the first carrier zero occurs at a jitter amplitude of App = 2.4/π = 0.76 which is equivalent to T = 27.3 ps
at fCLK = 28 GHz. Using the Bessel “nulls” method, specific values of App can be measured very accurately.

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Jittered Clock Source
Signal Generator #1
fCLK

Spectrum Analyzer
JitteredClock
SignalRF OutInput

FM Mode10 MHz Ref Out FM In
Signal Generator #2
fjitterVrms

RF OutFM
SignalFigure 6: Jitter calibration and verification setup using a spectrum analyzer.

Figure 7(a) shows a measured spectrum of the clock signal without FM, i.e. the carrier spectral component
is located at 28 GHz. Figure 7(b) illustrates the carrier zero in the spectrum of the FM modulated clock at a
modulation index of  = 2.4. The spectrum shows a ratio of the carrier and the first sideband of
20log(J1/J0) > 38 dB which corresponds to less than 1% deviation error. Figure 7(c) displays a screen
capture of the oscilloscope showing the corresponding eye diagram in the time domain. Clearly, a jitter
amplitude of 27 ps is achieved which is equivalent to 0.76 UI.

f = 10 MHz
P = 38.7 dB

(a)

(b)

(c)
Figure 7: Spectra of (a) unmodulated 28 GHz clock and (b) FM modulated clock with 10 MHz jitter
frequency showing the first carrier zero. (c) Corresponding clock eye diagram with 0.76 UI jitter
amplitude (27 ps).
SHF reserves the right to change specifications and design without notice – V006 – October 23, 2014

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Characterization of the Jitter Generation Setup
At a fixed fjitter and fCLK, the voltage rms level Vrms on signal generator #2 determines the jitter amplitude.
Inside generator #1, the FM input is usually applied to the voltage controlled oscillator. Practical limitations
arise due to the finite modulation bandwidth and the limited linearity range between FM input amplitude
Vrms and the actual modulation index of the output. Therefore, the relation between the FM input voltage
amplitude and the jitter amplitude should be characterized experimentally for a given combination of signal
generators.
The following steps describe a possible technique to characterize the jitter amplitude versus the FM input
amplitude Vrms using the setups shown in Figure 4 and 6.


Set the clock frequency of the signal generator #1 such that the specified bit rate is generated at
the SHF 12103 A or SHF 12104 A.



In order to derive a trigger signal, set the frequency of the signal generator #3 to an adequate
value depending on the clock frequency and the trigger requirements. Typically, the trigger
frequency is half or a quarter of the clock frequency.



Set the jitter frequency on signal generator #2 to the frequency fjitter at which you want to inject thesinusoidal jitter.



Adjust the FM amplitude level Vrms on generator #2, and the FM modulation sensitivity S on
generator #1. Measure the jitter amplitude App on the oscilloscope or on the spectrum analyzer
until the desired jitter amplitude is created. The result is a set of values for Vrms, S and App.

As a result, a range of amplitude values App can be determined as a function of fCLK, fjitter, S and Vrms.
These results can then be used for jitter injection measurements.

Jitter Generation Example
The jitter amplitude of a clock signal was measured for jitter frequencies of 500 kHz, 1 MHz, 4 MHz and
10 MHz using the time-domain and frequency-domain methods described above. The clock frequency wasset at 28 GHz. Figure 8 summarizes the results by showing the measured jitter amplitude of the clock
signal in UI as a function of the normalized FM level. It is convenient to define the normalized FM
amplitude level  FM as follows

 FM 

Vrms S,f jitter

(5)

where


Vrms is the rms voltage level of the FM signal at the signal generator #2 in Volts

f jitter is the frequency of the FM signal at the signal generator #2 in MHz



S is the sensitivity of the FM modulation at the signal generator #1 in MHz/V. In the case of theAnritsu 68197C, the sensitivity is adjustable.

The linear fit shown in Figure 8 is determined empirically and is given by

App  0.45  FM .

(6)

Note that this relation is only valid in a certain jitter frequency range and depends on the specific set of
instruments.
By assuming that the linear relation is valid, Equations (5) and (6) may be used to derive the necessary
FM signal generator settings for a desired jitter amplitude and frequency at a clock frequency of 28 GHz.
For example, if a jitter injection of 1.5 UI at fjitter = 1 MHz is required, the normalized FM level is obtained
 FM = 3.3. For a sensitivity of S = 20 MHz/V, the signal generator #2 is set to an absolute rms level of

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Clock Jitter Amplitude App [UI]

3.5
3.25

f_jitter=500kHz, Sens. 10MHz/V

3

f_jitter=1MHz, Sens. 20MHz/V

2.75

f_jitter=4MHz, Sens. 20MHz/V

2.5

f_jitter=10MHz, Sens. 20MHz/V

2.25

Linear Fit

2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

Normalized FM Level

Figure 8: Jitter amplitude imposed on a 28 GHz clock signal versus the normalized FM level obtainedusing the presented jitter injection setup for a range of jitter frequencies.

Vrms = fjitter ×  FM / S = 165 mV. Note that the validity of Equation (6) depends on the clock frequency andthe jitter frequency range. It should be calibrated in the range of interest.
The measurements show that the largest achievable modulation index and, hence, jitter amplitude andfrequency are limited by the FM modulation bandwidth of the Anritsu signal generator. With increasing
jitter frequency the maximum achievable jitter amplitude decreases due to the signal generator’s FM
deviation limit. The Anritsu 68197C will either give a locking error or a warning to reduce the input voltage
level. The frequency deviation limit can be taken from the signal generator’s data sheet or may be
determined experimentally.
By combining the information from the data sheet of the signal generator and the measurement results,
Figure 9 shows the achievable jitter amplitudes versus frequency using the Anritsu 68197C. At a numberof selected jitter values, the correct jitter transfer was verified on both the SHF 12103 A and SHF 12104 A
data output.
Further, it was tested if the generated jittered data signals are still error-free. For this experiment, thejittered clock signal was used to clock both the pattern generator and the error analyzer. This ensures thatthe error analyzer is not affected by the jitter. Error-free operation was successfully verified for themeasured points shown in the graph in Figure 9.
For comparison, the jitter standards requirements from Figure 1 are added. Clearly, the requirements atlower frequencies are easily met. However, jitter frequencies above 10 MHz exceed the FM modulation
bandwidth of the Anritsu 68197C signal generator.

Jitter Injection up to 1 GHz Using SHF 78210 / 78120
In order to use the jitter injection capabilities of the SHF 12103 A or SHF 12104 A up to 1 GHz, wedeveloped the SHF 78210 / 78120 Synthesized Clock Generator series which feature a modulation input
with 1 GHz bandwidth to apply arbitrary jitter with up to 60 ps amplitude to the clock signal. The setup is
shown in Figure 10. The jittered clock signal is fed into the BPG clock input.

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Peak-to-Peak Jitter Amplitude [UI]

1000

Signal Synthesizer FM Limit
IEEE 802.3ba 40G Ethernet
IEEE 802.3ba 100G Ethernet
ITU-T G.8251 OTU-2 (10 Gb/s)
ITU-T G.8251 OTU-3 (40 Gb/s)
Synthesizer @28 Gbit/s
Delay Line @28 Gbit/s
Delay Line @40 Gbit/s
Delay Line @10 Gbit/s

100

10

1

0.1

0.01
1k

10k

100k

1M
10M
Jitter Frequency [Hz]

100M

1000M

10000M

Figure 9: Maximum achievable sinusoidal jitter amplitude versus jitter frequency using theSHF 12103 A or SHF 12104 A BPG.

By analyzing the eye diagram and the spectrum, it was confirmed that the jittered data signal contains thesame amount of jitter as the clock input under all specified operating conditions. Additionally, error-freepattern generation was successfully verified for the delay line jitter injection technique for the measured
points shown in Figure 9. This confirms that both the 12103 A and the 12104 A are jitter-transparent in thesense that they transfer the clock jitter unaltered to the generated data signal.
Note that the modulation port of the SHF 78210 / 78120 not only supports sinusoidal but arbitrary jitter
types such as random jitter, rectangular (peak-to-peak) jitter or bounded uncorrelated jitter. Simply replace
the signal generator #2 by an arbitrary waveform generator (AWG). Setting the AWG to NOISE willproduce random jitter, for example. Further details can be found in the datasheets of the SHF 78210 /SHF 78120 at www.shf.de.
The SHF 78210 operates as a module in existing SHF BERT mainframes and the SHF 78120 provides thesame functionality in a standalone bench-top device. For further information, please contact our sales
team:
SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23 D
12277 Berlin, Germany
phone:
fax:
email:
web:+49 30 772051-0+49 30 7531078
sales@shf.de.
www.shf.de

SHF reserves the right to change specifications and design without notice – V006 – October 23, 2014

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Jittered Clock Source

Signal Generator #2
fjitterVrms

RF OutSinusoidal Jitter Signal

JitteredClock
SignalFigure 10: Jittered clock source using SHF 78210 D.

Conclusion
Jitter tolerance test setups were presented using the SHF 12103 A or SHF 12104 A, the SHF 78210 or 78120
clock generators and the FM function of an external signal generator. It was demonstrated that the SHF
pattern generators are jitter transparent, i.e. they correctly transfer the jitter from the clock signal to the data
output signal over the entire considered jitter frequency and amplitude range. The setups enable sinusoidal
jitter injection tests as required by many telecommunication standards such as 100G Ethernet and 40 GBit/s
OTN. Several hundreds UI of jitter amplitude can be generated at lower jitter frequencies in the 10 kHz range
using the FM technique. The maximum sinusoidal jitter frequency was limited to 10 MHz due to the signal
generator’s FM bandwidth. To overcome this limit and for injection of other jitter types, SHF offers the 78210 /
78120 Synthesized Clock Generator which feature a Modulation port with 1 GHz bandwidth and up to 60 ps
jitter amplitude. The proposed jitter injection setups meet the standards requirements with sufficient margin.

References
TM[1] IEEE 802.3ba -2010, Part 3, Amendment 4: Media Access Control Parameters, Physical Layers,
and Management Parameters for 40 Gb/s and 100 Gb/s Operation
available online: http://standards.ieee.org/about/get/802/802.3.html[2] Recommendation ITU-T G.8251 (09/2010), Series G: Transmission Systems and Media Digital
Systems and Networks, Packet over Transport aspects – Quality and availability, The control of jitter
and wander within the optical transport network (OTN)
available online: http://www.itu.int/rec/T-REC-G.8251-201009-I/en[3] Wolfgang Maichen. Digital Timing Measurements: From Scopes and Probes to Timing and Jitter.
Springer, 2006.
[4] Agilent Technologies Application Note AN-5988-9756EN: “Jitter Fundamentals: Agilent 81250
ParBERT Jitter Injection and Analysis Capabilities.” 2003.
[5] Agilent Technologies Tutorial 5988-6254EN: “Understanding Jitter and Wander Measurements andStandards.” Second Edition, 2003.

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