Article

2 kW Dual-Output Isolated DC/DC Converter Basedon Current Doubler and Step-Down Chopper
Yoshinori Matsushita 1,2, * , Toshihiko Noguchi 1 , Noritaka Taguchi 2 and Makoto Ishii 3
1
2
3

*

Graduate School of Science and Technology, Shizuoka University, Hamamatsu 432-8561, Japan;
noguchi.toshihiko@shizuoka.ac.jp
Yazaki Research and Technology Center, YAZAKI Corporation, Susono, Shizuoka 410-1194, Japan;
noritaka.taguchi@jp.yazaki.com
In-Vehicle Systems R & D Center, YAZAKI Corporation, Susono, Shizuoka 410-1194, Japan;
makoto.ishii@jp.yazaki.com
Correspondence: matsushita.yoshinori.15@shizuoka.ac.jp

Received: 5 November 2020; Accepted: 11 December 2020; Published: 14 December 2020


Abstract: In the context of the auxiliary power for motor-driven vehicles having two systems,
we propose a new topology for a dual-output isolated DC/DC converter, which offers advantages
in terms of efficiency and size. The proposed circuit consists of an H-bridge inverter, a transformer,
and an integrated circuit of a current doubler and step-down chopper. Considering the high power andhigh frequency, our objective was to evaluate and identify the issues of an actual device with a power
output of 2 kW and switching frequency of 400 kHz. The circuit feasibility was examined throughmeasurements of the prototype, and both the voltage target response and load disturbance response
characteristics were confirmed to operate as designed. The maximum and minimum efficienciesof this circuit were 81.3 and 61.5%, respectively, demonstrating that the load loss of the step-down
chopper had a significant impact on the efficiency. The loss analysis revealed that the loss at the
integrated circuit on the secondary side accounted for more than 50% of the total loss. Moreover,issues such as the behavior at power-on, efficiency, and size were identified and evaluated, thereby
achieving the objectives of the study.
Keywords: dual output; DC/DC converter; auxiliary power source; current doubler; step-down chopper

1. Introduction
Approximately one quarter of the global CO2 emissions, which are the cause of global warming,
originate from the transportation sector [1]. To reduce such emissions, the automotive industry has
introduced motor-driven vehicles such as electric vehicles (EVs), plug-in hybrid vehicles (PHVs),
and fuel cell vehicles (FCVs) into the market, the sales of which continue to increase [2]. In September
2020, the state of California announced a plan to ban the sale of new gasoline-driven vehicles in2035. Accordingly, the sale of motor-driven vehicles is expected to accelerate in the future. Isolated
DC/DC converters are used as auxiliary power for these motor-driven vehicles, with the power supply
for the motor drive as the input [3,4]. The capacity and power consumption of auxiliary power is
expected to increase in the future in response to the electrification of traditionally mechanical functions,such as steering and reclining mechanisms, as well as the increase in comfort-enhancing electricalcomponents such as seat heaters [5,6]. The increased capacity leads to an increase in the conduction
loss, and changing the conventional 12 V auxiliary power to 48 V has been proposed to reduce thisloss [7,8]. However, as loads that require a 12 V power supply still exist, the mixing of the two loadsystems, namely 48 and 12 V, continues to be necessary. At present, several methods are available
to realize the two systems’ auxiliary power; for example, installing two isolated DC/DC converters
World Electric Vehicle Journal 2020, 11, 78; doi:10.3390/wevj11040078

www.mdpi.com/journal/wevj

DC/DC converter for 48 and 12 V in a 48 V system [9]. However, these methods exhibit problems
such as an increased size owing to the installation of two units and reduced efficiency as a result of
the two power conversions. To overcome these issues, we propose a novel dual-output isolated
DC/DC converter, which includes an integrated circuit of a current doubler and step-down chopper
World Electric Vehicle Journal 2020, 11, 78
2 of 19on the secondary side and outputs both 48 V and 12 V [10]. Since the secondary side of the proposed
circuit is an integrated circuit and there is no need to convert voltage twice to generate 12 V, thewith the power supply input for the motor drive or inserting a non-isolated bidirectional DC/DC
proposed circuit is expected to have a smaller size and higher efficiency although the control method
converter for 48 and 12 V in a 48 V system [9]. However, these methods exhibit problems such as an
becomes increased
more complex.
Astheourprevious
based
on assimulations
downsized
size owing toinstallationof twostudies
units andwere
reducedefficiency
a result of the or
twoapower
prototype,no actual To
devicetesting
yet webeen
performed
powerisolated
for automotive
applications.
conversions.
overcomethesehasissues,proposea novel withdual-output
DC/DC converter,which
includesanintegrated
circuitofacurrent
doublerandstep-down
chopperonthesecondaryside
Meanwhile, a demand exists for the downsizing of power converters, and one of the methods
toandoutputs
both
48
V
and
12
V
[10].
Since
the
secondary
side
of
the
proposedcircuitisanintegrated
achieve this goal is increasing the frequency. In this manner, the passive components in circuits, suchcircuit and there is no need to convert voltage twice to generate 12 V, the proposed circuit is expected toas the transformer, inductance, and capacitance, can be downsized. Therefore, substantial research
have a smaller size and higher efficiency although the control method becomes more complex. As ourhas been previous
conducted
on werehigh-frequency
drive power
converters
usingnoswitching
devicesstudiesbased on simulations
or a downsized
prototype,
actual device
testing madehas yetof GaN,
which enable
faster switchingthan
Si devicesapplications.
[11–14]. However, as the frequency increases, the loss
been performed
with power
for automotive
Meanwhile,a demandexists for thedownsizingof power
converters,
and one ofdevice
the methods
at the downsizedpassivecomponents
andswitchingloss ofthe switchingalso toincrease,achieve
this
goal
is
increasing
thefrequency.
In
thismanner,thepassivecomponentsincircuits,
suchminimumasleading to a larger cooling mechanism. Therefore, a specific frequency exists to realize thethe transformer, inductance, and capacitance, can be downsized. Therefore, substantial research has
device size. This frequency is dependent on the input/output power conditions, but it is expected tobeen conducted on high-frequency drive power converters using switching devices made of GaN,
increase withimprovement
inthanthe Sistructuresand materials
thepassiveincreases,
components
whichtheenablefaster switching
devices [11–14].
However, asofthefrequency
the loss[15–17].
atWithinthis
context,
we
conducted
a
study
on
a
novel
dual-output
isolated
DC/DC
converter
the downsized passive components and switching loss of the switching device also increase, leading toa larger coolingmechanism.
Therefore,
a specificexistschopper
to realizeon
the theminimum
device side,
size. whichwith an integrated
circuitof a current
doubler
andfrequency
step-down
secondaryThisfrequency
isdependent
ontheinput/output
power
conditions,
but
it
is
expectedtoincreasewith
was previously only evaluated for downsizing. We constructed an actual device with a maximum
the improvement in the structures and materials of the passive components [15–17].
output power of 2 kW for automotive applications, examined its validity, and identified its issues. In
Within this context, we conducted a study on a novel dual-output isolated DC/DC converter
considerationof integrated
the trend circuitof higher
as explained
above,choppera switchingis set to 400with anof a frequency
current doubler
and step-downon thefrequency
secondary side,
kHz, which
is about
two times
higherthanforswitchingfrequenciesof existingstudies
onwitha three-portwhich
was previously
only
evaluated
downsizing.
We constructed
an actualdeviceamaximum
output
power
of
2
kW
for
automotive
applications,
examined
its
validity,
andidentified
its
isolated DC/DC converter [18–20].
issues. In consideration of the trend of higher frequency as explained above, a switching frequency is
to 400 kHz, which
is about
two times
higher than switching frequencies of existing studies on a
2. Circuitset
Configuration
andOperation
Principle
three-port-isolated DC/DC converter [18–20].

2.1. Circuit
Configuration
2. Circuit
Configuration and Operation Principle
Figurepresents
the proposed circuit, consisting of a dual-output isolated DC/DC converter,
2.1. 1Circuit
Configuration
with an inputFigure
voltage
Vin andthe
two
outputcircuit,voltages
Vout1 andout2. The input/output isolation is realized
1 presents
proposedconsistingof aVdual-output
isolated DC/DC converter,by a high-frequency
transformer.
An output
H-bridge
inverterconsisting
ofinput/output
S1–S4 is connectedwith an input voltage
Vin and two
voltages
V out1 andV out2 . The
isolation is on therealizedby a transformer.
high-frequency A
transformer.
An H-bridge
inverter consistingof S1–S4
connectedon(Figuretheprimary sideof thecurrent doubler
consistingof L11, L12,
D1,isD2,
and C12a)
primarysideofthetransformer.
A
current
doublerconsisting
of
L11,
L12,
D1,
D2,
and
C1
(Figure2a)
as well as an interleaved step-down chopper consisting of S5, S6, D1, D2, L21, L22, and C2 (Figure
as well as an interleaved step-down chopper consisting of S5, S6, D1, D2, L21, L22, and C2 (Figure 2b)2b) are connected on the secondary side of the transformer to form an integrated circuit. D1 and D2
are connected on the secondary side of the transformer to form an integrated circuit. D1 and D2
are included
in both incircuits,
therebyreducing
thethenumber
TheH-bridge
H-bridge
inverter andare included
both circuits,
therebyreducing
numberofofcomponents.
components. The
inverterhigh-frequency
transformer
have conventional
simpleandtwo outputs
areand high-frequency
transformer
have conventional
simpleconfigurations,configurations, andthe thetwo outputs
aresolelythewiththe secondaryside
circuit.
achievedachieved
solely withsecondaryside
circuit.
S1

S2

L11
Vtxs

L12

Vin
S5

C1 Vout1

S6

L21
S3

S4
D1

D2

L22

C2 Vout2

Figure1. Proposeddual-output DC/-DC
converter.
Figure1. Proposeddual-output
DC/-DC
converter.

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L11

Vout1

L12

C1

S5

S6
L21

D1

D1

D2

3 of 20

D2

(a)

L22

Vout2
C2

(b)

Figure 2. Decomposed configuration of secondary circuit: (a) current doubler; (b) step-down chopper.

Figure 2. Decomposed configuration of secondary circuit: (a) current doubler; (b) step-down chopper.
The current paths L11 and L12 are for the current doubler output, and the current paths L21 andL22
arefor paths
the step-down
chopper
output.
As acurrent
result, theconduction
loss is andreducedhalf compared
The current
L11 and
L12 arefor thedoubler
output,theby
current
paths L21 andtoasingle-loadcurrent
path.
Becausethephasesofthesecurrentsareinterleaved
with
a
shift
of
180◦ , by half
L22 are for the step-down chopper output. As a result, the conduction loss is reduced
the ripple frequencies at C1 and C2 become twice the inverter frequency, which reduces the capacity
compared to a single-load current path. Because the phases of these currents are interleaved with aand thereby the volume of C1 and C2 by half. To maintain the interleaving symmetry, the inductanceshift of 180°,
rippleC1L22
andC2 becomethevalues.
inverter frequency, which reduces
valuestheof L11and frequencies
L12 and of L21atandshouldbe set to twice
the samethe capacity and thereby the volume of C1 and C2 by half. To maintain the interleaving symmetry,
2.2. Operation Principle
the inductancevalues of L11 and L12 and of L21 and L22 should be set to the same values.
By switching S1 to S4, the H-bridge inverter generates three levels of voltage, namely +Vin , 0,and −VPrinciple
in , and these voltages are applied on the primary side of the transformer. This circuit includes
2.2. Operation
six operation modes based on the combination of the transformer secondary side voltage level Vtxs ,By switching
S1 to S4,according
the H-bridge
inverterlevelsof voltage,
namely +Vin, 0, andwhich is transformed
to the turns
ratiogenerates
N1:N2, andthree
the on–off
statesof S5 and S6.
Table
1 presents
states ofon
Vtxs
, S5,
and S6, as
well
thetransformer.
correspondingThis
operation
modes.
−Vin, and thesevoltages
aretheappliedtheprimaryside
ofasthecircuitincludes six
In
Table
1,
“1”,
“0”,
or
“−1”
for
V
representavoltageofapositivevalue,
0,oranegative
among
txs
operation modes based on the combinationof the transformer secondary side voltage levelthe
Vtxs, which
three levels, respectively. Moreover, “-” for S5 and S6 indicates that it is irrelevant whether it is on oris transformed
according to the turns ratio N1:N2, and the on–off states of S5 and S6.
off. The reason for this irrelevance is that in these cases, a current flows from the source to the drain inTable
1 presents
the passes
statesthroughof Vtxs, theS5,body
anddiodeS6, aswell
as thecorresponding operation modes. In
S5 or
S6; the current
evenin theoff state.

Table 1, “1”, “0”, or “−1” for Vtxs represent a voltage of a positive value, 0, or a negative among theTable“-”
1. Operation
modes
proposed circuit.
three levels, respectively. Moreover,for S5 andS6ofindicatesthat it is irrelevant whether it is on oroff. The reason for this irrelevance
isModethat in these
Operation
1
6 from the source to the drain
2cases,3 a current
4
5flowsin S5 or S6; the current passes throughthe body
diodeeven
in the−1off state.
Vtxs
1
1
0
−1
0
S5
S6

off
-

on
-

-

off

on

-

Table 1. Operation modes of proposed circuit.

To explain Operationeach operationmode, FigureMode
1 3 depicts
2 the3ideal waveforms
4
5 in the6main part of thesecondary side circuit in steady-state operation, whereas Figure 4 presents the equivalent circuit andVtxs mode in the1 secondary
1 side0circuit.−1−1 top, Figure0current flow of each operation
From the3 shows thetransformer secondary side
voltageV,theswitchingstates
of
S5
and
S6,
the
inductor
currents on
txs off
S5
on
the current doubler side IL11 and IL12 , and the inductor currents on the step-down chopper side IL21
S6
off
on
and IL22 .

To explain each operation mode, Figure 3 depicts the ideal waveforms in the main part of thesecondary side circuit in steady-state operation, whereas Figure 4 presents the equivalent circuit andcurrent flow of each operation mode in the secondary side circuit. From the top, Figure 3 shows thetransformer secondary side voltage Vtxs, the switching states of S5 and S6, the inductor currents on
the current doubler side IL11 and IL12, and the inductor currents on the step-down chopper side IL21 and
IL22.

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4 of 20
4 of 201
1

2
2

Operation modes
Operation modes

3
3

d1 T
d1 T

4 5
T 4 5
T
(1-d1)T(1-d1)T

6
6

d1 T
d1 T

Vtxs
Vtxs
d2 T
d2 T

(1-d2)T(1-d2)T

S5
S5
dT
d22T
S6
S6
IIL12
L12
IIL11
L11

IIL22
L22
IIL21
L21

Figure3.
Ideal
waveformsof eacheach operation
operation mode.
mode.
Figure3.
3. Ideal
Ideal waveforms
waveforms of
Figure
mode.

L11
L11

VVtxstxs
S5
S5

S6
S6

L12
L12
L21
L21

Vtxs
S5
S5

S6

L22
L22
D1
D1

D2
D2

Vtxs
Vtxs
S5
S5

S6
S6

D1
D1

D2
D2

L11
L11

L11
L12
L21

VVtxs
txs
S5
S5

S6
S6

D1
D1

D2

L21
L21
L22
L22

L22
D1
D1

L12
L12

D2
D2

(a)
(a)

(b)
(b)

(c)
(c)

L11
L11
L12
L12

L11
L11
L12
L12

L11
L11
L12
L12

L21
L21
L22
L22

(d)

Vtxs
Vtxs
S5
S5

S6
S6

D1
D1

D2
D2

L21
L21
L22
L22

(e)
(e)

Vtxs
Vtxs
S5
S5

S6
S6

D1
D1

D2
D2

L21
L21
L22
L22

(f)

(f) (a) Mode 1;(d)Figure4.4.Equivalent
Equivalentcircuitand
andcurrent
currentflow
flowofofeacheachoperation
operation mode
mode inin secondary
secondary circuit:
circuit:Figurecircuit
1; Mode(b) Mode
2; Mode(c) Mode3; (d)Mode4; (e)Mode5; (f)Mode(b)2; (c)
3; (d)Mode4; (e)Mode5; (f)
Mode
6. 6.
Figure 4. Equivalent circuit and current flow of each operation mode in secondary circuit: (a) Mode
1;The(b)operation
Mode 2; (c)ofMode
3; (d) Modeside4; (e)circuit
Mode in
5;
Mode
6. is
The
the
each
mode
operationofthesecondary
secondaryside
circuit
in(f)
each
mode
is described below.
 1:Mode
Vtxs is positive
S5(Figureis off (Figure•
Mode
Vtxs is1:positive
and S5andis off4a). 4a).
The
side andcircuiteach mode is described below.
L11operationis chargedofbythe
Vtxssecondary
and L12, L21,
L22indischarge.
L11 is charged
by V
andL12, L21,and
andS5
discharge.
 Mode
1:
VVtxs
is on
off
(Figure 4b).
4a).
Mode
2:txs
txs isis positive
positive
and
S5L22
is
(FigureL11
ischarged
by
V
txs
and
L12,
L21,
and
L22
discharge.
As S5 is turned on, both L11 and L21 are charged by Vtxs, whereas L12 and L22 still discharge.
 ModeMode 2:
3: VVtxs
txs isis positive
0 (Figureand4c).S5 is on (Figure 4b).

World Electric Vehicle Journal 2020, 11, 78•

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Mode 2: Vtxs is positive and S5 is on (Figure 4b).

As S5 is turned on, both L11 and L21 are charged by Vtxs , whereas L12 and L22 still discharge.
•

Mode 3: Vtxs is 0 (Figure 4c).

When Vtxs is 0, there is no power, and therefore, L11, L12, L21, and L22 all discharge.
•

Mode 4: Vtxs is negative and S6 is off (Figure 4d).

L12 is charged by Vtxs and L11, L21, and L22 discharge.
•

Mode 5: Vtxs is negative and S6 is on (Figure 4e).

As S6 is turned on, L12 as well as L22 are charged. L11 and L21 still discharge.
•

Mode 6: Vtxs is 0 (Figure 4f).

As in Mode 3, as Vtxs is 0, L11, L12, L21, and L22 discharge.
Table 2 displays the output voltages of the proposed circuit in the steady-state operation Vout1 andVout2 ; the output currents Iout1 and Iout2 ; the output average inductor currents IL11 , IL12 , IL21 , and IL22 ;the inductor current ripple factors γL11 , γL12 , γL21 , and γL22 ; and the capacitor ripple currents ∆ic1 and∆ic2 . In this case, d1 and d2 in the equations are duty ratios for the period in which Vtxs is positive or
negative and for the period of Mode 2 or Mode 5, respectively, as illustrated in Figure 3. L1 and L2 are theinductance values of L11 or L12 and L21 or L22, respectively. R1 and R2 are the load resistance values of
the current doubler and step-down chopper outputs, respectively. Moreover, T is the time of one cycle.
Table 2. Theoretical formulas of proposed circuit.
SymbolV out1
Iout1

Value
d1 N2 Vin
N1
d1 N2 Vin
N1 R1

SymbolV out2
Iout2

Value
d2 N2 Vin
N1
d2 N2 Vin
N1 R 2

IL11
IL12

d1 N2 Vin
2N1 R1

IL21
IL22

d2 N2 Vin
2N1 R2γL11γL12

2R1 (1 − d1 )T
L1

γL21
γL22

2R2 (1 − d2 )T
L2

∆ic1

R1 (1 − d1 )TIout1
L1

∆ic2

R2 (1 − d2 )TIout2
L2

As indicated in Table 2, when Vin is constant, Vout1 and Vout2 are only dependent on the duty ratio
corresponding to each of these. That is, the switching of S1 to S4 controls V out1 , and that of S5 and S6controls Vout2 . This means that V out1 and V out2 can be controlled independently; however, this is only
possible when the circuit operates with the six operation modes described above. This means that thefollowing condition must be satisfied:
d1 > d2 .
(1)
If Equation (1) is not true (d1 5 d2 ), S5 and S6 are always on, while the transformer is transmitting
power from the primary side to the secondary side (when Vtxs is positive or negative). Consequently,
there will be no means of controlling V out2 and the dual-output converter cannot perform its function.
3. Actual Device Testing
3.1. Main Circuit Configuration
Table 3 summarizes the specifications of the experimental circuit that was constructed to operate
the proposed circuit at 400 kHz and 2 kW, the configuration and appearance of which are presented

short switching transition time was used for S1 to S6 considering the switching loss at 400 kHz. A SiC
Schottky barrier diode FFSH4065A (ON Semiconductor) with an extremely short reverse recovery
time was used for D1 and D2. Owing to the large current value in the secondary side circuit, S5, S6,
WorldElectricconnected
Vehicle Journal 2020,11, 786 of 19 voltage
D1, and D2
were
in parallel
and a snubber circuit was provided in light of the surge
in the off state. The transformer turns ratio was set to 4:2. The inductance values on the current
doubler sides
L11 5andwere set toThe
15 μH,
those
the input
step-down
chopperside
in Figures
andL126, respectively.
inputwhereas
voltage was300on
V, thecapacitor
was a 330
µFL21 and
electrolytic
capacitor,
therelationshipoutput voltageamongon the current
doublerside Vamplitude,theL22 werealuminum
set to 3 μH,
consideringthethe ripple
current
wire
diameter,out1 was 48 V, andvoltageon the capacitor
step-down chopperside V out2 doubler
was 12 V. side
The switching
and coreoutput
size. The
outputon the current
C1 wasfrequency
set to 44was
μF400
bykHz,
connecting
as described previously. For the FPGA to generate control signals, XC7K70T-1FBG484C (Xilinx) with a
two 22 μF ceramic capacitors in parallel, whereas that on the step-down chopper side C2 was set toclock cycle of 5 ns (200 MHz frequency) was used to obtain a sufficient time resolution for switching at
188 μF by400connecting
four 47 μF ceramic capacitors in parallel. Because the experimental circuit was
kHz (2.5 µs per cycle) to be obtained. A SiC MOSFET SCT3030AL (ROHM) with a short switching
constructedwith time
the aimof operating
400 kHz theand2 kW, thedevices
as well astransition
was used
for S1 to S6at
consideringswitchingloss selected
at 400 kHz.switching
A SiC Schottky
barrier
diode transformers
FFSH4065A (ONand
Semiconductor)
extremely
short reverse
recoverytime
was used forvoltage,
the designed
inductors withhad anplentyof roomin termsof thebreakdown
D1
and
D2.
Owing
to
the
large
current
value
in
the
secondaryside
circuit,
S5,
S6,
D1,
and
D2 werecurrent capacity, and saturation magnetic flux density.
connected in parallel and a snubber circuit was provided in light of the surge voltage in the off state.
The transformer turns ratio was set to 4:2. The inductance values on the current doubler sides L11
Table 3. Parameters of experimental circuit.
and L12 were set to 15 µH, whereas those on the step-down chopper side L21 and L22 were set to
3 µH, considering theParameter
relationship among the ripple current amplitude,
wire diameter, and core size.
Value
The output capacitor on the current doubler side C1 was set to 44 µF by connecting two 22 µF ceramic
Vin that on the step-down chopper side C2300
capacitors in parallel, whereas
wasV
set to 188 µF by connecting
four 47 µF ceramic capacitors
Cinin parallel. Because the experimental circuit
330 wasμF constructed with the aimof operating at 400 kHz and 2 kW, the selected switching devices as well as the designed transformers
Vout1side)of the breakdown voltage, 48
V capacity, and saturationand inductors
had(current
plenty of doubler
room in terms
current
magnetic flux
Vout2density.
(step-down chopper side)
12 V
Table 3. Parameters of experimental
Switching frequency
400circuit.
kHz (T = 2.5 μs)

FPGAParameter

XC7K70T-1FBG484C(Xilinx)
Value

Clock frequencyVinof FPGA

Cin
(current
doublerout1S3,
S1, VS2,
S4, S5,S6 side)V out2 (step-down chopper side)
Switching
D1, D2 frequency
FPGA
Transformer
turns ofratio
Clock frequency
FPGA
S1, S2, S3, S4, S5, S6
L11 andD1,
L12
D2
Transformer turns ratio
L21 and
L22
L11 and L12
L21 and L22
C1
C1
C2 C2

S1

300
V MHz
200
330 µF
48 V
SCT3030AL(ROHM)
12 V
400 kHz (T= 2.5Semiconductor)µs)
FFSH4065A(ON
XC7K70T-1FBG484C (Xilinx)
1:N2 = 4:2
200NMHz
SCT3030AL (ROHM)
15 μH
FFSH4065A (ON Semiconductor)
N1 :N2 = 4:2
5 μH
15 µH
5 µH
44 μF
44 µF
188 188
µF μF

S3

L11

Vtxp Vtxs

Iout1

Vin Cin
S5

S2

S6

L12
C1
L21

S4

Vfb1

Vout1

Iout2

L22

C2
D1

Vfb2

D2

Figure5. Configurationofof experimental
experimental testtest
circuit.
Figure5. Configuration
circuit.

Vout2

World Electric Vehicle Journal 2020, 11, 78
World Electric Vehicle Journal 2020, 11, x
World Electric Vehicle Journal 2020, 11, x

7 of 19
7 of 20
7 of 20

L11
L11Control circuitControl circuit

S5×2
S5×2
Transformer
Transformer

L12
L12

Cin
Cin

H-bridge
H-bridge
inverterinverter

L21
L21
L22
L22

FPGA board
FPGA board

D1×2
D1×2

C1
C1

S6×2
S6×2

D2×2
D2×2

C2
C2

12 V source for control circuit
12 V source for control circuit

(a)
(a)

(b)
(b)

Figure 6.
6. Experimental
circuitsetup:(a)(a)main
circuitwithcontrol
circuit;(b) maincircuit
without
FigureExperimentalcircuit
circuitsetup:
setup:(a)maincircuitwithcontrol
circuit;main
circuit
without
Figure
6. Experimental
main
circuitwithcontrol
circuit;(b)(b)
main
circuit
without
control
circuit.
control
circuit.
control circuit.

3.2. Control Circuit Configuration
3.2. Control Circuit Configuration
Figurecircuit.
Allswitchingsignals
forforS1 S1
toFigure 77 depicts
depictsthe
thecontrol
controlblock
blockdiagram
diagramofofthe
theproposed
proposedcircuit.
Allswitchingsignals
Figure 7 depicts the control block diagram of the proposed circuit. All switching signals for S1
S6
were
generated
by
the
FPGA
(Appendix
A),
providedwithappropriate
dead
time,
and
subsequently
to S6 were generated by the FPGA, provided with appropriate dead time, and subsequently input toto S6 were generated by the FPGA, provided with appropriate dead time, and subsequently input toinput
to eachvia the isolated
gate driver.
each gate
via gate
the isolated
gate driver.
each gate via the isolated gate driver.
FPGA
FPGA

400 kHz400 kHzPI
Vout2* +Vout2* + -- PI
Vfb2
Vfb2

-

Phase
Phase
shifter
shifter-++

Isoratedgate
drivers
Isoratedgate
drivers

400 kHz400 kHz
PI
+
PI
+-

Dead
time
Dead
time

Vfb1
Vfb1

Vout1* Vout1* - ++

S1
S1
S2
S2
S3
S3
S4
S4

S5
S5
S6
S6

800 kHz800 kHz

Figure 7.
7. Control
block
diagram ofof proposed
proposed circuit.
circuit.
FigureControl block
block diagram
diagramFigure7. Control
of proposed
circuit.

squarewave
wavewith
withaaduty
dutyratio
ratioofof0.50.5
anda frequencyof 400kHz
input
to gatethe gate
S1
A squareanda frequencyof 400kHz
waswasinput
to theof S1ofand
A square wave with a duty ratio of 0.5 and a frequency of 400 kHz was input to the gate of S1
andinverted
its inverted
was input
theofgateofphase-shifted
S2. A phase-shiftedsignalthe signal
S1 gatewas
signalwas
its
signalsignal
was input
to the to
gate
S2. A
signal of
the S1ofgate
inputtoand its inverted signal was input to the gate of S2. A phase-shifted signal of the S1 gate signal was
input
to of
theS3
gate
S3inverted
and its inverted
signalgateofsignalof S4.
Thisshift
phase
shift
was quantified
thegate
andofits
signal was
the wasgatethesignal
S4. Thisphase
wasquantified
by theinput to the gate of S3 and its inverted signal was the gate signal of S4. This phase shift was quantified
by the feedbackof the voltage
output on
voltageon thedoubler
current side
doubler
Vout1. In particular,
the deviation
feedbackof the output
the current
V out1side. In particular,
the deviation
betweenby the feedback of the output voltage on the current doubler
side Vout1. In particular, the deviation
betweenthevoltage
dividedofvoltage
of Vout1, denoted
fb1, andthe voltage
command
Vout1input* was toinput
thedividedV out1 , denotedby Vfb1 , byandVthevoltagecommandvalue Vvalue
theout1 * was
between the divided voltage
of Vout1, denotedby Vfb1, and the voltage command value
Vout1* was input
to calculation
the PI calculation
unit. Subsequently,
the ofoutputthe PI calculation
was compared
thePI
unit. Subsequently,
the output
the PIofcalculation
unit wasunit
comparedwith the with
400 kHzto the PI calculation unit. Subsequently, the output of the PI calculation unit was compared with the400
kHzsawtoothwave
synchronized
with
the
S1
gate
signal.
The
time
corresponding
to
the
pulse
sawtooth wave synchronized with the S1 gate signal. The time corresponding to the pulse width of the
400 kHz sawtooth wave synchronized with the S1 gate signal. The time corresponding to the pulse
width of theresultcomparison
was thequantity.
phase-shift quantity.
comparison
was theresult
phase-shiftwidth of the comparison result was the phase-shift quantity.
were
derivedfromthethefeedbackof thevoltageon the
The gategate signals
signalsofofS5
S5and
andS6S6
were
derivedfromfeedbackof output
the output
voltageonstepthe
The gate signals of S5 and S6 were derived from the feedback of the output voltage on the stepdown chopperside.side.
Similarto theprocessfor forthethegate
signalsof of
S3S3andstep-down
chopper
Similarto theprocessgate
signals
andS4,
S4,thethefirst
first step
step was todown chopper side. Similar to the process for the gate signals of S3 and S4, the first step was todifference between
between thethe divided
divided voltage
voltage of the output voltage on the step-down chopper
calculate the difference
calculate the difference between the divided voltage of the output voltage on the step-down chopperside V
Vout2
out2, ,denotedside
denoted byby V
Vfb2, ,and
andthethevoltage
voltage command
command value Vout2
Thereafter, thethe PI-calculated
PI-calculated signal
out2*.*.Thereafter,side Vout2, denoted by Vfb2fb2, and the voltage command value Vout2*. Thereafter, the PI-calculated signal
was compared
compared with
with thethe 800
800 kHzkHz sawtooth
sawtooth wave synchronized with the S1 gateof this difference wasof this difference was compared with the 800 kHz sawtooth wave synchronized with the S1 gate
signal. In this case, by setting the frequency
frequency of the sawtooth
sawtooth wave
wave toto twice
twice thethe switchingswitching frequency,
frequency,
signal. In this case, by setting the frequency of the sawtooth wave to twice the switching frequency,
the pulse
pulsesignal
signalafter
after
comparison
simultaneously
generatedtheinterleaved
S5
and
S6
switchingcomparison simultaneously generated the interleaved S5 and S6 switching
signals.
the pulse signal after comparison simultaneously generated the interleaved S5 and S6 switching
signals. Subsequently,
the inverted
AND (NAND)
of thispulse
and the inverter
H-bridge
inverter
Subsequently,
the inverted
AND (NAND)
of this pulse
signalandsignal
the H-bridge
switchingsignals. Subsequently, the inverted AND (NAND) of this pulse signal and the H-bridge inverter
switching signal was created to enable the assigned switching of S5 when Vtxs was positive and thatswitching signal was created to enable the assigned switching of S5 when Vtxs was positive and thatof S6 when Vtxs was negative, as demonstrated in Table 1 and Figure 3. For the modes in Table 1, inof S6 when Vtxs was negative, as demonstrated in Table 1 and Figure 3. For the modes in Table 1, inWorld Electric Vehicle Journal 2020, 11, 78

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World
Journal2020, 11,x assigned switching of S5 when V
signalElectric
was Vehicle
createdto enable
the

8 of 20

txs was positive and that of S6 whenVtxs was negative, as demonstrated in Table 1 and Figure 3. For the modes in Table 1, in which thewhich the switching states of S5 and S6 were irrelevant, S5 and S6 were turned on to prevent loss
switching states of S5 and S6 were irrelevant, S5 and S6 were turned on to prevent loss owing to aowing to a current flow to the body diode.
current flow to the body diode.

3.3.
3.3. Operation
Operation Points
PointsFigurepresents
measuredoperationand4 displays
Table 4thedisplaysthe measurement
Figure 88presents
thethemeasuredoperation
pointspoints
and Tablemeasurement
instruments.
instruments.
There
were
five
operation
pointsfortheoutputpower
onthecurrent
side P200
out1
There were five operation points for the output power on the current doubler side Pdoubler
betweenout1
betweenand 1400
W using an
inductiveof were8 Ω. There
were fourpoints
operation
pointsforand 1400200
W usingan inductive
resistanceofresistance
8 Ω. Therefour operation
for theoutputtheoutputpower
onthestep-down
choppersidePout2 between 150 and 500 W using a non-inductive
power on the step-down chopper side Pout2 between 150 and 500 W using a non-inductive resistance ofresistanceΩ. These points
20 operation
in total were
#01 to #20.operation
An additional
1 Ω. Theseof201operation
in totalpoints
were numberedfromnumbered#01 to #20.from
An additional
point
operation
point
#21
was
set
for
an
output
of
2
kW,
with
outputpower
onthecurrent
doublersideof#21 was set for an output of 2 kW, with output power on the current doubler side of 1421 W and output
1421
W
and
outputpower
onthestep-down
chopper
side
of
588
W.
Based
on
these
operation
points,power on the step-down chopper side of 588 W. Based on these operation points, the measurements
themeasurements
performed
as following,
described inwhere
the following,
where
the numbers
shown
Figurewere
performed aswere
described
in thethe numbers
shown
in Figure
8 areinused
to
8indicateare usedtoindicatetheoperation
points.
the operation points.
700

#21

600

#16

#17

#18

#19

#20

#11

#12

#13

#14

#15

300

#06

#07

#08

#09

#10

200

#01

#02

#03

#04

#05

Pout2 (W)

500
400

100
0
0

200

400

600

800

1000

1200

1400

1600

Pout1 (W)
FigureFigure 8. Measured
Measured operation
operation points.
points.
Table 4. Measurement instruments.
Table 4. Measurement instruments.
Instrument

Instrument

Oscilloscope
Oscilloscope
Voltagedifferential probe
Current
probe (<30A)
Voltage differential
probe
Current probe (>30 A)
Current(<30 A)
Deskewprobe
calibration
sourceCurrent probe (>30 A)
3.4. Voltage Target Value
Response
Characteristics
Deskew
calibration
sourceModel Number

Model Number

HDO6104A-MS (TELEDYNE)HDO6104A-MS(TELEDYNE)
700924 (YOKOGAWA)
TCP312A(Tektronix)
700924 (YOKOGAWA)
TCP303 (Tektronix)
TCP312A(Tektronix)
DCS025(TELEDYNE)

TCP303 (Tektronix)
DCS025 (TELEDYNE)

Figure 9 displays the output voltages V out1 and V out2 , and the output currents Iout1 and Iout2 from
3.4.
Voltage
Value state
Response
Characteristics
power-on toTarget
the steadyat operation
point #21 with a total output power of 2058 W. As indicatedin Figure
9,
both
the
voltageandcurrent
took
less
than
from
power-onto settling,
Figure 9 displays the output voltages Vout1
and
Vout21,sandtheoutput currents
Iout1demonstrating
and Iout2 fromtheabilitytocontroltwodifferent
voltagesatanoutputof
2
kW.
The
settledvoltagevalueswere
48.9 Vpower-on to the steady state at operation point #21 with a total output power of 2058 W. As
indicated
forFigure
V out1 and12.4theV for
V out2 . and
Thesewere shifted
from
their
valuestoofsettling,
48 and 12
V, which wasin9, bothvoltagecurrent
took lessthan
1 s commandfrom power-on
demonstrating
caused
by
an
error
in
the
voltagedividing
resistanceratio.
Inthesteadystate,
theripplevoltagewasthe ability to control two different voltages at an output of 2 kW. The settled voltage values
were 48.9±1.3
forandboth12.4
V out1
andVV, whereas
ripplecurrent±0.8 Avalues
for Iout1±1.6
Iout2 .
out2
V
for V
Vout1
V for
out2
. Thesewere theshiftedfromtheir wascommandof and48 and12AV,forwhich
The
reasonforthelargervalue
oftheripplecurrent
I
compared
to
I
is
that
TCP303(Tektronix),
out2
out1
was caused by an error in the voltage dividing resistance ratio. In the steady state, the ripple voltage
which
was
to measure, has
a lowerthe
resolution
than TCP312A
which
used
to.
was
±1.3
V usedfor both
Vout1 andIout2
Vout2, whereas
ripple current
was ±0.8(Tektronix),
A for Iout1 and±1.6wasA for
Iout2
measureIout1. the larger value of the ripple current Iout2 compared to Iout1 is that TCP303 (Tektronix),Thereasonforwhich was used to measure Iout2, has a lower resolution than TCP312A (Tektronix), which was used
to measure Iout1.

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9 of 20

60
50
40
30
20
10
0
60
50
40
30
20
10
0
0.0

Vout1
Vout2

Iout1
Iout2

0.2

0.4

0.6

0.8

1.0

Time (s)Figure9. Dual-port output
waveforms.
Figure9. Dual-port
outputwaveforms.

In this experiment, the DC power supply was powered on after starting the control, and in thisIn this manner,experiment,
DCthepower
was powered
on afterstarting
the control,
the time theto settle
voltagesupply
was constrainedby the rise timeof the DC
power supply.
That is, and in this
proportional
gain
andtime constant
the PI control unit,
which
were
control
were notmanner, thethetime
to settle
thevoltagewasofconstrainedby therise
timeof parameters,
the DC power
supply. That
involved in the behavior during power-on. These control parameters were optimized for the load
is, the proportional gain and time constant of the PI control unit, which were control parameters,
disturbance response, as described later. If this circuit is used as on-board auxiliary power, the control
were not involvedin thebehavior
during
These control
parameters
werestate
optimized forwill start withthe battery
voltageappliedpower-on.
to the input. Accordingly,
the time
to reach a steadythe load disturbance
response,
as todescribed
If thiscircuitis usedas on-board
auxiliary
power,
will be shortenedcomparedthat in thislater.
experiment,
andthe current
and voltage
overshoots
are
to be
larger.
prevent this,countermeasures
soft-start
are necessary, which
we to reach a
the control expected
will startwith
theTobattery
voltageapplied tosuch
theasinput.
Accordingly,
the time
consider as future tasks.
steady state will be shortened compared to that in this experiment, and the current and voltage
Waveforms
overshoots 3.5.
areOperating
expected
to be larger. To prevent this, countermeasures such as soft-start are necessary,
Figureas10future
presentstasks.
the waveforms at four operation points during the steady-state operation:
which we consider
Vtxp , Vtxs , Itxp , Itxs , Vgs5 , Vgs6 , Vds5 , Vds6 , Vdiode1 , Vdiode2 , IL11 , IL12 , IL21 , and IL22 . Vtxp is the transformer
primary side voltage, Itxp and Itxs are the transformer primary and secondary side currents, Vgs5 and3.5. Operating
Waveforms
Vgs6 are the gate-source voltages of S5 and S6, Vds5 and Vds6 are the drain-source voltages of S5 and S6,
Vdiode1 and the
Vdiode2
are the voltages
acrossoperation
D1 and D2, respectively.
In oursetup,
the oscilloscope
Figureand10 presents
waveforms
at fourpoints during
thesteady-state
operation: Vtxp,
had four channels and could not measure all waveforms simultaneously. Therefore, one channel was
Vtxs, Itxp, Itxs, usedVgs5,toVmeasuregs6, Vds5, Vds6, Vdiode1, Vdiode2, IL11, IL12, IL21, and IL22. Vtxp is the transformer primary side
the Itxp waveform constantly as the trigger channel to synchronize the results ofvoltage, Itxp multiple
and Itxsmeasurements.
are the transformer
primary
andsecondarycurrents,
gs5 andgs6 are the gateThe measurements
wereperformed
at fourside
operation
points: V#01,
whereVboth
Pout1 and
wereS6,minimized;#05,Vwhereonly
was maximized
based on of#01;S5#16,
whereout2andsource voltagesof PS5
Vds5 andds6 arethePout1
drain-source
voltagesandS6,onlyand Vdiode1 andPout2 was maximized in the same manner; and #20, where both Pout1 and Pout2 were maximized. As can
Vdiode2 are thebevoltages
across D1 and D2, respectively. In our setup, the oscilloscope had four channels
observed from Figure 10, the operation proceeded at 2.5 µs (400 kHz) per cycle at all four operationand could notmeasurewaveforms
simultaneously.
Therefore,
was results
used to measure
pointsand there all
were
indeed six operation
modes, as describedin Table one
1 andchannel
Figure 3. These
confirm thatconstantly
the proposed circuit
behavedas designed.
Meanwhile,surges and associatedringingof multiple
the Itxp waveformas thetriggerchannelto synchronize
the resultsappeared in the secondary side circuit voltage at all operation points. The ringing frequencies were
measurements. The measurements were performed at four operation points: #01, where both Pout1 andapproximately 15 and 60 MHz, and these were considered as resonances owing to the transformer
Pout2 were minimized;#05,andwhere
only P
out1 was maximized#16, where
only Pout2 wasleakage inductancethe parasitic
capacitanceof S5 and S6 andbased
D1 andonD2,#01;
respectively.
Noise wasat thesefrequencies
Vgs6 , indicating
noisemaximized.
propagated in As can be
maximized also
in observed
the samemanner;andin V#20,
whereboth Pthat
out1 high-frequency
and Pout2 were
gs5 andtheentiresecondaryside
circuit.
observed from Figure 10, the operation proceeded at 2.5 μs (400 kHz) per cycle at all four operation

points and there were indeed six operation modes, as described in Table 1 and Figure 3. These results
confirm that the proposed circuit behaved as designed. Meanwhile, surges and associated ringing
appeared in the secondary side circuit voltage at all operation points. The ringing frequencies wereapproximately 15 and 60 MHz, and these were considered as resonances owing to the transformer
leakage inductance and the parasitic capacitance of S5 and S6 and D1 and D2, respectively. Noise wasalso observed at these frequencies in Vgs5 and Vgs6, indicating that high-frequency noise propagated inWorld Electric Vehicle Journal 2020, 11, 78

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World Electric Vehicle Journal 2020, 11, x

10 of 20

Vtxp300
Vtxs150

Vtxp 300
Vtxs 150

-150

-150

Vtxp, Vtxs (V)

-300

-300

-300

-300

50

50

50

50
Itxp
Itxs 25

Itxp
Itxs 25

0

-50

-50

20

20

20

10

Vgs5
15
Vgs6
10

Vgs5
15
Vgs6
10

5

5

5

Vgs5 (V)

0

0

-50
20
Vgs5
Vgs6

10
5

0

0

-5

-5

-5

-5

300
250
200
150
100
50
0

Vds5300
Vds6250

Vds5 300
Vds6 250
200
150
100
50
0

Vds5 300
Vds6 250

Vdiode1300
Vdiode2
250
200
150
100
50
0

Vdiode1300
Vdiode2 250

Vdiode1300
Vdiode2 250

200
150
100
50
0

200
150
100
50
0

IL11 20
IL12 15

20

15
10

10

0

1

2

3

Vds5, Vds6 (V)Vdiode1, Vdiode2 (V)Vdiode1, Vdiode2 (V)10

10IL1, IL2 (A)20
IL11IL12 15

5

1

2

3

IL11
IL12

5

IL3, IL4 (A)

0
35
30
25
IL21 20
IL22 15
10
5
0
0
4
5

Vdiode1
Vdiode2

0
35
30
25
20
IL21 15
IL22 10504
50IL3, IL4 (A)IL1, IL2 (A)

0
35
30
25
IL21 20
IL22 15
10
5
0
4
5 0

200
150
100
50
0

15

IL11
IL12

5

IL3, IL4 (A)

0
35
30
25
20
15
10
5
0

IL1, IL2 (A)Vdiode1, Vdiode2 (V)Vdiode1, Vdiode2 (V)

5

Vds5
Vds6

Vds5, Vds6 (V)

0

20

Vgs5
Vgs6

15

0

200
150
100
50
0

Itxp
Itxs

-25

-25

Vds5, Vds6 (V)Vgs5 (V)Vds5, Vds6 (V)

0

-50

300
250
200
150
100
50
0

IL1, IL2 (A)Itxp
Itxs 25

-25

Vtxp
Vtxs

-150

Itxp, Itxs (V)

0
-25

0

Itxp, Itxs (V)25

15

IL3, IL4 (A)0

Vgs5 (V)0Itxp, Itxs (V)Itxp, Itxs (V)150

Vgs5 (V)Vtxp, Vtxs (V)-150

Vtxp, Vtxs (V)Vtxp 300
Vtxs 150

Vtxp, Vtxs (V)

300

1

2

3

IL21
IL22
2

1

3

Time (μs)

Time (μs)

Time (μs)

Time (μs)

(a)

(b)

(c)

(d)

4

5

Figure10.
10.Waveforms
Waveformsof
ofproposed
proposedcircuit:
circuit:(a)(a)#01;#01;(b)(b)#05;#05;(c)(c)#16;#16;(d)(d)#20.
#20.
Figure3.6. Detailed Operation Modes
3.6. Detailed Operation Modes
To explain the detailed steady-state operation, Figure 11 presents the waveforms of V , Vtxs , Itxp ,To explain the detailed steady-state operation, Figure 11 presents the waveforms of Vtxp
txp, Vtxs, Itxp,
Itxs , Vgs5 , Vgs6 , Vds5 , Vds6 , Vdiode1 , and Vdiode2 for a half period at three operation points, namely #01, #05,
Itxs, Vgs5, Vgs6, Vds5, Vds6, Vdiode1, and Vdiode2 for a half period at three operation points, namely #01, #05, andand #16, in an enlarged view. This half period corresponded to the ideal operation modes 1, 2, and 3,#16, in an enlarged view. This half period corresponded to the ideal operation modes 1, 2, and 3, as
as previously described in Table 1, Figures 3 and 4. Although the behavior varied slightly depending
previously described in Table 1, Figures 3 and 4. Although the behavior varied slightly dependingon the operation point, there were nine modes for the measured waveforms in total, which are divided
on the operation point, there were nine modes for the measured waveforms in total, which are
by tn (n = 1 to 11) in Figure 11. In addition to the ideal operation modes 1, 2, and 3, six additional
dividedby tn (n = 1 to 11) in Figure 11. In addition to the ideal operation modes 1, 2, and 3, sixmodes for state transitions were present. Table 5 displays the possible detailed operation modes for
additional modes for state transitions were present. Table 5 displays the possible detailed operationeach operation point, and Figure 12 depicts the current path of the secondary side circuit in eachmodes for each operation point, and Figure 12 depicts the current path of the secondary side circuit
operation mode. The operation in each mode is described below based on Figures 11 and 12.
in each operation mode. The operation in each mode is described below based on Figures 11 and 12.

World Electric Vehicle Journal 2020, 11, 78

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World Electric Vehicle Journal 2020, 11, x
t1 t2=t3 t4 t5

t6 t7 t8 t9 t10

11 of 20t11

t1 t2 t3 t4 t5

Vtxp
Vtxs

-150

Vtxp
Vtxs

-300

0

-300

50

50

25

25

25

Itxp
Itxs

-25

Itxp, Itxs (V)

50

0

0
Itxp
Itxs

-25

0

-50

20

20

15

15

5

15

10

0

5
0

0.6

1.2

Vds5, Vds6 (V)Vdiode1
Vdiode2
0.0

0.3

0.6

Vds5
Vds6

300
250
200
150
100
50
0
1.5 0.0

Vdiode1, Vdiode2 (V)Vds5, Vds6 (V)

0.9

0

300
250
200
150
100
50
0

Vds5
Vds6

Vdiode1, Vdiode2 (V)Vdiode1
Vdiode2
0.3

300
250
200
150
100
50
0
1.5

5
-5

300
250
200
150
100
50
0

Vds5
Vds6

Vgs5
Vgs6

10

Vgs5
Vgs6

-5

300
250
200
150
100
50
0
300
250
200
150
100
50
0
0.0

Vgs5, Vgs6 (V)

-50

20
Vgs5
Vgs6

Itxp
Itxs

-25

-50

10

Vtxp
Vtxs

-150

Vgs5, Vgs6 (V)Itxp, Itxs (V)Vds5, Vds6 (V)

150

0

-150

-5

Vdiode1, Vdiode2 (V)Vtxp, Vtxs (V)0t6 t7 t8 t9 t10 t11

t1 t2 t3 t5
300

150

-300

Vgs5, Vgs6 (V)Vtxp, Vtxs (V)

300

150

Itxp, Itxs (V)Vtxp, Vtxs (V)300

t6 t7 t8 t9 t10 t11

0.9

1.2

Vdiode1
Vdiode2
0.3

0.9

0.6

Time (μs)

Time (μs)

Time (μs)

(a)

(b)

(c)

1.2

1.5

Figureproposed circuit
circuitfor
forhalf
halfperiod:
period:(a)(a)#01;
#01;
#05;
#16.
Figure11.
11. Waveforms of proposed(b)(b)#05;(c)(c)#16.
Table 5. Detailed operation modes.
Table 5. Detailed operation modes.
Operation
Operation Point
Point
#01
#01
#05
#05
#16
#16

1.

11
t1t~1 ~t
t22
○#
○#
○#

2-12-1t2 ~t2t~t
3 3○#Operation
Mode
Operation
Mode
4 5
5 6
6 7
7 8
8 9
9
t3 ~ tt53 ~t5
t5 ~ t6t5 ~tt66 ~ t7t6 ~tt77 ~ t8t7 ~tt88 ~ t9t8 ~tt99 ~ tt109 ~tt10
10 ~ tt11
10 ~t11○ # ○ #○# ○# ○# ○ # ○ # ○ #○ # ○ #○
# ○# ○ # ○ # ○ # ○ ## ○# ○# ○ # ○ # ○ #○ # ○2-22-2 3-1a3-1a3-1b3-1b3-2 3-2 4○ #(t1 < t < t2 ) Period in which Vtxp began to increase (Figure 12a).

With the switching of the primary side inverter, Vtxp started to increase. Furthermore, S5, S6, D1,
and D2 were in the on-state. The currents flowed from the source to the drain in S5 and from thedrain to the source in S6, and a negative current flowed in the transformer. Because both ends of thetransformer were connected to GND, a voltage was generated at Vtxs corresponding to L di/dt of thecurrent path, but not corresponding to Vtxp .
2.

(t2 < t < t3 ) Period in which current flowed to S5 body diode (Figure 12b,c).

Vgs5 was turned off and the current flowing to S5 was commutated to the body diode. This mode
continued until the current in the body diode became zero. Accordingly, a larger S5 current (larger
output power) meant that this mode would last longer. In the case of #01, where Vgs5 was turned off,World Electric Vehicle Journal 2020, 11, 78

12 of 19

no current flowed from the source to the drain in S5; therefore, this mode did not exist for #01. In thecases of #05 and #16, owing to the different operation points, the commutated S5 body diode current
flowed in different paths (Figure 12b,c).
L11

Vtxs

L12

S5

S6

L21

D1

D2

L22
Rout2

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(k)

(l)

Rout1

L11

S5

Vtxs

L12

S6

L21
L22

D1

(i)

Rout2

D2

(j)

Rout1

: Current flow related to Rout1: Current flow related to Rout2: Current flow related to both outputs
Figure 12. Current path of experimental circuit in each operation mode; (a) Mode 1; (b) Mode 2-1;
Figure 12. Current path of experimental circuit in each operation mode; (a) Mode 1; (b) Mode 2-1; (c)(c) Mode 2-2; (d) Mode 3-1a; (e) Mode 3-1b; (f) Mode 3-2; (g) Mode 4; (h) Mode 5; (i) Mode 6; (j) Mode 7;
Mode 2-2; (d) Mode 3-1a; (e) Mode 3-1b; (f) Mode 3-2; (g) Mode 4; (h) Mode 5; (i) Mode 6; (j) Mode(k) Mode 8; (l) Mode 9.
7; (k) Mode 8; (l) Mode 9.

Furthermore, in this mode, both ends of the transformer were connected to GND, and thus,
no voltage corresponding to Vtxp was generated at Vtxs yet. Therefore, when the duty ratio was constantfor Vtxp , when this mode was longer (the output power was larger), the duty ratio d1 for Vtxs was
smaller. Because d1 was proportional to the output voltage V out1 (Table 2), it attempted to take aconstant value when V out1 was constant. As a result, the duty ratio for Vtxp increased as the output
power increased.
3.

(t3 < t < t5 ) Charging period for S5 parasitic capacitance Cds5 (Figure 12d–f).

World Electric Vehicle Journal 2020, 11, 78

13 of 19

The S5 body diode current became zero and Vtxs started to rise. This Vtxs acted as a power source
to charge Cds5 (Figure 12d,f). This charging current was the peak current of Itxs and the current change
generated a surge voltage at Vds5 . As described later, this noise propagated to the entire secondaryside circuit, including Vgs5 and Vgs6 . A larger Pout2 resulted in a larger rate of change in the current.
Therefore, the peak surge voltage was greater for #16 than for #01 and #05. Moreover, because the L21
current (D1 current) in the previous mode was small for #01 and #05, the charging current for Cds5
flowed to not only L21, but also to D1, causing the charging (t3 < t < t4 ) and discharging (t4 < t < t5 ) of
the D1 parasitic capacitance CD1 (Figure 12d,e). This charging and discharging generated a voltage ofapproximately 70 V at Vdiode1 . However, for #16, the D1 current in the previous mode was sufficiently
large, and thus, the charging current for Cds5 did not charge CD1 (Figure 12f).
4.

(t5 < t < t6 ) Period corresponding to ideal operation mode 1 (Figure 12g).
S5 was off and D1 was on, and it operated in mode 1 of the ideal operation principle.

5.

(t6 < t < t7 ) Discharging period for Cds5 (Figure 12h).

Discharging of Cds5 was caused by turning on Vgs5 , when the current flowing to L21 started toswitch from the D1 current to the S5 current. The current continued to flow into S5 and D1 until S5 wason and completely switched; therefore, both ends of Vtxs were connected to GND again, reducing Vtxs .
6.

(t7 < t < t8 ) Charging period for CD1 (Figure 12i).

Once the discharging of Cds5 was complete and S5 was completely on, the current started to flow
to L21 via S5. At the same time, the charging of CD1 started to turn off D1. The peak for Itxs was the
charging current. The current change at this point generated a surge voltage at Vdiode1 . The periods
t6 to t8 were the time from the start of discharging Cds5 until the end of charging CD1 . The current
involved in the charging and discharging was dependent on Pout2 . Consequently, #16, with a greater
Pout2 , had a longer t6 to t8 period than #01 and #05.
7.

(t8 < t < t9 ) Period corresponding to ideal operation mode 2 (Figure 12j).
D1 was completely off and it operated in mode 2 of the ideal operation principle.

8.

(t9 < t < t10 ) Discharging period for CD1 (Figure 12k).

By switching the primary side inverter, Vtxp and Vtxs decreased simultaneously. Accordingly,
the current flowing from the transformer to L21 decreased. To compensate for this current loss, D1 wasturned on. Discharging of CD1 occurred as a preliminary step.
9.

(t10 < t < t11 ) Period corresponding to ideal operation mode 3 (Figure 12l).

D1 was completely on, and it operated in mode 3 of the ideal operation principle.
The following half cycle behaved symmetrically with the nine modes described thus far.
The behavior at each operation point during steady-state operation has been described with theseries of operation modes above.
3.7. Load Disturbance Response Characteristics
Figures 13 and 14 present the actual measurement results and simulation results of V out1 , Iout1 ,V out2 , and Iout2 when the operation point was switched during steady-state operation. Figure 15 shows
the waveforms of Vtxs , V out1 , and V out2 at operation point #08. In Figure 13, operation points #02 and#03 were switched to switch Pout1 only. In Figure 14, #03 and #08 were switched to switch Pout2 only.
PSIM version 12.04 (Powersim) was used for the simulation. The parameters in Table 3 were used in
the simulation, and an ideal device was assumed for the switching devices. Furthermore, no parasitic

3.7. Load Disturbance Response Characteristics

Iout11(A)

16

16

14

14

54
52
50
48
46
44
42
20

Vout1 (V)

54
52
50
48
46
44
42
20
18

18

16
14

12

16
14

10

10

10

10

16

16

16

16

14

14

14

14

12

12

12

Vout2 (V)12

Vout2 (V)12

Vout2 (V)

12

12

10

10

8
16

8
16

8
16

14

14

14

14

12
10

10

12

8
50

8
0

1

2
3
Time (ms)4

12

Iout2 (A)

10

8
16

Iout2 (A)10

Iout2 (A)Iout11(A)Vout2 (V)Iout11(A)18

18

Iout2 (A)Vout1 (V)

54
52
50
48
46
44
42
20

Iout11(A)

54
52
50
48
46
44
42
20

Vout1 (V)Vout1 (V)Figures 13 and 14 present the actual measurement results and simulation results of Vout1, Iout1, Vout2,
and Iout2 when the operation point was switched during steady-state operation. Figure 15 shows the
waveforms of Vtxs, Vout1, and Vout2 at operation point #08. In Figure 13, operation points #02 and #03
were
to switch
Pout111,
only.
WorldswitchedElectric Vehicle
Journal 2020,
78 In Figure 14, #03 and #08 were switched to switch Pout2 only. PSIM
14 of 19version 12.04 (Powersim) was used for the simulation. The parameters in Table 3 were used in thesimulation, and an ideal device was assumed for the switching devices. Furthermore, no parasitic
resistance,inductance,
inductance,ororcapacitancecapacitanceexisted
existedininthe
thesimulation
simulationcircuit.
circuit.Figures
Figures1313andand1414verify
verifythetheresistance,
following:(1)
when
switchingPandswitchingP,
itrecoveredtoasteadystate
within
4
ms
after
out1
out2
following: (1) when switching Pout1
and switching Pout2, it recovered to a steady state within 4 ms aftertheswitchingoftheoperation
point,
and(2)
each
waveformswitchingto tothethe switching of the operation point, and (2) each waveformfrom
fromthetheoperation
operationpoint
point
switchingrecoveredsteady
state
was
in
good
agreementwiththesimulatedwaveform.
Based
on
these
results,
the recovered steady state was in good agreement with the simulated waveform. Based on these
the load
controlcontrol
was realized
as designed.
Comparedto theto
simulation
results,
the actual
results,
thevariationload variation
was realized
as designed.
Comparedthe simulation
results,themeasurement
results
exhibitedgreatersuperimposed
noise
in
the
voltageandcurrent.
These
noisesactual measurement results exhibited greater superimposed noise in the voltage and current. These
were inaccordancewith thesurgetimingtimingof Vtxsof, asillustrated
in Figure
15. Asabove,
a Vtxsnoiseswerein accordancewiththe surge
Vtxs, as illustrated
in Figure15.indicatedAs indicatedabove,
was wasgenerated
at thetimingof S5,
S6, S6,
D1,D1,
andand
D2,D2,
therebydemonstratingthatthea surgeVtxs surge
generated
at switching
the switching
timingof S5,
therebydemonstratingthatswitchingnoisesinthesecondaryside
circuitpropagatedtotheoutputvoltage.
This
indicatesthethe switching noises in the secondary side circuit propagated to the output voltage. This indicates thenoise
propagation
via
paths
that
could
not
be
absorbedbytheoutputsmoothingcapacitors
C1
and
C2,
noise propagation via paths that could not be absorbed by the output smoothing capacitors C1 andrevealing
thethelayoutdesignissue
of thesecondaryside
circuit.
C2,
revealinglayoutdesignissue
of thesecondaryside
circuit.

10

10

12

8
1

2
3
Time (ms)

4

5

0

1

2
3
Time (ms)

8
5 0

4

1

2
3
Time (ms)

4#02→#03#03→#02#02→#03#03→#02

From 552 W to 817 W

From 817 W to 552 W

From 552 W to 817 W

From 817 W to 552 W

(a)

(b)

Figure13.
13.Results
Results
Pout1
dynamic
response
when
141(a)
W:measurement(a) measurement
results;
Figureof of
Pout1
dynamic
response
testtest
when
Pout2P=out2
141= W:
results;(b)(b)
simulation
results.
simulation results.

5World Electric Vehicle Journal 2020, 11, 78

15 of 19

World
WorldElectricElectricVehicle
VehicleJournal
Journal2020,
2020,11,
11,xx
54
54
52
52
50
50
48
48
46
46
44
44
42
42
22
22

(V)
out1(V)
VVout1

46
46
44
44
22
22

20
20

20
20

18
18

16
16

16
16

46
46
44
44
22
22

14
14
21
21

18
18
15
15

18
18
15
15

18
18
15
15

16
16

14
14
21
21
18
18

(V)
out2(V)
VVout2(V)out2(V)
VVout2

14
14
21
21

(V)
out2(V)
VVout2

18
18

16
16

14
14
21
21

12
12
99

12
12
99

50
50
48
48

(A)
out11(A)IIout11(A)
out11(A)IIout11(A)
out11(A)IIout11

18
18

18
18

50
50
48
48

(A)
out11(A)IIout11

20
20

20
20

54
54
52
52

(V)
out1(V)
VVout1(V)
out1(V)
VVout1(V)
out1(V)
VVout1

54
54
52
52

(V)
out2(V)
VVout2

54
54
52
52
50
50
48
48
46
46
44
44
42
42
22
22

15
15of
of20
20

15
15
12
12

12
12
99

99
66
24
24

20
20

20
20

20
20

20
20

12
12

12
12

(A)
out2(A)
IIout2

16
16

16
16

88
00

11

22
33
Time
Time(ms)
(ms)

88
55 00

44

11

22
33
Time
Time(ms)
(ms)

44

16
16

(A)
out2(A)
IIout2

66
24
24
(A)
out2(A)
IIout2

66
24
24

(A)
out2(A)
IIout2

66
24
24

12
12

12
12

88
00

55

16
16

11

22
33
Time
Time(ms)
(ms)

44

88
55 00

11

22
33
Time
Time(ms)
(ms)

44

55

#03→#08#03→#08#08→#03#08→#03#03→#08#03→#08#08→#03#08→#03

From
From141
141W
Wto
to272
272W
W

From
From272
272W
Wto
to141
141W
W

From
From141
141W
Wto
to272
272W
W

From
From272
272W
Wto
to141
141W
W

(a)
(a)

(b)
(b)

Figureofdynamic
responsewhen
P=out1825
W:(a) measurement
Figure14.
Results
response
test
when
PPout1(a)measurement
results;(b)out2dynamic
Figure14.
14.Results
Results of
of PP
Pout2
out2
dynamic
response
testtest
when
out1
= 825
825=W:
W:(a)measurement
results;results;(b)simulation
results.
(b)
simulation
results.
simulation
results.

(V)
out1(V)
VVout1(V)
VVtxstxs(V)

300
300
200
200
100
100
00
-100
-100
-200
-200
-300
-300
54
54
52
52
50
50
48
48
46
46
44
44
42
42

(V)
out2(V)
VVout2

16
16
14
14
12
12
10
10
88
00

11

22

33

44

55

FigureFigure15.
15.Experimental
Experimentalwaveforms
waveformsof
ofVVtxstxs, ,VVout1
out1, ,and
andVVout2
out2atat#08.
#08.
Figure 15. Experimental waveforms of Vtxs , V out1 , and V out2 at #08.

World Electric Vehicle Journal 2020, 11, 78

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The measurement results of the voltage target value response and load disturbance response
World Electric Vehicle Journal 2020, 11, x
16 of 20
characteristics verified the behavior of the proposed circuit as designed. Thus, despite certain issues,the 400 kHz,kW dual-output
DC/DC
converter
wasvaluedemonstrated.
The2measurement
resultsof the voltage
targetresponse and load disturbance response
characteristics verified the behavior of the proposed circuit as designed. Thus, despite certain issues,

4. Efficiency
and 2Loss
EvaluationDC/DC converter was demonstrated.
the 400 kHz,kW dual-output
4.1. Efficiency
Characteristics
4. Efficiency
and Loss Evaluation
The
power
Pin and output power Pout1 and Pout2 were measured using a power analyzer,
4.1. input
Efficiency
Characteristics
namely WT1800 (YOKOGAWA). The efficiency η was measured at each operation point of the test
The input power Pin and output power Pout1 and Pout2 were measured using a power analyzer,
circuit based on the following equation:
namely WT1800 (YOKOGAWA). The efficiency η was measured at each operation point of the test
circuit based on the following equation:
P
+P

η=

out2

out1

Pout1
+ Pout2 .
Pin
η=
.
Pin

(2)

(2)

The measurement results are presented in Figure 16. The efficiency increased as Pout1 increased,
The measurement results are presented in Figure 16. The efficiency increased as Pout1 increased,
whereasit decreased
as Pasincreased.
efficiency
was
81.3%
at #05,
where
Pout1 wasout2
whereasit decreased
Pout2
increased.The
The maximum
maximum efficiency
was
81.3%
at #05,
where
Pout1 wasthe maximum
and P
was
thetheminimum.
minimumefficiency
efficiency
was
65.1%
at #16,
where
Pout2 wasthe maximum
andwasminimum.The
The minimum
was
65.1%
at #16,
where
Pout2 wasout2Pout2
the maximum
and and
Pout1Pout1
wastheresultsdemonstratedemonstratesignificant
influence
the maximum
wastheminimum.
minimum. These
These results
the thesignificant
influenceof the of theloadofloss
of Ponout2 theon thereducedefficiency.
efficiency.
load loss
Pout2
reducedTotal efficiency (%)

85

#03
#08
#13

80

#02
#07
#12

75

#01
#06
#11
#16

70
65
60
0

200

#18

#04

#05

#09
#14

#10
#15

#19

#20
Pout2 ≈ 141 W#17#Pout2 ≈ 273 W
Pout2 ≈ 394 W
Pout2 ≈ 501 W

400

600

800

1000

1200

1400

1600

Pout1 (W)
Figure16.Results
Results of efficiency
Figure16.
efficiencymeasurements.
measurements.

4.2.Characteristics
Loss Characteristics
4.2. Loss
The voltage
current
thetransformer on
andsecondarysidessides
were were
measured
The voltage
andandcurrentof ofthetransformer
on thetheprimaryprimary
andsecondarymeasuredusing
thedevices
in
Table
4
for
100
μs.
Moreover,
the
power
P
txp and Ptxs of the transformer on theusing the devices in Table 4 for 100 µs. Moreover, the power Ptxp and Ptxs of the transformer on the
primary and secondary sides, respectively, were calculated based on the following equation:
primary and secondary sides, respectively, were calculated based on the following equation:
40T

𝑃=

P=

1
∑
40Tv(t)i(t)T ,
40T
1 X
0

v(t)i(t)∆T,

(3)

(3)

where P is the power, and v(t) and i(t)40T
are 0the measured voltage and current, respectively.
Furthermore, T is the time of one cycle and ∆T is the time resolution of the oscilloscope with thewherevalues
P is theandmeasured
voltageandcurrent,
respectively.
Furthermore,of power,
T = 2.5 μs
andv(t)∆Tand= 0.1i(t)ns.areThethecalculated
Ptxp andPtxs aswell
as the measured
Pin, Pout1
, and
Pout2
were
to divide
loss
Wtotalinto three ofparts:
inverter loss
Winvthe, transformer
loss
T is thetimeof usedone cycle
andthe∆Ttotalis thetime
resolution
the theoscilloscopewithvalues of T
= 2.5 µsWtx,
andsecondary
side
loss
W
sec
.
The
derivation
formula
for
each
loss
is
displayed
in
Table
6.
Owing
and ∆T = 0.1 ns. The calculated Ptxp and Ptxs as well as the measured Pin , Pout1 , and Pout2 were used tothetotalconvenienceof themeasurement
system,the timelossof theWdata, transformer
acquisition byloss
the power
analyzer
dividetothe
loss Wtotal
into
three parts:
the inverter
Wtx , andsecondaryinv
and the oscilloscope was not simultaneous but differed in each case.

side loss Wsec . The derivation formula for each loss is displayed in Table 6. Owing to the convenienceof the measurement system, the time of the data acquisition by the power analyzer and the oscilloscope
was not simultaneous but differed in each case.
The results of the loss separation are illustrated in Figure 17. The subjects of the loss separation
were operation points #01, #05, #16, and #20, which had the maximum or minimum Pout1 or Pout2 ,respectively. The left axis indicates the power loss, and the right axis is the square of the total output

World Electric Vehicle Journal 2020, 11, 78

17 of 19

World Electric Vehicle Journal 2020, 11, x

17 of 20

Tableto
6. indicate
Loss calculations.
current Iout1 + Iout2 . The right axis is provided
the conduction loss. As illustrated in Figure 17,
the total loss and those at the different
locationsincreasedin the order of #01 < #05 < #16 < #20.
Part
SymbolEquation
This trend was consistent with theTotal
squareit was demonstrated thatloss of the total
Wtotal output
Pin − current.
(Pout1 + Pout2Thus,)
the conduction loss was dominantInverter
compared
to
the
iron
loss
or
switchingloss
at the 400 kHz operation.
loss
Winv
Pin − Ptxp
Moreover, the secondary side loss
accounted
for
more
than
half
of
the
total
loss
at all operation points.
Transformer loss
Wtx
Ptxp − Ptxs
Therefore, to improve the efficiencyof theeffective
the conduction loss in theSecondarysidetestloss circuit,
Wsec it is W
total − (Winvto+ Wreducetx)
secondary side circuit.

800

Power loss (W)

700
600
500

7000
Secondary side loss
Transformer loss
Inverter loss

6000
5000

349

400
300
193

200
100
0

113
43
37
#01

237

4000
3000

128

66
90

74
107

192

#05

#16

#20

2000
1000
0

Square of total output current (A 2)

The results of the loss separation are illustrated in Figure 17. The subjects of the loss separation
were operation points #01, #05, #16, and #20, which had the maximum or minimum Pout1 or Pout2,
Table 6. Loss calculations.
respectively. The left axis indicates the power loss, and the right axis is the square of the total output
current Iout1 + Iout2. The right axis is provided to indicate the conduction loss. As illustrated in Figure
Part
Equation
Symbol17, the total loss and those at the different locations increased in the order of #01 < #05 < #16 < #20.
Total loss
This trend was consistent
with the square of theit wasdemonstrated
that
WtotalPin −Thus,(Pout1+ Pout2)
total output current.
the conduction loss
was dominantcomparedWtoinvthe iron loss or switching
Inverterloss
Pin − Ptxploss at the 400 kHz
operation. Moreover,the secondary
for more thanTransformer
loss side loss accounted
Ptxphalf− Pof
Wtx
txs the total loss at all
operation points.
Therefore,
to loss
improve the efficiency
itiseffective
to reduce theSecondaryside
Wcircuit,−(W
Wsec of the test
total
inv + Wtx )conduction loss in the secondary side circuit.

Measurement point
FigureLoss analysis
results.
Figure17.17.Lossanalysis
results.

A main reduction measure for the secondary side circuit conduction loss is the reduction in the

A mainreduction measure for the secondary side circuit conduction loss is the reduction in the
on-resistance of the switching device. For example, S5 and S6 can be replaced with a low on-resistanceon-resistanceof thedevice. For
example,S5 D1
andand
S6D2
can
with
a lowthat
on-resistancedevicethatswitching
matches the operation
conditions,whereascanbe
be replaced
replaced with
MOSFET
matchestheoperation
conditions
andperforms
synchronousrectification
control.
Another
measuredevice that matches the operation conditions, whereas D1 and D2 can be replaced with MOSFET thatto change the transformer turns ratio and to increase the step-down ratio, which enables devices
matches theis operation
conditions and performs synchronous rectification control. Another measurewith a lower breakdown voltage to be selected and results in a further reduction in the on-resistance.
is to changeHowever,
the transformer
ratio andthetostep-down
increaseratio
the will
step-down
ratio, which
devicesin this case, turns
overly increasing
lead to a reductionin the enables
upper
limit
of the outputvoltage
power ontothebe
48 selected
V side.
with a lower
breakdown
and results in a further reduction in the on-resistance.
However, in this case, overly increasing the step-down ratio will lead to a reduction in the upper limit
5. Conclusionsof the output power on the 48 V side.
In this paper, a novel dual-output isolated DC/DC converter using an integrated circuit of acurrent doubler and step-down chopper on the secondary side of the high-frequency transformer
5. Conclusions
was proposed. Although the control method becomes more complex, the proposed circuit is expectedhave a smaller
sizedual-output
and higher efficiency
comparedto theconverter
existing circuits.
Foranautomotive
use, acircuit of aIn thistopaper,
a novelisolated
DC/DC
using
integrated
maximum output power was 2 kW and switching frequency was 400 kHz, which is a higher
current doubler
and step-down chopper on the secondary side of the high-frequency transformer was
frequency compared to the existing studies. The objective of this study was to operate, evaluate, andproposed. identify
Althoughcontrolmethodbecomes
morecomplex, the proposed circuit is expectedissuesthefor theproposedcircuit withthe above
condition.

to have a smaller size and higher efficiency compared to the existing circuits. For automotive use,a maximum output power was 2 kW and switching frequency was 400 kHz, which is a higher frequency
compared to the existing studies. The objective of this study was to operate, evaluate, and identify
issues for the proposed circuit with the above condition.
As a result of the actual prototype circuit test, both the voltage target response characteristics
and load disturbance response characteristics were observed as designed, confirming the validity ofthe proposed circuit. Moreover, we identified two solutions to specific issues: (1) soft-start control at
power-on and (2) a reduction in noise propagation to the output by improving the layout.
The maximum and minimum efficiencies of this circuit were 81.3 and 61.5%, respectively. Larger
output power on the current doubler side and smaller output power on the step-down chopper side

As a result of the actual prototype circuit test, both the voltage target response characteristics
and load disturbance response characteristics were observed as designed, confirming the validity ofthe proposed circuit. Moreover, we identified two solutions to specific issues: (1) soft-start control at
power-on and (2) a reduction in noise propagation to the output by improving the layout.
World Electric
Vehicle Journal
2020,
11, 78of 19
The maximum
andminimum
efficiencies of this circuit were 81.3 and 61.5%, respectively.18
Largeroutput power on the current doubler side and smaller output power on the step-down chopper side
resulted in higher efficiency. The loss analysis demonstrated that the loss on the secondary side
resulted in higher efficiency. The loss analysis demonstrated that the loss on the secondary side
accounted for more than 50%, suggesting that it is effective to reduce the on-resistance of theaccounted for more than 50%, suggesting that it is effective to reduce the on-resistance of the switchingswitching device on the secondary side to improve the efficiency.
device on the secondary side to improve the efficiency.
Although we demonstrated the feasibility of the proposed circuit, we did not show that it can
Although we demonstrated the feasibility of the proposed circuit, we did not show that it canbe compact and highly efficient as auxiliary power for EVs, PHVs, and FCVs owing to the nature of
be compact and highly efficient as auxiliary power for EVs, PHVs, and FCVs owing to the nature
the prototype. Therefore, future tasks for improving the efficiency and downsizing include theof the prototype. Therefore, future tasks for improving the efficiency and downsizing include theoptimization of the devices, parameters (switching device, transformer turns ratio, core material, core
optimization of the devices, parameters (switching device, transformer turns ratio, core material,
shape, and inductance value), and layout.
core shape, and inductance value), and layout.
Author Contributions: Conceptualization, Y.M., T.N.; methodology, Y.M., T.N.; software, Y.M.; validation, Y.M.,
AuthorContributions:Conceptualization,
T.N.; software,draft
Y.M.;preparation,
validation, Y.M.,
T.N.; formal
analysis, Y.M.;
investigation, Y.M.,
Y.M.;T.N.;
data methodology,
curation, Y.M.;Y.M.,
writing—original
Y.M.;
T.N.;
formalanalysis,
Y.M.;
investigation,
Y.M.;
data
curation,
Y.M.;
writing—originaldraft
preparation,
writing—review and editing, Y.M., T.N.; supervision, T.N.; project administration, N.T., M.I. All authorsY.M.;
have
writing—review and editing, Y.M., T.N.; supervision, T.N.; project administration, N.T., M.I. All authors have read
read
andagreedtothepublishedversionofthemanuscript.
and agreed to the published version of the manuscript.
Funding:This
Thisresearchresearchreceived
receivedno
noexternal
externalfunding.
funding.
Funding:
ConflictsofofInterest:
Interest:The
Theauthors
authorsdeclaredeclareno
noconflict
conflictofofinterest.
interest.
Conflicts

Appendix
AppendixAA
Figure
loop
image
ofof
the
proposedcircuit.
V fb1
FigureA1
A1indicatesindicateswhole
wholefeedback
feedback
loop
image
the
proposedcircuit.
Vfb1andandVV
fb2, ,thethefeedback
feedback
fb2
0
0
voltages
outputvoltageV out1~G6 arevoltagesofofthethemainmaincircuit
circuitoutputvoltageVout1and
andVV
out2,, areareinput
inputtotoFPGA.
FPGA.G1G1′~G6′
aregenerated
generated
out2
by
to to
thethegate
drive
circuits.
Gate
signals
G1~G6
adjustedby isolated
gate drivers
andbyFPGAFPGAandandinput
input
gate
drive
circuits.
Gate
signals
G1~G6
adjustedby isolated
gate drivers
gate
Rg in thedrive
circuits
to each
gate
S1~S6
in of
theS1~S6
main circuit,respectively.
andresistances
gate resistances
Rggatein thegate
driveinput
circuits
input
to of
each
gate
in the main
circuit,
S1~S4
control V
control(Vcontrol
is a wholeThis
feedback
loop
respectively.
S1~S4
control
out1 S6(Vfb1) and V
S5,
Vout2 (Vfb2),This
respectively.
is a wholeout1 (Vout2S6fb1 ) andVS5,
fb2 ), respectively.
image
of
the
proposedcircuit.
feedback loop image of the proposed circuit.
Control circuit

Main circuit
Primary circuit

Gate drive circuit

G1'
Vfb1

FPGA G2'

Vfb2

Isolated gate driver

Rg(on)

Gate
protection

S1
Vfb1
Transformer

Rg(on)

Gate
protection

G2

S2

Vout2

Rg(off)

Vfb2
G3

Gate drive circuit

G5'
G6'

Vout1
G1

Rg(off)

G3'
G4'

Secondary circuit

G4

S3
S4

S5

S6

G5
Gate drive circuit

G6

FigureA1.
A1.Whole
Wholefeedback
feedbackloop
loopimage
imageofofthe
theproposed
proposedcircuit.
circuit.
FigureReferences
1.
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