電気学会論文誌●（●●●●●●●部門誌）
IEEJ Transactions on ●●●●●●●●●●●●●●●
Vol.●● No.● pp.●-●●
DOI: ●.●●/ieejeiss.●●.●

Paper

Single-Phase AC Grid-Tied Inverter with Buck-Type Active Power
Decoupling Circuit Operated in Discontinuous Current Mode
Keisuke Kusaka＊) Member,
Nagisa Takaoka＊ Student member
Tomokazu Sakuraba＊) Member,
Hiroki Watanabe＊) Member,
Jun-ichi Itoh＊a) Senior Member(Manuscript received Jan. 00, 20XX, revised May 00, 20XX)
This study presents a novel circuit topology for a single-phase inverter using an active power decoupling circuit operated indiscontinuous current mode (DCM). In a conventional single-phase grid-tied inverter, bulky capacitors are used in a DC-link toabsorb a power ripple with twice the grid frequency. However, electrolytic capacitors limit a converter's lifetime. In contrast,
ceramic capacitors are used in the proposed circuit since the required capacitance is reduced. Furthermore, the active power
decoupling circuit in DCM has no inductor inside by utilizing the current zero cross featured in DCM for power ripple compensation
modes. An experimental verification using a 1-kW prototype shows a 90.2% current ripple reduction caused by the power ripple
with twice the grid frequency. The efficiency exceeds 94% in the 20% region of the rated power to 1-kW through 96.0% of the 650
W maximum. According to a theoretical evaluation using a Pareto-front optimization assumed as a 3-kW system, the proposed
circuit reaches the maximum power density at 20 kHz which is 115 % higher than that of the passive power decoupling method.
The inductor volume in the proposed circuit is reduced by 30.4% compared to a conventional buck-type active power decoupling
circuit.
Keywords : Single-phase inverter, Discontinuous current, Power density, Power decoupling;1.

rating semiconductors [14].
This study proposes a new buck-type active power decoupling
circuit characterized by no additional inductor in the circuit. The
proposed active power decoupling circuit utilizes discontinuous
current mode (DCM) to absorb the power ripple. The proposed
circuit achieves two operations independently with one boost
inductor by applying DCM. The high-power density is expected incomparison with the conventional active power decoupling circuits
because the additional inductor is not necessary for the proposed
active power decoupling circuit. Furthermore, high efficiency isalso expected since the semiconductor with a low on-resistance
rating is used. This paper is organized as follows. Firstly, in thesecond section, the features of conventional active power
decoupling methods and the proposed active power decoupling
circuit are introduced. Secondly, the operation principle of the
proposed active power decoupling circuit is explained based on acontrol strategy. Thirdly, the proposed active power decoupling
circuit is verified by an experiment using a 1-kW prototype. Finally,
theoretical evaluations using a Pareto-front optimization compare
the efficiency and the power density among a passive power
decoupling method, several conventional active power decoupling
circuits, and the proposed active power decoupling circuit in DCM.

Introduction

In recent years, power conversion systems (PCSs) for a DC tosingle-phase AC grid has been studied actively for photovoltaics
systems or battery energy storage systems and so on [1-3]. In the
single-phase grid, an instantaneous power oscillates at twice thegrid frequency, whereas the PV output power requires constant
power for achieving higher maximum power point tracking (MPPT)
efficiency. As a result, the power ripple with twice the gridfrequency is needed to be compensated in the PCSs. However, alifetime of the PCSs is limited in a conventional passive method
using bulky electrolytic capacitors, according to Arrhenius law [4].
As alternative compensation methods, active power decoupling
circuits have been proposed [5-9]. In the active power decoupling
circuits, the power ripple is absorbed by average stored energy
CΔV2/2 of buffer capacitors with large voltage oscillation ΔV. As aresult, a longer lifetime of the PCSs is expected since the film or
ceramic capacitors can be used. In recent years, not only highefficiency conversion but also high-power density is especiallyrequired to the PCSs [10-13]. However, the active power
decoupling circuits are suffering from the low power density due tothe additional components, especially the inductors. Although therequired inductance can be reduced by increasing switchingfrequency, a trade-off between the inductor volume and the coolingsystem count on the semiconductor switching loss, especially in aboost-type active power decoupling circuit needs high voltage

2.

In this section, the mechanism of a power ripple caused in DC tosingle-phase AC converters is explained at first.
2.1
Principal of active power decoupling
Figure 1 shows the relation among the input power pin, the output
power pout and the compensation power pbuf in the DC to singlephase AC converter. The instantaneous output power is shown ina) Correspondence to: Jun-ichi Itoh. Email:itoh@vos.nagaokaut.ac.jp＊
Nagaoka University of Technology
1603-1, Kamitomioka, Nagaoka, Niigata 940-2188, Japan© 200● The Institute of Electrical Engineers of Japan.

Active Power Decoupling circuits

1

Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)(1) when the output current is sinusoidal wave with unity power
factor.

pout =

is suffered from the power density reduction due to the additional
components, especially the inductor.

Vm I m1 − cos ( 2outt ) .......................................... (1)2

2.4
Buck-type active power decoupling circuit operated
in discontinuous current mode
The discharge mode for the buffer capacitor Cbuf is not realized
due to the impossibility of changing the current direction suddenly,
when the DC-DC converter operates in CCM. Thus, this paper cameup with the idea that the charge and the discharge are realized by
DCM. By utilizing the zero-current period of the DCM, the input
voltage is pushed up to the DC-link voltage, and stepped down tothe buffer capacitor voltage through only one boost inductor [15].
Figure 5 shows a circuit configuration of the proposed buck-type
active power decupling circuit operated in DCM. The proposed
active power decupling circuit in DCM is integrated in the DC-DC
conversion stage without no additional inductors. By the additional

where Vm is the peak voltage of the single-phase grid, Im is the peakcurrent of the inverter output, and ωout is the angular frequency of
the grid. The power ripple with twice the grid frequency occurs in
the DC-link because the input power is controlled to a constantvalue for high MPPT efficiency. In order to absorb the power ripple,
the instantaneous compensation power pbuf is controlled accordingtopbuf =

Vm I mcos ( 2out t ) ................................................. (2).
2

As a result of the energy charge or discharge of the buffer capacitor,
the input power pin is controlled to the constant value of the averagevalue of (1). The capacitance of the power decoupling circuit isdecided from a relation between the storage energy and thecapacitor voltage. From the instantaneous power in (2), the storage
power of the buffer capacitor is represented bypin

Input power
V I
Pin = m m
2
Constant value

0



1
2
2
PC = out Cbuf ( vave + vc ) − ( vave − vc ) ................... (3)2pbuf Buffer power
discharge

=
t

pout

+

0

0

t

t
Tout

chargewhere vave is the average voltage, and Δvc is the voltage oscillation
range of the buffer capacitor. In a passive power decoupling method
using bulky electrolytic capacitors, the power storage energy in (3)is satisfied with large capacitance. By contrast, the active buffers
apply larger voltage amplitude Δvc with smaller capacitance to thepower storage energy. Therefore, a long lifetime system is realized
by using film or ceramic capacitors in the active power decoupling
circuits.

Output power

Fig. 1. Schematic power relation among input, output and buffer.

Sc2
Lin
Vin

2.2
Passive power decoupling method with electrolytic
capacitors
Figure 2 shows a passive buffer topology applied to a DC tosingle-phase AC grid-tied connected inverter. This topology
consists of a boost chopper, bulky capacitors, and a voltage source
single-phase inverter (VSI). However, the electrolytic capacitors
limit a lifetime of the converter according to the Arrhenius law [14].

Lboost

Cdc

Sc1

Cin

Sup

Svp

Sun

Lgrid

Lfil

Cfil

vgrid

Svn

Passive power
Voltage source
single-phase inverter
decoupling method
Fig. 2. DC to single-phase AC converter with passive power decoupling
method with electrolytic capacitors.

2.3
Conventional active power decoupling circuits
Figure 3 shows a circuit configuration of a single-phase inverterwith a conventional boost-type active power decoupling circuit. In
this active power decoupling circuit, the boost chopper with thebuffer capacitor Cbuf to absorb the power ripple is connected to the
VSI in parallel. The active power decoupling circuit obtains alonger lifetime because the film or ceramic capacitors are used tothe buffer capacitor. However, additional components are necessary
to control the capacitor voltage. The additional inductor especiallytends to cause lower power density. The volume of a cooling
becomes larger due to the increase of switching loss, especially inthe boost chopper requiring the semiconductors with high rating
voltage, when the high switching frequency is required to reducethe inductor storage energy.
Figure 4 shows a circuit configuration of a conventional bucktype active power decoupling circuit. The semiconductors withlower rating voltage are used because the buffer capacitor voltage
is controlled to smaller than the DC-link voltage. However, this
topology also needs additional inductor in the active power
decoupling circuit. As a result, the active power decoupling circuit

Sc2

Sb2

Lboost

Lbuf

Cf
Cbuf

ibuf

VSI

Sb1

Sc1

Active power decoupling circuit

Fig. 3. Conventional boost-type active power decoupling circuit.

Sc2

Sb2

Lboost

Lbuf

Sc1

ibuf

Sb1

Cf

VSI

Cbuf
Active power decoupling circuit

Fig. 4. Conventional buck-type active power decoupling circuit.
2

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)bidirectional switch S4, the short connection between Cbuf and Cdc
is avoided. The additional switches require the devices with low
rating voltage. Therefore, the proposed active power decoupling
circuit achieves a high conversion efficiency.

3.

S2

vdc
Cf

LboostOperation Principle of Proposed Active Power
Decoupling Circuit in DCM

VSI

iL

This section explains an operation principle of the proposed
active power decoupling circuit in DCM. The operation modes andthe control strategy of the power ripple compensation are described.
Figure 6 shows operation modes of the buck-type active power
decoupling circuit. The proposed converter has the four operation
modes; Mode 1 and 2 for the boost chopper operation, and Mode 3
and 4 for the active power decoupling operation. It is characterizedthat the proposed converter must be operated in DCM to share theboost inductor Lboost for these controls.
Figure 7 shows the current waveforms of the boost inductor forthe capacitor charging operation and the discharging operation. In
Mode 1 and 2, the converter boosts the input voltage to the DC-link
voltage. Mode 1 and 2 are the typical boost operation irrespectiveof the charging and discharging operation of the buffer capacitor.
The buffer capacitor voltage is controlled in Mode 3 and 4. The
charging mode and the discharging mode of the buffer capacitor isswitched by changing the order of Mode 3 and 4. The boost chopper
operation and the active power decoupling operation time-share theboost inductor. In order to avoid the interference between the boost
chopper operation and the active power decoupling operation, theinductor current must have a zero-current period between thesecontrols. For this reason, the proposed converter must be operated
in DCM.
Note that the proposed converter has a limitation on therelationship among the input voltage, buffer capacitor voltage, andDC-link voltage to avoid the short circuit. The buffer capacitor
voltage must be larger than the input voltage vin and must lower thanthe DC-link voltage, as shown in

S3
S1

S4
vbuf
Cbuf
Active power decoupling circuit

Fig. 5. Buck-type active power decoupling circuit operated indiscontinuous current mode.

S2
iL

S2
S3

S4

LboostCbuf

vin S1

vdc

iL

S3

Lboostvbuf Cf

Mode 1vbuf Cf

Mode 3

S2
iL

Cbuf

vin S1

vdc

S4

S2
S3

S4

LboostCbuf

vin S1

iL

vdc

S3

vdc

S4

Lboostvbuf Cfvin S1Cbuf

vbuf Cf

Mode 2Mode 4
Boost chopper operation
Active power decoupling operation
Fig. 6. Operation modes.
1/fsw

Inductor current iL

Deadtimevin  vbuf  vdc ................................................................. (4).

Average current(constant)

Deadtime

Psw_off_dc

Current zero
period

ZVS

ZCS

0

3.1
Mode 1In the Mode1, the current is flowing to the boost inductor Lboost
from the DC-side, when the switching devices S1 is turned on. The
inductor current starts to increase from zero. Moreover, the flowing
current for the buffer capacitor is zero because the between of theactive power decoupling circuit and the input side is closed-off byusing a bidirectional switching devices S3 and S4. The buffer
capacitor voltage and the DC-link voltage are kept in the values atthe starting value of this mode.

Psw_off_buf
ZVS

Pnloss_S1
ZCS
Mode1
Mode2
Boost chopper operation

Pnloss_S1
t
Mode3
Mode4
Active power decoupling
operation (Capacitor charge)(a) Capacitor charging operation

Inductor current iL

1/fsw
Deadtime
Average current(constant)
Psw_off_dc

Deadtime
ZVS

0

3.2
Mode 2The switching devices S2 turns on, and S1 turns off. In Mode 2,
the energy of the boost inductor is transferred to DC-link. The
buffer capacitor voltage is continuously kept in the constant value,
and the current for the buffer capacitor is zero.
In this mode, the inductor current must reach zero for the
preparation for avoiding the interference between the Mode 1 and
2, and Mode 3 and 4.

Pnloss_S1
Mode1

ZCS
ZVS
Mode2

Pnloss_S3 ZCS
Psw_off_buf
Mode4

t

Mode3

Boost chopper operation

Active power decoupling
operation (Capacitor discharge)(b) Capacitor discharging operation
Fig. 7. Schematic current waveform of boost inductor in active power
decoupling circuit in DCM.

inductor is not necessary for the active power decoupling. Because
the instantaneous current at the start of Mode 3 is always zero by
the DCM operation, the active power decoupling operation is assame as the boost chopper with DCM.

3.3
Mode 3The Mode 3 and 4 are used for the active power decoupling. The
buffer capacitor voltage is controlled by the combination of theswitches of S1, S3, and S4. In the proposed method, the additional

1) Buffer capacitor charging operation
3

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)DC-link capacitor voltage control
vout
iout
vdc
÷
i*L_ave_dc
v*dc
+
+
+
+
PI

vdc
Vin
iL_ave_dc
Vinvdc − Vin
Buffer capacitor voltage control
v*buf_ave i*buf
i*L_ave_buf
++
+
+
PI
PI
vdc

2) Buffer capacitor discharging operation
By contrast, when the S3 is firstly turn-on, the buffer capacitor
discharges, as shown in Fig. 7 (b). Mode 3 continues until the
inductor current reaches zero to avoid the interference between the
boost chopper operation and the active power decoupling operation.
3.4

The current of the active power decoupling circuit is only flowing
in this Mode 4.

d3

Gate
Signal
S1~S4
4

vbuf
Vin

iL_ave_buf

3.6
Control strategy
Figure 8 shows the voltage control block diagram for the DC-link
and the buffer capacitor in the active power decoupling circuit in
DCM. The proposed control method consists of the current controlof the boost inductor as miner loops. The authors have demonstrated
that the DCM current control achieves the same current control
bandwidth of the CCM current control by eliminating thenonlinearity in the DCM current control [16]. Based on this concept,
the current control of the boost inductor is also designed as theCCM current control in the active power decoupling circuit in DCM.
Moreover, the DC-link voltage and the buffer capacitor voltage iscontrolled by the current on the common inductor because the zerocurrent period in the DCM is inserted in order to separate eachvoltage control, as shown in Fig. 7.

2) Buffer capacitor discharging mode
In the buffer capacitor discharging operation, as shown in Fig.
7(b), the converter firstly operates in Mode 4 in the active power
decoupling operation. The discharging operation of Mode 4 ispresented by the period from the zero to the current peak of theactive power decoupling operation ipeak’. Note that the peak current
ipeak’ is determined by the compensation current reference ibuf* of thetwice the grid frequency component in both charging or discharging
operation.
3.5
Calculating equations of each current
The average current iL_ave of the boost inductor is the sum of theaverage current for the DC-link voltage control iL_ave_dc as Mode 1
and 2, and the buffer capacitor voltage control iL_ave_buf as Mode 3
and 4.

1) DC-link capacitor voltage control
In Fig. 8, a voltage command of the DC-link should be higher
than the peak voltage of the gird. In addition, a constant DC-link
voltage is desirable to improve a THD characteristic of the inverter
output current. To control the DC-link voltage, firstly, the inverter
output power is calculated from a multiplication between thedetected grid voltage and the inverter output current. Then, thecalculated result of the inverter output power divided by thedetected the DC-link voltage is feedforwarded to an output of a PI
controller of the DC-link voltage control. As a result of thisfeedforward, the voltage ripple with twice the grid frequency iscompensated. Therefore, small capacitors are used in the DC-linkbecause the current flowing to the DC-link capacitors includes the
only switching frequency components caused by the inverter.

iL _ ave = iL _ ave _ dc + iL _ ave _ buf ............................................... (5)Each average current of these modes is controlled by using thecommon inductor Lboost independently.
1) Boost operation
The necessary current for the transported power to DC-link isgiven by2d2

where d3 and d4 are on-duties of S1 and S3, ipeak’ is the current peakof the buffer capacitor voltage control. These duties d3 and d4 of thecompensation operation for the ripple component are decided PI
controller. As a result, according to (6) and (7), the average currentof boost inductor is controlled at the constant value.

1) Buffer capacitor charging operation
In Fig. 7 (a), when the S3 is turned-on after Mode 3, the buffer
capacitor voltage increases in order to compensate the twice ringing
component caused by connecting single-phase load. The periodwith zero inductor current allows the buffer capacitor charging
operation: Mode 4.

i peakd1

d4
Vinvbuf − Vin
1Carrier0Fig. 8. Control strategy of DC link voltage and buffer capacitor voltage.
vbuf

Mode 4iL _ ave _ dc =PI

Modulation

In Fig. 7 (a), for charging the buffer capacitor, the S1 is firstly
turned-on and achieves ZCS. The necessary energy for the active
power decoupling operation is transported from the input side to theboost inductor in this buffer capacitor charging operation. Note thatthe input current in this mode is not flowing to the buffer capacitor
because the buffer capacitor voltage is higher than the input voltage
at all time. The voltage of the buffer capacitor is kept in the constantvalue in this mode.

( d1 + d2 ) .................................................. (6)where d1 and d2 are the on-duties of S1 and S2, and ipeak is the current
peak of the boost operation. The peak current ipeak and each duties
d1 and d2 of the boost operation is constant value by decided thetransported power.

2)
Buffer capacitor voltage control
In order to absorb the power ripple, the buffer capacitor voltage
is controlled to oscillate at twice the grid frequency. In the proposed
control method, an average voltage of the buffer capacitor is given
as the voltage reference. Therefore, the automatic voltage regulator(AVR) with high bandwidth is not necessary. The current reference
ibuf* is inserted to the output of a PI controller to make the capacitor
charge or discharge, which is represented by

2) Active power decoupling operation
In order to control the average current of the boost inductor to a
constant without the ripple component, iL_ave_buf is given byi 'iL _ ave _ buf = peak ( d3 + d 4 ) ............................................... (7),2
4IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)Table 1. Circuit parameters for 1-kW prototype
Rated power
Input voltage
DC-link voltage

P
Vin
vdc

Buffer capacitor
voltagevbuf_avevc

Switching frequency

fsw

CapacitanceInductance

Cbuf
Cf
Lboost
Lgrid
S1~S4

Switching device
Sup~Swn

ibuf

*

A

Boost inductor current iL + LPF [A]6.8

0

Buffer capacitor voltage [V]

300
250
200

120 mF (40 mF, 3P), Ceramic
54 mF (27 mF, 2P), Ceramic
48.7 mH, Ferrite core
1.6 mH (%Z=1.5%)
SiC-MOSFET
Rohm, SCH2080KE(S1:3P, S3:2P)
IGBT
Fuji electric, FGW30N60VD

B

50
0

10

Inverter output current [A]

10

300
250
200
5
0
-5

0
-10

10ms/div.

10ms/div.

(a) W/o active power decoupling (b) With active power decoupling
Fig. 9. Fundamental operation waveforms. The boost current waveformwith DCM is deiced by the mode of the buffer capacitor voltage.

Boost inductor current iL [A]

30
20
10
0

P
=
cos ( 2out t ) ..................................................... (8)
vbuf

15
10
5
0

where P is the rated output power. Finally, the gate signals of S1-S4
are given by a carrier comparison between a saw-tooth waveform
and the duties d1-d4.

4.

Boost inductor current iL [A]

60
40
20
0

1 kW
150 V
380 V
250 V
160 V
DC-DC converter : 20 kHz
Inverter : 10 kHz

Experimental Verifications of the Active Power
Decoupling Circuit in DCM by using 1-kW
Prototype

Boost inductor current iL + LPF [A]Buffer capacitor voltage [V]

15
10
5
0

300

300

250

250
200

200

Inverter output current [A]10

4.1
Fundamental operation in simulation
The fundamental operation of the proposed circuit in DCM ispresented by the simulation.
Table 1 shows the circuit parameters and the components used in
the experiments.

40
20
0
-20

10

0

0

-10

-10

50µs/div.

50µs/div.

(a) Area A of Fig. 9(b) Area B of Fig. 9
Fig. 10. Extended current waveform of area A and B in Fig. 9 with power
decoupling method using DCM. This figure shows the buffer capacitor in
the charging mode as shown in area A and the discharging mode as shownin area B of Fig. 9.

1)
Fundamental waveforms in simulation
Figure 9 shows the simulation waveforms of the proposed circuitwith or without the active power decoupling. Fig. 9 (a) shows aresult without the proposed active power decoupling. As shown in
Fig. 9 (a), the boost inductor current is distorted by the power ripple
component with twice the grid frequency. The proposed circuit has
a small capacitance of Cbuf which is not completely compensated tothe power ripple at 100 Hz. In contrast, Fig. 9 (b) shows a resultwith the active power decoupling. The current ripple caused by thepower ripple with twice the grid frequency is reduced in Fig. 9 (b),owing to the proposed active power decoupling.
Figure 10 shows the enlarged waveforms of areas A and B in Fig.
9. Figure 10 (a) shows the buffer capacitor charging mode, whereas
Fig. 9 (b) shows the buffer capacitor discharging mode. The boost
inductor current is discontinuous, i.e., DCM. As shown in Fig. 10(a), the first smaller current ripple operates whereas the second
current ripple performs the active power decoupling, i.e., the buffer
capacitor charging operation. Similarly, as shown in Fig. 10 (b), thepositive current performs the boost operation, whereas the negative
current ripple performs the active power decoupling, i.e., thedischarging operation of the buffer capacitor.

Boost inductor current iL [A]
50
0

10

Boost inductor current iL + LPF [A]50

Buffer capacitor voltage [V]DC-link voltage [V]

400
300
200

Inverter output current [A]50-5Load step change

20ms/div.

Fig. 11. Load transient response by proposed control method.

DC-link, and the settling times are 340 V and 0.09 s, respectively.
The maximum error ratio which is compared to the voltage
command of the DC-link voltage is 10.5%. Therefore, the steadystate and transient operation of the proposed topology is confirmed.
4.2
Experimental waveforms of 1-kW prototype
The experimental verifications using a 1 kW prototype has been
done. The experimental condition is the same as table 1. The
ceramic capacitors are connected in parallel with three capacitors
for the buffer capacitor and parallel with two for the filter capacitor,
respectively.

2) Proposed operation under transient state
Figure 11 shows the transient response at the load step with theactive power decoupling operation. This test conducted with change
in the load from 1 kW to 500 W. Note that the load step is provided
by the current source for simplicity. The overshoot voltage of the
5

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)Boost inductor current [20 A/div]0

0

Boost inductor current [20 A/div]
Input current [10 A/div]00Input current [10 A/div]0

Inverter output current [10 A/div]

Buffer capacitor voltage [250 V/div]00Inverter output current [10 A/div][4 ms/div]

Buffer capacitor voltage [250 V/div]0v=160 V[4 ms/div](a) Without voltage oscillation control of buffer capacitor.
(b) With capacitor voltage oscillation control.
Fig. 12. Experimental waveforms at 1 kW.

A gain of the frequency characteristic of the current control isstable in a region of several ten kilohertz in the DCM [17]. Thus,
the inductor current is fed by an open-loop control in the experiment.
Figure 12 shows experimental waveforms when the prototype
operates at 1 kW. In Fig. 12 (a), when the current reference ibuf* is
not applied, the input current oscillates at twice the grid frequency.
This current oscillation affects the MPPT efficiency. By contrast, inFig. 12 (b), the buffer capacitor voltage is oscillated at twice thegrid frequency with an oscillation range of 160 V by inserting ibuf*,
and the ripple of the input current can be significantly reduced.
Therefore, the power ripple is confirmed to be compensated by the
proposed control strategy.

100
Boost inductor current [%]100% : 100 Hz component
without power decoupling

90.2% reduces.
10
Without voltage oscillation
control of buffer capacitor
With voltage oscillation control
1

0.1

8 10 12 14 16 18 20
Harmonic number
Fig. 13. Harmonic analysis of the boost inductor current.

4.3
Harmonics analysis of boost inductor and DC-link
voltage1)
Boost inductor current
Figure 13 shows a harmonics analysis result of the boost inductor
current, which is normalized by its 100-Hz component without thevoltage oscillation control as 100%. Note that the number of theharmonic is based on 50 Hz as the fundamental grid frequency.
From Fig. 13, the 2nd-order harmonics of the boost inductor current
can be reduced by 90.2%. Thus, the power ripple compensation by
the proposed power decoupling active power decoupling circuit in
DCM is confirmed.

02(100 Hz)

4

6

DC-link voltage [%]100% : DC component

100

2)DC-link voltage
Figure 14 shows a harmonics analysis result of the DC-link
voltage. The results are normalized by the DC components as 100%.
The 2nd-order harmonics of the DC-link voltage is less than 1%
regardless of the voltage oscillation control of the buffer capacitor
voltage. Therefore, the proposed control strategy can control thebuffer capacitor voltage without a harmful effect to the DC-link
voltage.

10
Buffer capacitor voltage oscillation does not
impact on the DC-link voltage harmonics.
2nd-order harmonics is sufficiently small.
1
Without voltage oscillation
control of buffer capacitor
With voltage oscillation control
0.1

0

2

8 10 12 14 16 18
Harmonic number
Fig. 14. Harmonics analysis of the DC-link voltage.
(100 Hz)

4

6

20

97
Maximum efficiency : 96.0%

Efficiency [%]96

4.4
Measured efficiency characteristic respect to output
power
Figure 15 shows the measured efficiency characteristic in the 1kW prototype. The switching frequency of the DC-DC conversion
is set to 20 kHz. From Fig. 15, the active power decoupling circuitin DCM keeps the efficiency over 94.0% in region of more than
20% of the rated power. In particular, the maximum efficiency
reaches 96.0% when the output power is 650 W.

95
94
93
92
91

6

0

200

400
600
800
1000
Output power [W]
Fig. 15. Measured efficiency of the 1-kW prototype.

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)Comparison of Efficiency and Power Density ofConventional and Proposed Active Power
Decoupling Methods

Current ripple coefficient Kcap

5.

5.1
Selecting the electrolysis capacitors of passive power
decoupling method
In this paper, the electrolytic capacitors of the passive power
decoupling method are decided from the allowable ripple current.
The current flowing into the electrolytic capacitors includes not
only the power ripple component but also the switching frequency
component caused by the VSI. The capacitor ripple current is afunction of the output power factor and the modulation index,
which becomes a nonlinear value [18]. The effective value of thecapacitor ripple current is expressed by

0.5
0.5

cos =0.8
cos =0.6

0.4
0.4

cos =0.4

0.3
0.3

cos =0.2

0.2
0.2
0.1
0.1
0.1
0.2
0.3
0.1
0.2
0.3

0.4
0.5
0.6
0.7
0.8
0.4
0.5
0.6
0.7
0.8
Modulation index m

0.9
0.9

1
1.0

Start

where ϕ is the output power factor, m is the modulation index andKcap (ϕ, m) is the coefficient regarding to the ripple current obtained.
Figure 16 shows the Kcap(ϕ, m) obtained by an electrical circuit
simulation. For instance, when the unity power factor in the output
and the modulation index of 0.74 from Vm = 282 V divided by Vdc= 380 V, the Kcap(1, 0.74) is 0.56 from Fig. 16. Then, the allowable
ripple current is calculated by

Input
P
vdc
vout

out
vin

Decisions of vav e and vc by Eq. (12)Calculation
Capacitance Cbuf by Eq. (11)Selection of switching device
fsw=1 kHz~100 kHz

Calculations
Inductance by Eq. (13), (14), (23)2

 I
  1  2
I ' rms _ cap =  100 Hz  +   I nsw ....................... (10) K100 Hz   K sw  n −1
with the frequency multipliers, where I100Hz is the effective current
whose frequencies are twice the grid frequency, Insw is the effective
current at the switching frequency, K100Hz and Ksw are the frequency
multipliers at 100 Hz and the switching frequency, respectively.
Thus, the electrolytic capacitor, which has an allowable ripple
current higher than the result of (10), should be required. The
volume becomes smaller by parallel connection of capacitors,
which has small allowable ripple current when selecting theelectrolytic capacitor under the condition of the same rating voltage.
In this paper, the electrolytic capacitors which have allowable ripple
current of 1 A per one is connected in parallel to satisfy the ripple
current requirement with a margin of 50%.

Calculations
Inductor volume by Eq. (15)Calculations
Thermal resistance of cooling by Eq. (16)and Volhe atsink by Eq. (17)Calculations
Power density r and Efficiency hfsw
EndFig. 17. Design flowchart of active power decoupling circuit.

where vmax is the maximum voltage of the buffer capacitor, vmin is
the minimum voltage of the buffer capacitor and α is the voltage
margin of 10%.
Secondly, the switching devices are also selected from thepresent products. As a margin of withstand voltage, the voltage
rating is set to more than 1.5 times of the maximum voltage applied
to the semiconductors. For the boost-type active power decoupling
circuit, the switches of Sb1 and Sb2 are decided by the buffer
capacitor voltage. On the other hand, the DC-link voltage limits thevoltage rating of the Sb1 and Sb2 in the buck-type active power
decoupling circuit. For the MOSFETs, a margin of the rated current
is set to about 5 times of the effective current in this paper.
Thirdly, the inductance of the inductors is designed based on anallowable current ripple Δibuf in the conventional boost-type active
power decoupling circuit. The inductance becomes the maximum
value when the voltage difference between the DC-link and thebuffer capacitor reaches the maximum. Thus, the inductance iscalculated by (13) with current ripple of 30 % in this paper.

5.2
Design flow for conventional active power
decoupling circuits
Figure 17 explains the proposed flowchart for designing theactive power decoupling circuit. Firstly, the capacitance is decided
from the aspects of the voltage and the storage energy of (3). The
capacitance in the active power decoupling circuit is calculated by
Cbuf =

Power factor cos =1.0

0.6
0.6

Fig. 16. Current coefficient for calculation of ripple current flowing into
DC-link capacitor in DC to single-phase AC converter.

I rms _ cap = K cap ( , m) I m .................................................... (9)

2

0.7
0.7

P
..........................................................(11).
out vave vc

In the active power decoupling circuits, the voltage of the buffer
capacitor is controlled to large Δvc. Then, the required storage
energy is achieved with small capacitance. This is the principle tobe able to reduce the capacitance in the active power decoupling
circuits. The capacitor volume is determined from the present
products. Note that the average voltage of the buffer capacitor is
calculated by using the maximum and minimum of the buffer
capacitor voltage as following:v 
v + c  − vdc
vdc  ave
2 ..................................... (13)Lbuf =
v
iL f sw
vave + c
2

1
1
vave = vc + vmin = ( vmax − vmin ) + vmin22.......... (12)1= ( vdc −  vdc ) − ( vin +  vin ) + ( vin +  vin )2

where fsw is the switching frequency in the active power decoupling
7

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)circuit.
On the other hand, in the conventional buck-type active power
decoupling circuit, the inductance of the smooth inductor becomesthe maximum value when the capacitor voltage is a half of the DClink voltage. Thus, the inductance is designed by
Lbuf _ buck =operation decided from the output power, the voltages and thecurrent peak are obtained by

vdc .......................................................
(14).
4iL f sw

The inductor volume depends on many parameters of thecomponents. There are several ways to select the core for the
inductor. In this paper, the inductor is designed by Area Productconcept, which is using the core window area and the crosssectional area [19]. The inductor volume of the inductor is
calculated by

Ploss

(

vin
d1 ............................................................. (19)vdc − vin

d3 =P
2 vbuf − vin .................................
cos ( 2out t )(20)vini peak ' vbuf

d4 =

vin
d3 ............................................................ (21).
vbuf − vin

The current mode transits from DCM to CCM through the criticalcurrent mode (CRM) when (22) exceeded to 1. In the active power
decoupling circuit in DCM, the CCM is undesirable current mode
because it makes the impossibility of the energy discharge of theinductor to the buffer capacitor or the DC-link capacitor. The
current ripple of the inductor is minimized when the proposed
active power decoupling circuit operates in the CRM. As a result,the conduction losses caused by the semiconductors and the boost
inductor are minimized. Thus, this paper focuses on the CRM
condition to design the circuit parameters of the active power
decoupling circuit in DCM. The inductance of the boost inductor in
CRM is calculated by)− Rth( j − c ) + Rth(c − f ) ........................... (16)

Lboost =where Tj is the junction temperature of the switching device, Ta is
the ambient temperature, Ploss is the loss caused by thesemiconductors, Rth(j-c) is the thermal resistance between thejunction and the case and Rth(c-f) is the thermal resistance between
the case and the cooling system. In order to estimate the volume of
the cooling system, CSPI (Cooling System Performance Index) is
introduced in this paper [20]. The CSPI means a cooling
performance per unit volume of the cooling system. The coolingsystem is miniaturized when the CSPI becomes higher by the forced
cooling system [19]. However, the system lifetime is limited bythese fans. Thus, the cooling system is desirable to be designed on
the assumption that natural cooling is applied. The volume of thecooling system Volheatsink is provided by [19].

VoLheatsink =d2 =d1 + d2 + d3 + d4  1 ...................................................... (22)where Kv is the volume coefficient depending on the shape of cores,
Imax is the maximum current flowing to the inductor, Ku is thewindow utilization factor, Bmax is the maximum flux density of core,and J is the current density of wire. In this paper, Bmax=1.2 T of acharacteristic of nanocrystal line amorphous soft magnetic metal isused. The inductor volume is calculated from Kv=13.4, Ku=0.7 and
J=4 A/mm2 based on a present product of a toroidal coil.
A volume of a cooling system is calculated from a required
thermal resistance which is decided by losses caused by thesemiconductors. The required thermal resistance Rth(f-a) is calculatedfromT j − TaP
2 v −v1 − cos ( 2outt ) i dcv in ........................... (18)
vin
peak
dc

In order to avoid the interference between the two operations, thetotal of the duties is always necessary to meet the condition of (22).

3 Lbuf I max 2  4.............................................. (15)
VolLbuf = Kv 
 K B J 
 u max Rth( f − a ) =d1 =vin 2 ( di − 1) bd ( di − 1) 
4 f sw P di 1 +
2  di bd − 1 

2....................... (23)where αbd is the boost ratio of the average voltage of the buffer
capacitor to the DC-link voltage and αdi is the boost ratio of the DClink voltage to the input voltage. The inductor volume can be
estimated from (15).
The volume of the cooling system can be also estimated from
(17). The conduction loss of the semiconductors is calculated by(24) from the boost inductor current, and duties d1~d4.
Ploss _ cond =Toutron  Touti peak 2 ( d1 + d 2 ) dt +  i peak ' 2 ( d 3 + d 4 ) dt  (24)



0
0
3Tout where Tout is the period time of the grid, and ron is the on-resistanceof the semiconductors.
Figure 18 describes the patterns when the switching loss happens.
The total switching loss is sum of the turn-on loss, the turn-off loss,
the recovery loss in the free-wheeling diode (FWD) and the loss
caused by the parasitic capacitor discharge. In the active power
decoupling circuit in DCM, the turn-on loss does not occur becauseof zero current switching (ZCS). On the other hand, the turn-off
switching loss is caused near the current peak. Therefore, the turnoff switching losses are given by1.............................................. (17)Rth ( f − a )CSPI

Finally, in order to clarify the maximum power density point, aPareto-front of an efficiency η and a power density ρpower is obtainedwith switching frequency as a variable.
5.3
Design method of the proposed buck-type active
power decoupling circuit in DCM
The designing flow shown in Fig. 17 is applied to the proposed
active power decoupling circuit in DCM. In the active power
decoupling circuit in DCM, the voltage rating of all of thesemiconductors is decided from the DC-link voltage. Thus, theswitching devices with low rating voltage can be used.
In the equivalent current waveforms of Fig. 7, the duties of each

Psw _ off _ dc =8

eoff
Edcd I md

f sw

1 Toutvdci peak dt ........................ (25)Tout 0

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)Table 2. Selected components for 3 kW system.

Buck
type

Sb1, Sb2

Nippon Chemi-Con
450 V, 1.0 Arms
EKMZ451VSN181MP30S
180 mF
ROHM
650 V
SiC-MOSFET, SCT3022AL
65 A
Murata Manufacturing
400 V
30 mF
EVS20329S2G306MS09
Murata Manufacturing
450 V
1 mF
KC355WD72E225MH01
ROHM
1200 V
SiC-MOSFET, SCT3040KL
39 A
ROHM
650 V
SiC-MOSFET, SCT3030AL
49 A

Proposedcircuit

S1-S4

ROHM
SiC-MOSFET,SCT3017AL

Passive

Cdc

Boost
chopper

Sc1, Sc2

Boost typeactivepower
decoupling

Cbuf
Cf
Sb1, Sb2

Psw _ off _ buf =eoff
Edcd I md

f sw

99.8

Rating at 100°C

DC-DC conversion efficiency [%]Component

Proposed Circuit(20 kHz)

1 kHz

99

Passive (35 kHz)

98.6

Boost-type (45 kHz)

98.2

Buck-type(45 kHz)100 kHz

97.8
97.4
97

1200 V
83 A

fsw increases.

99.4

Rated power : 3 kW
02

100 kHz4
6
8Power density [kW/dm3]

1012Fig. 18. Calculated Pareto-front of DC-DC conversion with passive or
active power decoupling circuits.

1 Toutvbuf i peak 'dt .................... (26)Tout 0120
Volume [%] 100%=0.32 dm3Topology Symbol

where eoff is turn-off energy per the switching, Edcd and Imd are thevoltage and the current under the measurement condition referredto the datasheet. The recovery loss of S1 and S3 does not occur
because the FWDs are turned off naturally. However, when S 1 andS3 turn on, the losses are caused by the discharges of the parasitic
capacitors and calculated by3
Psw _ on _ s1 = Cdcvin 2 f sw ................................................... (27)
4

100

Lbuf

Heatsink(Power decoupling)Cf80

Device

60

Cbuf

40

Heatsink(Chopper)

20
0

2
1
Psw _ on _ s 2 = Cds ( vbuf − vin ) f sw ..................................... (28)4

Rated power : 3 kW
Electrolytic capacitor

LboostPassive(35 kHz)

Boost type Buck type Proposed circuit(45 kHz)(45 kHz)(20 kHz)

Fig. 19. Component volume distribution at the maximum power density
points.

where Cds is the capacitance between the drain and the source of theswitching device. From (25)-(28), the switching loss proportionally
increases with the increase of the switching frequency.

120
Cdc

Loss [%] 100%=35.2 W

100

5.4
Theoretical evaluation of proposed active power
decoupling circuit in DCM in terms of efficiency and power
density
Table 2 shows the selected components assumed to be used in 3kW system of each circuit topology. The inverter output power of
3-kW, the input voltage of 150 V, the DC-link voltage of 380 V, theinverter output voltage of 200 V with 50 Hz are assumed. Fig. 18
shows the Pareto-front of the efficiency and the power density withthe switching frequency as a variable in the DC-DC converter withthe power decoupling circuits. In Fig. 18, the losses caused by thesemiconductor and the resistive loss of the capacitor are considered.
In the active power decoupling circuits, the ceramic capacitor
with high energy density is selected as the buffer capacitor. The
parallel number of the ceramic capacitors is decided from (11) withconsideration of capacitance reduction effect due to the DC bias.
The current ripple of the inductor is set to 30% of the peak current.
The switching frequency in the active power decoupling circuits is
assumed to be same as in the boost chopper. The boost inductor in
the active power decoupling circuit in DCM is designed based on
the CRM condition. In Fig. 18, the power density of all of the circuit
topologies increases with the increase of the switching frequency atthe beginning, because the inductor volume can be reduced.
However, the heatsink volume increases due to the deterioration of
the switching loss. As a result, with increasing the switchingfrequency, the power density decreases after reached at the80

Cbuf, Cf

Switching loss
(Power decoupling)
Conduction loss
(Power decoupling)
Switching loss
(Chopper)60
40

Conduction loss
(Chopper)20
0

Cbuf, Cf

Passive(35 kHz)

Boost type Buck type Proposed circuit(45 kHz) (45 kHz)(20 kHz)

Fig. 20. Loss distribution at the maximum power density points.

maximum value.
According to Fig. 18, the maximum power density of the passive
power decoupling method is 9.3 kW/dm3 with the efficiency of
98.8% when the switching frequency is 35 kHz. The conventional
active power decoupling circuits in the boost-type and the bucktype reaches 9.5 kW/dm3 at 45 kHz and 9.9 kW/dm3 at 45 kHz
respectively. By contrast, the active power decoupling circuit in
DCM approaches 10.8 kW/dm3 with efficiency of 98.8% when theswitching frequency is 20 kHz. Therefore, the maximum power
density in the proposed active power decoupling circuit in DCM is115% and 108% compared with in the passive and the conventional
buck-type active power decoupling circuit, respectively.
Figure 19 shows the volume distributions of the components at
the maximum power density point of each circuit topology. The
9IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)component volume is normalized with the volume of the passive
power decoupling method as 100%. The active power decoupling
circuit in DCM reduces the inductor volume by 30.4% whencompared to the conventional buck-type active power decoupling
circuit. As a result, the total volume is reduced by 7.2%.
Figure 20 shows the loss distributions at the maximum power
density point of each circuit. These results are normalized with thetotal loss of the passive power decoupling method as 100%. The
total loss of the active power decoupling circuit in DCM is 98.7%of that of the passive power decoupling method. The conduction
loss of the chopper caused by S1 and S2 accounts for 45.9% of thewhole in the active power decoupling circuit in DCM. This isbecause the effective current flowing to the switching devices isincreased due to the higher current peak of the DCM.

6.

(6)

(7)

(8)

(9)

(10)

Conclusion(11)

This study proposed a novel buck-type active power decoupling
circuit operated in DCM to be applied to a DC to a single-phase AC
converter. The proposed active power decoupling circuit in DCM
absorbs the power ripple by ceramic or film capacitors instead ofelectrolytic capacitors, a long lifetime can be expected. Moreover,utilizing the current zero cross in DCM for the power ripplecompensation, the proposed active power decoupling circuit in
DCM doesn’t need additional inductors.
The experimental verifications by a 1-kW prototype of the active
power decoupling circuit in DCM showed the following results.
(1) A current ripple with twice the grid frequency was reduced by
90.2% by the proposed active power decoupling circuit in DCM.
(2) A voltage ripple of the DC-link is less than 1% against the DC
component. A non-interference between voltage controls of DClink and buffer capacitor can be achieved by utilizing the zerocurrent period in the DCM.
(3) A conversion efficiency exceeds 94 .0% in the region of 20%of the rated power to 1 kW, especially 96.0% of the maximum at
650 W.
According to a theoretical evaluation in an assumption of a 3-kW
system, the following results were clarified through a Pareto-frontof power density and efficiency clarified the following results.
(4) The maximum power density of the active power decoupling
circuit in DCM is achieved at 20 kHz, and 115 % higher than theelectrolytic capacitors of the passive power decoupling method.
(5) Compared to in a conventional buck-type active power
decoupling circuit, the proposed active power decoupling circuit in
DCM reduces the total inductor volume by 30.4%.

(12)

(13)

(14)

(15)

(16)

(17)

(18)
(19)
(20)

Keisuke Kusaka(Member) received his B.S. and M.S. degrees inelectrical, electronics and information engineeringfrom Nagaoka University of Technology, Niigata,Japan in 2011, 2013, respectively. From 2015 to 2016,he was with Swiss Federal Institute of Technology in
Lausanne (EPFL), Switzerland as a trainee. In 2016,
he received his Ph.D. degree in energy andenvironment science from Nagaoka University ofTechnology. Since 2016, he has been with Nagaoka
University of Technology, Niigata, Japan as a researcher. He is currently an
assistant professor at Nagaoka University of Technology. His current
research interests include the areas of inductive power transfer systems andhigh-frequency converters. He is a member of Institute of ElectricalEngineers of Japan, Society of Automotive Engineers of Japan and IEEE.

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10IEEJ Trans. ●●, Vol.●●, No.●, ●●●Buck-type Active Power Decoupling Circuit Operated in DCM (Keisuke Kusaka et al.)Nagisa Takaoka(Student Member) received her B.S. and M.S.
degrees in electrical, electronics and informationengineering from Nagaoka University of Technology,
Niigata, Japan, in 2014 and 2016 respectively. She iscurrently working toward the Ph.D. degree at the
Nagaoka University of Technology, Japan. She is amember of IEEJ and IEEE. Her current researchinterests include matrix converters, dc to singlephase ac converters.

Science and Technology, April 2017. He is a senior member of the Instituteof Electrical Engineers of Japan, the Society of Automotive Engineers ofJapan and the IEEE.

Tomokazu Sakuraba(Member) received his B.S. and M.S. degrees inelectrical, electronics and information engineeringfrom Nagaoka University of Technology, Niigata,Japan in 2015 and 2017, respectively. He has beenwith Mersen Japan K. K., Japan since 2017. From2018 to 2019, he was with Research andDevelopment department in Mersen France SB
S.A.S., France. He is a member of IEEJ and IEEE.
His current research interests over current protections
for power semiconductor and battery by fuses and new DC hybrid protection
devices.

Hiroki Watanabe(Member) received his B.S. and M.S. degrees
from Nagaoka University of Technology, Niigata,Japan in 2013, 2015, respectively. From 2017 to 2018,he was with Swiss Federal Institute of Technology in
Lausanne (EPFL), Switzerland as a trainee. In 2018,
he received his Ph.D. degree in energy andenvironment science from Nagaoka University ofTechnology. From 2018, he has been with Nagaoka
University of Technology as a researcher. His current
research interests include a single-phase power conversion systems andbidirectional isolated DC-DC converters.

Jun-ichi Itoh

(Senior member) received his M.S. and Ph.D.
degree in electrical and electronic systems
engineering from Nagaoka University of Technology,
Niigata, Japan in 1996, 2000, respectively. From1996 to 2004, he was with Fuji Electric Corporate
Research and Development Ltd., Tokyo, Japan. He
was with Nagaoka University of Technology, Niigata,Japan as an associate professor. Since 2017, he has
been a professor. His research interests are matrix
converters, dc/dc converters, power factor correction techniques, energy
storage system and adjustable speed drive systems. He received IEEJ
Academic Promotion Award (IEEJ Technical Development Award) in 2007.
In addition, he also received Isao Takahashi Power Electronics Award in
IPEC-Sapporo 2010 from IEEJ, 58th OHM Technology Award from The
Foundation for Electrical Science and Engineering, November, 2011,
Intelligent Cosmos Award from Intelligent Cosmos Foundation for the
Promotion of Science, May, 2012, and Third prize award from Energy
Conversion Congress and Exposition-Asia, June, 2013. Prizes for Scienceand Technology (Development Category) from the Commendation for
Science and Technology by the Minister of Education, Culture, Sports,
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