SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23D • 12277 Berlin • Germany
Phone +49 30 772051-0 • Fax +49 30 7531078
E-Mail: sales@shf.de • Web: http://www.shf.deDatasheet
SHF 11125 A
Compact Dual-Channel 32 Gbps
Error Analyzer

SHF reserves the right to change specifications and design without notice – SHF 11125 A - V002 – August 27, 2014 – Page 1/7

Description
The SHF 11125 A is a dual-channel 32 Gbps error analyzer (EA). It features two differential data inputs
with a high sensitivity and a wide delay range.
7910111520The compact instrument analyzes PRBS patterns with lengths of 2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 223-1,
31
and 2 -1. All operating data rates from 5 to 32 Gbps are supported. This allows bit error rate tests for avariety of different applications including, 100GbE and higher, 28 Gbps CEI, Infiniband , Fiber channel aswell as parallel channel data-com.
The operating bit rate is determined by a clock signal from an external clock source. The channels canwork with a common clock to operate at the same or with an individual clock to enable operation at
different data rates.
Its compact size and light weight allows a placement very close to the DUT.

Ease of Use
The SHF 11125 A is controlled over a standard Ethernet connection by an external computer (not part ofthe delivery). Every system comes along with the intuitive, easy to use BERT Control Center software(BCC). The BCC provides the user friendly interface for changing parameters and for taking
measurements such as a quick auto-search, Q-factor, jitter or eye contour analysis.
Further the unit allows for additional customization to suit the intended test and measurement applications,be it for system R&D or in the production environment.

Features





Two differential input channels
5 to 32 Gbps operation, ‘gap-free’
7910
1115202331
PRBS 2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 2 -1
Individual or common clock input
Two clock outputs for trigger purposes
Compact size and low power consumption
High Sensitivity and wide delay range
Extensive measurement capabilities such as quick auto-search, Q-factor, jitter and eye-contour

ApplicationsOn-Wafer Testing
CEI-28G
100G Ethernet
Infiniband
Fibre Channel ®
High Speed Serial Backplane Applications

InfiniBand is a registered trademark of the InfiniBand Trade Association

SHF reserves the right to change specifications and design without notice – SHF 11125 A - V002 – August 27, 2014 – Page 2/7

Specifications – SHF 11125 A
Parameter

SymbolUnitMin.

Minimum Bit Rate

Rmin

Gbps

Maximum Bit Rate

Rmax

Gbps

32Threshold Adjustment

Vthreshold

mV-2401VinmVTyp.

Max.

Comment

32 Gbps Data Inputs

Sensitivity

Delay / Clock Phase
Adjustment
Clock Phase Margin2CPM53324030

ps0°

200

Max. Input Amplitude
VinmVpp

Adjustable in 0.5 mV steps

50
140

Adjustable in 0.1 ps steps

800
1000

Single ended
Differential
Input AC coupled

Connectors

2.92 mm (K) female

Clock Inputs
Frequency

f

GHz

2.5

16Input Level

PindBm04Connectors

Half clock operation

2.92 mm (K) female

Clock Outputs
FrequencyfGHz

2.5Output Level

Vout

mV

350

450

Connectors

16Clock

700

Clock/2, AC coupled
2.92 mm (K) female

1Corresponds to the measured eye height on an Agilent 86100 C with 70 GHz sampling heads using 231-1 PRBS at a BER limit of 10-92

BER limit 10-9, PRBS: 231-1, Eye Height: 100 mVpp, Peak-to-Peak-Source-Jitter as displayed on an Agilent 86100 B with 70 GHz
sampling heads and precision time base, calculated using the formula:
Clock Phase Margin[]  360  

Measured Clock Margin[ps] - (Peak - to - Peak - Source - Jitter [ps])Eye Length [ps]SHF reserves the right to change specifications and design without notice – SHF 11125 A - V002 – August 27, 2014 – Page 3/7

Parameter

Symbol

Unit

Min.

Typ.

Max.

Comment

Pattern
ITU-T (CCITT) conform
PRBS patterns at a length of79101115
2 -1, 2 -1, 2 -1, 2 -1, 2 -1,2023
312 -1, 2 -1 & 2

Input PatternGeneral
Supply Voltage

VeeV

11.5

1212.5

Power Consumption

Ptot

W25HeightHmm

64

WidthWmm

116

Depth

Dmm

183

Weightmg

500

Case Temperature

Tcase°C

40+12V switching power supply
is included

SHF reserves the right to change specifications and design without notice – SHF 11125 A - V002 – August 27, 2014 – Page 4/7

Clock Distribution
The operating bit rate is determined by a clock signal from an external clock source which is not part of theerror analyzer. The error analyzer operates at half clock rate, e.g. a 15 GHz clock signal is required for
30 Gbps operation.
In common clock mode the unit operates with one single clock signal. In this case both data inputs operate
at the same data rate. A phase change of the clock signal will result in the same phase change at bothdata inputs.
In individual clock mode each data input has his designated clock input. Thus the individual channels canwork at different data rates. An asynchronous phase wander in the two channels will not require a delay
adjustment during error analysis if the (recovered) individual clocks keep track. This is very useful even if
both channels operate at the same data rate.
For trigger purposes each channel provides a copy of the input clock signal at the clock output at the rear
panel of the instrument

SHF reserves the right to change specifications and design without notice – SHF 11125 A - V002 – August 27, 2014 – Page 5/7

Graphical User Interface

Jitter Measurement

BERT Control Center Software
Main Window

Eye Contour Measurement

Q-Factor Measurement

SHF reserves the right to change specifications and design without notice – SHF 11125 A - V002 – August 27, 2014 – Page 6/7

Outline Drawing
7240CH 2

SHF 11125 A Error Analyzer
Data

Data

Data

Data
Clk In63.6

CH 1

Service

Clk Out

Clk In12V / 3A50

50

Channel 150

Channel 2

Ethernet

USB

22.4
17.6
16.8

35.4

50

47.1
44.3

On/Off

30
60
116

22
46.1
68.2
94

173.7
183.4

SHF reserves the right to change specifications and design without notice – SHF 11125 A - V002 – August 27, 2014 – Page 7/7

Clk Out