Monolithic Pixel Detector
with SOI technology

July. 1, 2011
@AGH Krakow
Yasuo Arai, KEK
yasuo arai@kek jp
yasuo.arai@kek.jp
http://rd.kek.jp/project/soi/

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OUTLINE•Introduction of SOI Pixel Project•SOI Detectors•Developing Techniques•SummaryS

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SOI Wafer (UNIBONDTM)(1995, LETI -> SOITEC)

SmartCut(1991)(Michel. Bruel)microbubbles
hydrophilic
bonding~500
500oC

CMOS(Low R)

Sensor(High R)3

Features of SOI Pixel Detector
Bonded wafer : High Resistivity (Sensor) + Low Resistivity (CMOS) .



Truly Monolithic Detector (->( > High Density
Density, Low materialmaterial, Thin Device).
Device)Standard CMOS can be used (-> Complex functions in a pixel).

N mechanicalNoh i lbbump bbondingdi ((->> HighHi h yield,i ld L
Low cost).
t)





Fully depleted sensor with small capacitance of the sense node
( 10fF Hi(~10fF,Highh conversion
i gain,i L
Low noise)i )Based on Industrial standard technology (-> Cost benefit andS l bilit )Scalability)

No Latch Up, Low SEE 

Low PowerOperate in wide temperature(4K-570K(300゜C)) range.

下部Siをセンサーとして利用...
4Bulk CMOS vs. SOI CMOS

In SOI, Each Device iscompletely isolated byOxide.
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Steep Sub Threshold Slope

Gate voltage is not wasted todeplete the bulk.
Lower Threshold (Leakage Current) is possible without
increasing Leakage Current (Vth).
(Vth)Copyright 2007 Oki Electric Industry Co.,Ltd

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Operation at Cryogenic Temperature

Bulk MOS

SOI MOS

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SOI

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SOI Pixel Project Brief History'05. 4 : Proposed to KEK Detector Technology Project.
(Generic R&D)
'05. 7 : Start Collaboration with OKI Semiconductor.
'05.10 : 1st Submission in VDEC 0.15 um MPW.
06.12 : 1st (and last) 0.15 um KEK MPW run.
'06.12'07.3 : 0.15 um lab. process line was closed.
 move tot 0.2
0 2 um mass production
d ti liline att Mi
Miyagi.
i'08.1 : 1st 0.2 um KEK SOI-MPW run.
'08.10 : OKI is owned by ROHM Co. Ltd.
((Lehman Shock)):'11 1 6th KEK SOI-MPW'11.1:
SOI MPW run
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SOI Pixel Process Flow
SOI (40 nm)
Box (BuriedOxide)(200 nm)

650um

Handle Waferp+n+Handle Wafer

n+Handle Wafer

p+50~650um

Al10OKI semi/ROHM 0.2 m FD-SOI Pixel Process
Process

0.2m Low-Leakage Fully-Depleted SOI CMOS
1 Poly, 5 Metal layers.
MIM Capacitor (1.5 fF/um2), DMOS
Core (I/O) Voltage = 1.8 (3.3) VSOIwafer

Diameter: 200 mm
mm, 720 mm thick
Top Si : Cz, ~18 -cm, p-type, ~40 nm thickB i dO
BuriedOxide:
id 200 nm thithickkHandle wafer: Cz (n) ~700 -cm,FZ(n) ~7k -cm, FZ(p) ~40 k -cmBackside Mechanical Grind
Grind, Chemical Etching
Etching, Back sideprocess Implant, Laser Annealing and Al plating
11MPW ((Multi ProjectjWafer)) run
We are operating MPW runs Twice / year.
(Next MPW run is Oct. 3rd.)
Louvain-la-Neuve Univ.

U off Hawaii
U.
Hii

INP K
Krakow
kIHEP Chi
China

U. Heidelberg

U. Tohoku
Kyoto Univ.

JAXA/ISAS
Tsukuba Univ.
AIST12

2006
0.64 mm2008~92.56 mm

SOI Pixel Detectors

32 32
32x32
Vbias~10V

2010
128x128

13.8 mmVbias~100V

832x512
Vbias~250V
13By the Way,Way
OKI Semi fab is located very nearto the Center of the Earthquake.

T MiT-Micro14

SOI Detectors
D15

Integration Type Pixel (INTPIX)

Vsense 

Q 0.6 fC
 70mVC8 fF

線

Size : 14 m x 14 mwith CDS circuit
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Integration Type Pixel (INTPIX4)

Largest Chip so far.

15 mm

10 mm

17x17 m, 512x832 (~430k）
pixels 13 Analog Out
pixels、13Out、CDS
CDS
circuit in each pixel.

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Data Acquisition Board• Soi EvAluation BoArd with Sitcp(SEABAS）
Sitcp(SEABAS）• A FPGA controlst l theth SOI Pixel
Pi l chiphi• Directly transferred to Ethernet

SEABASINTPIX4USER
FPGA

D t
DataTransfervia
Ethernet

ADC & DAC
300mm30018

Spatial Resolution (Contrast Transfer Function)•Comparison of contrasts with commercial X-ray devices.
– SOI Pixel : INTPIX4, Flat Panel Sensor (FPS), CCD, and Imaging Plate (IP)FPS

INTPIX4

CTF [%] = B / A

CCD

UUpperLiLineA

B
Under LineIP

Base Line19

INTPIX4Pixel Size : 17 um x 17 um
No. of Pixel : 512 x 832 (= 425,984)
Chi SizeChip
Si : 10.310 3 mm x 15.515 5 mmVsensor=200V,Vsensor=200V, 250us Int. x 500
X-ray Tube : Mo, 20kV, 5mA

Fine resolution & Highg Contrast

5mm
X-ray Image of a small dried sardine taken bya INTPIX4 sensor (3 images are combined).

(A. Takeda)

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XRPIX1

FWHM=260eV

Cu K and K isseparated
Noise ~ 23e@-50゜C
゜(Kyoto Univ.)21

CERN SPS
200GeV/C - beam

~1.2 m

LBNL & Padove
NIM A, M. Battaglia et al.,
http://dx.doi.org/10.1016/j.nima.2011.05.081

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e+ Beam Test at Tohoku Univ.

SOI beam test 2010 collaboratione+ Beam ~673MeV/c

~2.9 m(incl. multiple scattering)23

Counting Type Pixel (CNTPIX)

Energygy selection andCounting in each pixel.
4 pixels can becombined.

5 x15.4 mm272 x 272 pixels
64um x 64 um pixel
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CNTPIX5Pixel Layout

64 64 um264x64~600 Tr/pix
x 72 x 212= 10 M Trs
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CNTPIX X-ray
X ray Test
PixelsPiels are working
orking b
butt somecrosstalks are observed.

Count v.s. sensor bias.

Count v.s. X-ray Tube Current
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DDevelopingl i Techniques
T h i

1st AlHandle Wafer
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Buried p-Well (BPW)BPW Implantation

Substrate Implantation
BuriedOxide(BOX)SOI Si
Pixel

P+Peripheral
BPW• Cut Top Si and BOX• Keep Top Si not affected• High Dose

• Low Dose• Suppress
S
theth BackB k Gate
G t Effect.
Eff t• Shrink pixel size without loosing sensitive area.
• Increase break down voltage with low dose region.
• Less electric field in the BOX which improve radiation
hardness.

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Id-Vg and BPW
w/o BPW

with BPW=0V

NMOS

back channel openshift

Back ggate effect is suppressedppbyy the BPW.
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Radiation Tolerance
SOI isi Immune
Ito Single
Si l E
Event EffEffectGate Oxide
GateSiGate＋ －－ ＋＋ －－ ＋＋ －－ ＋＋ －－ ＋＋ －－ ＋＋ －Si＋ －BuriedOxide
Depletion
Layer

Bulk Device

SOI Device＋ －－ ＋＋ －－ ＋＋ －－ ＋

But not necessary strong to Total Ionization Dose due tothick BOX layer
GateSiBuriedOxide＋＋＋＋＋

TrappedHoles30

Radiation Tolerance and BPW
By adding the BPW layer, Electric field in the BOX is reduced and possibilityof chargeg recombination will increase. Thus increase radiation tolerance.

X-ray Irradiation31TID(Total Ionization Doze) Damage Compensation
Leak Current and VTh resumes to nearly originalvaluel byb bibiasingi bbackk side
id even att 100M
100Mrad.
dVback= 0 -10 -20 -30V
1015 p/cm2((~10000 Mrad)d)beforeirradiation

1015 p/cm2(~100 Mrad)

This can be done with nested
well or double SOI wafer

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FZ(p and n) SOI Wafer
It was difficult to process 8’’ FZ-SOI wafer in CMOS process.
Before Oxidation

Conventional SOIProcessImproved SOIProcess

SlipslWe optimized
pthe pprocess p
parameters,, and succeeded toperform the process without creating many slips.
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Wafer type and Leakage Current

INTPIX3e
INTPIX334

Nested BNW/BPW Structure• Signal is collectedwith the deep
Buried P-well
P-well.
• Back gate andCross Talk areshielded with theBuried N
N-well.
well

FEE2011 G. Deptuch (Fermilab)
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Impurity
Concentration

Peaks of BNW andBPW are separated~0.7 m to reduce
capacitance36

Double SOI Layer wafer
circuitsensor

additional
conduction layer
ShieldShild sensors
from circuit

In addition to the shielding between sensor
and electronics,* oxideid ttrappeddhholel can bbe compensatedt d* able to control Tr threshold voltage block byblock* additional components such as diode,resistors can be implemented.
pWafer is ready.
yProcess study is in progress.
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New Mask
Larger Mask
PPresentMask
M kLarger mask will be
used from next MPWrun.
 Larger Sensor &Reduced cost per area.

32 mmm20.8 mmx20.8 mm

25 mm
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Stitching
Stitching test is in preparation.

~30 mm~6666 mm39

Vertical (3D) Integration

T-micro + OKI Semi+ KEK/LBNL/Fermilab

We have submitted 3D test chips
p on Feb. 2009 and Feb. 2010 to theSOI process. These chips are being bonded with -bump technology(~5 um pitch) of T-micro Co (ZyCube).
We had a few technical problems and non
non-technicaltechnical issues
issues.

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41

T Micro
T-Micro-bumps
bumps fabrication

10 um

Copyright 2009 OKI semiconductor Co. Ltd.

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Difficult to Etching
Hi-R

Also Etchedfrom side

Hi-REEasytot Etching
Et hiLo-R

Change Low
Resistive Wafer forTop Chip
CHi R
Hi-R
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We observed Resist is
melting into the -bumpbumphole after back grinding.

B kG
BackGrindingd

We changed the order, so theb k sideback
id iis grinded
i d dbbeforefththe-bump hole formation.
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T-Micro

Before adhesivejinjection

Si etching

Before Si etching

After Si etchinggSi etching

Now Back side
Al plating isbeing done45

4. Summary• SOI technology has many good features; low power, large
range of operating temperature, low single event effect,
vertical integration, ...
• SOI Pixel process becomes more stable and practical touse. Most of the technical problems are solved.
• We have ~twice/year regular MPW runs with increasing no.
of users (Next MPW run is Oct. 3rd).
• Many pixel sensors are working and showing goodpperformance.
• The process is still progressing; Higher resistivity,Nested well structure,
structure Double SOISOI, Larger mask size,size
Stitching, …
• We welcome new users to the SOI pixel process.
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