SD Express (SD7.x)
Host Implementation Guideline

Design Guide | May 2020

1

SD Express (SD7.x) Host Implementation Guideline
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The information contained in this whitepaper is provided
as is without any representations or warranties of any kind.
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E-mail: help@sdcard.org

Specifications are subject to change without notice. Nonmetricweights and measurements are approximate. All data weredeemed correct a time of creation. SD Association is not liable forerrors or omissions. All brand, product, service names and logos
are trademarks and/or registered trademarks of their respective
owners and are hereby recognized and acknowledged.

Trademarks Notice:
SD and related marks and logos are trademarks of SD-3C LLC.
© 2019-2020 SD-3C LLC. All Rights Reserved.
Linux® is registered trademark of Linus Torvalds.
eMMC, UFS and UFS Card specifications originated by JEDECSATA (Serial ATA) is a specification originated by Serial ATA
International Organization (SATA-IO) which is owned today anddriven by INCITS T13 and T10 (SCSI)PCI Express® is a registered trademark of PCI-SIG®.
NVM ExpressTM and NVMeTM are trademarks of NVM Express, Inc.

2

SD Express (SD7.x) Host Implementation Guideline
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Table of Contents
1. Purpose And Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. SD Express Card – Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. SD Host Types That May Accept SD Express Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. SW Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Power and Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. SD Express and microSD Express Test Fixtures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix A: Common Thermal Conducting Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Appendix B: Off-The-Shelf SD Express Host Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 1 microSD Express and full size SD Express cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2 SD Express Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3 SD Express Host = SD and PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4 SD Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5 M.2/PCIe to SD7.x Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6 SD Express Host – Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7 Block Diagram of SD Express Host with new Control lines . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8 A Practical Example of Mux/De-Mux circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9 SD Host Controller Register Map with added SD Express Support . . . . . . . . . . . . . . . . . . . . 11
Figure 10 Flow Chart of Initialization process starts from PCIe drivers first . . . . . . . . . . . . . . . . . . . . . 13
Figure 11 Flow Chart of Initialization process starts from SD drivers first . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12 SD Express – Android Host Driver Layers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13 Flow Chart of the updated SD Drivers Operation during Initialization . . . . . . . . . . . . . . . 16
Figure 14 microSD Card and Host test adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15 microSD Express Test Adapter installed on standard CBB as PCIe add-in card . . . . . . . 18
Figure 16 microSD Express and SD Express Host Test Adapters may be inserted torelated SD Express hosts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17 Recommended PCB high level design concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18 Heat Pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19 Graphene Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table of Tables
Table 1 Voltage Ranges and Max Currents Allowed in SD Express card at PCIe mode  . . . . . . . . . 12
Table 2 NVMe Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3 Existing SD Drivers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4 Pros and Cons of Initialization options: SD-First or PCIe-First . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5 PCIe Power Substates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6 Card’s Maximum Card Case Temperature (Tc) allowed at each Power State . . . . . . . . . . . 17

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SD Express (SD7.x) Host Implementation Guideline
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1. Purpose And Scope
The SD Association (SDA) introduced SD Express via theSD7.0 and microSD SD7.1 specifications in anticipation of
new market demands for high performance applications
such as mobile computing, gaming and Internet ofThings (IoT) as well as opening new opportunities forremovable memory cards usage. SD Express integrates
PCIe/NVMe interface to the legacy SD interface for SD andmicroSD memory cards while maintaining full backward
compatibility.
The SDA prepared this document to provide
recommendations on how to implement SD Express into
host products to maximize the specification’s capabilitiesof the new PCIe/NVMe interface and maintain backwards
compatibility.

1.1 Referenced Documents
1.1.1 SDA Specifications:• Part 1 Physical Layer Specification Ver 7.0 (SD Express
full size introduced) referred hereafter as SD7.0 and its
Standard Size Mechanical Addendum Ver7.0.
• Part 1 Physical Layer Specification Ver 7.1 (microSD
Express added) referred hereafter as SD7.1 and themicroSD Card Addendum Ver 7.0. Note: When SD7.x
specification is mentioned, it relates to both SD7.0
and SD7.1.
• Part A2 Standard Host Controller Ver 6.0 – Referredalso as SHC. Note that SHC Ver 7 that will include
SD Express interface is under release process and is
expected to be available by mid-2020.
Note that only SDA members and host or card licensees may
get an access to the official SDA specifications. In order tobecome a member – please refer to this link.

Figure 1 microSD Express and full size SD Express cards

Also, the SDA published a simplified version of the above
mentioned specifications that non-members may download
for general study usage or drivers development. The
simplified specifications are not intended for product (cardor host) developments. Physical layer Simplified Specification
Ver 7.1 can be downloaded from the following link.
1.1.2 PCI-SIG Specifications• PCI Express Base Specification Revision 3.1a
PCI-SIG specifications may be downloaded from PCI-SIG sitethrough this link.

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SD Express (SD7.x) Host Implementation Guideline
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2. SD Express Card – Description
The functional interface:• In PCIe mode of operation, the card introduces itself
to the host as a standard “NVM Express Device” (PCIeClass ID: 01h->08h->02h; as shown in PCI Code ID
spec). This is the same as other NVMe devices like SSD
or M.2 devices, so standard PCI/NVMe drivers can be

SD Express and microSD Express memory cards are basedon SD Physical spec version 7.0 and 7.1, respectively. For
simplicity sake, we will refer to them both as SD Express
hereafter. Both have the same general block diagram, as
shown in Figure 2.
To simplify the concept, an SD Express card can beconsidered a traditional UHS-I memory card with the PCIeinterface and NVMe protocol.
SD Express Card Block Diagram
VDD1 3.3v

SD_DAT0/PCIe_REFCLK_P

SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
PCIe_PERST#
PCIe_CLKREQ#
PCIe_REFCLK_N

PCIe/NVMe
Interface

PCIe_REFCLK_P
PCIe_TX+
PCIe_TXPCIe_RX+
PCIe_RX-

PCIe_RX_P
PCIe_RX_N
PCIe_TX_P
PCIe_TX_N

Figure 2 SD Express Card Block Diagram

The physical interface:• The PCIe physical interface is as defined by PCI-SIG:
PCIe 3.1 specification, single lane.
• The SD Express adopted the PCIe 3.1 spec using thefollowing side band signals: PERST# and CLKREQ#.
• Power Supply of VDD2 = 1.8v (in addition to
VDD1=3.3v) is mandatory for the PCIe interface tooperate.
• Due to the limitation of space, the two side bandsignals and the REFCLK+/- signals are muxed with the
SD DATA lines.

5

Memory device

SD_DAT3/PCIe_PERST#
SD_DAT2/PCIe_CLKREQ#SD_DAT1/PCIe_REFCLK_N

Bi-directional
Mux/De-Mux

PCIe/SDMode

SD HostInterface
ModuleMemory management

SD_CLK
SD_CMD

CLK
CMD

DAT3
DAT2
DAT1
DAT0

CPU

SD/PCIe Mode indication

VDD2 1.8v

used to access the card in PCIe mode.
• SD Express card may be initialized either throughthe SD interface or through the PCIe interface. The
card may automatically recognize the PCIe mode ofoperation upon VDD2 supply from the host.
• If a host operates in PCIe mode, it may either:A. SD-First: Initialize the SD Express card through SD
interface first after power up of VDD1, check if card
supports PCIe, if it support PCIe it will switch to
PCIe mode by supplying VDD2.
B. PCIe-First: Access the card directly in PCIe moderight after power up of VDD1 followed by VDD2.
• Starting with SD interface initialization is recommended
because it allows faster initialization if a legacy
SD memory card is inserted. It is also the moststraightforward implementation without changing PCIeor NVMe drivers and has minimal effect on the overall
initialization time versus initializing through PCIeinterface (as further explained in section 5.4 below).
Bottom line:
Implementation of SD Express host is simple, because:
1. Existing PCIe interface may be used as is and existing
SD interface with minimal addition may be used.
2. A relatively simple hardware mux/de-mux unit needs
to be added at the front end allowing the separationof the PCIe side band and REFCLK+/- signals from the
SD DAT lines. There are readily available off-the-shelfdedicated units designed to perform mux/de-mux inthe market today, making implementation easy.
SD Express (SD7.x) Host Implementation Guideline
www.sdcard.org | ©2020 SD Association. All rights reserved3. As for software drivers, existing PCIe/NVMe drivers may be used. The only addition neededis the switching mechanism between SD drivers to PCIe and the control of VDD2 supply for
PCIe mode of operation that may be used also as the SD/PCIe mode selection for the front end
mux circuit. The SD drivers will require an update to support the new interface. That update is
expected to be contributed to the open source community (see the drivers section below).
4. Host vendors interested in implementing SD Express into host devices without having SD
Express cards may complete major portions of design verification processes by using SD
Express demonstration cards available from some card manufacturers. They can use theexisting PCIe interface for their PCIe interface mode tests along with legacy SD cards for their
SD mode tests. To complete host device electrical tests of the PCIe interface the existing
SD Express Card Load Boards that are available from SDA for the PCIe host electrical testing
may be used (as described in chapter 7). These tests may serve as preliminary host tests andmay complete a large amount of verification work until SD Express cards are released in themarketplace. Additional details are provided in the following sections.

3. SD Host Types That May Accept SD Express Card
SD Express Host

May operate ineither SD or PCIe

(SD+PCIe support)

Any of the following hosts can use SD Express cards:
SD Express Card

May operate ineitheror
PCIe
FigureHost
3 SD Express
Card
May SD
operatein Block
SD Express
SD Diagram
Express Card
SD mode only
SD Express Card
(SD+PCIe
SD support)
Host

SD Host6

May operate in
SD mode only

1. Host supporting both SD and PCIe interface (Figure 3):• Host and card can use either SD or PCIe interface operating the
SD Express card in either SD mode or PCIe mode.
2. Host supporting only SD interface (Figure 4):• Host and card will use SD pins operating the SD Express card in
SD mode.

SD Express Card

3. Host supporting only PCIe interface:This type of implementation is not backward compatible to legacy
Figure 4 SD Host
SD cards that use only the SD interface for access. Therefore, SDA is
not recommending implementation of such hosts, even though SD Express cards use a standard
PCIe/NVMe interface and it may be initialized through its PCIe interface. It can operate in such
host by operating the SD Express card in PCIe mode only. Such operation option is possible tobe used during development process and such option is described in section 3.2.

SD Express (SD7.x) Host Implementation Guideline
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3.1 SD Express Host
3.1.1 Pin out•		SD 7.0: Refer to Table 3.7.3-1 of SD7.0 Specification.
•		microSD 7.1: Refer to Figure 2-4, and Table 2-5 ofmicroSD Card Addendum Version 7.10 Specification.
3.1.2 Recommended Features
Refer to Section 8.1.3 to 8.1.6 of SD7.0 Specification for SD
7.x card supported, optional, not supported, and partially
supported features. SD 7.x Host is highly recommended
to support at least all mandatory SD 7.x card supported
features (Section 8.1.3 in SD7.0) on host side.
When designing an SD Express host device, consider thefollowing recommendations to best utilize SD Express card
capabilities.
SD Mode:•		Allow maximum power in default speed mode of SDXC
and SDUC cards by setting power control bit in ACM41,
XPC, to 1 as this is the maximum performance mode.
•		Send Power off notification to the card before turning
OFF the power to the card during idle time.
PCIe Mode:•		The SD Express PCIe interface uses CLKREQ# and
PERST# sideband signals only. The initialization
process/conditions should conform to the PCIe and
SD Express standard.
•		Support Single Lane (x1).
•		Support hot pluggable feature.
•		Host should allow SD Express card to work in fullswing operation mode (800mV) even though PCIeallows full swing operation and half swing operation.
•		Host should support the latest available NVMe 1.3+
(e.g., 1.3d at the publication of this document) toassure full backward compatibility and interoperability
to all cards in the market.
•		Support 1 namespace.
•		L1.1 and L1.2 power sub-states to be supported in
PCIe for power saving during standby.

7•		Host may manage power and thermal conditions
using card’s three power states: 0.72W, 1.44W and
1.8W (default) through the NVMe protocol.
3.1.3 Interface Detection and Initialization sequence
Refer to Section 3.17.2 in SD7.x for the initialization sequence
shown from host and card sides that covers all the cases. A
more detailed description of each specific case along withsignal diagrams can be found in Section 8.3.2 of SD7.x.

3.1 SD Host
Any legacy SD host in the market may support the operationof an SD Express card. In such a host, the SD interface of
the SD Express card will be used as guaranteed by the
specification. Speeds of SDR50 and DDR50 for microSD
Express will be supported while DDR50 in full size cards andSDR104 may also be supported if implemented by the cards.
Refer to section 3.17.2 in SD7.0 Specification for the SD
Express card internal state diagram. Initializing the card withlegacy SD host will move the card to its SD mode of operation
at the moment that SD CLK will be provided by the host.

3.2 PCIe Host
3.2.1 Interface Selection and Pinout•		As mentioned earlier – SDA is not recommending
implementation of PCIe host that does not support
SD, as this host will not be backward compatible toexisting legacy SD cards.
•		There is no issue to operate SD Express cards in PCIe
host because it supports initialization directly throughthe PCIe interface. Therefore, it can be used in such
ways for non-retail usage and for the development
process.
•		A standard PCIe 3 interface may be used on host sidewith the following considerations:- Side band signals used with SD Express card are
PERST# and CLKREQ#.
- Card Present Detect (PRSNT#) input shall besupported (as should be provided by any PCIeinterfaces supporting hot plug in/out).
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- In order for SD Express card to operate in PCIe
mode, it needs VDD1 (3.3v) and VDD2. (1.8v) powersources to be supplied plus VDD2 must be supplied
to the SD Express card after VDD1 is set to ON.
- SD Express card does not have internal AC coupling
capacitors on its PCIe output lines. The two AC
caps (176nF to 265nF as defined in PCIe standard)need to be added on host within a distance of up
to 12.5mm from the SD connector’s PCIe RX lanecontacts. Those caps are in addition to the AC
coupling caps already connected at the TX lane of
the PCIe lines of the host side.
• Refer to Section 3.7.3 and Table 3.7.3-1 of SD 7.0
Specification for SD form factor pin out.
• Refer to Section 2.4 and Table 2-5 of microSD Card
Addendum Ver 7.1 Specification for microSD pin out.
3.2.2 M.2/PCIe to SD 7.x Card Adapter
A practical example of PCIe Host usage for test and/or
development of PCIe interface of SD Express card may bedone through a M.2/PCIe Card to SD Express card adapter.
Such a solution may allow operation of SD Express card in
existing host that includes PCIe card or M.2 card slot. Figure
5 shows an example of an adapter card.

PCIe RX_lane_P/N AC caps
PCIe TX_lane_P/N

SD/uSD Express
SocketM.2 or PCIe slot

PREST#, CLKREQ#
PCIe_REF_CLK_100MHz
47uF
22uF

3.3V

DC-DC
Converter

1.8V

Figure 5 M.2/PCIe to SD7.x Adapter
Note that the 1.8V can be derived from 3.3V on the adapter board
using DC-DC converter as shown above (optional). The 1.8V supply
must be delivered to the card after the 3.3V supply is on.

8

3.2.3 Interface Detection and Initialization Sequence
Refer to section 3.17.2 in the SD7.0 specification for the
initialization sequence shown from host and card sides thatcovers all the cases. Use the PCIe direct path, not throughSD interface first. For the configuration shown in Figure 5,
host may use the existing standard PCIe/NVMe initialization
process and drivers. The card, as mentioned, will conform to
PCIe specification and introduce itself as standard NVMe
memory device.
3.2.4 Recommended Features•		SD Express host initialization process and conditions
should conform to the PCIe specification.
•		The host should support up to PCIe 3.1 with up to 985
MB/s and CLKREQ# + PERST# side band signals.
•		Support Single Lane (x1).
•		Support hot pluggable feature.
•		SD Express host should allow SD Express card to workin full swing operation mode (800mV).
•		Host should support the latest available NVMe 1.3+
(e.g., 1.3d at the publication of this document) to assure
full backward compatibility and interoperability to allcards in the market.
•		Support 1 namespace.
•		L1.1 and L1.2 power sub-states to be supported in PCIefor power saving during standby.
•		Host may manage power and thermal conditions usingcard’s three power states: 0.72W, 1.44W and 1.8W
(default) through the NVMe protocol.
Note: SD Express host is not required to recognize that theinserted card is an SD Express type of card. As mentioned, thecard appears as standard NVM Express device. However, incases where the host is aware of the existence of SD, and it
wants to read some of the unique SD registers information, it
may access it through some of the NVMe registers. For further
information, refer to Section 8.1.7 of SD7.0 Specification forregister mapping SD → NVMe/ PCIe.

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4. Hardware

In addition, there is a VDD2 (1.8v) supply to the card thatis required only for the PCIe mode. A possible solution is
to use an existing PCIe host module and existing PCIe/
NVMe drivers along with minimum changes in the SD hostcontroller with an added analog switch for the front end, is
recommended by SDA and described in the next paragraph.
Note that there are other solutions allowing use of existing
circuitry of PCIe interface from different vendors available
in the marketplace today. An example of such off-the-shelfsolution is provided in Appendix B.
The SD Express interface was defined in a way that existing
PCIe IP (supporting hot plugin) and SD host controller V3
may be used to implement the SD Express interface withminimal additions. The only challenge on the host side

9

PCIe/NVMe_
Interface_Enable
VDD2_ONTo PRSNT# of PCIe host interface

New

SD HostSD_DAT3
Controller SD_DAT2(At least 3.0) SD_DAT1
SD_DAT0PRSNT#

PCIe_PERST#
PCIe_CLKREQ#
PCIe/NVMe PCIe_REFCLK_N
PCIe_REFCLK_P

Interface(legacy with PCIe_TX_P
hot plugin PCIe_TX_N
PCIe_RX_P
support)

VDD2_ON
1.8v

Card Detect
SD_CLK
SD_CMDSD Express
Card Socket

VDD2
CLK
CMD

PCIe/SD
Mode

Bi-directional
Analog Switch

The PCIe interface used in SD Express card includes thefollowing three signal groups:•		Differential interfaces- PCIe_TX_P and PCIe_TX_N – Inputs to the card
- PCIe_RX_P and PCIe_RX_N – Outputs from the card
•		Differential CLK Interface- PCIe_REFCLK_P and PCIe_REFCLK_N – Inputs
to the card
These lines are muxed in the card with DAT0
and DAT1 of the SD interface•		Sideband Signals- PERST# – logic output from host to the card,
muxed in the card with DAT3 of the SD interface- CLKREQ# – Open drain I/O for both card and hostwith pullup on host side, muxed in the card with
DAT2 of the SD interface

System IO Registers

This section provides an overview of how a host may
utilize an existing SD host controller and existing PCIeinterface to implement the interface necessary to support
SD Express cards.

would be the handling of the switched signals. There arevarious ways to implement such switching considering thenature of the combined signals, especially if it is implemented
within a SoC. In this document a straight forward example of
Bi-Directional Analog Switch is shown. Any type of solutionthat meets the SD Express interface requirements is correct.

PCIe/NVMe Sys IO

4.1 SD and PCIe Host Interface withSD Express Socket

SD_DAT3/PCIe_PERST#
SD_DAT2/PCIe_CLKREQ#SD_DAT1/PCIe_REFCLK_N
SD_DAT0/PCIe_REFCLK_P

New

PCIe_RX_N

DAT3
DAT2
DAT1
DAT0

PCIe_TX+
PCIe_TXPCIe_RX+
PCIe_RX-Figure 6 SD Express Host – Block Diagram

The block diagram example of an SD Express host in Figure
6 shows a case in which host vendor, or chip-set vendor,
utilizes the existing PCIe host IP that supports hot plugin withcard presence detect PRSNT# input and SD Host Controller
with at least SD Host Controller (SHC) V3 specificationinterface with minimal addition of two new control registers
to implement a unified SD Express card interface.
The Bi-Directional Analog Switch shown is a functional
representation of various possible practical solutions that
may be implemented. Its functionality is to do the switching
between SD_DAT(3:0) lines and the side band signals + PCIeREFCLK, allowing a single functionality, at a single time,
towards the SD Express card – either as PCIe or as SD. It is
assumed that the PCIe/SD functionality is selected through acontrol line.
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SD Host

The VDD2 line supplied to the SD Express only for PCIe
operation mode may be used to switch the Analog Switch
to PCIe mode. Note that the PCIe/SD Mode control signal,used for the Switch, and VDD2 may be implemented as
separate control lines; however, it may be
Card Detect
GPIO2
VDD2_ONsimplified if VDD2 is used for the front end
SD_CLK
PCIe/SD mode selection (see example as
SD_CMDwell as the initialization flow charts shown in
SD_DATA0
Chapter 5).
SD_DATA1
SD_DATA2

Figure 8 shows a straightforward example of usage ofexternal discrete component serving as Bi-Directional Analog
Switch. Any type of solution that will meet the SD Express
interface requirements is acceptable.
Card Detect SW
5 SD_CLK
3 SD_CMD

7 SD_DATA0/PCIe_REFCLK_P
8 SD_DATA1/PCIe_REFCLK_N

EN

DC-DC
Regulator

1.8V
22uF

9 VDD2 ( 1.8V)

The Card Detection Mechanism in Figure
Off-the-shelf analog switch
PCIe/NVMe_Interface_Enable#
GPIO1
6 shows an existing SD socket card detect
PRSNT#
1 SD_DATA2/PCIe_CLKREQ#
switch connected to an existing SHC and the
2 SD_DATA3/PCIe_PERST#REFCLK_P
uSD Express
card presence detect of the PCIe interface
REFCLK_N
3V3
SocketR(PRSNT#) is connected to the output of the
4 VDD1 (3.3V)
CLKREQ#
47uF
Off-the-shelf analog switch
new SHC register (controlled by a new PCIe/PERST#
6, 10,13,16 VSS
AC Caps
TX_P
NVMe_Interface_Enable bit), allowing over all
11 PCIe_TX_P
TX_N
12 PCIe_TX_N
AC Caps
220nF
15 PCIe_RX_P
control of the drivers operations through the
RX_P
14 PCIe_RX_N
RX_N
220nF
SD drivers. Detailed description of new control
Figure 8 A Practical Example of Mux/De-Mux circuit
bits of registers (VDD2_ON, PCIe/NVMe_Interface_Enable and
PCIe/NVMe support) is provided in section 4.1.1 below.
The following are a few hardware considerations when
implementing the above example:
Figure 7 describes the SD Express Host connections with
•		Parasitic capacitance of multiplexer device should beemphasis on the new control lines and ability to performconsidered while selecting the multiplexer device andthe switching between SD and PCIe modes with theirdesigner should make sure the design meets the SI
associated drivers usage. A detailed flow chart of therequirements like jitter, insertion loss etc. for SD/PCIe
updated SD drivers that can support the given example isinterface as per SD Express specification.
shown in Section 5.4.
•		To support hot insertion of SD Express cards, hostSD Express Host
product design should provide enough capacitanceon host board on both VDD1 and VDD2 power rails
to reduce influence of voltage drop caused by hotStandard
PCIe interface
PCIe driverinsertion. See Host Power Deliver Network (PDN)
PCIe/NVMe
Card
Design Guide in Appendix E of SD 7.0 Specification forpresent
VDD2_ON control
Card_Detect
more details.
SD Express(Card

PCIe Host

SD_DATA3PRSNT#

PCIe/NVMe
Interface Enable
VDD2_ONSpecial SD
Express
Driver

VDD2_ON

PCIe/NVMe
Interface Enable#
VDD2_ON

Control added to
SDHC 3.0

SD Interface

Card
Detect

PCIe/SD mode

Insertion/Removal
Indication fromconnector’s switch)

PCIe/SD
Mux unit

Figure 7 Block Diagram of SD Express Host with new Control lines

10

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proposed register bit locations dedicated for SD Express areshown in Figure 9 as well. Additional details on the added
register bits are as follows:•		
VDD2_ON: Support of VDD2_ON was introduced in
SHC V4.0 (originally dedicated for the UHS-II interface)
and is described in the Power Control Register,
mapped as bit D04 in offset 29h. The same control bit
may be used for SD Express card. Turning on this bit
will connect VDD2 supply to the card as well as set thefront end Analog Switch in the host to PCIe mode.
• PCIe/NVMe_Interface_Enable: A new register area
is used for this new control bit – mapped as bit D00
to SD Express socket (< 12.5mm from Socket).
in offset 55h. This bit, if set to “1,” will assert PRSNT#
4.1.1 Proposed Additions to SD Host(to “0”) line connected to the PCIe host interface. The
PRSNT# line is available in PCIe host interfaces thatController – In Detailsupport hot plugin used originally as indication for
Additions to existing SD Host Controller that enable thecard insertion. Therefore, assertion of PRSNT# tells thesolution shown in Figure 6 are given below. Figure 9 shows
PCIe drivers to take the control and start to initiate
the lower range of the SD Host Controller Register Map (asthe card using the PCIe interface. The same way, if
provided in detail in the SD Host Controller Specification
PCIe/NVMe_Interface_Enable bit is set to “0”, PRSNT#
available for SDA members in SDA Website). The newlyis de-asserted (to “1”) which will indicate to the PCIe
host interface and drivers aboutcard removal.
• SD Express Support Indication:
Allowing the updated SD drivers
VDD2_ON: Use existing bit register
definition as appears in SHC ver 6.0 forto know whether the given SHC“SD BUS Power for VDD2”
supports SD Express interface the(just change the bit description to:“VDD2 Power On”)
Capabilities Register will be updated
PCIe/NVMe Support: Using reserved
to include a new bit indicating
bit D20 in capabilities register toindicate SHC supporting SD Express.
PCIe/NVMe Interface Support –If this bit is set to 1, it also means
1.8V VDD2 Support (D60) is set to 1
mapped as bit D20 in offset 40h.
If this bit indicates “1” (supporting
PCIe/NVMe_Interface_Enable: Define
new register using this reserved area.
SD Express) then bit 1.8V VDD2
Support (D60) in Capabilities
PCIe/NVMe_
Register is set to “1” as well.
Interface_Enable• The given components such as the analog Switch areprovided as an example for reference only. It is theimplementers responsibility to meet all the interface
electrical characteristics as defined in SD Express
specification.
• Updated SD drivers should take care of the selection
between the modes of operation by enabling/
disabling of VDD2 supply and indication to the PCIe
host unit about card insertion/removal.
• AC caps value can be from 176nF to 256nF for PCIe
Gen3 speed and these caps must be placed very close

Figure 9 SD Host Controller Register Map with added SD Express Support

11

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4.2 Power Supply

4.5 PCIe REFCLK guidelines

Table 1 describes the voltage ranges and max current levels
for SD Express card in PCIe mode of operation.

Refer to Section 8.2.3 and Table 8-3 of SD 7.0 Specification for
REFCLK specification.

Note that in any case, the card is not allowed to consume
more than 1.80W in total.

4.6 PCIe Sideband signals CLKREQ# and PERST#
Guidelines

Power Rail

Voltage Range

Peak Current [MaxAvg at 25usec (mA)]

Normal Current [MaxAvg at 1sec (mA)]

VDD1 (3.3)

2.7 - 3.6V

600

400

VDD2 (1.8)

1.7 – 1.95V

600

400

Table 1 Voltage Ranges and Max Currents
Allowed in SD Express card at PCIe mode

4.3 Hot Plug-in/Removal and Card Detection
The PCIe host should support Hot plug-in and removal.
It is highly recommended to turn off the power supplies
before card removal. An SD Express host should use thecard detection switch of the connector as the SD Express
card presence detection mechanism, which is the same asused by the existing SD Host Controller. The card presence
detection of the PCIe interface (PRSNT#) is connected to the
output of SHC, allowing the SD drivers to inform the PCIeinterface about card insertion/removal.
VDD2 shall be OFF while card is inserted. VDD2 should
be turned on only if PCIe interface is to be initiated andalways only after VDD1 was turned ON. VDD2 is used toswitch the front-end Analog Switch of the host to PCIe
mode as well as is one of the factors that will trigger cardto switch into PCIe mode.

4.4 PCIe Differential Voltage Swing
Refer to Section 8.2.2 of SD 7.0 Specification for differential
voltage swing details.
_____________(1) The listed sources are the companies known to the author at the publication
date. Any other SDA member that supply such connectors are welcome tocontact SDA office to be added in the given list.
(2) The listed sources are the companies known to the author at the publication
date. Any other SDA member that supply such connectors are welcome tocontact SDA office to be added in the given list.

12

Refer to Section 8.2.4 of SD 7.0 Specification for CLKREQ#
and PERST# electrical specification.

4.7 PCIe AC Coupling Capacitors
Refer to Section 8.2.5 of SD 7.0 Specification for A.C.
coupling capacitors placement guidelines.

4.8 PCIe TX/RX PHY Protection
Refer to Section 8.2.6 of SD 7.0 Specification for 3.3v IO tolerance
on PCIe TX/RX PHY.

4.9 ESD Recommendations
Refer to Section 6.8 of SD 7.0 Specification ESD Guidelines.

4.10 SD Express and microSD Express
Connectors Suppliers
4.10.1 SD Express Full Size Card Connector
The SD Express pads layout/location is identical to UHS-II;
therefore, any existing full-size SD UHS-II connectors that
operate in the desired speeds will work. It is recommended tocheck with the connector vendors for availability and supported
frequencies.
SDA members offering UHS-II connectors suppliers include:• Yamaichi - Link1 Link2• Amphenol ICC - Link
• Others1
4.10.2 microSD Express Connector
The microSD Express Card requires new connectors to be usedbecause the location and size of the second row is different fromthe microSD UHS-II cards.
microSD Express (SD7.1) connector suppliers:• Amphenol ICC - www.amphenol-icc.com/micro-sd-express• Others2
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5. SW Drivers
Before discussing the actual drivers - a flow
chart of two possible initialization processes
as defined in SD specification is shown in a
simplified manner. Figure 10 shows a casewhere the SD Express host initializes the SD
Express card through the PCIe interface. If theinitialization fails, it defaults to SD interface.
Figure 11 shows a case where the SD Express
host initializes the SD Express card first throughSD interface, checking if the card supports
PCIe then switches to PCIe mode.

Card Insertion Detect

Start SD CLK and initialization up
to CMD8

PCIe is supported

Check whether
PCIe is supported(R7 of CMD8)

PCIe Not supported
Continue SD initialization andoperation in SD mode

The example flows are simplified to assume that
PCIe and SD drivers can both be updated andmay control the transfer of control to the otherdriver. It is shown just for the sake of understanding thegeneral init flow. The solution provided in this document
allows change only of SD drivers while keeping the PCIe
drivers as is. The actual new flows that consider the
proposed HW above is given in section 5.4 below.

Stop SD CLKAssure PERST# asserted
and pullup on CLKREQ#(both done by PCIeinterface) and turn
VDD2 ON

Indicate to PCIe drivers to start
its initialization process

Proceed in PCIe/NVMe
operation

Figure 11 Flow Chart of Initialization process starts from SD drivers first

As shown, SD Express host or chipset providers can use
its existing PCIe and SD interfaces and combine themwith front end circuitry, that can be implemented either
externally to existing SoCs or inside a future SoC.

Card Insertion Detect

Regardless of the actual HW implementation, the host willneed to update its SW drivers to support the new SD Express
Assert PERST# and pullup on
CLKREQ# (as defined in PCIe training
Interface. Assuming that the host supports standard PCIe
process) and turn on VDD2
and NVMe drivers the only required update is to the SD
CLKREQ not asserted within 1mSdrivers as follows:
Wait for CLKREQ#Or PCIe Linkup failed
Turn VDD2 Off (not required by SD
asserted by card
express
spec
but
requiredfortheSDand PCIe linkup• Updated SD drivers supporting the new registers
Express Host Example shown
success
Indicate to SD drivers to start
proposed for the SHC that detect the SD Express card
its initialization process
Linkup process passed
type and perform the switch between the interfaces
Proceed with SD Initialization andProceed in PCIe/NVMe operation
operation(controls the VDD2 _ON and PCIe/NVMe_Interface_
Enable).
Figure 10 Flow Chart of Initialization process
starts from PCIe drivers first• In case that the host does not support NVMe, add
standard NVMe drivers above the PCIe, supporting astandard NVMe device interface.

13

SD Express (SD7.x) Host Implementation Guideline
www.sdcard.org | ©2020 SD Association. All rights reservedA description of the drivers layering in Android based
system is shown in Figure 12.
References to existing NVMe drivers and SD are
discussed in the following sections.
IMPORTANT: The proposed solution assumes usageof standard PCIe drivers (supporting hot plugin) while
the SD drivers need to be updated to support the newinit flow and switch control to/from SD/PCIe interface
as shown in section 5.4.

5.1 NVMe Drivers
Table 2 includes a list of a few available drivers for
NVMe for the various operating systems as provided in
http://www.nvmexpress.org/drivers/

Figure 12 SD Express – Android Host Driver Layers Overview

5.2 PCIe Drivers

Table 2 NVMe Drivers

14Standard PCIe drivers providing hot plugin are supported
by most of the OSs including Windows and Android (Linux/
Kernel). The Linux drivers can be found in the standard
Linux-Kernel code package: https://www.kernel.org/. The PCIe
Hotplug support is part of the whole package and can befound in the following kernel file tree: drivers/pci/hotplug/pciehp_hpc.c.

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5.3 Existing SD Drivers (for legacy cards)
Table 3 describes operating systems that support
existing SD drivers for SHC v3.0. SD Express updated
drivers will be required as described in section 5.4.
These new drivers are expected to be contributed tothe open source community and hopefully adopted

Table 3 Existing SD Drivers

by Windows.

5.4 The New SD Drivers Functionality
As mentioned earlier, in order to support the SD Express
Host example shown in Figure 7 only the SD drivers need
to be updated, in comparison to the SD-mode-only SHC
v3 drivers. Standard PCIe drivers that support hot plugin
and standard NVMe drivers may be used as-is. Figure 13
below shows more detail of the init flow of the SD Express
supported SD driver for SD-First case. The green blocks
relate to the SD driver and the blue to the PCIe drivers.

Case#

Inserted
card

Note that fallback option (switch PCIe mode to SD mode) inboth cases is not shown because it requires, for example, a
special OS Sys application that tracks the PCIe initialization
failure and provides the information to the SD drivers, andsuch information may not be provided directly from thestandard PCIe drivers. This application is not defined because
the fallback method relies on host system implementation.
Table 4 describes the advantages of one initialization process
over the other.

standard SD

Pros

Pros

Cons

#1 SD-FirstNo delayin init------#2 PCIe-First---1ms of PCIe training OR Linkup
time(in case that CLKREQ# ignoredby host) + OS App time if needed*

No
delay inInit

SD ExpressCons

Few mS delay due to SDs
74clks+CMD0+CMD8----(*) If we assume no change in PCIe driver then external OS Sys App is required to monitor for PCIe failure and inform the SD driver
The response time of such App is not so predictable, might take more significant time and therefore this option will not be discussed here
Table 4 Pros and Cons of Initialization options: SD-First or PCIe-First

15

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Enable the Card Insertion/Removal
interruptsA
Sleep(wait for interrupt)

Flow Chart of New SD Driver Process related to SD Express
Card
Insertion

Card
Removal- De-assert PCIe_PRSNT#- Turn Off VDD2Start SD CLK and Init up to CMD8A
Check whether PCIeis supported(R7 of CMD 8)

PCIe supported

PCIe Not supported- Stop SD CLK- Turn on VDD2 and assert PCIe/NVMe_Interface_Enable
A

Assertion of PCIe/NVMe_Interface_Enable asserts
PRSNT# to PCIe that initiate the PCIe driver
Continue in PCIe mode

Continue SD Init and operation in SD
mode

PCIe interface initialized:
Assure PERST# is asserted and pullup
on CLKREQ# - as defined in PCIe
training process
Continue PCIe training

Figure 13 Flow Chart of the updated SD Drivers Operation during Initialization

Host vendors should be aware that this interface supports
either legacy SD cards or SD Express cards. But for SD
Express cards, there is no fallback to SD option proposedin the rare chance of a malfunctioning PCIe interface.
SDA recommends implementation of the SD-First option
using an updated SD driver that can handle the switch
between either SD mode or PCIe/NVMe mode. This16

prevents SD Cards without the PCIe interface to go throughthe trial of PCIe and the subsequent time consuming
re-tries. As long as standard PCIe drivers are used – theoption of SD-First (without fallback option) is both thesafest and fastest solution.

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6. Power and Thermal Management
Power consumption affects two main aspects: Consumed
Energy, or power over time, which impacts battery life; andthermal issues arising from high power generating heatthat needs to be controlled and kept under the maximum
allowed temperatures.

by the card. SD Express specification defined three power
levels supported by any SD Express card as following: 1.8W
(default), 1.44W and 0.72W (Refer to Section 8.1.8 in SD7.x
specification for further information).

Following are the main two PCIe/NVMe features that should
be used by the host to take control over the above two issues.

usage by NVMe is provided in the NVMe Specification, Section 8.4.

6.1 PCIe Power Management
PCIe interface supports several Power Modes (PM) that
control the consumed power in idle state by setting internalvarious configurations of the differential interface as shownin Table 5. Each state might have different power vs. wakeup time characteristics.
For longer battery life host should support L1.0 and its
substates (L1.1 and L1.2) along with the control of CLKREQ#
signal (as introduced by PCIe 3.1) for maximum powersaving during idle mode.

The detailed description of the Power States structure and

For SD Express card operates in SD mode the same power
levels (1.8W, 1.44W and 0.72W) are supported and controlled
through the existing SD power modes control mechanism.
A SD Express host will use the NVMe power states for thermal
management assuming that limiting the card’s power
consumption should reduce the card’s case temperature.
Refer to the thermal management feature in NVMe Protocol
Section 8.4.5 for more information.

Table 6 Card’s Maximum Card Case Temperature (Tc)
allowed at each Power State

Host need to maintain card case temperature at a given
power state as shown in Table 6 (as shown in section 3.7 ofmicroSD Card Addendum version 7.1 and section 3.6 of Standard
Size SD Card Mechanical Addendum version 7.0 )Table 5 PCIe Power Substates

For more information, refer to power management featureusing L1.1 and L1.2 PM substates recommended in PCI-SIG
V3.1a Chapter 5.5.

6.2 NVMe Power States
NVMe specification supports the Power States featureallowing the host to control the maximum consumed power

17

In order to utilize best performance capabilities of the card,
it is recommended for host vendors to conduct a full systemlevel thermal simulation to arrive at optimized thermal design.
Following are some of the ways to counter thermal challenges:• Host PCB/s design• Connector design• Heat pipe
• Heat sink and fan• Graphene tapeThis document includes some commonly used ideas forthermal solutions in Appendix A.
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7. SD Express and microSD Express Test
Since SD Express is using a standard PCIe interface andintroduces itself as a standard NVMe device, any standard
off the shelf test equipment used for PCIe electrical andprotocol tests and NVMe protocol tests may be used to test
the PCIe/NVMe interface of the card side or host side.
SDA has built SD Express test fixtures that serve as adapters
to existing PCI SIG Compliance Load Board as well as
adapters for host testing. Those test fixtures are available by
SDA or any of our approved test labs.
Figure 14 to Figure 16 show pictures of the available test
fixtures. Card and host manufacturers may use them in thetest labs or in their own facilities and utilize existing PCIe/
NVMe test equipment to perform compliance tests used by
PCI SIG.

Figure 15 microSD Express Test Adapter installedon standard CBB as PCIe add-in card

Figure 16 microSD Express and SD Express Host Test Adapters
may be inserted to related SD Express hosts

Figure 14 microSD Card and Host test adapters

18

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Appendix A: Common Thermal Conducting Solutions
In addition to the power throttling mechanism
mentioned in section 6.2, a thermal management
and control require also a proper mechanical systemdesign considering the thermal issues. There arevarious methods used today in the industry. Someof the commonly used methods are provided in thisAppendix.

A.1 Host PCB/s Design
Proper thermal isolation from other heat dissipating
elements and more PCB area around socket, in general,
helps in heat spreading.

Figure 17 Recommended PCBhigh level design concepts

A.2 Heat Pipe
Host may use heat pipe for their processors.
Research shows use of exclusive heat pipe helps
to reduce card temperatures considerably.

Figure 18 Heat Pipe
Source: https://commons.wikimedia.org/wiki/File:Heat_Pipe_Mechanism.png
Note: Careful routing of heat pipes required, to take theheat away from hotspot to the colder regions in the system.

19

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A.3 Graphene Tape
Heat spreader tapes are used often in all electronic
devices to lower the hotspot temperature. In similarlines, it is recommended to use graphene tape thatshowed temperature drop of few degrees as per
related research. Thicknesses ranging from 20-50
um are available in the market. Two methods ofusing graphene tape may be considered. First,
it may be applied on the card itself. Second, themore beneficial method is to apply the tape on
the connector and PCB covering as much large
area as possible. It can be used as layer above cardconnector to uniformly distribute heat.

Figure 19 Graphene Tape

Reference: https://www.researchgate.net/publication/271551161_Characterization_for_graphene_as_heat_spreader_using_thermal_imaging_method

A.4 Connector Design
Minimizing thermal resistance between card/connector and between connector/host is critical.
Changing connector material from stainless steel to brass or copper and having better thermal
contact between connector and PCB to reduce air cavities helps to reduce card temperature.

A.5 Heat Sink and Fan Assembly
The proven heat sink and fan assembly is a go-to option in case there are no space constraints.
Recommended to use blower type fan to get focused jet of air over the heat sink.

20

SD Express (SD7.x) Host Implementation Guideline
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Appendix B:
Off-The-Shelf SD Express Host Solution
There are existing off-the-shelf SD Express host solutions available in the market that productmanufacturers may choose to adopt in case it fits their needs.
BayHub Technology provides a solution for SD Express (SD7.x) Host Controller implementation
as described in the following here: http://www.bayhubtech.com/upload/Image/20200414/202
00414013403_92715.jpg
Other off-the-shelf solutions may be available in the future3.

_____________(3) The listed resources are companies known to the author at the publication date. Any other SDA
member that supply such solutions are welcome to contact SDA office to be added in the given list.

21

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