Reduction techniques of the back gate effect in the SOI Pixel Detector
R. Ichimiya a, Y.Arai a, K. Fukuda b, I. Kurachi b, N. Kuriyama c, M. Ohno d, M. Okihara cfor the SOI Pixel collaborationaInstitute of Particle and Nuclear Studies, High Energy Accelerator Research Org., KEK, Tsukuba 305-0801, Japanb
Oki Semiconductor Co. Ltd., 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japanc
Oki Semiconductor Miyagi Co. Ltd., 1, Okinodaira, Ohira-mura, kurokawa-gun, Miyagi 981-3693, Japand
National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba 305-8568, Japanryo@post.kek.jp
Abstract
We have fabricated monolithic pixel sensors in 0.2 µm
Silicon-On-Insulator (SOI) CMOS technology, consisting of a
thick sensor layer and a thin circuit layer with an insulating
buried-oxide, which has many advantages. However, it has
been found that the applied electric field in the sensor layer
also affects the transistor operation in the adjacent circuitlayer. This limits the applicable sensor bias well below thefull depletion voltage. To overcome this, we performed aTCAD simulation and added an additional p-well (buried pwell) in the SOI process. Designs and preliminary results arepresented.

I. INTRODUCTION
A Silicon-on-Insulator (SOI) CMOS technology has a lotof advantages to realize a high-speed and low-power LSI
circuit. Nowadays, SOI CMOS technology is widely used forcommercial and industrial production. SOI technology
enables a monolithic pixel detector by bonding thick highresistivity silicon for sensor and thin low-resistivity silicon forreadout electronics interleaved with an insulating buried oxide
layer (BOX). Contacts between the sensing nodes of thesensor layer and the readout circuitry are made through theBOX layer [1-3]. Compared to conventional bulk CMOS
pixel sensors, SOI pixel sensor has following advantages:lNo mechanical bump bonding is required;minimizing multiple scattering in the detector andmaking smaller pixel size is possible.

l

Small parasitic capacitance (~10fF) of sensing nodes
gives a large conversion gain and lower noise.

lSmall active volume in each transistor ensures latchup immunity and high radiation tolerance.

lBoth sensor and readout electronics can be fabricatedwith the industry standard SOI process; furtherprogress and lower cost are expected.

Figure 1: Cross-sectional view of the SOI pixel detector

We have been developing an SOI pixel process based on OKI
Semiconductor Co. Ltd., 0.2 µm CMOS fully-depleted (FD-)
SOI commercial mass-production process [4].

II. SOI PIXEL PROCESS
Figure 2 shows a simplified procedure for the fabrication
process of the SOI pixel detector. After etching BOX layer,
implantation of p+/n+ to handle wafer is performed, thencontacts between the p+/n+ wells and the 1st metal layer areformed.
After wafer processing, the wafer backside is groundmechanically from 725 µm to 260 µm, then sputtered with
200 nm of aluminum. The detector bias voltage can be applied
from the backside and also from the top pads which areconnected to a high voltage n+ ring.
Characteristics and SOI process parameters are
summarized in Table 1. Three types of transistors, MetalInsulating-Metal (MIM) capacitors, depletion MOS (DMOS),
lateral diodes and several kinds of resistors are provided.

Figure 2: Conceptual SOI pixel detector process flow.
Table 1: SOI pixel process specifications.

Process

SOI wafer

BacksideTransistor

Optional
process

0.2 µm Low-Leakage Fully-Depleted SOICMOS,1 poly, 4 Metal layers, MIM cap., DMOS
option,Core (I/O) voltage = 1.8 (3.3) VDiameter: 200 mm φ
Top Si: Cz, ~18Ω-cm, p-type, ~40nm thickBuried Oxide: 200 nm thickHandle wafer: Cz n-type 700Ω-cm, 725 µm
thickThinned to 260 µm, and sputtered with Al(200 nm)
Normal and low threshold transistors areavailable for both core(1.8V) and IO(3.3V).
Three type of structure (body-floating,source-tie and body-tie) are available.
Buried p-well (BPW) formation.

We have been organizing Multi Project Wafer (MPW)
runs periodically to reduce development cost and shareknowledge. We have three MPW runs in 2009. In each MPWrun, we have about 15-20 designs from SOI pixel
collaborators [5-7]. This MPW runs are open to any academicusers.

Figure 3: A TCAD simulation result of electron current density
distribution of a core NMOS transistor is displayed. (Vd=0.1V,Vg=Vs=0V) Under a backside bias voltage Vback = 30V is applied, acurrent path is formed (back side channel) below gate at lower
surface of the SOI layer (displayed in orange color). Note that thegate electrode (gray) in this plot is not in scale.

Based on this TCAD simulation study, we have introduced
buried p-well (BPW) implantation process in the handle wafer.
A p-type dopant is implanted through the top Si layer to forma p-well just below the buried oxide (BOX) layer (Figure 4).
The doping level of BPW is about three orders lower than thatof the p+ sensor node and source/drain region, so it does notaffect transistor’s characteristics. We have optimized theimplantation energy by a TCAD process simulation so that thepeak density is located under the BOX region.
Figure 5 (6) shows the Id-Vgs curve of an NMOS (PMOS)
transistor of a TEG chip when the backside bias voltage isapplied. Especially NMOS transistor is affected by appliedbackside bias voltage. However, by introducing BPW, theback gate effect is effectively suppressed for both NMOS andPMOS transistors.
Top Si (SOI)
BOXIII. BACK GATE EFFECT REDUCTION TECHNIQUE
While the SOI structure is ideal for realizing themonolithic pixel detector, applied electric field in the sensor
layer also affects transistor operation in the adjacent LSI
circuit layer (back gate effect). Due to this phenomenon,
sufficient bias voltage to make the sensor fully depleted could
not be applied. To understand the back gate effect in detail,
we performed a TCAD simulation. Figure 3 shows the TCAD
simulation result of the electron current density distribution ofa core NMOS transistor. When a backside bias voltage Vback =30V is applied, a current path is formed (back side channel)
below gate at lower surface of the SOI layer (displayed inorange color). During the back side channel is open, thetransistor remains ON even if negative gate voltage is applied.

Figure 4: Buried p-well (BPW) implantation method is shown. By
implanting light p-type dopant under the BOX layer, the back gateeffect is effectively suppressed. In the pixel, BPW can be used toextend the sensor node.

A. Integration type pixel (INTPIX)
The integration type pixel (INTPIX) has 5 mm by 5 mmchip size and 128 x 128 pixels each 20 µm square. Figure 8
shows a readout circuit implemented for each pixel. Thedetector signal is buffered by a source follower and thenstored in a 100 fF capacitor (Cstore). When read_x is asserted,
Vstore is readout by an external ADC.
Figure 9 shows a visible light image taken by the INTPIX
detector.

Figure 5: Measured NMOS Id-Vgs curves without BPW (left) andwith BPW (right) shown for various backside bias voltages.

Figure 8: Readout circuit of integration type pixel (INTPIX).

Figure 6: Measured PMOS Id-Vgs curves without BPW (left) andwith BPW (right) shown for various backside bias voltages.

IV. PIXEL DETECTOR TEST RESULTS
Figure 7 shows the SOI pixel sensor I-V characteristics.
The break down voltage depends on the guard ring geometry
and the BPW layout. The BPW layer reduces electric field
gradients at critical points, so it increases the break down
voltage.
We are developing two kinds of pixel detectors. One isintegration type pixel detector named INTPIX. The other iscounting type pixel detector named CNTPIX.
Figure 9: A visible light image taken by the INTPIX detector with amask.

B. Counting type pixel (CNTPIX)
Figure 10 shows a readout circuit for each pixel of thecounting type pixel (CNTPIX). The preamplifier circuit isbased on the design proposed by Krummenacher [8] whichcontains leakage current compensation circuitry. It isequipped with low and high threshold discriminators so thatwindow comparator mode is possible. Discriminator output is
fed to a 16-bit counter. The size of a pixel is about 60 µmsquare.
Figure 11 shows an 8 keV X-ray image taken by theCNTPIX detector with a brass mask in front.

Figure 7: I-V characteristic of SOI pixel sensor (INTPIX3).

applied bias voltage has to be overcome. We have developed
a BPW implantation technique and confirmed it to suppress
the back gate effect effectively.
We have been organizing MPW runs to share runs withdesigns from SOI pixel collaborators. Two types of SOI pixel
detector (integration type and counting type) has beendeveloped and confirmed of their functionality.

VI. ACKNOWLEDGEMENTS

Figure 10:

Readout circuit of counting type pixel (CNTPIX).

This work is supported by Japan Science and Technology
Agency (JST) financially, also is supported by VLSI Designand Education Center (VDEC), the University of Tokyo incollaboration with Cadence Corporation and Mentor Graphics
Corporation.

VII.

REFERENCES[1] Y. Arai, `Electronics and Sensor Study with the OKI
SOI process’, Proceedings of Topical Workshop on
Electronics for Particle Physics (TWEPP-07), CERN-2007007, pp. 57-63.
[2] Y. Arai, et al., `SOI Pixel Developments in a 0.15 mmTechnology’, 2007 IEEE Nuclear Science Symposium
Conference Record, N20-2, pp. 1040-1046.
[3] SOIPIX Collaboration, http://rd.kek.jp/project/soi/[4] K. Morikawa, Y. Kajita, M. Mitarashi, `Low-PowerLSI Technology of 0.15 µm FD-SOI’, OKI Technical Review,
Issue 196, Vol. 70, No. 4, pp. 60-63, 2003.
[5] M. Battaglia, et al., Nucl. Instr. And Meth. A583,(2007) 526.
Figure 11:

X-ray image taken by counting type pixel(CNTPIX).

V. SUMMARY
We are developing SOI pixel detectors based on 0.2 µm
OKI Semiconductor FD-SOI commercial mass-production
process. While the SOI structure is ideal for realizing themonolithic pixel detector, the back gate effect caused by[6] D. Kobayashi, et. al, IEEE Trans. Nucl. Sci. Sci., Vol.
55 (2008) p.2872[7] K. Hara, et. al, IEEE Trans. Nucl. Sci., Vol. 56, Issue 5(2009), pp. 2896-2904[8] F. Kurmmenacher, Nucl. Instr. and Meth. A305(1991)
527.