KEK Seminar
28 January 2015
TsukubaR&D on SOI Counting Pixel Chips
Yunpeng Lu
Institute of High Energy Physics(IHEP)
Beijing, CHINA
E-mail: yplu@ihep.ac.cn

JUNO Exp.
•••

20K ton liquid scint.
3% energy resolution(at 1MeV)
700-meter deep underground2

Outline• Introduction to SOIPIX• Motivation of Counting Pixel R&D• Nested-Wells-based design– CPIXTEG2 by A-R-Tec– CPIXTEG3• DSOI-based design– CPIXTEG3b• Summary3

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SOIPIX Collaboration

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Outline• Introduction to SOIPIX• Motivation of Counting Pixel R&D• Nested-Wells-based design– CPIXTEG2 by A-R-Tec– CPIXTEG3• DSOI-based design– CPIXTEG3b• Summary7

Motivation(1)•Counting Pixel is an effective measure to study shielding effect in SOIPIXdetectors.
– A key issue in SOI Pixel Technology– Necessity of shielding recognized and understood by F. X. Pengg– Counting pixel suffered from charge injection most, while integrating pixel notsensitive to it.
9.4kΩ/□

0.2kΩ/□ not compatible with current process8••

more recent version: Nested-Wells
more fancy thing: Double SOI…

••

Shielding-well proposed by F. X. Pengg in hisdissertation “Monolithic Silicon Pixel Detectors in
SOI Technology”
Good in concept but not implemented successfully.

Motivation(2)•Counting Pixel is getting more and more popular in synchrotron radiation
application due to superior performance.
– Macromolecular Crystallography, Small-Angle Scattering (SAXS) etc.
– Fast readout / no readout noise / High dynamic range /Sharp point spreadfunction•Targeted on the detector proposed by Prof. Shunji Kishimoto (PF, KEK).
– Very compact pixel circuit– Very good S/N requiredSpecifications:
30*30 um2 pixel size
1k frames/s
14-bit counter
Low energy X-ray 2~4 keV

9Fundamental Issues•

On-chip circuit– Amp-Sha-Disc system– Counter and register in pixel•

Shielding (Charge Injection)

Preamplifier

Shaper-A-A– Nested-wells– Double SOI•DACCounter

Discriminator

Leakage current– Full depletion guaranteed– Contribute to noise level but can be mitigated by low temperature•

Radiation damage– Fine if back-illuminated by low energy X-ray10

Outline• Introduction to SOIPIX• Motivation of Counting Pixel R&D• Nested-Wells-based design– CPIXTEG2 by A-R-Tec– CPIXTEG3• DSOI-based design– CPIXTEG3b• Summary11

Amp-Sha-Disc in CPIXTEG2PreampliferShaper

Dual Discriminators

••

•

•
•

1000-10000eCf ~4fF

Vgain 2.5

A-R-Tec

Threshold window
Hysteresis

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A-R-Tec

Feedback and Leakage Compensation•The krummenacher scheme used for preamplifier and shaper– High gain amplifier in the core
– Leakage compensated by M2– Feedback current set by Ib = I1 - I2
– Vout DC set by Vref•

Very popular in pixel circuit but it relys on the precise I1 and I2– Failure if I2 > I1I1-AI2
The krummenacher scheme for P-in-N sensor

13

A-R-Tec

Discriminator•Hysteresis to avoid noise hit– Vtn, threshold for a Low to High transition– Vtp, threshold for a High to Low transition– Vhyst > 3σnoise•

Global threshold set by Vth– Local adjustment by a 4-bit DAC in pixel

VinVthPrinciple of hysteresis

Bit3 Bit2 Bit1 Bit0
4-bit DAC

Schematics of discriminator and DAC14

A-R-Tec

Discriminator•Hysteresis to avoid noise hit– Vtn, threshold for a Low to High transition– Vtp, threshold for a High to Low transition– Vhyst > 3σnoise•

Global threshold set by Vth– Local adjustment by a 4-bit DAC in pixelVinVthPrinciple of hysteresis

Bit3 Bit2 Bit1 Bit0
4-bit DAC

Schematics of discriminator and DAC

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A-R-Tec

Layout••••Chip size 5mm*5mm
Pixel size 64um*64um
16-bit Counter & 10-bit Register
Amp-Sha covered by Nested-wells– Bias voltage limited due to back gate effect
64um

5mmCOUNTERCPIXTEG2 Chip layout

DISCRI.
AMP&SHP
REGISTER
Nested-Wells

CPIXTEG2 Pixel layout

16Overview of CPIXTEG2 results
•

A-R-Tec

Amp-Sha-Disc system
Counter and Register
Bias and Aobuf
Current Source variation
Counter & Register access Shielding between analog
and sense node Response of Light stimulus• Shielding between counterand sense node not reported
analog waveform17

Circuit behaviors A-R-Tec
withsensor connected
Vb=20V

Vb=20V

Vb=1V

 Crosstalk between BPW andTransistors observed.
 Nested-wells is effective inshielding shaper.
• Shielding of discriminator andcounter not evaluated yet.
• Failure of current mirror,
overridden by external port.

VL_FB_AMP_N

Vb=20V18

Outline• Introduction to SOIPIX• Motivation of Counting Pixel R&D• Nested-Wells-based design– CPIXTEG2 by A-R-Tec– CPIXTEG3• DSOI-based design– CPIXTEG3b• Summary19

Continuing efforts of Nested-wells on CPIXTEG3•

Expand Nested-wells to full pixel– To suppress back gate effect– To evaluate shielding of digital part
– But large Cd due to BNW/BPW junction•More BNW contacts– BNW ~10KΩ/□•A few bugs fixed

BPW&BP2BNW
NS1BNWcontact

CPIXTEG2 pixel layout
CPIXTEG3 pixel layout

PSSenseNode20Measurement of crosstalk from discriminator••

Repeated all results on CPIXTEG2
And found more:– Discriminator crosstalk if overlapped with nested-wells

PREAMPSHAPER

Disable Disc.
via VH2

Discriminator_High
Discriminator_Low

1. Charge
Injection with
Discr. working

Vtest = 600mV;
VL_AMP_N = 280mV;
Vdet = +5V

2. Charge
injection with
Discr. stopped21

Measurement of crosstalk from counter•

Counter driven by external clock–•

Watch the analog output

Counter crosstalk large

SHAPER– Clearly pattern related– Largest on the transition between
all 1’s and all 0’s– Varing Vbnw and Vback, no change•

PREAMP

DO_14
Counter_clk

Not sufficient shielding
X011_1111_1111_1111
X100_0000_0000_0000

16 clks

X100_0000_0000_0111
X100_0000_0000_1000

16 clks

X100_0000_0001_0111
X100_0000_0001_1000

X100_0000_0010_0111
X100_0000_0010_1000

X111_1111_1111_1111
X000_0000_0000_0000

Outline• Introduction to SOIPIX• Motivation of Counting Pixel R&D• Nested-Wells-based design– CPIXTEG2 by A-R-Tec– CPIXTEG3• DSOI-based design– CPIXTEG3b• Summary23

Design consideration for CPIXTEG3b•

A constant feedback current scheme adopted– The krummenacher scheme would fail due to mismatch of current mirrors.

•Diode-biased-inverter discriminator– Narrow threshold spreading reported•

Cut the pixel smaller– 2->1 discriminator– 16->6 bits counter– 10->6 bits register– 64um->50um pixel pitch••

New shielding scheme based on DSOI process
Larger pixel array– 64*6424

Constant Current Feedback•

A constant current feedback used for Preamp and Shaper––––•

High gain amplifier in the core
M1 in linear region and compensate leakage current when no hit
M1 in saturation region and discharge Cf by copying Ib after a hit
Avoid the risk of failure as in the krummenacher scheme

Used in the ATLAS FEI pixel chips
A constant current feedback scheme-A25

Noise analysis by HSPICE simulation•

Noise @ PREAMP Output•

Noise @ SHAPER Output– no = 1.4mV– equivalent to 70 eENC (e-)– no = 6.8mV– equivalent to 57 e-ENC @ Shaper Output

120

Cd=100fF;
Cf=5fF;
Ccouple = 30fF
Ifb_preamp = Ifb_shaper = 1nA;

100y = 0.4089x + 14.856
80

60

Leakage Current Noise not Included
1/f noise and channel thermal noise included

40

20

0050

100

150

200

250

Cd (fF) 26

Diode-biased-inverter discriminator••

AC coupled, baseline of shaper blocked
Threshold voltages equals Vdiode /A

Diode-biased-inverter discriminator– Ithr = Is(eVdiode/VT -1)– VT = kT/e••-A

Limited range of possible threshold
Low threshold dispersion

Vdiode– 120e without threshold trim reportedThreshold dispersion
reported on PILATUS chip
NIMA 465 P235

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Simulation of PSD system
Ithreshold (I0) =40nA, input charge = 750e- to 2000eDiscriminator

ShaperPreamp28

Threshold adjustment•

Simulated Range: 25nA - 150nA–•

740-2920 e- in terms of input charge

Ithreshold tuning step: 2-5nA– 4-bit DAC
Threshold in terms ofinput charge(e-)
3500

I threshold

Threshold in termsof input charge (e-)

25nA743.7575nA

1618.75

125nA

2487.5

150nA

2925

3000

y = 17.441x + 308.69

2500

2925

2487.51nA ~ 17.4e2000
1618.75

1500

1000
743.7550000204060

80

100120140160

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Ithreshold (nA)Layout• New design freedom enabled by DSOI process(compared to Nested-wells)– SOI2 covers the full pixel as the shielding layer– Charge collection electrode overlaps with Preamp & SHP only, Cd ~ 100fF•DSOI contacts in between counter and collection electrode.
– 170kΩ/□ SOI2 layer•50um

Local bypass capacitors– Analog and digital power line
– SOI2 shielding line

•CounterBackgate/Shielding/Cd/CCE– First chips delivered on normal SOI wafer– DSOI chips to be delivered in Feb. 2015

SOI2 contacts

50um

Disc.

PREAMP

MOS
SOI2
BNW

SHP
Regiter

16um
P TypeSingle pixel in cross section

Pixel layout of CPIXTEG3b30

Pixel Circuit without sensor connected(1)•The new Amp-Sha-Disc system proved working!
– Safe to dismiss the glitches which were caused by output buffer

PREAMPSHAPERDISCRIMINATOR

Vtest_pulse = -200mV equivalent to ~4800eIthreshold = -113nA equivalent to ~ 2000e31

Pixel Circuit without sensor connected(2)•S-curve measurement– Noise– Threshold in terms of input charge•

Noise of analog system without sensor connected(Cd ~ 0)
– ~27e-, consistent with simulation•

Measured threshold agreed with simulation– Discrepancy due to different Cd and variation of Gain

Threshold in terms of inputcharge(e-)# of test pulses passed
discrimination (normalized)
1

4000

0.9

3500

0.8

3000

0.7
0.6

2500

0.5

2000

0.4

1500

0.3
0.2

SimulatedMeasured

Input charge ~ 1200e

10000.1

5000075808590

Ithreshold(nA)

95050100150

Ithreshold(nA)

20032

Pixel Circuit with sensor connected(1)•Managed to operate the circuit with sensor connected (No shielding at all!)– Vb = -4.2V– Vgain of shaper decreased andstopped oscillation.
– Input charge ~10ke– Counter off

PREAMPSHAPERDISCRIMINATOR

Vtest_pulse = 400mV, Ifb_shaper = -10nA
Counter off
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Pixel Circuit with sensor connected(2)• Counter on•

Amplitude of crosstalk is related tothe pattern of counter– Input charge ~ 20ke– The worst case is all 1’-> all 0’s

Counter transition:
63->0

Counter transition:32->3334

Counting results of a single column
Counting results

Counting results•

Input charge applied to column 0– 64 pixels– Pixel63 without sensor, counting correctly.
– Other pixel connected to sensor, a few
noise hit recorded.

•
Test pulse number

Further investigation needed.
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Counting results of the whole pixel array•

Input charge applied to the whole pixel array except column 0– 64*63 pixels– All pixels alive!

36Counting results of pulsed laser beam•

Pulsed infrared laser beam
– 1064nm– A few 100ps– ~200um in diameter– ~pJ/pulse•

Two adjacent pixels responded to thelaser stimulus and counted the pulses– A proof of principle!
Counting results

Laser pulse37number

Outline• Introduction to SOIPIX• Motivation of Counting Pixel R&D• Nested-Wells-based design– CPIXTEG2 by A-R-Tec– CPIXTEG3• DSOI-based design– CPIXTEG3b• Summary38

• Findings & Achievements– Nested-wells is effective to shield shaper, but not sufficient to shield counter– On-chip circuit works well
– Obtained very encouraging results of counting laser pulses– Firmware and software developed, well prepared for the forthcoming DSOIchips.

•Considerations for further optimization– Very compact memory cell developed by Prof. Kurachi is now ready for user.
– Option of a low power auto-zero comparator as discriminator– Option of a SDD-like sensor structure proposed by collaboration members in
Shizuoka U.
All efforts point to a counting pixel chip with: 30*30 um2 pixel size
 1k frames/s 14-bit counter Low energy X-ray 2~4 keV

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AcknowledgementsColleagues and Graduate students at IHEP:Qun Ouyang, Yi Liu, Hongyang Xin
and at collaborating institutes:
Yasuo Arai, Toshinobu Miyoshi, Ayaki Takeda(Kyoto U. now), Yukiko Ikemoto,Shunji Kishimoto (KEK)

Masao Okihara, Naoya Kuriyama, Noriyuki Miura, Hiroki Kasai (Lapis)
T. Imamura (A-R-Tec)

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