Pixel DAQ for the ATLAS upgrade R&D
DTP Seminar @ KEK
30 October, 2015
Minoru Hirose
Tokyo Institute of Technology

Chapter 3

LHC-ATLAS• LHC:The ATLAS experiment

The ATLAS1) detector is one of the general purpose detectors at LHC. The detector surrou
the interaction point and the beam pipe hermetically. It consists of cylindrical layers andend-caps. The detector is 44 m in length and 25 m in height, and has a weight of approxima
7000 tons. Figure 3.1 shows the full ATLAS detector. The detector components, calle
subsystems, are categorized into the inner tracker, the electromagnetic and hadron calorim
and the muon spectrometer, from inside to outside. Besides, the ATLAS detector is equipwith the magnets and the forward detectors.

ATLAS➡ World’s largest collider.
➡ Run-II operation is ongoing.
➡ Proton beams @ √s=13 TeV.
➡ Inst. Lumi. ~5×1033 cm-2s-1.

• ATLAS:➡ General purpose detector.
➡ Big achievements

by the past several years.
✓ Higgs observation.
✓ Precision measurementsof the standard model.

Figure 3.1: The full ATLAS detector [37].

In this chapter, sections are organized as follows. The ATLAS coordinate system is expla
in Section 3.1. The details of each subsystem are described in Section 3.2 to 3.6. After descri
the ATLAS detector, the trigger system and the data acquisition (DAQ) system is outline
Section 3.7. The ATLAS computing system is explained in Section 3.8.

~9km

1)

The ATLAS stands for ‘A Toroidal LHC ApparatuS’

LHC2• LHC:➡ World’s largest collider.
➡ Run-II operation is ongoing.
➡ Proton beams @ √s=13 TeV.
➡ Inst. Lumi. ~5×1033 cm-2s-1.

• ATLAS:➡ General purpose detector.
➡ Big achievements

by the past several years.
✓ Higgs observation.
✓ Precision measurementsof the standard model.

30
25

ATLAS

Data

H → ZZ* → 4l

Signal (m = 124.5 GeV µ = 1.66)
H∫ Ldt = 4.5 fb
s = 8 TeV: ∫ Ldt = 20.3 fb
s = 7 TeV:

Background ZZ*-1-1

Background Z+jets, t t
Systematic uncertainty

BDTZZ* output

Events / 2.5 GeV

LHC-ATLAS

35

Higgs!!

20
15

1
0.5
0

10
-0.5

5
0
80 90 100 110 120 130 140 150 160 170m4l [GeV]

-1
110

(a)

Figure 6: (a) Distribution of the four-lepton invariant mass for the selected candidate
8 TeV data samples. Superimposed are the expected distributions of a SM Higgs boson
strength, as well as the expected ZZ ⇤ and reducible backgrounds. (b) Distribution of t
the 110–140 GeV m4` range for the combined 7 TeV and 8 TeV data samples. The exindicated by the size of the blue boxes, and the total background is indicated by the in>1014

The measured Higgs boson mass in the H ! ZZ ⇤ ! 4` decay ch

mH = 124.51 ± 0.52 (stat) ± 0.06
= 124.51 ± 0.52 GeV

where the first error represents the statistical uncertainty and the sec
uncertainty is obtained from the quadrature subtraction of the fit uncer
uncertainties fixed at their best fit values. Due to the large di↵erence
tematic uncertainties, the numerical precision on the quadrature3 subtr

Cross Section[pb]+The ATLAS1) detector is one of the general purpose detectors at LHC. The detector surrou
the interaction point and the beam pipe hermetically. It consists of cylindrical layers and t
end-caps. The detector is 44 m in length and 25 m in height, and has a weight of approximat
7000 tons. Figure 3.1 shows the full ATLAS detector. The detector components, calledsubsystems, are categorized into the inner tracker, the electromagnetic and hadron calorime
and the muon spectrometer, from inside to outside. Besides, the ATLAS detector is equippwith the magnets and the forward detectors.

ATLAS Inner Detector• Inner detector in ATLAS➡Purpose :- Particle tracking- Vertexing➡Provides very important
information for “all”
reconstructed objects.

ATLAS Detector

2

CHAPTER 3. THE ATLAS EXPERIMENT

3.3

Inner tracker

The inner tracker is placed at the center of the ATLAS detector, thus inside the magnetic fiel
by the solenoid magnet. The inner tracker is 6.2 m long in the z-direction and 2.1 m in diamete
The primary purpose of the inner tracker is to detect the position where the charged particles gthrough. This information is essential to reconstruct charged particle tracks and to determin
pp interaction points and secondary vertices. The inner tracker consists of three detectors, Pixdetector, SemiConductor Tracker (SCT) and Transition Radiation Tracker (TRT). The layou
of these three detectors is shown in Figure 3.6.

Figure 3.1: The full ATLAS detector [37].

In this chapter, sections
are organized asInner
follows. The ATLAS
coordinate system is explain
ATLAS
Detector• ATLAS-Japan group is involvedin Section 3.1. The details of each subsystem are described in Section 3.2 to 3.6. After describ
the ATLAS detector, the trigger system and the data acquisition (DAQ) system is outlined
in silicon detector studies.
Section 3.7. The ATLAS computing system is explained in Section 3.8.
➡Pixel detector➡SemiConductor Tracker (SCT)1)

The ATLAS stands for ‘A Toroidal LHC ApparatuS’

4

ATLAS Inner Detector• Inner detector in ATLAS➡Purpose :- Particle tracking- Vertexing➡Provides very important
information for “all”
reconstructed objects.

2
e
s
a
b
.
o
l
3.3 Inner tracker
Much improved
Ca
The inner tracker is placed at the center of the ATLAS detector, thus inside the magnetic fielsein the z-direction and 2.1 m in diamete
Trkis. 6.2bmalongby the solenoid magnet. The inner tracker
CHAPTER 3. THE ATLAS EXPERIMENTThe primary purpose of the inner tracker is to detect the position where the charged particles gthrough. This information is essential to reconstruct charged particle tracks and to determin
pp interaction points and secondary vertices. The inner tracker consists of three detectors, Pixdetector, SemiConductor Tracker (SCT) and Transition Radiation Tracker (TRT). The layou
of these three detectors is shown in Figure 3.6.

• ATLAS-Japan group is involved ATLAS Inner Detector
in silicon detector studies.
➡Pixel detector➡SemiConductor Tracker (SCT)5

LHC-ATLAS schedule→ talks on Thursday morning
LHC schedule• There are several long shutdown (LS) are planned.

➡ Opportunity to upgrade detectors for the experiment side.

LHC

HL-LHC

from 2024~
Detector has to be upgraded toward HL-LHC

Phase-1 upgrades to be installed by end LS2: now → 2020 (1 year later)● Gives longer Run-2 with more time for exploitation of FTK, L1Topo...
● Main upgrades in LS2 - NSW, LAr electronics, L1 FEXes – have a little more time
Phase-2 upgrades for LS3: now 2024-2026→ Scoping document process6PixelDetector in HL-LHC
Inner Intro:
detector
in HL-LHC
ATLAS Pixel Detector

LHC: L=1x1034 cm-2 s-1

HL-LHC: L = 5x1034 cm-2 s-1~year 2015

~year 2024

FEIC

Inefficiency (%)• Many problems to keep using the current detector.
Increased radiation damage➡Intolerable radiation damage
Simulated FE-I3
16 n /cm-2
Maxfluenceof~10
eq
inefficiency
at162- Fluence of ~10 neq/cm
R=5cm
for the innermost pixel layer.
➡Unacceptable occupancy-Bandwidth
23 → 140 ppsaturation
collisions in one bunch crossing.
HL-LHC L=5x1034 cm-2s
newdesignis under study for the
upgrade.
• Completely
34 cm-2s-1
23 →~140
pile-upevents
L=3x10per 25ns bunch crossing

L=1034 cm-2s-1

7

ARTICLE IN PRESS60

Y. Unno / Nuclear Instruments and Methods in Physics Research A 511 (2003) 58–63

Y. Unno / Nuclear Instruments and Methods in Physics Research A 511 (2003) 58–63

Table 1SCT parameters in the barrel and in the endcap regions
installed into the inner detector complex in early2005 and the ATLAS detector to be completed at59

regions, the inner edge of the endcap siliconsensors rising to 270 mm from 259 mm in the
TDR. To cope with the reduction of radial
coverage, the location of the endcap disks was
rearranged and the inner modules of disk 1 moved
to disk 2 to optimise the average number of hits.

Overview of the upgraded detector
Barrel cylinderr (mm)

Tilt angle (deg) theModules
end of 2006 with the first beam collision in

B3
B4
B5
B6

299
371
443
514

11
11
11.25
11.25
total

February
2007.
384

480
576Tracking System
2. Central
672
2112 solenoid
2.1. Central• Full silicon tracker.
➡To have high granularity/fast responding detector.
• Larger detector acceptance.
Figure 3.10: The ATLAS SCT module [44]➡Extend up to |η|<4.0.
• Many studies are ongoing.
In proton equivalent units, the fluence is B3 !
10 protons=cm: Thelayout,
SCT has beensupport
specified to➡Detector
R&D,
structure, cooling etc...
be able to withstand these fluences.
Endcap disk

Inner r (mm)Outer r (mm)1,72,3,4,5,6
8
9

337
270
408
439

560
560
560
560
total

14

2

2.3. Semiconductor tracker (SCT)The SCT system consists of a barrel made offour cylinders and two endcaps each of nine disks.
The superconducting solenoid has been fabriModules
The cylinders together carry 2112 detector units,catedunder the supervision of KEK and thethe barrel modules described in Section 3. The
ATLAS-Japan group [5]. In order to reduce92
disks carry in total 1976 endcap modules. The
the amount of material and space in front of the
major geometrical parameters of the barrel and
Liquid 132
Argon electromagnetic calorimeter, the
Fig.
2.
ATLAS
SCT
barrel module.
92
endcapregions are summarised in Table 1. A total
superconducting coil and the calorimeter share aof 8448 barrel and 7104 endcap microstrip sensors
common 52
vacuum vessel. The solenoid was comare required, all being fabricated from 4-in. siliconpleted 1976
and tested in Japan in January 2001,
wafers.
transported to CERN in October 2001, and isTable
2
being integrated into the vessel.
2.4. Radiation level
Barrel module parameters2.2. Inner detector (ID)IDsmall
volumewill angle
be subject to a fluence ofDetection planes
TwoThewithstereocharged and neutral particles from the collision
A quadrant view of the ID is shown in Fig. 1. Acrossing
point and from back-scattered neutrons from the
major change since the ID TDR has been to
Sensors
63:56 ! 63:96 mm2 =sensor
calorimeters. An estimated fluence at the innerincorporate an insertion tube to facilitate installasingle-sided
most of thep-in-n
SCT, Si
in wafer
neutron equivalent units, istion of the PIXEL subsystem. This tube required
14
pair
of
sensorstop
andB2 ! 10 neutrons=cm2 in 10 years of operation.
an increase to the inner radius of the SCT endcap

I+gnir tpecnoC

Current design
Stripstnemeriuqer tih 01

3. SCT barrel modules
New design(Not final)

bottom side
80 mm pitch
126 mm length (2 mm dead in
middle)þ= # 20 mrad
#7$ C
6:0 W nominal
8:1 W max.
> 240 mW=mm2 at 0$ C

The barrel cylinders of SCT all carry detector
Strip directions
units of an identical design, the barrel modules. A
Operating temperature
Total chip power
3D view of the module is shown in Fig. 2. The
module components include four silicon microThermal runaway heat flux
strip sensors, a baseboard, and an electronic
Mechanical precisions
hybrid wrapped around near the centre of the
back-to-backo5 mm (in-plane lateral)
module [6]. The major design parameters are listed
o10 mm (in-planelongitudinal)
in Table 2.
o50 mm (out-of-plane)
The sensors were designed for the ATLAS SCT
Fixation point
o30 mm (in-plane)
specification [7]. The baseboard is made of thermal
Radiation length
1:2% X0
pyrolytic graphite (TPG), providing a mechanicalFig. 1. A quadrant view of the inner detector consisted of PIXEL, SCT, and TRT detector systems. The detector boxes indicate thestructure, a high thermal conductivity Figure
heat
path,
envelopesof active
elements.
The figure
is basedon the engineeringdrawing of
TB-0049-177-01-P.
3.11:
The
layoutof the
ATLAS
inner tracker[44].
The distances are given in mm.
8
and an electrical connection to the backside of thesensors [8]. The hybrid is made of four layers of|η|<4.0 (~2°)
proton beam

)
°
9
~
(
5
.
2
<
|
|η

Center of the detector

proton beam

ARTICLE IN PRESS60

Y. Unno / Nuclear Instruments and Methods in Physics Research A 511 (2003) 58–63

Y. Unno / Nuclear Instruments and Methods in Physics Research A 511 (2003) 58–63

Table 1SCT parameters in the barrel and in the endcap regions
installed into the inner detector complex in early2005 and the ATLAS detector to be completed at59

regions, the inner edge of the endcap siliconsensors rising to 270 mm from 259 mm in the
TDR. To cope with the reduction of radial
coverage, the location of the endcap disks was
rearranged and the inner modules of disk 1 moved
to disk 2 to optimise the average number of hits.

Overview of the upgraded detector
Barrel cylinderr (mm)

Tilt angle (deg) theModules
end of 2006 with the first beam collision in

B3
B4
B5
B6

299
371
443
514

11
11
11.25
11.25
total

February
2007.
384

480
576Tracking System
2. Central
672
2112 solenoid
2.1. Central• Full silicon tracker.
➡To have high granularity/fast responding detector.
- Sensor R&D• Larger detector acceptance.
Figure 3.10: The ATLAS SCT module [44]- Developmentof test DAQ system➡Extend up to |η|<4.0.
• Many studies are ongoing.
In proton equivalent units, the fluence is B3 !
10 protons=cm: The SCT
has been specified
to➡Detector
R&D,
layout,supportstructure, cooling etc...
be able to withstand these fluences.
Endcap disk

Inner r (mm)Outer r (mm)1,72,3,4,5,6
8
9

337
270
408
439

560
560
560
560
total

14

2

2.3. Semiconductor tracker (SCT)The SCT system consists of a barrel made offour cylinders and two endcaps each of nine disks.
The superconducting solenoid has been fabriModules
The cylinders together carry 2112 detector units,catedunder the supervision of KEK and thethe barrel modules described in Section 3. The
ATLAS-Japan group [5]. In order to reduce92
disks carry in total 1976 endcap modules. The
the amount of material and space in front of the
major geometrical parameters of the barrel and
Liquid 132
Argon electromagnetic calorimeter, the
Fig.
2.
ATLAS
SCT
barrel module.
92
endcapregions are summarised in Table 1. A total
superconducting coil and the calorimeter share aof 8448 barrel and 7104 endcap microstrip sensors
common 52
vacuum vessel. The solenoid was comare required, all being fabricated from 4-in. siliconpleted 1976
and tested in Japan in January 2001,
wafers.
transported to CERN in October 2001, and isTable
2
being integrated into the vessel.
2.4. Radiation level
Barrel module parameters2.2. Inner detector (ID)IDsmall
volumewill angle
be subject to a fluence ofDetection planes
TwoThewithstereocharged and neutral particles from the collision
A quadrant view of the ID is shown in Fig. 1. Acrossing
point and from back-scattered neutrons from the
major change since the ID TDR has been to
Sensors
63:56 ! 63:96 mm2 =sensor
calorimeters. An estimated fluence at the innerincorporate an insertion tube to facilitate installasingle-sided
most of thep-in-n
SCT, Si
in wafer
neutron equivalent units, istion of the PIXEL subsystem. This tube required
14
pair
of
sensorstop
andB2 ! 10 neutrons=cm2 in 10 years of operation.
an increase to the inner radius of the SCT endcap

I+gnir tpecnoC

Current design
Stripstnemeriuqer tih 01

3. SCT barrel modules
New design(Not final)

bottom side
80 mm pitch
126 mm length (2 mm dead in
middle)þ= # 20 mrad
#7$ C
6:0 W nominal
8:1 W max.
> 240 mW=mm2 at 0$ C

The barrel cylinders of SCT all carry detector
Strip directions
units of an identical design, the barrel modules. A
Operating temperature
Total chip power
3D view of the module is shown in Fig. 2. The
module components include four silicon microThermal runaway heat flux
strip sensors, a baseboard, and an electronic
Mechanical precisions
hybrid wrapped around near the centre of the
back-to-backo5 mm (in-plane lateral)
module [6]. The major design parameters are listed
o10 mm (in-planelongitudinal)
in Table 2.
o50 mm (out-of-plane)
The sensors were designed for the ATLAS SCT
Fixation point
o30 mm (in-plane)
specification [7]. The baseboard is made of thermal
Radiation length
1:2% X0
pyrolytic graphite (TPG), providing a mechanicalFig. 1. A quadrant view of the inner detector consisted of PIXEL, SCT, and TRT detector systems. The detector boxes indicate thestructure, a high thermal conductivity Figure
heat
path,
envelopesof active
elements.
The figure
is basedon the engineeringdrawing of
TB-0049-177-01-P.
3.11:
The
layoutof the
ATLAS
inner tracker[44].
The distances are given in mm.
9
and an electrical connection to the backside of thesensors [8]. The hybrid is made of four layers of|η|<4.0 (~2°)
proton beam

)
°
9
~
(
5
.
2
<
|
|η

Center of the detector

proton beam

Exapmle of the real ATLAS and test system…
Real ATLAS Electronics Hut Example of a test system• Real ATLAS DAQ system as a test system.

➡ This works well for some sub-systems (calolimeter, muon chambers).
➡ Then, for silicon…? Not handy since the detector is small!!
10

Requirement of the silicon test system• “Compact” and “versatile” system.
➡Compact:- Don’t need large crates just for testing prototypes...
✓E.g. NIM, CAMAC, VME, ATCA etc...
- Portable system is preferable.
✓We have to transport the system for the testbeam.
➡Versatile:- Have to test new features of the prototype quickly.

Small PCB board with …
1. enough data transfer speed
2. enough I/O ports via FPGA
is preferred.

11

The SEABAS board• SEABAS: Soipix EvAluation BoArd with Sitcp.
➡Originally developed for SOIPIX R&D.
➡Designed to test variety of pixel prototypes.
• Feature:➡120 FPGA pins are provided for “users”.
➡Fast data interface to PC by SiTCP (100 Mbps).
Connectors foreach application(120 signal lines
from UserFPGA)

12The SEABAS board• SEABAS: Soipix EvAluation BoArd with Sitcp.
➡Originally developed for SOIPIX R&D.
➡Designed to test variety of pixel prototypes.
• Feature:➡120 FPGA pins are provided for “users”.
➡Fast data interface to PC by SiTCP (100 Mbps).

13

The SEABAS2 board• Upgraded SEABAS board.
➡Newer FPGA than SEABAS1 (Virtex-5).
➡Faster SiTCP (1 Gbps)
Connectors foreach application(120 signal lines
from UserFPGA)NIM I/O
UserFPGA

SiTCP

Ethernet(via TCP/UDP)~ 20 cm

Matches our requirements😊

14

History of SEABAS test system in ATLAS• Silicon Strip Upgrade: since 2009.

➡ Contributers: W. Okamura, M. Endo, T. Kishida,

R. Nishimura, K. Todome, S. Sato

• Silicon Pixel Upgrade: since 2010.

➡ Contributers: Y. Takubo, J.J. Teoh, M. Hirose• Telescope: since 2012.

➡ Contributers: S. Higashino, N. Ishijima, K. Yajima• R&D with SEABAS is growing in the ATLAS-Japan silicon group.
➡ Now, SEABAS-Pixel DAQ is used some institutes in US.

15

Application of SEABAS
for ATLAS Pixel R&D

16

Upgrade of the pixel detector

Intro: New Front End IC• Readout ASIC: FE-I3 → FE-I4.
➡Smaller pixel size, faster readout speed.
- To cope with higher hit rate.
FE-I3

20mm

Pixel size
(µm2)

FE-I3
7.6mm

10.8mm

19mm

FE-I4

FE-I4

FE-I5

50 X FE-I3
400 50 x 250
FE-I425x150

Pixel array 18 X 160 80 x 336 136x33(total(26880)(45696
Pixel #)
array (2880)
18×16080×336
Data Rate160
40360(?)
2(Mb/s)
Pixel size (um ) 50×400 50×250
CMOS
130
65
Data(nm)rate 250
process
40
160(Mb/s)
CMOS
250
130!Largest
IC
in
HEP
to
date.
process (nm)!Higher radiation tolerance.
!Smaller pixel size:

17

FEI4-SEABAS2 DAQ system• Can readout up to four FEI4s➡MUX can be used to readout two FEI4s.

4-chipadapter card
SEABAS2LAN
FEI4×4Control,
analysis ...

SCC × 4

18

FEI4-SEABAS2 DAQ system• Can readout up to four FEI4s➡MUX can be used to readout two FEI4s.

4-chipadapter card
SEABAS2MUXLAN
FEI4×4Control,
analysis ...

SCC × 4

optional
19

Firmware/Software design• To make flexible DAQ system➡Only providing the interface for all (ten) FEI4 commands.
- e.g. LV1Trigger, CalibrationPulse, WrRegister etc...
➡All meaningful data from FEI4s are sent to PC.
• All operation can be done by software coding.
➡Relatively easy for non-DAQ expert to test new things.

FEI4×4
FEI4

FIFO0

Com.
decoder

FEI4
Data

PC

Command
10b→8bFEI4FEI4

SEABAS2

10b→8b

FIFO1

10b→8b

FIFO2

10b→8b

FIFO3

SiTCP
(RBCP)SiTCP(TCP)

Control
Analysis
20

Software Interface• DAQ software is worked on Linux and Mac.
➡Command line interface$./run (run_mode) (ChipMask)➡Configuration parameters : fed by a text file for each FEI4.
- Preamp parameters, injection timing etc...
➡Operation parameters : fed by a text file.
- FEI4 version, #Injections, target threshold etc...
➡Operation result : PostScript and ROOT format.
- All the histograms are stored in a root file.
- TTree is provided when taking data with ext. triggers.
21

5000

(chip,col,row)=(0,34,10)
1.2

10000
Charge[e]0r 2 / ndf

11.73 / 8Prob0.1638Hit efficiency

Example: threshold tuning
Threshold 2363 ± 10.88
Noise114.3 ± 18.36

1

5000

(chip,col,row)=(0,34,11)
1.2

Hit efficiency

0

10000
Charge[e]r 2 / ndf

5.685 / 8Prob0.6825Threshold 2412 ± 12.62
Noise140.7 ± 21.83

1

Threshold• To set same threshold among pixels.
0.6
0.6
determination➡Good example of the operation
0.4
0.4- Needs global configuration.
for
each
pixel
0.2
0.2
configuration.
- Needs pixel local
0
0
0
5000
10000
0
5000
10000
Charge[e]Charge[e]- Charge injection- etc...
Set global threshold
0.8

6

10

5

10

# pixels# pixels

0.8

12000

104

10000

After tuning

3

10

Before tuning

2

10

10
10

8000

Set local threshold
Charge injection × n

6000
4000

Extract threshold

RepeatMean:3596.3± 0.8[e]RMS :124.2[e]

2000
2000

4000

6000

8000
10000
Threshold [e]002000 best
4000 DAC
6000 value
8000
10000
Save
the
Threshold [e] 22

Threshold tuning algorithm• Threshold tuning for each pixel :➡Scanning DAC[4:0] for threshold in each pixel.
- 32 DAC value --> 6 trials with binary search.

2380 ± 19.11

106.2 ± 36.36

r 2 / ndf

10.84 / 5Prob0.05458

Threshold 2180 ± 11.46
Noise

1

Fitting S-curve

00
e[e]

1

0.6

0.4

0.4

0.2
0
0

5000

Prob

0.5577

Threshold 2261 ± 16.98

Noise

0.6

Threshold2.072 / 3

Set global threshold

0.8

0.5

r 2 / ndf

114.9 ± 35.31

Set local threshold
Charge injection × n
Extract threshold

Repeat0.8

70.17 ± 33.79(chip,col,row)=(1,45,267)
1.2

Hit efficiency

0.6549(chip,col,row)=(1,45,266)
1.2

Hit efficiency

1.62 / 3

0.2

10000
Charge[e]Save the5000
best DAC
value
10000

0
0

Charge[e]234.239 / 5

r 2 / ndf

3.249 / 5

r 2 / ndf

4.616 / 5

Threshold tuning algorithm• Threshold tuning for each pixel :➡Scanning DAC[4:0] for threshold in each pixel.
- 32 DAC value --> 6 trials with binary search.

Set global threshold
Set local threshold
Charge injection × n
Extract threshold

Repeat• So far, took 15 min.
➡Configuration : 7.5 min➡Data taking : 6.5 min➡S-curve fitting : 1 min• Tried to reduce configurationand data taking time.

Save the best DAC value2416.18 / 7
0.0235(chip,col,row)=(0,64,26)
1.2

r 2 / ndf

5.16 / 8Prob0.7404(chip,col,row)=(0,64,27)
1.2

r 2 / ndf

4.278 / 9Prob0.8922127 ± 10.47

Threshold 3661 ± 7.664
Noise

143.5 ± 10.5

1

0.8

Hit efficiency

To perform the tuning in short time

hold 3742 ± 7.509

Hit efficiencydf

Threshold 3546 ± 7.004
Noise122.6 ± 9.868

1

0.8• Optimizing injected charge range.
0.6
0.6• Full range (up to ~10000e) scan is not needed.
0.4
0.4➡Threshold dispersion before tuning : ~400e
0.2
0.2➡“Target threshold ± 500e” is scanned.
0
0
10000
0
5000
10000
0
5000
10000
Less
configuration
time
&
less
data
takingtime.
•
arge[e]Charge[e]Charge[e]0.8854hold 3442 ± 8.603
178.7 ± 13.25

10000
arge[e](chip,col,row)=(0,64,29)
1.2

r 2 / ndf

2.178 / 6Prob0.9026

Threshold 3520 ± 7.645
Noise135.1 ± 10.5

1(chip,col,row)=(0,64,30)
1.2

efficiency#Hitpixels

4.37 / 9Hit efficiency

df

2.767 / 7

Before tuningProb30.9056

Threshold 3731 ± 8.879

Noise

101

0.8

r 2 / ndf

175.4 ± 12.76

Mean 3433 ± 2.604
RMS

426.8

0.8
102

0.6
0.4

0.6

Scanning onlyaround this region

0.2
0
0

0.4
10
0.2
1

5000

10000
Charge[e]000200050004000

10000
6000
8000
10000
Charge[e]Threshold [e]25Result• Local threshold tuning time : 6.5 min➡Configuration : 2 min➡Data taking : 3.5 min➡S-curve fitting : 1 min# pixels• Can finish in less than a half time.
➡able to tune thresholdat the target (3600e)
with RMS<100e (specs).
➡Same quality
as the old algorithm.
104

10− Old method(RMS=56.6e)− New method(RMS=57.6e)

3

102

10

1
0

1000

2000

3000

4000

5000

6000

7000

8000

9000 10000

Threshold [e]26Demonstrating fast threshold tuningr 2 / ndf
Prob
p0
p1

(chip,col,row)=(1,41,241)8000

2.21e+04 / 6
07846 ± 39.18-197.6 ± 2.341

r 2 / ndf
Prob
p0
p1

(chip,col,row)=(1,41,242)
8000

4002 / 6
06389 ± 16.67-157.4 ± 0.9963

BestDAC=12

6000
5000
4000

Target

600

500

400

300

200

100

Slope dispersion

r 2 / ndf
1.011e+04 / 6
Prob
0
Mean
-154.7±0.03036p06324 ± 26.5
p1
-164.8± 1.584
RMS
4.977(chip,col,row)=(1,41,246)
8000
3

10
7000

Threshold [e]7000

1.075e+04 / 6
05453 ± 27.33-155.7 ± 1.633#Pixelsr 2 / ndf
Prob
p0
p1

(chip,col,row)=(1,41,245)
8000

700

Local TDAC

Threshold [e]ThresholdThreshold [e][e]Local TDAC

Threshold [e]Threshold [e]Threshold [e]• Completely diﬀerent way to find the best threshold DAC value.
7000
7000
➡Previous method :
6000
6000
5000
5000
value.
- Binary search for the best DAC
4000
4000
3000
3000
➡This method :
2000
2000
by assuming slope in1000 - Estimate the best DAC value1000
00threshold
DAC
0
5
10
15 vs 2025 value.
30
0
5
10
15
20
25
30

(ch
800

6000
5000
102

(ch
800

700

600

500

4000

400

3000

3000
10

300

2000

2000

200

1000
1
0
-200
0

100

Initial DAC

1000
0
0

5

10

15

20

25
30
Local TDAC

Threshold DAC valuer 2 / ndf

1.18e+04 / 6

5 -180 10

-160
15

-140
20

25 -120 30
Local TDAC

-100

Slope [e/DACstep]r 2 / ndf

1.068e+04 / 627

04 / 6

1000

Demonstrating fast threshold tuning
0
0

5

10

15

20

25
30
Local TDAC

r 2 / ndf
Prob
p0
p1

(chip,col,row)=(1,40,136)
8000

3348 / 606335 ± 15.25-153.9 ± 0.9112

Threshold [e]• Completely diﬀerent way to find the best threshold DAC value.
7000➡Previous method :
6000
5000
- Binary search for the best DAC value.
4000
3000
➡This method :2000- Estimate the best DAC value by assuming slope in
1000
0threshold
DAC
0
5
10
15 vs 2025 value.
30
Local TDAC
r 2 / ndf
Prob
p0
p1

(chip,col,row)=(1,40,140)
8000
7000

3091 / 608039 ± 14.65-174.3 ± 0.8756

BestDAC=24

6000

Slope dispersion
Mean -154.7 ± 0.03036
3

RMS

10

4.977

102

5000
4000

#Pixels

04 / 6
0
30.85
1.844

2000

ThresholdThreshold [e][e]04 / 6
0
26.81
1.602

3000

Target

3000

10

2000
1000
0
0

Initial DAC
5

10

15

1

20

25
30
Local TDAC

Threshold DAC valuer 2 / ndf

1.119e+04 / 6

-200

-180

-160

-140

-120

-100

Slope [e/DACstep]28

Result

9000
8000
7000
6000
5000

# pixels

10000

Threshold[e]• Only takes 1.5 min to finish the tuning.
➡Dispersion of threshold : a bit wider but still O.K. (~100e)• Some pixels seem not well tuned (#failed pixels~20).
➡Still, this method would be useful in the testbeam(i.e. in limited beam time).
104

10− New method(RMS=100.6e)− Prev. method(RMS=57.6e)

3

102

4000
3000

10

2000
1000
80

mn

0

1
0

1000

2000

3000

4000

5000

6000

7000

8000

9000 10000

Threshold [e]

29

ୈ1ষ

SCTJDAQ Software ͷ֓ཁIntegration in the telescope system• FEI4-SEABAS system was integrated

Online plots

SVXテレスコープ
into the SVX4-SEABAS
telescope. FPGA基板

based GUI (SCTJDAQ).
• Gigabit Ethernet, TCP/IP 規格• Web• 汎用読み出し基板
SEABAS2"
test will be held at CERN • FPGAを2つ搭載
Interface• Beam• KEK開発
from 2-16 November.

• SVX4の制御、データの処理、• テレスコープ4台を同時読出し

PCへのデータ送信ਤ 1.1: SCTJDAQ Software ಈ࡞Πϝʔδ

User
SiTCP FPGASCTJDAQFPGASoftware ͸ɺ֤‫ثػ‬Λ੍‫͠ޚ‬ɺσʔλΛॲཧ͢ΔͨΊͷ
DAQ ༻ιϑτ΢Σ
Ξ (SCTJDAQ Software) Ͱ͋Δɻຊ DAQ ༻ιϑτ΢ΣΞͷ։ൃʹ౰ͨͬͯɺABCn250

DaughterBoardಡग़͠༻ DAQ γεςϜͷ੍‫ʹޚ‬͸ɺ੍‫༻ޚ‬ιϑτ΢ΣΞʹ͍ͭͯ΋ԕ౻ࢯଞͷ։ൃͨ͠ιϑτ΢ΣΞͷιʔείʔυΛҰ෦ྲྀ༻͍ͯ͠Δ 1 ɻDAQ ιϑτ΢ΣΞͷϑϨʔϜϫʔΫʹ͍ͭ}1

NIM I/OϑΝʔϜ΢ΣΞʹ͍ͭͯԕ౻ࢯଞͷ։ൃͨ͠ϑΝʔϜ΢ΣΞΛ‫ػʹݩ‬ೳ௥Ճͨ͠΋ͷΛ࠾༻ͨͨ͠ΊɺίϚϯυॲཧମ‫΅΄͕ܥ‬ಉҰͰ͋Δ͜ͱ͔Β

5

DAQ"
PC
Telescopes

Photo from K. Yajima

SEABAS2

1Gbps
Ethernet

30

Other test systems• Similar systems with the same concept.
➡ Two of them are derived from the real (or future) ATLAS DAQ.
HSIO II ➡ The rest is for pure test purpose (like SEABAS).

RCE

Conn. adapter board

USBpix Hardware (n

YARR

TTC

Upgrade of the Multi-IO board Î MIO3

GPIO
Artix

Display

RCE mezzanine

QSFPMartin Kocian (SLAC)

SMA

Compatible with
FE-I4 adapter card
First$Layout$Table$Top$Card$–(top$view)#– Burn-In card
ROD/BOC– GPA card

SFP

SFP
HSIO II

12 V power
RJ45 GE
25 February 2015

4 / 13

170#mm#

210#mm#

USBpix31

Comparison of the hardware specs.
Size[mm2]

FPGA

RCE

280x332

Artix7,
Zync

ROD/
BOC

Spartan6,
170x210
Virtex5

#FEI4

MGT

◯

~1 Gbps
8 (18?)
×2

◯

◯

◯

~1 Gbps×2

16◯

Kintex7

×◯

4 Gbps8◯100x170 Spartan6×◯

8 Gbps4◯

××

1 Gbps4

×

USBpix 110x150
YARR

SEABAS 170x210

Virtex5

CPU◯

MemoryInterface
speed

32

Example: YARR
• Quite similar approach as the SEABAS system➡ The DAQ board just aggregate the FEI4 commands/data.
➡ Everything has beend done by software.

Software II• Quite sofisticated software with a multi-threading technique.
Tuning feedback

Histogram

BufferPick up data

BufferBufferStart Trigger
Unit

Analysis
Algorithm

Pick up data

Configure

SelectHistogram

Process data
Read Data

PublishHistogram

Publish Result

Scan Loop

Fei4
Data Processor

Histogrammer

Analyzer

Thread #1

Thread #2

Thread #3

Thread #4

Same scan loop running
for all chips, data isaggregated and read out
in big chunks.

Raw data byte stream
gets split up by chip andplaced into software
containers.

Histograms are thecommon representationof the Pixel data andallow easy analysis.

The analysis algorithms
look at different aspects
and give a feedback toscan loop to steer
tuning.

Timon Heim

Picture copied from Timon’s
8

ITk Week

33

Common DAQ-Software development• Human power spreads out in several independent development.
• Specs of all the hardwares are much enough.
➡ Even consumer products are getting much powerful.
✓ $90 FPGA test board (LX9) can do same things as SEABAS…
➡ Only requirement is enough data link speed:✓ Only 640 Mbps (=160 Mbps×4) is needed for module testing.
• Software can treat hardware as transparent.
➡Eﬀort to have a common DAQ software
to use with any hardwares is ongoing.

LX9

34

Future developments

35

RD53 Integrated Circuit• ATLAS-CMS integrated circuit R&D collaboration.

Command/Control➡ Next generation
pixelProtocol
readout chip for HL-LHC.
➡ Ahttp://rd53.web.cern.ch/RD53/
single serial stream does it all●• Proposal of command interface.
●●

DC balanced and allowing 40MHz clock recovery
Can trigger on any arbitrary combination of beam crossings
Commands always active (in parallel with triggers)
Fault tolerant➡ Single serial stream does all.
●●

40 MHz BXclock
160MbpsSerial stream

Decoderblock~20 Mbps command stream
Arb. Trigger
other outputs (eg resets)• Proposal of output standard.
6/05/2015

M. Garcia-Sciveres --- Vertex 201511

➡ Sub-LVDS or CML, 1x5Gbps or 2x2.5Gbps.

36

Upgrade work with RD53
• RD53 emulator will come in the next year.
➡ FPGA based emulator.

• What we have to do…?

➡ At least we need new powerful test board.

✓ Missing feature on SEABAS.
- Multi-Gigabit Interface.
- RAM: a few hundred MB?
✓ Other wishes.
- Latest FPGA or ZYNC…?
- Optimization of diﬀerential signals.

37

Comparison of the hardware specs.
Size[mm2]

FPGA

RCE

280x332

Artix7,
Zync

ROD/
BOC

Spartan6,
170x210
Virtex5

#FEI4

MGT

◯

~1 Gbps
8
(18?)
×2

◯

◯

◯

~1 Gbps×2

16◯

Kintex7

×◯

4 Gbps8◯100x170 Spartan6×◯

8 Gbps4◯

××

1 Gbps4

×

USBpix 110x150
YARR

SEABAS 170x210

Virtex5

CPU◯

MemoryInterface
speed

These missings are crucial for future R&D…
38

Summary• Test system development is very important.
• FEI4-SEABAS system was developed by Japanese group.
➡ Aiming to have simple DAQ system for testing.
➡ Basic functionalities are available.
➡ Beam test will be held in coming November.

• There are several independent test systems.

➡ All systems has enough specs to operate prototype.
➡ Task force was set up to have common DAQ software.
➡ Hardware will be transparent for users in future.

• SEABAS should be upgraded for the next generation ASIC.
39

Backup40