2007 International Symposium on Nonlinear Theory and itsApplications
NOLTA'07, Vancouver, Canada, September 16-19, 2007

Spice-Oriented Optimization Algorithm of Amplifiers- Based on Nonlinear Programing Akio Ushida†, Junji Kawata†, Yoshihiro Yamagami‡, Yoshifumi Nishio‡†Department of Mechanical and Electronic Engineering,
Tokushima Bunri University, Kagawa, 769-2193 JAPAN‡Department of Electrical and Electronic Engineering,
Tokushima University, Tokushima, 770-8506 JAPAN
Abstractfrom the sensitivity analysis, so that we introduce the numerical differentiation as follows;

We propose an efficient Spice-oriented design algorithmof amplifies for attaining both the DC maximum gains andthe low power consumptions. Our optimization algorithm isbased on a well-known steepest descent method combining
with nonlinear programming, which is realized by equivalent RC circuits composed of ABMs (analog behavior models) of Spice. The optimum parameters are given by theequilibrium points of the transient analysis. We show our
Spice-oriented optimization algorithm using the sensitivity
circuits in section 2, and the interesting illustrative examples
are shown in section 5.
sectionSv,i (p + ∆p) − Sv (p)dpi=−, i = 1, 2, . . . , k,ds∆pi∆p = (0, 0, . . . , ∆pi , . . . , 0)T

2. Sensitivity analysis andSpice-oriented optimization algorithm

1. Introduction

2.1 Sensitivity analysis: The steepest descent method is
the most basic optimization approach, where the gradientdirection is decided by solutions of the sensitivity circuit.
Let us derive the sensitivity circuit via tableau approach [8].
The tableau equation is given by;

Amplifiers are widely used as the building blocks of manyanalog circuits [1-4]. There are many kinds of designingitems such as the maximum gain, low power consumption,
minimum distortion and so on. We consider here a design
problem for attaining both the maximum gains and the lower
consumptions of amplifiers. These circuits are realized by
setting suitable bias voltages of transistors and/or choosing
suitable sizes (length, width) of MOSFETs, and the resistive
values. Traditionally, these optimization parameters havebeen found by trial and error methods with Spice simulations and the experimental knowledge of the designers. However, it is really time-consuming for the circuits containing alarge number of optimization parameters [6,10]. Therefore,
we propose here a simple fully Spice-oriented steepest descent optimization algorithm combining with nonlinear programming. Firstly, we define the objective function to beminimized as follow;nΦ(x, p), x ∈ R , p ∈ R

k

"

Ki
0
A

Kv
1
0

#"

0
−AT
0

#

i
v
vn

"

−

#

g(v, i)
E
AJ

"

=

0
0
0

#

(3)

The first row is the Ohm’s law where bf K i , Kv consist of
1 and 0 elements, the second and third rows are Kirchhoff’s
voltage and current laws, respectively. A is the incidence
matrix. E and J show the voltage and current sources. Now,
define the sensitivity as follow;
Sensitivity:
Sk,i ≡

∆xk

lim

(4)

∆pi →0 ∆pi

We can derive the sensitivity tableau equation as follows;

"

(1)

where
x: circuit variables such as voltages and currents.
p: optimization parameters such as bias voltages, resistor’svalues and the dimensions of MOSFETs W[width, µm] andL [length, µm] and so on.
Our optimization technique based on the steepest descentalgorithm is realized by the equivalent RC circuits, whose
input currents are obtained by the sensitivity circuits [8] andthe deviation circuits. The gradient direction for attaining
the maximum gain is given bydSv (p)dpi=−, i = 1, 2, . . . , k,
ds
dpi

(2.2)

with sufficiently small ∆p. Replacing the auxiliary variable“s” by time “t”, our descent algorithm can be realized by theequivalent nonlinear RC circuits, and the optimum parameters can be found by the equilibrium point of the transient
analysis. To design low power circuits, we need further tomodify the algorithm (2.2) which is shown in section 2.2.

Ki
0
A

Kv
1
0

"
−

0
−AT
0

#"

¯
¯

Si,pi
Sv,pi
Svn ,pi∂g(v,i)Si,pi∂i
v0 ,i0

δ(i)
Aδ(i)

#

#

"

−



¯
¯

∂g(v,i)Sv,pi∂v
v0 ,i000¯¯∂g(v,i)δ(i)∂pv0 ,i0

=

0
0

#




(5)

where δ(i) means a delta function satisfying
δ(i) =

1
[0,

2
0,

...
...,

i
1

...
...,

k
0]T

Thus, we can develop the sensitivity circuit for any pi parameter. Observe that the circuit configuration is equal tothe original except for the nonlinear elements being replacedby the linear incremental resistors at the operating points
V0 , I0 . Now, we summarize the algorithm for deriving thesensitivity circuit.

(2.1)

where S(p) is the gain, and pi is a optimization parameter. Unfortunately, it is impossible directly to evaluate dS(p)dpi1- 505 -

1. When one voltage source is chosen as an optimization
parameter, the voltage is set to “1[V]”. The other voltage sources are removed by the short-circuits.

The controlled current sources in the figure { Sv,i (p +∆p), Ii (p + ∆p), i = 1, 2, . . . , k } are obtained from thek sensitivity circuits and the small deviation ∆p circuits,
respectively. Thus, the optimization parameters satisfying
both the maximum gain and the low power consumption canbe found at the equilibrium points of the transient analysisof (6). Note that although C’s in Fig. 2 are set equal to“1” in (6), the convergence ratio will be largely increased bychoosing the smaller values. R0 ’s are sufficient large dummy
resistances to avoid C-J cut-set.

2. When one current source is chosen as an optimization
parameter, the current is set to “1[A]”. The other current sources are removed by the open-circuits.
3. When resistor is chosen as an optimum parameter, it
is replaced by the linear ¯incremental resistor with the¯controlled source ∂g(v,i)δ(i). Other resistors are∂p
v0 ,i0
only replaced by the incremental resistors.

3. Sensitivity modules of MOSFETs andbipolar transistors

Example 1: Now, consider a simple example nonlinear circuit shown in Fig.1(a), where the nonlinear resistor isNow, let us develop the sensitivity modules of MOSFETs
and bipolar transistors. Once these modules are stored inour computer library as the packages, we can easily formulate the sensitivity circuits.
3.1 Sensitivity module of MOSFET: We consider
Shichman-Hodges model [1-4] of nMOS in Fig.3(a);i = c1 v + c3 v 3 .
Let us calculate the gain Sv = dv/dE. For the optimum parameter E, we have the sensitivity circuit shown by Fig.1(b).
i

R1

Si

R1

1. Linear region(vGS > vT , 0 < vDS < vGS − vT )
E

Sv

1

v

G(v 0)

iD =

kn W
L

h

vDS
2

(vGS − vT ) −ivDS (1 + λvDS )(7.1)

2. Saturation region(vGS > vT , vDS ≥ vGS − vT )
(a)

(b)

kn W
(vGS − vT )2 (1 + λvDS )2L
where the threshold voltage is given byiD =Fig.1 (a) Simple nonlinear resistive circuit, (b) the sensitivity
circuit for the optimization parameter E.

The sensitivity is given by1
1/G(v0 )=,Sv =R1 + 1/G(v0 )1 + R1 G(v0 )for

G(v0 ) = c1 + 3c3 v02

Sv,i (p + ∆p) − Sv (p)dpi= K(IS − Ii (p + ∆p)) −
ds
∆pi
K=

∆iD =

(6)

SiD ,pi =∆p i

i=1,2, ..., k

∂ îD
∂ îD
∂ îD
Sv
+
Sv
+
Sv
∂vGS pi,GS∂vDS pi,DS∂vBS pi,BS
+

R0 p

∂ îD
∂ îD
δ(pi , W ) +δ(pi , L)∂W∂Lnδ(x1 , x2 ) =

1
0

(10)

for x1 = x2
for x2 =6 x2Thus, we have the MOSFET module shown in Fig.3(b),
where
GGS =

∂ îD
∂ îD
∂ îD
, GDS =, GBS =
∂vGS
∂vDS
∂vBS

SiD =

∂ îD
∂ îD
δ(pi , W ) +δ(pi , L).
∂W
∂L
D

D
vD

+
C

(8)

∂ îD
∂ îD
∂ îD
∂ îD
∂ îD
∆vGS +∆vDS +∆vBS +
∆W +
∆L
∂vGS
∂vDS
∂vBS
∂W
∂L
(9)

where δ means

v

i

(7.3)

Therefore, the sensitivity variables are given for each optimization parameter pi

where IS is the assigned current of the sources, which should
be set smaller value for the design of low consumption circuits. In this case, the solution curve of (6) will move tothe maximum point during IS > Ii . When the curve hasreached to the hyper-plane Ii = IS , it will moves on theplane and search the maximum point on the plane if wechoose a sufficiently large constant A. Thus, we can find thepoint satisfying both the maximum gain and the low power
consumption. Replacing the variable “s” by time “t’ in (6),
it is realized by RC circuit shown in Fig.2.
K(IS -I i (p+∆p) ) -φ ,iD = îD (vGS , vDS , vBS , W, L)

T

S (p+∆p) -S (p )p ´Then, we have the following variational equation;

0 : IS > Ii
A : IS ≤ Ii for sufficiently large A∆p = (0, 0, . . . , ∆pi , . . . , 0)

φ − vBS −where W and L are the width and length. For simplicity, werewrite (7) in the following form;

where v0 is the voltage of nonlinear resistor in Fig.1(a).
2.2 Spice-oriented optimization technique: Now, consider optimization problems for attaining both the DC maximum gain and the low power consumption of amplifier. In
this case, the steepest descent method for attaining the maximum gain given by (2.2) is modified as follows;½³p

vt = vT 0 + γ

(7.2)

vG

i

G

B
vS

-

iD

iS

vB

SiD

G
GGSSpi,GS GDSSpi,DS G Spi,BSBSSS(a) nMOS

Fig.2 A circuit configuration for attaining both the maximum
gain and the low power consumption.

(b) nMOS module

Fig.3(a) nMOS, (b) nMOS module.

2- 506 -

B

3.2 Sensitivity modules of bipolar transistor: Bipolar transistor is usually modeled with Ebers-Moll model orGummenl-Poon model [1-4]. The corrector current iC andbase current iB are functions of vBE and vBC as follows;
iC = îC (vBE , vBC )iB = îB (vBE , vBC )All the frequency response curves by models 1 and 2 arealmost same except for the cut-off frequency regions. Notethat even if the model 2 is complicate model compared withmodel 1, the response curve with model 2 is much more exact
than that of model 12 .

¾

(11)

5. Illustrative examples

Therefore, the sensitivities for optimization parameters pi
are given by
SiC ,pi=≡

SiB ,pi=≡∂ îC ∂vBE
∂ îC ∂vBC
+ ∂v
∂vBE ∂pi
BC ∂pi
GiC ,vBE Svpi,BE + GiC ,vBC Svpi,BC∂ îB ∂vBE
∂ îB ∂vBC
+ ∂v
∂vBE ∂pi
BC ∂pi
GiB ,vBE Svpi,BE + GiB ,vBC Svpi,BC

5.1 CMOS two-stage amplifier [4]: Consider a twostage amplifier as shown in Fig.6(a). Let us design it satisfying both the maximum gain and low power consumption.






(12)





+ VDD

Thus, the sensitivity module of NPN bipolar is given by
Fig.4(c)1 .
CCic

αSid 1

id2

id

i d1

αr i d2

re1
Sid 1

E

E

1
1
=
jωC
ωC

Kp = 19.344[µA],pW 9 = 10[µm],Kn = 74.209[µA]nW 3 = 1[µm]J = 90[µA]

E

R2 V

pλ = 0.1
pW 1 = 50[µm],nλ = 0.2
pL = nL = 0.5[µm]Then, we have obtained the results of Table 1.
No

A

1

104
105
106
106
106
106

2

[mA]

C2

pVT 0 = −0.8311[V ],pW 8 = 50[µm],nVT 0 = 0.6081[V ],nW 6 = 3[µm],1.5[µm] < pW 9, pW 8, pW 1, nW 3, nW 6 < 60[µm]5[µA] < Iin < 200[µA](13.1)

Example 2: Consider a simple circuit containing a series
and a parallel RC circuits as shown in Fig.5(a).
Resistive models of RC circuit

3

Modeling 2

0.4

Q6

Vout
RL

We get Gain=-1.956 from the transient analysis of Spice.
Next, we design the CMOS circuit with the initial conditions
as follows; pW 9 = 2[µm], pW 8 = pW 1 = nW 6 = 5[µm]nW 3 = 10[µm], J0 = 5[µA] and C = 0.01, R0 = 1000[kΩ]in the steepest descent method in Fig.2. We have restricted
the following 6 optimization parameters as follows;1
R(13.2), ZRC,P = √ω2 C 2
1 + ω 2 C 2 R2

0.6

Q3

CL

For the MOS and the circuit parameters from ref.[4]:

r

+

C0

Fig.6(a) Two stage CMOS amplifier.
VDD = 2.5[V ], VSS = −2.5[V ], Frequency =1[M Hz]
C0 = 10[nF ], CL = 1[nF ]2. The model 2 is replacing the series and parallel RC
circuits with the corresponding impedances as follows;

C 1 R1

+v

Q1

- VSS

The left hand side of our Spice-oriented optimization method
shown in Fig.2 is composed of the controlled-current sources
which are obtained from the small deviations ∆pi circuits
and the sensitivity circuits. Both circuits are resistive.
Therefore, our optimization method should not contain any
dynamical elements such as capacitors and inductors. On
the other hand, many kinds of amplifiers may consist of capacitors so that we need approximately to transform theminto the resistive models. We propose two types modelingas follows;
1. The model 1 is replacing each capacitor with the
impedance

R2 +

1

(c)

4. Resistive models of RC circuits

ZC = |

Q

Q3

Fig.4(a) NPN bipolar transistor, (b) Ebers-Moll model, (c)sensitivity modue of transistor module.

ZRC,S =Q9J

αr S id 2
E

(b)

(a)

-v

S id 2
re 2

B

B
ib

Q8

C

α i d1B

Q8

Table 1 Simulation results.
IS
Iin
J
GainD
(µA)
(µA)
(µA)
120.1
55.3
-19.6
50
52.4
23.3
-19.1
50
49.8
22.5
-20.4
50
49.6
22.4
-20.4
40
39.6
17.7
-3.30
40
39.7
17.7
-13.1
40
39.7
17.7
-18.7

GainT
-19.6
-20.1
-21.5
-21.5
-3.33
-13.3
-19.6

RL
(kΩ)
10
100
1000

Exact

where A is a sufficiently large constant in (6), and thecomputational time was around 225-230[sec]. Firstly, we
have assigned IS which is the current from bias VDD . It
is equal to sum of the current source J and the current
to VSS . Iin , GainD are the current and gain obtained byModeling 1

- 0.2
0
0

102

104

106

10

8 [rad/sec]

Fig.5(a) A simple RC circuit, (b) Frequency response
curves. R1 = R2 = 10[kΩ], C1 = 1[µF ], C2 = 10[pF ]2 Parasitic capacitors in transistors can not be neglected in
the high frequency. We recommend to use model 1 even if it iserroneous, because the circuit configurations are complicate.

1 The method can be also applied to Gummel-Poon model ofbipolar transistor.

3- 507 -

our optimization, and GainT is the gain estimated by thetransient analysis of Fig.6(a). We found interesting results
as follows;

We had the gain of 77.80[dB].
In order to attain the maximum gain, we have restricted the
optimization parameters as follows;

1. No.1 is the optimization result for only attaining the
maximum gain without no restrictions. We have thefollowing sizes;

10[kΩ] < R1 < 55[kΩ], 1[kΩ] < R2 < 6[kΩ],
0.5[kΩ] < R3 < 5[kΩ], 40[kΩ] < R4 < 60[kΩ],
10[kΩ] < R5 < 50[kΩ], R6 = 3[kΩ]Then, we had

pW 8 = pW 1 = nW 3 = 60[µm], pW 9 = nW 6 = 1.5[µm]R1 = 55[kΩ], R2 = 1.0[kΩ], R1 = 0.5[kΩ], R4 = 40[kΩ],R5 = 50[kΩ], R6 = 3[kΩ]where we have set pL = nL = 0.5[µm] for all the MOSFETs. Then, the input current Iin = 120.1[µA] is large.
Note that this kind of simulation is called nonlinear
programming [5].

whose maximum gain is equal to 87.07[dB]. The optimization result of the steepest descent method is shown in
Fig.7(b). Thus, we can design the operational amplifier having enough gain. The computation time was 36.95[sec].

2. No.2 is the results for attaining both the maximum gain
and low power consumption (IS = 50[µA]) without coupling capacitor (CL , RL ), where we set A from 104 to
106 in (6). For A = 104 , we had pW 8 = 17.82[µm] andIin = 52.39[muA] which is different from the assigned
current IS = 50[µA]. Thus, we can conclude that weneed to choose larger A > 105 .

6R4 [x10kΩ]

Optimization

3

Gain(x10000)

2
1
R2 [x10kΩ]0-1

1| = 159.
ZC = |jωCC

R3 [x10kΩ]
0

0.02

0.04

0.06

0.08

[sec]

0.1

Fig.7(b) Optimization result of operational amplifier.

Although the gains are largely changed by the load resistance RL , they are almost equal to the results fromthe transient analysis.

6. Conclusions and remarks
In this paper, we propose a Spice-oriented design algorithm of the amplifies for attaining both the maximum gain
and low power consumption. The algorithm is based on thesteepest descent method, which is realized by the nonlinear
RC circuits with ABMs of Spice. we found that our optimization simulator is much faster than a simulator ASCO(ASPICE Circuit Optimizer) [10].

60
Steepest descent method
CC=1[nF], RL=1000[kΩ]

pW8 [µ]pW1[µ]

20

R5 [x10kΩ]

4

3. No.3 is the results for the load impedances, where weused the model 1 in (13.1) for the capacitor CL and C0 ;40

R1 [x10kΩ]5nW3[µ]
Input Current [µA]
J [µA]

0

pW9,nW6 [µ]References

Gain_D

-20
8.2

8.4

8.8

8.6

[mS]

[1] G.Roubik, Introduction to CMOS OP-AMPs and Comparators, Wiley-Interscience Pub., 1999.

9.0

Fig.6(b) Optimization of two stage CMOS amplifier.
RL = 1000[kΩ], CL = 1[nF ], Frequency =1[M Hz][2] F.Maloberti, Analog Design for CMOS VLSI Systems,
KLuwer Academic Pub., 2001.
[3] S.M.Kang, and Y.Leblebici, CMOSW Digital Integrated Circuits: Analysis and Design, McGraw-Hill Co.Inc., 1996.

5.2 Operational amplifier [4]: Consider an operational
amplifier shown in Fig.7(a). The maximum gain is attainedby choosing suitable resistors R1 − R5 in the figure.
R1

R2

R1

[4] A.S.Sedra and K.C.Smith, Microelectronic Circuits, Oxford
Univ. Press, 2004.
[5] J.A.Snyman Practical Mathematical Optimization: An Introduction to Basic Optimization Theory and Classical and
New Gradient-Based Algorithm, Springer, 2005.

+15v

R3
Q7

Q4
Q1

+
+ vin
-

Q9

Q8

+
-vin
-

R4
Q3

[6] K.Ono, K.Saeki,Y.Sekine,“A design of an operational amplifier with high DC gain,” The Papers of Tech. meeting on
Electronic Circuits, IEE Japan, ECT-04-99, pp.1-5, 2004.

Q5

Q2

R5

Q6

[7] J.Guo, T.Nishi and N. Takahashi, “A method for solving optimization problems with equality constraints by using Spice program,” IEICE Trans, vol.E86-A, no.9,pp.23252332, 2003.

R6[8] L.O.Chua and P-M Lin, Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques,Prentice-Hall, 1975.

-15v

Fig.7(a) Bipolar operational amplifier.

[9] MicroSim: PSpice A/D circuit Analysis User’s Guides, MicroSim Co. 1995.

For parameter in ref[4],R1 = 10[kΩ], R2 = 3[kΩ], R1 = 2.3[kΩ], R4 = 28[kΩ],R5 = 15.7[kΩ], R6 = 3[kΩ][10] http://asco.sourceforge.net/

4- 508 -