Electronics and Sensor Studywith the OKI SOI process
TWEPP-07, Sep. 5, 2007

Yasuo Arai (KEK)KEK Detector Technology Project : [SOIPIX Group, http://rd.kek.jp/project/soi/]
Y. Arai, Y. Ikegami, Y. Unno, T. Tsuboyama, S. Terada, M. Hazumi, T. Kohriki, H. IkedaA,K. HaraB, H. IshinoC, H. MiyakeB, K. HanagakiD,
G. VarnerE, E. MartinE, H. TajimaF,
Y. HayashiG, M. OhnoG, K. FukudaG, H. KomatsubaraG, J. IdaG
KEK, JAXAA, U. TsukubaB, TITC, Osaka Univ.D, U. HawaiiE, SLACF,
OKI Elec. Ind. Co.G,
07.9.5 TWEPP-07 Yasuo Arai1OUTLINESOI Device
History of SOI
Features of FD-SOI

SOI Pixel Detector
Progress of SOI Pixel R&D
FY05 MPW Results
TCAD Simulations



FY06 MPW Run
Preliminary Results

Summary

07.9.5 TWEPP-07 Yasuo Arai2

OUTLINESOI Device
History of SOI
Features of FD-SOI

SOI Pixel Detector
Progress of SOI Pixel R&D
FY05 MPW Results
TCAD Simulations



FY06 MPW Run
Preliminary Results

Summary

07.9.5 TWEPP-07 Yasuo Arai

3

History of SOI (Silicon-On-Insulator)
First Planar IC (1959 R. Noyce)

Most ICs are built on
Bulk Si substrate.
Each transistor isisolated by reversebiased p-n junction

Bulk Si Technology
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Historical FET
Patent (1928)
J. E. Lilienfeld(Poland, 1882-1963)

Transistor is built on athin Si Film supported by
an Insulating Substrate.

(Prototype of SOI)
Unfortunately, No Evidence that this device was build and worked.
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Bulk and SOI Wafer
50-400 nm

circuit∼650 μm

20-200 nm
Top
Si (SOI Layer)
circuit

BOX(Buried Oxide)
SiPhysicalSubstrate(Handle Wafer)

SupportBulk Wafer

07.9.5 TWEPP-07 Yasuo Arai

SOI Wafer6First SOI Wafer for Integrated Circuit
SIMOX (Separation by Implanted Oxygen)
K. Izumi (NTT Japan, 1978)
Oxygen Ion Implantation
120-200 keV, 4-20x1017 cm-2

Si Substrate(Handle Wafer)07.9.5 TWEPP-07 Yasuo Arai

annealing
3-6 hours~1300 ºC

Si Overlayer
Buried Oxide Layer
Si Substrate(Handle Wafer)

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UNIBONDTM Process (1995, France LETI) -> SOITEC

microbubbles

hydrophilic
bonding~500oC

CMOS(Low R)

Sensor(High R)
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Bulk CMOS vs. SOI CMOS

In SOI, Each Device iscompletely isolated by
Oxide.
07.9.5 TWEPP-07 Yasuo Arai

9PD-SOI vs. FD-SOI
PD-SOI (Partially Depleted)

FD-SOI (Fully Depleted）◆Thick SOI thickness（TSOI）〜100-200nm◆Depletion layer < TSOI

◆Thin SOI thickness （TSOI）< 50nm
◆ Depletion layer > TSOI

◇Large floating body effect◇High drive Current by kink effect→ High speed application◇Less floating body effect◇Steep subthreshold slopes→ Low power application

Neutral Resign

Gate

Depletion
Layer

tSOI
Buried Oxide
Si Substrate

Gate

tSOI
Buried Oxide
Si Substrate

FD-SOI has advantage in performance
under very low voltage operation.
07.9.5 TWEPP-07 Yasuo Arai

Copyright 2007 Oki Electric Industry Co.,Ltd10

FD-SOI Structure
Cross Sectional SEM
Photograph

Lgate=
0.15umContact
Hole

Al
Ultra Thin Si Layer(40nm)

Buried Oxide
AlSi Substrate (High resistive)Al

Close up of MOSFET

Si

GATE
BOX (Buried Oxide)

Ultra Thin Si Layer (40nm)

Si Substrate (High resistive)

Si

Cross Sectional View of FD-SOI Device
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Copyright 2007 Oki Electric Industry Co.,Ltd11

07.9.5 TWEPP-07 Yasuo Arai

Copyright 2007 Oki Electric Industry Co.,Ltd12

FD-SOI LSI Products for Consumer Market
Radio Controlled Solar Watch
This Watch-LSI includes
MCU, SRAM, MROM, Power Unit,
LCD Driver etc
in One-chip.

70% Power reduction comparedwith bulk device
http://www.casio.co.jp

07.9.5 TWEPP-07 Yasuo Arai

Copyright 2007 Oki Electric Industry Co.,Ltd

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FD-SOI UV Sensor
9UV selective without external filters
9On chip analog / digital circuits
9Very high uniformity
0.1

Visible light

UV light+

P-

N+
Transparent

-

+

P+ Si

Intensity (A.U.)

Ultra Violet

Visible

0.08
UV-B

UV-A

0.06
0.04
0.02

Absorbing

SiO2

0
280

320

360

400

440

480

520

560

Wavelength
Wave
Length(nm)(nm)

Principal Schema
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Spectral of FD-SOI Photo-Diode
Copyright 2007 Oki Electric Industry Co.,Ltd

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Features of (FD-)SOI
z

z

z

z

z

Full Dielectric Isolation :Latchup Free, Small Area,
Good Circuit Isolation
No Back Bias Effect
Low Junction Capacitance :High Speed
Steep Subthreshold Slope
Low Power
No Kink Effect
Good for Analog Desugn
Less Impurity in Body
Good Vth Matching,Less 1/f Noise

z

z

z

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No Well junction, Thin Film :Low Leak,Low Vth Shift (High Temp).
Small Active Volume :High Soft Error Immunity
TID compensation by Back Bias
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Latchup Free Structure
Bulk CMOS

SOI CMOS(Ref. 'SOI Technology' by Jean-Pierre Colinge, Springer)

No Parasitic PNPN Structure

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Area reduction by SOI

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No Well Isolation17

Isolation between Analog and Digital Part
10-40dB lower than Well isolation of Bulk, when High-Resistive
Substrate is used

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Smaller Junction Capacitance

Cj is 1/10 of Bulk technology.
Gate Capacitance is 30-40%
Lower.

High Speed / Low Power07.9.5 TWEPP-07 Yasuo Arai

Copyright 2007 Oki Electric Industry Co.,Ltd

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Steep Sub Threshold Slope

Gate voltage is not wasted todeplete the bulk.
Lower Threshold (Leakage Current) is possible without
increasing Leakage Current (Vth).
07.9.5 TWEPP-07 Yasuo Arai

Copyright 2007 Oki Electric Industry Co.,Ltd

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Kink Effect on PD-SOI and FD-SOI
PD-SOI (good for digital)

FD-SOI(good for analog)

Kink

Impact Ionization create
electron-hole near thedrain, and increase
floating body potential.
07.9.5 TWEPP-07 Yasuo Arai

Copyright 2007 Oki Electric Industry Co.,Ltd

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Small Temperature Dependence

due to less change in depletion width

No latchup, Less leakage, Less Vth shift
FD-SOI can be operated in more than 300˚C.
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Copyright 2007 Oki Electric Industry Co.,Ltd22

High Soft Error Immunity
ChargedParticle

ChargedParticle
Gate Oxide

Gate
＋ −
− ＋
＋ −
− ＋
＋ −
− ＋
＋ −
− ＋
＋ −
− ＋
＋ −
− ＋
＋ −
− ＋
＋ −

Si

Bulk Device

Gate
Si

＋ −

BuriedOxide
Depletion
Layer

＋ −
− ＋
＋ −
− ＋
＋ −
− ＋
＋ −
− ＋
＋ −
− ＋

SOI Device

Higher soft error immunity due to ultra thin body Silicon.
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Total Ionizing Dose
OKI 0.15um FD-SOI

400krad(Si)(Data from JAXA)

Moderate TID Immunity (enough for space applications).
Charge trapped in BOX shifts Vth.
07.9.5 TWEPP-07 Yasuo Arai

Copyright 2007 Oki Electric Industry Co.,Ltd24

TID(2)
Leak Current and VTh resumes to nearly originalvalue by biasing back side even in 100Mrad.
Vback= 0 -10 -20 -30V
1015 p/cm2(~100 Mrad)

07.9.5 TWEPP-07 Yasuo Araibeforeirradiation

1015 p/cm2(~100 Mrad)

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Summary of this section• FD-SOI technology has many attractive features:
Latchup Free,
Radiation Hardness,
High Temperature Operation,
Low Power, ...
for use in High Energy and Space applications.
but the substrate Si is a simple physical structure
Can we integrate Radiation Sensor?

07.9.5 TWEPP-07 Yasuo Arai26

OUTLINESOI Device
History of SOI
Features of FD-SOI

SOI Pixel Detector
Progress of SOI Pixel R&D
FY05 MPW Results
TCAD Simulations



FY06 MPW Run
Preliminary Results

Summary

07.9.5 TWEPP-07 Yasuo Arai

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Progress of SOI Pixel R&D

Many people are seeking
an ideal pixel detector
High-R Semiconductor Sensor
withFully Integrated Amp. and R/O logic
using
Commercially Available Technology

SOI Monolitic Detector!
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Pioneering work by SUCIMA

Technology is not so advanced (~3μm technology at Lab.).
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KEK SOIPIX R&D History'05.5: Propose SOI Pixel R&D to KEK Detector Technology Project(Generic R&D).
7: Start Collaboration with OKI Elec. Co. Ltd. for SOI detector
R&D .
10: 1st TEG submissions in OKI MPW (Multi Project Wafer) run
with 0.15μm technology.
'06.3: Processes of the 1st TEG were finished.
4-8: Good response to Light and β-ray was confirmed.
12: 2nd TEG Submissions hosted by KEK with 17 designs.
'07.4 : Process of the 2nd TEG was finished.

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Features of SOI Monolithic Pixel detectorz

Bonded Wafer (High Resistive Substrate + Low Resistive Top Si).

zStandard CMOS Electronics (NMOS, PMOS, MIM Cap etc. ).

zMonolithic Detector, No Bump Bonds (Lower cost, Thin Device).

z

High density (Smaller Pixel Size is possible).

z

Small capacitance of the sense node (High gain V=Q/C)z

Industrial standard technology (Cost benefit and Scalability)

Explore the possibility of SOI
detector for future experiments(ILC, SLHC, Super-Belle etc.) andother applications (Medical,
Material etc.)
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SOI Pixel Process
Process

0.15μm Fully-Depleted SOI CMOS process,1 Poly, 5 Metal layers (OKI Electric Industry Co. Ltd.).

SOI wafer

Wafer Diameter: 150 mmφ,
Top Si : Cz, ~18 Ω-cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz、700 Ω-cm (n-type), 650 μm thick (SOITEC)

Backside

Thinned to 350 μm, and plated with Al (200 nm).

p+/n+ Implant andContact formation

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SOI Pixel Process Flow
SOI (50 nm)
Box (Buried
Oxide)(200 nm)

650um

Handle Waferp+n+Handle Wafern+
Handle Waferp+50~650um

Al
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Metal contact & p+ implantAl

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Copyright 2007 Oki Electric Industry Co.,Ltd34

FY05 MPW run
6"φ wafer

OKI 0.15 μm SOICMOS with
substrate implants
and contacts

Pixel, Strip
Amp/Shaper/Discri
Tr TEG ...
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First Pixel TEG

CMOS Active Pixel
Sensor Type
20 μm x 20 μm
32 x 32 pixels

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Pixel Layout
Window for Light
Illumination(5.4 x 5.4 um2)

p+ junction
Storage Capacitance(100 fF)

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2.5 x 2.5 mm237

Laser Image

β-ray (90Sr) Signal

32x32 image view with
670nm Laser and plastic
mask

Q 0.6 fC
Vsense = ≈= 70mVC
8 fF

Vdet = 10 V, Exposure Time = 7 ms
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Back Gate EffectThreshold Variation

Back Gate
Copyright 2007 Oki Electric Industry Co.,Ltd

Substrate Voltage act as Back
Gate, and change transistor
threshold.
Signal disappeared at Vdet=16V
due to the back gate effect.

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TCAD Simulations
ENEXSS :3D TCAD Simulator developed
by SELETE Consortium Japan.
Back Gate effect can be
reduced by placing p+
implant near transistors.
D = 2~40 μm

NMOS

BOX (200 nm)(5 μm wide p+, 1 x 1020 cm-3)
Bulk: n- (~6 x 1012 cm-3)
350μm
Backbias (0-100 V)
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p+ Guard for
I/O Buffer
It is hard to re-design
I/O buffers, so wejust surround thebuffer with p+ ring.

65 um

p+ ring
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p+ ring = 0V

10MHz Clockwithout p+ ringVdet=10V
Out

In

40V

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Signal Coupling Simulation
Circuit activity during measurement may affect sensor
signal due to coupling through the BOX.
metal
(0.4um x 6um)

p+ bias(0V)
BOX

p+

p+
10um

nsubstrate(10V)
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TCAD(Enexss) Simulation
Electric Field

Potential

metal(1V)

0V
0V
p+

10V

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Signal Coupling (cont.)• Pulses in SOI circuit can generate nonnegligible amount of charge to the sensor.

Input Signal @Metal• Need further simulations in more realistic
geometry.
• No effect in charge
integration type sensor.

Generated Current
Imetal• Differential signal can
reduce the effect.
• Use Double Gate/FIN SOI
Tr?
• Use some guard structure?

Ibias
Qmetal = 1750 [e]IsubQbias = 406 [e]Qsub = 938 [e]07.9.5 TWEPP-07 Yasuo Arai

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SOI Device Structure Road Map

SecondGate

FIN Tr

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Summary of this section• Processes for implanting p+/n+ to substrate andcreating contacts are established with 0.15 μm
technology.
• We could demonstrate the first SOI Pixel detects
light and β-rays.
• SOI specific issues become apparent.
- Back gate effect- Circuit to Sensor coupling• TCAD simulation is powerful to study these effects.

07.9.5 TWEPP-07 Yasuo Arai47

OUTLINESOI Device
History of SOI
Features of FD-SOI

SOI Pixel Detector
Progress of SOI Pixel R&D
FY05 MPW Results
TCAD Simulations



FY06 MPW Run
Preliminary Results :FNAL, LBL, U. of Hawaii, KEK

Summary

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Top Cell Name

FY06 MPW Run
17 designs were submitted on
Dec. 5, 2006
2.4 mm2 --- 10 chips

2.4 x
5.0 x 5.0 mm2 --- 6 chips
10.2 x 10.2mm2 --- 1 chipSome Preliminary
Results are presented.
(still under evaluation)

07.9.5 TWEPP-07 Yasuo Arai

Chip size

Affiliation

VARPIXEL

2.4 mmOsaka Univ.

TOPPIXN

2.4 mm

KEK

OKI06122.4 mmTokyo Univ.

Achip

2.4 mm

LBL

OKI_TOP

2.4 mmFNAL(BNL)

ATEG

2.4 mm

JAXA/ISAS

BTEG

2.4 mm

JAXA/ISAS

CTEG

2.4 mm

JAXA/ISAS

isas_set0612

2.4 mm

JAXA/ISAS

RADFET1

2.4 mmKEK

HawaiiNSUBSTRATE

5.0 mmU. of Hawaii

detectorPOLY

5.0 mmKEK

TOP_PIXELSTRIP

5.0 mmKEK

TOP_8PREAMP

5.0 mmKEK

TOPTEG2

5.0 mmKEK

TOPINTPIX

5.0 mmKEK

TOPCOUNT

10.2 mm

KEK
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SOI MPW Wafer

20.8 mm

20.8 mm07.9.5 TWEPP-07 Yasuo Arai

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FNAL: MAMBO - Monolithic Active pixel Matrix wit Binary cOunters
G. Deptuch

 applications• imaging detector for direct detection in electron microscopy (TEM), and soft X-rays,

design: test prototype 64x64 pixels, pitch 26μm, 4 parallel diodes /pixel (distance ~13μm),
 each pixel: CSA, CR-RC2 shaper, discriminator + 12 bit binary counter, counter reconfigurable to shift register – readout serial (caterpillar) throughall pixels.
26 μm
 pixel:• design uses:

total: 280 transistors
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FNAL: MAMBO

G. Deptuch

tests:  performed till now: measurements on test structures

Gain significantly lower and• analog channel with charge injection by pulse generator OK,
shaping much faster – seems• counter/shift register OK, (proper operation requires back-gate voltage
to be understood;
above certain level ~5V due to conflicting leakage of NMOS and PMOS
transistors in OFF state)• discriminator OK,
acquisition of full scale images is underway!

shaper:discriminator responseshaper response(5 kh+)

injecttrigger

inject delay
measured at
VBACK=5V

07.9.5 TWEPP-07 Yasuo Arai

feedback resistance
PMOS in saturation@ Vgs=const
design: 90 MΩmeasurements suggest:
5-10 MΩ (L=150nm PMOS
low VT)52

FNAL: MAMBO

lesson learnt:

G. Deptuch

 transistors in Silicon on Insulator technology are basically 5 terminal devices;• there is mutual interaction between transistors and the substrate (used as detector);• in fully depleted (FD) SOI, substrate plays role of a second gate with gate oxide
thickness equal to the thickness of buried oxide (200nm);

 measurements of low VT and high VT NMOS transistors ID(VGS): hints:

shift in threshold voltage !!! floating body and body tied tosource transistors are affected in the same degree• important is to use dense matrix of p+ implants to lower potential at the surface;• use rather low back-gate (generally it is enough VBACK=10V to deplete 50 µm of Si)- good for electron microscopy, high energy physics, etc.
07.9.5 TWEPP-07 Yasuo Araistill more to learn

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LBNL Pixel

07.9.5 TWEPP-07 Yasuo AraiPeter Denes

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Univ. of Hawaii:
Continuous Acquisition Pixel(CAP) Family
CAP1/2

CAP3 “full size” Detector

5mm
CAP4 AMS 0.35um Optoz

The area corresponds to 3250 x 1500 μm2.

z

Pixel size occupies 28.7 x 32.5 μm2.

z

The number of columns is 108 and rows is 44.

CAP5 SOI prototype
E. Martin, G. Varner
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KEK : I-V characterisiticof the detector
FY05

Round the corner of bias
ring.

Iback[uA]2.5 x 2.5 mm2 chip100

FY06(Std.)p+/n+ implant with higher E(~x4.7 deep).

80

FY06(High E Impla)

60

FY06(Std. Impla)

40

FY05 chip

20
0

0

50

100

150

Vback[V]FY06(HE)

become better, andreached to ~130V.
Micro Discharges areobserved with infrared
camera07.9.5 TWEPP-07 Yasuo AraiI = 40 μA, T = 1 min

Corner of the bias ring58

KEK : Integration Type Pixel (INTPIX)z

20 μm x 20 μm pixel(same as FY05 design)z

128 x 128 pixelsz

5x 5 mm2 chip

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INTPIX : First Image
2.56 mm0.64 mm2006 Image

2007 Image
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FY07 Submission Plan
• Next submission at the end of November (~Dec.).
• Due to OKI process movement, we will use 0.2 μm
process at the next run.
0.15 μm

0.2 μmWafer Diameter

6 inches

8 inches

Core (I/O) Voltage

1.0V (1.8V)

1.8V (1.8/3.3V)

Gate Length

0.14 μm

0.2 μmGate Oxide Thickness

2.5/5 nm

4.5/7 nm

BOX Thickness

200 nm

200 nm<100pA/μm<0.1pA/μm

Ioff

Space is still available !
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Summary• SOI device has many interesting features to use in HEP and Spaceapplications.
• We confirmed the basic operation of SOI pixel detector with OKI
0.15 μm FD-SOI technology.
• At the Second MPW run(FY06), we submited our own MPW run
with 17 designs including US and Japan Univ./Labs.
• We are planning the Third MPW run in Nov.-Dec. with 0.2 μm
technology• We welcome more people to join to use this interesting technology.

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