September 25, 2008

3D-LSI Technology
for Image Sensor
Makoto Motoyoshi
ZyCubeMitsumasa Koyanagi
Tohoku Univ./ZyCube

Pixel 2008 International Workshop @ FNAL

1

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

ZyCube History

ZyCubeFounded: 2002/3

ASET
Association of Super
Electronics Technologies

Tohoku University(Japanese Semiconductor Consortium)

Prof. M. Koyanagi (CTO)

M. Bonkohara (Chairman)

Pixel 2008 International Workshop @ FNAL

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M. Motoyoshi

September 25, 2008

Outline1．Introduction- Advantages of 3D-LSI- Potential Application

2．Technology Approach- Technology breakdown- TSV scaling, process- Bond/Stack approaches

3．TSV and μ-bump- Current technology
3D-LSI for Image Sensor- Next generation technology

4．Summary
Pixel 2008 International Workshop @ FNAL

3

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Advantages of 3D-LSI
Conventional SoC

3D-SoC

Compound semiconductor

Sync.
clock

Length of TSV:
1-50μmsegment 2D-SoC
into functional block

Short global interconnect
small RC delay, small CP
High band width
Small form factor

Long Global interconnect
large RC delay, large CP

1. Increase of electrical performances
2. Increase of circuit density
3. New Architecture (Hyper-parallel processing, Multifunction, etc)
4. Heterogeneous integration
5. Cost reduction
6. Realize high performance detector with ~100% area factor in chip
Pixel 2008 International Workshop @ FNAL

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M. Motoyoshi

September 25, 2008

3. 3D-LSIのメリット

3D Effect for Power Consumption
Estimation for MCU
・Ultra Parallel Via
interconnection ,High
speed Instruction
・Decrease the Buffer Tr.
・Low speed clock・Decrease the Internal
Circuit Tr size

BufferClockExponentialｌ decease ofPower consumption
Less
than
1／3

Internal
circuit

3D-SoC

Present 2D LSI PKG
Pixel 2008 International Workshop @ FNAL

5

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M. Motoyoshi

September 25, 2008

Potential application of 3D-LSI
Medical, HealthHome Game

Aero-space

PC, Server
Robot
DigitalConsumer
Mobile, PDA

Pixel Detector

3D-LSI

Flash Card

• High Energy Efficiency• Small Form Factor• Heterogeneous Integration

AI sensor

3DImage Sensor

3DProcessor

3DFPGA

3DMemory

CCD/CMOS sensor

CPU/MPU/MCU・GPU

FPGA/PLD

DRAM,SRAM,
Flash

Pixel 2008 International Workshop @ FNAL

6

3D-DSP

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3D-SOCASIC

M. Motoyoshi

September 25, 2008

Outline1．Introduction- Advantages of 3D-LSI- Potential Application

2．Technology Approach- Technology breakdown- TSV scaling, process- Bond/Stack approaches

3．TSV and μ-bump- Current technology
3D-LSI for Image Sensor- Next generation technology

4．Summary
Pixel 2008 International Workshop @ FNAL

8

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Determination of the 3D-LSI process
Application Definition
Supply Chainof base LSI wafers

3D-LSI
Architecture/design

TSV Dimension
NumberConductive material

3D-LSI process
Pixel 2008 International Workshop @ FNAL

9

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M. Motoyoshi

September 25, 2008

Technology Break Down
(1)Base Wafer Process- Substrate: bulk-Si, SOI,
Compound Semiconductor, MEMS
- Thinning: Grinding, Polish, CMP,
plasma etch, wet etch
- Handling: Thin wafer Support system(2)TSV formation-Via opening:
Laser drilling or DRIE
-Conductor:
Cu, W, PolySi, conductive paste-Filling method: plating, CVD, sputter, vapor deposition-Isolation:
conformal CVD, sputter,
vapor deposition

MemorySoC
Thickness Budget< 1 mmSensor chip
MM IC
MEMS
RF-IC
Analog LSI
Control IC
Power IC
Logic ICFlash memory

DRAM

Control IC

DRAM
Cache SRAM
Interposer

CPU

Interposer(4)Stacking approach:(3) New material(5)Interposer- Technology: Metal Thermo compression,-Adhesive
Direct Oxide (SiO2), Adhesive bonding…
-Substrate --silicon or organic?
(permanent/temporally）-Bump metal, barrier metal - Embedded chips & passives? - Integration scheme:
CoC, CoW or WoW?
-Conductive paste
Face to face or face to back?
-etc-Accuracy?
-Throughput ?
-How many dies to stack?
Pixel 2008 International Workshop @ FNAL

10

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Outline1．Introduction- Advantages of 3D-LSI- Potential Application

2．Technology Approach- Technology breakdown- TSV scaling, process- Bond/Stack approaches

3．TSV and μ-bump- Current technology
3D-LSI for Image Sensor- Next generation technology

4．Summary
Pixel 2008 International Workshop @ FNAL

11

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Road Map of TSV & Bump pitch
TSV / Bump pitch (μm)

100

FC pad pitch
CIS

SensorRF SW

Conv. design (2D) with small adjustment

Memorycamera module

For form factor driven market

Sensor Sensor

4G radioGaAs
polymer

10

Part
ia

lly 3
D de

High Performa
nce ApplicationFPGA, CPU, D
SP,CIS)

dica
ted
CIS

Des
ign Memory
FP G

A

Sensor chip
RF-IC
MM
MEMS
Analog IC
Control IC
Power
IC
LSI
Logic
Flash
IC
DRA
memoryCacheCPU
M SRAM
Interposer

Full
y

1.0

IP21

IP
IP
IP2n

3D d
edic
ated

IP
IP22
IP IP

Des
ign

SOI base 3D-LSI (very thin WoW)High perfor
mance CPU
s

0.1

2008

2010

2012

Pixel 2008 International Workshop @ FNAL

12

Year

2014

ystem

2016

Copyright © ZyCube Co., Ltd. All rights reserved

2018
M. Motoyoshi

September 25, 2008

Determination for 3D-LSI process
and TSV dimension
Application SoC, Memory , Sensor, FPGA
Supply Chain of base wafer
procure each wafers from one supplier or multi-supplier
New design or stack conventional LSI chips
Main purpose of 3D-LSI-Performance-Form Factor-Cost reduction-New architecture
TSV dimension
TSV diameter <1um

~10um 10~50um>50um

TSV depth<10um

10~100um>100um

TSV density<106/mm2

102~105/mm2<102/mm2

TSV process Choice Via First or Via Last

TSVs with very wide range of diameter can be realized now.
But there are few solution which satisfy target application,base wafer supply chain, purpose of productize 3D-LSI.
Pixel 2008 International Workshop @ FNAL

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M. Motoyoshi

September 25, 2008

TSV process classification
Allowable max. process temperature

1000ºC >Stacking

450~300ºC >600ºC >BEOL

MOS

Interlayer

After MOS

After
1st Interlayer

FEOL
Well
Isolation

Thinning

Handleglass

MOS
After BEOL

Before MOS

process

HandleWafer

HandleWafer
After Thinning

TSV
step
FEOL:Front End of Line
BEOL:Back End of Line

HandleWafer

Via first

Pixel 2008 International Workshop @ FNAL

Via last
15

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M. Motoyoshi

September 25, 2008

Outline1．Introduction- Advantages of 3D-LSI- Potential Application

2．Technology Approach- Technology breakdown- TSV scaling, process- Bond/Stack approaches

3．TSV and μ-bump- Current technology
3D-LSI for Image Sensor- Next generation technology

4．Summary
Pixel 2008 International Workshop @ FNAL

17

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M. Motoyoshi

September 25, 2008

Various Kinds of Wafer Bonding Methods (1)Organic film （Adhesive）

Oxide

Multi-level
metallization

Multi-level
metallization

Si

Si

Adhesive BondingSi

Direct Oxide Bonding

Pixel 2008 International Workshop @ FNAL

Metal

18

MicrobumpMulti-level
metallization

Direct Metal Bonding

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Various Kinds of Wafer Bonding Methods (2)Organic
film

Si

Oxide

MicrobumpMulti-level
metallization

Adhesive/ Metal Bonding

Pixel 2008 International Workshop @ FNALSi

MicrobumpMulti-level
metallization

Oxide/ Metal Bonding

19

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M. Motoyoshi

September 25, 2008

Various Kinds of Wafer Bonding Methods (3)(Tohoku University)

Adhesive
Metal

Si

MicrobumpMulti-level
metallization

Multi-level
metallizationSi

Wafer Alignment

Temporary Bonding(Metal Bonding)

Pixel 2008 International Workshop @ FNAL

20

Si

Multi-level
metallization

Adhesive Injection

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M. Motoyoshi

September 25, 2008

Process Sequence of Adhesive Injection Method

(a)

(b)

(c)

(d)

T. Matsumoto and M. Koyanagi et al, SSDM, pp.460-461, 1997.

Pixel 2008 International Workshop @ FNAL

21

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M. Motoyoshi

September 25, 2008

Fabrication Sequence of 3D LSI
LSI wafer (face-to-face)

2-D LSI

Through Si Via(TSV)Thinning andbump formation

Alignment andgluingThrough Si Via(TSV)

3-D LSI
Through Si Via(TSV)Pixel 2008 International Workshop @ FNAL

22

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Outline1．Introduction- Advantages of 3D-LSI- Potential Application

2．Technology Approach- Technology breakdown- TSV scaling, process- Bond/Stack approaches

3．TSV and μ-bump- Current technology
3D-LSI for Image Sensor- Next generation technology

4．Summary
Pixel 2008 International Workshop @ FNAL

24

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

The necessity of 3D-LSI Technologies for an Image sensor【Conventional COB 】
Lens mount

Cover glass
Wire bondSensor Chip
PCB or Flex

【ZyCSPTM】
cover glass

cavitypixel array

Thinneradhesive

Smaller

Cover glass

sensor LSI chip
Sensor Chipbond padTSVsolder ball

Pixel 2008 International Workshop @ FNAL

Using wafer thinning & TSV techniques of 3D-LSI technology

25

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M. Motoyoshi

September 25, 2008

50μmφ (80μm pitch) TSVTSVSi~110μmInterlayer
Bond Pad

109.9μm

113.7
100.0

50.0
3.8
-20.0

Pixel 2008 International Workshop @ FNAL

26

0.0

20.0

40.0

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60.0

(μm)

M. Motoyoshi

September 25, 2008

ZyCSPTM Process Sequence (1)LSI waferApplyhandle wafer

adhesivehandle wafer

Wafer thinning(BG/Polish)
TSV patternphotoresist mask

Backsidelithography

・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ ・・・・・・・・・・・・・・・・・・・ ・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

Si

Through Hole

Deep Si etch・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ ・・・・・・・・・・・・・・・・・・・ ・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

TSV
20μm

TSV after deep Si etch
Pixel 2008 International Workshop @ FNAL

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M. Motoyoshi

September 25, 2008

TSV after SiO2 RIE
TSV size:60μmφ
depth:100μm
a-carbon

M1

TSV
M2
M3
M4

Pixel 2008 International Workshop @ FNAL

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M. Motoyoshi

September 25, 2008

ZyCSPTM Process Sequence (2)Side wall insulation

Applying metal
conductor

Form Backside
Interconnect (BI)・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ ・・・・・・・・・・・・・・・・・・・ ・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ ・・・・・・・・・・・・・・・・・・・ ・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ ・・・・・・・・・・・・・・・・・・・ ・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

Pixel 2008 International Workshop @ FNAL

29

BI pattern
TSV cross section
after forming BI

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

ZyCSPTM Process Sequence (3)Replace handle wafer
with Cover Glass・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ ・・・・・・・・・・・・・・・・・・・ ・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

adhesivebump cover glass
・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ ・・・・・・・・・・・・・・・・・・・ ・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

Forming Bump

Sensor LSI Chipadhesive

cover glass
・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ ・・・・・・・・・・・・・・・・・・・ ・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

Dice

Package
Cover Glass

Mount on PCB
TSV

60°angle cut

CavityEncapsulation

Edge of ZyCSPTM

Sensor Chip
PCB

Pixel 2008 International Workshop @ FNAL

30

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M. Motoyoshi

September 25, 2008

ZyCSPTM mounting on the test board

TSV

cavitySensor LSI Chipcover glass

bump

module test board

Pixel 2008 International Workshop @ FNAL

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M. Motoyoshi

September 25, 2008

The ZyCSPTM for the camera module
1.3M pixel Sensor LSI(a) Top(c) ZyCSP mounting on module board(d) ZyCSP module with a Lens unit(b) backside

Back

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M. Motoyoshi

September 25, 2008

2M pixel Sensor CSP

Pixel 2008 International Workshop @ FNAL

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M. Motoyoshi

New Chip size Package

September 25, 2008

Working Sample Test System

Pixel 2008 International Workshop @ FNAL

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M. Motoyoshi

September 25, 2008

Fabrication Processes Comparison
Conventional Process
Device Ready
Wafer

Micro Lens

Yield Loss

Low Class CR

Dust

Si DustSensor Chip

BG/DC

Material Dust
Cover Glass

Au wire

DB/WB

PCB

Lens CoverZyCSPTM Process
Low Class CR(~1000)

Cleanroom classiufication（～１）
Back Side

・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

TH-ElectrodeSensor Chip

Bump

BI-Electrode・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

Cover Glass
PKG

・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・

Cover Glass

Lens Cover

PCB

DC

PKG Mounting

High Yield utilizing Wafer Level Process
Pixel 2008 International Workshop @ FNAL

36

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Outline1．Introduction- Advantages of 3D-LSI- Potential Application

2．Technology Approach- Technology breakdown- TSV scaling, process- Bond/Stack approaches

3．TSV and μ-bump- Current technology
3D-LSI for Image Sensor- Next generation technology

4．Summary
Pixel 2008 International Workshop @ FNAL

37

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Current 3D-LSI Technologies
Advantages-Available to use existing LSI chip design w/o or w/ minor modification-Reduce foot print eg. multifunctional SoC, High density memory

Get the best performanceout of 3D-LSI

Next Generation 3D-LSI Technologies

Pixel 2008 International Workshop @ FNAL

38

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M. Motoyoshi

September 25, 2008

Next Generation 3D-LSI Technologies
5Key technologies
Wafer thinningless than 30μm
Over coat

metal

SiO2

N+

N+

Nch-MOSFET

1st layer

P+ SiO2

P+SiO2

Pch-MOSFET

Adhesive

metal

Chip Alignment
High speed alignment
with less than0.2μm
alignment error

N+

P+

P+

SiO2

SiO2

N+

2nd layer

Pch-MOSFET

PWell

metal

metal
P+

SiO2

N+

N+

Nch-MOSFET

NWell

PWell

SiO2

P+

3rd layer
NWell

Si Substrateµ- bumpµ-TSVless than 5μm pitch

less than 5μm pitch

Pixel 2008 International Workshop @ FNAL

39

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M. Motoyoshi

September 25, 2008

SEM Cross Section of Poly-Si TSV(Via first)

2.5um
Poly-Si

55um

SiO2

2.4um

Si

(a) Si deep trench etching(b) Filling with Poly-Si
T. Matsumoto and M. Koyanagi et al., SSDM, 1995.

Pixel 2008 International Workshop @ FNAL

41

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M. Motoyoshi

September 25, 2008

SEM Cross Section of W/ Poly-Si TSV(Via first or Via before BEOL)
Adsorption time
tad = 1sec
Reduction timetred = 15sec
Evacuation time
tevc1 =5sec
tevc2 = 5sec
Deposition temperature
350℃

Y. Igarashi and M. Koyanagi et al., SSDM, 2001.

Pixel 2008 International Workshop @ FNAL

42

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M. Motoyoshi

September 25, 2008

Schematic Diagram of micro-bump structure using new
micro-bump fabrication process
Bump pitch
metal padbump openingδ

Metal padbump pitch

5.0 μm

Metal pad

4.0 x 4.0 μm

Bump opening

3.0 x 3.0 μm

Bump size

2x2 μm (bottom)

δOver coat

Metal pad

Clearance groove (δ) between bump opening and bump are formed by self-aligned process
Tohoku Univ. / ZyCube
Pixel 2008 International Workshop @ FNAL

45

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M. Motoyoshi

September 25, 2008

Micro-bump

2μm x 2μm Bumps

In/Au
polyimide

2um

Tohoku Univ. / ZyCube
Pixel 2008 International Workshop @ FNAL

46

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M. Motoyoshi

September 25, 2008

5μm pitch μ-bump
TEG chip

5μmUpper Chip

Lower Chip
Bond Pad

Daisy Chain with 104 m-bumps

Upper Chip

Lower Chip

Plain View（IR microscope)

Cross section
Pixel 2008 International Workshop @ FNAL

Tohoku Univ. / ZyCube

47

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M. Motoyoshi

September 25, 2008

Image sensor module with μ-bump & μ-TSV

On chip lens
TSV

color filter

Photo diodemicro-bumpadhesive

Si subLogic LSITSVCMOS Image sensor with TSV

Si subLogic LSI

Back illuminated type CMOS Image Sensor

By connecting the back illuminated type CMOS image sensor to Logic LSI, a highspeed Pixel detector system with 100% fill factor will be realize.
Pixel 2008 International Workshop @ FNAL

49

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M. Motoyoshi

September 25, 2008

High Speed Parallel Processing
Image Sensor with Memory
32 x 32 pixels
6M/4096(5859)pixel arrays
Pixel array

Dec ADC

1024x12 bit data (serial)
5859 parallel data
1024bit
32 x 32 x 12 (12288k) 12bit
W
rit

e

n

1024 pixel data (serial)
5859 parallel data

ci
rc
ui
t

Decoder
AD Converter

(0,3)
(0,2)
(0,1)
(0,0)

Memory Array

Pixel 2008 International Workshop @ FNAL

50

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12xn

M. Motoyoshi

September 25, 2008

3D LSI Prototype Chips Fabricated in Tohoku Univ.
Real-Time Image Processing System

3D shared memory

Image Sensor
ADC
ADC

AMP & ADC

ADC

RegisterProcessor
H. Kurino, M. Koyanagi et al., IEDM (1999)

K. W. Lee, M. Koyanagi et al., IEDM (2000)

3D artificial retina chip
Light

light

3D microprocessor chip

Quartz glass

DRAM

Photoreceptor layer

DRAM
DRAM

Horizontal cell &bipolar cell layer

SRAM

Ganglion cell layer

T. Ono, M. Koyanagi et al., IEEE COOL Chips (2002)

M. Koyanagi et al., ISSCC (2001)

Pixel 2008 International Workshop @ FNAL

Processor

51

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M. Motoyoshi

September 25, 2008

SEM Cross-Sectional View of 3-D Microprocessor
Chip Fabricated by Wafer-to-Wafer Bonding

Control Logic

Through–Si via
Multi-core CPU’s

Pixel 2008 International Workshop @ FNAL

52

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M. Motoyoshi

September 25, 2008

Cross-Sectional Structures of Human Retina and3D Artificial Retina Chip

Quartz glass

Photoreceptor layer

Horizontal cell andbipolar cell layer

Ganglion cell layer(a) human retina
Pixel 2008 International Workshop @ FNAL(b) 3D retina chip
55

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M. Motoyoshi

September 25, 2008

Photograph of 3D Artificial Retina Chip

1st Layer(Receptor cell layer)
2nd Layer(Retina cell layer)
3rd Layer(Pulse modulator layer)

Vertical Interconnection
Pixel 2008 International Workshop @ FNAL

56

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M. Motoyoshi

September 25, 2008

Photograph of Respective Chip in 3D Stacked Image Sensor
Chip with Three Stacked Layers

1st Layer

2nd Layer

3rd Layer(Photosensor circuit) (Register circuit) (ADC & ALU circuit)( Chip size : 6 mm x 6 mm, 112 pins )Pixel 2008 International Workshop @ FNAL

57

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M. Motoyoshi

September 25, 2008

Photomicrograph of 3D Artificial Retina Chip

3D Artificial Retina Chip

Quartz Glass
Stacked Chips

Pixel 2008 International Workshop @ FNAL

58

WiringSubstrate(Si)

Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Configuration of 3D Super Chip
Sensor chip
MEMS
RF-IC
MM IC
Analog LSIPower IC Control IC
Logic ICFlash memory
DRAM
Cache SRAM
CPU
Interposer
Tohoku Univ. / ZyCube
Pixel 2008 International Workshop @ FNAL

59

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M. Motoyoshi

September 25, 2008

Current 3D-LSI stack approaches
COC (chip on chip)

COW (chip on wafer)

WOW (wafer on wafer)

stack

dicingProcess cost

High

High~Middle

Low

Stack chips withdifferent chip size

Easy

Easy

Impossible

Chip alignment
accuracy<0.2μm (3σ)

Difficult from economical stand point

Miscellaneous

dicingpossible ?
Need high yield wafers

Need a high speed COW technology with the highalignment accuracy and the practical process cost
Pixel 2008 International Workshop @ FNAL

60

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M. Motoyoshi

September 25, 2008

High speed and high accuracy Chip Alignment

Requirement

Alignment Error< 0.2um
TAT (turn around time) ~ wafer process

In order to reduce cost, short process time (batch process)is indispensable
Pixel 2008 International Workshop @ FNAL

61

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M. Motoyoshi

September 25, 2008

3-D Technology Based on New Chip-to-Wafer Bondingin Tohoku University : Super-Chip Integration

Chip Self-Assembly

Batch alignment
Wafer testing

Sorting of KGDs

Chip-to-wafer
3-D integration
by self-assembly

3rd layer chips

2nd layer chips

3-D LSI
1st layer chips
Pixel 2008 International Workshop @ FNAL

62

Supporting LSI wafer
Copyright © ZyCube Co., Ltd. All rights reserved

M. Motoyoshi

September 25, 2008

Stack
Approach

WoW Bulk

Before MOS
Poly-Si
Tohoku Univ.
(ZyCube)
IBM
Dalsa

FEOL
after BEOL
（After MOS） before Stack
W, Cu, etc
Poly-Si, W
TSMC
Tezzaron
RPI
Ziptronix
Chartered Semi.

SOI

Stack inwafer process

Tohoku.U
ZyCubeToshiba
Samsung
IMEC

Tohoku U.
EｌpidaNAND Memory

Pixel 2008 International Workshop @ FNAL

after Stack
W, Cu, etc
Ziptronix
Albany NanoTech
IMEC
Samsung・・・・・・・・・・・
IBM
MIT（Lincoln Lab.）
RPI

Tohoku.U

CoW w/
self-assembly Tohoku U.
technique

CoC

Via last

Via first

Low

Frounhofer IZM
ZyCube/Tohoku U.
Low
Samsung
CEA-LETI
Ziptronix
IMEC ・・・・・・・・・・・
ZyCube<Sidewall connection>
ASET
TESSERAIntel, Infineon, IMEC,
High
3DplusSamsung, Toshiba,
Fujitsu
VCI
Renesas ,NEDO

Chip Stackwith different
chip size

TSV process
Conductor Mat.

Processcost

3D-LSI Process Selection --Which is best ?--Impossible

Easy

Easy

TFT-NAND（Samsung）
BiCS-NAND(Toshiba）

65

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M. Motoyoshi

September 25, 2008

Summary
1. The Current & future 3D-LSI technologies with TSV were described.
2. Advantages of 3D-LSIs are(a) Increase of electrical performances(b) Increase of circuit density(c) New Architecture (Hyper-parallel processing, Multifunction, etc)(d) Heterogeneous integration(e) Cost reduction

3. Many 3D-Integration approach have been reported. Considering supply
chain of the base LSIs and variety of application, it is difficult to unify.
4. The CSP for 1.3M pixel CMOS image sensor was successfully fabricatedwithout performances degradation.
5. By connecting the back illuminated type CMOS image sensor to Logic LSI, ahigh speed Pixel detector system with 100% fill factor will be realize.
3. In order to enter mass market for 3D-LSI, suppressing a rise in price ofchip stack is essential. In this standpoint, for realizing 3D-Super chip,
the high speed and high accurate CoW will be indispensable.
Pixel 2008 International Workshop @ FNAL

66

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M. Motoyoshi