Reduction techniques of the back gateeffect in the SOI Pixel Detector
R. Ichimiya (KEK)*for the SOI Pixel collaboration
http://rd.kek.jp/project/soi/
SOI Pixel Collaboration
KEK : Y. Unno, S. Terada, Y. Ikegami, T. Tsuboyama, T. Kohriki, Y. Ikemoto, T. Miyoshi,
K. Tauchi, R. Ichimiya, Y. Fujita, D. Nio, Y. Arai (representative)
Tsukuba Univ. : K. Hara, H. Miyake, T. Sega, M. Kochiyama
Osaka Univ.: K. Hanagaki, J. Uchida
Tohoku Univ. : Y. Onuki, Y. Horii, H. Yamamoto, Y. Takubo, T. Nagamine, Y. Sato
Kyoto Univ. : T. Tsuru, H. Matsumoto, S. G. Ryu
Kyoto U. of Education : R. Takashima, A. Takeda
JAXA/ISAS : H. Ikeda, D. Kobayashi, T. Wada, H. Nagata
RIKEN : T. Hatsui, T. Kudo, T. Hirono, M. Yabashi, Y. Furukawa, A. Taketani. T. Kameshima
LBNL : M. Battaglia, P. Denes, C. Vu, D. Contarato, P. Giubilato, L. Glesener
FNAL : G. Deptuch, R. Yarema, M. Trimpl, R. Lipton,U. of Hawaii : G. Varner, M. Cooney, H. Hoedlmoser, H. SahooINP, Krakow : P. Kapusta, H. Palka
INFN Padova : Dario Bisello, Serena Mattiazzo, Devis Pantano, Piero Giubilato
OKI Semiconductor Co. Ltd. : K. Fukuda, I. Kurachi, M. Okihara , ....
* ryo@post.kek.jp1Outline
1.
2.
3.
4.

SOI technology and SOI pixel detector
Pixel Test Results
On going R&Ds
Summary2

Hybrid Pixel v.s. SOI pixel

SOI Pixel◦◦

Hybrid Pixel (conventional pixel detector)◦Fabricate Sensor and Readout chip individually.

◦Make contacts by bump bonding for each pixel.

◦Granuarity is limited (~50um) from bump-bonding
fabrication .

◦Speed and Gain reduction by parasitic capacitance.

◦It becomes thick detector by bump-bondingstructure.

◦◦

◦
◦
◦
◦

Bonded wafer: High Resistivity (Sensor) and Low
Resistivity (CMOS).
Truly Monolithic Detector◦ High Density, Low material, Thin device
No mechanical bonding.
◦ High yield, Low cost.
Fully depleted sensor with small capacitance of thesense node.
◦ ~10fF, High gain, Low noise
Based on Industrial standard technology◦ Cost benefit and scalability.
No Latch-up, Radiation hardness, Low power.
Low to High temperature operation (4K-300C).
…
3

Oki 0.2µ0.2µm FDFD-SOI Pixel Process
Process

0.2µm Low-Leakage Fully-Depleted SOI CMOS (OKI)
1 Poly, 4 Metal layers, MIM Capacitor, DMOS option
Core (I/O) Voltage = 1.8 (3.3) V

SOI wafer

Diameter: 200 mmφ,
Top Si : Cz, ~18 Ω-cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz、700 Ω-cm (n-type), 650 µm thickBackside

Thinned to 260 µm, and sputtered with Al (200 nm).

An example of a
SOI Pixel crosssection

Depletion layer
4

SOI Pixel process flow
SOI (40 nm)
Box (BuriedOxide)(200 nm)

650um

Handle Waferp+n+

Handle Wafern+
Handle Wafer
Alp+

50~650um

5

Metal contact & p+ implant

1st AlHandle Wafer
Copyright 2007 Oki Electric Industry Co.,Ltd6

8inch SOI Wafer

7

KEK SOI Multi Project Wafer (MPW) run•3 MPW runs are scheduled in 2009 FY.
•We welcome your Designs.

http://rd.kek.jp/project/soi/MPWrun/

8

Back gate effect on SOI pixelTransistors locate very close (=200nm) to the Sensor where high voltage applied.

Substrate (Sensor) Voltage acts as Back Gate in a MOS transistor, and change its
threshold voltage.

Unless we solve this dilemma, we cannot operate this detector with fully depletedcondition.

Egate
Ebias

9

Buried pp-well technologyIn order to shield the transistors fromelectrical field from the Sensor,

Implant p-Well through SOI and BOX
layer. (buried p-Well)

Benefits:SOIBOX◦ Suppress back gate effects.
◦ Reduce electric field around p+sensor.
◦ Less electric field in BOX toimprove radiation hardness.

Essential and breakthrough technology
to overcome the back gete effect.
10

Id-Vgs curveunder bias voltage applied
NMOS

PMOSgate opens.

w/o BPW

w/ BPW=0V•Back gate effect is effectively suppressed by BPW even at 100V bias voltage.

11

Pixel test Results

CNTPIX3 pixel

12Breakdown voltage & leak current
Vbreak down ~ 162V
Ileak ~ 10nA@100V

R ing TEG IV
1.0E-03Vbreak down ~ 230V

1.0E-04

2.5mmx2.5mm chip (INTPIX3)

Ileak ~ 80nA@230V] 1.0E-05
A[tne1.0E-06
rruCeg1.0E-07akaeL
1.0E-08

D3D2

1.0E-09
1.0E-10050

100150V back [V ]TEG

20025013

Integration type Pixel (INTPIX)

readout circuit (/pixel)

20µm x 20µm pixel

14

SOI pixel Laser Images
2008

INTPIX2

2.56 mm2006
0.64 mm32x32

with Plastic mask

128x12815

X-ray Irradiation test

X-ray generator: Rigaku FR-D

Target: Cu (Cu Kα ~8keV)

Power: 30-35 kV, 10-30mA

Intensity: ~104 photons/pixel/sec@30kV, 10mA

INTPIX2(pixel size=20µmx20µm)

slit w=25µm

X-ray Test Chart
25 µm Slit is well separated.

12.5[lp/mm]162016

Counting type Pixel (CNTPIX)
5mm



Discriminated signal is counted by a16-bit counter.

Energy window can be set in each pixel.

15.4mm

CNTPIX3(row:218 x column:72)
Readout circuit (/pixel)

64x64 µm2

17

SOI pixel Laser Image(CNTPIX)
X-rayTubeSOIPixel•Image taken by X-ray irradiation

X-ray

40kV-40mA
Substracted by background countIntegration time 64ms / vth 350mVVback=15V

Counter works well18

On going R&Ds


Process improvement:

Larger sensitive area; stitching,…

◦ High radiation tolerance, high resistivelywafer, deeper depletion layer, waferthining,…

3D integration

19

3D Integration with ZyCube µ-bump
Use ZyCube Co. Ltd.(Japan) µ-bump bonding (~5µm pitch) technology.
 This enables◦ Dead-Area Free Large pixel detector.
◦ ADC integration,…

5µm20

3D Integration

21

Summary
The SOI Pixel detector is a unique and attractive monolithic pixel detector.
It features such as high speed, low material budget, high resolution,…
 As SOI pixel detector uses commercial mass production process, it has
cost benefits and scalability. (Moore’s Law)
 We have overcome the back gate effect (electrical field of bias voltagechanges transistor’s threshold voltage) by Buried p-well (BPW)
implantation. Now SOI pixel detector becomes practical detector.
 We have confirmed good sensitivity of the SOI pixel detector to Light,
X-rays and charged particles. They functioned well as expected.
 We have done 4 MPW runs. Each run includes 15~25 designs from manyinstitutes.
 In this FY2009, we are scheduling 3 MPW runs.
 Improving SOI process with Oki Semiconductor Co. Ltd. to improve theperformance, and trying 3D integration with ZyCube Co. Ltd.
 we would like to contribute to future particle-physics experiments such as
SHLC upgrade, ILC or Super B factory
22

Backup23

24

PDPD-SOI v.s. FD
FD--SOI

25

PDPD-SOI v.s. FD
FD--SOI (2)26CNTPIX3• 4 kinds of Pixel Block
216 x 72 (15,552) pixels• 5.0 x 15.4 mm2 chip size
• 64 x 64 um2 pixel size
• Enable Tiling27