Basic research on SOI pixel detectors with internal gain
based on avalanche multiplication

Bipin Subedi
Master’s Program in Physics

Submitted to the Graduate School ofPure and Applied Sciencesin Partial Fulfillment of the Requirements
for the Degree of Master of Scienceat theUniversity of Tsukuba

February 2017

2

Basic research on SOI pixel detectors with internal gain
based on avalanche multiplication

Bipin Subedi
Master’s Program in Physics

Submitted to the Graduate School ofPure and Applied Sciencesin Partial Fulfillment of the Requirements
for the Degree of Master of Scienceat theUniversity of Tsukuba

February 20173

4

Abstract

Modern silicon detectors are required to have good recording efficiency of ionizing
radiation, high response time, high spatial resolution, resistance to radiation, 2-dimensional
readout, etc. but it is difficult to achieve them all using traditional detector technologies. SiliconOn-Insulator (SOI) technology has been shown to have those advantages including small pixel
size, low power consumption, greater radiation tolerance, etc. Using SOI technology, monolithic
pixel detectors can be fabricated by separating CMOS circuit and semiconductor detector layerswith a Buried Oxide (BOX) layer in between.
New type of Avalanche Photodiode (APD) was designed at KEK, Japan using SOI
technology. Currently, novel photodetectors with high response time and sensitivity withadequate gain are being sought and our SOIAPD is a potential candidate expected to achieve that
quality. It is the first time in the world that SOIAPD was designed, fabricated and tested
successfully. From this research, the SOIAPD has been shown to operate with gain of 10 times ~1000 times. Other characteristics of the SOIAPD like temperature dependence and radiation
tolerance were also tested which showed versatility of its operation in various conditions.
Although the current SOIAPD was tested for its electrical characteristics by direct contact fromthe sensor electrodes, the next step would be to integrate CMOS circuits like amplifier andshaper above the BOX layer to enhance the signals from sensor. Usable Double-SOI structures
also could be implemented to enhance radiation tolerance. In the future, SOIAPD can be
expected to be developed for use as detectors in high energy physics experiments as well as
various industrial applications.

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Contents
ABSTRACT..................................................................................................................................... 5

Chapters
1. Introduction of Semiconductors ....................................................................................................... 9
1.1 Electrical properties of solids and band theory ................................................................ 8
1.2 Types of semiconductors .................................................................................................11
1.2.1 Intrinsic semiconductors ......................................................................................11
1.2.2 Extrinsic semiconductors .................................................................................... 12
1.2.2 .1 p-type semiconductor............................................................................ 12
1.2.2 .1 n-type semiconductor............................................................................ 12
1.3 p-n junctions ................................................................................................................... 13
1.3.1 Forward and reverse bias of p-n diode ............................................................... 14
1.3.2 p-n junction breakdown...................................................................................... 15
1.3.2 .1 Avalanche breakdown .......................................................................... 15
1.3.2 .2 Zener breakdown ................................................................................. 15
1.4 Photodiode ..................................................................................................................... 16
1.4.1 Avalanche photodiode(APD) ............................................................................ 17

1.5 Semiconductor Detectors .......................................................................................... 21
1.5.1 Large Hadron Collider (LHC) .................................................................. 22
1.5.2ILC (International Linear Collider) ........................................................... 23

2. SOI pixel detector .................................................................................................................... 24
2.1 Introduction to SOI pixel detectors ................................................................................ 24
2.2 SOI Manufacturing process ..................................................................................... 25

2.3 SOI-CMOS .............................................................................................................. 27
2.3.1 Monolithic-type SOI detector ............................................................................. 28
2.4 Problems with SOI detectors .......................................................................................... 29
2.4.1 Back-gate effects ................................................................................................ 29
2.4.2 Crosstalk ............................................................................................................. 29
2.4.3 Radiation tolerance ............................................................................................. 30

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2.4.3.1 SEE (Single Event Effect) ..................................................................... 30
2.4.3.2TID (Total Ionizing Dose) effect ............................................................ 30
2.5 The Double SOI structure .............................................................................................. 29
3. SOI APD .................................................................................................................................. 34
3.1 SOIAPD TCAD Simulation ........................................................................................... 38
3.1.1 Process Simulator ............................................................................................... 38
3.1.2 Device Simulator ................................................................................................ 39
3.1.3 Plotting tool ........................................................................................................ 40
3.1.4 Plotting tool ........................................................................................................ 40

4. SOIAPD Measurements ........................................................................................................... 45
4.1 IV and CV Measurement ....................................................................................... 45
4.2 Temperature Dependence ...................................................................................... 50
4.3 LED response ........................................................................................................ 54
4.3 Co-60 γ irradiation............................................................................................... 61

5. Summary and conclusion ......................................................................................................... 65

Acknowledgement…………………………………………….……………………………….….66
Bibliography……………………….………………………………………………………….......67
List of Figures……………………………………………………………………………………...70
List of Tables………………………………………………………………………………………73
Appendix 1 (TCAD source code) ………………………………………………………………….74
Appendix 2 (TCAD simulation models)……………………………………………………………81

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Chapter 1

Introduction of semiconductors

1.1 Electrical properties of solids and band theory
Electrical properties of materials can be explained properly with the help of band
theory. According to the Pauli’s exclusion principle, electrons in a single atom occupy
discrete levels of energy, no two energy levels in an atom can have the same energy andeach energy level can contain at most two electrons. When multiple atoms (N) cometogether to form a solid, the energy levels in individual atoms interact with the energy
levels of the neighbouring atoms which causes shift in energy levels and since no morethan two electrons can occupy the same energy level, N distinct energy levels withslightly different energy are created forming a broader band of energy levels or valenceband as shown in fig1.

9

Figure 1 Energy levels and bandgap

Conductivity of a material is determined by whether free electrons are available in the
conduction band or not. In insulators, there is a large energy gap (forbidden gap)
between the valence band energy and conduction band energy level due to which theelectrons can’t move freely to the conduction band at room temperature . In case of
conductors, the valence band overlaps with the conduction band and electrons canfreely move to it causing the flow of electric current. However, for semiconductors, theforbidden energy gap between the two bands is sufficiently small to make it mucheasier for significant numbers of electrons to move across this gap and go from thevalence band to the conduction band. This can happen if suffic ient energy is supplied,for example if there is some thermal excitation. Thus, semiconductors exhibit increased
conductivity with increasing temperatures. In many semiconductors, a temperature
increase of 10 K will permit a doubling of the numbers of elec trons in the conduction
band.

10

Figure 2 Conduction band, valence band and bandgap

Fermi function can be used to find the probability that an available energy level will beoccupied by an electron at a given temperature. Fermi function (f(E)) is the probability
that a level with energy E will be filled by an electron.
f(E) =1𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇 + 1

In the equation above, k B is Boltzmann’s constant, 8.62×10−5 [eV/K], and T is thetemperature in degrees Kelvin. E F is called the Fermi energy or Fermi level. It isdetermined as the energy point where the probability of occupancy by an electron isexactly 50%, or 0.5. Using the Fermi function, it can be found that the higher thetemperature, greater the chance that the electrons can bridge the band gap to participate
in electrical conduction as shown in fig 3. The Fermi function gives a finite value in the
bandgap but there the electron population density in the region is still 0 as electron
population density is given by the product of Fermi function and the electron density ofstates. At 0K, the fermi Function is 0 (for E > E f ) and there are no electrons in the
conduction band although energy levels are available. At higher temperatures, both thedensity of states and the Fermi function have finite values in the conduction band soelectric conduction becomes possible.

11Figure 3 Mechanism of electrical conduction in semiconductors

1.2 Types of semiconductors
1.2.1 Intrinsic semiconductors
At low temperatures, pure or undoped semiconductors (intrinsic semiconductors)
have very low electric conductivity. Each Si atom has four electrons in its valenceshell and need four more electrons to achieve more stable state, so each Si atom
makes covalent bonds with four surrounding Si atoms sharing 1 electron fromeach. As all the valence electrons are involved in forming covalent bonds, no freeelectrons are available, hence low conductivity of intrinsic semiconductors. But,
since the energy band gap (1.09eV of Si) between valence band and conduction
band in Si is smaller compared to insulators, relatively smaller excitation energy(in the form of heat etc.) is sufficient for pushing significant number of electrons
to valence band for current flow.

12Figure 4 Intrinsic semiconductor

1.2.2 Extrinsic semiconductors
As explained in the above paragraph, intrinsic semiconductors have low conductivity
and have no use as they are, but the trick to make them useful is by changing theirelectric properties by adding impurities. Adding impurities (dopants) in to intrinsic
semiconductors is known as doping and it makes the semiconductor extrinsic. Two typeof semiconductors can be manufactures by doping different types of dopants , n-type andp-type.

1.2.2.1 p-type semiconductor
Group-III elements in the periodic table such as Boron (B), Aluminium(Al) have 3
electrons in their valence shells. The 3 electrons make covalent bonds with 3
surrounding Si atoms but the dopant atom still wants one more electron (h ence called
acceptor), which causes a ‘vacancy’ of an electron, also called a hole. Such hole canattract electron from nearby Si atom, stabilizing itself but leaving hole in the Si atomand so on, thereby propagating the hole. Such hole can be considered as a positive
charge that can travel through the valence band of the material . Such type ofsemiconductors (called p-type semiconductors) contain more holes in the valence band
than electrons in the conduction band, so holes are the majority carriers and e lectrons
are the minority carriers.

1.2.2.2 n-type semiconductor
However, if atoms of Group-V elements like Phosphorus(P) or Arsenic(As) to theintrinsic semiconductor, n-type semiconductor is formed. Such dopant elements contain
5 electrons in their valence shell and therefore have an excess electron when they makecovalent bonds with 4 surrounding Si atoms. These kinds of dopants are called donors
as they provide free electrons to the semiconductor. The extra free electron s can easily

13

jump to the conduction band and enable conduction of electric current since suchelectrons have energy level close to the energy level of the conduction band.

Figure 5 p-type semiconductor

Figure 6 n-type semiconductor

1.3 p-n junctions
A p-n junction is the connection interface between two oppositely doped (n-type and ptype) ends of a semiconductor crystal and such semiconductor is called a p-n junction
diode. When n-type and p-type regions come into contact, the electrons from n -dopedside diffuse to the p-doped side and combine with the holes from the p-doped sidecreating a space charge region or depletion region around the p -n junction. An electricfield is created in the space charge region in n-doped to p-doped direction. Electrons
and holes in the junction move back and forth from p-doped to n-doped side and vice14

versa (diffusion current) and an equilibrium is reached.

Figure 7 Operation of a p-n diode [17]1.3.1 Forward and reverse bias of a p-n diodeIf the n-type side of a p-n diode is connected to the negative terminal of a power supply
and the p-type side is connected to the positive terminal of the power supply, the diodeis said to be forward biased. In such condition, if the external voltage applied is greaterthan the potential difference across the depletion region (0.7V for Si), the electrons
from n-type side are pushed across the depletion region and electric conduction
occurs.
On the other hand, if the power supply is reversed from forward bias, any additional
voltage applied goes into expanding the conduction barrier or depletion region further
and further. Only a tiny current can flow in this bias condition (called leakage curr ent)
because of small number of holes and electrons present in the depletion region of the15

semiconductor material. Since, leakage current is mostly undesirable, Si is preferred tosome other semiconductors like Ge to operate in room temperature since Si has
significantly smaller leakage current compared to Ge (due to larger energy gap between
the valence and conduction bands in Si).

1.3.2 Junction breakdown
If the reverse bias voltage is further increased, at a specific voltage (reverse bias
breakdown voltage), the electrons and holes break through the p -n junction resulting ina large flow of current. There are two different phenomena that cause such nondestructive p-n junction breakdown.

1.3.2.1 Avalanche breakdown
Avalanche breakdown occurs if p-n junction diodes are moderately doped and havewider depletion region. When a reverse bias is applied in such diode, the electric field
across the p-n junction increases and after a certain voltage (avalanche breakdown
voltage), the electrons start getting free off their covalent bonds and drift across thejunction. The drifting electrons carry kinetic energy which collide and knock offelectrons from other atoms generating more free electrons resulting in a rapid increaseof electric current (avalanche mechanism). In avalanche breakdown, since thedisturbance by atoms is smaller at lower temperatures, the avalanche multiplication
becomes large by decreasing the temperature.

1.3.2.2 Zener breakdown
If a p-n junction diode is heavily doped, the electrons can tunnel through the thinjunction. When the reverse bias voltage is increased across the diode, the electric fieldat the junction increases but still not enough so that the avalanche multiplication does
not take place. The recombination of electrons and holes in the region cause a net drift
current which increases rapidly with increase in reverse bias voltage.

16

Figure 8 IV characteristics of a p-n junction diode1.4 PhotodiodeA photodiode is a p-n junction diode operated in reverse bias in which the electric
current flowing through can be varied by using optical signals. As photons pass throughthe photodiode, the depletion region helps separate the photogenerated electron -holepairs causing the flow of electric current. In a photodi ode, higher quantum efficiency
and higher response speed are desired. Quantum efficiency is the fraction of incident
photons contributing to the photocurrent. Higher quantum efficiency requires thedepletion region to be sufficiently wide for larger number of photons to be absorbed(along with other factors like wavelength, absorption coefficient, doping, geometry,etc)
but response time is better with smaller depletion region width, so balance of the twoparameters is important to achieve desired photodiode performance.
The basic structure and working of a pin photodetector is shown in fig 11.
17

Figure 9 Basic structure of a pin photodiodeFigure 10 Basic working principle of a pin photodiode

There are 3 regions in this type of photodiode, short heavily doped n and p regions arein either sides of a wider (wider than the space charge region) intrinsic region. In thiscase the photodiode is operated in the reverse bias voltage not enough to create e lectricfield enough to start avalanche mechanism.
Few terms used in understanding photodiodes:
Quantum efficiency: Quantum efficiency is denoted by symbol R and is defined as thefraction of incident photons having energy enough to free electrons in the P D. Quantum
efficiency depends both on wavelength of incident light as well as composing
semiconductor material.
Responsivity: It is the measure of output current relative to the number of incident
photons. Responsivity is defined as average output current divided by average incident
optical power and its units are A/W.
Gain: Gain is the multiplication factor of the primary photon current. It is the ratio of
output current at an operating voltage to the current at a low voltage where the gain isunity, i.e. no multiplication occurs.
Dark Current: Due to the leakage current in reverse biased photodiode, some small
current flows even when there are no incident photons which is called dark current.
Dark current in orders of less than 10^-10 A is usually considered to have insignificant
effect in photodiode performance [20].

1.4.1 Avalanche photodiode (APD)
Avalanche photodiode (APD) is a photodetector that provide higher sensitivity due tothe internal gain through avalanche multiplication of photogenerated elec trons as shownin fig10. APD is operated in reverse-bias voltage sufficient to create electric fieldrequired for avalanche multiplication (impact ionization) to take place. Generally,
higher the reverse voltage, higher the gain and normal APDs can show current gain inorder of 10 2 but by varying doping concentration and other parameters APDs can bemade to work in voltages over 1500V achieving gains in orders of 10 3 . As thephotocurrent in an APD is amplified by the gain factor due to avalanche effect,
resulting current is much higher than in pin photodiode.
18

Figure 11 Avalanche mechanism in APD [10]APDs can be operated in different voltage ranges as shown in fig 11

19

Figure 12 Various modes of operation of an APD [12]At low voltages (Normal mode in the fig 12), when electric field is not strong enough to startavalanche mechanism, APDs are inoperable.
Once the electric field is strong enough to start avalanche mechanism, electron -hole pairs are
generated and actively collected at the opposite terminals. At voltages below and near the
breakdown voltage, collection dominates, causing the avalanche current to decay andultimately stop. Since the gain is linearly dependent on applied reverse bias voltage in thismode, the gain is finite and largely predictable. This characteristic enables us to statisticallycalculate the number of photons absorbed by the photodetector. This voltage region is known
as linear mode range and the APDs designed for tes t purpose in this thesis are operated in thisrange. Once the breakdown voltage is crossed, increase in electric current is very high in
relation to the applied reverse bias voltage (Geiger mode range). In this mode, electron-hole
pair generation exceeds collection speed which causes accumulation of electrons and holes at then- and p-sides of the depletion region, respectively, creating an internal electric field in opposition to theapplied bias limiting the growth of current. As long as the applied bias voltage is maintained, thephotodetector remains in that state. Here, the gain is virtually infinite and an electrical event resulting
20

from a single photon or multiple photons arriving simultaneously is indistinguishable. Our APDs areinoperable in such voltages.

Figure 13 Impact ionization rate of electrons and holes [12] Figure 14 Excess noise in APD depending on gain [12]The graph above in the left, fig 13, shows the difference in impact ionization rate of electrons(
α𝑒 ) and holes( αℎ ). At low electric field strength (at smaller reverse bias voltages) impact
ionization rate of electrons is significantly greater than that of holes and the difference closes
as electric field strength is increased. In fig 14, Excess noise, F is plotted against thegain/Multiplication factor. The parameter k is the ratio of impact ionization rate of holes toelectrons. Excess noise is plotted for k>0.1 i.e. in electric field strength greater thanapproximately 200V/cm. As can be seen in the graph, noise increases with increase inmultiplication factor and that noise is smaller of smaller value of k, i.e. at smaller reve rse bias
voltage. The curves are parametrized by the following equations.

a e (E) = exp(Ae +Be)E

a h (E) = exp(Ah +

Bh
)
E

𝐤=

𝜶𝒆
𝜶𝒉

(M -1)2
F = M (1- (1- k)
)
M2

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1.5

Semiconductor Detectors

Semiconductor detectors are most commonly in modern high energy physics
experiments. In semiconductor detectors, the fundamental information carriers areelectron-hole pairs, which are produced along the path taken by the charged particle(primary or secondary) through the detector. By the movement of electrons and holes,
the detection signal is induced on the readout electrode. Of the available semiconductormaterials, silicon is mainly used for charged particle detectors and soft X -ray detectors
while germanium is widely used for gamma-ray spectroscopy. As shown in figure 15,
the electron hole pairs created in the Si-bulk due to incident radiation, drift towards the
opposite poles producing a signal of detection. The energy needed to produce anelectron-hole pairs is independent of energy of radiation, type of radiation andtemperature. The average needed is same as ionization energy which is about 3.62eVfor Si and 2.96eV for Ge.

Figure 15 Working of a basic silicon detector

221.5.1 Large Hadron Collider (LHC)The Large Hadron Collider (LHC) is the world's largest and most powerful particle
collider in the world. Its aim is to test the predictions of different theories of particle
physics like the Standard Model, and particularly prove or disprove the existence of thetheorized Higgs boson (which was detected in 2013) and of the large family of newparticles predicted by supersymmetric theories. It contains four major detectors ALICE,ATLAS, CMS, LHCb and smaller detectors each designed for certain kinds of research.

Figure 16 Components of Large Hadron Collider [19]ATLAS is one of the two versatile detectors designed to study Higgs phenomenon,
making use of semiconductor detectors to make measurements of collision of proton
beams at high energies.
Silicon-Conductor Tracker (SCT) is a silicon micro strip detector at the heart of the
ATLAS experiment at the CERN Large Hadron Collider. Together with the rest of the
ATLAS Inner Detector it provides vital precision tracking information of charged
particles. This detector is constructed from silicon wafers 6cm in diameter. Particles aredetected by strips 0.080mm apart running along the beam pipe (z-axis). Alternate layers
have strips running at 40mrad with respect to z axis, allowing to reconstruct the hit
positions three dimensionally. The path of the particle is measu red with a point
precision of ~0.02mm perpendicular to the strips.

23

Figure 17 ATLAS inner detector showing SCT, Pixel detector and TRT [18]In order to perform higher precision particle detection, ATLAS has pixel detectors
places in the inner side of SCT. This detector has high space-point resolution (≈12µm inr φ, ≈90µm in z) and greater radiation hardness (50MRad or 10 15 /cm 2 neutronequivalent). The sensor part of it has an active area of 2×6 cm2 and 250μm thickness. It
has 41984 normal pixels (50µm ×400µm) and 5284 long pixels (50µm ×600µm) .

1.5.2 ILC (International Linear Collider)
The International Linear Collider (ILC) is a proposed linear particle accelerator. It isplanned to have a collision energy of 500 GeV initially, with the possibility for a later
upgrade to 1000 GeV. Two detectors ILD (International Large Detector) and SiD(Silicon Detector) are being developed for the project. The radiation dose at the vertex
detector inside ILD is supposed to be about 1kGy/year.

24Figure 18 Schematic layout of the International Linear Collider (ILC) [21]Chapter 2

SOI Pixel Detectors

2.1 Introduction to SOI pixel detectors
SOI(Silicon-On-Insulator) is a semiconductor manufacturing technol ogy in whichtransistors are formed in thin layers of silicon that are isolated from the main body of
the wafer by a layer of electrical insulator, usually silicon dioxide. By bonding two
silicon layers in which the lower Si layer of high resistivity acts as detector of charged
particles and upper SOI layer is for readout circuit, integrated SOI pixel detector withreadout circuit is realised which is shown in figure 19. The sensor layer can vary inthickness from 50~500μm and the Buried Oxide (BOX) layer which lies between theupper electronic layer and sensor layer is about 200nm thick. Pixels are formed byappropriately implanting heavily doped ions below the BOX layer. As a reverse bias
voltage is applied to create a depletion zone, the electron-hole pairs liberated by the
charged particles passing through the depletion zone in the sensor are collected in thesensor electrodes which are then passed through the metal vias to the circuit which istreated as detected signals at that point and can be passed on to the electronic circuitry
for amplification and processing.

25

Figure 19 General SOI structure

2.2 SOI Manufacturing process26

Development of SOI monolithic pixel detectors was started as a project at KEK Detector
Technology Project (KEK DTP) since 2005. Currently, Silicon On Insulator PIXel detectors(SOIPIX) projects are being carried out since 2005, led by KEK and supported by Japan Society
for Promotion of Science (JSPS). [12]Table 1 SOI process details [22]Process

0.2mm Low-Leakage Fully-Depleted (FD) SOI CMOS

(Lapis Semiconductor Co.
Ltd.)

1 Poly, 5 Metal layers (MIM Capacitor and DMOS option)
 Total thickness above top Si (SOI layer) ~ 9 mm
Core (I/O) voltage : 1.8 (3.3) V

SOI wafer

Diameter: 200 mm, 720 m thick(200 mm φ=8 inch)

Top Si : Cz, ~18 -cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickSensors

CZn ~ 700 -cm, thickness~300μm (Default)
FZn~ > 3 k -cm, thickness~500μm (2009-)
FZp ~ 25 k-cm, thickness~500μm (2010-)
Double SOI (CZn) (2012-) and (CZp) (2015-)

Backside process

Mechanical Grind Chemical Etching Back side Implant Laser
Annealing  Al plating

Silicon-on-insulator (SOI) technology is based on 0.2μm low-leakage fully-depleted SOI CMOS
technology. High-resistivity substrate as sensing part and a thin low-resistivity Si layer for
CMOS circuits are integrated into a single unit in a SOI wafer. KEK organizes MPW (Multi
Project Wafer) runs twice a year in which the mask is shared among SOI projects in different
Universities and institutions to reduce the cost of design and production. [13]27Figure 20 SOITEC SOI process [14]2.3 SOI-CMOS
In traditional Bulk-CMOS, transistors are separated by making p-n junction inside thewafer structure. On the other hand, in SOI-CMOS each transistor is separated
completely by the buried oxide (BOX) layer as shown in figure 22. The separation by
insulating layer prevents electrical contact between the transistors which gives thefollowing advantages over the bulk type.
a) Very low leakage current due to the insulating BOX layer , which contributes to thelower power consumption, ability to operate in low voltages.
b) Transistors are better isolated having small capacitive couplings to neighbours, which
contributes to better speed at lower noise.
c) Better latch-up tolerance due to absence of parasitic device inside transistor.

28

Bulk CMOS

SOI-CMOS

Figure 21 Bulk CMOS vs SOI-CMOS

2.3.1

Monolithic-type SOI detector

In traditional hybrid silicon pixel detectors, the sensor part and the readout circuit partare connected by metallic bump bonding. But in SOI monolithic detectors the two parts
are constructed together into one integrated detector connecting using metal vias.

Figure 22 (a) Hybrid type silicon detector (b) Monolithic type SOI detector

The monolithic type SOI detector has following advantages over the traditio nal hybrid
type silicon detector.
a) Since no mechanical bonding is required due to it being monolithic, it helps minimize
multiple scattering, smaller pixel size is achievable and amount of materials and cost
can be reduced. [11]29b) Due to the decrease of parasitic capacitance, high speed and low power consumption,high S / N ratio of reading can be achieved.
c) Leakage path from CMOS circuitry to signal detection part is absent, which allows
greater temperature range of operation. [15]d) Problems of latch-up effect and Single Event Effect (SEE) are eradicated due to theisolation of CMOS circuitry from the sensor layer by SiO 2 layer (BOX layer).
e) 3-D integration possibility using μ -bump technology is another advantage of SOI
technology being monolithic type and high miniaturization. [16]2.4Problems with SOI detectors

Due to the many advantages of SOI detectors over traditional silicon detectors, it isbeing considered as the pixel detector of future. But, there have been a few problems
that needed to be addressed with the original SOI detectors.

2.4.1

Back-gate effectSince the readout circuit part and the sensor part are integrated together in SOI pixel
detectors, the reverse bias (back-bias voltage) applied in the sensor affects the transistor
operation parameters including its threshold voltage. This effect is called back -gate
effect.
In order to remove this effect, BPW (Buried P -Well) structure was introduced in SOI
process. The BPW which controls the electric potential is formed by adding p -type
impurities to the n-bulk sensor part immediately below the BOX layer. The BPW isoften connected to the pixel nodes, which usually enhances the charge collection. This,
however increases the detector capacitances and reduces the signal height. The designof the BPW is thus carefully carried out.

2.4.2

CrosstalkBecause of miniaturization of the detectors, the sensor part and readout circuit part are
separated only by thin layer of buried oxide (BOX) (~200nm) and they can interfere
electrically. This phenomenon is known as crosstalk. Crosstalk can originate between
the adjacent pixels as well. This effect leads to errors in precision position
measurements because of which circuits free of crosstalk need to be designed.

30

Figure 23 Crosstalk mechanism

2.4.3

Figure 24 Backgate effectRadiation tolerance

Detectors in high energy experiments are exposed to very high doses of radiation
because of which they made to be tolerant to those conditions. The Pixel detector whichlies at the centre of ATLAS detector in LHC is exposed to 158kGy/yr of radiation at
distance of 4.3 cm from the beam. This value is expected to go up 10 times for theplanned HL-LHC (High Luminosity LHC). Similarly, in ILC (international Linear
Collider), silicon detectors will be exposed to 1.5kGy of radiation in 3 years. Therefore,
SOI detectors need to meet the required radiation tolerance if they are to be used inhigh-energy experiments.
Effects of ionising radiation on SOI detectors can be classified in the following two
types.

2.4.3.1

SEE (Single Event Effect)

When radiation like heavy charged particles pass through the SOI detectors, manyelectron-hole pairs are produced because of which breakdown and latch -up
phenomenon may be observed. This effect is called SEE effect. In case of SOI-CMOS,
since the sensor part is separated by the buried oxide layer, and since the thickness ofactive silicon layer is also about 40nm, chance of breakdown occurrence is less.
Similarly, as transistors are also separated completely, occurrence of latch -up is also
prevented. Hence, SOI pixel detectors are highly tolerant to single event effect .

2.4.3.2

TID (Total Ionizing Dose) effect

When the detector is irradiated, electron-hole pairs are produced not only in the Silayer but also in the BOX (buried oxide) and gate oxide layer. The drift velocity ofholes is much slow than that of electrons in these layers because of which holes gettrapped and a positive charge is developed and affects the transistor parameters. Thiseffect is called TID effect. Different to that in Bulk CMOS, transistors lie close to the31buried oxide later in SOI CMOS due to which its effect in SOI pixel detectors is to becarefully studied.

Figure 25 TID effect in SOI-CMOS

2.5 Double SOI
Double-SOI pixel detector technology was introduced to solve the problems found with normal
single SOI pixel detectors. Double-SOI structure consists of two layers of buried oxide with thin
middle Si layer in between (shown in fig 26) of which electric potential can be varied as required
to recover transistor properties. Introduction of middle Si layer also has other advantages likeacting as an insulating layer between sensor and circuit layer, which helps in reduction of crosstalk, back-gate effect, etc.

32

Figure 26 Structure of double-SOI pixel detector

Double SOI process involves performing the normal single SOI manufacturing process twice asshown in fig 27.

Figure 27 Double-SOI process (SOITEC)

33

Figure 28 Cross-section view of Double SOI structure using SEM (Courtesy of Lapis Semiconductor)

Fig 28 shows the cross-sectional image of first successfully manufactured Double-SOI structure
taken using SEM (Scanning Electron Microscope). The wafers use for evaluation in this thesis
were manufactured by SOITEC.

34

Chapter 3

SOI-APD

SOI APDs are designed to take advantage of both the internal gain available from avalanche
mechanism and the benefits from using SOI process technology mentioned in the previous
chapter. By integrating SOIPixel sensor part with avalanche photodiode structure, SOIAPD withinternal gain and high sensitivity can be achieved which is not possible with bulk CMOS
technology [23].
Advantages of SOIAPD over normal APD and PPD (Pixelated Photon Detector) can besummarized is the table below.
APD
Avalanche Gain

PPD

SOIAPD

10~100105~106

10~100Conversion circuit gain

-

-

5-10

Random Noise Rate

Low

High

Low

Size / pixel~ mm sq.

~ mm sq.

~10 umsq.

No. of Pixel

１pixelUsually 1 pixel~million pixels

Incidence side

Front side

Front side

Front and back side

On-chip signal
processingNoNopossible

Energy measurement

No

No

Possible is X-ray
regionTable 2 Advantages of SOIAPD over APD and PPD

Basic design and structure of our test SOIAPD chip
In SOIAPD, the high resistivity Si sensor part in SOI structure is replaced with APD structure asshown in fig 29.

35

Figure 29 SOI structure

Our test chip was APDTEGh (model: MX1850-IK15) manufactured in 2015 KEK MPW run.
Based on the requirement of MPW run mask at the time, Double Photodiode structure ofInterrupted finger type (fig 30) with N+/PWell/Nsubstrate or P+/Nwell/Psubstrate was
implemented. SOI Avalanche Double Photodiode and SOI reach-through APD are other typed of
SOIAPD designs currently not implemented.

Figure 30 SOI Interrupted-N-Finger APD

36

Figure 31 SOI Avalanche Double PhotodiodeFigure 32 SOI Reach-through APD

8 types of SOIAPD structures with varying well size and polarity of electrodes were designed
and fabricated in CZn, FZn, FZp and DSOI wafers. SOIAPD with structure shown in fig 33(apd4_retype2_4pixel) was one tested more extensively for this thesis.

37

Figure 33 a. Top view of a single pixel of SOIAPD b. cross-sectional view of the same

The structure Fig 33 shows the pixel structure of our test SOIAPD. P-well and n+, p+ electrodes
are implanted on top of n- substrate in the pixel. The substrate is set as floating, p+ as ground andthe potential at n+ electrode is varied in the reverse bias voltages. Each of these structures is readout as a single pixel. Our test chips contain such single pixels as well as integrated super pixels
38

of 10*10 array of single pixels. Each pixel is 26μm *26μm size and array size is 260μm *260μm.
The size of APDTEGh chip is 2.9mm*2.9mm and it contains many single pixels and arrayed
pixels.

Figure 34 SOIAPD test chip APDTEGh

3.1

SOIAPD TCAD simulation

TCAD simulations were performed for prediction of our SOIAPD test chip characteristics.
TCAD (Technology Computer-Aided Design) refers to the use of computer simulations todevelop and optimize semiconductor processing technology and devices. It can be used tounderstand process of the device and the device physics. Various parameters that are otherwise
very difficult or impossible to measure with fabricated device can be virtually measured using
TCAD tools. By performing TCAD simulations, problems and potential issues under various
conditions can be determined so that they can be fixed before fabrication which saves time andmoney. TCAD simulation software was first developed at Stanford University in 1977 and now
different tools are available among which ENEXSS is the tool used in our simulations since it
supports the manufacturing process used to fabricate SOI detectors. There are three tools that canbe used in ENEXSS TCAD simulator:

3.1.1. Process simulator (Hyper Synthesised Process Simulator (HySyProS))
The process involved in fabrication like deposition, etching, implantation,etc of SOI detector are
virtualized in the simulator using Simulation Control language(SCL). Impurities doping profile ispredicted by solving diffusion equation in 3D environment using different models in HySyProS.
39

The impurities available for doping in ENEXSS are Boron(B) and Indium(In) from group III and
Phosphorus(P) and Arsenic(As) from group V. Impurities are homogeneously doped by default
but can also be manually varied using Gaussian or linear distributions. The generated 3D
impurity profile is then used in device simulator.

3.1.2. Device simulator (HyDeLEOS)
Several electrical, mechanical, thermal and optical properties of the semiconductor device can bemodelled using device simulator. HyDeLEOS is a device simulator tool available in ENEXSS
which can be used to solve drift diffusion equation, quantum mechanical calculations and opticalmodes computations. HyDeLEOS is used for single device (threshold voltage, saturation andleakage current, capacitance, etc.), circuit design (wire resistance and capacitance, propagation
delay), and the defect analysis (Electro Static Discharge (EDS) and latch-up). The behavior ofthe device is predicted by providing the geometry, characteristics, and internal operation
conditions of the device to HyDeLEOS. It consists of three sections. First, in the preprocessing
section (deleos_shell), the device structure, dopant distribution, electrode name and position, andmesh methods are deﬁned and the generated file is then used in the calculation section "deleos".
In calculation section (deleos) the basic equations of a semiconductor like drift diffusion
equation, Poisson’s equation, continuity equation, heat and electrical conduction equation, etc
are solved using the device structure (deﬁned in deleos_shell), boundary conditions, andelectrical characteristics such as terminal current (deﬁned in deleos). Finally, the post-processing
section (deleos_extrac) parameters of the device like threshold voltage, drain current, scaling
factor, etc are extracted and used for optimization function and prepared for extraction ofcharacteristic values from electrodes.
Basic equations used in device simulation:
Poisson Equation∇ (ε∇ψ) = −q(HD − NA − n + p)
ψ: static potential, n: electron density, p: hole density
ε: dielectric constant, q: elementary charge
ND: donor impurity concentration, NA: acceptor impurity concentration
Equation of continuity of electron current
𝛿𝑛 1= ∇𝐽 + 𝐺 − 𝑅
𝛿𝑡 𝑞 𝑛𝐽𝑛 = −𝑞𝑛𝜇𝑛 ∇ψ + qD𝑛 ∇n(drift diffusion approximation)

t: time, Jn: electron current, G: generation term, R: recombination term
μn: electron mobility, Dn: electron diffusion constant40

Equation of continuity of hole current
𝛿𝑝 1= ∇𝐽 + 𝐺 − 𝑅
𝛿𝑡 𝑞 𝑝
𝐽𝑝 = −𝑞𝑝𝜇𝑝 ∇ψ + qD𝑝 ∇pt: time, Jp: hole current, G: generation term, R: recombination term
μp: hole mobility, Dp: hole diffusion constant

3.1.3. Plotting tool (SGraph)
The results from above steps can be plotted using SGraph in 1D,2D or 3D as required. Usefulfeatures like bird’s eye view of physical values, multiple graph, cross sectional view and 3Dview of device structure, dopant distribution, potential distribution, etc are available with
SGraph.

TCAD simulation and results
Electron density and electric field distribution of apd4_retype2_4pixel_1 pixel was predictedusing the TCAD simulation tools explained above.

Figure 36 apd_retype2_4pixel structure

Figure 35 TCAD mesh creation for pixel on therightFirst virtual substrate of thickness 100μm and width 200μm is created as shown in fig 35. Photoresistors of width 5μm and SiO2 layer of width 248nm are deposited and etching is done. P wellis then implanted and photo-resistors are removed. p+(PS) and n+(NS) are implanted in that area
in concentrations as shown in fig37. After that, annealing is performed at 1050℃ for 10
seconds.
41

Figure 37 Impurity concentration (depth=-0.2μm)

Figure 38 . Impurity concentration (Center.NS,PS)As reverse bias is applied between p+(PS) and n+(NS) in the created TCAD model, following
results were seen. In the first row of fig 40 below, reverse bias was varied from 0V to -20V andexpansion of depletion region was plotted in 2D figure. In the second row, change in electron
density in depth-wise direction from the center of the detector is visualized. As can be seen in
figure 40, at higher reverse bias voltage, depletion region expands sweeping away the electrons
decreasing the electron density.

42Figure 39 Electron density profile at different voltages

Electron density (/cm^3)

Figure 40 Electron density at different depths of the pixel

1019
1018
1017
1016
1015
1014
1013
1012
1011
1010
109
108
107
106
105
-100

Electron density vs detector thickness
Center position@Vop=0V
Center position@Vop=-5V
Center position@Vop=-10V
Center position@Vop=-15V
Center position@Vop=-20V

-90

-80

-70

-60

-50

-40

-30

-20

-10
0
Depth (um)Figure 41 Electron density at different depths from the top (at different reverse voltages)

43Simulation results of electric field (fig 42) in the whole of pixel is shown in the plots below. The
second-row plots show magnified view of upper part of pixel with n+ (NS) and p+(PS).
Avalanche mechanism occurs in this region where electric field strength is high.

Figure 42 Electric field intensity at different regions of SOIAPD pixel

Fig 35 shows plotted values of electric field of the region above and different operation voltages.
Large electric field (~10^6 V/cm) appears to be concentrating around the edges of n+. The flat
region shows electric field of about 10^4 V/cm. Avalanche breakdown takes place in linear
mode at electric field strengths of about 300kV/cm ~ 800kV/cm. SOIAPD is operated at k factor< 0.2 range since Geiger mode multiplication starts above that which is not desired for SOIAPD.

Fig 34.
44

Electric field (V/cm)

106
Electric field dependece

10@Vop=0V

5@Vop=-5V@Vop=-10V@Vop=-15V

104@Vop=-20V

103
102

10

1

0

20

40

60

80

100 120 140 160 180 200
Position of x-direction-detector (um)Electric field (V/cm)

Figure 43 Electric field intensity variation across different regions of SOIAPD (at y=-0.2μm)
106
105
104
103
Electric field dependece

102@Vop=0V@Vop=-5V@Vop=-10V@Vop=-15V

10

1@Vop=-20V

85

90

95

100
105
110
115
Position of x-direction-detector (um)Figure 44 magnified view of the previous figure to show the region near n+, p well

45

Chapter 4
4.1

SOIAPD Measurements

IV and CV Measurement

IV and CV measurements were made using bare APDTEGh (our SOIAPD) chips fabricated in
CZn, FZn, FZp and DSOI wafers. FZ (Float-zone silicon) and CZ (Czochralski silicon) are two
growth techniques for mono-crystalline silicon. Majority of the commercially grown silicon is
Czochralski silicon due to the better resistance of the wafers to thermal stress, the speed ofproduction, the low cost and the high oxygen concentration that offers the possibility of Internal
Gettering. Float-zone silicon is a high-purity alternative to crystals grown by the Czochralski
process. The concentrations of light impurities, such as carbon and oxygen, are extremely low.
Another light impurity, nitrogen, helps to control microdefects and brings about an improvement
in mechanical strength of the wafers, and is now being intentionally added during the growthstages [26]. Double SOI wafers are based on CZn and since 2014 production of double SOI
wafers based on CZp have also started.
Table 3 Basic data of different wafer types
Wafer type

CZN

FZN

FZP

resistivity

700Ω・cm

2kΩ・cm 25kΩ・cm 1kΩ・cm

Wafer
thickness

510 um510 um

510um

DSOI

310um

CZn

FZn

FZp

DSOI

Figure 45 Test SOIAPD chips

46

Measuring device used was Keithley 4200-Semiconductor Characterization System. This device
can provide voltage range of up to 210V with minimum resolution of 1μV. And withmeasurable current resolution is up to 100aA (10-18A), it is a very sensitive machine. Probers
pins are used to make connection with the terminal contacts as shown in fig 46 and 47.

Figure 46 Kiethley 4200-SCS Semiconductor Characterization System

Figure 47 Test chip during measurement using Kiethley-4200-SCS

In each of the measurements of dark current fig 48 , low leakage current (~1-14 A for single
pixels and ~1-12A for 10*10 array pixel) was seen and breakdown voltage was about 18V for all.

47

Figure 48 Dark current from 10*10-pixel array and single pixel

Figure 49 shows the ratio of dark current between array and single pixel. Leakage current of
10*10 array pixels is found to be about 10^2 times that of single pixels as expected which
confirms the operation of SOIAPD in linear multiplication mode.

48

Figure 49 Ratio of dark current from 10*10-pixel array to that from a single pixel

5

Capacitance(F)Capacitance(F)CV measurments show that the SOIAPD has very low capacitance of about 3pF which is good
for APD.
· 10-12CV curve with apd4_retype2_4pixel

4.5

HR1_wafer

45· 10-124.5

CV curve with apd4_retype2_4pixel
NFZ_wafer

4
3.5

3.5

3
3

2.5

2.5

2

2

1.5

1.5
1
0

2

4

6

8

10

12

14

16

18

20

Reverse voltage(|V|)

1
0

2

4

6

8

10

12

14

16

18

20

Reverse voltage(|V|)

49

4.5

5 · 10-12

Capacitance(F)Capacitance(F)5 · 10CV curve with apd4_retype2_4pixel

4

FZP_wafer

3.5

4.5

3
2.5

2

2

1.5

1.5
4

6

8

10

12

14

16

18

DSOI_wafer

3.5

3

2

CV curve with apd4_retype2_4pixel

4

2.5

1
0

-12

1
0

20

2

4

6

8

10

12

Reverse voltage(|V|)

14

16

18

20

Reverse voltage(|V|)

Figure 50 Capacitance versus reverse bias voltage for different wafer type samples· 1021

450

-2

500

1/C (F )2

1/C V curve with apd4_retype2_4pixel

2

2

-2

1/C (F )1/C^2 versus Reverse voltage plots are shown in figure 51. Doping profile of the SOIAPD can becalculated using these plots.

400

HR1_wafer

500 · 1021

450

1/C2V curve with apd4_retype2_4pixel

400

FZN_wafer

350
350

300

300

250

250

200

200

150

150

100

100

50

50

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

1/C2V curve with apd4_retype2_4pixel

400

2

450

21

-2

500 · 10

FZP_wafer

500

300

300

250

250

200

200

150

150

100

100

50

50
4

6

8

10

12

14

16

18

20

Reverse voltage(|V|)

20

1/C2V curve with apd4_retype2_4pixel

400

350

2

18

· 1021

450

350

0

16

Reverse voltage(|V|)

1/C (F )1/C2(F-2)

Reverse voltage(|V|)

140

DSOI_wafer

2

4

6

8

10

12

14

16

18

20

Reverse voltage(|V|)

Figure 51 1/C2 versus reverse bias voltage

50

4.2

Temperature dependence of SOIAPD

Figure 53 Sub-board for testing

Figure 52 Temperature chamber

Temperature dependence was measured by setting up the wire bonded APDTEGh chip in acustom manufactured board and varying temperature using temperature chamber (figure 53).
Measurements were made by cooling down the chip to 200C, 00C, -200C, -400C and -600C
temperatures.

51

Figure 54 Dark current vs reverse voltage curves at varying temperatures (CZN wafer), original graph on theright, same graph magnified in near breakdown voltage region on the right

Figure 55 Dark current vs reverse voltage curves at varying temperatures (FZN wafer), original graph on theright, same graph magnified in near breakdown voltage region on the right

Figure 56 Dark current vs reverse voltage curves at varying temperatures (FZP wafer), original graph on theright, same graph magnified in near breakdown voltage region on the right52

Figure 57 Dark current vs reverse voltage curves at varying temperatures (DSOI wafer), original graph on
the right, same graph magnified in near breakdown voltage region on the rightTemperature (0C)
CZN
FZN
FZP
DSOI
20
17.1V
17V
16.2V
16.4V
0
17.3V
17.2V
16.4V
16.6V
-20
17.5V
17.4V
16.7V
16.9V
-40
17.7V
17.6V
16.9V
17.5V
-60
17.9V
17.9V
17V
18.2V
5
Table 4 Breakdown voltages (here taken as voltage where current exceeds 10 A) at different temperatures

Due to the increase in vibration of crystal lattice with increase in temperature, accelerated
carriers collide with the lattice before reaching sufficient energy level to trigger impact
ionization. Therefore, greater reverse bias voltage is required (increasing reverse bias voltage
results in more carriers having sufficient initial energy to trigger avalanche mechanism) totrigger avalanche mechanism at higher temperature (as the availability of carriers with sufficientenergy reduces with increase in temperature) as seen in the figures 54 to 57, where breakdown
voltage increases with increase in temperature. Again, greater dark current seen in themeasurements at higher temperature is because of availability of more heat generated electrons
and holes which can be explained as follows.

In a one sided abrupt P+/N junction, reverse bias saturation current can be expresses as follows
as the sum of diffusion current in the neutral region and current generated in the depletion
region.
𝐷𝑝 𝑛𝑖2 𝑞𝑊𝑛𝑖
𝐼𝑅 ≅ 𝑞√
+
𝜏𝑝 𝑁𝐷
𝜏𝑔

(1)

53

𝐷𝑝 : Hole diffusion current, 𝜏𝑝 ：Hole lifetime,𝜏𝑔 ：generation time,

𝑁𝐷 ：donor density（N side） 𝑛𝑖 ：Intrinsic carrier density,𝑊：depletion region width,𝑘：Boltzmann constant,

𝑇：Temperature,

𝑞：unit electric charge

It can be expressed as follows using bandgap of intrinsic carrier density Eg (1.12 eV in case ofSi), state density of valence and conduction bands Nc, Nv.
𝑛𝑖 = √𝑁𝑐 𝑁𝑉 exp (−𝐸𝑔
𝐸𝑔) ∝ exp (−
) (2)
2𝑘𝑇
2𝑘𝑇

Using the equation for avalanche mechanism and mobility of holes μh , diffusion coefficient
can be expressed as follows.
𝐷𝑝 =

𝜇ℎ 𝑘𝑇
𝑞

(3)

Using equations (1) and (3), in case when diffusion current is dominant, considering the effect of
only the term 𝑛𝑖2 ,𝑞𝜇ℎ 𝑘𝑇 𝑛𝑖2
1
𝐼𝑅 ≅ √∝ exp (−𝐸𝑔 )
𝜏𝑝 𝑁𝐷
𝑘𝑇

(4)

From equation (4) it is seen that current flow increases with increase in temperature, which was
also seen from the results of temperature dependence of dark current of SOIAPD.

54

4.3

LED response of SOIAPD

LED output from standard fiber coupled LED (model M530F-1, light wavelength: 53nm) wasused along with LED driver (model: DC2200). LED output could be varied by changing thecurrent from 0.1mA to 1000mA. Before measuring the LED response of SOIAPD, standard
photodetectors were used as reference. HPK S1787-12 was one of those and it had lightsensitivity of 0.27A/W at 530nm wavelength. It was operated at 9V (max operation voltage:
10V).

Figure 58 LED device (M530F-1)
Table 5 LED device specifications

55

Figure 59 Forward current vs forward voltage of LED device [Hamamatsu Photonics HPK]

Figure 60 wavelength distribution of output LED light [HPK]A photodetector (model: S1787-12) was use as reference to calculate the power output from theLED.

Figure 61 Specifications of reference photodetector [HPK]56

Figure 62 Dark current of reference photodetector as given by production specification [HPK]Figure 63 light sensitivity of reference photodetector versus wavelength of flight [HPK]57

Figure 64 Setup for LED response measurement

1· 10
0.9 HPK S1787-04 reference PD
0.8
0.7
0.6
0.5
· 2 / ndf
2.231e-16 / 130.4
p02.208e-09 · 1.57e-09
p1
2.451e-09 · 3.098e-11
0.3
0.2
ref_PD# Fiber coupled LED response
0.1

Current [A]dumy

-6

0

100

200

300

400

500

600

Current#LED driver(mA)dummy
Figure 65 LED response of reference photodetector

4 · 10

Energy [W]dumy-6· 2 / ndf

3.5

3.055e-15 / 12

p0

9.529e-09 · 6.536e-09

p1

9.062e-09 · 1.246e-10

3
2.5
2
1.5
1

HPK S1787-04 reference PD

0.5
0
0

ref_PD# Fiber coupled LED response

100

200

300

400

500

600

Current#LED driver(mA)dummy

Figure 66 LED response of reference photodetector in terms of power58

In figure 65, current from photodetector is plotted against output power of LED in mA. In the
figure 66, current from photodetector is changed to energy absorbed by the photodetector per
second. It was found that for incident LED power below 100mA, detected number of photons
increased linearly, but above 100mA sensitivity of the photodetector seems to decrease.
Next, LED response of SOIAPD was measured. For better sensitivity, due to more pixels andminimizing error during LED irradiation, 10*10 array (26μm* 26μm size) was used. LED output
power of ranging from 50mA to 500mA with wavelength 530nm was used. Keithley 2612A wasused for this IV measurement.
From fig 67, increase in current can be seen with increase in input LED power. The fig 68,. isadjusted to show the current from SOIAPD per unit input LED power and all the curves appear
to coincide with each other (except at breakdown voltage) confirming the photodetective
characteristic of the SOIAPD.

Current [|A|]dumy

10-5
SOI-Interrupted-N-Finger APD
IV curves @19.5deg,33%

10-6
10-7
10-8
10-9

dark_current
0.89uW@100mA
2.18uW@300mA
3.22uW@500mA

10-10
10-11
0

2

4

6

8

0.49uW@50mA
1.58uW@200mA
2.72uW@400mA

10 12 14 16 18 20

Reverse voltage [|V|]dummy

Current [|A|/W]dmy

Figure 67 LED response at different incident led powers versus breakdown voltage
103
SOI-Interrupted-N-Finger APD
IV curves @19.5deg,33%

2

10

0.49uW@50mA
1.58uW@200mA
2.72uW@400mA

10

0.89uW@100mA
2.18uW@300mA
3.22uW@500mA

1
10-1
10-2

0

2

4

6

8

10 12 14 16 18 20

Reverse voltage [|V|]dummy
Figure 68 LED response per watt of incident led power, measured at different led intensities

59

Gaindummmy

In the fig 69, gain is plotted against reverse bias voltage. From this graph, it can be inferred thatit can produce internal gain of up to 100 times as well as it is also confirmed that gain per reverse
voltage increase is constant. From fig 70 it is seen that the multiplication factor or gain is low
below 17V and above 17V to breakdown voltage, gain increase is very high. This characteristic
is due to the difference in k factor as explained in previous chapters.

102
SOI-Interrupted-N-Finger APD
IV curves @19.5deg,33%

10

1
0.49uW@50mA
1.58uW@200mA
2.72uW@400mA

10-1
0

2

4

6

8

0.89uW@100mA
2.18uW@300mA
3.22uW@500mA

10 12 14 16 18 20

Reverse voltage [|V|]dummy

dG/dVdummmy

Figure 69 Change in gain with reverse bias voltage
102
SOI-Interrupted-N-Finger APD
IV curves @19.5deg,33%
0.49uW@50mA
1.58uW@200mA
2.72uW@400mA

10

0.89uW@100mA
2.18uW@300mA
3.22uW@500mA

1

10-1
0

2

4

6

8

10 12 14 16 18 20

Reverse voltage [|V|]dummy

Figure 70 rate of change of gain at different bias voltages

60

Gaindummmy

10
9 SOI-Interrupted-N-Finger APD
IV curves @19.5deg,33%
0.49uW@50mA
0.89uW@100mA8
1.58uW@200mA
2.18uW@300mA
7
2.72uW@400mA
3.22uW@500mA
6
5
4
3
2
1
0

2

4

6

8

10 12 14 16 18 20

Reverse voltage [|V|]dummy

Gaindummmy

Figure 71 change in gain with reverse voltage: alternative measurement
600
500

SOI-Interrupted-N-Finger APD
IV curves @19.5deg,33%

400

0.49uW@50mA
1.58uW@200mA
2.72uW@400mA

0.89uW@100mA
2.18uW@300mA
3.22uW@500mA

300
200
100
17.2

17.4

17.6

17.8

18

18.2

Reverse voltage [|V|]dummy

Figure 72 change in gain with reverse voltage: alternative measurement

Operation of SOIAPD in as a detector with internal gain was successfully demonstrated. By
identifying suitable voltage range for operation in linear multiplication mode SOIAPD could be
used in future high performance detectors. As seen in figure 72, gain of more than 200~600
times is also possible without quenching resistor.

61

4.4

Co-60 γ irradiation

We performed ɤ-ray irradiation at food irradiation building, Takasaki Advanced Radiation ResearchInstitute, Japan Atomic Energy Agency from 2017/01/06 to 2017/01/08. SOIAPD chips each of CZn,
FZn , FZp and DSOI wafer were subjected to radiation. Each sample was irradiated up to 200kGy except
1MGy for DSOI based chip.

Figure 73 γ ray irradiation setup at Takasaki irradiation facility

The samples were positioned for irradiation based on the provided radiation dose distribution curve
below.

62

Figure 74 Radiation dose rate to distance curve

Figure 75 radiation dose distribution table63

IV measurements for dark current and led response were made to investigate any changes before andafter irradiation.

Figure 76 Change in dark current (left) and gain (right) before and after 200kGy irradiation in CZn based
APTTEGh pixel

Figure 77 Change in dark current (left) and gain (right) before and after 200kGy irradiation in FZn based
APTTEGh pixel

64

Figure 78 Change in dark current (left) and gain (right) before and after 200kGy irradiation in FZp based
APTTEGh pixel

Figure 79 Change in dark current (left) and gain (right) before and after 1MGy irradiation in DSOI based
APTTEGh pixel

Figures 76 to 79 show the graphs of change in dark current and gain measured before and after γ ray
irradiation. It is clearly seen that dark current is increased across each sample which can be attributed tothe increase in surface charge due to trapped holes. Breakdown voltage increased in samples of CZnand FZn wafers while decreased in case of FZp and DSOI wafers. Gain was observed in the SOIAPD
samples even after irradiation but was decreased in value.

65

Chapter 5

Summary and Conclusion

Currently, novel photodetectors with high precision and sensitivity are being sought. A new type of
Avalanche Photodiode (APD) designed and fabricated using SOI technology at KEK, Japan. This
SOIAPD is expected to have high gain, response time and good S/N ratio as well as all other advantagesof using SOI like small size, low energy consumption, greater radiation tolerance, etc.
SOIAPD test chip APDTEGh was used for evaluation. Of the four types of wafers (CZn, FZn, FZp,
DSO) used to fabricate APDTEGh, all of them showed response as APDs. The dark current was measured
to be very low (in order of 10^-14A) for single pixels of SOIAPD and 10^2 times as much for 10*10pixel array. Similarly, in C-V curve measurements, capacitance of SOIAPD in APDTEGh was found tobe as low as 3pF which is ideal for APD. In temperature dependence measurements, increase in darkcurrent and breakdown voltages were observed with increase in temperature as expected. Thisphenomenon of increased dark current is supposed to appear due to higher production of electron holepairs because of increased heat energy and shift in breakdown voltage I supposed to be due to collision ofcarriers before initiating avalanche mechanism with vibrating lattice suppressing impact ionization.
Radiation hardness test of SOIAPD test samples showed that while dark current was observed to rise andbreakdown voltages were shifted, internal gain was still available (although in reduced value and greater
incosistancy) after γ-ray irradiation upto 1MGy.
Internal gain (multiplication factor from avalanche mechanism) as high as 100 times wasachieved with the APDTEGh test chip. By identifying suitable voltage range for operation in linear
multiplication mode SOIAPD could be used in future high performance detectors. Although the current
SOIAPD was tested for its electrical characteristics by direct contact from parts in the sensor layer, thenext step would be to integrate CMOS circuits like amplifier and shaper above the BOX layer to enhance
the signals from sensor. Similary, introduction of Double-SOI with adjustable middle Si voltage could be
used to enhance radiation hardness. In the future, SOIAPD can be expected to be developed for use asdetectors in high energy physics experiments as well as various industrial applications.

66

Acknowledgement
I would like to convey my sincere thanks to many people without the support of whom this thesis could
not have been completed. Firstly, I want to express my deep gratitude to Prof. Kazuhiko HARA for his
guidance and support in my research. Without his advice and explanations at times when I was stuck theresearch, I couldn’t have moved forward. Similarly, I want to thank Prof. Fumihiko Ukegawa for his
advice, help and motivation in numerous difficult situations. I am extremely grateful for the continuous
guidance and help by Ryutaro Hamasaki, PhD candidate at KEK. He was the one to guide me through thebasics of my research and was always ready to help me whenever I’m stuck into something. I would also
like to thank all the members of SOI group in Tsukuba University as well as SOIPix (specially Prof.
Yasuo Arai) for allowing me to collaborate in their research projects. I also want to remember all
individuals from my laboratory as well as family and friends who put help and effort put into me atdifferent stages ok my research.

67

Bibliography[1] S.L. Miller., “Ionization Rates for Holes and Electrons in Silicon,” Phys.Rev.105,1246(1957).

[2] Lee, Myung-Jae, “Effects of Guard-Ring Structure on the Performanceof Silicon Avalanche Photodetectors Fabricated With Standard CMOS
Technology” IEEE ELECTRON DEVICE LETTERS, Jan. 2012, Vol. 33 No. 1[3] Ehsan Kamrani, “Efficient premature edge breakdown prevention in
SiAPD fabrication using the standard CMOS process ” Semicond. Sci.
Technol. , Aug. 2013

[4] 音野瑛俊, “ガイガーモードで駆動するピクセル化された新型半導体光検出器の基礎特性に関する研究,”
修士論文、(2008).

[5] 村瀬拓郎, “ プロセス・デバイスシミュレーターを用いた半導体光検出器 PPD の基本特性における研究,”
修士論文、(2010).
[6] LHC, http://public.cern.ch/[7] ATLAS, http://atlas.web.cern.ch/[8] ILC, http://www.liearcollider.org/

68[9] Lectures on photodiode detectors
http://course.ee.ust.hk/elec509/notes/Lect12-photodiode%20detectors.pdf[10] APD Hamamatsu handout
http://unicorn.ps.uci.edu/243/handouts/APDHamamatsu.pdf[11] Monolithic pixel detectors with FD-SOI pixel process
http://www.sciencedirect.com/science/article/pii/S0168900213008498[12] Semiconductor Devices Physics and Technology 2nd Edition -S.M. Sze[13] http://hep-www.px.tsukuba.ac.jp/CiRfSE/LDPPD/slide160302/arai20160302.pdf[14] https://www.soitec.com/en/products/smart-cut[15] http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05402397[16] http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6262959[17] https://en.wikipedia.org/wiki/P%E2%80%93n_junction[18] http://www.hep.upenn.edu/atlas/[19] http://physiquereussite.fr/lhc/[20] Optical Communications Systems Laboratory, Dr. Gerald Farrell 2002[21] https://ilc.kek.jp/RDR/69

[22] http://superb.kek.jp/1st-skekb/slide/pxd/Arai.ppt[23] http://www.essderc2002.deis.unibo.it/data/pdf/Jackson.pdf[24] http://meroli.web.cern.ch/meroli/Lecture_silicon_floatzone_czochralski.html

70List of Figures
Figure 1 Energy levels and bandgap ........................................................................................................... 10
Figure 2 Conduction band, valence band and bandgap............................................................................... 11
Figure 3 Mechanism of electrical conduction in semiconductors ............................................................... 12
Figure 4 Intrinsic semiconductor ................................................................................................................ 13
Figure 5 p-type semiconductor
Figure 6 n-type semiconductor.................... 14
Figure 7 Operation of a p-n diode [17] ....................................................................................................... 15
Figure 8 IV characteristics of a p-n junction diode ..................................................................................... 17
Figure 9 Basic structure of a pin photodiodeFigure 10 Basic working principle of a pin photodiode. 18
Figure 11 Avalanche mechanism in APD [10] ............................................................................................ 19
Figure 12 Various modes of operation of an APD [12] ............................................................................... 20
Figure 13 Impact ionization rate of electrons and holes [12] ..................................................................... 21
Figure 14 Excess noise in APD depending on gain [12]............................................................................... 21
Figure 15 Working of a basic silicon detector ............................................................................................. 22
Figure 16 Components of Large Hadron Collider [19] ................................................................................ 23
Figure 17 ATLAS inner detector showing SCT, Pixel detector and TRT [18] ............................................... 24
Figure 18 Schematic layout of the International Linear Collider (ILC) [21]................................................. 25
Figure 19 General SOI structure.................................................................................................................. 26
Figure 20 SOITEC SOI process [14] .............................................................................................................. 28
Figure 21 Bulk CMOS vs SOI-CMOS ............................................................................................................. 29
Figure 22 (a) Hybrid type silicon detector (b) Monolithic type SOI detector ............................................. 29
Figure 23 Crosstalk mechanism
Figure 24 Backgate effect ......................................... 31
Figure 25 TID effect in SOI-CMOS ............................................................................................................... 32
Figure 26 Structure of double-SOI pixel detector ....................................................................................... 33
Figure 27 Double-SOI process (SOITEC) ...................................................................................................... 33
Figure 28 Cross-section view of Double SOI structure using SEM (Courtesy of Lapis Semiconductor)...... 34
Figure 29 SOI structure ............................................................................................................................... 36
Figure 30 SOI Interrupted-N-Finger APD..................................................................................................... 36
Figure 31 SOI Avalanche Double Photodiode ............................................................................................. 37
Figure 32 SOI Reach-through APD .............................................................................................................. 37
Figure 33 a. Top view of a single pixel of SOIAPD b. cross-sectional view of the same ............................. 38
Figure 34 SOIAPD test chip APDTEGh ......................................................................................................... 39
Figure 35 TCAD mesh creation for pixel on the right ................................................................................. 41
Figure 36 apd_retype2_4pixel structure .................................................................................................... 41
Figure 37 Impurity concentration (depth=-0.2μm) .................................................................................... 42
Figure 38 . Impurity concentration (Center.NS,PS)..................................................................................... 42
Figure 39 Electron density profile at different voltages ............................................................................. 43
Figure 40 Electron density at different depths of the pixel ........................................................................ 43
Figure 41 Electron density at different depths from the top (at different reverse voltages) .................... 43
Figure 42 Electric field intensity at different regions of SOIAPD pixel........................................................ 44
Figure 43 Electric field intensity variation across different regions of SOIAPD (at y=-0.2μm) ................... 45
Figure 44 magnified view of the previous figure to show the region near n+, p well ................................ 45
71

Figure 45 Test SOIAPD chips ....................................................................................................................... 46
Figure 46 Kiethley 4200-SCS Semiconductor Characterization System ...................................................... 47
Figure 47 Test chip during measurement using Kiethley-4200-SCS ........................................................... 47
Figure 48 Dark current from 10*10-pixel array and single pixel ................................................................ 48
Figure 49 Ratio of dark current from 10*10-pixel array to that from a single pixel ................................... 49
Figure 50 Capacitance versus reverse bias voltage for different wafer type samples ............................... 50
Figure 51 1/C2 versus reverse bias voltage ................................................................................................. 50
Figure 52 Temperature chamber ................................................................................................................ 51
Figure 53 Sub-board for testing .................................................................................................................. 51
Figure 54 Dark current vs reverse voltage curves at varying temperatures (CZN wafer), original graph on
the right, same graph magnified in near breakdown voltage region on the right ..................................... 52
Figure 55 Dark current vs reverse voltage curves at varying temperatures (FZN wafer), original graph on
the right, same graph magnified in near breakdown voltage region on the right ..................................... 52
Figure 56 Dark current vs reverse voltage curves at varying temperatures (FZP wafer), original graph on
the right, same graph magnified in near breakdown voltage region on the right ..................................... 52
Figure 57 Dark current vs reverse voltage curves at varying temperatures (DSOI wafer), original graph on
the right, same graph magnified in near breakdown voltage region on the right ..................................... 53
Figure 58 LED device ................................................................................................................................... 55
Figure 59 Forward current vs forward voltage of LED device..................................................................... 56
Figure 60 wavelength distribution of output LED light ............................................................................... 56
Figure 61 Specifications of reference photodetector ................................................................................. 56
Figure 62 Dark current of reference photodetector as given by production specification ........................ 57
Figure 63 light sensitivity of reference photodetector versus wavelength of flight .................................. 57
Figure 64 Setup for LED response measurement ....................................................................................... 58
Figure 65 LED response of reference photodetector ................................................................................. 58
Figure 66 LED response of reference photodetector in terms of power.................................................... 58
Figure 67 LED response at different incident led powers versus breakdown voltage ............................... 59
Figure 68 LED response per watt of incident led power, measured at different led intensities ................ 59
Figure 69 Change in gain with reverse bias voltage.................................................................................... 60
Figure 70 rate of change of gain at different bias voltages ........................................................................ 60
Figure 71 change in gain with reverse voltage: alternative measurement ................................................ 61
Figure 72 change in gain with reverse voltage: alternative measurement ................................................ 61
Figure 73 γ ray irradiation setup at Takasaki irradiation facility................................................................. 62
Figure 74 Radiation dose rate to distance curve ........................................................................................ 63
Figure 75 radiation dose distribution table ................................................................................................ 63
Figure 76 Change in dark current (left) and gain (right) before and after 200kGy irradiation in CZn based
APTTEGh pixel ............................................................................................................................................. 64
Figure 77 Change in dark current (left) and gain (right) before and after 200kGy irradiation in FZn based
APTTEGh pixel ............................................................................................................................................. 64
Figure 78 Change in dark current (left) and gain (right) before and after 200kGy irradiation in FZp based
APTTEGh pixel ............................................................................................................................................. 65
Figure 79 Change in dark current (left) and gain (right) before and after 1MGy irradiation in DSOI based
APTTEGh pixel ............................................................................................................................................. 65

72

List of Tables
Table 1 SOI process details [22] .................................................................................................................. 27
Table 2 Advantages of SOIAPD over APD and PPD ..................................................................................... 35
Table 3 Basic data of different wafer types ................................................................................................ 46
Table 4 Breakdown voltages (here taken as voltage where current exceeds 105A) at different
temperatures .............................................................................................................................................. 53
Table 5 LED device specifications ............................................................................................................... 5573

Appendix 1
TCAD source code.
<process simulator>####################################################################################### ====Variables=== ###DP1=40
DP2=0.78 #PS 0.78
DP3=0.78 #NS 0.78
DW1=0.8 #0.81
DW2=3.72
DW3=2.22
xDL=0
Zmask=2.0
zSUB=100
rmax1=1e10
dxmin=0.1
dxmax=0.3
nx=1dzmin=0.2
nz=3##Direction
xDL=0
xWL=DP1
xP1L=xWL+DW1
xP1R=xP1L+DP2
xP2L=xP1R+DW2
xP2R=xP2L+DP3
xP3L=xP2R+DW3
xP3R=xP3L+DP3
xP4L=xP3R+DW3
xP4R=xP4L+DP3

74

xP5L=xP4R+DW3
xP5R=xP5L+DP3
xP6L=xP5R+DW2
xP6R=xP6L+DP2
xWR=xP6R+DW1
xDR=xWR+DP1

xC1=(xWL+xP1L)/2
xC2=(xP1L+xP1R)/2
xC3=(xP1R+xP2L)/2
xC4=(xP2L+xP2R)/2
xC5=(xP2R+xP3L)/2
xC6=(xP3L+xP3R)/2
xC7=(xP3R+xP4L)/2
xC8=(xP4L+xP4R)/2
xC9=(xP4R+xP5L)/2
xC10=(xP5L+xP5R)/2
xC11=(xP5R+xP6L)/2
xC12=(xP6L+xP6R)/2
xC13=(xP6R+xWR)/2

y01=0
y02=1.0z01=-zSUB
z02=-10z03=0
z04=z03+Zmask

grid.x.add(loc=xDL, tag="xDL")
grid.x.add(loc=xWL, tag="xWL")
grid.x.add(loc=xC1, tag="xC1")
grid.x.add(loc=xP1L, tag="xP1L")
grid.x.add(loc=xC2, tag="xC2")
grid.x.add(loc=xP1R, tag="xP1R")
grid.x.add(loc=xC3, tag="xC3")
grid.x.add(loc=xP2L, tag="xP2L")

75

grid.x.add(loc=xC4, tag="xC4")
grid.x.add(loc=xP2R, tag="xP2R")
grid.x.add(loc=xC5, tag="xC5")
grid.x.add(loc=xP3L, tag="xP3L")
grid.x.add(loc=xC6, tag="xC6")
grid.x.add(loc=xP3R, tag="xP3R")
grid.x.add(loc=xC7, tag="xC7")
grid.x.add(loc=xP4L, tag="xP4L")
grid.x.add(loc=xC8, tag="xC8")
grid.x.add(loc=xP4R, tag="xP4R")
grid.x.add(loc=xC9, tag="xC9")
grid.x.add(loc=xP5L, tag="xP5L")
grid.x.add(loc=xC10, tag="xC10")
grid.x.add(loc=xP5R, tag="xP5R")
grid.x.add(loc=xC11, tag="xC11")
grid.x.add(loc=xP6L, tag="xP6L")
grid.x.add(loc=xC12, tag="xC12")
grid.x.add(loc=xP6R, tag="xP6R")
grid.x.add(loc=xC13, tag="xC13")
grid.x.add(loc=xWR, tag="xWR")
grid.x.add(loc=xDR, tag="xDR")
grid.x.refine(from="xWL",to="xDL", start=dxmin,end=dxmax*20, rmax=rmax1)
grid.x.refine(from="xWL",to="xC1", start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP1L",to="xC1",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP1R",to="xC2",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP1R",to="xC3",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP2L",to="xC3",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP2L",to="xC4",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP2R",to="xC4",start=dxmin,end=dxmax,rmax=rmax1)

grid.x.refine(from="xP2R",to="xC5",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP3L",to="xC5",start=dxmin,end=dxmax,rmax=rmax1)

grid.x.refine(from="xP3L",to="xC6",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP3R",to="xC6",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP3R",to="xC7",start=dxmin,end=dxmax,rmax=rmax1)

76

grid.x.refine(from="xP4L",to="xC7",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP4L",to="xC8",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP4R",to="xC8",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP4R",to="xC9",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP5L",to="xC9",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP5L",to="xC10",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP5R",to="xC10",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP5R",to="xC11",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP6L",to="xC11",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP6L",to="xC12",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP6R",to="xC12",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xP6R",to="xC13",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xWR", to="xC13",start=dxmin,end=dxmax,rmax=rmax1)
grid.x.refine(from="xWR",to="xDR", start=dxmin,end=dxmax*20, rmax=rmax1)
grid.y.add(loc=y01,tag="y01")
grid.y.add(loc=y02,tag="y02")
grid.z.add(loc=z01,tag="z01")
grid.z.add(loc=z02,tag="z02")
grid.z.add(loc=z03,tag="z03")
grid.z.add(loc=z04,tag="z04")
grid.z.refine(from="z02",to="z01",start=0.5,end=(z02-z01)/(4*nz),rmax=rmax1)
grid.z.refine(from="z03",to="z02",start=dxmin,end=0.5,rmax=rmax1)
grid.z.refine(from="z03",to="z04",num=Zmask/nz)#---SUB--##region.substrate(
xmin="xDL",xmax="xDR",
ymin="y01",ymax="y02",
zmin="z01",zmax="z03",
orient="100",imp="P",conc=2.16e12)
init_sypros()save.sgraph("00_mesh.sg2",posy="min")oxi_ctrl.set(force_oxidation=true)#--WELL(BP2+BP3+BPW)##

77

deposit(mat="resist",model="planar",thick_from_top=5.0)
WELL=[[xWL,y01],[xWR,y01],[xWR,y02],[xWL,y02]]etch(mat="resist",thick=5.0,mask_pattern=WELL,mask_type="nega")
deposit(mat="SiO2",thick=0.248)
implant(ion="B",energy=500,dose=1.0e12)
implant(ion="B",energy=220,dose=1.0e12)
implant(ion="B",energy=100,dose=1.0e12)etch(mat="SiO2",model="remove_all")etch(mat="resist",model="remove_all")save.sgraph("01_well.sg2",posy="min")#--PIX--##
P1=[[xP1L,y01],[xP1R,y01],[xP1R,y02],[xP1L,y02]]
P2=[[xP2L,y01],[xP2R,y01],[xP2R,y02],[xP2L,y02]]
P3=[[xP3L,y01],[xP3R,y01],[xP3R,y02],[xP3L,y02]]
P4=[[xP4L,y01],[xP4R,y01],[xP4R,y02],[xP4L,y02]]
P5=[[xP5L,y01],[xP5R,y01],[xP5R,y02],[xP5L,y02]]
P6=[[xP6L,y01],[xP6R,y01],[xP6R,y02],[xP6L,y02]]

deposit(mat="resist",model="planar",thick_from_top=5.0)
etch(mat="resist",thick=5.0,mask_pattern=[P2,P3,P4,P5],mask_type="nega")
implant(ion="P",energy=30,dose=5.0e15)etch(mat="resist",model="remove_all")deposit(mat="resist",model="planar",thick_from_top=5.0)
etch(mat="resist",thick=5.0,mask_pattern=[P1,P6],mask_type="nega")
implant(ion="B",energy=40,dose=5.0e15)etch(mat="resist",model="remove_all")save.sgraph("02_PIX.sg2",posy="min")#--DIFF--##
diffuse(amb="nitrogen",temp=1050,time=10/60)
save.sgraph("04_diff.sg2",posy="min")#####output_file######
save.sgraph ( file = "profile.sg2",posy="min")save.deleos ( file = "profile.geo", x =500, y =0.5)
save.deleos ( file = "profile_2D.geo", posy = "min")78

#print1d(value = "field_data",field="B_ac",file="profile_B_ac",x="xC2",y=0.0)#print1d(value = "field_data",field="P_ac",file="profile__P_ac",x="xC2",y=0.0)#####finish#####
end_sypros()<structure simulation>#!variable
profile="profile_2D.geo"
Width=1.0
DP1=40
DP2=0.78 #PS 0.78
DP3=0.78 #NS 0.78
DW1=0.8 #0.81
DW2=3.72
DW3=2.22
zSUB=100xDL=0xWL=DP1
xP1L=xWL+DW1
xP1R=xP1L+DP2
xP2L=xP1R+DW2
xP2R=xP2L+DP3
xP3L=xP2R+DW3
xP3R=xP3L+DP3
xP4L=xP3R+DW3
xP4R=xP4L+DP3
xP5L=xP4R+DW3
xP5R=xP5L+DP3
xP6L=xP5R+DW2
xP6R=xP6L+DP2
xWR=xP6R+DW1
xDR=xWR+DP1#!structure
dimension(dimension=2,width=Width)mesh(file_name=profile)region(material="all",file_name=profile)
doping(type="B",file_name=profile)
doping(type="P",file_name=profile)electrode(name="Back",x_min=0,x_max=xDR,y_min=-zSUB-0.1,y_max=-zSUB)
electrode(name="P1", x_min=xP1L,x_max=xP1R,y_min=0,y_max=0.1)
electrode(name="P2", x_min=xP2L,x_max=xP2R,y_min=0,y_max=0.1)
electrode(name="P3", x_min=xP3L,x_max=xP3R,y_min=0,y_max=0.1)
electrode(name="P4", x_min=xP4L,x_max=xP4R,y_min=0,y_max=0.1)
electrode(name="P5", x_min=xP5L,x_max=xP5R,y_min=0,y_max=0.1)
electrode(name="P6", x_min=xP6L,x_max=xP6R,y_min=0,y_max=0.1)
outfile ( dst = "profile.dst", sgn = "profile.sgd", )structure ( )<Device simulator>#####variables####bias_start = 0.0
bias_end = -22
bias_step = 0.5
dc_temp=300
dc_reset=10#!analysis

79set_method(damp=ON)
set_method(mtx_solver=SUPERNODAL)
set_method(ej_mob=false)
set_method(ej_others=true)
set_method(minpsi=1.0,minele=1e18,minhol=1e18)
set_method(errpsi=1e-2,errele=1e-1,errhol=1e-1)
set_method(conv_cond=CONV_EQUATION_AND_CURRENT,errbdc=1e-2,resbdc=1e-2)
initial_guess("Linear")
set_mobility(lattice=ON,coulomb=MASETTI,surface=OFF,vsat=SCHARFETTER)
set_grrate(srh=ON,aug=ON,ii=ON,btbt=ON,sur=OFF)
set_quantum(model=OFF)
set_output(cur_filename="iv.cur")
set_output(dis_filename="iv.dis",
dis_out=ALL,
dis_vars=[Psi,E,Hole,Elec,II,SRH,Jn,Jp])
set_bias(name="P2",0)
set_bias(name="P3",link="P2")
set_bias(name="P4",link="P2")
set_bias(name="P5",link="P2")
set_bias(name="P1",v0 = bias_start, v1 = bias_end, dv = bias_step,)
set_bias(name="P6",link="P1")
run_dc(temp=dc_temp,reset=dc_reset,cont=true)
ds_exit()80

Appendix 2
Carrier generation/recombination models
Carrier generation/recombination U can be expressed using Shockley-Read-Hall’s
generation/recombination term USRH, surface recombination term USUR, Inter-band tunnelingterm UBTBT, Auger recombination term UAUG and Impact Ionization term UIMPACT as follows:
U = 𝑈𝑆𝑅𝐻 + 𝑈𝑆𝑈𝑅 + 𝑈𝐵𝑇𝐵𝑇 + 𝑈𝐴𝑈𝐺 + 𝑈𝐼𝑀𝑃𝐴𝐶𝑇
Surface recombination model and impact ionization model can be expressed below:
1. Surface recombination model,𝑛 2 −𝑝𝑛

U𝑆𝑈𝑅 = 𝑛+𝑛𝑖 𝑖 𝑝+𝑛𝑖 𝛿(𝑦)
𝑠𝑝

+

𝑠𝑛

ni: intrinsic carrier densityn, p: electron or proton density
N: impurity concentration (donor and acceptor)sn,sp: model parameter
2. Impact ionization model

TL: lattice temperature
TL0: surrounding temperature
Jn, Jp: electron/hole current vector
Αn0, βn0, En0, βn1: model parameters (electrons)
Αp0, βp0, Ep0, βp1: model parameters (holes)

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