Introduction of SOI
Pixel Development
Feb. 1, 2013
IHEP@Beijing
Yasuo Arai, KEK
yasuo.arai@kek.jp
http://rd.kek.jp/project/soi/OUTLINE

•!Introduction of SOI Technology•!SOI Pixel Detector Development•!On-Going R&D’s•!SummarySOI Wafer Production (Smart Cut by SOITEC)

CMOS(Low R)

Sensor(High R)Bulk CMOS vs. SOI CMOS

In SOI, Each Device iscompletely isolated byOxide.
Faces many barriers
to further
miniaturization


Our SOI

Industry move : Bulk CMOS to PD-/FD- SOI CMOS

(from "Fully DepletedSOI", Xavior Cauchy, SOI Industry Consortium)

Steep Sub Threshold Slope

Gate voltage is not wasted todeplete the bulk.
Lower Threshold (Leakage Current) is possible without
increasing Leakage Current (Vth).
Copyright 2007 Oki Electric Industry Co.,LtdSOI Performance : Smaller Junction Capacitance

Cj is 1/10 of Bulk technology.
Gate Capacitance is 30-40%
Lower.

High Speed / Low PowerRadiation Tolerance
SOI is Immune to Single Event EffectGate Oxide
GateSi% && %
% && %
% && %
% && %
% && %
% &Gate
Si% &Buried
Oxide

Depletion
Layer

Bulk Device

SOI Device% && %
% && %
% && %

But not necessary strong to Total Ionization Dose due to thick BOX layer
GateThis must be remedy forthe application under highradiation environment.

SiBuried
Oxide% % % % %

TrappedHolesOperation at Cryogenic Temperature

Bulk MOS

4.2K

SOI MOS(worked in 1.4K)



SOI Pixel Detector (SOIPIX)
Monolithic Detector having fine resolution of silicon
and data processing power of CMOS LSI by using
Silicon-On-Insulator (SOI) Technology.

Feature of SOI Pixel Detector
•! No mechanical bonding. Fabricated with semiconductor
process only, so high reliability, low cost are expected.
•! Fully depleted thick sensing region with Low sense
node capacitance.
•! On Pixel processing with CMOS transistors.
•! Can be operated in wide temperature (4K-570K) range,and has low single event cross section.
•! Based on Industry StandardTechnology.

Lapis (*) Semiconductor 0.2 µm FD-SOI Pixel Process
Process

0.2µm Low-Leakage Fully-Depleted SOI CMOS
1 Poly, 5 Metal layers.
MIM Capacitor (1.5 fF/um2), DMOS
Core (I/O) Voltage = 1.8 (3.3) VSOIwafer

Diameter: 200 mm!, 720 µm thick
Top Si : Cz, ~18 "-cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz (n) ~700 "-cm,FZ(n) >1 k "-cm, FZ(p) >1 k "-cm

Backside Mechanical Grind, Chemical Etching, Back sideprocess Implant, Laser Annealing and Al plating(*) Former OKI Semiconductor Co. Ltd.
Regular Multi-Project Wafer(MPW) run. (~twice/year)

U. of Hawaii
Fermi Nat'l Accl. Lab.

JAXA

RIKEN

Osaka U.KEK

Lawrence Berkeley Nat'l Lab.
INP Krakow
U. Heidelberg
Louvain-la-Neuve Univ.

Kyoto U.AISTTohoku U.
Tsukuba U.

IHEP/IMECAS/SARI China
SOIPIX MPW runWaferSubmission from Chinese Coleague
•! 2013.1 MX1594
IHEP (Lu Yunpeng) 6x6 mm2 + 2.9x2.9 mm2
SARI (Ning, Wang, Li Tian) 2.9x2.9 mm2•! 2012.7 MX1542
IMECAS(Zhao Kai) 12.2x12.2 mm2 + 2.9x2.9mm2•! 2011.10 MX1501
IHEP (Liu Gang, Lei Fan) 2.9x2.9 mm2
IHEP (Lu Yunpeng) 2.9x2.9mm2•! 2011.1 MX1442
IHEP(Liu Gang) 2.4x2.4mm2•! 2010.8 MX1413
IHEP(Zheng Wang, Lei Fan) 2.4x2.4 mm2 x2

Transistor Type
Core Transistor (1.8V) : Normal Vth & Low Vth
I/O Transistor (3.3V) : Normal Vth & High Vthp

Body FloatingSource-Tie(Type 1)

p

Source-Tie(Type 2)

Structure of Top Si

1 Poly + 5 Metal
MIM Capacitor on 3M Sensor Structure

•!PS & NS --- High Doping Density Layer (Top Si is removed)•!BPW, BP2, BP3 & BNW --- Low Doping Density Layer (TopSi is not removed)

 

Trace Fuse (option)
You can chase the chip location
where it come from if you include
this fuse in your design.
Number of Fuse (total 16 lines)* Lot No. : 4 lines (1~15)* Wafer No. : 5 lines (1~31)* Chip Location in wafer : 7 lines (1~127)

Laser Cut 

I/O Cell LibrariesWe prepared several I/O frames
for your convenience.

Chip Frame for Pixel

I/O Buffers+ Vdet ring
+ Vbias ring+ BPW

2.9 mm Frame

6 mm FrameWe get minimum
number of I/O cells
from Lapis.
Then we have createdmany more for users.

Please provide us
your I/O cells if youdevelop new one.Mask

31 mm

•! We are using relatively
large mask to enable
many designs and largesensors•! Low cost per area.
•! Smallest chip area :#2.9 x 2.9 mm224.8 mmStitching Exposure
Mask Layout

If you want much larger detector !
Exposed Layout

PixelBlindBlind



Riken SOPHIAS detector
BufferRegion
10um

Shot A

Shot ABufferRegion
10um

Shot A

Shot B•! Width of the Buffer Region can be less than 10um.
•! Accuracy of Overwrap is better than 0.025um.


FZ(p and n) SOI Wafer
It was difficult to process 8’’ FZ-SOI wafer in CMOS process.
" ! !
SlipsWe optimized the process parameters, and succeeded toperform the process without creating many slips.
High Resistive wafers

INTPIX3eData Acquisition Board*!   &%$  "'$$! +*!    $" #$ (!
*! "$)$"#""$  $"$    $"#"&$"$   

On-Going SOI Projects in Japan•!INTPIX : Genera Purpose Integration Type•!CNTPIX : General Purpose Counting Type•!SOPHIAS : Large Dynamic Range for XFEL•!PIXOR : Belle II Vertex Detector•!XRPIX : X-ray Astronomy in Satellite•!MALPIX : TOF Imaging Mass Spectrometer•!TDIPIX : Contamination Inspection•!LHDPIX : Nuclear Fusion Plasma X-ray•!!       

Q 0.6 fC
Vsense = "= 70mVC
8 fF

#

Size : 14 µm x 14 µm
with CDS circuit 

INTPIX6 Pixel2 Gain
12 x 12 um2 INTPIX4Pixel Size : 17 um x 17 um
No. of Pixel : 512 x 832 (= 425,984)
Chip Size : 10.3 mm x 15.5 mm
Vsensor=200V, 250us Int. x 500X-ray Tube : Mo, 20kV, 5mAFine resolution & High Contrast

5mm
X-ray Image of a small dried sardine taken bya INTPIX4 sensor (3 images are combined).

(A. Takeda)


X-ray Energy Spectrum

XRPIX1

Cu K$ and K# is separated
Noise ~ 23e- @-50$C

FWHM=260eV

(Kyoto Univ.)
Compton Electrons from High-Energy X-raysIsuues in SOI Pixel
Sensor and Electronics are located very near. This cause ..

We need additional back-plane to suppress these effects.Buried p-Well (BPW)
BPW Implantation

Substrate Implantation!*+),-(&.)-,(/!&01%&'(%)
").,2

"$",+)34,+52!"#•! Cut Top Si and BOX•! High Dose•! Keep Top Si not affected•! Low Dose•!Suppress the Back Gate Effect.
•!Shrink pixel size without loosing sensitive area.
•!Increase break down voltage with low dose region.
•!Less electric field in the BOX which improve radiation
hardness.

Id-Vg and BPW NMOS

w/o BPW

with BPW=0V

back channel open
shift

Back gate effect is suppressed by the BPW.
Double SOI Wafer
circuit
sensoradditionalconduction layer

•!Shield transistors from bottom electric field•!Compensate electric field generated by the trappedhole in the BOX.
•!Reduce crosstalk between sensors and circuits.

 Cross Talk Simulation
Signal On the Sensor

Induced Signal at the Sensor
Standard SOI(690e-)
Double SOI(63e-)

Cross Talk from the circuit to the sensor can be reduced 1/10,
and signal shape will be bipolar. ! disappear in charge amp.  Negative View

GateTop-SOI

BOX2BOX1
SubMiddle-SOI

0.3um
Suppression of Back-Gate Effect with Middle-Si layerb) Middle-Si = GND

   

a) Middls-Si Floating

 



Back-Gate Effect is fully suppressed withthe Middle Si Layer of fixed voltage.













Nch Core Normal-Vt
L / W = 0.2 / 5.0um
Vd=0.1V

41

Trapped Charge Compensation (Threshold Control)with Middle-Si LayerThreshold voltage of a transistor
is controlled with the bias voltegeof the Middle-Si layer.
This indicate effects of thetrapped charge in the BOX canbe compensated with the biasvoltage.





Nch Core Normal-Vt
L / W = 0.2 / 5.0 um
Vd=0.1V, Vback'floating42

Double SOI Irradiation Test

Preliminary!

N33_IONVT_ST2_L0.4_w5NMOS
Vsoi2

Vsoi2=-2.0[V]
Vsoi2=-1.0[V]

Vsoi2=-2.0[V]
PMOS
Vsoi2=0.0[V]

Vsoi2=0.0[V]
Vsoi2
Vsoi2=-1.0[V]
Dose[kGy]

We could observe restoration of the threshold shift withapplying negative voltage to the SOI2 layer.

43

Summary
•!SOI technology has many good features; low power, lowvariability, large operating temperature range, no latch
up..., and Industries are moving to extremely thin SOI.
•!SOIPIX is monolithic detector, and many kinds of detectors
are already working.
•!We have ~twice/year regular MPW runs with increasing
no. of users.
•!The process technology is still progressing; Higher
resistivity wafer, Nested well structure, Larger mask size,Stitching, and Double SOI, etc. !
•!We welcome new collaborators to the SOI pixel
development!
