SiGe ROC chips for HEP
at OMEGA lab
KEK seminar, つくば市 (日本国)
Salleh AHMAD, Sylvie BLIN, Stéphane CALLIER, Frederic DULUCQ, Julien
FLEURY, Christophe de LA TAILLE, Gisèle MARTIN-CHASSARD, Ludovic
RAUX Nathalie SEGUIN-MOREAU, Damien THIENPONT, Jeanne TONGBONGOMEGA microelectronics laboratory
Ecole Polytechnique & CNRS IN2P3
http://omega.in2p3.fr& WEEROC SAS
http://weeroc.com

Organization for Micro-Electronics desiGn and Applications

Outline• Evolution of technologies, advantages of SiGe
• Examples of OMEGA chips in SiGe for photdetector
readout• Evolution of SiGe projects

CdLT SiGe ROC ASICs KEK seminar

2

ITRS 2011 roadmap

http://www.itrs.net/Links/2011ITRS/2011Chapters/2011ExecSum.pdf

21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

3

MOS and Bipolar© K. Troki (CMP)

http://cmp.imag.fr/aboutus/slides/Slides2011/02_Runs_2011.pdf
21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

4

SiGe technology• Faster bipolar transistors for RF telecom© R. Hermel– Better mobility and FT– Better current gain (beta)– Better Early voltage– Interesting improvement at low T– Compact CMOS (0.25 or 0.35µm) for mixed-signal design

21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

5

Power and speed with SiGe
• BJT : best gm /I ratio (1/UT)– Large transconductance with small
devices• Speed goes as FT= gm /2πC
– C~10 fF gm typ mA/V
– FT ~60 GHz for SiGe 0.35µm– Interesting for fast preamps• Not forgetting 100V Early voltage andmatching performance (A~mV*µm)• VBE=VTLn(IC/IS)• Large swing : VCEsat ~3 UT

21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

6

Evolution of technologies in practice• Performant design is at transistor level• More and more functions are integrated inside chips (ASICs)• Evolution of technologies make them more and more performant but
more and more complex

10 ans d'évolution des spécifications techniques pour la réalisation d' ASIC

© G.G.Deptusch
FNAL
Deptuch, Fermilab

CdLT SiGe ROC ASICs KEK seminar

7

Design Groups – Current Status© G.L. de Geronimo (BNL) TIPP2014

design groups ≈ 30-40
...

...

...

...

active designs ≈ 30-40...
... NOvA APV25
MAPS POM
3D FSSR2 ASDQPACIFIC ICECAL
FE-I5 CBC LBNE VMM
MAROC3CLARO
KPIX nEXOLAPAS ASDCDC SAMPABEAN QIEVELOPIX
ABC ... SAO3
...
CLIC
SALT
TARGET ISR3B

Average one design per group• institutions leading collaborative efforts• institutions performing R&D on technologies
One FE-ASIC design currently requires
2-4 full-time designers and 2-4 years
21 apr 2015

average, fromconcept
to ready-for-production
CdLT
SiGe ROC ASICs
KEK seminar

8Design Groups – Current Status
In order to be efficient and maintain state-of-the-art
ASIC groups must:• develop 1-2 new designs and 2-4 revisions per year
• work with 2 technologies (re-usage & next)• perform R&D on circuits and technologies

The critical minimum is currently 5-6 designers
Need to diversify while contributing to PP
with an average of 25-30 % of resources
PP currently supports/uses up to 25-30 %21 apr 2015

CdLT SiGe ROC ASICs KEK seminar9

Omega microelectronics lab

Education,
SchoolResearch,
Institute

Industry, company

CdLT SiGe ROC ASICs KEK seminar

10

OMEGA laboratory
•
•
•
•
•

Mutualized ASIC design team
10 research engineers (1 IR0, 2 IR1, 6 IR2, 1CDD), 2 pHD students
Importance of critical mass for more and more complex circuits
Cross-fertilization between projects
Technology transfer via startup WEEROC

21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

11

OMEGA ROC chips••

Use of Silicon Germanium 0.35 µm BiCMOS technology since 2004
Readout for MaPMT and SiPM for ILC calorimeters and other applications•

Very high level of integration : System on Chip (SoC)
Chip

detectorch

DR (C)

MAROC

PMT

64

-2f-50p

SPIROC

SiPM

36+10f-200p

SKIROCSi

64+0.3f-10p

HARDROC

RPC

64-2f-10p

PARISROC

PM

16-5f-50p

SPACIROC

PMT

64-5f-15p

MICROROCµMegas64-0.2f-0.5p

PETIROC

SiPM

3250fC-300pC

CdLT SiGe ROC ASICs KEK seminar

MAROC3

http://omega.in2p3.fr
HARDROC2

MICROROC1SKIROC2SPIROC2SPACIROC
PARISROC2

12

Photomultipliers Readout• MAROC• SPACIROC• PARISROCCdLT SiGe ROC ASICs KEK seminar

13

MAROC for MAPMT• Started with OPERA_ROC (2001)– 32 Channels in BiCMOS 0.8 µm– 3000 chips produced in 2002
– Readout OPERA Target tracker in Gran Sasso

7m• MAROC1 (2004)– First prototype with 64 channels– AMS SiGe 0.35 µm (12 mm2, Pw=5 mW/ch)• MAROC2 (2006)– 1000 chips produced and bonded on a compact PCB
for ATLAS luminometer (ALFA)OPERA_ROC• MAROC3 (2009)– Lower power dissipation– Wilkinson ADC added– 1000 chips produced in 2010

• Many applications: Double-Chooz, Menphyno,
medical imaging(Valencia, ISS Roma)…
MAROC2
CdLT SiGe ROC ASICs KEK seminar

14

MAROC3 : MultiAnode Read-Out Chip•

Complete front-end chip for 64 channels multi-anode photomultipliers––––

6bit-individual gain correction
Auto-trigger on 1/3 p.e. at 10 MHz
12 bit charge output with internal ADC
SiGe 0.35 µm, 12 mm2, Pd = 5 mW/ch

vdd_pa32u/0.5u

in_pmos
vb_pa

Rc=30k
Q2

100

in_pa

Q1

ibi_pa21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

Preamplifier « supercommon base »15

MAROC3 layout
AMS SiGe 0.35µm
Package: CQFP240
Area: 16 mm2

10bit DACs
CdLT SiGe ROC ASICs KEK seminar

64 trigger outputs

ADC logic

Discriminators

Shapers

Preamps

64 PM inputs

1 MUX charge output

2 Fast OR
outputs
16

Rms = 3.5 fC

180

Threshold = 50 fC = 1/3 pe
Jitter < 100 ps

160
140

Séri
e1

120
100
80
60

40
20
0
0

Qin = 50 fC = 1/3 pecrosstalk ~1%

CdLT SiGe ROC ASICs KEK seminar

200

400

600

800

1000

1200

Time walk (ns)Jitter (ps rms)

MAROC3 performance

Input charge (fC)

Chrage readout 20 pC

17

MAROC3 users

2012-2013
Ralf ENGELS
Vladimir SOLOVOV
Scott Lumsden
JJ Velthuis
Piero Giorgio FALLICA/ ST
micro
Vincent TATISCHEFF
Alexander Nadeev
Domenico Lo Pesti
E.L. Rizzini
D. Lo Presti
P. Rodrigues
Stephen Wotton
JJ Velthuis
Riccardo Faccini
Patrizia Rossi
Sima Cristina
Patrizia Rossi
D.Cussans/P.Baesso
Paolo Baesso

Allemagne/Juelich
Portugal/ Coimbra
UK/Glasgow
UK/Bristol
Italie/ Catania
France/Orsay
RussieItaly/Catania
Suisse/Genève
Italie/ Catania
Portugal/Lisboa
Suisse/Genève
UK/Bristol
Italie/Roma
Italie/Frascati
Roumanie/Magurele
Italie/Frascati
UK/Bristol
UK/Bristol

Alain Blondel

Suisse/Genève

Pedro Rodriguez

Portugal / Lisboa

William Brooks

Chili / Valparaiso

Stephane Colonges

France / Paris

Evandro Lodi Rizzini

Suisse / Genève

Günter Kemmerling

Allemagne/JuelichThomas Schweizer

Allemagne/Munich

Jason Legere

USA / Durham

Evandro Lodi Rizzini

Suisse / Genève

Ronan Oger

France / Paris

Erik Vallazza

Suisse / Genève

Daniel Bertrand

Belgique / Bruxelles

Ronan Oger

France / Paris

Jason Legere

USA / Durham

Tanushyam Bhattcharjee

Kolkota/IndeVincent Tatischef

France / Orsay

CdLT SiGe ROC ASICs KEK seminar

Gabriela Llosa
Pierre Salin
Prof. A.A.Petrukhin
Erik Vallazza
Riccardo Faccini
Pierre Salin
Prof. A.A.Petrukhin
Mr Patzak

Espagne / Valence
Sofia Antipolis/France
Russie/Moscou
Suisse / Genève
Roma/Italie
Sofia
Antipolis/France
Russie/Moscou
Paris VII
Bari - Italie
France / Paris
Italie / Pise
Italie / Rome
Corée
Italie / Rome
Orsay
Japon
USA
France / Orsay
France / Orsay
France / Paris
France / Orsay

ATLAS lumi : 500chips (LAL)
Double Chooz : 1000 (Nevis)
JJ Jaeger
Gabriela Llosa
Garibaldi/Cisbani
Shinwo Nam
Garibaldi/Cisbani
SuperNemo
Manobu Tanaka
John Parsons
Bernard Genolini
Nicoleta Dinu
JJ Jaeger
Vincent Tatischef

CLAS12 RICH (INFN)
LHCb RICH ? (CERN)JUNO Veto ? (IPHC)18

© L. Cojocariu Univ Bucharest

CdLT SiGe ROC ASICs KEK seminar

19

Variant : SPACIROC for JEM-EUSO• JEM-EUSO (JAXA)– Cosmic ray imaging from ISS• EUSO balloon (CNES)– Test flight 25/8/14• TA experiment (UTAH)CdLT SiGe ROC ASICs KEK seminar

20

SPACIROC• 100 MHz Photon counting for JEM-EUSO• 64 ch radtol MaPMT readout• Pd < 1 mW/ch

CdLT SiGe ROC ASICs KEK seminar

21

SPACIROC3 performance

CdLT SiGe ROC ASICs KEK seminar

22

PARiSROC for PMm2
• Photomultiplier ARray Integrated SiGe ROC– « Large area PMT array » with centralized ASIC
– Auto-trigger at 1/3 p.e.
– Charge and time measurement (10-12 bits)– Data driven : « One cheap wire out »CdLT SiGe ROC ASICs KEK seminar

2

LAGUNA/LHAASO : PARiSROC (PMm²)• Next generation large area photomultipliers– Replace large PMTs by arrays of smaller
ones (PMm² project)– Centralized ASIC 16 independent channels– Data driven : zero suppressed digital output– Single photoelectron sensitive, 100 ps timing

Large scale demonstrator
with 7680 electronic
channels in liquid Argon© Tomas Patzak,
Margherita Buizza
APC, Paris, France© Tiina Suomijarvi, Yingtao Chen IPN, Orsay
CdLT SiGe ROC ASICs KEK seminar2

PMm² demonstrator
PARISROC2 chip

1-in (XP3102) single p.e. noise spectrum.

Watertight box

2m x 2m array

8-in (Hamamatsu R5912)
Single p.e. noise spectrum.

CdLT SiGe ROC ASICs KEK seminar25

Performance

10000
HV1250 Ext_trig
HV1300 Ext_trig

9000
8000

EVENTS

7000
6000
5000
4000
3000
2000
1000
0

CdLT SiGe ROC ASICs KEK seminar

60

80

100

120
LSB

140

160 2

180

Silicon-Photomultipliers Readout• SPIROC• EASIROC/CITIROC• PETIROC• TRIROCCdLT SiGe ROC ASICs KEK seminar

27

SiPM from SPIROC to TRIROC
•

•
•

•

•

FLC_SiPM designed and produced to equip the Analog H-Cal physics prototype for
the ILC in 2005 (1 cubic meter, 38 layers, 2cm steel plates, 8000 tiles with SiPM)
 1st ASIC to readout SiPMSPIROC developed in November 2007 to equip the CALICE AHCAL and ECAL
EUDET technological prototypes
Variants of SPIROC: EASIROC designed in September 2009, CITIROC in 2013
 EASIROC/CITIROC : “light” analog version of SPIROC for SiPM users who
don’t need the ILC specific digital core
Others applications using SPIROC/EASIROC/CITIROC chips for SiPM readout Astrophysics: PEBS experiment (Aachen University), CTA
 Medical imaging (Roma, Pisa, INMC Orsay, Valencia, etc.)
 Nuclear physics: E40 experiment (KEK) Volcanology: MuRay muon radiography of geological structures (INFN Napoli)
Dedicated chip for fast timing and high timing resolution applications
 PETIROC (November 2013)
 TRIROC (March 2014) “FP7” project

CdLT SiGe ROC ASICs KEK seminar

28

SPIROC for SiPM readout•

SPIROC : Silicon Photomultiplier Integrated
Readout Chip
– Developed to read out the analog hadronic
calorimeter for CALICE (ILC)– DESY collaboration (EUDET project)– Chip embedded in detector : low power !

•36 channels autotrigger 15bit readout––––

Energy measurement : 15 bits in 2 gains
Autotrigger down to ½ p.e.
Time measurement to ~1ns
Power dissipation : 25µW/ch (power pulsed)

21 apr 2015

(0.36m)2 Tiles + SiPM + SPIROC (144ch)

2

CdLT

SPIROC : System On Chip
ValidHoldAnalogb

16

RazRangN
16

Chipsat
16

ReadMesureb

NoTrigAcquisition
ExtSigmaTM (OR36)

gain

StartAcqt
SlowClock

System On Chip
Hit channel register 16 x 36 x 1 bits

Wilkinson ADC
Discri output

TM (Discri trigger)

Trigger discri Output

36

BCID 16 x 8 bits

Channel 0
gain

Conversion
ADC

36
ValGain (low gain or
high Gain)
36
Wilkinson ADC
Discri output

EndRamp (Discri ADC
Wilkinson)

Trigger discri Output

Channel 1..…
…
TDC ramp

FlagTDC

TransmitOn
StartConvDAQb
RamFull
OutSerie

readout

EndReadOut+

StartReadOut

EcritureRAM

Rstb
Clk40MHzADC ramp

Startrampb(wilkinson
ramp)

OR36
StartRampTDC

Chip ID register 8 bits

RAM

ChipID
8

ASIC

ValDimGray

ValDimGray 12 bits

12

CdLT SiGe ROC ASICs KEK seminar

DAQ
30

SPIROC performance

36-channel S-curves: trigger efficiency
versus threshold (1 LSB = 2 mV)

Pedestal

50fC
injected

CdLT SiGe ROC ASICs KEK seminar

31

SPIROC2 performance
SiPM SPECTRUM with Autotrigger

32
CdLT SiGe ROC ASICs KEK seminar

32

Variant : EASIROC/CITIROC
Channel 31
1
input

Hold

Read Low Gain

0.1pF - 1.5pF

in_calib
3pF

Low Gain
PreAmp.

Multiplexed
Output25 - 175 ns

3pF

Hold

IN
Ch0

Read High Gain

0.1pF - 1.5pF
High Gain
PreAmp.

Variable Low
Gain PA (4 bits)

Variable High
Gain PA (4 bits)

1
outputChannel0_trigger

32
outputs

Trigger
Multiplexed
Output1
output25 - 175 ns

c15p

8-bit DAC
0-5V

Multiplexed
Output+Slow Shaper

15pF

ON

1
output+Slow Shaper

1.5pF

32
inputs•Channel 0
Ctest•

RS or Discri

Bipolar Fast
Shaper
15 ns

Latch
RS

V_th

DiscriLG Slow Shaper
Variable Shaping
Time (3 bits)

HG Slow Shaper
Variable Shaping
Time (3 bits)

Read

10-bitDAC

1
OR32 output
Ch31_trigger•

32-channel front-end readout(analogue part of SPIROC)– 2 multiplexed analog outputs(high gain, low gain) [tri state
outputs]
Trigger output– 32 Trigger outputs– OR32 output– Trigger multiplexed output(latch included) [Tri state
output]Low power : 4.84 mW/channel,
155 mW/chip

Common to the 32 channels

SipMed, IMNC, LAL, OMEGA

JPARC

33
CdLT SiGe ROC ASICs KEK seminar

33

CdLT SiGe ROC ASICs KEK© seminar
T. Takeshita (Shinshu)

34© T. Shiozaki, R. Honda, K. Miwa
S. Akawa(Tohoku, Univ)
T. Uchida, K. Ucheno (KEK E-sys)

CdLT SiGe ROC ASICs KEK seminar

CFT tracker E40

35

The “Shadow” of the Vesuvius© P. Strolin INFN Napoli
21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

36

CITIROC• Evolution of EASIROC 32 ch SiPM readout––––

32 channels, positive input, 5V input DAC HV adjustment
32 trigger outputs & High Gain / Low gain multiplexed charge output
Peak detector and two trigger level (timing & energy)
Gain adjustment per channel (6 bits)

CdLT SiGe ROC ASICs KEK seminar

37

PDM Electronics
ASSEMBLING

SiPM board(9 +1 temperature
sensors embedded

FOV = 9.6°
Ø = 350mm

Photon Detection Module (PDM)

Front-End board(2 CITIROCASIC)PDM FPGA Board(XILINX ARTIX 7)

Pixel = 0.17°  6.2 x 6.2 mm© O. Cataneo INAF Palermo
CdLT SiGe ROC ASICs KEK seminar

38

CITIROC: Peak detector
2200

P
D

2000

ADC Unit

1800© O. Cataneo INAF Palermo

SCA

1600

1400

1200

1000
0

10

20

30

40

50

60

x 2.5 ns

21 apr 2015

CdLT SiGe ROC ASICs KEK

Osvaldo Catalano– 7th SST Meeting - Geneva 2013, 16-18 December

39

CITIROC: Trigger Linearity
Gain premplifier =4*25fF  150 nom.
Shaping Time = 50ns
Steps of 1,2,3,4,5,6,7,8,9,10 pe

SiPM 4 pixel High Gain =150
Shaping Time = 50ns
delay time = 38 x 2.5 ns
Temp = 23.7 °C Uover = 1V
Resistance = 50 Ohm
Threshold = 922 DAC ~50% of 1
plateau
21 apr 2015
CdLT SiGe ROC ASICs KEK seminar

40

SiGe GHz Front End••

R&D of 10GHz GBWP preamps for applications where fast timing or high timing
resolution is needed (Time Of Flight PET MRI, preclinical, particle physics…)
3 architectures in 0.35µm SiGe technology integrated and tested
1 pe-=160fC
RF (Common Emitter)

Testboard #3
With 100pf/50 Ohm injector (SiPM emulation)

Common BaseSuper Common BaseVb_cb : 400 #DAC

Vb_scb : 1023 #DAC

Noise floor (pedestal)

185-187 #DAC / 1.196V

216-224 #DAC / 1.259V

340-342 #DAC / 1.514V

Signal value @ 10pe

235 #DAC / 1.300V

137 #DAC / 1.085V

115 #DAC / 1.038V

Signal amplitude @ 10pe (signal minus pedestal)

50 #DAC / 110mV

83 #DAC / 174mV

226 #DAC / 476mV

Gain (mV/pe)

10.4mV/pe (5 #DAC/pe)

17.4mV (8.3 #DAC)

47.6mV/pe (22.6 #DAC/pe)

Jitter - threshold 1 pe @10pe

13ps RMS
8ps RMS

6ps RMS
6ps RMS

8ps RMS
8ps RMS

Jitter - threshold 3 pe @10pe
With 100nF DC block (for voltage gain & BW meas.)

18mV injection

18mV injection

7mV injection

Signal Value

267 #DAC / 1.371V

41 #DAC / 0.884V

192 #DAC / 1.2V

Signal amplitude (signal minus pedestal)81 #DAC / 175mV

179 #DAC / 375mV

150 #DAC / 320mV

Voltage gain (before 50 ohm bridge => factor of 0 .5)

4.86 V/V

10.4 V/V

22.5 V/V

Bandwidth, after discriminator (Δt 10% T50% meas.)Δt : 150ps / 660MHz

Δt : 360ps / 280MHz

Δt : 400ps / 250MHz

 Design of PETIROC1: 16 channels with RF amplifier PETIROC2 32ch TRIROC 64 ch
21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

41

PETIROC1: Triggers on first pe• Tests on EPTIROC1 (analog version of
PETIROC2)• 1x1mm SiPM Hamamatsu• Laser for low light injection– 405nm, Jitter : 28 ps FWMH

Minimum

2200

Mean
RMS
c2 / ndf
Constant
Mean
Sigma

2000
1800

153.2 ± 0.407
70.26 ± 0.2878
327.5 / 81700 ± 25.6
199.4 ± 0.1
8.509 ± 0.099

1600
1400
1200
1000
800

• Petiroc can trigger on first photoelectron• Petiroc is low noise : single photon
identification

600
400
200
0

0

50

100

150

200

250
300
350
Minimum value (mV)

2 ns/div
1 pe laser injection
threshold 0.5pe
Preamp + trigger

10 pe laser injection
threshold 5pe
Preamp + trigger

2 ns/div
CdLT SiGe ROC ASICs KEK

42
2 ns/div42

Petiroc : bandwidth issues• Pulser vs SiPM comparison• SiPM is significantly slower than Petiroc– Pulser with 100pF injection capacitance, 10pe injected– SiPM illuminated with laser pulse, 10pe measured– Threshold from 1pe to 9pe• Petiroc bandwidth meas. : 877MHz with pulser• With SiPm: limitation due to the stray inductance

L/R

RC
Q/Cd

21 apr 2015

CdLT SiGe ROC ASICs KEK seminar

C=100 pF
L=10 nH
R=50 Ω
43

PETIROC2••••

32 ch SiPM GHz readout ASIC, dual polarity, 100 fC-400 pC, 6 mW/ch
32 trigger outputs and multiplexed data output
Embedded 10 bit ADC and 50 ps TDC
Dual threshold : first photons and energy

CdLT SiGe ROC ASICs KEK seminar

44

PETIROC2: Input DAC uniformity•

Linearity and dispersion of the 32 8-bit input DAC
Slope dispersion 75 uV rms or 2% rms

Intercept dispersion 6 mV rms or 0.6 % rms

CdLT SiGe ROC ASICs KEK seminar

45

PETIROC2: « S-curves »•Trigger efficiency measurements:

CdLT SiGe ROC ASICs KEK seminar

46

PETIROC2: efficiency uniformity••

Trigger efficiency measurements: Linearity
One 10-bit DAC Unit= 923 µV

10-bit DAC linearity
923µV/DAC code

CdLT SiGe ROC ASICs KEK seminar

47

PETIROC2: Time measurement••••

Jitter vs threshold & injection
Jitter improves with signal
Clock couplings (understood)
Jitter below 20ps

48
CdLT SiGe ROC ASICs KEK seminar

PETIROC2: TAC measurement•

TAC

Slope dispersion:~1% rms or 10ps/1ns
or 250ps/25ns=> Calibration

Due to digital coupling
Intercept dispersion:~1% rms => Calibration

Non Lin: ~0.25% or ±50ps

49
CdLT SiGe ROC ASICs KEK seminar

ZJ, a commercially available system that has already been tested in the hybrid PET/MR environment will b
tegrated
the PET/MR european
system proposed project
here. System integration will take care of synchronisation of th
The into
TRIMAGEree modalities and the display of the data from them. As noted earlier, the integration of all of three modalities
ET, MR and EEG is per se a demanded step forward in this field. A design of the proposed integrated instrumen• Cost effective tri-modality (PET – MR – EEG) imaging tools
presented in Fig. 5.

12

Project Partners

Role in the project

University of Pisa (UNIPI)

Coordinator & PET systemdevelopment

Technological Educational
Institute of Athens (TEIA)

Dissemination & Monte
Carlo simulations

Forschungszentrum JuelichGmbH (FZJ)

Coil design & PET/MR/EEG
integration

JARA BRAIN, RWTH (JRB)

Clinical application

Technische Universitat
Munich (TUM)

Image quantification &clinical application
Patient recruitment &50

of Zurich(PUK)(left) and artistic view (right) of the dedicated brain PET/M R/EEG system (the EEG cap is not
Fig.University
5: Dimensional
outlineclinical data analysis
shown).
Istituto Nazionale di Fisica
Nucleare (INFN)PET system development &characterization

AdvanSiD (ASD)

SiPMs and chip-scale
package development

Weeroc (WRC)PET modules production &testing

Raytest GmbH (RAY)

Mechanical parts design &market strategy

RS2D (RS2D)

Design, assembly, test 1.5T
MRI
CdLT SiGe ROC ASICs KEK seminar

TRIROC• 64-channel SiPM readout : positive & negative polarity inputs• 8-bit Input DAC for SiPM HV tuning• Time Stamp and ADC charge outputs

CdLT SiGe ROC ASICs KEK seminar

51

Technology transfer• Several chips transfered to other academic users• Non-profit « academic price »• Industry transfer via startup « WEEROC »
chip

year

IN2P3 users

external users
NEVIS, KEK, CERN, Roma, Seoul, Pisa,
Bari, Genève, Mocow, Valencia, Kolkata,Durham, Bruxelles, München, Jülich,
Valparaiso, Lisboa, Bristol, Frascatti,
Budapest, Catania, Glasgow, Coimbra,
Grenoble

MAROC3

2010

LAL, APC, CSNSM

HARDROC2BSPIROC2BSKIROC2SPACIROC1

2010
2010
2010
2010

IPNL, LPCCF
LAL, LLR
APC, LAL

EASIROC2010

IMNC, LAL, LLR,

PARISROC2

2010

IPNO, LAPP, LLR, APC

CITIROC2013

PETIROC2

2013

IPNL, LPCCF
CdLT SiGe ROC ASICs KEK seminar

DESY (D), TOHOKU (JP), Bergen (N)
IHEPPalermo, FNAL, KEK, München, Dijon,
CERN, Roma, Aachen, Toulouse, Lyon,
Seoul, Bari, Tokyo, Pusan, Kyushu, Osaka
IHEP
INAF, CERN, JLAB, Rio, Berne, Mendoza,
Aachen
KEK, Tohoku
52

Production Run : Feb 2015
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

MAROC3A
PHOTOROC (MAROC4)
HARDROC3B (RPC)
SPIROC2D(SiPM)SKIROC2B (Si PIN)
CATIROC (PARISROC3)PETIROC2ASPACIROC3A
CITIROC1ACITIROC1B
EASIROC1B
DOSIROC1ADOPIROC2
TRIROC1AMICROROC (µMEGAS)

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Evolution of SiGe for HEP• Motivation :– SiGe 0,35µm getting outdated– Particularly for digital part too slow

• AIDA2020 EU proposal– Microelectronics workpackage tostudy 130/180 nm SiGe process– Proposed consortium to shareexpertise on SiGe
– Study for LHC run 2, ILC…

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Conclusion• SiGe is an interesting technology for high speed, lowpower, large dynamic range readout chips• A large family of ROC ASICs has been realized by
OMEGA over the last 10 years in AMS SiGe 350 nm.
They are used by many groups and available forresearch.
• A new SiGe 130nm is now being investigated within
AIDA2020 EU program to enhance analog and digital
performance of SoC

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SUMMARY

http://omega.in2p3.fr/ http://www.weeroc.com/

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Backup slides•

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Summary• Main activity : Analog and mixed-signal ASIC design• Research topics :– multi-channel ASICs for particle physics and astrophysics detectors– BiCMOS SiGe and deep submicron CMOS technologies– ultra-low noise, low power and high speed design– radiation tolerance, reliability and space applications– integration with sensors and System on Chip (SoC)– chips for photodetectors, semiconductors or gaseous detectors• Specific Applications :– medical imaging– low light "single photon" imaging– utilization in space
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CALICE = « imaging calorimetry »• Calorimeter readout: auto-trigger, analog
storage, digitization and token-ring readout…
• power pulsing : <1 % duty cycle• Optimized commonalities within EUDET/AIDA

HARDROC2SDHCAL RPC
64 ch 16 mm2

SKIROC2ECAL Si
64 ch. 70 mm2

SPIROC2AHCAL SiPM
36 ch 30 mm2
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HARDROC2 for RPC readout•

HARDROC2: 64 channels (RPC DHCAL)
–
–
–
–
–
–
–

preamp + shaper+ 3 discris (semi digital readout)
Auto trigger on 10fC up to 20 pC
5 0.5 Kbytes memories to store 127 events
Full power pulsing => 7.5 µW/ch
Fully integrated ILC sequential readout
10 000 chips produced to equip 400 000 ch
SDHCAL technological proto with 40 layers (5760 HR2 chips) built in 2010-2011.
• Successful TB in 2012 : 40 layers with Power Pulsing mode
Cosmic hadronic shower
X

X

Y

Z

Y

Blue : 150 fC
Green : 2 pC
Red : 18 pC

Z

@IPNL

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Variant: MICROROCMICROROC: 64 channels forµMegas (DHCAL ILC)

0 fC

 Very similar to HARDROC except
for the input preamp (collaboration
with LAPP Annecy) and shapers (100150 ns)

1 fC

 Noise: 0.2fC Cd=80 pF => Autotrigger on 1fC up to 500fC

2 fC

 Pulsed power: 10 µW/ch (0.5 %duty cycle)@LAPP Annecy

 HV sparks protection
 1 m2 in TB in August and October
2011. Very good performance of theelectronics and detector (Threshold
set to 1fC).

 2012: 4 m2 in TB
1m2 equipped with 144 MICROROC
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SKIROC : SiECAL chip
• 64 ch Si readout chip
– Autotrigger @ ½ MIP = 2 fC
– Charge measurement 15 bits
– Time measurement 1 ns

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