Advanced technology for
ILC Calorimeters
Readout and DAQ parts
NANNI Jérôme
Electronics engineer
Laboratoire Leprince Ringuet (France)
KEK seminar
2017, December 12

Electronics challenges for ILC ECALDAQ introduction
Electronics development
Beam tests results
Next steps
Feeding others projects
nanni@llr.in2p3.fr - KEK seminar - 2017December122

Preview of prototypes

NEW
ELECTRONICS
DESIGN

2nd prototype
6 layers ~ 6k channels

1st prototype
30 layers ~ 10k channels
Proof of concept• Linearity• Resolution• Sensors• Very front-end

Feasibility of designoptionsConstruction• Compactness• Granularity• Front-end• Power pulsing• Long SLAB

• Integration• Environment• Services• Industrialization• Tooling• Project org.

Time

Last prototype
10 layers ~ 10k channels

nanni@llr.in2p3.fr - KEK seminar - 2017December123Introducing the DAQ
Calicoes
CCC board
Clock andControl
Card
ASU board
ActiveSensor Unitwafers

FEV board
Front EndBoard

GDCC board
Gigabyte Data Concentrator
Card

DIF board Dectector
InterFace

SMB board
Sweat Main Board

nanni@llr.in2p3.fr - KEK seminar - 2017December12

SLAB4Calicoes• Highly modular anddistributed• Control the Ecalelectronics but also theperipheral devices(Power supply, pulse
generator,…)• Provides a high levelstate machine for finaluser• Scripting language(Python)• Good stability
Global control-command architecturenanni@llr.in2p3.fr - KEK seminar - 2017December125

Calicoes

Load connectivity
Allocate memory
structures

Destroy memory
structures

Reset device
Load configuration
Configure devices
Synchronize clocks
Power on high voltage

Power off high voltage
Close connections

Start acquisition
signals

Stop acquisition signals
Flush files

Documentation: http://llr.in2p3.fr/sites/pyrame/calicoes/documentation/index.html
nanni@llr.in2p3.fr - KEK seminar - 2017December12

6

GDCC (Gigabyte Data Concentrator Card)
CCC (Clock and Control Card)
CCC Board
Able to connect 7 DIF-

Base on Xilinx Spartan XC6SLX75
Marvell component for Ethernet

FPGA
ETHERNETMARVELL

MCLK
TRIG

GEMAC

CCC
interface

Main
Interface(based onseveral
FSM)

DIFs
Links
(Protocolfsm
ser-des
8b/10b)

TO
DIF

-GDCC
nanni@llr.in2p3.fr - KEK seminar - 2017December12Until 8 HDMI connections
Synchronize all sub-systems
Distribute asynchronous
trigger/busy signals
Capable to distribute clock
50MHz7DIF (Detector InterFace to the DAQ)
Goal: connect the detector to control and
DAQ system by serial link synchronous to40MHz.
- Condition signals to VFE chips- Configuration- Readout- Generate clock 2.5MHz for ReadOut- Get information like board status,
firmware version …
Able to read several thousands of detector
channels up to 13000.
Able to read different chips for many
experiments in our laboratory.

nanni@llr.in2p3.fr - KEK seminar - 2017December128

SMB (Sweat Main Board)
Goal: condition signals for VFE
chips, power supply and clock
integrity.
FEV
connector

Regulator for
Analogue and Digital
power supply
DIF connector

Big capacitance (300mF) toabsorb the dynamic power
supply current, design for 1 ms
acquisition in the barrel.

Buffer to drive theclocks 40MHz and2.5MHz

nanni@llr.in2p3.fr - KEK seminar - 2017December129

FEV board (Front End Board)1024 pixels- Read energy of 1024 pixels- Slow Control for 16 Skiroc2- Readout for 2 partitions of 8 chips- 2 power supply (analogue & digital)- 16 layers
Pedestal

FEV board (bottom view)
MIP

Glued wafers

16 Skiroc2 chip
FEV board (top view)
nanni@llr.in2p3.fr - KEK seminar - 2017December1210

Skiroc chip
SKIROC: Silicon Kalorimeter Integrated Read Out Chip
- SILICON SENSORS (325µmthick) : 26000e-/MIP- Cdetector estimated 9pF +10pF for PCB pad’s- PIN diode leakage up to10nA / channel- Ultra low power
consumption (to Minimizecooling)  25 µW/ch with
Full Power Pulsing- 1 MIP = 4fC- 64 channels- 250 pads
- Technology: AMS SiGe 0.35µm- Size: 65mm²- Very low noise: 2500e- (0.4fC)- Dynamic range: 0.4fC  10pC

nanni@llr.in2p3.fr - KEK seminar - 2017December1211

Skiroc chip
Fast shaper noise studies

Scurves vs threshold

Preamplifier DC level uniformity

rms noise= 5.3 mV ie 1/9 MIP  S/N>9

DC PreAmplifier SKIROC2
2,02

2,01

2

1,99

DC (V)

1,98

1,97

Pedestal=167 DAC Units
1 Mip ≈4 fC = 20 DAC Units
Noise= 2 DAC Units

1,96

1,95<>=1.969 V
rms=1.5 mV

1,94

1,93

1,920

102030405060

Channelnanni@llr.in2p3.fr - KEK seminar - 2017December1212

First tests of ASU bench
There is a specific bench to test FEV board before
gluing.
Possibility to place a wafer, a mechanic interface andthe FEV board.
Goal: verify all chipanswered, pcb as noshortcut.
Also, it’s interesting toestimate noise on eachchip.
nanni@llr.in2p3.fr - KEK seminar - 2017December1213

Scurves, noisy channels
Instead activated all channel,
run 8 by 8.
Reduce effect of crosstalk.

Masked channel

Uniform noise around220-240uDAC.
Reproducible measure intime.
Number of hit

Number of hit

After masking channel

Trigger threshold
reduced.
Trigger (uDAC)

nanni@llr.in2p3.fr - KEK seminar - 2017December12

Trigger (uDAC)

14

Introduce short SLAB
Goal: first studies to improve design.
- Be able to detect a MIP (Minimum Ionization Particle)- Configure all chip compare to noise- Have adapted signals for clock and control- Get a S/N > 10
Aluminium cover- Read raw data in few ms.
FEV board (Front End Version)
Thermic layer (copper)

SMB board (Sweat Main Board)
DIF board (Detector InterFace)High Voltage kapton
Carbon structure in U
nanni@llr.in2p3.fr - KEK seminar - 2017December1215

Short SLAB
Get a final layer design include chips, PCB, wafer …
Thickness of electronics < 4mm (half alveolar size)
Kapton interconnector

HV connector
nanni@llr.in2p3.fr - KEK seminar - 2017December1216

Last prototype
Compact detector
Include up to 10 layers
Possibility to place Tungsten
between each layer
Connect each power supply by afront panel.
Auto-masking of noisy channels:
Every layers are adjusted inlaboratory with optimize scripts.
10 layers adjusted in 3h !!!
nanni@llr.in2p3.fr - KEK seminar - 2017December12

17

Test beam 2017 @DESY

Excellent results,
S/N~20 better
than 2015.
Pedestal position dispersion for all channels (~6 ADC)

S/N ratio for all SLABSS/N = 20 ; Dispersion = 7,8%

Concept is validate  next step LONG SLAB

Test beam performance presentation: https://indico.cern.ch/event/629521/contributions/2703010/
nanni@llr.in2p3.fr - KEK seminar - 2017December1218

Event Display

Compact shower+ “cosmic”
Shower(event layer/layer)
nanni@llr.in2p3.fr - KEK seminar - 2017December1219

ILD Slab (for final detector)
For ILD 8 to 12 ASU / layer  Layer length = 2.2 meters
Many challenges:- Interconnection solution- Kapton- Connector- Propagate signal on 3 meters- Clock (delay, load, attenuation, …)- Control signals- ReadOut (data integrity, amount of data)- Power distribution ?
- Power tree
- cross board- Mechanical structure- Design with minimize distortion- Weigh- Transportation
nanni@llr.in2p3.fr - KEK seminar - 2017December1220

ILD Slab (for final detector)
12 ASU full equipped of wafer 120k€
Need to make physics with less costUse mini wafer (4x4 pixels instead of16x16)

Alpha source put under thelong slab for physics

Scurves analysis for baby wafer
glue on long slab

nanni@llr.in2p3.fr - KEK seminar - 2017December1221

ILD Slab (for final detector)
New mechanical structure,able to receive 12 ASU
 Total length 3mSystem to place ASU onstructure with 3d printed
nanni@llr.in2p3.fr - KEK seminar - 2017December1222

CALICE TO WAGASCILocation: J-PARK neutrino beam, JAPAN
Physics goal: Cross section ratio measurement
between H2O/CH for charged-current interaction
with different Neutrino energy ranges.

40 MPPC
40 ASU
2 DIF
nanni@llr.in2p3.fr - KEK seminar - 2017December1223

CALICE TO HGCAL CMS
DIF board
SMB+FEV board

Base on Calice design:
GDCC board
2 pcb layers- read out: 4 chip
SKIROC2cms, 4x32 channels- FPGA: ALTERA MAX10- sensor (200µm, 6” siliconwafer)nanni@llr.in2p3.fr - KEK seminar - 2017December1224

Summary Electronics and instrumentation department of LLR develop many prototypes(conception, production and tests), with high technology and good performances.
The results of ILD Slab in the next test beam will shows the ability to instrument
2.2 meters active layer (readout, clock, power, data integrity, …).
 LLR DAQ is generic and adapt for many experiments, local, international(HGCAL CMS) and with Japan (T2K WAGASCI) on innovative and complex
projects of detector.
 LLR able to solve Electronics, DAQ, instrumentation Challenges, in a context ofinternational project with R&D phase, tests definition, proposal solutions. …

nanni@llr.in2p3.fr - KEK seminar - 2017December1225