Total Dose Effects
for 0.15µm FD-SOI CMOS Transistors
Y. Ikegami1, Y. Arai1, K. Hara2, M. Hazumi1, H. Ikeda3,H. Ishino4, T. Kohriki1, H. Miyake2, A. Mochizuki2,
S. Terada1, T. Tsuboyama1, Y. Unno1
1IPNS, KEK, Tsukuba, Ibaraki, Japan
2Inst. for Pure and Applied Sciences, University of Tsukuba,Tsukuba, Ibaraki, Japan
3ISAS, JAXA, Kanagawa, Japan
4Department of Physics, Tokyo Institute of Technology,Tokyo, Japan
2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

1Motivation• The silicon-on-insulator (SOI) CMOS technology has a number ofadvantages over the standard bulk CMOS technology, such as no latchup effect, high speed and low power dissipation.
• A monolithic pixel detector featuring of these advantages is being
developed under KEK Detector Technology Project.
• The fully depleted SOI (FD-SOI) CMOS technology provided by OKI
Electric Industry Co., Ltd. is realizing the full features of the advantages.
• High radiation tolerance is expected, since the devices are fabricatedusing a very thin silicon layer.
• We investigated the total dose effects for transistors fabricated using the
OKI 0.15µm FD-SOI CMOS process.

2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

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OKI 0.15µm FD-SOI Transistor parameters
VthGate OxideThickness

VoltageTolerance

Low VT (LVT)
For analog~ 0.2V

2.5nm<1V

High VT (HVT)
For logic~ 0.4V

2.5nm

<1VIO
For I/O~ 0.5V

5.0nm

<1.5V

Buried Oxide: 200 nm thickHandle wafer: 650 µm thick (SOITEC)
Backside Thinned to 350 µm, and plated with Al (200 nm)
Body Control : floating body and body tie
Body is connected with source in the body tie transistor.

2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

3Transistor TEG
L/W=
0.14/280

L/W=
0.2/400

L/W=
0.3/600

L/W=
0.5/1000

Low VT

Floating+ Body Tie

Body Tie

Floating+ Body Tie

Body Tie

High VT

Floating+ Body Tie

Body Tie

Floating+ Body Tie

Body Tie

Floating+ Body Tie

Floating+ Body Tie

IO

16 NMOS and 16 PMOS transistors
W/L ratio is fixed to 2000.
Sources were connected together in the TEG.
Gates were connected together andDrains are selected by relays on a test PC board.

2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

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Irradiation• Tohoku Univ. Cyclotron and Radioisotpoe Center (CYRIC)• 70 MeV proton• Beam profile
x~15mm y~16mm• Al Collimator
Φ10mm x 30mm (length)• Scan15mm x 15mm (TrTEG size :5mm x 5mm)
• The fluence was calculated later by measuring the Na24 productfrom the Al foil attached toeach TEG chip.
• All terminals were shorted using conductive sponge.
Expected
1MeV n-eq/cm2protoncurrent[nA]

Irradiationtime[min.]Measured
proton/cm2

Measured
1MeV n-eq/cm2

Ionizationdose toSiO2# of chips

1014

20

21

4.5x1013

6.4x1013

54 K Gy

1 chip

1015

200

21

4.0x1014

5.8x1014

0.49 M Gy

1 chip

1016

400

105

3.8x1015

5.5x1015

4.7M Gy

1 chipTotal 3 TrTEG s
2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

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Ids-Vgs Characteristics
1.E-03

1.E-03

Vds=0.5V

8.E-04

6E13
6E14
6E15
pre6.E-04∆VT @ Ids=500µA
4.E-04Ids [A]

8.E-04Ids [A]

Vds=0.5V
6E13
6E14
6E15
pre6.E-04

4.E-04

2.E-04

2.E-040.E+000.E+00
00.2

0.4

0.6

0.8

-1

1-0.8

1.E-02

1.E-02

1.E-03

1.E-03

1.E-04

1.E-04

1.E-05

1.E-05
6E13
6E14
6E15
pre1.E-06

Typical NMOS
Low VT
L/W=0.14/280
Floating Body

1.E-07
1.E-08
1.E-09
1.E-101.E-11

Ids [A]Ids [A]Vgs [V]-0.6-0.4
Vgs [V]

-0.2

0

6E13
6E14
6E15
pre1.E-06

Typical PMOS
Low VTL/W=0.14/280
Floating Body

1.E-07
1.E-08
1.E-09
1.E-101.E-11
1.E-12

1.E-1200.2

0.40.6Vgs [V]

2007/11/01 Y.Ikegami, KEK

0.8

1-1-0.8-0.6-0.4
Vgs [V]IEEE Nuclear Science Symposium N44-6, Hawaii

-0.2

06

VT shift (Dose dependence)
PMOS VT shift00-0.1-0.1
ΔVT [V]

ΔVT [V]NMOS VT shift

-0.2
-0.3
-0.4-0.2
LVT
HVT
IO
-0.3

LVT
HVTIO

-0.4-0.5
1E+13

1E+14
1E+151 MeV n-eq/cm2

L/W = 0.14/280
for LVT, HVT= 0.30/600
for IO
Body : Floating

1E+16-0.5
1E+13

1E+14
1E+15
1 MeV n-eq/cm2

1E+16A voltage reference is defined by Vgs, where Ids=500µA.
∆VT=Vgs after irradiation – Vgs before irradiation∆VT=-0.13 ~ -0.12 V for NMOS LVT=-0.21 ~ -0.16 V for NMOS HVT=-0.44 ~ -0.29 V for NMOS IO=-0.16 ~ -0.11 V for PMOS LVT=-0.08 ~ -0.06 V for PMOS HVT=< -0.5 ~ -0.20 V for PMOS IO

2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

7VT shift (gate length dependence)
VT shift (5.8E14 1MeV n-eq/cm2)
0

ΔVT [V]-0.1
NMOS LVTNMOS HVTNMOS IOPMOS LVTPMOS HVTPMOS IO-0.2-0.3

VT shifts slightly increased
as gate lengths became
longer, except LVT NMOS.

-0.4

Table shows∆VTmax – ∆VTminwith different gate lengths.

-0.5
0200
400
gate length [nm]

600

Dose
[1MeV n-eq/cm2 ]

NMOS
LVT

NMOS
HVTNMOSIO

PMOS
LVTPMOS
HVT

PMOS
IO6.4x1013

182821321210

5.8x1014

519203212105.5x1015

3525181816

2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

Unit [mV]8VT shift (Body Tie effect)
NMOS VT shift

PMOS VT shift00-0.2

ΔVT [V]

ΔVT [V]

-0.1

-0.3
-0.4
-0.5
1.00E+131.00E+141.00E+151 MeV n-eq/cm2

1.00E+16-0.1
LVT F
LVT T
HVT F
-0.2
HVT T
IO F
IO T-0.3-0.4
1.00E+13

LVT F
LVT T
HVT F
HVT T
IO FIO T

1.00E+14
1.00E+15
1 MeV n-eq/cm2

VT shifts of body tie transistors were slightly larger.
Table shows ΔVT(Body Tie) – ΔVT(Floating).

1.00E+16

F :Floating Body Tr.
T :Body Tie Tr.

Dose[1MeV n-eq/cm2 ]

NMOS
LVT

NMOS
HVT

NMOS
IO

PMOS
LVT

PMOS
HVT

PMOS
IO

6.4x1013

34143

5

15

5.8x1014

4

9

5

11

16

16

5.5x1015

1212523

2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

Unit [mV]9Back gate compensationgatesource1.E-02drain+++++++++++++

Ids [A]

8.E-03
VBG=0V
VBG=20V
VBG=40V
pre

6.E-03
4.E-03buried oxide
Silicon substrate

2.E-030.E+00
00.2

0.4
0.6
0.8
1Vgs [V]
NMOS BG compensation (LVT L/W=0.14/280 Floating Body)

VBG

1.E-02
1.E-03Ids [A]

1.E-04

VBG=0V
VBG=20V
VBG=40V
pre

1.E-05
1.E-06
1.E-07

In order to reduce large VT shift, compensationby the back gate voltage is investigated.
This figure shows the Ids-Vgs characteristics oftypical NMOS transistor for some back gatevoltages (Low VT; L/W=0.14/280; Floating) .

1.E-08
00.2

0.4
0.6
Vgs [V]

0.8

2007/11/01 Y.Ikegami, KEK

1IEEE Nuclear Science Symposium N44-6, Hawaii

10Back Gate Compensation Voltage
A voltage reference is defined by Vgs, where Ids=500µA.
∆VT=Vgs after irradiation – Vgs before irradiation
A back gate compensation voltage is defined by VBG, where ∆VT=0V.
Back Gate Compensation Voltage

Back Gate Voltage [V]6050
NMOS LVTNMOS HVTNMOS IOPMOS LVTPMOS HVTPMOS IO

4030201001E+131E+141E+151 MeV n-eq/cm2

2007/11/01 Y.Ikegami, KEK

1E+16Dose [1MeV n-eq/cm2 ]VBG [V]∆ VBG [V]6.4x1013

6 ~ 19135.8x1014

18 ~ 35

175.5x1015

34 ~ 53

19

IEEE Nuclear Science Symposium N44-6, Hawaii

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Back Gate Compensation (VT shift)
NMOS VT shift after compensation

PMOS VT shift after compensation

0.2

0.2

Compensated Tr.

0.1

0ΔVT [V]

ΔVT [V]

0.1

-0.1
-0.2

LVT0
HVTIO-0.1

LVT
HVTIO

-0.2-0.3
1E+131E+141E+151 MeV n-eq/cm2

1E+16-0.3
1E+1 3

1E+14
1E+151 MeV n-eq/cm2

1E+16When LVT (L/W=0.14/280; Floating Body) w/o bias condition was compensatedby its VBG, VT shifts for other type transistors were investigated.
∆VT=-0.08 ~ -0.04 V for NMOS HVT=-0.16 ~ -0.01 V for NMOS IO=-0.05 ~ +0.06 V for PMOS LVT=+0.01~ + 0.08 V for PMOS HVT=< -0.5 ~ +0.06 V for PMOS IO
2007/11/01 Y.Ikegami, KEKIEEE Nuclear Science Symposium N44-6, Hawaii

12Summary•Irradiation tests up to 5.5x1015 p/cm2 for OKI SOI MOS transistors
were performed.

•

Maximum threshold shifts were found to be∆VT = -0.13V for NMOS (LVT)∆VT = -0.19V for NMOS (HVT)∆VT = -0.44V for NMOS (IO)
∆VT = -0.14V for PMOS (LVT)∆VT = -0.08V for PMOS (HVT)∆VT > -0.5Vfor PMOS (IO)•

Minor difference (~20mV) was found in different gate length.

•

Minor difference was (~9mV) found in different body tie structure•

Compensation with biasing back gate worked effective in recoveryof radiation damage.

2007/11/01 Y.Ikegami, KEK

IEEE Nuclear Science Symposium N44-6, Hawaii

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