AGH University of Science and Technology
Doctoral Thesis

Development of monolithic pixel detectors

Author:
mgr inż. Szymon Bugiel

Supervisor:
prof. dr hab. inż. Marek Idzik
dr inż. Tomasz Fiutowski

Faculty or Physics and Applied Computer Science
Department of Particle Interactions and Detection Techniques

August 12, 2019

iii

Declaration of Authorship
Declaration of the author of this dissertation:
Aware of legal responsibility for making untrue statements I hereby declare that I have written
this dissertation myself and all the contents of the dissertation have been obtained by legalmeans.

Sign:
Date:

Declaration of the dissertation Supervisors:
This dissertation is ready to be reviewed.

Sign:
Date:

v

Abstract
Szymon Bugiel
Development of monolithic pixel detectors

The main goal of the presented thesis was the research and development on the capabilitiesof the Lapis 200 nm SOI (Silicon-On-Insulator) technology in terms of its usage for the designof monolithic detectors. In the SOI structure a thin silicon layer, dedicated for the electronic
circuitry implementation, is separated from the handling wafer by an insulator layer. Since forthe handling wafer a highly resistive silicon can be used, it may be directly used as a sensing
element. The researches were aimed to broaden the existing knowledge of the SOI monolithic
detectors behaviour by designing and characterizing different detector prototypes.
The studies began with the measurements of INTPIX6 detector prototypes which area large area integrating type pixel detectors, suitable for imaging applications, developed by
the Japanese group from KEK (The High Energy Accelerator Research Organization). The
prototypes fabricated on different handling wafers have been investigated and all have shown
very good energy resolution with the equivalent noise charge (ENC) on the level of 70 e− . They
have also proved good imaging capabilities sharply reproducing small 100 µm wide details of
the photographed structures. The measurements of INTPIX6 detector have also revealed themain weakness of the SOI technology that is a poor radiation hardness. The selected device has
been irradiated up to 60 krad dose, but its performance has started to significantly deteriorate
after exceeding 25 krad.
Further research covered not only the measurements of different monolithic detector prototypes, but have been extended also to their design as well as the preparation of the appropriate
measurement setup. Several different detectors have been developed by the Cracow group andthe two most meaningful are presented in this thesis.
The first one is a general purpose pixel detector designed to get familiar with the technology,
test different readout architectures and sensor geometries. Various measurements performed
with different radiation sources (from soft X-rays to MIPs (minimum ionizing particles)) allowed for the full characterisation of that device. The studies comprised also the comparison of
the standard SOI structure with its modification called the Double SOI. The detailed analysis
of gathered data revealed a strong dependence of the readout circuitry performance from thesubstrate structure and sensor geometry, which provided an important guidance for future
designs. This detector also showed a good energy resolution with the ENC of about 100 e−
for the best case, but its main advantage was an excellent spatial resolution reaching 2.1 µm,
with the 30 µm × 30 µm pixels.

vi
The second presented device is CLIPS (CLIC pixel SOI) detector, which is targeting therequirements of the CLIC (Compact Linear Collider) vertex detector. Besides a precise position
reconstruction it has to provide also the ToA (Time-of-Arrival) timing information. This
device has been designed and is already fabricated, but its measurements have not yet started.
Currently, a dedicated readout system is under preparation and the measurements are foreseenin the nearest future. Nevertheless, basing on the simulation results presented in this thesis
one can expect the spatial resolution below 3 µm, obtained with the sensor thinned down to150 µm and the ToA accuracy on the order of several nanoseconds.
All of the presented measurement results and their comparison with the simulations provide
a broad overview of the Lapis SOI process capabilities in terms of its usage for the monolithic
detectors fabrication. The performed studies show a high potential of presented technology
for applications in high energy physics experiments, as well as for imaging purposes.

vii

Abstrakt
Szymon Bugiel
Development of monolithic pixel detectors

Głównym celem przedstawionej pracy były badania możliwości oferowanych przez technologię Lapis 200 nm SOI (Silicon-On-Insulator) w kontekście jej wykorzystania do produkcji
monolitycznych pikselowych detektorów promieniowania jonizującego. Istotą tego rozwiązania
jest wykorzystanie wafla krzemowego, który zawiera cienką warstwę krzemu dedykowaną pod
elektronikę, oddzieloną izolatorem od podłoża. Podłoże, które może być wykonane z użyciem
wysokorezystywnego krzemu, stanowi zarazem element detekcyjny. Przeprowadzone badania
miały na celu poszerzenie obecnej wiedzy na temat zachowania detektorów wyprodukowanych
w technologii SOI, poprzez badanie właściwości wyprodukowanych prototypów jak i projektowanie nowych.
Prace badawcze rozpoczęły się od pomiarów detektorów z rodziny INTPIX6. Są to wielkopowierzchniowe detektory pikselowe pracujące w trybie całkującym, odpowiednie do zastosowań w obrazowaniu. Są one rozwijane przez japońską grupę naukowców z KEK (The HighEnergy Accelerator Research Organization) w Tsukubie. Pomiary kilku prototypów wyprodukowanych z wykorzystaniem różnych podłoży pokazały, że detektory te charakteryzują
się wysoką rozdzielczośią energetyczną, potwierdzoną przez ekwiwalentny ładunek szumowy(ENC) na poziomie 70 e− . Wyniki pomiarów wskazują również na ich wysokie predyspozycje do wykorzystania w obrazowaniu. Bez trudu rekonstruowały one detale fotografowanych
struktur o rozmiarach rzędu 100 µm. Badania prowadzone z wykorzystaniem tych detektorów
pokazały także największą słabość technologii SOI, jaką niewątpliwie jest słaba odporność radiacyjna. Jeden z prototypów napromieniowany został dawką około 60 krad, a jego właściwości
zaczęły się znacząco pogarszać już po przekroczeniu 25 krad.
Dalsze badania dotyczyły nie tylko pomiarów kolejnych prototypów detektorów, lecz także
ich projektowania oraz przygotowywania dedykowanej infrastruktury pomiarowej. Krakowska
grupa, w której skład wchodzi autor niniejszej pracy, przygotowała kilka własnych prototypów,
z których dwa najbardziej znaczące w kontekście tematyki tej pracy zostały szczegółowo przedstawione.
Pierwszym z nich jest detektor, którego projekt miał na celu zaznajomienie sie z technologią
Lapis 200 nm SOI CMOS oraz przetestowanie różnych architektur odczytu detektora oraz geometrii sensorów. Szczegółowe pomiary tego detektora przeprowadzone z wykorzystaniemróżnych typów promieniowania jonizującego (począwszy od miękkiego promieniowania X aż
po cząstki minimalnie jonizujące) pozwoliły na jego pełną charakteryzację. Przeprowadzone

viii
badania dotyczyły również porównania działania prototypów wyprodukowanych na różnych
podłożach, czyli standardowej struktury SOI oraz jej modyfikacji zwanej Double SOI. Analiza
zebranych danych wskazała na silną zależność pomiędzy zachowaniem elektroniki odczytu,a użytym podłożem, jak i geometrią sensora. Zebrane informacje pozwoliły na wypracowanie szeregu rozwiązań mających na celu zminimalizowanie negatywnego wpływu sensora na
elektronikę. Wyniki pomiarów wskazują, że zaproponowany detektor cechuje się rozdzielczością energetyczną wyrażoną ekwiwalentnym ładunkiem szumowym na poziomie 100 e− .
Jego szczególną zaletą jest znakomita rozdzielczość przestrzenna, sięgająca 2.1 µm przy rozmiarach piksela 30 µm × 30 µm.
Kolejnym z przedstawionych układów jest detektor pikselowy o nazwie CLIPS (CLIC pixel
SOI), który zaprojektowany został z myślą o potencjalnym wykorzystaniu w układzie detekcji
wierzchołka w przyszłym zderzaczu liniowym CLIC. W tym wypadku wymagane było przygotowanie detektora potrafiącego nie tylko precyzyjnie wyznaczyć pozycję przechodzącej cząstki,
ale także czas jej przybycia. Detektor został już wyprodukowany i obecnie przygotowywany
jest dedykowany układ pomiarowy, który pozwoli na rozpoczęcie pomiarów. Niemniej jednak,
wyniki symulacji wskazują na to, że można oczekiwać rozdzielczości przestrzennej poniżej
3 µm i dokładności pomiaru czasu rzędu pojedynczych nanosekund, uwzględniając pocienienie
detektora do 150 µm.
Wyniki pomiarów oraz symulacji prezentowanych w niniejszej pracy pozwoliły uzyskać
szeroki wgląd w potencjał technologii SOI w kontekście zastosowania jej do produkcji monolitycznych detektorów pikselowych. Przeprowadzone badania wskazują jednoznacznie na wysoki
potencjał użytej technologii zarówno dla eksperymentów fizyki wysokich energii, jak i dla zastosowań w obrazowaniu.

ix

Acknowledgements
The completion of my dissertation has been made possible through valuable assistance, support
and guidance that I have received from many people to whom I feel myself obliged to pay mysincere gratitudes.
First of all, I would like to thank my supervisor Marek Idzik for his constant motivationand time spent on discussions, as well as for all the opportunities that allowed me to broaden
my horizons. I would also like to thank my supervisor and co-supervisor Tomasz Fiutowski,
for the time they spent on revising this manuscript.
Furthermore, I am also thankful to other colleagues from the Nuclear Electronics andRadiation Detection Group: Krzysztof Świentek, Jakub Moroń and Mirosław Firlej for theshared knowledge and experience. Here, I would also like to thank Przemysław Terlecki for
the invaluable help and day-and-night technical assistance.
In addition, during the PhD studies I have been privileged to collaborate with many great
people, mostly from CLICdp and KEK communities. I am deeply thankful for all the support
provided during test-beams. It is difficult to mention everyone here, but it has been a great
pleasure to work with you.
Most importantly, I have offer my heartfelt gratitude to You, Roma. Without your support
this dissertation would probably never arose. I would also like to thank you for all the things
you did for me and which I don’t even know about.
Finally, I would thank my parents, for all the support they provided to me, but especiallyfor leaving me a free hand in all the choices that I had to made.
This work was financed by the European Union Horizon 2020 Marie Sklodowska-Curie Research and Innovation Staff Exchange program under Grant Agreement no. 645479 (E-JADE)
and also by the Polish Ministry of Science and Higher Education from funds for science in theyears 2017 – 2018 allocated to an international co-financed project.

xiContents
Declaration of Authorshipiii

Abstractv

Abstraktvii

Acknowledgements

ix

Introductionxvii

1 Basics of radiation detectors

1

1.1

Historical outline of semiconductor radiation sensors . . . . . . . . . . . . . . .

1

1.2

Basic principles of semiconductor sensors. . . . . . . . . . . . . . . . . . . . .

4

1.2.1

pn-junction as a sensor. . . . . . . . . . . . . . . . . . . . . . . . . . .

4

1.2.2

Interaction of particles with matter . . . . . . . . . . . . . . . . . . . . .

8Charged particles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8Photons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

Signal formation – Shockley-Ramo theorem . . . . . . . . . . . . . . . .

12Basics of monolithic detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13

1.3.1

Monolithic versus hybrid solutions . . . . . . . . . . . . . . . . . . . . .

13

1.3.2

Available technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

DEPFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14High Voltage CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14High Resistivity CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

Silicon-On-Insulator CMOS . . . . . . . . . . . . . . . . . . . . . . . . .

16

1.2.3
1.3

2 Silicon-On-Insulator technology

19

2.1

General overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

2.2

Wafer preparation methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

2.3

SOI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

2.3.1

Partially-Depleted and Fully-Depleted SOI . . . . . . . . . . . . . . . .

21

2.3.2

Kink effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

2.3.3

History effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

2.3.4

Subthreshold swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

2.3.5

Device parameters mismatch . . . . . . . . . . . . . . . . . . . . . . . .

24

2.3.6

Back-gate effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

2.3.7

Radiation hardness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

xii
2.4

Double SOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

2.5

Lapis Semiconductor process . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

3 INTPIX6 detector studies

31

3.1

INTPIX6 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31

3.2

Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32

3.3

Data processing and analysis flow . . . . . . . . . . . . . . . . . . . . . . . . . .

34

3.4

Measurements results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40

3.5

Detector calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40

3.6

Noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

44

3.7

Studies of radiation hardness . . . . . . . . . . . . . . . . . . . . . . . . . . . .

45

3.8

INTPIX6 imaging capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48

3.9

INTPIX6 results summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

50

4 SOI detector prototype for general studies
4.1

51

Design overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

52

4.1.1

Pixels architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

Source-follower architecture . . . . . . . . . . . . . . . . . . . . . . . . .

53

Charge-sensitive pre-amplifier architecture . . . . . . . . . . . . . . . . .

54

Feedback capacitance in CPA . . . . . . . . . . . . . . . . . . . . . . . .

55

Switches in CPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

58

Column amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

60

4.2

Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

62

4.3

Measurements setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

65

4.3.1

Data acquisition software . . . . . . . . . . . . . . . . . . . . . . . . . .

66

4.4

Data analysis software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

68

4.5

Spotted issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

69

4.6

Radioactive source measurements . . . . . . . . . . . . . . . . . . . . . . . . . .

71

4.6.1

Energy resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

78

Spatial resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

80

4.1.2

4.7

5 CLIPS detector design

83

5.1

CLIPS detector overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

84

5.2

Pixel design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

84

5.2.1

Pre-amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

85

5.2.2

Baseline adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

86

5.2.3

Charge measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

87

5.2.4

Discriminator and Time-of-Arrival measurement . . . . . . . . . . . . .

88

5.3

Readout control and periphery circuitry . . . . . . . . . . . . . . . . . . . . . .

92

5.4

Matrix variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

93

5.4.1

Sensor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

93

5.4.2

Feedback circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

94

Current status and future intentions . . . . . . . . . . . . . . . . . . . . . . . .

96

5.5

xiii
Conclusions

97

A Additional plots for INTPIX6 FZ(n) detector

99

Bibliography

101

xv

List of Abbreviations
ASIC

Application-Specific Integrated Circuit

ADC

Analog to Digital Converter

ADU

Analog to Digital converter Units

BNL

Brookhaven National Laboratory

BNW

Buried N-Well

BPW

Buried P-Well

BOX

Buried OXide

BSOIBond Silicon On Insulator

CCD

Charge Coupled Device

CERN

The European Organization for Nuclear Research

CDS

Correlated Double Sampling

CMFB

Common Mode FeedBack

CMOS

Complementary Metal-Oxide Semiconductor

CLIC

Compact Linear Collider

CLIPS

CLIC Pixel SOI

CPACharge-sensitive Pre-Amplifier

CZ(n)Czochralski type n

DAC

Digital to Analog Converter

DAQ

Data AcQuisitionDC

Direct Current

DRC

Design Rule Check

DSOI

Double SOI

DUT

Device Under Test

ENC

Equivalent Noise Charge

ELO

Epitaxial Layer Overgrowth

ELT

Enclosed Layout Transistor

ELTRAN

Epitaxial Layer TRANsfer

FC

Folded Cascode

FD-SOI

Fully-Depleted SOIFPGA

Field-Programmable Gate ArrayFZ(n)Floating Zone type nFZ(p)Floating Zone type pGUI

Graphical User Interface

HEP

High Energy Physics

HL-LHC

High-Luminosity Large Hadron Collider

xvi
HR-CMOSHigh-Resistivity CMOS

HVHigh Voltage

HV-CMOSHigh-Voltage CMOS

I/O

Input/Output

ILC

International Linear Collider

INTPIX

INTegration type PIXels

KEK

The High Energy Accelerator Research Organization

LHC

Large Hadron Collider

LDD

Lightly Dopped Drain

MIP

Minimum Ionizing Particle

MIP

Metal Insulator Metal

MPV

Most Probable ValuenMOSn-channel MOSFET

PD-SOI

Partially-Depleted SOI

PCB

Printed Circuit Board

pMOS

p-channel MOSFET

R&D

Research and Development

RFC

Recycling Folded Cascode

RHIC

Relativistic Heavy Ion Collider

RMS

Root Mean Square

ROI

Region Of Interest

SEABASSOI EvAluation BoArd with SiTcp

SEE

Single Event Effects

SEU

Single Event Upset

SET

Single Event TransientSF

Source Follower

SIMOX

Separation by Implementation of OXygen

SNR

Signal to Noise Ratio

SOI

Silicon-On-Insulator

SOS

Silicon-On-Sapphire

TCP/IP

Transmission Control Protocol/Internet Protocol

TID

Total Ionizing Dose

ToATime of Arrival

UDP

User Datagram Protocol

VHDCI

Very-High-Density Cable Interconnect

VLSI

Very Large Scale of Integration

xvii

Introduction
The growing demands on the performance of the detection systems for the high energy physics
experiments, medical imaging, as well as for commercial applications, force the continuous
development of the detector technologies. This allows to overcome the existing limitations (inexample on detector segmentation) and ensures the constant technology upgrading. In termsof the tracking detectors, presently the standard solution are hybrid pixels detectors thatare widely used in particle physics experiments. In this approach the readout electronics isfabricated independently from the sensor and those two components are connected using the
bump-bonding technique. Unfortunately, such solution introduces a lot of “non-active” material into the whole detection system. The existence of that additional material highly increases
the probability of Coulomb scattering of the measured particles, which directly deteriorates
the measurement precision. Moreover, physical dimensions of the bumps are limiting the granularity of the device. For these reasons, the requirements for the future detection systems haverecently started to exceed the capabilities of the hybrid detectors.
Fortunately, there is an alternative solution to the hybrid devices, namely the monolithic
pixel detectors. For this type of devices the readout electronics is implemented on the same
wafer as the sensing matrix. This solution allows to overcome the limitations of the hybrid
detectors, but its implementation is technologically challenging. There are several different
approaches for the monolithic detectors fabrication, each having its own strong and weak
points that have to be taken into account when considering its application.
This thesis is fully devoted to the development of the monolithic detectors utilizing the
Silicon-On-Insulator (SOI) technology. On the top of the SOI structure there is a thin siliconlayer dedicated for the electronics implementation. This layer is electrically separated fromthe handling wafer by an insulator layer, which allows to use the existing silicon substrate asa radiation sensitive element. The goal of this thesis was the research and development on
the monolithic pixel detectors fabricated in the Lapis 200 nm SOI CMOS technology. The
work was aimed to verify its capabilities in terms of the usage for ionizing radiation detection,
mainly for the future high energy experiments. Thus, the researches were aimed to estimate
noise performance of different SOI detector prototypes, verify theirs imaging potential andthe spatial resolution, as well as test theirs radiation hardness. For that purpose, not onlya precise characterisation of several detectors was needed, but also a direct comparison of theiroperation with the simulations.
The core of this thesis is comprised of two chapters providing the essential theoretical background followed by three chapters devoted to different detector prototypes characterisation.
The whole work is summarized in the final part with conclusion. Chapter 1 begins with a shorthistorical introduction into the topic of semiconductor radiation detectors. After that a basic

xviiiworking principles of semiconductor sensors are presented. The next chapter is fully devoted
to the description of the Lapis 200 nm SOI CMOS technology. It describes different methodsof SOI wafers production and shows all main features of the SOI structure. In chapter 3 thecharacterization of the first detector prototype is presented. The studies have been performed
with the INTPIX6 – a large area, integrating type pixel detector, suitable for imaging applications, which was developed by the Japanese group from KEK. Its measurements were focusedon the estimation of the energy resolution as well as its imaging capabilities.
Beside the INTPIX6, there are two another detectors presented in this thesis. These were
fully developed by the Cracow group and author of this thesis was one of theirs main designer.
First device is introduced in chapter 4. It is a general purpose detector aimed for tests ofdifferent readout architectures as well as different sensor geometries. It has been precisely
characterized thanks to the complete set of lab measurements and tests with the particle
beam.
The second prototype is the CLIPS detector presented in chapter 5. It was designed to fulfil
the requirements of the CLIC vertex detector. Its measurements have not yet been performed,
but a detailed description of its architecture together with the simulation results are presented.
The conclusions summarize the obtained results remaining the most meaningful outcomes
and also give on overview on future works being a continuation of studies presented in thisthesis.

1

Chapter 1

Basics of radiation detectors
1.1

Historical outline of semiconductor radiation sensors

The history of semiconductor nuclear detectors has began in 1943. At that time it was alreadyknown that “some kind of solids” namely crystals are sensitive to the light due to the photoelectric effect. P.J. van Heerden concluded that they could also be sensitive to the ionizing
particles (α, β and γ). He performed an experiment in which 4 mm thick AgCl crystal withsilver contacts was cooled down by liquid air. The high voltage was applied and the sensor wasconnected to two stage tube amplifier. Finally, the signal induced in crystal (or semiconductor
using contemporary language) by ionising particles was observed on cathode ray oscillograph.
The obtained dataset was precise enough to calculate the energy needed to generate an electron–hole pair in AgCl to be 7.6 eV and the bandgap energy of 3.2 eV [1], which is in good
agreement with later measurements.
Shortly after that, in the early 1950s, the germanium detectors were developed in Bell
Telephone Laboratories by Kenneth McKay. Germanium was chosen because at that time it
was already possible to produce large single crystals of known properties and because of its
similarities to diamond. This time it was already a pn-junction created by a germanium rod,
half n-type and half p-type, reversely biased and exposed to α particles. With this setup anenergy loss of α particle per electron-hole pair creation of 3.04 eV was measured [2].
Few years later, when the silicon monocrystals became available, different groups havestarted the development of the silicon nuclear detectors. Two approaches were investigated inparallel, devices based on evaporated gold surface barriers and a pn-junction [3]. At that time
the silicon devices started to be very interesting for nuclear physics experiments. In comparison
to the available gaseous detectors they had offered extremely short response times, convenientphysical dimensions, insensitivity to magnetic fields together with excellent energy resolution(due to around ten times lower electron-hole pair creation energy).
The growing interest and continues improvement of technology resulted in a rapid development of the silicon detectors. Already in year 1961, the first segmented detector was fabricatedby Dearnaley [4]. It contained three separate surface barrier counters evaporated on a single
silicon wafer (as showin in Fig. 1.1A).
At the same time there was a demand for large area detectors able to provide not only
the energy but also position information. An example of such system built for heavy ion
Coulomb excitation, shown in Fig. 1.1B, worked at Yale University and was constructed by

2

Chapter 1. Basics of radiation detectors(A) Triple semiconductor surface barrier
detector.

(B) Large area parallel semiconductor mosaic detector.

Figure 1.1: Examples of pioneering silicon detectors from the early 1960s(pictures from [4]).

J. S. Greenberg [4]. It was a mosaic of 32 individual, 1 cm2 large, silicon detectors arranged in
an array with a dedicated readout for each channel. Therefore, it can be treated as a precursorof today’s pixel detectors.
Next, in 1969, the concept of a single detector providing 2D spatial information had been
introduced, the Charge Coupled Device (CCD) proposed by W. Boyle and G. Smith [5]. This
invention had a huge impact on digital imaging technology. CCD’s had dominated the digital
camera market and were, and still are, widely used in medicine and scientific applications,because they could provide an excellent signal to noise ratio together with the large area
coverage. The CCD invention was found to be so important that in 2009 Boyle and Smith
were awarded the Nobel Prize for Physics. In spite of that, CCD’s at that time were notsuitable for particle physics experiments because of too small signal from minimum ionizing
particles (due to very shallow depletion).
In the early 1970’s few groups around the world had been developing the strip sensors whichwere much more suitable for particle physics experiments. For example, in 1971 a group fromKarlsruhe reported [6] the strip silicon detector providing angular information together withenergy information. In their device one side of the sensor was segmented into 5 or 12 strips
by using a thin-wire mask during the gold evaporation, whereas the second side was fully
covered with aluminium. In contrast to the today’s solutions the segmented side provided
only the information about the position while the energy was measured by a common channel
connected to the aluminium electrode.
The first usage of silicon detector as a tracking device was in 1981 dictated by the willingnessof observation of the short living mesons containing charm quark. Their predicted live-times
were of an order of 0.1 ps (corresponding to decay lengths cτ ∼ 30 µm), so the fast and precise
devices were needed. Therefore, NA11 and NA32 experiments at CERN have installed planesof silicon strip detectors located close to the interaction point, for precise tracking and vertex
reconstruction. It was also a time when silicon detectors have started to gain profits from theplanar technology development for the integrated circuits production. By using the planar1.1. Historical outline of semiconductor radiation sensors

3

process it became possible to design much more fine and precise sensor geometries.
The successful operation of the NA11 and NA32 experiments proved the high capabilities ofsilicon sensors for the precise track and vertex reconstruction in a high particle multiplicity environment, therefore they started to dominate all the high energy physics (HEP) experiments.
But with the constantly increasing multiplicities the problem with proper signal assignment
from strips had grown. Thus, there was a high demand for a two-dimensional detector [7].
Finally in year 1983, group from the Rutherford Laboratory reported the successful usage of
the CCD for ionizing particles tracking [8] with a 12.7 mm by 8.5 mm large matrix of 576 times
385 pixels with a pitch of 22 µm. The depletion thickness was only 8 µm, but the detection was
still possible thanks to limiting the dark current by cooling the sensor down to 120 K. Even
with the signal of only 1300 electrons the device showed very good performance of a pointing
resolution of 4.3 µm in X direction and 6.1 µm in Y, with the efficiency on the level of 98 %.
This kind of the detectors were later used in NA32 experiment in the vertex telescope.
In the next years the progress of the technology allowed for the continuous development of
the detectors with more compact readouts thanks to the VLSI (Very Large Scale of Integration)
electronics, but the real milestone was made in 1990’s, when hybrid pixel detectors appearedin the HEP experiments [9]. Similar to the CCD’s they allowed for two dimensional tracking,but in addition they overcome the main limitation of CCD’s which was the long readout time.
From that time pixel detectors have became almost obligatory part of the innermost tracking
system and started to gradually replace strip detectors [1, 10].
Together with the hybridization concept another approach towards pixelization has been
introduced – monolithic detectors. It was an idea of integrating the readout electronics andthe detector on the same wafer. Since both of them are made of silicon it seems to be a natural
solution, but there are few technical difficulties that have to be overcome. To allow a large
depletion depths of a sensor a high resistivity wafers are needed, which are not a typicalsolution for the electronics production. First successful attempts were performed already inearly 1990’s [11]. Later on, this kind of detectors have started to gradually supersede the
CCD’s from the digital cameras market and currently they are the most widely used solution
for a visible light imaging.
Despite of their success in commercial market, currently operating particle physics experiments use almost only hybrid pixel detectors, which is mainly caused by theirs high radiation
hardness. Only recently, in year 2014, STAR experiment at the Relativistic Heavy Ion Collider(RHIC) at the Brookhaven National Laboratory (BNL) has installed a first large-scale tracking device based on monolithic detectors [12]. For the future, post-LHC experiments, manymonolithic solutions are being considered, since it seems to be the only solution allowing fora further material budget reduction while the technology starts to be mature enough to deal
with the high radiation.

4

Chapter 1. Basics of radiation detectors

1.2

Basic principles of semiconductor sensors

Silicon is the second most abundant element in the Earth’s crust (about 28 % by mass) after
oxygen (about 47 %), but it very rarely occurs in the pure form. It mainly exists in various forms of silica (silicon dioxide) or silicates. Silicate minerals are the main rock-forming
materials that make up around 90 % of the Earth’s crust.
In case of pure silicon there are two allotropic forms that exist at room temperature,amorphous and crystalline. Amorphous silicon appears as a brown powder while crystalline
one has a greyish, metallic color. For the first time the crystalline silicon was prepared byHenri Deville in 1854, but large monocrystals became widely available after year 1915 when
Czochralski process was introduced.
The physical properties of silicon qualify it as a semiconductor with an energy gap between
the valence and conduction bands of about 1.12 eV at the room temperature. In its crystal
form it has a face-centred cubic lattice structure (the same as diamond), with a lattice constantof 5.34 Å.

1.2.1

pn-junction as a sensor

Silicon wafers are often used as radiation sensors, but even in an intrinsic, pure crystal structure, there are about 1010 free charge carriers per cubic centimetre [13], whereas the numberof electrons induced by an ionising particle is in the order of 104 . It is obvious that in suchconditions the signal from the passing particle would be lost. Therefore, there is a need for themechanism allowing a significant reduction of free charges. In principle there are two solutions
to achieve that. First, it can be done by cooling down the sensor to reduce the probability ofthermal excitation of electron to the conduction band. But since a cryogenic temperatures areneeded it is not a convenient method especially for a large scale applications. Therefore thesecond solution, which is based on a pn-junction, is much more popular.
To control the conductivity of a semiconductor a small fraction of impurities can be introduced into a silicon lattice (with typical concentrations between 1012 and 1019 cm−3 ). This
process is called doping and depending on what kind of the additional element is used, thesilicon can be n or p doped. In n-type silicon the introduced impurities comes from V-thgroup of the periodic table (most commonly it is Phosphorus) providing extra electrons to thelattice. Therefore, they are often termed as donors. The excessive electrons are not tightly
bound with the atom so they form an additional energy band located close to the conduction
band. The energy gap differs for different doping atoms, but usually the difference is so smallthat these spare electrons have enough thermal energy to easily transfer into conduction band.
On the other hand, when the impurities come from III-rd group (mainly Boron) the deficiency of electrons appears. This kind of dopant is therefore often called as acceptor. In termsof a band theory an additional energy level is introduced just above the valence band, closeenough for thermal excitations of valance electrons. The configurations of the valence electrons
in the pure and doped silicon are schematically shown in Fig. 1.2.
At the first glance, introducing a doping into the silicon only affects its conductivity (resistivity). But its real potential reveals after connecting a p-type and n-type regions, forming

5

1.2. Basic principles of semiconductor sensors

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

P

Si

Si

B

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

(A) Pure silicon.

(B) n doped silicon.

(C) p doped silicon.

Figure 1.2: Electronic configurations of the valence electrons in pure and doped
silicon lattice. Excessive and missing electrons are marked with filled and empty
red circles respectively.

a pn-junction. In such a case an excess of the electrons from the n doped side can freely
diffuse into a p doped side and fill out the holes. After moving out of the n-type side electrons
are leaving there uncovered positively charged ions. Similarly on the p-type side, the additional electrons occupying the holes generate an uncompensated negative space charge. The
existence of this space charge on both sides results in the build-up of an electric field acrossthe junction, which acts against the carriers exchange. At some point an equilibrium state isreached when the electric field is large enough to stop further migration. Therefore, in thesteady state three regions can be distinguished: p doped side, n doped side and between thema region without free charge carriers – depletion region (as sketched in Fig. 1.3). Its worth tonotice, that the reduction of free charges was needed to use the silicon as a radiation sensor
and that is exactly what is happening within the depletion region.
qNd

ρ(x)
-dp

Depleted region
-qNa

E(x)

-dp

0

dn

0

dn

x

x
p+
(Na)

Φ(x)

n+
(Nd)
-dp

0

dn

Vbi
x

-dp

0

dn

x

Figure 1.3: Sketch of a pn-junction and corresponding distributions of spacecharge ρ(x), electric field E (x), and build-in potential φ(x). Uncovered, positively and negatively charged ions are marked with squares and rhombuses
respectively.

The size of the depletion region and the electric field across the junction depends on thedoping concentration of both sides and can be calculated assuming that all dopant atoms are
ionized within the depletion region.

6

Chapter 1. Basics of radiation detectors
The electric field E (x) can be obtained using the Gauss law:dE (x)
ρ(x)
=
dx
0 r

(1.1)

where ρ(x) is space charge distribution, 0 and r are respectively vacuum permittivity andrelative permittivity. Since in the depletion region there are no free charges the space charge
distribution is formed only by uniformly distributed dopant ions. Because of the charge conservation:
qNd dn = qNa dp
where:
q–electron charge,

Na–

acceptor concentration,

Nd–donor concentration,

dp–

depletion depth on acceptor side,dn–

depletion depth on donor side.

(1.2)

Assuming the junction at x = 0 with p-type doping on the left side and n-type doping on
the right side (as presented in Fig. 1.3), the space charge can be expressed as:(

ρ(x) =−qNa for x ∈ (−dp : 0)qNd

for x ∈ (0 : dn )(1.3)

After applying to Eq. 1.1 and performing integration:
for x ∈ (−dp : 0)

( −qN

a

E (x) =

0 r (x + dp )qNd
0 r (x − dn )for x ∈ (0 : dn )(1.4)

To get the distribution of the build-in potential φ(x) one more integration is needed. Therefore,taking as a boundary condition φ(x = 0) = 0, one gets:( qN

φ(x) =

a 1 2
0 r ( 2 x + xdp )−qNd 1 20 r ( 2 x − xdn )for x ∈ (−dp : 0)for x ∈ (0 : dn )(1.5)

The build-in voltage (Vbi ) across the junction can be calculated as:
Vbi = φ(dn ) − φ(−dp ) =q(Nd d2n + Na d2p )20 r

(1.6)

Finally, the relation for the total depletion depth D = dn + dp may be obtained from Eq. 1.2
and Eq. 1.6:sD=

20 r Nd + Na
Vbi
q
Nd Na

(1.7)

Since the build-in voltage in silicon is around 0.6 - 0.7 V the self-created depletion region usually7

1.2. Basic principles of semiconductor sensors

spreads only across several dozen micrometers. However, by applying an external voltage tothe junction its width may be changed: shorten for a forward bias and widen for a reverse
bias. Since for the radiation sensor the larger the depletion region is the better, let us consider
the second option. By applying the negative voltage to the p side and positive to the n side
more electrons are forced to leave the n side, leaving unbalanced donor ions. And vice versa
in the p type part, which straightforwardly leads to the extension of the volume without freecharges. Since all the mechanisms leading to build-up the depletion region are the same as
in derivation above, the equation 1.7 for the total depletion depth can by simply adopted byintroducing an additional variable corresponding to the external bias voltage Vbias .
sD=

20 r Nd + Na
(Vbi + Vbias )
q
Nd Na

(1.8)

As it was already mentioned, the signal can be extracted from the silicon devoid of free charges.
Therefore, in most applications the depletion of the whole sensor volume is desired. For thatreason a highly asymmetrical (in the sense of dopings) junctions are often used. Following theequation 1.2 it is clear that having a Na  Nd (or Nd  Na ) the depletion range towards
n-doped side (or p-doped side respectively) will be much larger than to the opposite. That is
why the sensors are usually made of very lightly doped wafers (either p or n type) with thetypical concentrations on the order of 1012 to 1014 atoms per cubic centimeter and shallow
highly doped implants of the type opposite to the wafer on the top side.
An often used sensor parameter is a full depletion voltage VF D which is the minimum voltage that provides depletion across the whole sensor thickness. It can be directly extracted fromequation 1.8, assuming certain detector thickness Ddet and neglecting the build-in potential
which is typically orders of magnitude lower than the external bias voltage:
VF D =q
Nd Na
D2
20 r Nd + Na det(1.9)

Having in mind the condition of high asymmetry in the doping concentration, the highly doped
factor can be cancelled out leaving only a term connected with the wafer doping concentration
Nw (Nw = Nd for n-type wafer or Nw = Na for p-type):
VF D 'q2
Nw Ddet20 r

(1.10)

1
It can be further written in terms of wafer resistivity ρ = qµN
as:w

VF D '

2Ddet
20 r µρ(1.11)

where µ is electron mobility in silicon (µe ∼ 1350 cm2 V−1 s−1 ) for n-type wafer or holemobility (µh ∼ 450 cm2 V−1 s−1 ) for p-type one [3]. Furthermore, a simplified formula for the
depletion depth can be written as:D'

20 r µρVbias

p(1.12)

8

Chapter 1. Basics of radiation detectors

Now its clearly visible that the higher the wafer resistivity is the easier the depletion develops,
so its very desired to have it as high as possible. Moreover, it may happen that with the low
resistive wafer the full depletion voltage can be higher than the breakdown voltage making thefull-depletion impossible. Therefore, depending on the sensor bias voltage, a detector may operate in three different conditions: under-depletion (Vbias < VF D ), full-depletion (Vbias = VF D )and over-depletion (Vbias > VF D ). The electric field distribution inside the wafer is:

E (x) =


2Vbiasx D (1 + D )for x ∈ (0 : D )for x ∈ (0 : DF D ) − over-depletion

2VF D
x
DF D (1 + DF D )Vbias −VF D
2VF DxDF D (1 + DF D ) +DF D− under-depletion

for x ∈ (0 : DF D ) − full-depletion(1.13)To achieve the possibility of position measurement a top implants are usually segmented into
strips (providing one-dimensional information) or into pixels (for two-dimensional measurement). Therefore, each of these segments creates a separate pn-junction and allow for an
independent measurement. The distance between the strips or pixels centers is usually called
the pitch. The lower the pitch is the finer the segmentation, allowing for more precise measurement.
Another very important sensor parameter directly connected with the segmentation is thesensing node capacitance CD . Since the depletion region acts same as a plate capacitor withthe silicon as a dielectric, one can define:
CD =


q
 0 r S =for Vbias ≤ VF D

for Vbias > VF DSiD
2ρµVbias
0 r SDF D = const(1.14)

where, S is the “plate” area which corresponds to the area of strip or pixel implant size. One
has to notice that this formula takes into account only the capacitance created between thesensing node and the back plane of the detector. In some particular situations also othercomponents (for example capacitance between the neighbouring strips/pixels) may not be
negligible.

1.2.2

Interaction of particles with matter

There are several mechanisms by which a particle may interact with a sensor while passing
through its volume, but the most significant are the electromagnetic interactions. The signal
formation inside a sensor volume highly depends on the incident particle type, its energy ormass. Fortunately, all different cases can be categorized into few groups, that have to bestudied separately.
Charged particles
All charged particles may interact electromagnetically either with the electrons or with theatoms nuclei, which will lead to change of theirs energy and movement direction. Nevertheless,the interactions with the nucleus are highly suppressed by the low cross-section, so in thefirst order only the interactions with the shell electrons have to be considered. The incident

91.2. Basic principles of semiconductor sensors

particle mass has also significant impact on the interaction dynamics, therefore light lepton
beams (electrons and positrons) have to be studied separately. All the other charged hadronic
particles and heavy leptons may be studied together since their mass is at least two orders ofmagnitude higher than electron mass.
In general, there are two main processes that lead to the energy transfer between theincident particle and the sensor volume, the ionization and the radiative losses. The radiative
looses correspond to the interactions of the moving charged particle with the electric field
inside a sensor, which can lead for example to the Bremsstrahlung photons emission or theelectron-positron pairs creation. For high mass particles this phenomena occurs only at very
high energies exceeding several hundred GeV. Therefore, ionization plays a dominant role inthe charge generation by theheavy charged particles.
D E
The mean energy lossdE
dxof a charged particle per distance travelled through the matteris described by the Bethe-Bloch formula [14]:dE−dx

1 2me c2 β 2 γ 2 Tmax
δ (βγ )ln
− β2 −
2
β A 2
I
2

z2 Z
= 4πNA re2 me c2 2

"

#





NA

–

Avogadro number,re–classical electron radius,me–rest mass of an electron,c–speed of light,z–charge of incident particle,

Z–

atomic number of the medium,A–

atomic mass of the medium,

β

–

γ

–

incident particle velocity (β = vc ),Lorentz factor (γ = √ 1 ),

Tmax

–

maximum kinetic energy that can be transferred in a single collision,I–mean excitation energy,δ (βγ )–

density correction.

where:(1.15)1−β 2Fig. 1.4 shows the Bethe-Bloch relation for three exemplary particles in different materials.
As one can see the overall function shape remains the same (especially for materials with
Z > 2) with slightly decreasing mean energy loss for heavier materials. The common feature
independent on the passing particle type and the medium is the rapid growth at low energies,
which leads to a high energy depositions just before stopping the passing particle. This iscommonly known as the Bragg peak. Another common feature is a shallow minimum atβγ ∼ 3. Particles with energies close to that minimum are often referred to be minimum
ionizing particles (MIP). Towards the higher energies the mean energy loss starts to growslightly due to increasing probability for radiative processes. A one can notice, scales for themuon and pion, which are very close in mass, are very similar, whereas for almost ten times
heavier proton the momentum scale is around one order of magnitude higher. Nevertheless,from the practical point of view, all heavy charged particles in high energy experiments are10

Chapter 1. Basics of radiation detectors

Figure 1.4: The mean energy loss in various materials presented for muons,pions and protons (figure from [14].)often treated as MIPs since theirs energies are high enough to place them in the plateau region,
where the differences in the mean energy loss are minor.
The only exception are the electrons (and positrons) mentioned before. For them theminimum appears slightly above 1 MeV and, what is most important, the radiative processes
start to dominate over the ionisation already around 20 MeV, which is still inside the observed
momentum range.
Ionisation across the passage of the incident particle is a stochastic process therefore thefluctuations of the energy loss appear, which is not described by the Bethe-Bloch formula. For
large energy depositions the fluctuations undergo normal distribution, but this is not the casefor a thin radiation sensor typically used in a particle physics experiments. For a thin detector
there is a limited number of high-energy transfer collisions, which result in an asymmetrictail towards higher values in the deposited energy distribution. There are few approaches to
describe this energy spectrum, but the most common is the Landau-Vavilov distribution thatcan successfully predict the most probable value (MPV) of the energy deposition (which is

11

1.2. Basic principles of semiconductor sensors
typically the value of interest) instead of mean value [14]:2me c2 β 2 γ 2ξ∆E = ξ ln+ ln + 0.2 − β 2 − δ (βγ )II"where:
ξ = 2πNA re2 me c2



Z
A



#

(1.16)x
β2

and x is moderate sensor thickness given in g cm−2 .
An example of energy loss spectrum for 500 MeV pions passing through the thin siliconlayers of different thickness is shown in Fig. 1.5, where the difference between the mean energy
loss and the most probable energy loss is clearly visible. Moreover, comparing the curves
obtained for different thicknesses one can directly spot the decreasing energy transfer per
micrometer for thin detectors.

f(ΔE/x)

ΔE/x

MPV

ΔE/x
Figure 1.5: Energy loss spectrum for thin silicon layers, normalized to unity
at the most probable value (figure from [14]).

Photons
The interaction of photons with matter looks completely different. Contrary to the charged
particles they do not loose their energy gradually along the travelled path. There are several
different processes through which photons can interact with matter but regardless of that they
are usually fully absorbed in a single interaction or at least they transfer a significant fractionof theirs energy.
For low energetic photons (ultraviolet or soft X-rays) with energies up to ∼10 keV, theinteraction is mainly dominated by the photoelectric effect. In this process an incident photon
interacts with an inner-shell electron bound in an atom. Its energy is fully transferred to the12Chapter 1. Basics of radiation detectors

electron which is knocked out of the atom, with the kinetic energy equal to the incident photon
energy reduced by the electron binding energy.
For hard X-rays, with energies from ∼100 keV up to 1 MeV the Compton effect dominates.
In this process the incident photon interacts with loosely bind electrons from the valence shell,
and its energy is only partially transferred. Therefore, after the interaction, beside the knocked
electron also a scattered photon remains, but its energy is usually highly decreased.
After exceeding 1 MeV, photon energy becomes large enough to unlock another process –pair production. In the vicinity of a nucleus the incoming photon may interact with its electricfield and convert into an electron-positron pair. The cross-section for all mentioned processes

Attenuation [cm2 g-1]

in the function of photon energy is shown in Fig. 1.6.

Energy [MeV]

Figure 1.6: Photon flux attenuation coefficient in the function of photon energy. Components from different processes drawn with different colours, whereas
a combined value is shown in black (figure from [15]).

1.2.3

Signal formation – Shockley-Ramo theorem

A common approach is to consider the carriers arriving to the collection electrode as a signal.
However, to properly describe the input signal one has to consider the current induced in thesensing node by the motion of the carriers in the electric field of the sensor. Thus to specify
the signal seen on the input of the readout electronics one has to follow the Shockley-Ramotheorem [16, 17]. It states that the current ik (t) induced by the k-th component Qk of thetotal charge is given by:−−→−i k ( t ) = Qk →vk (t) · Ewk (r )(1.17)−−→−
where →
vk (t) is velocity of the k-th charge component and Ewk (r ) is so called weighting field.

This is a hypothetical electric field at point r, that would be induced after removing Qk

13

1.3. Basics of monolithic detectors

charge from the sensor volume and after applying 1 V to the collecting electrode, with allother electrodes of the sensor grounded.
It has to be pointed out that this method converges with a naive approach, in the sensethat the total current signal integrated over the collection time is equal to the total chargecollected at the electrode.

1.3

Basics of monolithic detectors

1.3.1

Monolithic versus hybrid solutions

The idea of hybrid pixel detectors is a straightforward evolution of the concept known fromthe strip detectors, where a sensor and a readout electronics are fabricated separately andconnected afterwords by the wire-bonding. It is a simple and convenient method since boththe sensor and the electronics can be developed and optimized separately. Unfortunately, forthe pixel detectors the wire-bonding technique is no longer suitable because the number ofindividual channels becomes to large, but once a bump-bonding technique was developed, thesensor-readout interconnection was no longer a problem (as shown in Fig. 1.7A).

SensorReadout electronics

p+

Bumps

n+

n+

p

n+
n

p- (epi)p++ (substrate)

Electronics(A) Hybrid pixel detector.

(B) Monolithic detector.

Figure 1.7: Schemes of monolithic and hybrid detector.

The flexibility of the hybrid detectors caused their widespread use in many fields of sophisticated and demanding applications. On the other hand, even if the bump-bonding process isused from many years its yield is still not perfect, what highly increases the costs of hybrid
detectors. It is one of the reasons why a monolithic approach to the pixel detectors fabrication
is being considered. Since both the sensor and the electronics are made on silicon wafers it
is somehow natural to try to integrate them and fabricate together on the same wafer (asshown in Fig. 1.7B). Unfortunately, there are several issues that for many years successfully
prevented the utilization of monolithic devices. For example the sensing wafer is usually very
lightly doped (to allow its easy depletion), whereas for the electronics fabrication a relatively

14

Chapter 1. Basics of radiation detectors

highly doped wafers are used. Beside that, when both the sensor end the electronics are implemented in the same wafer, they start to interfere with each other, which also causes many
issues. Fortunately, after many years of the development and the evolution of the CMOS process, nowadays there are several different methods that allow for the fabrication of monolithic
pixel detectors. Of course they are not yet as mature as the hybrid devices, but they have juststarted showing theirs capabilities.

1.3.2

Available technologies

DEPFET
DEpleted P-channel Field Effect Transistor (DEPFET) detectors are based on the concept of
the FET transistor, which channel conductivity is controlled by an electric field. Schematic
view of the DEPFET structure, with the potential level across its depth is shown in Fig. 1.8.
Gate

Drain

RESET

p+

n+

p+

n+

V

SourcepInternal gate

n+

n
p+

x

Depletion zone

HV

Figure 1.8: Schematic of DEPFET detector structure on the n-type wafer,with the ionizing particle passing through its volume and a waveform showing
the electrostatic potential in function of the detector depth.

Its working principle is very simple. Once a charge is induced within a depleted sensing
volume the fields lines push the electrons towards the local potential maximum located at
the internal gate. The growing amount of electrons within the internal gate increases the
conductivity of the FET transistor, generating therefore the electric current proportional to
the gathered charge. The charges remain in the internal gate until the positive resetting pulse
appears, which attracts them to the reset electrode. The main advantage of this kind of
structure is that a single FET transistor may act as a sensor, an amplifier and a memory cell.
First devices based on DEPFET technology have been recently installed in the Belle II Vertex
Detector [18].
High Voltage CMOSHigh Voltage CMOS (HV-CMOS) technology is based on a standard CMOS process that has
been adopted in the way that one can bias the substrate with a high voltage. The scheme

15

1.3. Basics of monolithic detectors

showing the HV-CMOS detector structure is presented in Fig. 1.9. In this approach the whole
readout electronics is located in a large well that at the same time acts as the sensing node.
This solution ensures shielding of the electronics from the influence of high voltage applied tothe substrate, but on the other hand the size of the input node is determined by the complexityof the in-pixel electronics. Thus, in this solution there is a trade-off between the input nodecapacitance (determining the input noise) and the signal processing capabilities.
Incident particle

Input node

HV
n++

nMOS

pMOS

p+

n+

Deple
tio

n zonepp+

Figure 1.9: Schematic of HV-CMOS detector structure on the p-type wafer,with the ionizing particle passing through its volume.

One of the main advantages of this approach is definitely its similarity to the classical
CMOS structure. In principle it may be produced in any foundry offering multiple well CMOS
process, and so such devices can be widely available. Unfortunately, there are also several
quite important downsides. One of them is already mentioned trade-off between the readout
electronics complexity and the input capacitance. Another very important aspect is a major
problem with the full-depletion of this kind of devices, which not only reduces the input signal
but also may lead to detector inefficiency. Nevertheless, for some applications HV-CMOS
detectors may suit very well. For example they are being considered for the Mu3e experiment[19] or for the ATLAS Inner Tracker upgrade [20].
High Resistivity CMOS
The High Resistivity CMOS (HR-CMOS) detectors derive from a very similar approach as
the HV-CMOS devices. They are also fabricated in a standard CMOS technology, but slightly
modified to allow the substrate depletion. In contrary to the HV-CMOS, in HR-CMOS thereadout electronics is not placed within the sensing well, which overcomes one of the main
issues of the HV-CMOS. The sketch of the HR-CMOS detector is shown in Fig. 1.10.
In this kind of devices the electronics is placed in the well used for the sensor biasing,whereas the input node is formed by a small implantation of the opposite type to the substrate
doping. Moreover, such strategy has several repercussions. First of all it is beneficial in termsof the input capacitance reduction and thus allow for a very low-noise detectors fabrication.
But according to Fig. 1.10 one can see that in this approach the pn-junction is formed not only

16

Chapter 1. Basics of radiation detectors
Incident particle

Input node
HV

pMOS

nMOS

p++

P+

n+

De

pMOS
p+

p
zo leti
ne on

p
p+

Figure 1.10: Schematic of HR-CMOS detector structure on the p-type wafer,with the ionizing particle passing through its volume.

between the sensor bias (HV) and the input node, like in the previous solution. Here anotherpn-junction is also created between the sensor bias and the implemented electronics, which
results in a quite restrictive limitation on the maximum sensor bias voltage. In order to preventfrom the breakdowns the HV usually has to be kept below ∼ ±10 V. Unfortunately, low sensor
polarization voltage together with a small sensing implantation directly leads to a very small
depletion zone, which is the main disadvantage of this solution. In order to minimise thisissue one has to utilize a high resistive substrate, which allow for a broader depletion zone
development (and give the name of this technique). Nevertheless, even with the highly resistive
wafers it is very hard to force the depletion zone development below the wells containing theelectronics. Fortunately, several modifications of the doping plan have been proposed recently,that allow for the shallow depletion layer formation over the whole pixel area. This approachseems to be promising and it is developed by many groups. For example HR-CMOS detector
called ALIPDE is considered for the ALICE Inner Tracking System upgrade [21].
Silicon-On-Insulator CMOS
Another CMOS process that may be adopted for the monolithic detectors fabrication is the
Silicon-On-Insulator (SOI) CMOS. The schematic view of the SOI detector structure is presented in Fig 1.11. In this approach a thin silicon layer with electronics is being separated fromthe handling wafer (substrate) by an insulator. Originally it was aimed for the improvementof the circuitry performance, but it also gives a perfect opportunity for the monolithic detectors design. As shown in Fig 1.11 in the SOI detectors the sensor is formed by an pn-junction
implemented within the substrate, whereas the whole readout electronics is located just above.
In the SOI the handling wafer may have completely different characteristics than the silicon
dedicated for the electronics. Thus one can freely use a highly resistive substrates similar tothe ones used in the hybrid sensors and so there are no major problems with the full depletionof the entire substrate volume, even a thick one.

17

1.3. Basics of monolithic detectors

Since the SOI technology was the one that was exploited for the purpose of this thesis its
wider characterization is presented in the next section.

SiO2
p+

n

Depletion zonen+
HV

Figure 1.11: Schematic of SOI detector structure on the n-type wafer, with
the ionizing particle passing through its volume.

19

Chapter 2

Silicon-On-Insulator technology
2.1

General overview

The Silicon-On-Insulator (SOI) CMOS technology refers to the microelectronics manufacturingmethod where instead of a single crystal substrate wafer a more complex structure is used. The
SOI wafer consists of a thin single crystal silicon layer where the electronics is implemented,
separated from the handling wafer by an insulating layer (typically silicon dioxide or sapphire).
The SOI structure has been introduced to overcome the limitations encountered during
the continuous miniaturization of microelectronics devices. There are several benefits of using
the SOI wafer instead of a traditional bulk substrate:• reduction of the parasitic capacitances to the substrate,• latch-up immunity due to full isolation of n-well and p-well devices,• limitation of the leakage currents,• increased resistance to the Single Event Upsets induced by the ionizing radiation,• better wafer utilization thanks to higher component densities at the same technologynode.
All these advantages allow to increase the operation speed together with the reduction of
the power consumption, which is very desired especially for the complex digital circuitries.
Moreover, from the fabrication perspective, the SOI wafers are almost completely compatible with the standard CMOS production process. Therefore, many leading IC companies
decided to establish the SOI process for their high-end products. As an example, in the year
2000 IBM released their top microprocessor RS64-IV “Istar” fabricated on the SOI wafer. Also
AMD has began to manufacture their x86 architecture microprocessors on the SOI, startingfrom the single-core Opteron fabricated in 130 nm and its multi-core successors produced in
90 nm, 65 nm, 45 nm and 32 nm nodes. Thanks to the high-performance capabilities of the SOI
based processors many of the top supercomputers exploits the SOI microprocessors. For example the supercomputer called “Summit” at Oak Ridge National Laboratory, which currently is
the most powerful machine in the world (operating at 143 PFLOPS/s), exploits IBM POWER9processors manufactured in the 14 nm FinFET SOI technology. Also many of the commercial
gaming consoles, like XBOX 360, Play Station or Wii, contain processors fabricated on the
SOI wafers [22, 23].

20

Chapter 2. Silicon-On-Insulator technology
All those examples show how beneficial is the separation of the electronics from the sub-strate wafer in terms of the chip performance. But concerning the scope of this thesis themost important feature of the SOI wafer is the possibility to use a thick bottom silicon layer
as a radiation sensor with a readout electronics placed on top of it in thin silicon layer, andthus forming together a monolithic detector. Moreover, thanks to the fact that the top andthe bottom silicon layers in the SOI structure come from two different initial wafers, they
may have completely different electrical characteristics. The top layer can have relatively low
resistivity suitable for the electronics implementation, whereas for the bottom sensing parta high purity silicon can be used.

2.2

Wafer preparation methods

Over the years, many SOI wafer preparation methods have been developed. The first attempts
were made in 1960s, where instead of the silicon dioxide, a sapphire was used as an insulator.
In 1963 Harold Manasevit successfully prepared a Silicon-On-Sapphire (SOS) wafer utilizing
the epitaxial silicon growth over the single crystal sapphire layer. Currently, the SOS wafers
are still being prepared using this technique, but obtaining a high quality silicon layer is stilla challenge.
In early 70’s an alternative method based on the epitaxial lateral overgrowth (ELO) was
explored. In this approach holes are drilled in initially oxidized silicon wafer, which allows forthe lateral growth of the silicon through the hole and later on over the insulator layer. The
downside of this method is a substantial limitation on the area of the overgrowth.
The demand for the radiation-hard devices for space and military applications revealed in
the intensified interest in the SOI technology. Unfortunately, none of mentioned method was
suitable for the industrial scale production. The augmented effort for the evolution of the SOI
technologies contributed to the development of SIMOX process (Separation by IMplantationof OXygen), where an insulating silicon dioxide layer is introduced within a standard CMOS
wafer. This technique is based on the ion beam implantation. The oxygen ions are introduced
at certain depth and afterwards during the high temperature annealing form buried oxide(BOX) layer [24].
Later on several other SOI wafer preparation methods, suitable for mass-scale production,
were proposed. In contrary to SIMOX process they do not act on a single wafer, but utilizea direct bonding of two silicon wafers. The most widely used are BSOI (Bond Silicon-OnInsulator), Eltran and Smart Cut technologies, which became mature enough to provide the
SOI silicon quality comparable with the bulk silicon wafers.
The BSOI method was introduced in 1980s when several processes for the direct bondingof silicon wafers were developed. The BSOI process employs two initial silicon wafers. In thefirst step one of them is oxidized over its surface (by the thermal growth or a deposition),
which forms a BOX layer. Next, two wafers are bond together and annealed to enhance theconnection. Afterwords, one side is being grinded to the desired thickness which finishes the
SOI wafer fabrication [24].

2.3. SOI features

21

Eltran, which stands for Epitaxial Layer TRANsfer process was developed by Canon andis more cost-effective because it is non-destructive to the undesired silicon part (no grindingof almost whole wafer thickness as in BSOI is needed). The remains from one process can bereused later. Similarly to the BSOI technique the Eltran also utilizes two initial wafers. On
one of them a porous silicon layer is formed on its surface. Later on, a high quality epitaxial
layer is deployed on top of the porous layer. After that the BOX layer is formed by the thermaloxidation of the top part of the high quality epitaxial layer. Next, such a structure is bonded
to the second (handling) wafer. After the bonding, a separation is done along the mechanicallyweak, porous layer by applying a mechanical stress. The remaining porous layer is removed,
leaving only the high quality epitaxial layer on top of the SOI structure, whereas the second
part may be reused during the next iteration [24].
The most recent from the presented techniques, and particularly important concerning thescope of the presented thesis, is the Smart Cut technology, which was exploited for the wafer
production for all presented prototypes. The Smart Cut technique, being developed since
1993, is suitable for the large scale production, therefore it is relatively widely used for the
SOI wafer manufacturing. This approach is also based on the direct bonding of two wafers,
similar to BSOI and Eltran methods. The Smart Cut process flow is shown in Fig. 2.1. In
the first step the surface of one of the initial wafers is thermally oxidized. After that, lightions (like hydrogen or helium) are implanted through the oxide into the silicon, which leads
to the formation of mechanically weak surface at the certain depth of the wafer. Later onboth wafers are carefully cleaned and their surfaces are prepared for the wafer bonding. When
two wafers are bonded together the separation along the previously produced weakened surface
takes place. It may be carried out by heating the whole structure up to the temperature, when
the thermal energy is sufficient to initiate the splitting or by applying the mechanical force.
A final step is a standard conditioning treatment of created SOI structure, which includes
polishing of the surface and annealing that strengthen the bonding interface [24].
The leftover wafer part, which was split out off the SOI wafer, is also subjected to theconditioning treatment. The weakened volume is grinded, its surface is repolished and thewafer is suitable for use in the subsequent Smart Cut process as one of the initial wafers.

2.3

SOI features

There are many benefits of SOI CMOS, which have been already mentioned, but its utilization
is limited to the hi-end or very unconventional products. The main obstacle preventing thewidespread use of the SOI CMOS are still the wafer quality and higher costs. Moreover, despite
many similarities between the SOI and bulk CMOS process, there are several deferences thatneed to be taken into account during the SOI IC design.

2.3.1

Partially-Depleted and Fully-Depleted SOIApart from the wafer preparation method, there are two types of SOI CMOS processes:
Partially-Depleted (PD-SOI) and Fully-Depleted (FD-SOI). This terms refer to the relation
between the thickness of the top thin silicon layer and the thickness of channel depletion layer

22

Chapter 2. Silicon-On-Insulator technology

A

Wafer A oxidation

A
H+ ions

Introducing mechanicallyweak surface byion implantation

B

SiO2

A

"New" A or B wafer

Initial silicon wafers

A
Wafer bonding

B

Final conditioning(polishing/annealing/...)

A

Thermal/mechanicalsplittion along
weakend surface

B
SOI wafer

Figure 2.1: Sketch of the Smart Cut process flow.

after setting a device into the operating point. In the Partially-Depleted process the siliconlayer is thicker than the channel depth, whereas for the Fully-Depleted the channel is createdover the whole top silicon thickness. The process classification depends mainly on the siliconlayer thickness above the insulator and the doping concentration within the channel volume.
Typically, to obtain the Fully-Depleted SOI, the top silicon layer has to be thinned down toabout 100 nm or less. For example for 100 nm the transistor channel will spread over the wholesilicon volume with the channel doping concentrations corresponding to the threshold voltages
in the order of 300 − 400 mV. On the other hand, for 200 nm thick layer the doping should
be reduced to the level corresponding to threshold voltages below 100 mV, which is no longer
useful in practical applications [25].
There are several specific features of each process type that differ SOI CMOS from bulk
CMOS, which have to be taken into account during the design as well as the technology
characterization. For example one of the main drawback of the PD-SOI is the existence of thebody-like region below the channel. In standard CMOS the bulk potential is always set to the
fixed voltage, but in the SOI the undepleted body region remains floating which introduces
atypical behaviour of PD-SOI transistors.

23

2.3. SOI features

2.3.2

Kink effect

The most distinctive effect is called the kink effect [26] because it reveals as a kink in the
output characteristic (shown in Fig. 2.2A). To explain it let us consider nMOS transistor ina saturation mode, as shown in Fig. 2.2B. The electrons are flowing through the channel (ICh )to the region with a high electric field located close to the drain. In this region they areaccelerated enough to induce the impact ionization and therefore create additional electronhole pairs. The new electrons flow to the drain, whereas holes (IH ) flows towards the source.
But at the source contact they encounter a potential barrier (VBS ), therefore holes start toaccumulate within a body region. As the number of the gathered holes increases the bodypotential rises. The accumulation process stops when the body potential is high enough toallow the holes to flow to the source. At that point the system is in a balanced state where
a number of generated holes is equal to the number of holes able to flow to the source. But
since a certain number of holes is “trapped” within a body region, this causes the reduction

Drain current (ID)of a transistor threshold voltage and thus drain current increases.

VS

Without kink effectWith kink effect

VG
ChannelAvalanche
multiplication

ICh

ID

IHS
n

+

VBS

IH

IHB

p
Body

VD

n+
Depletion region

Drain-Source voltage (VDS)(A) Sketch of transistor output characteristic
showing the influence of kink effect.

(B) Sketch of the nMOS transistor showing theorigin of kink effect.

Figure 2.2: Kink effect.

2.3.3

History effectFormer mechanism refers rather to the analog applications, but it affects also a digital circuitry.
In digital applications the transistors analog characteristics are not necessarily concerned,
but they have a direct reflection in the transistor switching time which is a very importantparameter. Therefore, in the digital domain a similar mechanism reveals in issue called thehistory effect. This term refers to the transistors switching time dependence on its previous
state. Since the switching time is directly connected with the transistor threshold voltage,
its deviation leads to the excess of the timing uncertainty. On the other hand, for somespecific conditions (specified by the previous state), the history effect leads to the reductionof the switching time. Thus, it should be noticed that this issue is not necessarily bad. The
conscious usage of this feature may speed up an overall circuity performance.
To overcome all the floating-body effects, a separate contact may be introduced for the
body polarization (as in standard CMOS) or a build-in body connection with source may be
implemented within the transistor structure. Unfortunately, this solution makes the transistor

24

Chapter 2. Silicon-On-Insulator technology
technology
bulk CMOS
PD-SOI
FD-SOI
theoretical limitSS−th
85 − 90 mV/dec
80 − 85 mV/dec
65 − 70 mV/dec∼ 60 mV/dec

Table 2.1: Standard subthreshold swing values at room temperature for different technologies [25].

unit larger, which reduces the transistor density per area. Another solution is to use the
FD-SOI technology instead of PD where these effects are highly suppressed [24].

2.3.4Subthreshold swing

Another very important factor that enhances the usage of the SOI technology (especially
FD-SOI) over the bulk CMOS is a low value of a subthreshold swing SS−th [27]. It describes
the drain current behaviour at very low gate voltages and is usually defined as:
SS−th = ln(10) ·CkT(1 + dep )
q
Cox

(2.1)

where kT
q is a thermal voltage, Cdep is a depletion layer capacitance and Cox is a gate-oxide
capacitance.

Basically, SS−th parameter determines how much the gate voltage has to increase/decrease
to obtain ten times larger/smaller drain current. It is very important for the low voltage/low
power applications to keep it as close as possible to the theoretical limit. It is so, becausefrom one hand the transistor threshold voltage should be high to keep the leakage currents low(and therefore reduce the static power dissipation). On the other hand the lower the thresholdvoltage, the higher the speed. So having a low subthreshold swing it is possible to have a device
with a relatively low threshold voltage (∼200 mV) for high speed performance, but at the sametime keeping its off-current low. The typical values for different technologies together with thetheoretical limit determined by the thermal voltage are shown in Tab. 2.1 [25].

2.3.5

Device parameters mismatch

All features mentioned above show the predominance of the FD-SOI over the PD-SOI. However, there is one issue that affects the fully depleted structure more than the partially depleted
one. It is the sensitivity to the nonuniformities of the top silicon layer thickness. This imposesquite excessive requirements on the wafer quality because even a single nanometer variation of
the silicon layer thickness results in a threshold voltage shift of around 10 mV. Nevertheless,the wafer fabrication methods became more and more mature, which allows for a significant
suppression of the mismatch issue and a straightforward trend towards the FD-SOI is seen [24].

2.3.6

Back-gate effectBesides all the issues connected directly with the electronics fabricated on the SOI wafer, there
are also additional effects that come from an nonstandard application of SOI technology, such

25

2.3. SOI features

as the radiation detectors. As already mentioned to exploit the SOI structure as a monolithic
detector, an extra layers have to be implemented within handling wafer to form the sensing
diode. Its reverse bias allows to build-up the depletion zone. However, it has turned out thatthe sensor polarization voltage has a non-negligible impact also on the electronic circuitry
implemented on the top of the structure. Since the top silicon is separated from the sensor by
an insulator, applying a sensor bias voltage acts on transistor in the similar way as applying
a voltage to its gate. This issue has been called a back-gate effect. Of course the back-gate hasmuch lower impact than the standard gate because the thickness of the gate oxide is around
two orders of magnitude lower than the thickness of a buried oxide. Nevertheless, one has toremember that voltages applied to bias the sensor are usually also hundred times larger thantypical gate voltages. In practice, the influence of the sensor biasing voltage is clearly observedin the transistors characteristics, which in the extreme case may even lead to the constantly
switched on or off transistors, independently from theirs gate voltages.
Since this issue became critical in terms of the SOI monolithic detectors, a solution for thisproblem has to be found out. A simple way to eliminate the back-gate effect is shielding of theelectronics from the sensor electric field. The sensor electric field may be easily kept within
the handling wafer part by introducing an additional doping layer – a lightly doped buried
well located just beneath the oxide, p-type for the n-type substrate (BPW – Buried p-Well)
and n-type for the p-type one (BNW – Buried n-Well), as shown in Fig. 2.3. Applying a fixed
ground potential to this layer successfully eliminates the back-gate effect [28].
Such a solution works perfectly for the peripheral circuitry but it has also a negative impact
on the sensing part of the readout. In order not to lose the efficiency, the buried well can not
be directly biased by the fixed voltage because some part of the signal induced within a sensor
would flow into this node and therefore would be lost. Thus the only solution is to connect
the buried well directly with the sensing node. In this case the electronics is still shielded, theefficiency remains on the similar level but the capacitance of the sensing node is increased. This
has a direct impact on increased readout noise and may also deteriorate the signal amplitude(depending on the input stage architecture).

SiO2
BPW

n
n+
HV

Figure 2.3: Sketch of the SOI structure with a BPW layer used to shield thereadout electronics from the sensor bias voltage.

26

Chapter 2. Silicon-On-Insulator technology

2.3.7

Radiation hardness

Radiation hardness is another very important parameter that has to be concerned in terms ofsome specific areas of the SOI devices utilization (for example the military or aerospace applications). It is also one of a key limitations for the applications in highly radiative environmentsof high energy physics experiments.
There are two major categories of ionizing radiation related issues: Single Event Effects(SEE) and Total Ionization Dose (TID) effects. In general the first group covers all theimmediate consequences of the particle passage through the electronics, whereas the second
one deals with the long term device parameters modifications. Their influence on the SOI
wafer is schematically presented in Fig. 2.4.
The Single Event Effect occurs when a high energy particle or a gamma ray ionizes theelectronics active layer. The highly localized charge carriers created in the sensitive device
regions may cause an incorrect circuitry behaviour or can even lead to its irreversible damage.
Several types of the SEE can be distinguished according to the effects that they cause.
Probably the least harmful is the Single Event Transient (SET) which reveals as a fakesignal travelling through the circuitry. This effect may of course lead to a failure behaviour
but does not cause any permanent damage. After the fake signal has been propagated, theproper chip operation is restored.
Another type is the Single Event Upset (SEU) that corresponds to the change of the state
saved in the memory cell. The consequences of SEU are highly determined by the memory
cell purpose. It may have a minor consequence when for example some data storage cell isharmed, but on the other hand when a control bit is flipped the chip operation can be switched
into an improper mode or even stopped. Nevertheless, SEUs do not introduce any irreversible
changes into the circuitry itself, in the worse case they may extort chip reconfiguration or
power cycling to recover.
Finally, the issue that may cause an irreversible change is called the Single Event Latchup (SEL). As the name suggests, it refers to the creation of a latch-up – a forward biased
thyristor-like pnpn structure, induced by the ionization. Since the latch-up’s are self-biasing,
the low resistivity path that they create between two nodes will be maintained until switching
off the device. Moreover, the currents flowing through this parasitic path may be high enoughto permanently damage the device.
There are several methods to cope with the SEE issues. Probably the most popular one
is the triplication of the critical design parts, followed by the voting system. Therefore even
if some kind of issue appears in one part of the circuitry, the other two will remain unaffected
and the voting will provide the proper information. This solution highly increases the chip
power consumption as well as its area.
Fortunately, the electronics fabricated on the SOI structure is highly resistant to any kindof the SEE issues and does not require any special treatment. Thanks to the full isolationof each transistor it is totally immune to the SEL effect. In case of SET and SEU effects
the probability of its occurrence is significantly reduced in comparison with the standard bulk
CMOS. This is a direct implication of the low thickness of the top silicon layer, that reduces
the volume in which the ionization may occur. This SOI feature makes it a perfect candidate

27

2.3. SOI features

for all the applications that have to cope with cosmic radiation and require a high reliability.
These are for example the space probes or satellites that once lunched do not allow for any
maintenance. It is also a very desired feature in terms of usage in any kind of aircraft’s orspacecraft’s.
Ionizing radiation

Ionizing particle

SiO2

SiO2

BPW

n
n+

BPW

n
n+

HV

HV

(A) Single Event Effect.

(B) Total Ionizing Dose.

Figure 2.4: Schemes showing two main categories of the ionizing radiation
damages to the SOI structure.

Unfortunately, the SOI does not show a similar immunity to the Total Ionizing Dose issues,
what is worse, it is even much more vulnerable to this kind of effects than a standard CMOS
structure. To explain the reason of this, one has to examine how does the long-term ionization
affects the CMOS devices. There are several processes that contribute to the behaviour ofirradiated MOSFET’s but they all originate from the presence of the silicon dioxide in its
structure. When the ionization takes place within SiO2 , electron-hole pairs are created andsome fraction of them will recombine almost immediately, but the rest will remain. Since there
is a huge difference in the mobility of the electrons and holes in silicon dioxide, in favour ofthe former, the electrons are sweeped out of the insulator layer within a nanoseconds or less.
Whereas the holes mobility is so low that they remain almost immobile. Overall, this leads
to accumulation of a positive charge in the SiO2 which results in a threshold voltage shift ofa MOS device [29].
Another process that has similar consequences is a radiation induced build-up of relatively
long-living trap states at the Si/SiO2 interface, which can remain for hours or years. Suchstates may be occupied by the holes that have almost escaped from the silicon dioxide or theones created directly in its vicinity. Nevertheless, the holes trapped in these states are exposedto the annealing process which allows for a gradual recovering after the irradiation.
Bulk CMOS is also affected by this process but on much lower scale. The most vulnerable
region in modern CMOS technologies is Shallow Trench Isolation (STI). This refers to theinsulator layer that surrounds each transistor and ensures their separation. It is also formedby the silicon dioxide, so it also gathers the positive charges, but because of the side locationof the STI its influence is less harmful (comparing to the contribution from the BOX layer in
the SOI structure).
In standard CMOS there are several techniques that allow for the radiation-hardening of thecircuitry. Predominantly utilized one is the usage of Enclosed Layout Transistors (ELT) instead

28

Chapter 2. Silicon-On-Insulator technologyof the “classical” ones. In the ELT devices the drain implantation is located in the center of thetransistor structure, which is then encircled by the gate, and the gate is further enclosed by thesource region. Such a solution moves the STI region away from the transistor channel proximity
and thus suppresses its negative influence. It should be also pointed out that the directionof the CMOS technology development is somehow in-lined with its radiation hardening. As
the miniaturization process proceeds, the gate oxides becomes thinner, which directly reduces
the volume of TID sensitive insulating layer. Moreover, in the smallest technology nodes thegate insulation is so thin that a tunnelling processes starts to take place which increases theprobability for holes trapped within SiO2 recombination.
All the solutions devoted to the bulk CMOS, have similar effects also on the SOI MOSFET‘s. Unfortunately, SOI devices are mostly affected by the thick insulator layer located justbeneath the top silicon, and none of the standard methods suppresses this influence. Therefore
the standard SOI electronics is very prone to the TID radiation effects. To overcome this issue
a SOI structure modification, called Double SOI (DSOI), has been proposed [30].

2.4

Double SOI

Double SOI structure is presented in the Fig. 2.5A. It is obtained by repeating the SOI fabrication process twice on the same handling wafer, therefore between the top silicon layer
dedicated for the electronics and the handle wafer there is additional isolated thin middle
silicon layer (MidSi). Such solution introduces several new capabilities, especially in terms ofdetector applications. The existence of additional conducting layer (with relatively low resistivity) between the sensor and the electronics provides an easy way to shield the circuitry fromthe negative influence of a back-gate effect. When grounded, this layer prevents the interaction
between the radiation sensitive volume and the readout electronics. Moreover, by use of the
middle silicon layer for shielding, the restrictions on the sensing node dimensions (explained
in section 2.3.6) are no longer valid. Therefore the sensor capacitance can be reduced and its
shape may be designed independently from the readout.
Although the electronics shielding ensured by the Double SOI structure is highly beneficial,
its main power revels in terms of radiation hardening. The middle silicon layer provides thepossibility to overcome the SOI weakest point, which certainly is the TID vulnerability. In
Double SOI the influence of the positive charge trapped within BOX layer may be compensatedby applying the appropriate negative voltage to the MidSi layer, as shown in Fig. 2.5B. The
compensation voltage may constantly follow the dose and thus restore the initial transistor
threshold voltage. The results presented in [30] show transistors performance irradiated up to
2 MGy and the SOI detector system maintaining its pre-irradiation capabilities up to 500 kGy.

2.5

Lapis Semiconductor process

The Lapis Smiconductor is a Japanese semiconductor manufacturer, which services have been
exploited for the scope of the presented thesis. The company was established in 2008 asa spin-off of the OKI Electric Industry Company. Lapis products, which are mainly digital29

2.5. Lapis Semiconductor process

VMidSi

VMidSi
MidSi

SiO2

SiO2

BPW
n
n+

n
n+
HV

HV

(A) Wafer structure.

(B) Irradiated Double SOI wafer with the MidSi
negatively biased in order to compensate the positive charge trapped in SiO2 .

Figure 2.5: Schemes showing the Double SOI structure and its utilization for
the radiation hardening.

LSI’s such as memories, display drivers, logic IC’s (Integrated Circuits), are available on the
global market. Despite of its commercial activity Lapis provides the 200 nm Fully-Depleted
SOI CMOS technology for the scientific applications. The company remains in collaboration
with the Japanese High Energy Accelerator Research Organization (KEK).
To provide the possibility for the monolithic radiation detectors manufacturing, Lapis has
adopted their process line. They offer several buried wells of different doping concentrations
located at different depths of the handle wafer as well as the connection via to the substrate,
which are necessary to form a sensing diode.
For the scientific purposes Lapis utilizes the SOI wafers provided by the French company
Soitec, which is manufacturing them using the Smart Cut technique. Since for the semiconductor detectors the silicon quality is crucial, Lapis decided to offer their products fabricatedon different types of substrates. The available wafer types are:
CZ(n) n doped substrate obtained by the Czochralski method, with declared resistivity higher
than 700 Ω cm,
FZ(n) n doped substrate obtained by the Floating Zone method, with declared resistivity
higher than 2 kΩ cm,
FZ(p) p doped substrate obtained by the Floating Zone method, with declared resistivity
higher than 4 kΩ cm,
DSOI(p) p doped Double SOI wafer, with the substrate obtained by the Floating Zone
method, which declared resistivity is higher than 1 kΩ cm.
The availability of different substrates does not only provide a flexibility in the choice ofthe most appropriate sensor for specific application. It is also very useful for the studies ofcoupling between the electronics and the sensor. Testing the performance of prototypes having
exactly the same readout electronics, but fabricated on different substrates helps in in-depth
understanding of detectors behaviour.

31

Chapter 3

INTPIX6 detector studies
The INTPIX6 detectors represent the sixth generation of the large area, general purpose
INTegration type PIXels (INTPIX) family, which are being developed by the Japanese groupfrom KEK under the supervision of Yasuo Arai [31, 32]. The development of the INTPIX
detectors has been started in early 2000 and is still ongoing. Successive prototypes and theirmeasurements provided a lot of informations essential to understand the behaviour of monolithic detector based on the SOI technology. For example, a back gate effect was studied withthe second generation of INTPIX detectors and provided the knowledge necessary to overcome
this issue [30, 33]. Since the KEK group cooperates with the foundry, all informations are beneficial not only for the guidance in the electronics design but also for the modifications of theprocess itself. The INTPIX6 detector was fabricated on few different wafer types and thanks
to the close collaboration with KEK, few prototypes of CZ(n) and FZ(n) devices together withthe readout boards were sent for measurements to AGH University.

3.1

INTPIX6 architecture

The INTPIX6 detector prototype wire-bonded to the test board is presented in Fig. 3.1A. The
chip size after dicing is 18.5 mm × 12.3 mm, with the sensitive area of 16.9 mm × 10.75 mm,
which is about 80 % of the whole detector. The pixel matrix consists of 1408 × 896 square
pixels, 12 µm × 12 µm each. The matrix is logically segmented into eleven blocks of 128 × 896
pixels to provide the possibility of parallel readout of each block to reduce the readout time.
The schematic block diagram of the INTPIX6 chip is presented in Fig. 3.1B. The peripheral
circuitry is reduced to the necessary minimum, which is the row and column decoders, biasing
block and output buffers driving analog signals out of the chip. Regarding the in-pixel readout
circuitry, in the input stage there is a pMOS transistor in the source-follower configuration with
two gain settings, followed by a simple sample and hold block based on a storage capacitor.
The schematic view of the in-pixel circuitry is shown in Fig. 3.1C.
The matrix readout can operate either in a global shutter mode or in a rolling shutter mode.
In the global shutter mode the integration period is common for the whole matrix, whereas
in the rolling shutter mode the integration periods are different for different matrix sub-parts(usually for each row). Since in the rolling shutter mode the integration period is limitedby the readout speed all measurements results presented in this thesis are obtained with theglobal shutter mode in which the integration time can be set independently. Moreover, unless

32

Chapter 3. INTPIX6 detector studies

otherwise stated, most of the measurements were performed with the region of interest (ROI)
limited to the matrix sub-part of 256 × 256 pixels, which was motivated by the reduction of

12.3 mmthe readout time.

18.5 mm(A) Photograph of prototype assembled to the test board.

COL_OUT

GAIN

RST

READ

STORE

LOAD

pixel diodeCA[10:0]

COLUMN ADDRESS

Cstore896 x 1408
= 1 261 568 pixels

12 um x 12 um, 128 x 896 pixels

x 11

VDD
12 um x 12 um, 128 x 896 pixels

12 um x 12 um, 128 x 896 pixels

12 um x 12 um, 128 x 896 pixels

ROW ADDRESS

12.2 mm

18.4 mm

VDET VRST
11(+1) analog out(B) Block diagram of the readout electronics.

(C) Schematic of the in-pixel circuitry.

Figure 3.1: INTPIX6 detector.

3.2

Measurement setup

To carry out the measurements of the INTPIX6 chip the SEABAS (Soi EvAluation BoArd
with Sitcp) readout board was used. Each detector chip was glued and wire-bonded to thededicated small chip board compatible with the SEABAS board, which allows for a fast andeasy assemblies replacement without the need of separate readout board for each prototype.
The role of this separate chip board is practically limited to routing all of the signals from thechip to the appropriate SEABAS board ports, whereas the whole functionality is moved to
the readout board. The INTPIX6 chip board and the SEABAS readout board are presented
in Fig. 3.2A and Fig. 3.2B respectively.

33

3.2. Measurement setup

A heart of the SEABAS boards are two Virtex4 FPGAs (Field-Programmable Gate Array):
the first one is dedicated to the user defined chip communication, data taking and buffering, thesecond one is responsible for establishing a TCP/IP (Transmission Control Protocol/Internet
Protocol) connection and sending the data to PC. Beside that there are several DACs (Digital
to Analog Converter) providing biasing currents and voltages and a multi-channel 12-bit ADC(Analog to Digital Converter) for digitalization of all analog outputs.
A dedicated data acquisition software and FPGA firmware were also developed by thegroup from KEK and provided together with the readout board. The data acquisition software (DAQ) utilizes ROOT Data Analysis Framework [34] to create a simple graphical userinterface (GUI), establish TCP/IP sockets for connection with the board, interpret the incoming data and save them in a TTree (data container type) for the offline analysis. It provides
all functionalities required for the chip configuration: preparation of an appropriate commandsequence necessary to set up a desired chip operation mode, adjustment of all biasing voltages and currents, controlling the matrix timing settings and selecting the region of interest.
Additionally, through the GUI one can also control the data acquisition itself by setting up
a number of frames to be measured, data file name and its path. Beside that, it assures basic
online data quality check, thanks to the possibility of online monitoring of every n-th frame
and its basic properties (for example the mean value of pixels amplitudes).
The INTPIX6 detector is sensitive to a visible light therefore all the measurement have tobe performed in light sealed environment. For this reason the readout board and chip board
were always placed in a metal box.

(A) INTPIX6 chip board.

(B) SEABAS readout board.

Figure 3.2: Photograph of the readout boards used for the INTPIX6 detector
measurements.

34

3.3

Chapter 3. INTPIX6 detector studies

Data processing and analysis flow

The data analysis software for hit reconstruction was not provided by the KEK group. Therefore, a dedicated analysis chain was developed by the author of this thesis. Since raw data are
stored in ROOT files the analysis software was also implemented basing on ROOT6 libraries.
The main steps of the data evaluation process and the functionality it provides are discussed
below.
• Raw data reader
To perform the analysis an appropriate input file has to be loaded. Each measurement saves theseparate file comprising a single ROOT TTree container, which holds several leafs (representing
certain variable) carrying basic informations about chip configuration and the main leaf withthe 2D array containing raw signal amplitude value of each pixel. Therefore each consecutive
event in the tree represents a single frame. Each data file consists of several thousands of“calibration” data (taken without any radiation source) and “true” data taken with the signal
source.
• Bad frames rejection
The first step before the analysis is the bad frame rejection, which was added to the analysis
flow after spotting an issue with the readout. It was observed that some frames have significantly increased mean frame value MFrame (mean value of the amplitudes collected by eachpixel in single frame). The example plot showing the mean frame value for the “calibration”
events sample is presented in Fig. 3.3A, where all the “spikes” correspond to the mentioned
issue. It was also noticed that the frequency of these “spikes” depends on the speed of thelink between the readout board and the PC. Fig. 3.3A and Fig. 3.3B show a comparison of two
similar samples taken with different settings of the online data quality monitoring. During
the data-taking of the sample shown in Fig. 3.3A the data quality checks were done every
1 s, whereas for the sample shown in Fig. 3.3B every 100 s. Since the DAQ software is singlethreaded, the time needed for computations related with data quality checks slows down thelink throughput, which directly reflects in more frequent buffer overloading. This was further
leading to the disturbance in the timing of control signals in given frame, which reveals inhighly increased mean frame value. In the end, to minimize this issue the data were takenwith the lowest frequency of online quality checks, but even then some frames were still affected, therefore a bad frame rejection algorithm was implemented. For this purpose the meanvalue of mean frame hMFrame i over the whole data sample and its standard deviation σMFrameare calculated. A frame is marked as a “bad” one and rejected from the further analysis if its
mean value is more than three sigma away from the mean value of all frames:| MFrame − hMFrame i |> 3 · σMFrame

(3.1)

35

890
880
870

890
Mean frame [ADU]

Mean frame [ADU]

3.3. Data processing and analysis flow

860
850
840
830
820
0

880
870
860
850
840
830
820

200

400 600 800 1000 1200
Event number(A) Data quality checks repeated once per second.

0200

400 600 800 1000 1200
Event number(B) Data quality checks repeated once per one
hundred seconds.

Figure 3.3: Plots showing the mean frame values in consecutive frames for the“calibration” events sample at two different frequencies of data quality checks.
Observed spikes indicate improper readout behaviour.

• Pedestal and noise calculation
The core of the analysis starts with estimation of the pedestal and noise values for each pixelin the matrix. These parameters are extracted from the “calibration” sample. For each single
pixel a separate histogram is created and filled with its measured raw signal amplitudes. The
mean value of this distribution is the pixel pedestal P [i][j ] and its standard deviation the
pixel noise σ [i][j ] (where i is row number and j is column number). The examples of plots
showing the pedestal and noise distribution over the matrix are presented in the Fig. 3.4A
and Fig. 3.4B. On the noise distribution one can easily spot that for several rows the noise
is notably increased. The origin of such behaviour has been studied but unfortunately theconclusive explanation of this issue was not found.
250

700

150
650
100
600

50
50

100 150
X [pixels]

200(A) Pedestal map P [i][j ].

250

550

Y [pixels]

Y [pixels]

200

0
0

250

750

2.2

200

2

150

1.8

100

1.6
1.4

50
0
0

1.2
50

100 150
X [pixels]

200(B) Noise map σ [i][j ].

Figure 3.4: Plots showing map of the pedestal and noise distribution overthe INTPIX6 matrix given in ADC counts (ADU). Results obtained with the
INTPIX6 detector fabricated on CZ(n) wafer.

250

36

Chapter 3. INTPIX6 detector studies• Signal extraction
The next step in the analysis is the signal extraction. A pixel signal S [i][j ] is basically obtainedby subtracting the pedestal value from the raw amplitude recorded by each pixel in a given
frame. The correctness of this algorithm can be cross-checked by plotting the pixels signal
spectrum for the “calibration” data. Since these data do not contain any “true” signal, thesignal spectrum should undergo a Gaussian distribution centred around zero with the standard
deviation equal to the pixel noise value. The plots showing the pixel signal spectrum for whole“calibration” sample and the pixel noise distribution are shown in Fig. 3.5A and Fig. 3.5B
respectively.
The signal spectrum changes significantly for the “true” data where an external signal
source distorts symmetrical Gaussian shape by introducing a long tail towards the higher
signal values. The examples of plots showing the pixel signal map for the “true” data frame
and the corresponding signal spectrum are presented in Fig. 3.6A and Fig. 3.6B.
• Clusterization
The total signal generated by a single particle may be splitted over more than one pixel, so to
extract its energy a clusterization algorithm has to be introduced. In the presented analysis
a procedure based on two threshold levels was implemented. In the first step the signal map isscanned to find a pixel which signal (S [i][j ]) exceeds the seed threshold. The threshold value(thseed · σ [i][j ]) is usually expressed in terms of pixel noise what means that a pixel has to havethe signal larger than thseed times the pixel noise to be taken as a seed:(3.2)

S [i][j ] > thseed · σ [i][j ]The specific threshold value has to be adjusted depending on the measurement condition or
detector performance. It must be large enough to reject noise entries, but at the same time low
×109

×103
μ= -0.02
σ = 1.471
0.82CountsCountsμ= 1.47σ = 0.11

2.5

0.6

1.5

0.4

1

0.2

0.5

0

−4

−2
0
2
Pixel signal [ADU]

4(A) Spectrum of the pixel signal S [i][j ], combined for all pixels in the matrix.

01

1.2 1.4 1.6 1.8 2 2.2 2.4
Pixel noise [ADU](B) Spectrum of the pixel noise σ [i][j ].

Figure 3.5: Plots showing spectra of the pixel signal and the pixel noise forthe “calibration” data sample. Obtained with the INTPIX6 detector fabricatedon CZ(n) wafer.

37

3.3. Data processing and analysis flow

109
108
107
Counts

106
105
104
103
102
10
1
−50 0

(A) Pixel signal S [i][j ] map from a single frame.

50 100 150 200 250 300 350 400
Pixel signal [ADU](B) Pixel signal S [i][j ] spectrum, combined forall pixels in the matrix.

Figure 3.6: Plots showing the pixel signal map and the pixel signal spectrum
for the “true” data sample taken with the 241 Am radiation source. Obtainedwith the INTPIX6 detector fabricated on CZ(n) wafer.

enough in order not to lose the particle related hits. Since the INTPIX6 detector show very
good noise performance it was easy to separate the signal from the noise and the seed thresholdsetting was rather arbitrary. For the presented analysis it was typically set to thseed = 10.
After finding the seed, all pixels around it are checked with the different threshold condition:
S [i][j ] > thneighbour · σ [i][j ](3.3)

The threshold for the neighbouring pixels thneighbour is less restrictive and its typical value
in the analysis was thneighbour = 2 which was found to be an optimum. The value of thisparameter has direct influence on the detector energy resolution because too large thneighbour
increases the amount of the missing energy, whereas its too low value increases the probability
for adding a noisy pixel into the cluster.
The searching for neighbours is repeated around any new pixel added into the cluster andends when there are no more pixels fulfilling the neighbour criteria in the vicinity of the current
cluster. When the full cluster is found, it is stored and its main parameters (such as totalenergy or cluster size) are extracted. After that the procedure returns to search for a new seed
pixel in the current frame but excluding all already clusterized pixels.
• Data selection
For the clusters reconstructed on the edge of the matrix it may happen that only part of thesignal is recorded. Since this would naturally affect the energy reconstruction, all the clusters
containing the boarder pixel are discarded from the further analysis.
• Gain uniforming
When a representative data set is selected, the cluster energy spectra plots can be drawn andthe detector performance may be verified. However, this merges the informations from all
pixels in the matrix, which means that any differences between pixels will have negative effect38

Chapter 3. INTPIX6 detector studies

on the overall performance. Therefore, to obtain the best results, limited only by the inherent
noise, one should also apply a correction for the pixel to pixel gain variations or ensure that
this variations are negligible. For the INTPIX6 detector a strange behaviour was alreadyobserved on the pedestal map (see Fig. 3.4A) where one can notice gradient starting from thebottom left corner (pixel (0,0)) towards the upper right corner (pixel (255,255)). It was also
proven that this pattern does not come from the pixels themself. Benefiting from the fact thatthe matrix (1408 × 896 pixels) is much larger than the chosen region of interest (256 × 256
pixels) it was confirmed that the pattern remains the same irrespective of the chosen region.
Therefore this effect had to be attributed to the readout issue. Since the matrix operates ina snapshot mode and all pixels are serialised into a single analog output, each pixel “waits”
for a different period of time to be read out. Since the charge information is stored on pixel
as a voltage across a capacitor, therefore any leakage current is going to change its amplitude
over the time. This mechanism fits perfectly to the observed behaviour where the first readout pixel (0,0), has the highest pedestal, whereas the last one (255, 255) has the lowest.
The described mechanism does not directly implicate the gain variations between pixels.
If the leakage currents are constant despite of the voltage across the capacitance, then theabsolute measured values will still be affected but after pedestal subtraction it should cancel
out, leaving the gain uniform over the whole matrix. Whereas, if the leakage current depends
on the voltage level, then for the pixels containing the signal the voltage drop on the capacitancewill be different than the voltage drop for the same pixels but without the signal (like during
the pedestal measurement). Therefore, it will result in the decrease of the effective gain for
pixels waiting longer to be read out.

×103

80

3

× 10

3.5
3.5

70

3

μ= 30.47
σ = 0.69

3

60

2.5

50

2

CountsCounts

2.5

2

1.5

40
30

1.5

1

20

0.5

10

1

0.5

0
10
0

10

15
15

20
20

25
30
35
Energy [ADU]
25

30

35

40
40

45
45

(A) 55 F e spectra with the Gaussian fit around the 55 F e peak(different colors represent different cells).

028 29 30 31 32 33
Energy [ADU](B) 55 F e energy peak position
distribution.

Figure 3.7: 55 F e spectra and 55 F e peak position plotted separately for different 10 × 10 pixels cells to confirm the need for per-pixel gain uniforming.
Obtained with the INTPIX6 detector fabricated on CZ(n) wafer.

39

3.3. Data processing and analysis flow

To check which case is valid for the given prototype one needs to perform the measurementwith physical signal source, and check if the extracted signal amplitudes vary depending on thehit position. For this purpose the 55 F e source was used. This source mainly emits soft X-rays
Kαof energy E55
F e ' 5.9 keV, which during top illumination penetrates only several micrometersof the detector. Because of to that, the vast majority of the reconstructed clusters are single
pixel clusters, meaning that the whole hit energy is gathered by a single pixel, providing perfectconditions for the single pixel gain estimation.
To obtain statistics high enough to become insensitive to random fluctuations the whole
region of interest was divided into a smaller 10 × 10 pixels cells and the measured energy
distributions for each cell were processed separately. Fig. 3.7A and Fig. 3.7B shows the 55 F espectra and 55 F e peak position distribution respectively. One can notice that there is a shift
in the relative spectra position depending on cell position. It leads to the dispersion of thereconstructed energy peak on the level of 0.68 ADU. The differences between peak positions
were then used to estimate the gain correction factors for each pixel. For that purpose a plane
function is fitted to the histogram of a normalized nonuniformity in the detector response,

Gain correction

with respect to the cell position (shown in the Fig. 3.8).

1.06
1.04
1.02
1
0.98
0.96
0.94
25
20
Y 15
[pi 10
xe
lc 5
ell
] 0 0

20
15
10
]
5
el cellX [pix25

Figure 3.8: Normalized non-uniformity of the detector response with respect tothe cell position (color bar histogram) with the fitted plane (red grid). Obtained
for the INTPIX6 detector fabricated on CZ(n) wafer.

Using the fitted function a gain correction factor was obtained for each pixel. The results
after applying the correction factor are shown in Fig. 3.9A and Fig. 3.9B where the spectra
for each cell and 55 F e peak position distribution are presented. Now, independently on thecell position, each spectra is centered around the same mean value and the peak position
distribution is much more narrow than before the correction, with the dispersion on the levelof 0.15 ADU (4.5 times lower).

40

Chapter 3. INTPIX6 detector studies

×103
3

3.5

× 10

μ= 30.60

3.5

350

3

σ = 0.15

3

300

2.5

250

2

CountsCounts

2.5

2

1.5

200
150

1.5

1

100

0.5

50

1

0.5

0
10
0

10

15
15

20
20

25
30
35
Energy [ADU]
25

30

35

40
40

45
45

(A) 55 F e spectra with the Gaussian fits around the 55 F e peak(different colors represent different cells).

028 29 30 31 32 33
Energy [ADU](B) 55 F e energy peak position
distribution.

Figure 3.9: 55 F e spectra and 55 F e peak position plotted separately for different 10 × 10 pixels cells after applying the gain uniforming algorithm. Obtainedwith the INTPIX6 detector fabricated on CZ(n) wafer.

3.4

Measurements results

After the analysis flow had been set up, a set of measurements dedicated to characterize theperformance of the chip was performed. For this purpose two radioactive sources were used
as a signal source: 241 Am and 55 F e. The 241 Am source was chosen to perform the detector
calibration because it has six main, well separated lines distributed over a quite large energy
range (covering the energies from around 10 keV up to almost 60 keV).
All measurements (unless otherwise stated) were performed in very similar, stable conditions at ambient temperature of 23 ◦C with the sensor biased at 100 V and with integration
time set to 10 µs. Moreover, most of the measurements were carried out for two different sensor
wafer types: Floating Zone n-type – FZ(n) and Czochralski n-type – CZ(n). For the clarity, all
the intermediate results of the analysis process are shown in details for the CZ(n) wafer only,
whereas the final conclusions are presented for both assemblies. The complementary plots for
FZ(n) are presented in the Appendix A.

3.5

Detector calibration

The detector calibration requires the estimation of the conversion ratio from the arbitrary energy units expressed in ADC counts into the absolute energy, usually expressed in electronvolts.
In this approach all the fragmentary coefficients such as the mean energy needed for an e-h pair
production, pixel input stage conversion coefficient or readout chain amplification are combined together into one effective conversion ratio G. Moreover, if radiation source provides

41

3.5. Detector calibration
×103
3

×

Merged clusters
2 hit cluster
4 hit cluster
6 hit cluster
8 hit cluster

10

50
50

40

1 hit cluster
3 hit cluster
5 hit cluster
7 hit cluster>8 hit clusters

Counts

40

30
30

20
20

10
10

0
0

0
0

50
50

100
100

150
150

200
250
Energy [ADU]
200

250

300
300

350
350

400
400

450
450

Figure 3.10: Combined spectrum shown in black, whereas individual contributions from clusters of certain size presented in different colors.

more than one energy line (within the acceptance of the detector) not only the conversion
ratio can be found but also its linearity over certain energy range can be checked.
An example of energy spectrum obtained from the measurement with the 241 Am sourceis shown in Fig. 3.10. For the more detailed investigation a separate spectrum formed fromthe data sub-sample containing clusters of given size is drawn with different color, whereas
a combined spectrum is drawn in black. It can be noticed that individual contributions fromdifferent cluster sizes have slightly shifted peak values. This is very undesired effect because it
broadens the width of the combined peak, which defines the noise performance of the detector.
To investigate the scale of this issue and a method to overcome it, a dedicated analysis
was prepared basing on ROOT6 libraries. It utilizes an automatic peak finding algorithm
followed by fitting a Gaussian function. An sample plot showing the result of its operation ispresented in Fig. 3.11. All founded peaks are marked with the red triangles, and a Gaussian
fitted to the highest one is plotted with the red curve. The procedure returns the mean µ andwidth σ (standard deviation) of the fitted function for each peak that was found in the given
spectrum. All the constituent spectra were analysed separately and the results are shown in
Tab. 3.1.
The origin of the observed discrepancies in the peak positions was attributed to the differences in the missing energy. One can imagine that some part of the carriers induced by theincident photon diffused to the pixels that did not have enough signal to exceed the threshold,causing a reduction of the total measured energy. Such variations will by related to the hit
position within the pixel, and so also to the cluster size. For example for hits that occur
close to the corners of the pixels it is very likely that each of four pixels near this corner will
gather enough energy to be treated as a signal and therefore the significant energy loss is not42

Chapter 3. INTPIX6 detector studies

Peak number →Clustersize ↓
1
2
3
4
Combined

1

2

3

4

5

6

µ

σ

µ

σ

µ

σ

µ

σ

µ

σ

µ

σ

37.6
38.5
—
—
37.6

6.63
13.7
—
—
10.1

72.5
73.0
69.3
76.8
72.7

5.16
6.50
6.70
5.40
6.02

91.1
91.1
89.0
95.0
91.2

6.67
7.17
7.01
5.64
7.20

112.6
111.7
108.9
115.0
111.9

6.80
7.74
9.70
7.41
7.70

143.7
141.4
139.1
143.0
142.2

5.56
7.96
7.40
6.11
7.02

—
—
341.5
336.1
338.7

—
—
11.0
10.6
12.0

Table 3.1: Peak positions µ and their widths σ for the 241 Am spectra measured separately for contributions from different cluster sizes as well as for the
combined one.

expected. On the contrary, for a three pixels clusters it seems very likely that some part ofsignal reaches also the fourth pixel but not large enough to exceed the threshold, therefore allthat part of the energy is lost. This is only a qualitative interpretation but it is in a good
agreement with the obtained results, where the highest energy is obtained for the four pixel
clusters, while the lowest for the three pixel clusters, and values in between for one and two
pixel clusters.
It should also be mentioned, that for photons the cluster shape and the missing energy
also highly depend on the depth at which the interaction with the sensor took place. The
reasoning presented above is mainly valid for a lower X-ray energies for which the induced
signal is relatively low and comes almost only from a shallow penetration. For higher energies,
it becomes more likely that interaction occurs also deeper inside the sensor. Therefore, carriers
may have more time to diffuse, which naturally enlarges the cluster size. Thus, for the high
X-ray energies the individual peaks in the spectrum are additionally smeared, by contributions
coming from different interaction depths.
Since there are various effects affecting the measured cluster energy, it is hard to give any
quantitative correction procedure, but one should have in mind that there are several mechanisms that affect the measured particle energy and the final spectrum quality is determined
not only by the noise of the readout chain.
×103
50Counts

40
30
20
10
0

0

50 100 150 200 250 300 350 400 450
Energy [ADU]

Figure 3.11: Result of the peak finding procedure. With the red triangles all
found peaks are marked, whereas with the red curve a Gaussian fit to one ofthem is displayed.

43

3.5. Detector calibration

10

13.9 keV(Np)8.01keV(Cu)

5

5

10

17.8 keV(Np)
17.8 keV(Np)

104

4

10

26.3 keV(Am)Merged clusters
2 hit cluster
4 hit cluster
6 hit cluster
8 hit cluster

1 hit cluster
3 hit cluster
5 hit cluster
7 hit cluster>8 hit clusters
59.5 keV(Am)3Counts103

1033.2 keV(Am)

102

2

10

10
1

10

1

0
0

50
50

100

150

100

150

200
250
Energy [ADU]
200

300

250

300

350
350

400
400

450
450

Figure 3.12: 241 Am spectrum for CZ(n) wafer with peak attributed to corresponding X-ray energies.

The final 241 Am spectrum for CZ(n) wafer is shown in the Fig. 3.12 with all peaks assigned
to the expected X-ray energies. The 241 Am decays into 237 N p which results in six main
X-ray energy lines and one characteristic 8.01 keV fluorescence line from copper. After peakidentification the calibration curve can be drawn by plotting the measured peak position versus
corresponding photon energy. It is shown in Fig. 3.13 together with a linear regression line.
The INTPIX6 detector shows good linear behaviour over the whole available energy range
with the conversion coefficient G = 5.59 ADU
keV . It is also worth to notice that the y-intercept isequal to −2.5, which corresponds to the small energy offset below 450 eV.

Peak position [ADU]

400
350
300
250
200

5

5

5.

y=

.
-2
x
9

150
100
50
0
0

10 20 30 40 50
Energy [keV]

60 70

Figure 3.13: Calibration curve for INTPIX6 detector showing the peak position in ADC counts versus X-ray energy.

44

Chapter 3. INTPIX6 detector studies

3.6

Noise performance

Usually the electronic noise is expressed in terms of voltage and current fluctuations, but for
the radiation detector the signal comes directly from the charge induced during the interaction.
Therefore, it is very useful to express the detector noise in terms of charge. For that reason
a parameter called Equivalent Noise Charge (ENC) was introduced. Equivalent Noise Charge
is defined as the amount of charge QN , that introduced to the input of the readout chain asa Dirac delta current pulse I (t) = QN δ (t) results in the output signal equal to the root meansquare value of the readout noise. In other words the ENC is equal to the input charge forwhich the signal to noise ratio is equal one [17]. Describing the detector noise performancein terms of the ENC allows for direct comparison of different detectors, irrespective of any
differences in theirs designs.
The readout noise distribution is obtained during one of the analysis flow steps (describedin Sec. 3.3) and shown in the Fig. 3.5B. The ENC can be calculated by taking the mean pixel
noise value of hσN i together with the previously determined conversion coefficient G andassuming that 3.6 eV is needed for the e-h pair production:
1
eV
1 e−
EN C [e ] = hσN i [ADU ] ··G ADU 3.6 eV
−





"

#

(3.4)

The ENC obtained for the CZ(n) wafer type equals to 73 e− , whereas after applying thesame procedure to the data sample taken with the FZ(n) wafer the ENC is even a bit lower
on the level of 70 e− .
There is one more thing concerning the noise performance requiring a supplementary remark. One may already noticed quite a large difference between the pixel noise measured
during the calibration which was around 1.5 ADU and widths of the peaks in the 241 Am spectrum given in Tab. 3.1 (usually between 6 to 10 ADU). On the first glance this may looksuspicious, but one has to remember that the width of the energy peak depends not only
on the readout noise. As already mentioned, the whole 241 Am spectrum consists of many
constituent photon energy levels, therefore it is not possible to extract a single energy line
and check its width. Beside that, there is an additional factor coming from the fluctuationof the unmeasured charge (due to its arrival to the pixel that has too low signal amplitude
to exceed the threshold). Moreover, for the clusters larger than one pixel, each pixel in thecluster contributes to the overall cluster noise therefore the whole cluster noise is increased.
An additional measurement was performed with the 55 F e source, which has much lesscomplex energy line structure. It has two dominant, closely located Kα lines at aroundβKα
E55
F e ' 5.9 keV and an about ten times less frequent Kβ line with the energy of E55 F e ' 6.5 keV.

K

Therefore, the 55 F e source is much more suitable for estimation of the energy resolution than241 Am. The obtained 55 F e spectrum for the CZ(n) wafer is shown in Fig. 3.14A and Fig. 3.14B,

before and after gain correction algorithm application respectively. One can spot the 5% reduction of the peak width thanks to the gain correction. The noise level calculated from thecorrected 55 F e peak width corresponds to around 110 e− which is much closer to the pure pixel
noise. This measurement confirms the INTPIX6 detector capabilities in terms of spectroscopy

45

3.7. Studies of radiation hardness
applications.
×106

1.8

μ= 30.46
σ = 2.36

1.6
1.4

μ= 30.60
σ = 2.24

1.6
1.4

1.2

1.2

1

CountsCounts

×106

0.8

1
0.8

0.6

0.6

0.4

0.4

0.2

0.2

0
10

15

20

25 30 35
Energy [ADU]

40

0
10

45

(A) 55 F e spectrum before gain uniforming procedure.

15

20

25 30 35
Energy [ADU]4045(B) 55 F e spectrum after gain uniforming procedure.

Figure 3.14: Spectrum of the 55 F e source taken with the INTPIX6 CZ(n)detector.

3.7

Studies of radiation hardness

To gather a large statistics for detailed studies, a 24 hour long measurement with a highintensity 55 F e source was carried out. Unfortunately, after this measurement the detector
started to behave incomprehensibly. A very high nonuniformity was found on the pedestal
map. An example of frame taken after that long measurement is shown in Fig. 3.15A, where
an increased pedestal values in the central part of the detector are clearly visible. Since theobserved pattern size and shape directly correspond to the used 55 F e source and it appears
exactly at the position of the source placement, the radiation damage was suspected. Becauseof the existence of a quite thick insulator layer (∼ 200 nm) located just under the electronics the
SOI structure is mainly susceptible to the Total Ionisation Dose (TID) effects. Therefore, toconfirm the presumptions, a total dose deposited within the buried oxide (BOX) layer needed
to be estimated.
The 55 F e source emits low energy X-rays, which are mainly absorbed within few micrometers of the detector. Before reaching the sensing volume of the detector, they have to passthrough the chip passivation layer (of thickness unknown precisely), five layers of metallisation (with nonuniform coverage across the pixel) and the silicon layer with the electronics, so
the direct estimation of the deposited dose would be inaccurate. Fortunately, the total dose
received by the BOX layer can be also calculated based on the exponential nature of X-ray
attenuation and the number of measured X-rays that have reached the sensing volume. As it
can be seen in Fig. 3.15A the scale of the radiation damages highly depends on the detector
region. Thus, for the estimation of the received dose only a central region was chosen.
The mean number of clusters hN i reconstructed in a single frame (during integration timeτ = 10 µs) was around 70. Because of very short radiation length it may be assumed that

46

Chapter 3. INTPIX6 detector studies

Y [pixels]

800
700
600
500
400
300
200
100
0

0

200

400

600

800

X [pixels]

1000 1200 1400

(A) The example of row signal map taken with
the CZ(n) wafer irradiated up to 60 krad showing the increased pedestal in the central region.

(B) Mean frame (blue) and number of clusters
reconstructed in single frame (red) in function of
the total dose.

Figure 3.15: Plots showing the INTPIX6 CZ(n) detector behaviour during themeasurement with the high intensity 55 F e source.

all photons that have reached the sensing volume have also decayed within it. Therefore,
from the number of measured clusters, the intensity at the bottom side of the insulating layer
I (y = BOXbot ) (according to Fig 3.16) can be directly obtained as:
I (y = BOXbot ) =70 particles
particles
hN i
=
=7
τ
10 µs
µs

(3.5)

Following the decay law, the intensity I (y = BOXtop ) at the top side of the buried oxide
layer may be calculated taking the BOX thickness yBOX = 0.2 µm and the radiation lengthfor ∼6 keV photons in SiO2 of x0SiO2 = 55 µm:
I (y = BOXtop ) = I (y = BOXbot ) · e

xBOX
x0
SiO2

ΔI

Ionizing radiation

(3.6)

BPW

BOXbotnn+yHVFigure 3.16: Sketch of the irradiated SOI structure with the waveform of theincident radiation intensity in function of depth (not to scale).

I

I0

BOXtopSiO2

473.7. Studies of radiation hardness
Which gives the total number of photons attenuated within the insulator layer:(3.7)∆I = I (y = BOXtop ) − I (y = BOXbot )= I (y = BOXbot )(eparticles= 0.14
µs

xBOX
x0
SiO2

− 1)

From above, the total irradiation dose DBOX can be designated as:
DBOX =∆I · Eγ · t= 60 krad
mBOX

(3.8)

where t is the irradiation time of 24 hours and mBOX is mass of the considered material volumeof 4.16 µg.
The irradiation was performed during the ongoing measurement, therefore the information
about the detector performance at different dose levels can be easily extracted. The numberof reconstructed clusters per frame and the mean frame value in function of dose are shown in
Fig. 3.15B. Since the mean frame is changing significantly during the measurement the analysis
flow had to be adopted to this behaviour. Therefore, for this analysis the pedestal value foreach pixel was updated continuously to follow the observed trend. Also the bad pixel finding
algorithm was adopted to look for noisy pixels not only within the “calibration” data sample,
but periodically also in the “true” data during the analysis.
From the observed hit rate it is clear that the detector behaves stable up to about 25 krad,
while above this value a significant drop of the detection efficiency is observed. The main reasonof this decrease is the growing number of bad pixels. It may be seen from Fig. 3.17A where
the pixel noise is shown before and after irradiation. The number of bad (highly fluctuating)103

0-10 krad10-20 krad20-30 krad30-40 krad40-50 krad50-60 krad106

Befor irradiation

105

After irradiation

CountsCounts

104
102

10

103
102
10
1

1
0

10

20
30
Pixel noise [ADU]

4050(A) Pixel noise distribution before the irradiation
and after receiving 60 krad.

0 20 40 60 80 100 120 140 160 180 200
Energy [ADU](B) 55 F e spectra shown separately for different
dose ranges.

Figure 3.17: Comparison of INTPIX6 CZ(n) performance before and after
irradiation.

48

Chapter 3. INTPIX6 detector studies

pixels grows with irradiation dose. At certain point their fraction is so high that the cluster
searching algorithm, which requires good pixels without signal at the cluster boundary, starts
to lose efficiency.
Very similar conclusions can be drawn from the plot shown in Fig. 3.17B where 55 F espectra are shown for different dose ranges. The spectra in the plot are done taking clusters of
all sizes but at such low energies practically all events are single pixel clusters. It is seen thatup to 20 krads the curves are practically not changed with the same efficiency and resolution.
The peaks from single, double (or even triple) 55 F e photon events can be easily identified. For
the doses up to 30 krad the main spectrum features are still preserved. For higher doses boththe efficiency and the peaks shape deteriorate.

3.8

INTPIX6 imaging capabilities

To precisely determinate the imaging capabilities of the detector one should follow the specified
methodology. Since in our case, the proper equipment was not available only several, simple
measurements were performed to get the rough feeling about INTPIX6 potential. For that
purpose the whole (1408 × 896 pixels) matrix was read out. As a “photographed” object
a metal plate with different patterns, shown in Fig. 3.18A, was used. Most of the measurements
were taken using the shape with the finest structure, marked by a red circle. An additional
independent test was performed with the microscope to recognize dimensions of used structure.
The picture of its central part is shown in Fig. 3.18B. The smallest details have the widths ofabout ∼100 µm.
During the measurement the chosen pattern was placed about 2 mm above the detector
surface and illuminated using a defocused laser light. Two different wavelengths were used:
660 nm and 1060 nm. Each measurement consisted of 100 individual frames, taken with the
integration time of 1000 µs. The final pictures were obtained offline by summing up all frames
from a single run.

100 μm(A) Global view, showing all available patterns, with the one mostly used marked with
red circle.

(B) Picture from microscope taken to determine the pattern dimensions.

Figure 3.18: Pictures of a metal mask used to check the imaging capabilitiesof the INTPIX6 detector.

49

3.8. INTPIX6 imaging capabilities

The examples of obtained images using the FZ(n) wafer type are presented in Fig. 3.19A
for which the 660 nm laser was used and in Fig. 3.19B for the 1060 nm laser. It can be
immediately noticed that the illumination was nonuniform. This was caused by the problems
with defocusing the laser while keeping its intensity high enough. Nevertheless, for bothcases the pattern was reconstructed at the very detailed level. One can notice that the picture
obtained with the 660 nm laser seems to be slightly sharper which is caused by the very shallow
penetration of the 660 nm photons, which gives no time for the induced charges to diffuse
before arriving to the sensing electrodes. Whereas 1060 nm photons may penetrate the wholedetector thickness, therefore the generated charge diffuses more. This is even more explicit
after looking on the picture taken with the 660 nm laser but during the illumination from thebackside, which is presented in Fig. 3.20A. The overall shape is still visible but its sharpness
is significantly deteriorated, which is directly related to the increased diffusion comparing to

800
700

800
700

600
500
400

600
500
400

300
200
100
0

Y [pixels]

Y [pixels]

the front illumination.

0

200

400

600

800

X [pixels]

1000 1200 1400

(A) Image obtained during front illumination of
the FZ(n) wafer with the 660 nm laser.

300
200
100
0

0

200

400

600

800

X [pixels]

1000 1200 1400

(B) Image obtained during front illumination ofa FZ(n) wafer with the 1060 nm laser.

800
700

800
700

600
500
400

600
500
400

300
200
100
0

Y [pixels]

Y [pixels]

Figure 3.19: Images of the test pattern taken with the INTPIX6 detector.

0

200

400

600

800

X [pixels]

1000 1200 1400

(A) Image obtained during back illumination ofa FZ(n) wafer with the 660 nm laser.

300
200
100
0

0

200

400

600

800

X [pixels]

1000 1200 1400

(B) Image obtained with the 660 nm laser during
front illumination of a irradtated CZ(n) wafer(after 60 krad).

Figure 3.20: Images of the test pattern taken with the INTPIX6 detector.

50

Chapter 3. INTPIX6 detector studies
Similar measurement was also performed for the irradiated CZ(n) wafer. Its result is shownin Fig. 3.20B. Regardless the degradation in efficiency and energy resolution a reasonable image
quality is still preserved.

3.9

INTPIX6 results summary

The INTPIX6 monolithic pixel detector performance was studied in detail with the use of
two different X-ray sources (241 Am and 55 F e) including its irradiation up to 60 krad dose.
The ENC of about 70 e− (pixel noise) or 110 e− (width of 55 F e peak) was obtained before
the irradiation. The detector showed such a good performance, reflected by its small ENC
and negligible number of bad pixels, up to about 25 krad dose. Above this value the numberof noisy pixels started to increase significantly but the detector was still operational, giving
reasonable response to the laser and X-ray signals even after 60 krad dose. The presented
studies were done for the standard Lapis SOI process. An improvement of radiation hardness
is expected from the recent SOI process updates like Lightly Dopped Drain (LDD) transistors
or double SOI wafer [29].

51

Chapter 4

SOI detector prototype for general
studies
After very promising results obtained with the INTPIX6 detector, it was decided to design
the SOI device targeting the application in particle physics experiments. Since for high energy
particle detectors there is a growing demand on the material budget reduction, a step towards
monolithic solutions seems to be a natural direction. However, a lot of R&D work is stillrequired to bring these technologies to the level mature enough to build a reliable, complex
detector systems.
Before undertaking a project dedicated to the requirements of a specific detection systema small general purpose test device was designed. It aimed to check the technology capabilities,
test different architectures and become familiar with all available structures.

M1
M3

M2

(A) Layout of the final design.

(B) Photograph of the fabricated prototype.

Figure 4.1: Layout and photograph of the SOI detector prototype designed
for the general studies.

52

Chapter 4. SOI detector prototype for general studies

4.1

Design overview

The layout of the final design and photograph of the fabricated chip are presented in Fig. 4.1A
and Fig. 4.1B. Due to its test purposes, it encomposes several small independent matrices,utilizing different readout approaches. First, main matrix (M1) exploits an integrating type
pixels, the second one (M2) contains pixels with shaper and peak-detector (designed without
participation of the thesis author), whereas the third one (M3) is a self-triggering matrix withan on-chip digitalization and data serialization. This section will be fully devoted to the first
matrix (M1).
The block diagram of the readout electronics of the main matrix is presented in Fig. 4.2,
with parts designed by the author of this thesis marked. The heart of the design is a small,16 × 36 pixel matrix operating in rolling-shutter mode. The matrix is divided into two halves,
with different input stage architectures. One part utilizes a simple source-follower (SF) architecture, whereas the second one a charge-sensitive pre-amplifier (CPA). The CPA matrix
was further divided into two parts. One, CPA(small), with small (5 µm × 5 µm) sensing diodelocated in the center of the pixel and the second, CPA(large) with the large sensing diodecovering the entire in-pixel electronics. The first approach is suitable for DSOI(p) wafer where
there is no need for the additional electronics shielding, whereas the second type is aimed for all
standard SOI wafers. The large diode have to cover almost whole pixel area (29 µm × 29 µm).
To slightly reduce its capacitance, the sensing implant is having the cut offs in the regions
without the active electronics components, which results in its irregular shape.
The readout control block is common for the whole matrix. It is realized according to therolling-shutter readout mode and provides all steering signals necessary to control the signal

control signals fanout(large)CPA(small)Readout Control

Biasing

SF

Column Amp's
Out AmpOutput
Pads

Figure 4.2: Block diagram of the main matrix. Blocks designed by the authorof the thesis have been marked with the color background.

53

4.1. Design overview

flow from each pixel towards the output pad. The column amplifiers buffer the charge signal
received from pixels and redirect it to the output amplifier which is driving the signal out of
the chip.

4.1.1

Pixels architecture

Source-follower architecture
As already mentioned, two different architectures of pixel electronics were implemented. The
source-follower in-pixel circuitry is presented in Fig. 4.3A. The charge sensitive volume is represented by a diode reversely-biased by the high voltage (HV). The sensing node is directly
connected to the gate of the nMOS transistor in the source-follower configuration. In this
topology the voltage gain is close to unity, which means that any voltage change on the input(which in this case is a gate terminal), will cause almost identical voltage change at the output (source). Since the input node does not have any direct current (DC) path, any charge
generated within the active sensor volume QIN will be stored across the input node capacitance CIN leading to the voltage shift ∆VSFIN on the input node. For the source-follower, thesame voltage shift is observed on its output ∆VSFOU T . In this way the charge induced by theradiation is converted into the voltage signal and its amplitude corresponds to the amount ofinitial charge.
∆VSFOU T ' ∆VSFIN =

QIN
CIN

(4.1)

In the next step the signal goes to the two parallel sample and hold blocks formed by a pairof switches and capacitances. Together, they operate in a Correlated Double Sampling (CDS)
mode, which means that in the first step (switch F1 shorted) a baseline voltage (the output
voltage level after the reset) is stored on one of the capacitances. Later on, after the integration
time, a second sample (switch F2 shorted) is stored on the second capacitance. This one storesthe voltage level corresponding to the baseline plus any signal induced during integration.
Thus in an ideal case, the difference between this to samples correspond directly to the input
charge.
There are several benefits of using the CDS technique, but it has also some drawbacks. In
principle, carrying out two consecutive measurements allows to filter out the low frequency
noise component and the shorter the interval between samples the wider suppressed frequency
band is. But on the other hand both measurements contribute with theirs thermal noise which√in consequence multiplies the overall noise by the factor of 2. Therefore, the profits from theusage of the CDS are highly case-dependent. Unfortunately, the provided technology models
do not allow for a reliable noise simulation. Nevertheless, since the design was devoted to thetest structures it was decided to use the CDS technique. It has also a beneficial side effect,
which is the conversion of a single ended into a differential signal, which is much less sensitive
to the distortions induced during the readout.

54

Chapter 4. SOI detector prototype for general studies
Once both, baseline and signal samples are stored on the capacitances, they are waiting to

be read out off the pixel. It occurs when the READ signal appears and connects them to the
input of a column amplifier located outside the matrix.
T4

T6

T3

T5

Vb3

VRST

RST

F1

CS1

Vb2

RST

VOUT1

VOUT1

READ

READ
Vb1

CF
VOUT2

F2

CS1

F1

T2
T1

CS2

HV

VOUT2
CS2

Vb1
F2

HV

(A) In-pixel circuitry of the source-follower
pixel.

(B) In-pixel circuitry of the charge sensitive
pre-amplifier pixel.

HIT

integration period

RST
F1
F2
READ
VOPre V
VCS1
VCS2

ΔVOUT

t
(C) Sketch of the waveforms showing the steering signals (black) and the voltage levels on the outputof the input stage (VO P re ), across CS1 capacitance (VCS1 ) and CS2 capacitance (VCS2 ).
Figure 4.3: Schematic diagrams of in-pixel readout electronics with the waveforms of the main signals.

Charge-sensitive pre-amplifier architecture
The general readout approach in the second type of the pixels (Fig. 4.3B) is similar – the input
stage is followed by the CDS block. As already mentioned, instead of a source-follower there
is a charge-sensitive pre-amplifier in the input stage. The main advantage of this solution ishighly reduced dependence of the output signal magnitude on the input capacitance. This
gives the opportunity to amplify the signal in the first stage of the readout chain, suppressing
the noise contribution from the subsequent stages.
According to the simple scheme of charge-sensitive pre-amplifier presented in Fig. 4.4 its
voltage response VCP AOU T on the input charge QIN can be calculated knowing that the whole
injected charge will be divided between CD and CF capacitances:
QIN = QD + QF

(4.2)

55

4.1. Design overview
CF
QF
VIN

QIN

-KV

VCPAOUT

QD
CD
Figure 4.4: Simple scheme of the charge-sensitive pre-amplifier.

Using the fact that voltage across the capacitance is given by V = Q
C and the pre-amplifier
assures VCP AOU T = −KV · VIN , we get:

QIN = VIN CD + (VIN − VCP AOU T )CF(4.3)= VIN (CD + (KV + 1)CF )VCP AOU T(CD + (KV + 1)CF )=−KVWhich finally leads to:
VCP AOU T = −QIN
K → ∞ QIN−−−V−−−−→
CF +CDCF
CF + KV(4.4)

where CF is the feedback capacitance, CD is the detector capacitance and KV is the openloop voltage gain of the pre-amplifier. This directly shows that when the high gain of the
pre-amplifier is assured the output signal amplitude becomes independent from the usually
dominating detector capacitance and depends only in the CF value.
For the pre-amplifier a telescopic cascode architecture was chosen. In this configuration
voltage gain is given by [35]:KV = gm1 · (rds2 (1 + gm2 rds1 )||rds3 (1 + gm3 rds4 ))(4.5)

where gmX is a transconductance of X-th transistor and rdsX is its small-signal drain-source
resistance. To obtain a high KV value the additional current source (formed by T5 + T6 ) was
introduced which increases the input transistor transconductance gm1 , without lowering themain current source resistance (rds3 (1 + gm3 rds4 )).
Feedback capacitance in CPA
To fully utilize the charge sensitivity of the pre-amplifier for a small input charge detection(below 100 aC) one has to provide a small feedback capacitance CF . According to equation
4.4 the value of CF determines the charge to voltage conversion ratio, the smaller feedback
capacitance is the larger output voltage amplitude. For example, to obtain a 100 mV signal
from the 100 aC of input charge, the capacitance CF should be 1 fF. Unfortunately, it is not

56

Chapter 4. SOI detector prototype for general studies

easy to implement such a small capacitance. The smallest standard MIM (metel-insulatormetal) capacitor available in the used technology is 37.5 fF, which is far too much for thisapplication.
The easiest method to lower the capacitance is connecting several capacitors in series, since
the total capacitance is equal to the reciprocal of the sum of the reciprocals of their individual
capacitances. But in this particular case it will mean that to obtain a value around 1 fF one
has to use a series of about 37 minimal capacitors. This of course is not suitable for the pixel
design where the available area is highly limited.
C1
CF
A

C2

A

B

B
C3

Figure 4.5: T-shape capacitor structure, used to minimise the feedback capacitance.

Another solution is a “T-shape” capacitor structure, shown in Fig. 4.5. In this approachthe capacitance seen between terminals A and B is given by:
CAB =

C1 C2
C1 + C2 + C3

(4.6)

C1
3
2+ C
C1

(4.7)

Which for C1 = C2 simplifies to:
CAB =

C3
This shows how the effective feedback capacitance may be reduced by keeping a high C
ratio.
1

According to the above example, using the “T-shape” structure with minimal size C1 and C2

capacitors, to get the 1 fF feedback capacitance, the C3 has to be about 35 times larger thanC1. This means that total capacitance needed in both presented approaches is exactly thesame, but implementing a single large capacitance requires much less area than 35 independentones. This is mainly because each single capacitor needs a special boundary treatment, which
has a significant impact on its area.
Another way to produce a small capacitance is a custom plate capacitor formed by two
metal layers. But since it is not a standardized structure available from the component libraryprovided by the vendor, its value may vary significantly.
The consistency of the feedback capacitance over the whole pixel matrix is very importantfactor. In the ideal case one expects exactly the same response of each pixel in the matrix.
However, during the chip production every single component of the whole design is subjected
to a mismatch variation. Since the feedback capacitance has direct influence on the output
signal magnitude, its variation immediately deteriorates the chip performance. The component
parameters fluctuations are described by the technology vendor. For the capacitance it mainly
depends on its dimensions, the larger the capacitance, the smaller its relative capacitancevariation.

57

4.1. Design overview

To estimate the spread of the feedback capacitance for these two approaches let us consider
the case in which n-folded reduction of a minimal available capacitance (Cmin ) is obtainedusing the smallest area. For the series capacitance connection this means a chain of n Cmin
capacitances. Thus:
1
1
1
1
+
+ ... +=
CFSeries
C1 C2
Cn

(4.8)

and for C1 = C2 = · · · = Cn = Cmin it simplifies to:
CFSeries =

Cmin
n

(4.9)

Assuming that each single capacitance in the chain has its own uncertainty ∆Cmin and contributes to the resultant uncertainty ∆CFSeries according to the error propagation law, one
gets:∆CFSeries =

∆Cmin
√
n

(4.10)

Concerning the same assumptions for the second approach, according to equation 4.6 one has
to implement C1 = C2 = Cmin and C3 = (n − 2)Cmin . The total capacitance CFT shape is thenequal:

C1 C2
C1 + C2 + C3
2
Cmin
Cmin
=
=
2Cmin + (n − 2)Cminn(4.11)

CFT shape =To estimate its spread ∆CFT shape , one needs to make an additional assumption on the uncertainty of C3 capacitance. Taking the worst case scenario for√C3 let us assume a constantrelative uncertainty which means that ∆C3 will be equal to n − 2∆Cmin . Following theuncertainty propagation law:s
∆CFT shape =

s
∆C1

=

2

s
∆C1 2

=

∆C1 2

2

+ ∆C2 2C2 ( C1 + C2 + C3 ) − C1 C2( C1 + C2 + C3 ) 2

C2 ( C2 + C3 )(C1 + C2 + C3 )2

2

Cmin 2 (n − 1)(nCmin )2

2

∆Cmin

2

∆Cmin

2

s
=

∂CFT shape
∂C1



s
=





 

n−1
2
n2

2

2

+ ∆C2 2

n−2
+
n4



∂CFT shape
∂C2

+ ∆C2



+ ∆Cmin



2

2



2

Cmin 2 (n − 1)(nCmin )2r= ∆Cmin∂CFT shape∂C3

C1 (C1 + C2 + C3 ) − C1 C2( C1 + C2 + C3 ) 2C1 ( C1 + C3 )( C1 + C2 + C3 ) 2

+ ∆C3 22n − 3n3

2

2+ ∆C3 2

2

2

(4.12)

+ ∆C3

2

C1 C2
( C1 + C2 + C3 ) 2+ (n − 2)∆Cmin

2





−C1 C2( C1 + C2 + C3 ) 2

2

Cmin 2(nCmin )2

2

2

58

Chapter 4. SOI detector prototype for general studies
Comparing the results obtained for both solutions its clearly visible that the second method

provides smaller mismatch of the capacitance, for all allowed n values (n > 2)
∆Cmin

r

∆Cmin
2n − 3< √3nn(4.13)∆CFT shape < ∆CFSeries
Therefore, since the T-shape approach provides a better matching and is less area consuming
it was implemented in the design. Moreover, the C3 capacitance was divided into two parallel
capacitors: one always connected C3a and second one C3b which may be optionally added.
Such a solution allows for different gain selection. Final values of C3a and C3b were dictatedby the available area and they were set to C3a = 75 fF and C3b = 187.5 fF, which results in
4.17 fF of the feedback capacitance in the high gain mode and 9.375 fF in the low gain mode.
Besides that, one has to remember that there are always some parasitic capacitances, formed
within a transistor structure or between the interconnection wiring, adding up to the effective
capacitance. Unfortunately, the precise tool for the parasitic capacitance extraction was notavailable, but basing on the experience from other technologies the total parasitic feedback
capacitance should not be larger than few femtofarads.
Switches in CPA
Another very sensitive part of the presented architecture is the reset of input stage. Since in
the integrating type pixels there is no DC connection between the input and output nodes, theproper operating point of the input transistor has to be set during the resetting phase. Thusin this architecture the reset is done by a switch shorting the output of the pre-amplifier to its
input (RST switch in Fig. 4.3B). Such a solution not only ensures that the charge gatheredin the input node during the previous cycle is removed, but it also sets the appropriate selfconsistent operating point of the pre-amplifier.
In CMOS technology switches are usually implemented as a two transistor structure called
the transmission gate (or T-gate) shown in Fig. 4.6. It consists of a pair of pMOS and nMOS
transistors, where source of the nMOS is connected with the drain of pMOS forming an input
node, and vice-versa for the output node. The gates are connected to the digital steering
signal, opposite for the pMOS and nMOS. Therefore, either in both transistors are “on” orboth of them are “off”.
S
IN

OUT
S

Figure 4.6: Schematic of the transmission gate controlled by the steering signal S and its negation S.

A pair of nMOS and pMOS transistors is needed to allow the switch operation in the wholeavailable voltage range since a single nMOS transistor is not able to transmit the voltages close

59

4.1. Design overview

to the supply voltage (VDD ), whereas a pMOS can not transmit voltages close to the ground(VSS ). It is so, because they are not able to form a channel when the gate-source voltage(VGS )is below the threshold voltage. Nevertheless in some cases, when the full voltage swing
is not required, a single nMOS or pMOS transistor may be used as a switch. This was exactly
the case in the presented design where the input voltage range was already limited from thebottom by the VGS of the input transistor, thus for the resetting a single pMOS transistor was
sufficient.
Another issue connected with CMOS transistors used as switches, is a charge injection
occurring during switching them off. This is particularly crucial for the presented design since
any charge injected into the input node is processed in the exactly same way as the input charge
generated in the sensor. Thus this issue needs to be studied carefully. Once a switch transistor
is turned on a channel is created by the electrons (nMOS) or holes (pMOS) induced by thegate voltage. It allows for an easy current flow between source and drain so their potentials
are equalized. When the transistor switches off the charges gathered within the channel are
no longer attracted, the channel is shrinking and so charges move out through the drain andsource terminals. Thus it produces a tiny current flowing into the nodes connected to theseterminals. If that node has any DC path, it will just pass through without any long-term
consequences, but if that node is only AC coupled the injected charge will remain there. Thisissue is schematically shown in Fig. 4.7A.
"ON"

"OFF"

S
S
A) UncompensatedSS- - - - - -- - --- - --- - - - - - - -- -- - - -- - - - - - -S- -- -- - - -- - -- - - --dVB) CompensatedSS- - --- - - - - - - -- -- - - -- - - - - - -SS- - - - - -- - --- -- -- - - -SS-- - - - - -dV ~ 0Figure 4.7: Sketch showing the charge injection during switching off the transistor. The first case (A) presents the uncompensated switch, whereas in thesecond case (B) a dummy transistor is added to minimise the issue.

Since in the presented design the reset switch is connected between the output and the inputof the pre-amplifier some charge will be injected into these two nodes. The charge injection
into the output can be neglected since there is a DC current flowing from the power supply

60

Chapter 4. SOI detector prototype for general studies

line, through this node to the ground. Unfortunately, it is not the case for the input node,
which after reset is only capacitively coupled with the rest of the circuitry. Moreover, since
this is the input of the charge-sensitive pre-amplifier it will respond to the charge injection
exactly in the same way as to the charge induced in the sensor and thus its performance may
be deteriorated.
It is hard to overcome this issue since it is not obvious how the charge will be divided
between the drain and source terminal. In principle the division should be proportional to thetotal capacitances seen on these nodes but there are several factors that also contribute to thefinal division factor, for example the switching time. Beside that, the amount of charge in thechannel is also not constant, it highly depends on the input signal level, since it defines thegate-source voltage.
It is almost impossible to control this issue precisely but there are few solutions that may
reduce its impact. Usually a dummy transistor controlled by a reverse signal is added into
the sensitive node. Therefore, at the same time when the switch is turning off and injects the
charge, the dummy transistor is switching on and pulls this charge to form its own channel(Fig. 4.7B). Since it is hard to determine the amount of injected charge usually an assumptionof equal division is used and thus the size of the dummy transistor is two times smaller (to form
two times shorter channel). The main advantage of this solution is that both the switchingtransistor and the dummy transistor are seeing exactly the same input voltage (same VGS )therefore the dependence from the input signal it suppressed.

4.1.2

Column amplifier

During the matrix readout phase the signal from each pixel in a given row is redirected toa separate column amplifier. The global picture of the readout scheme is shown in Fig. 4.8A.
The column amplifier together with the storage capacitances located in the pixel form a fullydifferential switched capacitor amplifier. The main purpose of this device is buffering thesignal and shifting its common mode voltage to half of the supply voltage, which maximizes
the output voltage range.
The working principle of the amplifier in this configuration is presented in Fig. 4.8B (forsimplicity a single-ended version is presented). Switched capacitor circuits base on transferring
the charge gathered on the capacitance by switching it between different nodes, thus theiroperation is divided into non-overlapping phases. In the first phase (φ1 ) the amplifier circuit
is reset by shorting the output of the amplifier with its input, which removes all the charge
gathered across the feedback capacitance CF . At the same time the input voltage Vin is storedinon the CIN capacitance (which corresponds to the charge Qin = CVIN). After that, in thesecond phase (φ2 ) the C1 capacitance is switched to the input of the amplifier. Assuming theinfinite open loop gain of the amplifier, all the charge stored previously on C1 will now flow to
the CF capacitance, which will result in the output voltage equal to:
Vout = −Qin
CIN= −Vin ·CFCF(4.14)

61

4.1. Design overview
Following this relation a voltage gain in this amplifier configuration is defined by:
KV =

CIN
Vout
=−
Vin
CF

(4.15)

Therefore, such a configuration allows not only for the signal buffering but also for its amplification and this opportunity was utilized in the final design. By switching on and off anadditional capacitance into the feedback there are two possible gain settings: unity gain andmultiplication by a factor of two.
GAIN

CF2
CF1

COLUMNAMPLIFIER

1

1

RST

PIXEL

CL

C1

CL
RST

CF1
GAIN

CF2

(A) Scheme of the column amplifier.

CF
VOUT

CIN

READ
C2

2

VIN

1
2

VOUT

C
-VIN CIN
F(B) Working principle of the switched capacitor
amplifier.

Figure 4.8: Scheme and working principle of the column amplifier.

The core of each column amplifier is designed exploiting the fully-differential Recycling
Folded Cascode (RFC) amplifier architecture and is presented in Fig. 4.9. This architecture is
an improved version of a classic Folded Cascode (FC) which allows for the power consumption
reduction by a factor of two, maintaining its performance on the same level. A detailed
description of the RFC amplifier architecture and the comparison with its predecessor can befound in [36, 37].
To assure a proper voltage levels on the output of the fully-differential amplifiers an additional circuitry called Common Mode Feedback (CMFB) is required. It sets the averaged
output voltage (VCM = Vout+ +2 Vout− ) to the desired voltage level, which is usually a half of the

supply voltage since such a condition allows for the maximum output voltage range. There are
numerous CMFB circuits with their own pros and cons. In the presented design a switchedcapacitor CMFB architecture was utilized (shown in Fig. 4.9). The main advantage of thissolution is no static power consumption as well as no limitations in terms of the output voltage levels. On the other hand it requires an additional steering signals and does not provide
continuous output signal so the output voltage has to be sampled within a certain time period.
But in this particular case when the whole column amplifier is already based on a switchedcapacitor approach all these restrictions already exist. Therefore a phase control signals may
be shared between these two circuits. A wider discussion on the switched capacitor CMFB
can found in [38].

62

Chapter 4. SOI detector prototype for general studies

COMMON MODE FEEDBACK

RECYCLING FOLDED CASCODE
VDD

Vb3

Vb3
OUT OUT +IN IN +
Vb2

Vb2

Vb1

Vb1

φ1

φ2
VCM
Vb1

VSS

VCMFB

φ1

VCM

φ2

φ1

φ2

φ1

Vb1

φ2

φ1

VCM

φ2

Figure 4.9: Schematic view of the fully-differential recycling folded cascodearchitecture with the capacitive common mode feedback circuitry implemented
in column amplifier.

4.2

Simulations

To ensure the proper behaviour of the designed circuits numerous simulations were performed,
starting from the individual analysis of each single component of the readout chain and ending with a complete simulation of the whole design. It has to be pointed out that the usedtechnology is still being in the development phase, therefore the simulation models provided
by the vendor are not precisely tuned, and some of the possible issues may not show up in
the simulations. For example it was not possible to perform the Monte-Carlo simulation for
estimation of the pixel-to-pixel component mismatch, that may cause a gain variations. Nev-

70
60
50
40
30
20
10
0
5 uA
-10
10 uA
-20
15 uA
-30
10-4 10-2 100 102 104 106
Frequency [Hz](A) Open loop gain.

Phase [°]

Open loop gain [dB]ertheless, each cell passed a series of simulations which includes: transient simulations showing

108

180
160
140
120
100
80
60
40

5 uA
10 uA
15 uA

20
0
10-4 10-2 100 102 104 106
Frequency [Hz](B) Phase.

Figure 4.10: Pre-amplifier AC characteristics.

108

63

4.2. Simulations

the circuitry behaviour over the time, AC simulations that allows to ensure the amplifier stability and estimate its parameters, as well as DC simulations necessary to check the transistors
operating points.
The pre-amplifier AC characteristics showing its open loop gain and the output signal phaseare presented in the Fig. 4.10. One can see a minor dependence on the biasing current, withthe expected trend towards slightly faster response at the expense of the power consumption.
The stability summary showing the basic amplifier parameters as: gain, phase margin andgain-bandwidth product is presented in Tab. 4.1. It shows a gain of around 60 dB which isa reasonable value for a single stage amplifier, whereas the phase margin is around 60◦ whichis enough to ensure its stability.
Biasing
current [uA]51015

Gain [dB]

Phase margin [◦ ]

61.8
58.8
56.5

66.4
58.4
56.0

Gain-bandwidth
product [MHz]
138
178
191

Table 4.1: Pre-amplifier stability summary.

To evaluate the charge sensitivity of the pre-amplifier and its input dynamic range a seriesof transient simulations of the pre-amplifier response to input charge injection was performed.
The combined results together with fitted regression lines are shown in Fig. 4.11. Results arepresented for both high and low gain modes of the pre-amplifier and the linear regions havebeen marked with dark and light gray respectively. The input charge dynamic range is from
−1.8 fC up to 2.5 fC for the high gain and from −4 fC to 7 fC for the low gain. It covers
both signal polarities because the fabrication on different substrate wafer types was foreseen.
Nevertheless, there is a small asymmetry towards the positive input charges because p-type
Double SOI wafer was the primary choice.
Beside that, the charge to voltage conversion ratio can be obtained from the fitted functions:V+ 0.0025 [V ]
fC


V
L
∆Vout
[V ] = Qin · 0.1111+ 0.0014 [V ]
fC
H
∆Vout
[V ] = Qin · 0.2422



at high gain,(4.16)

at low gain.

(4.17)

They also show a negligible constant offset values (at the level of millivolts), but the simulations
do not take into account any sensor-related effects, such as leakage current, so there is no reasonh ifor any offset. Simulated values of charge conversion ratios are respectively GH = 0.2422
for the high gain mode and GL = 0.1111

h

V
fC

i

V
fC

for the low gain. Assuming the theoretical

relation given by Eq. 4.4 and taking the final values of the feedback capacitance as 4.17 fF in
the high gain mode and 9.375 fF in the low gain mode, one can compare the simulation results
h iwith the theoretical expectations. The calculated conversion ratios are: GH
th = 0.2398
and GLth = 0.1067

h

V
fC

i

V
fC

respectively, which is in a very good agreement with the simulations.

Similar simulations were performed for the column amplifier. Its AC characteristics are

64

Chapter 4. SOI detector prototype for general studies
High gain

Low gain

1.00

ΔVout[V]

0.75
0.50
0.25
0.00
-0.25

Nonlinearity [V]

-0.50
-0.75
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-10-8 -6 -4 -2 0 2 4 6 8 10 12 14 16
QIN[fC]
Figure 4.11: Pre-amplifier response to the input charge QIN injection. ∆Vout
represents the relative output voltage change, whereas nonlinearity represents
the deviation from the fitted regression line.

shown in Fig. 4.12 and the obtained parameters in the Tab. 4.2. Here also a consistent behaviour over the biasing current setting is observed. The open loop gain is on the similarlevel as in the pre-amplifier, which is expected since column amplifier also incorporates single
cascoded amplifying stage. The stability of this device is very good with the phase margin over90◦ , whereas its gain-bandwidth product is much lower due to much higher output capacitance.
Biasing
current [uA]51020

Gain [dB]

Phase margin [◦ ]

58.0
58.4
59.9

91
92
91

Gain-bandwidth
producs [MHz]
4.2
4.8
5.8

Table 4.2: Column amplifier stability summary.

To check the input dynamic range of the column amplifier, similarly to the previous case,a set of transient simulations with different input voltage amplitudes was executed. The
combined results are shown in Fig. 4.13. Since it is a fully differential amplifier the input−+
signal is given by a voltage difference on its two input terminals Vin = Vin− Vin. Because−+
both Vin
and Vinmay vary from 0 to 1.8 V (supply voltage), the effective input voltage range

is from −1.8 to 1.8 V.

65

4.3. Measurements setup

40
20

Phase [°]

Open loop gain [dB]

60

0
-20
-40
-60
-80
10-2

5 uA
10 uA
20 uA

100

102 104 106
Frequency [Hz]

108

1010

180
160
140
120
100
80
60
5 uA
40
10 uA
20
20 uA
0
10-2 100 102 104 106
Frequency [Hz](A) Open loop gain.

108

1010

(B) Phase.

Figure 4.12: Column amplifier AC characteristics.

As mentioned earlier two different working modes of the column amplifier were implemented: buffering (unity gain) and amplifying (doubling the signal). The simulated gain canbe extracted from the fitted functions:
Buf
∆Vout
= Vin · 0.994

buffering mode,(4.18)Amp∆Vout= Vin · 1.978

amplifying mode.

(4.19)The simulated gains of GBuf = 0.994

h i
V
V

for the buffering mode and GAmp = 1.978

h i
V
V

for

the amplifying mode are in very good agreement with the design assumptions. Moreover, thesimulated offset was negligible (on the order of several microvolts). The input dynamic range,
for which the amplifier response remains linear, was determined as [-1.1 : 1.1] and [-0.55 : 0.55]
respectively and is marked with a dark and light gray boxes.
Usually the noise performance of the readout chain (especially the input stage) is also
a subject of a detailed simulations. Unfortunately, provided technology parametrization does
not allow for a reliable noise simulation thus the noise optimisation was not possible.

4.3

Measurements setup

After finishing the design and simulation phase, the project was sent for fabrication and theextensive work on the measurement setup preparation had began. A dedicated readout system
had to be prepared from the scratch, which means: design of the printed circuit board (PCB),
selection of a readout control hardware platform and development of appropriate firmware, as
well as the development of a data acquisition software (DAQ). The author of this thesis wasdeveloping the DAQ, whereas other tasks were entrusted to other members of the group.
The main purpose of the PCB design was to provide a set of appropriate biasing voltages
and currents, retrieve the analog output signal from the chip and digitize it, as well as assure
the communication with the chip necessary to control its behaviour. Since this required incorporation of quite a lot of electronics it has been decided to split the PCB design into two

66

Chapter 4. SOI detector prototype for general studies
High gain

Low gain

1.50

Vout[V]

1.00
0.50
0.00
-0.50
-1.00

Nonlinearity [V]

-1.50
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-2 -1.5 -1 -0.5 0 0.5
Vin[V]

1

1.5

2

Figure 4.13: Column amplifier response on the input voltage change, where−−++
and Vout = Vout
− Vout. Nonlinearity represents the deviation− Vin
Vin = Vinfrom the fitted regression line.

boards. The “mother” board containing all functional circuitry, and the second small “mezzanine” board with the chip glued and bonded to it. This solution gives a lot of flexibility interms of the number of potentially tested assemblies, since it does not require the unnecessary
multiplication of all of the “mother” board electronics, which highly reduces the overall costs.
The photographies of the manufactured and assembled PCB boards are shown in Fig. 4.14.
The final design incorporates a 16-channel digital to analog (DAC) converter (DAC128S085 )with voltage buffers and voltage to current converters for biassing the chip. The analog
signal information from the chip is being retrieved by a fully differential instrumentation
amplifier which drives a high speed 12-bit differential analog to digital (ADC) converter(AD9235BRUZ ). The digitized information is sent further through the VHDCI connectorsthat assure the communication between the readout control system and the “mother” board.
The readout control system bases on the commercially available Genesys Virtex-5 FPGA
Development Board, which gives a possibility to include a lot of functionalities within the
FPGA firmware. Thus, the FPGA provides the digital steering signals for the chip and readoutboard, controls ADC operation, buffers the digitized data and forms the data frame structure.
Moreover, a TCP/IP protocol was implemented in the FPGA firmware to allow the efficient
data transfer between the control board and PC via the Ethernet connection.

4.3.1

Data acquisition software

As mentioned earlier, the dedicated data acquisition software was developed by the authorof the thesis. Since it has to have quite a wide range of functionality it was written in C++

67

4.3. Measurements setup(B) “Mezzanine” board.

(A) “Mother” board.

(C) Close-up on bonded chip.

Figure 4.14: Photographies of readout boards with all the components soldered
and chip bonded.

exploiting existing libraries from the ROOT Data Analysis Software and Boost [39]. The
software was responsible for controlling the FPGA operation, so a set of basic commands
understood by the FPGA was introduced. They allow for setting a desired conditions for thedetector operation (as biasing currents and voltages levels, on-chip electronics settings likefor example amplifiers gains, and so on). Beside that, they allow for the measurement flow
control through the commands starting, stopping or pausing the ongoing measurement. Since
the whole communication was done through the Ethernet connection the implementation of
TPC/IP socket was necessary. Along that, the integration with another detection system,
the beam-test telescope [40], was also needed. To allow a synchronous operation of these
two systems a separate TCP socket was implemented to listen and interpret the commands
broadcasted by the telescope control software.
The software was also intended to receive the row data coming from the FPGA and store
them. For that purpose a ROOT TTree structure was incorporated. Thus all the row data
are stored in separate TTree leafs containing the informations about the signal amplitude oneach pixel in a given frame, the frame ordinal number and the time-stamp attached to it.

68

Chapter 4. SOI detector prototype for general studies

Moreover, each tree contains also some basic information about the settings used during themeasurements. Beside that, for easy measurements tracking an automatic log file was created,
containing the summary information for each run.
To increase the utility of the DAQ control software a Graphical User Interface (GUI), based
also on the ROOT libraries, was added. It provides all the functionality required from thedetector user point of view. There is a possibility to set all the biasing levels, chip settings,
number of frames to be taken or the output file name. Moreover, within a GUI there isa separate section that allows for the basic online data quality monitoring. Every n-th frame(where n can be set) is displayed on the user interface and also a mean frame value is calculated
and shown on a separate plot. Thus, an immediate check of the detector behaviour is possible.
Even if all these side amenities provide a very useful features, they should not affect themain purpose of a DAQ software which is of course receiving and saving the data. Therefore,
to not limit a data link throughput, by involving significant fraction of computation time into
the side tasks, a multi-threading was implemented. Once a separate thread is created for thedata socket, its performance is no longer affected by the other software parts. In the final
version of the DAQ separate threads were assigned also to the data monitoring features, GUI
and telescope socket, which allows for its fluent operation, regardless of the conditions.

4.4

Data analysis software

The functionality expected from the data analysis software for the SOI detector designed in
Cracow was very similar to the one for the INTPIX6 detector. Since the data analysis software
for the INTPIX6 had been already well developed and its operation verified the core of thesoftware was reused. Only minor changes were needed to adapt the system to a sightly different
input data format and detector geometry. Whereas all the algorithms for pedestal and noise
calculation, signal extraction and clusterization remained the same.
The whole analysis flow is also very similar to the one already introduced for the INTPIX6
detector in section 3.3. Thus only a brief reminder will be presented here with the focus on
the parts that are different.
In the first step the data file is loaded. After that, in the INTPIX6 software the bad frames
are rejected, but for this system there are no issues affecting the data quality during the dataacquisition, thus this step is omitted. Directly after loading the data file the pedestal and noiseare calculated for each pixel in the matrix, using the “calibration” sample (no signal source).
Later on a true data sample is processed. For each frame the signal is extracted from the raw
data and hits are formed using the two threshold clusterization method. The default setting
for the thresholds was 6σ for the seed and 2σ for the neighbours. Before creating the final hits
sample, cuts are applied to rejects all clusters touching the detector borders. In the end theprocessed hits informations are stored in the output data file and basic plots (as pedestal andnoise distributions, hit energy spectra) are displayed. In the INTPIX6 software there was also
a procedure for the pixel gain calibration, but since the matrix size in our prototype is muchsmaller it does not show similar misbehaviour, and thus this step was skipped in the analysis
flow.

69

4.5. Spotted issues

4.5

Spotted issues

There were several issues spotted during the measurements. Thus to assure the reliability ofthe presented results, it is necessary to clearly introduce all of them. For this reason someof the measurement results have to be shown already in this paragraph, without the in-depth
examination which is presented in subsequent sections.
First of all an unexpected behaviour was noticed during applying a high voltage to the backplane of the DSOI(p) wafer. As it can be seen in Fig. 4.15A the current consumption starts torise significantly after exceeding −50 V, preventing further depletion development. Using theinformation from other measurements it can be concluded that it happens at about 150 µm, far
before reaching the full depletion, since the full sensor thickness is two times larger. Designed
detectors allow for the high voltage application either directly to the backside metallisation or
through the contacts located on top of the sensor, but according to the presented results theissue is present independently from the polarization method. It should be also noticed that thepedestal shown in Fig. 4.15B does not follow the trend observed for the current consumption.
This means that this issue is not related with the increased leakage from the sensor matrix
volume, whereas it took place at some part of the detector located outside the matrix. The
origin of such behaviour is not known, but most probably it is attributed to the problems
during the production or handling of this type of wafer, since it was found also on different
prototypes.
Another observation is that the energy spectra taken with the CPA matrix on the DSOI(p)wafer deteriorates significantly after exceeding −50 V of back bias. It may be connected withthe previous issue, but it is not straightforward since it is observed only in the sub-matrix withthe large sensing implant, whereas the one with small diode seems to be insensitive. Plots
showing this behaviour are presented in Fig. 4.16. As it can be seen, a significant degradationof the spectra sharpness is visible only for the CPA(large) at −60 V (Fig. 4.16D). Moreover,

Back
Top

Current [uA]

102
101
100

10-1
10-2
0

20 40 60 80 100|Back bias voltage| [V](A) Current consumption
from the back bias voltage
power supply.

Mean pedestal [ADU]

103

2040
2030
2020
2010
2000
1990
1980
1970
1960
1950
1940
1930

SF
CPA (small)
CPA (large)

20 30 40 50 60 70 80|Back bias voltage| [V](B) Mean pedestal.

Pixel noise [ADU]

similar lost of performance does not reveal in the pixel noise (Fig. 4.15C) or the change of the

7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5

SF
CPA (small)
CPA (large)

20 30 40 50 60 70 80|Back bias voltage| [V](C) Mean pixel noise.

Figure 4.15: Results from the DSOI(p) wafer showing the unexpected detector
behaviour.

70

Chapter 4. SOI detector prototype for general studies

pedestal (Fig. 4.15B). The baseline is stable across the whole back bias range, whereas the
pixel noise (for this matrix only) is even improving with the increase of the bias voltage.
103

3 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

103
102

CountsCounts102

Combined

10

3 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

10

1

1
0

200

400
600
800
Energy [ADU]

1000

1200

0

(A) CPA(small), −40 V of back bias.
103
102

200

400
600
800
Energy [ADU]

1000

1200

(B) CPA(large), −40 V of back bias.

Combined

3 hit cluster

Combined

3 hit cluster

1 hit cluster

4 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

2 hit cluster>4 hit cluster

103
102

CountsCountsCombined

10

10
1

1
0

200

400
600
800
Energy [ADU]

1000

1200

0

(C) CPA(small), −60 V of back bias.

200

400
600
800
Energy [ADU]

1000

1200

(D) CPA(large), −60 V of back bias.

Figure 4.16: Example of 241 Am spectra taken with the prototype fabricated on
DSOI(p) wafer. Different colours represent individual contributions from given
cluster sizes, whereas black curve shows the combined spectrum.

102

Combined

3 hit cluster

Combined

3 hit cluster

1 hit cluster

4 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

2 hit cluster>4 hit cluster

103
102

CountsCounts

103

10
1

10
1

0

100 200 300 400 500 600 700 800 900 1000
Energy [ADU](A) FZ(n) wafer, CPA(small) sub-matrix.

0

100 200 300 400 500 600 700 800 900 1000
Energy [ADU](B) FZ(n) wafer, CPA(large) sub-matrix.

Figure 4.17: Example of 241 Am spectra showing the divergent behaviour of
sub-matrices that differ only in the sensing implant size (both at 70 V of backbias).

4.6. Radioactive source measurements

71

A similar unexpected behaviour of the CPA(large) sub-matrix is observed also on the FZ(n)wafer. Contrary to the theoretical expectation pixels with the small diode show good spectra
quality, whereas the sub-matrix with the large one shows a blurred image as presented inFig. 4.17. Similarly to the DSOI(p) wafer no major difference in the pixel noise is observed
comparing these two sensor geometries. Other than for the DSOI(p) wafer, for the FZ(n) such
behaviour persists for the whole back bias voltage range, from 10 V up to 200 V (which is far
above full depletion).
Summarizing the main issues found during the measurements, the incomprehensible performance of the CPA(large) sub-matrix has been spotted. Thus the results will be presented
mainly for the SF and CPA(small) sub-matrices. Moreover, when comparing the outcomes fordifferent wafers, one has to remember that the full depletion of the DSOI(p) sensor was notpossible, which may complicate drawing of the final conclusions.

4.6

Radioactive source measurements

Similarly to the INTPIX6 detector measurements, the 241 Am source was used to calibrate thedetector. Since the presented device is sensitive to the visible light, all the measurements havebeen carried out within a light-sealed box. If not specified otherwise, the results for the FZ(n)wafer are presented for the back bias voltage set to 70 V, whereas for the DSOI(p) to −50 V.
The example of 241 Am spectra for both FZ(n) and DSOI(p) wafers, for each readout
architecture and two different pre-amplifier gain settings are presented in Fig. 4.18 and Fig. 4.19
respectively. Different colors represent contributions from different cluster sizes, whereas theblack curve shows the combined result. For consistency the energy scale is the same for allcases except the SF matrix for the DSOI(p) where the signal is almost order of magnitude
lower. It is clearly visible that the obtained results are highly dependent on the substrate
wafer.
Source-followers behave much better on the FZ(n) wafer (Fig. 4.18A) than on the DSOI(p)(Fig. 4.19A). For the FZ(n) wafer all expected energy lines are clearly distinguishable bothon the combined spectra and on the individual ones. This in not the case for the DSOI(p)where only highest energy line (59.5 keV) is well separated. Nevertheless, such a behaviour was
expected since the DSOI(p) is characterized by much larger pixel capacitance, what directlyreduces the signal amplitude (which is also visible comparing these two plots).
The situation is completely different for the CPA architecture, where the results obtainedwith the DSOI(p) (Fig. 4.19B and Fig. 4.19C) are not deteriorated. All energy lines are well
separated for both low and high pixel gain settings. An unexpected behaviour is observed
for the FZ(n) wafer (Fig. 4.18B and Fig. 4.18C), for which the spectra quality seems to be
decreased. Moreover, comparing the peak positions, also for this architecture the pixel gain
seems to be wafer dependent. Independently from the pre-amplifier gain setting the measurements show that for the FZ(n) wafer the pixel gain is lower than for the DSOI(p), which should
not be the case. In principle, the pixel gain in this architecture should be independent from thewafer type, since it is determined only by the feedback capacitance (which obviously should

72

Chapter 4. SOI detector prototype for general studies

104

Counts10

3

Combined

3 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

102
10

1
0

100

200

300

400 500 600
Energy [ADU]

700

800

900 1000(A) FZ(n) wafer, SF sub-matrix.

Counts10

3

Combined

3 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

102

10

1
100

0

200

300

400 500 600
Energy [ADU]

700

800

900 1000(B) FZ(n) wafer, CPA(small) sub-matrix, low pre-amplifier gain.
103

Combined

3 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

2

Counts

10

10

1
0

100

200

300

400 500 600
Energy [ADU]

700

800

900 1000(C) FZ(n) wafer, CPA(small) sub-matrix, high pre-amplifier gain.
Figure 4.18: The examples of 241 Am spectra taken with INTPIX6 FZ(n).

734.6. Radioactive source measurements

104

Counts103

Combined

3 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

102
10
1
0

20

40

60

80 100 120
Energy [ADU]

140

160

180

(A) DSOI(p) wafer, SF sub-matrix.

103

Combined

3 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

Counts

102

10

1
0

100

200

300

400 500 600
Energy [ADU]

700

800

900 1000(B) DSOI(p) wafer, CPA(small) sub-matrix, low pre-amplifier gain.

103

Combined

3 hit cluster

1 hit cluster

4 hit cluster

2 hit cluster>4 hit cluster

2

Counts

10

10

1
0

100

200

300

400 500 600
Energy [ADU]

700

800

900 1000(C) DSOI(p) wafer, CPA(small) sub-matrix, high pre-amplifier gain.
Figure 4.19: The examples of 241 Am spectra taken with INTPIX6 DSOI(p).

74

Chapter 4. SOI detector prototype for general studies

be independent from the substrate wafer). Since such a behaviour was observed perpetuallyfor all the measurements, its origin had to be investigated.
To examine this issue quantitatively the calibration plots for each configuration can beused, which are presented in Fig. 4.20 together with the fitted regression lines. First of all, it isworth to notice that all fitted curves are passing close to the origin, which is expected. Beside
that, the linear coefficients (Ax ) can be translated into the charge to voltage conversion ratioof the input stage. For that purpose the voltage gain of the whole readout chain behind the
input stage has to be estimated and the voltage corresponding to one ADC unit has to be
known. The latter is determined by the ADC configuration andits ivalue may be taken fromhthe data sheet. In our case 1 ADU = 488 µV (GADC = 488
1

µV
ADU

). The determination of

the former is much more complex since it depends both on the PCB design as well as the chip
design. In first approximation the amplification on PCB was set to unity (GP CB = 1[ VV ]) andalso the on-chip column amplifier gain was set to unity. However, because of slight differencesin the in-pixel signal storage capacitances between the SF and CPA architectures, the effective
gain of the column amplifier differs. Basing on the design it is equal to unity for CPA matrix

350
FZ(n)
DSOI(p)Peak position [ADU]

300
250

1

8
0.

6x

200
y

150

=

6
4.

57

100

y

50

1.
71x= 1.

00

1020 30 40 50
Energy [keV]60(A) Source-Follower.
900

900
FZ(n) Low gain
DSOI(p) Low gain

700
600
500

61

400
y=

300
200

y=

100

FZ(n) High gain
DSOI(p) High gain

800
Peak position [ADU]

Peak position [ADU]

800

3.
4x7
.
7

0.43
55x+

5.

700

6
.4

-8
8x

.8

600
500

y

=

400
y=

300

13

3.6
x+
0
.1

6

8

200
100

0

0
0

10

20 30 40 50
Energy [keV]60(B) CPA(small) with low gain setting.

010

20 30 40 50
Energy [keV]60(C) CPA(small) with high gain setting.

Figure 4.20: Calibration curves for detector prototype designed in Cracow.

75

4.6. Radioactive source measurements
A(GCP
chip = 1h i
VV), whereas for the SF matrix GSF
chip = 0.9

h i
V
V

. Assuming that 3.6 eV is needed

to produce one electron-hole pair, one can obtain the charge to voltage conversion ratios (Gx )for each configuration, according to:


Gx

"

#

ADU
eV
V
e−
V
= Ax
· 3.6 − · 6241.5· Gchip
fC
eV
e
fC
V
















· GP CBVV· GADCV
ADU

(4.20)
The combined results of the measured and simulated charge to voltage conversion ratios foreach configuration are presented in Tab. 4.3. Now the high discrepancy of the results obtained
for the charge pre-amplifiers on different wafers is clearly visible. Beside that, for both wafers
and both gain settings there is also a significant deviation from the values expected from thesimulations.
Architecture
SF
CPA

Gain
—
Low
High

FZ(n)
0.04600.06090.0888

DSOI(p)0.01690.08490.1522

Sim—
0.1111
0.2422

Table 4.3: Measured and simulated charge to voltage conversionhratios
i of theV
input stage for different architectures and wafers, given in f C .

The conversion ratios are directly determined by the capacitances in the input stage (total
input capacitance in case of the SF architecture and feedback capacitance for the CPA – asdescribed in Sec. 4.1). Therefore, from the measured conversion ratios one can calculate theexperimental values of the corresponding capacitances (CIN and CF ). It can be done according
to the equations 4.1 and 4.4 introduced previously.
The resulting capacitances are presented in Tab. 4.4. First of all, basing on the results for
the SF matrix it is clear that introducing an additional Middle Si layer (DSOI(p) case) highly
increases the detector capacitance. This is not obvious, since in the standard approach thesensor capacitance is usually determined by the plate capacitor formed between the sensing
implant and the back plane (or the end of the depletion zone for not fully depleted devices).
Whereas, here the origin has to be different, since even taking into account different thicknessesof the depletion depths for these two sensors, such a difference can not be explained.
Architecture
SF
CPA

Gain
—
Low
High

FZ(n)
21.75
16.43
11.26

DSOI(p)
59.26
11.78
6.57

Sim
—
9.38
4.17

Table 4.4: Experimentally estimated and intended capacitances determining
the gain of input stage (total input capacitance for SF architecture and feedback
capacitance for CPA) for different wafers, given in [f F ].

To estimate the total input capacitance of the detector fabricated on the standard SOI
structure, one has to take into account also the coupling between the sensing implantationand the electronics. As presented in Fig. 4.21A in the standard SOI the parasitic capacitances

76

Chapter 4. SOI detector prototype for general studies

to the transistors diffusion layer appear. Since the distance between the sensing implant andtransistor layer is usually few orders of magnitude lower than the distance to the back plane,these capacitances provide a significant contribution to the total capacitance. Thus for the
standard SOI, to determine the total capacitance of the input node one has to take into accountthe dispersed capacitance to the electronics, the coupling to the back plane, as well as the gate
capacitance of the input transistor.
The situation looks different for the Double SOI wafers, where the Middle Si layer separates
the sensing implant from the electronics, as sketched in Fig. 4.21B. Thus in this case instead ofthe dispersed capacitance to the electronics one has to take into account the coupling between
the sensing implant and the Middle Si. Its contribution is even more pronounced since theMiddle Si covers almost the whole sensor area. Moreover, the insulator thickness separating
appropriate layers is usually lower in the Double SOI case, which further emphasise the differences. This explains qualitatively the significant difference in the total input capacitanceobserved for the SF matrix.
VMidSi

MidSi

SiO2

SiO2

CD2

BPW

CD2

CD1

BPW

CD1

n

n

n+

n+
HV

HV

(A) Single SOI case.

(B) Double SOI case.

Figure 4.21: Elementary sensor parasitic capacitances contributing to the total
input capacitance.

The precise estimation of the parasitic coupling between the sensing implant and electronics
par) is impossible without a proper tools, but one can try to estimate it assuming that each(CDcomponent forms a plate capacitor with the BPW layer:parCD= 0 rAd(4.21)

where: 0 and r are vacuum permittivity and relative permittivity of the insulator layer, A is
the plate area and d is the distance between plates. The electronics active area can be taken
directly from the layout, whereas the thickness of the silicon dioxide separating the electronics
layer from the handling wafer is unfortunately not known precisely. According to the basicparspecification of the wafers it should be around 150 nm. This gives a CDof about 7.5 fF forthe standard SOI case. The input transistor gate capacitance is around 10 fF, which gives

in total 17.5 fF. Taking into account the parasitic capacitance coming from the electronics
interconnection, which should add several femtofarads, it agrees very well with the measured
value of 21.75 fF.

4.6. Radioactive source measurements

77

For the Double SOI the effective plate area of the parasitic contribution is imposed by the
BPW layer size. Thus for this wafer the coupling between BPW layer and the Middle Si gives
above 40 fF. Including 10 fF from the input transistor and the interconnections it also matches
the measured 59.26 fF.
Now moving to the puzzling behaviour of the charge pre-amplifiers, one may suspect thatit originates in insufficient open loop gain, since its high value is required to become independent from the input node capacitance. But in such a case the larger the detector capacitancethe higher signal deterioration should be observed. As already presented, based on the results for the SF matrix, the sensor capacitance for the DSOI(p) is much larger than for the
FZ(n), thus eventual signal degradation would mostly appear on the DSOI(p) wafer. Since
the effect is completely opposite and what’s more, there are no differences between the submatrices with small and large sensing node, the open loop gain of the pre-amplifier has to belarge enough. Therefore the spotted issue most probably originates in the discrepancy in the
feedback capacitance.
One can notice that for the DSOI(p) wafer the difference between the designed capacitanceand the measured one is almost identical for both low and high pre-amplifier gain settings. Thisadditional 2.4 fF can be attributed to the parasitic capacitance introduced by the electronics
interconnections. Unfortunately, since the used technology in not fully parametrized, theparasitic extraction tool can not be used to anticipate its value, but several femtofarads are
expected.
Even if the situation seems to be clear for the DSOI(p) wafer, it does not explain the further
capacitance increase for the single SOI. In principle the parasitic capacitance coming from theinterconnections should not depend on the substrate, thus there has to be an additional factor
revealing only on the single SOI wafer. Also in this case the difference between simulation andmeasurements is very similar independently from the gain settings, which means that mostprobably it also comes from some parasitic capacitance parallel to the feedback capacitance.
Subtracting 2.4 fF coming from the interconnections, there is still about 4.7 fF from unknown
source. Having in mind the differences between the standard SOI and Double SOI spotted with
the SF matrix one can find out that similar mechanism may cause the observed behaviour.
Since in the standard SOI there is a significant coupling between the electronics layer andthe sensing implantation, all of the source and drain terminals belonging to the pre-amplifier
output node are forming a capacitance parallel to the feedback capacitance, as it is presented
in Fig. 4.22. Its value obtained by a rough estimation is around 3 fF. Now, concerning the
Double SOI there is no direct coupling between the electronics layer and sensing node since
they are shielded by the Middle Si layer, thus there is no additional capacitance between the
input and output of the pre-amplifier. So finally, after taking into account all the discussed
effects, the outcomes from the 241 Am source measurement results that looked a bit strange
on the first glance, can be fully understood. Moreover, they have provided an important
knowledge about the SOI technology for future designs.

78

Chapter 4. SOI detector prototype for general studies

Vb3

RST

Vb2

CF

F1

CS1
VOUT1

READ
F2

VOUT2
CS2

HV
Figure 4.22: Parasitic capacitances between the sensing node and pre-amplifier
output influencing its charge to voltage conversion coefficient.

4.6.1

Energy resolution

Once having the energy calibration done, the measured pixel noise given in the arbitrary ADU
units can be recalculated into the ENC (introduced in Sec. 3.6 on page 44). The example ofpixel noise spectra for both the FZ(n) and DSOI(p) wafers are shown in Fig. 4.23 separately
for all sub-matrices, with the mean values (after boundary pixel rejection) given in the legend.
Since for the most conclusive sub-matrices (SF and CPA(small)) the noise dependence fromthe back bias voltage was marginal (as shown in Fig. 4.15C), the results will be presented only
for the default conditions. These are 70 V for the FZ(n) wafer (its full depletion voltage) and−50 V for the DSOI(p) (highest voltage without strange leakage occurrence).

(A) FZ(n) wafer at 70 V.

(B) DSOI(p) wafer at −50 V.

Figure 4.23: Example of pixel noise spectra for each sub-matrix.

The mean pixel noise values for all different cases are summarized in Tab. 4.5 for consistency, whereas much more conclusive values of the corresponding ENC are presented in79

4.6. Radioactive source measurements

Tab. 4.6. The results for the CPA(large) on the FZ(n) wafer are marker with red to remindthat these values may not be representative because of the issue spotted on this sensor geometry (introduced in Sec. 4.5).
Wafer
FZ(n)
DSOI(p)Pre-amp Gain
low
high
low
high

SF
1.87
1.75

CPA(small)
3.19
3.85
4.54
6.46

CPA(large)
3.13
4.40
3.79
5.06

Table 4.5: Mean pixel noise given in ADU (FZ(n) wafer at 70 V, DSOI(p)wafer at −50 V).

Wafer
FZ(n)
DSOI(p)Pre-amp Gain
low
high
low
high

SF
111
284

CPA(small)
160
132
163
129

CPA(large)
157
150
136
101

Table 4.6: ENC values for all sub-matrices on different wafers, given in electrons (FZ(n) wafer at 70 V, DSOI(p) wafer at −50 V).

As one can see for the FZ(n) wafer the best performing sub-matrix is the one with thesource-follower in the input stage having the ENC of 111 electrons. The CPA architecture withhigh gain behaves slightly worse, with about 20 electrons more. On the DSOI(p) wafer the SF
performance is highly degraded, which is naturally driven by much higher sensor capacitance.
With this substrate the usage of charge pre-amplifier architecture is much more beneficial. The
noise performance of the CPA(small) seems to be almost independent on the wafer showing
roughly the same ENC value of about 130 e− for the high gain and 160 e− for low.
In spite of the incomprehensible behaviour of the CPA(large) sub-matrix on the DSOI(p)wafer after exceeding −50 V, for lower back bias voltages this architecture provides the bestenergy resolution with the ENC of 101 e− for the high gain. It is not clear why there is sucha difference in favour of the large collection diode and unfortunately it can not be cross-checkedwith the results from the FZ(n) wafer.
Beside the conclusions regarding the best performing architecture, it is worth to noticealmost a constant difference in ENC of about 30 e− between the low and high pre-amplifier
gain setting for all conclusive results for the CPA architecture. This suggests that a significant
amount of noise comes from the readout electronics located after the pre-amplifier. Thus, if
the signal becomes amplified in the input stage the relative influence from the further noise
sources becomes less substantial.
Summarizing, the observed performance providing the ENC values close to 100 e− is a very
good result, especially taking into account that it was obtained with a test device. What iseven more promising, it seems that there is still quite a lot of room for further improvements
in terms of the energy resolution, since all of the noise sources after the input stage may byfurther suppressed by a proper readout electronics design.

80

Chapter 4. SOI detector prototype for general studies

4.7

Spatial resolution

Beside the spectroscopy capabilities, for some applications the spatial resolution and tracking
potential are of the main interest, as for example in the vertex detector of high energy physics
experiment. The spatial resolution usually depends on the precision of the charge measurement(at least for non-binary readouts), but the overall tracking performance is a way more complex
subject. Thus, the separate studies, aimed to verify the spatial resolution of the presented
device, were performed by the other member of the group [41]. Despite the results are notdirectly obtained by the author of this thesis, it is worth to quote the most relevant results to
get thorough overview of the detector performance.
The studies of the spatial resolution were performed in CERN SPS North Area at H6 beamline in collaboration with the CLICdp group. For that purpose a pion beam of 120 GeV wasused. The examples of energy spectra from the beam tests are presented in Fig. 4.24A andFig. 4.24B for the FZ(n) and DSOI(p) wafer respectively. At 120 GeV pions can be treatedas the minimum ionising particles (MIP), thus the energy distributions undergo the Landau
distribution (or precisely speaking the convolution of Landau and Gaussian functions).
Since for the MIP-like particles ionisation takes place along their whole path within thesensor, they can be used to study the depletion depth. For that purpose a set of measurementswith different back bias voltages were performed. The combined results are shown in Fig 4.25,
where the most probable value (MPV) of the measured energy is plotted in a function of
the square root of back bias voltage. As it can be seen for the FZ(n) wafer the measured
energy grows proportionally to the depletion depth and saturates at around 70 V, when thefull depletion is reached. Thus, for the FZ(n) wafer the full depletion voltage is 70 V. Knowing
the full depletion voltage and the sensor thickness one can estimate the substrate resistivity
according to equation 1.11 (introduced on page 7). Obtained resistivity is around 12.3 kΩcm,
which is much higher than 2 kΩcm declared by the manufacturer.

FZ(n)

700

CPA(large)

600

CPA(large)

103

CPA(small)

500

CPA(small)

SF

SF

CountsCountsDSOI(p)

400
300

2

10

10

200
100
0
0 200

1
600

1000 1400 1800 2200
Energy [ADU](A) FZ(n) wafer at 130 V.

0 200

600

1000 1400 1800 2200
Energy [ADU](B) DSOI(p) wafer at −70 V.

Figure 4.24: Examples of energy spectra from the beam test data. Obtainedwith 120 GeV pions. Plots from [41].

81

4.7. Spatial resolution
CPAsmall
1200

CPAlarge

FZ(n)

600

800
600
400
200
0

DSOI(p)500
Energy [ADU]

Energy [ADU]

1000

SF

400
300
200
100

2

4
6
8
10 12 14
Sqaure root of back bias [V0.5]

0

16

1

2

3
4
5
6
7
8
Sqaure root of back bias [V0.5]

9

Figure 4.25: Most probable value of energy deposited by 120 GeV pions infunction of square root of back bias voltage. Plots from [41].

One can also notice that the most probable energy value literally saturates after 70 V only
for the SF sub-matrix, whereas for the both CPA sub-matrices it starts to decrease slightly.
Unfortunately, the origin of such behaviour was not found.
In case of the Double SOI, it is clear that the full depletion has not been reached, since
there is no plateau region. Assuming that the amount of charge induced per travelled distanceis the same for both wafers, and taking into account the measured charge to voltage conversion
ratios, one can conclude that the DSOI(p) wafer can be depleted up to about 150 µm.
Finally, the spatial resolution in function of back bias voltage is presented in Fig 4.26. For
the FZ(n) wafer all matrices show a very good performance, with the resolutions below 3 µm
after the full depletion. The best result is obtained with the SF sub-matrix which reaches∼2.3 µm at 100 V.
CPAsmall
3.8

3.2
3
2.8
2.6
2.4

DSOI(p)7

Y resolution [um]Y resolution [um]

3.4

SF

7.5

FZ(n)

3.6

2.2

CPAlarge

6.5
6
5.5
5
4.5
4

0

20

40

60
80 100Back bias [V]

120

3.5

0

10

20

30 40 50
|Back bias| [V]Figure 4.26: Plots showing the spatial resolution in function of back bias
voltage, separately for each sub-matrix and wafer type. Plots from [41].

60

70

82

Chapter 4. SOI detector prototype for general studies
For the Double SOI the results are slightly worse. The performance of SF matrix on

the DSOI(p) is naturally deteriorated by the high sensor capacitance. Whereas the spatial
resolution of the CPA architecture (which is much less sensitive to the increased sensor capacitance) fluctuate between 4 and 5 µm. The direct comparison between these two wafers is notstraightforward. One has to remember that there is a significant difference in the input signal
amplitude between the FZ(n) and DSOI(p), in favour of the first one. This is caused by the
problems with full depletion of the DSOI(p) sensor.

83

Chapter 5

CLIPS detector design
After the very promising results obtained with the first detector it was decided to designa next one, however no longer a general purpose test device, but this time targeting a specificapplication. Since group of AGH University has been already involved in several designs ofdetectors for high energy physics experiments, it was a natural direction. The choice fell on
the vertex detector for the Compact Linear Collider (CLIC) experiment. Since it is a lepton
collider, the main weakness of the SOI devices, which is the poor TID radiation hardness, is not
an issue. The radiation levels even for the vertex detector (located closest to the interaction
point) are low enough.
CLIC is currently during advanced R&D phase and so there are intensive searches for novel
solutions able to fulfil its demanding specifications. The SOI seems to be a very attractive
technology for the tracking devices, since there are almost no limitations in terms of pixel
granularity and so a very fine spatial resolution can be achieved. Thanks to its monolithic
nature the SOI detectors come ahead the growing demands on the material budget limitation. Moreover, there is a full CMOS process available, which is necessary to provide all thefunctionality required from the on-chip readout electronics. Beside that, currently there isno device which is able to simultaneously meet all the requirements set for the CLIC vertex
detector, so it is a good opportunity for developing a state-of-the-art detection system.
The main requirements for a single plane of the CLIC vertex detector are presented in
Tab. 5.1. To fulfil all of them simultaneously, substantial modifications have to be implemented
comparing to the previous design. First of all, a single point resolution below 3 µm has to beobtained with much thinner sensor. Moreover, in the first design the measurement of thearrival time was not considered, thus an additional functionality has to be added. There arealso strong restrictions on the power consumption because of the cooling system based only
on the air flow. Fortunately, there is a relatively long time (about 20 ms) between very short(156 ns) bunch trains. Such a low train repetition rate allows to highly decrease the overall
Material budget
Spatial resolution
Time stamping(time resolution)

Power consuption

0.2%X0 (<150 µm of silicon)
3 µm
10 ns
√
(10/ 12 ns)

50 mW cm−2

Table 5.1: Requirements for the single plane of CLIC vertex detector (X0stands for the radiation length).

84

Chapter 5. CLIPS detector design

power consumption by the so-called power pulsing, which means that the most of the readout
electronics is switched on only for a short time when the collisions take place. To provide
a detector able to meet these requirements the design of the CLIPS (CLIc Pixel SOI) chip has
been started.

5.1

CLIPS detector overview

Similarly to the previous design, also here few different approaches have been implemented.
The chip comprise three different, fully independent matrices (see Fig. 5.1). Beside that there
is a slow control block, common for the whole chip, and a test structure which allows fordeeper investigation of the in-pixel electronics performance. Thanks to much larger chip area,
comparing to the design described in the previous section, the size of each matrix is significantly
bigger. Now they consists of 64 × 64 pixels, which should be very beneficial in terms of theboundary effects suppression as well as the better statistics.
The differences between the matrices are minor and mostly refer to the modification of
sensor layout or pre-amplifier feedback capacitance. Thus, at first a general overview of the

64x64
Matrix A

64x64
Matrix B

Slow control

64x64
Matrix C

Test
structures

4.45 mmdesign will be presented, while the variations between the matrices will be discussed later.

4.45 mm(A) Block diagram of the chip.

(B) Layout of the final design.

Figure 5.1: Block diagram and layout of the CLIPS detector.

5.2

Pixel design

Thinning the sensor down to 100 – 150 µm highly suppresses the charge diffusion within a sensor
volume. Thus the charge sharing between neighbouring pixels is also limited. Unfortunately
to obtain a good spatial resolution it is essential to have the signal divided between several
pixels. For this reason, to maintain the resolution obtained with the previous design, thepixel size should be decreased. The aim was to reduce it to 20 µm × 20 µm, but it directly
introduced a high limitation on area available for the in-pixel circuitry. Despite the reduction

85

5.2. Pixel designof available area, additional functionality of the particle Time-of-Arrival (ToA) measurement
needed to be implemented. This extorts the usage of nonstandard solutions, providing a desired
functionality, but limiting the utilized area. The overview of CLIPS in-pixel circuitry is shownin Fig. 5.2, where the different functional blocks are highlighted with different colors.

Discriminator

TimingOutputs

RST

TRIGGER

TH

CT

RST

RST

BASE_CNTRL

Pre-Amp

TIME

ACTIVE
iT

STORE

CA

HV

READ

CF

AMPLITUDE

ChargeFigure 5.2: CLIPS pixel schematic.

5.2.1

Pre-amplifier

Due to the mentioned area limitations, the pre-amplifier had to be simplified even further incomparison with the design described in previous section. The telescopic cascode architecture
was replaced by a simple common source configuration. This reduces the total number ofrequired transistors, but also has a negative impact on the pre-amplifier performance. The
stability simulation results comprising both, the open loop gain and output signal phase areshown in Fig. 5.3. Comparing to the previous prototype, the open loop gain of the CLIPS
pre-amplifier has decreased (to the level of about 40 dB) because it is no longer boosted by
the gain of cascode transistor. Thus, according to equation 4.4 (on page 55), the contribution
from the sensor capacitance to the overall charge to voltage conversion ratio of the input
stage can not be fully neglected. Even though, with the gain value above 100 it should belarge enough to significantly suppress its influence. The total capacitance of the input node isestimated to be below 30 fF, even for the worst case scenario. Therefore, its contribution tothe overall charge to voltage conversion ratio should not exceed the equivalent of additional
0.3 fF in feedback capacitance. A broader discussion on the feedback capacitance will bepresented in separate section dedicated to the differences between matrices, since there areseveral approaches regarding its implementation.

86

Chapter 5. CLIPS detector design50

30

Phase [Deg]Open loop gain [dB]

40

20
10
0
-10

1 uA
2 uA
3 uA

10-2

100

102 104 106
Frequency [Hz](A) Open loop gain.

108

180
160
140
120
100
80
60
40
20
0

1 uA
2 uA
3 uA

10-2

100 102 104 106
Frequency [Hz]108(B) Phase.

Figure 5.3: AC characteristics of the CLIPS pre-amplifier.

5.2.2

Baseline adjustment

The DSOI(p) wafer has been chosen as a primary substrate, mainly due to its radiation
hardness potential. Thus the input stage electronics was optimised for the p-type sensor. But
since the foundry may also deliver chips fabricated on other substrates, it was very desired
to provide the flexibility in terms of the input signal polarity. It can be achieved by setting
the baseline in the middle of the available output voltage range, but this solution is strongly
limiting the input dynamic range. Therefore it is much more desired to have the possibility ofsetting an adequate baseline voltage depending on the sensor type.
For that reason, a novel baseline voltage adjustment technique was implemented. It uses
the effect of charge injection from the transistors working as a switch, which is usually very
undesirable. This issue has been already discussed in Sec. 4.1.1 (on page 58), together witha possible solutions for the suppression of this effect. Here the idea of having a dummytransistor which “consumes” the redundant charge has been pushed further. Since the charge
injected from the reset switch into the input node changes the baseline value, instead ofminimising this effect one can exploit it. In the resetting branch, which is shown in Fig. 5.4A,
an independent BASE_CN T RL signal is connected to the gate of the dummy transistor
instead of negated reset signal (RST ). Since the amount of the charge injected from thetransistor channel depends on the gate-source voltage, the charge injection can be controlled
by the BASE_CN T RL signal amplitude (VBASE ). Ensuring that the dummy switch closes(or opens) just after the reset phase it directly changes the baseline voltage value (VOP RE ).

The simulation results showing a baseline voltage (VOP RE ) in function of BASE_CN T RL

signal amplitude (VBASE ) are presented in Fig. 5.4B. The positive VBASE values correspond to
the BASE_CN T RL signal polarity opposite the RST polarity, whereas the negative values
to the same polarity of both signals. One can see that the proposed mechanism can be used
to change the baseline voltage in a broad range, from roughly 0.4 V up to 1.3 V, which covers
most of the output dynamic range.

87

CF

Baseline voltage [V]RSTBASE_CNTRL

5.2. Pixel design

RST

VOPRE

BASE_CNTRL
VBASE

1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
-2 -1.5 -1 -0.5 0 0.5
VBASE[V]HV(A) Pre-amplifier scheme, with waveforms ofsteering signal used for baseline addjustment.

1

1.5

2

(B) Baseline voltage level (VOP RE ) in function of
VBASE amplitude.

Figure 5.4: Baseline adjustment system.

The most important feature of the proposed solution is that it provides the new functionality without any additional power and area consumption. However, it does not allow for an
independent baseline setting of each pixel, only common for the entire matrix, thus any pixel
to pixel baseline variation can not be compensated.

5.2.3

Charge measurement

The charge measurement is done based on the same concept as in the design described in previous section, in which the voltage level on the output of the pre-amplifier directly corresponds
to the amount of charge injected to its input. Since in the input stage there is a charge-sensitive
pre-amplifier, the charge to voltage conversion ratio is mainly determined by the feedback capacitance. In this design it was desired to have as large conversion ratio as possible. This was
driven by two reasons, first of all, as already mentioned, it is planed to thin down the sensor,
and so the expected input signal is only about 1 fC. Beside that the measurements of the first
prototype show that the higher signal on the pre-amplifier output, the better signal to noise
ratio. Moreover, in terms of the discriminator performance, it is also very desired to have as
high voltage signal from the pre-amplifier as possible. Thus to maximize the charge to voltage
conversion ratio several different approaches of the feedback capacitance were implemented.
The simulated voltage response of the pre-amplifier in function of injected charge is presented in Fig. 5.5. The results are shown for the default readout electronics configuration (forthe details see the section 5.4, where the differences between matrices are explained). The
voltage change on the pre-amplifier output and on the pixel output (after the output buffer)
are shown separately. The simulated charge to voltage conversion ratio for the default configuration is about 0.5 fVC , but one has to remember that it does not include parasitic components,

which can not be neglected. The linear dynamic range for the input charge is around 1 fC and

it is limited from the top by the voltage swing on the output of the pre-amplifier, whereas
from the bottom by the output buffer.

88

Chapter 5. CLIPS detector design

Signal amplitude [V]

1.2
1
0.8

preamp out
pixel out

0.6

.0
+0
x
1

0.4

y=

0.2

1

0.5

0
-0.2
-0.4
-0.5

0

0.5
1
Qin[fC]

1.5

2

Figure 5.5: CLIPS pixel response to the injected charge, measured directly on
the pre-amplifer output preamp out and on the pixel output pixel out (after thein-pixel buffer).

As one can notice form Fig. 5.2, the sample and hold block has changed in comparison to
the previous design. The CDS is no longer utilized, only a single switch and capacitance isimplemented due to the area limitations.

5.2.4

Discriminator and Time-of-Arrival measurement

To provide the functionality of Time-of-Arrival measurement, it was necessary to add discriminator to the in-pixel circuitry. Unfortunately, the commonly used solutions are too complex
to fit into the 20 µm × 20 µm pixel. Thus just a chain of two inverters capacitively coupled
to the pre-amplifier output are utilized for that purpose (already introduced in another SOI
detector [42]). During the reset phase the input of the first inverter is being shorted with its
output, thus it is set to a semi-stable transition state where both nMOS and pMOS transistors
are conducting. Therefore, a small voltage change on its input will be enough for the transition
from this undefined state into a well defined high or low state (depending on the input signal
polarity). Such a solution itself would be highly unpredictable since in principle it may goout from the semi-stable state on any voltage fluctuation. But one can notice that after the
reset, the input node of the first inverter does not have any dc-connection, thus to ensure its
initial state a charge injection mechanism can be exploited (similar as for the baseline setting). Moreover, it can be also used for the threshold voltage adjustment, since the amount of
injected charge directly corresponds to the minimum amplitude of the input signal needed tochange the inverter state.
This mechanism is schematically presented in Fig. 5.6A. Similarly to the baseline adjustment, the discrimination threshold level is set by changing the voltage step amplitude (VT H )of the T H signal. The simulation results showing the discrimination levels expressed in the
input charge in function of VT H are shown in Fig. 5.6B. The positive VT H corresponds to thesituation when both RST and T H signals have the same polarity, whereas the negative values

89

5.2. Pixel design

mean that the T H polarity is opposite. The results are presented for the default pixel configuration. In these conditions the threshold can be set from zero up to 0.3 fC, which is around
30% of the expected input charge.
300
250

RST

200
Qin[aC]DISCRIIM
RST
TH

TH

150
100

V_TH

50
0
-1

(A) Discriminator circuitry, with waveforms ofsteering signal used for threshold addjustment.

-0.5

0

0.5
1
Vth[V]

1.5

2(B) Minimal input signal needed to trigger thediscriminarot in function of VT H .

Figure 5.6: Sketch showing the working principle of discriminator circuitry
and its simulated threshold values.

Same as for the baseline, only a global discrimination level can be set. There was no spacefor independent fine tuning on single pixel level. Since the amount of charge in the transistor
channel depends on its width and length, any fluctuation of these parameters during the
production will result in the dispersion of the threshold level over the matrix. This may be themain issue of the proposed solution. Unfortunately, it can not be verified by the simulations
since the technology vendor does not provide necessary Monte-Carlo models. Thus only themeasurements of the fabricated devices may show how big are the pixel-to-pixel thresholdvariations and how they affect the overall timing performance.
Beside the discrimination, a circuitry able to register the particle arrival time is needed.
The standard approach is to implement a counter in each pixel and store the ToA informationin digital form. But for relatively large technology size (which 200 nm process certainly is,when thinking about the digital circuitry) this solution would consume too much area to fit
within pixel. Moreover, it also requires the distribution of a fast clock over the whole matrix,
which is very unfavourable in terms of the analog circuitry performance. Therefore a different
technique of ToA measurement had to be utilized.
A circuitry responsible for recording the particle arrival time is presented in Fig. 5.7. The
ToA information is stored in the analog form, as a voltage accros the CT capacitance. The
basic principle of the proposed solution is as follows. After the reset phase both plates of CT
capacitance are set to the power supply voltage (VDD ). If the discriminator (DISCRIM ) fires
during the ACT IV E phase, both switches will start to conduct and so the CT capacitancestarts to be charged with a constant current iT . This will result in a linear voltage drop at thebottom plate of the capacitance (VTP IX ). Charging will stop when the ACT IV E time finish,

and so the voltage level stored on the CT capacitance will correspond to the ToA.

90

Chapter 5. CLIPS detector design

RST

Timing

HIT
VT

PIX

iT

VTOUT
READ

DISCRIMACTIVERST

CT

ACTIVEDISCRIM
VTPIX

Figure 5.7: The scheme of the timing block, with waveforms showing its operation.

Proposed mechanism of ToA measurement is very flexible regarding the integration phaseduration. One only needs to set the desired ACT IV E length (τA ) and proper iT current. The
voltage across the CT capacitance is given by V = CQT , where Q = iT · τA , so the current needsT
to be set to iT = V τ·C. Of course the iT current can not be infinitely low, because of theAtechnical implementation limitations. Thus for the long integration time a large CT capacitanceis desired. Fortunately it is not the case for the CLIC experiment where the ACT IV E window(train duration) is only around 160 ns. In the final design the CT capacitance is 105 fF, whichallows to extend the ACT IV E time to several dozen of microseconds, which will be beneficial
for the tests on the beam.
The simulation results showing the voltage level on the bottom plate of the CT capacitanceP(VT IX ) as well as the corresponding voltage on the output of the pixel (VTOU T ) in functionof hit arrival time are shown in Fig. 5.8A, together with the fitted linear regression lines. The
simulation was performed for 1 µs long ACT IV E time.
The precision of the time measurement is restricted by the VTOU T voltage fluctuation. The

shorter the integration time the larger iT current can be set and so the voltage change per
the time unit will be larger. This means that VTOU T voltage fluctuation will be less harmful tothe time measurement accuracy. In other words, one can determine the relative ToA precision
given in the percentage of the ACT IV E time, as shown in Fig. 5.8B. One can notice that therelative non-linearity is below 0.5%, which corresponds to 5 ns for the 1 µs long ACT IV E timeand should improve even further to ∼1 ns for the targeted conditions.
Unfortunately, this is not the only source of the inaccuracy of the ToA measurement.
One has to take into account also the promptness of the discriminator response, which highly
depends on the input charge as well as on the discrimination level. The simulation results
showing the difference between the reconstructed ToA and true ToA in function of relative
input signal (input charge Qin divided by the threshold charge Qth ) are shown in Fig. 5.9. On
the first glance the differences seem to be quite significant, but even for a very conservative seedthreshold the expected signal should exceeded it at least ten times. Moreover, the constantoffset can be subtracted and so the expected discrepancy is in order of single nanoseconds.

91

5.2. Pixel design

VT

PIX

VT

OUT

VT

1.6
Voltage level [V]

VT

OUT

0.4
Nonlinearity [% active time]

1.8

PIX

1.4
1.2
1
0.8
0.6
0.4

0.3
0.2
0.1
0
-0.1
-0.2

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ToA [us]

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ToA [us](A) Simulated VTP IX and VTOU T voltage levels
in function of hit arrival time with fited linear
regresion lines.

(B) Relative differences between obtained ToA
and fited linear regresion line in function of hit
time.

Figure 5.8: Simulation results showing the operation of the timing block.

Beside that, this issue may be further reduced on the analysis level. Thanks to the accurate
information about the input charge one may apply an offline timing correction.

ToAmeas-ToAtrue[ns]

18
16
14
12
10
8
6
4
0

5

10
Qin/Qth

15

20

Figure 5.9: Difference between reconstructed and true ToA in funcion of injected charge to threshold charge ratio Qin /Qth .

Except for the mentioned issues, a significant pixel-to-pixel fluctuations are expected, since
there are multiple factors that will affect the time reconstruction. Any deviation of the CT
capacitance or iT current will directly affect the timing performance. In addition it is also
indirectly dependent on the threshold voltage fluctuations, as well as on the charge to voltage
conversion ratio of the input stage. Thus to neglect all these factors, an individual timing
calibration is foreseen for each pixel in the matrix and a suitable functionality has been implemented in the design.
It should also be noticed, that the ToA is always measured with respect to the falling

92

Chapter 5. CLIPS detector designedge of the ACT IV E time (end of integration phase), so to get the full ToA information, theaccurate knowledge of the end of the ACT IV E time is also needed. For that reason ACT IV E
signal is synchronized with the external clock, and the time corresponding to the rising andfalling edges of ACT IV E signal is stored in the global time domain (in the units of external
clock cycles). It is done by a dedicated periphery circuit, because these values are the samefor the whole matrix, as described in the following section.

5.3

Readout control and periphery circuitry

Contrary to the previous design, the CLIPS detector operates in a snapshot mode, which isdriven by the application specification. According to the experiment requirements, the device
has to be sensitive only for 160 ns after which there is about 20 ms for the readout. Therefore
the large dead time of this operation mode is not an issue.
The periphery circuitry, which supports the matrix operation is schematically presented
on the block diagram in Fig. 5.10. There are several digital control blocks (marked with green
background), providing steering signals for the proper pixel operation and controlling the signal
flow. Beside that, there are few analog blocks (yellow background), such as buffers driving
analog signals out of the chip and biasing circuitry assuring proper voltages and currents.
For the periphery circuitry only a basic concept, essential to understand the general chip
operation, is presented, since the author of this thesis was not the main designer of the digitalpart.
The matrix operation is triggered by the Reset Control block that generates the IN IT
signal (start of new frame acquisition) after receiving the positive feedback information fromthe Readout Control block (READ_DON E) or after receiving the external reset pulse(EXT ERN AL_RST ). The IN IT signal is passed to the T ime Control and M atrix Control
blocks. The latter is responsible for providing all steering signals necessary to set up pixels
in the matrix. It ensures the proper timing for resetting the pre-amplifier and discriminator, as well as controls the baseline and threshold adjustment. After the matrix is set up it
sends the ACT IV E signal to the T ime Control circuitry. This block has two main purposes.
First of all, it controls the global time counter and stores the T oA_REF EREN CE time (thecoarse timing information assigned to the whole frame). Secondly, it synchronizes the internal ACT IV E signal with the global time domain, which is essential to refer the fine in-pixel
timing to the global frame time. The synchronized ACT IV E signal is next sent to the matrix
which becomes sensitive for its duration. After that the Readout Control block takes overand starts to process the time and amplitude informations from each pixel towards the output
pads. For that purpose, in the first step the output signals from all pixels in a given row are
passed to the Column Buf f ers. After that, the initially buffered signals are serialized andone by one sent out of the chip. There are separate output buffers for the time and amplitude
informations thus both analog signals are sent out in parallel. After 64 cycles, when the wholerow is processed, the next one is being connected to the column buffers and the procedure
repeats until the last row. Once the whole matrix is read out the Readout Control sends the
READ_DON E information and the acquisition of the next frame may start.

93

5.4. Matrix variants

Reset Control

ActiveToA_Reference

Matrix Control

Active(synch)Read_CLK

64x64
Matrixx128

Bias Currents

Biasing

Column Buﬀers

Trigger

Readout Control

Global 64b
Time Counter
Time Control

Time_CLK

External_RST
Read_Done

x64

Init (new frame)

x128

Serializer

ToA

Output Buﬀers
Amp

CHIP

Figure 5.10: Block diagram showing periphery circuitry of CLIPS electronics.
Analog blocks are filled with yellow color, wheras digital with green.

To increase the testability of the designed detector an additional T RIGGER signal issent out from the matrix. It indicates whether a hit was detected during the ACT IV E time
window. Therefore the Readout Control block may decide to not read the “empty” frame andinstead start the next acquisition immediately. This should be highly beneficial in terms ofthe number of recorded events per measurement time, since the time needed to read out thewhole frame (around 120 µs) will be usually much longer than the ACT IV E time.
As already mentioned, all three matrices included in the design are fully independent,
which means that each of them has a separate set of peripheral circuitry. This allows for
simultaneous tests of all three matrices, as long as the readout board is able to cope with themsimultaneously.

5.4

Matrix variants

Contrary to the first design, the differences between matrices are not connected with different
readout electronics architectures, but rather with variations in the technical realization ofcertain components. They concern either the sensing diode design or the feedback capacitance
implementation, which are the most sensitive parts of the design and determine the final
performance. Overall, four different approaches were implemented. According to Fig. 5.1,
Matrix A and B consist of exactly the same readout electronics, with the default feedback
capacitance implementation, whereas matrix C was splitted into two halves, with non-standard
feedback realisation.

5.4.1

Sensor design

The basic sensing node design, used in Matrix A, is presented in Fig. 5.11A. It consists of an
octagonal BP W layer, formed on the base of 8 µm × 8 µm square, and small highly dopped p+

94

Chapter 5. CLIPS detector design

region for the interconnection ohmic contact. The p+ implantation and the connection via areslightly off-centered due to the difficulties with fitting all the circuitry into the 20 µm × 20 µm
square. However, since it is entirely encircled by the well centered BW P layer it should not
introduce any major asymmetry in the electric field.
For Matrices B and C the sensor design is slightly different (Fig. 5.11B). Beside the sensing
diode (which is exactly the same as in the basic design) there is a BN W ring around eachpixel. It has been advised by other users of this technology that with such small pixel pitch
there may be a problem with pixel separation on the sensor level. Thus to investigate if theissue really exists and to ensure the proper operation of at least two matrices they have beenequipped with this separation ring.
Regarding the sensor design, it should be pointed out that the presented schemes are valid
for the n type substrate, whereas for the p type substrates the implantations are reversed.
In other words, the BP W layer always represents the implantation opposite to the substrate
type, whereas the BN W layer represents the implantation of the same type as the substrate.

p+

p+

BPW

BPW

BNW
(A) Sensor layout used in Matrix A, with onlyof the diode implantation.

(B) Sensor layout used in Matrix B and C, withdiode implantation and a BNW ring around eachpixel.

Figure 5.11: CLIPS sensor layouts.

5.4.2

Feedback circuitry

To achieve high sensitivity for input charges far below 1 fC, a high charge to voltage conversion ratio in the input stage is essential. Therefore, a further reduction of the feedback
capacitance, comparing to the previous design, was needed. Unfortunately, it was not possible with previously used “T-shape” capacitor structure, especially with significantly decreased
pixel area.
To obtain an effective capacitance of about 1 fF the “T-shape” structure was still exploited,
but the MIM capacitances (which minimum available value of 37.5 fF was the limiting factor)
have been replaced by transistors, as presented in Fig. 5.12. This solution has two main95

5.4. Matrix variants

advantages. First of all, the gate capacitance of a smallest available transistor is much lower
than the smallest MIM-cap, but also it is much less area consuming, which are both very
desired for the presented design. The capacitance of the transistor is mainly determined by
the coupling between its gate and channel, which means that its value highly depends on gatesource voltage. Therefore to effectively use a transistor as a capacitance one has to ensure its
proper operating point, where the channel is well established. Fortunately the voltage levels on“A” and “B” terminals are limited by the input stage design, and they should not drop below
0.6 V. Thus, one has only ensure the ground potential on the internal node of the “T-shape”
structure to get VGS ≥ 0.6 V, which is above the transistor threshold voltage. It was realisedby an additional transistor in the diode-like connection to the ground.

T1

T2

B

A
T3

VCAP
Figure 5.12: Scheme of the transistor-based “T-shape” capacitor structure.

Moreover, according to Fig. 5.12, the gate of the T3 transistor has been connected toan external voltage source (VCAP ). Since the total capacitance of transistor depends onthe voltage across gate and source, the total feedback capacitance can be tuned by changing VCAP potential. In the submitted chip, the T1 and T2 were of the same size and had
T1
T2
T3
CG
= CG
' 6 f F , whereas CG
can vary between 15 f F and 55 f F for differT OT AL
T OT ALT OT ALent VCAP voltages. According to equation 4.6 (on page 56) this leads to effective feedback
capacitance between 0.5 fF and 1.5 fF. The T-shape approach has been assumed as a basic
solution and implemented in Matrices A and B.
Since the parasitic capacitance can play a dominant role, even with the layout optimized
very carefully, two different solutions have been applied in Matrix C design. Its bottom half
was equipped with a custom capacitance, formed by the interconnection metallization layer andappropriate path guidance. According to the technology specification its capacitance should
correspond to 1 fF. In case of the second half of Matrix C, the intended feedback capacitancehas been totally removed, so it will be fully determined by the parasitic couplings.
The main issue with these two solutions could be a high pixel-to-pixel capacitance variation,
which will cause the dispersion of the pixels conversion ratios. It is highly undesired effect, butsince the matrix provide the precise charge measurement it allows for pixel-level calibration.
Thus, the negative influence of the discrepancies between pixel may significantly alleviated.

96

Chapter 5. CLIPS detector design

5.5

Current status and future intentionsFirst prototypes of CLIPS detector have been already fabricated. The photography of received
chips is presented in Fig. 5.13, where the basic building blocks (introduced in Fig. 5.1A) canbe easily distinguished with the bare eye. In the near future a detailed characterization ofthis chip is foreseen. It is planed to perform similar measurements as for the first detector
prototype. These are the studies with the radioactive sources, aimed to calibrate the device
and estimate the ENC, as well as the beam tests dedicated to the spatial and timing resolution
evaluation.

Figure 5.13: Photography of fabricated CLIPS prototypes.

However, before starting the measurements a completely new readout system has to be
developed. There are major differences between the first detector prototype and the CLIPS
detector, so it is not possible to reuse the previous setup. Thus, currently a dedicated PCB
is being designed and its integration with the modular test system for the silicon sensor R&D(CARIBOU – Control and Readout Itk BOard [43]) is foreseen. Depending on the measurement results the decision about the future development will be taken.

97Conclusions
The goal of this thesis was the research and development on monolithic pixel detectors fabricated in the Lapis 200 nm SOI CMOS technology. The work was devoted to verify its
capabilities in terms of the usage for ionizing radiation detection, mainly for the future highenergy physics experiments. For that purpose author of the thesis designed several monolithic
pixel detector prototypes, prepared appropriate measurement setups, developed the data acquisition system, performed different kinds of measurements and analysed the obtained results
to characterize the prototype devices.
Thanks to the close collaboration with the Japanese group working on the same technology,
author of this thesis was able to measure several prototypes of large area integrating typemonolithic pixel detector INTPIX6 developed at KEK. The tested prototypes have shown avery good energy resolution, with the ENC calculated from the pixel noise of about 70 e− . One
prototype has been irradiated up to 60 krad, but its good performance was maintained only
up to 25 krad, what has revealed the SOI main weakness, which definitely is a poor radiation
hardness. Beside that, that detector showed good imaging capabilities sharply reproducing
100 µm large details even after irradiation. To study the INTPIX6 detector performance authorof presented thesis had to prepare the measurement stand, perform numerous measurements
using different signal sources and different detector assemblies, as well as prepare a dedicateddata analysis software allowing to extract the detector parameters.
After obtaining promising results with the INTPIX6 detector, author of the thesis was
highly involved in the design of several SOI monolithic pixel detectors prototypes, of which thetwo most important are presented in this work. First of them was a general purpose detector
comprising different readout approaches. For this prototype the obtained ENC values werearound 100 e− and 110 e− for the best configurations on the FZ(n) and the DSOI(p) wafers
respectively. Thanks to the implementation of different readout architectures and different
sensor geometries, a high coupling between the electronics and sensor was found and its origin
was well understood. This was a very important outcome in terms of the next devices design.
In addition to the lab-measurements, this prototype pixel detector was also studied during
several test-beams. The best performing configuration showed an excellent spatial resolutionof 2.1 µm for 30 µm × 30 µm pixels.
During the design of this prototype, author of this thesis was mainly responsible for the
charge pre-amplifier pixels matrix and the periphery analog parts. Beside the design, author
has also prepared the dedicated data acquisition software allowing for the communication withthe readout board, performed the measurements and developed the data analysis software.
Author also took part in many test-beam campaigns, during which he was responsible for the
integration of the DAQ system with the external infrastructure and the data acquisition.

98

Chapter 5. CLIPS detector design
The last part of the PhD studies was devoted to the design of much more complex detector,

named CLIPS, aiming for the demanding requirements of the CLIC vertex detector. It requires∼150 µm thick device with very high granularity, to provide position measurement with theaccuracy below 3 µm and 10 ns time-stamping. To meet these demands, several non-standard
solutions were introduced in the CLIPS detector design (such as analog ToA measurement).
Finally, an appropriate performance was achieved on the simulation level and the chip was sent
for fabrication. The next step will be the verification of its performance by the measurementsof already fabricated prototypes, which is foreseen after the PhD. During the design of CLIPS
detector author of this thesis has prepared pixel matrices of three different types, analog partsof the readout chain (such as buffers, analog multiplexers/serializers), as well as composed all
the individual functional blocks into the final detector structure.
To sum up, during the PhD studies:• INTPIX6 detector was characterized, its radiation hardness and imaging capabilities
were checked,• general purpose, monolithic SOI pixel detector was designed and and its noise performance was estimated during the lab-measurements, whereas its spatial resolution wasverified during the test-beams,• CLIPS detector was designed and its behaviour was checked on the simulation level.
Thus, the main goal of this thesis, namely the research and development on the capabilitiesof the Lapis SOI technology in terms of its usage for the design of monolithic pixel detectors,
was fully achieved.
All the performed measurements allowed to broaden the knowledge about the Lapis 200 nm
SOI CMOS technology, especially in terms of monolithic pixel detectors design. It has been
proven that this process allows for fabrication of fully functional devices overcoming the limitations of hybrid detectors (for instance allowing the fine segmentation or detector capacitance
reduction). The in-depth analysis of obtained results provide important guidelines for the future designs and reveals the areas of research that should be further studied (e.g. radiation
hardness).
Besides all the content presented in this thesis, its author was also involved in different
projects. For example, he took part in the development of the SALT (Silicon ASIC for LHCb
tracking) readout chip for LHCb upgrade, for which he designed the biasing DACs. He also
took part in several internships at CERN and KEK, which allowed for strengthen the cooperation with the leading research centers. The significance of the performed studies can be
confirmed by the numerous presentations on international conferences and several publications
in peer-reviewed journals.

99

Appendix A

Additional plots for INTPIX6 FZ(n)detector
Additional plots showing the basic behaviour of the INTPIX6 detector fabricated on the FZ(n).
250
200

900

150

850

100

800

Y [pixels]

Y [pixels]

250

950

200

2

150

1.8

1.4

750

50

0
0

700

0
0

100 150
X [pixels]

200(A) Pedestal map P [i][j ].

250

1.6

100

50
50

2.2

1.2
50

100 150
X [pixels]

200(B) Noise map σ [i][j ].

Figure A.1: Exemplary plots showing the pedestal and noise distribution overthe matrix given in ADC counts [ADU]. Obtained with the INTPIX6 detector
fabricated on FZ(n) wafer.

250

100

Appendix A. Additional plots for INTPIX6 FZ(n) detector×103

μ= 1.46σ = 0.10

4

1

3.5

0.8

3

CountsCounts4.5

μ= -0.01
σ = 1.37

1.2

×103

0.6

2
1.5

0.4

1

0.2
0

2.5

0.5
−4

−2
0
2
Pixel signal [ADU]

04(A) Spectrum of the pixel signal S [i][j ], combined for all pixels in the matrix.

1

1.2 1.4 1.6 1.8 2 2.2 2.4
Pixel noise [ADU](B) Spectrum of the pixel noise σ [i][j ].

Figure A.2: Exemplary plots showing spectra of the pixel signal and the pixel
noise for the “calibration” data sample. Obtained with the INTPIX6 detector
fabricated on FZ(n) wafer.

107

30

106

25

5

104

CountsCounts

10

103

20
15

102

10

10

5

1

−40 −20

0 20 40 60
Pixel signal [ADU]

80 100(A) Spectrum of the pixel signal (before clusterization).

×103

0
10

15

20

25 30 35
Energy [ADU]

40(B) Spectrum of the cluster energy.

Figure A.3: Exemplary plots showing the spectra of pixel signal and cluster
energy. Obtained with the INTPIX6 detector fabricated on FZ(n) wafer using
55 F e radiation source.

45

101

Bibliography[1]

E. Heijne, “Semiconductor detectors in the low countries”, Nuclear Instruments andMethods in Physics Research Section A Aug. 2003, 1–16.

[2]

K. McKay, “Electron-Hole Production in Germanium by Alyha-Particles”, Physical Review 1951, 84, 829–832.

[3] Evolution of Silicon Sensor Technology in Particle Physic, Springer, 2009.
[4]

D. Bromley, “Nuclear Experimentations with Semiconductor Detectors”, IEEE Transactions on Nuclear Science 1962, 9, 135 –154.

[5]

W. S. Boyle, G. E. Smith, “Charge Coupled Semiconductor Devices”, The Bell System
Technical Jurnal 1970, 49, 588 –593.

[6]

E. Haase et al., “Striped semiconductor detectors for digital position encoding”, Nuclear
Instruments and Methods 1971, 97, 465 –469.

[7]

C. Damerell et al., “Charge-Coupled Devices for Particle Detection with High Spatial
Resolution”, Nuclear Instruments and Methods 1981, 185, 33 –42.

[8]

R. Bailey et al., “First measurement of efficiency and precision of CCD detectors forhigh energy physics”, Nuclear Instruments and Methods 1983, 213, 201 –215.

[9]S. Shapiro et al., “Silicon PIN diode array hybrids for charged particle detection”, Nuclear
Instruments and Methods 1989, 275, 580 –586.

[10]

M. Turala, “Silicon Tracking Detectors - historical Overview”, Nuclear Instruments andMethods 2015, 541, 1 –14.

[11]

W. Snoyes, et al., “A new integrated pixel detector for high energy physics”, IEEE
Transactions on Nuclear Science 1992, 457 –460.

[12]

G. Contin, et al., “The STAR MAPS-based PiXeL detector”, Nuclear Instruments andMethods 2018, A907, 60 –80.

[13] ANALOG INTEGRATED CIRCUIT DESIGN (Second edition), John Wiley & Sons,
Inc., 2000.
[14] Handbook of Particle Detection and Imaging, Springer, 2012.
[15] https://www.nuclear-power.net/.
[16]

S. Ramo, “Currents Induced by Electron Motion”, Proceedings of the IRE 1939, 27, 584–585.

[17] UKŁADY ELEKTRONIKI "FRONT-END", Uczelniane wydawnictwa naukowo-dydaktyczne
AGH, 2000.

102

BIBLIOGRAPHY[18]

B. Paschenc et al., “Belle II pixel detector: Performance of final DEPFET modules”,
Nuclear Inst. and Methods in Physics Research A 2019.

[19]

H. Augustina, et. all, “The MuPix high voltage monolithic active pixel sensor for the
Mu3e experiment”, Journal of Instrumentation 2015, 10, C03044 –C03044.

[20]

B. Ristic, “Active Pixel Sensors in AMS H18/H35 HV-CMOS Technology for the ATLAS
HL-LHC Upgrade”, Nuclear Inst. and Methods in Physics Research A 2016, 831.

[21]

G. A. Rinella, on behalf of the ALICE Collaboration, “The ALPIDE pixel sensor chipfor the upgrade of the ALICE Inner Tracking System”, Nuclear Inst. and Methods inPhysics Research A 2017, 845, 583 –587.

[22]

B. Y. Nguyen et al., “A Review of SOI Technology and its Applications”, Journal of
Integrated Circuits and Systems 2009. 4, 51–54.

[23] https://www.top500.org.
[24] Silicon-On-Insulator (SOI) Technology: Manufacture and Applications, Woodhead Publishing (Elsevier), 2014.
[25]

R. K. Singh et al., “Silicon On Insulator Technology Review”, International Journal ofEngineering Sciences and Emerging Technologies 2011, 1, 2231–6604.

[26]

A. Chauhan, A. Prakash, “Analysis of Floating Body Effects in SOI Transistor”, International Research Journal of Engineering and Technology 2016, 3, 1123–1131.

[27] Physics o Semiconductor Devices (Thirrd edition), John Wiley & Sons, Inc., 2007.
[28]

Y. Arai et al., “Development of SOI pixel process technology”, Nuclear Inst. and Methods
in Physics Research A 2011, 636, S31–S36.

[29]

I. Kurachi et al., “Investigation of radiation hardness improvement by applying back-gatebias for FD-SOI MOSFETs”, Nuclear Inst. and Methods in Physics Research A 2018,
924, 404–408.

[30]

K. Hara, et. all, “Radiation hardness of silicon-on-insulator pixel devices”, Nuclear Inst.
and Methods in Physics Research A 2018, 924, 426 –430.

[31]

T. Miyoshi et al., “SOI monolithic pixel detector”, Journal of Instrumentation 2014, 9,
C05044.

[32]

S. Bugiel et al., “Performance of the INTPIX6 SOI pixel detector”, Journal of Instrumentation 2017, 12, C01028–C01028.

[33]

M. Asanoa et al., “Characteristics of non-irradiated and irradiated double SOI integration type pixel sensor”, Nuclear Instruments and Methods in Physics Research Section
A 2016, 831, 315–321.

[34]

CERN, ROOT Data Analysis Framework, https://root.cern.ch/.

[35] Design of Analog CMOS Integrated Circuits, McGraw-Hill Education, 2001.
[36]

J. Silva-Martinez, R. Assaad., “The recycling folded cascode: A general enhancementof the folded cascode amplifier”, IEEE Journal of Solid-State Circuits 2009, 44, 2535
–2542.

BIBLIOGRAPHY
[37]

103

J. Silva-Martinez, R. Assaad., “Enhancing general performance of folded cascode amplifier by recycling current”, Electronics Letters 2007, 43.

[38]

S. Bugiel, MA thesis, AGH University, 2014.

[39] https://www.boost.org/.
[40]

N. Alipour Tehrani, PhD thesis, ETH ZURICH, 2017.

[41]

R. Bugiel, PhD thesis, AGH University, 2019.

[42]

S. Ono et al., “Development of a pixel sensor with fine space-time resolution based on SOI
technology for the ILC vertex detector”, Nuclear Instruments and Methods in Physics
Research Section A 2018, 845, 139–142.

[43]

M. Benoit et al., “Development of a modular test system for the silicon sensor R&D of
the ATLAS Upgrade”, Journal of Instrumentation 2017, 12.