DETECTOR TECHNOLOGY PROJECTINTERNATIONAL REVIEWCOMMITTEE 2013
DECEMBER 10-11, 2013
Part I
SOI

KEK
Detector Technology Project OfficeSOI PROJECT
v.4 Dec. 6, 2013, Yasuo ARAI (KEK)

Contents:
1. Introduction ..................................................................................................................... 3
2. SOI Pixel Process ........................................................................................................... 4
2.1 Wafer Process ........................................................................................................................................... 4
2.2 Back Gate Effect & BPW ......................................................................................................................... 5
2.3 Sensor Layers ........................................................................................................................................... 6
2.4 High Resistive Wafer ............................................................................................................................... 7
2.5 Leakage current ....................................................................................................................................... 9
2.6 Multi

Project Wafer Run ..................................................................................................................... 10

2.7 Stitching ................................................................................................................................................. 11

3. Detector Developments ................................................................................................ 12
3.1 SEABAS Readout Board ........................................................................................................................ 12
3.2 Integration Type Pixel Detector (INTPIX) ........................................................................................... 13
3.3 X-ray Detector for Astrophysics (XRPIX) ............................................................................................. 15
3.4 XFEL Detector (SOPHIAS) ................................................................................................................... 17
3.5 Vertex Detector (PIXOR) ....................................................................................................................... 18
3.6 Low Temperature Applications ............................................................................................................. 19
3.7 Other Detector R&Ds ............................................................................................................................ 21

4. Advanced R&Ds ............................................................................................................ 23
4.1 Double SOI ............................................................................................................................................. 23
4.2 3D Vertical Integration ......................................................................................................................... 26

5. Data Base ..................................................................................................................... 29
5.1 Development History ............................................................................................................................. 29
5.2 Collaboration Members ......................................................................................................................... 29
5.3 Master Thesis ......................................................................................................................................... 32
5.4 Publications ............................................................................................................................................ 33
5.5 External Fundings ................................................................................................................................. 37
5.6 Patents.................................................................................................................................................... 37

6. References .................................................................................................................... 372

"'%#('#"

The Silicon-On-Insulator (SOI) pixel R&D [i] is targeting to develop monolithic pixel
detectors for future high-energy physics experiments, X-ray experiments, and otherapplications. It integrates both radiation sensors and LSI circuits in one chip, and achieve
high-resolution and intelligent detectors.
Fig. 1 shows the schematic view of the SOI pixel detector (SOIPIX). The SOI wafer iscomposed of a thick, high-resistivity substrate (sensor part) and a thin low-resistivity Si layer(CMOS circuitry) sandwiching a buried oxide (BOX) layer. After removing the top Si and the
BOX layer in the region of the sensing node contacts, p or n dopant is implanted to thesubstrate. Then contact vias and metal connections from the p-n junction to the transistors
are created. The main advantages of the SOI detectors are;•

There is no mechanical bump bonding, so obstacles, which will cause multiple
scattering, are eliminated and smaller pixel size is possible.

•

Parasitic capacitances of sensing nodes are very small (~10fF), so large conversion
gain and low noise operation are possible.

•

Full CMOS circuitry can be implemented in the pixel.

•

The cross section of single event effects caused by radiation is very small. A latch-up
mechanism, which destroys conventional bulk CMOS LSI, is absent.

•

Unlike conventional CMOS process, there is no leakage path to bulk. Thus SOI
transistors are shown to work over a very large temperature range from 4K to 600K.

•

The technology is based on industry standards, and one of most promisingtechnology for future LSIs. Thus further progress and lower cost are foreseeable.

•

Emerging vertical (3D) integration techniques are a natural extension of the SOI
technology, so a much higher integration density is possible.

We have started this R&D in 2005 by collaborating with Lapis Semiconductor Co. Ltd (see
5.1 Development History). Our process is developed based on their 0.2 µm CMOS
fully-depleted (FD-) SOI process [ii].

3Fig. 1 Schematic view of the SOI Pixel Detector.

&#$+ $%#&& * % $ %#&& Main specifications of the process are summarized in Table 1. We have been trying
several kinds of high-resistivity wafers (CZ and FZ) for both n- and p-type wafers (see 2.4
High Resistive Wafer). To reduce development cost, we called academic sectors to join our
MPW runs (see 2.6 Multi Project Wafer Run). The process has 5 layers of metal and canbe implement MIM capacitor located on 3rd metal (Fig. 2) [iii].
Table 1. SOI pixel process specifications.
Process

0.2µm Low-Leakage Fully-Depleted SOI CMOS,
1 Poly, 5 Metal layers, MIM capacitor (1.5 fF/um2), DMOS option. Core (I/O)
Voltage = 1.8 (3.3) V

SOI wafer

Diameter: 200 mm!,Top Si: Cz, ~18 "-cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: 720 µm thick. Cz(n) ~ 700 "-cm,
FZ(n) ~ 7k"-cm, FZ(p) ~ 25 k"-cm, etc.
Thinned to 100 ~ 500 µm by mechanical grind, and chemical etching. Thenadequate impurity is implant, laser Annealed, and Al is plated (200 nm).

BacksideTransistors
Optional
process

Normal and low threshold transistors are available for both core and IO
transistors.
Three types of structures (body-floating, source-tie and body-tie) are available.
Buried p-well formation
Vertical integration with µ-bumps.

4Fig. 2. Upper structure of the SOI process.

    '  '   $*One of the major difficulties to build a radiation sensor in SOI wafer is the back gate effect.
Since the sensor and the transistors are located very near (~200 nm), transistors become
ON when high voltage is applied to the sensor (Fig. 4-a). To shield the electric field of thetransistors from the sensor voltage, we developed Buried Well (BW) process. We implantp(n)-type dopant without removing the top Si layer to create a buried p(n)-well region(BPW(BNW)) under the BOX. As shown in Fig. 4, leakage current of transistors becomesvery high at the back side voltage of above 10V if there is no BPW layer. However, thetransistor characteristic does not change at 100V by introducing the BPW layer. (Actually
there is no back gate effect seen even more than 200V).

Fig. 3. Cross sectional view of a typical SOI pixel detector.
5Fig. 4. NMOS transistor Ids-Vds curve and back side voltage. (a) Without BPW layer, (b) with
BPW layer connected to ground. By introducing the BPW layer, the back gate effect is fully
suppressed.

  & "&#% ,%& After introducing the BPW/BNW layers successfully, several structures that require
additional layers were proposed and introduced. Fig. 5 shows present possible layers underthe BOX. PS and NS layers are high-density implant region to create p+ and n+ region andcontact to metal layer. These implant will be done after removing top Si and SiO2 layers.
BP3 is same mask layer used in the BPW, and is used when deeper implant is required.
BP2 is deepest buried layer to create nested structure with the BNW.
We are using same layout both for n-type and p-type substrate. Therefore, when we
process p-type substrate p-implant and n-implant are reversed. Thus, in p-type substrate,
BPW mask is used for buried n-well, and BNW mask is used for buried p-well and so on.
As for the backside of the wafer, following processes are done normally.
i)Mechanical grind to desired thickness,ii)

Wet etching by 40um,

iii)

Implant of n (p) dopant to n(p)-substrate (depth ~ 0.5um),

iv)

Aluminum plating (~200 nm).

6

Fig. 5. Structure of the sensor part for n-substrate and p-substrate. Capital letters are layer
name and inside of parenthis shows actual doping.

    % &&') * % 

We have been mainly using high resistive SOI wafer from standard products of SOITEC
Co. The handle wafer is made in Czochralski (Cz) method (called HR1 wafer), which isn-type and has about 700 Ohm•cm resistivity. However, it is desirable to get much higher
resistivity to create thicker depletion depth with lower voltage. We asked SOITEC to makespecial SOI wafer by bonding with Floating Zone (FZ) wafer. That FZ wafers was supplied
from us since it is not easy to get 8" FZ wafer.
To do CMOS process on FZ wafer is not easy task since CMOS high temperatureprocess will cause slips in the wafer (Fig. 6 center). After careful tuning of the hightemperature process, we succeeded to process FZ-SOI wafer without major slips (Fig. 6
right).
Fig. 7 shows leakage current vs. depletion depth for different wafers. FZ(n) and FZ(p)wafers of 500um thick become full depletion with 112V and 55V respectively, while Cz(n)wafer needs 237V to deplete 260um thick wafer.

Fig. 6. X-ray inspections of FZ-SOI wafers and slips.
7

Fig. 7. Leakage current and depletion width of INTPIX3e chip fordifferent kinds of wafers. Backside of the Cz(n) wafer is mechanicalgrind only, while the FZ(n) and FZ(p) wafers are chemical etching is

Fig. 8. 1/C2 plot of the INTPIX4 detector measured at 1kHz.
Calculated resistivity from the corner voltage is 6.0 kOhm•cm and 1.1

8  (%%"' 

While leakage current of the sensor is not so important for short integration time
applications, it is important for long integration time applications such as astronomical X-ray
observation and measurements that require good energy resolution.
Table 2 shows leakage current of a few detectors. CZ(n)(=HR1) wafer shows relatively
large leakage current (> 100nA/cm2@Room Temp.), while FZ(n) wafer shows better leakage
current (10nA/cm2@20ºC). Fig. 9 shows temperature dependence of the XRPIX1 leakage
current. By lowering temperature, leakage current will decrease but become constant below-20 ºC. We have not yet identified the source of the constant leak curent.
Table 2. Summary of leakage current @Vdet=10V.
Chip/TEG

Wafer

Temp.

Leakage current

XRPIX1XRPIX1XRPIX1XRPIX1
MAMBO IV (nested well)
INTPIX/CNTPIX

Cz(n)
Cz(n)
FZ(n)
FZ(n)
FZ(n)
Cz(n)

25 ºC
-50 ºC
20 ºC-20 ºCRoom T
Room T

440 nA/cm2
0.3 nA/cm2
10 nA/cm2
0.1 nA/cm2<100 nA/cm2
100~300 nA/cm2

Fig. 9. Dark Current of the XRPIX1 FZ-SOI. Pixel size is 30.6 um square.
Target spec is 2pA/cm2.

9

Fig. 10 shows Arrhenius plot of the XRPIX2b-Cz(n). Until full depletion occurs around
250V, the activation energy is about 0.55eV. This implies main source of the current comesfrom generation current in the depletion region. When full depletion achieved above 300V,
activation energy decreases below 0.35eV. This implies back side surface is the source of
the additional leakage current.

Fig. 10. Arrhenius plot of the XRPIX2b-Cz(n) detector.

  ! ( '  $ %#' * % % (" The cost of semiconductor process is not cheap. Major part of the cost is mask set. To
reduce development cost and have multiple chances for developments, we decided tooperate this SOI pixel process as Multi Project Wafer (MPW) runs. In past a few years, wehave been doing the MPW runs twice per year except year 2011 when large earthquake wasoccurred and Lapis semiconductor fab was damaged.
In addition to many Japanese institutes, we have been collaborating with
US/Europe/Asian researchers through this MPW runs. Our present collaborator/user are
listed in section 5.2 "Collaboration Member"
In 2011, we changed the mask size from 20.6mm x 20.6mm to 24.6mm x 30.8mm, so that
we can accept more designs and build larger detector Fig. 11.

10

Fig. 11.. Examples of Mask layouts. (Left) FY2010 : 20.6mm x 20.6mm.

  & ''" 

Large area detectors are often required in some experiments, but the mask size is limited
to 24.6mm x 30.8mm in size. Therefore, we have developed stitching technique to makelarge format detector by using only one mask set. Fig. 12 shows the stitching method andphotographs of the processed wafer.
The development is mainly driven by Riken group for the SOPHIAS detector. Since thiswas our first trial, we took buffer region size of 10um and connect only minimum number oflayers (PS, NS and metal 1). However, Lapis is confident to make buffer region shorter andconnects all metals.

11

Fig. 12. Stitching exposure for the SOPHIAS detector. Both edge structure and pixel structure weredrawn in a mask. Part of the mask is blocked during exposure. In this detector (SOPHIAS), pixel
layout was repeated 3 times and edge structures are exposed at both ends.

''#%) #$!"'&

There are many activities of detector developments using the SOI pixel process. In thissection, we flash major activities of the developments.
 &&  % #('  #% 

To test manufactured chip quickly, we have developed SEABAS (SOI EvAluation BoArd
with Sitcp) read out board. The board contains two FPGAs one for controlling the SOI pixel
and the other is for transferring the data through Ethernet (called SiTCP).
Fig. 13 and Fig. 14 show block diagram and photograph of the SEABAS2 (2nd generation
board) respectively. By using the SEABAS2 board, we could take ~70 frame/sec withINTPIX4 detector (425k pixels).

12Fig. 13. Block diagram of the SEABAS2..

Fig. 14, Photograph of the SEABAS2 board and the INTPIX4 sub-board.

  "'%'#" ' ,$ $ +   ''#% "'$+

Main SOI detectors developed so far are integration-type pixel detectors. The basic
schematic of the sensor and a layout are shown in Fig. 15. The circuit is similar to that of the
CMOS optical imager. Smallest size of the pixel we have developed is 8 µm square. Many of
the integration-type pixels have correlated double sampling (CDS) circuit in each pixel or incolumn circuit. Largest chip (INTPIX5/6) so far tested has 896 x 1408 (~1.3 M) pixels, andnew chip (INTPIX7) under process has 1408 x 1408 (~2M) pixels. Specifications of major
integration-type detector are summarized in Table 3.
An example of X-ray image taken by the INTPIX4 detector is shown in Fig. 16.

13

Fig. 15. (Left) A typical circuit schematic of the integration-type pixel with CDS function. (Right) Layoutof INTPIX7 pixel. The size of the pixel is 12um x 12um.

Table 3. Specification of major integration-type pixel detectors.

Pixel Size [um]Chip Size [mm]
BPW width [um]CDSStore Switch
Wafer
Gain
Max. Charge
No. of Pixels
No. of Output
Rolling Shutter

DIPIX1/2

FPIX1

INTPIX4

INTPIX5/6

14 x 145x5
10Pixel CDS
O

8x8
6x6
6
-

17 x 1710.2 x 15.4
12
Pixel CDSOn or pn and pn

12 x 1212.2 x 18.4
9
Column CDS
O
n and p (INT5)n or p (INT6N or P)
2 gain(~16 or 2.5 uV/e-)~70 or 460 ke896 x 1408(~1,260 kpix

Fix(9.3 uV/e-)~110 ke256 x 128 x 2(~65 kpix)

1
-

Fix
Fix
(~28 uV/e-)(12.6 uV/e-)~40 ke80 ke512 x 512
512 x 832(~260 kpix ~430 kpix

1 or 9O

1 or 13-

1 or 11O

INTPIX7(under process)12 x 1218.4 x 18.4
9
Pixel CDSO
p (Double SOI)
Fix
1408 x 1408(~1,982 kpix

1 or 11O

14

Fig. 16 An example of X-ray image (small fish) taken by the integration-type SOI sensor.

   + %,  ''#%#%  &'%#$,&& +%$+

XRPIX detector [iv] has been developed for X-ray astronomical satellite by Kyoto Univ.
and KEK/SOKENDAI member. Basic structure of the detector is same as that of theintegration type detector, but it also has trigger generation function. By combining the trigger
function and active shield system, background event caused by charged particles can beremoved (Fig. 17).
In addition to source-follower type pixel used in the INTPIX, we have also developed
Charge Sensitive Amplifier (CSA) type pixel recently. Fig. 17 shows energy spectrum of 55Fe
X-rays taken by the XRPIX CSA pixel. CSA type pixel shows much better resolution
compared to source follower type, and achieved noise level of 33 e- while source follower
type has 76 e- noise level.

15

Fig. 17 Concept of an active shield system with the XRPIX. Non-X-ray background can berejected by anti-coincidence with the active shield (scintillation counters).

Fig. 18 Block diagram of the XRPIX detector.

16

Fig. 19. Energy spectrum of 55Fe taken with the XRPIX detectors. CSA type pixel showed better
resolution.

   +   ''#% &#$&

A large dynamic range X-ray image Sensor has been developed for X-ray Free-electron
Laser Facility, SACLA. The detector is named SOPHIAS (Silicon-On-Insulator PHoton
Imaging Array Sensor) and developed by Riken group [v]. The sensor consists of 1.9 M
pixels with 30 um pixel square shape. The single layer sensor give 40 % quantum efficiency
at 20 keV X-ray photons with 500um thick handle wafer.
Each pixel has high and low gain channels to achieve large dynamic range. The different
gain is achieved by different value of the input capacitance and different number of sensor
nodes (Fig. 20). To fabricate larger detector than mask size, stitching technique isdeveloped and used (see 2.7 Stiching).

17

Fig. 20. Outlook of the SOPHIAS detector and schematics of the pixel.

   ) %'+  ''#% $+#%

As an R&D for future vertex detector for Belle II experiment, a new detector PIXOR (PIXelOR) is being developed by Tohoku Univ. group [vi]. An analog signal from each pixelated
sensor is divided into two-dimensional directions, and 2N signal channels from a small
N-by-N pixel matrix are ORed as N column and N row channels (Fig. 21). Then the signals
are processed by a readout circuit in each small matrix and wait for a trigger (Fig. 22).
This PIXOR scheme reduces the number of readout channels and avoids a deteriorationof intrinsic position resolution due to large circuit area that was a common issue formonolithic detectors. This feature allows high resolution, low occupancy and on-sensor
signal processing at the same time.

18

Fig. 21. Conceptual view of PIXOR (4x4 Super Pixel case). A charged particle penetrates the green
pixel. The signal is divided into X(blue)/Y(red) directions. In this figure, readout circuit is notshown.

Fig. 22 Schematic of the single channel PIXOR1 circuit.

   #* ' !$%'(%  $$ '#"& People in JAXA/ISAS have interest in using SOI devices in cryogenic temperature. Theydeveloped CMOS amplifiers and switches by using the SOI process, and confirmed to workwithout problem in low temperature where bulk CMOS devices cannot work. Typicalperformance of the amplifier is shown in Table 4.

19

Table 4. Performance of FD-SOI CMOS amplifier at 4.2K.

After the success of the cryogenic operation, we started a project to build
Superconducting Tunnel Junction (STJ) devices on processed SOI wafer with Univ. of
Tsukuba group. When we want to arrange the STJ devices in array, extraction of STJ
signals to room temperature is always annoying issue. If we succeed to build the STJ on
processed SOI wafer and make good connections between them, number of the connection
can be greatly reduced and S/N can be improved.
We have tested characteristics of SOI transistors at below 1K (Fig. 23). Both NMOS andPMOS show good performance. Then we build Nb/Al STJ device on top of the SOI wafer.
The STJ devices successfully build and output signal is observed by illuminating laser light(465 nm) to the device (Fig. 24).

Fig. 23. Ids-Vgs characteristics of NMOS and PMOS transistors at 960mK and 750mK respectively.

20

Fig. 24. (Left) Test structure of an element. (Right) Signal from the Nb/Al-STJ
built on the SOI wafer.

   # '%  ''#% % & 

There are many other detectors R&Ds which are going on by using our MPW run.
Counting-type pixel (CNTPIX)
One of most important R&D for next step is development of counting type detectors.
Schematic of the counting type pixel and its pixel layout are shown in Fig. 25. We alreadyhave test chips that show proper responses, but we also observe crosstalk between sensor
and the circuits. Thus the development is postponed until double SOI technology is available(4.1 Double SOI).

Fig. 25. (Left) Schematic of the counting type pixel (CNTPIX). (Right) layout of the counting type pixelof 64um x 64um size.

21

Detector for Imaging Mass Spectrometer (MALPIX)
Multi-Turn Time of Flight Mass Spectrometer (MULTUM) is being developed at Osaka
Univ. as a compact and high performance mass spectrometer for next generation. It requires
two-dimensional detector that can measure ion arrival timing in 1 ns resolution. Although it
does not use sensor part of the SOIPIX, our pixel circuit can be utilized for this application.
Then we started collaboration with Osaka group and developing a pixel detector called
MALPIX. Ions from the spectrometer are converted to electrons by using Micro-Channel
Plate (MCP), and a prototype detector was successfully tested.

Fig. 26. (Top) Overview of the MULTUM mass spectrometer. (Bottom) Schematics ofthe MALPIX.

LHD pixel
To investigate inside of nuclear fusion plasma, measurement of X-rays from the inside ofplasma gives valuable information. We have started collaboration with National Institute for22

Fusion Science (NIFS) for measurement of Large Helical Device (LHD). First test isscheduled on Dec. 2013.
TDI pixel
X-ray detectors are used widely in many kinds of inspection system. Especially to findsmall metallic debris of ~10um size within battery has crucial demand in future electricalvehicles and so on. To find such small debris from materials on high-speed belt conveyor,
SOIPIX is very suitable with its high resolution. However, to receive enough X-rays frommoving object, Time Delayed Integration (TDI) method is mandatory. Although it is easy to
implement the TDI in CCD device, it is difficult to do in CMOS device. We have invented a
new method to implement digital TDI in the SOIPIX.
RADPIX
After the accident of the Fukushima nuclear power plant, people become very sensitive toradiations. Although SOIPIX does not have high efficiency for a few hundreds keV gamma
rays, pixelated sensor has advantage to identify type of the radiation and detection of alphaand beta rays. Thus we are developing a pixel detector (RADPIX) for monitoring
environmental radiation. It includes leakage current compensation circuit for continuous
detection of radiation.
)"%&  #(  &#

While we solved the back gate problem by introducing BPW layer, there still remain two
issues to make the SOIPIX used widely.
• Crosstalk between sensor node and circuit,• Radiation tolerance of the detector.
The crosstalk generates unwanted signals and makes operation of the detector unstable.
While the SOI is immune to Single Event Effect (SEE), it is not so rad-hard to Total
Ionization Dose (TID) due to the BOX and surrounding oxide. Tolerable radiation level ofpresent SOIPIX devices is about 2 kGy, and many applications require more than 10 kGy (1Mrad) tolerance.
After all, to solve these issues, we need another conduction layer between sensor andcircuit. We asked SOITEC to make double SOI wafer which has two sets of thin Si and BOX
pair layers. General view of the double SOI pixel detector is shown in Fig. 27, and crosssection of processed double SOI wafer is shown in Fig. 28. In addition to above two issues,
the newly introduced middle Si layer (SOI2) shields back gate effect too (Fig. 29), so that we
can optimize the size of the BPW without considering the back gate effect.

23

Fig. 27. General view of the pixel detector using the double SOI wafer.

Fig. 28. Cross sectional view of the double SOI wafer. In addition to top SOI and substrate,
we introduced middle SOI layer. (Unfortunately, the contact to the middle Si is out of thephotograph.)

The first double SOI wafers were produced by SOITEC Co. with n-substrate, but second
DSOI wafers have been produced by Shin-Etsu Chemical Co. Ltd, Japan, with p-type
substrate.
When we irradiate gamma rays to the SOI, transistor threshold voltage will move tonegative direction (Fig. 29 left) due to hole trapping in the oxide. However, by applying
negative voltage to the middle Si, electric field generated by the hole is compensated andthe threshold voltage will return to almost original value (Fig. 30).

24

Fig. 29. Back gate effect suppression by the middle Si. (Left) Middle Si is floating. (Right) Middle Si
is connected to ground and the back gate effect is fully suppressed.

Fig. 30. Id-Vgs curve change with g-ray irradiation and middle Si voltage (VSOI2). (Top) NMOS,(Bottom) PMOS.

Fig. 31 plots optimum value of the SOI2 layer to return the threshold value to original value[vii]. The statistics of the data is not yet enough and there is large variation in the data of
NMOS core transistors. However we can see the optimum value for dose up to 20 kGy looks
same for all the transistors. On the other hand, at above 20 kGy, we see some rebound in25

NMOS transistors. Then we may need to separate the SOI2 layer between NMOS andPMOS for the application that requires more than 20 kGy radiation tolerance.

Fig. 31. Optimum SOI2 value to return threshold for various kinds of transistors. Both 'NMOS and
PMOS' and 'Core and IO' transistors are showing similar tendency.

   ) %'   "'%'#" Although the SOI detector is successfully being developed, future pixel detectors such as
used in the International Linear Collider (ILC) requires much more transistors to implement
memories and data processing logics than available today. Since the readout circuit needs
analog amplification circuits etc., it is not necessary good to go fine node process.
If we try to implement such memory and logics inside the pixel, the pixel size must be verylarge (> 60 x 60 um2), while the experiment requires smaller pixel size less than 20 x 20 um2.
To solve this, we have started R&D of 3D vertical integration by using µ-bump technology[viii] in collaboration with T-Micro Co.
Fig. 32 shows the process flow of the vertical stacking of circuit layers. Base SOI chips as
upper and lower tiers are fabricated in a SOI wafer. Minimum bump pad opening size is 3µm x 3 µm. After forming under bump metallization (UBM), Indium bumps are formed using26

evaporation and lift-off technique. The minimum bump size and pitch are 2.5-µm sq. and 5µm respectively.
Lower tier and upper tier are aligned using IR microscope. Initial alignment error before
welding bumps must be kept less than 1.0 µm in order to obtain stable electrical connection.
After fusing into one connection, the tiers are self-aligned to less than 0.6 µm. The gap
between tiers is about 1.5 µm. An array of Indium µ-bump junctions does not have enoughmechanical strength. So combining gap fill with adhesive is indispensable and injection
method is the key of this process.
Fig. 33 shows layout of alignment mark and photographs of the alignment marks at 4

corners after the bonding and the adhesive injection. The chips are aligned at better than 1
um accuracy. Since the space between tiers is not uniform due to unbalance distribution ofthe µ-bumps in the chip, adhesive injection caused voids at the points where rapid pressure
loss occurs. White island area seen in Fig. 33-bottom upper left photo is such a void. Numberof the voids is greatly reduced by controlling differential pressure assisted capillary action.
Although we are bonding chip to chip in this study, chip to wafer bonding techniques are also
being developed for mass production.

Fig. 32. Process flow for the stack process with micro bump technology.

27

Fig. 33. (Top) Alignment mark size, (Bottom) Alignment of upper and lower chips after stacking.

28'&  ) #$!"'  &'#%, 2005. 52005. 7

Propose SOI Pixel R&D to KEK Detector Technology ProjectStart Collaboration with OKI Electronics Co. Ltd.

2005.10
2006.122007.3First submission to Univ. of Tokyo (VDEC) 0.15µm SOI MPW run.
First MPW run of 0.15um SOI process operated by KEK.
First SOI Workshop @KEK

2007. 6
2007.10Process change to Miyagi 0.2um line due to discontinue of Hachioji 0.15 µm line.
First User Meeting @U. of Hawaii (IEEE NSS)

2008. 1
2008.32008.10First MPW run of 0.2µm SOI process.
SOI Workshop @KEK
OKI semiconductor division was spin-off to OKI semiconductor Co. Ltd, and enters
under Rohm Co. group.
Metal Pitch is shrunken from 0.88um to 0.58um.
Introduce Buried P-Well structure.
SOI W.S. @Kyoto Univ.
Collab. Mtg. @Fermilab
International Review @KEK
OKI Semi Miyagi Fab. was damaged by the large earthquake.
Name of OKI Semi was changed to Lapis Semiconductor Co. Ltd.
Mask size was increased from 20.6 mm square to 24.6 mm x 30.8 mm.
Collab. Mtg. @LBNL
First double SOI wafer was processed.
PIXEL2012 conference @Fukushima.
Mini Workshop @IHEP (China)
Collab. Mtg. @Krakow (AGH & IFJ)
10th 0.2um MPW run was submitted.

2009. 1
2009.2
2010.32011.2
2011.32011.92011.102012.32012.82012.92013.2
2013.52013.8##%'#" ! !%& [Japanese Members]
Name
Koichi NAGASE
Hirokazu Ikeda
Testuichi Kishishita
Daisuke Kobayashi
Takehiko WADA
Ryuichi Takashima
Shou Moritake
Shinya Nakashima
Hironori Matsumoto
Syukyo G. Ryu
Takeshi Tsuru
Takaaki Tanaka
Hideaki Matsumura
Jiro Ida

Affiliation
JAXA/ISAS
JAXA/ISAS
JAXA/ISAS
JAXA/ISAS
JAXA/ISAS
Kyoto Univ. of Education
Kyoto Univ. of Education
Kyoto Univ.
Nagoya Univ.
Kyoto Univ.
Kyoto Univ.
Kyoto Univ.
Kyoto Univ.
Kanazawa Institute of Technology
29

Kazuya Tauchi
Ryo Ichimiya
Susumu Terada
Takashi Kohriki
Tomohisa Uchida
Toru Tsuboyama
Toshinobu Miyoshi
Yasuo Arai
Yoichi Ikegami
Yoshinobu Unno
Yowichi Fujita
Yukiko Ikemoto
Shingo Mitsui
Motohiko Omodani
Takashi Kameshima
Hirofumi Tadokoro
Masashi Yanagihara
Morifumi Ohno
Yasushi Igarashi
Hidehiko Nakaya
Ayaki Takeda
Daisuke Nio
Kazunori Hanagaki
Minoru Hirose
Toshihiro Idehara
Kazuhiko Hara
Yuji Takeuchi
Shinhong Kim
Mari Asano
Naoshi Tobita
Tatsuya Maeda
Kouhei Tsuchida
Shunsuke Honda
Kouta Kasahara
Kouhei Shinsho
Yoshiyuki Onuki
Hideki Hamagaki
Yuuko Sekiguchi
Hitoshi Yamamoto
Akimasa Ishikawa
Yutaro Sato
Hironori Katsurayama
Shinoda Naoyuki
Yoshimasa Ono
Kouji Mori
Yuusuke Nishioka
Kazuo Kobayashi
Shun Ono
Takaki Hatsui
Tougo Kudo
Kameshima Takashi
Yoichi Kirihara
Sadatsugu Muto

KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
KEK, High Energy Accelerator Research Organization
JASRI, XFEL division
JASRI, XFEL division
National Institute of Advanced Industrial Science and Technology
National Institute of Advanced Industrial Science and Technology
National Institute of Advanced Industrial Science and Technology
National Institute of Advanced Industrial Science and Technology
National Astronomical Observatory of JapanThe Graduate University for Advanced StudiesSchool of High Energy
Accelerator
The Graduate University for Advanced StudiesSchool of High Energy
Accelerator Science
Department of Physics, Osaka Univ.
Department of Physics, Osaka Univ.
Department of Physics, Osaka Univ.
Univ. of Tsukuba, Faculty of Pure and Applied Sciences
Univ. of Tsukuba, Faculty of Pure and Applied Sciences
Univ. of Tsukuba, Faculty of Pure and Applied Sciences
Univ. of Tsukuba, Graduate School of Pure and Applied Sciences
Univ. of Tsukuba, Graduate School of Pure and Applied Sciences
Univ. of Tsukuba, Graduate School of Pure and Applied Sciences
Univ. of Tsukuba, Graduate School of Pure and Applied Sciences
Univ. of Tsukuba, Graduate School of Pure and Applied Sciences
Univ. of Tsukuba, Graduate School of Pure and Applied Sciences
Univ. of Tsukuba, Graduate School of Pure and Applied Sciences
Univ.of Tokyo
Univ.of Tokyo
Univ.of Tokyo
Tohoku Univ.
Tohoku Univ.
Tohoku Univ.
Tohoku Univ.
Tohoku Univ.
Tohoku Univ.
Miyazaki Univ.
Miyazaki Univ.
RIKEN, RIKEN SPring-8 Center
RIKEN, RIKEN SPring-8 Center
RIKEN, RIKEN SPring-8 Center
RIKEN, RIKEN SPring-8 Center
RIKEN, RIKEN SPring-8 Center
RIKEN, RIKEN SPring-8 Center
National Institute for Fusion Science30

Shigeru Sudo
Naoki Tamura
Yasuhiko Ito
Hideya Nakanishi
Tsukada Kiwamu
Masayuki Ikebe
Shoji Kawahito
Keiichiro Kagawa
Keita Yasutomi
Takeo Watanabe
Nobukazu Teranishi

National Institute for Fusion Science
National Institute for Fusion Science
National Institute for Fusion Science
National Institute for Fusion Science
Nagoya Institute of Technology
Hokkaido Univ.
Shizuoka Univ.
Shizuoka Univ.
Shizuoka Univ.
Univ. of Hyogo
Univ. of Hyogo[Foreign Members]
Name
Chih Hsun Lin
Minglee Chu
Sebastian Glab
Wojciech Kucewicz
Marek Idzik
Mohammed Imran Ahmed
Piotr Kapusta
Farah Khalid
Grzegorz Deptuch
Marcel Trimpl
Raymond Yarema
Ronald Lipton
Ivan PericPeter Fischer
Lei FanLiu Gang
Xiaoshan JIANG
Yunpeng Lu
Zheng Wang
Yi LiuQi Zhang
Ning Wang
Tian Li
Hui Wang
Qi Zhang
Zhao Kai
Chinh Vu
Devis Contarato
Lindsay GlesenerPeter Denes
Craig S Tindall

Affiliation
Academia Sinica, Taiwan
Academia Sinica, Taiwan
Department of Electronics AGH-University of Science and Technology(AGH-UST)
Department of Electronics AGH-University of Science and Technology(AGH-UST)
Krakow's University of Science and Technology (AGH-UST)
Institute of Nuclear Physics, Krakow
Institute of Nuclear Physics, Krakow
Fermilab
Fermilab
Fermilab
Fermilab
FermilabInstitut für Technische Informatik der Universität Heidelberg
Institut für Technische Informatik der Universität Heidelberg
Institute of High Energy Physics, Chinese Academy of Sciences
Institute of High Energy Physics, Chinese Academy of Sciences
Institute of High Energy Physics, Chinese Academy of Sciences
Institute of High Energy Physics, Chinese Academy of Sciences
Institute of High Energy Physics, Chinese Academy of Sciences
Institute of High Energy Physics, Chinese Academy of Sciences
Shanghai Advanced Research Institute, Chinese Academy of Sciences.
(SARI, CAS)
Shanghai Advanced Research Institute, Chinese Academy of Sciences.
(SARI, CAS)
Shanghai Advanced Research Institute, Chinese Academy of Sciences.
(SARI, CAS)
Shanghai Advanced Research Institute, Chinese Academy of Sciences.
(SARI, CAS)
Shanghai Advanced Research Institute, Chinese Academy of Sciences.
(SARI, CAS)The Institute of Microelectronics of the Chinese Academy of Sciences(IMECAS)
LBNL
LBNL
LBNL
LBNL
LBNL
31

Marco Battaglia
Eduardo Cortina
Elena Martin
Lawrence Soungyee
Paula liliana alvarez
rengifoGary Varner
Michael Cooney
Angel Dieguez
Dario BiselloDevis Pantano
Serena Mattiazzo
Piero Giubilato

LBNL, UC Santa Cruz
Louvain-la-Neuve University
Universitat Autonoma de Barcelona
Louvain-la-Neuve University
Louvain-la-Neuve University
Univ. of Hawaii
Univ. of Hawaii
University of Barcelona
University of Padova & INFN Padova, Italy
University of Padova & INFN Padova, Italy
University of Padova & INFN Padova, Italy
University of Padova and INFN Padova, Italy, & LBNL,

USA[Cooperation Companies]
Name
Lapis Semiconductor Co. Ltd.
Lapis Semiconductor Miyagi Co. Ltd.
A-R-Tec Co.
Rigaku Co.
T-micro Co. Ltd.
REPIC Co. Ltd.
Digian Technology Inc.

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ÚHH';4;7A(:5B H!-> ĸ &EA7E; %EAJ&# Òđ\õLQêTMN[ÊÇ¯ĽĆÖå§UĮ÷MZVěĜĴKHE;@;(:5B H1. ĸ !5:;>A5>;?1J&# Òđ\õLQ­ $5D18 å§õĞWOginxUĮ÷H¢Vü­ $5D18å§UÐĊěKH#?-7-(:5B H1. ĸ ,A65&-13A?- J&# Òđ\õLQÁå§UĮ÷KH';7E;:?@ ;2'1/4 H1. ĸ 5!;/45FA75 J&585/;:#::?A8-@;> Òđ\õLQĞO¨ģ­g~evcjå§UĮ÷úýKH(:5B ;2'?A7A.-!->    $ ( '#"& [English]1 "Hard X-Ray SOI Sensor Prototype", E. Martin, G. Varner, M. Barbero, J. Kennedy, H. Tajima, Y. Arai,IEEE Ph. D. Research in Microelectronics and Electronics, 11 - 16 June 2006, Otranto (Lecce), Italy
2 "First Results of 0.15um CMOS SOI Pixel Detector", Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima,
S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda, H. Ikeda, K. Hara, H. Ishino, T. Kawasaki, E. Martin, G.
Varner, H. Tajima, M. Ohno, K. Fukuda, H. Komatsubara, J. Ida, SNIC Symposium, Stanford, California,
3-6 April 2006, SLAC-PUB-12079, KEK preprint, 2006-34, SLAC Electronic Conference Proceedings
Archive(SLAC-R-842,
eConf:
C0604032)
PSN-0016.
http://www.slac.stanford.edu/econf/C0604032/papers/0016.PDF.
3 "Monolithic Pixel Detector in a 0.15mm FD-SOI Technology", Y. Arai,presented at the 6th Hiroshima
symposium of Development and Application of semiconductor tracking devices, Sep. 11-15, 2006,
Carmel, California, U.S.A.
4 "Development of a CMOS SOI Pixel Detector", Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S.
Terada T. Tsuboyama, Y. Unno, Y. Ushiroda, H. Ikeda, K. Hara, H. Ishino, T. Kawasaki, H. Miyake, E.
Martin, G. Varner, H. Tajima M. Ohno, K. Fukuda, H. Komatsubara, J. Ida,Proceedings of 12th Workshop
on Electronics for LHC and Future Experiments (LECC 2006), 25-29 September 2006, Valencia SPAIN.
5 "Monolithic Pixel Detector in a 0.15um SOI Technology", Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O.
Tajima, S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda, H. Ikeda, K. Hara, H. Ishino, T. Kawasaki, E.
Martin, G. Varner, H. Tajima, M. Ohno, K. Fukuda, H. Komatsubara, J. Ida, H. Hayashi,, IEEE Nuclear Sci.
Symposium, San Diego, Oct. 29 - Nov. 4, 2006, Conference Record, Vol. 3, Oct. 2006 Page(s):1440 1444, Digital Object Identifier 0.1109/NSSMIC.2006.354171.
6 "Evaluation of OKI SOI Technology",Y. Ikegami, Y. Arai, K. Hara, M. Hazumi, H. Ikeda, Ishino, T. Kohriki,
H. Miyake, A. Mochizuki, S. Terada, T. Tsuboyama, Y. Unno,, presented at the 6th Hiroshima symposiumof Development and Application of semiconductor tracking devices, Sep. 11-15, 2006, Carmel, California,
U.S.A., Nuclear Instruments and Methods in Physics Research Section A, Volume 579, Issue 2, 1 Sept.
2007, Pages 706-711,
7 "Deep sub-micron FD-SOI for front-end application", Nuclear Instruments and Methods in Physics
Research Section A, Volume 579, Issue 2, 1 September 2007, Pages 701-705, H. Ikeda, Y. Arai, K. Hara,
H. Hayakawa, K. Hirose, Y. Ikegami, H. Ishino, Y. Kasaba, T. Kawasaki, T. Kohriki, et al., Proceedings ofthe 11th Symposium on Radiation Measurements and Applications (SORMA XI): Ann Arbor, USA, May
23_26, 2006, Nucl. Instr. and Meth. A, Vol. 579, Issue 2, 1 Sep. 2007, p.p. 701-705.
8 "Electronics and Sensor Study with the OKI SOI process", Y. Arai, , Topical Workshop on Electronics for
Particle Physics (TWEPP-07), 3-7 Sep. 2007, Prague, Czech Republic. CERN-2007-007, pp. 57-63.
9 "SOI Monolithic Pixel Detector R&D in a 0.15 mm SOI Technology", Y. Arai, Y. Ikegami, Y. Unno, T.
Tsuboyama, S. Terada, M. Hazumi, T. Kohriki, H. Ikeda, K. Hara, H. Ishino, H. Miyake, K. Hanagaki, G.
Varner, E. Martin, H. Tajima, Y. Hayashi, M. Ohno, K. Fukuda, H. Komatsubara, J. Ida., 16th
International Workshop on Vertex detectors, September 23-28, 2007, Lake Placid, NY, USA, Vertex 2007,
Poster Presentation.
10 "SOI Pixel Developments in a 0.15µm Technology”,, Y. Arai, Y. Ikegami, Y. Unno, T. Tsuboyama, S.
Terada, M. Hazumi, T. Kohriki, H. Ikeda, K. Hara, H. Miyake, H. Ishino, G. Varner, E. Martin, H. Tajima, M.
Ohno, K. Fukuda, H. Komatsubara, J. Ida, H. Hayashi, Y. Kawai, , 2007 IEEE Nuclear Science
Symposium Conference Record, N20-2, pp. 1040-1046.
11 "Total Dose Effects on 0.15µm FD-SOI CMOS Transistors”, , Y. Ikegami, Y. Arai, K. Hara, M. Hazumi, H.
Ikeda, H. Ishino, T. Kohriki, H. Miyake, A. Mochizuki, S. Terada, T.Tsuboyama and Y. Unno,, 2007 IEEE
33

Nuclear Science Symposium Conference Record, N44-6, pp. 2173-2177.
12 “A monolithic pixel sensor in fully depleted SOI technology”, , Marco Battaglia, Dario Bisello, Devis
Contarato, Peter Denes, Piero Giubilato, Lindsay Glesener, Chinh Vu. , Nuclear Instruments and Methods
in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment,
Volume 583, Issues 2-3, 21 December 2007, Pages 526-528.
13 "R&D of a pixel sensor based on 0.15 µm fully depleted SOI technology", Toru Tsuboyama, Yasuo Arai,
Koichi Fukuda, Kazuhiko Hara, Hirokazu Hayashi, Masashi Hazumi, Jiro Ida, Hirokazu Ikeda, Yoichi
Ikegami, Hirokazu Ishino, Takeo Kawasaki, Takashi Kohriki, Hirotaka Komatsubara, Elena Martin, Hideki
Miyake, Ai Mochizuki, Morifumi Ohno, Yuuji Saegusa, Hiro Tajima, Osamu Tajima, Tomiaki Takahashi,
Susumu Terada, Yoshinobu Unno, Yutaka Ushiroda and Gary Varner, Proceedings of the 15th
International Workshop on Vertex Detectors: Perugia, Italy, Sep., 2006, Nucl. Instr. and Meth. A. Vol. 582,
Issue 3, Dec. 2007, Pages 861-865, http://dx.doi.org/10.1016/j.nima.2007.07.130,
14 "Radiation Resistance of SOI Pixel Sensors Fabricated with OKI 0.15µm FD-SOI Technology", K. Hara, M.
Kochiyama, A. Mochizuki, T. Sega, Y. Arai, K. Fukuda, H. Hayashi, M. Hazumi, J. Ida, H. Ikeda, Y.
Ikegami, H. Ishino, Y. Kawai, T. Kohriki, H. Komatsubara, H. Miyake, M. Ohno, M. Okihara, S. Terada, T.
Tsuboyama, Y. Unno, N04-5, Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE,
19-25 Oct. 2008 Page(s):1369 _ 1374, Digital Object Identifier 10.1109/NSSMIC.2008.4774670, IEEE
Transactions on Nuclear Science, Volume 56, Issue 5, Part 2, Oct. 2009 Page(s):2896 - 2904.
15 "Development of Silicon-on-Insulator Sensor for X-Ray Free-Electron Laser Applications",T. Kudo, T.
Hatsui, Y. Arai, Y. Ikegami, Y. Unno, T. Tsuboyama, S. Terada, M. Hazumi, T. Kohriki, H. Ikeda, K. Hara,
A. Mochizuki, H. Miyake, H. Ishino, Y. Saegusa, S. Ono, M. Ohno, K. Fukuda, H. Komatsubara, J. Ida, H.
Hayashi, Y. Kawai, M. Okihara, T. Ishikawa, IEEE Nucl. Sci. Symp., Oct. 2008, Poster R12-58,
16 "Waveform Observation of Digital Single-Event Transients Employing Monitoring Transistor Technique",Daisuke Kobayashi, Kazuyuki Hirose, Yoshimitsu Yanagawa, Hirokazu Ikeda, Hirobumi Saito, V´eroniqueFerlet-Cavrois, Dale McMorrow, Marc Gaillardin, Philippe Paillet, Yasuo Arai, and Morifumi Ohno,IEEE
Trans. Nucl. Sci., Volume 55, Issue 6, Part 1, Dec. 2008 Page(s):2872 _ 2879, Digital Object
Identifier 10.1109/TNS.2008.2006836.
17 "High-speed charge-to-time converter ASIC for the Super-Kamiokande detector, H. Nishino, K. Awai, Y.
Hayato, S. Nakayama, K. Okumura, M. Shiozawa, A. Takeda, K. Ishikawa, A. Minegishi, Y. Arai,
Nucl.Instrum.Meth.A610:710-717,2009.
18 "Device-physics-based analytical model for single event transients in SOI CMOS logics”,D. Kobayashi, K.
Hirose, V. Ferlet-Cavrois, D. McMorrow, M. Gaillardin, T. Makino, H. Ikeda, Y. Arai, and M. Ohno,, 2009
IEEE Nuclear and Space Radiation Effects Conference (NSREC), Quebec, Canada, July 20--24, IEEE
Trans. Nucl. Sci. 56 (2009) 3043.
19 "Developments of SOI Monolithic Pixel Detectors", Y. Arai, T. Miyoshi, Y. Unno, T. Tsuboyama, S. Terada,
Y. Ikegami, T. Kohriki, K. Tauchi, Y. Ikemoto, R. Ichimiya, H. Ikeda, K. Hara, H. Miyake, M. Kochiyama, T.
Sega, K. Hanagaki, M. Hirose, T. Hatsui, T. Kudo, T. Hirono, M. Yabashi, Y. Furukawa, G. Varner, M.
Cooney, H. Hoedlmoser, J. Kennedy, H. Sahoo, M. Battaglia, P. Denes, C. Vu, D. Contarato, P. Giubilato,
L. Glesener, R. Yarema, R. Lipton, G. Deptuch, M. Trimpl, M. Ohno, K. Fukuda, H. Komatsubara, J. Ida,
M. Okihara, H. Hayashi, Y. Kawai, A. Ohtomo, , Technology and Instrumentation in Particle Physics 2009
in Tsukuba, Japan, 11-17 March, 2009, Nucl. Instr. and Meth. A 623(2010)186-188,
doi:10.1016/j.nima.2010.02.190
20 "Silicon-on-insulator technology enables next-generation radiation image sensors", Yasuo Arai and
Toshinobu
Miyoshi,August2009,
SPIE
Newsroom.
http://spie.org/x36212.xml?highlight=x2414&ArticleID=x36212,DOI:10.1117/2.1200907.1725.
21 "Development of SOI Pixel Process Technology",Y. Arai, T. Miyoshi, Y. Unno, T. Tsuboyama, S. Terada,
Y. Ikegami, R. Ichimiya, T. Kohriki, K. Tauchi, Y. Ikemoto, R. Ichimiya, Y. Fujita, T. Uchida, H. Ikeda, K.
Hara, H. Miyake, M. Kochiyama, T. Sega, K. Hanagaki, M. Hirose, J. Uchida, Y. Onuki, Y. Horii, H.
Yamamoto, T. Tsuru, H. Matsumoto, S. G. Ryu, R. Takashima, A. Takeda, H. Ikeda, D. Kobayashi, T.
Wada, H. Nagatg, T. Hatsui, T. Kudo, A. Taketani, T. Kameshima, T. Hirono, M. Yabashi, Y. Furukawa,
M. Battaglia, P. Denes, C. Vu, D. Contarato, P. Giubilato, T. S. Kim, T. Hatsui, T. Kudo, T. Hirono, M.
Yabashi, Y. Furukawe, M. Ohno, K. Fukuda, I. Kurachi, H. Komatsubara, J. Ida, M. Okihara, N. Kuriyama,
M. Motoyoshi, 7th International "Hiroshima" Symposium on Development and Applications of
Semiconductor Tracking Devices, Hiroshima, Japan, Aug. 29-Sep.1, 2009, Nucl. Instr. and Meth.
doi:10.1016/j.nima.2010.04.081. Vol. 636, Issue 1, Supplement, 2011, Pages S31-S36.
22 "Reduction techniques of the back gate effect in the SOI Pixel Detector",R. Ichimiya, Y.Arai, K. Fukuda, I.
Kurachi, N. Kuriyama, M. Ohno, M. Okihara, for the SOI Pixel collaboration,Proceedings of Topical
Workshop on Electronics for Particle Physics (TWEPP-09), 21-25 Sep. 2009, CERN-2009-006, pp. 68-71.
23 "New Techniques in SOI Pixel Detector",Y. Arai, 2009 IEEE Nuclear Science Symposium and Medical
34

Imaging Conference, Orlando Florida, Oct. 25-31, 2009, Conference Record, N22-2, pp. 1161-1164.
Digital Object Identifier: 10.1109/NSSMIC.2009.5402397
24 "Vertical Integration of Radiation Sensors and Readout Electronics",Y.Arai,15th MediterranianElectromechanical Conference, Melecon 2010, Valletta, Malta, 25-28 April, 2010, pp. 1062-1067.
25 "Integrated Radiation Image Sensors with SOI technology", Yasuo Arai, Toshinobu Miyoshi, Ryo Ichimiya,
Kazuhiko Hara, Yoshiyuki Onuki, SOI Conference (SOI), 2010 IEEE International Digital Object Identifier:10.1109/SOI.2010.5641403, Publication Year: 2010 , Page(s): 1 - 5.
26 "Readout ASIC With SOI Technology for X-Ray CCDs", Kishishita, T.; Idehara, T.; Ikeda, H.; Tsunemi, H.;
Arai, Y.; Sato, G.; Takahashi, T.;, Nuclear Science, IEEE Transactions on Volume: 57 , Issue: 4 , Part: 2,
Digital Object Identifier: 10.1109/TNS.2010.2049371, Publication Year: 2010 , Page(s): 2359 - 2364.
27 "Large SET Duration Broadening in a Fully-Depleted SOI Technology-Mitigation With Body Contacts",
Ferlet-Cavrois, V.; Kobayashi, D.; McMorrow, D.; Schwank, J. R.; Ikeda, H.; Zadeh, A.; Flament, O.;
Hirose, K.;, Nuclear Science, IEEE Transactions on Volume: 57 , Issue: 4 , Part: 1, Digital Object
Identifier: 10.1109/TNS.2010.2048927, Publication Year: 2010 , Page(s): 1811 - 1819.
28 "Development of INTPIX and CNTPIX Silicon-On-Insulator Monolithic Pixel Devices", K. Hara, M.
Kochiyama, K. Koike, T. Sega, K. Shinsho, Y. Arai, Y. Fujita, R. Ichimiya, Y. Ikegami, Y. Ikemoto, T.
Kohriki, T. Miyoshi, K. Tauchi, S.Terada, T. Tsuboyma, Y. Unno, Y. Horii, Y. Onuki, D. Nio, A. Takeda,
K.Hanagaki, J. Uchida, T. Tsuru, S.G. Ryu, I. Kurachi, H. Kasai, N. Kuriyama, N.Miura, M. Okihara, M.
Motoyoshi,
VERTEX
2010,
Loch
Lomond,
UK,
June,
2010,
http://pos.sissa.it/cgi-bin/reader/conf.cgi?confid=113, PoS(VERTEX 2010)033.
29 "Development of X-ray Imaging Spectroscopy Sensor with SOI CMOS Technology", Syukyo Gando Ryu,
Takesahi Go Tsuru, Shinya Nakashima, Yasuo Arai, Ayaki Takeda, T. Miyoshi, R. Ichimiya, Y. Ikemoto, R.
Takashima d, T. Imamura, T. Ohmoto, and A. Iwata, 2010 IEEE Nuclear Science Symposium,
Conference record. doi: 10.1109/NSSMIC.2010.5873714, 2010 , Page(s): 43-48.
30 "Evaluation of Monolithic Silicon-On-Insulator Pixel Devices Thinned to 100 um", K. Shinsho, K. Hara, Y.
Arai, Y. Ikemoto, T. Kohriki, T. Miyoshi, 2010 IEEE Nuclear Science Symposium, Conference record, doi:
10.1109/NSSMIC.2010.5873838, 2010, Page(s): 646-649
31 "Radiation test on FD-SOI Readout ASIC of Pair-monitor for ILC", Yutaro Sato , Yasuo Arai, Hirokazu
Ikeda, Tadashi Nagamine, Yosuke Takubo, Toshiaki Tauchi, Hitoshi Yamamoto, Nucl. Instr. and Meth.
A(2011), doi:10.1016/j.nima.2010.12.149, Volume 650, Issue 1, 11 September 2011, Pages 106-110.
32 "Performance study of SOI monolithic pixel detectors for X-ray application", T. Miyoshi, Y. Arai, M. Hirose,
R. Ichimiya, Y. Ikemoto, T. Kohriki, T. Tsuboyama, Y. Unno, 7th International "Hiroshima" Symposium on
Development and Applications of Semiconductor Tracking Devices, International Conference Center
Hiroshima, Japan, Aug. 29-Sep.1, 2009, Nucl. Instr. and Meth. A, doi:10.1016/j.nima.2010.04.117, Vol.
636 (2011)pp. S237-S241.
33 "Radiation effects in silicon-on-insulator transistors with back-gate control method fabricated with OKI
Semiconductor 0.20 µm FD-SOI technology",M. Kochiyama, T. Sega, K. Hara, Y. Arai, T. Miyoshi, Y.
Ikegami, S. Terada, Y. Unno, K. Fukuda, M. Okihara, Nucl. Instr. and Meth. A(2010),
doi:10.1016/j.nima.2010.04.086, Volume 636, Issue 1, Supplement, 21 April 2011, Pages S62-S67.
34 "SOI Readout ASIC of Pair-monitor for International Linear Collider",Yutaro Sato, Yasuo Arai, Hirokazu
Ikeda, Tadashi Nagamine, Yosuke Takubo, Toshiaki Tauchi, Hitoshi Yamamoto, Nuclear Inst. andMethods in Physics Research, A10.1016/j.nima.2011.02.063, Vol. 637, Isuue 1, May 2011, pp. 53-59.
35 "Tests of monolithic pixel detectors in SOI technology with depleted substrate", Piero Giubilato, MarcoBattaglia, Dario Bisello, Devis Contarato, Peter Denes b, Tae Sung Kim,Serena Mattiazzo, Devis Pantano,NicolaPozzobon,
C.S.Tindall,
Sarah
Zalusky,
Nucl.Instr.andMeth.
A(2010),
doi:10.1016/j.nima.2010.11.185,
36 "Monolithic pixel detectors in a deep submicron SOI process",Grzegorz Deptuch,Nuclear Instruments andMethods in Physics Research A623(2010)183_185,37 "First Performance Evaluation of an X-Ray SOI Pixel Sensor for Imaging Spectroscopy and Intra-Pixel
Trigger",Syukyo Gando Ryu, Takeshi Go Tsuru, Shinya Nakashima, Ayaki Takeda,Yasuo Arai,
Toshinobu Miyoshi, Ryo Ichimiya, Yukiko Ikemoto, Hironori, Matsumoto, Toshifumi Imamura, Takafumi
Ohmoto, and Atsushi Iwata, IEEE Transactions on Nuclear Science, Vol. 58, No. 5, Oct. 2011, pp.
2528-2536, ISSN: 0018-9499, Digital Object Identifier: 10.1109/TNS.2011.2160970
38 "Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array",Hirohisa NAGATA, Takehiko WADA, Hirokazu IKEDA, Yasuo ARAI, Morifumi OHNO, Koichi NAGASE,
IEICE
TRANSACTIONSon
Communications,
Vol.
E94-B
No.11,
pp.2952-2960,2011,http://search.ieice.org/bin/summary.php?id=e94-b_11_2952&category=B&year=201
1&lang=E&abst=,
39 "SOI detector developments", Y. Onuki, H. Katsurayama,Y. Ono, H. Yamamoto, Y. Arai, Y. Fujita, R.
35

Ichimiya, Y. Ikegami, Y. Ikemoto, T. Kohriki, T. Miyoshi, K. Tauchi, S. Terada, T. Tsuboyama, Y. Unno, T.
Uchida, K. Hara, K. Shinsho, A. Takeda, K. Hanagaki, T. G. Tsuru, S.G. Ryu, S. Nakashima, H.
Matsumoto, R. Takashima, H. Ikeda, D. Kobayashi, T. Wada, T. Hatsui, T. Kudo, A. Taketani, K.
Kobayashi, Y. Kirihara, S. Ono, M. Omodani, T. Kameshima, Y. Nagatomo, H. Kasai, N. Kuriyama, N.
Miura, M. Okihara, The 20th Anniversary International Workshop on Vertex Detectors - VERTEX 2011,
June 19 - 24, 2011, Rust, Lake Neusiedl, Austria, Proceedings of Science, PoS(Vertex 2011)043.
40 "SOI Pixel Technology",Y. Arai, The 8th international "Hiroshima" Symposium on the Development andApplication of Semiconductor Tracking Detectors (HSTD-8) , Dec. 5-8, 2011, Taipei, Invited Talk.
41 "Development
of
Low
Power
Cryogenic
Readout
Integrated
Circuits
Using
Fully-Depleted-Silicon-on-Insulator CMOS Technology for Far-Infrared Image Sensors", T. Wada, H.
Nagata, H. Ikeda, Y. Arai, M. Ohno and K. Nagase,Journal of Low Temperature Physics, Issn: 0022-2291,
2012,DOI:10.1007/s10909-012-0461-6, http://www.springerlink.com/content/j7306844556t5397/,
42 "Development of an SOI analog front-end ASIC for X-ray charge coupled devices", Tetsuichi Kishishita,
Goro Sato, Hirokazu Ikeda, Motohide Kokubun, Tadayuki Takahashi, Toshihiro Idehara, Hiroshi Tsunemi,
Yasuo Arai, Nuclear Instruments and Methods in Physics Research Section A: Accelerators,
Spectrometers, Detectors and Associated Equipment, Volume 636, Issue 1, Supplement, 21 April 2011,
Pages S143-S148.
43 "X-Ray Detector Activities in Japan", DOE Basic Energy Science Neutron and Photon Detector W.S.,@Gaithersburg, Invited Talk, 2012.8.1, Yasuo Arai.
44 "Advanced Radiation Image Sensors with SOI Technology", Yasuo Arai, Sep. 25, 2012, IEEE Solid
State Device and Materials, Kyoto, Invited Talk.Extended abstract, J-1-1, pp. 1107-1108.
45 “Progress of SOI Pixel Process”, Y. Arai, International Workshop on Semiconductor Pixel Detectors for
Particles and Imaging, September 3 – 7, 2012 in Inawashiro, Japan, Invited Talk.
46 "High-Resolution Monolithic Pixel Detectors in SOI Technology", Oral, T. MIYOSHI, Y. ARAI, I. M.
AHMED, P. KAPUSTA, R. ICHIMIYA, Y. IKEMOTO, Y. FUJITA, K. TAUCHI, A. TAKEDA, International
Workshop on Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2012), Inawashiro, Japan.
47 "High Resolution X-ray Imaging Sensor with SOI Technology", poster, A. TAKEDA, Y. ARAI, T. MIYOSHI,
M. OKIHARA, H. KASAI, N. MIURA, N. KURIYAMA, Y. NAGATOMO, International Workshop on
Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2012), Inawashiro, Japan.
48 "Development of the Pixel OR SOI Detector for High Energy Physics Experiments", Y. Ono, A. Ishikawa,
Y. Arai, T. Tsuboyama, Y. Onuki, A. Iwata, T. Imamura, T. Ohmoto, International Workshop on
Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2012), Inawashiro, Japan. Nuclear
Instruments & Methods in Physics Research A (2013), http://dx.doi.org/10.1016/j. nima.2013.06.044i.
49 "Design and Evaluation of a SOI Pixel Sensor for X-ray Trigger-driven Readout", Ayaki Takeda, Yasuo
Arai, Syukyo Gando Ryu, Shinya Nakashima, Takeshi Go Tsuru,Toshifumi Imamura, Takafumi Ohmoto,and Atsushi Iwata, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL PP,Issue 99, 2013. DigitalObject Identifier: 10.1109/TNS.2012.2225072.
50 "Tests With Soft X-rays of an Improved Monolithic SOI Active Pixel Sensor", Ryu, S. G.; Tsuru, T. G.;
Prigozhin, G.; Kissel, S.; Bautz, M.; LaMarr, B.; Nakashima, S.; Foster, R. F.; Takeda, A.; Arai, Y.;
Imamura, T.; Ohmoto, T.; Iwata, A. Nuclear Science, IEEE Transactions on Volume:60, Issue: 1, Part:
2,Digital Object Identifier: 10.1109/TNS.2012.2231880, Publication Year: 2013 , Page(s): 465- 469
51 "X-Ray Detection Using SOI Monolithic Sensors at a Compact High-Brightness X-Ray Source Based on
Inverse Compton Scattering", Oral, T. Miyoshi, Y. Arai, M. Fukuda, J. Haba, H. Hayano, Y. Honda, K.
Sakaue, H. Shimizu, A. Takeda, J. Urakawa, K. Watanabe, 2012 IEEE Nuclear Science Symposium,
Anaheim, CA, USA. Nov. 2012.
52 "Monolithic pixel detectors with 0.2 um FD-SOI pixel process technology", Oral, T. MIYOSHI, Y. ARAI, Y.
IKEMOTO,Y. UNNO, Y. IKEGAMI, R. ICHIMIYA, Y. FUJITA, K. TAUCHI, T. TSUBOYAMA, A. TAKEDA,
T. TSURU, S. NAKASHIMA, G. S. RYU, T. KOHRIKI, 13th Vienna Conference on Instrumentation(VCI2013), Vienna, Austria. Nuclear Instruments & Methods in Physics Research A (2013),
http://dx.doi.org/10.1016/j. nima.2013.06.029.
53 Development of a built-in Analog-to-Digital Converter for a X-ray Astronomy Detector with the SOI CMOS
Technology, S.Nakashima, S.G.Ryu. T.G.Tsuru, Y.Arai, A.Takeda, H.Nakajima, H.Tsunemi, J.P.Doty,
T.Imamura, T.Ohmoto, T.Maeda, A.Iwata, 2011 IEEE Nuclear Science Symposium, Valencia, Spain,
Conf. Rec., Nov. 2011.
54 Progress in Development of Monolithic Active Pixel Detector for X-ray Astronomy with SOI CMOS
Technology, S.Nakashima, S.G.Ryu, T.G.Tsuru, A.Takeda, Y.Arai, T.Miyoshi, R.Ichimiya, Y.Ikemoto,T.Imamura, T.Ohmoto, A.Iwata, Physics Procedia, Vol. 37, 2012, pp.1373-1380, doi: j.phpro.2012.04.100
55 Development and characterization of the latest X-ray SOI pixel sensor for a future astronomical mission,
S.Nakashima, S.G.Ryu, T.Tanaka, T.G.Tsuru, A.Takeda, Y.Arai, T.Imamura, T.Ohmoto, A.Iwata, Nuclear
36

Instruments and Methods in Physics Research Section A (NIMA), Vol 731, 2013, pp. 74-78,
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[i] SOIPIX collaboration. http://rd.kek.jp/project/soi/. Interdisciplinary research on quantum imaging
opened with 3D semiconductor detector, http://soipix.jp.
[ii] K. Morikawa, Y. Kajita, M. Mitarashi, OKI Technical Review, Issue 196, Vol. 70, No. 4, pp. 60-63,
2003.
[iii] Y. Arai, et al., "Development of SOI Pixel Process Technology", Nucl. Instr. and Meth A.
doi:10.1016/j.nima.2010.04.081. Vol. 636, Issue 1, Supplement, 21 2011, pp. S31-S36.
SOI Pixel collaboration http://soipix.jp.
[iv] A. Takeda, et al., "Design and Evaluation of a SOI Pixel Sensor for X-ray Trigger-driven
Readout", IEEE Trans. on Nucl. Sci., Vol pp, Issue 99, 2013. Digital Object Identifier:10.1109/TNS.2012.2225072.
[v] T. Hatsui, "SOI Pixel Sensor Process",
http://www-ppd.fnal.gov/EPPOffice-W/Research_Techniques_Seminar/talks/Hatsui.pdf[vi] Y. Ono, et al., "Development of the Pixel OR SOI Detector for High Energy Physics Experiments",
Nucl. Instr. & Meth. A, (2013), http://dx.doi.org/10.1016/j. nima.2013.06.044i.
[vii]S. Honda, K. Hara, M. Asano, T. Maeda, N. Tobita, Y. Arai, T. Miyoshi, M. Ohno, T. Hatsui, T.
Tsuru, N. Miura, H. Kasai, M. Okihara, "Total Ionization Damage Effects in Double
Silicon-on-Insulator Devices", IEEE Nucl. Sci. Symposium, Conference Record, N42-2.
[viii] M. Motoyoshi, et al., "Stacked SOI Pixel Detector using Versatile Fine Pitch m-Bump
Technology", IEEE Int. 3D System Integration Conf.2011 (3D-IC), 2012, Session 5-2

38