SOI Pixel Developments
in a 0.15 μm Technology
IEEE NSS, Oct. 31, 2007, N20-2

Yasuo Arai (KEK)KEK Detector Technology Project : [SOIPIX Group, http://rd.kek.jp/project/soi/]
Y. Arai, Y. Ikegami, Y. Unno, T. Tsuboyama, S. Terada, M. Hazumi, T. Kohriki, H. IkedaA,K. HaraB, H. IshinoC, H. MiyakeB, K. HanagakiD,G. VarnerE, E. MartinE, H. TajimaF,Y. HayashiG, M. OhnoG, K. FukudaG, H. KomatsubaraG, J. IdaG
KEK, JAXAA, U. TsukubaB, TITC, Osaka Univ.D, U. HawaiiE, SLACF,
OKI Elec. Ind. Co.G,
07.10.31 IEEE NSS yasuo.arai@kek.jp

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OUTLINE• Introduction• Features of SOI Pixel Detector• SOI Pixel MPW run• Test Results• SummaryN20-3 : TCAD Simulation for SOI Pixel Detector
N20-5 : A SOI Implementation of a 5th generation CAP
N44-6 : TID for 0.15um FD-SOI CMOS Tr
07.10.31 IEEE NSS yasuo.arai@kek.jp2

Introduction : KEK SOIPIX R&D History‘05. 7: Start Collaboration with OKI Elec. Co. Ltd. for SOI Pixeldetector R&D .
’05.10: FY05 TEG submission in OKI MPW (Multi Project Wafer)run with 0.15μm technology.
‘06. 3: Fabrication was finished.
FY05 TEG chips are successfully tested.
Response to Light and β-ray is confirmed.
-------------------------‘06.12: First MPW run hosted by KEK with 17 designs which includes
submissions from US lab/univ.
‘07. 4 : Fabrication was finished.
-------------------------‘08.1: Second KEK MPW run is scheduled.
07.10.31 IEEE NSS yasuo.arai@kek.jp

3Features of SOI Monolithic Pixel detectorz

Bonded Wafer (High Resistive Substrate + Low Resistive Top Si).

zStandard CMOS Electronics (NMOS, PMOS, MIM Cap etc. ).

zMonolithic Detector, No Bump Bonds (Lower cost, Thin Device).

z

High density (Smaller Pixel Size is possible).

z

Small capacitance of the sense node (~10fF, High gain V=Q/C)z

Industrial standard technology (Cost benefit and Scalability)z

No Latch Upz

Low Powerz...

07.10.31 IEEE NSS yasuo.arai@kek.jp

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0.15 μm SOI Pixel Process
Process

0.15μm Fully-Depleted SOI CMOS process,1 Poly, 5 Metal layers (OKI Electric Industry Co. Ltd.).

SOI wafer

Wafer Diameter: 150 mmφ,Top Si : Cz, ~18 Ω-cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz、700 Ω-cm (n-type), 650 μm thick (SOITEC)

Backside

Thinned to 350 μm, and plated with Al (200 nm).

p+/n+ Implant andContact formation

07.10.31 IEEE NSS yasuo.arai@kek.jp

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SOI Pixel Process Flow
SOI (40 nm)
Box (BuriedOxide)(200 nm)

650um

Handle Wafer

p+n+Handle Wafer

n+Handle Waferp+50~650um

Al07.10.31 IEEE NSS yasuo.arai@kek.jp

6Metal contact & p+ implant

1st AlHandle Wafer
07.10.31 IEEE NSS yasuo.arai@kek.jp

Copyright 2007 Oki Electric Industry Co.,Ltd

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Back Gate Effect
Substrate Voltage act as Back Gate,and change transistor threshold.

Back Gate

Threshold Variation

Copyright 2007 Oki Electric Industry Co.,Ltd07.10.31 IEEE NSS yasuo.arai@kek.jp

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p+ Guard for
I/O Buffer
It is hard to re-design
I/O buffers, so wejust surround thebuffer with p+ ring.

65 um

p+ ring
07.10.31 IEEE NSS yasuo.arai@kek.jp

9with p+ ring = 0V

10MHz Clockwithout p+ ringVdet=10V
OutIn

40V

07.10.31 IEEE NSS yasuo.arai@kek.jp10FY06 KEKMPW Run17 designs were submitted on
Dec. 5, 2006
2.4 x 2.4 mm2 --- 10 chips
5.0 x 5.0 mm2 --- 6 chips
10.2 x 10.2mm2 --- 1 chip

Top Cell Name

Chip size

VARPIXEL

2.4 mmOsaka Univ.

TOPPIXN

2.4 mm

KEK

OKI06122.4 mmTokyo Univ.

Achip

2.4 mm

LBL

OKI_TOP

2.4 mmFNAL(BNL)

ATEG

2.4 mm

JAXA/ISAS

BTEG

2.4 mm

JAXA/ISAS

CTEG

2.4 mm

JAXA/ISAS

isas_set0612

2.4 mm

JAXA/ISASRADFET1

2.4 mm

KEK

N20-4 Å------ HawaiiNSUBSTRATE 5.0 mm

U. of Hawaii

detectorPOLY

5.0 mmKEK

TOP_PIXELSTRIP

5.0 mmKEK

TOP_8PREAMP

5.0 mmKEK

5.0 mmKEK

TOPINTPIX

5.0 mmKEK

TOPCOUNT

10.2 mmKEK

N44-6 Å------ TOPTEG2

07.10.31 IEEE NSS yasuo.arai@kek.jp

Affiliation

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KEK SOI MPW run Wafer

20.8 mm

20.8 mm07.10.31 IEEE NSS yasuo.arai@kek.jp12KEK : I-V characterisiticof the detector
FY05

Round the corner of bias
ring.

Iback[uA]2.5 x 2.5 mm2 chip100FY06(Std.)p+/n+ implant with higher E(~x4.7 deep).

80

FY06(High E Impla)

60

FY06(Std. Impla)

40

FY05 chip

200050100150Vback[V]FY06(HE)

become better, andreached to ~130V.
Micro Discharges areobserved with infraredcamera
07.10.31 IEEE NSS yasuo.arai@kek.jp

I = 40 μA, T = 1 min

Corner of the bias ring
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KEK : Integration Type Pixel (INTPIX)z

20 μm x 20 μm pixel(Standard APS type pixel)

z128 x 128 pixelsz

5x 5 mm2 chip

07.10.31 IEEE NSS yasuo.arai@kek.jp

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INTPIX : Laser Image
2.56 mmPlastic Mask for PCB
is infront of the pixel.
Red Laser Illumination
λ=670 nm, φ~3mm

07.10.31 IEEE NSS yasuo.arai@kek.jp

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FY07 Submission Plan
• Next submission is scheduled on Jan 5th 2008.
• Due to OKI process movement, we will use 0.2 μm
process at the next run.

Wafer DiameterCore (I/O) Voltage
Gate Length
Gate Oxide Thickness
BOX Thickness
Ioff
07.10.31 IEEE NSS yasuo.arai@kek.jp

0.15 μm
6 inches
1.0V (1.8V)

0.2 μm8 inches
1.8V (1.8/3.3V)

0.14 μm
2.5/5 nm
200 nm

0.2 μm
4.5/7 nm
200 nm<100 pA/μm<0.1 pA/μm
16Summary• SOI pixel device has many interesting features to use
in HEP and Space applications.
• We successfully confirmed the basic operations of SOI
pixel detector with OKI 0.15 μm FD-SOI technology.
• We hosted the SOI pixel MPW run last year, andsubmitted 17 designs including US and Japan Univ./Labs.
• We are planning the next MPW run in Jan. 2008 with
0.2 μm technology• We are opening this unique process to everyone whointerested in the SOI pixel.
07.10.31 IEEE NSS yasuo.arai@kek.jp

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