Future Pixel Detectors
Fermilab 3D and SOI Technology
Developments
KEK

June 25, 2007
Marcel Demarteau
For the Fermilab Detector & Physics R&D Group
Tsukuba, Japan
June 25, 2007fVertex Detectors•

Vertex Pixel detectors are very difficult– Good angular coverage with many layers close to the interaction point– Excellent point resolution (< 4 µm)– Superb impact parameter resolution ( 5µm ⊕ 10µm/(p sin3/2θ) )– Transparency (~0.1% X0 per layer)– Robust pattern recognition (track finding in vertex detector alone)– Integration over small number of bunch crossings for ILC• <150 = ~50 µs– Electromagnetic Interference (EMI) immunity– Power Constraint (< ~100 Watts) with gas cooling– Radiation hard for LHC experiments•

The physics drives the design of HEP pixel electronics and detectors to evermore stringent requirements in all these areas•

As an example, a pixel detector for the LHC and ILC

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 2

f

LHC Pixel Detectors•

All LHC pixel detectors are hybrid pixel detectors:
Separate detector and readout chip, connectedby bump bonds– sensor and read-out chip (roc) can be
optimized separately•

Issues with this technology:– At least twice the mass of the detector since thereadout chip is as thick as the silicon sensor– Power consumption in the chip is high– Need active cooling of detectors– Bump bonding is very expensive– Pixel size is too large• CMS pixel size is 100x150µm2 = 15,000 µm2• Atlas pixel size is 50x400µm2 = 20,000 µm2• ILC need ~ 20x20µm2 = 400 µm2• Area LHC/ILC = 50

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

CMS

Slide 3f•

ILC Pixel Detectors
Vertex detector requirements– Very low mass: 0.1% X0 per layer (equivalent of 100 µm of Si)• Low mass requires no active cooling, hence low power– High resolution: impact parameter resolution of ~ 5 µm
• Requires smaller pixels which increases the readout circuit density– Good and robust pattern recognition, integrated design• Low occupancies, bunch crossing time stamp– Modest radiation tolerance for ILC applications

969 µs••~199 ms

969 µs

ILC beam structure– Five trains of 2625 bunches per second– Bunch separation of 369.2 ns
ILC Maximum hit occupancy– Assumed to be 0.03 particles/crossing/mm2– Assume 3 pixels hit/particle (obviously this depends somewhat on pixel size, hit
location, and charge spreading)– Hit rate = 0.03 part./bx/mm2 x 3 hits/part. x 2625 bx/train gives
252 hits/train/mm2

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 4f••

ILC Detector Geometry
At an e+e- linear collider there is a premium on the small angle region– more events are in the forward/backward regions than in the central
regions
Detector configurations– Short barrels with disks• Barrels: five layers, Longitudinal coverage: ± 62.5 mm, Radial coverage: 14<R<61 mm• Disks: Four disks, z = ± 72, ± 92, ± 123, ± 172 mm, Radial coverage: R<71 mm•– Long barrels, limited disk coverage
Extraction of signals, power distribution, cable plant non-trivial

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 5

Pixel Detectorsf•

As mentioned, pixel detectors are very difficult
–
–
–

•

Significant progress has been made to address these issues by integrating
sensors and front end electronics within the pixel cell:
Monolithic Active Pixel Sensors (MAPS)–•

Many competing requirements
All projects will benefit from advances in any area
New technologies are applicable to many areas of science

Fundamental limitations• Small signal dependent on epi thickness• Most designs are limited to NMOS transistors• Not 100% fill factor• Slow rise time set by diffusion

Fermilab is pursuing alternatives:––

SOI (Silicon On Insulator) Pixel Sensors• Offers improvements over MAPS
3D integrated circuits• Also SOI process, but offers improved performanceover SOI pixel sensors.

Pixel control, CDS,
A/D conversion
Diode

Diode

Analog readout Analog readout
circuitry
circuitry

Diode

Diode

A
S

Analog readout Analog readout
circuitry
circuitry

Conventional MAPS 4 Pixel Layout

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 6

SOI Detector ConceptfAdvantages
–
–
–
–
–

•

Bonded Wafer: low resistive top layer + high resistive substrate, separated
through a Buried OXide (BOX) layer
–
–
–

•
•
•
•

100% fill factor
Large and fast signal
Small active volume: highsoft error immunity
Full di-electric isolation:
latchup free
Low Junction Capacitance:high speed, low power

Top layer: standard CMOS Electronics (NMOS, PMOS, etc. can be used)
Bottom substrate layer forms detector volume
The diode implants are formed beneath the BOX and connected by vias

Monolithic detector, no bump bonds (lower cost, thin device)High density and smaller pixel size is possible
Small capacitance of the sense node (high gain V=Q/C)
Industrial standard technology (cost benefit and scalability)

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 7

Vertical Scale Integrated Circuits (3D)f•

SOI detector technology offers several advantages over MAPS; 3D offers
advantages over SOI detectors
Optical In•

Power InA 3D device is a chip comprised of
2 or more layers of semiconductor
devices which have been thinned,
bonded, and interconnected to forma monolithic circuit

Opto Electronics
and/or Voltage Regulation

Optical Out

Digital Layer
Analog Layer

50 um

Sensor Layer•

Advantages of 3D over SOI
–
–
–

•

Increased circuit density due to multiple tiers of electronics
Independent control of substrate materials for each of the tiers.
Ability to mate various technologies in a monolithic assemblyTechnology driven by industry––––

Circuit performance limited by interconnects• Stacked, wirebonded asics
Desire to limit area of active elements
Provide increased functionality
Reduce interconnect power, crosstalkFermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

System on a Chip
DRAM
Logic
MPU Core

ROM
AnalogCache

Slide 8

Benefits of Vertical Integrationf•

Many benefits of 3D integration – also for HEP applications
–
–
–
–
–
–
–
–

Integration of heterogeneous technologies possible
IC fabrication optimized for each functionality reducing cost & increasing yield• Process optimization for each layer (also called tier)
2-D
3-D
Replaces long horizontal traces with short verticalinterconnects
A/2
Interconnect length decreases therefore
Area A
R, L, C decreases for higher speed
Reduce interconnect power, crosstalk
A/2
Power, delay and noise reduction
Very long wire
Reduce chip I/O pads
Short verticalinterconnects
Provide increased functionality
Pixel control, CDS,
A/D conversion•

Benefits of pixellated arrays––

Massively parallel signal
processing
Dramatically increased
electronic functionality
in each pixel

Diode

Diode

Analog readout Analog readout
circuitry
circuitry

Diode

Diode

DigitalAnalogSensorAnalog readout Analog readout
circuitry
circuitry

Conventional MAPS 4 Pixel Layout
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

3D 4 Pixel Layout
Slide 9f

Key Technologies for 3D•

There are 4 key technologies for vertical scale integration– Wafer thinning• Target thickness < 30 µm• Thickness tolerance = ± 1 µm
• Temporary carrier mounting/demounting and thin die singulation without damage
to ICs– Through-wafer via formation and metallization• High aspect ratio 3-D interconnects through SiO2 and Si• Interconnects need to be insulated– High precision alignment• Uniform alignment < ±1 µm– Bonding between layers• Multiple techniques being employed•

Many of these technologies are also used in the development of SOI detectors

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 10

f
•
•

•

Key Technology: Wafer Thinning
For compact, low mass devices, layers to be thinned as much as possible
Through-wafer vias typically have an 8 to 1 aspect ratio. In order to keep
the area associated with the via as small as possible, the wafers should bethinned as much as possible
Thinning is typically done by a combination of grinding, lapping, andchemical or plasma etching

Photos fromMIT LLSix inch wafer thinned to 6 microns and mounted to 3 mil kapton.
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 11

f Key Technology: Via Formation and Metallization••

Two different procedures are generally followed: Via First or Via Last
– Via First: via hole creation and via metallization takes place on a wafer
before wafer bonding– Via Last: via hole creation and via metallization takes place on a wafer
after wafer bonding
Vias in CMOS are formed using the Bosch process and are passivated before
filling with metal, while vias in SOI are formed using a plasma oxide etchand are filled without passivation

Tier-2Metal

Via usingoxide etch
process(Lincoln
Labs)

SEM of 3 vias
using Boschprocess

Bond Interface

CVD-W
Plug
Tier-1
Metal

Typical diameters are 1-2 microns
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 12

f•

Key Technology: Wafer Alignment
Alignment of die-to-wafer (D2W) or wafer-to-wafer (W2W) is generally
better than 1 µm
– MIT-LL 0.5 µm 3-sigma overlay demonstrated

Photo courtesy of Ziptronix

Die to Wafer alignment
and placement

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Photo courtesy of Ziptronix

Wafer to Wafer alignment
and placement

Slide 13

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Key Technology: Wafer Bonding•

Two approaches being followed:•

Die-to-Wafer (D2W) Bonding– Lower throughput– Can handle multiple die sizes– known good die (KGD)
methods– Easier to stack mixed
technologies and/or materials– Lower development cost– die-to-die process can further
reduce development costs•

Wafer-to-Wafer (W2W) Bonding– High throughput– Compound yield loss
– Wafer size must match– Die size must match– Larger development costs

KGDÖ Dice/test

Die to wafer bonding
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Wafer to wafer bonding
Slide 14

f•

Key Technology: Wafer Bonding
Bonding techniques between die/wafer and wafer– Adhesive bondÖ

Polymer(BCB)– Oxide Bond: SiO2 to SiO2

Ö

SiO2
Bond

Ö

Cu3Sn
Eutectic
Bond

Ö

Cu
Bond

Ö

Oxide Metal
Bond– Cu Sn Eutectic

Cu– Cu Thermocompression

Cu– Direct Bond Interconnect (DBI) Metal•

Sn

Electrical connections are formed after the bonding process for the first two
processes; for the last three processes, the electrical and mechanicalconnections are made at the same time

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 15

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•

•

•

•

Advantages of SOI for 3D
The electrically active portion of
an integrated circuit wafer is < 1%of the total wafer thickness
Buried oxide layer in SOI provides
ideal etch stop for wafer thinning
operation prior to 3D integration
Full oxide isolation between
transistors allows direct 3D via
formation without the addedcomplexity of a via isolation layer

SOI Cross-Section
Bonding Layer
Buried Oxide
Handle Silicon

Oxide

~6 µm

~675 µm

SOI’s enhanced low-power operation(compared to bulk CMOS) reduces
circuit stack heat loadFermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 16

Development of a 3D Demo Chipf•

MIT Lincoln Laboratories (MIT-LL) has developed the technology thatenables 3D integration––•

Demonstrated the 3D technology
through fabrication of imaging devices
Has infrastructure to allow for 3D
Multi-Project Run fabrication

3D ViaWe were invited to participate in the
MIT-LL three-tier multi-project run––

3D design to be laid out in MIT-LL
0.18 µm SOI process• SOI provides additional advantages:
BOX, full isolation, direct via formation,enhanced low-power operation
3 levels of metal in each layer

•
•
•
•

Submission deadline was Oct. 15, 2006
Requested wafer space of ~ 2.5 x 2.5 mm2
Pixel size 20 x 20 µm; 64 x 64 pixel array
No integrated sensor•

Chip to be received sometime in fallFermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Tier 38.2 µmTier 27.8 µmoxide-oxide bondTier 16.0 µmSlide 17

f•

Architecture of Demonstrator Chip
Design:– Provide analog and binary readout information– Time stamping of pixel hit for ILC environment• Divide bunch train into 32 time slices; each hit pixel can store one time stamp equivalent
to 5 bits of time information– Sparsification to reduce data rate
• Use token passing scheme with look-ahead to reduce data output– During acquisition, a hit sets a latch– Sparse readout performed row by row with x- and y-address stored at end of row
and column– Chip divided into 3 tiers• Pixels as small as possible but with significant functionality.
• Design for 1000 x 1000 array but layout only for 64 x 64 array.
Test inject
Discriminator
Integrator

Time
stamp
circuit

Write data
Hit latch
S
Q
R

Vth
Read allAnalog out
Analog front end
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Pixel
skip
logic

D FF
Data clk

Pixel sparsification circuitry

T.S.
out

Read
data
To x, yaddress

Schematic pixel cell
block diagram

Time stamp
Slide 18

f

Pixel Readout Scheme•

Pixel being read points to the x address and y address stored on theperimeter.
At same time, time stamp information and analog pulse height is read out
During pixel readout, token scans ahead for the next hit pixel (200 ps/cell)••

Assume 1000 x 1000 array
X and Y addresses are 10
bits each

X
Y
Time

DigitalData Mux
X,Y,Time

Serial Data out(30 bits/hit)

Y address bus
Analogoutputs

Start
Readout
Token
10

Y=1

1

10

10
X=1

T1buf

X=2

T2buf

1

5

1

5

cell
1:1

T1

cell
2:1

T2

X=1000cell
1000:1
Token to row Y=2

cell
1:2

cell
2:2

Y=2

cell
1000:2
Token to row Y=3

cell
1:3

cell
2:3

cell
1000:3

Y=3

Note: All the Y address registers can be replaced by one counter thatis incremented by the last column token.

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 19

f
•
•

•

•

3D Three Tier Pixel Layout
Readout speed for an ILC environment
Assume 1k x 1k array with 20 x 20 µm2 pixels– First pixel in each row always read out• Adds 1000 cells, small increase indata volume– Time to scan 1 row:
200 ps x 1000 = 200 ns– Time to readout cell
30 bits x 20 ns/bit = 600 ns– Plenty of time to find next hit pixel
during readout
Assume maximum number of hits/chip of
250 hits/mm2– For a 1000 x 1000 array of 20 µm pixels,
100k hits/chip– For 50 MHz readout clock and 30 bits/hit,
readout time:
100,000 hits x 30 bits/hit x
20 ns/bit = 60 msec.
Readout time is far less than the ILC
allowed 200 msec. Thus the readout clock
can be even slower or several chips can be
put on the same bus. Readout time is evenless for smaller chips

Pad to sensor

Sample1

Sample2

VthAnalog

Delay

3D
vias

S. Trig

To analog output buses
5

Tier 2

Digital time stamp bus

Time Stamp
Write data

Analog T.S.

b0 b1 b2 b3 b4

Read data
Analog ramp bus

3D
via

Analog time output bus
In
Inject
Test input S.R.
pulse
Out

Y address
X address

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Tier 3Sample 1

D FF
Data clk

Tier 1
Token In Data Sparse.
Pixel
skip
logic

Q S
R

Token out

Read
all
Read data
Slide 20

f
•
•
•
•
•
•
•

•
•

Tier 1: Sparsification
OR for READ ALL cells
Hit latch
Pixel skip logic for token
passing
D flip flop (static),
conservative design
X, Y line pull down
Register for programmable
test input.
Could probably add disable
pixel feature with little
extra space
65 transistors
3 via pads

X, Y line
control
OR, SR FF
Token
D FF passing logic
Test input
circuit
20 µm

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 21

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•
•

•
•
•

Tier 2: Time Stamp
5 bit digital time stamp
Analog time stamp –resolution to be
determined by analog
offsets and off chip ADC
Gray code counter on
periphery72 transistors
3 viasb3
Analog
T. S.

b2
b1

b4
b0
20 µm
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 22

Tier 3: Analogue

f
•
•
•
•

•
•
•

Integrator
Double correlated
sample plus readout
Discriminator
Chip scale
programmablethreshold input
Capacitive test input
38 transistors
2 viasSchmitt
Trigger+NOR
Discriminator

DCS + Readout

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Integrator
Pad foredgeless
detector

Slide 23

3D Stack

f
•
•

•
•
•

•
•

Form 2 vias, 1.5 x 7.3 µm,
through tier 3 to tier 2Tier 3– Integrator, DCS plus readout– Discriminator– 2 vias– 38 transistors
Bond Tier 3 to Tier 2
Form 3 vias, 1.5 x 7.3 µm,
through Tier 2 to Tier 1
Tier 2– 5 bit digital time stamp– Analog time stamp (ts)
• Either analog or digital ts– 3 vias– 72 transistors
Bond Tier 2 to Tier 1
Tier 1– OR for READ ALL cells– Pixel skip logic for token passing– 3 vias– 65 transistors

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

175 Transistors
in 20 x 20 µm2 pixel

2000 ohm-cm p-type substrate

Buried Oxide(BOX) 400 nm
thick

Slide 24

SOI Detector Developmentf•

SOI detector development is being pursued by Fermilab at two different
foundries––

OKI Electric Industry Co. Ltd. in Japan through Multi-Project Wafer submission (KEK)
American Semiconductor Inc. (ASI) in US, through SBIR phase I grant (Cypress
semiconductor)

OKI

ASI

Process 0.15µm Fully-Depleted SOI CMOS
process

Process 0.18µm Partially-Depleted dual
gate SOI CMOS process,Dual gate transistor (Flexfet)
No poly, 5 Metal layers

1 Poly, 5 Metal layers
SOI
wafer

Wafer Diameter: 150 mmφ
Top Si : Cz, ~18 Ω-cm,
p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz、>1k Ω-cm
(No type assignment), 650 µm thickBackside Thinned to 350 µm
no contact processing
plated with Al (200 nm).

•

SOI
wafer

Wafer Diameter: 200 mmφHandle wafer: FZ>1k Ω-cm
(n type)Backside Thinned to 50-100 µm
polished, laser annealed andplated with Al.

Goal is to understand the advantages and problems of SOI detector design, inparticular issues related to trapped charges in the BOX layer due to radiationand its potential remedies through voltage on the substrate and the reductionof “back gate effect”

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 25

f

OKI Process•

KEK organized first SOI Detector Workshop (March 6, 2007 at KEK) and two
multi-project wafer (MPW) runs at the OKI foundry– The 2nd MPW run has 17 designs from 7 different organizations– A 3rd run is planned for later this yearnd
Reticule for 2

•

•

•
•

OKI MPW run

Fermilab submission on MPW: Counting pixel
detector plus readout circuit– Maximum counting rate ~ 1 MHz/pixel.
Simplified architecture due to design time
constraint– Reconfigurable counter/shift register• 12 bit dynamic range– Limited peripheral circuitry• Drivers and bias generator
Array size 64x64 pixels
350 micron detector thickness

Amplifier

ShaperFermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Discriminator

12bit Counter

Slide 26

Pixel Design in OKI Processf•

MAMBO Chip: Monolithic Active pixel Matrix with Binary cOunters–••

A wide dynamic range counting pixel detector plus readout circuitry, sensitive to100-400 keV electrons, high energy X-rays, and minimum ionizing particles,
designed in the OKI 0.15 micron process

OKI process incorporates diode formation by implantation through the BOX
Chip architecture (simplified due to design time constraint):
amplifier – shaper – discriminator – binary counter––Maximum counting rate ~ 1 MHz/pixel
Reconfigurable counter/shift register
•

–
–
–

–
–

12 bit dynamic range

Limited peripheral circuitry–
Drivers and bias generator
Submitted Dec. 15, ’06; delivered this month.

Array size 64x64 pixels, 26µmx26µm
13 µm implant pitch, to minimize the“back gate” effect•4 diodes per pixel

350 micron detector thickness

13 um

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 27

f•

Pixel Design in OKI Process
Schematic circuit diagram

Charge Sensitive Preamplifier
with CRRC shaper:~ 150 mV/1000 e-,
150 ns peaking time

280 transistors/pixel cell

CommonThresholdFor all
discriminators

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 28

f

Simplified 3x3 Matrix

Operates in twomodes:
Acquire/Read out

12 bit counter isreset by changing
counter to ashift register
configuration andshifting in zeros
during read out.

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 29

Pixel Cell Layoutf•Layout of single 26mmx26mm pixel cell

One of four
detector diodes

All analog
circuits arelocated incenter of
pixel cell
between
diodes andsurrounded
by guardring

One of twelve
D flip-flops
arranged aroundperimeter of pixel
cell

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

26 microns

Slide 30

Pixel Design in ASI Processf••

SBIR Phase I grant with American Semiconductor (ASI), Boise, Idaho
ASI process (0.18µm) based on an SOI dual gate transistor called a Flexfet™
– Flexfet has a top and bottom gate
– Bottom gate shields the transistor
channel from
• Charge build up in the BOX causedby radiation.
• Voltage on the substrate and thus
removes the back gate voltage problem–––

Modeling and process simulationof a thinned, fully depleted
sensor/readout device.
Studies of backside thinning,
implantation, and laser annealing
in collaboration with Cornell
Circuit design for ILC pixel cell
• Voltage ramp for time marker• ~20 micron analog pixel• Sample 1 - crossing time
• Sample 2 - time over threshold foranalogue pulse height information• Coarse time stamp

Diode simulation in Flexfet process

http://www.americansemi.com/
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 31

f Development of Thinned Edgeless Sensors••

3D chip provides only readout. In parallel we have submitted a design for
sensors on 6”, high resistivity, float-zone, n-type wafers to be bonded to 3Dchips
The sensors are of the “Thin Edgeless” design

20 um
Detector
bias

m
20 µ

To other
Diode implants pixels
Trench on
detectoredge filledwith polyand connected
to bottom
implant

Equipotential lines in detector near
one detector edge
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Implant withlaser annealing

Detector Cross section near
one detector edge

Slide 32•Producing a set of detectors at MIT-LL, thinned to 50-100 microns for beamand probe tests
n++
n+
–

–
–

•

Masks designed at FNAL, standard p-on-n diodes• Strip detectors (12.5 cm x ~2 cm)• Test structures
Sensors to mate with 3D chip, 20 micron pitch
Sensors to mate with FPIX chip, 50 micron pitch

Goal to validate the process––

Explore and validate the technologies
which provide thinned detectors
sensitive to the edge
Measure the actual dead region
in a test beambottom-side bias pads

Sensor Design

5 µ trench

f

20 µm

3D Chip sensor

50 µm

FPIX sensor
Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 33

Device Thinningf•

Gaining experience on device thinning andthinned devices– Thinning of individual FPIX die at RTI• Two step procedure:dead pixel areas– Backgrind and polish to 150 µm» 7 chips failed out of 72– Plasma thinning down to 50/25/15/10 µm» 4 responding out of 20 testable die;crack
all have areas of dead pixels• Repeat after evaluation– 6 chips out of 8 working (2 dead)– Thinning of full wafer at IZM• Yield ~50%••

No indication of subtle electrical effects associatedwith thinning the wafer. The IZM wafer looks(visual inspection) very good except.
Small (~10%) apparent noise and thresholddispersion increase observed for parts thinnedby both RTI & IZM that tested "good“ notunderstoodFermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 34

f••

Vertex Detector Mechanical Design
Multi-layered, high precision, very thin, low mass detectors– Goal: layer thickness of 0.1% X0 per layer, equivalent of 100 µm of Si
Collaborating with the University of Washington
on carbon-fiber mechanical support structures•

Developing techniques for fabricating and handlingthin-walled carbon fiber structures•

Prototypes of carbon-fiber support structures– Three prototype half-shell structures fabricatedfor evaluation and testing
Develop assembly tooling/mandrels– Assembly mandrel, end ring glue fixture andvacuum chuck for precision placement of siliconwafers on support structure
FEA analysis of mechanical and thermal behavior– Deflection under gravity OK• maximum deflection vector is about 0.6 µm– Thermal deflections unacceptably large• assuming -10 0C operation, CTE mismatch• CTE = -1.9 ppm/C. δmax = 10.3 µm••– CTESi is 2.49 ppm/K

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Prototype

T = -10 0C, CTE = -1.9 ppm/Cδmax = 10.3 µm

Slide 35

f

Fermilab Strategy•

We believe the 3D and SOI technologies are very promising – not just for
HEP pixel detectors
Our intent is to understand these technologies through the design andtesting of demonstrator devices with test structures for the ILC/LHC andother applications
With that goal, we are– Collaborating for the 3D technology with MIT-Lincoln Laboratory, RTI,
IZM, Ziptronix, …
– Exploring commercial processes which include processing of the handle
wafer as part of the fabrication process for SOI (OKI, American
Semiconductor)– Developing expertise in necessary technologies• Post processing (handling of thinned wafers, annealing, dicing…)
R&D is underway to understand– How to retain good, low leakage current, detector performance throughthe CMOS topside processing– What is the optimal process for forming the detector diodes?
• Model charge collection, shielding– Performance under radiation, notably behavior of the BOX
We are, in addition, carrying out R&D in mechanical support structures andsystem integration issues for pixel vertex detectors

•
•

•

•

Fermilab Pixel Technologies, KEK June 25, 2007 -- M. Demarteau

Slide 36