REVISIONSLTR

DESCRIPTIONA

Update boilerplate to current MIL-PRF-38535
requirements. - PHN

DATE

APPROVED

19-04-29

Thomas M. Hess•l~h

Prepared in accordance with ASME Y14.24.

Vendor item drawing

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REV STATUS
OF PAGESPMIC N/A

PREPARED BY
Phu H. Nguyen

Original date of drawing
YY MM DDCHECKED BY

14-04-07

APPROVED BY

Phu H. Nguyen

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil

TITLE
MICROCIRCUIT, DIGITAL, MIXED SIGNALMICRCONTROLLER, MONOLITHIC SILICON

Thomas M. Hess
SIZE

CODE IDENT. NO.

AREVDWG NO.

V62/13628

16236
A

PAGE

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

1

OF

36
5962-V077-19

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller microcircuit, with
an operating temperature range of -40°C to +105°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/13628

-

01

X

I

Drawing
numberE

I

Device type
(See 1.2.1)

I

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

MSP430F5328-EP

Mixed signal microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

X

64

Package style
Plastic quad flatpack, No-leads

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Material
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

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1.3 Absolute maximum ratings.

1/

Voltage applied at VCC to VSS .......................................................................................................... -0.3 V to 4.1 V
Voltage apply to any pin (excluding VCORE, LDOI) ...................................................................... -0.3 V to VCC + 0.3 V 2/
Diode current at any device pin ....................................................................................................... ±2 mA
Storage temperature ....................................................................................................................... -55°C to 150°C
3/
1.4 Thermal characteristics.

t--------~---+-----tlI I
Junction to ambient thermal resistance, still air θJA

Low K board (JESD 51-3)
High K board (JESD 51-7)

55
25
12
6

Junction to case thermal resistance, θJC
Junction to board thermal resistance, θJB°C/W

1.5 Recommended operating conditions.
Supply voltage during program execution and flas programming (AVCCx = DVCCx = VCC):
4/ 5/
PMMCOREVx = 0 .................................................................................................................... 1.8 V to 3.6 V
PMMCOREVx = 0,1 ................................................................................................................. 2.0 V to 3.6 V
PMMCOREVx = 0,1, 2 ............................................................................................................. 2.2 V to 3.6 V
PMMCOREVx = 0,1, 2, 3 ......................................................................................................... 2.4 V to 3.6 V
Supply voltage (AVSSx = DVSSx =VSS) .......................................................................................... 0 V
Operating free air temperature (TA) ................................................................................................. -40°C to 105°C
Operating junction temperature (TJ) ................................................................................................ -40°C to 105°C
Recommemnded capacitor at VCORE (CVCORE) (VCC = 3.3 V and TA = 25°C) ................................ 470 Typical nF
Capacitor ratio of DVCC to VCORE (CDVCC/CVCORE) ....................................................................... 10
Processor frequency (maximum MCLK frequency) 6/ (See Figure 4)
PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V, (default condition) .................................................... 0 MHz to 8.0 MHz
PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V ................................................................................... 0 MHz to 12.0 MHz
PMMCOREVx = 1, 2.2 V ≤ VCC ≤ 3.6 V ................................................................................... 0 MHz to 20.0 MHz
PMMCOREVx = 1, 2.4 V ≤ VCC ≤ 3.6 V ................................................................................... 0 MHz to 25.0 MHz

1/

2/
3/
4/
5/
6/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
All voltage referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD 020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC
can be tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side thresholdparameters for the exact values and further details.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
JESD51JESD51-3
JESD51-7
J-STD-020

–
–
–
–
–

Registered and Standard Outlines for Semiconductor Devices
Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device).
Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface
mount devices.

Applications for copies should be addressed to the Electronic Industries Alliance, 3103 North 10th Street, Suite 240–S, Arlington, VA
22201-2107 or online at https://www.jedec.org.
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Functional block diagram. The functional block diagram shall be as shown in figure 3.

3.5.4

Maximum system frequency. The maximum system frequency shall be as shown in figure 4.

3.5.5

SPI master mode, CKPH = 0. The SPI master mode, CKPH = 0 shall be as shown in figure 5.

3.5.6

SPI master mode, CKPH = 1. The SPI master mode, CKPH = 1 shall be as shown in figure 6.

3.5.7

SPI slave mode, CKPH = 0. The SPI slave mode, CKPH = 0 shall be as shown in figure 7.

3.5.8

SPI slave mode, CKPH = 1. The SPI slave mode, CKPH = 1 shall be as shown in figure 8.

3.5.9

I2C mode timing. The I2C mode timing shall be as shown in figure 9.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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3.5.10

Ports PU.0, PU.1 typical low level output characteristics. The ports PU.0, PU.1 typical low level output characteristics shallbe as shown in figure 10.

3.5.11

Ports PU.0, PU.1 typical high level output characteristics. The ports PU.0, PU.1 typical high level output characteristics shallbe as shown in figure 11.

3.5.12

Ports PU.0, PU.1 typical input threshold characteristics. The ports PU.0, PU.1 typical input threshold characteristics shall be
as shown in figure 12.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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TABLE I. Electrical performance
characteristics.
1/- TestExecution

Condition

Memory2/

VCC PMMCOREVx

1 MHz
Typ Max

Active Mode Supply Current into VCC Excluding External Current
IAM, Flash

3V

Flash

IAM, RAM

3V

RAM

Test

SymbolCondition
2/

0
1
2
3
0
1
2
3

VCC

Frequency (fDCO = fMCLK = fSMCLK)
Unit
8 MHz
12 MHz20 MHz25 MHzTyp Max Typ Max Typ Max Typ Max

3/ 4/ 5/

0.36
0.40
0.44
0.46
0.20
0.22
0.24
0.26

0.47

0.24

2.32
2.65
2.90
3.10
1.20
1.35
1.50
1.60

2.60

-40°C

PMMCOREVx Typ

Max

3/ 4/

Low power mode 0
6/ 7/
Low power mode 2
7/ 8/

ILPM0,

Low power mode 3,
crystal mode
9/ 7/

ILPM3,

73
79
6.5
7.0
1.60
1.65
1.75
1.8
1.9
2.0
2.0
1.1
1.1
1.2
1.3
0.9
1.1
1.2
1.3
0.15

ILPM2

2.2 V
3V
2.2 V
3V
2.2 V

XT1LF

3V
Low power mode 3,
VLO mode
7/ 10/

ILPM3,VLO

Low power mode 4
7/ 11/

ILPM4

Low power mode 4.5 12/

ILPM4.5

3V

3V

0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3

3V

4.4

2.0
2.2
2.4

2.2

7.1
7.6

7.7
10.1 11.0

1.30

Low Power Mode Supply Current (into VCC) Excluding External Current
1MHz

mA
4.0
4.3
4.6

mA
3.7
3.9

25°C

4.2
5.3

60°C

Typ Max Typ
77
85
80
83
92
88
6.5
12
10
7.0
13
11
1.90
2.6
2.00
2.7
2.15
2.9
2.1 2.9 2.8
2.3
2.9
2.4
3.0
2.5 3.9 3.1
1.4 2.7 1.9
1.4
2.0
1.5
2.1
1.6 3.0 2.2
1.1 1.5 1.8
1.2
2.0
1.2
2.1
1.3 1.6 2.2
0.18 0.35 0.26

6.2

Unit

105°C

Max

Typ

Max

85
95
11
12
5.6
5.9
6.1
5.8
6.1
6.3
6.4
4.9
5.2
5.3
5.4
4.8
5.1
5.2
5.3
0.5

97
105
17
18

µA

8.3

9.3
7.4

8.5
7.3

8.1
1.0

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Min

Schmitt-Trigger Inputs – General Purpose I/O 13/(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
Positive going input threshold voltage
VIT+
Negative going input thresholdvoltage

VIT+

Input voltage hysteresis (VIT+ - VIT-)

Vhys

Pullup/Pulldown resistor

RPull

Input capacitance
Inputs – Ports P1 and P2 15/(P1.0 to P1.7, P2.0 to P2.7)
External interrupt timing
16/

CI

-

I

1.8 V
3V
1.8 V
3V
1.8 V
3V

For pullup: VIN = VSS
For pulldown: VIN = VCC
VIN = VSS or VCCt(int)

Limits

VCC

External trigger pulse
width to set interrupt flag

0.80
1.50
0.45
0.75
0.3
0.4
20

Unit

Typ

Max

35

1.40
2.10
1.00
1.65
0.8
1.0
50

5

2.2 V,
3V

Leakage Current – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
High-impedance leakage current
Ilkg(Px.x)
17/ 18/
1.8 V,
3V
Outputs – General Purpose I/O (Full Drive Strength)(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
I(OHmax) = –3 mA 19/
1.8 V
High level output voltage
VOH
I(OHmax) = –10 mA 20/
I(OHmax) = –5 mA 19/
3V
I(OHmax) = –15 mA 20/
I(OLmax) = 3 mA 19/
1.8 V
Low level output voltage
VOL
I(OLmax) = 10 mA 20/
I(OLmax) = 5 mA 19/
3V
I(OLmax) = 15 mA 20/

V

kΩ
pF

20

ns

I- -

VCC - 0.25
VCC - 0.60
VCC - 0.25
VCC - 0.60
VSS
VSS
VSS
VSS

±50

nA

VCC
VCC
VCC
VCC
VSS + 0.25
VSS + 0.60
VSS + 0.25
VSS + 0.60

V

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Limits

VCC
Min

Outputs – General Purpose I/O (Reduced Drive Strength)(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
I(OHmax) = –1 mA 19/
High level output voltage
VOH
I(OHmax) = –3 mA 20/
I(OHmax) = –2 mA 19/
I(OHmax) = –6 mA 20/
I(OLmax) = 1 mA 19/
Low level output voltage
VOL
I(OLmax) = 3 mA 20/
I(OLmax) = 2 mA 19/
I(OLmax) = 6 mA 20/
Output Frequency – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
VCC = 1.8 V,
22/ 23/
PMMCOREVx = 0
fPx.yPort output frequency
VCC = 3 V,
(with load)
PMMCOREVx = 3
VCC = 1.8 V,
ACLK,
PMMCOREVx = 0
SMCLK,
Clock output frequency
fPort_CLK
MCLK,
VCC = 3 V,
CL = 20 pF
PMMCOREVx = 3
23/

1.8 V
3V
1.8 V
3V

Typ

VCC - 0.25
VCC - 0.60
VCC - 0.25
VCC - 0.60
VSS
VSS
VSS
VSS

Unit
Max

VCC
VCC
VCC
VCC
VSS + 0.25
VSS + 0.60
VSS + 0.25
VSS + 0.60

V

16

MHz

25
16
25

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolCrystal Oscillator, XT1, Low-Frequency Mode

Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode

XT1 oscillator crystal frequency,
LF modeXT1 oscillator logic-level squarewave input frequency, LF modefXT1,LF,SW

XTS = 0, XT1BYPASS = 1

OALF

Integrated effective load
capacitance, LF mode

CL,eff28/

Duty cycle, LF mode
fFault,LF

tSTAR,LF
Startup time, LF modeMin

fXT1,LF0

ΔIDVCC.LF

Limits

VCC

24/
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
XTS = 0, XT1BYPASS = 0

Oscillation allowance for LF
crystals
27/

Oscillator fault frequency, LF
mode
30/

Conditions
2/

Typ

3V

Unit
Max

0.075

µA

0.170

0.290

32768

25/ 26/

10

XTS = 0,XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0,XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0 29/
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
XTS = 0
31/

32768

Hz
50

KHz

210

kΩ

300

2
5.5
8.5
12.0

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C, CL,eff = 12 pF

pF

30

70

%

10

10000

Hz

3V

1000

ms

500

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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9TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

VCC

fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
XT2DRIVEx = 0, XT2BYPASS = 0 34/
XT2DRIVEx = 1, XT2BYPASS = 0 34/
XT2DRIVEx = 2, XT2BYPASS = 0 34/
XT2DRIVEx = 3, XT2BYPASS = 0 34/
XT2BYPASS = 1 34/
35/

3V

Limits
Min

Typ

Unit
Max

Crystal Oscillator, XT2

XT2 oscillator crystal current
consumption

XT2 oscillator crystal frequency, mode 0
XT2 oscillator crystal frequency, mode 1
XT2 oscillator crystal frequency, mode 2
XT2 oscillator crystal frequency, mode 3
XT2 oscillator logic-level square wave
input frequency, bypass mode

Oscillation allowance for HF crystals
36/

IDVCC.XT2

fXT2,HF0
fXT2,HF0
fXT2,HF0
fXT2,HF0

fXT2,HF,SW

OAHF

tSTART,HF

Startup time

Integrated effective load capacitance, HF
mode
32/ 37/
Duty cycle, HF mode
Oscillator fault frequency 38/

XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 p
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 12 MHz, CL,eff = 15 p
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 20 MHz, CL,eff = 15 p
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 32 MHz, CL,eff = 15 p
fOSC = 6 MHz,XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
fOSC = 20 MHz,XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF

200

260

325

450

4
8
16
24
0.7

8
16
24
32
32

MHz

MHz

450

Ω

320
200
200
3V

0.5

ms

0.3

CL,eff

fFault,HFµA

1
Measured at ACLK, fXT2,HF2 = 20 MHz
XT2BYPASS = 1
39/

40
30

pF

50

60
300

%
kHz

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Internal Very-Low-Power Low-Frequency Oscillator (VLO)
VLO frequency
fVLO
Measured at ACLKVLO frequency temperature drift
dfVLO/dT
Measured at ACLK

LimitsVCC

1.8 V to 3.6 V
1.8 V to 3.6 V

40/

VLO frequency supply voltage drift
dfVLO/dVCC
Measured at ACLK 41/
Duty cycle
Measured at ACLKInternal Reference, Low-Frequency Oscillator (REFO)REFO oscillator current consumption
IREFO
TA = 25°C
REFO frequency calibrated
Measured at ACLK
fREFO
Full temperature range
REFO absolute tolerance calibrated
TA = 25°C
REFO frequency temperature drift
dfREFO/dT
Measured at ACLK 40/
REFO frequency supply voltage drift
dfREFO/dVCC Measured at ACLK 41/
Duty cycle
Measured at ACLKREFO startup time
tSTART
40%/60% duty cycle

I

1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
3V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V

I

Unit

Min

Typ

Max

6

9.4
0.5

14

40

I

4
50

I 60 I

3
32768
±3.5
±1.5

40

0.01
1.0
50
25

60

kHz
%/°C
%/V
%
µA
Hz
%
%
%/°C
%/V
%
µs

See footnotes at end of table.

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11

TABLE I. Electrical performance characteristics - Continued. 1/
Test
DCO frequency
DCO frequency (0, 0) 42/
DCO frequency (0, 31) 42/
DCO frequency (1, 0) 42/
DCO frequency (1, 31) 42/
DCO frequency (2, 0) 42/
DCO frequency (2, 31) 42/
DCO frequency (3, 0) 42/
DCO frequency (3, 31) 42/
DCO frequency (4, 0) 42/
DCO frequency (4, 31) 42/
DCO frequency (5, 0) 42/
DCO frequency (5, 31) 42/
DCO frequency (6, 0) 42/
DCO frequency (6, 31) 42/
DCO frequency (7, 0) 42/
DCO frequency (7, 31) 42/
Frequency step between range
DCORSEL and DCORSEL + 1
Frequency step between tap
DCO and DCO + 1
Duty cycle
DCO frequency temperaturedrift
DCO frequency voltage drift

SymbolfDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fCORSELSDCO

Conditions
2/

LimitsMin

DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
Measured at SMCLK

Typ

Unit
Max

0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
12.3
2.5
23.7
4.6
39.0
8.5
60
1.2

0.20
1.70
0.36
3.45
0.75
7.38
1.51
14.0
3.2
28.2
6.0
54.1
10.7
88.0
19.6
135
2.3

1.02

1.12

40

60

MHz

ratio

dfDCO/dTfDCO = 1 MHz

50
0.1

%

dfDCO/dVCC

fDCO = 1 MHz

1.9

%/V

CODE IDENT NO.
16236

DWG NO.

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REV

PAGE

%/°C

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

A

12

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolPMM, Brown-Out Reset (BOR)
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis�����/NMI pin to accept a
Pulse length required at RST
reset
PMM, Core Voltage
Core voltage, active mode, PMMCOREV = 3
Core voltage, active mode, PMMCOREV = 2
Core voltage, active mode, PMMCOREV = 1
Core voltage, active mode, PMMCOREV = 0
Core voltage, low current mode, PMMCOREV = 3
Core voltage, low current mode, PMMCOREV = 2
Core voltage, low current mode, PMMCOREV = 1
Core voltage, low current mode, PMMCOREV = 0
PMM, SVS High SideSVS current consumption

Limits

Unit

Min

Typ

Max

0.80
60
2

1.30

1.45
1.50
250

V(DVCC_BOR_IT–)
V(DVCC_BOR_IT+)
V(DVCC_BOR_hys)
tRESET| dDVCC/dt | < 3 V/s| dDVCC/dt | < 3 V/s

VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)

2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V

1.90
1.80
1.60
1.40
1.94
1.84
1.64
1.44

V

SVSHE = 0, DVCC = 3.6 V
SVSHE = 1, DVCC = 3.6 V,
SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V,
SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
SVSHE = 1, SVSHRVL = 1
SVSHE = 1, SVSHRVL = 2
SVSHE = 1, SVSHRVL = 3
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
SVSHE = 1, SVSMHRRL = 4
SVSHE = 1, SVSMHRRL = 5
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
SVSHE = 1, SVSHFP = 1
dVDVCC/dt = 10 mV/μs,
SVSHE = 1, SVSHFP = 0
dVDVCC/dt = 1 mV/μs
SVSHE = 0 → 1, SVSHFP = 1
dVDVCC/dt = 10 mV/μs,
SVSHE = 0 → 1, SVSHFP = 0
dVDVCC/dt = 10 mV/μs,

0
200

nA
nA

1.5

µA

I(SVSH)SVSH on voltage level

43/

V(SVSH_IT–)SVSH off voltage level

43/

V(SVSH_IT+)SVSH propagation delay

tpd(SVSH)

SVSH on or off delay timet(SVSH)

DVCC rise time

Conditions
2/dVDVCC/dt

1.57
1.79
1.98
2.10
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90

1.68
1.88
2.08
2.18
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
2.5

1.78
1.98
2.21
2.31
1.85
2.07
2.28
2.42
2.55
2.88
3.23
3.23

V
V
mV
µs

V

µs

20
12.5
100
0

1000

V/s

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolPMM, SVM High SideSVMH current consumption

I(SVMH)

SVMH on or off voltage level
44/

V(SVMH)

SVMH propagation delay

tpd(SVMH)

SVMH on or off delay timet(SVMH)

Conditions
2/

LimitsMin

SVMHE = 0, DVCC = 3.6 V
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
SVMHE = 1, SVSMHRRL = 1
SVMHE = 1, SVSMHRRL = 2
SVMHE = 1, SVSMHRRL = 3
SVMHE = 1, SVSMHRRL = 4
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, SVMHFP = 1
dVDVCC/dt = 10 mV/μs,
SVMHE = 1, SVMHFP = 0
dVDVCC/dt = 1 mV/μs
SVMHE = 0 → 1, SVMHFP = 1
dVDVCC/dt = 10 mV/μs,
SVMHE = 0 → 1, SVMHFP = 0
dVDVCC/dt = 10 mV/μs,

1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90

Typ

Unit
Max

0
200
1.5
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
3.75
2.5

1.85
2.07
2.28
2.42
2.55
2.88
3.23
3.23

nA
nA
µA
V

µs

20
12.5

µs

100

PMM, SVS Low SideSVSL current consumption

I(SVSL)SVSL propagation delay

tpd(SVSL)SVSL on or off delay timet(SVSL)SVSLE = 0, PMMCOREV = 2
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/μs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/μs, SVSLFP = 0
SVSLE = 0 → 1, dVCORE/dt = 10 mV/μs, SVSLFP = 1
SVSLE = 0 → 1, dVCORE/dt = 1 mV/μs, SVSLFP = 0

0
200
1.5
2.5
20
12.5
100

nA
nA
µA
µs

SVMLE = 0, PMMCOREV = 2
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/μs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/μs, SVMLFP = 0
SVMLE = 0 → 1, dVCORE/dt = 10 mV/μs, SVMLFP = 1
SVMLE = 0 → 1, dVCORE/dt = 1 mV/μs, SVMLFP = 0

0
200
1.5
2.5
20
12.5
100

nA
nA
µA
µs

PMM, SVM Low Side
SVML current consumption

I(SVML)

SVML propagation delay

tpd(SVML)

SVML on or off delay timet(SVML)See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/Min

Wake-Up From Low Power Modes and Reset
Wake up time from LPM2,tWAKE-UP- PMMCOREV = SVSMLRRL = n fMCLK ≥ 4.0 MHz
LPM3, or LPM4 to active
FAST(where n = 0, 1, 2, or 3),
1.0 MHz < fMCLK
mode
45/
SVSLFP = 1< 4.0 MHz
Wake up time from LPM2,tWAKE-UP- PMMCOREV = SVSMLRRL = n
LPM3, or LPM4 to active
SLOW
where n = 0, 1, 2, or 3),
mode
46/
SVSLFP = 0
Wake up time from LPM4.5 to tWAKE-UPactive mode
45/
LPM5
tWAKE-UPWake up time from �����
RST orRESET
BOR event to active mode
47/
Timer_A
Internal: SMCLK, ACLK,
Timer_A input clockfTA
External: TACLK,
frequency
Duty cycle = 50% ± 10%
All capture inputs
Timer_A capture timingtTA,cap
Minimum pulse width required for capture
Timer_B
Internal: SMCLK, ACLK,
Timer_B input clock
fTB
External: TBCLK,
frequency
Duty cycle = 50% ± 10%
All capture inputs
Timer_B capture timing
tTB,cap
Minimum pulse width required for capture
USCI (UART Mode) Recommended Operating Conditions
Internal: SMCLK, ACLK,USCI input clock frequency
fUSCI
External: UCLK,
Duty cycle = 50% ± 10%
BITCLK clock frequency
fBITCLK(equals baud rate in MBaud)USCI (UART Mode)
UART receive deglitch time

Limits

VCC

Typ

Max

3.5
4.5

7.5
9

µs

150

165

µs

2

3

ms

2

3

ms

25

MHz

1.8 V,
3V
1.8 V,
3V

20

ns

1.8 V,
3V
1.8 V,
3V

25

MHz

20

ns

fSYSTEM

MHz

1

2.2 V
3V

tT

Unit

50
50

USCI (SPI Master Mode) Recommended Operating Conditions
Internal: SMCLK, ACLK,USCI input clock frequency
fUSCI
Duty cycle = 50% ± 10%

600
600

ns

fSYSTEMMHz

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolUSCI (SPI Master Mode)49/

USCI input clock frequency
SOMI input data setup time

Conditions
2/

Min

tHD,MIPMMCOREV = 0

PMMCOREV = 0
PMMCOREV = 3

tVALID,MO50/

SIMO output data hold time

tHD,MO
51/

Unit
Max
fSYSTEM

PMMCOREV = 3

SIMO output data valid timeTypsee FIGURE 5 and 6
SMCLK, ACLK,
fUSCIDuty cycle = 50% ± 10%
tSU,MISOMI input data hold time

LimitsVCC

UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3

1.8 V
3V
2.4 V
3V
1.8 V
3V
2.4 V
3V
1.8 V
3V
2.4 V
3V
1.8 V
3V
2.4 V
3V

55
38
30
25
0
0
0
0

MHz
ns

20
18
16
15
-10
-8
-10
-8

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test
USCI (SPI Slave Mode)

Symbol52/

Conditions
2/Min

tSTE,LEAD

1.8 V
3V
2.4 V
3V
1.8 V
3V
2.4 V
3V
1.8 V
3V
2.4 V
3V
1.8 V
3V
2.4 V
3V
1.8 V
3V
2.4 V
3V
1.8 V
3V
2.4 V
3V
1.8 V
3V

PMMCOREV = 0
PMMCOREV = 3

STE lag time, Last clock to STE hightSTE,LAG

PMMCOREV = 0
PMMCOREV = 3

STE access time, STE low to SOMI
data outtSTE,ACC

STE disable time, STE high to SOMI
high impedancetSTE,DISSIMO input data setup time

tSU,SIPMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3

tHD,SIPMMCOREV = 0
PMMCOREV = 3

SOMI output data valid time(

SOMI output data hold time(

Typ

Unit
Max

see FIGURE 7 and 8

STE lead time, STE low to clock

SIMO input data hold time

LimitsVCC

tVALID,SO

tHD,SOUCLK edge to SOMI valid,
CL = 20 pF
PMMCOREV = 0
UCLK edge to SOMI valid,
CL = 20 pF
PMMCOREV = 3
CL = 20 pF
PMMCOREV = 0
CL = 20 pF
PMMCOREV = 3

11
8
7
6
3
3
3
3
66
50
36
30
30
23
16
13
5
5
2
2
5
5
5
5
76
60

2.4 V
3V
1.8 V
3V
2.4 V
3V

ns

44
40
18
12
10
8

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Limits

VCC
Min

Typ

Unit
Max

USCI (I2C Mode) see FIGURE 9
USCI input clock frequency

fUSCI

SCL clock frequency

fSCL

Hold time (repeated) START

tHD,STA

Setup time for a repeated STARTtSU,STA

Data hold time
Data setup time

tHD,DATtSU,DAT

Setup time for STOP

tSU,STO

Pulse width of spikes suppressedby input filter

Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%

fSYSTEM MHz

2.2 V, 3 V
2.2 V, 3 V

fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz

Input MUX ON resistance
12-Bit ADC, Timing Parameters

RI

ADC conversion clockfADC12CLKInternal ADC12 oscillator

fDC12OSC

Conversion timetCONVERT

Sampling time

tSample

600
600

ns

2.2

3.6

V

0
125
150
20

AVCC
155
220
25

V
µA

10

200

1900

Ω

0.45

4.8

5.0

MHz

0.45

2.4

4.0

0.45

2.4

2.7

4.2
2.4

4.8

5.4
3.1

2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V

fSCL ≤ 100 kHz
fSCL > 100 kHz

2.2 V
3V

12-Bit ADC, Power Supply and Input Range Conditions
55/
AVCC and DVCC are connected together,
Analog supply voltage
AVCC
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
Analog input voltage range 56/
V(Ax)All ADC12 analog input pins Ax
Operating supply current into
IADC12_A fADC12CLK = 5.0 MHz
58/
57/
AVCC terminal
CI400

2.2 V, 3 V

tSP

Input capacitance

0
4.0
0.6
4.7
0.6
0
250
4.0
0.6
50
50

For specified performance of ADC12 linearity
parameters using an external reference
voltage or AVCC as reference59/
For specified performance of ADC12 linearity
parameters using the internal reference 60/
For specified performance of ADC12 linearity
parameters using the internal reference 61/
ADC12DIV = 0, fADC12CLK = fADC12OSC
REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock
External fADC12CLK from ACLK, MCLK, or
SMCLK,ADC12SSEL ≠ 0
RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,
Ƭ = [RS + RI] × CI

ns
ns
µs

2.2 V
3V

Only one terminal Ax can be selected at onetime
0 V ≤ VAx ≤ AVCC
2.2 V, 3 V

2.2 V, 3 V
2.2 V, 3 V

kHz
µs

pF

MHz
µs

63/

2.2 V, 3 V

1000

ns

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Limits

VCC

Min
12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
1.4 V ≤ dVREF ≤ 1.6 V
66/
2.2 V, 3 V
Integral linearity error
EI
1.6
V
<
dVREF
66/
65/
Differential linearity error
65/

66/

2.2 V, 3 V

dVREF ≤ 2.2 V
66/
dVREF > 2.2 V
66/
Gain error
67/
EG
66/
dVREF
≤ 2.2 V
66/
Total unadjusted error
ET
dVREF > 2.2 V
66/
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz
Integral linearity error
EI
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz
65/

2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V

Offset error

67/

ED
EO

Differential linearity error
65/

ED

Offset error

67/

EO

Gain error

67/

EG

Total unadjusted error

ET

Typ

fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz

2.2 V, 3 V

ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz

2.2 V, 3 V

Max
±2.0
±1.7

LSB

±1.0
±1.0
±1.0
±1.0
±1.4
±1.4

2.2 V, 3 V

ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0

Unit

±2.0
±2.0
±2.0
±3.5
±3.5
±1.7
±2.5

-1.0
-1.0
-1.0

2.2 V, 3 V
2.2 V, 3 V

±1.0
±1.0
±1.0

±1.4

±2.0
±1.5
±2.5
±2.0
±2.0
±2.0
±1.5%
69/
±3.5
±1.5%
69/

LSB

VREF
LSB
VREF

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/Min

12-Bit ADC, Temperature Sensor and Built-In VMID
70/
ADC12ON= 1, INCH = 0Ah,
71/
VSENSORTA = 0°C
ADC12ON = 1, INCH = 0Ah
TCSENSOR
Sample time required
if channel 10 is selected 72/
AVCC divider at channel 11,
VAVCC factor

tSENSOR(sample)
VMID

ADC12ON = 1, INCH = 0Bh
ADC12ON = 1, INCH = 0Bh

Sample time requiredtVMID(sample)
if channel 11 is selected 73/
REF, External Reference74/
Positive external reference
VeREF+
voltage input
Negative external reference
VREF–/VeREF–
voltage input
Differential external reference(VeREF+ –voltage input
VREF–/VeREF–)

ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB

Capacitance at VREF+/-terminal

IVeREF+,
IVREF–/VeREF–

2.2 V
3V
2.2 V
3V
2.2 V
3V
2.2 V

ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB

AVCC divider at channel 11

Static input current

Limits

VCC

Typ

Unit
Max

680
680
2.25
2.25
100
100
0.48
AVCC
1.06
1.44
1000

2.2 V
3V
2.2 V, 3 V

mV
mV/°C
µs

0.5
AVCC
1.1
1.5

0.52
AVCC
1.14
1.56

V
V
ns

VeREF+ > VREF–/VeREF–

75/

1.4

AVCC

VeREF+ > VREF–/VeREF–

76/

0

1.2

VeREF+ > VREF–/VeREF–

77/

1.4

AVCC

2.2 V, 3 V

-26

26

µA

2.2 V, 3 V

-1

1

µA

1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V, fADC12CLK = 5 MHz,ADC12SHTx = 1h,
Conversion rate 200 ksps
1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V, fADC12CLK = 5 MHz,ADC12SHTx = 8h,
Conversion rate 200 ksps

10
78/

CVREF+/-VµF

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test
REF, Built-In Reference

Positive built-in reference
voltage outpu

AVCC minimum voltage,
Positive built-in reference
activeOperating supply current
into AVCC terminal(

SymbolConditions
2/

Unit

Min

Typ

Max

3V

2.462

2.50

2.537

3V

1.950

1.98

2.009

2.2 V,
3V

1.467

1.49

1.512

3V

70

100

µA

3V

0.45

0.75

mA

3V

210

310

µA

3V

0.95

1.7

mA

2500

µV/mA

100

pF

30

50

ppm/°C

120

300

µV/V

79/

VREF+

AVCC(min)IREF+

REFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {1} for 2.0 V,
REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {0} for 1.5 V
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
ADC12SR = 1 82/ , REFON = 1,
REFOUT = 0, REFBURST = 0
ADC12SR = 1 82/ , REFON = 1,
REFOUT = 1, REFBURST = 0
ADC12SR = 1 82/ , REFON = 1,
REFOUT = 0, REFBURST = 0
ADC12SR = 1 82/ , REFON = 1,
REFOUT = 1, REFBURST = 0
REFVSEL = (0, 1, 2},
IVREF+ = +10 μA/–1000 μA,
AVCC = AVCC(min) for each reference level,
REFVSEL = (0, 1, 2}, REFON = REFOUT = 1

Load-current regulation,
VREF+ terminal(

IL(VREF+)

Capacitance at VREF+
terminals

CVREF+

REFON = REFOUT = 1

Temperature coefficient ofbuilt-in reference

TCREF+

Power supply rejection
ratio (DC)

PSRR_DCPower supply rejection
ratio (AC)

PSRR_AC

IVREF+ = 0 A,
REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC(min) - AVCC(max),
TA = 25°C, REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC(min) - AVCC(max),
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC(min) - AVCC(max),
REFVSEL = (0, 1, 2}, REFOUT = 0,
REFON = 0 → 1
AVCC = AVCC(min) - AVCC(max),
CVREF = CVREF(max),
REFVSEL = (0, 1, 2}, REFOUT = 1,
REFON = 0 → 1

Settling time of reference
voltage

LimitsVCC

tSETTLE

V

2.2
2.3
2.8

20

6.4

mV/V

75

75

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Comparator B
Supply voltage

Symbol

IAVCC_COMP

Quiescent current of local reference
voltage amplifier into AVCC
Common mode input range
Input offset voltage

IAVCC_REF

RSIN

Propagation delay, response time

tPD

Comparator enable time, settling
time
Resistor reference enable time
Reference voltage for a given tap

tPD,filter

tEN_CMPtEN_REFVCB_REF

Typ

1.8
1.8 V
2.2 V
3V
2.2/3 V
2.2/3 VCBPWRMD = 00

30
40
10
0.1

CBREFACC = 1, CBREFLx = 01
CBPWRMD = 00
CBPWRMD = 01, 10

CIN

Series input resistance

Propagation delay with filter active

Min

CBPWRMD = 00
CBPWRMD = 00

VIC
VOFFSET

Limits

VCC

VCC

Comparator operating supply current
into AVCC. Excludes reference
resistor ladder

Input capacitanceConditions
2/

Unit
Max
3.6
40
50
65
30
0.5
22

V
µA

VCC - 1
±20
±10

V
mV

µA

5
3

4

0.35

0.6

450
600
50
1.0

0.6

1.0

1.8

1.0

1.8

3.4

1.8

3.4

6.5

CBON = 0 to CBON = 1
CBPWRMD = 00, 01, 10

1

2

CBON = 0 to CBON = 1

1
VIN x
(n+1)
/32

1.5

ON - switch closed
OFF - switch opened
CBPWRMD = 00, CBF = 0
CBPWRMD = 01, CBF = 0
CBPWRMD = 10, CBF = 0
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 1130

VIN = reference into resistor ladder(n = 0 to 31)

pF
kΩ
MΩ
ns
ns
µs
µs

V

Ports PU.0 and PU.1
High-level output voltage

VOH

Low-level output voltage

VOL

High-level input voltage

VIH

Low-level input voltage

VIL

VLDOO = 3.3 V ± 10%, IOH = -25 mA,
See Figure 11 for typical characteristics
VLDOO = 3.3 V ± 10%, IOL = 25 mA,
See Figure 10 for typical characteristics
VLDOO = 3.3 V ± 10%,
See Figure 12 for typical characteristics
VLDOO = 3.3 V ± 10%,
See Figure 12 for typical characteristics

2.4

V
0.4

2.0
0.8

See footnotes at end of table.

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Test
LDO-PWR (LDO Power System)
LDO input detection threshold
LDO input voltage
LDO output voltage
LDOO terminal input voltage with LDO disabled
Maximum external current from LDOO terminal
LDO current overload detection
85/
LDOI terminal recommended capacitanceLDOO terminal recommended capacitance
Settling time VLDOFlash Memory
Program or erase supply voltage
Average supply current from DVCC during program
Average supply current from DVCC during erase
Average supply current from DVCC during masserase or bank erase
Cumulative program time
Program and erase endurance
Data retention duration
Word or byte program time
Block program time for first byte or word
Block program time for each additional byte or word,
except for last byte or word
Block program time for last byte or word
Erase time for segment, mass erase, and bankerase (when available)
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)

SymbolVLAUNCH
VLDOI
VLDO
VLDO_EXT
ILDOO
IDET
CLDOI
CLDOO
tENABLE

DVCC(PGM/ERASE)IPGM
IERASEIMERASE,
IBANK
tCPT

Conditions
2/

Limits
Min

Typ

3.76
3.3
LDO disabled
LDO is on

1.8
60

Unit
Max
3.75
5.5
±9%
3.6
20
100

2

mA
mA
µF
nF
ms

3.6
5
11
11

V
mA
mA
mA

16

ms
cycles
years
µs

4.7
220
Within 2%, recommended
capacitances
1.8
3
6
6
86/

V

tBlock, 1–(N–1)

TJ = 25°C
87/
87/
87/

104
100
64
49
37

tBlock, N
tErase

87/
87/

55
23

73
32

ms

0

1

MHz

tRetention
tWord
tBlock, 0

fMCLK,MGR

105
85
65
49

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolJTAG and Spy-Bi-Wire Interface
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse length
Spy-Bi-Wire enable time (TEST high toacceptance of first clock edge)
88/
Spy-Bi-Wire return to normal operation time
TCK input frequency, 4-wire JTAGInternal pulldown resistance on TEST89/

Conditions
2/fSBW
tSBW,LowtSBW, En

LimitsVCC
Min
2.2 V, 3 V
2.2 V, 3 V

Typ

0
0.025

MHz
µs

1

tSBW,Rst

15
0
0
45

2.2 V
3V
2.2 V, 3 V

Rinternal

Max
20
15

2.2 V, 3 V

fTCK

Unit

60

100
5
10
80

MHz
MHz
kΩ

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
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Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
Over recommended ranges of supply voltage and operating free air temperature (unless otherwise noted).
All inputs tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal andexternal load capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing. LDO disabled (LDOEN = 0). fACLK = 32786 Hz, fDCO = fMCLK = fSMCLKat specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz LDO disabled(LDOEN = 0).
Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL,
SVML). High side monitor disabled (SVMH). RAM retention enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation(XTS = 0,
XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz,fSMCLK = fDCO = 0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled.) LDO disabled (LDOEN = 0).
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0,
XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0. (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz.
LDO disabled (LDOEN = 0).
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0(LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz. LDO disabled (LDOEN = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz. LDO disabled (LDOEN = 0).
Internal regulator disabled. No data retention. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5);
fDCO = fACLK = fMCLK = fSMCLK = 0 MHz.
Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Also applies to �����
RST pin when pullup/pulldown resistor is enabled.
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals
shorter than t(int).
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Selecting reduced drive strength may reduce EMI.

A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For
full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet.
Maximum frequency of operation of the entire device cannot be exceeded.

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TABLE I. Electrical performance characteristics - Continued.
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Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:(a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF(b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF(c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF(d) For XT1DRIVEx = 3, CL,eff ≥ 6 p
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it isrecommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitanceshould always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.

Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance of up to 18
pF can be supported.

To improve EMI on the XT2 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it isrecommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitanceshould always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)).
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V).
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within therange of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO
frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, rangen, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that
if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set
to report that theselected range is at its minimum or maximum tap setting.
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings andusage from manufacturer data sheet.
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings andusage from manufacturer data sheet.
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on theperformance mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with
SVSLand SVML in full performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for
SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor
chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

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TABLE I. Electrical performance characteristics - Continued.
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61/
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63/
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65/
66/

67/
68/
69/
70/
71/

72/
73/

This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on theperformance mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are innormal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML
while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the
MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) from manufacturer data sheet.
This value represents the time from the wakeup event to the reset vector execution.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses
are correctly recognized their width should exceed the maximum specification of the deglitch time.
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) andtVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing
diagrams in Figure 5 and Figure 6.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that thedata on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagramsin Figure 5 and Figure 6.
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)). For the master's parameters tSU,MI(Master)and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing
diagrams in Figure 7 and Figure 8.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in
Figure 7 and Figure 8.
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If thereference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required (see REF, External Reference and REF, Built-In Reference from manufacturer data sheet).
The internal reference supply current is not included in current consumption parameter IADC12_A.
ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0.
REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 =0, SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources,
the specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured
when using the ADC12OSC divided by 2.
The ADC12OSC is sourced directly from MODOSC inside the UCS.
13 × ADC12DIV × 1/fADC12CLK.
Approximately ten Tau (Ƭ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) x (RS + RI) × CI + 800 ns,
where n = ADC resolution = 12, RS = external source resistance.
Parameters are derived using the histogram method.
The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-, VR+ < AVCC,
VR- > AVSS. Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two
decoupling capacitors, 10 μF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the
MSP430x5xx and MSP430x6xxFamily User's Guide (SLAU208) from manufacturer data sheet.
Parameters are derived using a best fit curve.
The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ - VR-.
The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In
this mode the reference voltage used by the ADC12_A is not available on a pin.
The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current
consumption of the temperature sensor.
The temperature sensor offset can be significant. A single-point calibration is recommended to minimize the offset error of thebuilt-in temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the availablereference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature,°C) + VSENSOR, where
TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430x5xx and
MSP430x6xx Family User's Guide (SLAU208) from manufacturer data sheet.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

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TABLE I. Electrical performance characteristics - Continued.
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The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci,
is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should
follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with
reduced accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be appliedwith reduced accuracy requirements.
Two decoupling capacitors, 10 μF and 100 nF, should be connected to VREF to decouple the dynamic current required for an
external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide(SLAU208) from manufacturer data sheet.
The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internalbuffers, one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+
terminal, as well as, used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference isonly used as the reference for the conversion and utilizes the smaller buffer.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless aconversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with
REFON =1 and REFOUT = 0.
For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
A current overload is detected when the total current supplied from the LDO exceeds this value.
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine.
Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.

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Case X

A1

D/E

THERMAL PAD

SEATING
PLANE
A2

D1/E1
17

32

16

33

- - · ·- ·- ·- ·- ·- ·- ··- ·- ·-·-·- ·
I

·- -

I

I
I
I

I

1

48
64

PIN 1
INDEX AREA

Symbol
A
A1
A2
b

49

b1
64 PLSAe1

Dimensions
Millimeters
SymbolMin
Max

Millimeters
Min
Max

0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30

0.30
0.50
8.85
9.15
7.50 BSC
0.50 BSC

b1
D/E
D1/E1
e1

b
64 PLSNOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Quad Flatpack, No-leads (QFN) package configuration.
4. The package thermal pad must be soldered to the board for thermal and mechanical performance.
5. See the addition figure in the manufacturer product data sheet for details regarding the exposed thermal pad features anddimensions.
FIGURE 1. Case outline.

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Case outline X
Terminal
numberTerminal symbol

Terminal
numberTerminal symbol

1

P6.0/CB0/A0

64

2

P6.1/CB1/A1

63

3

P6.2/CB2/A2

62�����/NMI/SBWTDIO
RST4

P6.3/CB3/A3

61

5

P6.4/CB4/A460

PJ.0/TDO

6

P6.5/CB5/A5

59

TEST/SBWTCK

7

P6.6/CB6/A6

58

P5.3/XT2OUT

8

P6.7/CB7/A7

57

P5.2/XT2IN

9

P5.0/A8/VREF+/VeREF+

56

AVSS2

10

P5.1/A9/VREF−/VeREF−

55

NC

11

AVCC1

54

LDOO

12

P5.4/XIN

53

LDO

13

P5.5/XOUT

52

PU.1

14

AVSS1

51

NC

15

DVCC1

50

PU.0

16

DVSS1

49

VSSU

17

VCORE

48

P4.7/PM_NONE

18

P1.0/TA0CLK/ACLK

47

P4.6/PM_NONE

19

P1.1/TA0.0

46

P4.5/PM_UCA1RXD/PM_UCA1SOMI

20

P1.2/TA0.1

45

P4.4/PM_UCA1TXD/PM_UCA1SIMO

21

P1.3/TA0.2

44

P4.3/PM_UCB1CLK/PM_UCA1STE

22

P1.4/TA0.3

43

P4.2/PM_UCB1SOMI/PM_UCB1SCL

23

P1.5/TA0.4

42

P4.1/PM_UCB1SIMO/PM_UCB1SDA

24

P1.6/TA1CLK/CBOUT

41

P4.0/PM_UCB1STE/PM_UCA1CLK

25

P1.7/TA1.0

40

DVCC2

26

P2.0/TA1.1

39

DVSS2

27

P2.1/TA1.2

38

P3.4/UCA0RXD/UCA0SOMI

28

P2.2/TA2CLK/SMCLK

37

P3.3/UCA0TXD/UCA0SIMO

29

P2.3/TA2.0

36

P3.2/UCB0CLK/UCA0STE

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

30

P2.4/TA2.1

35

P3.1/UCB0SOMI/UCB0SCL

31

P2.5/TA2.2

34

P3.0/UCB0SIMO/UCB0SDA

32

P2.6/RTCCLK/DMAE033

P2.7/UCB0STE/UCA0CLKFIGURE 2. Terminal connections.

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XT2OUT

- fe,

-

.....

XOUT

RST/NMI

DVCC

I

I

I

'

t

t

I
t

UNIFIEDCLOCK
SYSTEMf-. SMCLK

t

DVSS

VCORE

AVCC

AVSS

I

I

I

I

' ' ' '

128KB
96KB
64KB
32KB

8KB+2KB
6KB+2KB
4KB+2KB

SYS

FLASH

WATCHDOG

PB

}

P2.x

PC

}

}

P3.x

LDOO LDOI
PU.0,
PU.1

} }

P4.x

P5.x

P6.x

I I

I

I

I/O PORTS
P1/P2
2x8 I/Os
INTERRUPT& WAKEUP

I/O PORTS
P3/P4
1x5 I/Os
1x8 I/OsI/O PORTS
P5/P6
1x6 I/Os
1x8 I/Os

PA
1x16 I/Os

PB
1x13 I/Os

PC
1x14 I/Os

I I I
PU PORT

RAM

LDO
SVM/SVSBROWNOUT

PORT MAP
CONTROL
(P4)

MAB

t

t

MDB

I

t.-

MPY32

TA0

TA1

TA2

TA0

TIMER_A
5 CC
REGISTERSTIMER_A
3 CC
REGISTERSTIMER_A
3 CC
REGISTERSTIMER_B
7 CC
REGISTERS

RTC_A

CRC16

JTAG/
SBW
INTERFACE

USC10,1

ADC12_A

USCI_Ax:UART
IrDA,SPI

12 BIT
200 KSPSUSCI_Bx
SPI,I2C

t

11

't

EEM
(L:8+2)

t t I

LDO

MCLK

CPUXV2
AND
WORKINGREGISTERS

PA

}

P1.x

POWER
MANAGEMENT

f-. ACLK

12 CHANNELS(10 EXT/
2 INT)AUTOSCANDMA
3 CHANNEL't
REF

COMP_B
8 CHANNELSFIGURE 3. Functional block diagram.

25

20
SYSTEM FREQUENCY-MHz

XT2IN

X1N

12

8

I
I
I
I
I

3

______ J I ______ J I _____ _
I
I
I

I
I
I

I

I

I
______ J I _____ _

I
I

I
I
I
I
I
I

0

0

1.8

2.0

2

2,3

1

1,2

1,2,3

0,1

0,1,2

0,1,2,3

2.2

2.4

3.6

SUPPLY VOLTAGE-V
THE NUMBERS WITHIN THE FIELDS DENOTE
THE SUPPORTED PMMCOREVx SETTINGSFIGURE 4. Maximum system frequency.

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1/f
UCxCLKCKPL=0UCLKCKPL=1
t

LO/HI

SOMI

F \ 7 \
I
\
l !i
14
t

\

ss\

I

t
SU,MI

LO/HI

t
HD,MO

rr-

~

SIMO

ss_/

t

t
HD,MI

(

)

VALID,MOX

FIGURE 5. SPI master mode, CKPH = 0.

r=

CKPL=0
UCLK

t

LO/HI

\

I

\

CKPL=1

1/f
UCxCLK

t

7

s~

1:

sJ

LO/HI

SOMI
t

SIMO

HD,MO

rr-

X

(

t

VALID,MO

t

I

SU,MI

-1

s

\

~/
t

}

'

:

HD,MI

FIGURE 6. SPI master mode, CKPH = 1.

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t
STE,LEAD

STE--{ -~t
STE,LAG

1/f
UCxCLKCKPL=0UCLKIICKPL=1
t

LO/HI

I

-I

I-

t

I

t

ICJ<

SOMI

HD,SO

14
~

t

1

I
t
SU,SI

LO/HI

SIMO
t
STE,ACC

1·

ss

t
HD,SI

t
STE,DISVALID,SOX

FIGURE 7. SPI slave mode, CKPH = 0.

t
STE,LEADt
STE,LAGSTE
1/f
UCxCLKCKPL=0UCLKCKPL=1
t
LO/HI

t
LO/HI

t
SU,SI

t
HD,SI

SIMO
t
STE,ACC

t

t

MO,SO

t

STE,DISVALID,SO

SOMI

FIGURE 8. SPI slave mode, CKPH = 1.

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tt

HD,STAt

SU,STAt

HD,STA

BUF

SDA
t
LOW

t
HIGH

t

SP

SCL
t

t

HD,DATt

SU,DAT

SU,STOFIGURE 9. I2C mode timing.

TYPICAL LOW-LEVEL OUTPUT CURRENT
VS
LOW-LEVEL OUTPUT VOLTAGE
90
V CC =3.0 V
T A =25°C

OL-TYPICAL LOW-LEVEL OUTPUT CURRENT-mA

80

I

V CC =3.0 V
T A =85°C

I

70

I

V CC =1.8 V
T A =25°C

60
50

V CC =1.8 V

40

T A =85°C

30
20
10
0

0

0.1

0.2

0.3
V

OL

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

-LOW-LEVEL OUTPUT VOLTAGE-V

FIGURE 10. Ports PU.0, PU.1 typical low level output characteristics.

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TYPICAL HIGH-LEVEL OUTPUT CURRENT
VS
HIGH-LEVEL OUTPUT VOLTAGE
0-TYPICAL HIGH-LEVEL OUTPUT CURRENT-mA

/ ~

-20
-30

-60
-70

=1.8 VCC
T =85°CA~

loo"""'----I,,"- - --.......

.......

~

~

/ /

A

-

~

/

V

=3.0 VCC
T =85°C
A

V=1.8 VCC
T =25°C
A

J

I
1.5

I/ I V=3.0 VCC
T =25°C
A

2

I

-

I

2.5

3

I

1

I

I

)

J I/J '

I V

J

-90
0.5

//
)'/
,v,

.,~V

I

-80

OH

,

V

-40 f - -50

I

I

-10

V

OH

-HIGH-LEVEL OUTPUT VOLTAGE-V

FIGURE 11. Ports PU.0, PU.1 typical high level output characteristics.
TYPICAL PU.0,PU.1 INPUT THRESHOLD
2.0

TA =25°C, 85°C

1.8
1.6

INPUT THRESHOLD-V

1.4
1.2
1.0
0.8
0.6

1....--

VIT+ ,POSITIVE-GOING INPUT THRESHOLD

---

-i--

-- ------- ----- -~

i--

~

-

~

i--

~

~

i-- ~

~

~

i--

~

~

--

VIT+ ,NEGATIVE-GOING INPUT THRESHOLD

0.4
0.2
0.0
1.8

2.2

2.6

3

LDOO SUPPLY VOLTAGE,V

LDOO

3.4
-V

FIGURE 12. Ports PU.0, PU.1 typical input threshold characteristics.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee ofpresent or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/
V62/13628-01XE

I

Devicemanufacturer
CAGE code

Vendor part number

01295

MSP430F5328RGCEP

1/ The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

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