SOI and Related Activities in AGH-UST and IFJ PAN(1) Sebastian Głąb, M.I. Ahmed, Mateusz Baszczyk, Szymon Bugiel, Piotr Dorosz,
Roma Dasgupta, Marek Idzik, Wojciech Kucewicz, Jakub Moroń, Maria Sapor(2) Piotr Kapusta, Michał Turała(1) AGH University of Science and Technology,
A. Mickiewicza 30, 30-059 Krakow, Poland(2) Institute of Nuclear Physics Polish Academy of Sciences,Radzikowskiego 152, 31-342 Krakow, Poland
Email: sglab@agh.edu.plAgenda• Presentation of AGH University of Science and Technology;••••

General description of submitted chips;
First matrix of pixels;
Second matrix of pixels;
Third and fourth matrix of pixels;• Successive Approximation Register Analog-to-Digital Converter;• Bandgap voltage reference with temperature sensor;• Synthesizable digital library.

2

AGH UST history

In 1913, Emperor Francis Joseph
approved the establishment of a higher
school of mining in Krakow.
In 1919, Józef Piłsudski, the Headof the State, inaugurated theAcademy of Mining.

In 1947, an internal resolution was
adopted to change the name to the
Academy of Mining and Metallurgy.

www.agh.edu.pl

Facts and figures• 16 faculties• 57 fields of study• more than 200 specialisations• total number of students: 32,245••••

full-time students:
26,314
part-time students:
5,931
doctoral students:
1002
postgraduate students: 2284

• over 170,000 graduates• over 2,000 researchers including
560 independent research workers
www.agh.edu.pl

Results of scientific research activity• International projects – nearly 200• Domestic projects – over 2,000• Research and innovation:• obtained patents – 93
• patent pending innovations – 112• Licences:• licence agreements – 39

Publications

5871

Books

141

Chapters in books

479

Articles in magazines

2547

Reports and papers

2425
www.agh.edu.plResearch and laboratories
The supercomputer “Zeus” classified among 100 mostpowerful computers in the world

The latest generation
analytical electron
microscope (S)TEM FEI
Titan Cubed G-2 60-300
www.agh.edu.pl

Infrastructure

Academic Centre of Materials
and Nanotechnology

Faculty of Energy and Fuels

Centre of Computer ScienceCentre of Ceramics www.agh.edu.plDescription of submitted chips

8

SOI chips submitted by AGH & IFJ

Chip no. 1 (submitted in July 2012):a) One matrix of pixels 32x32(two layouts: small and large BPW);b) two asynchronous, dynamic logic,
10 bit SAR ADCs;c) bandgap voltage reference andtemperature sensor (ver. 1 and ver. 2).

9

SOI chips submitted by AGH & IFJ, cont.
Chip no. 2 (submitted in July 2013):a) matrix of pixels 32x32(two layouts: small and noBPW);b) digital library test structures;c) bandgap voltage reference andtemperature sensor (ver. 2b and ver. 3);d) history effect test circuit;e) bare test pixels;f) bandgap diodes test structures;g) SOI2 strip.

10

SOI chips submitted by AGH & IFJ, cont.
Chip no. 3 (submitted in July 2014):a) matrix of pixels 16x32 (charge
amplifier; small and large BPW);b) matrix of pixels 16x32 (charge
amplifier, shaper, peak detector);c) Two asynchronous, static logic,
10 bit SAR ADC;d) bandgap voltage reference andtemperature sensor (ver. 4 and ver. 4b).

11

Next MPW submission plans
Chip no. 4 (?April 2015?):a) matrix of self addressing pixels;b) matrix of pixels with Time Over
Threshold;c) Improved 10 bit SAR ADC;d) 6 bit, column SAR ADC;e) bandgap voltage reference andtemperature sensor (to be decided).

12Pixel matrices

13First version of pixel

Designed by Piotr Kapusta

14

First version of pixel, cont.
SMALL

Laid by Sebastian GłąbLARGE

Laid by Piotr Kapusta

15

First version of pixel, cont.
• The measured ENC value was found to be about 115 electrons at 60 V bias and 82
μs integration time (in which 56 e came from the leakage current, 34 e from the input
transistor and the rest, i.e. 94 electrons is produced in the readout electronics(including out of chip components).
• The chip operates in the “rolling shutter” mode, the dead time equals 2.7%.
• The calculated gain is 9.3ADC units/eV, with non-linearity better than 2.6ADC units.

Total Equivalent Noise Charge vs detector bias. Integration time = 90 μs.

16First version of pixel, cont.

Am241 spectra from different sensor areas.
M. I. Ahmed, S. Głąb, M. Idzik, P. J. Kapusta, M. Turała, Prototype pixel detector in the SOI technology,
Journal of Instrumentation; ISSN 1748-0221. - 2014 vol. 9 no. 2, s. 1–8 article no. C02010.
http://iopscience.iop.org/1748-0221/9/02/C02010

17Second version of pixel matrix• Circuit schematics same as in first version;• Added SOI2 layer to all pixels;• Large pixels substituted by pixels without BPW area;• One bug fixed (BPW line shorted with bias line);• Broken output amplifier – matrix can not be read…

18

Third version of pixel

A telescopecascode with anadditional current
source for higher
output resistance.

Correlated double sampling.

Designed by Szymon Bugiel

Two different gains.

19New Column Amplifier

Designed by Szymon Bugiel

20

Third version of pixel, summary• The new pixels use newly designed frontend electronics in the charge amplifier
configuration, in order to obtain significantly lower noise level than in the first
prototype.
• Thanks to use of recycling folded cascode as the column amplifiers a significant
reduction of the power consumption should be possible.
• Two separate SOI2 areas; one below all PMOS transistors, second one under all
NMOS transistors. Possibility to study compensation of radiation damage effects.
• Two layouts of pixels: half of the pixels were drawn using standard BPW/BNW
layer and other half without it. Possibility to study effectiveness of SOI2 shielding.

Szymon Bugiel, Roma Dasgupta, Sebastian Głąb, Marek Idzik, Piotr Kapusta, Development of pixel detector in novel sub-micron
technology SOI CMOS 200 nm, MIXDES 2014; proceedings of the 21st international conference;
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6872186

21

Fourth version of pixel

Designed by Piotr Kapusta
Details are unknown…
22

3rd and 4th pixel layouts comparison

Designed by Szymon Bugiel

Designed by Piotr Kapusta

23

Successive Approximation Register Analog-to-Digital converter24

10 bit SAR ADC

Designed by Roma Dasgupta

25

10 bit SAR ADC, cont.

Schematics of designed DAC

Designed by Roma Dasgupta

26

10 bit SAR ADC, cont.

27

Designed by Roma Dasgupta

10 bit SAR ADC, cont.
• 10 bit resolution, 20 MSps at a power consumption of about 900 μW.
• Zero static power dissipation.

• The differential, segmented DAC with merge capacitor switching (MCS) scheme.
• The MCS scheme achieves 93.4% less switching energy as compared to theconventional SAR architecture.
• Layout size is about 200 μm × 300 μm.
The dynamic parameters of designed SAR ADC

Roma Dasgupta, Szymon Bugiel, Sebastian Głąb, Marek Idzik, Jakub Moroń, Piotr Kapusta, Design and simulations of the28
10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS, MIXDES 2014; proceedings of the 21st international conference;
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6872180

Bandgap Voltage Reference and Temperature Sensor

29

Positive temperature coefficient (PTC)
It was recognized in 1964 that if two bipolar transistors operate at unequal current
densities, then the difference between their base-emitter voltages is directly
proportional to the absolute temperature.

kT
VBE  Vth ln n  m ln n  m
q
Vth
mV
 0.087
TK

30

Negative temperature coefficient (NTC)
Forward voltage of p-n junction VBE has negative temperature coefficient.

VBE VBE  4  mVth  Eg / q

T
T
3
2
kT
Vth 
q

Temperature exponent of mobility: m  
Thermal voltage:
Bandgap energy of silicon:

Eg  1.12eV

With VBE = 750 mV, T = 300 K:

VBEmV 1.5
T
K

31

Schematic of the circuit

32Layout of the circuit
Version 1 and 2 based on „cold” and „hot” diodemodel respectively.
267 μm x 124 μm(submitted in July 2012)

Version 2 with improved layout and version 3.
298 μm x 185 μm(submitted in July 2013)

Version 4.
240 μm x 157 μm(submitted in January 2014)
Not yet available.

33Bandgap („hot” diode model)

The simulations were done for temperature range from -10 °C to +130 °C showing very
good temperature sensor linearity and stable (within 1 mV) bandgap voltage output inthe whole range.
34

Measurements of PTAT

All temperature
sensors were
designed so as tohave sensitivity of
about 3.5 mV/K.

Substrate
type

Smallest

Sensitivity [mV/K]
Average
Largest

RMS

CZN

2.877

3.055

3.241

0.111

FZN

2.771

2.867

3.028

0.081

FZP

2.457

2.648

2.922

0.164

Chips will bemeasured inenvironmental
chamber herein KEK.

35

Measurements of bandgap

Due to moderate
accuracy of diodemodels included indesign kit,measurements
results for version 1
and 2 are muchworse thatsimulation results.

CircuitversionSmallest

Version 1

Sensitivity [μV/K]
Average
Largest-498

RMS

Version 2

-277

-357

-516

69

Version 3

-21

-101

-258

74

36

Measurements of bandgap (version 3 only)

Substrate
type

Smallest

Sensitivity [μV/K]
Average
Largest

RMS

CZN

-21

-35

-52

13

FZN

-54

-78

-90

17

FZP

-123

-191

-258

55

Circuits fabricatedon CZN substrate
have satisfactory
behavior withtemperature.
Whereas circuits
fabricated on newly
introduced
substrates FZN and
FZP exhibit clearlyworse performance.
This phenomena
must be consulted
with substrates
foundry.
37

Bandgap voltage source and temperature sensor,
summary• A temperature sensor and bandgap voltage reference source were designed andproduced in novel submicron 200 nm SOI technology comprising electronics andsensor layers.
• A satisfactory operation of both circuits was verified in a wide temperature range.
• The temperature sensor shows sensitivity of about 3 mV/K which is consistent withsimulations.
• Subsequent versions of the bandgap voltage reference show major improvementssuggesting that modification of diode model would be desirable.
• Both circuits exhibit similar degradation of performance for substrates other than
CZN. This needs further studies because higher resistivity FZP and FZN floating zone
substrates are more desirable for production of radiation detectors.

S. Głąb, M. Baszczyk, P. Dorosz, M. Idzik, W. Kucewicz, M. Sapor, P. Kapusta, Y. Arai, T. Miyoshi, A. Takeda, Bandgap Voltage Reference andTemperature Sensor in Novel SOI Technology, ICSES 2014; proceedings of the International Conference on Signals and Electronics;
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6948708

Synthesizable Digital Library39

Motivation

Manually placed logic

Synthetized logic

40

Digital library
Digital Library contains 93 elements:• Half adders and full adders (ADD21, ADD22, ADD31, ADD32);• And-Or-Invert (AOI210, AOI211, AOI220, AOI221, AOI310, AOI311, AOI2110, AOI2111);• Basic logic gates with 2 or 3 inputs (AND20, AND21, AND22, AND30, NAND20, NAND30, NOR20,
NOR30, OR20, OR21, XNR20, XOR20);• Clock buffer, tri-state buffers, buffers with enable input (CLKBU2, BUFT2, BUFT3, BUFE2,
BUFE3, BUF2, BUF3, BUF4, BUF5, BUF7);• Bus holder (BUSHD);• D-type flip-flops with asynchronous clear, preset, chip enable (DF1, DF2, DFC1, DFC2,
DFCP1, DFCP2, DFP1, DFP2, DFE1, DFEC1, DFECP1, DFEP1);• T-type flip-flops with asynchronous clear, preset, chip enable (TFC1, TFC2, TFCP1, TFCP2,
TFP1, TFP2, TFEC1, TFECP1, TFEP1);• Glue cells (FILL1, FILL2, FILL4, FILL8);• Inverters (CLKIN0, INV0, INV1, INV2, INV4, INV5, INV6, INV7, INV8, INV9);• Constant logic level source (LOGIC0, LOGIC1);• D-type latches with asynchronous clear and preset (DL1, DL2, DLC1, DLC2, DLCP1, DLCP2,DLCPQ1, DLCPQ2, DLCQ1, DLCQ2, DLP1, DLP2, DLPQ1, DLPQ2, DLQ1, DLQ2);• Multiplexers (IMUX20, IMUX30, IMUX40, MUX20, MUX30).
41

Design assumptions

Layout of D-type flip-flop with asynchronous clear and preset• Elements are optimized in terms of area;• All internal wiring drawn on polysilicon and first metal layers;• Height of 7.68 µm was chosen for all layout cells.

42

Design assumptions cont’d• Minimal transistor’s channel length of
0.2 µm was used in all transistors;• NMOS channel width is set to 0.5 μm(minimum size in this technology);• PMOS channel width is set to 1.2 μm;• This channel width ratio (i.e. 1:2.4)
ensures the equality of rise and falltimes at the signal output;• In output stages transistors withchannel width of 1 μm (NMOS) and2.4 μm (PMOS) were used.

43

Simulation results

Logic component

Lapis Semiconductor SOI 0.2 µm
Rise time
Fall time
Delay
Area
[ps]
[ps]
[ps]
[µm2]

Rise time[ps]

AMS 0.35 µm
Fall time
Delay
[ps]
[ps]

Area
[µm2]

Inverter

124

104

50

14.75

195

77

73

39.76

Not AND

257

194

114

22.12

282

120

106

55.86

Not OR

264

199

119

22.12

339

201

166

55.86

Exclusive OR

255

220

219

51.61

400

178

411

204.82

Exclusive NOR

293

246

150

51.61

506

229

252

111.72D-type flip flop

138

140

386

125.34

235

140

829

279.30− Results presented in table are based on simulations of schematics.
− Cells with similar output current were selected from both libraries.
− Designed elements have steeper output signal slope in most cases.
− Five elements of the new library from among six that have been investigated havesmaller delay time when compared to the elements of the AMS library.
− Designed digital library achieved comparable speed with just 37% - 46% of areaof similar item from the AMS library.
44

Ring oscillators test structures
Each ring oscillator contains large number of gates arranged in series to accurately
estimate the delay introduced by a single component based on oscillation’s period.
Fourteen ring oscillators were designed:• Ring_Inv0, Ring_Inv0_load1, Ring_Inv0_load2;• Ring_Inv8, Ring_Inv8_load1, Ring_Inv8_load2;• Ring_Inv0x150;• Ring_Inv4;• Ring_Nand20 and Ring_Nand20u;• Ring_Nor20 and Ring_Nor20u;• Ring_Xor20 and Ring_Xor20u.
Using the same masks set, the test structures were fabricated on
Czochralski n-type (CZN), Floating Zone n-type (FZN) and Floating Zone
p-type (FZP) substrates.
Additionally, for FZN substrate results from two batches will be presented.
45

Measurements and results
Averaged delay introduced by component calculated from all 12 chips disregarding
wafer type.
Measured delay

Simulated
delay [ps]Average [ps]RMS

Av. / Sim [%]Ring_NAND20

132,47297,12

14,08

224

Ring_NAND20u

151,11

302,5814,88

200

Ring_NOR20u

187,04

315,81

15,98

169

Ring_NOR20

254,94369,1918,54145

Ring_XOR20u323,58565,51

26,81

175

Ring_XOR20

363,21

654,32

28,17

180

Ring_Inv4

104,26146,63

6,44

141

Ring_Inv8

106,93

155,506,63145

Ring_Inv8_load1

111,49166,22

7,06

149

Ring_Inv8_load2

116,44

175,807,47151

Ring_Inv0x150

108,48226,32

11,43

209

Ring_Inv0

109,01

229,5912,29

211

Ring_Inv0_load1

184,95377,17

20,52

204

Ring_Inv0_load2

262,08521,3526,39

199

Circuit name46

Measurements and results
Averaged delay introduced by component but taking into account the difference in awafer type (average delay measured in three chips of the same batch).

Circuit name

Simulated
delay [ps]Ring_NAND20
Ring_NAND20u
Ring_NOR20u
Ring_NOR20
Ring_XOR20u
Ring_XOR20
Ring_Inv4
Ring_Inv8
Ring_Inv8_load1
Ring_Inv8_load2
Ring_Inv0x150
Ring_Inv0
Ring_Inv0_load1
Ring_Inv0_load2

132,47
151,11
187,04
254,94
323,58363,21
104,26
106,93
111,49116,44
108,48109,01
184,95
262,08

1J-HR1 (CZN)
AverageRMS[ps]304,73
5,726
309,885,183
323,54
5,432
379,55
6,235
578,72
10,136
669,01
9,068
149,97
1,539
158,58
1,774
169,502,040
179,34
2,188
233,58
3,679
236,73
4,484
389,83
8,173
537,369,875

E2J-FZN
AverageRMS[ps]315,640,455
322,800,857
337,41
1,239
393,501,177
602,02
0,994
692,43
0,809
155,41
0,585
164,750,291
176,070,260
186,170,247
240,51
1,186
245,080,526
402,440,568
553,962,435

2JB-FZN
AverageRMS[ps]286,01
2,420
290,082,241
303,502,752
354,36
1,905
541,983,925
629,303,091
140,500,741
149,800,485
160,13
0,327
169,21
0,566
217,902,880
221,22
2,829
363,104,110
504,195,701

3JB-FZP
AverageRMS[ps]282,102,008
287,57
3,091
298,81
4,012
349,34
4,433
539,34
3,278
626,54
3,967
140,630,729
148,84
0,688
159,17
0,768
168,480,849
213,31
2,344
215,31
3,308
353,305,785
489,906,75147

Digital library, summary• A digital library dedicated to currently developed FD-SOI 0.2 µm technology provided
by Lapis Semiconductor was designed.
• During the layout process a large emphasis on obtaining the lowest possible size oflayout cells was placed.
• Designed digital library allows automatic implementation of complicated digital blockusing its descriptions in HDL.
• It was possible to achieve satisfactory timing with more than twofold decrease inoccupied area when compared to library created in AMS 0.35 µm technology.
• Test structures of some of the library components were fabricated and measured.
• Obtained results show typical discrepancy between simulations of schematic andfabricated circuit performance.
• Test structures were produced on different substrates and no clear dependence wasobserved.

S. Głąb, M. Baszczyk, P. Dorosz, M. Idzik, W. Kucewicz, M. Sapor, P. Kapusta, Y. Arai, T. Miyoshi, A. Takeda, Synthetizable Digital Library
Created to Facilitate Design of SOI Detectors in 200 nm SOI Technology, ICSES 2014; proceedings of the International Conference on Signals
and Electronics;
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6948729

Thank you for your attention

49