BD0       ADS1000
SBAS357 – SEPTEMBER 2006

LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER
with I2C™ INTERFACEFEATURESDESCRIPTION•

The ADS1000 is an I2C-compatible serial interface
Analog-to-Digital (A/D) converter with differential
inputs and 12 bits of resolution in a tiny SOT23-6
package. Conversions are performed ratiometrically,using the power supply as the reference voltage. The
ADS1000 operates from a single power supply
ranging from 2.7V to 5.5V.

•
•
•
•
•
•
•
•

Complete 12-Bit Data Acquisition System ina Tiny SOT-23 Package
Low Current Consumption: Only 90µA
Integral Nonlinearity: 1LSB Max
Single-Cycle Conversion
Programmable Gain Amplifier
Gain = 1, 2, 4 or 8
128SPS Data Rate
I2C Interface with Two Available Addresses
Power Supply: 2.7V to 5.5V
Pin- and Software-Compatible with 16-Bit
ADS1100

The ADS1000 performs conversions at a rate of 128
samples per second (SPS). The onboard
programmable gain amplifier (PGA), which offers
gains of up to 8, allows smaller signals to bemeasured with high resolution. In single-conversion
mode, the ADS1000 automatically powers down after
a conversion, greatly reducing current consumption
during idle periods.

APPLICATIONS
•
•
•
•
•

The ADS1000 is designed for applications where
space and power consumption are major
considerations. Typical applications include portable
instrumentation, consumer goods, and voltage
monitoring.

Voltage Monitors
Battery Management
Industrial Process Control
Consumer Goods
Temperature Measurement
VDD
A = 1, 2, 4, or 8
VIN+
PGA
VIN-

A/D
Converter2

IC
Interface

SCL
SDA

Clock
Oscillator
ADS1000
GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Royal Philips Electronics B.V., The Netherlands.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does notnecessarily include testing of all parameters.

Copyright © 2006, Texas Instruments Incorporated

ADS1000
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SBAS357 – SEPTEMBER 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the endof this datasheet or see the TI website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)over operating free-air temperature range (unless otherwise noted)
ADS1000
VDD to GND

UNIT–0.3 to +6

V

Input Current (Momentary)

100

mA

Input Current (Continuous)

10

mA

Voltage to GND, VIN+, VIN–

–0.3 to VDD to +0.3

V

Voltage to GND, SDA, SCL–0.5 to +6

V

+150

°C

Operating Temperature–40 to +125

°C

Storage Temperature–60 to +150

°C

+300

°C

Maximum Junction Temperature, TJ

Lead Temperature (soldering, 10s)
(1)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.

PIN CONFIGURATION
VIN- VDD SDA
6

5

VIN- VDD SDA

4

6

BD0
1

2

5

4

BD1

3

1

2

3

VIN+ GND SCL

VIN+ GND SCL

I C address: 1001000

I C address: 1001001

2

2

2

NOTE: Marking text direction indicates pin 1. Marking text depends on I C address; see Package Option Addendum.

2

ADS1000
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SBAS357 – SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS
All specifications at –40°C to +85°C, VDD = 5V, GND = 0V, and all PGAs, unless otherwise noted.
ADS1000
PARAMETERCONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT
Full-Scale Input Voltage(VIN+) – (VIN–)

Analog Input Voltage

VIN+, VIN– to GND±VDD/PGA (1)GND – 0.2

Differential Input ImpedanceCommon-Mode Input Impedance

V
VDD + 0.2V

2.4/PGAMΩ8

MΩ

SYSTEM PERFORMANCE
Resolution

No Missing Codes

12

Data Rate

104

Bits
128

184

SPS

Integral Nonlinearity (INL)

±0.1

1

LSB

Offset Error

1

±2

LSB

Gain Error

0.01

0.1

%

0.7 GND

6V

GND – 0.5

0.3 VDD

V

GND

0.4

V

10

µA

DIGITAL INPUT/OUTPUT
Logic Level
VIH
VIL
VOL

IOL = 3mA

Input Leakage
IIH

VIH = 5.5V

IIL

VIL = GND

– 10

VDD

2.7

µA

POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Supply Current

5.5

VPower-Down

0.05

2

µA

Active

90

150

µA
µA

Power Dissipation(1)

VDD = 5.0V

450

VDD = 3.0V

210

750

µW
µW

Each input, VIN+ and VIN–, must meet the absolute input voltage specifications.

3

ADS1000
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SBAS357 – SEPTEMBER 2006

TYPICAL CHARACTERISTICS
At TA = 25°C and VDD = 5V, unless otherwise indicated.
SUPPLY CURRENT vs I2C BUS FREQUENCYSUPPLY CURRENT vs TEMPERATURE
250

120

225
VDD = 5V

200
IVDD (µA)

I VDD (µA)

100

80

25_C

175
125_C

150
125
100

60
VDD = 2.7V

−40_C

75

40

50
−60 −40 −20

0Temperature (_C)

100
1k
I2C Bus Frequency (kHz)

Figure 1.

Figure 2.

20

40

60

80

100 12010140

OFFSET ERROR vs TEMPERATURE

10k

GAIN ERROR vs TEMPERATURE

2.0

0.04
0.03
PGA = 4

PGA = 80.02
PGA = 8

PGA = 4

PGA = 2

PGA = 1Gain Error (%)

Offset Error (mV)

1.0

0.0

-1.0

PGA = 1

0.01
0.00
-0.01
-0.02
PGA = 2
-0.03

-2.0
-60

-40

-20

0

20

40

60

80

-0.04
-60 -40

100 120 140

-20

0

40

60

Temperature (°C)

Figure 3.

Figure 4.
DATA RATE vs TEMPERATURE

160
VDD = 2.7V
Data Rate (SPS)

144

128
VDD = 5V
112

96
−60 −40 −20

0

20

40

60

Temperature (_C)

Figure 5.

420

Temperature (°C)

80

100 120140

80

100 120 140

ADS1000
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SBAS357 – SEPTEMBER 2006

THEORY OF OPERATIONThe ADS1000 is a fully differential, 12-bit A/Dconverter. The ADS1000 allows users to obtain
precise measurements with a minimum of effort, andthe device is extremely easy to design with andconfigure.
The ADS1000 consists of an A/D converter core withadjustable gain, a clock generator, and an I2C
interface. Each of these blocks are described indetail in the sections that follow.

ANALOG-TO-DIGITAL CONVERTER
The ADS1000 uses a switched-capacitor input stage.
To external circuitry, it looks roughly like a
resistance. The resistance value depends on thecapacitor values and the rate at which they areswitched. The switching clock is generated by the
onboard clock generator, so its frequency, nominally275kHz, is dependent on supply voltage andtemperature. The capacitor values depend on the
PGA setting.
The common-mode and differential input impedances
are different. For a gain setting of PGA, thedifferential input impedance is typically 2.4MΩ/PGA.
The common-mode impedance is typically 8MΩ.

OUTPUT CODE CALCULATIONThe ADS1000 outputs codes in binary two’s
complement format. The output code is confined to
the range of numbers: –2048 to 2047, and is given
by:Output Code + 2048(PGA)ǒV V*V Ǔ
IN−

IN)

DD

CLOCK GENERATOR
The ADS1000 features an onboard clock generator.
The Typical Characteristics show variations in data
rate over supply voltage and temperature. It is notpossible to operate the ADS1000 with an external
clock.

USING THE ADS1000
OPERATING MODESThe ADS1000 operates in one of two modes:
continuous conversion and single conversion.

places the result in the output register, andimmediately begins another conversion. When the
ADS1000 is in continuous conversion mode, theST/BSY bit in the configuration register always reads'1'.
In single conversion mode, the ADS1000 waits until
the ST/BSY bit in the conversion register is set to '1'.
When this happens, the ADS1000 powers up andperforms a single conversion. After the conversion
completes, the ADS1000 places the result in the
output register, resets the ST/BSY bit to '0' andpowers down. Writing a '1' to ST/BSY while aconversion is in progress has no effect.
When switching from continuous conversion mode to
single conversion mode, the ADS1000 will complete
the current conversion, reset the ST/BSY bit to '0'
and power-down the device.
RESET AND POWER-UP
When the ADS1000 powers up, it automatically
performs a reset. As part of the reset, the ADS1000
sets all of the bits in the configuration register to theirrespective default settings.
The ADS1000 responds to the I2C General Call
Reset command. When the ADS1000 receives aGeneral Call Reset, it performs an internal reset,
exactly as though it had just been powered on.
I2C INTERFACEThe ADS1000 communicates through an I2C(Inter-Integrated Circuit) interface. The I2C interface
is a two-wire, open-drain interface supporting
multiple devices and masters on a single bus.
Devices on the I2C bus only drive the bus lines low,by connecting them to ground; they never drive thebus lines high. Instead, the bus wires are pulled highby pull-up resistors, so the bus wires are high whenno device is driving them low. This way, two devices
cannot conflict; if two devices drive the bus
simultaneously, there is no driver contention.
Communication on the I2C bus always takes place
between two devices, one acting as the master andthe other acting as the slave. Both masters andslaves can read and write, but slaves can only do sounder the direction of the master. Some I2C devices
can act as masters or slaves, but the ADS1000 can
only act as a slave device.

In continuous conversion mode, the ADS1000
continuously performs conversions. Once a
conversion has been completed, the ADS1000

5

ADS1000
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SBAS357 – SEPTEMBER 2006

An I2C bus consists of two lines, SDA and SCL. SDA
carries data; SCL provides the clock. All data istransmitted across the I2C bus in groups of eight bits.
To send a bit on the I2C bus, the SDA line is driven
to the bit level while SCL is low (a Low on SDA
indicates the bit is '0'; a High indicates the bit is '1').
Once the SDA line has settled, the SCL line isbrought high, then low. This pulse on SCL clocks the
SDA bit into the receiver shift register.
The I2C bus is bidirectional: the SDA line is usedboth for transmitting and receiving data. When amaster reads from a slave, the slave drives the dataline; when a master sends to a slave, the master
drives the data line. The master always drives theclock line. The ADS1000 never drives SCL, because
it cannot act as a master. On the ADS1000, SCL isan input only.
Most of the time the bus is idle, no communication
takes place, and both lines are high. Whencommunication takes place, the bus is active. Only
master devices can start a communication. They dothis by causing a start condition on the bus.
Normally, the data line is only allowed to change
state while the clock line is low. If the data line
changes state while the clock line is high, it is eithera start condition or its counterpart, a stop condition.
A start condition is when the clock line is high andthe data line goes from high to low. A stop condition
is when the clock line is high and the data line goesfrom low to high.
After the master issues a start condition, it sends abyte that indicates with which slave device it wants tocommunicate. This byte is called the address byte.
Each device on an I2C bus has a unique 7-bit
address to which it responds. (Slaves can also have6

10-bit addresses; see the I2C specification for
details.) The master sends an address in theaddress byte, together with a bit that indicates
whether it wishes to read from or write to the slave
device.
Every byte transmitted on the I2C bus, whether it beaddress or data, is acknowledged with an
acknowledge bit. When a master has finishedsending a byte, eight data bits, to a slave, it stops
driving SDA and waits for the slave to acknowledge
the byte. The slave acknowledges the byte by pulling
SDA low. The master then sends a clock pulse toclock the acknowledge bit. Similarly, when a masterhas finished reading a byte, it pulls SDA low to
acknowledge to the slave that it has finished reading
the byte. It then sends a clock pulse to clock the bit.
(Remember that the master always drives the clockline.)A not-acknowledge is performed by simply leaving
SDA high during an acknowledge cycle. If a device is
not present on the bus, and the master attempts toaddress it, it will receive a not-acknowledge because
no device is present at that address to pull the line
low.
When a master has finished communicating with aslave, it may issue a stop condition. When a stop
condition is issued, the bus becomes idle again. A
master may also issue another start condition. Whena start condition is issued while the bus is active, it iscalled a repeated start condition.
A timing diagram for an ADS1000 I2C transaction isshown in Figure 6. Table 1 gives the parameters forthis diagram.

ADS1000
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SBAS357 – SEPTEMBER 2006
t(LOW)tRt(HDSTA)tF

SCLt(HDSTA)t(HIGH)t(HDDAT)t(SUSTO)t(SUSTA)t(SUDAT)SDAt(BUF)PSS

P

Figure 6. I2C Timing Diagram
Table 1. Timing Diagram Definitions
FAST MODE
PARAMETERMIN

HIGH-SPEED MODE
MAX

MIN

0.4

MAX

UNITS

3.4

MHz

SCLK Operating Frequencyf(SCLK)Bus Free Time Between STOP and START
Conditiont(BUF)

600

160

ns

Hold Time After Repeated START Condition.
After this period, the first clock is generated.

t(HDSTA)

600

160

ns

Repeated START Condition Setup Timet(SUSTA)

600

160

ns

STOP Condition Setup Timet(SUSTO)

600

160

ns

Data Hold Timet(HDDAT)00ns

Data Setup Timet(SUDAT)

100

10

ns

SCLK Clock Low Periodt(LOW)

1300

160

ns

SCLK Clock High Periodt(HIGH)

600

60

ns

Clock/Data Fall Time

tF

300

160

ns

Clock/Data Rise Time

tR

300

160

ns

7

ADS1000
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SBAS357 – SEPTEMBER 2006

ADS1000 in Standard or Fast modes, but
High-speed mode must be activated. To activate
High-speed mode, send a special address byte of00001XXX following the start condition, where the
XXX bits are unique to the Hs-capable master. This
byte is called the Hs master code. (Note that this isdifferent from normal address bytes; the low bit does
not indicate read/write status.) The ADS1000 will not
acknowledge this byte; the I2C specification prohibits
acknowledgment of the Hs master code. On
receiving a master code, the ADS1000 will switch on
its High-speed mode filters, and will communicate at
up to 3.4MHz. The ADS1000 switches out of Hs
mode with the next stop condition.

ADS1000 I2C ADDRESSESThe ADS1000 I2C address is either 1001000 or
1001001, set at the factory. The address is identified
with an A0 or an A1 within the orderable name.
The two different I2C variants are also marked
differently. Devices with an I2C address of 1001000
have packages marked BD0, while devices with an
I2C address of 1001001 are marked with BD1. See
the Package/Ordering Information Table for acomplete listing of the ADS1000 I2C addresses andtape and reel size.
I2C GENERAL CALL

For more information on High-speed mode, consult
the I2C specification.

The ADS1000 responds to General Call Reset,
which is an address byte of 00h followed by a databyte of 06h. The ADS1000 acknowledges both bytes.

REGISTERSThe ADS1000 has two registers that are accessible
via its I2C port. The output register contains theresult of the last conversion; the configuration
register allows users to change the ADS1000
operating mode and query the status of the device.

On receiving a General Call Reset, the ADS1000
performs a full internal reset, just as though it had
been powered off and then on. If a conversion is inprocess, it is interrupted; the output register is set tozero, and the configuration register returns to its
default setting.

OUTPUT REGISTER

The ADS1000 always acknowledges the General
Call address byte of 00h, but it does not
acknowledge any General Call data bytes other than
04h or 06h.

The 16-bit output register contains the result of thelast conversion in binary two’s complement format.
Since the port yields 12 bits of data, the ADS1000
outputs right-justified and sign-extended codes. This
output format makes it possible to perform averaging
using a 16-bit accumulator.

I2C DATA RATESThe I2C bus operates in one of three speed modes:
Standard, which allows a clock frequency of up to
100kHz; Fast, which allows a clock frequency of up
to 400kHz; and High-speed mode (also called Hsmode), which allows a clock frequency of up to
3.4MHz. The ADS1000 is fully compatible with all
three modes.

Following reset or power-up, the output register iscleared to '0'; it remains zero until the first conversion
is completed. Therefore, if a user reads the
ADS1000 just after reset or power-up, the output
register will read '0'.
The output register format is shown in Table 2.

No special action needs to be taken to use theTable 2. OUTPUT REGISTER
BIT

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

NAME

D15 (1)

D14 (1)

D13 (1)

D12 (1)

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

(1)

8

D15–D12 are sign extensions of 12-bit data.

ADS1000
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SBAS357 – SEPTEMBER 2006

CONFIGURATION REGISTER

Bits 1 - 0: PGA

A user controls the ADS1000 operating mode and
PGA settings via the 8-bit configuration register. The
configuration register format is shown in Table 3.
The default setting is 80H.

Bits 1 and 0 control the ADS1000 gain setting; see
Table 4.

Table 3. CONFIGURATION REGISTER
7

6

5

4

3

2

ST/BSY

0

0

SC

0

0

1

0

PGA1 PGA0

Bit 7: ST/BSY
The meaning of the ST/BSY bit depends on whether
it is being written to or read from.
In single conversion mode, writing a '1' to the
ST/BSY bit causes a conversion to start, and writing
a '0' has no effect. In continuous conversion mode,
the ADS1000 ignores the value written to ST/BSY.
When read in single conversion mode, ST/BSY
indicates whether the A/D converter is busy taking a
conversion. If ST/BSY is read as '1', the A/D
converter is busy, and a conversion is taking place; if'0', no conversion is taking place, and the result of
the last conversion is available in the output register.
In continuous mode, ST/BSY is always read as '1'.
Bits 6 - 5: Reserved
Bits 6 and 5 must be set to zero.
Bit 4: SC
SC controls whether the ADS1000 is in continuous
conversion or single conversion mode. When SC is'1', the ADS1000 is in single conversion mode; when
SC is '0', the ADS1000 is in continuous conversion
mode. The default setting is '0'.
Bits 3 - 2: Reserved
Bits 3 and 2 must be set to zero.

Table 4. PGA Bits
PGA1

PGA0

GAIN

0(1)

0(1)

1(1)

0

1

2

1

0

4

1

1

8

(1) Default setting.

READING FROM THE ADS1000
A user can read the output register and the contentsof the configuration register from the ADS1000. To
do this, address the ADS1000 for reading, and readthree bytes from the device. The first two bytes are
the output register contents; the third byte is theconfiguration register contents.
A user does not always have to read three bytes
from the ADS1000. If only the contents of the output
register are needed, read only two bytes.
Reading more than three bytes from the ADS1000
has no effect. All of the bytes beginning with thefourth byte will be FFh. See Figure 7 for a timing
diagram of an ADS1000 read operation.
WRITING TO THE ADS1000
A user can write new contents into the configuration
register (the contents of the output register cannotchange). To do this, address the ADS1000 for
writing, and write one byte to it. This byte is written
into the configuration register.
Writing more than one byte to the ADS1000 has noeffect. The ADS1000 ignores any bytes sent to it
after the first one, and will only acknowledge the first
byte. See Figure 8 for a timing diagram of an
ADS1000 write operation.

9

ADS1000
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SBAS357 – SEPTEMBER 2006
9

1

9

1

···

SCL

SDA

1

0

0

1

A2

A1

R/W

A0

Start By
Master

D15

D14

ACK ByADS1000
2

SDA(Continued)

···

9

D7

D6

D5

D4

D3

D2

D11 D10

D9

···

D8

ACK ByMasterFrame 2: Output Register Upper Byte

1

···

D12

From
ADS1000

Frame 1: I C Slave Address Byte

SCL(Continued)

D13

D1

1

ST/
BSY

D0

From
ADS1000

9

0

0

SC

ACK ByMaster

0

0

PGA1 PGA0ACK ByMasterFrom
ADS1000

Frame 3: Output Register Lower Byte

Stop By
MasterFrame 4: Configuration Register(Optional)

Figure 7. Timing Diagram for Reading from the ADS1000
1

9

1

9

SCL

1

SDA

0

0

1

A2

A1

A0

Start By
Master

R/W

ST/
BSY

0

0

SC

0

0

ACK ByADS1000
2

Frame 1: I C Slave Address Byte

ACK ByADS1000
Frame 2: Configuration Register

Figure 8. Timing Diagram for Writing to the ADS1000

10PGA1 PGA0

Stop By
MasterADS1000
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SBAS357 – SEPTEMBER 2006

APPLICATION INFORMATIONThe ADS1000 interfaces directly to standard mode,
fast mode, and high-speed mode I2C controllers. Any
microcontroller I2C peripheral, including master-only
and non-multiple-master I2C peripherals, will workwith the ADS1000. The ADS1000 does not perform
clock-stretching (that is, it never pulls the clock linelow), so it is not necessary to provide for this unlessother devices are on the same I2C bus.

BASIC CONNECTIONS
For many applications, connecting the ADS1000 is
extremely simple. A basic connection diagram for the
ADS1000 is shown in Figure 9.
The fully differential voltage input of the ADS1000 is
ideal for connection to differential sources withmoderately low source impedance, such as bridge
sensors and thermistors. Although the ADS1000 canread bipolar differential signals, it cannot accept
negative voltages on either input. It may be helpful tothink of the ADS1000 positive voltage input asnoninverting, and of the negative input as inverting.

Pull-up resistors are necessary on both the SDA and
SCL lines because I2C bus drivers are open-drain.
The size of these resistors depends on the bus
operating speed and capacitance of the bus lines.
Higher-value resistors consume less power, but
increase the transition times on the bus, limiting thebus speed. Lower-value resistors allow higher speed
at the expense of higher power consumption. Longbus lines have higher capacitance and require
smaller pullup resistors to compensate. The resistors
should not be too small; if they are, the bus drivers
may not be able to pull the bus lines low.

When the ADS1000 is converting, it draws current inshort spikes. The 0.1µF bypass capacitor supplies
the momentary bursts of extra current needed fromthe supply.

Positive Input(0V to 5V)

Negative Input(0V to 5V)

2

I C Pull-Up Resistors
1kW to 10kW (typ.)

VDD
ADS1000

Microcontroller orMicroprocessor

VDD

1

VIN+

VIN-

6

with I C Port

2

GND

VDD

5

SCL

3

SCL

SDA

4

2

4.7mF (typ.)

SDA

Figure 9. Typical Connections of the ADS1000

11

ADS1000
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CONNECTING MULTIPLE DEVICES

VDD

ADS1000

Connecting two ADS1000s to a single bus is almost
trivial. An example showing two ADS1000s and one
ADS1100 connected on a single bus is shown in
Figure 10. Multiple devices can be connected to asingle bus (provided that their addresses aredifferent).
Note that only one set of pull-up resistors is needed
per bus. A user might find that he or she needs tolower the pull-up resistor values slightly tocompensate for the additional bus capacitancepresented by multiple devices and increased line
length.
VDD
ADS1000A0
Microcontroller orMicroprocessor

1

VIN+

VIN-

6

with I C Port

2

GND

VDD

5

SCL

3

SCL

SDA

4

1

VIN+

VIN-

6

2

GND

VDD

5

3

SCL

SDA

4

2

1

VIN+

VIN-

6

with I C Port

2

GND

VDD

5

SCL

3

SCL

SDA

4

2

SDA
NOTE: ADS1000 power
and input connections
omitted for clarity.

Figure 11. Using GPIO with a Single ADS1000

2

I C Pull-Up Resistors
1kW to 10kW (typ.)Microcontroller orMicroprocessor

SDA

Bit-banging I2C with GPIO pins can be done bysetting the GPIO line to zero and toggling it between
input and output modes to apply the proper bus
states. To drive the line low, the pin is set to output a'0'; to let the line go high, the pin is set to input.
When the pin is set to input, the state of the pin canbe read; if another device is pulling the line low, thisdevice will read as a '0' in the port input register.

ADS1000A1

NOTE: ADS1000 power
and input connections
omitted for clarity.

ADS1100A2
1

VIN+

VIN-

6

2

GND

VDD

5

3

SCL

SDA

4

Figure 10. Connecting Multiple ADS1000s

USING GPIO PORTS FOR I2C
Most
microcontrollers
have
programmable
input/output pins that can be set in software to act as
inputs or outputs. If an I2C controller is not available,
the ADS1000 can be connected to GPIO pins, andthe I2C bus protocol simulated, or bit-banged, insoftware. An example of this for a single ADS1000 isshown in Figure 11.

Note that no pull-up resistor is shown on the SCL
line. In this simple case, the resistor is not needed;
the microcontroller can simply leave the line on
output, and set it to '1' or '0' as appropriate. It can dothis because the ADS1000 never drives its clock line
low. This technique can also be used with multiple
devices, and has the advantage of lower current
consumption resulting from the absence of a
resistive pull-up.
If there are any devices on the bus that may drive
their clock lines low, the above method should not be
used; the SCL line should be high-Z or zero and apull-up resistor provided as usual. Note also that thiscannot be done on the SDA line in any case,because the ADS1000 does drive the SDA line low
from time to time, as all I2C devices do.
Some microcontrollers have selectable strong pull-up
circuits built into the GPIO ports. In some cases,
these can be switched on and used in place of an
external pull-up resistor. Weak pull-ups are also
provided on some microcontrollers, but usually these
are too weak for I2C communication. If there is any
doubt about the matter, test the circuit before
committing it to production.

SINGLE-ENDED INPUTS
Although the ADS1000 has a fully differential input, it
can easily measure single-ended signals. A simple
single-ended connection scheme is shown in
Figure 12. The ADS1000 is configured forsingle-ended measurement by grounding either of its
12

ADS1000
www.ti.com
SBAS357 – SEPTEMBER 2006

input pins, usually VIN–, and applying the input signal
to VIN+. The single-ended signal can range from
–0.2V to VDD + 0.3V. The ADS1000 loses no linearity
anywhere in its input range. Negative voltages
cannot be applied to this circuit because the
ADS1000 inputs can only accept positive voltages.
VDD

Figure 13 shows a circuit for a low-side shunt-typecurrent monitor. The circuit reads the voltage acrossa shunt resistor, which is sized as small as possible
while still giving a readable output voltage. This
voltage is amplified by an OPA335 low-drift op-amp,
and the result is read by the ADS1000.
11.5kW

0V - VDD
Single-Ended

Filter Capacitor
33pF to 100pF(typ.)

LOW-SIDE CURRENT MONITOR

ADS1000
1

VIN+

VIN-

6

2

GND

VDD

5

5V

V

FS = 0.63V
Load

3

SCL

SDA

4

5V

OutputCodes
0 - 2048

OPA335
(1)

(2)
RS

R3
49.9kW1kW
G = 12.5-5V

ADS1000

2

IC(PGA Gain = 8)
5V FS

Figure 12. Measuring Single-Ended Inputs
The ADS1000 input range is bipolar differential withrespect to the reference, that is, ±VDD. The
single-ended circuit shown in Figure 12 covers only
half the ADS1000 input scale because it does notproduce differentially negative inputs; therefore, one
bit of resolution is lost. The DRV134 balanced line
driver can be employed to regain this bit for
single-ended signals.
Negative input voltages must be level-shifted. A goodcandidate for this function is the THS4130 differential
amplifier, which can output fully differential signals.
This device can also help recover the lost bit noted
previously for single-ended positive signals.
Level-shifting can also be performed using the
DRV134.

NOTES: (1) Pull-down resistor to allow accurate swing to 0V.
(2) RS is sized for a 50mV drop at full-scale current.

Figure 13. Low-Side Current Measurement
It is recommended that the ADS1000 be operated ata gain of 8. The gain of the OPA335 can then be set
lower. For a gain of 8, the op amp should be
configured to give a maximum output voltage of no
greater than 0.75V. If the shunt resistor is sized toprovide a maximum voltage drop of 50mV at
full-scale current, the full-scale input to the ADS1000
is 0.63V.

13

ADS1000
www.ti.com
SBAS357 – SEPTEMBER 2006

ADDITIONAL RECOMMENDATIONSThe ADS1000 is fabricated in a small-geometry
low-voltage process. The analog inputs feature
protection diodes to the supply rails. However, thecurrent-handling ability of these diodes is limited, and
the ADS1000 can be permanently damaged byanalog input voltages that remain more thanapproximately 300mV beyond the rails for extended
periods. One way to protect against overvoltage is toplace current-limiting resistors on the input lines. The
ADS1000 analog inputs can withstand momentary
currents of as large as 10mA.
The previous paragraph does not apply to the I2C
ports, which can both be driven to 6V regardless ofthe supply.
If the ADS1000 is driven by an op amp with highvoltage supplies, such as ±12V, protection should be
provided, even if the op amp is configured so that it
will not output out-of-range voltages. Many op amps
seek to one of the supply rails immediately whenpower is applied, usually before the input has

14stabilized; this momentary spike can damage the
ADS1000. Sometimes this damage is incremental
and results in slow, long-term failure—which can be
distastrousforpermanently
installed,
lowmaintenance systems.
If using an op amp or other front-end circuitry with
the ADS1000, be sure to take the performance
characteristics of this circuitry into account; a chain is
only as strong as its weakest link.
Any data converter is only as good as its reference.
For the ADS1000, the reference is the power supply,
and the power supply must be clean enough toachieve the desired performance. If a power-supply
filter capacitor is used, it should be placed close to
the VDD pin, with no vias placed between thecapacitor and the pin. The trace leading to the pinshould be as wide as possible, even if it must be
necked down at the device.

PACKAGE OPTION ADDENDUM
www.ti.com

6-Dec-2006

PACKAGING INFORMATION
Orderable Device

Status (1)Package
Type

Package
Drawing

Pins Package Eco Plan (2)Qty

Lead/Ball Finish

MSL Peak Temp (3)ADS1000A0IDBVR

ACTIVE

SOT-23DBV

63000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMADS1000A0IDBVRG4ACTIVE

SOT-23DBV

63000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMADS1000A0IDBVTACTIVE

SOT-23

DBV

6

250

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMADS1000A0IDBVTG4ACTIVE

SOT-23

DBV

6

250

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMADS1000A1IDBVR

ACTIVE

SOT-23DBV

63000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMADS1000A1IDBVRG4ACTIVE

SOT-23DBV

63000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMADS1000A1IDBVTACTIVE

SOT-23

DBV

6

250

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIMADS1000A1IDBVTG4ACTIVE

SOT-23

DBV

6

250

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

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