AN11689
Recommendations for PCB assembly of DSN1006
Rev. 1 — 29 July 2015

Application note

Document information
Info

Content

Keywords

DSN1006, DSN1006-2, DSN1006U-2, SOD993, SOD995, 0402 package
size, reflow soldering, surface mount, solder paste, stencil aperture,
Printed-Circuit Board (PCB), Solder Mask Defined (SMD), footprint,
landing pattern, pick and place, Chip-Scale Package (CSP)

Abstract

This application note provides guidelines for board assembly of theultra-small DSN1006 (1.0  0.6 mm2) chip-scale package. The main focus
is on recommendations for reflow soldering.
For general information about footprint design and reflow soldering see
application note AN10365 (Surface mount reflow soldering description).

AN11689

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Recommendations for PCB assembly of DSN1006

Revision history
Rev

Date

Description

1

20150729

Initial version

Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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1. Introduction
Due to the trend of reduced dimensions and increased density of functionality insmartphones and other mobile devices, there is an increasing request from the industry
for extremely small components. NXP supports this trend with the new DSN1006-2(SOD993, symmetrical contacts) and DSN1006U-2 (SOD995, asymmetrical contacts)
packages. They are ultra small surface-mount chip-scale diode packages with a size of
only 1.0 mm  0.6 mm  0.27 mm (0402).
Due to the very small size of the component, NXP investigated the board assembly
process intensively in order to offer board mounting recommendations.
This includes PCB mounting pads, stencil apertures, solder paste and board assembly
process parameters.
Using the recommended dimensions for pads and stencil as described in this document
will help to achieve:• optimum stand-up height• minimum tilt
• minimum rotation• good board assembly process performance
While this application note helps minimizing any unexpected failures, following the advice
in this document is not a guarantee for a perfect Surface-Mount Technology (SMT)
assembly result. The results may differ depending on the machine capability, ambientconditions, material, etc.

2. DSN1006 (SOD993, SOD995): package details
DSN1006-2 (SOD993) and DSN1006U-2 (SOD995) are Discrete Silicon No-leads (DSN)
packages. They feature tin (Sn) plated metal contacts under the package (bottom
terminations) similar to Discrete Flat No-leads (DFN) style packages. The DSN-style
package allows 100 % utilization of the package area for active silicon, offering asignificant performance advantage per board area compared to products inplastic-molded packages.
Key Features:• Ultra small and flat package (1.0  0.6  0.27 mm3)
• Sn-plated contacts for soldering on PCB• Symmetrical contact pads for DSN1006-2 (SOD993)• Asymmetrical contact pads for DSN1006U-2 (SOD995)
The visual appearance of DSN1006-2 (SOD993) is shown in Figure 1 whereas Figure 2
shows the package dimensions.
The visual appearance of DSN1006U-2 (SOD995) is shown in Figure 3 whereas Figure 4
shows the package dimensions.

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Recommendations for PCB assembly of DSN1006

Fig 1.

DSN1006-2 (SOD993): visual appearance
DSN1006-2, leadless ultra small package; 2 terminals; body 1.0 x 0.6 x 0.27 mm

Lb

SOD993

L

1

2

b

e1

A1

A

E

D

(1)

0

0.5 mmscale

Dimensions (mm are the original dimensions)
Unit
mm

A

A1

b

D

E

e1

max 0.30
nom
min 0.24

0.03

0.51

0.65

1.05

0.49

0.55

0.95

L
0.26

0.65
0.24

Note
1. The marking bar indicates the cathode.
Outlineversionsod993_po

References
IEC

JEDEC

JEITA

Issue date
14-10-24
14-10-24

SOD993

Fig 2.

Europeanprojection

DSN1006-2 (SOD993): package dimensions

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Recommendations for PCB assembly of DSN1006

Fig 3.

DSN1006U-2 (SOD995): visual appearance
DSN1006U-2, leadless ultra small package; 2 terminals; body 1.0 x 0.6 x 0.27 mm

Lb

SOD995

L1

1

2

e1

b

e2

A1

A

E

D

(1)

0

0.5 mmscale

Dimensions (mm are the original dimensions)
Unit
mm

A

A1

b

D

E

e1

max 0.30
nom
min 0.24

0.03

0.51

0.65

1.05

0.49

0.55

0.95

L

e2

L1

0.26 0.41
0.325 0.25
0.24 0.39

Note
1. The marking bar indicates the cathode.
Outlineversionsod995_po

References
IEC

JEDEC

JEITA

Issue date
14-12-09
15-05-29

SOD995

Fig 4.

Europeanprojection

DSN1006U-2 (SOD995): package dimensions

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Recommendations for PCB assembly of DSN1006

3. PCB solder pattern
3.1 Solder pad design: general options
There are two types of solder pad / solder resist designs:
Solder Mask Defined (SMD) and Non-Solder Mask Defined (NSMD).
SMD is a method of designing the solder resist to partially overlap the copper (Cu) landing
pattern on the PCB. NSMD designs have a gap between the solder resist and the Cu
landing pattern on the PCB. These two types are described in more detail in the next
chapter.

3.1.1 SMD solder pad versus NSMD solder pad
If the solder mask extends onto the solder lands, the remaining solderable area is Solder
Mask Defined (SMD). The effective solder pad is equal to the copper area that is notcovered by the solder mask. This situation is illustrated in Figure 5, left column. In case of
an SMD pad, the copper will normally extend 75 m down to 50 m underneath the solder
mask on all sides. In other words, the copper dimension is 0.1 mm to 0.15 mm larger than
the solder mask dimension. These values may vary depending on the class of PCBs
used. This allows tolerances in copper etching and solder mask placement during PCB
production.
If the solder mask layer starts outside of the solder lands, and does not cover the copper,
this is referred to as Non-Solder Mask Defined (NSMD). The effective solder pad is equal
to the copper area. In case of an NSMD, the solder mask should be at least 50 m awayfrom the solder land on all sides. In other words, the solder mask dimension is 100 mlarger than the copper dimension. These values may vary depending on the class of
PCBs used. The main requirement is that the solder mask is sufficiently far away from thecopper, such that - with the given tolerances in solder mask application - it does notextend onto the copper. An NSMD footprint is shown in Figure 5, right column.

001aac832

001aac831

a. SMD solder pad
Fig 5.

b. NSMD solder pad

Solder Mask Defined (SMD) versus Non-Solder Mask Defined (NSMD) solder pads

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3.2 Solder pad design for DSN1006 packages (SOD993, SOD995)
3.2.1 Recommended reflow solder footprints
Based on the small dimensions of 1006 (0402) devices and the given tolerances for PCB
manufacturing, it is recommended to use Non-Solder Mask Defined (NSMD) solder pads.
The DSN1006-2 (SOD993) solder footprint with dimensions and the solder footprint
together with the package outline are shown in Figure 6.

0.6 mm
0.6 mm

0.5 mm

0.35
mm

0.35
mm

0.3
mm

1 mm

0.35
mm

0.3
mm

0.35
mm

aaa-019077

a. Reflow solder footprint
Fig 6.

0.25
mm

1 mm

0.25
mm

aaa-019078

b. Reflow solder footprint and package outline

Recommended solder footprint for DSN1006-2 (SOD993)

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The DSN1006U-2 (SOD995) solder footprint with dimensions and the solder footprint
together with the package outline are shown in Figure 7.

0.6 mm
0.5 mm

0.6 mm

0.47
mm

0.47
mm

0.13
mm

0.13
mm

1.2
mm

0.25
mm

1.2
mm

0.6
mm

1 mm

0.6
mm

aaa-019080

aaa-019079

a. Reflow solder footprint
Fig 7.

0.4
mm

b. Reflow solder footprint and package outline

Recommended solder footprint for DSN1006U-2 (SOD995)

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Recommendations for PCB assembly of DSN1006

4. Solder stencil
4.1 Stencil recommendations
Due to small apertures and pad dimensions, use a high-quality stainless-steel stencil
manufactured by laser-cut and with electropolish or plasma coating.
The recommended stencil thickness is 100 m for the DSN1006 packages.
For the DSN1006-2 (SOD993) recommended NXP footprint (see Section 3.2.1, Figure 6),
the optimum stencil aperture is shown in Figure 8.

0.25
mm

0.5 mmaaa-019081

Fig 8.

AN11689

Application note

Recommended stencil aperture for DSN1006-2 (SOD993)

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Recommendations for PCB assembly of DSN1006

For the DSN1006U-2 (SOD995) recommended NXP footprint (see Section 3.2.1,
Figure 7, the optimum stencil aperture is shown in Figure 9.

0.5 mm

0.37
mm

0.5
mm

aaa-019082

Fig 9.

AN11689

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Recommended stencil aperture for DSN1006U-2 (SOD995)

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4.2 Stencil aperture design
Area and aspect ratio are key design-guidelines for stencil apertures. The area ratio for astandard approach is > 0.66. Smaller values are possible with adequate process control.
Of course, it depends on the manufacturing environment and other requirements of the
manufacturer.
The aspect ratio should be > 1.5 which is less critical to fulfil. For explanation of area andaspect ratio, refer to Figure 10.

Cross -sectional view of a stencil
aaa-019083

of aperture opening
LW
Area ratio = area---------------------------------------------------------- = -------------------------------------area of aperture walls
2  L + W  T
Wwidth of the aperture
Aspect ratio = --------------------------------------------------------------- = -----  1 5
T
thickness of the stencil foil
Fig 10. Explanation of area and aspect ratio
Table 1.
Area and aspect ratio for stencil apertures as recommended
Stencil thickness T = 100 m
NXP recommended footprint

Aperture size

Area ratio
target > 0.62

Aspect ratio
target > 1.5

DSN1006-2 (SOD993)

250  200 m2

0.83

2.50

DSN1006U-2 (SOD995)

370 / 500  500 m2

minimum 1.06

minimum 3.70

Table 1 shows the values for aspect and area ratio of the optimum stencil apertures with astencil thickness of 100 m. It results in acceptable area ratios for the NXP footprint
recommendations.

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5. Solder paste
Besides stencil aperture and thickness, the used solder paste has a significant impact on
the printing performance. As shown in Table 2, solder pastes are available in different
solder powder grain sizes.
Table 2.

Solder paste types

Type

Powder grain size in mLess than 0.5 %larger than

10 % max. between 80 % max between

10 % max. less
than

1

160

150-160

75-150

75

2

80

75-80

45-75

45

3

60

45-60

25-45

25

4

50

38-50

20-38

20

5

40

25-40

15-25

15

6

25

15-25

5-15

5

7

15

11-15

2-11

2

Use a solder paste type 4 and higher (smaller grain size) in combination with a stencil
aperture thickness of 100 m for the DSN1006 (SOD993, SOD995) packages. As solder
paste is sensitive to age, temperature, and humidity, follow the handling recommendationsof the paste manufacturer.

6. Soldering process
For soldering of DSN1006 packages, following standard reflow processes and typicaltemperature profiles are suitable:• Convection reflow under nitrogen atmosphere is preferred to improve the solder
wetting.

• Convection reflow under air atmosphere also works, but solder joint surfaces arerough, flux residues often become darker and the soldering behavior may deteriorate.

• Vapor phase soldering is also possible.
A reflow solder profile for tin-silver-copper alloys, so-called SAC alloys (SnAg3.8Cu0.7)
based on the IPC/JEDEC joint industry standard J-STD-020D is recommended. Refer toFigure 11 and Table 3.

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Recommendations for PCB assembly of DSN1006

temperaturetp
critical zone
TL to Tp

Tp
ramp-up
TL

tL

Tsmax

Tsmin
ramp-downtspreheat

25 °C
time

T25 °C to peakaaa-019084

Fig 11. Reflow solder profile based on IPC/JEDEC J-STD-020D
Table 3.

Pb-free profile feature and specification based on IPC/JEDEC J-STD-020D

Profile feature

Values for Pb-free assembly

Average ramp-up rate (Tsmax to Tp)

3 C/s maximum

Preheat
Minimum temperature (Tsmin)

150 C

Maximum temperature (Tsmax)

200 CTime (ts) from Tsmin to Tsmax

60 s to 180 s

Liquidus temperature (TL)

217 CTime (tL) maintained above TL

60 s to 150 s

Peak/classification temperature (Tp)

260 CTime within 5 C of actual peak temperature (tp)

10 s to 30 s

Ramp-down rate

6 C/s maximum

Time 25 C to peak temperature (t25°C to peak)

8 minutes maximum

7. Handling recommendations
Besides the PCB and stencil design requirements, the ultra small size of the DSN1006
and as consequence the low weight of the component requires that some attention be
paid to the pick and place (P&P) process. Electrostatic charge may cause problems
during the pick and place (tape out) process. NXP has implemented preventive measures
such as using a conductive plastic carrier tape (embossed tape).
For rework, use equipment suitable for the ultra small package size and for handling baresilicon devices. Manual handling with tweezers (e.g. for repair) is not recommended.

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8. Summary
8.1 Recommended solder footprint and stencil aperture
The recommended solder footprint including stencil aperture are shown in Figure 12 for
DSN1006-2 (SOD993) and in Figure 13 for DSN1006U-2 (SOD995).

SOD993

1.2
0.65
0.3

0.7 0.6 0.5(2x) (2x) (2x)

0.8

0.2

0.25
(2x)

occupied area

solder resist

0.35
(2x)

solder lands

solder paste

0.45
(2x)

Dimensions in mm

15-02-20
15-03-05

sod993_fr

Recommended stencil thickness: 100 m

Fig 12. DSN1006-2 (SOD993): solder footprint and stencil aperture

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Recommendations for PCB assembly of DSN1006

SOD995

1.4
1.3
0.67
0.3

0.37

0.6 0.5(2x) (2x)0.7 0.8

0.37

0.5
0.6
occupied area

solder resist

solder lands

solder paste

0.47
0.13

15-02-09
15-02-20

Dimensions in mm

sod995_fr

Recommended stencil thickness: 100 m

Fig 13. DSN1006U-2 (SOD995): solder footprint and stencil aperture

8.2 Further recommendations
8.2.1 Stencil layout and solder paste• Stencil thickness of 100 m in combination with type 4 solder paste (refer to Table 2)
is recommended.

• A stencil aperture dimension as shown in Figure 8 and Figure 12 is recommended for
DSN1006-2 (SOD993).

• A stencil aperture dimension as shown in Figure 9 and Figure 13 is recommended for
DSN1006U-2 (SOD995).

• To get best printing (and soldering) results, control the cleaning cycle of the stencil.
8.2.2 Solder pad design• Non-Solder Mask Defined (NSMD) pads with a gap between Cu pad and solder resistof 50 m are recommended.

• Conductor (Cu trace) between solder pads on PCB is not recommended.
• Do not connect solder pads by -via.
• Connection by Cu traces (lines) is preferred.

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8.2.3 Soldering process• Convection reflow under nitrogen atmosphere is preferred.
• Convection reflow under air atmosphere also works, but:
– Using an unfavorable layout, products lean towards undefined tilting and rotationand solder joints tend to increase voiding.
– Solder joint surfaces are rough, flux residues often become darker and thesoldering behavior may deteriorate.

• Vapor phase soldering is also possible.
8.2.4 Handling recommendations• Manual handling with tweezers (e.g. for repair) is not recommended.
• Keep control of thawing time of solder paste bundle to avoid too much humidity inpaste.

• To prevent drying of flux in solder paste, maintain the relative humidity of shop floor atsolder paste print until reflow to 40 % to 60 %.

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9. Legal information
9.1

Definitions

Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.

9.2

Disclaimers

Limited warranty and liability — Information in this document is believed tobe accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordancewith the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product

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design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with theirapplications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in thecustomer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications andthe products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express, impliedor statutory, including but not limited to the implied warranties of
non-infringement, merchantability and fitness for a particular purpose. The
entire risk as to the quality, or arising out of the use or performance, of thisproduct remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be liable
to customer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for loss of business, businessinterruption, loss of use, loss of data or information, and the like) arising out
the use of or inability to use the product, whether or not based on tort(including negligence), strict liability, breach of contract, breach of warranty or
any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above andall direct or general damages), the entire liability of NXP Semiconductors, itsaffiliates and their suppliers and customer’s exclusive remedy for all of theforegoing shall be limited to actual damages incurred by customer based onreasonable reliance up to the greater of the amount actually paid by customer
for the product or five dollars (US$5.00). The foregoing limitations, exclusions
and disclaimers shall apply to the maximum extent permitted by applicablelaw, even if any remedy fails of its essential purpose.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

9.3

Trademarks

Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.

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10. Contents
1
2
3
3.1
3.1.1
3.2
3.2.1
4
4.1
4.2
5
6
7
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
9
9.1
9.2
9.3
10

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DSN1006 (SOD993, SOD995): package details 3
PCB solder pattern . . . . . . . . . . . . . . . . . . . . . . 6
Solder pad design: general options . . . . . . . . . 6
SMD solder pad versus NSMD solder pad . . . . 6
Solder pad design for DSN1006 packages(SOD993, SOD995) . . . . . . . . . . . . . . . . . . . . . 7
Recommended reflow solder footprints . . . . . . 7
Solder stencil . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stencil recommendations . . . . . . . . . . . . . . . . . 9
Stencil aperture design . . . . . . . . . . . . . . . . . . 11
Solder paste . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Soldering process . . . . . . . . . . . . . . . . . . . . . . 12
Handling recommendations . . . . . . . . . . . . . . 13
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Recommended solder footprint and stencil
aperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Further recommendations . . . . . . . . . . . . . . . 15
Stencil layout and solder paste . . . . . . . . . . . . 15
Solder pad design. . . . . . . . . . . . . . . . . . . . . . 15
Soldering process . . . . . . . . . . . . . . . . . . . . . . 16
Handling recommendations . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2015.

All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 July 2015
Document identifier: AN11689