GIGALIGHT 2x100GBASE-SR4 QSFP DD Optical Transceiver Module
P/N: GQD-MPO201-DSR4CFeatures

8 channels full-duplex transceiver modules

Transmission data rate up to 26Gbps per channel



8 channels 850nm VCSEL array

8 channels PIN photo detector arrayInternal CDR circuits on both receiver and transmitter channels

Support CDR bypass

Low power consumption <4W



Hot Pluggable QSFP DD form factor

Maximum link length of 70m on OM3 Multimode Fiber (MMF)and 100m on OM4 MMF

MPO24 connector receptacle



Operating case temperature 0℃ to +70℃



3.3V power supply voltage

RoHS2.0 compliant(lead free)

Applications
IEEE 802.3bm 100GBASE SR4Description
The Gigalight Technologies GQD-MPO201-DSR4C is a Eight-Channel, Pluggable, Parallel, Fiber-Optic QSFP
Double Density for 2x100 Gigabit Ethernet Applications. This transceiver is a high performance module forshort-range multi-lane data communication and interconnect applications. It integrates eight data lanes in eachdirection with 8x25.78125Gbps bandwidth. Each lane can operate at 25.78125Gbps up to 70 m using OM3 fiber or
100 m using OM4 fiber. These modules are designed to operate over multimode fiber systems using a nominal
wavelength of 850nm. The electrical interface uses a 76 contact edge type connector. The optical interface uses
an 24 fiber MTP (MPO) connector. This module incorporates Gigalight Technologies proven circuit and VCSEL
technology to provide reliable long life, high performance, and consistent service.

17-Apr-21 Rev. V21

Figure1. Module Block Diagram
2x100GBASE-SR4 QSFP DD is one kind of parallel transceiver. VCSEL and PIN array package is key technique,through I2C system can contact with module.

Absolute Maximum Ratings
Parameter

SymbolMinMax

Unit

Supply Voltage

Vcc-0.3

3.6

V

Input Voltage

Vin-0.3

Vcc+0.3

V

Storage TemperatureTst-2085℃

Case Operating Temperature

Top

070℃

Humidity(non-condensing)

Rh

595%

17-Apr-21 Rev. V2

2

Recommended Operating Conditions
Parameter

SymbolMin

TypicalMax

Unit

Supply Voltage

Vcc

3.13

3.3

3.47

V

Operating Case temperature

Tca

070℃

Data Rate Per Lane

fd

Humidity

Rh

Power DissipationPm

25.78125
5Gbps
85%

4W

Electrical Specifications
Parameter

SymbolMin

TypicalMax

Unit

Differential input impedanceZin

90100110ohm

Differential Output impedanceZout

90100110ohm

Differential input voltage amplitudeaAmplitude

ΔVin

300

1100

mVp-p

Differential output voltage amplitude

ΔVout

500

800

mVp-p

Skew

Sw300

ps

Bit Error Rate

BER

5E-5

Input Logic Level High

VIH

2.0

VCC

V

Input Logic Level Low

VIL00.8

V

Output Logic Level High

VOH

VCC-0.5

VCC

V

Output Logic Level Low

VOL00.4

V

Note：
1. BER=5E-5; PRBS 2^31-1@25.78125Gbps. Pre-FEC
2.
3.

Differential input voltage amplitude is measured between TxnP and TxnN.
Differential output voltage amplitude is measured between RxnP and RxnN.

17-Apr-21 Rev. V23

Optical Characteristics
Table 3 - Optical Characteristics
ParameterSymbol

Min

TypicalMax

Unit

Notes

Transmitter
Centre Wavelength

λc

840

850860nm-

RMS spectral width∆λ--0.6nm-

Average launch power, each lane

Pout-8.4

-

2.4

dBm

-

Optical Modulation Amplitude(OMA),each lane

OMA-6.43dBm-

Transmitter and dispersion eyeclosure(TDEC),each lane

TDEC

4.3dBExtinction Ratio

ER-dB-

-30

dB-

3-

Average launch power of OFF
transmitter, each lane
Eye Mask coordinates:
X1, X2, X3, Y1, Y2, Y3

Hit Ratio =5x10-5SPECIFICATION VALUES{0.3,0.38,0.45,0.35,0.41.0.5}

ReceiverCentre Wavelength

λc

840

850

Stressed receiver sensitivity inOMA

860

nm

-

-5.2dBm

1-

Maximum Average power atreceiver , each lane
input, each lane
Minimum Average power atreceiver , each lane

2.4dBm-10.3

dBm

Receiver Reflectance-12dB-dBm-dBm-dB-LOS Assert-30

LOS De-Assert – OMA
LOS Hysteresis

-7.5
0.5

Note：

1．Measured with conformance test signal at TP3 for BER = 5E-5 Per-FEC

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4

Pin Description

17-Apr-21 Rev. V2

5

17-Apr-21 Rev. V26

Figure2. Electrical Pin-out Details
ModSelL Pin
The ModSelL is an input signal that must be pulled to Vcc in the QSFP-DD module. When held low by the host, themodule responds to 2-wire serial communication commands. The ModSelL allows the use of multiple QSFP-DDmodules on a single 2-wire interface bus. When ModSelL is “High”, the module shall not respond to oracknowledge any 2-wire interface communication from the host.

17-Apr-21 Rev. V27

In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the ModSelL
de-assert time after any QSFP-DD modules are deselected. Similarly, the host must wait at least for the period of
the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting
periods of different modules may overlap as long as the above timing requirements are met.
ResetL Pin
The ResetL signal shall be pulled to Vcc in the module. A low level on the ResetL signal for longer than theminimum pulse length (t_Reset_init) (SeeTable 13 ) initiates a complete module reset, returning all user module

settings to their default state.
InitMode Pin
InitMode is an input signal. The InitMode signal must be pulled up to Vcc in the QSFP-DD module. The InitModesignal allows the host to define whether the QSFP-DD module will initialize under host software control (InitModeasserted High) or module hardware control (InitMode deasserted Low). Under host software control, the module
shall remain in Low Power Mode until software enables the transition to High Power Mode, as defined in Section
7.5. Under hardware control (InitMode de-asserted Low), the module may immediately transition to High Power
Mode after the management interface is initialized. The host shall not change the state of this signal while themodule is present. In legacy QSFP applications, this signal is named LPMode. See SFF-8679 for signal
description.
ModPrsL PinModPrsL must be pulled up to Vcc Host on the host board and grounded in the module. The ModPrsL is asserted“Low” when the module is inserted and deasserted “High” when the module is physically absent from the hostconnector.
IntL Pin
IntL is an output signal. The IntL signal is an open collector output and must be pulled to Vcc Host on the hostboard. When the IntL signal is asserted Low it indicates a change in module state, a possible module operational
fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serialinterface. The IntL signal is deasserted “High” after all set interrupt flags are read.

17-Apr-21 Rev. V28Power Supply Filtering
The host board should use the power supply filtering shown in Figure3.

Figure3. Host Board Power Supply Filtering

Optical Interface Lanes and Assignment
The optical interface port is a male MPO24 connector .

Figure 4. Optical Receptacle and Channel Orientation

DIAGNOSTIC MONITORING INTERFACE(OPTIONAL)
Digital diagnostics monitoring function is available on all Gigalight QSFP DD products. A 2-wire serialinterfaceprovides user to contact with module.
The structure of the memory is shown in Figure 5. The memory space is arranged into a lower, single page,address space of 128 bytes and multiple upper address space pages. This structure permits timely access toaddresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID
information and threshold settings, are available with the Page Select function. The structure also provides
address expansion by adding additional upper pages as needed.
.

17-Apr-21 Rev. V2

9

The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order toenable a one-time-read for all data related to an interrupt situation. After an interrupt, IntL, has been asserted,
the host can read out the flag field to determine the affected channel and type of flag.

Figure5. QSFP DD Memory Map

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10

Figure6. Low Memory Map

17-Apr-21 Rev. V2

11

Figure7. Page 00 Memory Map

Timing for Soft Control and Status Functions

Figure9. Timing Specification

17-Apr-21 Rev. V212

Mechanical Dimensions

Figure10. Mechanical Specifications

Regulatory Compliance
Gigaligth GDM-SPO201-LR8C are Class 1 Laser Products. They are compliant with the followingstandards:
FeatureLaser Safety

Electrical Safety
Environmental protection

17-Apr-21 Rev. V2Standard
IEC 60825-1:2014 (3rd Edition)
IEC 60825-2:2004/AMD2:2010
EN 60825-1-2014
EN 60825-2:2004+A1+A2
EN 62368-1: 2014
IEC 62368-1:2014
UL 62368-1:2014
Directive 2011/65/EU with amendment(EU)2015/863

13

FeatureStandard

CE EMC

EN55032：2015
EN55035：2017
EN61000-3-2:2014
EN61000-3-3:2013
FCC Part 15, Subpart B
ANSI C63.4-2014

FCC

Complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice
No. 50, dated June 24, 2007.

References
1. QSFP-DD Hardware Rev 5.0
2. CMIS V4.0
3. Ethernet 100GBASE-SR4 IEEE802.3bm

Ordering information
Part Number
GQD-MPO201-DSR4C

Product Description
QSFP DD, 2x100GBASE-SR4, 70m on OM3 Multimode Fiber (MMF)and 100m on
OM4 MMF

Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be
specifically confirmed in writing by GIGALIGHT before they become applicable to any particular order orcontract. In accordance with the GIGALIGHT policy of continuous improvement specifications may change
without notice.
The publication of information in this data sheet does not imply freedom from patent or other protective rightsof GIGALIGHT or others. Further details are available from any GIGALIGHT sales representative.

sales@gigalight.com
http://www.gigalight.com

17-Apr-21 Rev. V214

Revision History
Revision

Date

Description

Aug.01, 2017

Advance Release.

V1Jun.15, 2020

Mechanical Specifications revised, update QSFP-DD standard
reference

V2

Apr-17-2021

Modify Regulatory Compliance.

V017-Apr-21 Rev. V215