Phase Shifter Module
PN L-6001-PHS6-1
DESCRIPTION
PHS6-1 is a phase shifter module that plugs into the XBERT andParalleX™ Chassis. The phase shifter module splits the REF-CLK into 6
different REF-CLK output signals, where every REF-CLK output signal
can be delayed by up to ±200ps. This allows the user to align the output
patterns of multiple E-BERT modules, or to introduce well defined delays.
This could help with crosstalk measurements in multi-channel applications
for example.

KEY FEATURESLabView

GPIB/USB/LAN Interface via XBERT Chassis.

Small size: width 25.4mm (1”)

Phase shift resolution 1ps with ±5ps accuracy

Max. phase shift ±200ps with minimum ±5ps
and maximum 10% accuracy

6 independent phase shiftable reference clock
output signals

TMdrivers available

PHASE SHIFTER MODULE PN L-6001-PHS6-1
FUNCTIONAL BLOCK DIAGRAM

Channel 1
OutputSingle Ended
Channel 2
OutputSingle Ended

Ref. Clock
Input
Single Ended

Channel 3
OutputSingle Ended
Channel 4
OutputSingle Ended
Channel 5
OutputSingle Ended
Channel 6
OutputSingle Ended

Reference
Clock Output
Single EndedXBERT PLATFORM: LETS YOU START SMALL AND GROWXBERT is a low-cost, modular Bit Error Rate Test
Platform used for verification and test of 10Gb/s andabove optical and electrical chip, sub assembly andsystem designs. ParalleX™ allows users to performseveral BER tests at once using a single clock source.
The system is ideal for developers desiring to run
simultaneous BER tests on parallel interfaces or multiple
independent interfaces. XBERT and ParalleX™ arescalable so users can start off with a single channel andadd modules to grow the system. Manufacturers canrealize great savings by taking advantage of the XBERTand ParalleX™ system’s scalability to perform parallel
testing in volume production environments.

PB PHS6-1 Rev. A.01 Issued date 2010.03.10

All specifications are subject to change without noticePHS6-1ModuleProductOverview

Phase Shifter Module PN L-6001-PHS6-1
KEY PERFORMANCE PARAMETERS

INPUT
PARAMETERSYMBOL

MIN

MAX

UNIT

Reference Clock Input frequency

Rref

400

850

MHz

Reference Clock Input Voltage Swing

Vin5001400mV

Reference Clock Input Termination

NOTE

AC - coupled

Reference Clock Input Duty Cycle

tDCin

4555%Reference Clock Input Impedance

ZRef

Reference Clock Rise and Fall timetr / tf

455590350

ps

20% - 80%MINMAXUNITNOTEOUTPUT DELAYED REFERENCE CLOCK CHANNEL 1-6PARAMETERSYMBOLΔφ Cycle-to-Cycle Jitter

tc-cJ

2

psRMS

Note 1

Δφ Total Jitter

tTJ

18

psPP

Note 1

Δφ Random Jitter

tRJ

2

psRMS

Note 1

Δφ Reference Clock Output Voltage Swing

Vout

950mV550

Δφ Reference Clock Output Termination

AC - coupled

Δφ Reference Clock Output Duty CycletDCout4060%

Δφ Reference Clock Output Impedance

ZoRef

4555

Δφ Reference Clock Rise and Fall timetr / tf50350

ps

Δφ Reference Clock Output phase uncertainty

RPS±5[ps]±10[%]

Δφ Reference Clock Output phase shift total

RShift±200

ps±10%Δφ Reference Clock Output increment of phaseshift fine tuning

RFT

1ps

Note 2

20% - 80%
Note 1

PHS6-1ModuleProductMISCELLANEOUS
PARAMETERSYMBOL

MIN

Warm up time

tw30

Operating Temperature

TOP

10

Note:
1
Depending on stability and quality of input signal.
2Works for a total range of ±200ps.
3Min. warm up time to achieve the specified limits

Am Borsigturm 1313507 Berlin-Germany+49 30 814 512 40 00 ph+49 30 814 512 40 20 fax
www.luceotec.com
sales@luceotec.com

MAX50UNITNOTE

min

Note 3°C

Ambient temp.

Overview