Proceedings of IBIC2012, Tsukuba, Japan

MOPA12CHARACTERIZATION OF A WIDE DYNAMIC-RANGE,RADIATION-TOLERANT CHARGE-DIGITIZER ASIC FORMONITORING OF BEAM LOSSES
Giuseppe Guido Venturini∗ , CERN / EPFL, Switzerland
Francis Anghinolfi, CERN, Geneva, Switzerland
Bernd Dehning, CERN, Geneva, Switzerland
Maher Kayal, EPFL, STI IEL GR-KA, Lausanne, Switzerland

An Application Specific Integrated Circuit (ASIC) has
been designed and fabricated to provide a compact solution to digitize current signals from ionization chambers
and diamond detectors, employed as beam loss monitors
at CERN and several other high energy physics facilities.
The circuit topology has been devised to accept positive
and negative currents, to have a wide dynamic range (above
120 dB), withstand radiation levels over 10 Mrad and offer different modes of operation, covering a broad range
of applications. Furthermore, an internal conversion reference is employed in the digitization, to provide an accurate
absolute measurement. This paper discusses the detailed
characterization of the first prototype: linearity, radiation
tolerance and temperature dependence of the conversion,as well as implications and system-level considerations regarding its use for beam instrumentation applications in ahigh energy physics facility.

INTRODUCTION
A Beam Loss Monitoring (BLM) system is employedthroughout the accelerators at CERN. The aim of the system is threefold: ensure machine protection, provide diagnostics information and aid machine setup. Different kindsof radiation monitors are employed, depending on the accelerator, measurement and expected signal, among themionization chambers and diamond detectors. The monitors
are exposed to the secondary particles shower that is initiated when a high-energy particle escapes from the beam
and impacts against the vacuum chamber. The number ofparticles that are lost from the beam and the energy deposited in the machine components – such as the LHC superconducting magnets – are reconstructed from the output
signal provided by the monitors, which are situated in studied locations along the rings, injection and extraction lines,
and dump targets.
The BLM system for a large accelerator like the LHC has
several channels – over 4000 – and it extends over a significant distance. The system is built in layers: the analog output signal of the monitors is digitized by data acquisition
cards located in the tunnel, implementing a Current to Fre∗ giuseppe.guido.venturini@cern.ch

Table 1: Specifications
Parameter
Dynamic range
1 × 106
Input polarity
doubleMinimum detected current 1 nA
(through averaging)
1 pA
Linearity error< ±10 %
Integration window
40 µs
Total ionizing dose
10 Mrad in 20 years

quency Converter (CFC) and providing a conversion code
every 40 µs. The front-end acquisition boards transmit thedata to the Threshold Comparators (TC), located in VME
crates on the surface, via double redundant optical links.
The TCs collect, analyze the data and optionally trigger abeam abort, when losses that could potentially compromise
the machine are detected. A Combiner and Survey (CS)card installed in the same VME crate receives and handles
the beam abort signals. The data are then forwarded for
logging and display [1].
In this context, this contribution discusses the state of
the research that has been carried out at CERN, regarding
the first step of the data processing outlined above: dataacquisition from the monitors.

REQUIREMENTS
The requirements for the BLM front-end acquisition arelisted in Table 1.
The intensity of the ionizing radiation detected by theparticle monitors can span several decades, as a consequence of the characteristics of the accelerator, the operational status of the machine, the location in which the monitor is installed and the background radiation. For this reason, the different kinds of beam loss monitors designed andemployed at CERN are able to provide a linear responseover a wide dynamic range (DR) [2].
Since before the beginning of operation of the LHC, aneffort has been made in the BE/BI/BL section to study anddesign a single-gain acquisition board, able to cover thewhole dynamic range of the input signal [3]. This work follows the same approach as the currently operational LHC

ISBN 978-3-95450-119-9
Beam Loss Detection

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c 2012 by the respective authors — cc Creative Commons Attribution 3.0 (CC BY 3.0)
Copyright ○AbstractMOPA12

Proceedings of IBIC2012, Tsukuba, Japan

design and aims to provide further improved performances.
The reasons behind the requirement for double polarity
operation in this design are: flexibility, reliability and resistance to interference. During machine operation, someinterference – eg. an external coupling to the HV power
supply line – could lead to the signal to be digitized appearing of opposite polarity for a short duration of time. The
minimum requirement for the front-end design is avoiding saturation. In the case of an input range extending toboth signal polarities this problem is not present. Additionally, in this case both positive and negative HV power
supplies can be used to bias the monitors. The circuit topology presented here is able to digitize positive and negative charge inputs, covering the −1.05 mA/1.05 mA range,
without any change in configuration.

c 2012 by the respective authors — cc Creative Commons Attribution 3.0 (CC BY 3.0)
Copyright ○The analog to digital conversion performed by the frontend will inevitably be affected by an error. Since the data
provided by the front-end is to be compared with threshold values in the TCs, the requirement for the front-end isto provide a measurement affected by an error well below
the uncertainty level of the threshold values [4]. For thisreason, a linearity error equal to 10% or better is required.
The integration time has an important impact on the design of the front-end: as the input current is integrated overshorter time intervals, the front-end design becomes morechallenging, since the A/D conversion has to occur with thesame dynamic range but over a shorter time frame. The integration time is dictated by machine requirements. For the
LHC, and for this design, it is fixed to 40 µs [1, 3].
The digitized output from the front-end electronics is, after processing, compared with threshold values provided bysimulations, available in terms of charge. It is hence necessary that the measurement data can be re-conducted tocharge values, in Coulomb. For this reason, each front-end
circuit needs to have available on board an absolute charge
reference, which has to be common to all interfaces. Additionally, the charge reference shall be insensitive, within
the maximum allowed error, to drifts due to temperatureand ionizing radiation effects.
The radiation tolerance has an effect on the location
where the front-end electronics can be installed: as themonitor is exposed to ionizing radiation, either ability towithstand the radiation effects or a cabling infrastructure
to carry the analog signal to a location where the radiationlevel isn’t of concern are required. Employing custom layout techniques and opportune design choices, the radiation
tolerance that can be achieved with an ASIC allows the user
to place the front-end electronics close to the detector. This
option provides advantageous features: the measurement
is carried out in loco, with an analog front-end loaded by
the minimum capacitance, then the results transmitted digitally, reliably and at high data rate, as digital transmissions
have a low sensitivity to noise and interference. The disadvantage is additional complexity inherent in analog integrated circuit (IC) design.

I

I

V
t

t

t
VTH

I

V
QREF

1/f

t

t

Qref

Figure 1: Charge-balance current-to-frequency conversion
scheme.

CIRCUIT TOPOLOGY
Current-to-Frequency Conversion
The topology here presented has its roots in the chargebalance CFC architecture [5]. A Current-to-Frequency
Converter produces a series of pulses at a frequency fc thatis proportional to the input signal level. Referring to Fig. 1,
the input current is integrated until a threshold (VT H ) isreached, then a pulse triggers the subtraction of a fixedcharge (QREF ) from the integrator, and another cycle begins. The charge subtraction is implemented summing, at
the input node, a current −IREF for a fixed time TREF ,generated by a timing circuit (eg. one-shot).
It is possible to show that the ideal relationship between
the oscillation frequency fc and the DC input current IIN
is given by Eq. 1.
fc =

IIN
QREF

(1)

The charge collected in a time interval (0, TW ) can be
estimated simply counting the pulses in the same interval(Eq. 2, quantization error neglected):
´ TW

ˆ TW
Nc =

fc dt =00

Iin (t) dt
QIN
=
QREF
QREF

(2)

The conversion does not depend on many circuit parameters: in particular, it does not depend on the value of thethreshold voltage and the capacitors values, linking output
voltage and input charge in the integrator. The quantization error is stored in the integrator and added to the next
measurement, allowing decreasing the minimum detectablesignal increasing TW or, equivalently, summing together
multiple consecutive samples. These features make thetopology interesting for implementing the front-end electronics of a BLM system.
The main limitation is the dynamic range that can beachieved: at the upper end, increasing the input level, bandwidth limitations will prevent the generation and summation of an accurate charge packet, and, as a result, the minimum value for QREF is fixed. At the lower end, the input
current can decrease until the point where the accumulated
charge in TW is below QREF , minimum detectable signal,
prompting the designer to reduce further the value of thereference charge, but QREF can only be reduced until theISBN 978-3-95450-119-92Beam Loss DetectionProceedings of IBIC2012, Tsukuba, JapanI

Table 2: Subdivision of the Dynamic Range in Sub-ranges,
in Terms of Absolute Values of DC Currents

I
V

t

IN

t

clk

-VTH

Configuration
logic

REF
V

Sens.
0
1
2
3

VTH
t

disabled
by DAC

I

t
QREF

-I

I

QREF
t

Max
200 nA
4.1 µA
65.5 µA
1.05 mA

Overlap
N/A
1.6
1.6
1.6

DR
256
25.6
25.6
25.6

V

I

+I

Min
1 nA
160 nA
2.56 µA
41 µA

bit+
CODE

bit-

V

t

t

1.5bit reconfigurable
current-output DAC

Figure 2: Circuit topology.
minimum value due to the aforementioned bandwidth limitation is met.
To further increase the dynamic range, it is possible, in
principle, to extend the measurement time TW , lowering
the minimum detectable signal, see Eq. 2, but in many applications, such as the one under consideration, that is not
an option.
A different approach has to be adopted to cover a dynamic range of six decades with a 40us integration time.
Other solutions have been proposed in the literature: theCFC board employed in the LHC BLM system pairs thefrequency conversion with a 12bit pipeline ADC, increasing the DR of the CFC converter of a more than three
decades, but requires matching of the CFC and the ADC
data [3]. See also [6, 7].

Circuit Topology
Since the maximum frequency at which the charge injection can be performed is behind the dynamic range limitation, and the frequency is set by QREF (Eq. 1), the input
dynamics can be extended adjusting the reference charge tokeep the front-end in the operative frequency range.
A simplified diagram of the circuit topology is shownin Fig. 2. Similarly to the CFC, the analog part of thecircuit provides current integration, detection of thresholdcrossing and injection of charge packets to balance the integrator, implemented through a fully-differential integrator, with configurable feedback capacitance, two dynamic
comparators and a configurable three-level current-output
Digital-to-Analog Converter (DAC).
The integrator is fully differential (differential input /differential output) to take advantage of the better power
supply rejection of differential structures, minimize the influence of noise, ease the requirements on the comparators and to reduce even-order harmonic distortion. An adjustment in the integrator is necessary: the value of the
feedback capacitance needs to be scaled with the reference
charge of the converter, or the requirements on comparators
resolution would become challenging.
Additionally, due to the small unit capacitance, the routing parasitic capacitance can have a considerable influenceon the ratio of feedback capacitances, especially for thehighest sensitivity setting. To minimize this effect, thethreshold voltages start at 1V for the highest sensitivity
configuration and are decreased of a factor two for every
sensitivity step, correspondingly, the capacitor values canbe increased by the same factor.
The comparators are responsible for generating the signals that trigger the charge injection: an additional one ispresent in Fig. 2 compared to Fig. 1, to allow operation
with positive and negative inputs. The third output level inthe DAC is introduced for the same reason. The comparators are clocked at 12.8 MHz and provide two symmetricdifferential thresholds.
The circuit-wide configuration is set by a logic circuitthat monitors the comparators output. A first version ofthis logic was implemented on chip with a Triple Modular
Redundant (TMR) design, while configuration inputs areavailable to disable it and implement the logic off-chip (forexample in an FPGA). This strategy has been useful for
testing the device and optimizing the algorithm.
The modulator input ranges for each sensitivity are listed
in Table 2: an overlap factor equal to 1.6 has been ensured
between the ranges to allow an hysteresis in the transitions.
A robust scheme has been implemented to provide thereference charge the A/D conversion: the charge packets
are generated by enabling the current-output DAC according to a time reference provided by a 12.8 MHz clock, generated off-chip with a temperature-compensated piezoelectric oscillator. The DAC is biased by a current reference
embedded on chip, based on a 1.2 V radiation-hardened
band-gap reference, to minimize temperature dependence,with an optional external resistor for LSB step calibration.
The output code is generated counting the charge injections events, grouped by reference charge value, with a positive sign when it is a positive charge that has been injected,
and a negative sign when a negative charge has been injected. The final output code is given by the sum of theweighted contributions of each reference charge, as shownin Eq. 3.

QREF,1
Nc,1 +QREF,0 D
D
|
{z
}


 24 QREF,2
QREF,3+
Nc,2 +
Nc,3
QREF,0 D
QREF,0 D
|
{z
}
|
{z
}

h

QIN
QREF,0i

28= Nc,0 +(3)

212

ISBN 978-3-95450-119-9
Beam Loss Detection

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c 2012 by the respective authors — cc Creative Commons Attribution 3.0 (CC BY 3.0)
Copyright ○t

MOPA12MOPA12

Proceedings of IBIC2012, Tsukuba, JapanThe ratio of the reference charges has been opportunely
selected to be a power of 2, hence the weighing operationis performed with a bit shift.
The ASIC has an additional operation mode: the integrator outputs are connected to an ADC and the configurationof the front-end is set externally by the user, implementing
a setup similar to [3], with the additional advantages of having a selectable full-scale charge (8 pC, 164 pC, 2.56 nC or
42 nC, adjustable within 20 %) and double polarity operation. The fully differential integrator outputs are matched
to common radiation-tolerant ADCs, such as [8]. Thismode provides an alternative radiation-tolerant solution.

(a) Layout of the chip.

FIRST PROTOTYPE AND
MEASUREMENT RESULTS
The prototype was designed using a three-metal 0.25 µm
CMOS technology and then ported to a six metal stack to
be submitted in a Multi-Project Wafer (MPW). The prototype has two channels, each one as shown in the diagramin Fig. 3.
BIAS

CEXT_P,N

VREF_P VREF_N

VDD_PERIVDD_DIGITAL
VDD_ANALOG

CLK

GND_PERIGND_DIGITAL
GND_ANALOG(b) Microscope picture.

clk

IN

-I
ENCODE

I

+I
CODE

DOUT
GS

1.5bit reconfigurable
current-output DAC

IN
NEG

Figure 4: Layout and microscope picture of the fabricatedprototype.

REFERENCE

disabled
by DAC

c 2012 by the respective authors — cc Creative Commons Attribution 3.0 (CC BY 3.0)
Copyright ○MODEfront-end integrator

comparators bank

V/I

VCM
Voltagereference

Configuration
logic

Voltagereference

CONF
DTH(5:2)

G(1:0)DAC reference

VBG

Table 3: Device Characterization Summary

RESET_NV/I

REXT

IEXT DCONF(1:0)

Figure 3: Diagram of a single A/D channel.
The chip layout and a full micrograph are shown in
Fig. 4a and Fig. 4b, respectively. In the layout, it is possible to see two channel arranged horizontally, with theanalog part on the outside and the digital circuitry in the
middle, separated from the sensitive parts. Considering thechannel on the left side, the left half of the analog part consists of the DAC and the charge reference, on the right handside it is possible to see the capacitors and the amplifier inbetween. On the right of the amplifier there are the comparators, which bridge the analog and the digital parts. The
chip size is 2.4 mm x 3.775 mm.
The test-bench setup has been developed as follows: ananalog board hosts the DUT, providing separated analog,
digital and pad power supplies, biasing and voltage references. The analog board is connected to the instrument
providing the test stimuli and to an optional secondary
board with an Altera Cyclone IV FPGA to set the configuration remotely and provide the measurement resultsover TCP/IP. A set of software tools have been developed
to read, process and display the data, and control the instruments through a GPIB-TCP/IP bridge.

A/D converter
Integration time
Input current range
Input charge range
Offset(currently WIP)
Default LSB step
Dynamic range
Linearity error
Peak S/N ratio
SFDR at 999Hz, 1mA
Total ionizing dose
Supply voltage
Clock
Power

40 µs
−1.05 mA to 1.05 mA−42 nC to 42 nC
12 fC
300 pA over 40 µs
50 fC ±20 %, adjustable
120 dB< ±5 %
53 dB
50 dB
10 Mrad(Si)
2.5 V
12.8 MHz
40 mW

Reference charge
Drift with TID
Drift with temperature

3 % at 10 × 106 rad(Si)< 600 ppm/◦C

The results from DC, AC, temperature and radiation tolerance (TID) measurements are summarized in Table 3.
The linearity error is defined as 2(ym − yid )/(ym + yid ),where ym is the measured output code and yid is the output
code expected by fitting the measurement points. It is limited by different effects: at low input signals, the current

ISBN 978-3-95450-119-9
4Beam Loss DetectionProceedings of IBIC2012, Tsukuba, Japanfollowed by a 1 week annealing cycle at 100 ◦C. From the
beginning to the end of the irradiation cycles, the full scalecharge drifts of approximately 3 %.
Measurements taken in a climatic chamber in the 13 ◦C43 ◦C range showed a negative temperature dependence ofthe reference charge with the temperature, in absolute value
below 600 ppm/◦C and in reasonable agreement with simulations (within 30 %). An external resistor can be provided
to further reduce the temperature coefficient.

SNR (LSQ sine fitting at 91Hz)

60
9 bit

50

8 bit
7 bit

S/N ratio [dB]

40 6 bit
5 bit

30
4 bit

20

MOPA12

3 bit

CONCLUSIONS

2 bit

0 -9
10

10

-8

-7

-6

-5

10
10
10
Input current amplitude [A]

10

-4

10

-3

Figure 5: Measured SNR.

leakage of the input structures provide an additional chargethat is superimposed to the test stimulus and introduce ameasurement error. As the input signal increases, the frontend switches between different configurations (sensitivities). The transistor matching imperfections introduce a
different linearity error for every input signal range. Near
the full-scale, dynamic effects cause an additional error in
the injected charge. Overall the linearity error is within±5 %.
Additionally, in the current setup, there is a spurious input signal of variable amplitude below 1 nA. The reason
is probably a ground loop effect and it is currently being
investigated. Because of that, the offset in Table 3 is 12 fC(300 pA integrated for 40 µs), the expectation is that the effective device offset is 40 aC (1 pA integrated for 40 µs).
Figure 5 plots the measured SNR versus input amplitude
for a sinusoidal current stimulus at a frequency equal to91 Hz. In the figure, the measurement is compared withthe theoretical peak SNR for traditional A/D converters andwith the measured SNR of each configuration, obtained
disabling the configuration logic. The SNR increases withthe amplitude, as an effect of the reduced weight of thequantization error, until the amplitude falls in the next
range: at this point the sine wave is partially digitized witha coarser quantization step and, correspondingly, the SNRdrops. The same effect repeats every time the front-end
configuration changes.
FFT spectra were acquired with a sinusoidal input current at a frequency close to 1 kHz and amplitude equal to
1 mA. The measured SFDR is 50 dB and it is limited bythird order harmonic distortion.
The radiation tolerance – Total Ionizing Dose (TID) effects – has been investigated at CERN in an X-ray irradiation facility. A tungsten tube provided an X-ray beam witha peak at 20 keV and a dose rate of 47.5 krad(Si)/min. The
characteristics of the device have been measured at logarithmically spaced total dose values, up to 10 Mrad(Si),The 120 dB DR ASIC presented provides a compact andflexible solution to convert a wide dynamic range charge toa digital code. The IC operates DC-coupled to the detector,
it has an on-chip charge reference and it digitizes positive
and negative currents. The ASIC has been irradiated with
X-rays up to 10 Mrad with only minor changes in the circuit performance.

ACKNOWLEDGMENTS
The authors would like to thank the many people who
provided advice, MPW support, code and instrumentation at CERN, EPFL and PSI. In particular, Maciej
Kwiatkowski for writing the TCP/IP code used in the testbench FPGA, and William Viganò, for providing the FPGA
board.

REFERENCES[1] E.B. Holzer, B. Dehning, E. Effinger, J. Emery, G. Ferioli,
and et al. Beam loss monitoring system for the LHC. In
Nuclear Science Symposium Conference Record, IEEE, volume 2, pages 1052 – 1056, 2005.
[2] B. Dehning, E. Effinger, J. Emery, G. Ferioli, E. B. Holzer,
D. Kramer, L. Ponce, M. Stockner, and C. Zamantzas. LHC
beam loss detector design: Simulations and measurements.
(LHC-PROJECT-Report-1026):4 p, 2007.
[3] E. Effinger, B. Dehning, J. Emery, G. Ferioli, and C. Zamantzas. Single gain radiation tolerant LHC beam loss acquisition card. Technical Report CERN-AB-2007-028, CERN,
Geneva, 2007.
[4] M.Stockner and C. W. Fabjan. Beam Loss Calibration Studies
for High Energy Proton Accelerators. PhD thesis, Vienna,
Tech. U., 2007.
[5] D. N. MacLennan and F. H. Wells. A wide range digitizer
for direct coupled analogue signals. Journal of Physics E:
Scientific Instruments, 1(3):284, 1968.
[6] H. Flemming and E. Badura. A high dynamic charge to frequency converter ASIC, 2004.
[7] W. Viganò, B. Dehning, E. Effinger, G. Venturini, and C. Zamantzas. Comparison of three different concepts of high dynamic range and dependability current measurement digitisers for beam loss systems. IBIC’2012, 2012.
[8] G. Magazzu, A. Marchioro, and P. Moreira. A rad-hard 8channel 12-bit resolution ADC for slow control applicationsin the LHC environment. 2001.

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