Fixed Delay Lines

LTCC Chip Delay Lines

CDM

T h e C D M - t y p e D e l a y L i n e i s a n LT C C ( L o w - Te m p e r a t u r e , C o - f i r e dCeramic) chip Delay Line. By removing one (1) line fromthe CDKD-type differential Delay Line, we have been able toaccommodate a very compact overall area of only 5mm x 2.5mm.

FEATURES•

We have described a CDM/CDKD common land pattern
on which the CDM-type should be mounted for delaytimes within a 3ns delay range, and on which the CDKDtype should be mounted as a single-ended Delay Line,
with the 2 differential lines connected in series (CDKD2-line connection), for delay times over 3ns. We provide
a 0.1~10ns delay range using a CDM/CDKD common landpattern.It is a RoHS-compliant component.

COMMON SPECIFICATIONS
Impedance:
50ȍ±10%Waveform Distortion:
Overshoot/preshoot under 20%
Delay Time Temp. Coefficient: 0~150ppm/°C
Insulation Resistance:
DC50V, over 100Mȍ
Operating Temperature Range: -40°C to +85°C
Storage Temperature Range: -40°C to +120°CPACKAGE DIMENSIONS & PIN CONFIGURATION
Unit:mm (inch)
To l e r a n c e : ± 0 . 1 ( ± 0 . 0 0 4 )To p Vi e w

0ART .UMBER#$-^#$-#$-^#$-#$- #$-

$IMENSION OF 4
-AX -AX
-AX -AX
-AX -AXP l e a s e r e f e r t o t h e C D K D p a g e i n t h e d i ff e r e n t i a l D e l a y L i n e s e c t i o n
for CDKD-series Package Dimensions and Pin Configuration.

Note: Published speciﬁcations are subject to change without prior notice.
WN 124009I/12.02

Fixed Delay Lines

LTCC Chip Delay Lines

CDM

CDM Product Speciﬁcations
Part Number

Delay Time

CDM0105
CDM0205
CDM0305
CDM0405
CDM0505
CDM0605
CDM0705
CDM0805
CDM0905
CDM1005
CDM1205
CDM1305
CDM1405
CDM1505
CDM1605
CDM1805
CDM2005
CDM2505
CDM3005

100ps±50ps
200ps±50ps
300ps±50ps
400ps±50ps
500ps±50ps
600ps±50ps
700ps±50ps
800ps±50ps
900ps±50ps
1.0ns±50ps
1.2ns±60ps
1.3ns±65ps
1.4ns±70ps
1.5ns±75ps
1.6ns±80ps
1.8ns±90ps
2.0ns±100ps
2.5ns±125ps
3.0ns±150ps

Rise/Fall Time
(20%-80%)
100ps Max.
100ps Max.
100ps Max.
100ps Max.
100ps Max.
100ps Max.
110ps Max.
120ps Max.
130ps Max.
150ps Max.
180ps Max.
190ps Max.
210ps Max.
220ps Max.
240ps Max.
270ps Max.
300ps Max.
360ps Max.
400ps Max.

Actual(1)*DC䌾15GHz
DC䌾10GHz
DC䌾10GHz
DC䌾7.5GHz
DC䌾6GHz
DC䌾5GHzDC䌾4.3GHz
DC䌾3.8GHz
DC䌾3.3GHz
DC䌾3GHzDC䌾2.5GHz
DC䌾2.3GHz
DC䌾2.1GHz
DC䌾2GHzDC䌾1.8GHz
DC䌾1.7GHz
DC䌾1.5GHz
DC䌾1.2GHz
DC䌾1.1GHz-3dB Passband
DC
Actual(2)*Guarantee(3)* Resistance
1.0ȍMax.
DC䌾3GHz
DC䌾3GHz
DC䌾3GHz
DC䌾3GHz1.0ȍMax.
DC䌾3GHz
DC䌾3GHz1.0ȍMax.
DC䌾3GHz
DC䌾3GHz1.5ȍMax.
DC䌾3GHz
DC䌾3GHz1.5ȍMax.
DC䌾3GHz
DC䌾3GHz3.0ȍMax.
DC䌾3GHz
DC䌾3GHz3.0ȍMax.
DC䌾3GHz
DC䌾3GHz3.0ȍMax.
DC䌾3GHzDC䌾2.7GHz 3.5ȍMax.
DC䌾3GHzDC䌾2.4GHz 3.5ȍMax.
DC䌾2.5GHz DC䌾2GHz
4.0ȍMax.
DC䌾2.3GHz DC䌾1.9GHz 4.5ȍMax.
DC䌾2.1GHz DC䌾1.7GHz 4.5ȍMax.
DC䌾2GHzDC䌾1.6GHz 4.0ȍMax.
DC䌾1.8GHz DC䌾1.5GHz 4.5ȍMax.
DC䌾1.7GHz DC䌾1.3GHz 4.5ȍMax.
DC䌾1.5GHz DC䌾1.2GHz 5.0ȍMax.
DC䌾1.2GHz DC䌾960MHz 5.0ȍMax.
DC䌾1.1GHz DC䌾880MHz 5.0ȍMax.

(1)* Actual (1) is the typical value when utilizing land pattern #1.
(2)* Actual (2) is the prospective value when utilizing land pattern #2, derived from EM Simulation.
(3)* The guaranteed value of -3dB passband is limited by the band width of the pin probe during
product inspection.

Characteristics of CDKD 2-Line Connection on land pattern #2 (For reference only.)
Part Number

Delay Time

CDKD2005 (2 Line Connection)
CDKD2505 (2 Line Connection)
CDKD3005 (2 Line Connection)
CDKD3505 (2 Line Connection)
CDKD4005 (2 Line Connection)
CDKD4505 (2 Line Connection)
CDKD5005 (2 Line Connection)

4.0±0.2 ns
5.0±0.25 ns
6.0±0.3 ns
7.0±0.35 ns
8.0±0.4 ns
9.0±0.45 ns
10.0±0.5 ns

Rise/Fall Time(4)*(20%-80%)
0.3ns Typ.
0.4ns Typ.
0.5ns Typ.
0.65ns Typ.
0.8ns Typ.
0.9ns Typ.
1.0ns Typ.

-3dB Passband
Actual(4)*DC䌾750MHz
DC䌾600MHz
DC䌾500MHz
DC䌾350MHz
DC䌾300MHz
DC䌾250MHz
DC䌾200MHz

DC
Resistance
10.0ȍMax.
10.0ȍMax.
10.0ȍMax.
12.0ȍMax.
15.0ȍMax.
15.0ȍMax.
15.0ȍMax.

(4)* Rise/Fall time and –3dB passband for 2-line connection use are only reference values, as
the CDKD-series is inspected and guaranteed as a differential Delay Line.

REFLOW SOLDERING CONDITIONS㪪㫋㫆㫉㪸㪾㪼㩷㪺㫆㫅㪻㫀㫋㫀㫆㫅㫊㩷㪸㫉㪼㩷㪸㫊㩷㫇㪼㫉㩷㪤㪪㪣㪈㪅㩷㪫㪿㪼㫊㪼㩷㪺㫆㫄㫇㫆㫅㪼㫅㫋㩷㪽㪸㫄㫀㫃㫀㪼㫊㩷㪸㫉㪼㩷㫅㫆㫋㩷㫄㫆㫀㫊㫋㫌㫉㪼㪄㫊㪼㫅㫊㫀㫋㫀㫍㪼㪅㩷
Baking prior to reflow is not required.

4EMP

J-STD-020C Pb-Free Standard

 #
 #

 # -AX^ SEC^ SEC

0REHEAT ^ #  ^ SEC

4IME
Note: Published speciﬁcations are subject to change without prior notice.
WN 124009I/12.02

Fixed Delay Lines

CDM

LTCC Chip Delay Lines

SUGGESTED LAND PATTERN
Unit:mm (inch)
To l e r a n c e : ± 0 . 1 ( ± 0 . 0 0 4 )(1) Land Pattern #1 (CDM only)(2) Land Pattern #2 (CDM/CDKD common land)

Conditions for 50Ω Line
Line width: 0.76mm(0.03inch)
Line thickness: 10~55μm
PWB εr: 4.0
Distance from GND plane: 0.4mm(3) CDM-type mounting configuration, land pattern #2
Solder Paste Mask
To p Vi e w
Pad Position(4) CDKD-type mounting configuration for 2-Line Connection, land pattern #2
Solder Paste Mask
To p Vi e w
Pad Position

Note: Published speciﬁcations are subject to change without prior notice.
WN 124009I/12.02

Fixed Delay Lines

CDM

LTCC Chip Delay LinesTYPICAL APPLICATIONS AND TERMINATION METHODS(1) Analog circuit

r:Impedance of signal source

Rin :Input adjustment resistance
Zo :Characteristics impedance of internalElements (=Output impedance)
Ro :Internal adjustment resistance (=Zo)
r+Rin=Zo=R(2) PECL( 3 ) LV P E C L(4) TTL, CMOS

Ro should be adjusted to a value near Zo.

Note: Published speciﬁcations are subject to change without prior notice.
WN 124009I/12.02

Fixed Delay LinesLTCC Chip Delay Lines

CDM

OUTPUT WAVEFORMS (1)(1) 0.5ns CDM0505, Land Pattern #1
Output waveform (Step function)
㪈㪅㪌㪇

In

㪇
㪄㪈
㪄㪉
㪄㪊
㪄㪋
㪄㪌㪄㪍㪄㪎
㪄㪏㪄㪐㪄㪈㪇Out㪤㪸㪾㫅㫀㫋㫌㪻㪼㪲㪻㪙㪴㪈㪅㪇㪇

Sdd21 Amplitude / Frequency㪇㪅㪌㪇
㪇㪅㪇㪇
㪄㪇㪅㪌㪇
㪄㪈㪅㪇㪇
㪄㪈㪅㪌㪇
㪇㪅㪇㪇

㪇㪅㪌㪇

㪈㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪈㪅㪌㪇㪇㪉㪅㪇㪇

Output waveform (1GHz Clock)㪇㪅㪌㪇㪞㫉㫆㫌㫇㩷㪛㪼㫃㪸㫐㪲㫅㫊㪴

InOut㪇㪅㪇㪇
㪄㪇㪅㪌㪇
㪄㪈㪅㪇㪇
㪄㪈㪅㪌㪇
㪇㪅㪇㪇

㪇㪅㪌㪇

㪈㪅㪇㪇
㪫㫀㫄㪼㪲㫅㫊㪴

㪈㪅㪌㪇

㪉
㪊
㪋
㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴

㪌㪍㪌㪍Group Delay㪈㪅㪌㪇㪈㪅㪇㪇㪈㪉㪅㪇㪇㪈㪇㪅㪐㪇㪅㪏㪇㪅㪎㪇㪅㪍㪇㪅㪌㪇㪅㪋㪇㪅㪊㪇㪅㪉㪇㪅㪈㪇㪇㪈㪉㪊㪋㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴(2) 1ns CDM1005, Land Pattern #1Sdd21 Amplitude / Frequency

Output waveform (Step function)
㪈㪅㪌㪇InOut㪤㪸㪾㫅㫀㫋㫌㪻㪼㪲㪻㪙㪴㪈㪅㪇㪇㪇㪅㪌㪇㪇㪅㪇㪇㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇㪈㪅㪇㪇㪉㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪊㪅㪇㪇㪋㪅㪇㪇

Output waveform (1GHz Clock)㪈㪅㪌㪇㪇㪄㪈㪄㪉㪄㪊㪄㪋㪄㪌㪄㪍㪄㪎㪄㪏㪄㪐㪄㪈㪇㪇㪞㫉㫆㫌㫇㩷㪛㪼㫃㪸㫐㪲㫅㫊㪴㪇㪅㪌㪇Out㪇㪅㪇㪇
㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇㪇㪅㪌㪇㪈㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪈㪅㪌㪇㪉㪅㪇㪇㪉㪊㪋㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴㪌

㪍

㪌

㪍

Group DelayIn㪈㪅㪇㪇

㪈

㪉
㪈㪅㪏
㪈㪅㪍
㪈㪅㪋
㪈㪅㪉
㪈
㪇㪅㪏
㪇㪅㪍
㪇㪅㪋
㪇㪅㪉
㪇
㪇

㪈

㪉

㪊
㪋
㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴Note: Published speciﬁcations are subject to change without prior notice.
WN 124009I/12.02

Fixed Delay Lines

LTCC Chip Delay Lines

CDMOUTPUT WAVEFORMS (2)(3) 2ns CDM2005, Land Pattern #1
Output waveform (Step function)
In㪈㪅㪇㪇

Out㪤㪸㪾㫅㫀㫋㫌㪻㪼㪲㪻㪙㪴㪈㪅㪌㪇

Sdd21 Amplitude / Frequency㪇㪅㪌㪇㪇㪅㪇㪇㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇㪈㪅㪇㪇㪉㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪊㪅㪇㪇

㪇

㪋㪅㪇㪇

Output waveform (500MHz Clock)㪈㪅㪌㪇㪇㪅㪌㪇

Out㪇㪅㪇㪇㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇㪈㪅㪇㪇㪉㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪊㪅㪇㪇㪇㪅㪌㪈㪈㪅㪌㪉㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴㪉㪅㪌

㪊

㪉㪅㪌

㪊

Group Delay㪞㫉㫆㫌㫇㩷㪛㪼㫃㪸㫐㪲㫅㫊㪴In㪈㪅㪇㪇

㪇
㪄㪈
㪄㪉
㪄㪊㪄㪋
㪄㪌
㪄㪍
㪄㪎
㪄㪏
㪄㪐
㪄㪈㪇

㪋㪅㪇㪇

㪋
㪊㪅㪌㪊㪉㪅㪌
㪉
㪈㪅㪌
㪈
㪇㪅㪌
㪇㪇㪇㪅㪌

㪈㪈㪅㪌㪉㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴(4) 3ns CDM3005, Land Pattern #1
Output waveform (Step function)
㪈㪅㪌㪇

In

   Out㪤㪸㪾㫅㫀㫋㫌㪻㪼㪲㪻㪙㪴㪈㪅㪇㪇

Sdd21 Amplitude / Frequency㪇㪅㪌㪇㪇㪅㪇㪇㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇㪈㪅㪇㪇㪉㪅㪇㪇㪊㪅㪇㪇㪋㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪌㪅㪇㪇㪍㪅㪇㪇

Output waveform (333MHz Clock)㪇㪄㪈㪄㪉㪄㪊㪄㪋㪄㪌
㪄㪍㪄㪎㪄㪏㪄㪐
㪄㪈㪇㪇㪍㪈㪅㪇㪇

㪌㪞㫉㫆㫌㫇㩷㪛㪼㫃㪸㫐㪲㫅㫊㪴    InOut㪇㪅㪇㪇
㪄㪇㪅㪌㪇
㪄㪈㪅㪇㪇
㪄㪈㪅㪌㪇
㪇㪅㪇㪇

㪉㪅㪇㪇

㪋㪅㪇㪇
㪫㫀㫄㪼㪲㫅㫊㪴

㪍㪅㪇㪇㪈㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴

㪈㪅㪌

㪉

㪈㪅㪌

㪉

Group Delay㪈㪅㪌㪇
㪇㪅㪌㪇

㪇㪅㪌

㪋
㪊
㪉
㪈
㪇
㪇

㪇㪅㪌

㪈
㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴Note: Published speciﬁcations are subject to change without prior notice.
WN 124009I/12.02

Fixed Delay Lines

LTCC Chip Delay Lines

CDM

OUTPUT WAVEFORMS (3)(5) 4ns CDKD2005- 2 Line Connection
Output waveform (Step function)
In㪈㪅㪇㪇

 Out㪤㪸㪾㫅㫀㫋㫌㪻㪼㪲㪻㪙㪴㪈㪅㪌㪇

Sdd21 Amplitude / Frequency㪇㪅㪌㪇㪇㪅㪇㪇㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇㪉㪅㪇㪇㪋㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪍㪅㪇㪇

㪇

㪏㪅㪇㪇

Output waveform (250MHz Clock)㪞㫉㫆㫌㫇㩷㪛㪼㫃㪸㫐㪲㫅㫊㪴

㪈㪅㪇㪇

Out

㪇㪅㪇㪇
㪄㪇㪅㪌㪇
㪄㪈㪅㪇㪇
㪄㪈㪅㪌㪇
㪇㪅㪇㪇

㪉㪅㪇㪇㪋㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪍㪅㪇㪇㪇㪅㪌㪈㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴

㪈㪅㪌㪉

㪈㪅㪌

㪉

Group Delay㪈㪅㪌㪇    In㪇㪅㪌㪇

㪇
㪄㪈
㪄㪉
㪄㪊
㪄㪋
㪄㪌
㪄㪍
㪄㪎
㪄㪏
㪄㪐
㪄㪈㪇

㪏
㪎
㪍
㪌
㪋
㪊
㪉
㪈
㪇
㪇

㪏㪅㪇㪇

㪇㪅㪌

㪈
㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴(6) 6ns CDKD3005- 2 Line Connection
Output waveform (Step function)㪈㪅㪌㪇In   Out㪤㪸㪾㫅㫀㫋㫌㪻㪼㪲㪻㪙㪴㪈㪅㪇㪇Sdd21 Amplitude / Frequency㪇㪅㪌㪇㪇㪅㪇㪇㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇㪉㪅㪇㪇㪋㪅㪇㪇㪍㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪏㪅㪇㪇Out㪇㪅㪇㪇㪈㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴㪈㪅㪌㪉㪈㪅㪌㪉Group Delay㪞㫉㫆㫌㫇㩷㪛㪼㫃㪸㫐㪲㫅㫊㪴㪇㪅㪌㪇㪇㪅㪌㪈㪉In㪈㪅㪇㪇㪇㪈㪇㪅㪇㪇

Output waveform (167MHz Clock)
㪈㪅㪌㪇

㪇
㪄㪈
㪄㪉
㪄㪊㪄㪋
㪄㪌
㪄㪍
㪄㪎
㪄㪏㪄㪐
㪄㪈㪇㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇

㪈㪇
㪏㪍
㪋㪉
㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇

㪉㪅㪇㪇

㪋㪅㪇㪇

㪍㪅㪇㪇
㪏㪅㪇㪇
㪫㫀㫄㪼㪲㫅㫊㪴

㪈㪇㪅㪇㪇

㪈㪉㪅㪇㪇

㪇

㪇㪅㪌

㪈
㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴Note: Published speciﬁcations are subject to change without prior notice.
WN 124009I/12.02

Fixed Delay Lines

LTCC Chip Delay Lines

CDM

OUTPUT WAVEFORMS (4)(7) 10ns CDKD5005- 2 Line Connection
Sdd21 Amplitude / Frequency

Output waveform (Step function)
㪈㪅㪌㪇In   Out㪤㪸㪾㫅㫀㫋㫌㪻㪼㪲㪻㪙㪴㪈㪅㪇㪇㪇㪅㪌㪇㪇㪅㪇㪇㪄㪇㪅㪌㪇㪄㪈㪅㪇㪇㪄㪈㪅㪌㪇㪇㪅㪇㪇㪌㪅㪇㪇㪈㪇㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴㪈㪌㪅㪇㪇㪇㪉㪇㪅㪇㪇

Output waveform (100MHz Clock)㪈㪅㪌㪇㪇㪄㪈㪄㪉㪄㪊
㪄㪋㪄㪌㪄㪍㪄㪎
㪄㪏㪄㪐㪄㪈㪇

Out㪇㪅㪇㪇

㪇㪅㪏㪈㪉㪇㪞㫉㫆㫌㫇㩷㪛㪼㫃㪸㫐㪲㫅㫊㪴㪇㪅㪌㪇㪇㪅㪋㪇㪅㪍㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴Group DelayIn㪈㪅㪇㪇

㪇㪅㪉

㪄㪇㪅㪌㪇
㪄㪈㪅㪇㪇

㪈㪌
㪈㪇
㪌
㪇

㪄㪈㪅㪌㪇
㪇㪅㪇㪇

㪌㪅㪇㪇㪈㪇㪅㪇㪇㪫㫀㫄㪼㪲㫅㫊㪴

㪈㪌㪅㪇㪇

㪉㪇㪅㪇㪇

㪇

㪇㪅㪉

㪇㪅㪋
㪇㪅㪍
㪝㫉㪼㫈㫌㪼㫅㪺㫐㪲㪞㪟㫑㪴㪇㪅㪏㪈

RoHS Compliance Status
Initially developed only as a RoHS-compliant component.

Note: Published speciﬁcations are subject to change without prior notice.
WN 124009I/12.02