Electrical BERT Module
PN L-6001-EBERT-5
DESCRIPTIONEBERT is a Bit Error Rate Test module that plugs in to the XBERT andParalleX™ Chassis. EBERT-5 can generate and receive electrical datafrom 8.5 Gb/s up to 11.3 Gb/s (options are available to extend this range).
Optionally the EBERT-5 module can operate in the 5G range. User
programmable PRBS patterns can be changed via an easy to use GUI. A
pattern trigger output provides an electrical trigger synchronous with thepattern for use with an oscilloscope or other test equipment. Front panel
indicators give immediate status for Tx and Rx Data.

KEY FEATURES
Data Rates 8.5 to 11.3 Gbps. (standard)
Option 112: 8.0 to 11.3Gbps
Option 114: additional 4.25 to 5.65Gbps mode
Opt 112 & 114 can be combined to give 4.0 to 5.65Gbps
Option 124: 8.5 to 12.5Gbps
Option 133: 8.5 to 11.3Gbps and 4.25 to 6.25Gbps

ELECTRICAL BERT MODULE PN L-6001-EBERT-5

Differential Electrical Pattern Generator (SMA Connector)
Differential Electrical Error Detector (SMA Connector)

Ref. ClockOutputDifferential orSingle EndedFUNCTIONAL BLOCK DIAGRAM

Output crossing adjustable from 20% to 80%
Variable data output level from 1 to 3V
PRBS:
7, 9, 10, 11, 15, 21, 23, 31
User-Pattern: 8Bit - 8Kbyte
1111
Clock-Pattern: /1, /2, /4, /8
Additional:
K28.0-K28.7, CJPAT, SSPS-64
and others

Clock
Input

Data output polarity swap and Data input polarity swap

Error
Checker

10G
Data Input
Differential orSingle Ended

Pattern
Generator

10G
Data Output
Differential orSingle Ended

Clock
DomainBER detection: 0.5 to < 10E-15

Ref. Clock
InputSingle Ended

Single error and error rate injection:1 E-3 to 1E-15µC via GPIB

Data log Gating-time: up to 5000h
Reference Clock Input (single ended)
and Output (diff)
TMLabViewdrivers available

Small size: width 50.8mm (2”)
XBERT PLATFORM: LETS YOU START SMALL AND GROW BIGXBERT is a low-cost, modular Bit Error Rate Test
Platform used for verification and test of 10Gb/s andabove optical and electrical chip, sub assembly andsystem designs. ParalleX™ allows users to performseveral BER tests at once using a single clock source.
The system is ideal for developers desiring to run
simultaneous BER tests on parallel interfaces or multiple
independent interfaces. XBERT and ParalleX™ arescalable so users can start off with a single channel andadd modules to grow the system. Manufacturers canrealize great savings by taking advantage of the XBERTand ParalleX™ system’s scalability to perform parallel
testing in volume production environments.

PB EBERT-5 Rev. A.02 Issued date 2010.04.06 | All specifications are subject to change without noticeElectrical BERT Module PN L-6001-EBERT-5
KEY PERFORMANCE PARAMETERSEPG10-x
PARAMETER

Data RateSYMBOL

MinMaxUNIT

NOTE

8.5 (8.0)

11.3Gbps

Standard mode
8.0 Gbps Opt112

4.3 (4.0)

5.65Gbps

Option 114
4.0 Gbps Opt112

DR

Data Formats

NRZ
7, 9, 10, 11, 15, 21,23, 31

PRBS PatternUser-Defined Pattern

865536Bit

Note 413Vpp

Others available
on request23

ps

20% - 80%

1.5ps

Note 5%Adjustable

Data Output Signal Channel P or N(single ended)

DOutP/N

Data Output Rise and Fall timetr / tf

Output JitterJrms

CrossingCr

2080

Differential Output Impedance

ZODiff90110

Data Output Termination

TypicalTypicalAC - coupled

Measurable Bit Error Rate

BER

<10E-150.5

Data Input Signal Channel P or N

DInP/N

1001000mVpp

Single ended

Differential Data Input signal(DInDiff=DInP-DInN)

DInDiff

200

2000

mVpp

Note 2Differential Input Impedance

ZInDiff

90110

MHz

Opt112 500MHzmin

Data Input Termination

Note 1AC - coupled

Reference Clock Input Frequency

Pref531.25707.35

Reference Clock Input Impedance

ZRef

4555

Reference Clock Input Termination

AC - coupled

Sync Signal

Sync

550

1100mVpp

Note 3Operating Temperature

TOP040°C

Ambient temp.

Note:
12345
Opt112
Opt114

BER of better than 10E-15 can only be achieved if the min input voltage level is applied
Minimum input voltage to guarantee error free detection (BER < 10 -15)
Default function is pattern trigger. Other functions like pulse per error byte are possible. For more detailed information
contact Luceo Technologies
Pattern input from 8 to 128 bit in 8 bit steps and from 128 to 65536 bit in 128 bit steps.
Preset patterns eg K28.5, CJPAT etc are available on requestMeasured at: duty cycle 50%, PRBS31, DR= 11.3Gbps, output voltage= 2V, BER= 1E-12This option extends the operating data rate for the EBERT-5 down to 8.0Gbps
This option is for the additional ‘5G mode’ that covers 4.3 to 5.7Gbps. In combination with Opt112, the lower data rate
is moved to 4.0Gbps
ELECTRICAL EYE-DIAGRAM Duty cycle 50%, PRBS31,DR=11.3Gbps, output voltage=2.5V

Am Borsigturm 1313507 Berlin-Germany+49 30 814 512 40 00 ph+49 30 814 512 40 20 fax
www.luceotec.com
sales@luceotec.com