Uniform Sector
XccelaTM Flash Memory

GD25LX256E

GD25LX256EDATASHEET

http://www.elm-tech.com

1

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Contents
1

FEATURES .........................................................................................................................................................42

GENERAL DESCRIPTIONS..............................................................................................................................5

3

MEMORY ORGANIZATION...............................................................................................................................94

DEVICE OPERATIONS....................................................................................................................................10
4.1

SPI MODE ............................................................................................................................................................ 10

4.2

OPI MODE............................................................................................................................................................ 10

4.3

RESET FUNCTION .................................................................................................................................................. 104.4

ECC FUNCTION ...................................................................................................................................................... 11

4.5

DATA STROBE FUNCTION ......................................................................................................................................... 11

5

DATA PROTECTION........................................................................................................................................12

6

DATA INTEGRITY CHECK ..............................................................................................................................14

7

8

9

6.1

ECC (ERROR CHECKING AND CORRECTING) ................................................................................................................. 14

6.2

ECS# (ERROR CORRECTED SIGNAL) PIN ...................................................................................................................... 15

6.3

PARITY CHECK (CRC) .............................................................................................................................................. 15

REGISTERS......................................................................................................................................................16
7.1

STATUS REGISTER ................................................................................................................................................... 16

7.2

FLAG STATUS REGISTER ........................................................................................................................................... 17

7.3

EXTENDED ADDRESS REGISTER .................................................................................................................................. 18

INTERNAL CONFIGURATION REGISTER ...................................................................................................20
8.1

NONVOLATILE CONFIGURATION REGISTER ................................................................................................................... 20

8.2

VOLATILE CONFIGURATION REGISTER ......................................................................................................................... 22

8.3

SUPPORTED CLOCK FREQUENCIES .............................................................................................................................. 25

8.4

DATA SEQUENCE WRAPS BY DENSITY ......................................................................................................................... 26

COMMAND DESCRIPTIONS..........................................................................................................................27
9.1

ENABLE 4-BYTE MODE (B7H) .................................................................................................................................. 31

9.2

DISABLE 4-BYTE MODE (E9H).................................................................................................................................. 31

9.3

WRITE ENABLE (WREN) (06H)................................................................................................................................ 32

9.4

WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 32

9.5

WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 33

9.6

WRITE STATUS REGISTER (WRSR) (01H) ................................................................................................................... 33

9.7

WRITE EXTENDED ADDRESS REGISTER (C5H)............................................................................................................... 34

9.8

WRITE NONVOLATILE/VOLATILE CONFIGURATION REGISTER (WRCR) (B1H/81H) ............................................................ 35

9.9

READ STATUS REGISTER (RDSR) (05H)...................................................................................................................... 35

9.10

READ FLAG STATUS REGISTER (RDSR) (70H) .............................................................................................................. 36

http://www.elm-tech.com

2

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

9.11

READ NONVOLATILE/VOLATILE CONFIGURATION REGISTER (B5H/85H)........................................................................... 37

9.12

READ EXTENDED ADDRESS REGISTER (C8H) ................................................................................................................ 38

9.13

READ DATA BYTES (READ) (03H/13H) .................................................................................................................... 39

9.14

READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH/0CH)...................................................................................... 39

9.15

OCTAL OUTPUT FAST READ (8BH/7CH) .................................................................................................................... 40

9.16

OCTAL I/O FAST READ (CBH/CCH) .......................................................................................................................... 41

9.17

OCTAL I/O DTR READ (FDH)................................................................................................................................... 43

9.18

PAGE PROGRAM (PP) (02H/12H)............................................................................................................................ 44

9.19

OCTAL PAGE PROGRAM (82H/84H) ......................................................................................................................... 45

9.20

EXTEND OCTAL PAGE PROGRAM (C2H/8EH).............................................................................................................. 46

9.21

SECTOR ERASE (SE) (20H/21H)............................................................................................................................... 47

9.22

32KB BLOCK ERASE (BE32) (52H/5CH)................................................................................................................... 48

9.23

64KB BLOCK ERASE (BE64) (D8H/DCH) .................................................................................................................. 49

9.24

CHIP ERASE (CE) (60H/C7H) .................................................................................................................................. 50

9.25

DEEP POWER-DOWN (DP) (B9H)............................................................................................................................. 51

9.26

RELEASE FROM DEEP POWER-DOWN (ABH) ............................................................................................................... 51

9.27

READ UNIQUE ID (4BH).......................................................................................................................................... 52

9.28

READ IDENTIFICATION (RDID) (9FH/9EH) ................................................................................................................. 53

9.29

PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................................... 54

9.30

PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 55

9.31

ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 56

9.32

PROGRAM SECURITY REGISTERS (42H)....................................................................................................................... 57

9.33

READ SECURITY REGISTERS (48H) ............................................................................................................................. 58

9.34

INDIVIDUAL BLOCK/SECTOR LOCK (36H)/UNLOCK (39H)/READ (3DH)........................................................................... 59

9.35

GLOBAL BLOCK/SECTOR LOCK (7EH) OR UNLOCK (98H)............................................................................................... 61

9.36

ENABLE RESET (66H) AND RESET (99H)..................................................................................................................... 62

9.37

READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)................................................................................................. 63

10

ELECTRICAL CHARACTERISTICS ..........................................................................................................65

10.1

POWER-ON TIMING ................................................................................................................................................ 65

10.2

INITIAL DELIVERY STATE ........................................................................................................................................... 65

10.3

ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 65

10.4

CAPACITANCE MEASUREMENT CONDITIONS................................................................................................................. 66

10.5

DC CHARACTERISTICS .............................................................................................................................................. 67

10.6

AC CHARACTERISTICS .............................................................................................................................................. 70

11

ORDERING INFORMATION........................................................................................................................79
11.1

12

VALID PART NUMBERS ............................................................................................................................................ 80
PACKAGE INFORMATION .........................................................................................................................81

12.1

PACKAGE SOP16 300MIL ...................................................................................................................................... 81

12.2

PACKAGE TFBGA-24BALL (5X5 BALL ARRAY)............................................................................................................. 81

13

REVISION HISTORY....................................................................................................................................83

http://www.elm-tech.com

3

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

1 FEATURES◆ 256M-bit XccelaTM Flash◆ Fast Program/Erase Speed- 32M-Byte- Page Program time: 0.3ms typical- 256 Bytes per programmable page

- Sector Erase time: 30ms typical- Block Erase time: 0.1/0.2s typical◆ Standard, Octal SPI, DTR Octal SPI- Chip Erase time: 50s typical- Standard SPI: SCLK, CS#, SI, SO, IO[7:2], WP#, RESET#- Octal SPI: SCLK, CS#, IO[7:0], WP#, RESET#◆ Flexible Architecture- OPI DTR (Double Transfer Rate) Read

- Sector of 4K-Byte- 3- or 4-Byte Address Mode

- Block of 32/64K-Byte- Erase/Program Suspend/Resume◆ High Speed Clock Frequency- 200MHz for fast read

◆ Low Power Consumption- OPI Mode Data transfer up to 166MBytes/s- 25μA typical stand-by current- Octal I/O Data transfer up to 166MBytes/s- 5μA typical power-down current- DTR Octal I/O Data transfer up to 400MBytes/s with DQS◆ Advanced Security Features◆ Allows XIP(eXecute in Place) Operation- 128-bit Unique ID- High speed Read reduce overall XiP instruction fetch time

- 4K-Byte Security Registers With OTP Lock

- Continuous Read with Wrap further reduce data latency tofill up SoC cache◆ Single Power Supply Voltage- Full voltage range: 1.65~2.0V◆ Software/Hardware Write Protection- Write protect all/portion of memory via software◆ Endurance and Data Retention- Enable/Disable protection with WP# Pin- Minimum 100,000 Program/Erase Cycles- Individual Block Protection- 20-year data retention typical◆ Data Integrity Check◆ Package Information- On-chip ECC (1-bit correction every 8-Byte) (1)- SOP16 300mil- CRC detects accidental changes to raw data

- TFBGA-24ball (5x5 Ball Array)

Note:
1. When ECC is enabled, it is required to program minimum one or multiple aligned 8-Byte granularities. Every aligned 8Byte granularity should only be programmed once before Erase to ensure correct ECC operations.

http://www.elm-tech.com

4

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
2

GD25LX256E

GENERAL DESCRIPTIONSThe GD25LX256E (256M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Octal
SPI and DTR mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2, I/O3 ,I/O4, I/O5, I/O6, I/O7, WP#,
DQS, ECS# and RESET#. The Octal I/O & Octal output data is transferred with speed of 166MBytes/s, and the DTR
Octal I/O data is transferred with speed of 400MBytes/s.

CONNECTION DIAGRAM AND PIN DESCRIPTION
Figure 1 Connection Diagram for SOP16 package

IO3

1

16

SCLK

VCC

2

15

SI
(IO0)

RESET#

3

14

IO4

IO7

4

13

DQS

IO5

5

12

IO6

VSS

6

11

VCC

CS#

7

10

VSS

SO
(IO1)

8

9

IO2

Top View

16-LEAD SOP
Table 1. Pin Description for SOP16 300mil package
Pin No.

Pin Name

I/O

Description

1

IO3

I/O

Data Input Output 3

2

VCC

3

RESET#

I

Reset Input

4

IO7

I/O

Data Input Output 7

5

IO5

I/O

Data Input Output 5

6

VSS

7

CS#

I

Chip Select Input

8

SO (IO1)

I/O

Data Output (Data Input Output 1)

9

IO2

I/O

Data Input Output 2

10

VSS

Ground11

VCC

Power Supply

12

IO6

I/O

Data Input Output 6

13

DQS

O

Data Strobe Signal Output

14

IO4

I/O

Data Input Output 4

http://www.elm-tech.com

Power Supply

Ground5

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

15

SI (IO0)

I/O

Data Input (Data Input Output 0)

16

SCLK

I

Serial Clock Input

Note:
1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
2. The RESET# pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware resetfunction is not used, this pin must be connected to VCC in the system.
3. Both two sets of VCC/VSS must be connected.

Figure 2 Connection Diagram for TFBGA24 5x5 ball array package

Top View
A2

A3

NC

NC

B1

B2

B3

B4

B5

NC

SCLK

VSS

VCC

NC

C1

C2

C3

C4

C5

VSS

CS#

DQS

IO2

WP#

D1

D2

D3

D4

D5

IO3

IO4

VCC

SO(IO1) SI(IO0)A4A5RESET# ECS#

E1

E2

E3

E4

E5

IO7

IO6

IO5

VCC

VSS

24-BALL TFBGA (5x5 ball array)
Table 2 Ball Description for TFBGA24 5x5 ball array package
Pin No.

Pin Name

I/O

Description

A4

RESET#

I

Reset Input

A5

ECS#

O

ECC Correction Signal (Open Drain)

B2

SCLK

I

Serial Clock Input

B3/C1/E5

VSS

Ground

B4/D1/E4

VCC

Power Supply

C2

CS#

I

Chip Select Input

C3

DQS

O

Data Strobe Signal Output

C4

IO2

I/O

Data Input Output 2

C5

WP#

I

Write Protect Input

D2

SO (IO1)

I/O

Data Output (Data Input Output 1)

D3

SI (IO0)

I/O

Data Input (Data Input Output 0)

D4

IO3

I/O

Data Input Output 3

D5

IO4

I/O

Data Input Output 4

http://www.elm-tech.com

6

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

E1

IO7

I/O

Data Input Output 7

E2

IO6

I/O

Data Input Output 6

E3

IO5

I/O

Data Input Output 5

Note:
1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
2. The DNU ball must be floating. It may connect to internal signal inside.
3. The NC ball is not connected to any internal signal. It is OK to connect it to the system ground (GND) or leave it floating.
4. The RESET# pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware resetfunction is not used, this pin must be connected to VCC in the system.
5. If WP# is unused, it must be driven high by the host, or an external pull-up resistor must be placed on the PCB in order
to avoid allowing WP# input to float.

http://www.elm-tech.com

7

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

BLOCK DIAGRAM

Write Control
Logic

StatusRegisterRESET#
IO[7:2]SCLKCS#
SI(IO0)

SPI
Command &Control Logic

High Voltage
Generators
Page Address
Latch/Counter

SO(IO1)

http://www.elm-tech.com

Flash
MemoryColumn Decode And
256-Byte Page Buffer

DQS
ECS#

Write Protect Logic
and Row Decode

WP#

Byte Address
Latch/Counter

8

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
3

GD25LX256E

MEMORY ORGANIZATION

GD25LX256E
Each device has

Each block has

Each sector has

Each page has

32M

64/32K

4K

256

Bytes

128K

256/128

16

-

pages

8K

16/8

-

-

sectors

512/1K---

blocksUNIFORM BLOCK SECTOR ARCHITECTURE
GD25LX256E 64K Bytes Block Sector Architecture
Block
511

510

……

……

2

1

0

http://www.elm-tech.com

SectorAddress range

8191

1FFF000H

1FFFFFFH

……

……

……

8176

1FF0000H

1FF0FFFH

8175

1FEF000H

1FEFFFFH

……

……

……

8160

1FE0000H

1FE0FFFH

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

47

02F000H

02FFFFH

……

……

……

32

020000H

020FFFH

31

01F000H

01FFFFH

……

……

……

16

010000H

010FFFH

1500F000H

00FFFFH

……

……

……

0

000000H

000FFFH

9

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

4 DEVICE OPERATIONS
4.1

SPI ModeStandard SPI
The GD25LX256E features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the risingedge of SCLK and data shifts out on the falling edge of SCLK.
Octal SPIThe GD25LX256E supports Octal SPI operation when using the “Octal Output Fast Read”, “Octal I/O Fast Read”, “Octal
Input Page Program, Extended Octal Input Fast Program” (8BH/7CH, CBH/CCH, 82H/84H,C2H/8EH) commands. These
commands allow data to be transferred to or from the device at eight times the rate of the standard SPI. When using the
Octal SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Octal DTR SPIThe GD25LX256E supports DTR Octal SPI operation when using the “DTR Octal I/O Fast Read” (FDH) command. This
command allows data to be transferred to or from the device at sixteen times the rate of the standard SPI, and data output
will be latched on both rising and falling edges of the serial clock. When using the DTR Octal SPI command the SI andSO pins become bidirectional I/O pins: IO0 and IO1.

4.2

OPI ModeStandard OPI
The GD25LX256E supports Octal Peripheral Interface (OPI) operations only when the device is switched to OPI mode bysetting Byte<0> in Nonvolatile/Volatile Configuration Register. The OPI mode utilizes all 8 IO pins to input the commandcode. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Only one mode canbe active at any given times. Upon power-up and after software reset using “Enable Reset (66H) and Reset (99H)” command,the state of the device is defined by the setting of Byte<0> in Nonvolatile Configuration Register.
DTR OPI
The GD25LX256E supports DTR OPI operation when the device is switched to DTR OPI mode by setting Byte<0> in
Nonvolatile/Volatile Configuration Register. The data input/output will be latched on both rising and falling edges of theserial clock. Only one mode can be active at any given times. Upon power-up and after software reset using “Enable
Reset (66H) and Reset (99H)” command, the state of the device is defined by the setting of Byte<0> in Nonvolatile
Configuration Register.

4.3

RESET Function

The RESET# pin allows the device to be reset by the control.
The RESET# pin goes low for a minimum period of tRLRH will reset the flash. After reset cycle, the flash is at the following
states:- Standby mode
- All the volatile bits will return to the default status as power on.

http://www.elm-tech.com

10

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 3 RESET ConditionCS#

RESET#RESET

4.4

ECC Function

The ECC Correction Signal (ECS#) pin is provided to the system hardware designers to determine the ECC status during
any Read operation. The ECS# pin will be pulled low during any 8-Byte Read data output period in which an ECC event
has occurred. ECS# pin can be used to represent SEC (Single Error Correction) event. ECC Correction Signal Output
pin is an Open-Drain connection.

4.5

Data Strobe Function

The Data Strobe function is enabled as default for this device, and the DQS pin is an active output pin for the Data Strobe(DQS) signal during Read operations. The DQS signal is typically used in high speed applications to indicate when the
output data is ready to be fetched by the controllers. When the data strobe function is enabled, DQS signal is driven to
ground once CS# goes LOW, and will start to toggle when the output data is ready on the I/O pins. The toggling frequency
is the same as the CLK frequency. For STR Read operations, the data should only be latched on the rising edge of DQS
signal. For DTR Read operations, the data should be latched on both rising edge and falling edge of the DQS signal.
The Data Strobe function can also be disabled by setting the non-volatile or volatile Configuration Register Byte<0>.
Please refer to the Configuration Register description for details. When disabled, the DQS signal is not driven and will stayat Hi-Z state.

http://www.elm-tech.com

11

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
5

GD25LX256E

DATA PROTECTION

The GD25LX256E provide the following data protection methods:◆

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:- Power-Up/ Software reset (66H+99H)- Write Disable (WRDI)- Write Status Register (WRSR)- Write Extended Address Register (WEAR)- Write Nonvolatile Configuration Register (WNVCR)- Write Volatile Configuration Register (WVCR)- Page Program (PP)- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)- Erase Security Registers / Program Security Registers◆

Software Protection Mode:-The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be readbut cannot be changed.
- Individual Block Protection bit provides the protection selection of each individual block.

◆Hardware Protection Mode: WP# goes low to protect the BP0~BP4 bits and SRP0 bit.

◆

Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down Mode command and reset command (66H+99H).
Table 3. GD25LX256E Protected area size
Status Register Content

Memory Content

BP4

BP3

BP2

BP1

BP0

BlocksAddresses

Density

Portion

X

0

0

0

0

NONE

NONE

NONE

NONE

0

0

0

0

1

511

01FF0000h-01FFFFFFh

64KB

Upper 1/512

0

0

0

1

0

510 to 511

01FE0000h-01FFFFFFh

128KB

Upper 1/256

0

0

0

1

1

508 to 511

01FC0000h-01FFFFFFh

256KB

Upper 1/128

0

0

1

0

0

504 to 511

01F80000h-01FFFFFFh

512KB

Upper 1/64

0

0

1

0

1

496 to 511

01F00000h-01FFFFFFh

1MB

Upper 1/32

0

0

1

1

0

480 to 511

01E00000h-01FFFFFFh

2MB

Upper 1/16

0

0

1

1

1

448 to 511

01C00000h-01FFFFFFh

4MB

Upper 1/8

0

1

0

0

0

384 to 511

01800000h-01FFFFFFh

8MB

Upper 1/4

0

1

0

0

1

256 to 511

01000000h-01FFFFFFh

16MB

Upper 1/2

1

0

0

0

1

0

00000000h-0000FFFFh

64KB

Lower 1/512

1

0

0

1

0

0 to 100000000h-0001FFFFh

128KB

Lower 1/256

1

0

0

1

1

0 to 300000000h-0003FFFFh

256KB

Lower 1/128

1

0

1

0

0

0 to 700000000h-0007FFFFh

512KB

Lower 1/64

1

0

1

0

1

0 to 1500000000h-000FFFFFh

1MB

Lower 1/32

1

0

1

1

0

0 to 3100000000h-001FFFFFh

2MB

Lower 1/16

1

0

1

1

1

0 to 6300000000h-003FFFFFh

4MB

Lower 1/8

http://www.elm-tech.com

12

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

1

1

0

0

0

0 to 127

00000000h-007FFFFFh

8MB

Lower 1/4

1

1

0

0

1

0 to 255

00000000h-00FFFFFFh

16MB

Lower 1/2

X

1

1

0

X

ALL

00000000h-01FFFFFFh

32MB

ALL

X

1

X

1

X

ALL

00000000h-01FFFFFFh

32MB

ALL

Table 4. GD25LX256E Individual Block Protection (WPS=0)
Block

SectorAddress range

Individual Block Lock Operation

8191

01FF F000h

01FF FFFFh

512 Blocks

……

……

……

Block Lock: 36H+Address

8176

01FF 0000h

01FF 0FFFh

Block Unlock: 39H+Address

510

8160~8175

01FE 0000h

01FE FFFFh

Read Block Lock: 3DH+Address

……

……

……

……

Global Block Lock: 7EH

……

……

……

……

Global Block Unlock: 98H

……

……

……

……

1

16~31

0001 0000h

0001 FFFFh

150000 F000h

0000 FFFFh

……

……

……

0

0000 0000h

0000 0FFFh

511

0Notes:
1. Protection configuration: This bit is used to select which Write Protect scheme should be used.
2. Individual Block Protection bits are volatile lock bits. Each volatile bit corresponds to and provides volatile protection for
an individual memory sector, which is locked temporarily (protection is cleared when the device is reset or powered down).
3. The first and last sectors will have volatile protections at the 4KB sector level. Each 4KB sector in these sectors can be
individually locked by volatile lock bits setting.

http://www.elm-tech.com

13

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
6

GD25LX256E

DATA INTEGRITY CHECKThe data storage and transmission errors will cause unexpected Flash device variation that makes a harmful impact onoverall system functions. To prevent these errors, GD25LX256E product provides advanced Data Integrity Check function.
For the data storage and data transmission in the flash device, Data Integrity Check can check errors and correct them,allowing self-checking and preventing errors in advance.
The Data Integrity Check function includes two methods:- ECC (Error Checking and Correcting): to prevent the data storage errors- CRC (Cyclic Redundancy Check): to prevent the data transmission errors
The register data and software signals can also be used to associate the Data Integrity Check function to fully record theresults of checking, and can also immediately feedback.

6.1

ECC (Error Checking and Correcting)Error Correction Codes (ECC) is a commonly used technique in non-volatile memory to reduce the device Bit Error Rate
(BER) during the device operation life and improve device reliability. To achieve error detection and correction, redundancy
data must be added to store the ECC calculation results for a given length of data. In GD25LX256E, every aligned 8-Byte
data (A[2:0] = 0, 0, 0) stored in the memory array will be checked by the internal ECC engine using SEC (Single Error
Correction) Hsiao Codes algorithm. With 8-Byte ECC data granularity, ECC calculation latency time can be minimized andhighest level of data integrity can be preserved.
The default value of all memory data is FFH (Erased) when the device is shipped from the factory. A “Page Program(02H/12H)” or “Octal Page Program (82H/84H)” or “Extend Octal Page Program (C2H/8EH)” command can be used toprogram the user data into the memory array. ECC calculation will be performed during the internal programming operationand the results are stored in the redundancy or spare area of the memory array. It is necessary to program every page inaligned 8-Byte granularity so that ECC engine can store the correct ECC information. It is also required that every aligned
8-Byte data granularity can only be programmed once to avoid additional ECC calculation in the same granularity resulting
incorrect ECC results. A technique previously known as “Incremental Byte/Bit Programming to the same Byte location”
cannot be used for GD25LX256E when ECC is enabled.
During data read operations, the internal ECC engine will check the ECC results stored in the spare area and apply
necessary error correction or error detection to the main array data being read out. It is necessary to check the ECC Status
Bits (SEC) in the Status Register after every Read operation to see if the data read out contains one error or not. A Read
operation can start from any Byte address and continue through the entire memory array, so it is not necessary to align the
8-Byte granularity boundary address to start a Read command.
Additional hardware monitoring of the ECC status can also be used to observe the ECC status in real time during any data
output. When configured, the ECS# (ECC Correction Signal) pin will be pulled low during any aligned 8-Byte data output if
it contains SEC event.
The SEC bit can be reset through anyone of the following situations:- Sending a new Read Command- Issuing Software Reset Command- Hardware Reset- Power-up cycle

http://www.elm-tech.com

14

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
6.2

GD25LX256E

ECS# (Error corrected Signal) Pin

The ECS# pin is a real time hardware signal to feedback the ECC correction status. The ECS# pin is designed as an open
drain structure and a pull-up resistor (Rp) is required. In normal situation, the ECS# is kept on High-Z state. Once error
correction begins, the ECS# pin will pull low during the whole ECC chunk unit after a duration of tECSV delay timing.
The ECS# (ECC Correction Signal) pin will be pulled low during any aligned 8-Byte data output if it contains SEC (Single
Error Correction) event.
Figure 4. ECS# TimingCS#
SCLK
IO[7:0]Command & Address & Dummys
High-ZECS#ECC chunk (8 Bytes)

ECC chunk (8 Bytes)

tECSV

6.3

High-Z

ECC chunk with
ECC error detected

Parity Check (CRC)

The parity check function can only be operated in DTR read mode, and it is not supported in STR mode. The bit7~6 in
Byte<4> of the Configuration Register can set the parity check function.
For read operation after the Parity check function is enabled, the data CRC bit should be output by each CRC chunk unit.
Otherwise, read CRC code might be error.
The CRC Chunk size can be configured as 16-Byte, 32-Byte, or 64-Byte by the Configuration Register setting. However,when the device enters the “Read with Wrap” mode, while the CRC function is also enabled, and the CRC Chunk size will
be set to be identical with the Wrap Length (16-Byte, 32-Byte, or 64-Byte) by internal circuitry. Only when the device is notin the “Read with Wrap” mode, the original CRC Chunk size setting will be restored.
The data CRC Bytes are calculated by exclusive-OR on each I/O bus in the CRC chunk.
Figure 5. CRC TimingCS#
SCLK
IO[7:0]CRC

Command & Address & Dummys
Multiple of CRC chunks

http://www.elm-tech.com

15

Rev.1.3

CRC
Multiple of CRC chunks

Uniform Sector
XccelaTM Flash Memory
7

REGISTERS

7.1

Status Register

GD25LX256E

Table 5. Status RegisterNo.

Bit Name

Description

Note

S7

SRP0

Status Register Protection

Non-volatile writable

S6

BP4

Block Protect Bits

Non-volatile writable

S5

BP3

Block Protect Bits

Non-volatile writable

S4

BP2

Block Protect Bits

Non-volatile writable

S3

BP1

Block Protect Bits

Non-volatile writable

S2

BP0

Block Protect Bits

Non-volatile writable

S1

WEL

Write Enable Latch

Volatile, read only

S0

WIP

Erase/Write In Progress

Volatile, read only

The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register or configuration
register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register or configuration
register progress, when WIP bit sets 0, means the device is not in program/erase/write status register or configuration
register progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write
Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write, Program or Erase command isaccepted.
BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are set to 1, the relevant memory area becomes protectedagainst Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) commandis executed only if none sector or block is protected.
SRP0 bit
The Status Register Protect SRP0 bit are non-volatile Read/Write bits in the status register. The SRP0 bit in conjunction
with SRP1 bit (Reference Configuration Register) control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable protection.
SRP1

SRP0

WP#

Status Register

X

0

X

Software Protected

http://www.elm-tech.com

Description
The Status Register can be written to after a Write Enablecommand, WEL=1. (Default)
16

Rev.1.3

Uniform Sector
XccelaTM Flash Memory010Hardware Protected

0

1

1

Hardware Unprotected

1

1

X

One Time Program(1)GD25LX256E
WP#=0, the Status Register locked and cannot be written to.
WP#=1, the Status Register is unlocked and can be written
to after a Write Enable command, WEL=1.
Status Register is permanently protected and cannot be
written to.

NOTE:
1. This feature is available on special order. Please contact GigaDevice for details.

7.2

Flag Status Register
Table 6. Flag Status RegisterNo.

Bit Name

Description

Note

FS7

RY/BY#

Ready/Busy#

Volatile, read only

FS6

SUS1

Erase Suspend

Volatile, read only

FS5

EE

Erase Error bit

Volatile, read only

FS4

PE

Program Error bit

Volatile, read only

FS3

Reserved

Reserved

Volatile, read only

FS2

SUS2

Program Suspend

Volatile, read only

FS1

PTE

Protection Error bit

Volatile, read only

FS0

ADS

Current Address Mode

Volatile, read only

The status and control bits of the Flag Status Register are as follows:
ADS bit
The Address Status (ADS) bit is a read only bit that indicates the current address mode the device is operating in. The
device is in 3-Byte address mode when ADS=0 (default), and in 4-Byte address mode when ADS=1.
PTE bit
The PTE bit is a read only bit that indicates a program or erase failure. Indicates whether an ERASE or PROGRAM operation
has attempted to modify the protected array sector, or whether a PROGRAM operation has attempted to access the locked
OTP space. PTE is cleared to "0" after program or erase operation resumes.
SUS1, SUS2 bits
The SUS1 and SUS2 bits are read only bit in the Flag Status Register (FS6 and FS2) that are set to 1 after executing an
Erase/Program Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the
SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Erase/Program Resume (7AH) command, software reset(66H+99H) command as well as a power-down, power-up cycle.
PE bit
The Program Error (PE) bit is a read only bit that indicates a program failure. It will also be set when the user attempts toprogram a protected array sector or access the locked OTP space. PE is cleared to "0" after program operation resumes

http://www.elm-tech.com

17

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

EE bit
The Erase Error (EE) bit is a read only bit that indicates an erase failure. It will also be set when the user attempts to erase
a protected array sector or access the locked OTP space. EE is cleared to "0" after erase operation resumes
RY/BY# bit
The RY/BY# bit is a read only bit that indicates Program or Erase Status bit. Indicates whether one of the following command
cycles is in progress: WRITE STATUS REGISTER, WRITE NONVOLATILE CONFIGURATION REGISTER, PROGRAM, or
ERASE.

7.3

Extended Address Register
Table 7 Extended Address Register

No.

Name

Description

Note

EA7

SEC

Single Error Correction Bit

Volatile, read only

EA6

Reserved

Reserved

Reserved

EA5

Reserved

Reserved

Reserved

EA4

Reserved

Reserved

Reserved

EA3

Reserved

Reserved

Reserved

EA2

Reserved

Reserved

Reserved

EA1

Reserved

Reserved

Reserved

EA0

A24

Address bit

Volatile writable

The extended address register is only used when the address mode is 3-Byte mode, as to set the higher address. The
default value of the address bit is “0”.
For the read operation, the whole array can be continually read out with one command. Data output starts from the selected
128Mb, and it can cross the boundary. When the last Byte of the segment is reached, the next Byte (in a continuous reading)is the first Byte of the next segment. However, the EAR (Extended Address Register) value does not change. The random
access reading can only be operated in the selected segment.
The Chip erase command will erase the whole chip and is not limited by EAR selected segment. However, the sector erase,
block erase, program operation are limited in selected segment and will not cross the boundary.
A24 bit
The Extended Address Bits A24 is used only when the device is operating in the 3-Byte Address Mode (ADS=0), which isvolatile writable by C5H command. The lowest 128Mb memory array (00000000h – 00FFFFFFh) is selected when A24 =0,
and all instructions with 3-Byte addresses will be executed within that region.
If Configuration Register Byte <5> set to FEH, or an “Enter 4-Byte Address Mode (B7H)” instruction is issued, the device
will require 4-Byte address input for all address related instructions, and the Extended Address Bit setting will be ignored.
A24

Address Range

00000 0000h-00FF FFFFh

1

0100 0000h-01FF FFFFh

SEC bit

http://www.elm-tech.com

18

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

SEC (Single Error Correction) Status Bit are used to show the ECC results for the last Read operation. SEC bit will becleared to 0 once the device accepts a new Read command.
SEC
01

http://www.elm-tech.com

Definitions
No ECC events in all aligned 8-Byte granularities
SEC events in single or multiple 8-Byte granularities, and the data is OK to use.
(Unless it contains more than one odd bit errors in 8-Byte granularity)

19

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

8 INTERNAL CONFIGURATION REGISTER
The memory configuration is set by an internal configuration register that is not directly accessible to users. The user canchange the default configuration at power up by using the WRITE NONVOLATILE CONFIGURATION REGISTER.
Information from the nonvolatile configuration register overwrites the internal configuration register during power on or after
a reset.
The user can change the configuration during device operation using the WRITE VOLATILE CONFIGURATION REGISTER
command. Information from the volatile configuration registers overwrite the internal configuration register immediately after
the WRITE command completes.

Nonvolatile to volatile register
download after power-on or RESET

Nonvolatile configuration register

Nonvolatile to internal register download after
power-on or RESET

Volatile configuration register

Volatile to internal register download after Write
Volatile Configuration Register Command

Internal configuration register

Device behavior

8.1

Nonvolatile Configuration Register

Nonvolatile Configuration Register bits set the device configuration after power-up or reset. All bits are erased (FFh) unlessstated otherwise. This register is read from and written to using the READ NONVOLATILE CONFIGURATION REGISTER
and the WRITE NONVOLATILE CONFIGURATION REGISTER commands, respectively. The commands use the mainarray address scheme, but only the LSB is used to access different register settings, thereby providing up to 256 Bytes ofregisters (See the table below for the details). A WRITE command to a reserved address will set the device to the default
status of the corresponding Byte.
Table 8. Nonvolatile Configuration Register
Addr

<0>

Settings

I/O mode

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Description

1

1

1

1

1

1

1

1

SPI with DQS (Default)

1

1

0

1

1

1

1

1

SPI W/O DQS

1

1

1

0

0

1

1

1

Octal DTR with DQS

1

1

0

0

0

1

1

1

Octal DTR W/O DQS

1

0

1

1

0

1

1

1

Octal STR with DQS

1

0

0

1

0

1

1

1

Octal STR W/O DQSOthers<1>

Dummy cycle

http://www.elm-tech.com

0

Reserved
0

0

0

0
20

Rev.1.30

1

1

3 DummyUniform Sector
XccelaTM Flash Memory
configuration(6-7)

GD25LX256E

0

0

0

0

0

1

0

0

…

…

…

…

…

…

…

…

Others<2>

OTP configuration<3>

configuration

x

x

x

x

x

0

x

x

x

x

x

x

x

1

Security Registers Locked

x

x

x

0

x

x

x

x

SRP1 Unlocked (Default)

x

x

x

1

x

x

x

x

SRP1 Locked(11)(Default)

Reserved

1

1

1

1

1

1

1

1

50 Ohm (Default)

1

1

1

1

1

1

1

0

35 Ohm

1

1

1

1

1

1

0

1

25 Ohm

1

1

1

1

1

1

0

0

18 OhmReserved

1

x

x

x

x

x

x

CRC Disabled (Default)

1

0

x

x

x

x

x

x

16-Byte CRC

0

1

x

x

x

x

x

x

32-Byte CRC

0

0

x

x

x

x

x

x

64-Byte CRC

x

x

1

1

x

x

x

x

ODT Disabled (Default)

x

x

1

0

x

x

x

x

150-Ohm ODT

x

x

0

1

x

x

x

x

100-Ohm ODT

x

x

0

0

x

x

x

x

50-Ohm ODT

x

x

x

x

1

x

x

x

DLP Disabled (Default)

x

x

x

x

0

x

x

x

DLP Enabled

Protection

x

x

x

x

x

1

x

x

BP Protection (Default)

configuration

x

x

x

x

x

0

x

x

WPS Protection(8)

x

x

x

x

x

x

x

1

ECC Enabled (Default)

x

x

x

x

x

x

x

0

ECC Disabled

On die termination<4>
DLP configuration

ECC configuration

Others<7>

Security Registers Unlockedx

1
CRC configuration<6>(Default=10h)x

Others

<5>05~1E: 5~30 DummyReserved

OthersDriver Strength

4 DummyBeyond 128Mb
addr configuration
Continuous Readconfiguration(9)Wrapconfiguration(10)Reserved

1

1

1

1

1

1

1

1

3-Byte Address (Default)

1

1

1

1

1

1

1

0

4-Byte Address

OthersReserved

1

1

1

1

1

1

1

1

XIP Disabled (Default)

1

1

1

1

1

1

1

0

XIP Enabled

OthersReserved

1

1

1

1

1

1

1

1

Wrap Disabled (Default)

1

1

1

1

1

1

1

0

64-Byte Wrap

1

1

1

1

1

1

0

1

32-Byte Wrap

1

1

1

1

1

1

0

0

16-Byte Wrap

Othershttp://www.elm-tech.com

Reserved

21

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Notes:
1. The number of cycles must be set to accord with the clock frequency, which varies by the type of FAST READ command(See Supported Clock Frequencies table). Insufficient dummy clock cycles for the operating frequency causes the memory
to read incorrect data.
2. 03H/13H: SPI 0 dummy; OPI&DTR N/A
3. 05H/70H/9EH/9FH: SPI 0dummy; OPI&DTR 8 dummy.
4. 3DH: SPI 0dummy; OPI&DTR 8 dummy.
5. 4BH/5AH/B5H/85H: SPI&OPI&DTR 8 dummy.
6. 0BH/0CH/8BH/7CH/48H: SPI 8 dummy; OPI&DTR dummy follow CONFIGURATION REGISTER<1> (initiation = 16
dummy)
7. CBH/CCH/FDH: SPI&OPI&DTR dummy follow CONFIGURATION REGISTER<1> (initiation = 16 dummy)
8. When WPS protection is enabled, the entire memory array is being protected after Power-up or Reset.
9. Only Octal I/O Fast Read (CBH/CCH) and DTR Octal I/O Fast Read (FDH) support Continuous Read.
10. Only Octal I/O Fast Read (CBH/CCH) and DTR Octal I/O Fast Read (FDH) support Wrap read.
11. This feature is available on special order. Please contact GigaDevice for details.

8.2

Volatile Configuration Register

Volatile Configuration Register bits temporarily set the device configuration after power-up or reset. All bits are erased (FFh)unless stated otherwise. This register is read from and written to using the READ VOLATILE CONFIGURATION REGISTER
and the WRITE VOLATILE CONFIGURATION REGISTER commands, respectively. The commands use the main array
address scheme; however, only the LSB is used to access different register settings to provide up to 256 Bytes of registers(See the table below for the details). A WRITE command to a reserved address will set the device to the default status of
the corresponding Byte.
Table 9 Volatile Configuration Register
Addr

<0>

Settings

I/O mode

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Description

1

1

1

1

1

1

1

1

SPI with DQS (Default)

1

1

0

1

1

1

1

1

SPI W/O DQS

1

1

1

0

0

1

1

1

Octal DTR with DQS

1

1

0

0

0

1

1

1

Octal DTR W/O DQS

1

0

1

1

0

1

1

1

Octal STR with DQS

1

0

0

1

0

1

1

1

Octal STR W/O DQSOthers<1>

Dummy cycle
configuration(6-7)

Reserved

0

0

0

0

0

0

1

1

3 Dummy

0

0

0

0

0

1

0

0

4 Dummy

…

…

…

…

…

…

…

…

Others

<3>

05~1E: 5~30 Dummy(Default=10h)
Reserved

1

1

1

1

1

1

1

1

50 Ohm (Default)

Driver Strength

1

1

1

1

1

1

1

0

35 Ohmconfiguration

1

1

1

1

1

1

0

1

25 Ohm

1

1

1

1

1

1

0

0

18 Ohmhttp://www.elm-tech.com

22

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

OthersReserved

1

1

x

x

x

x

x

x

CRC Disabled (Default)

1

0

x

x

x

x

x

x

16-Byte CRC

0

1

x

x

x

x

x

x

32-Byte CRC

0

0

x

x

x

x

x

x

64-Byte CRC

x

x

1

1

x

x

x

x

ODT Disabled (Default)

x

x

1

0

x

x

x

x

150-Ohm ODT

x

x

0

1

x

x

x

x

100-Ohm ODT

x

x

0

0

x

x

x

x

50-Ohm ODT

x

x

x

x

1

x

x

x

DLP Disabled (Default)

x

x

x

x

0

x

x

x

DLP Enabled

Protection

x

x

x

x

x

1

x

x

BP Protection (Default)

configuration

x

x

x

x

x

0

x

x

WPS Protection(8)

x

x

x

x

x

x

x

1

ECC Enabled (Default)

x

x

x

x

x

x

x

0

ECC Disabled

CRC configuration

On die termination<4>
DLP configuration

ECC configuration

Others
<5>

<6>

<7>

Beyond 128Mb
addr configuration
Continuous Readconfiguration(9)Wrapconfiguration(10)Reserved

1

1

1

1

1

1

1

1

3-Byte Address (Default)

1

1

1

1

1

1

1

0

4-Byte Address

OthersReserved

1

1

1

1

1

1

1

1

XIP Disabled (Default)

1

1

1

1

1

1

1

0

XIP Enabled

OthersReserved

1

1

1

1

1

1

1

1

Wrap Disabled (Default)

1

1

1

1

1

1

1

0

64-Byte Wrap

1

1

1

1

1

1

0

1

32-Byte Wrap

1

1

1

1

1

1

0

0

16-Byte Wrap

OthersReserved

Notes:
1. The number of cycles must be set to accord with the clock frequency, which varies by the type of FAST READ command(See Supported Clock Frequencies table). Insufficient dummy clock cycles for the operating frequency causes the memory
to read incorrect data.
2. 03H/13H: SPI 0 dummy; OPI&DTR N/A
3. 05H/70H/9EH/9FH: SPI 0dummy; OPI&DTR 8 dummy.
4. 3DH: SPI 0dummy; OPI&DTR 8 dummy.
5. 4BH/5AH/B5H/85H: SPI&OPI&DTR 8 dummy.
6. 0BH/0CH/8BH/7CH/48H: SPI 8 dummy; OPI&DTR dummy follow CONFIGURATION REGISTER<1> (initiation = 16
dummy)
7. CBH/CCH/FDH: SPI&OPI&DTR dummy follow CONFIGURATION REGISTER<1> (initiation = 16 dummy)
8. When WPS protection is enabled, the entire memory array is being protected after Power-up or Reset.
9. Only Octal I/O Fast Read (CBH/CCH) and DTR Octal I/O Fast Read (FDH) support Continuous Read.
10. Only Octal I/O Fast Read (CBH/CCH) and DTR Octal I/O Fast Read (FDH) support Wrap read.

http://www.elm-tech.com

23

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

DLP bit
The DLP bit is Data Learning Pattern Enable bit, which is writable by B1/81H command. For Octal output, Octal I/O and
Octal I/O DTR Fast Read commands, a pre-defined “Data Learning Pattern” can be used by the flash memory controller todetermine the flash data output timing on 8 I/O pins. When DLP=0, from the falling edge of the fourth dummy clock, theflash will output “00110100” Data Learning Pattern sequence on each of the I/O or 8 I/O pins until data output. If the dummy
clock is not enough for the output of the whole Data Learning Pattern, the last several bit of the Data Learning Pattern would
be cut-off. During this period, controller can fine tune the data latching timing for each I/O pins to achieve optimum system
performance. DLP=1 will disable the Data Learning Pattern output.
Figure 6. Data Learning Pattern Sequence Diagram (STR, Dummy Clock ≥ 12)

CS#
SCLK
Address

Dummy

Data

Data Learning Pattern
IO[7:0] Command

Address

Predrive

00 FF FF 0 FF 0

0

0

0 D

7

6

0

7

6

5

4

3

2

1

Data

D

Note: 14 dummy cycle example
Figure 7. Data Learning Pattern Sequence Diagram (STR, Dummy Clock < 12)

CS#
SCLK
Address

Dummy

Data

Data Learning
Pattern
IO[7:0] Command

Address

Predrive

00 FF FF 0 FF D D

7

6

Note: 10 dummy cycle example

http://www.elm-tech.com

24

Rev.1.3

5

4

3

2

Data

D D

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 8. Data Learning Pattern Sequence Diagram (DTR, Dummy Clock ≥ 8)

CS#
SCLK
Address

Dummy
Data Learning Pattern

IO[7:0] Command

Predrive

Address

00 FF FF 0 FF 0

0

0

0

7

6

0

7

6

5

4

3

2

1

CS#
SCLK
Data
IO[7:0]

D D

Data

D D

Note: 9 dummy cycle example
Figure 9. Data Learning Pattern Sequence Diagram (DTR, Dummy Clock < 8)

CS#
SCLK
Address

Dummy

Data
Data Learning
Pattern

IO[7:0] Command

Predrive

Address

00 FF FF 0 FF D

7

6

5

4

3

Data

2

Note: 7 dummy cycle example

8.3

Supported Clock Frequencies
Table 10 Clock Frequencies of TFBGA-24 (5x5 Ball Array)
Octal I/O FAST READ

Number of Dummy ClockOPI DTR

Cycle

STR

DTR

4

40

40

40

6

84

84

84

8

104

104

104

10

133

133

133

12

152

152

152

14

166

166

166

16 and above

166

200

200

http://www.elm-tech.com

25

Rev.1.3

DUniform Sector
XccelaTM Flash Memory

GD25LX256E

Table 11 Clock Frequencies of SOP16 (300mil)
Octal I/O FAST READ

Number of Dummy ClockOPI DTR

Cycle

STR

DTR

4

40

40

40

6

84

84

84

8

104

104

104

10

133

133

133

12

152

152

152

14 and above

166

166

166

Note:
1.

Values are guaranteed by characterization and not 100% tested in production

2.

Dummy clock cycle listed above is recommended. Please contact GigaDevice for clock frequency of dummy clock
cycle configuration out of the table above.

8.4

Data Sequence Wraps by Density
Table 12 Sequence of Bytes during Wrap

Starting Address

16-Byte Wrap

32-Byte Wrap

64-Byte Wrap00-1-2- . . . -15-0-1- . .

0-1-2- . . . -31-0-1- . .

0-1-2- . . . -63-0-1- . .

1

1-2- . . . -15-0-1-2- . .

1-2- . . . -31-0-1-2- . .

1-2- . . . -63-0-1-2- . .

….

….
15-16-17- . . . -63-0-1- . .

….

….

15

15-0-1-2-3- . . . -15-0-1- . .

15-16-17- . . . -31-0-1- . .

….

….

….

31

-

31-0-1-2-3- . . . -31-0-1- . .

31-32-33- . . . -63-0-1- . .

…

….

….

….

63

-

-

63-0-1- . . . -63-0-1- . .

http://www.elm-tech.com

26

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
9

GD25LX256E

COMMAND DESCRIPTIONSAll commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the firstrising edge of SCLK after CS# is driven low. Then, the one-Byte command code must be shifted in to the device, with mostsignificant bit first on SI, and each bit is latched on the rising edges of SCLK.
Every command sequence starts with a one-Byte command code. Depending on the command, this might be followed byaddress Bytes, or by data Bytes, or by both or none. CS# must be driven high after the last bit of the command sequence
has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down,
and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can becompleted after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return todeselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write
Disable or Deep Power-Down command, CS# must be driven high exactly at a Byte boundary, otherwise the command isrejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low
is an exact multiple of eight. For Page Program, if at any time the input Byte is not a full Byte, nothing will happen and WEL
will not be reset.
Table 13 Commands (Extended/Octal SPI)
Extended SPI
Command nameCode

CMD-AddrData

Dummy

Octal SPI
CMD- Addr- CMD- Addr-

Dummy

Addr.

Data

Bytes

Bytes

Clock

Data

Data

Clock

Cycles(S-D-D)(S-S-S)

CyclesSoftware Reset Operations
Enable Reset

66h

1-0-0

0

8-0-0

8-0-0

0

0

0

Reset

99h

1-0-0

0

8-0-0

8-0-0

0

0

0

9Eh/9Fh1-0-(1)08-0-(8)8-0-(8)8

0

1 to 45Ah

1-1-(1)88-8-(8)8-8-(8)84Bh1-1-(1)88-8-(8)8-8-(8)83(4)1 to ∞

03h1-1-(1)

0

—

—

—

3(4)

1 to ∞

0Bh

1-1-(1)88-8-(8)8-8-(8)16

3(4)1 to ∞

8Bh

1-1-(8)88-8-(8)8-8-(8)16

3(4)1 to ∞

CBh

1-8-(8)168-8-(8)8-8-(8)16

3(4)1 to ∞

0

—

—

—

4

1 to ∞

Read ID Operations
Read
Identification
Read Serial Flash
Discoverable
Parameter
Read Unique ID

3 (STR)
4 (DTR)

1 to ∞

Read Memory Operations
Read Data Bytes
Read Data Bytes
at Higher Speed
Octal Output Fast
Read
Octal I/O Fast
Read

Read Memory Operations with 4-Byte Address
4-Byte Read Data
Bytes

13h

http://www.elm-tech.com

1-1-(1)

27

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

4-Byte Read Data
Bytes at Higher

0Ch

1-1-(1)88-8-(8)8-8-(8)16

4

1 to ∞

7Ch

1-1-(8)88-8-(8)8-8-(8)16

4

1 to ∞

CCh

1-8-(8)168-8-(8)8-8-(8)16

4

1 to ∞

FDh

1-8d-(8d)168-8-(8)8-8d-(8d)164

1 to ∞

Write Enable

06h

1-0-0

0

8-0-0

8-0-0

0

0

0

Write Disable

04h

1-0-0

0

8-0-0

8-0-0

0

0

0

05h

1-0-(1)08-0-(8)8-0-(8)8

0

1 to ∞

70h

1-0-(1)08-0-(8)8-0-(8)8

0

1 to ∞

C8h

1-0-(1)08-0-(8)8-0-(8)

8

0

1

B5h

1-1-(1)88-8-(8)8-8-(8)

8

3(4)

1

85h

1-1-(1)88-8-(8)8-8-(8)

8

3(4)

1

01h

1-0-1

0

8-0-8

8-0-8

0

0

1

C5h

1-0-1

0

8-0-8

8-0-8

0

0

1

50h

1-0-0

0

8-0-0

8-0-0

0

0

0

B1h

1-1-1

0

8-8-8

8-8-8

0

3(4)

1

81h

1-1-1

0

8-8-8

8-8-8

0

3(4)

1

02h

1-1-1

0

8-8-8

8-8-8

0

3(4)

Speed
4-Byte Octal
Output Fast Read
4-Byte Octal I/O
Fast Read
4-Byte Octal I/O
DTR Fast Read
Write Operations

Read Register Operations
Read Status
Register
Read Flag Status
Register
Read Extended
Addr. Register
Read Nonvolatile
Configuration
Register
Read Volatile
Configuration
RegisterWrite Register Operations
Write Status
RegisterWrite Extended
Addr. Register
Write Enable for
Volatile Status
RegisterWrite Nonvolatile
Configuration
RegisterWrite Volatile
Configuration
Register
Program Operations
Page Program

http://www.elm-tech.com

28

Rev.1.3

1 to256

Uniform Sector
XccelaTM Flash Memory
Octal Page
ProgramExtended Octal
Page Program

GD25LX256E

82h

1-1-8

0

8-8-8

8-8-8

0

3(4)

C2h

1-8-8

0

8-8-8

8-8-8

0

3(4)

1 to
256
1 to
256

Program Operations with 4-Byte Address
4-Byte Page

1 to

12h

1-1-1

0

8-8-8

8-8-8

0

4

84h

1-1-8

0

8-8-8

8-8-8

0

4

8Eh

1-8-8

0

8-8-8

8-8-8

0

4

Sector Erase

20h

1-1-0

0

8-8-0

8-8-0

0

3(4)

0

32KB Block Erase

52h

1-1-0

0

8-8-0

8-8-0

0

3(4)

0

64KB Block Erase

D8h

1-1-0

0

8-8-0

8-8-0

0

3(4)

0

1-0-0

0

8-0-0

8-0-0

0

0

0

Program
4-Byte Octal Page
Program
4-Byte Extended
Octal Page
Program

256
1 to
256
1 to
256

Erase Operations

Chip Erase

C7h/60hErase Operations with 4-Byte Address
4-Byte Sector
Erase
4-Byte 32KB
Block Erase
4-Byte 64KB
Block Erase

21h

1-1-0

0

8-8-8

8-8-0

0

4

0

5Ch

1-1-0

0

8-8-8

8-8-0

0

4

0

DCh

1-1-0

0

8-8-0

8-8-0

0

4

0

75h

1-0-0

0

8-0-0

8-0-0

0

0

0

7Ah

1-0-0

0

8-0-0

8-0-0

0

0

0

1 to ∞

Suspend/Resume Operations
Program/Erase
Suspend
Program/Erase
ResumeOne-Time Programmable(OTP) Operations
Read Security
Registers
Program Security
Registers
Erase Security
Registers

48h1-1-(1)88-8-(8)8-8-(8)

16

3(4)

42h

1-1-1

0

8-8-8

8-8-8

0

3(4)

44h

1-1-0

0

8-8-0

8-8-0

0

3(4)

0

B7h

1-0-0

0

8-0-0

8-0-0

0

0

0

E9h

1-0-0

0

8-0-0

8-0-0

0

0

0

1 to
256

4-ByteAddress Mode Operations
Enable 4-Byte
Address Mode
Disable 4-Byte
Address Mode

Deep Power-Down Operations

http://www.elm-tech.com

29

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
Deep PowerDown

GD25LX256E

B9h

1-0-0

0

8-0-0

8-0-0

0

0

0

ABh

1-0-0

0

8-0-0

8-0-0

0

0

0

Release From
Deep PowerDown
Advanced Sector Protection Operations
Individual
Block/Sector Lock

36h

1-1-0

0

8-8-0

8-8-0

0

3(4)

0

39h

1-1-0

0

8-8-0

8-8-0

0

3(4)

0

3Dh

1-1-(1)08-8-(8)8-8-(8)

8

3(4)

1

7Eh

1-0-0

0

8-0-0

8-0-0

0

0

0

98h

1-0-0

0

8-0-0

8-0-0

0

0

0

Individual
Block/Sector
UnlockRead Individual
Block/Sector Lock
GlobalBlock/Sector Lock
GlobalBlock/Sector
UnlockTable of ID Definitions
GD25LX256E
Operation Code

M7-M0

ID23-ID16

ID15-ID8

ID7-ID0

9EH/9FH

C8

68

19

FF

http://www.elm-tech.com

30

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
9.1

GD25LX256E

Enable 4-Byte Mode (B7H)

The Enable 4-Byte Mode command enables accessing the address length of 32-bit for the memory area of the higher
density (larger than 128Mb). After sending the Enable 4-Byte Mode command, the ADS bit (FS0) will be set to 1 to indicate
the 4-Byte address mode has been enabled. Once the 4-Byte address mode is enabled, the address length becomes 32bit.
Figure 10. Enable 4-Byte Mode Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

B7H

Figure 11. Enable 4-Byte Mode Sequence Diagram (OPI)

CS#
SCLK

CommandIO[7:0]9.2

B7H

Disable 4-Byte Mode (E9H)

The Disable 4-Byte Mode command is executed to exit the 4-Byte address mode and enter the 3-Byte address mode. Aftersending the Disable 4-Byte Mode command, the ADS bit (FS0) will be clear to be 0 to indicate the 4-Byte address mode
has been disabled, and then the address length will return to 24-bit.
Figure 12. Disable 4-Byte Mode Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

E9H

Figure 13. Disable 4-Byte Mode Sequence Diagram (OPI)

CS#
SCLK
CommandIO[7:0]

http://www.elm-tech.com

E9H

31

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
9.3

GD25LX256E

Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must
be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register(WRSR), Write Extended Address Register (WEAR), Write Nonvolatile/Volatile configure register and Erase/Program
Security Registers command. The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enablecommand  CS# goes high.
Figure 14. Write Enable Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

06H

Figure 15. Write Enable Sequence Diagram (OPI)
CS#
SCLK

CommandIO[7:0]9.4

06H

Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS#
goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up
and upon completion of the Write Status Register, Write Extended Address Register, Write Nonvolatile/Volatile configure
register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands.
Figure 16. Write Disable Sequence Diagram (SPI)
CS#

0

1

2

3

4

5

6

7

SCLK
CommandSI

04H

Figure 17. Write Disable Sequence Diagram (OPI)

CS#
SCLK

CommandIO[7:0]

http://www.elm-tech.com

04H

32

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
9.5

GD25LX256E

Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system
configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting
the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be
issued prior to a Write Status Register command, and any other commands cannot be inserted between them. Otherwise,
Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set
the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit
values.
Figure 18. Write Enable for Volatile Status Register Sequence Diagram (SPI)
CS#

0

1

2

3

4

5

6

7

SCLK

CommandSI

50H

Figure 19. Write Enable for Volatile Status Register Sequence Diagram (OPI)

CS#
SCLK

CommandIO[7:0]

9.6

50H

Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
CS# must be driven high after the eighth of the data Byte has been latched in. Otherwise, the Write Status Register (WRSR)
command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW)
is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value ofthe Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, andis 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2,
BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR)
command also allows the user to set or reset the Status Register Protect (SRP0) bit in accordance with the Write Protect(WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be putin the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware
Protected Mode is entered.

http://www.elm-tech.com

33

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 20. Write Status Register Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

6

SCLK

CommandSI

Status Register in

01H

5

4

3

2

1

0

MSB

Figure 21. Write Status Register Sequence Diagram (OPI)

CS#

0

1

SCLK

Command

SR in

01H

SR7-0

IO[7:0]

9.7

Write Extended Address Register (C5H)

The Extended Address Register is a volatile register that stores the 4th Byte address when the device is operating in the 3Byte Address Mode (ADS=0). To write the Extended Address Register bits, a Write Enable (06H) instruction must previously
have been executed for the device to accept the Write Extended Address Register instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code “C5H”, andthen writing the Extended Address Register data Byte.
Upon Power-up or the execution of a Software/Hardware Reset, the Extended Address Register bits will be cleared to 0.
The Extended Address Bits is only effective when the device is in the 3-Byte Address Mode. When the device operates in
the 4-Byte Address Mode (ADS=1), any command with address input of A31-A24 will replace the Extended Address
Register values. It is recommended to check and update the Extended Address Register if necessary when the device isswitched from 4-Byte to 3-Byte Address Mode
Figure 22. Write Extended Address Register Sequence Diagram (SPI)CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLKCommandSI

EAR in
7 6

C5H

4

5

3 2 1

0

MSB
Figure 23. Write Extended Address Register Sequence Diagram (OPI)
CS#

0

1

Command

EAR inC5H

EAR7-0SCLK

IO[7:0]

http://www.elm-tech.com

34

Rev.1.3

Uniform Sector
XccelaTM Flash Memory
9.8

GD25LX256E

Write Nonvolatile/Volatile Configuration Register (WRCR) (B1H/81H)

The Write Nonvolatile/Volatile Configuration Register (WRCR) command allows new values to be written to the
Nonvolatile/Volatile Configuration Register. Before it can be accepted, a Write Enable (WREN) command must previously
have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write
Enable Latch (WEL).
CS# must be driven high after the data Byte has been latched in. If not, the Write Configuration Register (WRCR) commandis not executed. As soon as CS# is driven high, the self-timed Write Configuration Register cycle (whose duration is tW for
B1H) is initiated. The Write In Progress (WIP) bit is 1 during the self-timed Write Configuration Register cycle, and is 0 when
it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
Figure 24. Write Nonvolatile/Volatile Configuration Register Sequence Diagram (SPI)
CS#

0

1

2

3

4

5

6

8

7

28 29 30 31 32 33 34 35 36 37 38 39

9

SCLK

CommandSI

24-bit address
23 22 21
3 2 1

B1H/81H

Configuration register in
0 7 6 5 4 3 2 1 0
MSB

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 25. Write Nonvolatile/Volatile Configuration Register Sequence Diagram (STR OPI)
CS#

0

1

2

3

4

SCLK

Address

Command
B1H/81H

IO[7:0]

CR in
CR

A7-A0

A15-A7

A23-A16

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 26. Write Nonvolatile/Volatile Configuration Register Sequence Diagram (DTR OPI)
CS#

0

1

2

3

SCLK

CommandIO[7:0]9.9

B1H/81H

Address

Addr. Addr. Addr. Addr.

CR in
CR

Read Status Register (RDSR) (05H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any
time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it
is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. The SO will output Status Register bits S7~S0.

http://www.elm-tech.com

35

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 27. Read Status Register Sequence Diagram (SPI)CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLKCommand
SI

05H
High-Z

SO

Predrive

SR outSR out7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB

MSB

Figure 28. Read Status Register Sequence (STR OPI)
CS#

0

1

9

10

SR outSR outSR out

SR7-0

SR7-0

SR7-0

8

SCLK

Dummy

CommandIO[7:0]Pre-drive

05H

Figure 29. Read Status Register Sequence (DTR OPI)

CS#
0

7

1

8

9

SCLK
Dummy

CommandIO[7:0]SR outPre-drive

05H

SR

SR

SR

SR

9.10 Read Flag Status Register (RDSR) (70H)
The Read Flag Status Register command is for reading the Flag Status Register. The Flag Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Flag Status Register continuously. The SO will output Status Register bits FS7~FS0.
Figure 30. Read Flag Status Register Sequence Diagram (SPI)CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLKCommand
SI
SO

70H
High-Z

Predrive

FSR out
FSR out
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB

http://www.elm-tech.com

MSB

36

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 31. Read Flag Status Register Sequence (STR OPI)
CS#

0

1

9

10

FSR out

FSR out

FSR out

FSR7-0

FSR7-0

FSR7-0

8

SCLK

Dummy

CommandIO[7:0]Pre-drive

70H

Figure 32. Read Flag Status Register Sequence (DTR OPI)

CS#
0

7

1

8

9

SCLK
Dummy

Command

FSR out
Pre-drive70H

IO[7:0]

FSR

FSR

FSR

FSR

9.11 Read Nonvolatile/Volatile Configuration Register (B5H/85H)
The Read Nonvolatile/Volatile Configuration Register command is for reading the Nonvolatile/Volatile Configuration
Registers. It is followed by a 3-Byte address (A23-A0) or a 4-Byte address (A31-A0) and a dummy Byte, and each bit islatched-in on the rising edge of SCLK. Then the Configuration Register, at that address, is shifted out on SO, and each bit
is shifted out, at a Max frequency fC, on the falling edge of SCLK. Read Nonvolatile/Volatile Configuration Register command,
while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 33. Read Configuration Registers Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

8

7

9 10

28 29 30 31

SCLK

24-bit address

Command23 22 21

B5H/85H

SI

2

3

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
Dummy Byte
SI
SO

7

6

5

4

3

2

1

0
Predrive

7 6
MSB

5

CR out4 3 2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

37

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 34. Read Configuration Registers Sequence (STR OPI)

CS#

0

2

1

10

4

3

12

11

SCLK

IO[7:0]

Dummy

CMD

Address

B5H/85H Addr.

Addr. Addr.

Predrive CR out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 35. Read Configuration Registers Sequence (DTR OPI)

CS#
0

1

2

10

3

SCLK

IO[7:0]CommandAddress

B5H/85H

Addr. Addr. Addr. Addr.

Dummy
Pre-drive

CR out9.12 Read Extended Address Register (C8H)
The Read Extended Address Register instruction is entered by driving CS# low and shifting the instruction code “C8H” into
the SI pin on the rising edge of SCLK. The Extended Address Register bits are then shifted out on the SO pin at the fallingedge of SCLK with most significant bit (MSB) first.
When the device is in the 4-Byte Address Mode, the value of Address bits is ignored.
Figure 36. Read Extended Address Register Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Predrive

7

6

SCLK
CommandSI

C8H
High-ZSO

5

EAR out
4 3 2

1

0

MSB
Figure 37. Read Extended Address Register Sequence Diagram (STR OPI)

CS#

0

7

1

8

9

Predrive

EAR
out

SCLK

CMD
IO[7:0]

http://www.elm-tech.com

Dummy

C8H

38

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 38. Read Extended Address Register Sequence Diagram (DTR OPI)

CS#
0

7

1

8

SCLK
Dummy

Command

Pre-drive

C8H

IO[7:0]EAR
out

9.13 Read Data Bytes (READ) (03H/13H)
The Read Data Bytes (READ) command is followed by a 3-Byte address (A23-A0) or a 4-Byte address (A31-A0), and each
bit is latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit isshifted out, at a Max frequency fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address
is automatically incremented to the next higher address after each Byte of data is shifted out. The whole memory can,therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 39. Read Data Bytes Sequence DiagramCS#

28 29 30 31 32 33 34 35 36 37 38 39

0 1 2 3 4 5 6 7 8 9 10

SCLK

24-bit address

CommandSI

03H

23 22 213 2 1 0

Data Out1SO
7 6 5 4 3 2 1 0
MSB
Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
High-Z

MSB

Predrive

Data Out2

9.14 Read Data Bytes at Higher Speed (Fast Read) (0BH/0CH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-Byte
address (A23-A0) or a 4-Byte address (A31-A0) and dummy clocks, and each bit is latched-in on the rising edge of SCLK.
Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency f C, on thefalling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented to the next
higher address after each Byte of data is shifted out.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be even.

http://www.elm-tech.com

39

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 40. Read Data Bytes at Higher Speed Sequence Diagram (SPI)

CS#
0

SCLK

1

2

3

4

5

6

8

7

28 29 30 31

24-bit address

CommandSI

9 10

23 22 21

0BH

2

3

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
Dummy Byte

SI

7

5

6

3

4

2

1

0
Predrive

SO

7 6
MSB

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 41. Read Data Bytes at Higher Speed Sequence Diagram (STR OPI)

CS#

0

2

1

18

4

3

19

20

21

SCLK

CMD

Dummy

Address

Predrive

0BH Addr. Addr. Addr.

IO[7:0]

Byte 1 Byte 2
Data
out

Data Data out
out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 42. Read Data Bytes at Higher Speed Sequence Diagram (DTR OPI)
CS#

0

1

2

18

19

SCLK
Dummy

IO[7:0]0BH

Addr. Addr. Addr. Addr.

Pre-drive

Data
out

Data Data out
out

DQS

9.15 Octal Output Fast Read (8BH/7CH)
The Octal Output Fast Read command is followed by 3-Byte address (A23-A0) or a 4-Byte address (A31-A0) and dummy
clocks, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 8-bit per clock cyclefrom IO[7:0]. The first Byte addressed can be at any location. The address is automatically incremented to the next higher
address after each Byte of data is shifted out.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be even.

http://www.elm-tech.com

40

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 43. Octal Output Fast Read Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

30 31 32 33

938 39 40 41 42 43

SCLK

8BH

IO0

Dummy

Address

Command

1

23 22

0

High-ZIO[7:1]

Data out
Predrive

0

0

0

0

0

Predrive 7:1 7:1 7:1 7:1 7:1

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 44. Octal Output Fast Read Sequence Diagram (STR OPI)

CS#

0

1

2

18

4

3

19

20

21

SCLK

CMD

Dummy

Address

Predrive

8BH Addr. Addr. Addr.

IO[7:0]

Byte 1 Byte 2
Data
out

Data Data out
out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 45. Octal Output Fast Read Sequence Diagram (DTR OPI)
CS#

0

1

2

18

19

SCLK
Dummy

IO[7:0]8BH

Addr. Addr. Addr. Addr.

Pre-drive

Data
out

Data Data out
out

DQS

9.16 Octal I/O Fast Read (CBH/CCH)
The Octal I/O Fast Read command is similar to the Octal Output Fast Read command but with the capability to input the 3Byte address (A23-0) or a 4-Byte address (A31-A0) and a “Continuous Read Mode” Byte and dummy clocks. 8-bit per clock
is transferred by IO[7:0] and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4bit per clock cycle from IO[7:0]. The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address after each Byte of data is shifted out.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be even.

http://www.elm-tech.com

41

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 46. Octal I/O Fast Read Sequence Diagram (SPI, M5-4 ≠ (1, 0))

CS#
0

1

2

3

4

5

6

7

8

9 10 11 1225 26 27 28 29 30

SCLKCommand

IO0

Addr.

CBH
High-ZIO[7:1]

Data out

Dummy

16 8

0 M0

Predrive

23:17 15:9

7:1 M7-1

Predrive 7:1 7:1 7:1 7:1 7:1

0

0

0

0

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 47. Octal I/O Fast Read Sequence Diagram (STR OPI, M5-4 ≠ (1, 0))

CS#

0

2

1

18

4

3

19

20

21

SCLK

CMD

Dummy

Address

Predrive

CBH Addr. Addr. Addr.

IO[7:0]

Byte 1 Byte 2
Data Data out
out

Data
out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 48. Octal I/O Fast Read Sequence Diagram (DTR OPI, M5-4 ≠ (1, 0))
CS#

0

1

2

18

19

SCLK
Dummy

IO[7:0]CBH

Addr. Addr. Addr. Addr.

Pre-drive

Data
out

Data Data out
out

DQS

Octal I/O Fast Read with “Continuous Read Mode”
The Octal I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-Byte address (A23-A0) or a 4-Byte address (A31-A0). If the “Continuous Read Mode” bits (M54) = (1, 0), then the next Octal I/O Fast Read command (after CS# is raised and then lowered) does not require the
CBH/CCH command code. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires
the first CBH/CCH command code, thus returning to normal operation.
Figure 49. Octal I/O Fast Read Sequence Diagram (STR, M5-4 = (1, 0))

CS#

0

1

2

3

17

4

18

19

20

SCLK

Dummy

Address
IO[7:0]

Byte 1 Byte 2

Predrive

Addr. Addr. Addr. M7-0

Data
out

Data Data out
out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

42

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 50. Octal I/O Fast Read Sequence Diagram (DTR OPI, M5-4 = (1, 0))
CS#

0

1

17

2

18

SCLK
Dummy

IO[7:0]Addr. Addr. Addr. Addr. M7-0

Pre-drive

Byte 1 Byte 2 Byte 3
Data Data Data Data out
out
out
out

DQS

Octal I/O Fast Read with “16/32/64-Byte Wrap Around”
The Octal I/O Fast Read command can be used to access a specific portion within a page by issuing Wrap configuration
register Byte prior to CBH/CCH. The data being accessed can be limited to either a 16/32/64-Byte section of a 256-Byte
page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the
16/32/64-Byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cacheafterwards within a fixed length (16/32/64-Byte) of data without issuing multiple read commands.

9.17 Octal I/O DTR Read (FDH)
The Octal I/O DTR Read command enables Double Transfer Rate throughput on Octal I/O of Serial Flash in read mode.
The address (interleave on 8 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 8 I/O pins)
shift out on both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock edge, and 8-bit data canbe read out at one clock edge, which means 8 bits at rising edge of clock, the other 8 bits at falling edge of clock. The first
address Byte can be at any location. The address is automatically increased to the next higher address after each Byte datais shifted out, so the whole memory can be read out at a single Octal I/O DTR Read command. The address counter rolls
over to 0 when the highest address has been reached.
While Program/Erase/Write Status Register cycle is in progress, DTROIO instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be even.
Figure 51. DTR Octal I/O Fast Read Sequence Diagram (SPI)
CS#

0

7

8

9

10

24

25

26

27

SCLK

IO0

Address

FDH

24 16 80Predrive

31:25 23:17 15:9

7:1

Predrive 7:1 7:1 7:1 7:1

High-ZIO[7:1]

DQS

CommandHigh-Z

http://www.elm-tech.com

43

Rev.1.3

Dummy
0

0

0

0

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 52. DTR Octal I/O Fast Read Sequence Diagram (OPI)
CS#

0

1

2

18

19

SCLK
Dummy

IO[7:0]FDH

Addr. Addr. Addr. Addr.

Data
out

Pre-drive

Data Data out
out

DQS

9.18 Page Program (PP) (02H/12H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three or four address
Bytes and at least one data Byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted datathat goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low  sending Page Program command  3-Byte address or 4-Byte
address on SI  at least 1 Byte data on SI  CS# goes high. If more than 256 Bytes are sent to the device, previously
latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data Bytes are sent to device, they are correctly programmed at the requested addresses without having
any effects on the other Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has beenlatched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be even.
Figure 53. Page Program Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

8

7

28 29 30 31 32 33 34 35 36 37 38 39

9 10

SCLK
24-bit address

5

4

3

2

1

2077

2078

2079

1

0

0 7

1

MSB

MSB

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2072

CS#

6

2076

2

3

2075

23 22 21

02H

2073

SI

Data Byte 1

2074

Command

SCLK

Data Byte 3

Data Byte 2
SI

7

6

5

4

3

2

1

0 7

6

5

4

3

2

Data Byte 256
1

0

7

6

5

4

3

2

MSB
MSB
MSB
Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

44

Rev.1.30Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 54. Page Program Sequence Diagram (STR OPI)

CS#

0

2

1

257

5

4

3

258

259

Byte
255

Byte
256

SCLK

CMD

Byte nAddr. Addr. Addr. Byte1 Byte2

02H

IO[7:0]

Data in

Address

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 55. Page Program Sequence Diagram (DTR OPI)

CS#
0

1

2

3

130

SCLK
CommandIO[7:0]Address

02H

Data in

Addr. Addr. Addr. Addr. Byte1 Byte2

Byte
256

Byte n9.19 Octal Page Program (82H/84H)
The Octal Page Program command is for programming the memory using four pins: IO[7:0]. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Programcommand. The Octal Page Program command is entered by driving CS# Low, followed by the command code (82H/84H),
three or four address Bytes and at least one data Byte on IO pins.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes areguaranteed to be programmed correctly within the same page. If less than 256 data Bytes are sent to device, they arecorrectly programmed at the requested addresses without having any effects on the other Bytes of the same page. CS#
must be driven high after the eighth bit of the last data Byte has been latched in; otherwise the Octal Page Program (PP)command is not executed.
As soon as CS# is driven high, the self-timed Octal Page Program cycle (whose duration is tPP) is initiated. While the Octal
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write in Progress (WIP) bit is 1 during the self-timed Octal Page Program cycle, and is 0 when it is completed. At someunspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Octal Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be evenFigure 56. Octal Page Program Sequence Diagram (SPI)

1

2

3

4

5

6

7

8

9

30 31 32 33

Command

IO0
IO[7:1]82H

Address

23 22High-Z

287

0

SCLK

286

CS#

0

0

Data in

1

0

0

0

7:1 7:1

7:1 7:1

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

45

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 57. Page Program Sequence Diagram (STR OPI)

CS#

0

2

1

257

5

4

3

258

259

Byte
255

Byte
256

SCLK

CMD
82H

IO[7:0]

Data in

Address

Byte nAddr. Addr. Addr. Byte1 Byte2

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 58. Page Program Sequence Diagram (DTR OPI)

CS#
0

1

2

3

130

SCLK
CommandIO[7:0]82H

Address

Data in

Addr. Addr. Addr. Addr. Byte1 Byte2

Byte
256

Byte n9.20 Extend Octal Page Program (C2H/8EH)
The Extend Octal Page Program command is for programming the memory using eight pins: IO0, IO1, IO2, IO3, IO4, IO5,
IO6 and IO7. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)
bit before sending the Page Program command. The extend Octal Page Program command is entered by driving CS# Low,
followed by the command code (C2H/8EH), three or four address Bytes and at least one data Byte on IO pins.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes areguaranteed to be programmed correctly within the same page. If less than 256 data Bytes are sent to device, they arecorrectly programmed at the requested addresses without having any effects on the other Bytes of the same page. CS#
must be driven high after the eighth bit of the last data Byte has been latched in; otherwise the Extend Octal Page Program(EPP) command is not executed.
As soon as CS# is driven high, the self-timed Extend Octal Page Program cycle (whose duration is tPP) is initiated. While
the Extend Octal Page Program cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Extend Octal Page Program cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
An Extend Octal Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be even.
Figure 59. Extend Octal Page Program Sequence Diagram (SPI)

1

2

3

4

5

6

7

8

9 10 11 12 13

266

0

265

CS#
SCLK

IO0
IO[7:1]

CommandAddress

C2H

16 8

0

23:17 15:9

7:1

High-Z000

7:1 7:1

7:1

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

46

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 60. Page Program Sequence Diagram (STR OPI)

CS#

0

2

1

257

5

4

3

258

259

Byte
255

Byte
256

SCLK

CMD

Data in

Address

Byte nC2H Addr. Addr. Addr. Byte1 Byte2

IO[7:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 61. Page Program Sequence Diagram (DTR OPI)

CS#
0

1

2

3

130

SCLK
CommandIO[7:0]Address

C2H

Data in

Addr. Addr. Addr. Addr. Byte1 Byte2

Byte nByte
256

9.21 Sector Erase (SE) (20H/21H)
The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered bydriving CS# low, followed by the command code, and 3- Byte address or 4-Byte address on SI. Any address inside thesector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-Byte address or 4-Byte
address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in;otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase
cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read tocheck the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) bit is not executed.
Figure 62. Sector Erase Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK
24 Bits Address

Command

SI

20H

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

47

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 63. Sector Erase Sequence Diagram (STR OPI)

CS#

0

2

1

3

SCLK

CMD

Address

20H

Addr. Addr. Addr.

IO[7:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 64. Sector Erase Sequence Diagram (DTR OPI)

CS#
0

1

2

SCLK
CommandAddress

20H

Addr. Addr. Addr. Addr.

IO[7:0]9.22 32KB Block Erase (BE32) (52H/5CH)
The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase command is entered bydriving CS# low, followed by the command code, and 3-Byte address or 4-Byte address on SI. Any address inside the block
is a valid address for the 32KB Block Erase command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-Byte address or
4-Byte address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has beenlatched in; otherwise the 32KB Block Erase command is not executed. As soon as CS# is driven high, the self-timed Block
Erase cycle (whose duration is tBE1) is initiated. While the Block Erase cycle is in progress, the Status Register may be readto check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A 32KB Block Erase command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits is not executed.
Figure 65. 32KB Block Erase Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK
24 Bits Address

Command

SI

52H

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

48

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 66. 32KB Block Erase Sequence Diagram (STR OPI)

CS#

0

2

1

3

SCLK

CMD

Address

52H

Addr. Addr. Addr.

IO[7:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 67. 32KB Block Erase Sequence Diagram (DTR OPI)

CS#
0

1

2

SCLK
CommandAddress

52H

Addr. Addr. Addr. Addr.

IO[7:0]9.23 64KB Block Erase (BE64) (D8H/DCH)
The 64KB Block Erase command is erased the all data of the chosen block. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase command is entered bydriving CS# low, followed by the command code, and 3-Byte address or 4-Byte address on SI. Any address inside the block
is a valid address for the 64KB Block Erase command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-Byte address or
4-Byte address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has beenlatched in; otherwise the 64KB Block Erase command is not executed. As soon as CS# is driven high, the self-timed Block
Erase cycle (whose duration is tBE2) is initiated. While the Block Erase cycle is in progress, the Status Register may be readto check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A 64KB Block Erase command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits is not executed.
Figure 68. 64KB Block Erase Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK
CommandSI

D8H

24 Bits Address

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

49

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 69. 64KB Block Sequence Diagram (STR OPI)

CS#

0

2

1

3

SCLK

CMD

Address

D8H Addr. Addr. Addr.

IO[7:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 70. 64KB Block Sequence Diagram (DTR OPI)

CS#
0

1

2

SCLK
CommandAddress

D8H

Addr. Addr. Addr. Addr.

IO[7:0]9.24 Chip Erase (CE) (60H/C7H)
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously havebeen executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low,
followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. CS# must be
driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed.
As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase
cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write inProgress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if theBlock Protect (BP2, BP1, and BP0) bits are 0 The Chip Erase (CE) command is ignored if one or more sectors are protected.
Figure 71. Chip Erase Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

60H/C7H

Figure 72. Chip Erase Sequence Diagram (OPI)
CS#
SCLK

CommandIO[7:0]

http://www.elm-tech.com

60H/C7H

50

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

9.25 Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (theDeep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in activeuse, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device,
and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the DeepPower-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command.
Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down (ABH) or Enable Reset (66H) and Reset (99H) commands. These commands can release the device fromthis mode. The Release from Deep Power-Down command releases the device from deep power down mode.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-Up.
The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high.
CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down(DP) command is not executed. As soon as CS# is driven high, it requires a delay of t DP before the supply current is reduced
to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 73. Deep Power-Down Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

tDP

7

SCLK
CommandDeep Power-down mode

B9H

SI

Figure 74. Deep Power-Down Sequence Diagram (OPI)
CS#

tDP
SCLK
Deep Power-down mode

CommandIO[7:0]B9H

9.26 Release from Deep Power-Down (ABH)
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high. Release from Power-Down will take the time duration of tRES1 (See AC
Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin mustremain high during the tRES1 time duration.
When used to release the device from the Power-Down state, the command is the same as previously described, After
this time duration the device will resume normal operation and other command will be accepted. If the Release from PowerDown command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command isignored and will not have any effects on the current cycle.

http://www.elm-tech.com

51

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 75. Release Power-Down Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

6

t RES17

SCLK

Command
ABH

SI

Deep Power-down modeStand-by mode

Figure 76. Release Power-Down Sequence Diagram (OPI)

CS#

tRES1
SCLK
Deep Power-down mode

CommandIO[7:0]Stand-by mode

ABH

9.27 Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique
ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command  3-Byte address (000000H)
or 4-Byte address (00000000H) on SI 1 Byte Dummy 128bit Unique ID Out CS# goes high.
Figure 77. Read Unique ID Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

8

7

9 10

28 29 30 31

SCLK

24-bit address

CommandSI

23 22 21

4BH

3

2

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
Dummy Byte

SI

7

6

5

4

3

2

1

0
Data Out1
6 5 4 3 2

Data Out2
1 0 7 6 5
7
SO
MSB
MSB
Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Predrive

http://www.elm-tech.com

52

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 78. Read Unique ID Sequence Diagram (STR OPI)

CS#

0

2

1

10

4

3

11

12

13

SCLK

CMD

Dummy

Address

4BH Addr. Addr. Addr.

IO[7:0]

Byte 1 Byte 2

Predrive

Data
out

Data Data out
out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 79. Read Unique ID Sequence Diagram (DTR OPI)
CS#

0

1

2

10

11

SCLK
Dummy

IO[7:0]4BH

Addr. Addr. Addr. Addr.

Pre-drive

Data
out

Data Data out
out

DQS

9.28 Read Identification (RDID) (9FH/9EH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by three Bytes ofdevice identification. The device identification indicates the memory type in the first Byte, and the memory capacity of thedevice in the second Byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress, is notdecoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followedby the 32-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The Read
Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high,the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decodeand execute commands.

http://www.elm-tech.com

53

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 80. Read Identification ID Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLK

SI

9FH/9EH
Predrive

SO

7 6
MSB

CS#

Manufacturer ID
5 4 3 2 1

Device ID23-ID16
6 5 4 3 2 1

7

0

0

MSB

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK

SI
7

SO

Device ID15-ID8
6 5 4 3 2 1

MSB

Device ID7-ID0

0

7

6

5

4

3

2

Manufacturer ID

1

0

MSB

7

6

5

4

3

2

1

0

MSB

Figure 81. Read Identification ID Sequence Diagram (STR, OPI)

CS#
0

1

7

8

9

10

11

12

13

SCLK

CMD
IO[7:0]Dummy

ID out Cycle

Predrive

9FH/9EH

MID

DID

DID

ID out Cycle

DID

MID

DID

Figure 82. Read Identification ID Sequence Diagram (DTR, OPI)

CS#

0

9

8

10

11

SCLK

IO[7:0]9FH/9EH

Dummy

ID out Cycle

Pre-drive

MID

DID

DID

ID out Cycle

DID

MID

DID

DID

DQS

9.29 Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Register command (01H, B1H) and Erase/Program
Security Registers command (44H, 42H) and Erase commands (20H/21H, 52H/5CH, D8H/DCH, C7H, 60H) and Page
Program command (02H/12H, 82H/84H, C2H/8EH) are not allowed during Program suspend. The Write Register command(01H, B1H) and Erase Security Registers command (44H) and Erase commands (20H/21H, 52H/5CH, D8H/DCH, C7H,
60H) are not allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/blockerase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Flag Status Register

http://www.elm-tech.com

54

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1
bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1
to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off
during the suspend period will reset the device and release the suspend state.
Figure 83. Program/Erase Suspend Sequence Diagram (SPI)
CS#

0

1

2

3

4

5

6

7

tSUS

SCLK

Command75H

SI

High-ZSO

Accept read command

Figure 84. Program/Erase Suspend Sequence Diagram (OPI)

CS#

tSUS
SCLK
Accept read command

CommandIO[7:0]75H9.30 Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a
Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared
from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase
operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active.
Figure 85. Program/Erase Resume Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

7AH
Resume Erase/Program

http://www.elm-tech.com

55

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 86. Program/Erase Resume Sequence Diagram (OPI)

CS#
SCLK

Resume Program/Erase

CommandIO[7:0]

7AH

9.31 Erase Security Registers (44H)
The GD25LX256E provides 4K-Byte Security Registers which can be erased and programmed individually. These registers
may be used by the system manufacturers to store security and other important information separately from the main
memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  CS#
goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the Erase
Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle(whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be readto check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security
Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Security Registers Lock Bit in the Configuration Register can be used to OTP protect the
security registers. Once the bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers
command will be ignored.
Address
Security RegisterA23-1600HA15-120000

A11-8Page Address

A7-0
Byte Address

Figure 87. Erase Security Registers command Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK
CommandSI

24 Bits Address

2

23 22
MSB

44H

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 88. Erase Security Registers command Sequence Diagram (STR, OPI)

CS#

0

1

2

3

SCLK

IO[7:0]

CMD

Address

44H

Addr. Addr. Addr.

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

56

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 89. Erase Security Registers command Sequence Diagram (DTR, OPI)

CS#

0

1

2

SCLK

CommandAddress

44H

Addr. Addr. Addr. Addr.

IO[7:0]9.32 Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. The security register contains 16
pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)
bit before sending the Program Security Registers command. The Program Security Registers command is entered bydriving CS# Low, followed by the command code (42H), three address Bytes and at least one data Byte on SI. As soon asCS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit is set to 1, the Security Registers will be permanently locked. Program Security Registers
command will be ignored.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be even.
Address
Security RegisterA23-1600HA15-120000

A11-8Page Address

A7-0
Byte Address

Figure 90. Program Security Registers command Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31 32 33 34 35 36 37 38 39

SCLKCommand24-bit address

1

6

5

4

3

2

1

2077

2078

2079

0 7

2076

2

2075

3

23 22 21

2074

42H

SI

Data Byte 1

1

0

MSB

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2073

CS#

2072

MSB

7

6

SCLK
Data Byte 2
SI

7

6

5

4

MSB

3

2

Data Byte 3

1

0 7

6

5

4

3

2

MSB

Data Byte 256

1

0

5

4

3

2

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

57

Rev.1.30Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 91. Program Security Registers command Sequence Diagram (STR OPI)

CS#

0

2

1

257

5

4

3

258

259

Byte
255

Byte
256

SCLK

CMD
42H

IO[7:0]

Data in

Address

Byte nAddr. Addr. Addr. Byte1 Byte2

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 92. Program Security Registers command Sequence Diagram (DTR OPI)

CS#
0

1

2

3

130

SCLK
CommandIO[7:0]Address

42H

Data in

Addr. Addr. Addr. Addr. Byte1 Byte2

Byte
256

Byte n9.33 Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-Byte or 4-Byte
address (A23-A0 or A31-A0) and a dummy Byte, and each bit is latched-in on the rising edge of SCLK. Then the memory
content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency f C, on the falling edge of SCLK.
The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after
each Byte of data is shifted out. Once the A11-A0 address reaches the last Byte of the register (Byte FFFH), it will reset to
000H, the command is completed by driving CS# high.
In DTR mode, the starting address given must be even (A0=0) and data Byte number must be even.
Address
Security RegisterA23-1600HA15-120000

A11-8Page Address

A7-0
Byte Address

Figure 93. Read Security Registers command Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31

SCLKCommand24-bit address

48H

SI

3

23 22 212

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO

Dummy Byte

7

6

5

4

3

2

1

0
Predrive

7 6
MSB

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

58

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 94. Read Security Registers command Sequence Diagram (STR OPI)

CS#

0

2

1

18

4

3

20

19

21

SCLK

IO[7:0]

Dummy

CMD

Address

48H

Addr. Addr. Addr.

Byte 1 Byte 2

Predrive

Data
out

Data Data out
out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 95. Read Security Registers command Sequence Diagram (DTR OPI)
CS#

0

1

2

18

19

SCLK
Dummy

IO[7:0]48H

Addr. Addr. Addr. Addr.

Pre-drive

Data
out

Data Data out
out

DQS

9.34 Individual Block/Sector Lock (36H)/Unlock (39H)/Read (3DH)
The individual block/sector lock provides an alternative way to protect the memory array from adverse Erase/Program. In
order to use the Individual Block/Sector Locks, the WPS bit in Configuration Register bit 2 at address 04h must be set to 0.
If WPS=1, the write protection will be determined by the combination of BP (4:0) bits in the Status Register.
The individual Block/Sector Lock command (36H) sequence: CS# goes low SI: Sending individual Block/Sector Lockcommand SI: Sending 3-Byte or 4-Byte individual Block/Sector Lock Address  CS# goes high.
The individual Block/Sector Unlock command (39H) sequence: CS# goes low SI: Sending individual Block/Sector Unlock
command SI: Sending 3-Byte or 4-Byte individual Block/Sector Lock Address  CS# goes high.
The Read individual Block/Sector lock command (3DH) sequence: CS# goes low  SI: Sending Read individual
Block/Sector Lock command SI: Sending 3-Byte or 4-Byte individual Block/Sector Lock Address  SO: The Block/Sector
Lock Bit will out CS# goes high. If the least significant bit (LSB) is1, the corresponding block/sector is locked, if the LSB
is 0, the corresponding block/sector is unlocked, Erase/Program operation can be performed.
Figure 96. Individual Block/Sector Lock command Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK

24 Bits Address

Command

SI

36H

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

59

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 97. Individual Block/Sector Lock command Sequence Diagram (STR OPI)

CS#

0

2

1

3

SCLK

IO[7:0]

CMD

Address

36H

Addr. Addr. Addr.

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 98. Individual Block/Sector Lock command Sequence Diagram (DTR OPI)

CS#

0

1

2

SCLK

CommandAddress

36H

Addr. Addr. Addr. Addr.

IO[7:0]Figure 99. Individual Block/Sector Unlock command Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK

24 Bits Address

Command

SI

23 22
MSB

39H

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 100. Individual Block/Sector Unlock command Sequence Diagram (STR OPI)

CS#

0

1

2

3

SCLK

IO[7:0]

CMD

Address

39H

Addr. Addr. Addr.

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 101. Individual Block/Sector Unlock command Sequence Diagram (DTR OPI)

CS#

0

1

2

SCLK

IO[7:0]

http://www.elm-tech.com

CommandAddress

39H

Addr. Addr. Addr. Addr.

60

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 102. Read Individual Block/Sector lock command Sequence Diagram (SPI)CS#
29 30 31 32 33 34 35 36 37 38 39

0 1 2 3 4 5 6 7 8 9

SCLKCommand

2 1 0

23 22

3DH

SI

High-Z

SO

Predrive

MSB

Lock value out
X X X X X X X 0

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 103. Read Individual Block/Sector lock command Sequence Diagram (STR OPI)

CS#

0

2

1

10

4

3

11

12

SCLK

CMD

Dummy

Address

Pre- Lockdrive Value

3DH Addr. Addr. Addr.

IO[7:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 104. Read Individual Block/Sector lock command Sequence Diagram (DTR OPI)
CS#

0

1

9

2

10

SCLK

Dummy
IO[7:0]3DH

Pre-drive

Addr. Addr. Addr. Addr.

Lock
Value

9.35 Global Block/Sector Lock (7EH) or Unlock (98H)
All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock command, or can set to 0 by the Global
Block/Sector Unlock command.
The Global Block/Sector Lock command (7EH) sequence: CS# goes low SI: Sending Global Block/Sector Lockcommand CS# goes high.
The Global Block/Sector Unlock command (98H) sequence: CS# goes low SI: Sending Global Block/Sector Unlock
command CS# goes high.
Figure 105. The Global Block/Sector Lock Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

SCLK

CommandSI
SO

http://www.elm-tech.com

7EH
High-Z

61

Rev.1.3

6

7

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 106. The Global Block/Sector Lock Sequence Diagram (OPI)
CS#
SCLK

CommandIO[7:0]

7EH

Figure 107. The Global Block/Sector Unlock Sequence Diagram (SPI)
CS#

0

1

2

3

4

5

6

7

SCLK

CommandSI

98H
High-ZSO

Figure 108. The Global Block/Sector Unlock Sequence Diagram (OPI)CS#
SCLKCommand

98H

IO[7:0]9.36 Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default
power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status(WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous Read Modebit setting (M7-M0) .
When Flash is in OPI Mode, DTR Mode or Continuous Read Mode (XIP), 66H&99H cannot reset Flash to power-on state.
Therefore, it is recommended to send the following sequence to reset Flash in these modes:
1.

8CLK with IO<7:0>=all “H” or all “L”: ensure Flash quit XIP mode

2.

OPI format 66H/99H: ensure Flash in OPI mode and DTR mode can be reset

3.

SPI format 66H/99H: ensure Flash in SPI mode can be reset

The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or OPI mode. The “Reset (99H)”
command sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low 
Sending Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will takeapproximately tRST / tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if
there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by thedevice. It is recommended to check the WIP bit and the SUS1/SUS2 bits in Flag Status Register before issuing the Resetcommand sequence.

http://www.elm-tech.com

62

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 109. Enable Reset and Reset command Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCLK

CommandCommand

66H

99H

SI

High-ZSO

Figure 110. Enable Reset and Reset command Sequence Diagram (OPI)

CS#
SCLK
CommandCommand

66H

99H

IO[7:0]9.37 Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional andfeature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can beinterrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216C.
Figure 111. Read Serial Flash Discoverable Parameter command Sequence Diagram (SPI)

CS#
0

1

2

3

4 5

6

7

8

9 10

28 29 30 31

SCLKCommandSISO

24-bit address

5AH

3

23 22 212

1

0

High-ZCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK

Dummy Byte
SI
SO

http://www.elm-tech.com

7 6 5 4 3 2 1 0
Predrive

7 6
MSB

63

Rev.1.3

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 112. Read Serial Flash Discoverable Parameter command Sequence Diagram (STR OPI)

CS#

0

2

1

10

4

3

11

12

13

SCLK

CMD

Dummy

Address

Predrive

5AH Addr. Addr. Addr.

IO[7:0]

Byte 1 Byte 2
Data
out

Data Data out
out

Figure 113. Read Serial Flash Discoverable Parameter command Sequence Diagram (DTR OPI)
CS#

0

1

2

10

11

SCLK
Dummy

IO[7:0]5AH

Addr. Addr. Addr. Addr.

Pre-drive

Data
out

Data Data out
out

DQS

Table 14 Signature and Parameter Identification Data Values (Please contact GigaDevice for Details)

http://www.elm-tech.com

64

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

10 ELECTRICAL CHARACTERISTICS
10.1 Power-On Timing
Figure 114 Power-on Timing
Vcc(max)
Chip Selection is not allowed

Vcc(min)
Device is fully
accessible

tVSL

VWI

Time

Table 15 Power-Up Timing and Write Inhibit Threshold
SymbolParameter

Min.

tVSL

VCC (min.) to device operation

1.5

VWI

Write Inhibit Voltage

1

Max.

Unit
ms
V

1.4

10.2 Initial Delivery StateThe device is delivered with the memory array erased: all bits are set to 1 (each Byte contains FFH). The Status Registercontains 00H (all Status Register bits are 0).

10.3 Absolute Maximum Ratings
Parameter

Value

Unit

Ambient Operating Temperature (TA)

-40 to 85℃-40 to 105-40 to 125
Storage Temperature-65 to 150℃

Transient Input/Output Voltage (note: overshoot)-2.0 to VCC+2.0

V

Applied Input/Output Voltage-0.6 to VCC+0.4

V-0.6 to 2.5

V

VCC

http://www.elm-tech.com

65

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 115. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns

Maximum Positive Overshoot Waveform

20ns

20ns

Vss

Vcc + 2.0V
Vss-2.0V
Vcc

20ns

20ns

20ns

10.4 Capacitance Measurement Conditions
SymbolParameter

Min.

Typ.

Max.

Unit

Conditions

CIN

Input Capacitance6

pF

VIN=0V

COUT

Output Capacitance8pF

VOUT=0V

CL

Load Capacitance

30

pF

Input Rise And Fall time

5ns

Input Pulse Voltage

0.1VCC to 0.8VCC

V

Input Timing Reference Voltage

0.2VCC to 0.7VCC

V

Output Timing Reference Voltage

0.5VCCV

Figure 116. Absolute Maximum Ratings Diagram

0.8VCC

Input timing reference level

0.1VCC

0.7VCC
0.2VCC

Output timing reference level
AC Measurement Level

Note: Input pulse rise and fall time are<5ns

http://www.elm-tech.com

66

Rev.1.3

0.5VCCUniform Sector
XccelaTM Flash Memory

GD25LX256E

10.5 DC Characteristics(TA = -40℃~85℃, VCC=1.65~2.0V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

μA

ILO

Output Leakage Current

±2

μA

ICC1

Standby Current

25

150

μA

ICC2

Deep Power-Down Current

5

50

μA

30

50

mA

50

70

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 166MHz,

ICC3Operating Current (Read)

Q=Open(x8 I/O)
CLK=0.1VCC / 0.9VCC
at 200MHz DTR,
Q=Open(x8 I/O)

ICC4Operating Current (PP)

CS#=VCC

15

30

mA

ICC5

Operating Current (WRSR)

CS#=VCC

15

30

mA

ICC6

Operating Current (SE)

CS#=VCC

15

30

mA

ICC7

Operating Current (BE)

CS#=VCC

15

30

mA

ICC8

Operating Current (CE)

CS#=VCC

15

30

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

67

Rev.1.3

VUniform Sector
XccelaTM Flash Memory

GD25LX256E(TA = -40℃~105℃, VCC=1.65~2.0V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

μA

ILO

Output Leakage Current

±2

μA

ICC1

Standby Current

25

300

μA

ICC2

Deep Power-Down Current

5

60

μA

30

55

mA

50

75

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 166MHz,

ICC3Operating Current (Read)

Q=Open(x8 I/O)
CLK=0.1VCC / 0.9VCC
at 200MHz DTR,
Q=Open(x8 I/O)

ICC4Operating Current (PP)

CS#=VCC

15

35

mA

ICC5

Operating Current (WRSR)

CS#=VCC

15

35

mA

ICC6

Operating Current (SE)

CS#=VCC

15

35

mA

ICC7

Operating Current (BE)

CS#=VCC

15

35

mA

ICC8

Operating Current (CE)

CS#=VCC

15

35

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

68

Rev.1.3

VUniform Sector
XccelaTM Flash Memory

GD25LX256E(TA = -40℃~125℃, VCC=1.65~2.0V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±3

μA

ILO

Output Leakage Current

±3

μA

ICC1

Standby Current

25

600

μA

ICC2

Deep Power-Down Current

5

100

μA

30

60

mA

40

70

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 166MHz,

ICC3Operating Current (Read)

Q=Open(x8 I/O)
CLK=0.1VCC / 0.9VCC
at 166MHz DTR,
Q=Open(x8 I/O)

ICC4Operating Current (PP)

CS#=VCC

15

40

mA

ICC5

Operating Current (WRSR)

CS#=VCC

15

40

mA

ICC6

Operating Current (SE)

CS#=VCC

15

40

mA

ICC7

Operating Current (BE)

CS#=VCC

15

40

mA

ICC8

Operating Current (CE)

CS#=VCC

15

40

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

69

Rev.1.3

VUniform Sector
XccelaTM Flash Memory

GD25LX256E

10.6 AC Characteristics(TA = -40℃~85℃, VCC=1.65~2.0V)
SymbolfC1
fC2

Parameter

Min.

Serial Clock Frequency for all instructions except
Read (03H, 13H) in STR mode
Serial Clock Frequency for all instructions in DTR
mode

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time

Serial Clock Rise/Fall Time (Slew Rate)

166

MHz

200(4)

MHz

60

MHz
ns

45%

ns

(1/fcMax)

Serial Clock Rise/Fall Time (Slew Rate)
tCHCL

Unit.

(1/fcMax)(fSCLK≤100MHz)(fSCLK>100MHz)

Max.

45%

Serial Clock Rise/Fall Time (Slew Rate)

tCLCH

Typ.

(fSCLK>133MHz)
Serial Clock Rise/Fall Time (Slew Rate)(fSCLK>166MHz)

0.6

V/ns

0.8

V/ns

1

V/ns

1.2

V/ns

tSLCH

CS# Active Setup Time

4

ns

tCHSH

CS# Active Hold Time

4

ns

tCLSH

CS# Active Hold Time (DTR)

4

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5ns

CS# High Time (Read)20

ns

CS# High Time (Write)

40

ns

tSHSL
tSHQZ
tCLQX

Output Disable Time8ns

Output Hold Time

1.8

ns

Data In Setup Time (STR) (fSCLK≤133MHz)2

ns

Data In Setup Time (STR) (fSCLK>133MHz)

1

ns

Data In Setup Time (DTR) (fSCLK≤100MHz)

1

ns

tDVCH

Data In Setup Time (DTR) (fSCLK>100MHz)

0.8

ns

tDVCL

Data In Setup Time (DTR) (fSCLK>133MHz)

0.6

ns

Data In Setup Time (DTR) (fSCLK>166MHz)

0.5

ns

Data In Hold Time (STR) (fSCLK≤133MHz)2

ns

Data In Hold Time (STR) (fSCLK>133MHz)

1

ns

Data In Hold Time (DTR) (fSCLK≤100MHz)

1

ns

tCHDX

Data In Hold Time (DTR) (fSCLK>100MHz)

0.8

ns

tCLDX

Data In Hold Time (DTR) (fSCLK>133MHz)

0.6

ns

Data In Hold Time (DTR) (fSCLK>166MHz)

0.5

ns

tCHQX
tDVCH

tCHDX

http://www.elm-tech.com

70

Rev.1.3

Uniform Sector
XccelaTM Flash MemorytQSV

GD25LX256E

Clock Transient to DQS Valid Time

Align to 30pF tCLQVns

SIO Valid Skew Related to DQS (TFBGA, 12pF)

0.4

ns

SIO Valid Skew Related to DQS (SOP, 12pF)

0.6

ns

SIO Hold Skew Factor (TFBGA, 12pF)

0.4

ns

SIO Hold Skew Factor (SOP, 12pF)

0.6

ns

tECSV

ECS# Setup Time

10

ns

tCLQV

Clock Transient to Output Valid (30pF)

8

ns

tCHQV

Clock Transient to Output Valid (12pF)

6

ns

tWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

tDP

CS# High To Deep Power-Down Mode

tDQSQ
tQHS

tRES1

CS# High To Standby Mode Without Electronic
Signature ReadtSUS

CS# High To Next Command After SuspendtRS

Latency Between Resume And Next Suspend

tRST

3

μs

30

μs

20

μs

100

μs

CS# High To Next Command After Reset (From Read

40

μs

25

ms

2

25

ms

or From Program)CS# High To Next Command After Reset (From ErasetRST_Eor From Write Status/Non-volatile Configuration
Register)tW

Write Status Register Cycle Time
Write Non-Volatile Configuration Register Cycle TimetBP1

Byte Program Time (First Byte)

30

70

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

12

μs

tPP

Page Programming Time

0.3

1.2

ms

tSE

Sector Erase Time

30

300

ms

tBE1

Block Erase Time (32K Bytes)

0.1

1

s

tBE2

Block Erase Time (64K Bytes)

0.2

2

s

tCE

Chip Erase Time (GD25LX256E)

50

200

s

Note:
1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Time of CS# High To Next Command After Reset from 01H/B1H command would be tW + tRST
4. For SOP16 package, fC1 = 166MHz, fC2 = 166MHz.

http://www.elm-tech.com

71

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E(TA = -40℃~105℃, VCC=1.65~2.0V)
SymbolfC1
fC2

Parameter

Min.

Serial Clock Frequency for all instructions except
Read (03H, 13H) in STR mode
Serial Clock Frequency for all instructions in DTR
mode

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time

Serial Clock Rise/Fall Time (Slew Rate)

166

MHz

200(4)

MHz

60

MHz
ns

45%

ns

(1/fcMax)

Serial Clock Rise/Fall Time (Slew Rate)
tCHCL

Unit.

(1/fcMax)(fSCLK≤100MHz)(fSCLK>100MHz)

Max.

45%

Serial Clock Rise/Fall Time (Slew Rate)

tCLCH

Typ.

(fSCLK>133MHz)
Serial Clock Rise/Fall Time (Slew Rate)(fSCLK>166MHz)

0.6

V/ns

0.8

V/ns

1

V/ns

1.2

V/ns

tSLCH

CS# Active Setup Time

4

ns

tCHSH

CS# Active Hold Time

4

ns

tCLSH

CS# Active Hold Time (DTR)

4

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5ns

CS# High Time (Read)20

ns

CS# High Time (Write)

40

ns

tSHSL
tSHQZ
tCLQX

Output Disable Time8ns

Output Hold Time

1.8

ns

Data In Setup Time (STR) (fSCLK≤133MHz)2

ns

Data In Setup Time (STR) (fSCLK>133MHz)

1

ns

Data In Setup Time (DTR) (fSCLK≤100MHz)

1

ns

tDVCH

Data In Setup Time (DTR) (fSCLK>100MHz)

0.8

ns

tDVCL

Data In Setup Time (DTR) (fSCLK>133MHz)

0.6

ns

Data In Setup Time (DTR) (fSCLK>166MHz)

0.5

ns

Data In Hold Time (STR) (fSCLK≤133MHz)2

ns

Data In Hold Time (STR) (fSCLK>133MHz)

1

ns

Data In Hold Time (DTR) (fSCLK≤100MHz)

1

ns

tCHDX

Data In Hold Time (DTR) (fSCLK>100MHz)

0.8

ns

tCLDX

Data In Hold Time (DTR) (fSCLK>133MHz)

0.6

ns

Data In Hold Time (DTR) (fSCLK>166MHz)

0.5

ns

tCHQX
tDVCH

tCHDX

http://www.elm-tech.com

72

Rev.1.3

Uniform Sector
XccelaTM Flash MemorytQSV

GD25LX256E

Clock Transient to DQS Valid Time

Align to 30pF tCLQVns

SIO Valid Skew Related to DQS (TFBGA, 12pF)

0.4

ns

SIO Valid Skew Related to DQS (SOP, 12pF)

0.6

ns

SIO Hold Skew Factor (TFBGA, 12pF)

0.4

ns

SIO Hold Skew Factor (SOP, 12pF)

0.6

ns

tECSV

ECS# Setup Time

10

ns

tCLQV

Clock Transient to Output Valid (30pF)

8

ns

tCHQV

Clock Transient to Output Valid (12pF)

6

ns

tWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

tDP

CS# High To Deep Power-Down Mode

tDQSQ
tQHS

tRES1

CS# High To Standby Mode Without Electronic
Signature ReadtSUS

CS# High To Next Command After SuspendtRS

Latency Between Resume And Next Suspend

tRST

3

μs

30

μs

20

μs

100

μs

CS# High To Next Command After Reset (From Read

40

μs

25

ms

2

30

ms

or From Program)CS# High To Next Command After Reset (From ErasetRST_Eor From Write Status/Non-volatile Configuration
Register)tW

Write Status Register Cycle Time
Write Non-Volatile Configuration Register Cycle TimetBP1

Byte Program Time (First Byte)

30

140

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

25

μs

tPP

Page Programming Time

0.3

2

ms

tSE

Sector Erase Time

30

500

ms

tBE1

Block Erase Time (32K Bytes)

0.1

1.6

s

tBE2

Block Erase Time (64K Bytes)

0.2

3

s

tCE

Chip Erase Time (GD25LX256E)

50

300

s

Note:
1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Time of CS# High To Next Command After Reset from 01H/B1H command would be tW + tRST
4. For SOP16 package, fC1 = 166MHz, fC2 = 166MHz.

http://www.elm-tech.com

73

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E(TA = -40℃~125℃, VCC=1.65~2.0V)
SymbolfC1
fC2

Parameter

Min.

Typ.

Serial Clock Frequency for all instructions except
Read (03H, 13H) in STR mode
Serial Clock Frequency for all instructions in DTR
mode

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low TimetCHCL

(fSCLK>100MHz)

166(4)

MHz

166(4)

MHz

60

MHz
ns

(1/fcMax)45%

ns(1/fcMax)(fSCLK≤100MHz)
Serial Clock Rise/Fall Time (Slew Rate)

Unit.

45%

Serial Clock Rise/Fall Time (Slew Rate)
tCLCH

Max.

Serial Clock Rise/Fall Time (Slew Rate)(fSCLK>133MHz)

0.6

V/ns

0.8

V/ns

1

V/ns

tSLCH

CS# Active Setup Time

4

ns

tCHSH

CS# Active Hold Time

4

ns

tCLSH

CS# Active Hold Time (DTR)

4

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5ns

CS# High Time (Read)20

ns

CS# High Time (Write)

40

ns

tSHSL
tSHQZ
tCLQX
tCHQX
tDVCH
tDVCH
tDVCL
tCHDX
tCHDX
tCLDX
tQSV
tDQSQ
tQHS

Output Disable Time8ns

Output Hold Time

1.8

ns

Data In Setup Time (STR) (fSCLK≤133MHz)2

ns

Data In Setup Time (STR) (fSCLK>133MHz)

1

ns

Data In Setup Time (DTR) (fSCLK≤100MHz)

1ns

Data In Setup Time (DTR) (fSCLK>100MHz)

0.8

ns

Data In Setup Time (DTR) (fSCLK>133MHz)

0.6

ns

Data In Hold Time (STR) (fSCLK≤133MHz)2

ns

Data In Hold Time (STR) (fSCLK>133MHz)

1

ns

Data In Hold Time (DTR) (fSCLK≤100MHz)

1ns

Data In Hold Time (DTR) (fSCLK>100MHz)

0.8

ns

Data In Hold Time (DTR) (fSCLK>133MHz)

0.6

ns

Clock Transient to DQS Valid Time

Align to 30pF tCLQVns

SIO Valid Skew Related to DQS (TFBGA, 12pF)

0.4

ns

SIO Valid Skew Related to DQS (SOP, 12pF)

0.6

ns

SIO Hold Skew Factor (TFBGA, 12pF)

0.4

ns

SIO Hold Skew Factor (SOP, 12pF)

0.6

ns

http://www.elm-tech.com

74

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

tECSV

ECS# Setup Time

10

ns

tCLQV

Clock Transient to Output Valid (30pF)

8

ns

tCHQV

Clock Transient to Output Valid (12pF)

6

ns

tWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

tDP

CS# High To Deep Power-Down ModetRES1

CS# High To Standby Mode Without Electronic
Signature ReadtSUS

CS# High To Next Command After SuspendtRS

Latency Between Resume And Next Suspend

tRST

3

μs

30

μs

20

μs

100

μs

CS# High To Next Command After Reset (From Read

40

μs

25

ms

2

30

ms

or From Program)CS# High To Next Command After Reset (From ErasetRST_Eor From Write Status/Non-volatile Configuration
Register)tW

Write Status Register Cycle Time
Write Non-Volatile Configuration Register Cycle TimetBP1

Byte Program Time (First Byte)

30

140

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

25

μs

tPP

Page Programming Time

0.3

3

ms

tSE

Sector Erase Time

30

700

ms

tBE1

Block Erase Time (32K Bytes)

0.1

1.6

s

tBE2

Block Erase Time (64K Bytes)

0.2

3

s

tCE

Chip Erase Time (GD25LX256E)

50

300

s

Note:
1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Time of CS# High To Next Command After Reset from 01H/B1H command would be tW + tRST
4. For SOP16 package, fC1 = 133MHz, fC2 = 133MHz.
Figure 117. Serial Input Timing

tSHSL

CS#
tCHSL

SCLK

tSLCH

tDVCH

MSB

SO

High-Z

tSHCH
tCHCL

tCLCH

tCHDX

SI

http://www.elm-tech.com

tCHSH

LSB

75

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 118. Output Timing

CS#

tCLH

SCLK
tCLQV

tCLQV

tCLQX

tSHQZ

tCLL

tCLQX

SO

LSB

SI
Least significant address bit (LIB) in

Figure 119. Serial Input Timing (DTR)

tSHSL
CS#

tSLCH

tCHSL

tCLSH

tSHCH

SCLK

tDVCL
tDVCH

tCLDX

IO

tCHCL

tCLCH

MSB

LSB

tCHDX
Figure 120. Serial Output Timing (DTR)

CS#
tCLH

tCLQV

SCLK

tCLL

tCHQV

tCLQX

tCHQX

http://www.elm-tech.com

tSHQZ
LSB

MSB

IO

76

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 121. DQS Output Timing (STR)

CS#

SCLK
tQSV

DQS
tDQSQ

tQHS

tSHQZ

IO

Figure 122. DQS Output Timing (DTR)

CS#

SCLK
tQSV

DQS
tDQSQ

tDQSQ
tQHS

tSHQZ

IO
tQHS
Figure 123. Resume to Suspend Timing Diagram

CS#

ResumeCommandtRS

SuspendCommandFigure 124. WP# Timing

CS#
tWHSL

tSHWL

WP#

SCLK
IO
Input

http://www.elm-tech.com

Write Status Register allowed

77

Rev.1.3

Write Status Register NOT allowedUniform Sector
XccelaTM Flash Memory

GD25LX256E

Figure 125. RESET Timing

tRB

CS#

RESET#
tRLRH

tRHSL

Table 16. Reset Timing
SymbolParameter

Min.

Typ.

Max.

Unit.

tRLRH

Reset Pulse Width

1

μs

tRHSL

Reset Hold time before next Operation

50

ns

tRB

Reset Recovery Time (From Read or Program)40μs

Reset Recovery Time (From Erase)

25

ms

Note:
1. Time of Reset Recovery Time from 01H/B1H command would be tW + tRB
2. The device need tRB (max) at most to get ready for all commands after RESET# low.

http://www.elm-tech.com

78

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

11 ORDERING INFORMATIONGD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
R: Pb Free + Halogen Free Green Package + RESET# Pin
K: Pb Free + Halogen Free Green Package + RESET# Pin +SRP1 Function
Temperature Range
I: Industrial (-40℃ to +85℃)
J: Industrial+ (-40℃ to +105℃)
E: Industrial+ (-40℃ to +125℃)
F: Industrial+ (-40℃ to +85℃)**
3: Automotive (-40℃ to +85℃)*
2: Automotive (-40℃ to +105℃)*
A: Automotive (-40℃ to +125℃)*
Package Type
F: SOP16 300mil
B: TFBGA-24ball (5x5 Ball Array)
Generation
E: E Version
Density256: 256M bit
Series
LX: 1.8V, 4KB Uniform Sector, x8I/O
Product Family
25: SPI NOR Flash*Please contact GigaDevice sales for automotive products.
**F grade has implemented additional test flows to ensure higher product quality than I grade.

http://www.elm-tech.com

79

Rev.1.3

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

11.1 Valid Part Numbers
Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40℃ to +85℃)

Product Number

Clock

GD25LX256EFIR
GD25LX256EFIK
GD25LX256EBIR

166MHz166MHz200MHzGD25LX256EBIK

200MHzDensity

Package Type

256Mbit

SOP16 300mil

256MbitTFBGA-24ball (5x5 Ball Array)

Packing
Options
T/Y/R
T/Y/R
Y/R
Y/R

Temperature Range J: Industrial+ (-40℃ to +105℃)

Product Number

Clock

GD25LX256EFJR
GD25LX256EFJK
GD25LX256EBJR

166MHz166MHz200MHzGD25LX256EBJK

200MHzDensity

Package Type

256Mbit

SOP16 300mil

256MbitTFBGA-24ball (5x5 Ball Array)

Packing
Options
T/Y/R
T/Y/R
Y/R
Y/R

Temperature Range E: Industrial+ (-40℃ to +125℃)

Product Number

Clock

GD25LX256EFER
GD25LX256EFEK
GD25LX256EBER

133MHz133MHz166MHzGD25LX256EBEK

166MHzDensity

Package Type

256Mbit

SOP16 300mil

256MbitTFBGA-24ball (5x5 Ball Array)

Packing
Options
T/Y/R
T/Y/R
Y/R
Y/R

Temperature Range F: Industrial+ (-40℃ to +85℃)

Product Number

Clock

GD25LX256EFFR
GD25LX256EFFKGD25LX256EBFR

166MHz166MHz200MHzGD25LX256EBFK

200MHzhttp://www.elm-tech.com

Density

Package Type

256Mbit

SOP16 300mil

256MbitTFBGA-24ball (5x5 Ball Array)

80

Rev.1.3

Packing
Options
T/Y/R
T/Y/R
Y/R
Y/R

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

12 PACKAGE INFORMATION
12.1 Package SOP16 300MIL
D
16

9

E1

E

h
1

“A”

L

h

8

L1

θ

b
0.1 C
SEATING PLANEbBase Metal

c

A2 A

Detail “A”

A1e

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.10

2.05

0.31

0.10

10.20

10.10

7.40

Nom

-

0.20

-

0.41

0.25

10.30

10.30

7.50

Max

2.65

0.30

2.55

0.51

0.33

10.40

10.50

7.60

Unit
mm

Note:
1. Both the package length and width do not include the mold flash.

http://www.elm-tech.com

81

Rev.1.3

e

L

L1

0.40
1.27

1.27

1.40

h

θ

0.25

0

-

-

0.75

8

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

12.2 Package TFBGA-24BALL (5x5 ball array)

1

2

3

4

5

5

4

3

2

1

A

A

B

B

b

C

D

C

D1

D

D

e

E

E
e

E

E1

A2

A

A1

Dimensions
Symbol

A

A1

A2

b

E

Min

-

0.25

0.75

0.35

5.90

Nom

-

0.30

0.80

0.40

6.00

Max

1.20

0.35

0.85

0.45

6.10

Unit
mm

E1

82

Rev.1.3

D1

e

4.00

1.00

7.90
4.00

Note: Both the package length and width do not include the mold flash.

http://www.elm-tech.com

D

8.00
8.10

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

13 REVISION HISTORY
Version No
1.0

1.1

Description

Page

Date

Initial releaseAll

2019-8-8

Remove 30h command---

Modify tVSL

P65

Modify ICC4-8

P67

Modify tCLQV/tRSET/tRET_E/tW @-40 to 85℃

P70

Modify tPP(typ.)/tSE(max.)/tBE1(max.) @-40 to 85℃

P70

Modify tRS

P74

2020-8-10

P68, 71, 72

Add DC/AC @-40 to 105℃
Modify default value of Byte <1> and Byte<4> in non-volatile/volatileP22-24

configuration register
1.2

Modify tCHSH/tCLSH from 3ns to 4ns

P70, 72

Modify tSHCH from 3ns to 5ns

P70, 72

Modify tCLQX/tCHQX from 1ns to 1.8ns

P70, 72

Modify tW (max) @-40 to 85℃ from 20ms to 25ms

P71
P69, 74-75

Add DC/AC @-40 to 125℃
Add Note of WP# Pin and NC Ball

P7

Modify Typo of ECS# Timing

P15

Modify Typo of DLP
1.3

P24-25

Update ILI / ILO of 125℃ from ±2μA to ±3μA

P69

Add WP# Timing

P77

Update Ordering Information

P79-80Add Coplanarity of SOP16

P81

http://www.elm-tech.com

2020-12-30

83

Rev.1.3

2022-1-21

Uniform Sector
XccelaTM Flash Memory

GD25LX256E

Important NoticeThis document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
according to the laws of the People’s Republic of China and other applicable laws. The Company reserves all rights undersuch laws and no Intellectual Property Rights are transferred (either wholly or partially) or licensed (either expressly or
impliedly). The names and brands of third party referred thereto (if any) are the property of their respective owner andreferred to for identification purposes only.
The Company does not assume any warranty or condition, express or implied, with regard to this document or any
Product, including, but not limited to, the implied warranties of merchantability, fitness for any particular purpose, noninfringement, or any warranty arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document toproperly design, program, and test the functionality and safety of any application and any product produced. Except forcustomized products which has been expressly identified in the applicable agreement, the Products are designed,
developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only. The
Products are not designed or intended for use in, and no warranty is made respect to, any applications designed or intended
for the operation of weaponry, nuclear equipment, atomic energy control instruments, combustion control instruments,
airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical devices orsystems (including resuscitation equipment and surgical implants etc.), pollution control or hazardous substancesmanagement, or other uses where failure to perform can reasonably be expected to result in personal injury, death, property
or environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, andcustomers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold theCompany as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and otherliabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Customers shall discard the device according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves theright to make changes, corrections, modifications or improvements to this document and the Products andservices described herein at any time, without notice. And the company shall have no responsibility whatsoever
for conflicts or incompatibilities arising from future changes to them.

http://www.elm-tech.com

84

Rev.1.3